diff --git a/TESTS/mbed_hal/qspi/flash_configs/flash_configs.h b/TESTS/mbed_hal/qspi/flash_configs/flash_configs.h index ca388c377c..cca42129c8 100644 --- a/TESTS/mbed_hal/qspi/flash_configs/flash_configs.h +++ b/TESTS/mbed_hal/qspi/flash_configs/flash_configs.h @@ -67,7 +67,7 @@ defined(TARGET_CY8CKIT_062S2_43012) || \ defined(TARGET_CY8CKIT_062S2_4343W) || \ defined(TARGET_CY8CKIT_064S2_4343W) || \ - defined(TARGET_CYESKIT_064B0S2_4343W) || \ + defined(TARGET_CY8CKIT_064B0S2_4343W) || \ defined(TARGET_CY8CPROTO_062_4343W) || \ defined(TARGET_CY8CPROTO_062S2_43012) || \ defined(TARGET_CY8CPROTO_062S3_4343W) || \ @@ -78,9 +78,6 @@ #elif defined(TARGET_CYW9P62S1_43012EVB_01) #include "S25FS512S_config.h" -#elif defined(TARGET_CY8CPROTO_064_SB) -#include "S25FL128S_config.h" - #endif #endif // MBED_FLASH_CONFIGS_H diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c similarity index 93% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c index 04783e4b97..7b3eac9a81 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c @@ -4,8 +4,8 @@ * Description: * Wrapper function to initialize all generated code. * This file was automatically generated and should not be modified. -* Device Configurator: 2.0.0.1483 -* Device Support Library (libs/psoc6pdl): 1.4.1.2240 +* cfg-backend-cli: 1.2.0.1483 +* Device Support Library (libs/psoc6pdl): 1.6.0.4266 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h similarity index 94% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h index f469a01ea8..59b32b9018 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h @@ -4,8 +4,8 @@ * Description: * Simple wrapper header containing all generated files. * This file was automatically generated and should not be modified. -* Device Configurator: 2.0.0.1483 -* Device Support Library (libs/psoc6pdl): 1.4.1.2240 +* cfg-backend-cli: 1.2.0.1483 +* Device Support Library (libs/psoc6pdl): 1.6.0.4266 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp old mode 100755 new mode 100644 similarity index 90% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp index 216bafabba..d8d85b9715 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp @@ -1,26 +1,26 @@ -/******************************************************************************* -* File Name: cycfg.timestamp -* -* Description: -* Sentinel file for determining if generated source is up to date. -* This file was automatically generated and should not be modified. -* Device Configurator: 2.0.0.1483 -* Device Support Library (libs/psoc6pdl): 1.4.1.2240 -* -******************************************************************************** -* Copyright 2017-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -********************************************************************************/ - +/******************************************************************************* +* File Name: cycfg.timestamp +* +* Description: +* Sentinel file for determining if generated source is up to date. +* This file was automatically generated and should not be modified. +* cfg-backend-cli: 1.2.0.1483 +* Device Support Library (libs/psoc6pdl): 1.6.0.4266 +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c similarity index 91% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c index 2797add790..c2836a6951 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c @@ -4,8 +4,8 @@ * Description: * Clock configuration * This file was automatically generated and should not be modified. -* Device Configurator: 2.0.0.1483 -* Device Support Library (../../../psoc6pdl): 1.4.1.2240 +* cfg-backend-cli: 1.2.0.1483 +* Device Support Library (libs/psoc6pdl): 1.6.0.4266 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation @@ -27,7 +27,7 @@ #include "cycfg_clocks.h" #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj = + const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj = { .type = CYHAL_RSC_CLOCK, .block_num = CYBSP_CSD_CLK_DIV_HW, diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h similarity index 94% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h index 28b058deac..f00f300b2b 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h @@ -4,8 +4,8 @@ * Description: * Clock configuration * This file was automatically generated and should not be modified. -* Device Configurator: 2.0.0.1483 -* Device Support Library (../../../psoc6pdl): 1.4.1.2240 +* cfg-backend-cli: 1.2.0.1483 +* Device Support Library (libs/psoc6pdl): 1.6.0.4266 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h similarity index 93% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h index 0d31cfa23b..a00457a515 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h @@ -5,8 +5,8 @@ * Contains warnings and errors that occurred while generating code for the * design. * This file was automatically generated and should not be modified. -* Device Configurator: 2.0.0.1483 -* Device Support Library (libs/psoc6pdl): 1.4.1.2240 +* cfg-backend-cli: 1.2.0.1483 +* Device Support Library (libs/psoc6pdl): 1.6.0.4266 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c similarity index 92% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c index de38a7a37c..3800fe587d 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c @@ -4,8 +4,8 @@ * Description: * Peripheral Hardware Block configuration * This file was automatically generated and should not be modified. -* Device Configurator: 2.0.0.1483 -* Device Support Library (libs/psoc6pdl): 1.4.1.2240 +* cfg-backend-cli: 1.2.0.1483 +* Device Support Library (libs/psoc6pdl): 1.6.0.4266 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation @@ -34,5 +34,5 @@ cy_stc_csd_context_t cy_csd_0_context = void init_cycfg_peripherals(void) { - Cy_SysClk_PeriphAssignDivider(PCLK_CSD_CLOCK, CY_SYSCLK_DIV_8_BIT, 3U); + Cy_SysClk_PeriphAssignDivider(PCLK_CSD_CLOCK, CY_SYSCLK_DIV_8_BIT, 0U); } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h similarity index 93% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h index d0d105469c..ef5c2fe9aa 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h @@ -4,8 +4,8 @@ * Description: * Peripheral Hardware Block configuration * This file was automatically generated and should not be modified. -* Device Configurator: 2.0.0.1483 -* Device Support Library (../../../psoc6pdl): 1.4.1.2240 +* cfg-backend-cli: 1.2.0.1483 +* Device Support Library (libs/psoc6pdl): 1.6.0.4266 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation @@ -37,8 +37,8 @@ extern "C" { #define CYBSP_CSD_ENABLED 1U #define CY_CAPSENSE_CORE 4u -#define CY_CAPSENSE_CPU_CLK 96000000u -#define CY_CAPSENSE_PERI_CLK 48000000u +#define CY_CAPSENSE_CPU_CLK 100000000u +#define CY_CAPSENSE_PERI_CLK 100000000u #define CY_CAPSENSE_VDDA_MV 3300u #define CY_CAPSENSE_PERI_DIV_TYPE CY_SYSCLK_DIV_8_BIT #define CY_CAPSENSE_PERI_DIV_INDEX 0u diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c similarity index 97% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c index ccaccdf0ca..55a7f9565c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c @@ -4,8 +4,8 @@ * Description: * Pin configuration * This file was automatically generated and should not be modified. -* Device Configurator: 2.0.0.1483 -* Device Support Library (libs/psoc6pdl): 1.4.1.2240 +* cfg-backend-cli: 1.2.0.1483 +* Device Support Library (libs/psoc6pdl): 1.6.0.4266 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation @@ -74,11 +74,11 @@ const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config = .channel_num = CYBSP_WCO_OUT_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config = +const cy_stc_gpio_pin_config_t CYBSP_CSD_RX_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, - .hsiom = CYBSP_CSD_TX_HSIOM, + .hsiom = CYBSP_CSD_RX_HSIOM, .intEdge = CY_GPIO_INTR_DISABLE, .intMask = 0UL, .vtrip = CY_GPIO_VTRIP_CMOS, @@ -91,11 +91,11 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CSD_TX_obj = + const cyhal_resource_inst_t CYBSP_CSD_RX_obj = { .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_CSD_TX_PORT_NUM, - .channel_num = CYBSP_CSD_TX_PIN, + .block_num = CYBSP_CSD_RX_PORT_NUM, + .channel_num = CYBSP_CSD_RX_PIN, }; #endif //defined (CY_USING_HAL) const cy_stc_gpio_pin_config_t CYBSP_SWO_config = @@ -425,7 +425,7 @@ void init_cycfg_pins(void) #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_CSD_TX_obj); + cyhal_hwmgr_reserve(&CYBSP_CSD_RX_obj); #endif //defined (CY_USING_HAL) Cy_GPIO_Pin_Init(CYBSP_SWO_PORT, CYBSP_SWO_PIN, &CYBSP_SWO_config); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h similarity index 89% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h index a54e4c7ad8..3d96f034f5 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h @@ -4,8 +4,8 @@ * Description: * Pin configuration * This file was automatically generated and should not be modified. -* Device Configurator: 2.0.0.1483 -* Device Support Library (libs/psoc6pdl): 1.4.1.2240 +* cfg-backend-cli: 1.2.0.1483 +* Device Support Library (libs/psoc6pdl): 1.6.0.4266 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation @@ -53,6 +53,9 @@ extern "C" { #if defined (CY_USING_HAL) #define CYBSP_WCO_IN_HAL_PORT_PIN P0_0 #endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_WCO_IN P0_0 +#endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_WCO_IN_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) @@ -77,6 +80,9 @@ extern "C" { #if defined (CY_USING_HAL) #define CYBSP_WCO_OUT_HAL_PORT_PIN P0_1 #endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_WCO_OUT P0_1 +#endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_WCO_OUT_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) @@ -86,29 +92,32 @@ extern "C" { #if defined (CY_USING_HAL) #define CYBSP_WCO_OUT_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG #endif //defined (CY_USING_HAL) -#define CYBSP_CSD_TX_ENABLED 1U -#define CYBSP_CSD_TX_PORT GPIO_PRT1 -#define CYBSP_CSD_TX_PORT_NUM 1U -#define CYBSP_CSD_TX_PIN 0U -#define CYBSP_CSD_TX_NUM 0U -#define CYBSP_CSD_TX_DRIVEMODE CY_GPIO_DM_ANALOG -#define CYBSP_CSD_TX_INIT_DRIVESTATE 1 +#define CYBSP_CSD_RX_ENABLED 1U +#define CYBSP_CSD_RX_PORT GPIO_PRT1 +#define CYBSP_CSD_RX_PORT_NUM 1U +#define CYBSP_CSD_RX_PIN 0U +#define CYBSP_CSD_RX_NUM 0U +#define CYBSP_CSD_RX_DRIVEMODE CY_GPIO_DM_ANALOG +#define CYBSP_CSD_RX_INIT_DRIVESTATE 1 #ifndef ioss_0_port_1_pin_0_HSIOM #define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_GPIO #endif -#define CYBSP_CSD_TX_HSIOM ioss_0_port_1_pin_0_HSIOM -#define CYBSP_CSD_TX_IRQ ioss_interrupts_gpio_1_IRQn +#define CYBSP_CSD_RX_HSIOM ioss_0_port_1_pin_0_HSIOM +#define CYBSP_CSD_RX_IRQ ioss_interrupts_gpio_1_IRQn #if defined (CY_USING_HAL) - #define CYBSP_CSD_TX_HAL_PORT_PIN P1_0 + #define CYBSP_CSD_RX_HAL_PORT_PIN P1_0 #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_CSD_TX_HAL_IRQ CYHAL_GPIO_IRQ_NONE + #define CYBSP_CSD_RX P1_0 #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_CSD_TX_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CSD_RX_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_CSD_TX_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG + #define CYBSP_CSD_RX_HAL_DIR CYHAL_GPIO_DIR_INPUT +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_CSD_RX_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG #endif //defined (CY_USING_HAL) #define CYBSP_SWO_ENABLED 1U #define CYBSP_SWO_PORT GPIO_PRT6 @@ -125,6 +134,9 @@ extern "C" { #if defined (CY_USING_HAL) #define CYBSP_SWO_HAL_PORT_PIN P6_4 #endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_SWO P6_4 +#endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_SWO_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) @@ -149,6 +161,9 @@ extern "C" { #if defined (CY_USING_HAL) #define CYBSP_SWDIO_HAL_PORT_PIN P6_6 #endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_SWDIO P6_6 +#endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_SWDIO_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) @@ -173,6 +188,9 @@ extern "C" { #if defined (CY_USING_HAL) #define CYBSP_SWDCK_HAL_PORT_PIN P6_7 #endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_SWDCK P6_7 +#endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_SWDCK_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) @@ -197,6 +215,9 @@ extern "C" { #if defined (CY_USING_HAL) #define CYBSP_CINA_HAL_PORT_PIN P7_1 #endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_CINA P7_1 +#endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CINA_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) @@ -221,6 +242,9 @@ extern "C" { #if defined (CY_USING_HAL) #define CYBSP_CINB_HAL_PORT_PIN P7_2 #endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_CINB P7_2 +#endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CINB_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) @@ -245,6 +269,9 @@ extern "C" { #if defined (CY_USING_HAL) #define CYBSP_CMOD_HAL_PORT_PIN P7_7 #endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_CMOD P7_7 +#endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CMOD_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) @@ -269,6 +296,9 @@ extern "C" { #if defined (CY_USING_HAL) #define CYBSP_CSD_BTN0_HAL_PORT_PIN P8_1 #endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_CSD_BTN0 P8_1 +#endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_BTN0_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) @@ -293,6 +323,9 @@ extern "C" { #if defined (CY_USING_HAL) #define CYBSP_CSD_BTN1_HAL_PORT_PIN P8_2 #endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_CSD_BTN1 P8_2 +#endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_BTN1_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) @@ -317,6 +350,9 @@ extern "C" { #if defined (CY_USING_HAL) #define CYBSP_CSD_SLD0_HAL_PORT_PIN P8_3 #endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_CSD_SLD0 P8_3 +#endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_SLD0_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) @@ -341,6 +377,9 @@ extern "C" { #if defined (CY_USING_HAL) #define CYBSP_CSD_SLD1_HAL_PORT_PIN P8_4 #endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_CSD_SLD1 P8_4 +#endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_SLD1_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) @@ -365,6 +404,9 @@ extern "C" { #if defined (CY_USING_HAL) #define CYBSP_CSD_SLD2_HAL_PORT_PIN P8_5 #endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_CSD_SLD2 P8_5 +#endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_SLD2_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) @@ -389,6 +431,9 @@ extern "C" { #if defined (CY_USING_HAL) #define CYBSP_CSD_SLD3_HAL_PORT_PIN P8_6 #endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_CSD_SLD3 P8_6 +#endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_SLD3_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) @@ -413,6 +458,9 @@ extern "C" { #if defined (CY_USING_HAL) #define CYBSP_CSD_SLD4_HAL_PORT_PIN P8_7 #endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_CSD_SLD4 P8_7 +#endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_SLD4_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) @@ -431,9 +479,9 @@ extern const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config; #if defined (CY_USING_HAL) extern const cyhal_resource_inst_t CYBSP_WCO_OUT_obj; #endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config; +extern const cy_stc_gpio_pin_config_t CYBSP_CSD_RX_config; #if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_CSD_TX_obj; + extern const cyhal_resource_inst_t CYBSP_CSD_RX_obj; #endif //defined (CY_USING_HAL) extern const cy_stc_gpio_pin_config_t CYBSP_SWO_config; #if defined (CY_USING_HAL) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c similarity index 94% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c index f8200c70ef..e0ba904bb8 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c @@ -4,8 +4,8 @@ * Description: * Establishes all necessary connections between hardware elements. * This file was automatically generated and should not be modified. -* Device Configurator: 2.0.0.1483 -* Device Support Library (libs/psoc6pdl): 1.4.1.2240 +* cfg-backend-cli: 1.2.0.1483 +* Device Support Library (libs/psoc6pdl): 1.6.0.4266 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h similarity index 89% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h index 87481e9a9b..e0cfe03b1c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h @@ -4,8 +4,8 @@ * Description: * Establishes all necessary connections between hardware elements. * This file was automatically generated and should not be modified. -* Device Configurator: 2.0.0.1483 -* Device Support Library (../../../psoc6pdl): 1.4.1.2240 +* cfg-backend-cli: 1.2.0.1483 +* Device Support Library (libs/psoc6pdl): 1.6.0.4266 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation @@ -40,15 +40,15 @@ void init_cycfg_routing(void); #define ioss_0_port_6_pin_4_HSIOM P6_4_CPUSS_SWJ_SWO_TDO #define ioss_0_port_6_pin_6_HSIOM P6_6_CPUSS_SWJ_SWDIO_TMS #define ioss_0_port_6_pin_7_HSIOM P6_7_CPUSS_SWJ_SWCLK_TCLK -#define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_AMUXB +#define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_AMUXA #define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_AMUXB -#define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_AMUXB +#define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_AMUXA #define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_AMUXB #define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_AMUXB #define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_AMUXB #define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_AMUXB #define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_AMUXB -#define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_AMUXB +#define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_AMUXA #define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_AMUXB #if defined(__cplusplus) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c new file mode 100644 index 0000000000..d3aa57ca05 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c @@ -0,0 +1,1181 @@ +/******************************************************************************* +* File Name: cycfg_system.c +* +* Description: +* System configuration +* This file was automatically generated and should not be modified. +* cfg-backend-cli: 1.2.0.1483 +* Device Support Library (libs/psoc6pdl): 1.6.0.4266 +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#include "cycfg_system.h" + +#define CY_CFG_SYSCLK_ECO_ERROR 1 +#define CY_CFG_SYSCLK_ALTHF_ERROR 2 +#define CY_CFG_SYSCLK_PLL_ERROR 3 +#define CY_CFG_SYSCLK_FLL_ERROR 4 +#define CY_CFG_SYSCLK_WCO_ERROR 5 +#define CY_CFG_SYSCLK_CLKBAK_ENABLED 1 +#define CY_CFG_SYSCLK_CLKBAK_SOURCE CY_SYSCLK_BAK_IN_CLKLF +#define CY_CFG_SYSCLK_CLKFAST_ENABLED 1 +#define CY_CFG_SYSCLK_CLKFAST_DIVIDER 0 +#define CY_CFG_SYSCLK_FLL_ENABLED 1 +#define CY_CFG_SYSCLK_FLL_MULT 500U +#define CY_CFG_SYSCLK_FLL_REFDIV 20U +#define CY_CFG_SYSCLK_FLL_CCO_RANGE CY_SYSCLK_FLL_CCO_RANGE4 +#define CY_CFG_SYSCLK_FLL_ENABLE_OUTDIV true +#define CY_CFG_SYSCLK_FLL_LOCK_TOLERANCE 10U +#define CY_CFG_SYSCLK_FLL_IGAIN 9U +#define CY_CFG_SYSCLK_FLL_PGAIN 5U +#define CY_CFG_SYSCLK_FLL_SETTLING_COUNT 8 +#define CY_CFG_SYSCLK_FLL_OUTPUT_MODE CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT +#define CY_CFG_SYSCLK_FLL_CCO_FREQ 355 +#define CY_CFG_SYSCLK_FLL_OUT_FREQ 100000000 +#define CY_CFG_SYSCLK_CLKHF0_ENABLED 1 +#define CY_CFG_SYSCLK_CLKHF0_DIVIDER CY_SYSCLK_CLKHF_NO_DIVIDE +#define CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ 100UL +#define CY_CFG_SYSCLK_CLKHF0_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0 +#define CY_CFG_SYSCLK_CLKHF2_ENABLED 1 +#define CY_CFG_SYSCLK_CLKHF2_DIVIDER CY_SYSCLK_CLKHF_DIVIDE_BY_2 +#define CY_CFG_SYSCLK_CLKHF2_FREQ_MHZ 50UL +#define CY_CFG_SYSCLK_CLKHF2_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0 +#define CY_CFG_SYSCLK_CLKHF3_ENABLED 1 +#define CY_CFG_SYSCLK_CLKHF3_DIVIDER CY_SYSCLK_CLKHF_NO_DIVIDE +#define CY_CFG_SYSCLK_CLKHF3_FREQ_MHZ 100UL +#define CY_CFG_SYSCLK_CLKHF3_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0 +#define CY_CFG_SYSCLK_CLKHF4_ENABLED 1 +#define CY_CFG_SYSCLK_CLKHF4_DIVIDER CY_SYSCLK_CLKHF_NO_DIVIDE +#define CY_CFG_SYSCLK_CLKHF4_FREQ_MHZ 100UL +#define CY_CFG_SYSCLK_CLKHF4_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0 +#define CY_CFG_SYSCLK_ILO_ENABLED 1 +#define CY_CFG_SYSCLK_ILO_HIBERNATE true +#define CY_CFG_SYSCLK_IMO_ENABLED 1 +#define CY_CFG_SYSCLK_CLKLF_ENABLED 1 +#define CY_CFG_SYSCLK_CLKPATH0_ENABLED 1 +#define CY_CFG_SYSCLK_CLKPATH0_SOURCE CY_SYSCLK_CLKPATH_IN_IMO +#define CY_CFG_SYSCLK_CLKPATH0_SOURCE_NUM 0UL +#define CY_CFG_SYSCLK_CLKPATH1_ENABLED 1 +#define CY_CFG_SYSCLK_CLKPATH1_SOURCE CY_SYSCLK_CLKPATH_IN_IMO +#define CY_CFG_SYSCLK_CLKPATH1_SOURCE_NUM 0UL +#define CY_CFG_SYSCLK_CLKPATH2_ENABLED 1 +#define CY_CFG_SYSCLK_CLKPATH2_SOURCE CY_SYSCLK_CLKPATH_IN_IMO +#define CY_CFG_SYSCLK_CLKPATH2_SOURCE_NUM 0UL +#define CY_CFG_SYSCLK_CLKPERI_ENABLED 1 +#define CY_CFG_SYSCLK_CLKPERI_DIVIDER 0 +#define CY_CFG_SYSCLK_PLL0_ENABLED 1 +#define CY_CFG_SYSCLK_PLL0_FEEDBACK_DIV 36 +#define CY_CFG_SYSCLK_PLL0_REFERENCE_DIV 1 +#define CY_CFG_SYSCLK_PLL0_OUTPUT_DIV 2 +#define CY_CFG_SYSCLK_PLL0_LF_MODE false +#define CY_CFG_SYSCLK_PLL0_OUTPUT_MODE CY_SYSCLK_FLLPLL_OUTPUT_AUTO +#define CY_CFG_SYSCLK_PLL0_OUTPUT_FREQ 144000000 +#define CY_CFG_SYSCLK_PLL1_ENABLED 1 +#define CY_CFG_SYSCLK_PLL1_FEEDBACK_DIV 30 +#define CY_CFG_SYSCLK_PLL1_REFERENCE_DIV 1 +#define CY_CFG_SYSCLK_PLL1_OUTPUT_DIV 5 +#define CY_CFG_SYSCLK_PLL1_LF_MODE false +#define CY_CFG_SYSCLK_PLL1_OUTPUT_MODE CY_SYSCLK_FLLPLL_OUTPUT_AUTO +#define CY_CFG_SYSCLK_PLL1_OUTPUT_FREQ 48000000 +#define CY_CFG_SYSCLK_CLKSLOW_ENABLED 1 +#define CY_CFG_SYSCLK_CLKSLOW_DIVIDER 0 +#define CY_CFG_SYSCLK_CLKTIMER_ENABLED 1 +#define CY_CFG_SYSCLK_CLKTIMER_SOURCE CY_SYSCLK_CLKTIMER_IN_IMO +#define CY_CFG_SYSCLK_CLKTIMER_DIVIDER 0U +#define CY_CFG_SYSCLK_WCO_ENABLED 1 +#define CY_CFG_SYSCLK_WCO_IN_PRT GPIO_PRT0 +#define CY_CFG_SYSCLK_WCO_IN_PIN 0U +#define CY_CFG_SYSCLK_WCO_OUT_PRT GPIO_PRT0 +#define CY_CFG_SYSCLK_WCO_OUT_PIN 1U +#define CY_CFG_SYSCLK_WCO_BYPASS CY_SYSCLK_WCO_NOT_BYPASSED +#define CY_CFG_PWR_ENABLED 1 +#define CY_CFG_PWR_INIT 1 +#define CY_CFG_PWR_USING_PMIC 0 +#define CY_CFG_PWR_VBACKUP_USING_VDDD 1 +#define CY_CFG_PWR_LDO_VOLTAGE CY_SYSPM_LDO_VOLTAGE_LP +#define CY_CFG_PWR_USING_ULP 0 +#define CY_CFG_PWR_REGULATOR_MODE_MIN false + +#if defined (CY_DEVICE_SECURE) && (CY_CPU_CORTEX_M4) + static cy_stc_pra_system_config_t srss_0_clock_0_secureConfig; +#endif //defined (CY_DEVICE_SECURE) && (CY_CPU_CORTEX_M4) +#if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) + static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig = + { + .fllMult = 500U, + .refDiv = 20U, + .ccoRange = CY_SYSCLK_FLL_CCO_RANGE4, + .enableOutputDiv = true, + .lockTolerance = 10U, + .igain = 9U, + .pgain = 5U, + .settlingCount = 8U, + .outputMode = CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT, + .cco_Freq = 355U, + }; +#endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj = + { + .type = CYHAL_RSC_CLKPATH, + .block_num = 0U, + .channel_num = 0U, + }; +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj = + { + .type = CYHAL_RSC_CLKPATH, + .block_num = 1U, + .channel_num = 0U, + }; +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj = + { + .type = CYHAL_RSC_CLKPATH, + .block_num = 2U, + .channel_num = 0U, + }; +#endif //defined (CY_USING_HAL) +#if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) + static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_0_pllConfig = + { + .feedbackDiv = 36, + .referenceDiv = 1, + .outputDiv = 2, + .lfMode = false, + .outputMode = CY_SYSCLK_FLLPLL_OUTPUT_AUTO, + }; +#endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) +#if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) + static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_1_pllConfig = + { + .feedbackDiv = 30, + .referenceDiv = 1, + .outputDiv = 5, + .lfMode = false, + .outputMode = CY_SYSCLK_FLLPLL_OUTPUT_AUTO, + }; +#endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) + +__WEAK void cycfg_ClockStartupError(uint32_t error) +{ + (void)error; /* Suppress the compiler warning */ + while(1); +} +#if defined (CY_DEVICE_SECURE) && (CY_CPU_CORTEX_M4) + __STATIC_INLINE void init_cycfg_secure_struct(cy_stc_pra_system_config_t * secure_config) + { + #ifdef CY_CFG_PWR_ENABLED + secure_config->powerEnable = CY_CFG_PWR_ENABLED; + #endif /* CY_CFG_PWR_ENABLED */ + + #ifdef CY_CFG_PWR_USING_LDO + secure_config->ldoEnable = CY_CFG_PWR_USING_LDO; + #endif /* CY_CFG_PWR_USING_LDO */ + + #ifdef CY_CFG_PWR_USING_PMIC + secure_config->pmicEnable = CY_CFG_PWR_USING_PMIC; + #endif /* CY_CFG_PWR_USING_PMIC */ + + #ifdef CY_CFG_PWR_VBACKUP_USING_VDDD + secure_config->vBackupVDDDEnable = CY_CFG_PWR_VBACKUP_USING_VDDD; + #endif /* CY_CFG_PWR_VBACKUP_USING_VDDD */ + + #ifdef CY_CFG_PWR_USING_ULP + secure_config->ulpEnable = CY_CFG_PWR_USING_ULP; + #endif /* CY_CFG_PWR_USING_ULP */ + + #ifdef CY_CFG_SYSCLK_ECO_ENABLED + secure_config->ecoEnable = CY_CFG_SYSCLK_ECO_ENABLED; + #endif /* CY_CFG_SYSCLK_ECO_ENABLED */ + + #ifdef CY_CFG_SYSCLK_EXTCLK_ENABLED + secure_config->extClkEnable = CY_CFG_SYSCLK_EXTCLK_ENABLED; + #endif /* CY_CFG_SYSCLK_EXTCLK_ENABLED */ + + #ifdef CY_CFG_SYSCLK_ILO_ENABLED + secure_config->iloEnable = CY_CFG_SYSCLK_ILO_ENABLED; + #endif /* CY_CFG_SYSCLK_ILO_ENABLED */ + + #ifdef CY_CFG_SYSCLK_WCO_ENABLED + secure_config->wcoEnable = CY_CFG_SYSCLK_WCO_ENABLED; + #endif /* CY_CFG_SYSCLK_WCO_ENABLED */ + + #ifdef CY_CFG_SYSCLK_FLL_ENABLED + secure_config->fllEnable = CY_CFG_SYSCLK_FLL_ENABLED; + #endif /* CY_CFG_SYSCLK_FLL_ENABLED */ + + #ifdef CY_CFG_SYSCLK_PLL0_ENABLED + secure_config->pll0Enable = CY_CFG_SYSCLK_PLL0_ENABLED; + #endif /* CY_CFG_SYSCLK_PLL0_ENABLED */ + + #ifdef CY_CFG_SYSCLK_PLL1_ENABLED + secure_config->pll1Enable = CY_CFG_SYSCLK_PLL1_ENABLED; + #endif /* CY_CFG_SYSCLK_PLL1_ENABLED */ + + #ifdef CY_CFG_SYSCLK_CLKPATH0_ENABLED + secure_config->path0Enable = CY_CFG_SYSCLK_CLKPATH0_ENABLED; + #endif /* CY_CFG_SYSCLK_CLKPATH0_ENABLED */ + + #ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED + secure_config->path1Enable = CY_CFG_SYSCLK_CLKPATH1_ENABLED; + #endif /* CY_CFG_SYSCLK_CLKPATH1_ENABLED */ + + #ifdef CY_CFG_SYSCLK_CLKPATH2_ENABLED + secure_config->path2Enable = CY_CFG_SYSCLK_CLKPATH2_ENABLED; + #endif /* CY_CFG_SYSCLK_CLKPATH2_ENABLED */ + + #ifdef CY_CFG_SYSCLK_CLKPATH3_ENABLED + secure_config->path3Enable = CY_CFG_SYSCLK_CLKPATH3_ENABLED; + #endif /* CY_CFG_SYSCLK_CLKPATH3_ENABLED */ + + #ifdef CY_CFG_SYSCLK_CLKPATH4_ENABLED + secure_config->path4Enable = CY_CFG_SYSCLK_CLKPATH4_ENABLED; + #endif /* CY_CFG_SYSCLK_CLKPATH4_ENABLED */ + + #ifdef CY_CFG_SYSCLK_CLKPATH5_ENABLED + secure_config->path5Enable = CY_CFG_SYSCLK_CLKPATH5_ENABLED; + #endif /* CY_CFG_SYSCLK_CLKPATH5_ENABLED */ + + #ifdef CY_CFG_SYSCLK_CLKFAST_ENABLED + secure_config->clkFastEnable = CY_CFG_SYSCLK_CLKFAST_ENABLED; + #endif /* CY_CFG_SYSCLK_CLKFAST_ENABLED */ + + #ifdef CY_CFG_SYSCLK_CLKPERI_ENABLED + secure_config->clkPeriEnable = CY_CFG_SYSCLK_CLKPERI_ENABLED; + #endif /* CY_CFG_SYSCLK_CLKPERI_ENABLED */ + + #ifdef CY_CFG_SYSCLK_CLKSLOW_ENABLED + secure_config->clkSlowEnable = CY_CFG_SYSCLK_CLKSLOW_ENABLED; + #endif /* CY_CFG_SYSCLK_CLKSLOW_ENABLED */ + + #ifdef CY_CFG_SYSCLK_CLKHF0_ENABLED + secure_config->clkHF0Enable = CY_CFG_SYSCLK_CLKHF0_ENABLED; + #endif /* CY_CFG_SYSCLK_CLKHF0_ENABLED */ + + #ifdef CY_CFG_SYSCLK_CLKHF1_ENABLED + secure_config->clkHF1Enable = CY_CFG_SYSCLK_CLKHF1_ENABLED; + #endif /* CY_CFG_SYSCLK_CLKHF1_ENABLED */ + + #ifdef CY_CFG_SYSCLK_CLKHF2_ENABLED + secure_config->clkHF2Enable = CY_CFG_SYSCLK_CLKHF2_ENABLED; + #endif /* CY_CFG_SYSCLK_CLKHF2_ENABLED */ + + #ifdef CY_CFG_SYSCLK_CLKHF3_ENABLED + secure_config->clkHF3Enable = CY_CFG_SYSCLK_CLKHF3_ENABLED; + #endif /* CY_CFG_SYSCLK_CLKHF3_ENABLED */ + + #ifdef CY_CFG_SYSCLK_CLKHF4_ENABLED + secure_config->clkHF4Enable = CY_CFG_SYSCLK_CLKHF4_ENABLED; + #endif /* CY_CFG_SYSCLK_CLKHF4_ENABLED */ + + #ifdef CY_CFG_SYSCLK_CLKHF5_ENABLED + secure_config->clkHF5Enable = CY_CFG_SYSCLK_CLKHF5_ENABLED; + #endif /* CY_CFG_SYSCLK_CLKHF5_ENABLED */ + + #ifdef CY_CFG_SYSCLK_CLKPUMP_ENABLED + secure_config->clkPumpEnable = CY_CFG_SYSCLK_CLKPUMP_ENABLED; + #endif /* CY_CFG_SYSCLK_CLKPUMP_ENABLED */ + + #ifdef CY_CFG_SYSCLK_CLKLF_ENABLED + secure_config->clkLFEnable = CY_CFG_SYSCLK_CLKLF_ENABLED; + #endif /* CY_CFG_SYSCLK_CLKLF_ENABLED */ + + #ifdef CY_CFG_SYSCLK_CLKBAK_ENABLED + secure_config->clkBakEnable = CY_CFG_SYSCLK_CLKBAK_ENABLED; + #endif /* CY_CFG_SYSCLK_CLKBAK_ENABLED */ + + #ifdef CY_CFG_SYSCLK_CLKTIMER_ENABLED + secure_config->clkTimerEnable = CY_CFG_SYSCLK_CLKTIMER_ENABLED; + #endif /* CY_CFG_SYSCLK_CLKTIMER_ENABLED */ + + #ifdef CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED + #error Configuration Error : ALT SYSTICK cannot be enabled for Secure devices. + #endif /* CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED */ + + #ifdef CY_CFG_SYSCLK_PILO_ENABLED + secure_config->piloEnable = CY_CFG_SYSCLK_PILO_ENABLED; + #endif /* CY_CFG_SYSCLK_PILO_ENABLED */ + + #ifdef CY_CFG_SYSCLK_ALTHF_ENABLED + secure_config->clkAltHfEnable = CY_CFG_SYSCLK_ALTHF_ENABLED; + #endif /* CY_CFG_SYSCLK_ALTHF_ENABLED */ + + #ifdef CY_CFG_PWR_LDO_VOLTAGE + secure_config->ldoVoltage = CY_CFG_PWR_LDO_VOLTAGE; + #endif /* CY_CFG_PWR_LDO_VOLTAGE */ + + #ifdef CY_CFG_PWR_REGULATOR_MODE_MIN + secure_config->pwrCurrentModeMin = CY_CFG_PWR_REGULATOR_MODE_MIN; + #endif /* CY_CFG_PWR_REGULATOR_MODE_MIN */ + + #ifdef CY_CFG_PWR_BUCK_VOLTAGE + secure_config->buckVoltage = CY_CFG_PWR_BUCK_VOLTAGE; + #endif /* CY_CFG_PWR_BUCK_VOLTAGE */ + + #ifdef CY_CFG_SYSCLK_ECO_FREQ + secure_config->ecoFreqHz = CY_CFG_SYSCLK_ECO_FREQ; + #endif /* CY_CFG_SYSCLK_ECO_FREQ */ + + #ifdef CY_CFG_SYSCLK_ECO_CLOAD + secure_config->ecoLoad = CY_CFG_SYSCLK_ECO_CLOAD; + #endif /* CY_CFG_SYSCLK_ECO_CLOAD */ + + #ifdef CY_CFG_SYSCLK_ECO_ESR + secure_config->ecoEsr = CY_CFG_SYSCLK_ECO_ESR; + #endif /* CY_CFG_SYSCLK_ECO_ESR */ + + #ifdef CY_CFG_SYSCLK_ECO_DRIVE_LEVEL + secure_config->ecoDriveLevel = CY_CFG_SYSCLK_ECO_DRIVE_LEVEL; + #endif /* CY_CFG_SYSCLK_ECO_DRIVE_LEVEL */ + + #ifdef CY_CFG_SYSCLK_ECO_GPIO_IN_PRT + secure_config->ecoInPort = CY_CFG_SYSCLK_ECO_GPIO_IN_PRT; + #endif /* CY_CFG_SYSCLK_ECO_GPIO_IN_PRT */ + + #ifdef CY_CFG_SYSCLK_ECO_GPIO_OUT_PRT + secure_config->ecoOutPort = CY_CFG_SYSCLK_ECO_GPIO_OUT_PRT; + #endif /* CY_CFG_SYSCLK_ECO_GPIO_OUT_PRT */ + + #ifdef CY_CFG_SYSCLK_ECO_GPIO_IN_PIN + secure_config->ecoInPinNum = CY_CFG_SYSCLK_ECO_GPIO_IN_PIN; + #endif /* CY_CFG_SYSCLK_ECO_GPIO_IN_PIN */ + + #ifdef CY_CFG_SYSCLK_ECO_GPIO_OUT_PIN + secure_config->ecoOutPinNum = CY_CFG_SYSCLK_ECO_GPIO_OUT_PIN; + #endif /* CY_CFG_SYSCLK_ECO_GPIO_OUT_PIN */ + + #ifdef CY_CFG_SYSCLK_EXTCLK_FREQ + secure_config->extClkFreqHz = CY_CFG_SYSCLK_EXTCLK_FREQ; + #endif /* CY_CFG_SYSCLK_EXTCLK_FREQ */ + + #ifdef CY_CFG_SYSCLK_EXTCLK_GPIO_PRT + secure_config->extClkPort = CY_CFG_SYSCLK_EXTCLK_GPIO_PRT; + #endif /* CY_CFG_SYSCLK_EXTCLK_GPIO_PRT */ + + #ifdef CY_CFG_SYSCLK_EXTCLK_GPIO_PIN + secure_config->extClkPinNum = CY_CFG_SYSCLK_EXTCLK_GPIO_PIN; + #endif /* CY_CFG_SYSCLK_EXTCLK_GPIO_PIN */ + + #ifdef CY_CFG_SYSCLK_EXTCLK_GPIO_HSIOM + secure_config->extClkHsiom = CY_CFG_SYSCLK_EXTCLK_GPIO_HSIOM; + #endif /* CY_CFG_SYSCLK_EXTCLK_GPIO_HSIOM */ + + #ifdef CY_CFG_SYSCLK_ILO_HIBERNATE + secure_config->iloHibernateON = CY_CFG_SYSCLK_ILO_HIBERNATE; + #endif /* CY_CFG_SYSCLK_ILO_HIBERNATE */ + + #ifdef CY_CFG_SYSCLK_WCO_BYPASS + secure_config->bypassEnable = CY_CFG_SYSCLK_WCO_BYPASS; + #endif /* CY_CFG_SYSCLK_WCO_BYPASS */ + + #ifdef CY_CFG_SYSCLK_WCO_IN_PRT + secure_config->wcoInPort = CY_CFG_SYSCLK_WCO_IN_PRT; + #endif /* CY_CFG_SYSCLK_WCO_IN_PRT */ + + #ifdef CY_CFG_SYSCLK_WCO_OUT_PRT + secure_config->wcoOutPort = CY_CFG_SYSCLK_WCO_OUT_PRT; + #endif /* CY_CFG_SYSCLK_WCO_OUT_PRT */ + + #ifdef CY_CFG_SYSCLK_WCO_IN_PIN + secure_config->wcoInPinNum = CY_CFG_SYSCLK_WCO_IN_PIN; + #endif /* CY_CFG_SYSCLK_WCO_IN_PIN */ + + #ifdef CY_CFG_SYSCLK_WCO_OUT_PIN + secure_config->wcoOutPinNum = CY_CFG_SYSCLK_WCO_OUT_PIN; + #endif /* CY_CFG_SYSCLK_WCO_OUT_PIN */ + + #ifdef CY_CFG_SYSCLK_FLL_OUT_FREQ + secure_config->fllOutFreqHz = CY_CFG_SYSCLK_FLL_OUT_FREQ; + #endif /* CY_CFG_SYSCLK_FLL_OUT_FREQ */ + + #ifdef CY_CFG_SYSCLK_FLL_MULT + secure_config->fllMult = CY_CFG_SYSCLK_FLL_MULT; + #endif /* CY_CFG_SYSCLK_FLL_MULT */ + + #ifdef CY_CFG_SYSCLK_FLL_REFDIV + secure_config->fllRefDiv = CY_CFG_SYSCLK_FLL_REFDIV; + #endif /* CY_CFG_SYSCLK_FLL_REFDIV */ + + #ifdef CY_CFG_SYSCLK_FLL_CCO_RANGE + secure_config->fllCcoRange = CY_CFG_SYSCLK_FLL_CCO_RANGE; + #endif /* CY_CFG_SYSCLK_FLL_CCO_RANGE */ + + #ifdef CY_CFG_SYSCLK_FLL_ENABLE_OUTDIV + secure_config->enableOutputDiv = CY_CFG_SYSCLK_FLL_ENABLE_OUTDIV; + #endif /* CY_CFG_SYSCLK_FLL_ENABLE_OUTDIV */ + + #ifdef CY_CFG_SYSCLK_FLL_LOCK_TOLERANCE + secure_config->lockTolerance = CY_CFG_SYSCLK_FLL_LOCK_TOLERANCE; + #endif /* CY_CFG_SYSCLK_FLL_LOCK_TOLERANCE */ + + #ifdef CY_CFG_SYSCLK_FLL_IGAIN + secure_config->igain = CY_CFG_SYSCLK_FLL_IGAIN; + #endif /* CY_CFG_SYSCLK_FLL_IGAIN */ + + #ifdef CY_CFG_SYSCLK_FLL_PGAIN + secure_config->pgain = CY_CFG_SYSCLK_FLL_PGAIN; + #endif /* CY_CFG_SYSCLK_FLL_PGAIN */ + + #ifdef CY_CFG_SYSCLK_FLL_SETTLING_COUNT + secure_config->settlingCount = CY_CFG_SYSCLK_FLL_SETTLING_COUNT; + #endif /* CY_CFG_SYSCLK_FLL_SETTLING_COUNT */ + + #ifdef CY_CFG_SYSCLK_FLL_OUTPUT_MODE + secure_config->outputMode = CY_CFG_SYSCLK_FLL_OUTPUT_MODE; + #endif /* CY_CFG_SYSCLK_FLL_OUTPUT_MODE */ + + #ifdef CY_CFG_SYSCLK_FLL_CCO_FREQ + secure_config->ccoFreq = CY_CFG_SYSCLK_FLL_CCO_FREQ; + #endif /* CY_CFG_SYSCLK_FLL_CCO_FREQ */ + + #ifdef CY_CFG_SYSCLK_PLL0_FEEDBACK_DIV + secure_config->pll0FeedbackDiv = CY_CFG_SYSCLK_PLL0_FEEDBACK_DIV; + #endif /* CY_CFG_SYSCLK_PLL0_FEEDBACK_DIV */ + + #ifdef CY_CFG_SYSCLK_PLL0_REFERENCE_DIV + secure_config->pll0ReferenceDiv = CY_CFG_SYSCLK_PLL0_REFERENCE_DIV; + #endif /* CY_CFG_SYSCLK_PLL0_REFERENCE_DIV */ + + #ifdef CY_CFG_SYSCLK_PLL0_OUTPUT_DIV + secure_config->pll0OutputDiv = CY_CFG_SYSCLK_PLL0_OUTPUT_DIV; + #endif /* CY_CFG_SYSCLK_PLL0_OUTPUT_DIV */ + + #ifdef CY_CFG_SYSCLK_PLL0_LF_MODE + secure_config->pll0LfMode = CY_CFG_SYSCLK_PLL0_LF_MODE; + #endif /* CY_CFG_SYSCLK_PLL0_LF_MODE */ + + #ifdef CY_CFG_SYSCLK_PLL0_OUTPUT_MODE + secure_config->pll0OutputMode = CY_CFG_SYSCLK_PLL0_OUTPUT_MODE; + #endif /* CY_CFG_SYSCLK_PLL0_OUTPUT_MODE */ + + #ifdef CY_CFG_SYSCLK_PLL0_OUTPUT_FREQ + secure_config->pll0OutFreqHz = CY_CFG_SYSCLK_PLL0_OUTPUT_FREQ; + #endif /* CY_CFG_SYSCLK_PLL0_OUTPUT_FREQ */ + + #ifdef CY_CFG_SYSCLK_PLL1_FEEDBACK_DIV + secure_config->pll1FeedbackDiv = CY_CFG_SYSCLK_PLL1_FEEDBACK_DIV; + #endif /* CY_CFG_SYSCLK_PLL1_FEEDBACK_DIV */ + + #ifdef CY_CFG_SYSCLK_PLL1_REFERENCE_DIV + secure_config->pll1ReferenceDiv = CY_CFG_SYSCLK_PLL1_REFERENCE_DIV; + #endif /* CY_CFG_SYSCLK_PLL1_REFERENCE_DIV */ + + #ifdef CY_CFG_SYSCLK_PLL1_OUTPUT_DIV + secure_config->pll1OutputDiv = CY_CFG_SYSCLK_PLL1_OUTPUT_DIV; + #endif /* CY_CFG_SYSCLK_PLL1_OUTPUT_DIV */ + + #ifdef CY_CFG_SYSCLK_PLL1_LF_MODE + secure_config->pll1LfMode = CY_CFG_SYSCLK_PLL1_LF_MODE; + #endif /* CY_CFG_SYSCLK_PLL1_LF_MODE */ + + #ifdef CY_CFG_SYSCLK_PLL1_OUTPUT_MODE + secure_config->pll1OutputMode = CY_CFG_SYSCLK_PLL1_OUTPUT_MODE; + #endif /* CY_CFG_SYSCLK_PLL1_OUTPUT_MODE */ + + #ifdef CY_CFG_SYSCLK_PLL1_OUTPUT_FREQ + secure_config->pll1OutFreqHz = CY_CFG_SYSCLK_PLL1_OUTPUT_FREQ; + #endif /* CY_CFG_SYSCLK_PLL1_OUTPUT_FREQ */ + + #ifdef CY_CFG_SYSCLK_CLKPATH0_SOURCE + secure_config->path0Src = CY_CFG_SYSCLK_CLKPATH0_SOURCE; + #endif /* CY_CFG_SYSCLK_CLKPATH0_SOURCE */ + + #ifdef CY_CFG_SYSCLK_CLKPATH1_SOURCE + secure_config->path1Src = CY_CFG_SYSCLK_CLKPATH1_SOURCE; + #endif /* CY_CFG_SYSCLK_CLKPATH1_SOURCE */ + + #ifdef CY_CFG_SYSCLK_CLKPATH2_SOURCE + secure_config->path2Src = CY_CFG_SYSCLK_CLKPATH2_SOURCE; + #endif /* CY_CFG_SYSCLK_CLKPATH2_SOURCE */ + + #ifdef CY_CFG_SYSCLK_CLKPATH3_SOURCE + secure_config->path3Src = CY_CFG_SYSCLK_CLKPATH3_SOURCE; + #endif /* CY_CFG_SYSCLK_CLKPATH3_SOURCE */ + + #ifdef CY_CFG_SYSCLK_CLKPATH4_SOURCE + secure_config->path4Src = CY_CFG_SYSCLK_CLKPATH4_SOURCE; + #endif /* CY_CFG_SYSCLK_CLKPATH4_SOURCE */ + + #ifdef CY_CFG_SYSCLK_CLKPATH5_SOURCE + secure_config->path5Src = CY_CFG_SYSCLK_CLKPATH5_SOURCE; + #endif /* CY_CFG_SYSCLK_CLKPATH5_SOURCE */ + + #ifdef CY_CFG_SYSCLK_CLKFAST_DIVIDER + secure_config->clkFastDiv = CY_CFG_SYSCLK_CLKFAST_DIVIDER; + #endif /* CY_CFG_SYSCLK_CLKFAST_DIVIDER */ + + #ifdef CY_CFG_SYSCLK_CLKPERI_DIVIDER + secure_config->clkPeriDiv = CY_CFG_SYSCLK_CLKPERI_DIVIDER; + #endif /* CY_CFG_SYSCLK_CLKPERI_DIVIDER */ + + #ifdef CY_CFG_SYSCLK_CLKSLOW_DIVIDER + secure_config->clkSlowDiv = CY_CFG_SYSCLK_CLKSLOW_DIVIDER; + #endif /* CY_CFG_SYSCLK_CLKSLOW_DIVIDER */ + + #ifdef CY_CFG_SYSCLK_CLKHF0_CLKPATH + secure_config->hf0Source = CY_CFG_SYSCLK_CLKHF0_CLKPATH; + #endif /* CY_CFG_SYSCLK_CLKHF0_CLKPATH */ + + #ifdef CY_CFG_SYSCLK_CLKHF0_DIVIDER + secure_config->hf0Divider = CY_CFG_SYSCLK_CLKHF0_DIVIDER; + #endif /* CY_CFG_SYSCLK_CLKHF0_DIVIDER */ + + #ifdef CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ + secure_config->hf0OutFreqMHz = CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ; + #endif /* CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ */ + + #ifdef CY_CFG_SYSCLK_CLKHF1_CLKPATH + secure_config->hf1Source = CY_CFG_SYSCLK_CLKHF1_CLKPATH; + #endif /* CY_CFG_SYSCLK_CLKHF1_CLKPATH */ + + #ifdef CY_CFG_SYSCLK_CLKHF1_DIVIDER + secure_config->hf1Divider = CY_CFG_SYSCLK_CLKHF1_DIVIDER; + #endif /* CY_CFG_SYSCLK_CLKHF1_DIVIDER */ + + #ifdef CY_CFG_SYSCLK_CLKHF1_FREQ_MHZ + secure_config->hf1OutFreqMHz = CY_CFG_SYSCLK_CLKHF1_FREQ_MHZ; + #endif /* CY_CFG_SYSCLK_CLKHF1_FREQ_MHZ */ + + #ifdef CY_CFG_SYSCLK_CLKHF2_CLKPATH + secure_config->hf2Source = CY_CFG_SYSCLK_CLKHF2_CLKPATH; + #endif /* CY_CFG_SYSCLK_CLKHF2_CLKPATH */ + + #ifdef CY_CFG_SYSCLK_CLKHF2_DIVIDER + secure_config->hf2Divider = CY_CFG_SYSCLK_CLKHF2_DIVIDER; + #endif /* CY_CFG_SYSCLK_CLKHF2_DIVIDER */ + + #ifdef CY_CFG_SYSCLK_CLKHF2_FREQ_MHZ + secure_config->hf2OutFreqMHz = CY_CFG_SYSCLK_CLKHF2_FREQ_MHZ; + #endif /* CY_CFG_SYSCLK_CLKHF2_FREQ_MHZ */ + + #ifdef CY_CFG_SYSCLK_CLKHF3_CLKPATH + secure_config->hf3Source = CY_CFG_SYSCLK_CLKHF3_CLKPATH; + #endif /* CY_CFG_SYSCLK_CLKHF3_CLKPATH */ + + #ifdef CY_CFG_SYSCLK_CLKHF3_DIVIDER + secure_config->hf3Divider = CY_CFG_SYSCLK_CLKHF3_DIVIDER; + #endif /* CY_CFG_SYSCLK_CLKHF3_DIVIDER */ + + #ifdef CY_CFG_SYSCLK_CLKHF3_FREQ_MHZ + secure_config->hf3OutFreqMHz = CY_CFG_SYSCLK_CLKHF3_FREQ_MHZ; + #endif /* CY_CFG_SYSCLK_CLKHF3_FREQ_MHZ */ + + #ifdef CY_CFG_SYSCLK_CLKHF4_CLKPATH + secure_config->hf4Source = CY_CFG_SYSCLK_CLKHF4_CLKPATH; + #endif /* CY_CFG_SYSCLK_CLKHF4_CLKPATH */ + + #ifdef CY_CFG_SYSCLK_CLKHF4_DIVIDER + secure_config->hf4Divider = CY_CFG_SYSCLK_CLKHF4_DIVIDER; + #endif /* CY_CFG_SYSCLK_CLKHF4_DIVIDER */ + + #ifdef CY_CFG_SYSCLK_CLKHF4_FREQ_MHZ + secure_config->hf4OutFreqMHz = CY_CFG_SYSCLK_CLKHF4_FREQ_MHZ; + #endif /* CY_CFG_SYSCLK_CLKHF4_FREQ_MHZ */ + + #ifdef CY_CFG_SYSCLK_CLKHF5_CLKPATH + secure_config->hf5Source = CY_CFG_SYSCLK_CLKHF5_CLKPATH; + #endif /* CY_CFG_SYSCLK_CLKHF5_CLKPATH */ + + #ifdef CY_CFG_SYSCLK_CLKHF5_DIVIDER + secure_config->hf5Divider = CY_CFG_SYSCLK_CLKHF5_DIVIDER; + #endif /* CY_CFG_SYSCLK_CLKHF5_DIVIDER */ + + #ifdef CY_CFG_SYSCLK_CLKHF5_FREQ_MHZ + secure_config->hf5OutFreqMHz = CY_CFG_SYSCLK_CLKHF5_FREQ_MHZ; + #endif /* CY_CFG_SYSCLK_CLKHF5_FREQ_MHZ */ + + #ifdef CY_CFG_SYSCLK_CLKPUMP_SOURCE + secure_config->pumpSource = CY_CFG_SYSCLK_CLKPUMP_SOURCE; + #endif /* CY_CFG_SYSCLK_CLKPUMP_SOURCE */ + + #ifdef CY_CFG_SYSCLK_CLKPUMP_DIVIDER + secure_config->pumpDivider = CY_CFG_SYSCLK_CLKPUMP_DIVIDER; + #endif /* CY_CFG_SYSCLK_CLKPUMP_DIVIDER */ + + #ifdef CY_CFG_SYSCLK_CLKLF_SOURCE + secure_config->clkLfSource = CY_CFG_SYSCLK_CLKLF_SOURCE; + #endif /* CY_CFG_SYSCLK_CLKLF_SOURCE */ + + #ifdef CY_CFG_SYSCLK_CLKBAK_SOURCE + secure_config->clkBakSource = CY_CFG_SYSCLK_CLKBAK_SOURCE; + #endif /* CY_CFG_SYSCLK_CLKBAK_SOURCE */ + + #ifdef CY_CFG_SYSCLK_CLKTIMER_SOURCE + secure_config->clkTimerSource = CY_CFG_SYSCLK_CLKTIMER_SOURCE; + #endif /* CY_CFG_SYSCLK_CLKTIMER_SOURCE */ + + #ifdef CY_CFG_SYSCLK_CLKTIMER_DIVIDER + secure_config->clkTimerDivider = CY_CFG_SYSCLK_CLKTIMER_DIVIDER; + #endif /* CY_CFG_SYSCLK_CLKTIMER_DIVIDER */ + + #ifdef CY_CFG_SYSCLK_CLKALTSYSTICK_SOURCE + secure_config->clkSrcAltSysTick = CY_CFG_SYSCLK_CLKALTSYSTICK_SOURCE; + #endif /* CY_CFG_SYSCLK_CLKALTSYSTICK_SOURCE */ + + #ifdef CY_CFG_SYSCLK_ALTHF_BLE_ECO_CLOAD + secure_config->altHFcLoad = CY_CFG_SYSCLK_ALTHF_BLE_ECO_CLOAD; + #endif /* CY_CFG_SYSCLK_ALTHF_BLE_ECO_CLOAD */ + + #ifdef CY_CFG_SYSCLK_ALTHF_BLE_ECO_TIME + secure_config->altHFxtalStartUpTime = CY_CFG_SYSCLK_ALTHF_BLE_ECO_TIME; + #endif /* CY_CFG_SYSCLK_ALTHF_BLE_ECO_TIME */ + + #ifdef CY_CFG_SYSCLK_ALTHF_BLE_ECO_FREQ + secure_config->altHFfreq = CY_CFG_SYSCLK_ALTHF_BLE_ECO_FREQ; + #endif /* CY_CFG_SYSCLK_ALTHF_BLE_ECO_FREQ */ + + #ifdef CY_CFG_SYSCLK_ALTHF_BLE_ECO_CLK_DIV + secure_config->altHFsysClkDiv = CY_CFG_SYSCLK_ALTHF_BLE_ECO_CLK_DIV; + #endif /* CY_CFG_SYSCLK_ALTHF_BLE_ECO_CLK_DIV */ + + #ifdef CY_CFG_SYSCLK_ALTHF_BLE_ECO_VOL_REGULATOR + secure_config->altHFvoltageReg = CY_CFG_SYSCLK_ALTHF_BLE_ECO_VOL_REGULATOR; + #endif /* CY_CFG_SYSCLK_ALTHF_BLE_ECO_VOL_REGULATOR */ + } +#endif //defined (CY_DEVICE_SECURE) && (CY_CPU_CORTEX_M4) +#if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) + __STATIC_INLINE void Cy_SysClk_ClkBakInit() + { + Cy_SysClk_ClkBakSetSource(CY_SYSCLK_BAK_IN_CLKLF); + } +#endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) +#if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) + __STATIC_INLINE void Cy_SysClk_ClkFastInit() + { + Cy_SysClk_ClkFastSetDivider(0U); + } +#endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) +#if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) + __STATIC_INLINE void Cy_SysClk_FllInit() + { + if (CY_SYSCLK_SUCCESS != Cy_SysClk_FllManualConfigure(&srss_0_clock_0_fll_0_fllConfig)) + { + cycfg_ClockStartupError(CY_CFG_SYSCLK_FLL_ERROR); + } + if (CY_SYSCLK_SUCCESS != Cy_SysClk_FllEnable(200000UL)) + { + cycfg_ClockStartupError(CY_CFG_SYSCLK_FLL_ERROR); + } + } +#endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) +#if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) + __STATIC_INLINE void Cy_SysClk_ClkHf0Init() + { + Cy_SysClk_ClkHfSetSource(0U, CY_CFG_SYSCLK_CLKHF0_CLKPATH); + Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE); + } +#endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) +#if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) + __STATIC_INLINE void Cy_SysClk_ClkHf2Init() + { + Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF2, CY_CFG_SYSCLK_CLKHF2_CLKPATH); + Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF2, CY_SYSCLK_CLKHF_DIVIDE_BY_2); + Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF2); + } +#endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) +#if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) + __STATIC_INLINE void Cy_SysClk_ClkHf3Init() + { + Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF3, CY_CFG_SYSCLK_CLKHF3_CLKPATH); + Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF3, CY_SYSCLK_CLKHF_NO_DIVIDE); + Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF3); + } +#endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) +#if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) + __STATIC_INLINE void Cy_SysClk_ClkHf4Init() + { + Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF4, CY_CFG_SYSCLK_CLKHF4_CLKPATH); + Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF4, CY_SYSCLK_CLKHF_NO_DIVIDE); + Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF4); + } +#endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) +#if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) + __STATIC_INLINE void Cy_SysClk_IloInit() + { + /* The WDT is unlocked in the default startup code */ + Cy_SysClk_IloEnable(); + Cy_SysClk_IloHibernateOn(true); + } +#endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) +#if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) + __STATIC_INLINE void Cy_SysClk_ClkLfInit() + { + /* The WDT is unlocked in the default startup code */ + Cy_SysClk_ClkLfSetSource(CY_SYSCLK_CLKLF_IN_WCO); + } +#endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) +#if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) + __STATIC_INLINE void Cy_SysClk_ClkPath0Init() + { + Cy_SysClk_ClkPathSetSource(0U, CY_CFG_SYSCLK_CLKPATH0_SOURCE); + } +#endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) +#if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) + __STATIC_INLINE void Cy_SysClk_ClkPath1Init() + { + Cy_SysClk_ClkPathSetSource(1U, CY_CFG_SYSCLK_CLKPATH1_SOURCE); + } +#endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) +#if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) + __STATIC_INLINE void Cy_SysClk_ClkPath2Init() + { + Cy_SysClk_ClkPathSetSource(2U, CY_CFG_SYSCLK_CLKPATH2_SOURCE); + } +#endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) +#if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) + __STATIC_INLINE void Cy_SysClk_ClkPeriInit() + { + Cy_SysClk_ClkPeriSetDivider(0U); + } +#endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) +#if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) + __STATIC_INLINE void Cy_SysClk_Pll0Init() + { + if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllManualConfigure(1U, &srss_0_clock_0_pll_0_pllConfig)) + { + cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR); + } + if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllEnable(1U, 10000u)) + { + cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR); + } + } +#endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) +#if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) + __STATIC_INLINE void Cy_SysClk_Pll1Init() + { + if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllManualConfigure(2U, &srss_0_clock_0_pll_1_pllConfig)) + { + cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR); + } + if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllEnable(2U, 10000u)) + { + cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR); + } + } +#endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) +#if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) + __STATIC_INLINE void Cy_SysClk_ClkSlowInit() + { + Cy_SysClk_ClkSlowSetDivider(0U); + } +#endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) +#if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) + __STATIC_INLINE void Cy_SysClk_ClkTimerInit() + { + Cy_SysClk_ClkTimerDisable(); + Cy_SysClk_ClkTimerSetSource(CY_SYSCLK_CLKTIMER_IN_IMO); + Cy_SysClk_ClkTimerSetDivider(0U); + Cy_SysClk_ClkTimerEnable(); + } +#endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) +#if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) + __STATIC_INLINE void Cy_SysClk_WcoInit() + { + (void)Cy_GPIO_Pin_FastInit(GPIO_PRT0, 0U, 0x00U, 0x00U, HSIOM_SEL_GPIO); + (void)Cy_GPIO_Pin_FastInit(GPIO_PRT0, 1U, 0x00U, 0x00U, HSIOM_SEL_GPIO); + if (CY_SYSCLK_SUCCESS != Cy_SysClk_WcoEnable(1000000UL)) + { + cycfg_ClockStartupError(CY_CFG_SYSCLK_WCO_ERROR); + } + } +#endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) +#if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) + __STATIC_INLINE void init_cycfg_power(void) + { + /* Reset the Backup domain on POR, XRES, BOD only if Backup domain is supplied by VDDD */ + #if (CY_CFG_PWR_VBACKUP_USING_VDDD) + #ifdef CY_CFG_SYSCLK_ILO_ENABLED + if (0u == Cy_SysLib_GetResetReason() /* POR, XRES, or BOD */) + { + Cy_SysLib_ResetBackupDomain(); + Cy_SysClk_IloDisable(); + Cy_SysClk_IloInit(); + } + #endif /* CY_CFG_SYSCLK_ILO_ENABLED */ + #endif /* CY_CFG_PWR_VBACKUP_USING_VDDD */ + /* Configure core regulator */ + #if !((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) + #if CY_CFG_PWR_USING_LDO + Cy_SysPm_LdoSetVoltage(CY_SYSPM_LDO_VOLTAGE_LP); + #else + Cy_SysPm_BuckEnable(CY_SYSPM_BUCK_OUT1_VOLTAGE_LP); + #endif /* CY_CFG_PWR_USING_LDO */ + #if CY_CFG_PWR_REGULATOR_MODE_MIN + Cy_SysPm_SystemSetMinRegulatorCurrent(); + #else + Cy_SysPm_SystemSetNormalRegulatorCurrent(); + #endif /* CY_CFG_PWR_REGULATOR_MODE_MIN */ + #endif /* !((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) */ + /* Configure PMIC */ + Cy_SysPm_UnlockPmic(); + #if CY_CFG_PWR_USING_PMIC + Cy_SysPm_PmicEnableOutput(); + #else + Cy_SysPm_PmicDisableOutput(); + #endif /* CY_CFG_PWR_USING_PMIC */ + } +#endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) + + +void init_cycfg_system(void) +{ + #if ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) + cy_en_pra_status_t configStatus; + init_cycfg_secure_struct(&srss_0_clock_0_secureConfig); + #if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE_NUM != 0UL) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH_NUM == 0UL)) + #error Configuration Error : ECO, WCO, ALTHF, EXTCLK, ILO, PILO cannot drive HF0. + #endif + #if ((CY_CFG_SYSCLK_CLKPATH1_SOURCE_NUM != 0UL) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH_NUM == 1UL)) + #error Configuration Error : ECO, WCO, ALTHF, EXTCLK, ILO, PILO cannot drive HF0. + #endif + #if ((CY_CFG_SYSCLK_CLKPATH2_SOURCE_NUM != 0UL) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH_NUM == 2UL)) + #error Configuration Error : ECO, WCO, ALTHF, EXTCLK, ILO, PILO cannot drive HF0. + #endif + #if ((CY_CFG_SYSCLK_CLKPATH3_SOURCE_NUM != 0UL) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH_NUM == 3UL)) + #error Configuration Error : ECO, WCO, ALTHF, EXTCLK, ILO, PILO cannot drive HF0. + #endif + #if ((CY_CFG_SYSCLK_CLKPATH4_SOURCE_NUM != 0UL) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH_NUM == 4UL)) + #error Configuration Error : ECO, WCO, ALTHF, EXTCLK, ILO, PILO cannot drive HF0. + #endif + #if ((CY_CFG_SYSCLK_CLKPATH5_SOURCE_NUM != 0UL) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH_NUM == 5UL)) + #error Configuration Error : ECO, WCO, ALTHF, EXTCLK, ILO, PILO cannot drive HF0. + #endif + + configStatus = CY_PRA_FUNCTION_CALL_RETURN_PARAM(CY_PRA_MSG_TYPE_SYS_CFG_FUNC, + CY_PRA_FUNC_INIT_CYCFG_DEVICE, + &srss_0_clock_0_secureConfig); + if ( configStatus != CY_PRA_STATUS_SUCCESS ) + { + cycfg_ClockStartupError(configStatus); + } + + #ifdef CY_CFG_SYSCLK_EXTCLK_FREQ + Cy_SysClk_ExtClkSetFrequency(CY_CFG_SYSCLK_EXTCLK_FREQ); + #endif /* CY_CFG_SYSCLK_EXTCLK_FREQ */ + #else /* ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) */ + + /* Set worst case memory wait states (! ultra low power, 150 MHz), will update at the end */ + Cy_SysLib_SetWaitStates(false, 150UL); + #ifdef CY_CFG_PWR_ENABLED + #ifdef CY_CFG_PWR_INIT + init_cycfg_power(); + #else + #warning Power system will not be configured. Update power personality to v1.20 or later. + #endif /* CY_CFG_PWR_INIT */ + #endif /* CY_CFG_PWR_ENABLED */ + + /* Reset the core clock path to default and disable all the FLLs/PLLs */ + Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE); + Cy_SysClk_ClkFastSetDivider(0U); + Cy_SysClk_ClkPeriSetDivider(1U); + Cy_SysClk_ClkSlowSetDivider(0U); + for (uint32_t pll = CY_SRSS_NUM_PLL; pll > 0UL; --pll) /* PLL 1 is the first PLL. 0 is invalid. */ + { + (void)Cy_SysClk_PllDisable(pll); + } + Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH1, CY_SYSCLK_CLKPATH_IN_IMO); + + if ((CY_SYSCLK_CLKHF_IN_CLKPATH0 == Cy_SysClk_ClkHfGetSource(0UL)) && + (CY_SYSCLK_CLKPATH_IN_WCO == Cy_SysClk_ClkPathGetSource(CY_SYSCLK_CLKHF_IN_CLKPATH0))) + { + Cy_SysClk_ClkHfSetSource(0U, CY_SYSCLK_CLKHF_IN_CLKPATH1); + } + + Cy_SysClk_FllDisable(); + Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH0, CY_SYSCLK_CLKPATH_IN_IMO); + Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH0); + #ifdef CY_IP_MXBLESS + (void)Cy_BLE_EcoReset(); + #endif + + + /* Enable all source clocks */ + #ifdef CY_CFG_SYSCLK_PILO_ENABLED + Cy_SysClk_PiloInit(); + #endif + + #ifdef CY_CFG_SYSCLK_WCO_ENABLED + Cy_SysClk_WcoInit(); + #endif + + #ifdef CY_CFG_SYSCLK_CLKLF_ENABLED + Cy_SysClk_ClkLfInit(); + #endif + + #ifdef CY_CFG_SYSCLK_ALTHF_ENABLED + Cy_SysClk_AltHfInit(); + #endif + + #ifdef CY_CFG_SYSCLK_ECO_ENABLED + Cy_SysClk_EcoInit(); + #endif + + #ifdef CY_CFG_SYSCLK_EXTCLK_ENABLED + Cy_SysClk_ExtClkInit(); + #endif + + /* Configure CPU clock dividers */ + #ifdef CY_CFG_SYSCLK_CLKFAST_ENABLED + Cy_SysClk_ClkFastInit(); + #endif + + #ifdef CY_CFG_SYSCLK_CLKPERI_ENABLED + Cy_SysClk_ClkPeriInit(); + #endif + + #ifdef CY_CFG_SYSCLK_CLKSLOW_ENABLED + Cy_SysClk_ClkSlowInit(); + #endif + + #if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE_NUM == 0x6UL) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH_NUM == 0U)) + /* Configure HFCLK0 to temporarily run from IMO to initialize other clocks */ + Cy_SysClk_ClkPathSetSource(1UL, CY_SYSCLK_CLKPATH_IN_IMO); + Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH1); + #else + #ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED + Cy_SysClk_ClkPath1Init(); + #endif + #endif + + /* Configure Path Clocks */ + #ifdef CY_CFG_SYSCLK_CLKPATH0_ENABLED + Cy_SysClk_ClkPath0Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH2_ENABLED + Cy_SysClk_ClkPath2Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH3_ENABLED + Cy_SysClk_ClkPath3Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH4_ENABLED + Cy_SysClk_ClkPath4Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH5_ENABLED + Cy_SysClk_ClkPath5Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH6_ENABLED + Cy_SysClk_ClkPath6Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH7_ENABLED + Cy_SysClk_ClkPath7Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH8_ENABLED + Cy_SysClk_ClkPath8Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH9_ENABLED + Cy_SysClk_ClkPath9Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH10_ENABLED + Cy_SysClk_ClkPath10Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH11_ENABLED + Cy_SysClk_ClkPath11Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH12_ENABLED + Cy_SysClk_ClkPath12Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH13_ENABLED + Cy_SysClk_ClkPath13Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH14_ENABLED + Cy_SysClk_ClkPath14Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH15_ENABLED + Cy_SysClk_ClkPath15Init(); + #endif + + /* Configure and enable FLL */ + #ifdef CY_CFG_SYSCLK_FLL_ENABLED + Cy_SysClk_FllInit(); + #endif + + Cy_SysClk_ClkHf0Init(); + + #if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE_NUM == 0x6UL) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH_NUM == 0U)) + #ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED + /* Apply the ClkPath1 user setting */ + Cy_SysClk_ClkPath1Init(); + #endif + #endif + + /* Configure and enable PLLs */ + #ifdef CY_CFG_SYSCLK_PLL0_ENABLED + Cy_SysClk_Pll0Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL1_ENABLED + Cy_SysClk_Pll1Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL2_ENABLED + Cy_SysClk_Pll2Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL3_ENABLED + Cy_SysClk_Pll3Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL4_ENABLED + Cy_SysClk_Pll4Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL5_ENABLED + Cy_SysClk_Pll5Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL6_ENABLED + Cy_SysClk_Pll6Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL7_ENABLED + Cy_SysClk_Pll7Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL8_ENABLED + Cy_SysClk_Pll8Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL9_ENABLED + Cy_SysClk_Pll9Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL10_ENABLED + Cy_SysClk_Pll10Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL11_ENABLED + Cy_SysClk_Pll11Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL12_ENABLED + Cy_SysClk_Pll12Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL13_ENABLED + Cy_SysClk_Pll13Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL14_ENABLED + Cy_SysClk_Pll14Init(); + #endif + + /* Configure HF clocks */ + #ifdef CY_CFG_SYSCLK_CLKHF1_ENABLED + Cy_SysClk_ClkHf1Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF2_ENABLED + Cy_SysClk_ClkHf2Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF3_ENABLED + Cy_SysClk_ClkHf3Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF4_ENABLED + Cy_SysClk_ClkHf4Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF5_ENABLED + Cy_SysClk_ClkHf5Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF6_ENABLED + Cy_SysClk_ClkHf6Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF7_ENABLED + Cy_SysClk_ClkHf7Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF8_ENABLED + Cy_SysClk_ClkHf8Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF9_ENABLED + Cy_SysClk_ClkHf9Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF10_ENABLED + Cy_SysClk_ClkHf10Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF11_ENABLED + Cy_SysClk_ClkHf11Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF12_ENABLED + Cy_SysClk_ClkHf12Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF13_ENABLED + Cy_SysClk_ClkHf13Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF14_ENABLED + Cy_SysClk_ClkHf14Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF15_ENABLED + Cy_SysClk_ClkHf15Init(); + #endif + + /* Configure miscellaneous clocks */ + #ifdef CY_CFG_SYSCLK_CLKTIMER_ENABLED + Cy_SysClk_ClkTimerInit(); + #endif + + #ifdef CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED + Cy_SysClk_ClkAltSysTickInit(); + #endif + + #ifdef CY_CFG_SYSCLK_CLKPUMP_ENABLED + Cy_SysClk_ClkPumpInit(); + #endif + + #ifdef CY_CFG_SYSCLK_CLKBAK_ENABLED + Cy_SysClk_ClkBakInit(); + #endif + + /* Configure default enabled clocks */ + #ifdef CY_CFG_SYSCLK_ILO_ENABLED + Cy_SysClk_IloInit(); + #endif + + #ifndef CY_CFG_SYSCLK_IMO_ENABLED + #error the IMO must be enabled for proper chip operation + #endif + + #endif /* ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) */ + + #ifdef CY_CFG_SYSCLK_MFO_ENABLED + Cy_SysClk_MfoInit(); + #endif + + #ifdef CY_CFG_SYSCLK_CLKMF_ENABLED + Cy_SysClk_ClkMfInit(); + #endif + + #if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) + /* Set accurate flash wait states */ + #if (defined (CY_CFG_PWR_ENABLED) && defined (CY_CFG_SYSCLK_CLKHF0_ENABLED)) + Cy_SysLib_SetWaitStates(CY_CFG_PWR_USING_ULP != 0, CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ); + #endif + + /* Update System Core Clock values for correct Cy_SysLib_Delay functioning */ + SystemCoreClockUpdate(); + #ifndef CY_CFG_SYSCLK_ILO_ENABLED + #ifdef CY_CFG_SYSCLK_CLKLF_ENABLED + /* Wait 4 ILO cycles in case of unfinished CLKLF clock source transition */ + Cy_SysLib_DelayUs(200U); + #endif + Cy_SysClk_IloDisable(); + Cy_SysClk_IloHibernateOn(false); + #endif + + #endif /* ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) */ + + +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_0_obj); +#endif //defined (CY_USING_HAL) + +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_1_obj); +#endif //defined (CY_USING_HAL) + +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_2_obj); +#endif //defined (CY_USING_HAL) +} diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h similarity index 90% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h index 645a990b84..f3c1c9450f 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h @@ -4,8 +4,8 @@ * Description: * System configuration * This file was automatically generated and should not be modified. -* Device Configurator: 2.0.0.1483 -* Device Support Library (../../../psoc6pdl): 1.4.1.2240 +* cfg-backend-cli: 1.2.0.1483 +* Device Support Library (libs/psoc6pdl): 1.6.0.4266 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation @@ -29,7 +29,8 @@ #include "cycfg_notices.h" #include "cy_sysclk.h" -#include "cy_systick.h" +#include "cy_pra.h" +#include "cy_pra_cfg.h" #if defined (CY_USING_HAL) #include "cyhal_hwmgr.h" #endif //defined (CY_USING_HAL) @@ -42,22 +43,26 @@ extern "C" { #define cpuss_0_dap_0_ENABLED 1U #define srss_0_clock_0_ENABLED 1U -#define srss_0_clock_0_altsystickclk_0_ENABLED 1U #define srss_0_clock_0_bakclk_0_ENABLED 1U #define srss_0_clock_0_fastclk_0_ENABLED 1U #define srss_0_clock_0_fll_0_ENABLED 1U #define srss_0_clock_0_hfclk_0_ENABLED 1U #define CY_CFG_SYSCLK_CLKHF0 0UL +#define CY_CFG_SYSCLK_CLKHF0_CLKPATH_NUM 0UL #define srss_0_clock_0_hfclk_2_ENABLED 1U #define CY_CFG_SYSCLK_CLKHF2 2UL +#define CY_CFG_SYSCLK_CLKHF2_CLKPATH_NUM 0UL #define srss_0_clock_0_hfclk_3_ENABLED 1U #define CY_CFG_SYSCLK_CLKHF3 3UL +#define CY_CFG_SYSCLK_CLKHF3_CLKPATH_NUM 0UL #define srss_0_clock_0_hfclk_4_ENABLED 1U #define CY_CFG_SYSCLK_CLKHF4 4UL +#define CY_CFG_SYSCLK_CLKHF4_CLKPATH_NUM 0UL #define srss_0_clock_0_ilo_0_ENABLED 1U #define srss_0_clock_0_imo_0_ENABLED 1U #define srss_0_clock_0_lfclk_0_ENABLED 1U #define CY_CFG_SYSCLK_CLKLF_FREQ_HZ 32768 +#define CY_CFG_SYSCLK_CLKLF_SOURCE CY_SYSCLK_CLKLF_IN_WCO #define srss_0_clock_0_pathmux_0_ENABLED 1U #define srss_0_clock_0_pathmux_1_ENABLED 1U #define srss_0_clock_0_pathmux_2_ENABLED 1U diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/qspi_config.cfg b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/qspi_config.cfg similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/qspi_config.cfg rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/qspi_config.cfg diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list similarity index 86% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list index 42a9e417f6..47fe487d31 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list @@ -1,5 +1,5 @@ -[Device=CYB0644ABZI-D44] - +[Device=CYB0644ABZI-S2D44] + [Blocks] # WIFI # CYBSP_WIFI_SDIO diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/design.cycapsense b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/design.cycapsense similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/design.cycapsense rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/design.cycapsense diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi similarity index 98% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi index 6df618b3a8..58e8231d08 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi @@ -1,5 +1,5 @@ - + PSoC 6.xml diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/design.modus b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/design.modus similarity index 98% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/design.modus rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/design.modus index fb0a6ecc7f..853df6b348 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/design.modus +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/design.modus @@ -1,5 +1,5 @@ - + @@ -268,11 +268,6 @@ - - - - - @@ -286,7 +281,7 @@ - + @@ -345,7 +340,7 @@ - + @@ -386,7 +381,7 @@ - + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/PeripheralPins.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/PeripheralPins.c similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/PeripheralPins.c rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/PeripheralPins.c diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/cybsp.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/cybsp.c similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/cybsp.c rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/cybsp.c diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/cybsp.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/cybsp.h similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/cybsp.h rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/cybsp.h diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/cybsp_types.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/cybsp_types.h similarity index 90% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/cybsp_types.h rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/cybsp_types.h index d8d83a8b18..5652289a39 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/cybsp_types.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/cybsp_types.h @@ -1,9 +1,9 @@ /***************************************************************************//** -* \file CY8CKIT-064S2-4343W/cybsp_types.h +* \file CY8CKIT-064B0S2-4343W/cybsp_types.h * * Description: * Provides APIs for interacting with the hardware contained on the Cypress -* CY8CKIT-064S2-4343W pioneer kit. +* CY8CKIT-064B0S2-4343W pioneer kit. * ******************************************************************************** * \copyright @@ -100,32 +100,32 @@ extern "C" { * \{ */ -/** LED 8; User LED1 */ +/** LED 8; User LED1 (orange) */ #ifndef CYBSP_LED8 #define CYBSP_LED8 (P1_5) #endif -/** LED 9; User LED2 */ +/** LED 9; User LED2 (red) */ #ifndef CYBSP_LED9 -#define CYBSP_LED9 (P13_7) +#define CYBSP_LED9 (P11_1) #endif /** LED 5: RGB LED - Red; User LED3 */ #ifndef CYBSP_LED_RGB_RED -#define CYBSP_LED_RGB_RED (P0_3) +#define CYBSP_LED_RGB_RED (P1_1) #endif /** LED 5: RGB LED - Green; User LED4 */ #ifndef CYBSP_LED_RGB_GREEN -#define CYBSP_LED_RGB_GREEN (P1_1) +#define CYBSP_LED_RGB_GREEN (P0_5) #endif /** LED 5: RGB LED - Blue; User LED5 */ #ifndef CYBSP_LED_RGB_BLUE -#define CYBSP_LED_RGB_BLUE (P11_1) +#define CYBSP_LED_RGB_BLUE (P7_3) #endif -/** LED 8; User LED1 */ +/** LED 8; User LED1 (orange) */ #ifndef CYBSP_USER_LED1 #define CYBSP_USER_LED1 (CYBSP_LED8) #endif -/** LED 9; User LED2 */ +/** LED 9; User LED2 (red) */ #ifndef CYBSP_USER_LED2 #define CYBSP_USER_LED2 (CYBSP_LED9) #endif @@ -141,7 +141,7 @@ extern "C" { #ifndef CYBSP_USER_LED5 #define CYBSP_USER_LED5 (CYBSP_LED_RGB_BLUE) #endif -/** LED 8; User LED1 */ +/** LED 8; User LED1 (orange) */ #ifndef CYBSP_USER_LED #define CYBSP_USER_LED (CYBSP_USER_LED1) #endif @@ -158,11 +158,19 @@ extern "C" { #ifndef CYBSP_SW2 #define CYBSP_SW2 (P0_4) #endif +/** Switch 4; User Button 2 */ +#ifndef CYBSP_SW4 +#define CYBSP_SW4 (P1_4) +#endif /** Switch 2; User Button 1 */ #ifndef CYBSP_USER_BTN1 #define CYBSP_USER_BTN1 (CYBSP_SW2) #endif +/** Switch 4; User Button 2 */ +#ifndef CYBSP_USER_BTN2 +#define CYBSP_USER_BTN2 (CYBSP_SW4) +#endif /** Switch 2; User Button 1 */ #ifndef CYBSP_USER_BTN #define CYBSP_USER_BTN (CYBSP_USER_BTN1) @@ -206,7 +214,7 @@ extern "C" { #endif /** Pin: WIFI Host Wakeup */ #ifndef CYBSP_WIFI_HOST_WAKE -#define CYBSP_WIFI_HOST_WAKE (P2_7) +#define CYBSP_WIFI_HOST_WAKE (P4_1) #endif /** Pin: BT UART RX */ @@ -232,11 +240,11 @@ extern "C" { #endif /** Pin: BT Host Wakeup */ #ifndef CYBSP_BT_HOST_WAKE -#define CYBSP_BT_HOST_WAKE (P3_5) +#define CYBSP_BT_HOST_WAKE (P4_0) #endif /** Pin: BT Device Wakeup */ #ifndef CYBSP_BT_DEVICE_WAKE -#define CYBSP_BT_DEVICE_WAKE (P4_0) +#define CYBSP_BT_DEVICE_WAKE (P3_5) #endif /** Pin: UART RX */ @@ -247,6 +255,14 @@ extern "C" { #ifndef CYBSP_DEBUG_UART_TX #define CYBSP_DEBUG_UART_TX (P5_1) #endif +/** Pin: UART RX */ +#ifndef CYBSP_DEBUG_UART_RTS +#define CYBSP_DEBUG_UART_RTS (P5_2) +#endif +/** Pin: UART TX */ +#ifndef CYBSP_DEBUG_UART_CTS +#define CYBSP_DEBUG_UART_CTS (P5_3) +#endif /** Pin: I2C SCL */ #ifndef CYBSP_I2C_SCL @@ -295,6 +311,11 @@ extern "C" { #define CYBSP_QSPI_SCK (P11_7) #endif +/** Host-wake GPIO drive mode */ +#define CYBSP_WIFI_HOST_WAKE_GPIO_DM (CYHAL_GPIO_DRIVE_ANALOG) +/** Host-wake IRQ event */ +#define CYBSP_WIFI_HOST_WAKE_IRQ_EVENT (CYHAL_GPIO_IRQ_RISE) + /** Pin: SPI MOSI */ #ifndef CYBSP_SPI_MOSI #define CYBSP_SPI_MOSI (P12_0) @@ -312,11 +333,6 @@ extern "C" { #define CYBSP_SPI_CS (P12_4) #endif -/** Host-wake GPIO drive mode */ -#define CYBSP_WIFI_HOST_WAKE_GPIO_DM (CYHAL_GPIO_DRIVE_ANALOG) -/** Host-wake IRQ event */ -#define CYBSP_WIFI_HOST_WAKE_IRQ_EVENT (CYHAL_GPIO_IRQ_RISE) - /** \} group_bsp_pins_comm */ @@ -379,15 +395,15 @@ extern "C" { #endif /** Arduino D7 */ #ifndef CYBSP_D7 -#define CYBSP_D7 (P0_2) +#define CYBSP_D7 (P5_7) #endif /** Arduino D8 */ #ifndef CYBSP_D8 -#define CYBSP_D8 (P13_0) +#define CYBSP_D8 (P7_5) #endif /** Arduino D9 */ #ifndef CYBSP_D9 -#define CYBSP_D9 (P13_1) +#define CYBSP_D9 (P7_6) #endif /** Arduino D10 */ #ifndef CYBSP_D10 @@ -476,31 +492,15 @@ extern "C" { #endif /** Cypress J2 Header pin 14 */ #ifndef CYBSP_J2_14 -#define CYBSP_J2_14 (NC) +#define CYBSP_J2_14 (P9_6) #endif /** Cypress J2 Header pin 15 */ #ifndef CYBSP_J2_15 -#define CYBSP_J2_15 (P6_2) +#define CYBSP_J2_15 (P10_7) #endif /** Cypress J2 Header pin 16 */ #ifndef CYBSP_J2_16 -#define CYBSP_J2_16 (P9_6) -#endif -/** Cypress J2 Header pin 17 */ -#ifndef CYBSP_J2_17 -#define CYBSP_J2_17 (P6_3) -#endif -/** Cypress J2 Header pin 18 */ -#ifndef CYBSP_J2_18 -#define CYBSP_J2_18 (P9_7) -#endif -/** Cypress J2 Header pin 19 */ -#ifndef CYBSP_J2_19 -#define CYBSP_J2_19 (P13_6) -#endif -/** Cypress J2 Header pin 20 */ -#ifndef CYBSP_J2_20 -#define CYBSP_J2_20 (P13_7) +#define CYBSP_J2_16 (P9_7) #endif /** \} group_bsp_pins_j2 */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xxa_cm0plus.sct b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xxa_cm0plus.sct similarity index 97% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xxa_cm0plus.sct rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xxa_cm0plus.sct index 4e700abeaf..41d333f414 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xxa_cm0plus.sct +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xxa_cm0plus.sct @@ -4,7 +4,7 @@ ;******************************************************************************* ;* \file cyb06xxa_cm0plus.sct -;* \version 2.70.1 +;* \version 2.80 ;* ;* Linker file for the ARMCC. ;* @@ -55,7 +55,7 @@ #endif #if !defined(MBED_ROM_SIZE) - #define MBED_ROM_SIZE 0x80000 + #define MBED_ROM_SIZE 0x00010000 #endif ;* MBED_APP_SIZE is being used by the bootloader build script and @@ -67,11 +67,11 @@ #endif #if !defined(MBED_RAM_START) - #define MBED_RAM_START 0x08000000 + #define MBED_RAM_START 0x080E0000 #endif #if !defined(MBED_RAM_SIZE) - #define MBED_RAM_SIZE 0x00010000 + #define MBED_RAM_SIZE 0x0000C000 #endif #if !defined(MBED_PUBLIC_RAM_SIZE) @@ -186,11 +186,11 @@ LR_IROM1 (FLASH_START + BOOT_HEADER_SIZE) (FLASH_SIZE - BOOT_HEADER_SIZE - 0x800 ; Application heap area (HEAP) ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM2) - { + { } - + ; Stack region growing down - ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE + ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE { } } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_02_cm0plus.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_02_cm0plus.S similarity index 95% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_02_cm0plus.S rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_02_cm0plus.S index 2ebb953cfd..332737ec48 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_02_cm0plus.S +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_02_cm0plus.S @@ -1,5 +1,5 @@ ;/**************************************************************************//** -; * @file startup_psoc6_02_cm0plus.S +; * @file startup_psoc6_02_cm0plus.s ; * @brief CMSIS Core Device Startup File for ; * ARMCM0plus Device Series ; * @version V5.00 @@ -32,9 +32,12 @@ EXPORT __Vectors EXPORT __Vectors_End EXPORT __Vectors_Size - IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| -__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Base| + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Length| + +__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Base| + |Image$$ARM_LIB_STACK$$ZI$$Length| ; Top of Stack + DCD Reset_Handler ; Reset Handler DCD 0x0000000D ; NMI Handler located at ROM code @@ -101,6 +104,9 @@ Reset_Handler PROC ; Define strong function for startup customization BL Cy_OnResetUser + ; Disable global interrupts + CPSID I + ; Copy vectors from ROM to RAM LDR r1, =__Vectors LDR r0, =__ramVectors @@ -207,6 +213,10 @@ Internal7_IRQHandler ALIGN + +; User Initial Stack & Heap + IMPORT __use_two_region_memory + END diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cyb06xxa_cm0plus.ld b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cyb06xxa_cm0plus.ld similarity index 99% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cyb06xxa_cm0plus.ld rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cyb06xxa_cm0plus.ld index a987e9bd98..633610f14f 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cyb06xxa_cm0plus.ld +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cyb06xxa_cm0plus.ld @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cyb06xxa_cm0plus.ld -* \version 2.70.1 +* \version 2.80 * * Linker file for the GNU C compiler. * @@ -53,7 +53,7 @@ ENTRY(Reset_Handler) #endif #if !defined(MBED_ROM_SIZE) - #define MBED_ROM_SIZE 0x80000 + #define MBED_ROM_SIZE 0x00010000 #endif /* MBED_APP_SIZE is being used by the bootloader build script and @@ -65,11 +65,11 @@ ENTRY(Reset_Handler) #endif #if !defined(MBED_RAM_START) - #define MBED_RAM_START 0x08000000 + #define MBED_RAM_START 0x080E0000 #endif #if !defined(MBED_RAM_SIZE) - #define MBED_RAM_SIZE 0x00010000 + #define MBED_RAM_SIZE 0x0000C000 #endif #if !defined(MBED_PUBLIC_RAM_SIZE) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm0plus.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm0plus.S similarity index 99% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm0plus.S rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm0plus.S index 3fed47b01f..2641f62389 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm0plus.S +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm0plus.S @@ -148,6 +148,7 @@ Cy_OnResetUser: Reset_Handler: bl Cy_OnResetUser + cpsid i /* Firstly it copies data from read only memory to RAM. There are two schemes * to copy. One can copy more than one sections. Another can only copy @@ -282,7 +283,11 @@ Reset_Handler: str r0, [r1] dsb 0xF - bl _start +#ifndef __NO_SYSTEM_INIT + bl SystemInit +#endif + + bl main /* Should never get here */ b . diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cyb06xxa_cm0plus.icf b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cyb06xxa_cm0plus.icf similarity index 98% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cyb06xxa_cm0plus.icf rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cyb06xxa_cm0plus.icf index fe9af7acbb..31f77fc13a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cyb06xxa_cm0plus.icf +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cyb06xxa_cm0plus.icf @@ -1,6 +1,6 @@ /******************************************************************************* * \file cyb06xxa_cm0plus.icf -* \version 2.70.1 +* \version 2.80 * * Linker file for the IAR compiler. * @@ -54,7 +54,7 @@ if (!isdefinedsymbol(MBED_APP_START)) { } if (!isdefinedsymbol(MBED_ROM_SIZE)) { - define symbol MBED_ROM_SIZE = 0x80000; + define symbol MBED_ROM_SIZE = 0x00010000; } /* MBED_APP_SIZE is being used by the bootloader build script and @@ -66,11 +66,11 @@ if (!isdefinedsymbol(MBED_APP_SIZE)) { } if (!isdefinedsymbol(MBED_RAM_START)) { - define symbol MBED_RAM_START = 0x08000000; + define symbol MBED_RAM_START = 0x080E0000; } if (!isdefinedsymbol(MBED_RAM_SIZE)) { - define symbol MBED_RAM_SIZE = 0x00010000; + define symbol MBED_RAM_SIZE = 0x0000C000; } /*-Sizes-*/ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/device/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_psoc6_02_cm0plus.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/device/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_psoc6_02_cm0plus.S similarity index 96% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/device/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_psoc6_02_cm0plus.S rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/device/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_psoc6_02_cm0plus.S index 3b77acffe3..3fa2e866e7 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/device/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_psoc6_02_cm0plus.S +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/device/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_psoc6_02_cm0plus.S @@ -1,5 +1,5 @@ ;/**************************************************************************//** -; * @file startup_psoc6_02_cm0plus.S +; * @file startup_psoc6_02_cm0plus.s ; * @brief CMSIS Core Device Startup File for ; * ARMCM0plus Device Series ; * @version V5.00 @@ -49,6 +49,7 @@ EXTERN __iar_program_start EXTERN SystemInit EXTERN __iar_data_init3 + EXTERN __iar_dynamic_initialization PUBLIC __vector_table PUBLIC __vector_table_0x1c PUBLIC __Vectors @@ -157,6 +158,9 @@ Reset_Handler LDR R0, =Cy_OnResetUser BLX R0 + ; Disable global interrupts + CPSID I + ; Copy vectors from ROM to RAM LDR r1, =__vector_table LDR r0, =__ramVectors @@ -176,6 +180,16 @@ intvec_copy STR r0, [r1] dsb + ; Initialize data sections + LDR R0, =__iar_data_init3 + BLX R0 + + ; --manual_dynamic_initialization + BL __iar_dynamic_initialization + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start BLX R0 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM0P/system_psoc6_cm0plus.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/device/COMPONENT_CM0P/system_psoc6_cm0plus.c similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM0P/system_psoc6_cm0plus.c rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/device/COMPONENT_CM0P/system_psoc6_cm0plus.c diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx7_cm4.sct b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xxa_cm4_dual.sct similarity index 83% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx7_cm4.sct rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xxa_cm4_dual.sct index 3e8e0478d9..9b638fcf4e 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx7_cm4.sct +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xxa_cm4_dual.sct @@ -3,8 +3,8 @@ ; to pass a scatter file through a C preprocessor. ;******************************************************************************* -;* \file cyb06xx7_cm4.sct -;* \version 2.70.1 +;* \file cyb06xxa_cm4_dual.sct +;* \version 2.80 ;* ;* Linker file for the ARMCC. ;* @@ -42,36 +42,46 @@ ;* limitations under the License. ;******************************************************************************/ +; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. +; More about CM0+ prebuilt images, see here: +; https://github.com/cypresssemiconductorco/psoc6cm0p +; The size of the Cortex-M0+ application flash image +#define FLASH_CM0P_SIZE 0x10000 + #if !defined(MBED_ROM_START) #define MBED_ROM_START 0x10000000 #endif ;* MBED_APP_START is being used by the bootloader build script and -;* will be calculate by the system. Without bootloader the MBED_APP_START -;* is equal to MBED_ROM_START +;* will be calculate by the system. In case if MBED_APP_START address is +;* customized by the bootloader config, the application image should not +;* include CM0p prebuilt image. ;* + #if !defined(MBED_APP_START) - #define MBED_APP_START MBED_ROM_START + #define MBED_APP_START (MBED_ROM_START + FLASH_CM0P_SIZE) #endif +; The size of the MCU boot header area at the start of FLASH +#define BOOT_HEADER_SIZE 0x00000400 + #if !defined(MBED_ROM_SIZE) - #define MBED_ROM_SIZE 0x000D0000 + #define MBED_ROM_SIZE 0x00E8000 #endif ;* MBED_APP_SIZE is being used by the bootloader build script and -;* will be calculate by the system. Without bootloader the MBED_APP_SIZE -;* is equal to MBED_ROM_SIZE +;* will be calculate by the system. ;* #if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE MBED_ROM_SIZE + #define MBED_APP_SIZE (MBED_ROM_SIZE - FLASH_CM0P_SIZE) #endif #if !defined(MBED_RAM_START) - #define MBED_RAM_START 0x08000000 + #define MBED_RAM_START 0x08001800 #endif #if !defined(MBED_RAM_SIZE) - #define MBED_RAM_SIZE 0x0002A000 + #define MBED_RAM_SIZE 0x000DE800 #endif #if !defined(MBED_BOOT_STACK_SIZE) @@ -85,6 +95,11 @@ ; Use these defines to specify the memory regions available for allocation. ; The following defines control RAM and flash memory allocation for the CM4 core. +; You can change the memory allocation by editing RAM and Flash defines. +; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. +; Using this memory region for other purposes will lead to unexpected behavior. +; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat', +; where 'xx' is the device group; for example, 'cyb06xx7_cm0plus.scat'. ; RAM #define RAM_START MBED_RAM_START #define RAM_SIZE MBED_RAM_SIZE @@ -92,9 +107,6 @@ #define FLASH_START MBED_APP_START #define FLASH_SIZE MBED_APP_SIZE -; The size of the MCU boot header area at the start of FLASH -#define BOOT_HEADER_SIZE 0x00000400 - ; The following defines describe a 32K flash region used for EEPROM emulation. ; This region can also be used as the general purpose flash. ; You can assign sections to this memory region for only one of the cores. @@ -133,8 +145,17 @@ #define EFUSE_SIZE 0x100000 +; Cortex-M0+ application flash image area +LR_IROM (MBED_ROM_START + BOOT_HEADER_SIZE) (FLASH_CM0P_SIZE - BOOT_HEADER_SIZE) +{ + .cy_m0p_image +0 FLASH_CM0P_SIZE + { + * (.cy_m0p_image) + } +} + ; Cortex-M4 application flash area -LR_IROM1 (FLASH_START + BOOT_HEADER_SIZE) (FLASH_SIZE - BOOT_HEADER_SIZE) +LR_IROM1 FLASH_START FLASH_SIZE { ER_FLASH_VECTORS +0 { @@ -173,12 +194,12 @@ LR_IROM1 (FLASH_START + BOOT_HEADER_SIZE) (FLASH_SIZE - BOOT_HEADER_SIZE) ; Stack region growing down ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE { - } - + } + ; Used for the digital signature of the secure application and the ; Bootloader SDK application. The size of the section depends on the required ; data size. - .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256 + .cy_app_signature (MBED_ROM_START + MBED_ROM_SIZE - 256) 256 { * (.cy_app_signature) } @@ -269,7 +290,7 @@ CYMETA 0x90500000 /* The following symbols used by the cymcuelftool. */ /* Flash */ #define __cy_memory_0_start 0x10000000 -#define __cy_memory_0_length 0x000D0000 +#define __cy_memory_0_length 0x00200000 #define __cy_memory_0_row_size 0x200 /* Emulated EEPROM Flash area */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_02_cm4.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_02_cm4.S similarity index 99% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_02_cm4.S rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_02_cm4.S index 114d71efb8..4d54e8bed1 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_02_cm4.S +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_02_cm4.S @@ -1,5 +1,5 @@ ;/**************************************************************************//** -; * @file startup_psoc6_02_cm4.S +; * @file startup_psoc6_02_cm4.s ; * @brief CMSIS Core Device Startup File for ; * ARMCM4 Device Series ; * @version V5.00 @@ -32,9 +32,12 @@ EXPORT __Vectors EXPORT __Vectors_End EXPORT __Vectors_Size - IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| -__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Base| + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Length| + +__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Base| + |Image$$ARM_LIB_STACK$$ZI$$Length| ; Top of Stack + DCD Reset_Handler ; Reset Handler DCD 0x0000000D ; NMI Handler located at ROM code @@ -279,7 +282,7 @@ Vectors_Copy ; Enable the FPU if used LDR R0, =Cy_SystemInitFpuEnable BLX R0 - + LDR R0, =__main BLX R0 @@ -695,6 +698,10 @@ sdhc_1_interrupt_general_IRQHandler ALIGN + +; User Initial Stack & Heap + IMPORT __use_two_region_memory + END diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xxa_cm4.ld b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xxa_cm4_dual.ld similarity index 88% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xxa_cm4.ld rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xxa_cm4_dual.ld index 6bc500fffd..873c29b451 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xxa_cm4.ld +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xxa_cm4_dual.ld @@ -1,6 +1,6 @@ /***************************************************************************//** -* \file cyb06xxa_cm4.ld -* \version 2.70 +* \file cyb06xxa_cm4_dual.ld +* \version 2.80 * * Linker file for the GNU C compiler. * @@ -19,7 +19,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -40,36 +40,46 @@ SEARCH_DIR(.) GROUP(-lgcc -lc -lnosys) ENTRY(Reset_Handler) +/* By default, the COMPONENT_CM0P_SECURE prebuilt image is used for the CM0p core. +* More about CM0+ prebuilt images, see here: +* https://github.com/cypresssemiconductorco/psoc6cm0p +*/ +/* The size of the Cortex-M0+ application image at the start of FLASH */ +FLASH_CM0P_SIZE = 0x10000; + +/* The size of the MCU boot header area at the start of FLASH */ +BOOT_HEADER_SIZE = 0x400; + #if !defined(MBED_ROM_START) #define MBED_ROM_START 0x10000000 #endif -/* MBED_APP_START is being used by the bootloader build script and -* will be calculate by the system. Without bootloader the MBED_APP_START -* is equal to MBED_ROM_START +/* MBED_APP_START is being used by the bootloader build script and +* will be calculate by the system. In case if MBED_APP_START address is +* customized by the bootloader config, the application image should not +* include CM0p prebuilt image. */ #if !defined(MBED_APP_START) - #define MBED_APP_START MBED_ROM_START + #define MBED_APP_START (MBED_ROM_START + FLASH_CM0P_SIZE) #endif #if !defined(MBED_ROM_SIZE) - #define MBED_ROM_SIZE 0x001D0000 + #define MBED_ROM_SIZE 0xE8000 #endif /* MBED_APP_SIZE is being used by the bootloader build script and -* will be calculate by the system. Without bootloader the MBED_APP_SIZE -* is equal to MBED_ROM_SIZE +* will be calculate by the system. */ #if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE MBED_ROM_SIZE + #define MBED_APP_SIZE (MBED_ROM_SIZE - FLASH_CM0P_SIZE) #endif #if !defined(MBED_RAM_START) - #define MBED_RAM_START 0x08000000 + #define MBED_RAM_START 0x08001800 #endif #if !defined(MBED_RAM_SIZE) - #define MBED_RAM_SIZE 0x000EA000 + #define MBED_RAM_SIZE 0x000DE800 #endif #if !defined(MBED_BOOT_STACK_SIZE) @@ -79,9 +89,6 @@ ENTRY(Reset_Handler) /* The size of the stack section at the end of CM4 SRAM */ STACK_SIZE = MBED_BOOT_STACK_SIZE; -/* The size of the MCU boot header area at the start of FLASH */ -BOOT_HEADER_SIZE = 0x400; - /* Force symbol to be entered in the output file as an undefined symbol. Doing * this may, for example, trigger linking of additional modules from standard * libraries. You may list several symbols for each EXTERN, and you may use @@ -96,8 +103,13 @@ EXTERN(Reset_Handler) MEMORY { /* The ram and flash regions control RAM and flash memory allocation for the CM4 core. + * You can change the memory allocation by editing the 'ram' and 'flash' regions. + * Using this memory region for other purposes will lead to unexpected behavior. + * Your changes must be aligned with the corresponding memory regions for CM0+ core in 'xx_cm0plus.ld', + * where 'xx' is the device group; for example, 'cyb06xxa_cm0plus.ld'. */ ram (rwx) : ORIGIN = MBED_RAM_START, LENGTH = MBED_RAM_SIZE + cm0p_image (rx) : ORIGIN = (MBED_ROM_START + BOOT_HEADER_SIZE), LENGTH = FLASH_CM0P_SIZE flash (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE /* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash. @@ -156,10 +168,18 @@ GROUP(libgcc.a libc.a libm.a libnosys.a) SECTIONS { - /* Cortex-M4 application flash area */ - .text ORIGIN(flash) + BOOT_HEADER_SIZE : + /* Cortex-M0+ application flash image area */ + .cy_m0p_image ORIGIN(cm0p_image) : + { + . = ALIGN(4); + __cy_m0p_code_start = . ; + KEEP(*(.cy_m0p_image)) + __cy_m0p_code_end = . ; + } > cm0p_image + + /* Cortex-M4 application flash area */ + .text ORIGIN(flash) : { - /* Cortex-M4 flash vector table */ . = ALIGN(4); __Vectors = . ; KEEP(*(.vectors)) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm4.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm4.S similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm4.S rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm4.S diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xx7_cm4.icf b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xxa_cm4_dual.icf similarity index 82% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xx7_cm4.icf rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xxa_cm4_dual.icf index 42a971cffd..c3ca5c295c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xx7_cm4.icf +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xxa_cm4_dual.icf @@ -1,6 +1,6 @@ /******************************************************************************* -* \file cyb06xx7_cm4.icf -* \version 2.70.1 +* \file cyb06xxa_cm4_dual.icf +* \version 2.80 * * Linker file for the IAR compiler. * @@ -41,52 +41,77 @@ /*-Specials-*/ define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/* By default, the COMPONENT_CM0P_SECURE prebuilt image is used for the CM0p core. + * More about CM0+ prebuilt images, see here: + * https://github.com/cypresssemiconductorco/psoc6cm0p + */ +/* The size of the Cortex-M0+ application image */ +define symbol FLASH_CM0P_SIZE = 0x10000; + +/* The size of the MCU boot header area at the start of FLASH */ +define symbol BOOT_HEADER_SIZE = 0x00000400; + if (!isdefinedsymbol(MBED_ROM_START)) { define symbol MBED_ROM_START = 0x10000000; } -/* MBED_APP_START is being used by the bootloader build script and - * will be calculate by the system. Without bootloader the MBED_APP_START - * is equal to MBED_ROM_START +/* MBED_APP_START is being used by the bootloader build script and + * will be calculate by the system. In case if MBED_APP_START address is + * customized by the bootloader config, the application image should not + * include CM0p prebuilt image. */ if (!isdefinedsymbol(MBED_APP_START)) { - define symbol MBED_APP_START = MBED_ROM_START; + define symbol MBED_APP_START = (MBED_ROM_START + FLASH_CM0P_SIZE); } if (!isdefinedsymbol(MBED_ROM_SIZE)) { - define symbol MBED_ROM_SIZE = 0x000D0000; + define symbol MBED_ROM_SIZE = 0x00E8000; } /* MBED_APP_SIZE is being used by the bootloader build script and - * will be calculate by the system. Without bootloader the MBED_APP_SIZE - * is equal to MBED_ROM_SIZE + * will be calculate by the system. */ if (!isdefinedsymbol(MBED_APP_SIZE)) { - define symbol MBED_APP_SIZE = MBED_ROM_SIZE; + define symbol MBED_APP_SIZE = (MBED_ROM_SIZE - FLASH_CM0P_SIZE); } if (!isdefinedsymbol(MBED_RAM_START)) { - define symbol MBED_RAM_START = 0x08000000; + define symbol MBED_RAM_START = 0x08001800; } if (!isdefinedsymbol(MBED_RAM_SIZE)) { - define symbol MBED_RAM_SIZE = 0x0002A000; + define symbol MBED_RAM_SIZE = 0x000DE800; } if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) { - define symbol MBED_BOOT_STACK_SIZE = 0x400; + + if (!isdefinedsymbol(__STACK_SIZE)) { + define symbol MBED_BOOT_STACK_SIZE = 0x0400; + } else { + define symbol MBED_BOOT_STACK_SIZE = __STACK_SIZE; + } } +define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE; + /* The symbols below define the location and size of blocks of memory in the target. * Use these symbols to specify the memory regions available for allocation. */ /* The following symbols control RAM and flash memory allocation for the CM4 core. + * You can change the memory allocation by editing RAM and Flash symbols. + * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. + * Using this memory region for other purposes will lead to unexpected behavior. + * Your changes must be aligned with the corresponding symbols for CM0+ core in 'xx_cm0plus.icf', + * where 'xx' is the device group; for example, 'cyb06xx7_cm0plus.icf'. */ /* RAM */ define symbol __ICFEDIT_region_IRAM1_start__ = MBED_RAM_START; define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE - 1); /* Flash */ +define symbol __ICFEDIT_region_IROM0_start__ = MBED_ROM_START + BOOT_HEADER_SIZE; +define symbol __ICFEDIT_region_IROM0_end__ = (MBED_ROM_START + FLASH_CM0P_SIZE - 1); + define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START; define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE - 1); @@ -143,12 +168,6 @@ define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; /*-Sizes-*/ -if (!isdefinedsymbol(__STACK_SIZE)) { - define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE; -} else { - define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE; -} - /* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */ if (!isdefinedsymbol(__HEAP_SIZE)) { define symbol __ICFEDIT_size_heap__ = 0x0400; @@ -157,11 +176,8 @@ if (!isdefinedsymbol(__HEAP_SIZE)) { } /**** End of ICF editor section. ###ICF###*/ -/* The size of the MCU boot header area at the start of FLASH */ -define symbol BOOT_HEADER_SIZE = 0x400; - - define memory mem with size = 4G; +define region IROM0_region = mem:[from __ICFEDIT_region_IROM0_start__ to __ICFEDIT_region_IROM0_end__]; define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]; define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__]; @@ -182,6 +198,7 @@ define block RAM with fixed order {block RAM_DATA, block RAM_OTHER, block RAM_NO define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { }; +define block CM0P_RO with size = (FLASH_CM0P_SIZE - BOOT_HEADER_SIZE) { readonly section .cy_m0p_image }; define block RO {first section .intvec, readonly}; /*-Initializations-*/ @@ -190,8 +207,11 @@ do not initialize { section .noinit, section .intvec_ram }; /*-Placement-*/ +/* Flash - Cortex-M0+ application image */ +place at start of IROM0_region { block CM0P_RO }; + /* Flash - Cortex-M4 application */ -place at address (__ICFEDIT_region_IROM1_start__ + BOOT_HEADER_SIZE) { block RO }; +place at start of IROM1_region { block RO }; /* Used for the digital signature of the secure application and the Bootloader SDK application. */ ".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature }; @@ -230,7 +250,8 @@ place at end of IRAM1_region { block CSTACK }; ".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; -keep { section .cy_app_signature, +keep { section .cy_m0p_image, + section .cy_app_signature, section .cy_em_eeprom, section .cy_sflash_user_data, section .cy_sflash_nar, @@ -246,7 +267,7 @@ keep { section .cy_app_signature, /* The following symbols used by the cymcuelftool. */ /* Flash */ define exported symbol __cy_memory_0_start = 0x10000000; -define exported symbol __cy_memory_0_length = 0x000D0000; +define exported symbol __cy_memory_0_length = 0x00200000; define exported symbol __cy_memory_0_row_size = 0x200; /* Emulated EEPROM Flash area */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_02_cm4.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_02_cm4.S similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_02_cm4.S rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_02_cm4.S diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/device/COMPONENT_CM4/hex/psoc6_02_cm0p_secure.hex b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/device/COMPONENT_CM4/hex/psoc6_02_cm0p_secure.hex new file mode 100644 index 0000000000..b4ddc1683e --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/device/COMPONENT_CM4/hex/psoc6_02_cm0p_secure.hex @@ -0,0 +1,1800 @@ +:020000041000EA +:1004000000C00E08EB0400100D0000004D050010A8 +:1004100000000000000000000000000000000000DC +:10042000000000000000000000000000490500106E +:100430000000000000000000490500104905001000 +:100440004905001049050010490500104905001034 +:100450004905001049050010490500104905001024 +:100460004905001049050010490500104905001014 +:100470004905001049050010490500104905001004 +:1004800010B5064C2378002B07D1054B002B02D06A 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+:1073E000604700BFE304001001B40248844601BCBA +:1073F000604700BFD51E001001B40248844601BC9E +:10740000604700BF0521001001B40248844601BC5A +:10741000604700BF9120001001B40248844601BCBF +:08742000604700BFDB0400100F +:04000005100004EBF8 +:00000001FF diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM4/system_psoc6_cm4.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/device/COMPONENT_CM4/system_psoc6_cm4.c similarity index 98% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM4/system_psoc6_cm4.c rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/device/COMPONENT_CM4/system_psoc6_cm4.c index 7e634e2f31..c58b712a10 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM4/system_psoc6_cm4.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/device/COMPONENT_CM4/system_psoc6_cm4.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file system_psoc6_cm4.c -* \version 2.70.1 +* \version 2.80 * * The device system-source file. * @@ -40,6 +40,10 @@ #endif /* defined(CY_DEVICE_PSOC6ABLE2) */ #endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */ +#if defined(CY_DEVICE_SECURE) + #include "cy_pra.h" +#endif /* defined(CY_DEVICE_SECURE) */ + /******************************************************************************* * SystemCoreClockUpdate() @@ -160,7 +164,7 @@ void SystemInit(void) #ifdef __CM0P_PRESENT #if (__CM0P_PRESENT == 0) /* Configure data register (as CM0p in deep sleep state) of IPC structure #7, reserved for the Deep-Sleep operations. */ - REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = (CY_STARTUP_CM0_DP_STATE << + REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = (CY_STARTUP_CM0_DP_STATE << CY_STARTUP_IPC7_DP_OFFSET); /* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering. */ @@ -233,6 +237,11 @@ void SystemInit(void) #endif /* defined(CY_DEVICE_PSOC6ABLE2) */ #endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */ + +#if defined(CY_DEVICE_SECURE) + /* Initialize Protected Register Access driver */ + Cy_PRA_Init(); +#endif /* defined(CY_DEVICE_SECURE) */ } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/system_psoc6.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/device/system_psoc6.h similarity index 98% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/system_psoc6.h rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/device/system_psoc6.h index 0ad244b658..bd27b72ad6 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/system_psoc6.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/device/system_psoc6.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file system_psoc6.h -* \version 2.70.1 +* \version 2.80 * * \brief Device system header file. * @@ -321,6 +321,16 @@ * Reason for Change * * +* 2.80 +* Updated linker scripts for PSoC 64 Secure MCU devices. +* Updated FLASH and SRAM memory area definitions in cyb0xxx linker script templates +* in accordance with the PSoC 64 Secure Boot SDK policies. +* +* +* Added \ref Cy_PRA_Init() function call to \ref SystemInit() API for CM0+ core of PSoC 64 Secure MCU. +* Updated PSoC 64 Secure MCU startup sequence to initialize the Protected Register Access driver. +* +* * 2.70.1 * Updated documentation for the better description of the existing startup implementation. * User experience enhancement. diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp deleted file mode 100755 index 216bafabba..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp +++ /dev/null @@ -1,26 +0,0 @@ -/******************************************************************************* -* File Name: cycfg.timestamp -* -* Description: -* Sentinel file for determining if generated source is up to date. -* This file was automatically generated and should not be modified. -* Device Configurator: 2.0.0.1483 -* Device Support Library (libs/psoc6pdl): 1.4.1.2240 -* -******************************************************************************** -* Copyright 2017-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -********************************************************************************/ - diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c deleted file mode 100644 index 41fe86f553..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c +++ /dev/null @@ -1,47 +0,0 @@ -/******************************************************************************* -* File Name: cycfg_clocks.c -* -* Description: -* Clock configuration -* This file was automatically generated and should not be modified. -* Device Configurator: 2.0.0.1483 -* Device Support Library (libs/psoc6pdl): 1.4.1.2240 -* -******************************************************************************** -* Copyright 2017-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -********************************************************************************/ - -#include "cycfg_clocks.h" - -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj = - { - .type = CYHAL_RSC_CLOCK, - .block_num = CYBSP_CSD_CLK_DIV_HW, - .channel_num = CYBSP_CSD_CLK_DIV_NUM, - }; -#endif //defined (CY_USING_HAL) - - -void init_cycfg_clocks(void) -{ - Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 3U); - Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 3U, 255U); - Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 3U); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_CSD_CLK_DIV_obj); -#endif //defined (CY_USING_HAL) -} diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h deleted file mode 100644 index 1bbe7b6308..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h +++ /dev/null @@ -1,55 +0,0 @@ -/******************************************************************************* -* File Name: cycfg_clocks.h -* -* Description: -* Clock configuration -* This file was automatically generated and should not be modified. -* Device Configurator: 2.0.0.1483 -* Device Support Library (libs/psoc6pdl): 1.4.1.2240 -* -******************************************************************************** -* Copyright 2017-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -********************************************************************************/ - -#if !defined(CYCFG_CLOCKS_H) -#define CYCFG_CLOCKS_H - -#include "cycfg_notices.h" -#include "cy_sysclk.h" -#if defined (CY_USING_HAL) - #include "cyhal_hwmgr.h" -#endif //defined (CY_USING_HAL) - -#if defined(__cplusplus) -extern "C" { -#endif - -#define CYBSP_CSD_CLK_DIV_ENABLED 1U -#define CYBSP_CSD_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT -#define CYBSP_CSD_CLK_DIV_NUM 3U - -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj; -#endif //defined (CY_USING_HAL) - -void init_cycfg_clocks(void); - -#if defined(__cplusplus) -} -#endif - - -#endif /* CYCFG_CLOCKS_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h deleted file mode 100644 index 0d31cfa23b..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h +++ /dev/null @@ -1,32 +0,0 @@ -/******************************************************************************* -* File Name: cycfg_notices.h -* -* Description: -* Contains warnings and errors that occurred while generating code for the -* design. -* This file was automatically generated and should not be modified. -* Device Configurator: 2.0.0.1483 -* Device Support Library (libs/psoc6pdl): 1.4.1.2240 -* -******************************************************************************** -* Copyright 2017-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -********************************************************************************/ - -#if !defined(CYCFG_NOTICES_H) -#define CYCFG_NOTICES_H - - -#endif /* CYCFG_NOTICES_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h deleted file mode 100644 index 41388b9638..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h +++ /dev/null @@ -1,84 +0,0 @@ -/******************************************************************************* -* File Name: cycfg_peripherals.h -* -* Description: -* Peripheral Hardware Block configuration -* This file was automatically generated and should not be modified. -* Device Configurator: 2.0.0.1483 -* Device Support Library (libs/psoc6pdl): 1.4.1.2240 -* -******************************************************************************** -* Copyright 2017-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -********************************************************************************/ - -#if !defined(CYCFG_PERIPHERALS_H) -#define CYCFG_PERIPHERALS_H - -#include "cycfg_notices.h" -#include "cy_sysclk.h" -#include "cy_csd.h" - -#if defined(__cplusplus) -extern "C" { -#endif - -#define CYBSP_CSD_ENABLED 1U -#define CY_CAPSENSE_CORE 4u -#define CY_CAPSENSE_CPU_CLK 100000000u -#define CY_CAPSENSE_PERI_CLK 100000000u -#define CY_CAPSENSE_VDDA_MV 3300u -#define CY_CAPSENSE_PERI_DIV_TYPE CY_SYSCLK_DIV_8_BIT -#define CY_CAPSENSE_PERI_DIV_INDEX 3u -#define Cmod_PORT GPIO_PRT7 -#define CintA_PORT GPIO_PRT7 -#define CintB_PORT GPIO_PRT7 -#define Button0_Rx0_PORT GPIO_PRT8 -#define Button0_Tx_PORT GPIO_PRT1 -#define Button1_Rx0_PORT GPIO_PRT8 -#define Button1_Tx_PORT GPIO_PRT1 -#define LinearSlider0_Sns0_PORT GPIO_PRT8 -#define LinearSlider0_Sns1_PORT GPIO_PRT8 -#define LinearSlider0_Sns2_PORT GPIO_PRT8 -#define LinearSlider0_Sns3_PORT GPIO_PRT8 -#define LinearSlider0_Sns4_PORT GPIO_PRT8 -#define Cmod_PIN 7u -#define CintA_PIN 1u -#define CintB_PIN 2u -#define Button0_Rx0_PIN 1u -#define Button0_Tx_PIN 0u -#define Button1_Rx0_PIN 2u -#define Button1_Tx_PIN 0u -#define LinearSlider0_Sns0_PIN 3u -#define LinearSlider0_Sns1_PIN 4u -#define LinearSlider0_Sns2_PIN 5u -#define LinearSlider0_Sns3_PIN 6u -#define LinearSlider0_Sns4_PIN 7u -#define Cmod_PORT_NUM 7u -#define CintA_PORT_NUM 7u -#define CintB_PORT_NUM 7u -#define CYBSP_CSD_HW CSD0 -#define CYBSP_CSD_IRQ csd_interrupt_IRQn - -extern cy_stc_csd_context_t cy_csd_0_context; - -void init_cycfg_peripherals(void); - -#if defined(__cplusplus) -} -#endif - - -#endif /* CYCFG_PERIPHERALS_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h deleted file mode 100644 index e23fab508d..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h +++ /dev/null @@ -1,59 +0,0 @@ -/******************************************************************************* -* File Name: cycfg_routing.h -* -* Description: -* Establishes all necessary connections between hardware elements. -* This file was automatically generated and should not be modified. -* Device Configurator: 2.0.0.1483 -* Device Support Library (libs/psoc6pdl): 1.4.1.2240 -* -******************************************************************************** -* Copyright 2017-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -********************************************************************************/ - -#if !defined(CYCFG_ROUTING_H) -#define CYCFG_ROUTING_H - -#if defined(__cplusplus) -extern "C" { -#endif - -#include "cycfg_notices.h" -void init_cycfg_routing(void); -#define init_cycfg_connectivity() init_cycfg_routing() -#define ioss_0_port_0_pin_0_ANALOG P0_0_SRSS_WCO_IN -#define ioss_0_port_0_pin_1_ANALOG P0_1_SRSS_WCO_OUT -#define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_AMUXB -#define ioss_0_port_6_pin_4_HSIOM P6_4_CPUSS_SWJ_SWO_TDO -#define ioss_0_port_6_pin_6_HSIOM P6_6_CPUSS_SWJ_SWDIO_TMS -#define ioss_0_port_6_pin_7_HSIOM P6_7_CPUSS_SWJ_SWCLK_TCLK -#define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_AMUXB -#define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_AMUXA -#define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_AMUXB -#define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_AMUXB -#define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_AMUXB -#define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_AMUXB -#define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_AMUXB -#define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_AMUXB -#define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_AMUXB -#define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_AMUXB - -#if defined(__cplusplus) -} -#endif - - -#endif /* CYCFG_ROUTING_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c deleted file mode 100644 index 1aed94281c..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c +++ /dev/null @@ -1,598 +0,0 @@ -/******************************************************************************* -* File Name: cycfg_system.c -* -* Description: -* System configuration -* This file was automatically generated and should not be modified. -* Device Configurator: 2.0.0.1483 -* Device Support Library (libs/psoc6pdl): 1.4.1.2240 -* -******************************************************************************** -* Copyright 2017-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -********************************************************************************/ - -#include "cycfg_system.h" - -#define CY_CFG_SYSCLK_ECO_ERROR 1 -#define CY_CFG_SYSCLK_ALTHF_ERROR 2 -#define CY_CFG_SYSCLK_PLL_ERROR 3 -#define CY_CFG_SYSCLK_FLL_ERROR 4 -#define CY_CFG_SYSCLK_WCO_ERROR 5 -#define CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED 1 -#define CY_CFG_SYSCLK_CLKBAK_ENABLED 1 -#define CY_CFG_SYSCLK_CLKFAST_ENABLED 1 -#define CY_CFG_SYSCLK_FLL_ENABLED 1 -#define CY_CFG_SYSCLK_CLKHF0_ENABLED 1 -#define CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ 100UL -#define CY_CFG_SYSCLK_CLKHF0_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0 -#define CY_CFG_SYSCLK_CLKHF1_ENABLED 1 -#define CY_CFG_SYSCLK_CLKHF1_FREQ_MHZ 48UL -#define CY_CFG_SYSCLK_CLKHF1_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH1 -#define CY_CFG_SYSCLK_CLKHF2_ENABLED 1 -#define CY_CFG_SYSCLK_CLKHF2_FREQ_MHZ 50UL -#define CY_CFG_SYSCLK_CLKHF2_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0 -#define CY_CFG_SYSCLK_CLKHF3_ENABLED 1 -#define CY_CFG_SYSCLK_CLKHF3_FREQ_MHZ 48UL -#define CY_CFG_SYSCLK_CLKHF3_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH1 -#define CY_CFG_SYSCLK_CLKHF4_ENABLED 1 -#define CY_CFG_SYSCLK_CLKHF4_FREQ_MHZ 100UL -#define CY_CFG_SYSCLK_CLKHF4_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0 -#define CY_CFG_SYSCLK_ILO_ENABLED 1 -#define CY_CFG_SYSCLK_IMO_ENABLED 1 -#define CY_CFG_SYSCLK_CLKLF_ENABLED 1 -#define CY_CFG_SYSCLK_CLKPATH0_ENABLED 1 -#define CY_CFG_SYSCLK_CLKPATH0_SOURCE CY_SYSCLK_CLKPATH_IN_IMO -#define CY_CFG_SYSCLK_CLKPATH1_ENABLED 1 -#define CY_CFG_SYSCLK_CLKPATH1_SOURCE CY_SYSCLK_CLKPATH_IN_IMO -#define CY_CFG_SYSCLK_CLKPATH2_ENABLED 1 -#define CY_CFG_SYSCLK_CLKPATH2_SOURCE CY_SYSCLK_CLKPATH_IN_IMO -#define CY_CFG_SYSCLK_CLKPATH3_ENABLED 1 -#define CY_CFG_SYSCLK_CLKPATH3_SOURCE CY_SYSCLK_CLKPATH_IN_IMO -#define CY_CFG_SYSCLK_CLKPATH4_ENABLED 1 -#define CY_CFG_SYSCLK_CLKPATH4_SOURCE CY_SYSCLK_CLKPATH_IN_IMO -#define CY_CFG_SYSCLK_CLKPERI_ENABLED 1 -#define CY_CFG_SYSCLK_PLL0_ENABLED 1 -#define CY_CFG_SYSCLK_CLKSLOW_ENABLED 1 -#define CY_CFG_SYSCLK_CLKTIMER_ENABLED 1 -#define CY_CFG_SYSCLK_WCO_ENABLED 1 -#define CY_CFG_PWR_ENABLED 1 -#define CY_CFG_PWR_INIT 1 -#define CY_CFG_PWR_USING_PMIC 0 -#define CY_CFG_PWR_VBACKUP_USING_VDDD 1 -#define CY_CFG_PWR_LDO_VOLTAGE CY_SYSPM_LDO_VOLTAGE_LP -#define CY_CFG_PWR_USING_ULP 0 - -static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig = -{ - .fllMult = 500U, - .refDiv = 20U, - .ccoRange = CY_SYSCLK_FLL_CCO_RANGE4, - .enableOutputDiv = true, - .lockTolerance = 10U, - .igain = 9U, - .pgain = 5U, - .settlingCount = 8U, - .outputMode = CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT, - .cco_Freq = 355U, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj = - { - .type = CYHAL_RSC_CLKPATH, - .block_num = 0U, - .channel_num = 0U, - }; -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj = - { - .type = CYHAL_RSC_CLKPATH, - .block_num = 1U, - .channel_num = 0U, - }; -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj = - { - .type = CYHAL_RSC_CLKPATH, - .block_num = 2U, - .channel_num = 0U, - }; -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t srss_0_clock_0_pathmux_3_obj = - { - .type = CYHAL_RSC_CLKPATH, - .block_num = 3U, - .channel_num = 0U, - }; -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t srss_0_clock_0_pathmux_4_obj = - { - .type = CYHAL_RSC_CLKPATH, - .block_num = 4U, - .channel_num = 0U, - }; -#endif //defined (CY_USING_HAL) -static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_0_pllConfig = -{ - .feedbackDiv = 30, - .referenceDiv = 1, - .outputDiv = 5, - .lfMode = false, - .outputMode = CY_SYSCLK_FLLPLL_OUTPUT_AUTO, -}; - -__WEAK void cycfg_ClockStartupError(uint32_t error) -{ - (void)error; /* Suppress the compiler warning */ - while(1); -} -__STATIC_INLINE void Cy_SysClk_ClkAltSysTickInit() -{ - Cy_SysTick_SetClockSource(CY_SYSTICK_CLOCK_SOURCE_CLK_LF); -} -__STATIC_INLINE void Cy_SysClk_ClkBakInit() -{ - Cy_SysClk_ClkBakSetSource(CY_SYSCLK_BAK_IN_WCO); -} -__STATIC_INLINE void Cy_SysClk_ClkFastInit() -{ - Cy_SysClk_ClkFastSetDivider(0U); -} -__STATIC_INLINE void Cy_SysClk_FllInit() -{ - if (CY_SYSCLK_SUCCESS != Cy_SysClk_FllManualConfigure(&srss_0_clock_0_fll_0_fllConfig)) - { - cycfg_ClockStartupError(CY_CFG_SYSCLK_FLL_ERROR); - } - if (CY_SYSCLK_SUCCESS != Cy_SysClk_FllEnable(200000UL)) - { - cycfg_ClockStartupError(CY_CFG_SYSCLK_FLL_ERROR); - } -} -__STATIC_INLINE void Cy_SysClk_ClkHf0Init() -{ - Cy_SysClk_ClkHfSetSource(0U, CY_CFG_SYSCLK_CLKHF0_CLKPATH); - Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE); -} -__STATIC_INLINE void Cy_SysClk_ClkHf1Init() -{ - Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF1, CY_CFG_SYSCLK_CLKHF1_CLKPATH); - Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF1, CY_SYSCLK_CLKHF_NO_DIVIDE); - Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF1); -} -__STATIC_INLINE void Cy_SysClk_ClkHf2Init() -{ - Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF2, CY_CFG_SYSCLK_CLKHF2_CLKPATH); - Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF2, CY_SYSCLK_CLKHF_DIVIDE_BY_2); - Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF2); -} -__STATIC_INLINE void Cy_SysClk_ClkHf3Init() -{ - Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF3, CY_CFG_SYSCLK_CLKHF3_CLKPATH); - Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF3, CY_SYSCLK_CLKHF_NO_DIVIDE); - Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF3); -} -__STATIC_INLINE void Cy_SysClk_ClkHf4Init() -{ - Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF4, CY_CFG_SYSCLK_CLKHF4_CLKPATH); - Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF4, CY_SYSCLK_CLKHF_NO_DIVIDE); - Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF4); -} -__STATIC_INLINE void Cy_SysClk_IloInit() -{ - /* The WDT is unlocked in the default startup code */ - Cy_SysClk_IloEnable(); - Cy_SysClk_IloHibernateOn(true); -} -__STATIC_INLINE void Cy_SysClk_ClkLfInit() -{ - /* The WDT is unlocked in the default startup code */ - Cy_SysClk_ClkLfSetSource(CY_SYSCLK_CLKLF_IN_WCO); -} -__STATIC_INLINE void Cy_SysClk_ClkPath0Init() -{ - Cy_SysClk_ClkPathSetSource(0U, CY_CFG_SYSCLK_CLKPATH0_SOURCE); -} -__STATIC_INLINE void Cy_SysClk_ClkPath1Init() -{ - Cy_SysClk_ClkPathSetSource(1U, CY_CFG_SYSCLK_CLKPATH1_SOURCE); -} -__STATIC_INLINE void Cy_SysClk_ClkPath2Init() -{ - Cy_SysClk_ClkPathSetSource(2U, CY_CFG_SYSCLK_CLKPATH2_SOURCE); -} -__STATIC_INLINE void Cy_SysClk_ClkPath3Init() -{ - Cy_SysClk_ClkPathSetSource(3U, CY_CFG_SYSCLK_CLKPATH3_SOURCE); -} -__STATIC_INLINE void Cy_SysClk_ClkPath4Init() -{ - Cy_SysClk_ClkPathSetSource(4U, CY_CFG_SYSCLK_CLKPATH4_SOURCE); -} -__STATIC_INLINE void Cy_SysClk_ClkPeriInit() -{ - Cy_SysClk_ClkPeriSetDivider(0U); -} -__STATIC_INLINE void Cy_SysClk_Pll0Init() -{ - if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllManualConfigure(1U, &srss_0_clock_0_pll_0_pllConfig)) - { - cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR); - } - if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllEnable(1U, 10000u)) - { - cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR); - } -} -__STATIC_INLINE void Cy_SysClk_ClkSlowInit() -{ - Cy_SysClk_ClkSlowSetDivider(0U); -} -__STATIC_INLINE void Cy_SysClk_ClkTimerInit() -{ - Cy_SysClk_ClkTimerDisable(); - Cy_SysClk_ClkTimerSetSource(CY_SYSCLK_CLKTIMER_IN_IMO); - Cy_SysClk_ClkTimerSetDivider(0U); - Cy_SysClk_ClkTimerEnable(); -} -__STATIC_INLINE void Cy_SysClk_WcoInit() -{ - (void)Cy_GPIO_Pin_FastInit(GPIO_PRT0, 0U, 0x00U, 0x00U, HSIOM_SEL_GPIO); - (void)Cy_GPIO_Pin_FastInit(GPIO_PRT0, 1U, 0x00U, 0x00U, HSIOM_SEL_GPIO); - if (CY_SYSCLK_SUCCESS != Cy_SysClk_WcoEnable(1000000UL)) - { - cycfg_ClockStartupError(CY_CFG_SYSCLK_WCO_ERROR); - } -} -__STATIC_INLINE void init_cycfg_power(void) -{ - /* Reset the Backup domain on POR, XRES, BOD only if Backup domain is supplied by VDDD */ - #if (CY_CFG_PWR_VBACKUP_USING_VDDD) - #ifdef CY_CFG_SYSCLK_ILO_ENABLED - if (0u == Cy_SysLib_GetResetReason() /* POR, XRES, or BOD */) - { - Cy_SysLib_ResetBackupDomain(); - Cy_SysClk_IloDisable(); - Cy_SysClk_IloInit(); - } - #endif /* CY_CFG_SYSCLK_ILO_ENABLED */ - #endif /* CY_CFG_PWR_VBACKUP_USING_VDDD */ - - /* Configure core regulator */ - #if CY_CFG_PWR_USING_LDO - Cy_SysPm_LdoSetVoltage(CY_SYSPM_LDO_VOLTAGE_LP); - Cy_SysPm_LdoSetMode(CY_SYSPM_LDO_MODE_NORMAL); - #else - Cy_SysPm_BuckEnable(CY_SYSPM_BUCK_OUT1_VOLTAGE_LP); - #endif /* CY_CFG_PWR_USING_LDO */ - /* Configure PMIC */ - Cy_SysPm_UnlockPmic(); - #if CY_CFG_PWR_USING_PMIC - Cy_SysPm_PmicEnableOutput(); - #else - Cy_SysPm_PmicDisableOutput(); - #endif /* CY_CFG_PWR_USING_PMIC */ -} - - -void init_cycfg_system(void) -{ - /* Set worst case memory wait states (! ultra low power, 150 MHz), will update at the end */ - Cy_SysLib_SetWaitStates(false, 150UL); - #ifdef CY_CFG_PWR_ENABLED - #ifdef CY_CFG_PWR_INIT - init_cycfg_power(); - #else - #warning Power system will not be configured. Update power personality to v1.20 or later. - #endif /* CY_CFG_PWR_INIT */ - #endif /* CY_CFG_PWR_ENABLED */ - - /* Reset the core clock path to default and disable all the FLLs/PLLs */ - Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE); - Cy_SysClk_ClkFastSetDivider(0U); - Cy_SysClk_ClkPeriSetDivider(1U); - Cy_SysClk_ClkSlowSetDivider(0U); - for (uint32_t pll = CY_SRSS_NUM_PLL; pll > 0UL; --pll) /* PLL 1 is the first PLL. 0 is invalid. */ - { - (void)Cy_SysClk_PllDisable(pll); - } - Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH1, CY_SYSCLK_CLKPATH_IN_IMO); - - if ((CY_SYSCLK_CLKHF_IN_CLKPATH0 == Cy_SysClk_ClkHfGetSource(0UL)) && - (CY_SYSCLK_CLKPATH_IN_WCO == Cy_SysClk_ClkPathGetSource(CY_SYSCLK_CLKHF_IN_CLKPATH0))) - { - Cy_SysClk_ClkHfSetSource(0U, CY_SYSCLK_CLKHF_IN_CLKPATH1); - } - - Cy_SysClk_FllDisable(); - Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH0, CY_SYSCLK_CLKPATH_IN_IMO); - Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH0); - #ifdef CY_IP_MXBLESS - (void)Cy_BLE_EcoReset(); - #endif - - - /* Enable all source clocks */ - #ifdef CY_CFG_SYSCLK_PILO_ENABLED - Cy_SysClk_PiloInit(); - #endif - - #ifdef CY_CFG_SYSCLK_WCO_ENABLED - Cy_SysClk_WcoInit(); - #endif - - #ifdef CY_CFG_SYSCLK_CLKLF_ENABLED - Cy_SysClk_ClkLfInit(); - #endif - - #ifdef CY_CFG_SYSCLK_ALTHF_ENABLED - Cy_SysClk_AltHfInit(); - #endif - - #ifdef CY_CFG_SYSCLK_ECO_ENABLED - Cy_SysClk_EcoInit(); - #endif - - #ifdef CY_CFG_SYSCLK_EXTCLK_ENABLED - Cy_SysClk_ExtClkInit(); - #endif - - /* Configure CPU clock dividers */ - #ifdef CY_CFG_SYSCLK_CLKFAST_ENABLED - Cy_SysClk_ClkFastInit(); - #endif - - #ifdef CY_CFG_SYSCLK_CLKPERI_ENABLED - Cy_SysClk_ClkPeriInit(); - #endif - - #ifdef CY_CFG_SYSCLK_CLKSLOW_ENABLED - Cy_SysClk_ClkSlowInit(); - #endif - - #if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE == CY_SYSCLK_CLKPATH_IN_WCO) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH == CY_SYSCLK_CLKHF_IN_CLKPATH0)) - /* Configure HFCLK0 to temporarily run from IMO to initialize other clocks */ - Cy_SysClk_ClkPathSetSource(1UL, CY_SYSCLK_CLKPATH_IN_IMO); - Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH1); - #else - #ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED - Cy_SysClk_ClkPath1Init(); - #endif - #endif - - /* Configure Path Clocks */ - #ifdef CY_CFG_SYSCLK_CLKPATH0_ENABLED - Cy_SysClk_ClkPath0Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKPATH2_ENABLED - Cy_SysClk_ClkPath2Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKPATH3_ENABLED - Cy_SysClk_ClkPath3Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKPATH4_ENABLED - Cy_SysClk_ClkPath4Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKPATH5_ENABLED - Cy_SysClk_ClkPath5Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKPATH6_ENABLED - Cy_SysClk_ClkPath6Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKPATH7_ENABLED - Cy_SysClk_ClkPath7Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKPATH8_ENABLED - Cy_SysClk_ClkPath8Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKPATH9_ENABLED - Cy_SysClk_ClkPath9Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKPATH10_ENABLED - Cy_SysClk_ClkPath10Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKPATH11_ENABLED - Cy_SysClk_ClkPath11Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKPATH12_ENABLED - Cy_SysClk_ClkPath12Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKPATH13_ENABLED - Cy_SysClk_ClkPath13Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKPATH14_ENABLED - Cy_SysClk_ClkPath14Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKPATH15_ENABLED - Cy_SysClk_ClkPath15Init(); - #endif - - /* Configure and enable FLL */ - #ifdef CY_CFG_SYSCLK_FLL_ENABLED - Cy_SysClk_FllInit(); - #endif - - Cy_SysClk_ClkHf0Init(); - - #if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE == CY_SYSCLK_CLKPATH_IN_WCO) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH == CY_SYSCLK_CLKHF_IN_CLKPATH0)) - #ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED - /* Apply the ClkPath1 user setting */ - Cy_SysClk_ClkPath1Init(); - #endif - #endif - - /* Configure and enable PLLs */ - #ifdef CY_CFG_SYSCLK_PLL0_ENABLED - Cy_SysClk_Pll0Init(); - #endif - #ifdef CY_CFG_SYSCLK_PLL1_ENABLED - Cy_SysClk_Pll1Init(); - #endif - #ifdef CY_CFG_SYSCLK_PLL2_ENABLED - Cy_SysClk_Pll2Init(); - #endif - #ifdef CY_CFG_SYSCLK_PLL3_ENABLED - Cy_SysClk_Pll3Init(); - #endif - #ifdef CY_CFG_SYSCLK_PLL4_ENABLED - Cy_SysClk_Pll4Init(); - #endif - #ifdef CY_CFG_SYSCLK_PLL5_ENABLED - Cy_SysClk_Pll5Init(); - #endif - #ifdef CY_CFG_SYSCLK_PLL6_ENABLED - Cy_SysClk_Pll6Init(); - #endif - #ifdef CY_CFG_SYSCLK_PLL7_ENABLED - Cy_SysClk_Pll7Init(); - #endif - #ifdef CY_CFG_SYSCLK_PLL8_ENABLED - Cy_SysClk_Pll8Init(); - #endif - #ifdef CY_CFG_SYSCLK_PLL9_ENABLED - Cy_SysClk_Pll9Init(); - #endif - #ifdef CY_CFG_SYSCLK_PLL10_ENABLED - Cy_SysClk_Pll10Init(); - #endif - #ifdef CY_CFG_SYSCLK_PLL11_ENABLED - Cy_SysClk_Pll11Init(); - #endif - #ifdef CY_CFG_SYSCLK_PLL12_ENABLED - Cy_SysClk_Pll12Init(); - #endif - #ifdef CY_CFG_SYSCLK_PLL13_ENABLED - Cy_SysClk_Pll13Init(); - #endif - #ifdef CY_CFG_SYSCLK_PLL14_ENABLED - Cy_SysClk_Pll14Init(); - #endif - - /* Configure HF clocks */ - #ifdef CY_CFG_SYSCLK_CLKHF1_ENABLED - Cy_SysClk_ClkHf1Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKHF2_ENABLED - Cy_SysClk_ClkHf2Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKHF3_ENABLED - Cy_SysClk_ClkHf3Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKHF4_ENABLED - Cy_SysClk_ClkHf4Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKHF5_ENABLED - Cy_SysClk_ClkHf5Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKHF6_ENABLED - Cy_SysClk_ClkHf6Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKHF7_ENABLED - Cy_SysClk_ClkHf7Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKHF8_ENABLED - Cy_SysClk_ClkHf8Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKHF9_ENABLED - Cy_SysClk_ClkHf9Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKHF10_ENABLED - Cy_SysClk_ClkHf10Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKHF11_ENABLED - Cy_SysClk_ClkHf11Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKHF12_ENABLED - Cy_SysClk_ClkHf12Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKHF13_ENABLED - Cy_SysClk_ClkHf13Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKHF14_ENABLED - Cy_SysClk_ClkHf14Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKHF15_ENABLED - Cy_SysClk_ClkHf15Init(); - #endif - - /* Configure miscellaneous clocks */ - #ifdef CY_CFG_SYSCLK_CLKTIMER_ENABLED - Cy_SysClk_ClkTimerInit(); - #endif - - #ifdef CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED - Cy_SysClk_ClkAltSysTickInit(); - #endif - - #ifdef CY_CFG_SYSCLK_CLKPUMP_ENABLED - Cy_SysClk_ClkPumpInit(); - #endif - - #ifdef CY_CFG_SYSCLK_CLKBAK_ENABLED - Cy_SysClk_ClkBakInit(); - #endif - - /* Configure default enabled clocks */ - #ifdef CY_CFG_SYSCLK_ILO_ENABLED - Cy_SysClk_IloInit(); - #else - Cy_SysClk_IloDisable(); - Cy_SysClk_IloHibernateOn(false); - #endif - - #ifndef CY_CFG_SYSCLK_IMO_ENABLED - #error the IMO must be enabled for proper chip operation - #endif - - #ifdef CY_CFG_SYSCLK_MFO_ENABLED - Cy_SysClk_MfoInit(); - #endif - - #ifdef CY_CFG_SYSCLK_CLKMF_ENABLED - Cy_SysClk_ClkMfInit(); - #endif - - /* Set accurate flash wait states */ - #if (defined (CY_CFG_PWR_ENABLED) && defined (CY_CFG_SYSCLK_CLKHF0_ENABLED)) - Cy_SysLib_SetWaitStates(CY_CFG_PWR_USING_ULP != 0, CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ); - #endif - - /* Update System Core Clock values for correct Cy_SysLib_Delay functioning */ - SystemCoreClockUpdate(); - -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_0_obj); -#endif //defined (CY_USING_HAL) - -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_1_obj); -#endif //defined (CY_USING_HAL) - -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_2_obj); -#endif //defined (CY_USING_HAL) - -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_3_obj); -#endif //defined (CY_USING_HAL) - -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_4_obj); -#endif //defined (CY_USING_HAL) -} diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h deleted file mode 100644 index bace2bf4d1..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h +++ /dev/null @@ -1,113 +0,0 @@ -/******************************************************************************* -* File Name: cycfg_system.h -* -* Description: -* System configuration -* This file was automatically generated and should not be modified. -* Device Configurator: 2.0.0.1483 -* Device Support Library (libs/psoc6pdl): 1.4.1.2240 -* -******************************************************************************** -* Copyright 2017-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -********************************************************************************/ - -#if !defined(CYCFG_SYSTEM_H) -#define CYCFG_SYSTEM_H - -#include "cycfg_notices.h" -#include "cy_sysclk.h" -#include "cy_systick.h" -#if defined (CY_USING_HAL) - #include "cyhal_hwmgr.h" -#endif //defined (CY_USING_HAL) -#include "cy_gpio.h" -#include "cy_syspm.h" - -#if defined(__cplusplus) -extern "C" { -#endif - -#define cpuss_0_dap_0_ENABLED 1U -#define srss_0_clock_0_ENABLED 1U -#define srss_0_clock_0_altsystickclk_0_ENABLED 1U -#define srss_0_clock_0_bakclk_0_ENABLED 1U -#define srss_0_clock_0_fastclk_0_ENABLED 1U -#define srss_0_clock_0_fll_0_ENABLED 1U -#define srss_0_clock_0_hfclk_0_ENABLED 1U -#define CY_CFG_SYSCLK_CLKHF0 0UL -#define srss_0_clock_0_hfclk_1_ENABLED 1U -#define CY_CFG_SYSCLK_CLKHF1 1UL -#define srss_0_clock_0_hfclk_2_ENABLED 1U -#define CY_CFG_SYSCLK_CLKHF2 2UL -#define srss_0_clock_0_hfclk_3_ENABLED 1U -#define CY_CFG_SYSCLK_CLKHF3 3UL -#define srss_0_clock_0_hfclk_4_ENABLED 1U -#define CY_CFG_SYSCLK_CLKHF4 4UL -#define srss_0_clock_0_ilo_0_ENABLED 1U -#define srss_0_clock_0_imo_0_ENABLED 1U -#define srss_0_clock_0_lfclk_0_ENABLED 1U -#define CY_CFG_SYSCLK_CLKLF_FREQ_HZ 32768 -#define srss_0_clock_0_pathmux_0_ENABLED 1U -#define srss_0_clock_0_pathmux_1_ENABLED 1U -#define srss_0_clock_0_pathmux_2_ENABLED 1U -#define srss_0_clock_0_pathmux_3_ENABLED 1U -#define srss_0_clock_0_pathmux_4_ENABLED 1U -#define srss_0_clock_0_periclk_0_ENABLED 1U -#define srss_0_clock_0_pll_0_ENABLED 1U -#define srss_0_clock_0_slowclk_0_ENABLED 1U -#define srss_0_clock_0_timerclk_0_ENABLED 1U -#define srss_0_clock_0_wco_0_ENABLED 1U -#define srss_0_power_0_ENABLED 1U -#define CY_CFG_PWR_MODE_LP 0x01UL -#define CY_CFG_PWR_MODE_ULP 0x02UL -#define CY_CFG_PWR_MODE_ACTIVE 0x04UL -#define CY_CFG_PWR_MODE_SLEEP 0x08UL -#define CY_CFG_PWR_MODE_DEEPSLEEP 0x10UL -#define CY_CFG_PWR_SYS_IDLE_MODE CY_CFG_PWR_MODE_DEEPSLEEP -#define CY_CFG_PWR_SYS_ACTIVE_MODE CY_CFG_PWR_MODE_LP -#define CY_CFG_PWR_DEEPSLEEP_LATENCY 0UL -#define CY_CFG_PWR_USING_LDO 1 -#define CY_CFG_PWR_VDDA_MV 3300 -#define CY_CFG_PWR_VDDD_MV 3300 -#define CY_CFG_PWR_VBACKUP_MV 3300 -#define CY_CFG_PWR_VDD_NS_MV 3300 -#define CY_CFG_PWR_VDDIO0_MV 3300 -#define CY_CFG_PWR_VDDIO1_MV 3300 - -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj; -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj; -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj; -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_3_obj; -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_4_obj; -#endif //defined (CY_USING_HAL) - -void init_cycfg_system(void); - -#if defined(__cplusplus) -} -#endif - - -#endif /* CYCFG_SYSTEM_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi deleted file mode 100644 index f6145a495b..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi +++ /dev/null @@ -1,63 +0,0 @@ - - - - PSoC 6.xml - - - 0 - S25FL512S-4byteaddr - true - None - 0x18000000 - 0x4000000 - 0x1BFFFFFF - true - false - QUAD_SPI_DATA_0_3 - S25FL512S-4byteaddr - true - - - 1 - Not used - false - None - 0x18010000 - 0x10000 - 0x1801FFFF - false - false - SPI_MOSI_MISO_DATA_0_1 - default_memory.xml - true - - - 2 - Not used - false - None - 0x18020000 - 0x10000 - 0x1802FFFF - false - false - SPI_MOSI_MISO_DATA_0_1 - default_memory.xml - true - - - 3 - Not used - false - None - 0x18030000 - 0x10000 - 0x1803FFFF - false - false - SPI_MOSI_MISO_DATA_0_1 - default_memory.xml - true - - - diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/design.modus b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/design.modus deleted file mode 100644 index 4059eac047..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/design.modus +++ /dev/null @@ -1,486 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_02_cm0plus.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_02_cm0plus.S deleted file mode 100644 index 2ebb953cfd..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_02_cm0plus.S +++ /dev/null @@ -1,213 +0,0 @@ -;/**************************************************************************//** -; * @file startup_psoc6_02_cm0plus.S -; * @brief CMSIS Core Device Startup File for -; * ARMCM0plus Device Series -; * @version V5.00 -; * @date 02. March 2016 -; ******************************************************************************/ -;/* -; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. -; * -; * SPDX-License-Identifier: Apache-2.0 -; * -; * Licensed under the Apache License, Version 2.0 (the License); you may -; * not use this file except in compliance with the License. -; * You may obtain a copy of the License at -; * -; * www.apache.org/licenses/LICENSE-2.0 -; * -; * Unless required by applicable law or agreed to in writing, software -; * distributed under the License is distributed on an AS IS BASIS, WITHOUT -; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -; * See the License for the specific language governing permissions and -; * limitations under the License. -; */ - - PRESERVE8 - THUMB - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| - -__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack - DCD Reset_Handler ; Reset Handler - - DCD 0x0000000D ; NMI Handler located at ROM code - DCD HardFault_Handler ; Hard Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External interrupts Description - DCD NvicMux0_IRQHandler ; CPU User Interrupt #0 - DCD NvicMux1_IRQHandler ; CPU User Interrupt #1 - DCD NvicMux2_IRQHandler ; CPU User Interrupt #2 - DCD NvicMux3_IRQHandler ; CPU User Interrupt #3 - DCD NvicMux4_IRQHandler ; CPU User Interrupt #4 - DCD NvicMux5_IRQHandler ; CPU User Interrupt #5 - DCD NvicMux6_IRQHandler ; CPU User Interrupt #6 - DCD NvicMux7_IRQHandler ; CPU User Interrupt #7 - DCD Internal0_IRQHandler ; Internal SW Interrupt #0 - DCD Internal1_IRQHandler ; Internal SW Interrupt #1 - DCD Internal2_IRQHandler ; Internal SW Interrupt #2 - DCD Internal3_IRQHandler ; Internal SW Interrupt #3 - DCD Internal4_IRQHandler ; Internal SW Interrupt #4 - DCD Internal5_IRQHandler ; Internal SW Interrupt #5 - DCD Internal6_IRQHandler ; Internal SW Interrupt #6 - DCD Internal7_IRQHandler ; Internal SW Interrupt #7 - -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - EXPORT __ramVectors - AREA RESET_RAM, READWRITE, NOINIT -__ramVectors SPACE __Vectors_Size - - - AREA |.text|, CODE, READONLY - - -; Weak function for startup customization -; -; Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) -; because this function is executed as the first instruction in the ResetHandler. -; The PDL is also not initialized to use the proper register offsets. -; The user of this function is responsible for initializing the PDL and resources before using them. -; -Cy_OnResetUser PROC - EXPORT Cy_OnResetUser [WEAK] - BX LR - ENDP - -; Reset Handler -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT __main - - ; Define strong function for startup customization - BL Cy_OnResetUser - - ; Copy vectors from ROM to RAM - LDR r1, =__Vectors - LDR r0, =__ramVectors - LDR r2, =__Vectors_Size -Vectors_Copy - LDR r3, [r1] - STR r3, [r0] - ADDS r0, r0, #4 - ADDS r1, r1, #4 - SUBS r2, r2, #1 - CMP r2, #0 - BNE Vectors_Copy - - ; Update Vector Table Offset Register. */ - LDR r0, =__ramVectors - LDR r1, =0xE000ED08 - STR r0, [r1] - dsb 0xF - - LDR R0, =__main - BLX R0 - - ; Should never get here - B . - - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP - -Cy_SysLib_FaultHandler PROC - EXPORT Cy_SysLib_FaultHandler [WEAK] - B . - ENDP - -HardFault_Handler PROC - EXPORT HardFault_Handler [WEAK] - movs r0, #4 - mov r1, LR - tst r0, r1 - beq L_MSP - mrs r0, PSP - bl L_API_call -L_MSP - mrs r0, MSP -L_API_call - bl Cy_SysLib_FaultHandler - ENDP - -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - EXPORT Default_Handler [WEAK] - EXPORT NvicMux0_IRQHandler [WEAK] - EXPORT NvicMux1_IRQHandler [WEAK] - EXPORT NvicMux2_IRQHandler [WEAK] - EXPORT NvicMux3_IRQHandler [WEAK] - EXPORT NvicMux4_IRQHandler [WEAK] - EXPORT NvicMux5_IRQHandler [WEAK] - EXPORT NvicMux6_IRQHandler [WEAK] - EXPORT NvicMux7_IRQHandler [WEAK] - EXPORT Internal0_IRQHandler [WEAK] - EXPORT Internal1_IRQHandler [WEAK] - EXPORT Internal2_IRQHandler [WEAK] - EXPORT Internal3_IRQHandler [WEAK] - EXPORT Internal4_IRQHandler [WEAK] - EXPORT Internal5_IRQHandler [WEAK] - EXPORT Internal6_IRQHandler [WEAK] - EXPORT Internal7_IRQHandler [WEAK] - -NvicMux0_IRQHandler -NvicMux1_IRQHandler -NvicMux2_IRQHandler -NvicMux3_IRQHandler -NvicMux4_IRQHandler -NvicMux5_IRQHandler -NvicMux6_IRQHandler -NvicMux7_IRQHandler -Internal0_IRQHandler -Internal1_IRQHandler -Internal2_IRQHandler -Internal3_IRQHandler -Internal4_IRQHandler -Internal5_IRQHandler -Internal6_IRQHandler -Internal7_IRQHandler - - B . - ENDP - - ALIGN - - END - - -; [] END OF FILE diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_psoc6_02_cm0plus.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_psoc6_02_cm0plus.S deleted file mode 100644 index 3b77acffe3..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_psoc6_02_cm0plus.S +++ /dev/null @@ -1,317 +0,0 @@ -;/**************************************************************************//** -; * @file startup_psoc6_02_cm0plus.S -; * @brief CMSIS Core Device Startup File for -; * ARMCM0plus Device Series -; * @version V5.00 -; * @date 08. March 2016 -; ******************************************************************************/ -;/* -; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. -; * -; * SPDX-License-Identifier: Apache-2.0 -; * -; * Licensed under the Apache License, Version 2.0 (the License); you may -; * not use this file except in compliance with the License. -; * You may obtain a copy of the License at -; * -; * www.apache.org/licenses/LICENSE-2.0 -; * -; * Unless required by applicable law or agreed to in writing, software -; * distributed under the License is distributed on an AS IS BASIS, WITHOUT -; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -; * See the License for the specific language governing permissions and -; * limitations under the License. -; */ - -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - SECTION .intvec_ram:DATA:NOROOT(2) - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - EXTERN __iar_data_init3 - PUBLIC __vector_table - PUBLIC __vector_table_0x1c - PUBLIC __Vectors - PUBLIC __Vectors_End - PUBLIC __Vectors_Size - PUBLIC __ramVectors - - DATA - -__vector_table - DCD sfe(CSTACK) - DCD Reset_Handler - - DCD 0x0000000D ; NMI_Handler is defined in ROM code - DCD HardFault_Handler - DCD 0 - DCD 0 - DCD 0 -__vector_table_0x1c - DCD 0 - DCD 0 - DCD 0 - DCD 0 - DCD SVC_Handler - DCD 0 - DCD 0 - DCD PendSV_Handler - DCD SysTick_Handler - - ; External interrupts Description - DCD NvicMux0_IRQHandler ; CPU User Interrupt #0 - DCD NvicMux1_IRQHandler ; CPU User Interrupt #1 - DCD NvicMux2_IRQHandler ; CPU User Interrupt #2 - DCD NvicMux3_IRQHandler ; CPU User Interrupt #3 - DCD NvicMux4_IRQHandler ; CPU User Interrupt #4 - DCD NvicMux5_IRQHandler ; CPU User Interrupt #5 - DCD NvicMux6_IRQHandler ; CPU User Interrupt #6 - DCD NvicMux7_IRQHandler ; CPU User Interrupt #7 - DCD Internal0_IRQHandler ; Internal SW Interrupt #0 - DCD Internal1_IRQHandler ; Internal SW Interrupt #1 - DCD Internal2_IRQHandler ; Internal SW Interrupt #2 - DCD Internal3_IRQHandler ; Internal SW Interrupt #3 - DCD Internal4_IRQHandler ; Internal SW Interrupt #4 - DCD Internal5_IRQHandler ; Internal SW Interrupt #5 - DCD Internal6_IRQHandler ; Internal SW Interrupt #6 - DCD Internal7_IRQHandler ; Internal SW Interrupt #7 - -__Vectors_End - -__Vectors EQU __vector_table -__Vectors_Size EQU __Vectors_End - __Vectors - - SECTION .intvec_ram:DATA:REORDER:NOROOT(2) -__ramVectors - DS32 __Vectors_Size - - - THUMB - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default handlers -;; - PUBWEAK Default_Handler - SECTION .text:CODE:REORDER:NOROOT(2) -Default_Handler - B Default_Handler - - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Weak function for startup customization -;; -;; Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) -;; because this function is executed as the first instruction in the ResetHandler. -;; The PDL is also not initialized to use the proper register offsets. -;; The user of this function is responsible for initializing the PDL and resources before using them. -;; - PUBWEAK Cy_OnResetUser - SECTION .text:CODE:REORDER:NOROOT(2) -Cy_OnResetUser - BX LR - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Define strong version to return zero for -;; __iar_program_start to skip data sections -;; initialization. -;; - PUBLIC __low_level_init - SECTION .text:CODE:REORDER:NOROOT(2) -__low_level_init - MOVS R0, #0 - BX LR - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - THUMB - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER:NOROOT(2) -Reset_Handler - - ; Define strong function for startup customization - LDR R0, =Cy_OnResetUser - BLX R0 - - ; Copy vectors from ROM to RAM - LDR r1, =__vector_table - LDR r0, =__ramVectors - LDR r2, =__Vectors_Size -intvec_copy - LDR r3, [r1] - STR r3, [r0] - ADDS r0, r0, #4 - ADDS r1, r1, #4 - SUBS r2, r2, #1 - CMP r2, #0 - BNE intvec_copy - - ; Update Vector Table Offset Register - LDR r0, =__ramVectors - LDR r1, =0xE000ED08 - STR r0, [r1] - dsb - - LDR R0, =__iar_program_start - BLX R0 - -; Should never get here -Cy_Main_Exited - B Cy_Main_Exited - - - PUBWEAK NMI_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -NMI_Handler - B NMI_Handler - - - PUBWEAK Cy_SysLib_FaultHandler - SECTION .text:CODE:REORDER:NOROOT(1) -Cy_SysLib_FaultHandler - B Cy_SysLib_FaultHandler - - PUBWEAK HardFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -HardFault_Handler - IMPORT Cy_SysLib_FaultHandler - movs r0, #4 - mov r1, LR - tst r0, r1 - beq L_MSP - mrs r0, PSP - b L_API_call -L_MSP - mrs r0, MSP -L_API_call - ; Storing LR content for Creator call stack trace - push {LR} - bl Cy_SysLib_FaultHandler - - - PUBWEAK SVC_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SVC_Handler - B SVC_Handler - - PUBWEAK PendSV_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PendSV_Handler - B PendSV_Handler - - PUBWEAK SysTick_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SysTick_Handler - B SysTick_Handler - - - ; External interrupts - PUBWEAK NvicMux0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -NvicMux0_IRQHandler - B NvicMux0_IRQHandler - - PUBWEAK NvicMux1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -NvicMux1_IRQHandler - B NvicMux1_IRQHandler - - PUBWEAK NvicMux2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -NvicMux2_IRQHandler - B NvicMux2_IRQHandler - - PUBWEAK NvicMux3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -NvicMux3_IRQHandler - B NvicMux3_IRQHandler - - PUBWEAK NvicMux4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -NvicMux4_IRQHandler - B NvicMux4_IRQHandler - - PUBWEAK NvicMux5_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -NvicMux5_IRQHandler - B NvicMux5_IRQHandler - - PUBWEAK NvicMux6_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -NvicMux6_IRQHandler - B NvicMux6_IRQHandler - - PUBWEAK NvicMux7_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -NvicMux7_IRQHandler - B NvicMux7_IRQHandler - - PUBWEAK Internal0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -Internal0_IRQHandler - B Internal0_IRQHandler - - PUBWEAK Internal1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -Internal1_IRQHandler - B Internal1_IRQHandler - - PUBWEAK Internal2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -Internal2_IRQHandler - B Internal2_IRQHandler - - PUBWEAK Internal3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -Internal3_IRQHandler - B Internal3_IRQHandler - - PUBWEAK Internal4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -Internal4_IRQHandler - B Internal4_IRQHandler - - PUBWEAK Internal5_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -Internal5_IRQHandler - B Internal5_IRQHandler - - PUBWEAK Internal6_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -Internal6_IRQHandler - B Internal6_IRQHandler - - PUBWEAK Internal7_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -Internal7_IRQHandler - B Internal7_IRQHandler - - - END - - -; [] END OF FILE diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xxa_cm4.sct b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xxa_cm4.sct deleted file mode 100644 index c6b552dce0..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xxa_cm4.sct +++ /dev/null @@ -1,308 +0,0 @@ -#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 -; The first line specifies a preprocessor command that the linker invokes -; to pass a scatter file through a C preprocessor. - -;******************************************************************************* -;* \file cyb06xxa_cm4.sct -;* \version 2.70.1 -;* -;* Linker file for the ARMCC. -;* -;* The main purpose of the linker script is to describe how the sections in the -;* input files should be mapped into the output file, and to control the memory -;* layout of the output file. -;* -;* \note The entry point location is fixed and starts at 0x10000000. The valid -;* application image should be placed there. -;* -;* \note The linker files included with the PDL template projects must be -;* generic and handle all common use cases. Your project may not use every -;* section defined in the linker files. In that case you may see the warnings -;* during the build process: L6314W (no section matches pattern) and/or L6329W -;* (pattern only matches removed unused sections). In your project, you can -;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to -;* the linker, simply comment out or remove the relevant code in the linker -;* file. -;* -;******************************************************************************* -;* \copyright -;* Copyright 2016-2020 Cypress Semiconductor Corporation -;* Copyright 2020 Arm Limited -;* SPDX-License-Identifier: Apache-2.0 -;* -;* Licensed under the Apache License, Version 2.0 (the "License"); -;* you may not use this file except in compliance with the License. -;* You may obtain a copy of the License at -;* -;* http://www.apache.org/licenses/LICENSE-2.0 -;* -;* Unless required by applicable law or agreed to in writing, software -;* distributed under the License is distributed on an "AS IS" BASIS, -;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -;* See the License for the specific language governing permissions and -;* limitations under the License. -;******************************************************************************/ - -#include "../../../partition/region_defs.h" - -#if !defined(MBED_ROM_START) - #define MBED_ROM_START NS_CODE_START -#endif - -;* MBED_APP_START is being used by the bootloader build script and -;* will be calculate by the system. Without bootloader the MBED_APP_START -;* is equal to MBED_ROM_START -;* -#if !defined(MBED_APP_START) - #define MBED_APP_START MBED_ROM_START -#endif - -#if !defined(MBED_ROM_SIZE) - #define MBED_ROM_SIZE NS_CODE_SIZE -#endif - -;* MBED_APP_SIZE is being used by the bootloader build script and -;* will be calculate by the system. Without bootloader the MBED_APP_SIZE -;* is equal to MBED_ROM_SIZE -;* -#if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE MBED_ROM_SIZE -#endif - -#if !defined(MBED_RAM_START) - #define MBED_RAM_START NS_DATA_START -#endif - -#if !defined(MBED_RAM_SIZE) - #define MBED_RAM_SIZE NS_DATA_SIZE -#endif - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE NS_MSP_STACK_SIZE -#endif - -; Shared memory area between Non-secure and Secure -#define MBED_DATA_SHARED_SIZE NS_DATA_SHARED_SIZE - -; The defines below describe the location and size of blocks of memory in the target. -; Use these defines to specify the memory regions available for allocation. - -; The following defines control RAM and flash memory allocation for the CM4 core. -; RAM -#define RAM_START MBED_RAM_START -#define RAM_SIZE MBED_RAM_SIZE -; Flash -#define FLASH_START MBED_APP_START -#define FLASH_SIZE MBED_APP_SIZE - -; The following defines describe a 32K flash region used for EEPROM emulation. -; This region can also be used as the general purpose flash. -; You can assign sections to this memory region for only one of the cores. -; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. -; Therefore, repurposing this memory region will prevent such middleware from operation. -#define EM_EEPROM_START 0x14000000 -#define EM_EEPROM_SIZE 0x8000 - -; The following defines describe device specific memory regions and must not be changed. -; Supervisory flash: User data -#define SFLASH_USER_DATA_START 0x16000800 -#define SFLASH_USER_DATA_SIZE 0x00000800 - -; Supervisory flash: Normal Access Restrictions (NAR) -#define SFLASH_NAR_START 0x16001A00 -#define SFLASH_NAR_SIZE 0x00000200 - -; Supervisory flash: Public Key -#define SFLASH_PUBLIC_KEY_START 0x16005A00 -#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 - -; Supervisory flash: Table of Content # 2 -#define SFLASH_TOC_2_START 0x16007C00 -#define SFLASH_TOC_2_SIZE 0x00000200 - -; Supervisory flash: Table of Content # 2 Copy -#define SFLASH_RTOC_2_START 0x16007E00 -#define SFLASH_RTOC_2_SIZE 0x00000200 - -; External memory -#define XIP_START 0x18000000 -#define XIP_SIZE 0x08000000 - -; eFuse -#define EFUSE_START 0x90700000 -#define EFUSE_SIZE 0x100000 - - -; Cortex-M4 application flash area -LR_IROM1 FLASH_START FLASH_SIZE -{ - ER_FLASH_VECTORS +0 - { - * (RESET, +FIRST) - } - - ER_FLASH_CODE +0 FIXED - { - * (InRoot$$Sections) - * (+RO) - } - - ER_RAM_VECTORS RAM_START UNINIT - { - * (RESET_RAM, +FIRST) - } - - RW_RAM_DATA +0 - { - * (.cy_ramfunc) - * (+RW, +ZI) - } - - ; Place variables in the section that should not be initialized during the - ; device startup. - RW_IRAM1 +0 UNINIT - { - * (.noinit) - } - - ; Application heap area (HEAP) - ARM_LIB_HEAP +0 ALIGN 4 EMPTY RAM_START+RAM_SIZE-MBED_BOOT_STACK_SIZE-MBED_DATA_SHARED_SIZE-ImageLimit(RW_IRAM1) - { - } - - ; Stack region growing down - ARM_LIB_STACK RAM_START+RAM_SIZE-MBED_DATA_SHARED_SIZE ALIGN 4 EMPTY -MBED_BOOT_STACK_SIZE - { - } - - ; Stack area overflowed within RAM - ScatterAssert(ImageBase(ARM_LIB_STACK) + ImageLength(ARM_LIB_STACK) == RAM_START+RAM_SIZE-MBED_DATA_SHARED_SIZE) - - ; Shared region - ARM_LIB_SHARED RAM_START+RAM_SIZE-MBED_DATA_SHARED_SIZE ALIGN 4 EMPTY MBED_DATA_SHARED_SIZE - { - } - - ; Shared area overflowed within RAM - ScatterAssert(ImageBase(ARM_LIB_SHARED) + ImageLength(ARM_LIB_SHARED) == RAM_START+RAM_SIZE) - - - ; Used for the digital signature of the secure application and the - ; Bootloader SDK application. The size of the section depends on the required - ; data size. - .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256 - { - * (.cy_app_signature) - } -} - - -; Emulated EEPROM Flash area -LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE -{ - .cy_em_eeprom +0 - { - * (.cy_em_eeprom) - } -} - -; Supervisory flash: User data -LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE -{ - .cy_sflash_user_data +0 - { - * (.cy_sflash_user_data) - } -} - -; Supervisory flash: Normal Access Restrictions (NAR) -LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE -{ - .cy_sflash_nar +0 - { - * (.cy_sflash_nar) - } -} - -; Supervisory flash: Public Key -LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE -{ - .cy_sflash_public_key +0 - { - * (.cy_sflash_public_key) - } -} - -; Supervisory flash: Table of Content # 2 -LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE -{ - .cy_toc_part2 +0 - { - * (.cy_toc_part2) - } -} - -; Supervisory flash: Table of Content # 2 Copy -LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE -{ - .cy_rtoc_part2 +0 - { - * (.cy_rtoc_part2) - } -} - - -; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. -LR_EROM XIP_START XIP_SIZE -{ - .cy_xip +0 - { - * (.cy_xip) - } -} - - -; eFuse -LR_EFUSE EFUSE_START EFUSE_SIZE -{ - .cy_efuse +0 - { - * (.cy_efuse) - } -} - - -; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. -CYMETA 0x90500000 -{ - .cymeta +0 { * (.cymeta) } -} - -/* The following symbols used by the cymcuelftool. */ -/* Flash */ -#define __cy_memory_0_start 0x10000000 -#define __cy_memory_0_length 0x001D0000 -#define __cy_memory_0_row_size 0x200 - -/* Emulated EEPROM Flash area */ -#define __cy_memory_1_start 0x14000000 -#define __cy_memory_1_length 0x8000 -#define __cy_memory_1_row_size 0x200 - -/* Supervisory Flash */ -#define __cy_memory_2_start 0x16000000 -#define __cy_memory_2_length 0x8000 -#define __cy_memory_2_row_size 0x200 - -/* XIP */ -#define __cy_memory_3_start 0x18000000 -#define __cy_memory_3_length 0x08000000 -#define __cy_memory_3_row_size 0x200 - -/* eFuse */ -#define __cy_memory_4_start 0x90700000 -#define __cy_memory_4_length 0x100000 -#define __cy_memory_4_row_size 1 - - -/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xxa_cm4.ld b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xxa_cm4.ld deleted file mode 100644 index 914ebc35fd..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xxa_cm4.ld +++ /dev/null @@ -1,454 +0,0 @@ -/***************************************************************************//** -* \file cyb06xxa_cm4.ld -* \version 2.70.1 -* -* Linker file for the GNU C compiler. -* -* The main purpose of the linker script is to describe how the sections in the -* input files should be mapped into the output file, and to control the memory -* layout of the output file. -* -* \note The entry point location is fixed and starts at 0x10000000. The valid -* application image should be placed there. -* -* \note The linker files included with the PDL template projects must be generic -* and handle all common use cases. Your project may not use every section -* defined in the linker files. In that case you may see warnings during the -* build process. In your project, you can simply comment out or remove the -* relevant code in the linker file. -* -******************************************************************************** -* \copyright -* Copyright 2016-2020 Cypress Semiconductor Corporation -* Copyright 2020 Arm Limited -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ - -OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") -SEARCH_DIR(.) -GROUP(-lgcc -lc -lnosys) -ENTRY(Reset_Handler) - -#include "../../../partition/region_defs.h" - -#if !defined(MBED_ROM_START) - #define MBED_ROM_START NS_CODE_START -#endif - -/* MBED_APP_START is being used by the bootloader build script and -* will be calculate by the system. Without bootloader the MBED_APP_START -* is equal to MBED_ROM_START -*/ -#if !defined(MBED_APP_START) - #define MBED_APP_START MBED_ROM_START -#endif - -#if !defined(MBED_ROM_SIZE) - #define MBED_ROM_SIZE NS_CODE_SIZE -#endif - -/* MBED_APP_SIZE is being used by the bootloader build script and -* will be calculate by the system. Without bootloader the MBED_APP_SIZE -* is equal to MBED_ROM_SIZE -*/ -#if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE MBED_ROM_SIZE -#endif - -#if !defined(MBED_RAM_START) - #define MBED_RAM_START NS_DATA_START -#endif - -#if !defined(MBED_RAM_SIZE) - #define MBED_RAM_SIZE NS_DATA_SIZE -#endif - -/* Size of the stack section in CM4 SRAM area */ -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE NS_MSP_STACK_SIZE -#endif - -/* Shared memory area between Non-Secure and Secure */ -#define MBED_DATA_SHARED_SIZE NS_DATA_SHARED_SIZE - -/* Force symbol to be entered in the output file as an undefined symbol. Doing -* this may, for example, trigger linking of additional modules from standard -* libraries. You may list several symbols for each EXTERN, and you may use -* EXTERN multiple times. This command has the same effect as the -u command-line -* option. -*/ -EXTERN(Reset_Handler) - -/* The MEMORY section below describes the location and size of blocks of memory in the target. -* Use this section to specify the memory regions available for allocation. -*/ -MEMORY -{ - /* The ram and flash regions control RAM and flash memory allocation for the CM4 core. - */ - ram (rwx) : ORIGIN = MBED_RAM_START, LENGTH = MBED_RAM_SIZE - flash (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE - - /* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash. - * You can assign sections to this memory region for only one of the cores. - * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. - * Therefore, repurposing this memory region will prevent such middleware from operation. - */ - em_eeprom (rx) : ORIGIN = 0x14000000, LENGTH = 0x8000 /* 32 KB */ - - /* The following regions define device specific memory regions and must not be changed. */ - sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 /* Supervisory flash: User data */ - sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 /* Supervisory flash: Normal Access Restrictions (NAR) */ - sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 /* Supervisory flash: Public Key */ - sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 */ - sflash_rtoc_2 (rx) : ORIGIN = 0x16007E00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 Copy */ - xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */ - efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */ -} - -/* Library configurations */ -GROUP(libgcc.a libc.a libm.a libnosys.a) - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __Vectors_End - * __Vectors_Size - */ - - -SECTIONS -{ - /* Cortex-M4 application flash area */ - .text ORIGIN(flash) : - { - /* Cortex-M4 flash vector table */ - . = ALIGN(4); - __Vectors = . ; - KEEP(*(.vectors)) - . = ALIGN(4); - __Vectors_End = .; - __Vectors_Size = __Vectors_End - __Vectors; - __end__ = .; - - . = ALIGN(4); - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - /* Read-only code (constants). */ - *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*) - - KEEP(*(.eh_frame*)) - } > flash - - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > flash - - __exidx_start = .; - - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > flash - __exidx_end = .; - - - /* To copy multiple ROM to RAM sections, - * uncomment .copy.table section and, - * define __STARTUP_COPY_MULTIPLE in startup_psoc6_02_cm4.S */ - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - - /* Copy interrupt vectors from flash to RAM */ - LONG (__Vectors) /* From */ - LONG (__ram_vectors_start__) /* To */ - LONG (__Vectors_End - __Vectors) /* Size */ - - /* Copy data section to RAM */ - LONG (__etext) /* From */ - LONG (__data_start__) /* To */ - LONG (__data_end__ - __data_start__) /* Size */ - - __copy_table_end__ = .; - } > flash - - - /* To clear multiple BSS sections, - * uncomment .zero.table section and, - * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_02_cm4.S */ - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - LONG (__bss_start__) - LONG (__bss_end__ - __bss_start__) - __zero_table_end__ = .; - } > flash - - __etext = . ; - - - .ramVectors (NOLOAD) : ALIGN(8) - { - __ram_vectors_start__ = .; - KEEP(*(.ram_vectors)) - __ram_vectors_end__ = .; - } > ram - - - .data __ram_vectors_end__ : AT (__etext) - { - __data_start__ = .; - - *(vtable) - *(.data*) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(4); - - KEEP(*(.cy_ramfunc*)) - . = ALIGN(4); - - __data_end__ = .; - - } > ram - - - /* Place variables in the section that should not be initialized during the - * device startup. - */ - .noinit (NOLOAD) : ALIGN(8) - { - KEEP(*(.noinit)) - } > ram - - - /* The uninitialized global or static variables are placed in this section. - * - * The NOLOAD attribute tells linker that .bss section does not consume - * any space in the image. The NOLOAD attribute changes the .bss type to - * NOBITS, and that makes linker to A) not allocate section in memory, and - * A) put information to clear the section with all zeros during application - * loading. - * - * Without the NOLOAD attribute, the .bss section might get PROGBITS type. - * This makes linker to A) allocate zeroed section in memory, and B) copy - * this section to RAM during application loading. - */ - .bss (NOLOAD): - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > ram - - - .heap (NOLOAD): - { - __HeapBase = .; - __end__ = .; - end = __end__; - KEEP(*(.heap*)) - . = ORIGIN(ram) + LENGTH(ram) - MBED_BOOT_STACK_SIZE - MBED_DATA_SHARED_SIZE; - . = ALIGN(4); - __StackLimit = .; - __HeapLimit = .; - } > ram - - - __StackTop = (__StackLimit + MBED_BOOT_STACK_SIZE + 3) & 0xFFFFFFFC; - PROVIDE(__stack = __StackTop); - - .shared __StackTop (NOLOAD): - { - __SharedStart = .; - . += MBED_DATA_SHARED_SIZE; - KEEP(*(.shared*)) - __SharedLimit = .; - } > ram - - /* Check if Shared area overflowed within RAM */ - ASSERT(__SharedLimit == ORIGIN(ram) + LENGTH(ram), "Shared area overflowed within RAM") - - /* Used for the digital signature of the secure application and the Bootloader SDK application. - * The size of the section depends on the required data size. */ - .cy_app_signature ORIGIN(flash) + LENGTH(flash) - 256 : - { - KEEP(*(.cy_app_signature)) - } > flash - - - /* Emulated EEPROM Flash area */ - .cy_em_eeprom : - { - KEEP(*(.cy_em_eeprom)) - } > em_eeprom - - - /* Supervisory Flash: User data */ - .cy_sflash_user_data : - { - KEEP(*(.cy_sflash_user_data)) - } > sflash_user_data - - - /* Supervisory Flash: Normal Access Restrictions (NAR) */ - .cy_sflash_nar : - { - KEEP(*(.cy_sflash_nar)) - } > sflash_nar - - - /* Supervisory Flash: Public Key */ - .cy_sflash_public_key : - { - KEEP(*(.cy_sflash_public_key)) - } > sflash_public_key - - - /* Supervisory Flash: Table of Content # 2 */ - .cy_toc_part2 : - { - KEEP(*(.cy_toc_part2)) - } > sflash_toc_2 - - - /* Supervisory Flash: Table of Content # 2 Copy */ - .cy_rtoc_part2 : - { - KEEP(*(.cy_rtoc_part2)) - } > sflash_rtoc_2 - - - /* Places the code in the Execute in Place (XIP) section. See the smif driver - * documentation for details. - */ - .cy_xip : - { - KEEP(*(.cy_xip)) - } > xip - - - /* eFuse */ - .cy_efuse : - { - KEEP(*(.cy_efuse)) - } > efuse - - - /* These sections are used for additional metadata (silicon revision, - * Silicon/JTAG ID, etc.) storage. - */ - .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE -} - - -/* The following symbols used by the cymcuelftool. */ -/* Flash */ -__cy_memory_0_start = 0x10000000; -__cy_memory_0_length = 0x001D0000; -__cy_memory_0_row_size = 0x200; - -/* Emulated EEPROM Flash area */ -__cy_memory_1_start = 0x14000000; -__cy_memory_1_length = 0x8000; -__cy_memory_1_row_size = 0x200; - -/* Supervisory Flash */ -__cy_memory_2_start = 0x16000000; -__cy_memory_2_length = 0x8000; -__cy_memory_2_row_size = 0x200; - -/* XIP */ -__cy_memory_3_start = 0x18000000; -__cy_memory_3_length = 0x08000000; -__cy_memory_3_row_size = 0x200; - -/* eFuse */ -__cy_memory_4_start = 0x90700000; -__cy_memory_4_length = 0x100000; -__cy_memory_4_row_size = 1; - -/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xxa_cm4.icf b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xxa_cm4.icf deleted file mode 100644 index 397826cf1a..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xxa_cm4.icf +++ /dev/null @@ -1,272 +0,0 @@ -/******************************************************************************* -* \file cyb06xxa_cm4.icf -* \version 2.70.1 -* -* Linker file for the IAR compiler. -* -* The main purpose of the linker script is to describe how the sections in the -* input files should be mapped into the output file, and to control the memory -* layout of the output file. -* -* \note The entry point is fixed and starts at 0x10000000. The valid application -* image should be placed there. -* -* \note The linker files included with the PDL template projects must be generic -* and handle all common use cases. Your project may not use every section -* defined in the linker files. In that case you may see warnings during the -* build process. In your project, you can simply comment out or remove the -* relevant code in the linker file. -* -******************************************************************************** -* \copyright -* Copyright 2016-2020 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ - -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x00000000; - -if (!isdefinedsymbol(MBED_ROM_START)) { - define symbol MBED_ROM_START = 0x10000000; -} - -/* MBED_APP_START is being used by the bootloader build script and - * will be calculate by the system. Without bootloader the MBED_APP_START - * is equal to MBED_ROM_START - */ -if (!isdefinedsymbol(MBED_APP_START)) { - define symbol MBED_APP_START = MBED_ROM_START; -} - -if (!isdefinedsymbol(MBED_ROM_SIZE)) { - define symbol MBED_ROM_SIZE = 0x001D0000; -} - -/* MBED_APP_SIZE is being used by the bootloader build script and - * will be calculate by the system. Without bootloader the MBED_APP_SIZE - * is equal to MBED_ROM_SIZE - */ -if (!isdefinedsymbol(MBED_APP_SIZE)) { - define symbol MBED_APP_SIZE = MBED_ROM_SIZE; -} - -if (!isdefinedsymbol(MBED_RAM_START)) { - define symbol MBED_RAM_START = 0x08000000; -} - -if (!isdefinedsymbol(MBED_RAM_SIZE)) { - define symbol MBED_RAM_SIZE = 0x000EA000; -} - -if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) { - define symbol MBED_BOOT_STACK_SIZE = 0x400; -} - -/* The symbols below define the location and size of blocks of memory in the target. - * Use these symbols to specify the memory regions available for allocation. - */ - -/* The following symbols control RAM and flash memory allocation for the CM4 core. - */ -/* RAM */ -define symbol __ICFEDIT_region_IRAM1_start__ = MBED_RAM_START; -define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE - 1); -/* Flash */ -define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START; -define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE - 1); - -/* The following symbols define a 32K flash region used for EEPROM emulation. - * This region can also be used as the general purpose flash. - * You can assign sections to this memory region for only one of the cores. - * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. - * Therefore, repurposing this memory region will prevent such middleware from operation. - */ -define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000; -define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF; - -/* The following symbols define device specific memory regions and must not be changed. */ -/* Supervisory FLASH - User Data */ -define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800; -define symbol __ICFEDIT_region_IROM3_end__ = 0x160007FF; - -/* Supervisory FLASH - Normal Access Restrictions (NAR) */ -define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00; -define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF; - -/* Supervisory FLASH - Public Key */ -define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00; -define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF; - -/* Supervisory FLASH - Table of Content # 2 */ -define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00; -define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF; - -/* Supervisory FLASH - Table of Content # 2 Copy */ -define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00; -define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF; - -/* eFuse */ -define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000; -define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF; - -/* XIP */ -define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000; -define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF; - -define symbol __ICFEDIT_region_EROM2_start__ = 0x0; -define symbol __ICFEDIT_region_EROM2_end__ = 0x0; -define symbol __ICFEDIT_region_EROM3_start__ = 0x0; -define symbol __ICFEDIT_region_EROM3_end__ = 0x0; - - -define symbol __ICFEDIT_region_IRAM2_start__ = 0x0; -define symbol __ICFEDIT_region_IRAM2_end__ = 0x0; -define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; -define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; -define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; -define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; -define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; -define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; -/*-Sizes-*/ -if (!isdefinedsymbol(__STACK_SIZE)) { - define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE; -} else { - define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE; -} - -/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */ -if (!isdefinedsymbol(__HEAP_SIZE)) { - define symbol __ICFEDIT_size_heap__ = 0x0400; -} else { - define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE; -} -/**** End of ICF editor section. ###ICF###*/ - -/* The size of the MCU boot header area at the start of FLASH */ -define symbol BOOT_HEADER_SIZE = 0x400; - - -define memory mem with size = 4G; -define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]; -define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; -define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__]; -define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__]; -define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__]; -define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__]; -define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__]; -define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__]; -define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]; -define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]; - -define block RAM_DATA {readwrite section .data}; -define block RAM_OTHER {readwrite section * }; -define block RAM_NOINIT {readwrite section .noinit}; -define block RAM_BSS {readwrite section .bss}; -define block RAM with fixed order {block RAM_DATA, block RAM_OTHER, block RAM_NOINIT, block RAM_BSS}; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { }; - -define block RO {first section .intvec, readonly}; - -/*-Initializations-*/ -initialize by copy { readwrite }; -do not initialize { section .noinit, section .intvec_ram }; - -/*-Placement-*/ - -/* Flash - Cortex-M4 application */ -place at address (__ICFEDIT_region_IROM1_start__ + BOOT_HEADER_SIZE) { block RO }; - -/* Used for the digital signature of the secure application and the Bootloader SDK application. */ -".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature }; - -/* Emulated EEPROM Flash area */ -".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom }; - -/* Supervisory Flash - User Data */ -".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data }; - -/* Supervisory Flash - NAR */ -".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar }; - -/* Supervisory Flash - Public Key */ -".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key }; - -/* Supervisory Flash - TOC2 */ -".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 }; - -/* Supervisory Flash - RTOC2 */ -".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 }; - -/* eFuse */ -".cy_efuse" : place at start of IROM8_region { section .cy_efuse }; - -/* Execute in Place (XIP). See the smif driver documentation for details. */ -".cy_xip" : place at start of EROM1_region { section .cy_xip }; - -/* RAM */ -place at start of IRAM1_region { readwrite section .intvec_ram}; -place in IRAM1_region { block RAM}; -place in IRAM1_region { block HEAP}; -place at end of IRAM1_region { block CSTACK }; - -/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */ -".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; - - -keep { section .cy_app_signature, - section .cy_em_eeprom, - section .cy_sflash_user_data, - section .cy_sflash_nar, - section .cy_sflash_public_key, - section .cy_toc_part2, - section .cy_rtoc_part2, - section .cy_efuse, - section .cy_xip, - section .cymeta, - }; - - -/* The following symbols used by the cymcuelftool. */ -/* Flash */ -define exported symbol __cy_memory_0_start = 0x10000000; -define exported symbol __cy_memory_0_length = 0x001D0000; -define exported symbol __cy_memory_0_row_size = 0x200; - -/* Emulated EEPROM Flash area */ -define exported symbol __cy_memory_1_start = 0x14000000; -define exported symbol __cy_memory_1_length = 0x8000; -define exported symbol __cy_memory_1_row_size = 0x200; - -/* Supervisory Flash */ -define exported symbol __cy_memory_2_start = 0x16000000; -define exported symbol __cy_memory_2_length = 0x8000; -define exported symbol __cy_memory_2_row_size = 0x200; - -/* XIP */ -define exported symbol __cy_memory_3_start = 0x18000000; -define exported symbol __cy_memory_3_length = 0x08000000; -define exported symbol __cy_memory_3_row_size = 0x200; - -/* eFuse */ -define exported symbol __cy_memory_4_start = 0x90700000; -define exported symbol __cy_memory_4_length = 0x100000; -define exported symbol __cy_memory_4_row_size = 1; - -/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM4/system_psoc6_cm4.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM4/system_psoc6_cm4.c deleted file mode 100644 index 7e634e2f31..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM4/system_psoc6_cm4.c +++ /dev/null @@ -1,390 +0,0 @@ -/***************************************************************************//** -* \file system_psoc6_cm4.c -* \version 2.70.1 -* -* The device system-source file. -* -******************************************************************************** -* \copyright -* Copyright 2016-2020 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ - -#include -#include "system_psoc6.h" -#include "cy_device.h" -#include "cy_device_headers.h" -#include "cy_syslib.h" -#include "cy_sysclk.h" -#include "cy_wdt.h" - -#if !defined(CY_IPC_DEFAULT_CFG_DISABLE) - #include "cy_ipc_sema.h" - #include "cy_ipc_pipe.h" - #include "cy_ipc_drv.h" - - #if defined(CY_DEVICE_PSOC6ABLE2) - #include "cy_flash.h" - #endif /* defined(CY_DEVICE_PSOC6ABLE2) */ -#endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */ - - -/******************************************************************************* -* SystemCoreClockUpdate() -*******************************************************************************/ - -/** Default HFClk frequency in Hz */ -#define CY_CLK_HFCLK0_FREQ_HZ_DEFAULT (8000000UL) - -/** Default PeriClk frequency in Hz */ -#define CY_CLK_PERICLK_FREQ_HZ_DEFAULT (4000000UL) - -/** Default FastClk system core frequency in Hz */ -#define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT (8000000UL) - - -/** -* Holds the SlowClk (Cortex-M0+) or FastClk (Cortex-M4) system core clock, -* which is the system clock frequency supplied to the SysTick timer and the -* processor core clock. -* This variable implements CMSIS Core global variable. -* Refer to the [CMSIS documentation] -* (http://www.keil.com/pack/doc/CMSIS/Core/html/group__system__init__gr.html "System and Clock Configuration") -* for more details. -* This variable can be used by debuggers to query the frequency -* of the debug timer or to configure the trace clock speed. -* -* \attention Compilers must be configured to avoid removing this variable in case -* the application program is not using it. Debugging systems require the variable -* to be physically present in memory so that it can be examined to configure the debugger. */ -uint32_t SystemCoreClock = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT; - -/** Holds the HFClk0 clock frequency. Updated by \ref SystemCoreClockUpdate(). */ -uint32_t cy_Hfclk0FreqHz = CY_CLK_HFCLK0_FREQ_HZ_DEFAULT; - -/** Holds the PeriClk clock frequency. Updated by \ref SystemCoreClockUpdate(). */ -uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT; - -/** Holds the Alternate high frequency clock in Hz. Updated by \ref Cy_BLE_EcoConfigure(). */ -uint32_t cy_BleEcoClockFreqHz = 0UL; - -/* SCB->CPACR */ -#define SCB_CPACR_CP10_CP11_ENABLE (0xFUL << 20u) - - -/******************************************************************************* -* SystemInit() -*******************************************************************************/ - -/* CLK_FLL_CONFIG default values */ -#define CY_FB_CLK_FLL_CONFIG_VALUE (0x01000000u) -#define CY_FB_CLK_FLL_CONFIG2_VALUE (0x00020001u) -#define CY_FB_CLK_FLL_CONFIG3_VALUE (0x00002800u) -#define CY_FB_CLK_FLL_CONFIG4_VALUE (0x000000FFu) - -/* IPC_STRUCT7->DATA configuration */ -#define CY_STARTUP_CM0_DP_STATE (0x2uL) -#define CY_STARTUP_IPC7_DP_OFFSET (0x28u) - - -/******************************************************************************* -* SystemCoreClockUpdate (void) -*******************************************************************************/ - -/* Do not use these definitions directly in your application */ -#define CY_DELAY_MS_OVERFLOW_THRESHOLD (0x8000u) -#define CY_DELAY_1K_THRESHOLD (1000u) -#define CY_DELAY_1M_THRESHOLD (1000000u) - -uint32_t cy_delayFreqKhz = CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1K_THRESHOLD); - -uint8_t cy_delayFreqMhz = (uint8_t)CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1M_THRESHOLD); - -uint32_t cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * - CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1K_THRESHOLD); - - -/******************************************************************************* -* Function Name: SystemInit -****************************************************************************//** -* \cond -* Initializes the system: -* - Restores FLL registers to the default state for single core devices. -* - Unlocks and disables WDT. -* - Calls Cy_PDL_Init() function to define the driver library. -* - Calls the Cy_SystemInit() function, if compiled from PSoC Creator. -* - Calls \ref SystemCoreClockUpdate(). -* \endcond -*******************************************************************************/ -void SystemInit(void) -{ - Cy_PDL_Init(CY_DEVICE_CFG); - -#ifdef __CM0P_PRESENT - #if (__CM0P_PRESENT == 0) - /* Restore FLL registers to the default state as they are not restored by the ROM code */ - uint32_t copy = SRSS->CLK_FLL_CONFIG; - copy &= ~SRSS_CLK_FLL_CONFIG_FLL_ENABLE_Msk; - SRSS->CLK_FLL_CONFIG = copy; - - copy = SRSS->CLK_ROOT_SELECT[0u]; - copy &= ~SRSS_CLK_ROOT_SELECT_ROOT_DIV_Msk; /* Set ROOT_DIV = 0*/ - SRSS->CLK_ROOT_SELECT[0u] = copy; - - SRSS->CLK_FLL_CONFIG = CY_FB_CLK_FLL_CONFIG_VALUE; - SRSS->CLK_FLL_CONFIG2 = CY_FB_CLK_FLL_CONFIG2_VALUE; - SRSS->CLK_FLL_CONFIG3 = CY_FB_CLK_FLL_CONFIG3_VALUE; - SRSS->CLK_FLL_CONFIG4 = CY_FB_CLK_FLL_CONFIG4_VALUE; - - /* Unlock and disable WDT */ - Cy_WDT_Unlock(); - Cy_WDT_Disable(); - #endif /* (__CM0P_PRESENT == 0) */ -#endif /* __CM0P_PRESENT */ - - Cy_SystemInit(); - SystemCoreClockUpdate(); - -#ifdef __CM0P_PRESENT - #if (__CM0P_PRESENT == 0) - /* Configure data register (as CM0p in deep sleep state) of IPC structure #7, reserved for the Deep-Sleep operations. */ - REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = (CY_STARTUP_CM0_DP_STATE << - CY_STARTUP_IPC7_DP_OFFSET); - - /* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering. */ - REG_IPC_STRUCT_RELEASE(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = 0UL; - #endif /* (__CM0P_PRESENT == 0) */ -#endif /* __CM0P_PRESENT */ - -#if !defined(CY_IPC_DEFAULT_CFG_DISABLE) - -#ifdef __CM0P_PRESENT - #if (__CM0P_PRESENT == 0) - /* Allocate and initialize semaphores for the system operations. */ - static uint32_t ipcSemaArray[CY_IPC_SEMA_COUNT / CY_IPC_SEMA_PER_WORD]; - (void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, CY_IPC_SEMA_COUNT, ipcSemaArray); - #else - (void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, 0ul, NULL); - #endif /* (__CM0P_PRESENT) */ -#else - (void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, 0ul, NULL); -#endif /* __CM0P_PRESENT */ - - - /******************************************************************************** - * - * Initializes the system pipes. The system pipes are used by BLE and Flash. - * - * If the default startup file is not used, or SystemInit() is not called in your - * project, call the following three functions prior to executing any flash or - * EmEEPROM write or erase operation: - * -# Cy_IPC_Sema_Init() - * -# Cy_IPC_Pipe_Config() - * -# Cy_IPC_Pipe_Init() - * -# Cy_Flash_Init() - * - *******************************************************************************/ - /* Create an array of endpoint structures */ - static cy_stc_ipc_pipe_ep_t systemIpcPipeEpArray[CY_IPC_MAX_ENDPOINTS]; - - Cy_IPC_Pipe_Config(systemIpcPipeEpArray); - - static cy_ipc_pipe_callback_ptr_t systemIpcPipeSysCbArray[CY_SYS_CYPIPE_CLIENT_CNT]; - - static const cy_stc_ipc_pipe_config_t systemIpcPipeConfigCm4 = - { - /* .ep0ConfigData */ - { - /* .ipcNotifierNumber */ CY_IPC_INTR_CYPIPE_EP0, - /* .ipcNotifierPriority */ CY_SYS_INTR_CYPIPE_PRIOR_EP0, - /* .ipcNotifierMuxNumber */ CY_SYS_INTR_CYPIPE_MUX_EP0, - /* .epAddress */ CY_IPC_EP_CYPIPE_CM0_ADDR, - /* .epConfig */ CY_SYS_CYPIPE_CONFIG_EP0 - }, - /* .ep1ConfigData */ - { - /* .ipcNotifierNumber */ CY_IPC_INTR_CYPIPE_EP1, - /* .ipcNotifierPriority */ CY_SYS_INTR_CYPIPE_PRIOR_EP1, - /* .ipcNotifierMuxNumber */ 0u, - /* .epAddress */ CY_IPC_EP_CYPIPE_CM4_ADDR, - /* .epConfig */ CY_SYS_CYPIPE_CONFIG_EP1 - }, - /* .endpointClientsCount */ CY_SYS_CYPIPE_CLIENT_CNT, - /* .endpointsCallbacksArray */ systemIpcPipeSysCbArray, - /* .userPipeIsrHandler */ &Cy_SysIpcPipeIsrCm4 - }; - - Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm4); - -#if defined(CY_DEVICE_PSOC6ABLE2) - Cy_Flash_Init(); -#endif /* defined(CY_DEVICE_PSOC6ABLE2) */ - -#endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */ -} - - -/******************************************************************************* -* Function Name: Cy_SystemInit -****************************************************************************//** -* -* The function is called during device startup. Once project compiled as part of -* the PSoC Creator project, the Cy_SystemInit() function is generated by the -* PSoC Creator. -* -* The function generated by PSoC Creator performs all of the necessary device -* configuration based on the design settings. This includes settings from the -* Design Wide Resources (DWR) such as Clocks and Pins as well as any component -* configuration that is necessary. -* -*******************************************************************************/ -__WEAK void Cy_SystemInit(void) -{ - /* Empty weak function. The actual implementation to be in the PSoC Creator - * generated strong function. - */ -} - - -/******************************************************************************* -* Function Name: SystemCoreClockUpdate -****************************************************************************//** -* -* Gets core clock frequency and updates \ref SystemCoreClock, \ref -* cy_Hfclk0FreqHz, and \ref cy_PeriClkFreqHz. -* -* Updates global variables used by the \ref Cy_SysLib_Delay(), \ref -* Cy_SysLib_DelayUs(), and \ref Cy_SysLib_DelayCycles(). -* -*******************************************************************************/ -void SystemCoreClockUpdate (void) -{ - uint32 locHf0Clock = Cy_SysClk_ClkHfGetFrequency(0UL); - - if (0UL != locHf0Clock) - { - cy_Hfclk0FreqHz = locHf0Clock; - cy_PeriClkFreqHz = locHf0Clock / (1UL + (uint32_t)Cy_SysClk_ClkPeriGetDivider()); - SystemCoreClock = locHf0Clock / (1UL + (uint32_t)Cy_SysClk_ClkFastGetDivider()); - - /* Sets clock frequency for Delay API */ - cy_delayFreqMhz = (uint8_t)CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1M_THRESHOLD); - cy_delayFreqKhz = CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1K_THRESHOLD); - cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * cy_delayFreqKhz; - } -} - - -/******************************************************************************* -* Function Name: Cy_SystemInitFpuEnable -****************************************************************************//** -* -* Enables the FPU if it is used. The function is called from the startup file. -* -*******************************************************************************/ -void Cy_SystemInitFpuEnable(void) -{ - #if defined (__FPU_USED) && (__FPU_USED == 1U) - uint32_t interruptState; - interruptState = Cy_SysLib_EnterCriticalSection(); - SCB->CPACR |= SCB_CPACR_CP10_CP11_ENABLE; - __DSB(); - __ISB(); - Cy_SysLib_ExitCriticalSection(interruptState); - #endif /* (__FPU_USED) && (__FPU_USED == 1U) */ -} - - -#if !defined(CY_IPC_DEFAULT_CFG_DISABLE) -/******************************************************************************* -* Function Name: Cy_SysIpcPipeIsrCm4 -****************************************************************************//** -* -* This is the interrupt service routine for the system pipe. -* -*******************************************************************************/ -void Cy_SysIpcPipeIsrCm4(void) -{ - Cy_IPC_Pipe_ExecuteCallback(CY_IPC_EP_CYPIPE_CM4_ADDR); -} -#endif - - -/******************************************************************************* -* Function Name: Cy_MemorySymbols -****************************************************************************//** -* -* The intention of the function is to declare boundaries of the memories for the -* MDK compilers. For the rest of the supported compilers, this is done using -* linker configuration files. The following symbols used by the cymcuelftool. -* -*******************************************************************************/ -#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION < 6010050) -__asm void Cy_MemorySymbols(void) -{ - /* Flash */ - EXPORT __cy_memory_0_start - EXPORT __cy_memory_0_length - EXPORT __cy_memory_0_row_size - - /* Working Flash */ - EXPORT __cy_memory_1_start - EXPORT __cy_memory_1_length - EXPORT __cy_memory_1_row_size - - /* Supervisory Flash */ - EXPORT __cy_memory_2_start - EXPORT __cy_memory_2_length - EXPORT __cy_memory_2_row_size - - /* XIP */ - EXPORT __cy_memory_3_start - EXPORT __cy_memory_3_length - EXPORT __cy_memory_3_row_size - - /* eFuse */ - EXPORT __cy_memory_4_start - EXPORT __cy_memory_4_length - EXPORT __cy_memory_4_row_size - - /* Flash */ -__cy_memory_0_start EQU __cpp(CY_FLASH_BASE) -__cy_memory_0_length EQU __cpp(CY_FLASH_SIZE) -__cy_memory_0_row_size EQU 0x200 - - /* Flash region for EEPROM emulation */ -__cy_memory_1_start EQU __cpp(CY_EM_EEPROM_BASE) -__cy_memory_1_length EQU __cpp(CY_EM_EEPROM_SIZE) -__cy_memory_1_row_size EQU 0x200 - - /* Supervisory Flash */ -__cy_memory_2_start EQU __cpp(CY_SFLASH_BASE) -__cy_memory_2_length EQU __cpp(CY_SFLASH_SIZE) -__cy_memory_2_row_size EQU 0x200 - - /* XIP */ -__cy_memory_3_start EQU __cpp(CY_XIP_BASE) -__cy_memory_3_length EQU __cpp(CY_XIP_SIZE) -__cy_memory_3_row_size EQU 0x200 - - /* eFuse */ -__cy_memory_4_start EQU __cpp(0x90700000) -__cy_memory_4_length EQU __cpp(0x100000) -__cy_memory_4_row_size EQU __cpp(1) -} -#endif /* defined (__ARMCC_VERSION) && (__ARMCC_VERSION < 6010050) */ - - -/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/system_psoc6.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/system_psoc6.h deleted file mode 100644 index 0ad244b658..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/system_psoc6.h +++ /dev/null @@ -1,664 +0,0 @@ -/***************************************************************************//** -* \file system_psoc6.h -* \version 2.70.1 -* -* \brief Device system header file. -* -******************************************************************************** -* \copyright -* Copyright 2016-2020 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ - - -#ifndef _SYSTEM_PSOC6_H_ -#define _SYSTEM_PSOC6_H_ - -/** -* \addtogroup group_system_config -* \{ -* Provides device startup, system configuration, and linker script files. -* The system startup provides the followings features: -* - See \ref group_system_config_device_initialization for the: -* * \ref group_system_config_dual_core_device_initialization -* * \ref group_system_config_single_core_device_initialization -* - \ref group_system_config_device_memory_definition -* - \ref group_system_config_heap_stack_config -* - \ref group_system_config_default_handlers -* - \ref group_system_config_device_vector_table -* - \ref group_system_config_cm4_functions -* -* \section group_system_config_configuration Configuration Considerations -* -* \subsection group_system_config_device_memory_definition Device Memory Definition -* The flash and RAM allocation for each CPU is defined by the linker scripts. -* For dual-core devices, the physical flash and RAM memory is shared between the CPU cores. -* 2 KB of RAM (allocated at the end of RAM) are reserved for system use. -* For Single-Core devices the system reserves additional 80 bytes of RAM. -* Using the reserved memory area for other purposes will lead to unexpected behavior. -* -* \note The linker files provided with the PDL are generic and handle all common -* use cases. Your project may not use every section defined in the linker files. -* In that case you may see warnings during the build process. To eliminate build -* warnings in your project, you can simply comment out or remove the relevant -* code in the linker file. -* -* \note For the PSoC 64 Secure MCUs devices, refer to the following page: -* https://www.cypress.com/documentation/software-and-drivers/psoc-64-secure-mcu-secure-boot-sdk-user-guide -* -* -* ARM GCC\n -* The flash and RAM sections for the CPU are defined in the linker files: -* 'xx_yy.ld', where 'xx' is the device group, and 'yy' is the target CPU; for example, -* 'cy8c6xx7_cm0plus.ld' and 'cy8c6xx7_cm4_dual.ld'. -* \note If the start of the Cortex-M4 application image is changed, the value -* of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The -* \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the -* Cy_SysEnableCM4() function call. -* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. -* More about CM0+ prebuilt images, see here: -* https://github.com/cypresssemiconductorco/psoc6cm0p -* -* Change the flash and RAM sizes by editing the macros value in the -* linker files for both CPUs: -* - 'xx_cm0plus.ld', where 'xx' is the device group: -* \code -* flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x2000 -* ram (rwx) : ORIGIN = 0x08000000, LENGTH = 0x2000 -* \endcode -* - 'xx_cm4_dual.ld', where 'xx' is the device group: -* \code -* flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x100000 -* ram (rwx) : ORIGIN = 0x08002000, LENGTH = 0x45800 -* \endcode -* -* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the ROM ORIGIN's -* value (0x10000000) + FLASH_CM0P_SIZE value (0x2000, the size of a flash image -* of the Cortex-M0+ application should be the same value as the flash LENGTH in -* 'xx_cm0plus.ld') in the 'xx_cm4_dual.ld' file, where 'xx' is the device group. -* Do this by either: -* - Passing the following commands to the compiler:\n -* \code -D CY_CORTEX_M4_APPL_ADDR=0x10002000 \endcode -* or -* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where -* 'xx' is the device family:\n -* \code #define CY_CORTEX_M4_APPL_ADDR (0x10002000u) \endcode -* -* ARM Compiler\n -* The flash and RAM sections for the CPU are defined in the linker files: -* 'xx_yy.sct', where 'xx' is the device group, and 'yy' is the target CPU; for -* example 'cy8c6xx7_cm0plus.sct' and 'cy8c6xx7_cm4_dual.sct'. -* \note If the start of the Cortex-M4 application image is changed, the value -* of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The -* \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the \ref -* Cy_SysEnableCM4() function call. -* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. -* More about CM0+ prebuilt images, see here: -* https://github.com/cypresssemiconductorco/psoc6cm0p -* -* \note The linker files provided with the PDL are generic and handle all common -* use cases. Your project may not use every section defined in the linker files. -* In that case you may see the warnings during the build process: -* L6314W (no section matches pattern) and/or L6329W -* (pattern only matches removed unused sections). In your project, you can -* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to -* the linker. You can also comment out or remove the relevant code in the linker -* file. -* -* Change the flash and RAM sizes by editing the macros value in the -* linker files for both CPUs: -* - 'xx_cm0plus.sct', where 'xx' is the device group: -* \code -* #define FLASH_START 0x10000000 -* #define FLASH_SIZE 0x00002000 -* #define RAM_START 0x08000000 -* #define RAM_SIZE 0x00002000 -* \endcode -* - 'xx_cm4_dual.sct', where 'xx' is the device group: -* \code -* #define FLASH_START 0x10000000 -* #define FLASH_SIZE 0x00100000 -* #define RAM_START 0x08002000 -* #define RAM_SIZE 0x00045800 -* \endcode -* -* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the FLASH_START -* value (0x10000000) + FLASH_CM0P_SIZE value (0x2000, the size of a flash image -* of the Cortex-M0+ application should be the same value as the FLASH_SIZE in the -* 'xx_cm0plus.sct') in the 'xx_cm4_dual.sct' file, where 'xx' is the device group. -* Do this by either: -* - Passing the following commands to the compiler:\n -* \code -D CY_CORTEX_M4_APPL_ADDR=0x10002000 \endcode -* or -* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where -* 'xx' is the device family:\n -* \code #define CY_CORTEX_M4_APPL_ADDR (0x10002000u) \endcode -* -* IAR\n -* The flash and RAM sections for the CPU are defined in the linker files: -* 'xx_yy.icf', where 'xx' is the device group, and 'yy' is the target CPU; for example, -* 'cy8c6xx7_cm0plus.icf' and 'cy8c6xx7_cm4_dual.icf'. -* \note If the start of the Cortex-M4 application image is changed, the value -* of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The -* \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the \ref -* Cy_SysEnableCM4() function call. -* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. -* More about CM0+ prebuilt images, see here: -* https://github.com/cypresssemiconductorco/psoc6cm0p -* -* Change the flash and RAM sizes by editing the macros value in the -* linker files for both CPUs: -* - 'xx_cm0plus.icf', where 'xx' is the device group: -* \code -* define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000; -* define symbol __ICFEDIT_region_IROM1_end__ = 0x10001FFF; -* define symbol __ICFEDIT_region_IRAM1_start__ = 0x08000000; -* define symbol __ICFEDIT_region_IRAM1_end__ = 0x08001FFF; -* \endcode -* - 'xx_cm4_dual.icf', where 'xx' is the device group: -* \code -* define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000; -* define symbol __ICFEDIT_region_IROM1_end__ = 0x100FFFFF; -* define symbol __ICFEDIT_region_IRAM1_start__ = 0x08002000; -* define symbol __ICFEDIT_region_IRAM1_end__ = 0x080477FF; -* \endcode -* -* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the -* __ICFEDIT_region_IROM1_start__ value (0x10000000) + FLASH_CM0P_SIZE value -* (0x2000, the size of a flash image of the Cortex-M0+ application) in the -* 'xx_cm4_dual.icf' file, where 'xx' is the device group. The sum result -* should be the same as (__ICFEDIT_region_IROM1_end__ + 1) value in the -* 'xx_cm0plus.icf'. Do this by either: -* - Passing the following commands to the compiler:\n -* \code -D CY_CORTEX_M4_APPL_ADDR=0x10002000 \endcode -* or -* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where -* 'xx' is the device family:\n -* \code #define CY_CORTEX_M4_APPL_ADDR (0x10002000u) \endcode -* -* \subsection group_system_config_device_initialization Device Initialization -* After a power-on-reset (POR), the boot process is handled by the boot code -* from the on-chip ROM that is always executed by the Cortex-M0+ core. The boot -* code passes the control to the Cortex-M0+ startup code located in flash. -* -* \subsubsection group_system_config_dual_core_device_initialization Dual-Core Devices -* The Cortex-M0+ startup code performs the device initialization by a call to -* SystemInit() and then calls the main() function. The Cortex-M4 core is disabled -* by default. Enable the core using the \ref Cy_SysEnableCM4() function. -* See \ref group_system_config_cm4_functions for more details. -* \note Startup code executes SystemInit() function for the both Cortex-M0+ and Cortex-M4 cores. -* The function has a separate implementation on each core. -* Both function implementations unlock and disable the WDT. -* Therefore enable the WDT after both cores have been initialized. -* -* \subsubsection group_system_config_single_core_device_initialization Single-Core Devices -* The Cortex-M0+ core is not user-accessible on these devices. In this case the -* Flash Boot handles setup of the CM0+ core and starts the Cortex-M4 core. -* -* \subsection group_system_config_heap_stack_config Heap and Stack Configuration -* There are two ways to adjust heap and stack configurations: -* -# Editing source code files -* -# Specifying via command line -* -* By default, the stack size is set to 0x00001000 and the heap size is allocated -* dynamically to the whole available free memory up to stack memory and it -* is set to the 0x00000400 (for ARM GCC and IAR compilers) as minimal value. -* -* \subsubsection group_system_config_heap_stack_config_gcc ARM GCC -* - Editing source code files\n -* The heap and stack sizes are defined in the assembler startup files -* (e.g. startup_psoc6_01_cm0plus.S and startup_psoc6_01_cm4.S). -* Change the heap and stack sizes by modifying the following lines:\n -* \code .equ Stack_Size, 0x00001000 \endcode -* \code .equ Heap_Size, 0x00000400 \endcode -* Also, the stack size is defined in the linker script files: 'xx_yy.ld', -* where 'xx' is the device family, and 'yy' is the target CPU; for example, -* cy8c6xx7_cm0plus.ld and cy8c6xx7_cm4_dual.ld. -* Change the stack size by modifying the following line:\n -* \code STACK_SIZE = 0x1000; \endcode -* -* \subsubsection group_system_config_heap_stack_config_mdk ARM Compiler -* - Editing source code files\n -* The stack size is defined in the linker script files: 'xx_yy.sct', -* where 'xx' is the device family, and 'yy' is the target CPU; for example, -* cy8c6xx7_cm0plus.sct and cy8c6xx7_cm4_dual.sct. -* Change the stack size by modifying the following line:\n -* \code STACK_SIZE = 0x1000; \endcode -* -* \subsubsection group_system_config_heap_stack_config_iar IAR -* - Editing source code files\n -* The heap and stack sizes are defined in the linker script files: 'xx_yy.icf', -* where 'xx' is the device family, and 'yy' is the target CPU; for example, -* cy8c6xx7_cm0plus.icf and cy8c6xx7_cm4_dual.icf. -* Change the heap and stack sizes by modifying the following lines:\n -* \code Stack_Size EQU 0x00001000 \endcode -* \code Heap_Size EQU 0x00000400 \endcode -* -* - Specifying via command line\n -* Change the heap and stack sizes passing the following commands to the -* linker (including quotation marks):\n -* \code --define_symbol __STACK_SIZE=0x000000400 \endcode -* \code --define_symbol __HEAP_SIZE=0x000000100 \endcode -* -* \subsection group_system_config_default_handlers Default Interrupt Handlers Definition -* The default interrupt handler functions are defined as weak functions to a dummy -* handler in the startup file. The naming convention for the interrupt handler names -* is \_IRQHandler. A default interrupt handler can be overwritten in -* user code by defining the handler function using the same name. For example: -* \code -* void scb_0_interrupt_IRQHandler(void) -*{ -* ... -*} -* \endcode -* -* \subsection group_system_config_device_vector_table Vectors Table Copy from Flash to RAM -* This process uses memory sections defined in the linker script. The startup -* code actually defines the contents of the vector table and performs the copy. -* \subsubsection group_system_config_device_vector_table_gcc ARM GCC -* The linker script file is 'xx_yy.ld', where 'xx' is the device family, and -* 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.ld and cy8c6xx7_cm4_dual.ld. -* It defines sections and locations in memory.\n -* Copy interrupt vectors from flash to RAM: \n -* From: \code LONG (__Vectors) \endcode -* To: \code LONG (__ram_vectors_start__) \endcode -* Size: \code LONG (__Vectors_End - __Vectors) \endcode -* The vector table address (and the vector table itself) are defined in the -* assembler startup files (e.g. startup_psoc6_01_cm0plus.S and startup_psoc6_01_cm4.S). -* The code in these files copies the vector table from Flash to RAM. -* \subsubsection group_system_config_device_vector_table_mdk ARM Compiler -* The linker script file is 'xx_yy.sct', where 'xx' is the device family, -* and 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.sct and -* cy8c6xx7_cm4_dual.sct. The linker script specifies that the vector table -* (RESET_RAM) shall be first in the RAM section.\n -* RESET_RAM represents the vector table. It is defined in the assembler startup -* files (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s). -* The code in these files copies the vector table from Flash to RAM. -* -* \subsubsection group_system_config_device_vector_table_iar IAR -* The linker script file is 'xx_yy.icf', where 'xx' is the device family, and -* 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.icf and cy8c6xx7_cm4_dual.icf. -* This file defines the .intvec_ram section and its location. -* \code place at start of IRAM1_region { readwrite section .intvec_ram}; \endcode -* The vector table address (and the vector table itself) are defined in the -* assembler startup files (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s). -* The code in these files copies the vector table from Flash to RAM. -* -* \section group_system_config_MISRA MISRA Compliance -* -* -* -* -* -* -* -* -* -* -* -* -* -* -*
MISRA RuleRule Class (Required/Advisory)Rule DescriptionDescription of Deviation(s)
2.3RThe character sequence // shall not be used within a comment.The comments provide a useful WEB link to the documentation.
-* -* \section group_system_config_changelog Changelog -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -*
VersionChangesReason for Change
2.70.1Updated documentation for the better description of the existing startup implementation.User experience enhancement.
2.70Updated \ref SystemCoreClockUpdate() implementation - The SysClk API is reused.Code optimization.
Updated \ref SystemInit() implementation - The IPC7 structure is initialized for both cores.Provided support for SysPM driver updates.
Updated the linker scripts.Reserved FLASH area for the MCU boot headers.
Added System Pipe initialization for all devices. Improved PDL usability according to user experience.
Removed redundant legacy macros: CY_CLK_EXT_FREQ_HZ, CY_CLK_ECO_FREQ_HZ and CY_CLK_ALTHF_FREQ_HZ. -* Use \ref Cy_SysClk_ExtClkSetFrequency, \ref Cy_SysClk_EcoConfigure and \ref Cy_BLE_EcoConfigure functions instead them. Defect fixing.
2.60Updated linker scripts.Provided support for new devices, updated usage of CM0p prebuilt image.
2.50Updated assembler files, C files, linker scripts.Dynamic allocated HEAP size for Arm Compiler 6, IAR 8.
2.40Updated assembler files, C files, linker scripts.Added Arm Compiler 6 support.
2.30Added assembler files, linker scripts for Mbed OS.Added Arm Mbed OS embedded operating system support.
Updated linker scripts to extend the Flash and Ram memories size available for the CM4 core.Enhanced PDL usability.
2.20Moved the Cy_IPC_SystemSemaInit(), Cy_IPC_SystemPipeInit() functions implementation from IPC to Startup.Changed the IPC driver configuration method from compile time to run time.
2.10Added constructor attribute to SystemInit() function declaration for ARM MDK compiler. \n -* Removed $Sub$$main symbol for ARM MDK compiler. -* uVision Debugger support.
Updated description of the Startup behavior for Single-Core Devices. \n -* Added note about WDT disabling by SystemInit() function. -* Documentation improvement.
2.0Added restoring of FLL registers to the default state in SystemInit() API for single core devices. -* Single core device support. -*
Added Normal Access Restrictions, Public Key, TOC part2 and TOC part2 copy to Supervisory flash linker memory regions. \n -* Renamed 'wflash' memory region to 'em_eeprom'. -* Linker scripts usability improvement.
Added Cy_IPC_SystemSemaInit(), Cy_IPC_SystemPipeInit(), Cy_Flash_Init() functions call to SystemInit() API.Reserved system resources for internal operations.
Added clearing and releasing of IPC structure #7 (reserved for the Deep-Sleep operations) to SystemInit() API.To avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering.
1.0Initial version
-* -* -* \defgroup group_system_config_macro Macro -* \{ -* \defgroup group_system_config_system_macro System -* \defgroup group_system_config_cm4_status_macro Cortex-M4 Status -* \defgroup group_system_config_user_settings_macro User Settings -* \} -* \defgroup group_system_config_functions Functions -* \{ -* \defgroup group_system_config_system_functions System -* \defgroup group_system_config_cm4_functions Cortex-M4 Control -* \} -* \defgroup group_system_config_globals Global Variables -* -* \} -*/ - -/** -* \addtogroup group_system_config_system_functions -* \{ -* \details -* The following system functions implement CMSIS Core functions. -* Refer to the [CMSIS documentation] -* (http://www.keil.com/pack/doc/CMSIS/Core/html/group__system__init__gr.html "System and Clock Configuration") -* for more details. -* \} -*/ - -#ifdef __cplusplus -extern "C" { -#endif - - -/******************************************************************************* -* Include files -*******************************************************************************/ -#include - - -/******************************************************************************* -* Global preprocessor symbols/macros ('define') -*******************************************************************************/ -#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ - (defined (__ICCARM__) && (__CORE__ == __ARM6M__)) || \ - (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3))) - #define CY_SYSTEM_CPU_CM0P 1UL -#else - #define CY_SYSTEM_CPU_CM0P 0UL -#endif - - -/******************************************************************************* -* -* START OF USER SETTINGS HERE -* =========================== -* -* All lines with '<<<' can be set by user. -* -*******************************************************************************/ - -/** -* \addtogroup group_system_config_user_settings_macro -* \{ -*/ - - -/***************************************************************************//** -* \brief Start address of the Cortex-M4 application ([address]UL) -* (USER SETTING) -*******************************************************************************/ -#if !defined (CY_CORTEX_M4_APPL_ADDR) - #define CY_CORTEX_M4_APPL_ADDR (CY_FLASH_BASE + 0x2000U) /* <<< 8 kB of flash is reserved for the Cortex-M0+ application */ -#endif /* (CY_CORTEX_M4_APPL_ADDR) */ - - -/***************************************************************************//** -* \brief IPC Semaphores allocation ([value]UL). -* (USER SETTING) -*******************************************************************************/ -#define CY_IPC_SEMA_COUNT (128UL) /* <<< This will allow 128 (4*32) semaphores */ - - -/***************************************************************************//** -* \brief IPC Pipe definitions ([value]UL). -* (USER SETTING) -*******************************************************************************/ -#define CY_IPC_MAX_ENDPOINTS (8UL) /* <<< 8 endpoints */ - - -/******************************************************************************* -* -* END OF USER SETTINGS HERE -* ========================= -* -*******************************************************************************/ - -/** \} group_system_config_user_settings_macro */ - - -/** -* \addtogroup group_system_config_system_macro -* \{ -*/ - -#if (CY_SYSTEM_CPU_CM0P == 1UL) || defined(CY_DOXYGEN) - /** The Cortex-M0+ startup driver identifier */ - #define CY_STARTUP_M0P_ID ((uint32_t)((uint32_t)((0x0EU) & 0x3FFFU) << 18U)) -#endif /* (CY_SYSTEM_CPU_CM0P == 1UL) */ - -#if (CY_SYSTEM_CPU_CM0P != 1UL) || defined(CY_DOXYGEN) - /** The Cortex-M4 startup driver identifier */ - #define CY_STARTUP_M4_ID ((uint32_t)((uint32_t)((0x0FU) & 0x3FFFU) << 18U)) -#endif /* (CY_SYSTEM_CPU_CM0P != 1UL) */ - -/** \} group_system_config_system_macro */ - - -/** -* \addtogroup group_system_config_system_functions -* \{ -*/ -extern void SystemInit(void); - -extern void SystemCoreClockUpdate(void); -/** \} group_system_config_system_functions */ - - -/** -* \addtogroup group_system_config_cm4_functions -* \{ -*/ -extern uint32_t Cy_SysGetCM4Status(void); -extern void Cy_SysEnableCM4(uint32_t vectorTableOffset); -extern void Cy_SysDisableCM4(void); -extern void Cy_SysRetainCM4(void); -extern void Cy_SysResetCM4(void); -/** \} group_system_config_cm4_functions */ - - -/** \cond */ -extern void Default_Handler (void); - -void Cy_SysIpcPipeIsrCm0(void); -void Cy_SysIpcPipeIsrCm4(void); - -extern void Cy_SystemInit(void); -extern void Cy_SystemInitFpuEnable(void); - -extern uint32_t cy_delayFreqKhz; -extern uint8_t cy_delayFreqMhz; -extern uint32_t cy_delay32kMs; -/** \endcond */ - - -#if (CY_SYSTEM_CPU_CM0P == 1UL) || defined(CY_DOXYGEN) -/** -* \addtogroup group_system_config_cm4_status_macro -* \{ -*/ -#define CY_SYS_CM4_STATUS_ENABLED (3U) /**< The Cortex-M4 core is enabled: power on, clock on, no isolate, no reset and no retain. */ -#define CY_SYS_CM4_STATUS_DISABLED (0U) /**< The Cortex-M4 core is disabled: power off, clock off, isolate, reset and no retain. */ -#define CY_SYS_CM4_STATUS_RETAINED (2U) /**< The Cortex-M4 core is retained. power off, clock off, isolate, no reset and retain. */ -#define CY_SYS_CM4_STATUS_RESET (1U) /**< The Cortex-M4 core is in the Reset mode: clock off, no isolated, no retain and reset. */ -/** \} group_system_config_cm4_status_macro */ - -#endif /* (CY_SYSTEM_CPU_CM0P == 1UL) */ - - -/******************************************************************************* -* IPC Configuration -* ========================= -*******************************************************************************/ -/* IPC CY_PIPE default configuration */ -#define CY_SYS_CYPIPE_CLIENT_CNT (8UL) - -#define CY_SYS_INTR_CYPIPE_MUX_EP0 (1UL) /* IPC CYPRESS PIPE */ -#define CY_SYS_INTR_CYPIPE_PRIOR_EP0 (1UL) /* Notifier Priority */ -#define CY_SYS_INTR_CYPIPE_PRIOR_EP1 (1UL) /* Notifier Priority */ - -#define CY_SYS_CYPIPE_CHAN_MASK_EP0 (0x0001UL << CY_IPC_CHAN_CYPIPE_EP0) -#define CY_SYS_CYPIPE_CHAN_MASK_EP1 (0x0001UL << CY_IPC_CHAN_CYPIPE_EP1) - - -/******************************************************************************/ -/* - * The System pipe configuration defines the IPC channel number, interrupt - * number, and the pipe interrupt mask for the endpoint. - * - * The format of the endPoint configuration - * Bits[31:16] Interrupt Mask - * Bits[15:8 ] IPC interrupt - * Bits[ 7:0 ] IPC channel - */ - -/* System Pipe addresses */ -/* CyPipe defines */ - -#define CY_SYS_CYPIPE_INTR_MASK ( CY_SYS_CYPIPE_CHAN_MASK_EP0 | CY_SYS_CYPIPE_CHAN_MASK_EP1 ) - -#define CY_SYS_CYPIPE_CONFIG_EP0 ( (CY_SYS_CYPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \ - | (CY_IPC_INTR_CYPIPE_EP0 << CY_IPC_PIPE_CFG_INTR_Pos) \ - | CY_IPC_CHAN_CYPIPE_EP0) -#define CY_SYS_CYPIPE_CONFIG_EP1 ( (CY_SYS_CYPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \ - | (CY_IPC_INTR_CYPIPE_EP1 << CY_IPC_PIPE_CFG_INTR_Pos) \ - | CY_IPC_CHAN_CYPIPE_EP1) - -/******************************************************************************/ - - -/** \addtogroup group_system_config_globals -* \{ -*/ - -extern uint32_t SystemCoreClock; -extern uint32_t cy_BleEcoClockFreqHz; -extern uint32_t cy_Hfclk0FreqHz; -extern uint32_t cy_PeriClkFreqHz; - -/** \} group_system_config_globals */ - - - -/** \cond INTERNAL */ -/******************************************************************************* -* Backward compatibility macros. The following code is DEPRECATED and must -* not be used in new projects -*******************************************************************************/ - -/* BWC defines for functions related to enter/exit critical section */ -#define Cy_SaveIRQ Cy_SysLib_EnterCriticalSection -#define Cy_RestoreIRQ Cy_SysLib_ExitCriticalSection -#define CY_SYS_INTR_CYPIPE_EP0 (CY_IPC_INTR_CYPIPE_EP0) -#define CY_SYS_INTR_CYPIPE_EP1 (CY_IPC_INTR_CYPIPE_EP1) -#define cy_delayFreqHz (SystemCoreClock) - -/** \endcond */ - -#ifdef __cplusplus -} -#endif - -#endif /* _SYSTEM_PSOC6_H_ */ - - -/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/partition/flash_layout.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/partition/flash_layout.h deleted file mode 100644 index a1a0406675..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/partition/flash_layout.h +++ /dev/null @@ -1,185 +0,0 @@ -/* - * Copyright (c) 2017-2019 Arm Limited. All rights reserved. - * Copyright (c) 2019, Cypress Semiconductor Corporation. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __FLASH_LAYOUT_H__ -#define __FLASH_LAYOUT_H__ - -/* Flash layout with BL2: - * - * Not supported - * - * Flash layout if BL2 not defined: - * - * 0x1000_0000 Secure image primary (320 KB) - * 0x1005_0000 Non-secure image primary (1152 KB) - * 0x1017_0000 Secure image secondary (320 KB) - * 0x101c_0000 - 0x101f_ffff Reserved - * 0x101c_0000 Secure Storage Area (20 KB) - * 0x101c_5000 Internal Trusted Storage Area (16 KB) - * 0x101c_9000 NV counters area (512 Bytes) - * 0x101c_9200 Scratch area (27.5 KB) - * 0x101d_0000 Reserved (192 KB) - * 0x101f_ffff End of Flash - * - */ - -#define MAX(X, Y) (((X) > (Y)) ? (X) : (Y)) - -/* This header file is included from linker scatter file as well, where only a - * limited C constructs are allowed. Therefore it is not possible to include - * here the platform_base_address.h to access flash related defines. To resolve - * this some of the values are redefined here with different names, these are - * marked with comment. - */ - -/* The size of S partition */ -#define FLASH_S_PARTITION_SIZE 0x50000 /* 320 KB */ -/* The size of NS partition */ -#define FLASH_NS_PARTITION_SIZE 0x120000 /* 1152 KB */ - -/* Sector size of the flash hardware; same as FLASH0_SECTOR_SIZE */ -#define FLASH_AREA_IMAGE_SECTOR_SIZE (0x200) /* 512 B */ -/* Same as FLASH0_SIZE */ -#define FLASH_TOTAL_SIZE (0x00200000) /* 2 MB */ - -/* Flash layout info for BL2 bootloader */ -#define FLASH_BASE_ADDRESS (0x10000000U) /* same as FLASH0_BASE */ - -/* Reserved areas */ -#define FLASH_RESERVED_AREA_OFFSET (SECURE_IMAGE_OFFSET + \ - 2*SECURE_IMAGE_MAX_SIZE + \ - NON_SECURE_IMAGE_MAX_SIZE) - -/* FixMe: implement proper mcuboot partitioning for CYBL */ - -/* Reserved for Secure Storage Area */ -#define FLASH_SST_AREA_OFFSET (FLASH_RESERVED_AREA_OFFSET) -#define FLASH_SST_AREA_SIZE (0x5000) /* 20 KB */ - -/* Internal Trusted Storage Area */ -#define FLASH_ITS_AREA_OFFSET (FLASH_SST_AREA_OFFSET + \ - FLASH_SST_AREA_SIZE) -#define FLASH_ITS_AREA_SIZE (0x4000) /* 16 KB */ - -#define FLASH_NV_COUNTERS_AREA_OFFSET (FLASH_ITS_AREA_OFFSET + \ - FLASH_ITS_AREA_SIZE) -#define FLASH_NV_COUNTERS_AREA_SIZE (FLASH_AREA_IMAGE_SECTOR_SIZE) - -#ifdef BL2 -#error "BL2 configuration is not supported" -#else /* BL2 */ - -#define FLASH_AREA_SCRATCH_OFFSET (FLASH_NV_COUNTERS_AREA_OFFSET + \ - FLASH_NV_COUNTERS_AREA_SIZE) -#define FLASH_AREA_SCRATCH_SIZE (0x6e00) /* 27.5 KB */ -#endif /* BL2 */ - -#define FLASH_AREA_SYSTEM_RESERVED_SIZE (0x30000) /* 192 KB */ - - -/* Secure and non-secure images definition in flash area */ - -#define SECURE_IMAGE_OFFSET 0x0 - -#define SECURE_IMAGE_MAX_SIZE FLASH_S_PARTITION_SIZE - -#define NON_SECURE_IMAGE_OFFSET (SECURE_IMAGE_OFFSET + \ - SECURE_IMAGE_MAX_SIZE) - -#define NON_SECURE_IMAGE_MAX_SIZE FLASH_NS_PARTITION_SIZE - -/* Check if it fits into available Flash*/ - -#define FLASH_RESERVED_AREA_SIZE (FLASH_SST_AREA_SIZE + \ - FLASH_ITS_AREA_SIZE + \ - FLASH_NV_COUNTERS_AREA_SIZE + \ - FLASH_AREA_SCRATCH_SIZE + \ - FLASH_AREA_SYSTEM_RESERVED_SIZE) - -#if (FLASH_RESERVED_AREA_OFFSET + FLASH_RESERVED_AREA_SIZE) > (FLASH_TOTAL_SIZE) -#error "Out of Flash memory" -#endif - -/* Flash device name used by BL2 and SST - * Name is defined in flash driver file: Driver_Flash.c - */ -#define FLASH_DEV_NAME Driver_FLASH0 - -/* Secure Storage (SST) Service definitions - * Note: Further documentation of these definitions can be found in the - * TF-M SST Integration Guide. - */ -#define SST_FLASH_DEV_NAME Driver_FLASH0 - -/* In this target the CMSIS driver requires only the offset from the base - * address instead of the full memory address. - */ -#define SST_FLASH_AREA_ADDR FLASH_SST_AREA_OFFSET -/* Dedicated flash area for SST */ -#define SST_FLASH_AREA_SIZE FLASH_SST_AREA_SIZE -#define SST_SECTOR_SIZE FLASH_AREA_IMAGE_SECTOR_SIZE -/* Number of SST_SECTOR_SIZE per block */ -#define SST_SECTORS_PER_BLOCK 0x8 -/* Specifies the smallest flash programmable unit in bytes */ -#define SST_FLASH_PROGRAM_UNIT 0x1 -/* The maximum asset size to be stored in the SST area */ -#define SST_MAX_ASSET_SIZE 2048 -/* The maximum number of assets to be stored in the SST area */ -#define SST_NUM_ASSETS 10 - -/* Internal Trusted Storage (ITS) Service definitions - * Note: Further documentation of these definitions can be found in the - * TF-M ITS Integration Guide. The ITS should be in the internal flash, but is - * allocated in the external flash just for development platforms that don't - * have internal flash available. - */ -#define ITS_FLASH_DEV_NAME Driver_FLASH0 - -/* In this target the CMSIS driver requires only the offset from the base - * address instead of the full memory address. - */ -#define ITS_FLASH_AREA_ADDR FLASH_ITS_AREA_OFFSET -/* Dedicated flash area for ITS */ -#define ITS_FLASH_AREA_SIZE FLASH_ITS_AREA_SIZE -#define ITS_SECTOR_SIZE FLASH_AREA_IMAGE_SECTOR_SIZE -/* Number of ITS_SECTOR_SIZE per block */ -#define ITS_SECTORS_PER_BLOCK (0x8) -/* Specifies the smallest flash programmable unit in bytes */ -#define ITS_FLASH_PROGRAM_UNIT (0x1) -/* The maximum asset size to be stored in the ITS area */ -#define ITS_MAX_ASSET_SIZE (512) -/* The maximum number of assets to be stored in the ITS area */ -#define ITS_NUM_ASSETS (10) - -/* NV Counters definitions */ -#define TFM_NV_COUNTERS_AREA_ADDR FLASH_NV_COUNTERS_AREA_OFFSET -#define TFM_NV_COUNTERS_AREA_SIZE FLASH_NV_COUNTERS_AREA_SIZE -#define TFM_NV_COUNTERS_SECTOR_ADDR FLASH_NV_COUNTERS_AREA_OFFSET -#define TFM_NV_COUNTERS_SECTOR_SIZE MAX(FLASH_NV_COUNTERS_AREA_SIZE, \ - FLASH_AREA_IMAGE_SECTOR_SIZE) - -/* Use Flash to store Code data */ -#define S_ROM_ALIAS_BASE (0x10000000) -#define NS_ROM_ALIAS_BASE (0x10000000) - -/* Use SRAM to store RW data */ -#define S_RAM_ALIAS_BASE (0x08000000) -#define NS_RAM_ALIAS_BASE (0x08000000) - -#endif /* __FLASH_LAYOUT_H__ */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/partition/region_defs.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/partition/region_defs.h deleted file mode 100644 index d77f493327..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/partition/region_defs.h +++ /dev/null @@ -1,197 +0,0 @@ -/* - * Copyright (c) 2017-2019 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __REGION_DEFS_H__ -#define __REGION_DEFS_H__ - -#include "flash_layout.h" - -#define TOTAL_ROM_SIZE FLASH_TOTAL_SIZE -/* 2KB of RAM (at the end of the SRAM) are reserved for system use. Using - * this memory region for other purposes will lead to unexpected behavior. - * 94KB of RAM (just before the memory reserved for system use) are - * allocated and protected by Cypress Bootloader */ -/* FixMe: confirm exact available amount of RAM based on the actual - system allocation */ -#define TOTAL_RAM_SIZE (0x000E8000) /* CY_SRAM_SIZE - 96KB */ - -#define BL2_HEAP_SIZE 0x0001000 -#define BL2_MSP_STACK_SIZE 0x0001000 - -#define S_HEAP_SIZE 0x0001000 -#define S_MSP_STACK_SIZE_INIT 0x0000400 -#define S_MSP_STACK_SIZE 0x0000800 -#define S_PSP_STACK_SIZE 0x0000800 - -#define NS_HEAP_SIZE 0x0001000 -#define NS_MSP_STACK_SIZE 0x0000400 -#define NS_PSP_STACK_SIZE 0x0000C00 - -/* Relocation of vectors to RAM support */ -/* #define RAM_VECTORS_SUPPORT */ - -/* - * This size of buffer is big enough to store an attestation - * token produced by initial attestation service - */ -#define PSA_INITIAL_ATTEST_TOKEN_MAX_SIZE 0x250 - -/* - * MPC granularity is 128 KB on AN519 MPS2 FPGA image. Alignment - * of partitions is defined in accordance with this constraint. - */ - -#ifdef BL2 -#error "BL2 configuration is not supported" -#else -#define S_IMAGE_PRIMARY_PARTITION_OFFSET SECURE_IMAGE_OFFSET -#define NS_IMAGE_PRIMARY_PARTITION_OFFSET NON_SECURE_IMAGE_OFFSET -#endif /* BL2 */ - -/* TFM PSoC6 CY8CKIT_064 RAM layout: - * - * 0x0800_0000 - 0x0802_FFFF Secure (192KB) - * 0x0800_0000 - 0x0800_FFFF Secure unprivileged data (S_UNPRIV_DATA_SIZE, 64KB) - * 0x0801_0000 - 0x0802_EFFF Secure priviliged data (S_PRIV_DATA_SIZE, 124KB) - * 0x0802_F000 - 0x0802_FFFF Secure priv code executable from RAM (S_RAM_CODE_SIZE, 4KB) - * - * 0x0803_0000 - 0x080E_7FFF Non-secure (736KB) - * 0x0803_0000 - 0x080E_6FFF Non-secure OS/App (732KB) - * 0x080E_7000 - 0x080E_7FFF Shared memory (NS_DATA_SHARED_SIZE, 4KB) - * 0x080E_8000 - 0x080F_FFFF System reserved memory (96KB) - * 0x0810_0000 End of RAM - */ - -/* - * Boot partition structure if MCUBoot is used: - * 0x0_0000 Bootloader header - * 0x0_0400 Image area - * 0x1_FC00 Trailer - */ -/* Image code size is the space available for the software binary image. - * It is less than the FLASH_S_PARTITION_SIZE and FLASH_NS_PARTITION_SIZE - * because we reserve space for the image header and trailer introduced by the - * bootloader. - */ -#ifdef BL2 -#error "BL2 configuration is not supported" -#else -/* Even though TFM BL2 is excluded from the build, - * CY BL built externally is used and it needs offsets for header and trailer - * to be taken in account. - * */ -#define BL2_HEADER_SIZE (0x400) -#define BL2_TRAILER_SIZE (0x400) - -#endif /* BL2 */ - -#define IMAGE_S_CODE_SIZE \ - (FLASH_S_PARTITION_SIZE - BL2_HEADER_SIZE - BL2_TRAILER_SIZE) -#define IMAGE_NS_CODE_SIZE \ - (FLASH_NS_PARTITION_SIZE - BL2_HEADER_SIZE - BL2_TRAILER_SIZE) - -/* Alias definitions for secure and non-secure areas*/ -#define S_ROM_ALIAS(x) (S_ROM_ALIAS_BASE + (x)) -#define NS_ROM_ALIAS(x) (NS_ROM_ALIAS_BASE + (x)) - -#define S_RAM_ALIAS(x) (S_RAM_ALIAS_BASE + (x)) -#define NS_RAM_ALIAS(x) (NS_RAM_ALIAS_BASE + (x)) - -/* Secure regions */ -#define S_IMAGE_PRIMARY_AREA_OFFSET \ - (S_IMAGE_PRIMARY_PARTITION_OFFSET + BL2_HEADER_SIZE) -#define S_CODE_START (S_ROM_ALIAS(S_IMAGE_PRIMARY_AREA_OFFSET)) -#define S_CODE_SIZE IMAGE_S_CODE_SIZE -#define S_CODE_LIMIT (S_CODE_START + S_CODE_SIZE - 1) - -#define S_DATA_START (S_RAM_ALIAS(0)) -#define S_UNPRIV_DATA_SIZE 0x10000 -#define S_PRIV_DATA_SIZE 0x1F000 -/* Reserve 4KB for RAM-based executable code */ -#define S_RAM_CODE_SIZE 0x1000 - -/* Secure data area */ -#define S_DATA_SIZE (S_UNPRIV_DATA_SIZE + S_PRIV_DATA_SIZE + S_RAM_CODE_SIZE) -#define S_DATA_LIMIT (S_DATA_START + S_DATA_SIZE - 1) - -/* We need the privileged data area to be aligned so that an SMPU - * region can cover it. - */ -/* TODO It would be nice to figure this out automatically. - * In theory, in the linker script, we could determine the amount - * of secure data space available after all the unprivileged data, - * round that down to a power of 2 to get the actual size we want - * to use for privileged data, and then determine this value from - * that. We'd also potentially have to update the configs for SMPU9 - * and SMPU10. - * Leave the SMPU alignment check in SMPU configuration file. - */ -#define S_DATA_UNPRIV_OFFSET (0) -#define S_DATA_UNPRIV_START S_RAM_ALIAS(S_DATA_UNPRIV_OFFSET) - -#define S_DATA_PRIV_OFFSET (S_DATA_UNPRIV_OFFSET + S_UNPRIV_DATA_SIZE) -#define S_DATA_PRIV_START S_RAM_ALIAS(S_DATA_PRIV_OFFSET) - -/* Reserve area for RAM-based executable code right after secure unprivilaged - * and privilaged data areas*/ -#define S_RAM_CODE_OFFSET (S_DATA_PRIV_OFFSET + S_PRIV_DATA_SIZE) -#define S_RAM_CODE_START S_RAM_ALIAS(S_RAM_CODE_OFFSET) - -/* Non-secure regions */ -#define NS_IMAGE_PRIMARY_AREA_OFFSET \ - (NS_IMAGE_PRIMARY_PARTITION_OFFSET + BL2_HEADER_SIZE) -#define NS_CODE_START (NS_ROM_ALIAS(NS_IMAGE_PRIMARY_AREA_OFFSET)) -#define NS_CODE_SIZE IMAGE_NS_CODE_SIZE -#define NS_CODE_LIMIT (NS_CODE_START + NS_CODE_SIZE - 1) - -#define NS_DATA_START (S_RAM_ALIAS(S_DATA_SIZE)) -#define NS_DATA_SIZE (TOTAL_RAM_SIZE - S_DATA_SIZE) -#define NS_DATA_LIMIT (NS_DATA_START + NS_DATA_SIZE - 1) - -/* Shared memory */ -#define NS_DATA_SHARED_SIZE 0x1000 -#define NS_DATA_SHARED_START (NS_DATA_START + NS_DATA_SIZE - \ - NS_DATA_SHARED_SIZE) -#define NS_DATA_SHARED_LIMIT (NS_DATA_SHARED_START + NS_DATA_SHARED_SIZE - 1) - -/* Shared variables addresses */ -/* ipcWaitMessageStc, cy_flash.c */ -#define IPC_WAIT_MESSAGE_STC_SIZE 4 -#define IPC_WAIT_MESSAGE_STC_ADDR (NS_DATA_SHARED_START + \ - NS_DATA_SHARED_SIZE - \ - IPC_WAIT_MESSAGE_STC_SIZE) - -/* NS partition information is used for MPC and SAU configuration */ -#define NS_PARTITION_START \ - (NS_ROM_ALIAS(NS_IMAGE_PRIMARY_PARTITION_OFFSET)) - -#define NS_PARTITION_SIZE (FLASH_NS_PARTITION_SIZE) - -#ifdef BL2 -#error "BL2 configuration is not supported" -#endif /* BL2 */ - -/* Shared data area between bootloader and runtime firmware. - * Shared data area is allocated at the beginning of the privileged data area, - * it is overlapping with TF-M Secure code's MSP stack - */ -#define BOOT_TFM_SHARED_DATA_BASE (S_RAM_ALIAS(S_DATA_PRIV_OFFSET)) -#define BOOT_TFM_SHARED_DATA_SIZE 0x400 - -#endif /* __REGION_DEFS_H__ */ - diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/secure_image_parameters.json b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/secure_image_parameters.json deleted file mode 100644 index bae6642e49..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/secure_image_parameters.json +++ /dev/null @@ -1,17 +0,0 @@ -{ - "boot0" : { - "VERSION" : "0.1", - "ROLLBACK_COUNTER" : "0" - }, - - "boot1" : { - "VERSION" : "0.1", - "ROLLBACK_COUNTER" : "0" - }, - - "sdk_path" : "targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/", - "priv_key_file": "keys/USERAPP_CM4_KEY_PRIV.pem", - "aes_key_file": "keys/image-aes-128.key", - "dev_pub_key_file": "keys/dev_pub_key.pem", - "policy_file": "policy/policy_single_stage_CM4_2m.json" -} diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c deleted file mode 100644 index a6b6f0024c..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c +++ /dev/null @@ -1,34 +0,0 @@ -/******************************************************************************* -* File Name: cycfg.c -* -* Description: -* Wrapper function to initialize all generated code. -* This file was automatically generated and should not be modified. -* Device Configurator: 2.0.0.1483 -* Device Support Library (libs/psoc6pdl): 1.4.1.2240 -* -******************************************************************************** -* Copyright 2017-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -********************************************************************************/ - -#include "cycfg.h" - -void init_cycfg_all(void) -{ - init_cycfg_system(); - init_cycfg_routing(); - init_cycfg_pins(); -} diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h deleted file mode 100644 index 922d15d422..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h +++ /dev/null @@ -1,47 +0,0 @@ -/******************************************************************************* -* File Name: cycfg.h -* -* Description: -* Simple wrapper header containing all generated files. -* This file was automatically generated and should not be modified. -* Device Configurator: 2.0.0.1483 -* Device Support Library (libs/psoc6pdl): 1.4.1.2240 -* -******************************************************************************** -* Copyright 2017-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -********************************************************************************/ - -#if !defined(CYCFG_H) -#define CYCFG_H - -#if defined(__cplusplus) -extern "C" { -#endif - -#include "cycfg_notices.h" -#include "cycfg_system.h" -#include "cycfg_routing.h" -#include "cycfg_pins.h" - -void init_cycfg_all(void); - - -#if defined(__cplusplus) -} -#endif - - -#endif /* CYCFG_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c deleted file mode 100644 index 6a7bdfc535..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c +++ /dev/null @@ -1,235 +0,0 @@ -/******************************************************************************* -* File Name: cycfg_pins.c -* -* Description: -* Pin configuration -* This file was automatically generated and should not be modified. -* Device Configurator: 2.0.0.1483 -* Device Support Library (libs/psoc6pdl): 1.4.1.2240 -* -******************************************************************************** -* Copyright 2017-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -********************************************************************************/ - -#include "cycfg_pins.h" - -const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_ANALOG, - .hsiom = CYBSP_WCO_IN_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_WCO_IN_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_WCO_IN_PORT_NUM, - .channel_num = CYBSP_WCO_IN_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_ANALOG, - .hsiom = CYBSP_WCO_OUT_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_WCO_OUT_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_WCO_OUT_PORT_NUM, - .channel_num = CYBSP_WCO_OUT_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_ECO_IN_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_ANALOG, - .hsiom = CYBSP_ECO_IN_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_ECO_IN_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_ECO_IN_PORT_NUM, - .channel_num = CYBSP_ECO_IN_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_ECO_OUT_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_ANALOG, - .hsiom = CYBSP_ECO_OUT_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_ECO_OUT_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_ECO_OUT_PORT_NUM, - .channel_num = CYBSP_ECO_OUT_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_SWO_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_STRONG_IN_OFF, - .hsiom = CYBSP_SWO_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_SWO_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_SWO_PORT_NUM, - .channel_num = CYBSP_SWO_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_PULLUP, - .hsiom = CYBSP_SWDIO_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_SWDIO_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_SWDIO_PORT_NUM, - .channel_num = CYBSP_SWDIO_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_SWCLK_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_PULLDOWN, - .hsiom = CYBSP_SWCLK_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_SWCLK_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_SWCLK_PORT_NUM, - .channel_num = CYBSP_SWCLK_PIN, - }; -#endif //defined (CY_USING_HAL) - - -void init_cycfg_pins(void) -{ - Cy_GPIO_Pin_Init(CYBSP_WCO_IN_PORT, CYBSP_WCO_IN_PIN, &CYBSP_WCO_IN_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_WCO_IN_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_WCO_OUT_PORT, CYBSP_WCO_OUT_PIN, &CYBSP_WCO_OUT_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_WCO_OUT_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_ECO_IN_PORT, CYBSP_ECO_IN_PIN, &CYBSP_ECO_IN_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_ECO_IN_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_ECO_OUT_PORT, CYBSP_ECO_OUT_PIN, &CYBSP_ECO_OUT_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_ECO_OUT_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_SWO_PORT, CYBSP_SWO_PIN, &CYBSP_SWO_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_SWO_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_SWDIO_PORT, CYBSP_SWDIO_PIN, &CYBSP_SWDIO_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_SWDIO_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_SWCLK_PORT, CYBSP_SWCLK_PIN, &CYBSP_SWCLK_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_SWCLK_obj); -#endif //defined (CY_USING_HAL) -} diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h deleted file mode 100644 index 9deaeb62ca..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h +++ /dev/null @@ -1,246 +0,0 @@ -/******************************************************************************* -* File Name: cycfg_pins.h -* -* Description: -* Pin configuration -* This file was automatically generated and should not be modified. -* Device Configurator: 2.0.0.1483 -* Device Support Library (libs/psoc6pdl): 1.4.1.2240 -* -******************************************************************************** -* Copyright 2017-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -********************************************************************************/ - -#if !defined(CYCFG_PINS_H) -#define CYCFG_PINS_H - -#include "cycfg_notices.h" -#include "cy_gpio.h" -#if defined (CY_USING_HAL) - #include "cyhal_hwmgr.h" -#endif //defined (CY_USING_HAL) -#include "cycfg_routing.h" - -#if defined(__cplusplus) -extern "C" { -#endif - -#define CYBSP_WCO_IN_ENABLED 1U -#define CYBSP_WCO_IN_PORT GPIO_PRT0 -#define CYBSP_WCO_IN_PORT_NUM 0U -#define CYBSP_WCO_IN_PIN 0U -#define CYBSP_WCO_IN_NUM 0U -#define CYBSP_WCO_IN_DRIVEMODE CY_GPIO_DM_ANALOG -#define CYBSP_WCO_IN_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_0_pin_0_HSIOM - #define ioss_0_port_0_pin_0_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_WCO_IN_HSIOM ioss_0_port_0_pin_0_HSIOM -#define CYBSP_WCO_IN_IRQ ioss_interrupts_gpio_0_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_WCO_IN_HAL_PORT_PIN P0_0 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_WCO_IN_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_WCO_IN_HAL_DIR CYHAL_GPIO_DIR_INPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_WCO_IN_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG -#endif //defined (CY_USING_HAL) -#define CYBSP_WCO_OUT_ENABLED 1U -#define CYBSP_WCO_OUT_PORT GPIO_PRT0 -#define CYBSP_WCO_OUT_PORT_NUM 0U -#define CYBSP_WCO_OUT_PIN 1U -#define CYBSP_WCO_OUT_NUM 1U -#define CYBSP_WCO_OUT_DRIVEMODE CY_GPIO_DM_ANALOG -#define CYBSP_WCO_OUT_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_0_pin_1_HSIOM - #define ioss_0_port_0_pin_1_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_WCO_OUT_HSIOM ioss_0_port_0_pin_1_HSIOM -#define CYBSP_WCO_OUT_IRQ ioss_interrupts_gpio_0_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_WCO_OUT_HAL_PORT_PIN P0_1 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_WCO_OUT_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_WCO_OUT_HAL_DIR CYHAL_GPIO_DIR_INPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_WCO_OUT_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG -#endif //defined (CY_USING_HAL) -#define CYBSP_ECO_IN_ENABLED 1U -#define CYBSP_ECO_IN_PORT GPIO_PRT12 -#define CYBSP_ECO_IN_PORT_NUM 12U -#define CYBSP_ECO_IN_PIN 6U -#define CYBSP_ECO_IN_NUM 6U -#define CYBSP_ECO_IN_DRIVEMODE CY_GPIO_DM_ANALOG -#define CYBSP_ECO_IN_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_12_pin_6_HSIOM - #define ioss_0_port_12_pin_6_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_ECO_IN_HSIOM ioss_0_port_12_pin_6_HSIOM -#define CYBSP_ECO_IN_IRQ ioss_interrupts_gpio_12_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_ECO_IN_HAL_PORT_PIN P12_6 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_ECO_IN_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_ECO_IN_HAL_DIR CYHAL_GPIO_DIR_INPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_ECO_IN_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG -#endif //defined (CY_USING_HAL) -#define CYBSP_ECO_OUT_ENABLED 1U -#define CYBSP_ECO_OUT_PORT GPIO_PRT12 -#define CYBSP_ECO_OUT_PORT_NUM 12U -#define CYBSP_ECO_OUT_PIN 7U -#define CYBSP_ECO_OUT_NUM 7U -#define CYBSP_ECO_OUT_DRIVEMODE CY_GPIO_DM_ANALOG -#define CYBSP_ECO_OUT_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_12_pin_7_HSIOM - #define ioss_0_port_12_pin_7_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_ECO_OUT_HSIOM ioss_0_port_12_pin_7_HSIOM -#define CYBSP_ECO_OUT_IRQ ioss_interrupts_gpio_12_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_ECO_OUT_HAL_PORT_PIN P12_7 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_ECO_OUT_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_ECO_OUT_HAL_DIR CYHAL_GPIO_DIR_INPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_ECO_OUT_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG -#endif //defined (CY_USING_HAL) -#define CYBSP_SWO_ENABLED 1U -#define CYBSP_SWO_PORT GPIO_PRT6 -#define CYBSP_SWO_PORT_NUM 6U -#define CYBSP_SWO_PIN 4U -#define CYBSP_SWO_NUM 4U -#define CYBSP_SWO_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF -#define CYBSP_SWO_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_6_pin_4_HSIOM - #define ioss_0_port_6_pin_4_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_SWO_HSIOM ioss_0_port_6_pin_4_HSIOM -#define CYBSP_SWO_IRQ ioss_interrupts_gpio_6_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_SWO_HAL_PORT_PIN P6_4 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_SWO_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_SWO_HAL_DIR CYHAL_GPIO_DIR_OUTPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_SWO_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG -#endif //defined (CY_USING_HAL) -#define CYBSP_SWDIO_ENABLED 1U -#define CYBSP_SWDIO_PORT GPIO_PRT6 -#define CYBSP_SWDIO_PORT_NUM 6U -#define CYBSP_SWDIO_PIN 6U -#define CYBSP_SWDIO_NUM 6U -#define CYBSP_SWDIO_DRIVEMODE CY_GPIO_DM_PULLUP -#define CYBSP_SWDIO_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_6_pin_6_HSIOM - #define ioss_0_port_6_pin_6_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_SWDIO_HSIOM ioss_0_port_6_pin_6_HSIOM -#define CYBSP_SWDIO_IRQ ioss_interrupts_gpio_6_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_SWDIO_HAL_PORT_PIN P6_6 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_SWDIO_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_SWDIO_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_SWDIO_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLUP -#endif //defined (CY_USING_HAL) -#define CYBSP_SWCLK_ENABLED 1U -#define CYBSP_SWCLK_PORT GPIO_PRT6 -#define CYBSP_SWCLK_PORT_NUM 6U -#define CYBSP_SWCLK_PIN 7U -#define CYBSP_SWCLK_NUM 7U -#define CYBSP_SWCLK_DRIVEMODE CY_GPIO_DM_PULLDOWN -#define CYBSP_SWCLK_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_6_pin_7_HSIOM - #define ioss_0_port_6_pin_7_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_SWCLK_HSIOM ioss_0_port_6_pin_7_HSIOM -#define CYBSP_SWCLK_IRQ ioss_interrupts_gpio_6_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_SWCLK_HAL_PORT_PIN P6_7 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_SWCLK_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_SWCLK_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_SWCLK_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLDOWN -#endif //defined (CY_USING_HAL) - -extern const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_WCO_IN_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_WCO_OUT_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_ECO_IN_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_ECO_IN_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_ECO_OUT_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_ECO_OUT_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_SWO_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_SWO_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_SWDIO_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_SWCLK_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_SWCLK_obj; -#endif //defined (CY_USING_HAL) - -void init_cycfg_pins(void); - -#if defined(__cplusplus) -} -#endif - - -#endif /* CYCFG_PINS_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c deleted file mode 100644 index 82cd0ac6ff..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c +++ /dev/null @@ -1,266 +0,0 @@ -/******************************************************************************* -* File Name: cycfg_qspi_memslot.c -* -* Description: -* Provides definitions of the SMIF-driver memory configuration. -* This file was automatically generated and should not be modified. -* QSPI Configurator: 2.0.0.1483 -* -******************************************************************************** -* Copyright 2017-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -********************************************************************************/ - -#include "cycfg_qspi_memslot.h" - -const cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_readCmd = -{ - /* The 8-bit command. 1 x I/O read command. */ - .command = 0xEBU, - /* The width of the command transfer. */ - .cmdWidth = CY_SMIF_WIDTH_SINGLE, - /* The width of the address transfer. */ - .addrWidth = CY_SMIF_WIDTH_QUAD, - /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */ - .mode = 0x01U, - /* The width of the mode command transfer. */ - .modeWidth = CY_SMIF_WIDTH_QUAD, - /* The number of dummy cycles. A zero value suggests no dummy cycles. */ - .dummyCycles = 4U, - /* The width of the data transfer. */ - .dataWidth = CY_SMIF_WIDTH_QUAD -}; - -const cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_writeEnCmd = -{ - /* The 8-bit command. 1 x I/O read command. */ - .command = 0x06U, - /* The width of the command transfer. */ - .cmdWidth = CY_SMIF_WIDTH_SINGLE, - /* The width of the address transfer. */ - .addrWidth = CY_SMIF_WIDTH_SINGLE, - /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */ - .mode = 0xFFFFFFFFU, - /* The width of the mode command transfer. */ - .modeWidth = CY_SMIF_WIDTH_SINGLE, - /* The number of dummy cycles. A zero value suggests no dummy cycles. */ - .dummyCycles = 0U, - /* The width of the data transfer. */ - .dataWidth = CY_SMIF_WIDTH_SINGLE -}; - -const cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_writeDisCmd = -{ - /* The 8-bit command. 1 x I/O read command. */ - .command = 0x04U, - /* The width of the command transfer. */ - .cmdWidth = CY_SMIF_WIDTH_SINGLE, - /* The width of the address transfer. */ - .addrWidth = CY_SMIF_WIDTH_SINGLE, - /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */ - .mode = 0xFFFFFFFFU, - /* The width of the mode command transfer. */ - .modeWidth = CY_SMIF_WIDTH_SINGLE, - /* The number of dummy cycles. A zero value suggests no dummy cycles. */ - .dummyCycles = 0U, - /* The width of the data transfer. */ - .dataWidth = CY_SMIF_WIDTH_SINGLE -}; - -const cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_eraseCmd = -{ - /* The 8-bit command. 1 x I/O read command. */ - .command = 0x20U, - /* The width of the command transfer. */ - .cmdWidth = CY_SMIF_WIDTH_SINGLE, - /* The width of the address transfer. */ - .addrWidth = CY_SMIF_WIDTH_SINGLE, - /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */ - .mode = 0xFFFFFFFFU, - /* The width of the mode command transfer. */ - .modeWidth = CY_SMIF_WIDTH_SINGLE, - /* The number of dummy cycles. A zero value suggests no dummy cycles. */ - .dummyCycles = 0U, - /* The width of the data transfer. */ - .dataWidth = CY_SMIF_WIDTH_SINGLE -}; - -const cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_chipEraseCmd = -{ - /* The 8-bit command. 1 x I/O read command. */ - .command = 0x60U, - /* The width of the command transfer. */ - .cmdWidth = CY_SMIF_WIDTH_SINGLE, - /* The width of the address transfer. */ - .addrWidth = CY_SMIF_WIDTH_SINGLE, - /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */ - .mode = 0xFFFFFFFFU, - /* The width of the mode command transfer. */ - .modeWidth = CY_SMIF_WIDTH_SINGLE, - /* The number of dummy cycles. A zero value suggests no dummy cycles. */ - .dummyCycles = 0U, - /* The width of the data transfer. */ - .dataWidth = CY_SMIF_WIDTH_SINGLE -}; - -const cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_programCmd = -{ - /* The 8-bit command. 1 x I/O read command. */ - .command = 0x38U, - /* The width of the command transfer. */ - .cmdWidth = CY_SMIF_WIDTH_SINGLE, - /* The width of the address transfer. */ - .addrWidth = CY_SMIF_WIDTH_SINGLE, - /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */ - .mode = 0xFFFFFFFFU, - /* The width of the mode command transfer. */ - .modeWidth = CY_SMIF_WIDTH_QUAD, - /* The number of dummy cycles. A zero value suggests no dummy cycles. */ - .dummyCycles = 0U, - /* The width of the data transfer. */ - .dataWidth = CY_SMIF_WIDTH_QUAD -}; - -const cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_readStsRegQeCmd = -{ - /* The 8-bit command. 1 x I/O read command. */ - .command = 0x35U, - /* The width of the command transfer. */ - .cmdWidth = CY_SMIF_WIDTH_SINGLE, - /* The width of the address transfer. */ - .addrWidth = CY_SMIF_WIDTH_SINGLE, - /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */ - .mode = 0xFFFFFFFFU, - /* The width of the mode command transfer. */ - .modeWidth = CY_SMIF_WIDTH_SINGLE, - /* The number of dummy cycles. A zero value suggests no dummy cycles. */ - .dummyCycles = 0U, - /* The width of the data transfer. */ - .dataWidth = CY_SMIF_WIDTH_SINGLE -}; - -const cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_readStsRegWipCmd = -{ - /* The 8-bit command. 1 x I/O read command. */ - .command = 0x05U, - /* The width of the command transfer. */ - .cmdWidth = CY_SMIF_WIDTH_SINGLE, - /* The width of the address transfer. */ - .addrWidth = CY_SMIF_WIDTH_SINGLE, - /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */ - .mode = 0xFFFFFFFFU, - /* The width of the mode command transfer. */ - .modeWidth = CY_SMIF_WIDTH_SINGLE, - /* The number of dummy cycles. A zero value suggests no dummy cycles. */ - .dummyCycles = 0U, - /* The width of the data transfer. */ - .dataWidth = CY_SMIF_WIDTH_SINGLE -}; - -const cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_writeStsRegQeCmd = -{ - /* The 8-bit command. 1 x I/O read command. */ - .command = 0x01U, - /* The width of the command transfer. */ - .cmdWidth = CY_SMIF_WIDTH_SINGLE, - /* The width of the address transfer. */ - .addrWidth = CY_SMIF_WIDTH_SINGLE, - /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */ - .mode = 0xFFFFFFFFU, - /* The width of the mode command transfer. */ - .modeWidth = CY_SMIF_WIDTH_SINGLE, - /* The number of dummy cycles. A zero value suggests no dummy cycles. */ - .dummyCycles = 0U, - /* The width of the data transfer. */ - .dataWidth = CY_SMIF_WIDTH_SINGLE -}; - -const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL128S_SlaveSlot_0 = -{ - /* Specifies the number of address bytes used by the memory slave device. */ - .numOfAddrBytes = 0x03U, - /* The size of the memory. */ - .memSize = 0x1000000U, - /* Specifies the Read command. */ - .readCmd = (cy_stc_smif_mem_cmd_t*)&S25FL128S_SlaveSlot_0_readCmd, - /* Specifies the Write Enable command. */ - .writeEnCmd = (cy_stc_smif_mem_cmd_t*)&S25FL128S_SlaveSlot_0_writeEnCmd, - /* Specifies the Write Disable command. */ - .writeDisCmd = (cy_stc_smif_mem_cmd_t*)&S25FL128S_SlaveSlot_0_writeDisCmd, - /* Specifies the Erase command. */ - .eraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL128S_SlaveSlot_0_eraseCmd, - /* Specifies the sector size of each erase. */ - .eraseSize = 0x0001000U, - /* Specifies the Chip Erase command. */ - .chipEraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL128S_SlaveSlot_0_chipEraseCmd, - /* Specifies the Program command. */ - .programCmd = (cy_stc_smif_mem_cmd_t*)&S25FL128S_SlaveSlot_0_programCmd, - /* Specifies the page size for programming. */ - .programSize = 0x0000200U, - /* Specifies the command to read the QE-containing status register. */ - .readStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL128S_SlaveSlot_0_readStsRegQeCmd, - /* Specifies the command to read the WIP-containing status register. */ - .readStsRegWipCmd = (cy_stc_smif_mem_cmd_t*)&S25FL128S_SlaveSlot_0_readStsRegWipCmd, - /* Specifies the command to write into the QE-containing status register. */ - .writeStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL128S_SlaveSlot_0_writeStsRegQeCmd, - /* The mask for the status register. */ - .stsRegBusyMask = 0x01U, - /* The mask for the status register. */ - .stsRegQuadEnableMask = 0x02U, - /* The max time for the erase type-1 cycle-time in ms. */ - .eraseTime = 650U, - /* The max time for the chip-erase cycle-time in ms. */ - .chipEraseTime = 165000U, - /* The max time for the page-program cycle-time in us. */ - .programTime = 750U -}; - -const cy_stc_smif_mem_config_t S25FL128S_SlaveSlot_0 = -{ - /* Determines the slot number where the memory device is placed. */ - .slaveSelect = CY_SMIF_SLAVE_SELECT_0, - /* Flags. */ - .flags = CY_SMIF_FLAG_MEMORY_MAPPED | CY_SMIF_FLAG_WR_EN, - /* The data-line selection options for a slave device. */ - .dataSelect = CY_SMIF_DATA_SEL0, - /* The base address the memory slave is mapped to in the PSoC memory map. - Valid when the memory-mapped mode is enabled. */ - .baseAddress = 0x18000000U, - /* The size allocated in the PSoC memory map, for the memory slave device. - The size is allocated from the base address. Valid when the memory mapped mode is enabled. */ - .memMappedSize = 0x1000000U, - /* If this memory device is one of the devices in the dual quad SPI configuration. - Valid when the memory mapped mode is enabled. */ - .dualQuadSlots = 0, - /* The configuration of the device. */ - .deviceCfg = (cy_stc_smif_mem_device_cfg_t*)&deviceCfg_S25FL128S_SlaveSlot_0 -}; - -const cy_stc_smif_mem_config_t* const smifMemConfigs[] = { - &S25FL128S_SlaveSlot_0 -}; - -const cy_stc_smif_block_config_t smifBlockConfig = -{ - /* The number of SMIF memories defined. */ - .memCount = CY_SMIF_DEVICE_NUM, - /* The pointer to the array of memory config structures of size memCount. */ - .memConfig = (cy_stc_smif_mem_config_t**)smifMemConfigs, - /* The version of the SMIF driver. */ - .majorVersion = CY_SMIF_DRV_VERSION_MAJOR, - /* The version of the SMIF driver. */ - .minorVersion = CY_SMIF_DRV_VERSION_MINOR -}; - diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h deleted file mode 100644 index 6b41dd0a59..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h +++ /dev/null @@ -1,51 +0,0 @@ -/******************************************************************************* -* File Name: cycfg_qspi_memslot.h -* -* Description: -* Provides declarations of the SMIF-driver memory configuration. -* This file was automatically generated and should not be modified. -* QSPI Configurator: 2.0.0.1483 -* -******************************************************************************** -* Copyright 2017-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -********************************************************************************/ - -#ifndef CYCFG_QSPI_MEMSLOT_H -#define CYCFG_QSPI_MEMSLOT_H -#include "cy_smif_memslot.h" - -#define CY_SMIF_DEVICE_NUM 1 - -extern const cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_readCmd; -extern const cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_writeEnCmd; -extern const cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_writeDisCmd; -extern const cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_eraseCmd; -extern const cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_chipEraseCmd; -extern const cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_programCmd; -extern const cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_readStsRegQeCmd; -extern const cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_readStsRegWipCmd; -extern const cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_writeStsRegQeCmd; - -extern const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL128S_SlaveSlot_0; - -extern const cy_stc_smif_mem_config_t S25FL128S_SlaveSlot_0; -extern const cy_stc_smif_mem_config_t* const smifMemConfigs[CY_SMIF_DEVICE_NUM]; - -extern const cy_stc_smif_block_config_t smifBlockConfig; - - -#endif /*CY_SMIF_MEMCONFIG_H*/ - diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c deleted file mode 100644 index 7195301d04..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c +++ /dev/null @@ -1,31 +0,0 @@ -/******************************************************************************* -* File Name: cycfg_routing.c -* -* Description: -* Establishes all necessary connections between hardware elements. -* This file was automatically generated and should not be modified. -* Device Configurator: 2.0.0.1483 -* Device Support Library (libs/psoc6pdl): 1.4.1.2240 -* -******************************************************************************** -* Copyright 2017-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -********************************************************************************/ - -#include "cycfg_routing.h" - -void init_cycfg_routing(void) -{ -} diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h deleted file mode 100644 index 891fa6a171..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h +++ /dev/null @@ -1,48 +0,0 @@ -/******************************************************************************* -* File Name: cycfg_routing.h -* -* Description: -* Establishes all necessary connections between hardware elements. -* This file was automatically generated and should not be modified. -* Device Configurator: 2.0.0.1483 -* Device Support Library (libs/psoc6pdl): 1.4.1.2240 -* -******************************************************************************** -* Copyright 2017-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -********************************************************************************/ - -#if !defined(CYCFG_ROUTING_H) -#define CYCFG_ROUTING_H - -#if defined(__cplusplus) -extern "C" { -#endif - -#include "cycfg_notices.h" -void init_cycfg_routing(void); -#define init_cycfg_connectivity() init_cycfg_routing() -#define ioss_0_port_0_pin_0_ANALOG P0_0_SRSS_WCO_IN -#define ioss_0_port_0_pin_1_ANALOG P0_1_SRSS_WCO_OUT -#define ioss_0_port_6_pin_4_HSIOM P6_4_CPUSS_SWJ_SWO_TDO -#define ioss_0_port_6_pin_6_HSIOM P6_6_CPUSS_SWJ_SWDIO_TMS -#define ioss_0_port_6_pin_7_HSIOM P6_7_CPUSS_SWJ_SWCLK_TCLK - -#if defined(__cplusplus) -} -#endif - - -#endif /* CYCFG_ROUTING_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c deleted file mode 100644 index 22226cf4bf..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c +++ /dev/null @@ -1,567 +0,0 @@ -/******************************************************************************* -* File Name: cycfg_system.c -* -* Description: -* System configuration -* This file was automatically generated and should not be modified. -* Device Configurator: 2.0.0.1483 -* Device Support Library (libs/psoc6pdl): 1.4.1.2240 -* -******************************************************************************** -* Copyright 2017-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -********************************************************************************/ - -#include "cycfg_system.h" - -#define CY_CFG_SYSCLK_ECO_ERROR 1 -#define CY_CFG_SYSCLK_ALTHF_ERROR 2 -#define CY_CFG_SYSCLK_PLL_ERROR 3 -#define CY_CFG_SYSCLK_FLL_ERROR 4 -#define CY_CFG_SYSCLK_WCO_ERROR 5 -#define CY_CFG_SYSCLK_CLKBAK_ENABLED 1 -#define CY_CFG_SYSCLK_CLKFAST_ENABLED 1 -#define CY_CFG_SYSCLK_FLL_ENABLED 1 -#define CY_CFG_SYSCLK_CLKHF0_ENABLED 1 -#define CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ 100UL -#define CY_CFG_SYSCLK_CLKHF0_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0 -#define CY_CFG_SYSCLK_CLKHF2_ENABLED 1 -#define CY_CFG_SYSCLK_CLKHF2_FREQ_MHZ 50UL -#define CY_CFG_SYSCLK_CLKHF2_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0 -#define CY_CFG_SYSCLK_CLKHF3_ENABLED 1 -#define CY_CFG_SYSCLK_CLKHF3_FREQ_MHZ 48UL -#define CY_CFG_SYSCLK_CLKHF3_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH1 -#define CY_CFG_SYSCLK_ILO_ENABLED 1 -#define CY_CFG_SYSCLK_IMO_ENABLED 1 -#define CY_CFG_SYSCLK_CLKLF_ENABLED 1 -#define CY_CFG_SYSCLK_CLKPATH0_ENABLED 1 -#define CY_CFG_SYSCLK_CLKPATH0_SOURCE CY_SYSCLK_CLKPATH_IN_IMO -#define CY_CFG_SYSCLK_CLKPATH1_ENABLED 1 -#define CY_CFG_SYSCLK_CLKPATH1_SOURCE CY_SYSCLK_CLKPATH_IN_IMO -#define CY_CFG_SYSCLK_CLKPATH2_ENABLED 1 -#define CY_CFG_SYSCLK_CLKPATH2_SOURCE CY_SYSCLK_CLKPATH_IN_IMO -#define CY_CFG_SYSCLK_CLKPATH3_ENABLED 1 -#define CY_CFG_SYSCLK_CLKPATH3_SOURCE CY_SYSCLK_CLKPATH_IN_IMO -#define CY_CFG_SYSCLK_CLKPATH4_ENABLED 1 -#define CY_CFG_SYSCLK_CLKPATH4_SOURCE CY_SYSCLK_CLKPATH_IN_IMO -#define CY_CFG_SYSCLK_CLKPERI_ENABLED 1 -#define CY_CFG_SYSCLK_PLL0_ENABLED 1 -#define CY_CFG_SYSCLK_CLKSLOW_ENABLED 1 -#define CY_CFG_SYSCLK_WCO_ENABLED 1 -#define CY_CFG_PWR_ENABLED 1 -#define CY_CFG_PWR_INIT 1 -#define CY_CFG_PWR_USING_PMIC 0 -#define CY_CFG_PWR_VBACKUP_USING_VDDD 1 -#define CY_CFG_PWR_LDO_VOLTAGE CY_SYSPM_LDO_VOLTAGE_LP -#define CY_CFG_PWR_USING_ULP 0 - -static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig = -{ - .fllMult = 500U, - .refDiv = 20U, - .ccoRange = CY_SYSCLK_FLL_CCO_RANGE4, - .enableOutputDiv = true, - .lockTolerance = 10U, - .igain = 9U, - .pgain = 5U, - .settlingCount = 8U, - .outputMode = CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT, - .cco_Freq = 355U, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj = - { - .type = CYHAL_RSC_CLKPATH, - .block_num = 0U, - .channel_num = 0U, - }; -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj = - { - .type = CYHAL_RSC_CLKPATH, - .block_num = 1U, - .channel_num = 0U, - }; -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj = - { - .type = CYHAL_RSC_CLKPATH, - .block_num = 2U, - .channel_num = 0U, - }; -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t srss_0_clock_0_pathmux_3_obj = - { - .type = CYHAL_RSC_CLKPATH, - .block_num = 3U, - .channel_num = 0U, - }; -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t srss_0_clock_0_pathmux_4_obj = - { - .type = CYHAL_RSC_CLKPATH, - .block_num = 4U, - .channel_num = 0U, - }; -#endif //defined (CY_USING_HAL) -static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_0_pllConfig = -{ - .feedbackDiv = 30, - .referenceDiv = 1, - .outputDiv = 5, - .lfMode = false, - .outputMode = CY_SYSCLK_FLLPLL_OUTPUT_AUTO, -}; - -__WEAK void cycfg_ClockStartupError(uint32_t error) -{ - (void)error; /* Suppress the compiler warning */ - while(1); -} -__STATIC_INLINE void Cy_SysClk_ClkBakInit() -{ - Cy_SysClk_ClkBakSetSource(CY_SYSCLK_BAK_IN_WCO); -} -__STATIC_INLINE void Cy_SysClk_ClkFastInit() -{ - Cy_SysClk_ClkFastSetDivider(0U); -} -__STATIC_INLINE void Cy_SysClk_FllInit() -{ - if (CY_SYSCLK_SUCCESS != Cy_SysClk_FllManualConfigure(&srss_0_clock_0_fll_0_fllConfig)) - { - cycfg_ClockStartupError(CY_CFG_SYSCLK_FLL_ERROR); - } - if (CY_SYSCLK_SUCCESS != Cy_SysClk_FllEnable(200000UL)) - { - cycfg_ClockStartupError(CY_CFG_SYSCLK_FLL_ERROR); - } -} -__STATIC_INLINE void Cy_SysClk_ClkHf0Init() -{ - Cy_SysClk_ClkHfSetSource(0U, CY_CFG_SYSCLK_CLKHF0_CLKPATH); - Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE); -} -__STATIC_INLINE void Cy_SysClk_ClkHf2Init() -{ - Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF2, CY_CFG_SYSCLK_CLKHF2_CLKPATH); - Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF2, CY_SYSCLK_CLKHF_DIVIDE_BY_2); - Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF2); -} -__STATIC_INLINE void Cy_SysClk_ClkHf3Init() -{ - Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF3, CY_CFG_SYSCLK_CLKHF3_CLKPATH); - Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF3, CY_SYSCLK_CLKHF_NO_DIVIDE); - Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF3); -} -__STATIC_INLINE void Cy_SysClk_IloInit() -{ - /* The WDT is unlocked in the default startup code */ - Cy_SysClk_IloEnable(); - Cy_SysClk_IloHibernateOn(true); -} -__STATIC_INLINE void Cy_SysClk_ClkLfInit() -{ - /* The WDT is unlocked in the default startup code */ - Cy_SysClk_ClkLfSetSource(CY_SYSCLK_CLKLF_IN_WCO); -} -__STATIC_INLINE void Cy_SysClk_ClkPath0Init() -{ - Cy_SysClk_ClkPathSetSource(0U, CY_CFG_SYSCLK_CLKPATH0_SOURCE); -} -__STATIC_INLINE void Cy_SysClk_ClkPath1Init() -{ - Cy_SysClk_ClkPathSetSource(1U, CY_CFG_SYSCLK_CLKPATH1_SOURCE); -} -__STATIC_INLINE void Cy_SysClk_ClkPath2Init() -{ - Cy_SysClk_ClkPathSetSource(2U, CY_CFG_SYSCLK_CLKPATH2_SOURCE); -} -__STATIC_INLINE void Cy_SysClk_ClkPath3Init() -{ - Cy_SysClk_ClkPathSetSource(3U, CY_CFG_SYSCLK_CLKPATH3_SOURCE); -} -__STATIC_INLINE void Cy_SysClk_ClkPath4Init() -{ - Cy_SysClk_ClkPathSetSource(4U, CY_CFG_SYSCLK_CLKPATH4_SOURCE); -} -__STATIC_INLINE void Cy_SysClk_ClkPeriInit() -{ - Cy_SysClk_ClkPeriSetDivider(0U); -} -__STATIC_INLINE void Cy_SysClk_Pll0Init() -{ - if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllManualConfigure(1U, &srss_0_clock_0_pll_0_pllConfig)) - { - cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR); - } - if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllEnable(1U, 10000u)) - { - cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR); - } -} -__STATIC_INLINE void Cy_SysClk_ClkSlowInit() -{ - Cy_SysClk_ClkSlowSetDivider(0U); -} -__STATIC_INLINE void Cy_SysClk_WcoInit() -{ - (void)Cy_GPIO_Pin_FastInit(GPIO_PRT0, 0U, 0x00U, 0x00U, HSIOM_SEL_GPIO); - (void)Cy_GPIO_Pin_FastInit(GPIO_PRT0, 1U, 0x00U, 0x00U, HSIOM_SEL_GPIO); - if (CY_SYSCLK_SUCCESS != Cy_SysClk_WcoEnable(1000000UL)) - { - cycfg_ClockStartupError(CY_CFG_SYSCLK_WCO_ERROR); - } -} -__STATIC_INLINE void init_cycfg_power(void) -{ - /* Reset the Backup domain on POR, XRES, BOD only if Backup domain is supplied by VDDD */ - #if (CY_CFG_PWR_VBACKUP_USING_VDDD) - #ifdef CY_CFG_SYSCLK_ILO_ENABLED - if (0u == Cy_SysLib_GetResetReason() /* POR, XRES, or BOD */) - { - Cy_SysLib_ResetBackupDomain(); - Cy_SysClk_IloDisable(); - Cy_SysClk_IloInit(); - } - #endif /* CY_CFG_SYSCLK_ILO_ENABLED */ - #endif /* CY_CFG_PWR_VBACKUP_USING_VDDD */ - - /* Configure core regulator */ - #if CY_CFG_PWR_USING_LDO - Cy_SysPm_LdoSetVoltage(CY_SYSPM_LDO_VOLTAGE_LP); - Cy_SysPm_LdoSetMode(CY_SYSPM_LDO_MODE_NORMAL); - #else - Cy_SysPm_BuckEnable(CY_SYSPM_BUCK_OUT1_VOLTAGE_LP); - #endif /* CY_CFG_PWR_USING_LDO */ - /* Configure PMIC */ - Cy_SysPm_UnlockPmic(); - #if CY_CFG_PWR_USING_PMIC - Cy_SysPm_PmicEnableOutput(); - #else - Cy_SysPm_PmicDisableOutput(); - #endif /* CY_CFG_PWR_USING_PMIC */ -} - - -void init_cycfg_system(void) -{ - /* Set worst case memory wait states (! ultra low power, 150 MHz), will update at the end */ - Cy_SysLib_SetWaitStates(false, 150UL); - #ifdef CY_CFG_PWR_ENABLED - #ifdef CY_CFG_PWR_INIT - init_cycfg_power(); - #else - #warning Power system will not be configured. Update power personality to v1.20 or later. - #endif /* CY_CFG_PWR_INIT */ - #endif /* CY_CFG_PWR_ENABLED */ - - /* Reset the core clock path to default and disable all the FLLs/PLLs */ - Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE); - Cy_SysClk_ClkFastSetDivider(0U); - Cy_SysClk_ClkPeriSetDivider(1U); - Cy_SysClk_ClkSlowSetDivider(0U); - for (uint32_t pll = CY_SRSS_NUM_PLL; pll > 0UL; --pll) /* PLL 1 is the first PLL. 0 is invalid. */ - { - (void)Cy_SysClk_PllDisable(pll); - } - Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH1, CY_SYSCLK_CLKPATH_IN_IMO); - - if ((CY_SYSCLK_CLKHF_IN_CLKPATH0 == Cy_SysClk_ClkHfGetSource(0UL)) && - (CY_SYSCLK_CLKPATH_IN_WCO == Cy_SysClk_ClkPathGetSource(CY_SYSCLK_CLKHF_IN_CLKPATH0))) - { - Cy_SysClk_ClkHfSetSource(0U, CY_SYSCLK_CLKHF_IN_CLKPATH1); - } - - Cy_SysClk_FllDisable(); - Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH0, CY_SYSCLK_CLKPATH_IN_IMO); - Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH0); - #ifdef CY_IP_MXBLESS - (void)Cy_BLE_EcoReset(); - #endif - - - /* Enable all source clocks */ - #ifdef CY_CFG_SYSCLK_PILO_ENABLED - Cy_SysClk_PiloInit(); - #endif - - #ifdef CY_CFG_SYSCLK_WCO_ENABLED - Cy_SysClk_WcoInit(); - #endif - - #ifdef CY_CFG_SYSCLK_CLKLF_ENABLED - Cy_SysClk_ClkLfInit(); - #endif - - #ifdef CY_CFG_SYSCLK_ALTHF_ENABLED - Cy_SysClk_AltHfInit(); - #endif - - #ifdef CY_CFG_SYSCLK_ECO_ENABLED - Cy_SysClk_EcoInit(); - #endif - - #ifdef CY_CFG_SYSCLK_EXTCLK_ENABLED - Cy_SysClk_ExtClkInit(); - #endif - - /* Configure CPU clock dividers */ - #ifdef CY_CFG_SYSCLK_CLKFAST_ENABLED - Cy_SysClk_ClkFastInit(); - #endif - - #ifdef CY_CFG_SYSCLK_CLKPERI_ENABLED - Cy_SysClk_ClkPeriInit(); - #endif - - #ifdef CY_CFG_SYSCLK_CLKSLOW_ENABLED - Cy_SysClk_ClkSlowInit(); - #endif - - #if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE == CY_SYSCLK_CLKPATH_IN_WCO) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH == CY_SYSCLK_CLKHF_IN_CLKPATH0)) - /* Configure HFCLK0 to temporarily run from IMO to initialize other clocks */ - Cy_SysClk_ClkPathSetSource(1UL, CY_SYSCLK_CLKPATH_IN_IMO); - Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH1); - #else - #ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED - Cy_SysClk_ClkPath1Init(); - #endif - #endif - - /* Configure Path Clocks */ - #ifdef CY_CFG_SYSCLK_CLKPATH0_ENABLED - Cy_SysClk_ClkPath0Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKPATH2_ENABLED - Cy_SysClk_ClkPath2Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKPATH3_ENABLED - Cy_SysClk_ClkPath3Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKPATH4_ENABLED - Cy_SysClk_ClkPath4Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKPATH5_ENABLED - Cy_SysClk_ClkPath5Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKPATH6_ENABLED - Cy_SysClk_ClkPath6Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKPATH7_ENABLED - Cy_SysClk_ClkPath7Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKPATH8_ENABLED - Cy_SysClk_ClkPath8Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKPATH9_ENABLED - Cy_SysClk_ClkPath9Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKPATH10_ENABLED - Cy_SysClk_ClkPath10Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKPATH11_ENABLED - Cy_SysClk_ClkPath11Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKPATH12_ENABLED - Cy_SysClk_ClkPath12Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKPATH13_ENABLED - Cy_SysClk_ClkPath13Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKPATH14_ENABLED - Cy_SysClk_ClkPath14Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKPATH15_ENABLED - Cy_SysClk_ClkPath15Init(); - #endif - - /* Configure and enable FLL */ - #ifdef CY_CFG_SYSCLK_FLL_ENABLED - Cy_SysClk_FllInit(); - #endif - - Cy_SysClk_ClkHf0Init(); - - #if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE == CY_SYSCLK_CLKPATH_IN_WCO) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH == CY_SYSCLK_CLKHF_IN_CLKPATH0)) - #ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED - /* Apply the ClkPath1 user setting */ - Cy_SysClk_ClkPath1Init(); - #endif - #endif - - /* Configure and enable PLLs */ - #ifdef CY_CFG_SYSCLK_PLL0_ENABLED - Cy_SysClk_Pll0Init(); - #endif - #ifdef CY_CFG_SYSCLK_PLL1_ENABLED - Cy_SysClk_Pll1Init(); - #endif - #ifdef CY_CFG_SYSCLK_PLL2_ENABLED - Cy_SysClk_Pll2Init(); - #endif - #ifdef CY_CFG_SYSCLK_PLL3_ENABLED - Cy_SysClk_Pll3Init(); - #endif - #ifdef CY_CFG_SYSCLK_PLL4_ENABLED - Cy_SysClk_Pll4Init(); - #endif - #ifdef CY_CFG_SYSCLK_PLL5_ENABLED - Cy_SysClk_Pll5Init(); - #endif - #ifdef CY_CFG_SYSCLK_PLL6_ENABLED - Cy_SysClk_Pll6Init(); - #endif - #ifdef CY_CFG_SYSCLK_PLL7_ENABLED - Cy_SysClk_Pll7Init(); - #endif - #ifdef CY_CFG_SYSCLK_PLL8_ENABLED - Cy_SysClk_Pll8Init(); - #endif - #ifdef CY_CFG_SYSCLK_PLL9_ENABLED - Cy_SysClk_Pll9Init(); - #endif - #ifdef CY_CFG_SYSCLK_PLL10_ENABLED - Cy_SysClk_Pll10Init(); - #endif - #ifdef CY_CFG_SYSCLK_PLL11_ENABLED - Cy_SysClk_Pll11Init(); - #endif - #ifdef CY_CFG_SYSCLK_PLL12_ENABLED - Cy_SysClk_Pll12Init(); - #endif - #ifdef CY_CFG_SYSCLK_PLL13_ENABLED - Cy_SysClk_Pll13Init(); - #endif - #ifdef CY_CFG_SYSCLK_PLL14_ENABLED - Cy_SysClk_Pll14Init(); - #endif - - /* Configure HF clocks */ - #ifdef CY_CFG_SYSCLK_CLKHF1_ENABLED - Cy_SysClk_ClkHf1Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKHF2_ENABLED - Cy_SysClk_ClkHf2Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKHF3_ENABLED - Cy_SysClk_ClkHf3Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKHF4_ENABLED - Cy_SysClk_ClkHf4Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKHF5_ENABLED - Cy_SysClk_ClkHf5Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKHF6_ENABLED - Cy_SysClk_ClkHf6Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKHF7_ENABLED - Cy_SysClk_ClkHf7Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKHF8_ENABLED - Cy_SysClk_ClkHf8Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKHF9_ENABLED - Cy_SysClk_ClkHf9Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKHF10_ENABLED - Cy_SysClk_ClkHf10Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKHF11_ENABLED - Cy_SysClk_ClkHf11Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKHF12_ENABLED - Cy_SysClk_ClkHf12Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKHF13_ENABLED - Cy_SysClk_ClkHf13Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKHF14_ENABLED - Cy_SysClk_ClkHf14Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKHF15_ENABLED - Cy_SysClk_ClkHf15Init(); - #endif - - /* Configure miscellaneous clocks */ - #ifdef CY_CFG_SYSCLK_CLKTIMER_ENABLED - Cy_SysClk_ClkTimerInit(); - #endif - - #ifdef CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED - Cy_SysClk_ClkAltSysTickInit(); - #endif - - #ifdef CY_CFG_SYSCLK_CLKPUMP_ENABLED - Cy_SysClk_ClkPumpInit(); - #endif - - #ifdef CY_CFG_SYSCLK_CLKBAK_ENABLED - Cy_SysClk_ClkBakInit(); - #endif - - /* Configure default enabled clocks */ - #ifdef CY_CFG_SYSCLK_ILO_ENABLED - Cy_SysClk_IloInit(); - #else - Cy_SysClk_IloDisable(); - Cy_SysClk_IloHibernateOn(false); - #endif - - #ifndef CY_CFG_SYSCLK_IMO_ENABLED - #error the IMO must be enabled for proper chip operation - #endif - - #ifdef CY_CFG_SYSCLK_MFO_ENABLED - Cy_SysClk_MfoInit(); - #endif - - #ifdef CY_CFG_SYSCLK_CLKMF_ENABLED - Cy_SysClk_ClkMfInit(); - #endif - - /* Set accurate flash wait states */ - #if (defined (CY_CFG_PWR_ENABLED) && defined (CY_CFG_SYSCLK_CLKHF0_ENABLED)) - Cy_SysLib_SetWaitStates(CY_CFG_PWR_USING_ULP != 0, CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ); - #endif - - /* Update System Core Clock values for correct Cy_SysLib_Delay functioning */ - SystemCoreClockUpdate(); - -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_0_obj); -#endif //defined (CY_USING_HAL) - -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_1_obj); -#endif //defined (CY_USING_HAL) - -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_2_obj); -#endif //defined (CY_USING_HAL) - -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_3_obj); -#endif //defined (CY_USING_HAL) - -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_4_obj); -#endif //defined (CY_USING_HAL) -} diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h deleted file mode 100644 index 4c3ce8cf50..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h +++ /dev/null @@ -1,106 +0,0 @@ -/******************************************************************************* -* File Name: cycfg_system.h -* -* Description: -* System configuration -* This file was automatically generated and should not be modified. -* Device Configurator: 2.0.0.1483 -* Device Support Library (libs/psoc6pdl): 1.4.1.2240 -* -******************************************************************************** -* Copyright 2017-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -********************************************************************************/ - -#if !defined(CYCFG_SYSTEM_H) -#define CYCFG_SYSTEM_H - -#include "cycfg_notices.h" -#include "cy_sysclk.h" -#if defined (CY_USING_HAL) - #include "cyhal_hwmgr.h" -#endif //defined (CY_USING_HAL) -#include "cy_gpio.h" -#include "cy_syspm.h" - -#if defined(__cplusplus) -extern "C" { -#endif - -#define cpuss_0_dap_0_ENABLED 1U -#define srss_0_clock_0_ENABLED 1U -#define srss_0_clock_0_bakclk_0_ENABLED 1U -#define srss_0_clock_0_fastclk_0_ENABLED 1U -#define srss_0_clock_0_fll_0_ENABLED 1U -#define srss_0_clock_0_hfclk_0_ENABLED 1U -#define CY_CFG_SYSCLK_CLKHF0 0UL -#define srss_0_clock_0_hfclk_2_ENABLED 1U -#define CY_CFG_SYSCLK_CLKHF2 2UL -#define srss_0_clock_0_hfclk_3_ENABLED 1U -#define CY_CFG_SYSCLK_CLKHF3 3UL -#define srss_0_clock_0_ilo_0_ENABLED 1U -#define srss_0_clock_0_imo_0_ENABLED 1U -#define srss_0_clock_0_lfclk_0_ENABLED 1U -#define CY_CFG_SYSCLK_CLKLF_FREQ_HZ 32768 -#define srss_0_clock_0_pathmux_0_ENABLED 1U -#define srss_0_clock_0_pathmux_1_ENABLED 1U -#define srss_0_clock_0_pathmux_2_ENABLED 1U -#define srss_0_clock_0_pathmux_3_ENABLED 1U -#define srss_0_clock_0_pathmux_4_ENABLED 1U -#define srss_0_clock_0_periclk_0_ENABLED 1U -#define srss_0_clock_0_pll_0_ENABLED 1U -#define srss_0_clock_0_slowclk_0_ENABLED 1U -#define srss_0_clock_0_wco_0_ENABLED 1U -#define srss_0_power_0_ENABLED 1U -#define CY_CFG_PWR_MODE_LP 0x01UL -#define CY_CFG_PWR_MODE_ULP 0x02UL -#define CY_CFG_PWR_MODE_ACTIVE 0x04UL -#define CY_CFG_PWR_MODE_SLEEP 0x08UL -#define CY_CFG_PWR_MODE_DEEPSLEEP 0x10UL -#define CY_CFG_PWR_SYS_IDLE_MODE CY_CFG_PWR_MODE_DEEPSLEEP -#define CY_CFG_PWR_SYS_ACTIVE_MODE CY_CFG_PWR_MODE_LP -#define CY_CFG_PWR_DEEPSLEEP_LATENCY 0UL -#define CY_CFG_PWR_USING_LDO 1 -#define CY_CFG_PWR_VDDA_MV 3300 -#define CY_CFG_PWR_VDDD_MV 3300 -#define CY_CFG_PWR_VBACKUP_MV 3300 -#define CY_CFG_PWR_VDD_NS_MV 3300 -#define CY_CFG_PWR_VDDIO0_MV 3300 -#define CY_CFG_PWR_VDDIO1_MV 3300 - -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj; -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj; -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj; -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_3_obj; -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_4_obj; -#endif //defined (CY_USING_HAL) - -void init_cycfg_system(void); - -#if defined(__cplusplus) -} -#endif - - -#endif /* CYCFG_SYSTEM_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/qspi_config.cfg b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/qspi_config.cfg deleted file mode 100644 index 34dd53fc32..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/qspi_config.cfg +++ /dev/null @@ -1,3 +0,0 @@ -set SMIF_BANKS { - 0 {addr 0x18000000 size 0x1000000 psize 0x0000200 esize 0x0001000} -} diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list deleted file mode 100644 index 866126ae96..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list +++ /dev/null @@ -1,4 +0,0 @@ -[Device=CYB06447BZI-D54] - -[Blocks] -# Nothing needs to be reserved for this board diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi deleted file mode 100644 index 48e2d57e22..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi +++ /dev/null @@ -1,63 +0,0 @@ - - - - PSoC 6.xml - - - 0 - S25FL128S - true - None - 0x18000000 - 0x1000000 - 0x18FFFFFF - true - false - QUAD_SPI_DATA_0_3 - S25FL128S - true - - - 1 - Not used - false - None - 0x18010000 - 0x10000 - 0x1801FFFF - false - false - SPI_MOSI_MISO_DATA_0_1 - default_memory.xml - false - - - 2 - Not used - false - None - 0x18020000 - 0x10000 - 0x1802FFFF - false - false - SPI_MOSI_MISO_DATA_0_1 - default_memory.xml - false - - - 3 - Not used - false - None - 0x18030000 - 0x10000 - 0x1803FFFF - false - false - SPI_MOSI_MISO_DATA_0_1 - default_memory.xml - false - - - diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/design.modus b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/design.modus deleted file mode 100644 index f022060bb3..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/design.modus +++ /dev/null @@ -1,253 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/PeripheralPins.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/PeripheralPins.c deleted file mode 100644 index 433e728ea3..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/PeripheralPins.c +++ /dev/null @@ -1,474 +0,0 @@ -/* - * mbed Microcontroller Library - * Copyright (c) 2017-2018 Future Electronics - * Copyright (c) 2019 Cypress Semiconductor Corporation - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "PeripheralNames.h" -#include "PeripheralPins.h" -#include "pinmap.h" - -#if DEVICE_SERIAL -//*** SERIAL *** -const PinMap PinMap_UART_RX[] = { - {P0_2, UART_0, CYHAL_PIN_IN_FUNCTION(P0_2_SCB0_UART_RX)}, - {P1_0, UART_7, CYHAL_PIN_IN_FUNCTION(P1_0_SCB7_UART_RX)}, - {P2_0, UART_1, CYHAL_PIN_IN_FUNCTION(P2_0_SCB1_UART_RX)}, - {P3_0, UART_2, CYHAL_PIN_IN_FUNCTION(P3_0_SCB2_UART_RX)}, - {P4_0, UART_7, CYHAL_PIN_IN_FUNCTION(P4_0_SCB7_UART_RX)}, - {P5_0, UART_5, CYHAL_PIN_IN_FUNCTION(P5_0_SCB5_UART_RX)}, - {P6_0, UART_3, CYHAL_PIN_IN_FUNCTION(P6_0_SCB3_UART_RX)}, - {P6_4, UART_6, CYHAL_PIN_IN_FUNCTION(P6_4_SCB6_UART_RX)}, - {P7_0, UART_4, CYHAL_PIN_IN_FUNCTION(P7_0_SCB4_UART_RX)}, - {P8_0, UART_4, CYHAL_PIN_IN_FUNCTION(P8_0_SCB4_UART_RX)}, - {P9_0, UART_2, CYHAL_PIN_IN_FUNCTION(P9_0_SCB2_UART_RX)}, - {P10_0, UART_1, CYHAL_PIN_IN_FUNCTION(P10_0_SCB1_UART_RX)}, - {P11_0, UART_5, CYHAL_PIN_IN_FUNCTION(P11_0_SCB5_UART_RX)}, - {P12_0, UART_6, CYHAL_PIN_IN_FUNCTION(P12_0_SCB6_UART_RX)}, - {P13_0, UART_6, CYHAL_PIN_IN_FUNCTION(P13_0_SCB6_UART_RX)}, - {NC, NC, 0} -}; -const PinMap PinMap_UART_TX[] = { - {P0_3, UART_0, CYHAL_PIN_OUT_FUNCTION(P0_3_SCB0_UART_TX)}, - {P1_1, UART_7, CYHAL_PIN_OUT_FUNCTION(P1_1_SCB7_UART_TX)}, - {P2_1, UART_1, CYHAL_PIN_OUT_FUNCTION(P2_1_SCB1_UART_TX)}, - {P3_1, UART_2, CYHAL_PIN_OUT_FUNCTION(P3_1_SCB2_UART_TX)}, - {P4_1, UART_7, CYHAL_PIN_OUT_FUNCTION(P4_1_SCB7_UART_TX)}, - {P5_1, UART_5, CYHAL_PIN_OUT_FUNCTION(P5_1_SCB5_UART_TX)}, - {P6_1, UART_3, CYHAL_PIN_OUT_FUNCTION(P6_1_SCB3_UART_TX)}, - {P6_5, UART_6, CYHAL_PIN_OUT_FUNCTION(P6_5_SCB6_UART_TX)}, - {P7_1, UART_4, CYHAL_PIN_OUT_FUNCTION(P7_1_SCB4_UART_TX)}, - {P8_1, UART_4, CYHAL_PIN_OUT_FUNCTION(P8_1_SCB4_UART_TX)}, - {P9_1, UART_2, CYHAL_PIN_OUT_FUNCTION(P9_1_SCB2_UART_TX)}, - {P10_1, UART_1, CYHAL_PIN_OUT_FUNCTION(P10_1_SCB1_UART_TX)}, - {P11_1, UART_5, CYHAL_PIN_OUT_FUNCTION(P11_1_SCB5_UART_TX)}, - {P12_1, UART_6, CYHAL_PIN_OUT_FUNCTION(P12_1_SCB6_UART_TX)}, - {P13_1, UART_6, CYHAL_PIN_OUT_FUNCTION(P13_1_SCB6_UART_TX)}, - {NC, NC, 0} -}; -const PinMap PinMap_UART_RTS[] = { - {P0_4, UART_0, CYHAL_PIN_OUT_FUNCTION(P0_4_SCB0_UART_RTS)}, - {P1_2, UART_7, CYHAL_PIN_OUT_FUNCTION(P1_2_SCB7_UART_RTS)}, - {P2_2, UART_1, CYHAL_PIN_OUT_FUNCTION(P2_2_SCB1_UART_RTS)}, - {P3_2, UART_2, CYHAL_PIN_OUT_FUNCTION(P3_2_SCB2_UART_RTS)}, - {P5_2, UART_5, CYHAL_PIN_OUT_FUNCTION(P5_2_SCB5_UART_RTS)}, - {P6_2, UART_3, CYHAL_PIN_OUT_FUNCTION(P6_2_SCB3_UART_RTS)}, - {P6_6, UART_6, CYHAL_PIN_OUT_FUNCTION(P6_6_SCB6_UART_RTS)}, - {P7_2, UART_4, CYHAL_PIN_OUT_FUNCTION(P7_2_SCB4_UART_RTS)}, - {P8_2, UART_4, CYHAL_PIN_OUT_FUNCTION(P8_2_SCB4_UART_RTS)}, - {P9_2, UART_2, CYHAL_PIN_OUT_FUNCTION(P9_2_SCB2_UART_RTS)}, - {P10_2, UART_1, CYHAL_PIN_OUT_FUNCTION(P10_2_SCB1_UART_RTS)}, - {P11_2, UART_5, CYHAL_PIN_OUT_FUNCTION(P11_2_SCB5_UART_RTS)}, - {P12_2, UART_6, CYHAL_PIN_OUT_FUNCTION(P12_2_SCB6_UART_RTS)}, - {NC, NC, 0} -}; -const PinMap PinMap_UART_CTS[] = { - {P0_5, UART_0, CYHAL_PIN_IN_FUNCTION(P0_5_SCB0_UART_CTS)}, - {P1_3, UART_7, CYHAL_PIN_IN_FUNCTION(P1_3_SCB7_UART_CTS)}, - {P2_3, UART_1, CYHAL_PIN_IN_FUNCTION(P2_3_SCB1_UART_CTS)}, - {P3_3, UART_2, CYHAL_PIN_IN_FUNCTION(P3_3_SCB2_UART_CTS)}, - {P5_3, UART_5, CYHAL_PIN_IN_FUNCTION(P5_3_SCB5_UART_CTS)}, - {P6_3, UART_3, CYHAL_PIN_IN_FUNCTION(P6_3_SCB3_UART_CTS)}, - {P6_7, UART_6, CYHAL_PIN_IN_FUNCTION(P6_7_SCB6_UART_CTS)}, - {P7_3, UART_4, CYHAL_PIN_IN_FUNCTION(P7_3_SCB4_UART_CTS)}, - {P8_3, UART_4, CYHAL_PIN_IN_FUNCTION(P8_3_SCB4_UART_CTS)}, - {P9_3, UART_2, CYHAL_PIN_IN_FUNCTION(P9_3_SCB2_UART_CTS)}, - {P10_3, UART_1, CYHAL_PIN_IN_FUNCTION(P10_3_SCB1_UART_CTS)}, - {P11_3, UART_5, CYHAL_PIN_IN_FUNCTION(P11_3_SCB5_UART_CTS)}, - {P12_3, UART_6, CYHAL_PIN_IN_FUNCTION(P12_3_SCB6_UART_CTS)}, - {NC, NC, 0} -}; -#endif // DEVICE_SERIAL - - -#if DEVICE_I2C -//*** I2C *** -const PinMap PinMap_I2C_SCL[] = { - {P0_2, I2C_0, CYHAL_PIN_OD_FUNCTION(P0_2_SCB0_I2C_SCL)}, - {P1_0, I2C_7, CYHAL_PIN_OD_FUNCTION(P1_0_SCB7_I2C_SCL)}, - {P2_0, I2C_1, CYHAL_PIN_OD_FUNCTION(P2_0_SCB1_I2C_SCL)}, - {P3_0, I2C_2, CYHAL_PIN_OD_FUNCTION(P3_0_SCB2_I2C_SCL)}, - {P4_0, I2C_7, CYHAL_PIN_OD_FUNCTION(P4_0_SCB7_I2C_SCL)}, - {P5_0, I2C_5, CYHAL_PIN_OD_FUNCTION(P5_0_SCB5_I2C_SCL)}, - {P6_0, I2C_3, CYHAL_PIN_OD_FUNCTION(P6_0_SCB3_I2C_SCL)}, - {P6_0, I2C_8, CYHAL_PIN_OD_FUNCTION(P6_0_SCB8_I2C_SCL)}, - {P6_4, I2C_6, CYHAL_PIN_OD_FUNCTION(P6_4_SCB6_I2C_SCL)}, - {P6_4, I2C_8, CYHAL_PIN_OD_FUNCTION(P6_4_SCB8_I2C_SCL)}, - {P7_0, I2C_4, CYHAL_PIN_OD_FUNCTION(P7_0_SCB4_I2C_SCL)}, - {P8_0, I2C_4, CYHAL_PIN_OD_FUNCTION(P8_0_SCB4_I2C_SCL)}, - {P9_0, I2C_2, CYHAL_PIN_OD_FUNCTION(P9_0_SCB2_I2C_SCL)}, - {P10_0, I2C_1, CYHAL_PIN_OD_FUNCTION(P10_0_SCB1_I2C_SCL)}, - {P11_0, I2C_5, CYHAL_PIN_OD_FUNCTION(P11_0_SCB5_I2C_SCL)}, - {P12_0, I2C_6, CYHAL_PIN_OD_FUNCTION(P12_0_SCB6_I2C_SCL)}, - {P13_0, I2C_6, CYHAL_PIN_OD_FUNCTION(P13_0_SCB6_I2C_SCL)}, - {NC, NC, 0} -}; -const PinMap PinMap_I2C_SDA[] = { - {P0_3, I2C_0, CYHAL_PIN_OD_FUNCTION(P0_3_SCB0_I2C_SDA)}, - {P1_1, I2C_7, CYHAL_PIN_OD_FUNCTION(P1_1_SCB7_I2C_SDA)}, - {P2_1, I2C_1, CYHAL_PIN_OD_FUNCTION(P2_1_SCB1_I2C_SDA)}, - {P3_1, I2C_2, CYHAL_PIN_OD_FUNCTION(P3_1_SCB2_I2C_SDA)}, - {P4_1, I2C_7, CYHAL_PIN_OD_FUNCTION(P4_1_SCB7_I2C_SDA)}, - {P5_1, I2C_5, CYHAL_PIN_OD_FUNCTION(P5_1_SCB5_I2C_SDA)}, - {P6_1, I2C_3, CYHAL_PIN_OD_FUNCTION(P6_1_SCB3_I2C_SDA)}, - {P6_1, I2C_8, CYHAL_PIN_OD_FUNCTION(P6_1_SCB8_I2C_SDA)}, - {P6_5, I2C_6, CYHAL_PIN_OD_FUNCTION(P6_5_SCB6_I2C_SDA)}, - {P6_5, I2C_8, CYHAL_PIN_OD_FUNCTION(P6_5_SCB8_I2C_SDA)}, - {P7_1, I2C_4, CYHAL_PIN_OD_FUNCTION(P7_1_SCB4_I2C_SDA)}, - {P8_1, I2C_4, CYHAL_PIN_OD_FUNCTION(P8_1_SCB4_I2C_SDA)}, - {P9_1, I2C_2, CYHAL_PIN_OD_FUNCTION(P9_1_SCB2_I2C_SDA)}, - {P10_1, I2C_1, CYHAL_PIN_OD_FUNCTION(P10_1_SCB1_I2C_SDA)}, - {P11_1, I2C_5, CYHAL_PIN_OD_FUNCTION(P11_1_SCB5_I2C_SDA)}, - {P12_1, I2C_6, CYHAL_PIN_OD_FUNCTION(P12_1_SCB6_I2C_SDA)}, - {P13_1, I2C_6, CYHAL_PIN_OD_FUNCTION(P13_1_SCB6_I2C_SDA)}, - {NC, NC, 0} -}; -#endif // DEVICE_I2C - -#if DEVICE_SPI -//*** SPI *** -const PinMap PinMap_SPI_MOSI[] = { - {P0_2, SPI_0, CYHAL_PIN_OUT_FUNCTION(P0_2_SCB0_SPI_MOSI)}, - {P1_0, SPI_7, CYHAL_PIN_OUT_FUNCTION(P1_0_SCB7_SPI_MOSI)}, - {P2_0, SPI_1, CYHAL_PIN_OUT_FUNCTION(P2_0_SCB1_SPI_MOSI)}, - {P3_0, SPI_2, CYHAL_PIN_OUT_FUNCTION(P3_0_SCB2_SPI_MOSI)}, - {P4_0, SPI_7, CYHAL_PIN_OUT_FUNCTION(P4_0_SCB7_SPI_MOSI)}, - {P5_0, SPI_5, CYHAL_PIN_OUT_FUNCTION(P5_0_SCB5_SPI_MOSI)}, - {P6_0, SPI_3, CYHAL_PIN_OUT_FUNCTION(P6_0_SCB3_SPI_MOSI)}, - {P6_0, SPI_8, CYHAL_PIN_OUT_FUNCTION(P6_0_SCB8_SPI_MOSI)}, - {P6_4, SPI_6, CYHAL_PIN_OUT_FUNCTION(P6_4_SCB6_SPI_MOSI)}, - {P6_4, SPI_8, CYHAL_PIN_OUT_FUNCTION(P6_4_SCB8_SPI_MOSI)}, - {P7_0, SPI_4, CYHAL_PIN_OUT_FUNCTION(P7_0_SCB4_SPI_MOSI)}, - {P8_0, SPI_4, CYHAL_PIN_OUT_FUNCTION(P8_0_SCB4_SPI_MOSI)}, - {P9_0, SPI_2, CYHAL_PIN_OUT_FUNCTION(P9_0_SCB2_SPI_MOSI)}, - {P10_0, SPI_1, CYHAL_PIN_OUT_FUNCTION(P10_0_SCB1_SPI_MOSI)}, - {P11_0, SPI_5, CYHAL_PIN_OUT_FUNCTION(P11_0_SCB5_SPI_MOSI)}, - {P12_0, SPI_6, CYHAL_PIN_OUT_FUNCTION(P12_0_SCB6_SPI_MOSI)}, - {P13_0, SPI_6, CYHAL_PIN_OUT_FUNCTION(P13_0_SCB6_SPI_MOSI)}, - {NC, NC, 0} -}; -const PinMap PinMap_SPI_MISO[] = { - {P0_3, SPI_0, CYHAL_PIN_IN_FUNCTION(P0_3_SCB0_SPI_MISO)}, - {P1_1, SPI_7, CYHAL_PIN_IN_FUNCTION(P1_1_SCB7_SPI_MISO)}, - {P2_1, SPI_1, CYHAL_PIN_IN_FUNCTION(P2_1_SCB1_SPI_MISO)}, - {P3_1, SPI_2, CYHAL_PIN_IN_FUNCTION(P3_1_SCB2_SPI_MISO)}, - {P4_1, SPI_7, CYHAL_PIN_IN_FUNCTION(P4_1_SCB7_SPI_MISO)}, - {P5_1, SPI_5, CYHAL_PIN_IN_FUNCTION(P5_1_SCB5_SPI_MISO)}, - {P6_1, SPI_3, CYHAL_PIN_IN_FUNCTION(P6_1_SCB3_SPI_MISO)}, - {P6_1, SPI_8, CYHAL_PIN_IN_FUNCTION(P6_1_SCB8_SPI_MISO)}, - {P6_5, SPI_6, CYHAL_PIN_IN_FUNCTION(P6_5_SCB6_SPI_MISO)}, - {P6_5, SPI_8, CYHAL_PIN_IN_FUNCTION(P6_5_SCB8_SPI_MISO)}, - {P7_1, SPI_4, CYHAL_PIN_IN_FUNCTION(P7_1_SCB4_SPI_MISO)}, - {P8_1, SPI_4, CYHAL_PIN_IN_FUNCTION(P8_1_SCB4_SPI_MISO)}, - {P9_1, SPI_2, CYHAL_PIN_IN_FUNCTION(P9_1_SCB2_SPI_MISO)}, - {P10_1, SPI_1, CYHAL_PIN_IN_FUNCTION(P10_1_SCB1_SPI_MISO)}, - {P11_1, SPI_5, CYHAL_PIN_IN_FUNCTION(P11_1_SCB5_SPI_MISO)}, - {P12_1, SPI_6, CYHAL_PIN_IN_FUNCTION(P12_1_SCB6_SPI_MISO)}, - {P13_1, SPI_6, CYHAL_PIN_IN_FUNCTION(P13_1_SCB6_SPI_MISO)}, - {NC, NC, 0} -}; -const PinMap PinMap_SPI_SCLK[] = { - {P0_4, SPI_0, CYHAL_PIN_OUT_FUNCTION(P0_4_SCB0_SPI_CLK)}, - {P1_2, SPI_7, CYHAL_PIN_OUT_FUNCTION(P1_2_SCB7_SPI_CLK)}, - {P2_2, SPI_1, CYHAL_PIN_OUT_FUNCTION(P2_2_SCB1_SPI_CLK)}, - {P3_2, SPI_2, CYHAL_PIN_OUT_FUNCTION(P3_2_SCB2_SPI_CLK)}, - {P5_2, SPI_5, CYHAL_PIN_OUT_FUNCTION(P5_2_SCB5_SPI_CLK)}, - {P6_2, SPI_3, CYHAL_PIN_OUT_FUNCTION(P6_2_SCB3_SPI_CLK)}, - {P6_2, SPI_8, CYHAL_PIN_OUT_FUNCTION(P6_2_SCB8_SPI_CLK)}, - {P6_6, SPI_6, CYHAL_PIN_OUT_FUNCTION(P6_6_SCB6_SPI_CLK)}, - {P6_6, SPI_8, CYHAL_PIN_OUT_FUNCTION(P6_6_SCB8_SPI_CLK)}, - {P7_2, SPI_4, CYHAL_PIN_OUT_FUNCTION(P7_2_SCB4_SPI_CLK)}, - {P8_2, SPI_4, CYHAL_PIN_OUT_FUNCTION(P8_2_SCB4_SPI_CLK)}, - {P9_2, SPI_2, CYHAL_PIN_OUT_FUNCTION(P9_2_SCB2_SPI_CLK)}, - {P10_2, SPI_1, CYHAL_PIN_OUT_FUNCTION(P10_2_SCB1_SPI_CLK)}, - {P11_2, SPI_5, CYHAL_PIN_OUT_FUNCTION(P11_2_SCB5_SPI_CLK)}, - {P12_2, SPI_6, CYHAL_PIN_OUT_FUNCTION(P12_2_SCB6_SPI_CLK)}, - {NC, NC, 0} -}; -const PinMap PinMap_SPI_SSEL[] = { - {P0_5, SPI_0, CYHAL_PIN_OUT_FUNCTION(P0_5_SCB0_SPI_SELECT0)}, - {P1_3, SPI_7, CYHAL_PIN_OUT_FUNCTION(P1_3_SCB7_SPI_SELECT0)}, - {P2_3, SPI_1, CYHAL_PIN_OUT_FUNCTION(P2_3_SCB1_SPI_SELECT0)}, - {P3_3, SPI_2, CYHAL_PIN_OUT_FUNCTION(P3_3_SCB2_SPI_SELECT0)}, - {P5_3, SPI_5, CYHAL_PIN_OUT_FUNCTION(P5_3_SCB5_SPI_SELECT0)}, - {P6_3, SPI_3, CYHAL_PIN_OUT_FUNCTION(P6_3_SCB3_SPI_SELECT0)}, - {P6_3, SPI_8, CYHAL_PIN_OUT_FUNCTION(P6_3_SCB8_SPI_SELECT0)}, - {P6_7, SPI_6, CYHAL_PIN_OUT_FUNCTION(P6_7_SCB6_SPI_SELECT0)}, - {P6_7, SPI_8, CYHAL_PIN_OUT_FUNCTION(P6_7_SCB8_SPI_SELECT0)}, - {P7_3, SPI_4, CYHAL_PIN_OUT_FUNCTION(P7_3_SCB4_SPI_SELECT0)}, - {P8_3, SPI_4, CYHAL_PIN_OUT_FUNCTION(P8_3_SCB4_SPI_SELECT0)}, - {P9_3, SPI_2, CYHAL_PIN_OUT_FUNCTION(P9_3_SCB2_SPI_SELECT0)}, - {P10_3, SPI_1, CYHAL_PIN_OUT_FUNCTION(P10_3_SCB1_SPI_SELECT0)}, - {P11_3, SPI_5, CYHAL_PIN_OUT_FUNCTION(P11_3_SCB5_SPI_SELECT0)}, - {P12_3, SPI_6, CYHAL_PIN_OUT_FUNCTION(P12_3_SCB6_SPI_SELECT0)}, - {NC, NC, 0} -}; -#endif // DEVICE_SPI - -#if DEVICE_PWMOUT -//*** PWM *** -const PinMap PinMap_PWM_OUT[] = { - // 16-bit PWM outputs - {P0_0, PWM_16b_0, CYHAL_PIN_OUT_FUNCTION(P0_0_TCPWM1_LINE0)}, - {P0_2, PWM_16b_1, CYHAL_PIN_OUT_FUNCTION(P0_2_TCPWM1_LINE1)}, - {P0_4, PWM_16b_2, CYHAL_PIN_OUT_FUNCTION(P0_4_TCPWM1_LINE2)}, - {P1_0, PWM_16b_3, CYHAL_PIN_OUT_FUNCTION(P1_0_TCPWM1_LINE3)}, - {P1_2, PWM_16b_12, CYHAL_PIN_OUT_FUNCTION(P1_2_TCPWM1_LINE12)}, - {P1_4, PWM_16b_13, CYHAL_PIN_OUT_FUNCTION(P1_4_TCPWM1_LINE13)}, - {P2_0, PWM_16b_15, CYHAL_PIN_OUT_FUNCTION(P2_0_TCPWM1_LINE15)}, - {P2_2, PWM_16b_16, CYHAL_PIN_OUT_FUNCTION(P2_2_TCPWM1_LINE16)}, - {P2_4, PWM_16b_17, CYHAL_PIN_OUT_FUNCTION(P2_4_TCPWM1_LINE17)}, - {P2_6, PWM_16b_18, CYHAL_PIN_OUT_FUNCTION(P2_6_TCPWM1_LINE18)}, - {P3_0, PWM_16b_19, CYHAL_PIN_OUT_FUNCTION(P3_0_TCPWM1_LINE19)}, - {P3_2, PWM_16b_20, CYHAL_PIN_OUT_FUNCTION(P3_2_TCPWM1_LINE20)}, - {P3_4, PWM_16b_21, CYHAL_PIN_OUT_FUNCTION(P3_4_TCPWM1_LINE21)}, - {P4_0, PWM_16b_22, CYHAL_PIN_OUT_FUNCTION(P4_0_TCPWM1_LINE22)}, - {P5_0, PWM_16b_4, CYHAL_PIN_OUT_FUNCTION(P5_0_TCPWM1_LINE4)}, - {P5_2, PWM_16b_5, CYHAL_PIN_OUT_FUNCTION(P5_2_TCPWM1_LINE5)}, - {P5_4, PWM_16b_6, CYHAL_PIN_OUT_FUNCTION(P5_4_TCPWM1_LINE6)}, - {P5_6, PWM_16b_7, CYHAL_PIN_OUT_FUNCTION(P5_6_TCPWM1_LINE7)}, - {P6_0, PWM_16b_8, CYHAL_PIN_OUT_FUNCTION(P6_0_TCPWM1_LINE8)}, - {P6_2, PWM_16b_9, CYHAL_PIN_OUT_FUNCTION(P6_2_TCPWM1_LINE9)}, - {P6_4, PWM_16b_10, CYHAL_PIN_OUT_FUNCTION(P6_4_TCPWM1_LINE10)}, - {P6_6, PWM_16b_11, CYHAL_PIN_OUT_FUNCTION(P6_6_TCPWM1_LINE11)}, - {P7_0, PWM_16b_12, CYHAL_PIN_OUT_FUNCTION(P7_0_TCPWM1_LINE12)}, - {P7_2, PWM_16b_13, CYHAL_PIN_OUT_FUNCTION(P7_2_TCPWM1_LINE13)}, - {P7_4, PWM_16b_14, CYHAL_PIN_OUT_FUNCTION(P7_4_TCPWM1_LINE14)}, - {P7_6, PWM_16b_15, CYHAL_PIN_OUT_FUNCTION(P7_6_TCPWM1_LINE15)}, - {P8_0, PWM_16b_16, CYHAL_PIN_OUT_FUNCTION(P8_0_TCPWM1_LINE16)}, - {P8_2, PWM_16b_17, CYHAL_PIN_OUT_FUNCTION(P8_2_TCPWM1_LINE17)}, - {P8_4, PWM_16b_18, CYHAL_PIN_OUT_FUNCTION(P8_4_TCPWM1_LINE18)}, - {P8_6, PWM_16b_19, CYHAL_PIN_OUT_FUNCTION(P8_6_TCPWM1_LINE19)}, - {P9_0, PWM_16b_20, CYHAL_PIN_OUT_FUNCTION(P9_0_TCPWM1_LINE20)}, - {P9_2, PWM_16b_21, CYHAL_PIN_OUT_FUNCTION(P9_2_TCPWM1_LINE21)}, - {P9_4, PWM_16b_0, CYHAL_PIN_OUT_FUNCTION(P9_4_TCPWM1_LINE0)}, - {P9_6, PWM_16b_1, CYHAL_PIN_OUT_FUNCTION(P9_6_TCPWM1_LINE1)}, - {P10_0, PWM_16b_22, CYHAL_PIN_OUT_FUNCTION(P10_0_TCPWM1_LINE22)}, - {P10_2, PWM_16b_23, CYHAL_PIN_OUT_FUNCTION(P10_2_TCPWM1_LINE23)}, - {P10_4, PWM_16b_0, CYHAL_PIN_OUT_FUNCTION(P10_4_TCPWM1_LINE0)}, - {P10_6, PWM_16b_2, CYHAL_PIN_OUT_FUNCTION(P10_6_TCPWM1_LINE2)}, - {P11_0, PWM_16b_1, CYHAL_PIN_OUT_FUNCTION(P11_0_TCPWM1_LINE1)}, - {P11_2, PWM_16b_2, CYHAL_PIN_OUT_FUNCTION(P11_2_TCPWM1_LINE2)}, - {P11_4, PWM_16b_3, CYHAL_PIN_OUT_FUNCTION(P11_4_TCPWM1_LINE3)}, - {P12_0, PWM_16b_4, CYHAL_PIN_OUT_FUNCTION(P12_0_TCPWM1_LINE4)}, - {P12_2, PWM_16b_5, CYHAL_PIN_OUT_FUNCTION(P12_2_TCPWM1_LINE5)}, - {P12_4, PWM_16b_6, CYHAL_PIN_OUT_FUNCTION(P12_4_TCPWM1_LINE6)}, - {P12_6, PWM_16b_7, CYHAL_PIN_OUT_FUNCTION(P12_6_TCPWM1_LINE7)}, - {P13_0, PWM_16b_8, CYHAL_PIN_OUT_FUNCTION(P13_0_TCPWM1_LINE8)}, - {P13_2, PWM_16b_9, CYHAL_PIN_OUT_FUNCTION(P13_2_TCPWM1_LINE9)}, - {P13_4, PWM_16b_10, CYHAL_PIN_OUT_FUNCTION(P13_4_TCPWM1_LINE10)}, - {P13_6, PWM_16b_11, CYHAL_PIN_OUT_FUNCTION(P13_6_TCPWM1_LINE11)}, - // 16-bit PWM inverted outputs - {P0_1, PWM_16b_0, CYHAL_PIN_OUT_FUNCTION(P0_1_TCPWM1_LINE_COMPL0)}, - {P0_3, PWM_16b_1, CYHAL_PIN_OUT_FUNCTION(P0_3_TCPWM1_LINE_COMPL1)}, - {P0_5, PWM_16b_2, CYHAL_PIN_OUT_FUNCTION(P0_5_TCPWM1_LINE_COMPL2)}, - {P1_1, PWM_16b_3, CYHAL_PIN_OUT_FUNCTION(P1_1_TCPWM1_LINE_COMPL3)}, - {P1_3, PWM_16b_12, CYHAL_PIN_OUT_FUNCTION(P1_3_TCPWM1_LINE_COMPL12)}, - {P1_5, PWM_16b_14, CYHAL_PIN_OUT_FUNCTION(P1_5_TCPWM1_LINE_COMPL14)}, - {P2_1, PWM_16b_15, CYHAL_PIN_OUT_FUNCTION(P2_1_TCPWM1_LINE_COMPL15)}, - {P2_3, PWM_16b_16, CYHAL_PIN_OUT_FUNCTION(P2_3_TCPWM1_LINE_COMPL16)}, - {P2_5, PWM_16b_17, CYHAL_PIN_OUT_FUNCTION(P2_5_TCPWM1_LINE_COMPL17)}, - {P2_7, PWM_16b_18, CYHAL_PIN_OUT_FUNCTION(P2_7_TCPWM1_LINE_COMPL18)}, - {P3_1, PWM_16b_19, CYHAL_PIN_OUT_FUNCTION(P3_1_TCPWM1_LINE_COMPL19)}, - {P3_3, PWM_16b_20, CYHAL_PIN_OUT_FUNCTION(P3_3_TCPWM1_LINE_COMPL20)}, - {P3_5, PWM_16b_21, CYHAL_PIN_OUT_FUNCTION(P3_5_TCPWM1_LINE_COMPL21)}, - {P4_1, PWM_16b_22, CYHAL_PIN_OUT_FUNCTION(P4_1_TCPWM1_LINE_COMPL22)}, - {P5_1, PWM_16b_4, CYHAL_PIN_OUT_FUNCTION(P5_1_TCPWM1_LINE_COMPL4)}, - {P5_3, PWM_16b_5, CYHAL_PIN_OUT_FUNCTION(P5_3_TCPWM1_LINE_COMPL5)}, - {P5_5, PWM_16b_6, CYHAL_PIN_OUT_FUNCTION(P5_5_TCPWM1_LINE_COMPL6)}, - {P5_7, PWM_16b_7, CYHAL_PIN_OUT_FUNCTION(P5_7_TCPWM1_LINE_COMPL7)}, - {P6_1, PWM_16b_8, CYHAL_PIN_OUT_FUNCTION(P6_1_TCPWM1_LINE_COMPL8)}, - {P6_3, PWM_16b_9, CYHAL_PIN_OUT_FUNCTION(P6_3_TCPWM1_LINE_COMPL9)}, - {P6_5, PWM_16b_10, CYHAL_PIN_OUT_FUNCTION(P6_5_TCPWM1_LINE_COMPL10)}, - {P6_7, PWM_16b_11, CYHAL_PIN_OUT_FUNCTION(P6_7_TCPWM1_LINE_COMPL11)}, - {P7_1, PWM_16b_12, CYHAL_PIN_OUT_FUNCTION(P7_1_TCPWM1_LINE_COMPL12)}, - {P7_3, PWM_16b_13, CYHAL_PIN_OUT_FUNCTION(P7_3_TCPWM1_LINE_COMPL13)}, - {P7_5, PWM_16b_14, CYHAL_PIN_OUT_FUNCTION(P7_5_TCPWM1_LINE_COMPL14)}, - {P7_7, PWM_16b_15, CYHAL_PIN_OUT_FUNCTION(P7_7_TCPWM1_LINE_COMPL15)}, - {P8_1, PWM_16b_16, CYHAL_PIN_OUT_FUNCTION(P8_1_TCPWM1_LINE_COMPL16)}, - {P8_3, PWM_16b_17, CYHAL_PIN_OUT_FUNCTION(P8_3_TCPWM1_LINE_COMPL17)}, - {P8_5, PWM_16b_18, CYHAL_PIN_OUT_FUNCTION(P8_5_TCPWM1_LINE_COMPL18)}, - {P8_7, PWM_16b_19, CYHAL_PIN_OUT_FUNCTION(P8_7_TCPWM1_LINE_COMPL19)}, - {P9_1, PWM_16b_20, CYHAL_PIN_OUT_FUNCTION(P9_1_TCPWM1_LINE_COMPL20)}, - {P9_3, PWM_16b_21, CYHAL_PIN_OUT_FUNCTION(P9_3_TCPWM1_LINE_COMPL21)}, - {P9_5, PWM_16b_0, CYHAL_PIN_OUT_FUNCTION(P9_5_TCPWM1_LINE_COMPL0)}, - {P9_7, PWM_16b_1, CYHAL_PIN_OUT_FUNCTION(P9_7_TCPWM1_LINE_COMPL1)}, - {P10_1, PWM_16b_22, CYHAL_PIN_OUT_FUNCTION(P10_1_TCPWM1_LINE_COMPL22)}, - {P10_3, PWM_16b_23, CYHAL_PIN_OUT_FUNCTION(P10_3_TCPWM1_LINE_COMPL23)}, - {P10_5, PWM_16b_0, CYHAL_PIN_OUT_FUNCTION(P10_5_TCPWM1_LINE_COMPL0)}, - {P10_7, PWM_16b_2, CYHAL_PIN_OUT_FUNCTION(P10_7_TCPWM1_LINE_COMPL2)}, - {P11_1, PWM_16b_1, CYHAL_PIN_OUT_FUNCTION(P11_1_TCPWM1_LINE_COMPL1)}, - {P11_3, PWM_16b_2, CYHAL_PIN_OUT_FUNCTION(P11_3_TCPWM1_LINE_COMPL2)}, - {P11_5, PWM_16b_3, CYHAL_PIN_OUT_FUNCTION(P11_5_TCPWM1_LINE_COMPL3)}, - {P12_1, PWM_16b_4, CYHAL_PIN_OUT_FUNCTION(P12_1_TCPWM1_LINE_COMPL4)}, - {P12_3, PWM_16b_5, CYHAL_PIN_OUT_FUNCTION(P12_3_TCPWM1_LINE_COMPL5)}, - {P12_5, PWM_16b_6, CYHAL_PIN_OUT_FUNCTION(P12_5_TCPWM1_LINE_COMPL6)}, - {P12_7, PWM_16b_7, CYHAL_PIN_OUT_FUNCTION(P12_7_TCPWM1_LINE_COMPL7)}, - {P13_1, PWM_16b_8, CYHAL_PIN_OUT_FUNCTION(P13_1_TCPWM1_LINE_COMPL8)}, - {P13_3, PWM_16b_9, CYHAL_PIN_OUT_FUNCTION(P13_3_TCPWM1_LINE_COMPL9)}, - {P13_5, PWM_16b_10, CYHAL_PIN_OUT_FUNCTION(P13_5_TCPWM1_LINE_COMPL10)}, - {P13_7, PWM_16b_11, CYHAL_PIN_OUT_FUNCTION(P13_7_TCPWM1_LINE_COMPL11)}, - // 32-bit PWM outputs - {P0_0, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P0_0_TCPWM0_LINE0)}, - {P0_2, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P0_2_TCPWM0_LINE1)}, - {P0_4, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P0_4_TCPWM0_LINE2)}, - {P1_0, PWM_32b_3, CYHAL_PIN_OUT_FUNCTION(P1_0_TCPWM0_LINE3)}, - {P1_2, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P1_2_TCPWM0_LINE4)}, - {P1_4, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P1_4_TCPWM0_LINE5)}, - {P2_0, PWM_32b_6, CYHAL_PIN_OUT_FUNCTION(P2_0_TCPWM0_LINE6)}, - {P2_2, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P2_2_TCPWM0_LINE7)}, - {P2_4, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P2_4_TCPWM0_LINE0)}, - {P2_6, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P2_6_TCPWM0_LINE1)}, - {P3_0, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P3_0_TCPWM0_LINE2)}, - {P3_2, PWM_32b_3, CYHAL_PIN_OUT_FUNCTION(P3_2_TCPWM0_LINE3)}, - {P3_4, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P3_4_TCPWM0_LINE4)}, - {P4_0, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P4_0_TCPWM0_LINE5)}, - {P5_0, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P5_0_TCPWM0_LINE4)}, - {P5_2, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P5_2_TCPWM0_LINE5)}, - {P5_4, PWM_32b_6, CYHAL_PIN_OUT_FUNCTION(P5_4_TCPWM0_LINE6)}, - {P5_6, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P5_6_TCPWM0_LINE7)}, - {P6_0, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P6_0_TCPWM0_LINE0)}, - {P6_2, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P6_2_TCPWM0_LINE1)}, - {P6_4, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P6_4_TCPWM0_LINE2)}, - {P6_6, PWM_32b_3, CYHAL_PIN_OUT_FUNCTION(P6_6_TCPWM0_LINE3)}, - {P7_0, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P7_0_TCPWM0_LINE4)}, - {P7_2, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P7_2_TCPWM0_LINE5)}, - {P7_4, PWM_32b_6, CYHAL_PIN_OUT_FUNCTION(P7_4_TCPWM0_LINE6)}, - {P7_6, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P7_6_TCPWM0_LINE7)}, - {P8_0, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P8_0_TCPWM0_LINE0)}, - {P8_2, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P8_2_TCPWM0_LINE1)}, - {P8_4, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P8_4_TCPWM0_LINE2)}, - {P8_6, PWM_32b_3, CYHAL_PIN_OUT_FUNCTION(P8_6_TCPWM0_LINE3)}, - {P9_0, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P9_0_TCPWM0_LINE4)}, - {P9_2, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P9_2_TCPWM0_LINE5)}, - {P9_4, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P9_4_TCPWM0_LINE7)}, - {P9_6, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P9_6_TCPWM0_LINE0)}, - {P10_0, PWM_32b_6, CYHAL_PIN_OUT_FUNCTION(P10_0_TCPWM0_LINE6)}, - {P10_2, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P10_2_TCPWM0_LINE7)}, - {P10_4, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P10_4_TCPWM0_LINE0)}, - {P10_6, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P10_6_TCPWM0_LINE1)}, - {P11_0, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P11_0_TCPWM0_LINE1)}, - {P11_2, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P11_2_TCPWM0_LINE2)}, - {P11_4, PWM_32b_3, CYHAL_PIN_OUT_FUNCTION(P11_4_TCPWM0_LINE3)}, - {P12_0, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P12_0_TCPWM0_LINE4)}, - {P12_2, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P12_2_TCPWM0_LINE5)}, - {P12_4, PWM_32b_6, CYHAL_PIN_OUT_FUNCTION(P12_4_TCPWM0_LINE6)}, - {P12_6, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P12_6_TCPWM0_LINE7)}, - {P13_0, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P13_0_TCPWM0_LINE0)}, - {P13_2, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P13_2_TCPWM0_LINE1)}, - {P13_4, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P13_4_TCPWM0_LINE2)}, - {P13_6, PWM_32b_3, CYHAL_PIN_OUT_FUNCTION(P13_6_TCPWM0_LINE3)}, - // 32-bit PWM inverted outputs - {P0_1, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P0_1_TCPWM0_LINE_COMPL0)}, - {P0_3, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P0_3_TCPWM0_LINE_COMPL1)}, - {P0_5, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P0_5_TCPWM0_LINE_COMPL2)}, - {P1_1, PWM_32b_3, CYHAL_PIN_OUT_FUNCTION(P1_1_TCPWM0_LINE_COMPL3)}, - {P1_3, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P1_3_TCPWM0_LINE_COMPL4)}, - {P1_5, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P1_5_TCPWM0_LINE_COMPL5)}, - {P2_1, PWM_32b_6, CYHAL_PIN_OUT_FUNCTION(P2_1_TCPWM0_LINE_COMPL6)}, - {P2_3, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P2_3_TCPWM0_LINE_COMPL7)}, - {P2_5, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P2_5_TCPWM0_LINE_COMPL0)}, - {P2_7, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P2_7_TCPWM0_LINE_COMPL1)}, - {P3_1, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P3_1_TCPWM0_LINE_COMPL2)}, - {P3_3, PWM_32b_3, CYHAL_PIN_OUT_FUNCTION(P3_3_TCPWM0_LINE_COMPL3)}, - {P3_5, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P3_5_TCPWM0_LINE_COMPL4)}, - {P4_1, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P4_1_TCPWM0_LINE_COMPL5)}, - {P5_1, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P5_1_TCPWM0_LINE_COMPL4)}, - {P5_3, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P5_3_TCPWM0_LINE_COMPL5)}, - {P5_5, PWM_32b_6, CYHAL_PIN_OUT_FUNCTION(P5_5_TCPWM0_LINE_COMPL6)}, - {P5_7, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P5_7_TCPWM0_LINE_COMPL7)}, - {P6_1, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P6_1_TCPWM0_LINE_COMPL0)}, - {P6_3, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P6_3_TCPWM0_LINE_COMPL1)}, - {P6_5, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P6_5_TCPWM0_LINE_COMPL2)}, - {P6_7, PWM_32b_3, CYHAL_PIN_OUT_FUNCTION(P6_7_TCPWM0_LINE_COMPL3)}, - {P7_1, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P7_1_TCPWM0_LINE_COMPL4)}, - {P7_3, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P7_3_TCPWM0_LINE_COMPL5)}, - {P7_5, PWM_32b_6, CYHAL_PIN_OUT_FUNCTION(P7_5_TCPWM0_LINE_COMPL6)}, - {P7_7, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P7_7_TCPWM0_LINE_COMPL7)}, - {P8_1, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P8_1_TCPWM0_LINE_COMPL0)}, - {P8_3, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P8_3_TCPWM0_LINE_COMPL1)}, - {P8_5, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P8_5_TCPWM0_LINE_COMPL2)}, - {P8_7, PWM_32b_3, CYHAL_PIN_OUT_FUNCTION(P8_7_TCPWM0_LINE_COMPL3)}, - {P9_1, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P9_1_TCPWM0_LINE_COMPL4)}, - {P9_3, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P9_3_TCPWM0_LINE_COMPL5)}, - {P9_5, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P9_5_TCPWM0_LINE_COMPL7)}, - {P9_7, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P9_7_TCPWM0_LINE_COMPL0)}, - {P10_1, PWM_32b_6, CYHAL_PIN_OUT_FUNCTION(P10_1_TCPWM0_LINE_COMPL6)}, - {P10_3, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P10_3_TCPWM0_LINE_COMPL7)}, - {P10_5, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P10_5_TCPWM0_LINE_COMPL0)}, - {P10_7, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P10_7_TCPWM0_LINE_COMPL1)}, - {P11_1, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P11_1_TCPWM0_LINE_COMPL1)}, - {P11_3, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P11_3_TCPWM0_LINE_COMPL2)}, - {P11_5, PWM_32b_3, CYHAL_PIN_OUT_FUNCTION(P11_5_TCPWM0_LINE_COMPL3)}, - {P12_1, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P12_1_TCPWM0_LINE_COMPL4)}, - {P12_3, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P12_3_TCPWM0_LINE_COMPL5)}, - {P12_5, PWM_32b_6, CYHAL_PIN_OUT_FUNCTION(P12_5_TCPWM0_LINE_COMPL6)}, - {P12_7, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P12_7_TCPWM0_LINE_COMPL7)}, - {P13_1, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P13_1_TCPWM0_LINE_COMPL0)}, - {P13_3, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P13_3_TCPWM0_LINE_COMPL1)}, - {P13_5, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P13_5_TCPWM0_LINE_COMPL2)}, - {P13_7, PWM_32b_3, CYHAL_PIN_OUT_FUNCTION(P13_7_TCPWM0_LINE_COMPL3)}, - {NC, NC, 0} -}; -#endif // DEVICE_PWMOUT - -#if DEVICE_ANALOGIN -const PinMap PinMap_ADC[] = { - {P10_0, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, - {P10_1, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, - {P10_2, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, - {P10_3, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, - {P10_4, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, - {P10_5, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, - {P10_6, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, - {P10_7, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, - {NC, NC, 0} -}; -#endif // DEVICE_ANALOGIN - -#if DEVICE_ANALOGOUT -const PinMap PinMap_DAC[] = { - {P9_6, DAC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, - {NC, NC, 0} -}; -#endif // DEVICE_ANALOGIN - -#if DEVICE_QSPI -const PinMap PinMap_QSPI_SCLK[] = { - {P11_7, QSPI_0, CY_GPIO_CFG_CREATE(P11_7_SMIF_SPI_CLK, CY_GPIO_DM_STRONG_IN_OFF)}, - {NC, NC, 0}, -}; -const PinMap PinMap_QSPI_SSEL[] = { - {P11_2, QSPI_0, CY_GPIO_CFG_CREATE(P11_2_SMIF_SPI_SELECT0, CY_GPIO_DM_STRONG_IN_OFF)}, - {NC, NC, 0}, -}; -const PinMap PinMap_QSPI_DATA0[] = { - {P11_6, QSPI_0, CY_GPIO_CFG_CREATE(P11_6_SMIF_SPI_DATA0, CY_GPIO_DM_STRONG)}, - {NC, NC, 0}, -}; -const PinMap PinMap_QSPI_DATA1[] = { - {P11_5, QSPI_0, CY_GPIO_CFG_CREATE(P11_5_SMIF_SPI_DATA1, CY_GPIO_DM_STRONG)}, - {NC, NC, 0}, -}; -const PinMap PinMap_QSPI_DATA2[] = { - {P11_4, QSPI_0, CY_GPIO_CFG_CREATE(P11_4_SMIF_SPI_DATA2, CY_GPIO_DM_STRONG)}, - {NC, NC, 0}, -}; -const PinMap PinMap_QSPI_DATA3[] = { - {P11_3, QSPI_0, CY_GPIO_CFG_CREATE(P11_3_SMIF_SPI_DATA3, CY_GPIO_DM_STRONG)}, - {NC, NC, 0}, -}; -#endif // DEVICE_QSPI diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/cybsp.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/cybsp.c deleted file mode 100644 index acd73e3ebd..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/cybsp.c +++ /dev/null @@ -1,134 +0,0 @@ -/***************************************************************************//** -* \file cybsp.c -* -* Description: -* Provides initialization code for starting up the hardware contained on the -* Cypress board. -* -******************************************************************************** -* \copyright -* Copyright 2018-2020 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ - -#include -#include "cy_syspm.h" -#include "cy_sysclk.h" -#include "cybsp.h" -#if defined(CY_USING_HAL) -#include "cyhal_hwmgr.h" -#include "cyhal_syspm.h" -#endif - -#if defined(__cplusplus) -extern "C" { -#endif - -/* The sysclk deep sleep callback is recommended to be the last callback that -* is executed before entry into deep sleep mode and the first one upon -* exit the deep sleep mode. -* Doing so minimizes the time spent on low power mode entry and exit. -*/ -#ifndef CYBSP_SYSCLK_PM_CALLBACK_ORDER - #define CYBSP_SYSCLK_PM_CALLBACK_ORDER (255u) -#endif - -#if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL) -static cyhal_sdio_t sdio_obj; - -cyhal_sdio_t* cybsp_get_wifi_sdio_obj(void) -{ - return &sdio_obj; -} -#endif - -/** - * Registers a power management callback that prepares the clock system - * for entering deep sleep mode and restore the clocks upon wakeup from deep sleep. - * NOTE: This is called automatically as part of \ref cybsp_init - */ -static cy_rslt_t cybsp_register_sysclk_pm_callback(void) -{ - cy_rslt_t result = CY_RSLT_SUCCESS; - static cy_stc_syspm_callback_params_t cybsp_sysclk_pm_callback_param = {NULL, NULL}; - static cy_stc_syspm_callback_t cybsp_sysclk_pm_callback = { - .callback = &Cy_SysClk_DeepSleepCallback, - .type = CY_SYSPM_DEEPSLEEP, - .callbackParams = &cybsp_sysclk_pm_callback_param, - .order = CYBSP_SYSCLK_PM_CALLBACK_ORDER - }; - - if (!Cy_SysPm_RegisterCallback(&cybsp_sysclk_pm_callback)) - { - result = CYBSP_RSLT_ERR_SYSCLK_PM_CALLBACK; - } - return result; -} - -cy_rslt_t cybsp_init(void) -{ - /* Setup hardware manager to track resource usage then initialize all system (clock/power) board configuration */ -#if defined(CY_USING_HAL) - cy_rslt_t result = cyhal_hwmgr_init(); - - if (CY_RSLT_SUCCESS == result) - { - result = cyhal_syspm_init(); - } -#else - cy_rslt_t result = CY_RSLT_SUCCESS; -#endif - -#if defined(COMPONENT_BSP_DESIGN_MODUS) || defined(COMPONENT_CUSTOM_DESIGN_MODUS) - init_cycfg_all(); -#endif - - if (CY_RSLT_SUCCESS == result) - { - result = cybsp_register_sysclk_pm_callback(); - } - -#if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL) - /* Initialize SDIO interface. This must be done before other HAL API calls as some SDIO implementations require - * specific peripheral instances. - * NOTE: The full WiFi interface still needs to be initialized via cybsp_wifi_init_primary(). This is typically - * done when starting up WiFi. - */ - if (CY_RSLT_SUCCESS == result) - { - /* Reserves: CYBSP_WIFI_SDIO, CYBSP_WIFI_SDIO_D0, CYBSP_WIFI_SDIO_D1, CYBSP_WIFI_SDIO_D2, CYBSP_WIFI_SDIO_D3 - * CYBSP_WIFI_SDIO_CMD and CYBSP_WIFI_SDIO_CLK. - */ - result = cyhal_sdio_init( - &sdio_obj, - CYBSP_WIFI_SDIO_CMD, - CYBSP_WIFI_SDIO_CLK, - CYBSP_WIFI_SDIO_D0, - CYBSP_WIFI_SDIO_D1, - CYBSP_WIFI_SDIO_D2, - CYBSP_WIFI_SDIO_D3); - } -#endif /* defined(CYBSP_WIFI_CAPABLE) */ - - /* CYHAL_HWMGR_RSLT_ERR_INUSE error code could be returned if any needed for BSP resource was reserved by - * user previously. Please review the Device Configurator (design.modus) and the BSP reservation list - * (cyreservedresources.list) to make sure no resources are reserved by both. - */ - return result; -} - -#if defined(__cplusplus) -} -#endif diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/cybsp.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/cybsp.h deleted file mode 100644 index 1ec5ff5a60..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/cybsp.h +++ /dev/null @@ -1,73 +0,0 @@ -/***************************************************************************//** -* \file cybsp.h -* -* \brief -* Basic API for setting up boards containing a Cypress MCU. -* -******************************************************************************** -* \copyright -* Copyright 2018-2020 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ - -#pragma once - -#include "cy_result.h" -#include "cybsp_types.h" -#if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL) -#include "cyhal_sdio.h" -#endif - -#if defined(__cplusplus) -extern "C" { -#endif - -/** -* \addtogroup group_bsp_macros Macros -* \{ -*/ - -/** Failed to configure sysclk power management callback */ -#define CYBSP_RSLT_ERR_SYSCLK_PM_CALLBACK (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_BSP, 0)) - -/** \} group_bsp_macros */ - -/** -* \addtogroup group_bsp_functions Functions -* \{ -*/ - -/** - * \brief Initialize all hardware on the board - * \returns CY_RSLT_SUCCESS if the board is sucessfully initialized, if there is - * a problem initializing any hardware it returns an error code specific - * to the hardware module that had a problem. - */ -cy_rslt_t cybsp_init(void); - -#if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL) -/** - * \brief Get the initialized sdio object used for communicating with the WiFi Chip. - * \note This function should only be called after cybsp_init(); - * \returns The initialized sdio object. - */ -cyhal_sdio_t* cybsp_get_wifi_sdio_obj(void); -#endif /* defined(CYBSP_WIFI_CAPABLE) */ - -/** \} group_bsp_functions */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/cybsp_types.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/cybsp_types.h deleted file mode 100644 index 9d42d4735c..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/cybsp_types.h +++ /dev/null @@ -1,227 +0,0 @@ -/***************************************************************************//** -* \file CY8CPROTO-064-SB/cybsp_types.h -* -* Description: -* Provides APIs for interacting with the hardware contained on the Cypress -* CY8CPROTO-064-SB kit. -* -******************************************************************************** -* \copyright -* Copyright 2018-2020 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ - -#pragma once - -#if defined(CY_USING_HAL) -#include "cyhal_pin_package.h" -#endif -#if defined(COMPONENT_BSP_DESIGN_MODUS) || defined(COMPONENT_CUSTOM_DESIGN_MODUS) -#include "cycfg.h" -#endif - -#if defined(__cplusplus) -extern "C" { -#endif - -/** -* \addtogroup group_bsp_settings BSP Settings -* \{ -* -*
Peripheral Default HAL Settings:
-* | Resource | Parameter | Value | Remarks | -* | :------: | :-------: | :---: | :------ | -* | ADC | VREF | 1.2 V | | -* | ^ | Measurement type | Single Ended | | -* | ^ | Input voltage range | 0 to 2.4 V (0 to 2*VREF) | | -* | ^ | Output range | 0x000 to 0x7FF | | -* | DAC | Reference source | VDDA | | -* | ^ | Input range | 0x000 to 0xFFF | | -* | ^ | Output range | 0 to VDDA | | -* | ^ | Output type | Unbuffered output | | -* | I2C | Role | Master | Configurable to slave mode through HAL function | -* | ^ | Data rate | 100 kbps | Configurable through HAL function | -* | ^ | Drive mode of SCL & SDA pins | Open Drain (drives low) | External pull-up resistors are required | -* | LpTimer | Uses WCO (32.768 kHz) as clock source & MCWDT as counter. 1 count = 1/32768 second or 32768 counts = 1 second. ||| -* | SPI | Data rate | 100 kpbs | Configurable through HAL function | -* | ^ | Slave select polarity | Active low | | -* | UART | Flow control | No flow control | Configurable through HAL function | -* | ^ | Data format | 8N1 | Configurable through HAL function | -* | ^ | Baud rate | 115200 | Configurable through HAL function | -*/ -/** \} group_bsp_settings */ - -/** -* \addtogroup group_bsp_pin_state Pin States -* \{ -*/ - -/** Pin state for the LED on. */ -#ifndef CYBSP_LED_STATE_ON -#define CYBSP_LED_STATE_ON (0U) -#endif -/** Pin state for the LED off. */ -#ifndef CYBSP_LED_STATE_OFF -#define CYBSP_LED_STATE_OFF (1U) -#endif - -/** Pin state for when a button is pressed. */ -#ifndef CYBSP_BTN_PRESSED -#define CYBSP_BTN_PRESSED (0U) -#endif -/** Pin state for when a button is released. */ -#ifndef CYBSP_BTN_OFF -#define CYBSP_BTN_OFF (1U) -#endif - -/** \} group_bsp_pin_state */ - -#if defined(CY_USING_HAL) - -/** -* \addtogroup group_bsp_pins Pin Mappings -* \{ -*/ - -/** -* \addtogroup group_bsp_pins_led LED Pins -* \{ -*/ - -/** LED 3; User LED1 */ -#ifndef CYBSP_LED3 -#define CYBSP_LED3 (P13_7) -#endif -/** LED 4; User LED2 */ -#ifndef CYBSP_LED4 -#define CYBSP_LED4 (P1_5) -#endif - -/** LED 3; User LED1 */ -#ifndef CYBSP_USER_LED1 -#define CYBSP_USER_LED1 (CYBSP_LED3) -#endif -/** LED 4; User LED2 */ -#ifndef CYBSP_USER_LED2 -#define CYBSP_USER_LED2 (CYBSP_LED4) -#endif -/** LED 3; User LED1 */ -#ifndef CYBSP_USER_LED -#define CYBSP_USER_LED (CYBSP_USER_LED1) -#endif - -/** \} group_bsp_pins_led */ - -/** -* \addtogroup group_bsp_pins_btn Button Pins -* \{ -*/ - -/** Switch 2; User Button 1 */ -#ifndef CYBSP_SW2 -#define CYBSP_SW2 (P0_4) -#endif - -/** Switch 2; User Button 1 */ -#ifndef CYBSP_USER_BTN1 -#define CYBSP_USER_BTN1 (CYBSP_SW2) -#endif -/** Switch 2; User Button 1 */ -#ifndef CYBSP_USER_BTN -#define CYBSP_USER_BTN (CYBSP_USER_BTN1) -#endif - -/** \} group_bsp_pins_btn */ - - -/** -* \addtogroup group_bsp_pins_comm Communication Pins -* \{ -*/ - -/** Pin: UART RX */ -#ifndef CYBSP_UART_RX -#define CYBSP_UART_RX (P5_0) -#endif -/** Pin: UART TX */ -#ifndef CYBSP_UART_TX -#define CYBSP_UART_TX (P5_1) -#endif - -/** Pin: UART RX */ -#ifndef CYBSP_DEBUG_UART_RX -#define CYBSP_DEBUG_UART_RX (P5_0) -#endif -/** Pin: UART TX */ -#ifndef CYBSP_DEBUG_UART_TX -#define CYBSP_DEBUG_UART_TX (P5_1) -#endif - -/** Pin: I2C SCL */ -#ifndef CYBSP_I2C_SCL -#define CYBSP_I2C_SCL (P6_0) -#endif -/** Pin: I2C SDA */ -#ifndef CYBSP_I2C_SDA -#define CYBSP_I2C_SDA (P6_1) -#endif - -/** Pin: SWDIO */ -#ifndef CYBSP_SWDIO -#define CYBSP_SWDIO (P6_6) -#endif -/** Pin: SWDCK */ -#ifndef CYBSP_SWDCK -#define CYBSP_SWDCK (P6_7) -#endif -/** Pin: SWO */ -#ifndef CYBSP_SWO -#define CYBSP_SWO (P6_4) -#endif - -/** Pin: QUAD SPI SS */ -#ifndef CYBSP_QSPI_SS -#define CYBSP_QSPI_SS (P11_2) -#endif -/** Pin: QUAD SPI D3 */ -#ifndef CYBSP_QSPI_D3 -#define CYBSP_QSPI_D3 (P11_3) -#endif -/** Pin: QUAD SPI D2 */ -#ifndef CYBSP_QSPI_D2 -#define CYBSP_QSPI_D2 (P11_4) -#endif -/** Pin: QUAD SPI D1 */ -#ifndef CYBSP_QSPI_D1 -#define CYBSP_QSPI_D1 (P11_5) -#endif -/** Pin: QUAD SPI D0 */ -#ifndef CYBSP_QSPI_D0 -#define CYBSP_QSPI_D0 (P11_6) -#endif -/** Pin: QUAD SPI SCK */ -#ifndef CYBSP_QSPI_SCK -#define CYBSP_QSPI_SCK (P11_7) -#endif - -/** \} group_bsp_pins_comm */ - -/** \} group_bsp_pins */ - -#endif /* defined(CY_USING_HAL) */ - -#if defined(__cplusplus) -} -#endif diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xx7_cm0plus.sct b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xx7_cm0plus.sct deleted file mode 100644 index 548323c5b7..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xx7_cm0plus.sct +++ /dev/null @@ -1,307 +0,0 @@ -#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0 -; The first line specifies a preprocessor command that the linker invokes -; to pass a scatter file through a C preprocessor. - -;******************************************************************************* -;* \file cyb06xx7_cm0plus.sct -;* \version 2.70.1 -;* -;* Linker file for the ARMCC. -;* -;* The main purpose of the linker script is to describe how the sections in the -;* input files should be mapped into the output file, and to control the memory -;* layout of the output file. -;* -;* \note The entry point location is fixed and starts at 0x10000000. The valid -;* application image should be placed there. -;* -;* \note The linker files included with the PDL template projects must be -;* generic and handle all common use cases. Your project may not use every -;* section defined in the linker files. In that case you may see the warnings -;* during the build process: L6314W (no section matches pattern) and/or L6329W -;* (pattern only matches removed unused sections). In your project, you can -;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to -;* the linker, simply comment out or remove the relevant code in the linker -;* file. -;* -;******************************************************************************* -;* \copyright -;* Copyright 2016-2020 Cypress Semiconductor Corporation -;* SPDX-License-Identifier: Apache-2.0 -;* -;* Licensed under the Apache License, Version 2.0 (the "License"); -;* you may not use this file except in compliance with the License. -;* You may obtain a copy of the License at -;* -;* http://www.apache.org/licenses/LICENSE-2.0 -;* -;* Unless required by applicable law or agreed to in writing, software -;* distributed under the License is distributed on an "AS IS" BASIS, -;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -;* See the License for the specific language governing permissions and -;* limitations under the License. -;******************************************************************************/ - -#if !defined(MBED_ROM_START) - #define MBED_ROM_START 0x10000000 -#endif - -;* MBED_APP_START is being used by the bootloader build script and -;* will be calculate by the system. Without bootloader the MBED_APP_START -;* is equal to MBED_ROM_START -;* -#if !defined(MBED_APP_START) - #define MBED_APP_START MBED_ROM_START -#endif - -#if !defined(MBED_ROM_SIZE) - #define MBED_ROM_SIZE 0x80000 -#endif - -;* MBED_APP_SIZE is being used by the bootloader build script and -;* will be calculate by the system. Without bootloader the MBED_APP_SIZE -;* is equal to MBED_ROM_SIZE -;* -#if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE MBED_ROM_SIZE -#endif - -#if !defined(MBED_RAM_START) - #define MBED_RAM_START 0x08000000 -#endif - -#if !defined(MBED_RAM_SIZE) - #define MBED_RAM_SIZE 0x00010000 -#endif - -#if !defined(MBED_PUBLIC_RAM_SIZE) - #define MBED_PUBLIC_RAM_SIZE 0x200 -#endif - -; The size of the stack section at the end of CM0+ SRAM -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -#define STACK_SIZE MBED_BOOT_STACK_SIZE - -#if !defined(MBED_PUBLIC_RAM_START) - #define MBED_PUBLIC_RAM_START (MBED_RAM_START + MBED_RAM_SIZE - STACK_SIZE - MBED_PUBLIC_RAM_SIZE) -#endif - -; The defines below describe the location and size of blocks of memory in the target. -; Use these defines to specify the memory regions available for allocation. - -; The following defines control RAM and flash memory allocation for the CM0+ core. -; You can change the memory allocation by editing the RAM and Flash defines. -; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat', -; where 'xx' is the device group; for example, 'cyb06xx7_cm4_dual.scat'. -; RAM -#define RAM_START MBED_RAM_START -#define RAM_SIZE MBED_RAM_SIZE -; Public RAM -#define PUBLIC_RAM_START MBED_PUBLIC_RAM_START -#define PUBLIC_RAM_SIZE MBED_PUBLIC_RAM_SIZE -; Flash -#define FLASH_START MBED_APP_START -#define FLASH_SIZE MBED_APP_SIZE - -; The size of the MCU boot header area at the start of FLASH -#define BOOT_HEADER_SIZE 0x00000400 - -; The following defines describe a 32K flash region used for EEPROM emulation. -; This region can also be used as the general purpose flash. -; You can assign sections to this memory region for only one of the cores. -; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. -; Therefore, repurposing this memory region will prevent such middleware from operation. -#define EM_EEPROM_START 0x14000000 -#define EM_EEPROM_SIZE 0x8000 - -; The following defines describe device specific memory regions and must not be changed. -; Supervisory flash: User data -#define SFLASH_USER_DATA_START 0x16000800 -#define SFLASH_USER_DATA_SIZE 0x00000800 - -; Supervisory flash: Normal Access Restrictions (NAR) -#define SFLASH_NAR_START 0x16001A00 -#define SFLASH_NAR_SIZE 0x00000200 - -; Supervisory flash: Public Key -#define SFLASH_PUBLIC_KEY_START 0x16005A00 -#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 - -; Supervisory flash: Table of Content # 2 -#define SFLASH_TOC_2_START 0x16007C00 -#define SFLASH_TOC_2_SIZE 0x00000200 - -; Supervisory flash: Table of Content # 2 Copy -#define SFLASH_RTOC_2_START 0x16007E00 -#define SFLASH_RTOC_2_SIZE 0x00000200 - -; External memory -#define XIP_START 0x18000000 -#define XIP_SIZE 0x08000000 - -; eFuse -#define EFUSE_START 0x90700000 -#define EFUSE_SIZE 0x100000 - - -; Cortex-M0+ application flash area -LR_IROM1 (FLASH_START + BOOT_HEADER_SIZE) (FLASH_SIZE - BOOT_HEADER_SIZE - 0x8000) -{ - ER_FLASH_VECTORS +0 - { - * (RESET, +FIRST) - } - - ER_FLASH_CODE +0 FIXED - { - * (InRoot$$Sections) - * (+RO) - } - - ER_RAM_VECTORS RAM_START UNINIT - { - * (RESET_RAM, +FIRST) - } - - RW_RAM_DATA +0 - { - * (.cy_ramfunc) - * (+RW, +ZI) - } - - ; Place variables in the section that should not be initialized during the - ; device startup. - RW_IRAM1 +0 UNINIT - { - * (.noinit) - } - - RW_IRAM2 PUBLIC_RAM_START UNINIT - { - * (.cy_sharedmem) - } - - ; Application heap area (HEAP) - ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM2) - { - } - - ; Stack region growing down - ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE - { - } -} - - -; Emulated EEPROM Flash area -LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE -{ - .cy_em_eeprom +0 - { - * (.cy_em_eeprom) - } -} - -; Supervisory flash: User data -LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE -{ - .cy_sflash_user_data +0 - { - * (.cy_sflash_user_data) - } -} - -; Supervisory flash: Normal Access Restrictions (NAR) -LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE -{ - .cy_sflash_nar +0 - { - * (.cy_sflash_nar) - } -} - -; Supervisory flash: Public Key -LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE -{ - .cy_sflash_public_key +0 - { - * (.cy_sflash_public_key) - } -} - -; Supervisory flash: Table of Content # 2 -LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE -{ - .cy_toc_part2 +0 - { - * (.cy_toc_part2) - } -} - -; Supervisory flash: Table of Content # 2 Copy -LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE -{ - .cy_rtoc_part2 +0 - { - * (.cy_rtoc_part2) - } -} - - -; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. -LR_EROM XIP_START XIP_SIZE -{ - .cy_xip +0 - { - * (.cy_xip) - } -} - - -; eFuse -LR_EFUSE EFUSE_START EFUSE_SIZE -{ - .cy_efuse +0 - { - * (.cy_efuse) - } -} - - -; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. -CYMETA 0x90500000 -{ - .cymeta +0 { * (.cymeta) } -} - -/* The following symbols used by the cymcuelftool. */ -/* Flash */ -#define __cy_memory_0_start 0x10000000 -#define __cy_memory_0_length 0x000D0000 -#define __cy_memory_0_row_size 0x200 - -/* Emulated EEPROM Flash area */ -#define __cy_memory_1_start 0x14000000 -#define __cy_memory_1_length 0x8000 -#define __cy_memory_1_row_size 0x200 - -/* Supervisory Flash */ -#define __cy_memory_2_start 0x16000000 -#define __cy_memory_2_length 0x8000 -#define __cy_memory_2_row_size 0x200 - -/* XIP */ -#define __cy_memory_3_start 0x18000000 -#define __cy_memory_3_length 0x08000000 -#define __cy_memory_3_row_size 0x200 - -/* eFuse */ -#define __cy_memory_4_start 0x90700000 -#define __cy_memory_4_length 0x100000 -#define __cy_memory_4_row_size 1 - - -/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_01_cm0plus.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_01_cm0plus.S deleted file mode 100644 index 09d6b4ccfe..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_01_cm0plus.S +++ /dev/null @@ -1,261 +0,0 @@ -;/**************************************************************************//** -; * @file startup_psoc6_01_cm0plus.S -; * @brief CMSIS Core Device Startup File for -; * ARMCM0plus Device Series -; * @version V5.00 -; * @date 02. March 2016 -; ******************************************************************************/ -;/* -; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. -; * -; * SPDX-License-Identifier: Apache-2.0 -; * -; * Licensed under the Apache License, Version 2.0 (the License); you may -; * not use this file except in compliance with the License. -; * You may obtain a copy of the License at -; * -; * www.apache.org/licenses/LICENSE-2.0 -; * -; * Unless required by applicable law or agreed to in writing, software -; * distributed under the License is distributed on an AS IS BASIS, WITHOUT -; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -; * See the License for the specific language governing permissions and -; * limitations under the License. -; */ - - PRESERVE8 - THUMB - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| - -__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack - DCD Reset_Handler ; Reset Handler - - DCD 0x0000000D ; NMI Handler located at ROM code - DCD HardFault_Handler ; Hard Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External interrupts Description - DCD NvicMux0_IRQHandler ; CM0+ NVIC Mux input 0 - DCD NvicMux1_IRQHandler ; CM0+ NVIC Mux input 1 - DCD NvicMux2_IRQHandler ; CM0+ NVIC Mux input 2 - DCD NvicMux3_IRQHandler ; CM0+ NVIC Mux input 3 - DCD NvicMux4_IRQHandler ; CM0+ NVIC Mux input 4 - DCD NvicMux5_IRQHandler ; CM0+ NVIC Mux input 5 - DCD NvicMux6_IRQHandler ; CM0+ NVIC Mux input 6 - DCD NvicMux7_IRQHandler ; CM0+ NVIC Mux input 7 - DCD NvicMux8_IRQHandler ; CM0+ NVIC Mux input 8 - DCD NvicMux9_IRQHandler ; CM0+ NVIC Mux input 9 - DCD NvicMux10_IRQHandler ; CM0+ NVIC Mux input 10 - DCD NvicMux11_IRQHandler ; CM0+ NVIC Mux input 11 - DCD NvicMux12_IRQHandler ; CM0+ NVIC Mux input 12 - DCD NvicMux13_IRQHandler ; CM0+ NVIC Mux input 13 - DCD NvicMux14_IRQHandler ; CM0+ NVIC Mux input 14 - DCD NvicMux15_IRQHandler ; CM0+ NVIC Mux input 15 - DCD NvicMux16_IRQHandler ; CM0+ NVIC Mux input 16 - DCD NvicMux17_IRQHandler ; CM0+ NVIC Mux input 17 - DCD NvicMux18_IRQHandler ; CM0+ NVIC Mux input 18 - DCD NvicMux19_IRQHandler ; CM0+ NVIC Mux input 19 - DCD NvicMux20_IRQHandler ; CM0+ NVIC Mux input 20 - DCD NvicMux21_IRQHandler ; CM0+ NVIC Mux input 21 - DCD NvicMux22_IRQHandler ; CM0+ NVIC Mux input 22 - DCD NvicMux23_IRQHandler ; CM0+ NVIC Mux input 23 - DCD NvicMux24_IRQHandler ; CM0+ NVIC Mux input 24 - DCD NvicMux25_IRQHandler ; CM0+ NVIC Mux input 25 - DCD NvicMux26_IRQHandler ; CM0+ NVIC Mux input 26 - DCD NvicMux27_IRQHandler ; CM0+ NVIC Mux input 27 - DCD NvicMux28_IRQHandler ; CM0+ NVIC Mux input 28 - DCD NvicMux29_IRQHandler ; CM0+ NVIC Mux input 29 - DCD NvicMux30_IRQHandler ; CM0+ NVIC Mux input 30 - DCD NvicMux31_IRQHandler ; CM0+ NVIC Mux input 31 - -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - EXPORT __ramVectors - AREA RESET_RAM, READWRITE, NOINIT -__ramVectors SPACE __Vectors_Size - - - AREA |.text|, CODE, READONLY - - -; Weak function for startup customization -; -; Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) -; because this function is executed as the first instruction in the ResetHandler. -; The PDL is also not initialized to use the proper register offsets. -; The user of this function is responsible for initializing the PDL and resources before using them. -; -Cy_OnResetUser PROC - EXPORT Cy_OnResetUser [WEAK] - BX LR - ENDP - -; Reset Handler -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT __main - - ; Define strong function for startup customization - BL Cy_OnResetUser - - ; Copy vectors from ROM to RAM - LDR r1, =__Vectors - LDR r0, =__ramVectors - LDR r2, =__Vectors_Size -Vectors_Copy - LDR r3, [r1] - STR r3, [r0] - ADDS r0, r0, #4 - ADDS r1, r1, #4 - SUBS r2, r2, #1 - CMP r2, #0 - BNE Vectors_Copy - - ; Update Vector Table Offset Register. */ - LDR r0, =__ramVectors - LDR r1, =0xE000ED08 - STR r0, [r1] - dsb 0xF - - LDR R0, =__main - BLX R0 - - ; Should never get here - B . - - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP - -Cy_SysLib_FaultHandler PROC - EXPORT Cy_SysLib_FaultHandler [WEAK] - B . - ENDP - -HardFault_Handler PROC - EXPORT HardFault_Handler [WEAK] - movs r0, #4 - mov r1, LR - tst r0, r1 - beq L_MSP - mrs r0, PSP - bl L_API_call -L_MSP - mrs r0, MSP -L_API_call - bl Cy_SysLib_FaultHandler - ENDP - -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - EXPORT Default_Handler [WEAK] - EXPORT NvicMux0_IRQHandler [WEAK] - EXPORT NvicMux1_IRQHandler [WEAK] - EXPORT NvicMux2_IRQHandler [WEAK] - EXPORT NvicMux3_IRQHandler [WEAK] - EXPORT NvicMux4_IRQHandler [WEAK] - EXPORT NvicMux5_IRQHandler [WEAK] - EXPORT NvicMux6_IRQHandler [WEAK] - EXPORT NvicMux7_IRQHandler [WEAK] - EXPORT NvicMux8_IRQHandler [WEAK] - EXPORT NvicMux9_IRQHandler [WEAK] - EXPORT NvicMux10_IRQHandler [WEAK] - EXPORT NvicMux11_IRQHandler [WEAK] - EXPORT NvicMux12_IRQHandler [WEAK] - EXPORT NvicMux13_IRQHandler [WEAK] - EXPORT NvicMux14_IRQHandler [WEAK] - EXPORT NvicMux15_IRQHandler [WEAK] - EXPORT NvicMux16_IRQHandler [WEAK] - EXPORT NvicMux17_IRQHandler [WEAK] - EXPORT NvicMux18_IRQHandler [WEAK] - EXPORT NvicMux19_IRQHandler [WEAK] - EXPORT NvicMux20_IRQHandler [WEAK] - EXPORT NvicMux21_IRQHandler [WEAK] - EXPORT NvicMux22_IRQHandler [WEAK] - EXPORT NvicMux23_IRQHandler [WEAK] - EXPORT NvicMux24_IRQHandler [WEAK] - EXPORT NvicMux25_IRQHandler [WEAK] - EXPORT NvicMux26_IRQHandler [WEAK] - EXPORT NvicMux27_IRQHandler [WEAK] - EXPORT NvicMux28_IRQHandler [WEAK] - EXPORT NvicMux29_IRQHandler [WEAK] - EXPORT NvicMux30_IRQHandler [WEAK] - EXPORT NvicMux31_IRQHandler [WEAK] - -NvicMux0_IRQHandler -NvicMux1_IRQHandler -NvicMux2_IRQHandler -NvicMux3_IRQHandler -NvicMux4_IRQHandler -NvicMux5_IRQHandler -NvicMux6_IRQHandler -NvicMux7_IRQHandler -NvicMux8_IRQHandler -NvicMux9_IRQHandler -NvicMux10_IRQHandler -NvicMux11_IRQHandler -NvicMux12_IRQHandler -NvicMux13_IRQHandler -NvicMux14_IRQHandler -NvicMux15_IRQHandler -NvicMux16_IRQHandler -NvicMux17_IRQHandler -NvicMux18_IRQHandler -NvicMux19_IRQHandler -NvicMux20_IRQHandler -NvicMux21_IRQHandler -NvicMux22_IRQHandler -NvicMux23_IRQHandler -NvicMux24_IRQHandler -NvicMux25_IRQHandler -NvicMux26_IRQHandler -NvicMux27_IRQHandler -NvicMux28_IRQHandler -NvicMux29_IRQHandler -NvicMux30_IRQHandler -NvicMux31_IRQHandler - - B . - ENDP - - ALIGN - - END - - -; [] END OF FILE diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cyb06xx7_cm0plus.ld b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cyb06xx7_cm0plus.ld deleted file mode 100644 index 5629824b5d..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cyb06xx7_cm0plus.ld +++ /dev/null @@ -1,471 +0,0 @@ -/***************************************************************************//** -* \file cyb06xx7_cm0plus.ld -* \version 2.70.1 -* -* Linker file for the GNU C compiler. -* -* The main purpose of the linker script is to describe how the sections in the -* input files should be mapped into the output file, and to control the memory -* layout of the output file. -* -* \note The entry point location is fixed and starts at 0x10000000. The valid -* application image should be placed there. -* -* \note The linker files included with the PDL template projects must be generic -* and handle all common use cases. Your project may not use every section -* defined in the linker files. In that case you may see warnings during the -* build process. In your project, you can simply comment out or remove the -* relevant code in the linker file. -* -******************************************************************************** -* \copyright -* Copyright 2016-2020 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ - -OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") -SEARCH_DIR(.) -GROUP(-lgcc -lc -lnosys) -ENTRY(Reset_Handler) - -#if !defined(MBED_ROM_START) - #define MBED_ROM_START 0x10000000 -#endif - -/* MBED_APP_START is being used by the bootloader build script and -* will be calculate by the system. Without bootloader the MBED_APP_START -* is equal to MBED_ROM_START -*/ -#if !defined(MBED_APP_START) - #define MBED_APP_START MBED_ROM_START -#endif - -#if !defined(MBED_ROM_SIZE) - #define MBED_ROM_SIZE 0x80000 -#endif - -/* MBED_APP_SIZE is being used by the bootloader build script and -* will be calculate by the system. Without bootloader the MBED_APP_SIZE -* is equal to MBED_ROM_SIZE -*/ -#if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE MBED_ROM_SIZE -#endif - -#if !defined(MBED_RAM_START) - #define MBED_RAM_START 0x08000000 -#endif - -#if !defined(MBED_RAM_SIZE) - #define MBED_RAM_SIZE 0x00010000 -#endif - -#if !defined(MBED_PUBLIC_RAM_SIZE) - #define MBED_PUBLIC_RAM_SIZE 0x200 -#endif - -/* The size of the stack section at the end of CM0+ SRAM */ -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -STACK_SIZE = MBED_BOOT_STACK_SIZE; - -#if !defined(MBED_PUBLIC_RAM_START) - #define MBED_PUBLIC_RAM_START (MBED_RAM_START + MBED_RAM_SIZE - STACK_SIZE - MBED_PUBLIC_RAM_SIZE) -#endif - -/* The size of the MCU boot header area at the start of FLASH */ -BOOT_HEADER_SIZE = 0x400; - -/* Force symbol to be entered in the output file as an undefined symbol. Doing -* this may, for example, trigger linking of additional modules from standard -* libraries. You may list several symbols for each EXTERN, and you may use -* EXTERN multiple times. This command has the same effect as the -u command-line -* option. -*/ -EXTERN(Reset_Handler) - -/* The MEMORY section below describes the location and size of blocks of memory in the target. -* Use this section to specify the memory regions available for allocation. -*/ -MEMORY -{ - /* The ram and flash regions control RAM and flash memory allocation for the CM0+ core. - * You can change the memory allocation by editing the 'ram' and 'flash' regions. - * Your changes must be aligned with the corresponding memory regions for the CM4 core in 'xx_cm4_dual.ld', - * where 'xx' is the device group; for example, 'cyb06xx7_cm4_dual.ld'. - */ - ram (rwx) : ORIGIN = MBED_RAM_START, LENGTH = MBED_RAM_SIZE - public_ram (rw) : ORIGIN = MBED_PUBLIC_RAM_START, LENGTH = MBED_PUBLIC_RAM_SIZE - flash (rx) : ORIGIN = MBED_APP_START, LENGTH = (MBED_APP_SIZE - 0x8000) - - /* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash. - * You can assign sections to this memory region for only one of the cores. - * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. - * Therefore, repurposing this memory region will prevent such middleware from operation. - */ - em_eeprom (rx) : ORIGIN = 0x14000000, LENGTH = 0x8000 /* 32 KB */ - - /* The following regions define device specific memory regions and must not be changed. */ - sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 /* Supervisory flash: User data */ - sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 /* Supervisory flash: Normal Access Restrictions (NAR) */ - sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 /* Supervisory flash: Public Key */ - sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 */ - sflash_rtoc_2 (rx) : ORIGIN = 0x16007E00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 Copy */ - xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */ - efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */ -} - -/* Library configurations */ -GROUP(libgcc.a libc.a libm.a libnosys.a) - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __Vectors_End - * __Vectors_Size - */ - - -SECTIONS -{ - .cy_app_header : - { - KEEP(*(.cy_app_header)) - } > flash - - /* Cortex-M0+ application flash area */ - .text ORIGIN(flash) + BOOT_HEADER_SIZE : - { - . = ALIGN(4); - __Vectors = . ; - KEEP(*(.vectors)) - . = ALIGN(4); - __Vectors_End = .; - __Vectors_Size = __Vectors_End - __Vectors; - __end__ = .; - - . = ALIGN(4); - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - /* Read-only code (constants). */ - *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*) - - KEEP(*(.eh_frame*)) - } > flash - - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > flash - - __exidx_start = .; - - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > flash - __exidx_end = .; - - - /* To copy multiple ROM to RAM sections, - * uncomment .copy.table section and, - * define __STARTUP_COPY_MULTIPLE in startup_psoc6_01_cm0plus.S */ - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - - /* Copy interrupt vectors from flash to RAM */ - LONG (__Vectors) /* From */ - LONG (__ram_vectors_start__) /* To */ - LONG (__Vectors_End - __Vectors) /* Size */ - - /* Copy data section to RAM */ - LONG (__etext) /* From */ - LONG (__data_start__) /* To */ - LONG (__data_end__ - __data_start__) /* Size */ - - __copy_table_end__ = .; - } > flash - - - /* To clear multiple BSS sections, - * uncomment .zero.table section and, - * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_01_cm0plus.S */ - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - LONG (__bss_start__) - LONG (__bss_end__ - __bss_start__) - __zero_table_end__ = .; - } > flash - - __etext = . ; - - - .ramVectors (NOLOAD) : ALIGN(8) - { - __ram_vectors_start__ = .; - KEEP(*(.ram_vectors)) - __ram_vectors_end__ = .; - } > ram - - - .data __ram_vectors_end__ : AT (__etext) - { - __data_start__ = .; - - *(vtable) - *(.data*) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(4); - - KEEP(*(.cy_ramfunc*)) - . = ALIGN(4); - - __data_end__ = .; - - } > ram - - - /* Place variables in the section that should not be initialized during the - * device startup. - */ - .noinit (NOLOAD) : ALIGN(8) - { - KEEP(*(.noinit)) - } > ram - - - /* The uninitialized global or static variables are placed in this section. - * - * The NOLOAD attribute tells linker that .bss section does not consume - * any space in the image. The NOLOAD attribute changes the .bss type to - * NOBITS, and that makes linker to A) not allocate section in memory, and - * A) put information to clear the section with all zeros during application - * loading. - * - * Without the NOLOAD attribute, the .bss section might get PROGBITS type. - * This makes linker to A) allocate zeroed section in memory, and B) copy - * this section to RAM during application loading. - */ - .bss (NOLOAD): - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > ram - - - .heap (NOLOAD): - { - __HeapBase = .; - __end__ = .; - end = __end__; - KEEP(*(.heap*)) - . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE; - __HeapLimit = .; - } > ram - - - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ - .stack_dummy (NOLOAD): - { - KEEP(*(.stack*)) - } > ram - - - /* Public RAM */ - .cy_sharedmem (NOLOAD): - { - . = ALIGN(4); - KEEP(*(.cy_sharedmem)) - } > public_ram - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(ram) + LENGTH(ram); - __StackLimit = __StackTop - STACK_SIZE; - PROVIDE(__stack = __StackTop); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") - - - /* Emulated EEPROM Flash area */ - .cy_em_eeprom : - { - KEEP(*(.cy_em_eeprom)) - } > em_eeprom - - - /* Supervisory Flash: User data */ - .cy_sflash_user_data : - { - KEEP(*(.cy_sflash_user_data)) - } > sflash_user_data - - - /* Supervisory Flash: Normal Access Restrictions (NAR) */ - .cy_sflash_nar : - { - KEEP(*(.cy_sflash_nar)) - } > sflash_nar - - - /* Supervisory Flash: Public Key */ - .cy_sflash_public_key : - { - KEEP(*(.cy_sflash_public_key)) - } > sflash_public_key - - - /* Supervisory Flash: Table of Content # 2 */ - .cy_toc_part2 : - { - KEEP(*(.cy_toc_part2)) - } > sflash_toc_2 - - - /* Supervisory Flash: Table of Content # 2 Copy */ - .cy_rtoc_part2 : - { - KEEP(*(.cy_rtoc_part2)) - } > sflash_rtoc_2 - - - /* Places the code in the Execute in Place (XIP) section. See the smif driver - * documentation for details. - */ - .cy_xip : - { - KEEP(*(.cy_xip)) - } > xip - - - /* eFuse */ - .cy_efuse : - { - KEEP(*(.cy_efuse)) - } > efuse - - - /* These sections are used for additional metadata (silicon revision, - * Silicon/JTAG ID, etc.) storage. - */ - .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE -} - - -/* The following symbols used by the cymcuelftool. */ -/* Flash */ -__cy_memory_0_start = 0x10000000; -__cy_memory_0_length = 0x000D0000; -__cy_memory_0_row_size = 0x200; - -/* Emulated EEPROM Flash area */ -__cy_memory_1_start = 0x14000000; -__cy_memory_1_length = 0x8000; -__cy_memory_1_row_size = 0x200; - -/* Supervisory Flash */ -__cy_memory_2_start = 0x16000000; -__cy_memory_2_length = 0x8000; -__cy_memory_2_row_size = 0x200; - -/* XIP */ -__cy_memory_3_start = 0x18000000; -__cy_memory_3_length = 0x08000000; -__cy_memory_3_row_size = 0x200; - -/* eFuse */ -__cy_memory_4_start = 0x90700000; -__cy_memory_4_length = 0x100000; -__cy_memory_4_row_size = 1; - -/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_psoc6_01_cm0plus.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_psoc6_01_cm0plus.S deleted file mode 100644 index b46556a8a7..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_psoc6_01_cm0plus.S +++ /dev/null @@ -1,399 +0,0 @@ -/**************************************************************************//** - * @file startup_psoc6_01_cm0plus.S - * @brief CMSIS Core Device Startup File for - * ARMCM0plus Device Series - * @version V5.00 - * @date 02. March 2016 - ******************************************************************************/ -/* - * Copyright (c) 2009-2016 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - - /* Address of the NMI handler */ - #define CY_NMI_HANLDER_ADDR 0x0000000D - - /* The CPU VTOR register */ - #define CY_CPU_VTOR_ADDR 0xE000ED08 - - /* Copy flash vectors and data section to RAM */ - #define __STARTUP_COPY_MULTIPLE - - /* Clear single BSS section */ - #define __STARTUP_CLEAR_BSS - - .syntax unified - .arch armv6-m - - .section .stack - .align 3 -#ifdef __STACK_SIZE - .equ Stack_Size, __STACK_SIZE -#else - .equ Stack_Size, 0x00001000 -#endif - .globl __StackTop - .globl __StackLimit -__StackLimit: - .space Stack_Size - .size __StackLimit, . - __StackLimit -__StackTop: - .size __StackTop, . - __StackTop - - .section .heap - .align 3 -#ifdef __HEAP_SIZE - .equ Heap_Size, __HEAP_SIZE -#else - .equ Heap_Size, 0x00000400 -#endif - .globl __HeapBase - .globl __HeapLimit -__HeapBase: - .if Heap_Size - .space Heap_Size - .endif - .size __HeapBase, . - __HeapBase -__HeapLimit: - .size __HeapLimit, . - __HeapLimit - - .section .vectors - .align 2 - .globl __Vectors -__Vectors: - .long __StackTop /* Top of Stack */ - .long Reset_Handler /* Reset Handler */ - .long CY_NMI_HANLDER_ADDR /* NMI Handler */ - .long HardFault_Handler /* Hard Fault Handler */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long SVC_Handler /* SVCall Handler */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long PendSV_Handler /* PendSV Handler */ - .long SysTick_Handler /* SysTick Handler */ - - /* External interrupts Description */ - .long NvicMux0_IRQHandler /* CM0+ NVIC Mux input 0 */ - .long NvicMux1_IRQHandler /* CM0+ NVIC Mux input 1 */ - .long NvicMux2_IRQHandler /* CM0+ NVIC Mux input 2 */ - .long NvicMux3_IRQHandler /* CM0+ NVIC Mux input 3 */ - .long NvicMux4_IRQHandler /* CM0+ NVIC Mux input 4 */ - .long NvicMux5_IRQHandler /* CM0+ NVIC Mux input 5 */ - .long NvicMux6_IRQHandler /* CM0+ NVIC Mux input 6 */ - .long NvicMux7_IRQHandler /* CM0+ NVIC Mux input 7 */ - .long NvicMux8_IRQHandler /* CM0+ NVIC Mux input 8 */ - .long NvicMux9_IRQHandler /* CM0+ NVIC Mux input 9 */ - .long NvicMux10_IRQHandler /* CM0+ NVIC Mux input 10 */ - .long NvicMux11_IRQHandler /* CM0+ NVIC Mux input 11 */ - .long NvicMux12_IRQHandler /* CM0+ NVIC Mux input 12 */ - .long NvicMux13_IRQHandler /* CM0+ NVIC Mux input 13 */ - .long NvicMux14_IRQHandler /* CM0+ NVIC Mux input 14 */ - .long NvicMux15_IRQHandler /* CM0+ NVIC Mux input 15 */ - .long NvicMux16_IRQHandler /* CM0+ NVIC Mux input 16 */ - .long NvicMux17_IRQHandler /* CM0+ NVIC Mux input 17 */ - .long NvicMux18_IRQHandler /* CM0+ NVIC Mux input 18 */ - .long NvicMux19_IRQHandler /* CM0+ NVIC Mux input 19 */ - .long NvicMux20_IRQHandler /* CM0+ NVIC Mux input 20 */ - .long NvicMux21_IRQHandler /* CM0+ NVIC Mux input 21 */ - .long NvicMux22_IRQHandler /* CM0+ NVIC Mux input 22 */ - .long NvicMux23_IRQHandler /* CM0+ NVIC Mux input 23 */ - .long NvicMux24_IRQHandler /* CM0+ NVIC Mux input 24 */ - .long NvicMux25_IRQHandler /* CM0+ NVIC Mux input 25 */ - .long NvicMux26_IRQHandler /* CM0+ NVIC Mux input 26 */ - .long NvicMux27_IRQHandler /* CM0+ NVIC Mux input 27 */ - .long NvicMux28_IRQHandler /* CM0+ NVIC Mux input 28 */ - .long NvicMux29_IRQHandler /* CM0+ NVIC Mux input 29 */ - .long NvicMux30_IRQHandler /* CM0+ NVIC Mux input 30 */ - .long NvicMux31_IRQHandler /* CM0+ NVIC Mux input 31 */ - - .size __Vectors, . - __Vectors - .equ __VectorsSize, . - __Vectors - - .section .ram_vectors - .align 2 - .globl __ramVectors -__ramVectors: - .space __VectorsSize - .size __ramVectors, . - __ramVectors - - - .text - .thumb - .thumb_func - .align 2 - - /* - * Device startup customization - * - * Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) - * because this function is executed as the first instruction in the ResetHandler. - * The PDL is also not initialized to use the proper register offsets. - * The user of this function is responsible for initializing the PDL and resources before using them. - */ - .weak Cy_OnResetUser - .func Cy_OnResetUser, Cy_OnResetUser - .type Cy_OnResetUser, %function - -Cy_OnResetUser: - bx lr - .size Cy_OnResetUser, . - Cy_OnResetUser - .endfunc - - /* Reset handler */ - .weak Reset_Handler - .type Reset_Handler, %function - -Reset_Handler: - bl Cy_OnResetUser - -/* Firstly it copies data from read only memory to RAM. There are two schemes - * to copy. One can copy more than one sections. Another can only copy - * one section. The former scheme needs more instructions and read-only - * data to implement than the latter. - * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */ - -#ifdef __STARTUP_COPY_MULTIPLE -/* Multiple sections scheme. - * - * Between symbol address __copy_table_start__ and __copy_table_end__, - * there are array of triplets, each of which specify: - * offset 0: LMA of start of a section to copy from - * offset 4: VMA of start of a section to copy to - * offset 8: size of the section to copy. Must be multiply of 4 - * - * All addresses must be aligned to 4 bytes boundary. - */ - ldr r4, =__copy_table_start__ - ldr r5, =__copy_table_end__ - -.L_loop0: - cmp r4, r5 - bge .L_loop0_done - ldr r1, [r4] - ldr r2, [r4, #4] - ldr r3, [r4, #8] - -.L_loop0_0: - subs r3, #4 - blt .L_loop0_0_done - ldr r0, [r1, r3] - str r0, [r2, r3] - b .L_loop0_0 - -.L_loop0_0_done: - adds r4, #12 - b .L_loop0 - -.L_loop0_done: -#else -/* Single section scheme. - * - * The ranges of copy from/to are specified by following symbols - * __etext: LMA of start of the section to copy from. Usually end of text - * __data_start__: VMA of start of the section to copy to - * __data_end__: VMA of end of the section to copy to - * - * All addresses must be aligned to 4 bytes boundary. - */ - ldr r1, =__etext - ldr r2, =__data_start__ - ldr r3, =__data_end__ - - subs r3, r2 - ble .L_loop1_done - -.L_loop1: - subs r3, #4 - ldr r0, [r1,r3] - str r0, [r2,r3] - bgt .L_loop1 - -.L_loop1_done: -#endif /*__STARTUP_COPY_MULTIPLE */ - -/* This part of work usually is done in C library startup code. Otherwise, - * define this macro to enable it in this startup. - * - * There are two schemes too. One can clear multiple BSS sections. Another - * can only clear one section. The former is more size expensive than the - * latter. - * - * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former. - * Otherwise define macro __STARTUP_CLEAR_BSS to choose the later. - */ -#ifdef __STARTUP_CLEAR_BSS_MULTIPLE -/* Multiple sections scheme. - * - * Between symbol address __copy_table_start__ and __copy_table_end__, - * there are array of tuples specifying: - * offset 0: Start of a BSS section - * offset 4: Size of this BSS section. Must be multiply of 4 - */ - ldr r3, =__zero_table_start__ - ldr r4, =__zero_table_end__ - -.L_loop2: - cmp r3, r4 - bge .L_loop2_done - ldr r1, [r3] - ldr r2, [r3, #4] - movs r0, 0 - -.L_loop2_0: - subs r2, #4 - blt .L_loop2_0_done - str r0, [r1, r2] - b .L_loop2_0 -.L_loop2_0_done: - - adds r3, #8 - b .L_loop2 -.L_loop2_done: -#elif defined (__STARTUP_CLEAR_BSS) -/* Single BSS section scheme. - * - * The BSS section is specified by following symbols - * __bss_start__: start of the BSS section. - * __bss_end__: end of the BSS section. - * - * Both addresses must be aligned to 4 bytes boundary. - */ - ldr r1, =__bss_start__ - ldr r2, =__bss_end__ - - movs r0, 0 - - subs r2, r1 - ble .L_loop3_done - -.L_loop3: - subs r2, #4 - str r0, [r1, r2] - bgt .L_loop3 -.L_loop3_done: -#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */ - - /* Update Vector Table Offset Register. */ - ldr r0, =__ramVectors - ldr r1, =CY_CPU_VTOR_ADDR - str r0, [r1] - dsb 0xF - - bl _start - - /* Should never get here */ - b . - - .pool - .size Reset_Handler, . - Reset_Handler - - .align 1 - .thumb_func - .weak Default_Handler - .type Default_Handler, %function -Default_Handler: - b . - .size Default_Handler, . - Default_Handler - .weak Cy_SysLib_FaultHandler - .type Cy_SysLib_FaultHandler, %function - -Cy_SysLib_FaultHandler: - b . - .size Cy_SysLib_FaultHandler, . - Cy_SysLib_FaultHandler - .type Fault_Handler, %function - -Fault_Handler: - /* Storing LR content for Creator call stack trace */ - push {LR} - movs r0, #4 - mov r1, LR - tst r0, r1 - beq .L_MSP - mrs r0, PSP - b .L_API_call -.L_MSP: - mrs r0, MSP -.L_API_call: - /* Compensation of stack pointer address due to pushing 4 bytes of LR */ - adds r0, r0, #4 - bl Cy_SysLib_FaultHandler - b . - .size Fault_Handler, . - Fault_Handler - -.macro def_fault_Handler fault_handler_name - .weak \fault_handler_name - .set \fault_handler_name, Fault_Handler - .endm - -/* Macro to define default handlers. Default handler - * will be weak symbol and just dead loops. They can be - * overwritten by other handlers */ - .macro def_irq_handler handler_name - .weak \handler_name - .set \handler_name, Default_Handler - .endm - - def_irq_handler NMI_Handler - - def_fault_Handler HardFault_Handler - - def_irq_handler SVC_Handler - def_irq_handler PendSV_Handler - def_irq_handler SysTick_Handler - - def_irq_handler NvicMux0_IRQHandler /* CM0+ NVIC Mux input 0 */ - def_irq_handler NvicMux1_IRQHandler /* CM0+ NVIC Mux input 1 */ - def_irq_handler NvicMux2_IRQHandler /* CM0+ NVIC Mux input 2 */ - def_irq_handler NvicMux3_IRQHandler /* CM0+ NVIC Mux input 3 */ - def_irq_handler NvicMux4_IRQHandler /* CM0+ NVIC Mux input 4 */ - def_irq_handler NvicMux5_IRQHandler /* CM0+ NVIC Mux input 5 */ - def_irq_handler NvicMux6_IRQHandler /* CM0+ NVIC Mux input 6 */ - def_irq_handler NvicMux7_IRQHandler /* CM0+ NVIC Mux input 7 */ - def_irq_handler NvicMux8_IRQHandler /* CM0+ NVIC Mux input 8 */ - def_irq_handler NvicMux9_IRQHandler /* CM0+ NVIC Mux input 9 */ - def_irq_handler NvicMux10_IRQHandler /* CM0+ NVIC Mux input 10 */ - def_irq_handler NvicMux11_IRQHandler /* CM0+ NVIC Mux input 11 */ - def_irq_handler NvicMux12_IRQHandler /* CM0+ NVIC Mux input 12 */ - def_irq_handler NvicMux13_IRQHandler /* CM0+ NVIC Mux input 13 */ - def_irq_handler NvicMux14_IRQHandler /* CM0+ NVIC Mux input 14 */ - def_irq_handler NvicMux15_IRQHandler /* CM0+ NVIC Mux input 15 */ - def_irq_handler NvicMux16_IRQHandler /* CM0+ NVIC Mux input 16 */ - def_irq_handler NvicMux17_IRQHandler /* CM0+ NVIC Mux input 17 */ - def_irq_handler NvicMux18_IRQHandler /* CM0+ NVIC Mux input 18 */ - def_irq_handler NvicMux19_IRQHandler /* CM0+ NVIC Mux input 19 */ - def_irq_handler NvicMux20_IRQHandler /* CM0+ NVIC Mux input 20 */ - def_irq_handler NvicMux21_IRQHandler /* CM0+ NVIC Mux input 21 */ - def_irq_handler NvicMux22_IRQHandler /* CM0+ NVIC Mux input 22 */ - def_irq_handler NvicMux23_IRQHandler /* CM0+ NVIC Mux input 23 */ - def_irq_handler NvicMux24_IRQHandler /* CM0+ NVIC Mux input 24 */ - def_irq_handler NvicMux25_IRQHandler /* CM0+ NVIC Mux input 25 */ - def_irq_handler NvicMux26_IRQHandler /* CM0+ NVIC Mux input 26 */ - def_irq_handler NvicMux27_IRQHandler /* CM0+ NVIC Mux input 27 */ - def_irq_handler NvicMux28_IRQHandler /* CM0+ NVIC Mux input 28 */ - def_irq_handler NvicMux29_IRQHandler /* CM0+ NVIC Mux input 29 */ - def_irq_handler NvicMux30_IRQHandler /* CM0+ NVIC Mux input 30 */ - def_irq_handler NvicMux31_IRQHandler /* CM0+ NVIC Mux input 31 */ - - .end - - -/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cyb06xx7_cm0plus.icf b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cyb06xx7_cm0plus.icf deleted file mode 100644 index 97d3a8c9a7..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cyb06xx7_cm0plus.icf +++ /dev/null @@ -1,288 +0,0 @@ -/******************************************************************************* -* \file cyb06xx7_cm0plus.icf -* \version 2.70.1 -* -* Linker file for the IAR compiler. -* -* The main purpose of the linker script is to describe how the sections in the -* input files should be mapped into the output file, and to control the memory -* layout of the output file. -* -* \note The entry point is fixed and starts at 0x10000000. The valid application -* image should be placed there. -* -* \note The linker files included with the PDL template projects must be generic -* and handle all common use cases. Your project may not use every section -* defined in the linker files. In that case you may see warnings during the -* build process. In your project, you can simply comment out or remove the -* relevant code in the linker file. -* -******************************************************************************** -* \copyright -* Copyright 2016-2020 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ - -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x00000000; - -if (!isdefinedsymbol(MBED_ROM_START)) { - define symbol MBED_ROM_START = 0x10000000; -} - -/* MBED_APP_START is being used by the bootloader build script and - * will be calculate by the system. Without bootloader the MBED_APP_START - * is equal to MBED_ROM_START - */ -if (!isdefinedsymbol(MBED_APP_START)) { - define symbol MBED_APP_START = MBED_ROM_START; -} - -if (!isdefinedsymbol(MBED_ROM_SIZE)) { - define symbol MBED_ROM_SIZE = 0x80000; -} - -/* MBED_APP_SIZE is being used by the bootloader build script and - * will be calculate by the system. Without bootloader the MBED_APP_SIZE - * is equal to MBED_ROM_SIZE - */ -if (!isdefinedsymbol(MBED_APP_SIZE)) { - define symbol MBED_APP_SIZE = MBED_ROM_SIZE; -} - -if (!isdefinedsymbol(MBED_RAM_START)) { - define symbol MBED_RAM_START = 0x08000000; -} - -if (!isdefinedsymbol(MBED_RAM_SIZE)) { - define symbol MBED_RAM_SIZE = 0x00010000; -} - -/*-Sizes-*/ -if (!isdefinedsymbol(MBED_PUBLIC_RAM_SIZE)) { - define symbol MBED_PUBLIC_RAM_SIZE = 0x200; -} -if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) { - - if (!isdefinedsymbol(__STACK_SIZE)) { - define symbol MBED_BOOT_STACK_SIZE = 0x0400; - } else { - define symbol MBED_BOOT_STACK_SIZE = __STACK_SIZE; - } -} - -define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE; - -define symbol __ICFEDIT_size_proc_stack__ = 0x0; - -/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */ -if (!isdefinedsymbol(__HEAP_SIZE)) { - define symbol __ICFEDIT_size_heap__ = 0x0400; -} else { - define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE; -} - -if (!isdefinedsymbol(MBED_PUBLIC_RAM_START)) { - define symbol MBED_PUBLIC_RAM_START = (MBED_RAM_START + MBED_RAM_SIZE - __ICFEDIT_size_cstack__ - MBED_PUBLIC_RAM_SIZE); -} - -/* The symbols below define the location and size of blocks of memory in the target. - * Use these symbols to specify the memory regions available for allocation. - */ - -/* The following symbols control RAM and flash memory allocation for the CM0+ core. - * You can change the memory allocation by editing RAM and Flash symbols. - * Your changes must be aligned with the corresponding symbols for CM4 core in 'xx_cm4_dual.icf', - * where 'xx' is the device group; for example, 'cyb06xx7_cm4_dual.icf'. - */ -/* RAM */ -define symbol __ICFEDIT_region_IRAM1_start__ = MBED_RAM_START; -define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE - 1); -/* Public RAM */ -define symbol __ICFEDIT_region_IRAM2_start__ = MBED_PUBLIC_RAM_START; -define symbol __ICFEDIT_region_IRAM2_end__ = (MBED_PUBLIC_RAM_START + MBED_PUBLIC_RAM_SIZE - 1); -/* Flash */ -define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START; -define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE - 0x8000 - 1); - -/* The following symbols define a 32K flash region used for EEPROM emulation. - * This region can also be used as the general purpose flash. - * You can assign sections to this memory region for only one of the cores. - * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. - * Therefore, repurposing this memory region will prevent such middleware from operation. - */ -define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000; -define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF; - -/* The following symbols define device specific memory regions and must not be changed. */ -/* Supervisory FLASH - User Data */ -define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800; -define symbol __ICFEDIT_region_IROM3_end__ = 0x160007FF; - -/* Supervisory FLASH - Normal Access Restrictions (NAR) */ -define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00; -define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF; - -/* Supervisory FLASH - Public Key */ -define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00; -define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF; - -/* Supervisory FLASH - Table of Content # 2 */ -define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00; -define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF; - -/* Supervisory FLASH - Table of Content # 2 Copy */ -define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00; -define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF; - -/* eFuse */ -define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000; -define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF; - -/* XIP */ -define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000; -define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF; - -define symbol __ICFEDIT_region_EROM2_start__ = 0x0; -define symbol __ICFEDIT_region_EROM2_end__ = 0x0; -define symbol __ICFEDIT_region_EROM3_start__ = 0x0; -define symbol __ICFEDIT_region_EROM3_end__ = 0x0; - -define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; -define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; -define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; -define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; -define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; -define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; -/**** End of ICF editor section. ###ICF###*/ - -/* The size of the MCU boot header area at the start of FLASH */ -define symbol BOOT_HEADER_SIZE = 0x400; - - -define memory mem with size = 4G; -define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]; -define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; -define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__]; -define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__]; -define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__]; -define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__]; -define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__]; -define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__]; -define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]; -define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]; -define region IRAM2_region = mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__]; - -define block RAM_DATA {readwrite section .data}; -define block RAM_OTHER {readwrite section * }; -define block RAM_NOINIT {readwrite section .noinit}; -define block RAM_BSS {readwrite section .bss}; -define block RAM with fixed order {block RAM_DATA, block RAM_OTHER, block RAM_NOINIT, block RAM_BSS}; -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { }; -define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { }; -define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK}; -define block RO {first section .intvec, readonly}; - -/*-Initializations-*/ -initialize by copy { readwrite }; -do not initialize { section .noinit, section .intvec_ram }; - -/*-Placement-*/ - -/* Flash - Cortex-M0+ application */ -".cy_app_header" : place at start of IROM1_region { section .cy_app_header }; -place at address (__ICFEDIT_region_IROM1_start__ + BOOT_HEADER_SIZE) { block RO }; - -/* Emulated EEPROM Flash area */ -".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom }; - -/* Supervisory Flash - User Data */ -".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data }; - -/* Supervisory Flash - NAR */ -".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar }; - -/* Supervisory Flash - Public Key */ -".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key }; - -/* Supervisory Flash - TOC2 */ -".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 }; - -/* Supervisory Flash - RTOC2 */ -".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 }; - -/* eFuse */ -".cy_efuse" : place at start of IROM8_region { section .cy_efuse }; - -/* Execute in Place (XIP). See the smif driver documentation for details. */ -".cy_xip" : place at start of EROM1_region { section .cy_xip }; - -/* RAM */ -place at start of IRAM1_region { readwrite section .intvec_ram}; -place in IRAM1_region { block RAM}; -place in IRAM1_region { readwrite section .cy_ramfunc }; -place at end of IRAM1_region { block HSTACK }; - -/* Public RAM */ -place at start of IRAM2_region { section .cy_sharedmem }; - -/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */ -".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; - - -keep { section .cy_app_header, - section .cy_em_eeprom, - section .cy_sflash_user_data, - section .cy_sflash_nar, - section .cy_sflash_public_key, - section .cy_toc_part2, - section .cy_rtoc_part2, - section .cy_efuse, - section .cy_xip, - section .cymeta, - }; - - -/* The following symbols used by the cymcuelftool. */ -/* Flash */ -define exported symbol __cy_memory_0_start = 0x10000000; -define exported symbol __cy_memory_0_length = 0x000D0000; -define exported symbol __cy_memory_0_row_size = 0x200; - -/* Emulated EEPROM Flash area */ -define exported symbol __cy_memory_1_start = 0x14000000; -define exported symbol __cy_memory_1_length = 0x8000; -define exported symbol __cy_memory_1_row_size = 0x200; - -/* Supervisory Flash */ -define exported symbol __cy_memory_2_start = 0x16000000; -define exported symbol __cy_memory_2_length = 0x8000; -define exported symbol __cy_memory_2_row_size = 0x200; - -/* XIP */ -define exported symbol __cy_memory_3_start = 0x18000000; -define exported symbol __cy_memory_3_length = 0x08000000; -define exported symbol __cy_memory_3_row_size = 0x200; - -/* eFuse */ -define exported symbol __cy_memory_4_start = 0x90700000; -define exported symbol __cy_memory_4_length = 0x100000; -define exported symbol __cy_memory_4_row_size = 1; - -/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_psoc6_01_cm0plus.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_psoc6_01_cm0plus.S deleted file mode 100644 index e926966cf7..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_psoc6_01_cm0plus.S +++ /dev/null @@ -1,413 +0,0 @@ -;/**************************************************************************//** -; * @file startup_psoc6_01_cm0plus.S -; * @brief CMSIS Core Device Startup File for -; * ARMCM0plus Device Series -; * @version V5.00 -; * @date 08. March 2016 -; ******************************************************************************/ -;/* -; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. -; * -; * SPDX-License-Identifier: Apache-2.0 -; * -; * Licensed under the Apache License, Version 2.0 (the License); you may -; * not use this file except in compliance with the License. -; * You may obtain a copy of the License at -; * -; * www.apache.org/licenses/LICENSE-2.0 -; * -; * Unless required by applicable law or agreed to in writing, software -; * distributed under the License is distributed on an AS IS BASIS, WITHOUT -; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -; * See the License for the specific language governing permissions and -; * limitations under the License. -; */ - -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - SECTION .intvec_ram:DATA:NOROOT(2) - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - EXTERN __iar_data_init3 - PUBLIC __vector_table - PUBLIC __vector_table_0x1c - PUBLIC __Vectors - PUBLIC __Vectors_End - PUBLIC __Vectors_Size - PUBLIC __ramVectors - - DATA - -__vector_table - DCD sfe(CSTACK) - DCD Reset_Handler - - DCD 0x0000000D ; NMI_Handler is defined in ROM code - DCD HardFault_Handler - DCD 0 - DCD 0 - DCD 0 -__vector_table_0x1c - DCD 0 - DCD 0 - DCD 0 - DCD 0 - DCD SVC_Handler - DCD 0 - DCD 0 - DCD PendSV_Handler - DCD SysTick_Handler - - ; External interrupts Description - DCD NvicMux0_IRQHandler ; CM0+ NVIC Mux input 0 - DCD NvicMux1_IRQHandler ; CM0+ NVIC Mux input 1 - DCD NvicMux2_IRQHandler ; CM0+ NVIC Mux input 2 - DCD NvicMux3_IRQHandler ; CM0+ NVIC Mux input 3 - DCD NvicMux4_IRQHandler ; CM0+ NVIC Mux input 4 - DCD NvicMux5_IRQHandler ; CM0+ NVIC Mux input 5 - DCD NvicMux6_IRQHandler ; CM0+ NVIC Mux input 6 - DCD NvicMux7_IRQHandler ; CM0+ NVIC Mux input 7 - DCD NvicMux8_IRQHandler ; CM0+ NVIC Mux input 8 - DCD NvicMux9_IRQHandler ; CM0+ NVIC Mux input 9 - DCD NvicMux10_IRQHandler ; CM0+ NVIC Mux input 10 - DCD NvicMux11_IRQHandler ; CM0+ NVIC Mux input 11 - DCD NvicMux12_IRQHandler ; CM0+ NVIC Mux input 12 - DCD NvicMux13_IRQHandler ; CM0+ NVIC Mux input 13 - DCD NvicMux14_IRQHandler ; CM0+ NVIC Mux input 14 - DCD NvicMux15_IRQHandler ; CM0+ NVIC Mux input 15 - DCD NvicMux16_IRQHandler ; CM0+ NVIC Mux input 16 - DCD NvicMux17_IRQHandler ; CM0+ NVIC Mux input 17 - DCD NvicMux18_IRQHandler ; CM0+ NVIC Mux input 18 - DCD NvicMux19_IRQHandler ; CM0+ NVIC Mux input 19 - DCD NvicMux20_IRQHandler ; CM0+ NVIC Mux input 20 - DCD NvicMux21_IRQHandler ; CM0+ NVIC Mux input 21 - DCD NvicMux22_IRQHandler ; CM0+ NVIC Mux input 22 - DCD NvicMux23_IRQHandler ; CM0+ NVIC Mux input 23 - DCD NvicMux24_IRQHandler ; CM0+ NVIC Mux input 24 - DCD NvicMux25_IRQHandler ; CM0+ NVIC Mux input 25 - DCD NvicMux26_IRQHandler ; CM0+ NVIC Mux input 26 - DCD NvicMux27_IRQHandler ; CM0+ NVIC Mux input 27 - DCD NvicMux28_IRQHandler ; CM0+ NVIC Mux input 28 - DCD NvicMux29_IRQHandler ; CM0+ NVIC Mux input 29 - DCD NvicMux30_IRQHandler ; CM0+ NVIC Mux input 30 - DCD NvicMux31_IRQHandler ; CM0+ NVIC Mux input 31 - -__Vectors_End - -__Vectors EQU __vector_table -__Vectors_Size EQU __Vectors_End - __Vectors - - SECTION .intvec_ram:DATA:REORDER:NOROOT(2) -__ramVectors - DS32 __Vectors_Size - - - THUMB - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default handlers -;; - PUBWEAK Default_Handler - SECTION .text:CODE:REORDER:NOROOT(2) -Default_Handler - B Default_Handler - - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Weak function for startup customization -;; -;; Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) -;; because this function is executed as the first instruction in the ResetHandler. -;; The PDL is also not initialized to use the proper register offsets. -;; The user of this function is responsible for initializing the PDL and resources before using them. -;; - PUBWEAK Cy_OnResetUser - SECTION .text:CODE:REORDER:NOROOT(2) -Cy_OnResetUser - BX LR - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Define strong version to return zero for -;; __iar_program_start to skip data sections -;; initialization. -;; - PUBLIC __low_level_init - SECTION .text:CODE:REORDER:NOROOT(2) -__low_level_init - MOVS R0, #0 - BX LR - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - THUMB - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER:NOROOT(2) -Reset_Handler - - ; Define strong function for startup customization - LDR R0, =Cy_OnResetUser - BLX R0 - - ; Copy vectors from ROM to RAM - LDR r1, =__vector_table - LDR r0, =__ramVectors - LDR r2, =__Vectors_Size -intvec_copy - LDR r3, [r1] - STR r3, [r0] - ADDS r0, r0, #4 - ADDS r1, r1, #4 - SUBS r2, r2, #1 - CMP r2, #0 - BNE intvec_copy - - ; Update Vector Table Offset Register - LDR r0, =__ramVectors - LDR r1, =0xE000ED08 - STR r0, [r1] - dsb - - LDR R0, =__iar_program_start - BLX R0 - -; Should never get here -Cy_Main_Exited - B Cy_Main_Exited - - - PUBWEAK NMI_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -NMI_Handler - B NMI_Handler - - - PUBWEAK Cy_SysLib_FaultHandler - SECTION .text:CODE:REORDER:NOROOT(1) -Cy_SysLib_FaultHandler - B Cy_SysLib_FaultHandler - - PUBWEAK HardFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -HardFault_Handler - IMPORT Cy_SysLib_FaultHandler - movs r0, #4 - mov r1, LR - tst r0, r1 - beq L_MSP - mrs r0, PSP - b L_API_call -L_MSP - mrs r0, MSP -L_API_call - ; Storing LR content for Creator call stack trace - push {LR} - bl Cy_SysLib_FaultHandler - - - PUBWEAK SVC_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SVC_Handler - B SVC_Handler - - PUBWEAK PendSV_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PendSV_Handler - B PendSV_Handler - - PUBWEAK SysTick_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SysTick_Handler - B SysTick_Handler - - - ; External interrupts - PUBWEAK NvicMux0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -NvicMux0_IRQHandler - B NvicMux0_IRQHandler - - PUBWEAK NvicMux1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -NvicMux1_IRQHandler - B NvicMux1_IRQHandler - - PUBWEAK NvicMux2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -NvicMux2_IRQHandler - B NvicMux2_IRQHandler - - PUBWEAK NvicMux3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -NvicMux3_IRQHandler - B NvicMux3_IRQHandler - - PUBWEAK NvicMux4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -NvicMux4_IRQHandler - B NvicMux4_IRQHandler - - PUBWEAK NvicMux5_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -NvicMux5_IRQHandler - B NvicMux5_IRQHandler - - PUBWEAK NvicMux6_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -NvicMux6_IRQHandler - B NvicMux6_IRQHandler - - PUBWEAK NvicMux7_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -NvicMux7_IRQHandler - B NvicMux7_IRQHandler - - PUBWEAK NvicMux8_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -NvicMux8_IRQHandler - B NvicMux8_IRQHandler - - PUBWEAK NvicMux9_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -NvicMux9_IRQHandler - B NvicMux9_IRQHandler - - PUBWEAK NvicMux10_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -NvicMux10_IRQHandler - B NvicMux10_IRQHandler - - PUBWEAK NvicMux11_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -NvicMux11_IRQHandler - B NvicMux11_IRQHandler - - PUBWEAK NvicMux12_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -NvicMux12_IRQHandler - B NvicMux12_IRQHandler - - PUBWEAK NvicMux13_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -NvicMux13_IRQHandler - B NvicMux13_IRQHandler - - PUBWEAK NvicMux14_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -NvicMux14_IRQHandler - B NvicMux14_IRQHandler - - PUBWEAK NvicMux15_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -NvicMux15_IRQHandler - B NvicMux15_IRQHandler - - PUBWEAK NvicMux16_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -NvicMux16_IRQHandler - B NvicMux16_IRQHandler - - PUBWEAK NvicMux17_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -NvicMux17_IRQHandler - B NvicMux17_IRQHandler - - PUBWEAK NvicMux18_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -NvicMux18_IRQHandler - B NvicMux18_IRQHandler - - PUBWEAK NvicMux19_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -NvicMux19_IRQHandler - B NvicMux19_IRQHandler - - PUBWEAK NvicMux20_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -NvicMux20_IRQHandler - B NvicMux20_IRQHandler - - PUBWEAK NvicMux21_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -NvicMux21_IRQHandler - B NvicMux21_IRQHandler - - PUBWEAK NvicMux22_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -NvicMux22_IRQHandler - B NvicMux22_IRQHandler - - PUBWEAK NvicMux23_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -NvicMux23_IRQHandler - B NvicMux23_IRQHandler - - PUBWEAK NvicMux24_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -NvicMux24_IRQHandler - B NvicMux24_IRQHandler - - PUBWEAK NvicMux25_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -NvicMux25_IRQHandler - B NvicMux25_IRQHandler - - PUBWEAK NvicMux26_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -NvicMux26_IRQHandler - B NvicMux26_IRQHandler - - PUBWEAK NvicMux27_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -NvicMux27_IRQHandler - B NvicMux27_IRQHandler - - PUBWEAK NvicMux28_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -NvicMux28_IRQHandler - B NvicMux28_IRQHandler - - PUBWEAK NvicMux29_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -NvicMux29_IRQHandler - B NvicMux29_IRQHandler - - PUBWEAK NvicMux30_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -NvicMux30_IRQHandler - B NvicMux30_IRQHandler - - PUBWEAK NvicMux31_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -NvicMux31_IRQHandler - B NvicMux31_IRQHandler - - - END - - -; [] END OF FILE diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM0P/system_psoc6_cm0plus.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM0P/system_psoc6_cm0plus.c deleted file mode 100644 index 2e2b15209a..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM0P/system_psoc6_cm0plus.c +++ /dev/null @@ -1,526 +0,0 @@ -/***************************************************************************//** -* \file system_psoc6_cm0plus.c -* \version 2.70.1 -* -* The device system-source file. -* -******************************************************************************** -* \copyright -* Copyright 2016-2020 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ - -#include -#include "system_psoc6.h" -#include "cy_device.h" -#include "cy_device_headers.h" -#include "cy_syslib.h" -#include "cy_sysclk.h" -#include "cy_wdt.h" - -#if !defined(CY_IPC_DEFAULT_CFG_DISABLE) - #include "cy_ipc_sema.h" - #include "cy_ipc_pipe.h" - #include "cy_ipc_drv.h" - - #if defined(CY_DEVICE_PSOC6ABLE2) - #include "cy_flash.h" - #endif /* defined(CY_DEVICE_PSOC6ABLE2) */ -#endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */ - - -/******************************************************************************* -* SystemCoreClockUpdate() -*******************************************************************************/ - -/** Default HFClk frequency in Hz */ -#define CY_CLK_HFCLK0_FREQ_HZ_DEFAULT (8000000UL) - -/** Default PeriClk frequency in Hz */ -#define CY_CLK_PERICLK_FREQ_HZ_DEFAULT (4000000UL) - -/** Default SlowClk system core frequency in Hz */ -#define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT (4000000UL) - - -/** -* Holds the SlowClk (Cortex-M0+) or FastClk (Cortex-M4) system core clock, -* which is the system clock frequency supplied to the SysTick timer and the -* processor core clock. -* This variable implements CMSIS Core global variable. -* Refer to the [CMSIS documentation] -* (http://www.keil.com/pack/doc/CMSIS/Core/html/group__system__init__gr.html "System and Clock Configuration") -* for more details. -* This variable can be used by debuggers to query the frequency -* of the debug timer or to configure the trace clock speed. -* -* \attention Compilers must be configured to avoid removing this variable in case -* the application program is not using it. Debugging systems require the variable -* to be physically present in memory so that it can be examined to configure the debugger. */ -uint32_t SystemCoreClock = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT; - -/** Holds the HFClk0 clock frequency. Updated by \ref SystemCoreClockUpdate(). */ -uint32_t cy_Hfclk0FreqHz = CY_CLK_HFCLK0_FREQ_HZ_DEFAULT; - -/** Holds the PeriClk clock frequency. Updated by \ref SystemCoreClockUpdate(). */ -uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT; - -/** Holds the Alternate high frequency clock in Hz. Updated by \ref Cy_BLE_EcoConfigure(). */ -uint32_t cy_BleEcoClockFreqHz = 0UL; - - -/******************************************************************************* -* SystemInit() -*******************************************************************************/ - -/* CLK_FLL_CONFIG default values */ -#define CY_FB_CLK_FLL_CONFIG_VALUE (0x01000000u) -#define CY_FB_CLK_FLL_CONFIG2_VALUE (0x00020001u) -#define CY_FB_CLK_FLL_CONFIG3_VALUE (0x00002800u) -#define CY_FB_CLK_FLL_CONFIG4_VALUE (0x000000FFu) - - -/******************************************************************************* -* SystemCoreClockUpdate (void) -*******************************************************************************/ - -/* Do not use these definitions directly in your application */ -#define CY_DELAY_MS_OVERFLOW_THRESHOLD (0x8000u) -#define CY_DELAY_1K_THRESHOLD (1000u) -#define CY_DELAY_1M_THRESHOLD (1000000u) - -uint32_t cy_delayFreqKhz = CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1K_THRESHOLD); - -uint8_t cy_delayFreqMhz = (uint8_t)CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1M_THRESHOLD); - -uint32_t cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * - CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1K_THRESHOLD); - - -/******************************************************************************* -* Cy_SysEnableCM4(), Cy_SysRetainCM4(), and Cy_SysResetCM4() -*******************************************************************************/ -#define CY_SYS_CM4_PWR_CTL_KEY_OPEN (0x05FAUL) -#define CY_SYS_CM4_PWR_CTL_KEY_CLOSE (0xFA05UL) -#define CY_SYS_CM4_VECTOR_TABLE_VALID_ADDR (0x000003FFUL) - - -/******************************************************************************* -* Function Name: SystemInit -****************************************************************************//** -* -* Initializes the system: -* - Restores FLL registers to the default state. -* - Unlocks and disables WDT. -* - Calls Cy_PDL_Init() function to define the driver library. -* - Calls the Cy_SystemInit() function, if compiled from PSoC Creator. -* - Calls \ref SystemCoreClockUpdate(). -* -*******************************************************************************/ -void SystemInit(void) -{ - Cy_PDL_Init(CY_DEVICE_CFG); - - /* Restore FLL registers to the default state as they are not restored by the ROM code */ - uint32_t copy = SRSS->CLK_FLL_CONFIG; - copy &= ~SRSS_CLK_FLL_CONFIG_FLL_ENABLE_Msk; - SRSS->CLK_FLL_CONFIG = copy; - - copy = SRSS->CLK_ROOT_SELECT[0u]; - copy &= ~SRSS_CLK_ROOT_SELECT_ROOT_DIV_Msk; /* Set ROOT_DIV = 0*/ - SRSS->CLK_ROOT_SELECT[0u] = copy; - - SRSS->CLK_FLL_CONFIG = CY_FB_CLK_FLL_CONFIG_VALUE; - SRSS->CLK_FLL_CONFIG2 = CY_FB_CLK_FLL_CONFIG2_VALUE; - SRSS->CLK_FLL_CONFIG3 = CY_FB_CLK_FLL_CONFIG3_VALUE; - SRSS->CLK_FLL_CONFIG4 = CY_FB_CLK_FLL_CONFIG4_VALUE; - - /* Unlock and disable WDT */ - Cy_WDT_Unlock(); - Cy_WDT_Disable(); - - Cy_SystemInit(); - SystemCoreClockUpdate(); - - /* Clear data register of IPC structure #7, reserved for the Deep-Sleep operations. */ - REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = 0UL; - - /* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering. */ - REG_IPC_STRUCT_RELEASE(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = 0UL; - -#if !defined(CY_IPC_DEFAULT_CFG_DISABLE) - /* Allocate and initialize semaphores for the system operations. */ - CY_SECTION(".cy_sharedmem") - static uint32_t ipcSemaArray[CY_IPC_SEMA_COUNT / CY_IPC_SEMA_PER_WORD]; - - (void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, CY_IPC_SEMA_COUNT, ipcSemaArray); - - - /******************************************************************************** - * - * Initializes the system pipes. The system pipes are used by BLE and Flash. - * - * If the default startup file is not used, or SystemInit() is not called in your - * project, call the following three functions prior to executing any flash or - * EmEEPROM write or erase operation: - * -# Cy_IPC_Sema_Init() - * -# Cy_IPC_Pipe_Config() - * -# Cy_IPC_Pipe_Init() - * -# Cy_Flash_Init() - * - *******************************************************************************/ - - /* Create an array of endpoint structures */ - static cy_stc_ipc_pipe_ep_t systemIpcPipeEpArray[CY_IPC_MAX_ENDPOINTS]; - - Cy_IPC_Pipe_Config(systemIpcPipeEpArray); - - static cy_ipc_pipe_callback_ptr_t systemIpcPipeSysCbArray[CY_SYS_CYPIPE_CLIENT_CNT]; - - static const cy_stc_ipc_pipe_config_t systemIpcPipeConfigCm0 = - { - /* .ep0ConfigData */ - { - /* .ipcNotifierNumber */ CY_IPC_INTR_CYPIPE_EP0, - /* .ipcNotifierPriority */ CY_SYS_INTR_CYPIPE_PRIOR_EP0, - /* .ipcNotifierMuxNumber */ CY_SYS_INTR_CYPIPE_MUX_EP0, - /* .epAddress */ CY_IPC_EP_CYPIPE_CM0_ADDR, - /* .epConfig */ CY_SYS_CYPIPE_CONFIG_EP0 - }, - /* .ep1ConfigData */ - { - /* .ipcNotifierNumber */ CY_IPC_INTR_CYPIPE_EP1, - /* .ipcNotifierPriority */ CY_SYS_INTR_CYPIPE_PRIOR_EP1, - /* .ipcNotifierMuxNumber */ 0u, - /* .epAddress */ CY_IPC_EP_CYPIPE_CM4_ADDR, - /* .epConfig */ CY_SYS_CYPIPE_CONFIG_EP1 - }, - /* .endpointClientsCount */ CY_SYS_CYPIPE_CLIENT_CNT, - /* .endpointsCallbacksArray */ systemIpcPipeSysCbArray, - /* .userPipeIsrHandler */ &Cy_SysIpcPipeIsrCm0 - }; - - Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm0); - -#if defined(CY_DEVICE_PSOC6ABLE2) - Cy_Flash_Init(); -#endif /* defined(CY_DEVICE_PSOC6ABLE2) */ - -#endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */ -} - - -/******************************************************************************* -* Function Name: Cy_SystemInit -****************************************************************************//** -* -* The function is called during device startup. Once project compiled as part of -* the PSoC Creator project, the Cy_SystemInit() function is generated by the -* PSoC Creator. -* -* The function generated by PSoC Creator performs all of the necessary device -* configuration based on the design settings. This includes settings from the -* Design Wide Resources (DWR) such as Clocks and Pins as well as any component -* configuration that is necessary. -* -*******************************************************************************/ -__WEAK void Cy_SystemInit(void) -{ - /* Empty weak function. The actual implementation to be in the PSoC Creator - * generated strong function. - */ -} - - -/******************************************************************************* -* Function Name: SystemCoreClockUpdate -****************************************************************************//** -* -* Gets core clock frequency and updates \ref SystemCoreClock. -* -* Updates global variables used by the \ref Cy_SysLib_Delay(), \ref -* Cy_SysLib_DelayUs(), and \ref Cy_SysLib_DelayCycles(). -* -*******************************************************************************/ -void SystemCoreClockUpdate (void) -{ - uint32 locHf0Clock = Cy_SysClk_ClkHfGetFrequency(0UL); - - if (0UL != locHf0Clock) - { - cy_Hfclk0FreqHz = locHf0Clock; - cy_PeriClkFreqHz = locHf0Clock / (1UL + (uint32_t)Cy_SysClk_ClkPeriGetDivider()); - SystemCoreClock = cy_PeriClkFreqHz / (1UL + (uint32_t)Cy_SysClk_ClkSlowGetDivider()); - - /* Sets clock frequency for Delay API */ - cy_delayFreqMhz = (uint8_t)CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1M_THRESHOLD); - cy_delayFreqKhz = CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1K_THRESHOLD); - cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * cy_delayFreqKhz; - } -} - - -#if (CY_SYSTEM_CPU_CM0P == 1UL) || defined(CY_DOXYGEN) -/******************************************************************************* -* Function Name: Cy_SysGetCM4Status -****************************************************************************//** -* -* Returns the Cortex-M4 core power mode. -* -* \return \ref group_system_config_cm4_status_macro -* -*******************************************************************************/ -uint32_t Cy_SysGetCM4Status(void) -{ - uint32_t regValue; - - /* Get current power mode */ - regValue = CPUSS->CM4_PWR_CTL & CPUSS_CM4_PWR_CTL_PWR_MODE_Msk; - - return (regValue); -} - - -/******************************************************************************* -* Function Name: Cy_SysEnableCM4 -****************************************************************************//** -* -* Sets vector table base address and enables the Cortex-M4 core. -* -* \note If the CPU is already enabled, it is reset and then enabled. -* -* \param vectorTableOffset The offset of the vector table base address from -* memory address 0x00000000. The offset should be multiple to 1024 bytes. -* -*******************************************************************************/ -void Cy_SysEnableCM4(uint32_t vectorTableOffset) -{ - uint32_t regValue; - uint32_t interruptState; - uint32_t cpuState; - - CY_ASSERT_L2((vectorTableOffset & CY_SYS_CM4_VECTOR_TABLE_VALID_ADDR) == 0UL); - - interruptState = Cy_SysLib_EnterCriticalSection(); - - cpuState = Cy_SysGetCM4Status(); - if (CY_SYS_CM4_STATUS_ENABLED == cpuState) - { - Cy_SysResetCM4(); - } - - CPUSS->CM4_VECTOR_TABLE_BASE = vectorTableOffset; - - regValue = CPUSS->CM4_PWR_CTL & ~(CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM4_PWR_CTL_PWR_MODE_Msk); - regValue |= _VAL2FLD(CPUSS_CM4_PWR_CTL_VECTKEYSTAT, CY_SYS_CM4_PWR_CTL_KEY_OPEN); - regValue |= CY_SYS_CM4_STATUS_ENABLED; - CPUSS->CM4_PWR_CTL = regValue; - - while((CPUSS->CM4_STATUS & CPUSS_CM4_STATUS_PWR_DONE_Msk) == 0UL) - { - /* Wait for the power mode to take effect */ - } - - Cy_SysLib_ExitCriticalSection(interruptState); -} - - -/******************************************************************************* -* Function Name: Cy_SysDisableCM4 -****************************************************************************//** -* -* Disables the Cortex-M4 core and waits for the mode to take the effect. -* -* \warning Do not call the function while the Cortex-M4 is executing because -* such a call may corrupt/abort a pending bus-transaction by the CPU and cause -* unexpected behavior in the system including a deadlock. Call the function -* while the Cortex-M4 core is in the Sleep or Deep Sleep low-power mode. Use -* the \ref group_syspm Power Management (syspm) API to put the CPU into the -* low-power modes. Use the \ref Cy_SysPm_ReadStatus() to get a status of the -* CPU. -* -*******************************************************************************/ -void Cy_SysDisableCM4(void) -{ - uint32_t interruptState; - uint32_t regValue; - - interruptState = Cy_SysLib_EnterCriticalSection(); - - regValue = CPUSS->CM4_PWR_CTL & ~(CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM4_PWR_CTL_PWR_MODE_Msk); - regValue |= _VAL2FLD(CPUSS_CM4_PWR_CTL_VECTKEYSTAT, CY_SYS_CM4_PWR_CTL_KEY_OPEN); - regValue |= CY_SYS_CM4_STATUS_DISABLED; - CPUSS->CM4_PWR_CTL = regValue; - - while((CPUSS->CM4_STATUS & CPUSS_CM4_STATUS_PWR_DONE_Msk) == 0UL) - { - /* Wait for the power mode to take effect */ - } - - Cy_SysLib_ExitCriticalSection(interruptState); -} - - -/******************************************************************************* -* Function Name: Cy_SysRetainCM4 -****************************************************************************//** -* -* Retains the Cortex-M4 core and exists without waiting for the mode to take -* effect. -* -* \note The retained mode can be entered only from the enabled mode. -* -* \warning Do not call the function while the Cortex-M4 is executing because -* such a call may corrupt/abort a pending bus-transaction by the CPU and cause -* unexpected behavior in the system including a deadlock. Call the function -* while the Cortex-M4 core is in the Sleep or Deep Sleep low-power mode. Use -* the \ref group_syspm Power Management (syspm) API to put the CPU into the -* low-power modes. Use the \ref Cy_SysPm_ReadStatus() to get a status of the CPU. -* -*******************************************************************************/ -void Cy_SysRetainCM4(void) -{ - uint32_t interruptState; - uint32_t regValue; - - interruptState = Cy_SysLib_EnterCriticalSection(); - - regValue = CPUSS->CM4_PWR_CTL & ~(CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM4_PWR_CTL_PWR_MODE_Msk); - regValue |= _VAL2FLD(CPUSS_CM4_PWR_CTL_VECTKEYSTAT, CY_SYS_CM4_PWR_CTL_KEY_OPEN); - regValue |= CY_SYS_CM4_STATUS_RETAINED; - CPUSS->CM4_PWR_CTL = regValue; - - Cy_SysLib_ExitCriticalSection(interruptState); -} - - -/******************************************************************************* -* Function Name: Cy_SysResetCM4 -****************************************************************************//** -* -* Resets the Cortex-M4 core and waits for the mode to take the effect. -* -* \note The reset mode can not be entered from the retained mode. -* -* \warning Do not call the function while the Cortex-M4 is executing because -* such a call may corrupt/abort a pending bus-transaction by the CPU and cause -* unexpected behavior in the system including a deadlock. Call the function -* while the Cortex-M4 core is in the Sleep or Deep Sleep low-power mode. Use -* the \ref group_syspm Power Management (syspm) API to put the CPU into the -* low-power modes. Use the \ref Cy_SysPm_ReadStatus() to get a status of the CPU. -* -*******************************************************************************/ -void Cy_SysResetCM4(void) -{ - uint32_t interruptState; - uint32_t regValue; - - interruptState = Cy_SysLib_EnterCriticalSection(); - - regValue = CPUSS->CM4_PWR_CTL & ~(CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM4_PWR_CTL_PWR_MODE_Msk); - regValue |= _VAL2FLD(CPUSS_CM4_PWR_CTL_VECTKEYSTAT, CY_SYS_CM4_PWR_CTL_KEY_OPEN); - regValue |= CY_SYS_CM4_STATUS_RESET; - CPUSS->CM4_PWR_CTL = regValue; - - while((CPUSS->CM4_STATUS & CPUSS_CM4_STATUS_PWR_DONE_Msk) == 0UL) - { - /* Wait for the power mode to take effect */ - } - - Cy_SysLib_ExitCriticalSection(interruptState); -} -#endif /* #if (CY_SYSTEM_CPU_CM0P == 1UL) || defined(CY_DOXYGEN) */ - -#if !defined(CY_IPC_DEFAULT_CFG_DISABLE) -/******************************************************************************* -* Function Name: Cy_SysIpcPipeIsrCm0 -****************************************************************************//** -* -* This is the interrupt service routine for the system pipe. -* -*******************************************************************************/ -void Cy_SysIpcPipeIsrCm0(void) -{ - Cy_IPC_Pipe_ExecuteCallback(CY_IPC_EP_CYPIPE_CM0_ADDR); -} -#endif - - -/******************************************************************************* -* Function Name: Cy_MemorySymbols -****************************************************************************//** -* -* The intention of the function is to declare boundaries of the memories for the -* MDK compilers. For the rest of the supported compilers, this is done using -* linker configuration files. The following symbols used by the cymcuelftool. -* -*******************************************************************************/ -#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION < 6010050) -__asm void Cy_MemorySymbols(void) -{ - /* Flash */ - EXPORT __cy_memory_0_start - EXPORT __cy_memory_0_length - EXPORT __cy_memory_0_row_size - - /* Working Flash */ - EXPORT __cy_memory_1_start - EXPORT __cy_memory_1_length - EXPORT __cy_memory_1_row_size - - /* Supervisory Flash */ - EXPORT __cy_memory_2_start - EXPORT __cy_memory_2_length - EXPORT __cy_memory_2_row_size - - /* XIP */ - EXPORT __cy_memory_3_start - EXPORT __cy_memory_3_length - EXPORT __cy_memory_3_row_size - - /* eFuse */ - EXPORT __cy_memory_4_start - EXPORT __cy_memory_4_length - EXPORT __cy_memory_4_row_size - - /* Flash */ -__cy_memory_0_start EQU __cpp(CY_FLASH_BASE) -__cy_memory_0_length EQU __cpp(CY_FLASH_SIZE) -__cy_memory_0_row_size EQU 0x200 - - /* Flash region for EEPROM emulation */ -__cy_memory_1_start EQU __cpp(CY_EM_EEPROM_BASE) -__cy_memory_1_length EQU __cpp(CY_EM_EEPROM_SIZE) -__cy_memory_1_row_size EQU 0x200 - - /* Supervisory Flash */ -__cy_memory_2_start EQU __cpp(CY_SFLASH_BASE) -__cy_memory_2_length EQU __cpp(CY_SFLASH_SIZE) -__cy_memory_2_row_size EQU 0x200 - - /* XIP */ -__cy_memory_3_start EQU __cpp(CY_XIP_BASE) -__cy_memory_3_length EQU __cpp(CY_XIP_SIZE) -__cy_memory_3_row_size EQU 0x200 - - /* eFuse */ -__cy_memory_4_start EQU __cpp(0x90700000) -__cy_memory_4_length EQU __cpp(0x100000) -__cy_memory_4_row_size EQU __cpp(1) -} -#endif /* defined (__ARMCC_VERSION) && (__ARMCC_VERSION < 6010050) */ - - -/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_01_cm4.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_01_cm4.S deleted file mode 100644 index fa2247ebe9..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_01_cm4.S +++ /dev/null @@ -1,638 +0,0 @@ -;/**************************************************************************//** -; * @file startup_psoc6_01_cm4.S -; * @brief CMSIS Core Device Startup File for -; * ARMCM4 Device Series -; * @version V5.00 -; * @date 02. March 2016 -; ******************************************************************************/ -;/* -; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. -; * -; * SPDX-License-Identifier: Apache-2.0 -; * -; * Licensed under the Apache License, Version 2.0 (the License); you may -; * not use this file except in compliance with the License. -; * You may obtain a copy of the License at -; * -; * www.apache.org/licenses/LICENSE-2.0 -; * -; * Unless required by applicable law or agreed to in writing, software -; * distributed under the License is distributed on an AS IS BASIS, WITHOUT -; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -; * See the License for the specific language governing permissions and -; * limitations under the License. -; */ - - PRESERVE8 - THUMB - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| - -__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack - DCD Reset_Handler ; Reset Handler - - DCD 0x0000000D ; NMI Handler located at ROM code - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External interrupts Description - DCD ioss_interrupts_gpio_0_IRQHandler ; GPIO Port Interrupt #0 - DCD ioss_interrupts_gpio_1_IRQHandler ; GPIO Port Interrupt #1 - DCD ioss_interrupts_gpio_2_IRQHandler ; GPIO Port Interrupt #2 - DCD ioss_interrupts_gpio_3_IRQHandler ; GPIO Port Interrupt #3 - DCD ioss_interrupts_gpio_4_IRQHandler ; GPIO Port Interrupt #4 - DCD ioss_interrupts_gpio_5_IRQHandler ; GPIO Port Interrupt #5 - DCD ioss_interrupts_gpio_6_IRQHandler ; GPIO Port Interrupt #6 - DCD ioss_interrupts_gpio_7_IRQHandler ; GPIO Port Interrupt #7 - DCD ioss_interrupts_gpio_8_IRQHandler ; GPIO Port Interrupt #8 - DCD ioss_interrupts_gpio_9_IRQHandler ; GPIO Port Interrupt #9 - DCD ioss_interrupts_gpio_10_IRQHandler ; GPIO Port Interrupt #10 - DCD ioss_interrupts_gpio_11_IRQHandler ; GPIO Port Interrupt #11 - DCD ioss_interrupts_gpio_12_IRQHandler ; GPIO Port Interrupt #12 - DCD ioss_interrupts_gpio_13_IRQHandler ; GPIO Port Interrupt #13 - DCD ioss_interrupts_gpio_14_IRQHandler ; GPIO Port Interrupt #14 - DCD ioss_interrupt_gpio_IRQHandler ; GPIO All Ports - DCD ioss_interrupt_vdd_IRQHandler ; GPIO Supply Detect Interrupt - DCD lpcomp_interrupt_IRQHandler ; Low Power Comparator Interrupt - DCD scb_8_interrupt_IRQHandler ; Serial Communication Block #8 (DeepSleep capable) - DCD srss_interrupt_mcwdt_0_IRQHandler ; Multi Counter Watchdog Timer interrupt - DCD srss_interrupt_mcwdt_1_IRQHandler ; Multi Counter Watchdog Timer interrupt - DCD srss_interrupt_backup_IRQHandler ; Backup domain interrupt - DCD srss_interrupt_IRQHandler ; Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) - DCD pass_interrupt_ctbs_IRQHandler ; CTBm Interrupt (all CTBms) - DCD bless_interrupt_IRQHandler ; Bluetooth Radio interrupt - DCD cpuss_interrupts_ipc_0_IRQHandler ; CPUSS Inter Process Communication Interrupt #0 - DCD cpuss_interrupts_ipc_1_IRQHandler ; CPUSS Inter Process Communication Interrupt #1 - DCD cpuss_interrupts_ipc_2_IRQHandler ; CPUSS Inter Process Communication Interrupt #2 - DCD cpuss_interrupts_ipc_3_IRQHandler ; CPUSS Inter Process Communication Interrupt #3 - DCD cpuss_interrupts_ipc_4_IRQHandler ; CPUSS Inter Process Communication Interrupt #4 - DCD cpuss_interrupts_ipc_5_IRQHandler ; CPUSS Inter Process Communication Interrupt #5 - DCD cpuss_interrupts_ipc_6_IRQHandler ; CPUSS Inter Process Communication Interrupt #6 - DCD cpuss_interrupts_ipc_7_IRQHandler ; CPUSS Inter Process Communication Interrupt #7 - DCD cpuss_interrupts_ipc_8_IRQHandler ; CPUSS Inter Process Communication Interrupt #8 - DCD cpuss_interrupts_ipc_9_IRQHandler ; CPUSS Inter Process Communication Interrupt #9 - DCD cpuss_interrupts_ipc_10_IRQHandler ; CPUSS Inter Process Communication Interrupt #10 - DCD cpuss_interrupts_ipc_11_IRQHandler ; CPUSS Inter Process Communication Interrupt #11 - DCD cpuss_interrupts_ipc_12_IRQHandler ; CPUSS Inter Process Communication Interrupt #12 - DCD cpuss_interrupts_ipc_13_IRQHandler ; CPUSS Inter Process Communication Interrupt #13 - DCD cpuss_interrupts_ipc_14_IRQHandler ; CPUSS Inter Process Communication Interrupt #14 - DCD cpuss_interrupts_ipc_15_IRQHandler ; CPUSS Inter Process Communication Interrupt #15 - DCD scb_0_interrupt_IRQHandler ; Serial Communication Block #0 - DCD scb_1_interrupt_IRQHandler ; Serial Communication Block #1 - DCD scb_2_interrupt_IRQHandler ; Serial Communication Block #2 - DCD scb_3_interrupt_IRQHandler ; Serial Communication Block #3 - DCD scb_4_interrupt_IRQHandler ; Serial Communication Block #4 - DCD scb_5_interrupt_IRQHandler ; Serial Communication Block #5 - DCD scb_6_interrupt_IRQHandler ; Serial Communication Block #6 - DCD scb_7_interrupt_IRQHandler ; Serial Communication Block #7 - DCD csd_interrupt_IRQHandler ; CSD (Capsense) interrupt - DCD cpuss_interrupts_dw0_0_IRQHandler ; CPUSS DataWire #0, Channel #0 - DCD cpuss_interrupts_dw0_1_IRQHandler ; CPUSS DataWire #0, Channel #1 - DCD cpuss_interrupts_dw0_2_IRQHandler ; CPUSS DataWire #0, Channel #2 - DCD cpuss_interrupts_dw0_3_IRQHandler ; CPUSS DataWire #0, Channel #3 - DCD cpuss_interrupts_dw0_4_IRQHandler ; CPUSS DataWire #0, Channel #4 - DCD cpuss_interrupts_dw0_5_IRQHandler ; CPUSS DataWire #0, Channel #5 - DCD cpuss_interrupts_dw0_6_IRQHandler ; CPUSS DataWire #0, Channel #6 - DCD cpuss_interrupts_dw0_7_IRQHandler ; CPUSS DataWire #0, Channel #7 - DCD cpuss_interrupts_dw0_8_IRQHandler ; CPUSS DataWire #0, Channel #8 - DCD cpuss_interrupts_dw0_9_IRQHandler ; CPUSS DataWire #0, Channel #9 - DCD cpuss_interrupts_dw0_10_IRQHandler ; CPUSS DataWire #0, Channel #10 - DCD cpuss_interrupts_dw0_11_IRQHandler ; CPUSS DataWire #0, Channel #11 - DCD cpuss_interrupts_dw0_12_IRQHandler ; CPUSS DataWire #0, Channel #12 - DCD cpuss_interrupts_dw0_13_IRQHandler ; CPUSS DataWire #0, Channel #13 - DCD cpuss_interrupts_dw0_14_IRQHandler ; CPUSS DataWire #0, Channel #14 - DCD cpuss_interrupts_dw0_15_IRQHandler ; CPUSS DataWire #0, Channel #15 - DCD cpuss_interrupts_dw1_0_IRQHandler ; CPUSS DataWire #1, Channel #0 - DCD cpuss_interrupts_dw1_1_IRQHandler ; CPUSS DataWire #1, Channel #1 - DCD cpuss_interrupts_dw1_2_IRQHandler ; CPUSS DataWire #1, Channel #2 - DCD cpuss_interrupts_dw1_3_IRQHandler ; CPUSS DataWire #1, Channel #3 - DCD cpuss_interrupts_dw1_4_IRQHandler ; CPUSS DataWire #1, Channel #4 - DCD cpuss_interrupts_dw1_5_IRQHandler ; CPUSS DataWire #1, Channel #5 - DCD cpuss_interrupts_dw1_6_IRQHandler ; CPUSS DataWire #1, Channel #6 - DCD cpuss_interrupts_dw1_7_IRQHandler ; CPUSS DataWire #1, Channel #7 - DCD cpuss_interrupts_dw1_8_IRQHandler ; CPUSS DataWire #1, Channel #8 - DCD cpuss_interrupts_dw1_9_IRQHandler ; CPUSS DataWire #1, Channel #9 - DCD cpuss_interrupts_dw1_10_IRQHandler ; CPUSS DataWire #1, Channel #10 - DCD cpuss_interrupts_dw1_11_IRQHandler ; CPUSS DataWire #1, Channel #11 - DCD cpuss_interrupts_dw1_12_IRQHandler ; CPUSS DataWire #1, Channel #12 - DCD cpuss_interrupts_dw1_13_IRQHandler ; CPUSS DataWire #1, Channel #13 - DCD cpuss_interrupts_dw1_14_IRQHandler ; CPUSS DataWire #1, Channel #14 - DCD cpuss_interrupts_dw1_15_IRQHandler ; CPUSS DataWire #1, Channel #15 - DCD cpuss_interrupts_fault_0_IRQHandler ; CPUSS Fault Structure Interrupt #0 - DCD cpuss_interrupts_fault_1_IRQHandler ; CPUSS Fault Structure Interrupt #1 - DCD cpuss_interrupt_crypto_IRQHandler ; CRYPTO Accelerator Interrupt - DCD cpuss_interrupt_fm_IRQHandler ; FLASH Macro Interrupt - DCD cpuss_interrupts_cm0_cti_0_IRQHandler ; CM0+ CTI #0 - DCD cpuss_interrupts_cm0_cti_1_IRQHandler ; CM0+ CTI #1 - DCD cpuss_interrupts_cm4_cti_0_IRQHandler ; CM4 CTI #0 - DCD cpuss_interrupts_cm4_cti_1_IRQHandler ; CM4 CTI #1 - DCD tcpwm_0_interrupts_0_IRQHandler ; TCPWM #0, Counter #0 - DCD tcpwm_0_interrupts_1_IRQHandler ; TCPWM #0, Counter #1 - DCD tcpwm_0_interrupts_2_IRQHandler ; TCPWM #0, Counter #2 - DCD tcpwm_0_interrupts_3_IRQHandler ; TCPWM #0, Counter #3 - DCD tcpwm_0_interrupts_4_IRQHandler ; TCPWM #0, Counter #4 - DCD tcpwm_0_interrupts_5_IRQHandler ; TCPWM #0, Counter #5 - DCD tcpwm_0_interrupts_6_IRQHandler ; TCPWM #0, Counter #6 - DCD tcpwm_0_interrupts_7_IRQHandler ; TCPWM #0, Counter #7 - DCD tcpwm_1_interrupts_0_IRQHandler ; TCPWM #1, Counter #0 - DCD tcpwm_1_interrupts_1_IRQHandler ; TCPWM #1, Counter #1 - DCD tcpwm_1_interrupts_2_IRQHandler ; TCPWM #1, Counter #2 - DCD tcpwm_1_interrupts_3_IRQHandler ; TCPWM #1, Counter #3 - DCD tcpwm_1_interrupts_4_IRQHandler ; TCPWM #1, Counter #4 - DCD tcpwm_1_interrupts_5_IRQHandler ; TCPWM #1, Counter #5 - DCD tcpwm_1_interrupts_6_IRQHandler ; TCPWM #1, Counter #6 - DCD tcpwm_1_interrupts_7_IRQHandler ; TCPWM #1, Counter #7 - DCD tcpwm_1_interrupts_8_IRQHandler ; TCPWM #1, Counter #8 - DCD tcpwm_1_interrupts_9_IRQHandler ; TCPWM #1, Counter #9 - DCD tcpwm_1_interrupts_10_IRQHandler ; TCPWM #1, Counter #10 - DCD tcpwm_1_interrupts_11_IRQHandler ; TCPWM #1, Counter #11 - DCD tcpwm_1_interrupts_12_IRQHandler ; TCPWM #1, Counter #12 - DCD tcpwm_1_interrupts_13_IRQHandler ; TCPWM #1, Counter #13 - DCD tcpwm_1_interrupts_14_IRQHandler ; TCPWM #1, Counter #14 - DCD tcpwm_1_interrupts_15_IRQHandler ; TCPWM #1, Counter #15 - DCD tcpwm_1_interrupts_16_IRQHandler ; TCPWM #1, Counter #16 - DCD tcpwm_1_interrupts_17_IRQHandler ; TCPWM #1, Counter #17 - DCD tcpwm_1_interrupts_18_IRQHandler ; TCPWM #1, Counter #18 - DCD tcpwm_1_interrupts_19_IRQHandler ; TCPWM #1, Counter #19 - DCD tcpwm_1_interrupts_20_IRQHandler ; TCPWM #1, Counter #20 - DCD tcpwm_1_interrupts_21_IRQHandler ; TCPWM #1, Counter #21 - DCD tcpwm_1_interrupts_22_IRQHandler ; TCPWM #1, Counter #22 - DCD tcpwm_1_interrupts_23_IRQHandler ; TCPWM #1, Counter #23 - DCD udb_interrupts_0_IRQHandler ; UDB Interrupt #0 - DCD udb_interrupts_1_IRQHandler ; UDB Interrupt #1 - DCD udb_interrupts_2_IRQHandler ; UDB Interrupt #2 - DCD udb_interrupts_3_IRQHandler ; UDB Interrupt #3 - DCD udb_interrupts_4_IRQHandler ; UDB Interrupt #4 - DCD udb_interrupts_5_IRQHandler ; UDB Interrupt #5 - DCD udb_interrupts_6_IRQHandler ; UDB Interrupt #6 - DCD udb_interrupts_7_IRQHandler ; UDB Interrupt #7 - DCD udb_interrupts_8_IRQHandler ; UDB Interrupt #8 - DCD udb_interrupts_9_IRQHandler ; UDB Interrupt #9 - DCD udb_interrupts_10_IRQHandler ; UDB Interrupt #10 - DCD udb_interrupts_11_IRQHandler ; UDB Interrupt #11 - DCD udb_interrupts_12_IRQHandler ; UDB Interrupt #12 - DCD udb_interrupts_13_IRQHandler ; UDB Interrupt #13 - DCD udb_interrupts_14_IRQHandler ; UDB Interrupt #14 - DCD udb_interrupts_15_IRQHandler ; UDB Interrupt #15 - DCD pass_interrupt_sar_IRQHandler ; SAR ADC interrupt - DCD audioss_interrupt_i2s_IRQHandler ; I2S Audio interrupt - DCD audioss_interrupt_pdm_IRQHandler ; PDM/PCM Audio interrupt - DCD profile_interrupt_IRQHandler ; Energy Profiler interrupt - DCD smif_interrupt_IRQHandler ; Serial Memory Interface interrupt - DCD usb_interrupt_hi_IRQHandler ; USB Interrupt - DCD usb_interrupt_med_IRQHandler ; USB Interrupt - DCD usb_interrupt_lo_IRQHandler ; USB Interrupt - DCD pass_interrupt_dacs_IRQHandler ; Consolidated interrrupt for all DACs - -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - EXPORT __ramVectors - AREA RESET_RAM, READWRITE, NOINIT -__ramVectors SPACE __Vectors_Size - - - AREA |.text|, CODE, READONLY - - -; Weak function for startup customization -; -; Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) -; because this function is executed as the first instruction in the ResetHandler. -; The PDL is also not initialized to use the proper register offsets. -; The user of this function is responsible for initializing the PDL and resources before using them. -; -Cy_OnResetUser PROC - EXPORT Cy_OnResetUser [WEAK] - BX LR - ENDP - -; Reset Handler -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT Cy_SystemInitFpuEnable - IMPORT __main - - ; Define strong function for startup customization - BL Cy_OnResetUser - - ; Disable global interrupts - CPSID I - - ; Copy vectors from ROM to RAM - LDR r1, =__Vectors - LDR r0, =__ramVectors - LDR r2, =__Vectors_Size -Vectors_Copy - LDR r3, [r1] - STR r3, [r0] - ADDS r0, r0, #4 - ADDS r1, r1, #4 - SUBS r2, r2, #1 - CMP r2, #0 - BNE Vectors_Copy - - ; Update Vector Table Offset Register. */ - LDR r0, =__ramVectors - LDR r1, =0xE000ED08 - STR r0, [r1] - dsb 0xF - - ; Enable the FPU if used - LDR R0, =Cy_SystemInitFpuEnable - BLX R0 - - LDR R0, =__main - BLX R0 - - ; Should never get here - B . - - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP - -Cy_SysLib_FaultHandler PROC - EXPORT Cy_SysLib_FaultHandler [WEAK] - B . - ENDP -HardFault_Wrapper\ - PROC - EXPORT HardFault_Wrapper [WEAK] - movs r0, #4 - mov r1, LR - tst r0, r1 - beq L_MSP - mrs r0, PSP - bl L_API_call -L_MSP - mrs r0, MSP -L_API_call - bl Cy_SysLib_FaultHandler - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B HardFault_Wrapper - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B HardFault_Wrapper - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B HardFault_Wrapper - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B HardFault_Wrapper - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - EXPORT Default_Handler [WEAK] - EXPORT ioss_interrupts_gpio_0_IRQHandler [WEAK] - EXPORT ioss_interrupts_gpio_1_IRQHandler [WEAK] - EXPORT ioss_interrupts_gpio_2_IRQHandler [WEAK] - EXPORT ioss_interrupts_gpio_3_IRQHandler [WEAK] - EXPORT ioss_interrupts_gpio_4_IRQHandler [WEAK] - EXPORT ioss_interrupts_gpio_5_IRQHandler [WEAK] - EXPORT ioss_interrupts_gpio_6_IRQHandler [WEAK] - EXPORT ioss_interrupts_gpio_7_IRQHandler [WEAK] - EXPORT ioss_interrupts_gpio_8_IRQHandler [WEAK] - EXPORT ioss_interrupts_gpio_9_IRQHandler [WEAK] - EXPORT ioss_interrupts_gpio_10_IRQHandler [WEAK] - EXPORT ioss_interrupts_gpio_11_IRQHandler [WEAK] - EXPORT ioss_interrupts_gpio_12_IRQHandler [WEAK] - EXPORT ioss_interrupts_gpio_13_IRQHandler [WEAK] - EXPORT ioss_interrupts_gpio_14_IRQHandler [WEAK] - EXPORT ioss_interrupt_gpio_IRQHandler [WEAK] - EXPORT ioss_interrupt_vdd_IRQHandler [WEAK] - EXPORT lpcomp_interrupt_IRQHandler [WEAK] - EXPORT scb_8_interrupt_IRQHandler [WEAK] - EXPORT srss_interrupt_mcwdt_0_IRQHandler [WEAK] - EXPORT srss_interrupt_mcwdt_1_IRQHandler [WEAK] - EXPORT srss_interrupt_backup_IRQHandler [WEAK] - EXPORT srss_interrupt_IRQHandler [WEAK] - EXPORT pass_interrupt_ctbs_IRQHandler [WEAK] - EXPORT bless_interrupt_IRQHandler [WEAK] - EXPORT cpuss_interrupts_ipc_0_IRQHandler [WEAK] - EXPORT cpuss_interrupts_ipc_1_IRQHandler [WEAK] - EXPORT cpuss_interrupts_ipc_2_IRQHandler [WEAK] - EXPORT cpuss_interrupts_ipc_3_IRQHandler [WEAK] - EXPORT cpuss_interrupts_ipc_4_IRQHandler [WEAK] - EXPORT cpuss_interrupts_ipc_5_IRQHandler [WEAK] - EXPORT cpuss_interrupts_ipc_6_IRQHandler [WEAK] - EXPORT cpuss_interrupts_ipc_7_IRQHandler [WEAK] - EXPORT cpuss_interrupts_ipc_8_IRQHandler [WEAK] - EXPORT cpuss_interrupts_ipc_9_IRQHandler [WEAK] - EXPORT cpuss_interrupts_ipc_10_IRQHandler [WEAK] - EXPORT cpuss_interrupts_ipc_11_IRQHandler [WEAK] - EXPORT cpuss_interrupts_ipc_12_IRQHandler [WEAK] - EXPORT cpuss_interrupts_ipc_13_IRQHandler [WEAK] - EXPORT cpuss_interrupts_ipc_14_IRQHandler [WEAK] - EXPORT cpuss_interrupts_ipc_15_IRQHandler [WEAK] - EXPORT scb_0_interrupt_IRQHandler [WEAK] - EXPORT scb_1_interrupt_IRQHandler [WEAK] - EXPORT scb_2_interrupt_IRQHandler [WEAK] - EXPORT scb_3_interrupt_IRQHandler [WEAK] - EXPORT scb_4_interrupt_IRQHandler [WEAK] - EXPORT scb_5_interrupt_IRQHandler [WEAK] - EXPORT scb_6_interrupt_IRQHandler [WEAK] - EXPORT scb_7_interrupt_IRQHandler [WEAK] - EXPORT csd_interrupt_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw0_0_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw0_1_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw0_2_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw0_3_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw0_4_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw0_5_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw0_6_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw0_7_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw0_8_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw0_9_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw0_10_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw0_11_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw0_12_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw0_13_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw0_14_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw0_15_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw1_0_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw1_1_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw1_2_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw1_3_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw1_4_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw1_5_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw1_6_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw1_7_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw1_8_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw1_9_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw1_10_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw1_11_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw1_12_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw1_13_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw1_14_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw1_15_IRQHandler [WEAK] - EXPORT cpuss_interrupts_fault_0_IRQHandler [WEAK] - EXPORT cpuss_interrupts_fault_1_IRQHandler [WEAK] - EXPORT cpuss_interrupt_crypto_IRQHandler [WEAK] - EXPORT cpuss_interrupt_fm_IRQHandler [WEAK] - EXPORT cpuss_interrupts_cm0_cti_0_IRQHandler [WEAK] - EXPORT cpuss_interrupts_cm0_cti_1_IRQHandler [WEAK] - EXPORT cpuss_interrupts_cm4_cti_0_IRQHandler [WEAK] - EXPORT cpuss_interrupts_cm4_cti_1_IRQHandler [WEAK] - EXPORT tcpwm_0_interrupts_0_IRQHandler [WEAK] - EXPORT tcpwm_0_interrupts_1_IRQHandler [WEAK] - EXPORT tcpwm_0_interrupts_2_IRQHandler [WEAK] - EXPORT tcpwm_0_interrupts_3_IRQHandler [WEAK] - EXPORT tcpwm_0_interrupts_4_IRQHandler [WEAK] - EXPORT tcpwm_0_interrupts_5_IRQHandler [WEAK] - EXPORT tcpwm_0_interrupts_6_IRQHandler [WEAK] - EXPORT tcpwm_0_interrupts_7_IRQHandler [WEAK] - EXPORT tcpwm_1_interrupts_0_IRQHandler [WEAK] - EXPORT tcpwm_1_interrupts_1_IRQHandler [WEAK] - EXPORT tcpwm_1_interrupts_2_IRQHandler [WEAK] - EXPORT tcpwm_1_interrupts_3_IRQHandler [WEAK] - EXPORT tcpwm_1_interrupts_4_IRQHandler [WEAK] - EXPORT tcpwm_1_interrupts_5_IRQHandler [WEAK] - EXPORT tcpwm_1_interrupts_6_IRQHandler [WEAK] - EXPORT tcpwm_1_interrupts_7_IRQHandler [WEAK] - EXPORT tcpwm_1_interrupts_8_IRQHandler [WEAK] - EXPORT tcpwm_1_interrupts_9_IRQHandler [WEAK] - EXPORT tcpwm_1_interrupts_10_IRQHandler [WEAK] - EXPORT tcpwm_1_interrupts_11_IRQHandler [WEAK] - EXPORT tcpwm_1_interrupts_12_IRQHandler [WEAK] - EXPORT tcpwm_1_interrupts_13_IRQHandler [WEAK] - EXPORT tcpwm_1_interrupts_14_IRQHandler [WEAK] - EXPORT tcpwm_1_interrupts_15_IRQHandler [WEAK] - EXPORT tcpwm_1_interrupts_16_IRQHandler [WEAK] - EXPORT tcpwm_1_interrupts_17_IRQHandler [WEAK] - EXPORT tcpwm_1_interrupts_18_IRQHandler [WEAK] - EXPORT tcpwm_1_interrupts_19_IRQHandler [WEAK] - EXPORT tcpwm_1_interrupts_20_IRQHandler [WEAK] - EXPORT tcpwm_1_interrupts_21_IRQHandler [WEAK] - EXPORT tcpwm_1_interrupts_22_IRQHandler [WEAK] - EXPORT tcpwm_1_interrupts_23_IRQHandler [WEAK] - EXPORT udb_interrupts_0_IRQHandler [WEAK] - EXPORT udb_interrupts_1_IRQHandler [WEAK] - EXPORT udb_interrupts_2_IRQHandler [WEAK] - EXPORT udb_interrupts_3_IRQHandler [WEAK] - EXPORT udb_interrupts_4_IRQHandler [WEAK] - EXPORT udb_interrupts_5_IRQHandler [WEAK] - EXPORT udb_interrupts_6_IRQHandler [WEAK] - EXPORT udb_interrupts_7_IRQHandler [WEAK] - EXPORT udb_interrupts_8_IRQHandler [WEAK] - EXPORT udb_interrupts_9_IRQHandler [WEAK] - EXPORT udb_interrupts_10_IRQHandler [WEAK] - EXPORT udb_interrupts_11_IRQHandler [WEAK] - EXPORT udb_interrupts_12_IRQHandler [WEAK] - EXPORT udb_interrupts_13_IRQHandler [WEAK] - EXPORT udb_interrupts_14_IRQHandler [WEAK] - EXPORT udb_interrupts_15_IRQHandler [WEAK] - EXPORT pass_interrupt_sar_IRQHandler [WEAK] - EXPORT audioss_interrupt_i2s_IRQHandler [WEAK] - EXPORT audioss_interrupt_pdm_IRQHandler [WEAK] - EXPORT profile_interrupt_IRQHandler [WEAK] - EXPORT smif_interrupt_IRQHandler [WEAK] - EXPORT usb_interrupt_hi_IRQHandler [WEAK] - EXPORT usb_interrupt_med_IRQHandler [WEAK] - EXPORT usb_interrupt_lo_IRQHandler [WEAK] - EXPORT pass_interrupt_dacs_IRQHandler [WEAK] - -ioss_interrupts_gpio_0_IRQHandler -ioss_interrupts_gpio_1_IRQHandler -ioss_interrupts_gpio_2_IRQHandler -ioss_interrupts_gpio_3_IRQHandler -ioss_interrupts_gpio_4_IRQHandler -ioss_interrupts_gpio_5_IRQHandler -ioss_interrupts_gpio_6_IRQHandler -ioss_interrupts_gpio_7_IRQHandler -ioss_interrupts_gpio_8_IRQHandler -ioss_interrupts_gpio_9_IRQHandler -ioss_interrupts_gpio_10_IRQHandler -ioss_interrupts_gpio_11_IRQHandler -ioss_interrupts_gpio_12_IRQHandler -ioss_interrupts_gpio_13_IRQHandler -ioss_interrupts_gpio_14_IRQHandler -ioss_interrupt_gpio_IRQHandler -ioss_interrupt_vdd_IRQHandler -lpcomp_interrupt_IRQHandler -scb_8_interrupt_IRQHandler -srss_interrupt_mcwdt_0_IRQHandler -srss_interrupt_mcwdt_1_IRQHandler -srss_interrupt_backup_IRQHandler -srss_interrupt_IRQHandler -pass_interrupt_ctbs_IRQHandler -bless_interrupt_IRQHandler -cpuss_interrupts_ipc_0_IRQHandler -cpuss_interrupts_ipc_1_IRQHandler -cpuss_interrupts_ipc_2_IRQHandler -cpuss_interrupts_ipc_3_IRQHandler -cpuss_interrupts_ipc_4_IRQHandler -cpuss_interrupts_ipc_5_IRQHandler -cpuss_interrupts_ipc_6_IRQHandler -cpuss_interrupts_ipc_7_IRQHandler -cpuss_interrupts_ipc_8_IRQHandler -cpuss_interrupts_ipc_9_IRQHandler -cpuss_interrupts_ipc_10_IRQHandler -cpuss_interrupts_ipc_11_IRQHandler -cpuss_interrupts_ipc_12_IRQHandler -cpuss_interrupts_ipc_13_IRQHandler -cpuss_interrupts_ipc_14_IRQHandler -cpuss_interrupts_ipc_15_IRQHandler -scb_0_interrupt_IRQHandler -scb_1_interrupt_IRQHandler -scb_2_interrupt_IRQHandler -scb_3_interrupt_IRQHandler -scb_4_interrupt_IRQHandler -scb_5_interrupt_IRQHandler -scb_6_interrupt_IRQHandler -scb_7_interrupt_IRQHandler -csd_interrupt_IRQHandler -cpuss_interrupts_dw0_0_IRQHandler -cpuss_interrupts_dw0_1_IRQHandler -cpuss_interrupts_dw0_2_IRQHandler -cpuss_interrupts_dw0_3_IRQHandler -cpuss_interrupts_dw0_4_IRQHandler -cpuss_interrupts_dw0_5_IRQHandler -cpuss_interrupts_dw0_6_IRQHandler -cpuss_interrupts_dw0_7_IRQHandler -cpuss_interrupts_dw0_8_IRQHandler -cpuss_interrupts_dw0_9_IRQHandler -cpuss_interrupts_dw0_10_IRQHandler -cpuss_interrupts_dw0_11_IRQHandler -cpuss_interrupts_dw0_12_IRQHandler -cpuss_interrupts_dw0_13_IRQHandler -cpuss_interrupts_dw0_14_IRQHandler -cpuss_interrupts_dw0_15_IRQHandler -cpuss_interrupts_dw1_0_IRQHandler -cpuss_interrupts_dw1_1_IRQHandler -cpuss_interrupts_dw1_2_IRQHandler -cpuss_interrupts_dw1_3_IRQHandler -cpuss_interrupts_dw1_4_IRQHandler -cpuss_interrupts_dw1_5_IRQHandler -cpuss_interrupts_dw1_6_IRQHandler -cpuss_interrupts_dw1_7_IRQHandler -cpuss_interrupts_dw1_8_IRQHandler -cpuss_interrupts_dw1_9_IRQHandler -cpuss_interrupts_dw1_10_IRQHandler -cpuss_interrupts_dw1_11_IRQHandler -cpuss_interrupts_dw1_12_IRQHandler -cpuss_interrupts_dw1_13_IRQHandler -cpuss_interrupts_dw1_14_IRQHandler -cpuss_interrupts_dw1_15_IRQHandler -cpuss_interrupts_fault_0_IRQHandler -cpuss_interrupts_fault_1_IRQHandler -cpuss_interrupt_crypto_IRQHandler -cpuss_interrupt_fm_IRQHandler -cpuss_interrupts_cm0_cti_0_IRQHandler -cpuss_interrupts_cm0_cti_1_IRQHandler -cpuss_interrupts_cm4_cti_0_IRQHandler -cpuss_interrupts_cm4_cti_1_IRQHandler -tcpwm_0_interrupts_0_IRQHandler -tcpwm_0_interrupts_1_IRQHandler -tcpwm_0_interrupts_2_IRQHandler -tcpwm_0_interrupts_3_IRQHandler -tcpwm_0_interrupts_4_IRQHandler -tcpwm_0_interrupts_5_IRQHandler -tcpwm_0_interrupts_6_IRQHandler -tcpwm_0_interrupts_7_IRQHandler -tcpwm_1_interrupts_0_IRQHandler -tcpwm_1_interrupts_1_IRQHandler -tcpwm_1_interrupts_2_IRQHandler -tcpwm_1_interrupts_3_IRQHandler -tcpwm_1_interrupts_4_IRQHandler -tcpwm_1_interrupts_5_IRQHandler -tcpwm_1_interrupts_6_IRQHandler -tcpwm_1_interrupts_7_IRQHandler -tcpwm_1_interrupts_8_IRQHandler -tcpwm_1_interrupts_9_IRQHandler -tcpwm_1_interrupts_10_IRQHandler -tcpwm_1_interrupts_11_IRQHandler -tcpwm_1_interrupts_12_IRQHandler -tcpwm_1_interrupts_13_IRQHandler -tcpwm_1_interrupts_14_IRQHandler -tcpwm_1_interrupts_15_IRQHandler -tcpwm_1_interrupts_16_IRQHandler -tcpwm_1_interrupts_17_IRQHandler -tcpwm_1_interrupts_18_IRQHandler -tcpwm_1_interrupts_19_IRQHandler -tcpwm_1_interrupts_20_IRQHandler -tcpwm_1_interrupts_21_IRQHandler -tcpwm_1_interrupts_22_IRQHandler -tcpwm_1_interrupts_23_IRQHandler -udb_interrupts_0_IRQHandler -udb_interrupts_1_IRQHandler -udb_interrupts_2_IRQHandler -udb_interrupts_3_IRQHandler -udb_interrupts_4_IRQHandler -udb_interrupts_5_IRQHandler -udb_interrupts_6_IRQHandler -udb_interrupts_7_IRQHandler -udb_interrupts_8_IRQHandler -udb_interrupts_9_IRQHandler -udb_interrupts_10_IRQHandler -udb_interrupts_11_IRQHandler -udb_interrupts_12_IRQHandler -udb_interrupts_13_IRQHandler -udb_interrupts_14_IRQHandler -udb_interrupts_15_IRQHandler -pass_interrupt_sar_IRQHandler -audioss_interrupt_i2s_IRQHandler -audioss_interrupt_pdm_IRQHandler -profile_interrupt_IRQHandler -smif_interrupt_IRQHandler -usb_interrupt_hi_IRQHandler -usb_interrupt_med_IRQHandler -usb_interrupt_lo_IRQHandler -pass_interrupt_dacs_IRQHandler - - B . - ENDP - - ALIGN - - END - - -; [] END OF FILE diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xx7_cm4.ld b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xx7_cm4.ld deleted file mode 100644 index 7c8b13a05c..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xx7_cm4.ld +++ /dev/null @@ -1,447 +0,0 @@ -/***************************************************************************//** -* \file cyb06xx7_cm4.ld -* \version 2.70.1 -* -* Linker file for the GNU C compiler. -* -* The main purpose of the linker script is to describe how the sections in the -* input files should be mapped into the output file, and to control the memory -* layout of the output file. -* -* \note The entry point location is fixed and starts at 0x10000000. The valid -* application image should be placed there. -* -* \note The linker files included with the PDL template projects must be generic -* and handle all common use cases. Your project may not use every section -* defined in the linker files. In that case you may see warnings during the -* build process. In your project, you can simply comment out or remove the -* relevant code in the linker file. -* -******************************************************************************** -* \copyright -* Copyright 2016-2020 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ - -OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") -SEARCH_DIR(.) -GROUP(-lgcc -lc -lnosys) -ENTRY(Reset_Handler) - -#if !defined(MBED_ROM_START) - #define MBED_ROM_START 0x10000000 -#endif - -/* MBED_APP_START is being used by the bootloader build script and -* will be calculate by the system. Without bootloader the MBED_APP_START -* is equal to MBED_ROM_START -*/ -#if !defined(MBED_APP_START) - #define MBED_APP_START MBED_ROM_START -#endif - -#if !defined(MBED_ROM_SIZE) - #define MBED_ROM_SIZE 0x000D0000 -#endif - -/* MBED_APP_SIZE is being used by the bootloader build script and -* will be calculate by the system. Without bootloader the MBED_APP_SIZE -* is equal to MBED_ROM_SIZE -*/ -#if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE MBED_ROM_SIZE -#endif - -#if !defined(MBED_RAM_START) - #define MBED_RAM_START 0x08000000 -#endif - -#if !defined(MBED_RAM_SIZE) - #define MBED_RAM_SIZE 0x0002A000 -#endif - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -/* The size of the stack section at the end of CM4 SRAM */ -STACK_SIZE = MBED_BOOT_STACK_SIZE; - -/* The size of the MCU boot header area at the start of FLASH */ -BOOT_HEADER_SIZE = 0x400; - -/* Force symbol to be entered in the output file as an undefined symbol. Doing -* this may, for example, trigger linking of additional modules from standard -* libraries. You may list several symbols for each EXTERN, and you may use -* EXTERN multiple times. This command has the same effect as the -u command-line -* option. -*/ -EXTERN(Reset_Handler) - -/* The MEMORY section below describes the location and size of blocks of memory in the target. -* Use this section to specify the memory regions available for allocation. -*/ -MEMORY -{ - /* The ram and flash regions control RAM and flash memory allocation for the CM4 core. - */ - ram (rwx) : ORIGIN = MBED_RAM_START, LENGTH = MBED_RAM_SIZE - flash (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE - - /* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash. - * You can assign sections to this memory region for only one of the cores. - * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. - * Therefore, repurposing this memory region will prevent such middleware from operation. - */ - em_eeprom (rx) : ORIGIN = 0x14000000, LENGTH = 0x8000 /* 32 KB */ - - /* The following regions define device specific memory regions and must not be changed. */ - sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 /* Supervisory flash: User data */ - sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 /* Supervisory flash: Normal Access Restrictions (NAR) */ - sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 /* Supervisory flash: Public Key */ - sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 */ - sflash_rtoc_2 (rx) : ORIGIN = 0x16007E00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 Copy */ - xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */ - efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */ -} - -/* Library configurations */ -GROUP(libgcc.a libc.a libm.a libnosys.a) - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __Vectors_End - * __Vectors_Size - */ - - -SECTIONS -{ - /* Cortex-M4 application flash area */ - .text ORIGIN(flash) + BOOT_HEADER_SIZE : - { - /* Cortex-M4 flash vector table */ - . = ALIGN(4); - __Vectors = . ; - KEEP(*(.vectors)) - . = ALIGN(4); - __Vectors_End = .; - __Vectors_Size = __Vectors_End - __Vectors; - __end__ = .; - - . = ALIGN(4); - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - /* Read-only code (constants). */ - *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*) - - KEEP(*(.eh_frame*)) - } > flash - - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > flash - - __exidx_start = .; - - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > flash - __exidx_end = .; - - - /* To copy multiple ROM to RAM sections, - * uncomment .copy.table section and, - * define __STARTUP_COPY_MULTIPLE in startup_psoc6_01_cm4.S */ - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - - /* Copy interrupt vectors from flash to RAM */ - LONG (__Vectors) /* From */ - LONG (__ram_vectors_start__) /* To */ - LONG (__Vectors_End - __Vectors) /* Size */ - - /* Copy data section to RAM */ - LONG (__etext) /* From */ - LONG (__data_start__) /* To */ - LONG (__data_end__ - __data_start__) /* Size */ - - __copy_table_end__ = .; - } > flash - - - /* To clear multiple BSS sections, - * uncomment .zero.table section and, - * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_01_cm4.S */ - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - LONG (__bss_start__) - LONG (__bss_end__ - __bss_start__) - __zero_table_end__ = .; - } > flash - - __etext = . ; - - - .ramVectors (NOLOAD) : ALIGN(8) - { - __ram_vectors_start__ = .; - KEEP(*(.ram_vectors)) - __ram_vectors_end__ = .; - } > ram - - - .data __ram_vectors_end__ : AT (__etext) - { - __data_start__ = .; - - *(vtable) - *(.data*) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(4); - - KEEP(*(.cy_ramfunc*)) - . = ALIGN(4); - - __data_end__ = .; - - } > ram - - - /* Place variables in the section that should not be initialized during the - * device startup. - */ - .noinit (NOLOAD) : ALIGN(8) - { - KEEP(*(.noinit)) - } > ram - - - /* The uninitialized global or static variables are placed in this section. - * - * The NOLOAD attribute tells linker that .bss section does not consume - * any space in the image. The NOLOAD attribute changes the .bss type to - * NOBITS, and that makes linker to A) not allocate section in memory, and - * A) put information to clear the section with all zeros during application - * loading. - * - * Without the NOLOAD attribute, the .bss section might get PROGBITS type. - * This makes linker to A) allocate zeroed section in memory, and B) copy - * this section to RAM during application loading. - */ - .bss (NOLOAD): - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > ram - - - .heap (NOLOAD): - { - __HeapBase = .; - __end__ = .; - end = __end__; - KEEP(*(.heap*)) - . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE; - __HeapLimit = .; - } > ram - - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(ram) + LENGTH(ram); - __StackLimit = __StackTop - STACK_SIZE; - PROVIDE(__stack = __StackTop); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") - - - /* Used for the digital signature of the secure application and the Bootloader SDK application. - * The size of the section depends on the required data size. */ - .cy_app_signature ORIGIN(flash) + LENGTH(flash) - 256 : - { - KEEP(*(.cy_app_signature)) - } > flash - - - /* Emulated EEPROM Flash area */ - .cy_em_eeprom : - { - KEEP(*(.cy_em_eeprom)) - } > em_eeprom - - - /* Supervisory Flash: User data */ - .cy_sflash_user_data : - { - KEEP(*(.cy_sflash_user_data)) - } > sflash_user_data - - - /* Supervisory Flash: Normal Access Restrictions (NAR) */ - .cy_sflash_nar : - { - KEEP(*(.cy_sflash_nar)) - } > sflash_nar - - - /* Supervisory Flash: Public Key */ - .cy_sflash_public_key : - { - KEEP(*(.cy_sflash_public_key)) - } > sflash_public_key - - - /* Supervisory Flash: Table of Content # 2 */ - .cy_toc_part2 : - { - KEEP(*(.cy_toc_part2)) - } > sflash_toc_2 - - - /* Supervisory Flash: Table of Content # 2 Copy */ - .cy_rtoc_part2 : - { - KEEP(*(.cy_rtoc_part2)) - } > sflash_rtoc_2 - - - /* Places the code in the Execute in Place (XIP) section. See the smif driver - * documentation for details. - */ - .cy_xip : - { - KEEP(*(.cy_xip)) - } > xip - - - /* eFuse */ - .cy_efuse : - { - KEEP(*(.cy_efuse)) - } > efuse - - - /* These sections are used for additional metadata (silicon revision, - * Silicon/JTAG ID, etc.) storage. - */ - .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE -} - - -/* The following symbols used by the cymcuelftool. */ -/* Flash */ -__cy_memory_0_start = 0x10000000; -__cy_memory_0_length = 0x000D0000; -__cy_memory_0_row_size = 0x200; - -/* Emulated EEPROM Flash area */ -__cy_memory_1_start = 0x14000000; -__cy_memory_1_length = 0x8000; -__cy_memory_1_row_size = 0x200; - -/* Supervisory Flash */ -__cy_memory_2_start = 0x16000000; -__cy_memory_2_length = 0x8000; -__cy_memory_2_row_size = 0x200; - -/* XIP */ -__cy_memory_3_start = 0x18000000; -__cy_memory_3_length = 0x08000000; -__cy_memory_3_row_size = 0x200; - -/* eFuse */ -__cy_memory_4_start = 0x90700000; -__cy_memory_4_length = 0x100000; -__cy_memory_4_row_size = 1; - -/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_01_cm4.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_01_cm4.S deleted file mode 100644 index 3c2f44d1e0..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_01_cm4.S +++ /dev/null @@ -1,631 +0,0 @@ -/**************************************************************************//** - * @file startup_psoc6_01_cm4.S - * @brief CMSIS Core Device Startup File for - * ARMCM4 Device Series - * @version V5.00 - * @date 02. March 2016 - ******************************************************************************/ -/* - * Copyright (c) 2009-2016 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - - /* Address of the NMI handler */ - #define CY_NMI_HANLDER_ADDR 0x0000000D - - /* The CPU VTOR register */ - #define CY_CPU_VTOR_ADDR 0xE000ED08 - - /* Copy flash vectors and data section to RAM */ - #define __STARTUP_COPY_MULTIPLE - - /* Clear single BSS section */ - #define __STARTUP_CLEAR_BSS - - .syntax unified - .arch armv7-m - - .section .stack - .align 3 -#ifdef __STACK_SIZE - .equ Stack_Size, __STACK_SIZE -#else - .equ Stack_Size, 0x00001000 -#endif - .globl __StackTop - .globl __StackLimit -__StackLimit: - .space Stack_Size - .size __StackLimit, . - __StackLimit -__StackTop: - .size __StackTop, . - __StackTop - - .section .heap - .align 3 -#ifdef __HEAP_SIZE - .equ Heap_Size, __HEAP_SIZE -#else - .equ Heap_Size, 0x00000400 -#endif - .globl __HeapBase - .globl __HeapLimit -__HeapBase: - .if Heap_Size - .space Heap_Size - .endif - .size __HeapBase, . - __HeapBase -__HeapLimit: - .size __HeapLimit, . - __HeapLimit - - .section .vectors - .align 2 - .globl __Vectors -__Vectors: - .long __StackTop /* Top of Stack */ - .long Reset_Handler /* Reset Handler */ - .long CY_NMI_HANLDER_ADDR /* NMI Handler */ - .long HardFault_Handler /* Hard Fault Handler */ - .long MemManage_Handler /* MPU Fault Handler */ - .long BusFault_Handler /* Bus Fault Handler */ - .long UsageFault_Handler /* Usage Fault Handler */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long SVC_Handler /* SVCall Handler */ - .long DebugMon_Handler /* Debug Monitor Handler */ - .long 0 /* Reserved */ - .long PendSV_Handler /* PendSV Handler */ - .long SysTick_Handler /* SysTick Handler */ - - /* External interrupts Description */ - .long ioss_interrupts_gpio_0_IRQHandler /* GPIO Port Interrupt #0 */ - .long ioss_interrupts_gpio_1_IRQHandler /* GPIO Port Interrupt #1 */ - .long ioss_interrupts_gpio_2_IRQHandler /* GPIO Port Interrupt #2 */ - .long ioss_interrupts_gpio_3_IRQHandler /* GPIO Port Interrupt #3 */ - .long ioss_interrupts_gpio_4_IRQHandler /* GPIO Port Interrupt #4 */ - .long ioss_interrupts_gpio_5_IRQHandler /* GPIO Port Interrupt #5 */ - .long ioss_interrupts_gpio_6_IRQHandler /* GPIO Port Interrupt #6 */ - .long ioss_interrupts_gpio_7_IRQHandler /* GPIO Port Interrupt #7 */ - .long ioss_interrupts_gpio_8_IRQHandler /* GPIO Port Interrupt #8 */ - .long ioss_interrupts_gpio_9_IRQHandler /* GPIO Port Interrupt #9 */ - .long ioss_interrupts_gpio_10_IRQHandler /* GPIO Port Interrupt #10 */ - .long ioss_interrupts_gpio_11_IRQHandler /* GPIO Port Interrupt #11 */ - .long ioss_interrupts_gpio_12_IRQHandler /* GPIO Port Interrupt #12 */ - .long ioss_interrupts_gpio_13_IRQHandler /* GPIO Port Interrupt #13 */ - .long ioss_interrupts_gpio_14_IRQHandler /* GPIO Port Interrupt #14 */ - .long ioss_interrupt_gpio_IRQHandler /* GPIO All Ports */ - .long ioss_interrupt_vdd_IRQHandler /* GPIO Supply Detect Interrupt */ - .long lpcomp_interrupt_IRQHandler /* Low Power Comparator Interrupt */ - .long scb_8_interrupt_IRQHandler /* Serial Communication Block #8 (DeepSleep capable) */ - .long srss_interrupt_mcwdt_0_IRQHandler /* Multi Counter Watchdog Timer interrupt */ - .long srss_interrupt_mcwdt_1_IRQHandler /* Multi Counter Watchdog Timer interrupt */ - .long srss_interrupt_backup_IRQHandler /* Backup domain interrupt */ - .long srss_interrupt_IRQHandler /* Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ - .long pass_interrupt_ctbs_IRQHandler /* CTBm Interrupt (all CTBms) */ - .long bless_interrupt_IRQHandler /* Bluetooth Radio interrupt */ - .long cpuss_interrupts_ipc_0_IRQHandler /* CPUSS Inter Process Communication Interrupt #0 */ - .long cpuss_interrupts_ipc_1_IRQHandler /* CPUSS Inter Process Communication Interrupt #1 */ - .long cpuss_interrupts_ipc_2_IRQHandler /* CPUSS Inter Process Communication Interrupt #2 */ - .long cpuss_interrupts_ipc_3_IRQHandler /* CPUSS Inter Process Communication Interrupt #3 */ - .long cpuss_interrupts_ipc_4_IRQHandler /* CPUSS Inter Process Communication Interrupt #4 */ - .long cpuss_interrupts_ipc_5_IRQHandler /* CPUSS Inter Process Communication Interrupt #5 */ - .long cpuss_interrupts_ipc_6_IRQHandler /* CPUSS Inter Process Communication Interrupt #6 */ - .long cpuss_interrupts_ipc_7_IRQHandler /* CPUSS Inter Process Communication Interrupt #7 */ - .long cpuss_interrupts_ipc_8_IRQHandler /* CPUSS Inter Process Communication Interrupt #8 */ - .long cpuss_interrupts_ipc_9_IRQHandler /* CPUSS Inter Process Communication Interrupt #9 */ - .long cpuss_interrupts_ipc_10_IRQHandler /* CPUSS Inter Process Communication Interrupt #10 */ - .long cpuss_interrupts_ipc_11_IRQHandler /* CPUSS Inter Process Communication Interrupt #11 */ - .long cpuss_interrupts_ipc_12_IRQHandler /* CPUSS Inter Process Communication Interrupt #12 */ - .long cpuss_interrupts_ipc_13_IRQHandler /* CPUSS Inter Process Communication Interrupt #13 */ - .long cpuss_interrupts_ipc_14_IRQHandler /* CPUSS Inter Process Communication Interrupt #14 */ - .long cpuss_interrupts_ipc_15_IRQHandler /* CPUSS Inter Process Communication Interrupt #15 */ - .long scb_0_interrupt_IRQHandler /* Serial Communication Block #0 */ - .long scb_1_interrupt_IRQHandler /* Serial Communication Block #1 */ - .long scb_2_interrupt_IRQHandler /* Serial Communication Block #2 */ - .long scb_3_interrupt_IRQHandler /* Serial Communication Block #3 */ - .long scb_4_interrupt_IRQHandler /* Serial Communication Block #4 */ - .long scb_5_interrupt_IRQHandler /* Serial Communication Block #5 */ - .long scb_6_interrupt_IRQHandler /* Serial Communication Block #6 */ - .long scb_7_interrupt_IRQHandler /* Serial Communication Block #7 */ - .long csd_interrupt_IRQHandler /* CSD (Capsense) interrupt */ - .long cpuss_interrupts_dw0_0_IRQHandler /* CPUSS DataWire #0, Channel #0 */ - .long cpuss_interrupts_dw0_1_IRQHandler /* CPUSS DataWire #0, Channel #1 */ - .long cpuss_interrupts_dw0_2_IRQHandler /* CPUSS DataWire #0, Channel #2 */ - .long cpuss_interrupts_dw0_3_IRQHandler /* CPUSS DataWire #0, Channel #3 */ - .long cpuss_interrupts_dw0_4_IRQHandler /* CPUSS DataWire #0, Channel #4 */ - .long cpuss_interrupts_dw0_5_IRQHandler /* CPUSS DataWire #0, Channel #5 */ - .long cpuss_interrupts_dw0_6_IRQHandler /* CPUSS DataWire #0, Channel #6 */ - .long cpuss_interrupts_dw0_7_IRQHandler /* CPUSS DataWire #0, Channel #7 */ - .long cpuss_interrupts_dw0_8_IRQHandler /* CPUSS DataWire #0, Channel #8 */ - .long cpuss_interrupts_dw0_9_IRQHandler /* CPUSS DataWire #0, Channel #9 */ - .long cpuss_interrupts_dw0_10_IRQHandler /* CPUSS DataWire #0, Channel #10 */ - .long cpuss_interrupts_dw0_11_IRQHandler /* CPUSS DataWire #0, Channel #11 */ - .long cpuss_interrupts_dw0_12_IRQHandler /* CPUSS DataWire #0, Channel #12 */ - .long cpuss_interrupts_dw0_13_IRQHandler /* CPUSS DataWire #0, Channel #13 */ - .long cpuss_interrupts_dw0_14_IRQHandler /* CPUSS DataWire #0, Channel #14 */ - .long cpuss_interrupts_dw0_15_IRQHandler /* CPUSS DataWire #0, Channel #15 */ - .long cpuss_interrupts_dw1_0_IRQHandler /* CPUSS DataWire #1, Channel #0 */ - .long cpuss_interrupts_dw1_1_IRQHandler /* CPUSS DataWire #1, Channel #1 */ - .long cpuss_interrupts_dw1_2_IRQHandler /* CPUSS DataWire #1, Channel #2 */ - .long cpuss_interrupts_dw1_3_IRQHandler /* CPUSS DataWire #1, Channel #3 */ - .long cpuss_interrupts_dw1_4_IRQHandler /* CPUSS DataWire #1, Channel #4 */ - .long cpuss_interrupts_dw1_5_IRQHandler /* CPUSS DataWire #1, Channel #5 */ - .long cpuss_interrupts_dw1_6_IRQHandler /* CPUSS DataWire #1, Channel #6 */ - .long cpuss_interrupts_dw1_7_IRQHandler /* CPUSS DataWire #1, Channel #7 */ - .long cpuss_interrupts_dw1_8_IRQHandler /* CPUSS DataWire #1, Channel #8 */ - .long cpuss_interrupts_dw1_9_IRQHandler /* CPUSS DataWire #1, Channel #9 */ - .long cpuss_interrupts_dw1_10_IRQHandler /* CPUSS DataWire #1, Channel #10 */ - .long cpuss_interrupts_dw1_11_IRQHandler /* CPUSS DataWire #1, Channel #11 */ - .long cpuss_interrupts_dw1_12_IRQHandler /* CPUSS DataWire #1, Channel #12 */ - .long cpuss_interrupts_dw1_13_IRQHandler /* CPUSS DataWire #1, Channel #13 */ - .long cpuss_interrupts_dw1_14_IRQHandler /* CPUSS DataWire #1, Channel #14 */ - .long cpuss_interrupts_dw1_15_IRQHandler /* CPUSS DataWire #1, Channel #15 */ - .long cpuss_interrupts_fault_0_IRQHandler /* CPUSS Fault Structure Interrupt #0 */ - .long cpuss_interrupts_fault_1_IRQHandler /* CPUSS Fault Structure Interrupt #1 */ - .long cpuss_interrupt_crypto_IRQHandler /* CRYPTO Accelerator Interrupt */ - .long cpuss_interrupt_fm_IRQHandler /* FLASH Macro Interrupt */ - .long cpuss_interrupts_cm0_cti_0_IRQHandler /* CM0+ CTI #0 */ - .long cpuss_interrupts_cm0_cti_1_IRQHandler /* CM0+ CTI #1 */ - .long cpuss_interrupts_cm4_cti_0_IRQHandler /* CM4 CTI #0 */ - .long cpuss_interrupts_cm4_cti_1_IRQHandler /* CM4 CTI #1 */ - .long tcpwm_0_interrupts_0_IRQHandler /* TCPWM #0, Counter #0 */ - .long tcpwm_0_interrupts_1_IRQHandler /* TCPWM #0, Counter #1 */ - .long tcpwm_0_interrupts_2_IRQHandler /* TCPWM #0, Counter #2 */ - .long tcpwm_0_interrupts_3_IRQHandler /* TCPWM #0, Counter #3 */ - .long tcpwm_0_interrupts_4_IRQHandler /* TCPWM #0, Counter #4 */ - .long tcpwm_0_interrupts_5_IRQHandler /* TCPWM #0, Counter #5 */ - .long tcpwm_0_interrupts_6_IRQHandler /* TCPWM #0, Counter #6 */ - .long tcpwm_0_interrupts_7_IRQHandler /* TCPWM #0, Counter #7 */ - .long tcpwm_1_interrupts_0_IRQHandler /* TCPWM #1, Counter #0 */ - .long tcpwm_1_interrupts_1_IRQHandler /* TCPWM #1, Counter #1 */ - .long tcpwm_1_interrupts_2_IRQHandler /* TCPWM #1, Counter #2 */ - .long tcpwm_1_interrupts_3_IRQHandler /* TCPWM #1, Counter #3 */ - .long tcpwm_1_interrupts_4_IRQHandler /* TCPWM #1, Counter #4 */ - .long tcpwm_1_interrupts_5_IRQHandler /* TCPWM #1, Counter #5 */ - .long tcpwm_1_interrupts_6_IRQHandler /* TCPWM #1, Counter #6 */ - .long tcpwm_1_interrupts_7_IRQHandler /* TCPWM #1, Counter #7 */ - .long tcpwm_1_interrupts_8_IRQHandler /* TCPWM #1, Counter #8 */ - .long tcpwm_1_interrupts_9_IRQHandler /* TCPWM #1, Counter #9 */ - .long tcpwm_1_interrupts_10_IRQHandler /* TCPWM #1, Counter #10 */ - .long tcpwm_1_interrupts_11_IRQHandler /* TCPWM #1, Counter #11 */ - .long tcpwm_1_interrupts_12_IRQHandler /* TCPWM #1, Counter #12 */ - .long tcpwm_1_interrupts_13_IRQHandler /* TCPWM #1, Counter #13 */ - .long tcpwm_1_interrupts_14_IRQHandler /* TCPWM #1, Counter #14 */ - .long tcpwm_1_interrupts_15_IRQHandler /* TCPWM #1, Counter #15 */ - .long tcpwm_1_interrupts_16_IRQHandler /* TCPWM #1, Counter #16 */ - .long tcpwm_1_interrupts_17_IRQHandler /* TCPWM #1, Counter #17 */ - .long tcpwm_1_interrupts_18_IRQHandler /* TCPWM #1, Counter #18 */ - .long tcpwm_1_interrupts_19_IRQHandler /* TCPWM #1, Counter #19 */ - .long tcpwm_1_interrupts_20_IRQHandler /* TCPWM #1, Counter #20 */ - .long tcpwm_1_interrupts_21_IRQHandler /* TCPWM #1, Counter #21 */ - .long tcpwm_1_interrupts_22_IRQHandler /* TCPWM #1, Counter #22 */ - .long tcpwm_1_interrupts_23_IRQHandler /* TCPWM #1, Counter #23 */ - .long udb_interrupts_0_IRQHandler /* UDB Interrupt #0 */ - .long udb_interrupts_1_IRQHandler /* UDB Interrupt #1 */ - .long udb_interrupts_2_IRQHandler /* UDB Interrupt #2 */ - .long udb_interrupts_3_IRQHandler /* UDB Interrupt #3 */ - .long udb_interrupts_4_IRQHandler /* UDB Interrupt #4 */ - .long udb_interrupts_5_IRQHandler /* UDB Interrupt #5 */ - .long udb_interrupts_6_IRQHandler /* UDB Interrupt #6 */ - .long udb_interrupts_7_IRQHandler /* UDB Interrupt #7 */ - .long udb_interrupts_8_IRQHandler /* UDB Interrupt #8 */ - .long udb_interrupts_9_IRQHandler /* UDB Interrupt #9 */ - .long udb_interrupts_10_IRQHandler /* UDB Interrupt #10 */ - .long udb_interrupts_11_IRQHandler /* UDB Interrupt #11 */ - .long udb_interrupts_12_IRQHandler /* UDB Interrupt #12 */ - .long udb_interrupts_13_IRQHandler /* UDB Interrupt #13 */ - .long udb_interrupts_14_IRQHandler /* UDB Interrupt #14 */ - .long udb_interrupts_15_IRQHandler /* UDB Interrupt #15 */ - .long pass_interrupt_sar_IRQHandler /* SAR ADC interrupt */ - .long audioss_interrupt_i2s_IRQHandler /* I2S Audio interrupt */ - .long audioss_interrupt_pdm_IRQHandler /* PDM/PCM Audio interrupt */ - .long profile_interrupt_IRQHandler /* Energy Profiler interrupt */ - .long smif_interrupt_IRQHandler /* Serial Memory Interface interrupt */ - .long usb_interrupt_hi_IRQHandler /* USB Interrupt */ - .long usb_interrupt_med_IRQHandler /* USB Interrupt */ - .long usb_interrupt_lo_IRQHandler /* USB Interrupt */ - .long pass_interrupt_dacs_IRQHandler /* Consolidated interrrupt for all DACs */ - - - .size __Vectors, . - __Vectors - .equ __VectorsSize, . - __Vectors - - .section .ram_vectors - .align 2 - .globl __ramVectors -__ramVectors: - .space __VectorsSize - .size __ramVectors, . - __ramVectors - - - .text - .thumb - .thumb_func - .align 2 - - /* - * Device startup customization - * - * Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) - * because this function is executed as the first instruction in the ResetHandler. - * The PDL is also not initialized to use the proper register offsets. - * The user of this function is responsible for initializing the PDL and resources before using them. - */ - .weak Cy_OnResetUser - .func Cy_OnResetUser, Cy_OnResetUser - .type Cy_OnResetUser, %function - -Cy_OnResetUser: - bx lr - .size Cy_OnResetUser, . - Cy_OnResetUser - .endfunc - - /* Reset handler */ - .weak Reset_Handler - .type Reset_Handler, %function - -Reset_Handler: - bl Cy_OnResetUser - cpsid i - -/* Firstly it copies data from read only memory to RAM. There are two schemes - * to copy. One can copy more than one sections. Another can only copy - * one section. The former scheme needs more instructions and read-only - * data to implement than the latter. - * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */ - -#ifdef __STARTUP_COPY_MULTIPLE -/* Multiple sections scheme. - * - * Between symbol address __copy_table_start__ and __copy_table_end__, - * there are array of triplets, each of which specify: - * offset 0: LMA of start of a section to copy from - * offset 4: VMA of start of a section to copy to - * offset 8: size of the section to copy. Must be multiply of 4 - * - * All addresses must be aligned to 4 bytes boundary. - */ - ldr r4, =__copy_table_start__ - ldr r5, =__copy_table_end__ - -.L_loop0: - cmp r4, r5 - bge .L_loop0_done - ldr r1, [r4] - ldr r2, [r4, #4] - ldr r3, [r4, #8] - -.L_loop0_0: - subs r3, #4 - ittt ge - ldrge r0, [r1, r3] - strge r0, [r2, r3] - bge .L_loop0_0 - - adds r4, #12 - b .L_loop0 - -.L_loop0_done: -#else -/* Single section scheme. - * - * The ranges of copy from/to are specified by following symbols - * __etext: LMA of start of the section to copy from. Usually end of text - * __data_start__: VMA of start of the section to copy to - * __data_end__: VMA of end of the section to copy to - * - * All addresses must be aligned to 4 bytes boundary. - */ - ldr r1, =__etext - ldr r2, =__data_start__ - ldr r3, =__data_end__ - -.L_loop1: - cmp r2, r3 - ittt lt - ldrlt r0, [r1], #4 - strlt r0, [r2], #4 - blt .L_loop1 -#endif /*__STARTUP_COPY_MULTIPLE */ - -/* This part of work usually is done in C library startup code. Otherwise, - * define this macro to enable it in this startup. - * - * There are two schemes too. One can clear multiple BSS sections. Another - * can only clear one section. The former is more size expensive than the - * latter. - * - * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former. - * Otherwise define macro __STARTUP_CLEAR_BSS to choose the later. - */ -#ifdef __STARTUP_CLEAR_BSS_MULTIPLE -/* Multiple sections scheme. - * - * Between symbol address __copy_table_start__ and __copy_table_end__, - * there are array of tuples specifying: - * offset 0: Start of a BSS section - * offset 4: Size of this BSS section. Must be multiply of 4 - */ - ldr r3, =__zero_table_start__ - ldr r4, =__zero_table_end__ - -.L_loop2: - cmp r3, r4 - bge .L_loop2_done - ldr r1, [r3] - ldr r2, [r3, #4] - movs r0, 0 - -.L_loop2_0: - subs r2, #4 - itt ge - strge r0, [r1, r2] - bge .L_loop2_0 - - adds r3, #8 - b .L_loop2 -.L_loop2_done: -#elif defined (__STARTUP_CLEAR_BSS) -/* Single BSS section scheme. - * - * The BSS section is specified by following symbols - * __bss_start__: start of the BSS section. - * __bss_end__: end of the BSS section. - * - * Both addresses must be aligned to 4 bytes boundary. - */ - ldr r1, =__bss_start__ - ldr r2, =__bss_end__ - - movs r0, 0 -.L_loop3: - cmp r1, r2 - itt lt - strlt r0, [r1], #4 - blt .L_loop3 -#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */ - - /* Update Vector Table Offset Register. */ - ldr r0, =__ramVectors - ldr r1, =CY_CPU_VTOR_ADDR - str r0, [r1] - dsb 0xF - - /* Enable the FPU if used */ - bl Cy_SystemInitFpuEnable - - bl _start - - /* Should never get here */ - b . - - .pool - .size Reset_Handler, . - Reset_Handler - - .align 1 - .thumb_func - .weak Default_Handler - .type Default_Handler, %function - -Default_Handler: - b . - .size Default_Handler, . - Default_Handler - - - .weak Cy_SysLib_FaultHandler - .type Cy_SysLib_FaultHandler, %function - -Cy_SysLib_FaultHandler: - b . - .size Cy_SysLib_FaultHandler, . - Cy_SysLib_FaultHandler - .type Fault_Handler, %function - -Fault_Handler: - /* Storing LR content for Creator call stack trace */ - push {LR} - movs r0, #4 - mov r1, LR - tst r0, r1 - beq .L_MSP - mrs r0, PSP - b .L_API_call -.L_MSP: - mrs r0, MSP -.L_API_call: - /* Compensation of stack pointer address due to pushing 4 bytes of LR */ - adds r0, r0, #4 - bl Cy_SysLib_FaultHandler - b . - .size Fault_Handler, . - Fault_Handler - -.macro def_fault_Handler fault_handler_name - .weak \fault_handler_name - .set \fault_handler_name, Fault_Handler - .endm - -/* Macro to define default handlers. Default handler - * will be weak symbol and just dead loops. They can be - * overwritten by other handlers */ - .macro def_irq_handler handler_name - .weak \handler_name - .set \handler_name, Default_Handler - .endm - - def_irq_handler NMI_Handler - - def_fault_Handler HardFault_Handler - def_fault_Handler MemManage_Handler - def_fault_Handler BusFault_Handler - def_fault_Handler UsageFault_Handler - - def_irq_handler SVC_Handler - def_irq_handler DebugMon_Handler - def_irq_handler PendSV_Handler - def_irq_handler SysTick_Handler - - def_irq_handler ioss_interrupts_gpio_0_IRQHandler /* GPIO Port Interrupt #0 */ - def_irq_handler ioss_interrupts_gpio_1_IRQHandler /* GPIO Port Interrupt #1 */ - def_irq_handler ioss_interrupts_gpio_2_IRQHandler /* GPIO Port Interrupt #2 */ - def_irq_handler ioss_interrupts_gpio_3_IRQHandler /* GPIO Port Interrupt #3 */ - def_irq_handler ioss_interrupts_gpio_4_IRQHandler /* GPIO Port Interrupt #4 */ - def_irq_handler ioss_interrupts_gpio_5_IRQHandler /* GPIO Port Interrupt #5 */ - def_irq_handler ioss_interrupts_gpio_6_IRQHandler /* GPIO Port Interrupt #6 */ - def_irq_handler ioss_interrupts_gpio_7_IRQHandler /* GPIO Port Interrupt #7 */ - def_irq_handler ioss_interrupts_gpio_8_IRQHandler /* GPIO Port Interrupt #8 */ - def_irq_handler ioss_interrupts_gpio_9_IRQHandler /* GPIO Port Interrupt #9 */ - def_irq_handler ioss_interrupts_gpio_10_IRQHandler /* GPIO Port Interrupt #10 */ - def_irq_handler ioss_interrupts_gpio_11_IRQHandler /* GPIO Port Interrupt #11 */ - def_irq_handler ioss_interrupts_gpio_12_IRQHandler /* GPIO Port Interrupt #12 */ - def_irq_handler ioss_interrupts_gpio_13_IRQHandler /* GPIO Port Interrupt #13 */ - def_irq_handler ioss_interrupts_gpio_14_IRQHandler /* GPIO Port Interrupt #14 */ - def_irq_handler ioss_interrupt_gpio_IRQHandler /* GPIO All Ports */ - def_irq_handler ioss_interrupt_vdd_IRQHandler /* GPIO Supply Detect Interrupt */ - def_irq_handler lpcomp_interrupt_IRQHandler /* Low Power Comparator Interrupt */ - def_irq_handler scb_8_interrupt_IRQHandler /* Serial Communication Block #8 (DeepSleep capable) */ - def_irq_handler srss_interrupt_mcwdt_0_IRQHandler /* Multi Counter Watchdog Timer interrupt */ - def_irq_handler srss_interrupt_mcwdt_1_IRQHandler /* Multi Counter Watchdog Timer interrupt */ - def_irq_handler srss_interrupt_backup_IRQHandler /* Backup domain interrupt */ - def_irq_handler srss_interrupt_IRQHandler /* Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ - def_irq_handler pass_interrupt_ctbs_IRQHandler /* CTBm Interrupt (all CTBms) */ - def_irq_handler bless_interrupt_IRQHandler /* Bluetooth Radio interrupt */ - def_irq_handler cpuss_interrupts_ipc_0_IRQHandler /* CPUSS Inter Process Communication Interrupt #0 */ - def_irq_handler cpuss_interrupts_ipc_1_IRQHandler /* CPUSS Inter Process Communication Interrupt #1 */ - def_irq_handler cpuss_interrupts_ipc_2_IRQHandler /* CPUSS Inter Process Communication Interrupt #2 */ - def_irq_handler cpuss_interrupts_ipc_3_IRQHandler /* CPUSS Inter Process Communication Interrupt #3 */ - def_irq_handler cpuss_interrupts_ipc_4_IRQHandler /* CPUSS Inter Process Communication Interrupt #4 */ - def_irq_handler cpuss_interrupts_ipc_5_IRQHandler /* CPUSS Inter Process Communication Interrupt #5 */ - def_irq_handler cpuss_interrupts_ipc_6_IRQHandler /* CPUSS Inter Process Communication Interrupt #6 */ - def_irq_handler cpuss_interrupts_ipc_7_IRQHandler /* CPUSS Inter Process Communication Interrupt #7 */ - def_irq_handler cpuss_interrupts_ipc_8_IRQHandler /* CPUSS Inter Process Communication Interrupt #8 */ - def_irq_handler cpuss_interrupts_ipc_9_IRQHandler /* CPUSS Inter Process Communication Interrupt #9 */ - def_irq_handler cpuss_interrupts_ipc_10_IRQHandler /* CPUSS Inter Process Communication Interrupt #10 */ - def_irq_handler cpuss_interrupts_ipc_11_IRQHandler /* CPUSS Inter Process Communication Interrupt #11 */ - def_irq_handler cpuss_interrupts_ipc_12_IRQHandler /* CPUSS Inter Process Communication Interrupt #12 */ - def_irq_handler cpuss_interrupts_ipc_13_IRQHandler /* CPUSS Inter Process Communication Interrupt #13 */ - def_irq_handler cpuss_interrupts_ipc_14_IRQHandler /* CPUSS Inter Process Communication Interrupt #14 */ - def_irq_handler cpuss_interrupts_ipc_15_IRQHandler /* CPUSS Inter Process Communication Interrupt #15 */ - def_irq_handler scb_0_interrupt_IRQHandler /* Serial Communication Block #0 */ - def_irq_handler scb_1_interrupt_IRQHandler /* Serial Communication Block #1 */ - def_irq_handler scb_2_interrupt_IRQHandler /* Serial Communication Block #2 */ - def_irq_handler scb_3_interrupt_IRQHandler /* Serial Communication Block #3 */ - def_irq_handler scb_4_interrupt_IRQHandler /* Serial Communication Block #4 */ - def_irq_handler scb_5_interrupt_IRQHandler /* Serial Communication Block #5 */ - def_irq_handler scb_6_interrupt_IRQHandler /* Serial Communication Block #6 */ - def_irq_handler scb_7_interrupt_IRQHandler /* Serial Communication Block #7 */ - def_irq_handler csd_interrupt_IRQHandler /* CSD (Capsense) interrupt */ - def_irq_handler cpuss_interrupts_dw0_0_IRQHandler /* CPUSS DataWire #0, Channel #0 */ - def_irq_handler cpuss_interrupts_dw0_1_IRQHandler /* CPUSS DataWire #0, Channel #1 */ - def_irq_handler cpuss_interrupts_dw0_2_IRQHandler /* CPUSS DataWire #0, Channel #2 */ - def_irq_handler cpuss_interrupts_dw0_3_IRQHandler /* CPUSS DataWire #0, Channel #3 */ - def_irq_handler cpuss_interrupts_dw0_4_IRQHandler /* CPUSS DataWire #0, Channel #4 */ - def_irq_handler cpuss_interrupts_dw0_5_IRQHandler /* CPUSS DataWire #0, Channel #5 */ - def_irq_handler cpuss_interrupts_dw0_6_IRQHandler /* CPUSS DataWire #0, Channel #6 */ - def_irq_handler cpuss_interrupts_dw0_7_IRQHandler /* CPUSS DataWire #0, Channel #7 */ - def_irq_handler cpuss_interrupts_dw0_8_IRQHandler /* CPUSS DataWire #0, Channel #8 */ - def_irq_handler cpuss_interrupts_dw0_9_IRQHandler /* CPUSS DataWire #0, Channel #9 */ - def_irq_handler cpuss_interrupts_dw0_10_IRQHandler /* CPUSS DataWire #0, Channel #10 */ - def_irq_handler cpuss_interrupts_dw0_11_IRQHandler /* CPUSS DataWire #0, Channel #11 */ - def_irq_handler cpuss_interrupts_dw0_12_IRQHandler /* CPUSS DataWire #0, Channel #12 */ - def_irq_handler cpuss_interrupts_dw0_13_IRQHandler /* CPUSS DataWire #0, Channel #13 */ - def_irq_handler cpuss_interrupts_dw0_14_IRQHandler /* CPUSS DataWire #0, Channel #14 */ - def_irq_handler cpuss_interrupts_dw0_15_IRQHandler /* CPUSS DataWire #0, Channel #15 */ - def_irq_handler cpuss_interrupts_dw1_0_IRQHandler /* CPUSS DataWire #1, Channel #0 */ - def_irq_handler cpuss_interrupts_dw1_1_IRQHandler /* CPUSS DataWire #1, Channel #1 */ - def_irq_handler cpuss_interrupts_dw1_2_IRQHandler /* CPUSS DataWire #1, Channel #2 */ - def_irq_handler cpuss_interrupts_dw1_3_IRQHandler /* CPUSS DataWire #1, Channel #3 */ - def_irq_handler cpuss_interrupts_dw1_4_IRQHandler /* CPUSS DataWire #1, Channel #4 */ - def_irq_handler cpuss_interrupts_dw1_5_IRQHandler /* CPUSS DataWire #1, Channel #5 */ - def_irq_handler cpuss_interrupts_dw1_6_IRQHandler /* CPUSS DataWire #1, Channel #6 */ - def_irq_handler cpuss_interrupts_dw1_7_IRQHandler /* CPUSS DataWire #1, Channel #7 */ - def_irq_handler cpuss_interrupts_dw1_8_IRQHandler /* CPUSS DataWire #1, Channel #8 */ - def_irq_handler cpuss_interrupts_dw1_9_IRQHandler /* CPUSS DataWire #1, Channel #9 */ - def_irq_handler cpuss_interrupts_dw1_10_IRQHandler /* CPUSS DataWire #1, Channel #10 */ - def_irq_handler cpuss_interrupts_dw1_11_IRQHandler /* CPUSS DataWire #1, Channel #11 */ - def_irq_handler cpuss_interrupts_dw1_12_IRQHandler /* CPUSS DataWire #1, Channel #12 */ - def_irq_handler cpuss_interrupts_dw1_13_IRQHandler /* CPUSS DataWire #1, Channel #13 */ - def_irq_handler cpuss_interrupts_dw1_14_IRQHandler /* CPUSS DataWire #1, Channel #14 */ - def_irq_handler cpuss_interrupts_dw1_15_IRQHandler /* CPUSS DataWire #1, Channel #15 */ - def_irq_handler cpuss_interrupts_fault_0_IRQHandler /* CPUSS Fault Structure Interrupt #0 */ - def_irq_handler cpuss_interrupts_fault_1_IRQHandler /* CPUSS Fault Structure Interrupt #1 */ - def_irq_handler cpuss_interrupt_crypto_IRQHandler /* CRYPTO Accelerator Interrupt */ - def_irq_handler cpuss_interrupt_fm_IRQHandler /* FLASH Macro Interrupt */ - def_irq_handler cpuss_interrupts_cm0_cti_0_IRQHandler /* CM0+ CTI #0 */ - def_irq_handler cpuss_interrupts_cm0_cti_1_IRQHandler /* CM0+ CTI #1 */ - def_irq_handler cpuss_interrupts_cm4_cti_0_IRQHandler /* CM4 CTI #0 */ - def_irq_handler cpuss_interrupts_cm4_cti_1_IRQHandler /* CM4 CTI #1 */ - def_irq_handler tcpwm_0_interrupts_0_IRQHandler /* TCPWM #0, Counter #0 */ - def_irq_handler tcpwm_0_interrupts_1_IRQHandler /* TCPWM #0, Counter #1 */ - def_irq_handler tcpwm_0_interrupts_2_IRQHandler /* TCPWM #0, Counter #2 */ - def_irq_handler tcpwm_0_interrupts_3_IRQHandler /* TCPWM #0, Counter #3 */ - def_irq_handler tcpwm_0_interrupts_4_IRQHandler /* TCPWM #0, Counter #4 */ - def_irq_handler tcpwm_0_interrupts_5_IRQHandler /* TCPWM #0, Counter #5 */ - def_irq_handler tcpwm_0_interrupts_6_IRQHandler /* TCPWM #0, Counter #6 */ - def_irq_handler tcpwm_0_interrupts_7_IRQHandler /* TCPWM #0, Counter #7 */ - def_irq_handler tcpwm_1_interrupts_0_IRQHandler /* TCPWM #1, Counter #0 */ - def_irq_handler tcpwm_1_interrupts_1_IRQHandler /* TCPWM #1, Counter #1 */ - def_irq_handler tcpwm_1_interrupts_2_IRQHandler /* TCPWM #1, Counter #2 */ - def_irq_handler tcpwm_1_interrupts_3_IRQHandler /* TCPWM #1, Counter #3 */ - def_irq_handler tcpwm_1_interrupts_4_IRQHandler /* TCPWM #1, Counter #4 */ - def_irq_handler tcpwm_1_interrupts_5_IRQHandler /* TCPWM #1, Counter #5 */ - def_irq_handler tcpwm_1_interrupts_6_IRQHandler /* TCPWM #1, Counter #6 */ - def_irq_handler tcpwm_1_interrupts_7_IRQHandler /* TCPWM #1, Counter #7 */ - def_irq_handler tcpwm_1_interrupts_8_IRQHandler /* TCPWM #1, Counter #8 */ - def_irq_handler tcpwm_1_interrupts_9_IRQHandler /* TCPWM #1, Counter #9 */ - def_irq_handler tcpwm_1_interrupts_10_IRQHandler /* TCPWM #1, Counter #10 */ - def_irq_handler tcpwm_1_interrupts_11_IRQHandler /* TCPWM #1, Counter #11 */ - def_irq_handler tcpwm_1_interrupts_12_IRQHandler /* TCPWM #1, Counter #12 */ - def_irq_handler tcpwm_1_interrupts_13_IRQHandler /* TCPWM #1, Counter #13 */ - def_irq_handler tcpwm_1_interrupts_14_IRQHandler /* TCPWM #1, Counter #14 */ - def_irq_handler tcpwm_1_interrupts_15_IRQHandler /* TCPWM #1, Counter #15 */ - def_irq_handler tcpwm_1_interrupts_16_IRQHandler /* TCPWM #1, Counter #16 */ - def_irq_handler tcpwm_1_interrupts_17_IRQHandler /* TCPWM #1, Counter #17 */ - def_irq_handler tcpwm_1_interrupts_18_IRQHandler /* TCPWM #1, Counter #18 */ - def_irq_handler tcpwm_1_interrupts_19_IRQHandler /* TCPWM #1, Counter #19 */ - def_irq_handler tcpwm_1_interrupts_20_IRQHandler /* TCPWM #1, Counter #20 */ - def_irq_handler tcpwm_1_interrupts_21_IRQHandler /* TCPWM #1, Counter #21 */ - def_irq_handler tcpwm_1_interrupts_22_IRQHandler /* TCPWM #1, Counter #22 */ - def_irq_handler tcpwm_1_interrupts_23_IRQHandler /* TCPWM #1, Counter #23 */ - def_irq_handler udb_interrupts_0_IRQHandler /* UDB Interrupt #0 */ - def_irq_handler udb_interrupts_1_IRQHandler /* UDB Interrupt #1 */ - def_irq_handler udb_interrupts_2_IRQHandler /* UDB Interrupt #2 */ - def_irq_handler udb_interrupts_3_IRQHandler /* UDB Interrupt #3 */ - def_irq_handler udb_interrupts_4_IRQHandler /* UDB Interrupt #4 */ - def_irq_handler udb_interrupts_5_IRQHandler /* UDB Interrupt #5 */ - def_irq_handler udb_interrupts_6_IRQHandler /* UDB Interrupt #6 */ - def_irq_handler udb_interrupts_7_IRQHandler /* UDB Interrupt #7 */ - def_irq_handler udb_interrupts_8_IRQHandler /* UDB Interrupt #8 */ - def_irq_handler udb_interrupts_9_IRQHandler /* UDB Interrupt #9 */ - def_irq_handler udb_interrupts_10_IRQHandler /* UDB Interrupt #10 */ - def_irq_handler udb_interrupts_11_IRQHandler /* UDB Interrupt #11 */ - def_irq_handler udb_interrupts_12_IRQHandler /* UDB Interrupt #12 */ - def_irq_handler udb_interrupts_13_IRQHandler /* UDB Interrupt #13 */ - def_irq_handler udb_interrupts_14_IRQHandler /* UDB Interrupt #14 */ - def_irq_handler udb_interrupts_15_IRQHandler /* UDB Interrupt #15 */ - def_irq_handler pass_interrupt_sar_IRQHandler /* SAR ADC interrupt */ - def_irq_handler audioss_interrupt_i2s_IRQHandler /* I2S Audio interrupt */ - def_irq_handler audioss_interrupt_pdm_IRQHandler /* PDM/PCM Audio interrupt */ - def_irq_handler profile_interrupt_IRQHandler /* Energy Profiler interrupt */ - def_irq_handler smif_interrupt_IRQHandler /* Serial Memory Interface interrupt */ - def_irq_handler usb_interrupt_hi_IRQHandler /* USB Interrupt */ - def_irq_handler usb_interrupt_med_IRQHandler /* USB Interrupt */ - def_irq_handler usb_interrupt_lo_IRQHandler /* USB Interrupt */ - def_irq_handler pass_interrupt_dacs_IRQHandler /* Consolidated interrrupt for all DACs */ - - .end - - -/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_01_cm4.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_01_cm4.S deleted file mode 100644 index f4ca47b457..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_01_cm4.S +++ /dev/null @@ -1,1137 +0,0 @@ -;/**************************************************************************//** -; * @file startup_psoc6_01_cm4.S -; * @brief CMSIS Core Device Startup File for -; * ARMCM4 Device Series -; * @version V5.00 -; * @date 08. March 2016 -; ******************************************************************************/ -;/* -; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. -; * -; * SPDX-License-Identifier: Apache-2.0 -; * -; * Licensed under the Apache License, Version 2.0 (the License); you may -; * not use this file except in compliance with the License. -; * You may obtain a copy of the License at -; * -; * www.apache.org/licenses/LICENSE-2.0 -; * -; * Unless required by applicable law or agreed to in writing, software -; * distributed under the License is distributed on an AS IS BASIS, WITHOUT -; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -; * See the License for the specific language governing permissions and -; * limitations under the License. -; */ - -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - SECTION .intvec_ram:DATA:NOROOT(2) - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - EXTERN Cy_SystemInitFpuEnable - EXTERN __iar_data_init3 - PUBLIC __vector_table - PUBLIC __vector_table_0x1c - PUBLIC __Vectors - PUBLIC __Vectors_End - PUBLIC __Vectors_Size - PUBLIC __ramVectors - - DATA - -__vector_table - DCD sfe(CSTACK) - DCD Reset_Handler - - DCD 0x0000000D ; NMI_Handler is defined in ROM code - DCD HardFault_Handler - DCD MemManage_Handler - DCD BusFault_Handler - DCD UsageFault_Handler -__vector_table_0x1c - DCD 0 - DCD 0 - DCD 0 - DCD 0 - DCD SVC_Handler - DCD DebugMon_Handler - DCD 0 - DCD PendSV_Handler - DCD SysTick_Handler - - ; External interrupts Description - DCD ioss_interrupts_gpio_0_IRQHandler ; GPIO Port Interrupt #0 - DCD ioss_interrupts_gpio_1_IRQHandler ; GPIO Port Interrupt #1 - DCD ioss_interrupts_gpio_2_IRQHandler ; GPIO Port Interrupt #2 - DCD ioss_interrupts_gpio_3_IRQHandler ; GPIO Port Interrupt #3 - DCD ioss_interrupts_gpio_4_IRQHandler ; GPIO Port Interrupt #4 - DCD ioss_interrupts_gpio_5_IRQHandler ; GPIO Port Interrupt #5 - DCD ioss_interrupts_gpio_6_IRQHandler ; GPIO Port Interrupt #6 - DCD ioss_interrupts_gpio_7_IRQHandler ; GPIO Port Interrupt #7 - DCD ioss_interrupts_gpio_8_IRQHandler ; GPIO Port Interrupt #8 - DCD ioss_interrupts_gpio_9_IRQHandler ; GPIO Port Interrupt #9 - DCD ioss_interrupts_gpio_10_IRQHandler ; GPIO Port Interrupt #10 - DCD ioss_interrupts_gpio_11_IRQHandler ; GPIO Port Interrupt #11 - DCD ioss_interrupts_gpio_12_IRQHandler ; GPIO Port Interrupt #12 - DCD ioss_interrupts_gpio_13_IRQHandler ; GPIO Port Interrupt #13 - DCD ioss_interrupts_gpio_14_IRQHandler ; GPIO Port Interrupt #14 - DCD ioss_interrupt_gpio_IRQHandler ; GPIO All Ports - DCD ioss_interrupt_vdd_IRQHandler ; GPIO Supply Detect Interrupt - DCD lpcomp_interrupt_IRQHandler ; Low Power Comparator Interrupt - DCD scb_8_interrupt_IRQHandler ; Serial Communication Block #8 (DeepSleep capable) - DCD srss_interrupt_mcwdt_0_IRQHandler ; Multi Counter Watchdog Timer interrupt - DCD srss_interrupt_mcwdt_1_IRQHandler ; Multi Counter Watchdog Timer interrupt - DCD srss_interrupt_backup_IRQHandler ; Backup domain interrupt - DCD srss_interrupt_IRQHandler ; Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) - DCD pass_interrupt_ctbs_IRQHandler ; CTBm Interrupt (all CTBms) - DCD bless_interrupt_IRQHandler ; Bluetooth Radio interrupt - DCD cpuss_interrupts_ipc_0_IRQHandler ; CPUSS Inter Process Communication Interrupt #0 - DCD cpuss_interrupts_ipc_1_IRQHandler ; CPUSS Inter Process Communication Interrupt #1 - DCD cpuss_interrupts_ipc_2_IRQHandler ; CPUSS Inter Process Communication Interrupt #2 - DCD cpuss_interrupts_ipc_3_IRQHandler ; CPUSS Inter Process Communication Interrupt #3 - DCD cpuss_interrupts_ipc_4_IRQHandler ; CPUSS Inter Process Communication Interrupt #4 - DCD cpuss_interrupts_ipc_5_IRQHandler ; CPUSS Inter Process Communication Interrupt #5 - DCD cpuss_interrupts_ipc_6_IRQHandler ; CPUSS Inter Process Communication Interrupt #6 - DCD cpuss_interrupts_ipc_7_IRQHandler ; CPUSS Inter Process Communication Interrupt #7 - DCD cpuss_interrupts_ipc_8_IRQHandler ; CPUSS Inter Process Communication Interrupt #8 - DCD cpuss_interrupts_ipc_9_IRQHandler ; CPUSS Inter Process Communication Interrupt #9 - DCD cpuss_interrupts_ipc_10_IRQHandler ; CPUSS Inter Process Communication Interrupt #10 - DCD cpuss_interrupts_ipc_11_IRQHandler ; CPUSS Inter Process Communication Interrupt #11 - DCD cpuss_interrupts_ipc_12_IRQHandler ; CPUSS Inter Process Communication Interrupt #12 - DCD cpuss_interrupts_ipc_13_IRQHandler ; CPUSS Inter Process Communication Interrupt #13 - DCD cpuss_interrupts_ipc_14_IRQHandler ; CPUSS Inter Process Communication Interrupt #14 - DCD cpuss_interrupts_ipc_15_IRQHandler ; CPUSS Inter Process Communication Interrupt #15 - DCD scb_0_interrupt_IRQHandler ; Serial Communication Block #0 - DCD scb_1_interrupt_IRQHandler ; Serial Communication Block #1 - DCD scb_2_interrupt_IRQHandler ; Serial Communication Block #2 - DCD scb_3_interrupt_IRQHandler ; Serial Communication Block #3 - DCD scb_4_interrupt_IRQHandler ; Serial Communication Block #4 - DCD scb_5_interrupt_IRQHandler ; Serial Communication Block #5 - DCD scb_6_interrupt_IRQHandler ; Serial Communication Block #6 - DCD scb_7_interrupt_IRQHandler ; Serial Communication Block #7 - DCD csd_interrupt_IRQHandler ; CSD (Capsense) interrupt - DCD cpuss_interrupts_dw0_0_IRQHandler ; CPUSS DataWire #0, Channel #0 - DCD cpuss_interrupts_dw0_1_IRQHandler ; CPUSS DataWire #0, Channel #1 - DCD cpuss_interrupts_dw0_2_IRQHandler ; CPUSS DataWire #0, Channel #2 - DCD cpuss_interrupts_dw0_3_IRQHandler ; CPUSS DataWire #0, Channel #3 - DCD cpuss_interrupts_dw0_4_IRQHandler ; CPUSS DataWire #0, Channel #4 - DCD cpuss_interrupts_dw0_5_IRQHandler ; CPUSS DataWire #0, Channel #5 - DCD cpuss_interrupts_dw0_6_IRQHandler ; CPUSS DataWire #0, Channel #6 - DCD cpuss_interrupts_dw0_7_IRQHandler ; CPUSS DataWire #0, Channel #7 - DCD cpuss_interrupts_dw0_8_IRQHandler ; CPUSS DataWire #0, Channel #8 - DCD cpuss_interrupts_dw0_9_IRQHandler ; CPUSS DataWire #0, Channel #9 - DCD cpuss_interrupts_dw0_10_IRQHandler ; CPUSS DataWire #0, Channel #10 - DCD cpuss_interrupts_dw0_11_IRQHandler ; CPUSS DataWire #0, Channel #11 - DCD cpuss_interrupts_dw0_12_IRQHandler ; CPUSS DataWire #0, Channel #12 - DCD cpuss_interrupts_dw0_13_IRQHandler ; CPUSS DataWire #0, Channel #13 - DCD cpuss_interrupts_dw0_14_IRQHandler ; CPUSS DataWire #0, Channel #14 - DCD cpuss_interrupts_dw0_15_IRQHandler ; CPUSS DataWire #0, Channel #15 - DCD cpuss_interrupts_dw1_0_IRQHandler ; CPUSS DataWire #1, Channel #0 - DCD cpuss_interrupts_dw1_1_IRQHandler ; CPUSS DataWire #1, Channel #1 - DCD cpuss_interrupts_dw1_2_IRQHandler ; CPUSS DataWire #1, Channel #2 - DCD cpuss_interrupts_dw1_3_IRQHandler ; CPUSS DataWire #1, Channel #3 - DCD cpuss_interrupts_dw1_4_IRQHandler ; CPUSS DataWire #1, Channel #4 - DCD cpuss_interrupts_dw1_5_IRQHandler ; CPUSS DataWire #1, Channel #5 - DCD cpuss_interrupts_dw1_6_IRQHandler ; CPUSS DataWire #1, Channel #6 - DCD cpuss_interrupts_dw1_7_IRQHandler ; CPUSS DataWire #1, Channel #7 - DCD cpuss_interrupts_dw1_8_IRQHandler ; CPUSS DataWire #1, Channel #8 - DCD cpuss_interrupts_dw1_9_IRQHandler ; CPUSS DataWire #1, Channel #9 - DCD cpuss_interrupts_dw1_10_IRQHandler ; CPUSS DataWire #1, Channel #10 - DCD cpuss_interrupts_dw1_11_IRQHandler ; CPUSS DataWire #1, Channel #11 - DCD cpuss_interrupts_dw1_12_IRQHandler ; CPUSS DataWire #1, Channel #12 - DCD cpuss_interrupts_dw1_13_IRQHandler ; CPUSS DataWire #1, Channel #13 - DCD cpuss_interrupts_dw1_14_IRQHandler ; CPUSS DataWire #1, Channel #14 - DCD cpuss_interrupts_dw1_15_IRQHandler ; CPUSS DataWire #1, Channel #15 - DCD cpuss_interrupts_fault_0_IRQHandler ; CPUSS Fault Structure Interrupt #0 - DCD cpuss_interrupts_fault_1_IRQHandler ; CPUSS Fault Structure Interrupt #1 - DCD cpuss_interrupt_crypto_IRQHandler ; CRYPTO Accelerator Interrupt - DCD cpuss_interrupt_fm_IRQHandler ; FLASH Macro Interrupt - DCD cpuss_interrupts_cm0_cti_0_IRQHandler ; CM0+ CTI #0 - DCD cpuss_interrupts_cm0_cti_1_IRQHandler ; CM0+ CTI #1 - DCD cpuss_interrupts_cm4_cti_0_IRQHandler ; CM4 CTI #0 - DCD cpuss_interrupts_cm4_cti_1_IRQHandler ; CM4 CTI #1 - DCD tcpwm_0_interrupts_0_IRQHandler ; TCPWM #0, Counter #0 - DCD tcpwm_0_interrupts_1_IRQHandler ; TCPWM #0, Counter #1 - DCD tcpwm_0_interrupts_2_IRQHandler ; TCPWM #0, Counter #2 - DCD tcpwm_0_interrupts_3_IRQHandler ; TCPWM #0, Counter #3 - DCD tcpwm_0_interrupts_4_IRQHandler ; TCPWM #0, Counter #4 - DCD tcpwm_0_interrupts_5_IRQHandler ; TCPWM #0, Counter #5 - DCD tcpwm_0_interrupts_6_IRQHandler ; TCPWM #0, Counter #6 - DCD tcpwm_0_interrupts_7_IRQHandler ; TCPWM #0, Counter #7 - DCD tcpwm_1_interrupts_0_IRQHandler ; TCPWM #1, Counter #0 - DCD tcpwm_1_interrupts_1_IRQHandler ; TCPWM #1, Counter #1 - DCD tcpwm_1_interrupts_2_IRQHandler ; TCPWM #1, Counter #2 - DCD tcpwm_1_interrupts_3_IRQHandler ; TCPWM #1, Counter #3 - DCD tcpwm_1_interrupts_4_IRQHandler ; TCPWM #1, Counter #4 - DCD tcpwm_1_interrupts_5_IRQHandler ; TCPWM #1, Counter #5 - DCD tcpwm_1_interrupts_6_IRQHandler ; TCPWM #1, Counter #6 - DCD tcpwm_1_interrupts_7_IRQHandler ; TCPWM #1, Counter #7 - DCD tcpwm_1_interrupts_8_IRQHandler ; TCPWM #1, Counter #8 - DCD tcpwm_1_interrupts_9_IRQHandler ; TCPWM #1, Counter #9 - DCD tcpwm_1_interrupts_10_IRQHandler ; TCPWM #1, Counter #10 - DCD tcpwm_1_interrupts_11_IRQHandler ; TCPWM #1, Counter #11 - DCD tcpwm_1_interrupts_12_IRQHandler ; TCPWM #1, Counter #12 - DCD tcpwm_1_interrupts_13_IRQHandler ; TCPWM #1, Counter #13 - DCD tcpwm_1_interrupts_14_IRQHandler ; TCPWM #1, Counter #14 - DCD tcpwm_1_interrupts_15_IRQHandler ; TCPWM #1, Counter #15 - DCD tcpwm_1_interrupts_16_IRQHandler ; TCPWM #1, Counter #16 - DCD tcpwm_1_interrupts_17_IRQHandler ; TCPWM #1, Counter #17 - DCD tcpwm_1_interrupts_18_IRQHandler ; TCPWM #1, Counter #18 - DCD tcpwm_1_interrupts_19_IRQHandler ; TCPWM #1, Counter #19 - DCD tcpwm_1_interrupts_20_IRQHandler ; TCPWM #1, Counter #20 - DCD tcpwm_1_interrupts_21_IRQHandler ; TCPWM #1, Counter #21 - DCD tcpwm_1_interrupts_22_IRQHandler ; TCPWM #1, Counter #22 - DCD tcpwm_1_interrupts_23_IRQHandler ; TCPWM #1, Counter #23 - DCD udb_interrupts_0_IRQHandler ; UDB Interrupt #0 - DCD udb_interrupts_1_IRQHandler ; UDB Interrupt #1 - DCD udb_interrupts_2_IRQHandler ; UDB Interrupt #2 - DCD udb_interrupts_3_IRQHandler ; UDB Interrupt #3 - DCD udb_interrupts_4_IRQHandler ; UDB Interrupt #4 - DCD udb_interrupts_5_IRQHandler ; UDB Interrupt #5 - DCD udb_interrupts_6_IRQHandler ; UDB Interrupt #6 - DCD udb_interrupts_7_IRQHandler ; UDB Interrupt #7 - DCD udb_interrupts_8_IRQHandler ; UDB Interrupt #8 - DCD udb_interrupts_9_IRQHandler ; UDB Interrupt #9 - DCD udb_interrupts_10_IRQHandler ; UDB Interrupt #10 - DCD udb_interrupts_11_IRQHandler ; UDB Interrupt #11 - DCD udb_interrupts_12_IRQHandler ; UDB Interrupt #12 - DCD udb_interrupts_13_IRQHandler ; UDB Interrupt #13 - DCD udb_interrupts_14_IRQHandler ; UDB Interrupt #14 - DCD udb_interrupts_15_IRQHandler ; UDB Interrupt #15 - DCD pass_interrupt_sar_IRQHandler ; SAR ADC interrupt - DCD audioss_interrupt_i2s_IRQHandler ; I2S Audio interrupt - DCD audioss_interrupt_pdm_IRQHandler ; PDM/PCM Audio interrupt - DCD profile_interrupt_IRQHandler ; Energy Profiler interrupt - DCD smif_interrupt_IRQHandler ; Serial Memory Interface interrupt - DCD usb_interrupt_hi_IRQHandler ; USB Interrupt - DCD usb_interrupt_med_IRQHandler ; USB Interrupt - DCD usb_interrupt_lo_IRQHandler ; USB Interrupt - DCD pass_interrupt_dacs_IRQHandler ; Consolidated interrrupt for all DACs - -__Vectors_End - -__Vectors EQU __vector_table -__Vectors_Size EQU __Vectors_End - __Vectors - - SECTION .intvec_ram:DATA:REORDER:NOROOT(2) -__ramVectors - DS32 __Vectors_Size - - - THUMB - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default handlers -;; - PUBWEAK Default_Handler - SECTION .text:CODE:REORDER:NOROOT(2) -Default_Handler - B Default_Handler - - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Weak function for startup customization -;; -;; Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) -;; because this function is executed as the first instruction in the ResetHandler. -;; The PDL is also not initialized to use the proper register offsets. -;; The user of this function is responsible for initializing the PDL and resources before using them. -;; - PUBWEAK Cy_OnResetUser - SECTION .text:CODE:REORDER:NOROOT(2) -Cy_OnResetUser - BX LR - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Define strong version to return zero for -;; __iar_program_start to skip data sections -;; initialization. -;; - PUBLIC __low_level_init - SECTION .text:CODE:REORDER:NOROOT(2) -__low_level_init - MOVS R0, #0 - BX LR - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER:NOROOT(2) -Reset_Handler - - ; Define strong function for startup customization - LDR R0, =Cy_OnResetUser - BLX R0 - - ; Disable global interrupts - CPSID I - - ; Copy vectors from ROM to RAM - LDR r1, =__vector_table - LDR r0, =__ramVectors - LDR r2, =__Vectors_Size -intvec_copy - LDR r3, [r1] - STR r3, [r0] - ADDS r0, r0, #4 - ADDS r1, r1, #4 - SUBS r2, r2, #1 - CMP r2, #0 - BNE intvec_copy - - ; Update Vector Table Offset Register - LDR r0, =__ramVectors - LDR r1, =0xE000ED08 - STR r0, [r1] - dsb - - ; Initialize data sections - LDR R0, =__iar_data_init3 - BLX R0 - - LDR R0, =SystemInit - BLX R0 - - LDR R0, =__iar_program_start - BLX R0 - -; Should never get here -Cy_Main_Exited - B Cy_Main_Exited - - - PUBWEAK NMI_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -NMI_Handler - B NMI_Handler - - - PUBWEAK Cy_SysLib_FaultHandler - SECTION .text:CODE:REORDER:NOROOT(1) -Cy_SysLib_FaultHandler - B Cy_SysLib_FaultHandler - - PUBWEAK HardFault_Wrapper - SECTION .text:CODE:REORDER:NOROOT(1) -HardFault_Wrapper - IMPORT Cy_SysLib_FaultHandler - movs r0, #4 - mov r1, LR - tst r0, r1 - beq L_MSP - mrs r0, PSP - b L_API_call -L_MSP - mrs r0, MSP -L_API_call - ; Storing LR content for Creator call stack trace - push {LR} - bl Cy_SysLib_FaultHandler - - PUBWEAK HardFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -HardFault_Handler - B HardFault_Wrapper - - PUBWEAK MemManage_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -MemManage_Handler - B HardFault_Wrapper - - PUBWEAK BusFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -BusFault_Handler - B HardFault_Wrapper - - PUBWEAK UsageFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -UsageFault_Handler - B HardFault_Wrapper - - PUBWEAK SVC_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SVC_Handler - B SVC_Handler - - PUBWEAK DebugMon_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -DebugMon_Handler - B DebugMon_Handler - - PUBWEAK PendSV_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PendSV_Handler - B PendSV_Handler - - PUBWEAK SysTick_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SysTick_Handler - B SysTick_Handler - - - ; External interrupts - PUBWEAK ioss_interrupts_gpio_0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ioss_interrupts_gpio_0_IRQHandler - B ioss_interrupts_gpio_0_IRQHandler - - PUBWEAK ioss_interrupts_gpio_1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ioss_interrupts_gpio_1_IRQHandler - B ioss_interrupts_gpio_1_IRQHandler - - PUBWEAK ioss_interrupts_gpio_2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ioss_interrupts_gpio_2_IRQHandler - B ioss_interrupts_gpio_2_IRQHandler - - PUBWEAK ioss_interrupts_gpio_3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ioss_interrupts_gpio_3_IRQHandler - B ioss_interrupts_gpio_3_IRQHandler - - PUBWEAK ioss_interrupts_gpio_4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ioss_interrupts_gpio_4_IRQHandler - B ioss_interrupts_gpio_4_IRQHandler - - PUBWEAK ioss_interrupts_gpio_5_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ioss_interrupts_gpio_5_IRQHandler - B ioss_interrupts_gpio_5_IRQHandler - - PUBWEAK ioss_interrupts_gpio_6_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ioss_interrupts_gpio_6_IRQHandler - B ioss_interrupts_gpio_6_IRQHandler - - PUBWEAK ioss_interrupts_gpio_7_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ioss_interrupts_gpio_7_IRQHandler - B ioss_interrupts_gpio_7_IRQHandler - - PUBWEAK ioss_interrupts_gpio_8_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ioss_interrupts_gpio_8_IRQHandler - B ioss_interrupts_gpio_8_IRQHandler - - PUBWEAK ioss_interrupts_gpio_9_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ioss_interrupts_gpio_9_IRQHandler - B ioss_interrupts_gpio_9_IRQHandler - - PUBWEAK ioss_interrupts_gpio_10_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ioss_interrupts_gpio_10_IRQHandler - B ioss_interrupts_gpio_10_IRQHandler - - PUBWEAK ioss_interrupts_gpio_11_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ioss_interrupts_gpio_11_IRQHandler - B ioss_interrupts_gpio_11_IRQHandler - - PUBWEAK ioss_interrupts_gpio_12_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ioss_interrupts_gpio_12_IRQHandler - B ioss_interrupts_gpio_12_IRQHandler - - PUBWEAK ioss_interrupts_gpio_13_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ioss_interrupts_gpio_13_IRQHandler - B ioss_interrupts_gpio_13_IRQHandler - - PUBWEAK ioss_interrupts_gpio_14_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ioss_interrupts_gpio_14_IRQHandler - B ioss_interrupts_gpio_14_IRQHandler - - PUBWEAK ioss_interrupt_gpio_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ioss_interrupt_gpio_IRQHandler - B ioss_interrupt_gpio_IRQHandler - - PUBWEAK ioss_interrupt_vdd_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ioss_interrupt_vdd_IRQHandler - B ioss_interrupt_vdd_IRQHandler - - PUBWEAK lpcomp_interrupt_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -lpcomp_interrupt_IRQHandler - B lpcomp_interrupt_IRQHandler - - PUBWEAK scb_8_interrupt_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -scb_8_interrupt_IRQHandler - B scb_8_interrupt_IRQHandler - - PUBWEAK srss_interrupt_mcwdt_0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -srss_interrupt_mcwdt_0_IRQHandler - B srss_interrupt_mcwdt_0_IRQHandler - - PUBWEAK srss_interrupt_mcwdt_1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -srss_interrupt_mcwdt_1_IRQHandler - B srss_interrupt_mcwdt_1_IRQHandler - - PUBWEAK srss_interrupt_backup_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -srss_interrupt_backup_IRQHandler - B srss_interrupt_backup_IRQHandler - - PUBWEAK srss_interrupt_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -srss_interrupt_IRQHandler - B srss_interrupt_IRQHandler - - PUBWEAK pass_interrupt_ctbs_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -pass_interrupt_ctbs_IRQHandler - B pass_interrupt_ctbs_IRQHandler - - PUBWEAK bless_interrupt_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -bless_interrupt_IRQHandler - B bless_interrupt_IRQHandler - - PUBWEAK cpuss_interrupts_ipc_0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_ipc_0_IRQHandler - B cpuss_interrupts_ipc_0_IRQHandler - - PUBWEAK cpuss_interrupts_ipc_1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_ipc_1_IRQHandler - B cpuss_interrupts_ipc_1_IRQHandler - - PUBWEAK cpuss_interrupts_ipc_2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_ipc_2_IRQHandler - B cpuss_interrupts_ipc_2_IRQHandler - - PUBWEAK cpuss_interrupts_ipc_3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_ipc_3_IRQHandler - B cpuss_interrupts_ipc_3_IRQHandler - - PUBWEAK cpuss_interrupts_ipc_4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_ipc_4_IRQHandler - B cpuss_interrupts_ipc_4_IRQHandler - - PUBWEAK cpuss_interrupts_ipc_5_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_ipc_5_IRQHandler - B cpuss_interrupts_ipc_5_IRQHandler - - PUBWEAK cpuss_interrupts_ipc_6_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_ipc_6_IRQHandler - B cpuss_interrupts_ipc_6_IRQHandler - - PUBWEAK cpuss_interrupts_ipc_7_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_ipc_7_IRQHandler - B cpuss_interrupts_ipc_7_IRQHandler - - PUBWEAK cpuss_interrupts_ipc_8_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_ipc_8_IRQHandler - B cpuss_interrupts_ipc_8_IRQHandler - - PUBWEAK cpuss_interrupts_ipc_9_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_ipc_9_IRQHandler - B cpuss_interrupts_ipc_9_IRQHandler - - PUBWEAK cpuss_interrupts_ipc_10_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_ipc_10_IRQHandler - B cpuss_interrupts_ipc_10_IRQHandler - - PUBWEAK cpuss_interrupts_ipc_11_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_ipc_11_IRQHandler - B cpuss_interrupts_ipc_11_IRQHandler - - PUBWEAK cpuss_interrupts_ipc_12_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_ipc_12_IRQHandler - B cpuss_interrupts_ipc_12_IRQHandler - - PUBWEAK cpuss_interrupts_ipc_13_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_ipc_13_IRQHandler - B cpuss_interrupts_ipc_13_IRQHandler - - PUBWEAK cpuss_interrupts_ipc_14_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_ipc_14_IRQHandler - B cpuss_interrupts_ipc_14_IRQHandler - - PUBWEAK cpuss_interrupts_ipc_15_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_ipc_15_IRQHandler - B cpuss_interrupts_ipc_15_IRQHandler - - PUBWEAK scb_0_interrupt_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -scb_0_interrupt_IRQHandler - B scb_0_interrupt_IRQHandler - - PUBWEAK scb_1_interrupt_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -scb_1_interrupt_IRQHandler - B scb_1_interrupt_IRQHandler - - PUBWEAK scb_2_interrupt_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -scb_2_interrupt_IRQHandler - B scb_2_interrupt_IRQHandler - - PUBWEAK scb_3_interrupt_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -scb_3_interrupt_IRQHandler - B scb_3_interrupt_IRQHandler - - PUBWEAK scb_4_interrupt_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -scb_4_interrupt_IRQHandler - B scb_4_interrupt_IRQHandler - - PUBWEAK scb_5_interrupt_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -scb_5_interrupt_IRQHandler - B scb_5_interrupt_IRQHandler - - PUBWEAK scb_6_interrupt_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -scb_6_interrupt_IRQHandler - B scb_6_interrupt_IRQHandler - - PUBWEAK scb_7_interrupt_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -scb_7_interrupt_IRQHandler - B scb_7_interrupt_IRQHandler - - PUBWEAK csd_interrupt_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -csd_interrupt_IRQHandler - B csd_interrupt_IRQHandler - - PUBWEAK cpuss_interrupts_dw0_0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw0_0_IRQHandler - B cpuss_interrupts_dw0_0_IRQHandler - - PUBWEAK cpuss_interrupts_dw0_1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw0_1_IRQHandler - B cpuss_interrupts_dw0_1_IRQHandler - - PUBWEAK cpuss_interrupts_dw0_2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw0_2_IRQHandler - B cpuss_interrupts_dw0_2_IRQHandler - - PUBWEAK cpuss_interrupts_dw0_3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw0_3_IRQHandler - B cpuss_interrupts_dw0_3_IRQHandler - - PUBWEAK cpuss_interrupts_dw0_4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw0_4_IRQHandler - B cpuss_interrupts_dw0_4_IRQHandler - - PUBWEAK cpuss_interrupts_dw0_5_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw0_5_IRQHandler - B cpuss_interrupts_dw0_5_IRQHandler - - PUBWEAK cpuss_interrupts_dw0_6_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw0_6_IRQHandler - B cpuss_interrupts_dw0_6_IRQHandler - - PUBWEAK cpuss_interrupts_dw0_7_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw0_7_IRQHandler - B cpuss_interrupts_dw0_7_IRQHandler - - PUBWEAK cpuss_interrupts_dw0_8_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw0_8_IRQHandler - B cpuss_interrupts_dw0_8_IRQHandler - - PUBWEAK cpuss_interrupts_dw0_9_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw0_9_IRQHandler - B cpuss_interrupts_dw0_9_IRQHandler - - PUBWEAK cpuss_interrupts_dw0_10_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw0_10_IRQHandler - B cpuss_interrupts_dw0_10_IRQHandler - - PUBWEAK cpuss_interrupts_dw0_11_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw0_11_IRQHandler - B cpuss_interrupts_dw0_11_IRQHandler - - PUBWEAK cpuss_interrupts_dw0_12_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw0_12_IRQHandler - B cpuss_interrupts_dw0_12_IRQHandler - - PUBWEAK cpuss_interrupts_dw0_13_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw0_13_IRQHandler - B cpuss_interrupts_dw0_13_IRQHandler - - PUBWEAK cpuss_interrupts_dw0_14_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw0_14_IRQHandler - B cpuss_interrupts_dw0_14_IRQHandler - - PUBWEAK cpuss_interrupts_dw0_15_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw0_15_IRQHandler - B cpuss_interrupts_dw0_15_IRQHandler - - PUBWEAK cpuss_interrupts_dw1_0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw1_0_IRQHandler - B cpuss_interrupts_dw1_0_IRQHandler - - PUBWEAK cpuss_interrupts_dw1_1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw1_1_IRQHandler - B cpuss_interrupts_dw1_1_IRQHandler - - PUBWEAK cpuss_interrupts_dw1_2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw1_2_IRQHandler - B cpuss_interrupts_dw1_2_IRQHandler - - PUBWEAK cpuss_interrupts_dw1_3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw1_3_IRQHandler - B cpuss_interrupts_dw1_3_IRQHandler - - PUBWEAK cpuss_interrupts_dw1_4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw1_4_IRQHandler - B cpuss_interrupts_dw1_4_IRQHandler - - PUBWEAK cpuss_interrupts_dw1_5_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw1_5_IRQHandler - B cpuss_interrupts_dw1_5_IRQHandler - - PUBWEAK cpuss_interrupts_dw1_6_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw1_6_IRQHandler - B cpuss_interrupts_dw1_6_IRQHandler - - PUBWEAK cpuss_interrupts_dw1_7_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw1_7_IRQHandler - B cpuss_interrupts_dw1_7_IRQHandler - - PUBWEAK cpuss_interrupts_dw1_8_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw1_8_IRQHandler - B cpuss_interrupts_dw1_8_IRQHandler - - PUBWEAK cpuss_interrupts_dw1_9_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw1_9_IRQHandler - B cpuss_interrupts_dw1_9_IRQHandler - - PUBWEAK cpuss_interrupts_dw1_10_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw1_10_IRQHandler - B cpuss_interrupts_dw1_10_IRQHandler - - PUBWEAK cpuss_interrupts_dw1_11_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw1_11_IRQHandler - B cpuss_interrupts_dw1_11_IRQHandler - - PUBWEAK cpuss_interrupts_dw1_12_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw1_12_IRQHandler - B cpuss_interrupts_dw1_12_IRQHandler - - PUBWEAK cpuss_interrupts_dw1_13_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw1_13_IRQHandler - B cpuss_interrupts_dw1_13_IRQHandler - - PUBWEAK cpuss_interrupts_dw1_14_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw1_14_IRQHandler - B cpuss_interrupts_dw1_14_IRQHandler - - PUBWEAK cpuss_interrupts_dw1_15_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw1_15_IRQHandler - B cpuss_interrupts_dw1_15_IRQHandler - - PUBWEAK cpuss_interrupts_fault_0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_fault_0_IRQHandler - B cpuss_interrupts_fault_0_IRQHandler - - PUBWEAK cpuss_interrupts_fault_1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_fault_1_IRQHandler - B cpuss_interrupts_fault_1_IRQHandler - - PUBWEAK cpuss_interrupt_crypto_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupt_crypto_IRQHandler - B cpuss_interrupt_crypto_IRQHandler - - PUBWEAK cpuss_interrupt_fm_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupt_fm_IRQHandler - B cpuss_interrupt_fm_IRQHandler - - PUBWEAK cpuss_interrupts_cm0_cti_0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_cm0_cti_0_IRQHandler - B cpuss_interrupts_cm0_cti_0_IRQHandler - - PUBWEAK cpuss_interrupts_cm0_cti_1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_cm0_cti_1_IRQHandler - B cpuss_interrupts_cm0_cti_1_IRQHandler - - PUBWEAK cpuss_interrupts_cm4_cti_0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_cm4_cti_0_IRQHandler - B cpuss_interrupts_cm4_cti_0_IRQHandler - - PUBWEAK cpuss_interrupts_cm4_cti_1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_cm4_cti_1_IRQHandler - B cpuss_interrupts_cm4_cti_1_IRQHandler - - PUBWEAK tcpwm_0_interrupts_0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_0_interrupts_0_IRQHandler - B tcpwm_0_interrupts_0_IRQHandler - - PUBWEAK tcpwm_0_interrupts_1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_0_interrupts_1_IRQHandler - B tcpwm_0_interrupts_1_IRQHandler - - PUBWEAK tcpwm_0_interrupts_2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_0_interrupts_2_IRQHandler - B tcpwm_0_interrupts_2_IRQHandler - - PUBWEAK tcpwm_0_interrupts_3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_0_interrupts_3_IRQHandler - B tcpwm_0_interrupts_3_IRQHandler - - PUBWEAK tcpwm_0_interrupts_4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_0_interrupts_4_IRQHandler - B tcpwm_0_interrupts_4_IRQHandler - - PUBWEAK tcpwm_0_interrupts_5_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_0_interrupts_5_IRQHandler - B tcpwm_0_interrupts_5_IRQHandler - - PUBWEAK tcpwm_0_interrupts_6_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_0_interrupts_6_IRQHandler - B tcpwm_0_interrupts_6_IRQHandler - - PUBWEAK tcpwm_0_interrupts_7_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_0_interrupts_7_IRQHandler - B tcpwm_0_interrupts_7_IRQHandler - - PUBWEAK tcpwm_1_interrupts_0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_1_interrupts_0_IRQHandler - B tcpwm_1_interrupts_0_IRQHandler - - PUBWEAK tcpwm_1_interrupts_1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_1_interrupts_1_IRQHandler - B tcpwm_1_interrupts_1_IRQHandler - - PUBWEAK tcpwm_1_interrupts_2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_1_interrupts_2_IRQHandler - B tcpwm_1_interrupts_2_IRQHandler - - PUBWEAK tcpwm_1_interrupts_3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_1_interrupts_3_IRQHandler - B tcpwm_1_interrupts_3_IRQHandler - - PUBWEAK tcpwm_1_interrupts_4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_1_interrupts_4_IRQHandler - B tcpwm_1_interrupts_4_IRQHandler - - PUBWEAK tcpwm_1_interrupts_5_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_1_interrupts_5_IRQHandler - B tcpwm_1_interrupts_5_IRQHandler - - PUBWEAK tcpwm_1_interrupts_6_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_1_interrupts_6_IRQHandler - B tcpwm_1_interrupts_6_IRQHandler - - PUBWEAK tcpwm_1_interrupts_7_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_1_interrupts_7_IRQHandler - B tcpwm_1_interrupts_7_IRQHandler - - PUBWEAK tcpwm_1_interrupts_8_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_1_interrupts_8_IRQHandler - B tcpwm_1_interrupts_8_IRQHandler - - PUBWEAK tcpwm_1_interrupts_9_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_1_interrupts_9_IRQHandler - B tcpwm_1_interrupts_9_IRQHandler - - PUBWEAK tcpwm_1_interrupts_10_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_1_interrupts_10_IRQHandler - B tcpwm_1_interrupts_10_IRQHandler - - PUBWEAK tcpwm_1_interrupts_11_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_1_interrupts_11_IRQHandler - B tcpwm_1_interrupts_11_IRQHandler - - PUBWEAK tcpwm_1_interrupts_12_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_1_interrupts_12_IRQHandler - B tcpwm_1_interrupts_12_IRQHandler - - PUBWEAK tcpwm_1_interrupts_13_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_1_interrupts_13_IRQHandler - B tcpwm_1_interrupts_13_IRQHandler - - PUBWEAK tcpwm_1_interrupts_14_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_1_interrupts_14_IRQHandler - B tcpwm_1_interrupts_14_IRQHandler - - PUBWEAK tcpwm_1_interrupts_15_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_1_interrupts_15_IRQHandler - B tcpwm_1_interrupts_15_IRQHandler - - PUBWEAK tcpwm_1_interrupts_16_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_1_interrupts_16_IRQHandler - B tcpwm_1_interrupts_16_IRQHandler - - PUBWEAK tcpwm_1_interrupts_17_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_1_interrupts_17_IRQHandler - B tcpwm_1_interrupts_17_IRQHandler - - PUBWEAK tcpwm_1_interrupts_18_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_1_interrupts_18_IRQHandler - B tcpwm_1_interrupts_18_IRQHandler - - PUBWEAK tcpwm_1_interrupts_19_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_1_interrupts_19_IRQHandler - B tcpwm_1_interrupts_19_IRQHandler - - PUBWEAK tcpwm_1_interrupts_20_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_1_interrupts_20_IRQHandler - B tcpwm_1_interrupts_20_IRQHandler - - PUBWEAK tcpwm_1_interrupts_21_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_1_interrupts_21_IRQHandler - B tcpwm_1_interrupts_21_IRQHandler - - PUBWEAK tcpwm_1_interrupts_22_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_1_interrupts_22_IRQHandler - B tcpwm_1_interrupts_22_IRQHandler - - PUBWEAK tcpwm_1_interrupts_23_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_1_interrupts_23_IRQHandler - B tcpwm_1_interrupts_23_IRQHandler - - PUBWEAK udb_interrupts_0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -udb_interrupts_0_IRQHandler - B udb_interrupts_0_IRQHandler - - PUBWEAK udb_interrupts_1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -udb_interrupts_1_IRQHandler - B udb_interrupts_1_IRQHandler - - PUBWEAK udb_interrupts_2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -udb_interrupts_2_IRQHandler - B udb_interrupts_2_IRQHandler - - PUBWEAK udb_interrupts_3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -udb_interrupts_3_IRQHandler - B udb_interrupts_3_IRQHandler - - PUBWEAK udb_interrupts_4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -udb_interrupts_4_IRQHandler - B udb_interrupts_4_IRQHandler - - PUBWEAK udb_interrupts_5_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -udb_interrupts_5_IRQHandler - B udb_interrupts_5_IRQHandler - - PUBWEAK udb_interrupts_6_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -udb_interrupts_6_IRQHandler - B udb_interrupts_6_IRQHandler - - PUBWEAK udb_interrupts_7_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -udb_interrupts_7_IRQHandler - B udb_interrupts_7_IRQHandler - - PUBWEAK udb_interrupts_8_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -udb_interrupts_8_IRQHandler - B udb_interrupts_8_IRQHandler - - PUBWEAK udb_interrupts_9_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -udb_interrupts_9_IRQHandler - B udb_interrupts_9_IRQHandler - - PUBWEAK udb_interrupts_10_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -udb_interrupts_10_IRQHandler - B udb_interrupts_10_IRQHandler - - PUBWEAK udb_interrupts_11_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -udb_interrupts_11_IRQHandler - B udb_interrupts_11_IRQHandler - - PUBWEAK udb_interrupts_12_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -udb_interrupts_12_IRQHandler - B udb_interrupts_12_IRQHandler - - PUBWEAK udb_interrupts_13_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -udb_interrupts_13_IRQHandler - B udb_interrupts_13_IRQHandler - - PUBWEAK udb_interrupts_14_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -udb_interrupts_14_IRQHandler - B udb_interrupts_14_IRQHandler - - PUBWEAK udb_interrupts_15_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -udb_interrupts_15_IRQHandler - B udb_interrupts_15_IRQHandler - - PUBWEAK pass_interrupt_sar_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -pass_interrupt_sar_IRQHandler - B pass_interrupt_sar_IRQHandler - - PUBWEAK audioss_interrupt_i2s_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -audioss_interrupt_i2s_IRQHandler - B audioss_interrupt_i2s_IRQHandler - - PUBWEAK audioss_interrupt_pdm_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -audioss_interrupt_pdm_IRQHandler - B audioss_interrupt_pdm_IRQHandler - - PUBWEAK profile_interrupt_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -profile_interrupt_IRQHandler - B profile_interrupt_IRQHandler - - PUBWEAK smif_interrupt_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -smif_interrupt_IRQHandler - B smif_interrupt_IRQHandler - - PUBWEAK usb_interrupt_hi_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -usb_interrupt_hi_IRQHandler - B usb_interrupt_hi_IRQHandler - - PUBWEAK usb_interrupt_med_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -usb_interrupt_med_IRQHandler - B usb_interrupt_med_IRQHandler - - PUBWEAK usb_interrupt_lo_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -usb_interrupt_lo_IRQHandler - B usb_interrupt_lo_IRQHandler - - PUBWEAK pass_interrupt_dacs_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -pass_interrupt_dacs_IRQHandler - B pass_interrupt_dacs_IRQHandler - - - END - - -; [] END OF FILE diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/secure_image_parameters.json b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/secure_image_parameters.json deleted file mode 100644 index b66402fccc..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/secure_image_parameters.json +++ /dev/null @@ -1,17 +0,0 @@ -{ - "boot0" : { - "VERSION" : "0.1", - "ROLLBACK_COUNTER" : "0" - }, - - "boot1" : { - "VERSION" : "0.1", - "ROLLBACK_COUNTER" : "0" - }, - - "sdk_path" : "targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/", - "priv_key_file": "keys/USERAPP_CM4_KEY_PRIV.pem", - "aes_key_file": "keys/image-aes-128.key", - "dev_pub_key_file": "keys/dev_pub_key.pem", - "policy_file": "policy/policy_single_stage_CM4.json" -} diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c deleted file mode 100644 index 6fdc767d40..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c +++ /dev/null @@ -1,36 +0,0 @@ -/******************************************************************************* -* File Name: cycfg.c -* -* Description: -* Wrapper function to initialize all generated code. -* This file was automatically generated and should not be modified. -* Device Configurator: 2.0.0.1483 -* Device Support Library (../../../psoc6pdl): 1.4.1.2240 -* -******************************************************************************** -* Copyright 2017-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -********************************************************************************/ - -#include "cycfg.h" - -void init_cycfg_all(void) -{ - init_cycfg_system(); - init_cycfg_clocks(); - init_cycfg_routing(); - init_cycfg_peripherals(); - init_cycfg_pins(); -} diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h deleted file mode 100644 index 8c8d72f88d..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h +++ /dev/null @@ -1,49 +0,0 @@ -/******************************************************************************* -* File Name: cycfg.h -* -* Description: -* Simple wrapper header containing all generated files. -* This file was automatically generated and should not be modified. -* Device Configurator: 2.0.0.1483 -* Device Support Library (../../../psoc6pdl): 1.4.1.2240 -* -******************************************************************************** -* Copyright 2017-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -********************************************************************************/ - -#if !defined(CYCFG_H) -#define CYCFG_H - -#if defined(__cplusplus) -extern "C" { -#endif - -#include "cycfg_notices.h" -#include "cycfg_system.h" -#include "cycfg_clocks.h" -#include "cycfg_routing.h" -#include "cycfg_peripherals.h" -#include "cycfg_pins.h" - -void init_cycfg_all(void); - - -#if defined(__cplusplus) -} -#endif - - -#endif /* CYCFG_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp deleted file mode 100644 index 36387c70ae..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp +++ /dev/null @@ -1,26 +0,0 @@ -/******************************************************************************* -* File Name: cycfg.timestamp -* -* Description: -* Sentinel file for determining if generated source is up to date. -* This file was automatically generated and should not be modified. -* Device Configurator: 2.0.0.1483 -* Device Support Library (../../../psoc6pdl): 1.4.1.2240 -* -******************************************************************************** -* Copyright 2017-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -********************************************************************************/ - diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h deleted file mode 100644 index c709c9e26c..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h +++ /dev/null @@ -1,32 +0,0 @@ -/******************************************************************************* -* File Name: cycfg_notices.h -* -* Description: -* Contains warnings and errors that occurred while generating code for the -* design. -* This file was automatically generated and should not be modified. -* Device Configurator: 2.0.0.1483 -* Device Support Library (../../../psoc6pdl): 1.4.1.2240 -* -******************************************************************************** -* Copyright 2017-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -********************************************************************************/ - -#if !defined(CYCFG_NOTICES_H) -#define CYCFG_NOTICES_H - - -#endif /* CYCFG_NOTICES_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c deleted file mode 100644 index 7975fdc966..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c +++ /dev/null @@ -1,38 +0,0 @@ -/******************************************************************************* -* File Name: cycfg_peripherals.c -* -* Description: -* Peripheral Hardware Block configuration -* This file was automatically generated and should not be modified. -* Device Configurator: 2.0.0.1483 -* Device Support Library (../../../psoc6pdl): 1.4.1.2240 -* -******************************************************************************** -* Copyright 2017-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -********************************************************************************/ - -#include "cycfg_peripherals.h" - -cy_stc_csd_context_t cy_csd_0_context = -{ - .lockKey = CY_CSD_NONE_KEY, -}; - - -void init_cycfg_peripherals(void) -{ - Cy_SysClk_PeriphAssignDivider(PCLK_CSD_CLOCK, CY_SYSCLK_DIV_8_BIT, 0U); -} diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c deleted file mode 100644 index 0880c2f532..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c +++ /dev/null @@ -1,485 +0,0 @@ -/******************************************************************************* -* File Name: cycfg_pins.c -* -* Description: -* Pin configuration -* This file was automatically generated and should not be modified. -* Device Configurator: 2.0.0.1483 -* Device Support Library (../../../psoc6pdl): 1.4.1.2240 -* -******************************************************************************** -* Copyright 2017-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -********************************************************************************/ - -#include "cycfg_pins.h" - -const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_ANALOG, - .hsiom = CYBSP_WCO_IN_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_WCO_IN_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_WCO_IN_PORT_NUM, - .channel_num = CYBSP_WCO_IN_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_ANALOG, - .hsiom = CYBSP_WCO_OUT_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_WCO_OUT_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_WCO_OUT_PORT_NUM, - .channel_num = CYBSP_WCO_OUT_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_CSD_RX_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_ANALOG, - .hsiom = CYBSP_CSD_RX_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CSD_RX_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_CSD_RX_PORT_NUM, - .channel_num = CYBSP_CSD_RX_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_SWO_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_STRONG_IN_OFF, - .hsiom = CYBSP_SWO_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_SWO_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_SWO_PORT_NUM, - .channel_num = CYBSP_SWO_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_PULLUP, - .hsiom = CYBSP_SWDIO_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_SWDIO_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_SWDIO_PORT_NUM, - .channel_num = CYBSP_SWDIO_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_PULLDOWN, - .hsiom = CYBSP_SWDCK_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_SWDCK_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_SWDCK_PORT_NUM, - .channel_num = CYBSP_SWDCK_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_CINA_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_ANALOG, - .hsiom = CYBSP_CINA_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CINA_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_CINA_PORT_NUM, - .channel_num = CYBSP_CINA_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_CINB_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_ANALOG, - .hsiom = CYBSP_CINB_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CINB_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_CINB_PORT_NUM, - .channel_num = CYBSP_CINB_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_CMOD_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_ANALOG, - .hsiom = CYBSP_CMOD_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CMOD_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_CMOD_PORT_NUM, - .channel_num = CYBSP_CMOD_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_ANALOG, - .hsiom = CYBSP_CSD_BTN0_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CSD_BTN0_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_CSD_BTN0_PORT_NUM, - .channel_num = CYBSP_CSD_BTN0_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_ANALOG, - .hsiom = CYBSP_CSD_BTN1_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CSD_BTN1_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_CSD_BTN1_PORT_NUM, - .channel_num = CYBSP_CSD_BTN1_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_ANALOG, - .hsiom = CYBSP_CSD_SLD0_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CSD_SLD0_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_CSD_SLD0_PORT_NUM, - .channel_num = CYBSP_CSD_SLD0_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_ANALOG, - .hsiom = CYBSP_CSD_SLD1_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CSD_SLD1_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_CSD_SLD1_PORT_NUM, - .channel_num = CYBSP_CSD_SLD1_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_ANALOG, - .hsiom = CYBSP_CSD_SLD2_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CSD_SLD2_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_CSD_SLD2_PORT_NUM, - .channel_num = CYBSP_CSD_SLD2_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_ANALOG, - .hsiom = CYBSP_CSD_SLD3_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CSD_SLD3_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_CSD_SLD3_PORT_NUM, - .channel_num = CYBSP_CSD_SLD3_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_ANALOG, - .hsiom = CYBSP_CSD_SLD4_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CSD_SLD4_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_CSD_SLD4_PORT_NUM, - .channel_num = CYBSP_CSD_SLD4_PIN, - }; -#endif //defined (CY_USING_HAL) - - -void init_cycfg_pins(void) -{ - Cy_GPIO_Pin_Init(CYBSP_WCO_IN_PORT, CYBSP_WCO_IN_PIN, &CYBSP_WCO_IN_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_WCO_IN_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_WCO_OUT_PORT, CYBSP_WCO_OUT_PIN, &CYBSP_WCO_OUT_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_WCO_OUT_obj); -#endif //defined (CY_USING_HAL) - -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_CSD_RX_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_SWO_PORT, CYBSP_SWO_PIN, &CYBSP_SWO_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_SWO_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_SWDIO_PORT, CYBSP_SWDIO_PIN, &CYBSP_SWDIO_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_SWDIO_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_SWDCK_PORT, CYBSP_SWDCK_PIN, &CYBSP_SWDCK_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_SWDCK_obj); -#endif //defined (CY_USING_HAL) - -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_CINA_obj); -#endif //defined (CY_USING_HAL) - -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_CINB_obj); -#endif //defined (CY_USING_HAL) - -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_CMOD_obj); -#endif //defined (CY_USING_HAL) - -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_CSD_BTN0_obj); -#endif //defined (CY_USING_HAL) - -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_CSD_BTN1_obj); -#endif //defined (CY_USING_HAL) - -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_CSD_SLD0_obj); -#endif //defined (CY_USING_HAL) - -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_CSD_SLD1_obj); -#endif //defined (CY_USING_HAL) - -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_CSD_SLD2_obj); -#endif //defined (CY_USING_HAL) - -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_CSD_SLD3_obj); -#endif //defined (CY_USING_HAL) - -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_CSD_SLD4_obj); -#endif //defined (CY_USING_HAL) -} diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h deleted file mode 100644 index a49ede0f6a..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h +++ /dev/null @@ -1,498 +0,0 @@ -/******************************************************************************* -* File Name: cycfg_pins.h -* -* Description: -* Pin configuration -* This file was automatically generated and should not be modified. -* Device Configurator: 2.0.0.1483 -* Device Support Library (../../../psoc6pdl): 1.4.1.2240 -* -******************************************************************************** -* Copyright 2017-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -********************************************************************************/ - -#if !defined(CYCFG_PINS_H) -#define CYCFG_PINS_H - -#include "cycfg_notices.h" -#include "cy_gpio.h" -#if defined (CY_USING_HAL) - #include "cyhal_hwmgr.h" -#endif //defined (CY_USING_HAL) -#include "cycfg_routing.h" - -#if defined(__cplusplus) -extern "C" { -#endif - -#define CYBSP_WCO_IN_ENABLED 1U -#define CYBSP_WCO_IN_PORT GPIO_PRT0 -#define CYBSP_WCO_IN_PORT_NUM 0U -#define CYBSP_WCO_IN_PIN 0U -#define CYBSP_WCO_IN_NUM 0U -#define CYBSP_WCO_IN_DRIVEMODE CY_GPIO_DM_ANALOG -#define CYBSP_WCO_IN_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_0_pin_0_HSIOM - #define ioss_0_port_0_pin_0_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_WCO_IN_HSIOM ioss_0_port_0_pin_0_HSIOM -#define CYBSP_WCO_IN_IRQ ioss_interrupts_gpio_0_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_WCO_IN_HAL_PORT_PIN P0_0 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_WCO_IN_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_WCO_IN_HAL_DIR CYHAL_GPIO_DIR_INPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_WCO_IN_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG -#endif //defined (CY_USING_HAL) -#define CYBSP_WCO_OUT_ENABLED 1U -#define CYBSP_WCO_OUT_PORT GPIO_PRT0 -#define CYBSP_WCO_OUT_PORT_NUM 0U -#define CYBSP_WCO_OUT_PIN 1U -#define CYBSP_WCO_OUT_NUM 1U -#define CYBSP_WCO_OUT_DRIVEMODE CY_GPIO_DM_ANALOG -#define CYBSP_WCO_OUT_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_0_pin_1_HSIOM - #define ioss_0_port_0_pin_1_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_WCO_OUT_HSIOM ioss_0_port_0_pin_1_HSIOM -#define CYBSP_WCO_OUT_IRQ ioss_interrupts_gpio_0_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_WCO_OUT_HAL_PORT_PIN P0_1 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_WCO_OUT_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_WCO_OUT_HAL_DIR CYHAL_GPIO_DIR_INPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_WCO_OUT_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG -#endif //defined (CY_USING_HAL) -#define CYBSP_CSD_RX_ENABLED 1U -#define CYBSP_CSD_RX_PORT GPIO_PRT1 -#define CYBSP_CSD_RX_PORT_NUM 1U -#define CYBSP_CSD_RX_PIN 0U -#define CYBSP_CSD_RX_NUM 0U -#define CYBSP_CSD_RX_DRIVEMODE CY_GPIO_DM_ANALOG -#define CYBSP_CSD_RX_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_1_pin_0_HSIOM - #define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_CSD_RX_HSIOM ioss_0_port_1_pin_0_HSIOM -#define CYBSP_CSD_RX_IRQ ioss_interrupts_gpio_1_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_CSD_RX_HAL_PORT_PIN P1_0 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_CSD_RX_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_CSD_RX_HAL_DIR CYHAL_GPIO_DIR_INPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_CSD_RX_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG -#endif //defined (CY_USING_HAL) -#define CYBSP_SWO_ENABLED 1U -#define CYBSP_SWO_PORT GPIO_PRT6 -#define CYBSP_SWO_PORT_NUM 6U -#define CYBSP_SWO_PIN 4U -#define CYBSP_SWO_NUM 4U -#define CYBSP_SWO_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF -#define CYBSP_SWO_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_6_pin_4_HSIOM - #define ioss_0_port_6_pin_4_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_SWO_HSIOM ioss_0_port_6_pin_4_HSIOM -#define CYBSP_SWO_IRQ ioss_interrupts_gpio_6_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_SWO_HAL_PORT_PIN P6_4 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_SWO_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_SWO_HAL_DIR CYHAL_GPIO_DIR_OUTPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_SWO_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG -#endif //defined (CY_USING_HAL) -#define CYBSP_SWDIO_ENABLED 1U -#define CYBSP_SWDIO_PORT GPIO_PRT6 -#define CYBSP_SWDIO_PORT_NUM 6U -#define CYBSP_SWDIO_PIN 6U -#define CYBSP_SWDIO_NUM 6U -#define CYBSP_SWDIO_DRIVEMODE CY_GPIO_DM_PULLUP -#define CYBSP_SWDIO_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_6_pin_6_HSIOM - #define ioss_0_port_6_pin_6_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_SWDIO_HSIOM ioss_0_port_6_pin_6_HSIOM -#define CYBSP_SWDIO_IRQ ioss_interrupts_gpio_6_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_SWDIO_HAL_PORT_PIN P6_6 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_SWDIO_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_SWDIO_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_SWDIO_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLUP -#endif //defined (CY_USING_HAL) -#define CYBSP_SWDCK_ENABLED 1U -#define CYBSP_SWDCK_PORT GPIO_PRT6 -#define CYBSP_SWDCK_PORT_NUM 6U -#define CYBSP_SWDCK_PIN 7U -#define CYBSP_SWDCK_NUM 7U -#define CYBSP_SWDCK_DRIVEMODE CY_GPIO_DM_PULLDOWN -#define CYBSP_SWDCK_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_6_pin_7_HSIOM - #define ioss_0_port_6_pin_7_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_SWDCK_HSIOM ioss_0_port_6_pin_7_HSIOM -#define CYBSP_SWDCK_IRQ ioss_interrupts_gpio_6_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_SWDCK_HAL_PORT_PIN P6_7 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_SWDCK_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_SWDCK_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_SWDCK_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLDOWN -#endif //defined (CY_USING_HAL) -#define CYBSP_CINA_ENABLED 1U -#define CYBSP_CINA_PORT GPIO_PRT7 -#define CYBSP_CINA_PORT_NUM 7U -#define CYBSP_CINA_PIN 1U -#define CYBSP_CINA_NUM 1U -#define CYBSP_CINA_DRIVEMODE CY_GPIO_DM_ANALOG -#define CYBSP_CINA_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_7_pin_1_HSIOM - #define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_CINA_HSIOM ioss_0_port_7_pin_1_HSIOM -#define CYBSP_CINA_IRQ ioss_interrupts_gpio_7_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_CINA_HAL_PORT_PIN P7_1 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_CINA_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_CINA_HAL_DIR CYHAL_GPIO_DIR_INPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_CINA_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG -#endif //defined (CY_USING_HAL) -#define CYBSP_CINB_ENABLED 1U -#define CYBSP_CINB_PORT GPIO_PRT7 -#define CYBSP_CINB_PORT_NUM 7U -#define CYBSP_CINB_PIN 2U -#define CYBSP_CINB_NUM 2U -#define CYBSP_CINB_DRIVEMODE CY_GPIO_DM_ANALOG -#define CYBSP_CINB_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_7_pin_2_HSIOM - #define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_CINB_HSIOM ioss_0_port_7_pin_2_HSIOM -#define CYBSP_CINB_IRQ ioss_interrupts_gpio_7_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_CINB_HAL_PORT_PIN P7_2 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_CINB_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_CINB_HAL_DIR CYHAL_GPIO_DIR_INPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_CINB_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG -#endif //defined (CY_USING_HAL) -#define CYBSP_CMOD_ENABLED 1U -#define CYBSP_CMOD_PORT GPIO_PRT7 -#define CYBSP_CMOD_PORT_NUM 7U -#define CYBSP_CMOD_PIN 7U -#define CYBSP_CMOD_NUM 7U -#define CYBSP_CMOD_DRIVEMODE CY_GPIO_DM_ANALOG -#define CYBSP_CMOD_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_7_pin_7_HSIOM - #define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_CMOD_HSIOM ioss_0_port_7_pin_7_HSIOM -#define CYBSP_CMOD_IRQ ioss_interrupts_gpio_7_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_CMOD_HAL_PORT_PIN P7_7 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_CMOD_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_CMOD_HAL_DIR CYHAL_GPIO_DIR_INPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_CMOD_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG -#endif //defined (CY_USING_HAL) -#define CYBSP_CSD_BTN0_ENABLED 1U -#define CYBSP_CSD_BTN0_PORT GPIO_PRT8 -#define CYBSP_CSD_BTN0_PORT_NUM 8U -#define CYBSP_CSD_BTN0_PIN 1U -#define CYBSP_CSD_BTN0_NUM 1U -#define CYBSP_CSD_BTN0_DRIVEMODE CY_GPIO_DM_ANALOG -#define CYBSP_CSD_BTN0_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_8_pin_1_HSIOM - #define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_CSD_BTN0_HSIOM ioss_0_port_8_pin_1_HSIOM -#define CYBSP_CSD_BTN0_IRQ ioss_interrupts_gpio_8_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_CSD_BTN0_HAL_PORT_PIN P8_1 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_CSD_BTN0_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_CSD_BTN0_HAL_DIR CYHAL_GPIO_DIR_INPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_CSD_BTN0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG -#endif //defined (CY_USING_HAL) -#define CYBSP_CSD_BTN1_ENABLED 1U -#define CYBSP_CSD_BTN1_PORT GPIO_PRT8 -#define CYBSP_CSD_BTN1_PORT_NUM 8U -#define CYBSP_CSD_BTN1_PIN 2U -#define CYBSP_CSD_BTN1_NUM 2U -#define CYBSP_CSD_BTN1_DRIVEMODE CY_GPIO_DM_ANALOG -#define CYBSP_CSD_BTN1_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_8_pin_2_HSIOM - #define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_CSD_BTN1_HSIOM ioss_0_port_8_pin_2_HSIOM -#define CYBSP_CSD_BTN1_IRQ ioss_interrupts_gpio_8_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_CSD_BTN1_HAL_PORT_PIN P8_2 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_CSD_BTN1_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_CSD_BTN1_HAL_DIR CYHAL_GPIO_DIR_INPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_CSD_BTN1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG -#endif //defined (CY_USING_HAL) -#define CYBSP_CSD_SLD0_ENABLED 1U -#define CYBSP_CSD_SLD0_PORT GPIO_PRT8 -#define CYBSP_CSD_SLD0_PORT_NUM 8U -#define CYBSP_CSD_SLD0_PIN 3U -#define CYBSP_CSD_SLD0_NUM 3U -#define CYBSP_CSD_SLD0_DRIVEMODE CY_GPIO_DM_ANALOG -#define CYBSP_CSD_SLD0_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_8_pin_3_HSIOM - #define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_CSD_SLD0_HSIOM ioss_0_port_8_pin_3_HSIOM -#define CYBSP_CSD_SLD0_IRQ ioss_interrupts_gpio_8_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_CSD_SLD0_HAL_PORT_PIN P8_3 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_CSD_SLD0_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_CSD_SLD0_HAL_DIR CYHAL_GPIO_DIR_INPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_CSD_SLD0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG -#endif //defined (CY_USING_HAL) -#define CYBSP_CSD_SLD1_ENABLED 1U -#define CYBSP_CSD_SLD1_PORT GPIO_PRT8 -#define CYBSP_CSD_SLD1_PORT_NUM 8U -#define CYBSP_CSD_SLD1_PIN 4U -#define CYBSP_CSD_SLD1_NUM 4U -#define CYBSP_CSD_SLD1_DRIVEMODE CY_GPIO_DM_ANALOG -#define CYBSP_CSD_SLD1_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_8_pin_4_HSIOM - #define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_CSD_SLD1_HSIOM ioss_0_port_8_pin_4_HSIOM -#define CYBSP_CSD_SLD1_IRQ ioss_interrupts_gpio_8_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_CSD_SLD1_HAL_PORT_PIN P8_4 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_CSD_SLD1_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_CSD_SLD1_HAL_DIR CYHAL_GPIO_DIR_INPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_CSD_SLD1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG -#endif //defined (CY_USING_HAL) -#define CYBSP_CSD_SLD2_ENABLED 1U -#define CYBSP_CSD_SLD2_PORT GPIO_PRT8 -#define CYBSP_CSD_SLD2_PORT_NUM 8U -#define CYBSP_CSD_SLD2_PIN 5U -#define CYBSP_CSD_SLD2_NUM 5U -#define CYBSP_CSD_SLD2_DRIVEMODE CY_GPIO_DM_ANALOG -#define CYBSP_CSD_SLD2_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_8_pin_5_HSIOM - #define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_CSD_SLD2_HSIOM ioss_0_port_8_pin_5_HSIOM -#define CYBSP_CSD_SLD2_IRQ ioss_interrupts_gpio_8_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_CSD_SLD2_HAL_PORT_PIN P8_5 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_CSD_SLD2_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_CSD_SLD2_HAL_DIR CYHAL_GPIO_DIR_INPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_CSD_SLD2_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG -#endif //defined (CY_USING_HAL) -#define CYBSP_CSD_SLD3_ENABLED 1U -#define CYBSP_CSD_SLD3_PORT GPIO_PRT8 -#define CYBSP_CSD_SLD3_PORT_NUM 8U -#define CYBSP_CSD_SLD3_PIN 6U -#define CYBSP_CSD_SLD3_NUM 6U -#define CYBSP_CSD_SLD3_DRIVEMODE CY_GPIO_DM_ANALOG -#define CYBSP_CSD_SLD3_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_8_pin_6_HSIOM - #define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_CSD_SLD3_HSIOM ioss_0_port_8_pin_6_HSIOM -#define CYBSP_CSD_SLD3_IRQ ioss_interrupts_gpio_8_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_CSD_SLD3_HAL_PORT_PIN P8_6 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_CSD_SLD3_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_CSD_SLD3_HAL_DIR CYHAL_GPIO_DIR_INPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_CSD_SLD3_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG -#endif //defined (CY_USING_HAL) -#define CYBSP_CSD_SLD4_ENABLED 1U -#define CYBSP_CSD_SLD4_PORT GPIO_PRT8 -#define CYBSP_CSD_SLD4_PORT_NUM 8U -#define CYBSP_CSD_SLD4_PIN 7U -#define CYBSP_CSD_SLD4_NUM 7U -#define CYBSP_CSD_SLD4_DRIVEMODE CY_GPIO_DM_ANALOG -#define CYBSP_CSD_SLD4_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_8_pin_7_HSIOM - #define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_CSD_SLD4_HSIOM ioss_0_port_8_pin_7_HSIOM -#define CYBSP_CSD_SLD4_IRQ ioss_interrupts_gpio_8_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_CSD_SLD4_HAL_PORT_PIN P8_7 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_CSD_SLD4_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_CSD_SLD4_HAL_DIR CYHAL_GPIO_DIR_INPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_CSD_SLD4_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG -#endif //defined (CY_USING_HAL) - -extern const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_WCO_IN_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_WCO_OUT_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_CSD_RX_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_CSD_RX_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_SWO_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_SWO_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_SWDIO_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_SWDCK_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_CINA_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_CINA_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_CINB_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_CINB_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_CMOD_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_CMOD_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_CSD_BTN0_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_CSD_BTN1_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_CSD_SLD0_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_CSD_SLD1_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_CSD_SLD2_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_CSD_SLD3_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_CSD_SLD4_obj; -#endif //defined (CY_USING_HAL) - -void init_cycfg_pins(void); - -#if defined(__cplusplus) -} -#endif - - -#endif /* CYCFG_PINS_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c deleted file mode 100644 index 14d433859d..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c +++ /dev/null @@ -1,265 +0,0 @@ -/******************************************************************************* -* File Name: cycfg_qspi_memslot.c -* -* Description: -* Provides definitions of the SMIF-driver memory configuration. -* This file was automatically generated and should not be modified. -* -******************************************************************************** -* Copyright 2017-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -********************************************************************************/ - -#include "cycfg_qspi_memslot.h" - -const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readCmd = -{ - /* The 8-bit command. 1 x I/O read command. */ - .command = 0xECU, - /* The width of the command transfer. */ - .cmdWidth = CY_SMIF_WIDTH_SINGLE, - /* The width of the address transfer. */ - .addrWidth = CY_SMIF_WIDTH_QUAD, - /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */ - .mode = 0x01U, - /* The width of the mode command transfer. */ - .modeWidth = CY_SMIF_WIDTH_QUAD, - /* The number of dummy cycles. A zero value suggests no dummy cycles. */ - .dummyCycles = 4U, - /* The width of the data transfer. */ - .dataWidth = CY_SMIF_WIDTH_QUAD -}; - -const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeEnCmd = -{ - /* The 8-bit command. 1 x I/O read command. */ - .command = 0x06U, - /* The width of the command transfer. */ - .cmdWidth = CY_SMIF_WIDTH_SINGLE, - /* The width of the address transfer. */ - .addrWidth = CY_SMIF_WIDTH_SINGLE, - /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */ - .mode = 0xFFFFFFFFU, - /* The width of the mode command transfer. */ - .modeWidth = CY_SMIF_WIDTH_SINGLE, - /* The number of dummy cycles. A zero value suggests no dummy cycles. */ - .dummyCycles = 0U, - /* The width of the data transfer. */ - .dataWidth = CY_SMIF_WIDTH_SINGLE -}; - -const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeDisCmd = -{ - /* The 8-bit command. 1 x I/O read command. */ - .command = 0x04U, - /* The width of the command transfer. */ - .cmdWidth = CY_SMIF_WIDTH_SINGLE, - /* The width of the address transfer. */ - .addrWidth = CY_SMIF_WIDTH_SINGLE, - /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */ - .mode = 0xFFFFFFFFU, - /* The width of the mode command transfer. */ - .modeWidth = CY_SMIF_WIDTH_SINGLE, - /* The number of dummy cycles. A zero value suggests no dummy cycles. */ - .dummyCycles = 0U, - /* The width of the data transfer. */ - .dataWidth = CY_SMIF_WIDTH_SINGLE -}; - -const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_eraseCmd = -{ - /* The 8-bit command. 1 x I/O read command. */ - .command = 0xDCU, - /* The width of the command transfer. */ - .cmdWidth = CY_SMIF_WIDTH_SINGLE, - /* The width of the address transfer. */ - .addrWidth = CY_SMIF_WIDTH_SINGLE, - /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */ - .mode = 0xFFFFFFFFU, - /* The width of the mode command transfer. */ - .modeWidth = CY_SMIF_WIDTH_SINGLE, - /* The number of dummy cycles. A zero value suggests no dummy cycles. */ - .dummyCycles = 0U, - /* The width of the data transfer. */ - .dataWidth = CY_SMIF_WIDTH_SINGLE -}; - -const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_chipEraseCmd = -{ - /* The 8-bit command. 1 x I/O read command. */ - .command = 0x60U, - /* The width of the command transfer. */ - .cmdWidth = CY_SMIF_WIDTH_SINGLE, - /* The width of the address transfer. */ - .addrWidth = CY_SMIF_WIDTH_SINGLE, - /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */ - .mode = 0xFFFFFFFFU, - /* The width of the mode command transfer. */ - .modeWidth = CY_SMIF_WIDTH_SINGLE, - /* The number of dummy cycles. A zero value suggests no dummy cycles. */ - .dummyCycles = 0U, - /* The width of the data transfer. */ - .dataWidth = CY_SMIF_WIDTH_SINGLE -}; - -const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_programCmd = -{ - /* The 8-bit command. 1 x I/O read command. */ - .command = 0x34U, - /* The width of the command transfer. */ - .cmdWidth = CY_SMIF_WIDTH_SINGLE, - /* The width of the address transfer. */ - .addrWidth = CY_SMIF_WIDTH_SINGLE, - /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */ - .mode = 0xFFFFFFFFU, - /* The width of the mode command transfer. */ - .modeWidth = CY_SMIF_WIDTH_QUAD, - /* The number of dummy cycles. A zero value suggests no dummy cycles. */ - .dummyCycles = 0U, - /* The width of the data transfer. */ - .dataWidth = CY_SMIF_WIDTH_QUAD -}; - -const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readStsRegQeCmd = -{ - /* The 8-bit command. 1 x I/O read command. */ - .command = 0x35U, - /* The width of the command transfer. */ - .cmdWidth = CY_SMIF_WIDTH_SINGLE, - /* The width of the address transfer. */ - .addrWidth = CY_SMIF_WIDTH_SINGLE, - /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */ - .mode = 0xFFFFFFFFU, - /* The width of the mode command transfer. */ - .modeWidth = CY_SMIF_WIDTH_SINGLE, - /* The number of dummy cycles. A zero value suggests no dummy cycles. */ - .dummyCycles = 0U, - /* The width of the data transfer. */ - .dataWidth = CY_SMIF_WIDTH_SINGLE -}; - -const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readStsRegWipCmd = -{ - /* The 8-bit command. 1 x I/O read command. */ - .command = 0x05U, - /* The width of the command transfer. */ - .cmdWidth = CY_SMIF_WIDTH_SINGLE, - /* The width of the address transfer. */ - .addrWidth = CY_SMIF_WIDTH_SINGLE, - /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */ - .mode = 0xFFFFFFFFU, - /* The width of the mode command transfer. */ - .modeWidth = CY_SMIF_WIDTH_SINGLE, - /* The number of dummy cycles. A zero value suggests no dummy cycles. */ - .dummyCycles = 0U, - /* The width of the data transfer. */ - .dataWidth = CY_SMIF_WIDTH_SINGLE -}; - -const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeStsRegQeCmd = -{ - /* The 8-bit command. 1 x I/O read command. */ - .command = 0x01U, - /* The width of the command transfer. */ - .cmdWidth = CY_SMIF_WIDTH_SINGLE, - /* The width of the address transfer. */ - .addrWidth = CY_SMIF_WIDTH_SINGLE, - /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */ - .mode = 0xFFFFFFFFU, - /* The width of the mode command transfer. */ - .modeWidth = CY_SMIF_WIDTH_SINGLE, - /* The number of dummy cycles. A zero value suggests no dummy cycles. */ - .dummyCycles = 0U, - /* The width of the data transfer. */ - .dataWidth = CY_SMIF_WIDTH_SINGLE -}; - -const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512S_4byteaddr_SlaveSlot_0 = -{ - /* Specifies the number of address bytes used by the memory slave device. */ - .numOfAddrBytes = 0x04U, - /* The size of the memory. */ - .memSize = 0x04000000U, - /* Specifies the Read command. */ - .readCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_readCmd, - /* Specifies the Write Enable command. */ - .writeEnCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_writeEnCmd, - /* Specifies the Write Disable command. */ - .writeDisCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_writeDisCmd, - /* Specifies the Erase command. */ - .eraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_eraseCmd, - /* Specifies the sector size of each erase. */ - .eraseSize = 0x00040000U, - /* Specifies the Chip Erase command. */ - .chipEraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_chipEraseCmd, - /* Specifies the Program command. */ - .programCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_programCmd, - /* Specifies the page size for programming. */ - .programSize = 0x00000200U, - /* Specifies the command to read the QE-containing status register. */ - .readStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_readStsRegQeCmd, - /* Specifies the command to read the WIP-containing status register. */ - .readStsRegWipCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_readStsRegWipCmd, - /* Specifies the command to write into the QE-containing status register. */ - .writeStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_writeStsRegQeCmd, - /* The mask for the status register. */ - .stsRegBusyMask = 0x01U, - /* The mask for the status register. */ - .stsRegQuadEnableMask = 0x02U, - /* The max time for the erase type-1 cycle-time in ms. */ - .eraseTime = 2600U, - /* The max time for the chip-erase cycle-time in ms. */ - .chipEraseTime = 460000U, - /* The max time for the page-program cycle-time in us. */ - .programTime = 1300U -}; - -const cy_stc_smif_mem_config_t S25FL512S_4byteaddr_SlaveSlot_0 = -{ - /* Determines the slot number where the memory device is placed. */ - .slaveSelect = CY_SMIF_SLAVE_SELECT_0, - /* Flags. */ - .flags = CY_SMIF_FLAG_MEMORY_MAPPED | CY_SMIF_FLAG_WR_EN, - /* The data-line selection options for a slave device. */ - .dataSelect = CY_SMIF_DATA_SEL0, - /* The base address the memory slave is mapped to in the PSoC memory map. - Valid when the memory-mapped mode is enabled. */ - .baseAddress = 0x18000000U, - /* The size allocated in the PSoC memory map, for the memory slave device. - The size is allocated from the base address. Valid when the memory mapped mode is enabled. */ - .memMappedSize = 0x4000000U, - /* If this memory device is one of the devices in the dual quad SPI configuration. - Valid when the memory mapped mode is enabled. */ - .dualQuadSlots = 0, - /* The configuration of the device. */ - .deviceCfg = (cy_stc_smif_mem_device_cfg_t*)&deviceCfg_S25FL512S_4byteaddr_SlaveSlot_0 -}; - -const cy_stc_smif_mem_config_t* const smifMemConfigs[] = { - &S25FL512S_4byteaddr_SlaveSlot_0 -}; - -const cy_stc_smif_block_config_t smifBlockConfig = -{ - /* The number of SMIF memories defined. */ - .memCount = CY_SMIF_DEVICE_NUM, - /* The pointer to the array of memory config structures of size memCount. */ - .memConfig = (cy_stc_smif_mem_config_t**)smifMemConfigs, - /* The version of the SMIF driver. */ - .majorVersion = CY_SMIF_DRV_VERSION_MAJOR, - /* The version of the SMIF driver. */ - .minorVersion = CY_SMIF_DRV_VERSION_MINOR -}; - diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h deleted file mode 100644 index 0ee62b1d55..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h +++ /dev/null @@ -1,50 +0,0 @@ -/******************************************************************************* -* File Name: cycfg_qspi_memslot.h -* -* Description: -* Provides declarations of the SMIF-driver memory configuration. -* This file was automatically generated and should not be modified. -* -******************************************************************************** -* Copyright 2017-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -********************************************************************************/ - -#ifndef CYCFG_QSPI_MEMSLOT_H -#define CYCFG_QSPI_MEMSLOT_H -#include "cy_smif_memslot.h" - -#define CY_SMIF_DEVICE_NUM 1 - -extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readCmd; -extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeEnCmd; -extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeDisCmd; -extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_eraseCmd; -extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_chipEraseCmd; -extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_programCmd; -extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readStsRegQeCmd; -extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readStsRegWipCmd; -extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeStsRegQeCmd; - -extern const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512S_4byteaddr_SlaveSlot_0; - -extern const cy_stc_smif_mem_config_t S25FL512S_4byteaddr_SlaveSlot_0; -extern const cy_stc_smif_mem_config_t* const smifMemConfigs[CY_SMIF_DEVICE_NUM]; - -extern const cy_stc_smif_block_config_t smifBlockConfig; - - -#endif /*CY_SMIF_MEMCONFIG_H*/ - diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c deleted file mode 100644 index d44e67ee30..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c +++ /dev/null @@ -1,41 +0,0 @@ -/******************************************************************************* -* File Name: cycfg_routing.c -* -* Description: -* Establishes all necessary connections between hardware elements. -* This file was automatically generated and should not be modified. -* Device Configurator: 2.0.0.1483 -* Device Support Library (../../../psoc6pdl): 1.4.1.2240 -* -******************************************************************************** -* Copyright 2017-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -********************************************************************************/ - -#include "cycfg_routing.h" - -#include "cy_device_headers.h" - -void init_cycfg_routing(void) -{ - HSIOM->AMUX_SPLIT_CTL[2] = HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_AA_SL_Msk | - HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_AA_SR_Msk | - HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_BB_SL_Msk | - HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_BB_SR_Msk; - HSIOM->AMUX_SPLIT_CTL[4] = HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_AA_SL_Msk | - HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_AA_SR_Msk | - HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_BB_SL_Msk | - HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_BB_SR_Msk; -} diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c deleted file mode 100644 index 6ba1a500f2..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c +++ /dev/null @@ -1,573 +0,0 @@ -/******************************************************************************* -* File Name: cycfg_system.c -* -* Description: -* System configuration -* This file was automatically generated and should not be modified. -* Device Configurator: 2.0.0.1483 -* Device Support Library (../../../psoc6pdl): 1.4.1.2240 -* -******************************************************************************** -* Copyright 2017-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -********************************************************************************/ - -#include "cycfg_system.h" - -#define CY_CFG_SYSCLK_ECO_ERROR 1 -#define CY_CFG_SYSCLK_ALTHF_ERROR 2 -#define CY_CFG_SYSCLK_PLL_ERROR 3 -#define CY_CFG_SYSCLK_FLL_ERROR 4 -#define CY_CFG_SYSCLK_WCO_ERROR 5 -#define CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED 1 -#define CY_CFG_SYSCLK_CLKBAK_ENABLED 1 -#define CY_CFG_SYSCLK_CLKFAST_ENABLED 1 -#define CY_CFG_SYSCLK_FLL_ENABLED 1 -#define CY_CFG_SYSCLK_CLKHF0_ENABLED 1 -#define CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ 96UL -#define CY_CFG_SYSCLK_CLKHF0_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0 -#define CY_CFG_SYSCLK_CLKHF2_ENABLED 1 -#define CY_CFG_SYSCLK_CLKHF2_FREQ_MHZ 48UL -#define CY_CFG_SYSCLK_CLKHF2_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0 -#define CY_CFG_SYSCLK_CLKHF3_ENABLED 1 -#define CY_CFG_SYSCLK_CLKHF3_FREQ_MHZ 96UL -#define CY_CFG_SYSCLK_CLKHF3_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0 -#define CY_CFG_SYSCLK_CLKHF4_ENABLED 1 -#define CY_CFG_SYSCLK_CLKHF4_FREQ_MHZ 96UL -#define CY_CFG_SYSCLK_CLKHF4_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0 -#define CY_CFG_SYSCLK_ILO_ENABLED 1 -#define CY_CFG_SYSCLK_IMO_ENABLED 1 -#define CY_CFG_SYSCLK_CLKLF_ENABLED 1 -#define CY_CFG_SYSCLK_CLKPATH0_ENABLED 1 -#define CY_CFG_SYSCLK_CLKPATH0_SOURCE CY_SYSCLK_CLKPATH_IN_IMO -#define CY_CFG_SYSCLK_CLKPATH1_ENABLED 1 -#define CY_CFG_SYSCLK_CLKPATH1_SOURCE CY_SYSCLK_CLKPATH_IN_IMO -#define CY_CFG_SYSCLK_CLKPATH2_ENABLED 1 -#define CY_CFG_SYSCLK_CLKPATH2_SOURCE CY_SYSCLK_CLKPATH_IN_IMO -#define CY_CFG_SYSCLK_CLKPERI_ENABLED 1 -#define CY_CFG_SYSCLK_PLL0_ENABLED 1 -#define CY_CFG_SYSCLK_PLL1_ENABLED 1 -#define CY_CFG_SYSCLK_CLKSLOW_ENABLED 1 -#define CY_CFG_SYSCLK_CLKTIMER_ENABLED 1 -#define CY_CFG_SYSCLK_WCO_ENABLED 1 -#define CY_CFG_PWR_ENABLED 1 -#define CY_CFG_PWR_INIT 1 -#define CY_CFG_PWR_USING_PMIC 0 -#define CY_CFG_PWR_VBACKUP_USING_VDDD 1 -#define CY_CFG_PWR_LDO_VOLTAGE CY_SYSPM_LDO_VOLTAGE_LP -#define CY_CFG_PWR_USING_ULP 0 - -static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig = -{ - .fllMult = 504U, - .refDiv = 21U, - .ccoRange = CY_SYSCLK_FLL_CCO_RANGE4, - .enableOutputDiv = true, - .lockTolerance = 10U, - .igain = 9U, - .pgain = 4U, - .settlingCount = 8U, - .outputMode = CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT, - .cco_Freq = 320U, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj = - { - .type = CYHAL_RSC_CLKPATH, - .block_num = 0U, - .channel_num = 0U, - }; -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj = - { - .type = CYHAL_RSC_CLKPATH, - .block_num = 1U, - .channel_num = 0U, - }; -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj = - { - .type = CYHAL_RSC_CLKPATH, - .block_num = 2U, - .channel_num = 0U, - }; -#endif //defined (CY_USING_HAL) -static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_0_pllConfig = -{ - .feedbackDiv = 36, - .referenceDiv = 1, - .outputDiv = 2, - .lfMode = false, - .outputMode = CY_SYSCLK_FLLPLL_OUTPUT_AUTO, -}; -static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_1_pllConfig = -{ - .feedbackDiv = 30, - .referenceDiv = 1, - .outputDiv = 5, - .lfMode = false, - .outputMode = CY_SYSCLK_FLLPLL_OUTPUT_AUTO, -}; - -__WEAK void cycfg_ClockStartupError(uint32_t error) -{ - (void)error; /* Suppress the compiler warning */ - while(1); -} -__STATIC_INLINE void Cy_SysClk_ClkAltSysTickInit() -{ - Cy_SysTick_SetClockSource(CY_SYSTICK_CLOCK_SOURCE_CLK_LF); -} -__STATIC_INLINE void Cy_SysClk_ClkBakInit() -{ - Cy_SysClk_ClkBakSetSource(CY_SYSCLK_BAK_IN_CLKLF); -} -__STATIC_INLINE void Cy_SysClk_ClkFastInit() -{ - Cy_SysClk_ClkFastSetDivider(0U); -} -__STATIC_INLINE void Cy_SysClk_FllInit() -{ - if (CY_SYSCLK_SUCCESS != Cy_SysClk_FllManualConfigure(&srss_0_clock_0_fll_0_fllConfig)) - { - cycfg_ClockStartupError(CY_CFG_SYSCLK_FLL_ERROR); - } - if (CY_SYSCLK_SUCCESS != Cy_SysClk_FllEnable(200000UL)) - { - cycfg_ClockStartupError(CY_CFG_SYSCLK_FLL_ERROR); - } -} -__STATIC_INLINE void Cy_SysClk_ClkHf0Init() -{ - Cy_SysClk_ClkHfSetSource(0U, CY_CFG_SYSCLK_CLKHF0_CLKPATH); - Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE); -} -__STATIC_INLINE void Cy_SysClk_ClkHf2Init() -{ - Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF2, CY_CFG_SYSCLK_CLKHF2_CLKPATH); - Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF2, CY_SYSCLK_CLKHF_DIVIDE_BY_2); - Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF2); -} -__STATIC_INLINE void Cy_SysClk_ClkHf3Init() -{ - Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF3, CY_CFG_SYSCLK_CLKHF3_CLKPATH); - Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF3, CY_SYSCLK_CLKHF_NO_DIVIDE); - Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF3); -} -__STATIC_INLINE void Cy_SysClk_ClkHf4Init() -{ - Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF4, CY_CFG_SYSCLK_CLKHF4_CLKPATH); - Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF4, CY_SYSCLK_CLKHF_NO_DIVIDE); - Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF4); -} -__STATIC_INLINE void Cy_SysClk_IloInit() -{ - /* The WDT is unlocked in the default startup code */ - Cy_SysClk_IloEnable(); - Cy_SysClk_IloHibernateOn(true); -} -__STATIC_INLINE void Cy_SysClk_ClkLfInit() -{ - /* The WDT is unlocked in the default startup code */ - Cy_SysClk_ClkLfSetSource(CY_SYSCLK_CLKLF_IN_WCO); -} -__STATIC_INLINE void Cy_SysClk_ClkPath0Init() -{ - Cy_SysClk_ClkPathSetSource(0U, CY_CFG_SYSCLK_CLKPATH0_SOURCE); -} -__STATIC_INLINE void Cy_SysClk_ClkPath1Init() -{ - Cy_SysClk_ClkPathSetSource(1U, CY_CFG_SYSCLK_CLKPATH1_SOURCE); -} -__STATIC_INLINE void Cy_SysClk_ClkPath2Init() -{ - Cy_SysClk_ClkPathSetSource(2U, CY_CFG_SYSCLK_CLKPATH2_SOURCE); -} -__STATIC_INLINE void Cy_SysClk_ClkPeriInit() -{ - Cy_SysClk_ClkPeriSetDivider(1U); -} -__STATIC_INLINE void Cy_SysClk_Pll0Init() -{ - if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllManualConfigure(1U, &srss_0_clock_0_pll_0_pllConfig)) - { - cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR); - } - if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllEnable(1U, 10000u)) - { - cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR); - } -} -__STATIC_INLINE void Cy_SysClk_Pll1Init() -{ - if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllManualConfigure(2U, &srss_0_clock_0_pll_1_pllConfig)) - { - cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR); - } - if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllEnable(2U, 10000u)) - { - cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR); - } -} -__STATIC_INLINE void Cy_SysClk_ClkSlowInit() -{ - Cy_SysClk_ClkSlowSetDivider(0U); -} -__STATIC_INLINE void Cy_SysClk_ClkTimerInit() -{ - Cy_SysClk_ClkTimerDisable(); - Cy_SysClk_ClkTimerSetSource(CY_SYSCLK_CLKTIMER_IN_IMO); - Cy_SysClk_ClkTimerSetDivider(0U); - Cy_SysClk_ClkTimerEnable(); -} -__STATIC_INLINE void Cy_SysClk_WcoInit() -{ - (void)Cy_GPIO_Pin_FastInit(GPIO_PRT0, 0U, 0x00U, 0x00U, HSIOM_SEL_GPIO); - (void)Cy_GPIO_Pin_FastInit(GPIO_PRT0, 1U, 0x00U, 0x00U, HSIOM_SEL_GPIO); - if (CY_SYSCLK_SUCCESS != Cy_SysClk_WcoEnable(1000000UL)) - { - cycfg_ClockStartupError(CY_CFG_SYSCLK_WCO_ERROR); - } -} -__STATIC_INLINE void init_cycfg_power(void) -{ - /* Reset the Backup domain on POR, XRES, BOD only if Backup domain is supplied by VDDD */ - #if (CY_CFG_PWR_VBACKUP_USING_VDDD) - #ifdef CY_CFG_SYSCLK_ILO_ENABLED - if (0u == Cy_SysLib_GetResetReason() /* POR, XRES, or BOD */) - { - Cy_SysLib_ResetBackupDomain(); - Cy_SysClk_IloDisable(); - Cy_SysClk_IloInit(); - } - #endif /* CY_CFG_SYSCLK_ILO_ENABLED */ - #endif /* CY_CFG_PWR_VBACKUP_USING_VDDD */ - - /* Configure core regulator */ - #if CY_CFG_PWR_USING_LDO - Cy_SysPm_LdoSetVoltage(CY_SYSPM_LDO_VOLTAGE_LP); - Cy_SysPm_LdoSetMode(CY_SYSPM_LDO_MODE_NORMAL); - #else - Cy_SysPm_BuckEnable(CY_SYSPM_BUCK_OUT1_VOLTAGE_LP); - #endif /* CY_CFG_PWR_USING_LDO */ - /* Configure PMIC */ - Cy_SysPm_UnlockPmic(); - #if CY_CFG_PWR_USING_PMIC - Cy_SysPm_PmicEnableOutput(); - #else - Cy_SysPm_PmicDisableOutput(); - #endif /* CY_CFG_PWR_USING_PMIC */ -} - - -void init_cycfg_system(void) -{ - /* Set worst case memory wait states (! ultra low power, 150 MHz), will update at the end */ - Cy_SysLib_SetWaitStates(false, 150UL); - #ifdef CY_CFG_PWR_ENABLED - #ifdef CY_CFG_PWR_INIT - init_cycfg_power(); - #else - #warning Power system will not be configured. Update power personality to v1.20 or later. - #endif /* CY_CFG_PWR_INIT */ - #endif /* CY_CFG_PWR_ENABLED */ - - /* Reset the core clock path to default and disable all the FLLs/PLLs */ - Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE); - Cy_SysClk_ClkFastSetDivider(0U); - Cy_SysClk_ClkPeriSetDivider(1U); - Cy_SysClk_ClkSlowSetDivider(0U); - for (uint32_t pll = CY_SRSS_NUM_PLL; pll > 0UL; --pll) /* PLL 1 is the first PLL. 0 is invalid. */ - { - (void)Cy_SysClk_PllDisable(pll); - } - Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH1, CY_SYSCLK_CLKPATH_IN_IMO); - - if ((CY_SYSCLK_CLKHF_IN_CLKPATH0 == Cy_SysClk_ClkHfGetSource(0UL)) && - (CY_SYSCLK_CLKPATH_IN_WCO == Cy_SysClk_ClkPathGetSource(CY_SYSCLK_CLKHF_IN_CLKPATH0))) - { - Cy_SysClk_ClkHfSetSource(0U, CY_SYSCLK_CLKHF_IN_CLKPATH1); - } - - Cy_SysClk_FllDisable(); - Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH0, CY_SYSCLK_CLKPATH_IN_IMO); - Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH0); - #ifdef CY_IP_MXBLESS - (void)Cy_BLE_EcoReset(); - #endif - - - /* Enable all source clocks */ - #ifdef CY_CFG_SYSCLK_PILO_ENABLED - Cy_SysClk_PiloInit(); - #endif - - #ifdef CY_CFG_SYSCLK_WCO_ENABLED - Cy_SysClk_WcoInit(); - #endif - - #ifdef CY_CFG_SYSCLK_CLKLF_ENABLED - Cy_SysClk_ClkLfInit(); - #endif - - #ifdef CY_CFG_SYSCLK_ALTHF_ENABLED - Cy_SysClk_AltHfInit(); - #endif - - #ifdef CY_CFG_SYSCLK_ECO_ENABLED - Cy_SysClk_EcoInit(); - #endif - - #ifdef CY_CFG_SYSCLK_EXTCLK_ENABLED - Cy_SysClk_ExtClkInit(); - #endif - - /* Configure CPU clock dividers */ - #ifdef CY_CFG_SYSCLK_CLKFAST_ENABLED - Cy_SysClk_ClkFastInit(); - #endif - - #ifdef CY_CFG_SYSCLK_CLKPERI_ENABLED - Cy_SysClk_ClkPeriInit(); - #endif - - #ifdef CY_CFG_SYSCLK_CLKSLOW_ENABLED - Cy_SysClk_ClkSlowInit(); - #endif - - #if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE == CY_SYSCLK_CLKPATH_IN_WCO) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH == CY_SYSCLK_CLKHF_IN_CLKPATH0)) - /* Configure HFCLK0 to temporarily run from IMO to initialize other clocks */ - Cy_SysClk_ClkPathSetSource(1UL, CY_SYSCLK_CLKPATH_IN_IMO); - Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH1); - #else - #ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED - Cy_SysClk_ClkPath1Init(); - #endif - #endif - - /* Configure Path Clocks */ - #ifdef CY_CFG_SYSCLK_CLKPATH0_ENABLED - Cy_SysClk_ClkPath0Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKPATH2_ENABLED - Cy_SysClk_ClkPath2Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKPATH3_ENABLED - Cy_SysClk_ClkPath3Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKPATH4_ENABLED - Cy_SysClk_ClkPath4Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKPATH5_ENABLED - Cy_SysClk_ClkPath5Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKPATH6_ENABLED - Cy_SysClk_ClkPath6Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKPATH7_ENABLED - Cy_SysClk_ClkPath7Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKPATH8_ENABLED - Cy_SysClk_ClkPath8Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKPATH9_ENABLED - Cy_SysClk_ClkPath9Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKPATH10_ENABLED - Cy_SysClk_ClkPath10Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKPATH11_ENABLED - Cy_SysClk_ClkPath11Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKPATH12_ENABLED - Cy_SysClk_ClkPath12Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKPATH13_ENABLED - Cy_SysClk_ClkPath13Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKPATH14_ENABLED - Cy_SysClk_ClkPath14Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKPATH15_ENABLED - Cy_SysClk_ClkPath15Init(); - #endif - - /* Configure and enable FLL */ - #ifdef CY_CFG_SYSCLK_FLL_ENABLED - Cy_SysClk_FllInit(); - #endif - - Cy_SysClk_ClkHf0Init(); - - #if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE == CY_SYSCLK_CLKPATH_IN_WCO) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH == CY_SYSCLK_CLKHF_IN_CLKPATH0)) - #ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED - /* Apply the ClkPath1 user setting */ - Cy_SysClk_ClkPath1Init(); - #endif - #endif - - /* Configure and enable PLLs */ - #ifdef CY_CFG_SYSCLK_PLL0_ENABLED - Cy_SysClk_Pll0Init(); - #endif - #ifdef CY_CFG_SYSCLK_PLL1_ENABLED - Cy_SysClk_Pll1Init(); - #endif - #ifdef CY_CFG_SYSCLK_PLL2_ENABLED - Cy_SysClk_Pll2Init(); - #endif - #ifdef CY_CFG_SYSCLK_PLL3_ENABLED - Cy_SysClk_Pll3Init(); - #endif - #ifdef CY_CFG_SYSCLK_PLL4_ENABLED - Cy_SysClk_Pll4Init(); - #endif - #ifdef CY_CFG_SYSCLK_PLL5_ENABLED - Cy_SysClk_Pll5Init(); - #endif - #ifdef CY_CFG_SYSCLK_PLL6_ENABLED - Cy_SysClk_Pll6Init(); - #endif - #ifdef CY_CFG_SYSCLK_PLL7_ENABLED - Cy_SysClk_Pll7Init(); - #endif - #ifdef CY_CFG_SYSCLK_PLL8_ENABLED - Cy_SysClk_Pll8Init(); - #endif - #ifdef CY_CFG_SYSCLK_PLL9_ENABLED - Cy_SysClk_Pll9Init(); - #endif - #ifdef CY_CFG_SYSCLK_PLL10_ENABLED - Cy_SysClk_Pll10Init(); - #endif - #ifdef CY_CFG_SYSCLK_PLL11_ENABLED - Cy_SysClk_Pll11Init(); - #endif - #ifdef CY_CFG_SYSCLK_PLL12_ENABLED - Cy_SysClk_Pll12Init(); - #endif - #ifdef CY_CFG_SYSCLK_PLL13_ENABLED - Cy_SysClk_Pll13Init(); - #endif - #ifdef CY_CFG_SYSCLK_PLL14_ENABLED - Cy_SysClk_Pll14Init(); - #endif - - /* Configure HF clocks */ - #ifdef CY_CFG_SYSCLK_CLKHF1_ENABLED - Cy_SysClk_ClkHf1Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKHF2_ENABLED - Cy_SysClk_ClkHf2Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKHF3_ENABLED - Cy_SysClk_ClkHf3Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKHF4_ENABLED - Cy_SysClk_ClkHf4Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKHF5_ENABLED - Cy_SysClk_ClkHf5Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKHF6_ENABLED - Cy_SysClk_ClkHf6Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKHF7_ENABLED - Cy_SysClk_ClkHf7Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKHF8_ENABLED - Cy_SysClk_ClkHf8Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKHF9_ENABLED - Cy_SysClk_ClkHf9Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKHF10_ENABLED - Cy_SysClk_ClkHf10Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKHF11_ENABLED - Cy_SysClk_ClkHf11Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKHF12_ENABLED - Cy_SysClk_ClkHf12Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKHF13_ENABLED - Cy_SysClk_ClkHf13Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKHF14_ENABLED - Cy_SysClk_ClkHf14Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKHF15_ENABLED - Cy_SysClk_ClkHf15Init(); - #endif - - /* Configure miscellaneous clocks */ - #ifdef CY_CFG_SYSCLK_CLKTIMER_ENABLED - Cy_SysClk_ClkTimerInit(); - #endif - - #ifdef CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED - Cy_SysClk_ClkAltSysTickInit(); - #endif - - #ifdef CY_CFG_SYSCLK_CLKPUMP_ENABLED - Cy_SysClk_ClkPumpInit(); - #endif - - #ifdef CY_CFG_SYSCLK_CLKBAK_ENABLED - Cy_SysClk_ClkBakInit(); - #endif - - /* Configure default enabled clocks */ - #ifdef CY_CFG_SYSCLK_ILO_ENABLED - Cy_SysClk_IloInit(); - #else - Cy_SysClk_IloDisable(); - Cy_SysClk_IloHibernateOn(false); - #endif - - #ifndef CY_CFG_SYSCLK_IMO_ENABLED - #error the IMO must be enabled for proper chip operation - #endif - - #ifdef CY_CFG_SYSCLK_MFO_ENABLED - Cy_SysClk_MfoInit(); - #endif - - #ifdef CY_CFG_SYSCLK_CLKMF_ENABLED - Cy_SysClk_ClkMfInit(); - #endif - - /* Set accurate flash wait states */ - #if (defined (CY_CFG_PWR_ENABLED) && defined (CY_CFG_SYSCLK_CLKHF0_ENABLED)) - Cy_SysLib_SetWaitStates(CY_CFG_PWR_USING_ULP != 0, CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ); - #endif - - /* Update System Core Clock values for correct Cy_SysLib_Delay functioning */ - SystemCoreClockUpdate(); - -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_0_obj); -#endif //defined (CY_USING_HAL) - -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_1_obj); -#endif //defined (CY_USING_HAL) - -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_2_obj); -#endif //defined (CY_USING_HAL) -} diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/qspi_config.cfg b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/qspi_config.cfg deleted file mode 100644 index 5557ddecdd..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/qspi_config.cfg +++ /dev/null @@ -1,4 +0,0 @@ -set SMIF_BANKS { - 0 {addr 0x18000000 size 0x4000000 psize 0x00000200 esize 0x00040000} -} - diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list deleted file mode 100644 index 8453a4470f..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list +++ /dev/null @@ -1,20 +0,0 @@ -[Device=CY8C624ABZI-D44] - -[Blocks] -# WIFI -# CYBSP_WIFI_SDIO -sdhc[0] -# CYBSP_WIFI_SDIO_D0 -ioss[0].port[2].pin[0] -# CYBSP_WIFI_SDIO_D1 -ioss[0].port[2].pin[1] -# CYBSP_WIFI_SDIO_D2 -ioss[0].port[2].pin[2] -# CYBSP_WIFI_SDIO_D3 -ioss[0].port[2].pin[3] -# CYBSP_WIFI_SDIO_CMD -ioss[0].port[2].pin[4] -# CYBSP_WIFI_SDIO_CLK -ioss[0].port[2].pin[5] -# CYBSP_WIFI_WL_REG_ON -ioss[0].port[2].pin[6] \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/design.cycapsense b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/design.cycapsense deleted file mode 100644 index 978ea026ca..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/design.cycapsense +++ /dev/null @@ -1,402 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/PeripheralPins.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/PeripheralPins.c deleted file mode 100644 index 4df4072376..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/PeripheralPins.c +++ /dev/null @@ -1,467 +0,0 @@ -/* - * mbed Microcontroller Library - * Copyright (c) 2017-2018 Future Electronics - * Copyright (c) 2019 Cypress Semiconductor Corporation - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "PeripheralNames.h" -#include "PeripheralPins.h" -#include "pinmap.h" - -#if DEVICE_SERIAL -//*** SERIAL *** -const PinMap PinMap_UART_RX[] = { - {P0_2, UART_0, CYHAL_PIN_IN_FUNCTION(P0_2_SCB0_UART_RX)}, - {P1_0, UART_7, CYHAL_PIN_IN_FUNCTION(P1_0_SCB7_UART_RX)}, - {P2_0, UART_1, CYHAL_PIN_IN_FUNCTION(P2_0_SCB1_UART_RX)}, - {P3_0, UART_2, CYHAL_PIN_IN_FUNCTION(P3_0_SCB2_UART_RX)}, - {P4_0, UART_7, CYHAL_PIN_IN_FUNCTION(P4_0_SCB7_UART_RX)}, - {P5_0, UART_5, CYHAL_PIN_IN_FUNCTION(P5_0_SCB5_UART_RX)}, - {P6_0, UART_3, CYHAL_PIN_IN_FUNCTION(P6_0_SCB3_UART_RX)}, - {P6_4, UART_6, CYHAL_PIN_IN_FUNCTION(P6_4_SCB6_UART_RX)}, - {P7_0, UART_4, CYHAL_PIN_IN_FUNCTION(P7_0_SCB4_UART_RX)}, - {P8_0, UART_4, CYHAL_PIN_IN_FUNCTION(P8_0_SCB4_UART_RX)}, - {P9_0, UART_2, CYHAL_PIN_IN_FUNCTION(P9_0_SCB2_UART_RX)}, - {P10_0, UART_1, CYHAL_PIN_IN_FUNCTION(P10_0_SCB1_UART_RX)}, - {P11_0, UART_5, CYHAL_PIN_IN_FUNCTION(P11_0_SCB5_UART_RX)}, - {P12_0, UART_6, CYHAL_PIN_IN_FUNCTION(P12_0_SCB6_UART_RX)}, - {P13_0, UART_6, CYHAL_PIN_IN_FUNCTION(P13_0_SCB6_UART_RX)}, - {NC, NC, 0} -}; -const PinMap PinMap_UART_TX[] = { - {P0_3, UART_0, CYHAL_PIN_OUT_FUNCTION(P0_3_SCB0_UART_TX)}, - {P1_1, UART_7, CYHAL_PIN_OUT_FUNCTION(P1_1_SCB7_UART_TX)}, - {P2_1, UART_1, CYHAL_PIN_OUT_FUNCTION(P2_1_SCB1_UART_TX)}, - {P3_1, UART_2, CYHAL_PIN_OUT_FUNCTION(P3_1_SCB2_UART_TX)}, - {P4_1, UART_7, CYHAL_PIN_OUT_FUNCTION(P4_1_SCB7_UART_TX)}, - {P5_1, UART_5, CYHAL_PIN_OUT_FUNCTION(P5_1_SCB5_UART_TX)}, - {P6_1, UART_3, CYHAL_PIN_OUT_FUNCTION(P6_1_SCB3_UART_TX)}, - {P6_5, UART_6, CYHAL_PIN_OUT_FUNCTION(P6_5_SCB6_UART_TX)}, - {P7_1, UART_4, CYHAL_PIN_OUT_FUNCTION(P7_1_SCB4_UART_TX)}, - {P8_1, UART_4, CYHAL_PIN_OUT_FUNCTION(P8_1_SCB4_UART_TX)}, - {P9_1, UART_2, CYHAL_PIN_OUT_FUNCTION(P9_1_SCB2_UART_TX)}, - {P10_1, UART_1, CYHAL_PIN_OUT_FUNCTION(P10_1_SCB1_UART_TX)}, - {P11_1, UART_5, CYHAL_PIN_OUT_FUNCTION(P11_1_SCB5_UART_TX)}, - {P12_1, UART_6, CYHAL_PIN_OUT_FUNCTION(P12_1_SCB6_UART_TX)}, - {P13_1, UART_6, CYHAL_PIN_OUT_FUNCTION(P13_1_SCB6_UART_TX)}, - {NC, NC, 0} -}; -const PinMap PinMap_UART_RTS[] = { - {P0_4, UART_0, CYHAL_PIN_OUT_FUNCTION(P0_4_SCB0_UART_RTS)}, - {P1_2, UART_7, CYHAL_PIN_OUT_FUNCTION(P1_2_SCB7_UART_RTS)}, - {P2_2, UART_1, CYHAL_PIN_OUT_FUNCTION(P2_2_SCB1_UART_RTS)}, - {P3_2, UART_2, CYHAL_PIN_OUT_FUNCTION(P3_2_SCB2_UART_RTS)}, - {P5_2, UART_5, CYHAL_PIN_OUT_FUNCTION(P5_2_SCB5_UART_RTS)}, - {P6_2, UART_3, CYHAL_PIN_OUT_FUNCTION(P6_2_SCB3_UART_RTS)}, - {P6_6, UART_6, CYHAL_PIN_OUT_FUNCTION(P6_6_SCB6_UART_RTS)}, - {P7_2, UART_4, CYHAL_PIN_OUT_FUNCTION(P7_2_SCB4_UART_RTS)}, - {P8_2, UART_4, CYHAL_PIN_OUT_FUNCTION(P8_2_SCB4_UART_RTS)}, - {P9_2, UART_2, CYHAL_PIN_OUT_FUNCTION(P9_2_SCB2_UART_RTS)}, - {P10_2, UART_1, CYHAL_PIN_OUT_FUNCTION(P10_2_SCB1_UART_RTS)}, - {P11_2, UART_5, CYHAL_PIN_OUT_FUNCTION(P11_2_SCB5_UART_RTS)}, - {P12_2, UART_6, CYHAL_PIN_OUT_FUNCTION(P12_2_SCB6_UART_RTS)}, - {NC, NC, 0} -}; -const PinMap PinMap_UART_CTS[] = { - {P0_5, UART_0, CYHAL_PIN_IN_FUNCTION(P0_5_SCB0_UART_CTS)}, - {P1_3, UART_7, CYHAL_PIN_IN_FUNCTION(P1_3_SCB7_UART_CTS)}, - {P2_3, UART_1, CYHAL_PIN_IN_FUNCTION(P2_3_SCB1_UART_CTS)}, - {P3_3, UART_2, CYHAL_PIN_IN_FUNCTION(P3_3_SCB2_UART_CTS)}, - {P5_3, UART_5, CYHAL_PIN_IN_FUNCTION(P5_3_SCB5_UART_CTS)}, - {P6_3, UART_3, CYHAL_PIN_IN_FUNCTION(P6_3_SCB3_UART_CTS)}, - {P6_7, UART_6, CYHAL_PIN_IN_FUNCTION(P6_7_SCB6_UART_CTS)}, - {P7_3, UART_4, CYHAL_PIN_IN_FUNCTION(P7_3_SCB4_UART_CTS)}, - {P8_3, UART_4, CYHAL_PIN_IN_FUNCTION(P8_3_SCB4_UART_CTS)}, - {P9_3, UART_2, CYHAL_PIN_IN_FUNCTION(P9_3_SCB2_UART_CTS)}, - {P10_3, UART_1, CYHAL_PIN_IN_FUNCTION(P10_3_SCB1_UART_CTS)}, - {P11_3, UART_5, CYHAL_PIN_IN_FUNCTION(P11_3_SCB5_UART_CTS)}, - {P12_3, UART_6, CYHAL_PIN_IN_FUNCTION(P12_3_SCB6_UART_CTS)}, - {NC, NC, 0} -}; -#endif // DEVICE_SERIAL - - -#if DEVICE_I2C -//*** I2C *** -const PinMap PinMap_I2C_SCL[] = { - {P0_2, I2C_0, CYHAL_PIN_OD_FUNCTION(P0_2_SCB0_I2C_SCL)}, - {P1_0, I2C_7, CYHAL_PIN_OD_FUNCTION(P1_0_SCB7_I2C_SCL)}, - {P2_0, I2C_1, CYHAL_PIN_OD_FUNCTION(P2_0_SCB1_I2C_SCL)}, - {P3_0, I2C_2, CYHAL_PIN_OD_FUNCTION(P3_0_SCB2_I2C_SCL)}, - {P4_0, I2C_7, CYHAL_PIN_OD_FUNCTION(P4_0_SCB7_I2C_SCL)}, - {P5_0, I2C_5, CYHAL_PIN_OD_FUNCTION(P5_0_SCB5_I2C_SCL)}, - {P6_0, I2C_3, CYHAL_PIN_OD_FUNCTION(P6_0_SCB3_I2C_SCL)}, - {P6_0, I2C_8, CYHAL_PIN_OD_FUNCTION(P6_0_SCB8_I2C_SCL)}, - {P6_4, I2C_6, CYHAL_PIN_OD_FUNCTION(P6_4_SCB6_I2C_SCL)}, - {P6_4, I2C_8, CYHAL_PIN_OD_FUNCTION(P6_4_SCB8_I2C_SCL)}, - {P7_0, I2C_4, CYHAL_PIN_OD_FUNCTION(P7_0_SCB4_I2C_SCL)}, - {P8_0, I2C_4, CYHAL_PIN_OD_FUNCTION(P8_0_SCB4_I2C_SCL)}, - {P9_0, I2C_2, CYHAL_PIN_OD_FUNCTION(P9_0_SCB2_I2C_SCL)}, - {P10_0, I2C_1, CYHAL_PIN_OD_FUNCTION(P10_0_SCB1_I2C_SCL)}, - {P11_0, I2C_5, CYHAL_PIN_OD_FUNCTION(P11_0_SCB5_I2C_SCL)}, - {P12_0, I2C_6, CYHAL_PIN_OD_FUNCTION(P12_0_SCB6_I2C_SCL)}, - {P13_0, I2C_6, CYHAL_PIN_OD_FUNCTION(P13_0_SCB6_I2C_SCL)}, - {NC, NC, 0} -}; -const PinMap PinMap_I2C_SDA[] = { - {P0_3, I2C_0, CYHAL_PIN_OD_FUNCTION(P0_3_SCB0_I2C_SDA)}, - {P1_1, I2C_7, CYHAL_PIN_OD_FUNCTION(P1_1_SCB7_I2C_SDA)}, - {P2_1, I2C_1, CYHAL_PIN_OD_FUNCTION(P2_1_SCB1_I2C_SDA)}, - {P3_1, I2C_2, CYHAL_PIN_OD_FUNCTION(P3_1_SCB2_I2C_SDA)}, - {P4_1, I2C_7, CYHAL_PIN_OD_FUNCTION(P4_1_SCB7_I2C_SDA)}, - {P5_1, I2C_5, CYHAL_PIN_OD_FUNCTION(P5_1_SCB5_I2C_SDA)}, - {P6_1, I2C_3, CYHAL_PIN_OD_FUNCTION(P6_1_SCB3_I2C_SDA)}, - {P6_1, I2C_8, CYHAL_PIN_OD_FUNCTION(P6_1_SCB8_I2C_SDA)}, - {P6_5, I2C_6, CYHAL_PIN_OD_FUNCTION(P6_5_SCB6_I2C_SDA)}, - {P6_5, I2C_8, CYHAL_PIN_OD_FUNCTION(P6_5_SCB8_I2C_SDA)}, - {P7_1, I2C_4, CYHAL_PIN_OD_FUNCTION(P7_1_SCB4_I2C_SDA)}, - {P8_1, I2C_4, CYHAL_PIN_OD_FUNCTION(P8_1_SCB4_I2C_SDA)}, - {P9_1, I2C_2, CYHAL_PIN_OD_FUNCTION(P9_1_SCB2_I2C_SDA)}, - {P10_1, I2C_1, CYHAL_PIN_OD_FUNCTION(P10_1_SCB1_I2C_SDA)}, - {P11_1, I2C_5, CYHAL_PIN_OD_FUNCTION(P11_1_SCB5_I2C_SDA)}, - {P12_1, I2C_6, CYHAL_PIN_OD_FUNCTION(P12_1_SCB6_I2C_SDA)}, - {P13_1, I2C_6, CYHAL_PIN_OD_FUNCTION(P13_1_SCB6_I2C_SDA)}, - {NC, NC, 0} -}; -#endif // DEVICE_I2C - -#if DEVICE_SPI -//*** SPI *** -const PinMap PinMap_SPI_MOSI[] = { - {P0_2, SPI_0, CYHAL_PIN_OUT_FUNCTION(P0_2_SCB0_SPI_MOSI)}, - {P1_0, SPI_7, CYHAL_PIN_OUT_FUNCTION(P1_0_SCB7_SPI_MOSI)}, - {P2_0, SPI_1, CYHAL_PIN_OUT_FUNCTION(P2_0_SCB1_SPI_MOSI)}, - {P3_0, SPI_2, CYHAL_PIN_OUT_FUNCTION(P3_0_SCB2_SPI_MOSI)}, - {P4_0, SPI_7, CYHAL_PIN_OUT_FUNCTION(P4_0_SCB7_SPI_MOSI)}, - {P5_0, SPI_5, CYHAL_PIN_OUT_FUNCTION(P5_0_SCB5_SPI_MOSI)}, - {P6_0, SPI_3, CYHAL_PIN_OUT_FUNCTION(P6_0_SCB3_SPI_MOSI)}, - {P6_0, SPI_8, CYHAL_PIN_OUT_FUNCTION(P6_0_SCB8_SPI_MOSI)}, - {P6_4, SPI_6, CYHAL_PIN_OUT_FUNCTION(P6_4_SCB6_SPI_MOSI)}, - {P6_4, SPI_8, CYHAL_PIN_OUT_FUNCTION(P6_4_SCB8_SPI_MOSI)}, - {P7_0, SPI_4, CYHAL_PIN_OUT_FUNCTION(P7_0_SCB4_SPI_MOSI)}, - {P8_0, SPI_4, CYHAL_PIN_OUT_FUNCTION(P8_0_SCB4_SPI_MOSI)}, - {P9_0, SPI_2, CYHAL_PIN_OUT_FUNCTION(P9_0_SCB2_SPI_MOSI)}, - {P10_0, SPI_1, CYHAL_PIN_OUT_FUNCTION(P10_0_SCB1_SPI_MOSI)}, - {P11_0, SPI_5, CYHAL_PIN_OUT_FUNCTION(P11_0_SCB5_SPI_MOSI)}, - {P12_0, SPI_6, CYHAL_PIN_OUT_FUNCTION(P12_0_SCB6_SPI_MOSI)}, - {P13_0, SPI_6, CYHAL_PIN_OUT_FUNCTION(P13_0_SCB6_SPI_MOSI)}, - {NC, NC, 0} -}; -const PinMap PinMap_SPI_MISO[] = { - {P0_3, SPI_0, CYHAL_PIN_IN_FUNCTION(P0_3_SCB0_SPI_MISO)}, - {P1_1, SPI_7, CYHAL_PIN_IN_FUNCTION(P1_1_SCB7_SPI_MISO)}, - {P2_1, SPI_1, CYHAL_PIN_IN_FUNCTION(P2_1_SCB1_SPI_MISO)}, - {P3_1, SPI_2, CYHAL_PIN_IN_FUNCTION(P3_1_SCB2_SPI_MISO)}, - {P4_1, SPI_7, CYHAL_PIN_IN_FUNCTION(P4_1_SCB7_SPI_MISO)}, - {P5_1, SPI_5, CYHAL_PIN_IN_FUNCTION(P5_1_SCB5_SPI_MISO)}, - {P6_1, SPI_3, CYHAL_PIN_IN_FUNCTION(P6_1_SCB3_SPI_MISO)}, - {P6_1, SPI_8, CYHAL_PIN_IN_FUNCTION(P6_1_SCB8_SPI_MISO)}, - {P6_5, SPI_6, CYHAL_PIN_IN_FUNCTION(P6_5_SCB6_SPI_MISO)}, - {P6_5, SPI_8, CYHAL_PIN_IN_FUNCTION(P6_5_SCB8_SPI_MISO)}, - {P7_1, SPI_4, CYHAL_PIN_IN_FUNCTION(P7_1_SCB4_SPI_MISO)}, - {P8_1, SPI_4, CYHAL_PIN_IN_FUNCTION(P8_1_SCB4_SPI_MISO)}, - {P9_1, SPI_2, CYHAL_PIN_IN_FUNCTION(P9_1_SCB2_SPI_MISO)}, - {P10_1, SPI_1, CYHAL_PIN_IN_FUNCTION(P10_1_SCB1_SPI_MISO)}, - {P11_1, SPI_5, CYHAL_PIN_IN_FUNCTION(P11_1_SCB5_SPI_MISO)}, - {P12_1, SPI_6, CYHAL_PIN_IN_FUNCTION(P12_1_SCB6_SPI_MISO)}, - {P13_1, SPI_6, CYHAL_PIN_IN_FUNCTION(P13_1_SCB6_SPI_MISO)}, - {NC, NC, 0} -}; -const PinMap PinMap_SPI_SCLK[] = { - {P0_4, SPI_0, CYHAL_PIN_OUT_FUNCTION(P0_4_SCB0_SPI_CLK)}, - {P1_2, SPI_7, CYHAL_PIN_OUT_FUNCTION(P1_2_SCB7_SPI_CLK)}, - {P2_2, SPI_1, CYHAL_PIN_OUT_FUNCTION(P2_2_SCB1_SPI_CLK)}, - {P3_2, SPI_2, CYHAL_PIN_OUT_FUNCTION(P3_2_SCB2_SPI_CLK)}, - {P5_2, SPI_5, CYHAL_PIN_OUT_FUNCTION(P5_2_SCB5_SPI_CLK)}, - {P6_2, SPI_3, CYHAL_PIN_OUT_FUNCTION(P6_2_SCB3_SPI_CLK)}, - {P6_2, SPI_8, CYHAL_PIN_OUT_FUNCTION(P6_2_SCB8_SPI_CLK)}, - {P6_6, SPI_6, CYHAL_PIN_OUT_FUNCTION(P6_6_SCB6_SPI_CLK)}, - {P6_6, SPI_8, CYHAL_PIN_OUT_FUNCTION(P6_6_SCB8_SPI_CLK)}, - {P7_2, SPI_4, CYHAL_PIN_OUT_FUNCTION(P7_2_SCB4_SPI_CLK)}, - {P8_2, SPI_4, CYHAL_PIN_OUT_FUNCTION(P8_2_SCB4_SPI_CLK)}, - {P9_2, SPI_2, CYHAL_PIN_OUT_FUNCTION(P9_2_SCB2_SPI_CLK)}, - {P10_2, SPI_1, CYHAL_PIN_OUT_FUNCTION(P10_2_SCB1_SPI_CLK)}, - {P11_2, SPI_5, CYHAL_PIN_OUT_FUNCTION(P11_2_SCB5_SPI_CLK)}, - {P12_2, SPI_6, CYHAL_PIN_OUT_FUNCTION(P12_2_SCB6_SPI_CLK)}, - {NC, NC, 0} -}; -const PinMap PinMap_SPI_SSEL[] = { - {P0_5, SPI_0, CYHAL_PIN_OUT_FUNCTION(P0_5_SCB0_SPI_SELECT0)}, - {P1_3, SPI_7, CYHAL_PIN_OUT_FUNCTION(P1_3_SCB7_SPI_SELECT0)}, - {P2_3, SPI_1, CYHAL_PIN_OUT_FUNCTION(P2_3_SCB1_SPI_SELECT0)}, - {P3_3, SPI_2, CYHAL_PIN_OUT_FUNCTION(P3_3_SCB2_SPI_SELECT0)}, - {P5_3, SPI_5, CYHAL_PIN_OUT_FUNCTION(P5_3_SCB5_SPI_SELECT0)}, - {P6_3, SPI_3, CYHAL_PIN_OUT_FUNCTION(P6_3_SCB3_SPI_SELECT0)}, - {P6_3, SPI_8, CYHAL_PIN_OUT_FUNCTION(P6_3_SCB8_SPI_SELECT0)}, - {P6_7, SPI_6, CYHAL_PIN_OUT_FUNCTION(P6_7_SCB6_SPI_SELECT0)}, - {P6_7, SPI_8, CYHAL_PIN_OUT_FUNCTION(P6_7_SCB8_SPI_SELECT0)}, - {P7_3, SPI_4, CYHAL_PIN_OUT_FUNCTION(P7_3_SCB4_SPI_SELECT0)}, - {P8_3, SPI_4, CYHAL_PIN_OUT_FUNCTION(P8_3_SCB4_SPI_SELECT0)}, - {P9_3, SPI_2, CYHAL_PIN_OUT_FUNCTION(P9_3_SCB2_SPI_SELECT0)}, - {P10_3, SPI_1, CYHAL_PIN_OUT_FUNCTION(P10_3_SCB1_SPI_SELECT0)}, - {P11_3, SPI_5, CYHAL_PIN_OUT_FUNCTION(P11_3_SCB5_SPI_SELECT0)}, - {P12_3, SPI_6, CYHAL_PIN_OUT_FUNCTION(P12_3_SCB6_SPI_SELECT0)}, - {NC, NC, 0} -}; -#endif // DEVICE_SPI - -#if DEVICE_PWMOUT -//*** PWM *** -const PinMap PinMap_PWM_OUT[] = { - // 16-bit PWM outputs - {P0_0, PWM_16b_0, CYHAL_PIN_OUT_FUNCTION(P0_0_TCPWM1_LINE0)}, - {P0_2, PWM_16b_1, CYHAL_PIN_OUT_FUNCTION(P0_2_TCPWM1_LINE1)}, - {P0_4, PWM_16b_2, CYHAL_PIN_OUT_FUNCTION(P0_4_TCPWM1_LINE2)}, - {P1_0, PWM_16b_3, CYHAL_PIN_OUT_FUNCTION(P1_0_TCPWM1_LINE3)}, - {P1_2, PWM_16b_12, CYHAL_PIN_OUT_FUNCTION(P1_2_TCPWM1_LINE12)}, - {P1_4, PWM_16b_13, CYHAL_PIN_OUT_FUNCTION(P1_4_TCPWM1_LINE13)}, - {P2_0, PWM_16b_15, CYHAL_PIN_OUT_FUNCTION(P2_0_TCPWM1_LINE15)}, - {P2_2, PWM_16b_16, CYHAL_PIN_OUT_FUNCTION(P2_2_TCPWM1_LINE16)}, - {P2_4, PWM_16b_17, CYHAL_PIN_OUT_FUNCTION(P2_4_TCPWM1_LINE17)}, - {P2_6, PWM_16b_18, CYHAL_PIN_OUT_FUNCTION(P2_6_TCPWM1_LINE18)}, - {P3_0, PWM_16b_19, CYHAL_PIN_OUT_FUNCTION(P3_0_TCPWM1_LINE19)}, - {P3_2, PWM_16b_20, CYHAL_PIN_OUT_FUNCTION(P3_2_TCPWM1_LINE20)}, - {P3_4, PWM_16b_21, CYHAL_PIN_OUT_FUNCTION(P3_4_TCPWM1_LINE21)}, - {P4_0, PWM_16b_22, CYHAL_PIN_OUT_FUNCTION(P4_0_TCPWM1_LINE22)}, - {P5_0, PWM_16b_4, CYHAL_PIN_OUT_FUNCTION(P5_0_TCPWM1_LINE4)}, - {P5_2, PWM_16b_5, CYHAL_PIN_OUT_FUNCTION(P5_2_TCPWM1_LINE5)}, - {P5_4, PWM_16b_6, CYHAL_PIN_OUT_FUNCTION(P5_4_TCPWM1_LINE6)}, - {P5_6, PWM_16b_7, CYHAL_PIN_OUT_FUNCTION(P5_6_TCPWM1_LINE7)}, - {P6_0, PWM_16b_8, CYHAL_PIN_OUT_FUNCTION(P6_0_TCPWM1_LINE8)}, - {P6_2, PWM_16b_9, CYHAL_PIN_OUT_FUNCTION(P6_2_TCPWM1_LINE9)}, - {P6_4, PWM_16b_10, CYHAL_PIN_OUT_FUNCTION(P6_4_TCPWM1_LINE10)}, - {P6_6, PWM_16b_11, CYHAL_PIN_OUT_FUNCTION(P6_6_TCPWM1_LINE11)}, - {P7_0, PWM_16b_12, CYHAL_PIN_OUT_FUNCTION(P7_0_TCPWM1_LINE12)}, - {P7_2, PWM_16b_13, CYHAL_PIN_OUT_FUNCTION(P7_2_TCPWM1_LINE13)}, - {P7_4, PWM_16b_14, CYHAL_PIN_OUT_FUNCTION(P7_4_TCPWM1_LINE14)}, - {P7_6, PWM_16b_15, CYHAL_PIN_OUT_FUNCTION(P7_6_TCPWM1_LINE15)}, - {P8_0, PWM_16b_16, CYHAL_PIN_OUT_FUNCTION(P8_0_TCPWM1_LINE16)}, - {P8_2, PWM_16b_17, CYHAL_PIN_OUT_FUNCTION(P8_2_TCPWM1_LINE17)}, - {P8_4, PWM_16b_18, CYHAL_PIN_OUT_FUNCTION(P8_4_TCPWM1_LINE18)}, - {P8_6, PWM_16b_19, CYHAL_PIN_OUT_FUNCTION(P8_6_TCPWM1_LINE19)}, - {P9_0, PWM_16b_20, CYHAL_PIN_OUT_FUNCTION(P9_0_TCPWM1_LINE20)}, - {P9_2, PWM_16b_21, CYHAL_PIN_OUT_FUNCTION(P9_2_TCPWM1_LINE21)}, - {P9_4, PWM_16b_0, CYHAL_PIN_OUT_FUNCTION(P9_4_TCPWM1_LINE0)}, - {P9_6, PWM_16b_1, CYHAL_PIN_OUT_FUNCTION(P9_6_TCPWM1_LINE1)}, - {P10_0, PWM_16b_22, CYHAL_PIN_OUT_FUNCTION(P10_0_TCPWM1_LINE22)}, - {P10_2, PWM_16b_23, CYHAL_PIN_OUT_FUNCTION(P10_2_TCPWM1_LINE23)}, - {P10_4, PWM_16b_0, CYHAL_PIN_OUT_FUNCTION(P10_4_TCPWM1_LINE0)}, - {P10_6, PWM_16b_2, CYHAL_PIN_OUT_FUNCTION(P10_6_TCPWM1_LINE2)}, - {P11_0, PWM_16b_1, CYHAL_PIN_OUT_FUNCTION(P11_0_TCPWM1_LINE1)}, - {P11_2, PWM_16b_2, CYHAL_PIN_OUT_FUNCTION(P11_2_TCPWM1_LINE2)}, - {P11_4, PWM_16b_3, CYHAL_PIN_OUT_FUNCTION(P11_4_TCPWM1_LINE3)}, - {P12_0, PWM_16b_4, CYHAL_PIN_OUT_FUNCTION(P12_0_TCPWM1_LINE4)}, - {P12_2, PWM_16b_5, CYHAL_PIN_OUT_FUNCTION(P12_2_TCPWM1_LINE5)}, - {P12_4, PWM_16b_6, CYHAL_PIN_OUT_FUNCTION(P12_4_TCPWM1_LINE6)}, - {P12_6, PWM_16b_7, CYHAL_PIN_OUT_FUNCTION(P12_6_TCPWM1_LINE7)}, - {P13_0, PWM_16b_8, CYHAL_PIN_OUT_FUNCTION(P13_0_TCPWM1_LINE8)}, - {P13_2, PWM_16b_9, CYHAL_PIN_OUT_FUNCTION(P13_2_TCPWM1_LINE9)}, - {P13_4, PWM_16b_10, CYHAL_PIN_OUT_FUNCTION(P13_4_TCPWM1_LINE10)}, - {P13_6, PWM_16b_11, CYHAL_PIN_OUT_FUNCTION(P13_6_TCPWM1_LINE11)}, - // 16-bit PWM inverted outputs - {P0_1, PWM_16b_0, CYHAL_PIN_OUT_FUNCTION(P0_1_TCPWM1_LINE_COMPL0)}, - {P0_3, PWM_16b_1, CYHAL_PIN_OUT_FUNCTION(P0_3_TCPWM1_LINE_COMPL1)}, - {P0_5, PWM_16b_2, CYHAL_PIN_OUT_FUNCTION(P0_5_TCPWM1_LINE_COMPL2)}, - {P1_1, PWM_16b_3, CYHAL_PIN_OUT_FUNCTION(P1_1_TCPWM1_LINE_COMPL3)}, - {P1_3, PWM_16b_12, CYHAL_PIN_OUT_FUNCTION(P1_3_TCPWM1_LINE_COMPL12)}, - {P1_5, PWM_16b_14, CYHAL_PIN_OUT_FUNCTION(P1_5_TCPWM1_LINE_COMPL14)}, - {P2_1, PWM_16b_15, CYHAL_PIN_OUT_FUNCTION(P2_1_TCPWM1_LINE_COMPL15)}, - {P2_3, PWM_16b_16, CYHAL_PIN_OUT_FUNCTION(P2_3_TCPWM1_LINE_COMPL16)}, - {P2_5, PWM_16b_17, CYHAL_PIN_OUT_FUNCTION(P2_5_TCPWM1_LINE_COMPL17)}, - {P2_7, PWM_16b_18, CYHAL_PIN_OUT_FUNCTION(P2_7_TCPWM1_LINE_COMPL18)}, - {P3_1, PWM_16b_19, CYHAL_PIN_OUT_FUNCTION(P3_1_TCPWM1_LINE_COMPL19)}, - {P3_3, PWM_16b_20, CYHAL_PIN_OUT_FUNCTION(P3_3_TCPWM1_LINE_COMPL20)}, - {P3_5, PWM_16b_21, CYHAL_PIN_OUT_FUNCTION(P3_5_TCPWM1_LINE_COMPL21)}, - {P4_1, PWM_16b_22, CYHAL_PIN_OUT_FUNCTION(P4_1_TCPWM1_LINE_COMPL22)}, - {P5_1, PWM_16b_4, CYHAL_PIN_OUT_FUNCTION(P5_1_TCPWM1_LINE_COMPL4)}, - {P5_3, PWM_16b_5, CYHAL_PIN_OUT_FUNCTION(P5_3_TCPWM1_LINE_COMPL5)}, - {P5_5, PWM_16b_6, CYHAL_PIN_OUT_FUNCTION(P5_5_TCPWM1_LINE_COMPL6)}, - {P5_7, PWM_16b_7, CYHAL_PIN_OUT_FUNCTION(P5_7_TCPWM1_LINE_COMPL7)}, - {P6_1, PWM_16b_8, CYHAL_PIN_OUT_FUNCTION(P6_1_TCPWM1_LINE_COMPL8)}, - {P6_3, PWM_16b_9, CYHAL_PIN_OUT_FUNCTION(P6_3_TCPWM1_LINE_COMPL9)}, - {P6_5, PWM_16b_10, CYHAL_PIN_OUT_FUNCTION(P6_5_TCPWM1_LINE_COMPL10)}, - {P6_7, PWM_16b_11, CYHAL_PIN_OUT_FUNCTION(P6_7_TCPWM1_LINE_COMPL11)}, - {P7_1, PWM_16b_12, CYHAL_PIN_OUT_FUNCTION(P7_1_TCPWM1_LINE_COMPL12)}, - {P7_3, PWM_16b_13, CYHAL_PIN_OUT_FUNCTION(P7_3_TCPWM1_LINE_COMPL13)}, - {P7_5, PWM_16b_14, CYHAL_PIN_OUT_FUNCTION(P7_5_TCPWM1_LINE_COMPL14)}, - {P7_7, PWM_16b_15, CYHAL_PIN_OUT_FUNCTION(P7_7_TCPWM1_LINE_COMPL15)}, - {P8_1, PWM_16b_16, CYHAL_PIN_OUT_FUNCTION(P8_1_TCPWM1_LINE_COMPL16)}, - {P8_3, PWM_16b_17, CYHAL_PIN_OUT_FUNCTION(P8_3_TCPWM1_LINE_COMPL17)}, - {P8_5, PWM_16b_18, CYHAL_PIN_OUT_FUNCTION(P8_5_TCPWM1_LINE_COMPL18)}, - {P8_7, PWM_16b_19, CYHAL_PIN_OUT_FUNCTION(P8_7_TCPWM1_LINE_COMPL19)}, - {P9_1, PWM_16b_20, CYHAL_PIN_OUT_FUNCTION(P9_1_TCPWM1_LINE_COMPL20)}, - {P9_3, PWM_16b_21, CYHAL_PIN_OUT_FUNCTION(P9_3_TCPWM1_LINE_COMPL21)}, - {P9_5, PWM_16b_0, CYHAL_PIN_OUT_FUNCTION(P9_5_TCPWM1_LINE_COMPL0)}, - {P9_7, PWM_16b_1, CYHAL_PIN_OUT_FUNCTION(P9_7_TCPWM1_LINE_COMPL1)}, - {P10_1, PWM_16b_22, CYHAL_PIN_OUT_FUNCTION(P10_1_TCPWM1_LINE_COMPL22)}, - {P10_3, PWM_16b_23, CYHAL_PIN_OUT_FUNCTION(P10_3_TCPWM1_LINE_COMPL23)}, - {P10_5, PWM_16b_0, CYHAL_PIN_OUT_FUNCTION(P10_5_TCPWM1_LINE_COMPL0)}, - {P10_7, PWM_16b_2, CYHAL_PIN_OUT_FUNCTION(P10_7_TCPWM1_LINE_COMPL2)}, - {P11_1, PWM_16b_1, CYHAL_PIN_OUT_FUNCTION(P11_1_TCPWM1_LINE_COMPL1)}, - {P11_3, PWM_16b_2, CYHAL_PIN_OUT_FUNCTION(P11_3_TCPWM1_LINE_COMPL2)}, - {P11_5, PWM_16b_3, CYHAL_PIN_OUT_FUNCTION(P11_5_TCPWM1_LINE_COMPL3)}, - {P12_1, PWM_16b_4, CYHAL_PIN_OUT_FUNCTION(P12_1_TCPWM1_LINE_COMPL4)}, - {P12_3, PWM_16b_5, CYHAL_PIN_OUT_FUNCTION(P12_3_TCPWM1_LINE_COMPL5)}, - {P12_5, PWM_16b_6, CYHAL_PIN_OUT_FUNCTION(P12_5_TCPWM1_LINE_COMPL6)}, - {P12_7, PWM_16b_7, CYHAL_PIN_OUT_FUNCTION(P12_7_TCPWM1_LINE_COMPL7)}, - {P13_1, PWM_16b_8, CYHAL_PIN_OUT_FUNCTION(P13_1_TCPWM1_LINE_COMPL8)}, - {P13_3, PWM_16b_9, CYHAL_PIN_OUT_FUNCTION(P13_3_TCPWM1_LINE_COMPL9)}, - {P13_5, PWM_16b_10, CYHAL_PIN_OUT_FUNCTION(P13_5_TCPWM1_LINE_COMPL10)}, - {P13_7, PWM_16b_11, CYHAL_PIN_OUT_FUNCTION(P13_7_TCPWM1_LINE_COMPL11)}, - // 32-bit PWM outputs - {P0_0, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P0_0_TCPWM0_LINE0)}, - {P0_2, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P0_2_TCPWM0_LINE1)}, - {P0_4, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P0_4_TCPWM0_LINE2)}, - {P1_0, PWM_32b_3, CYHAL_PIN_OUT_FUNCTION(P1_0_TCPWM0_LINE3)}, - {P1_2, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P1_2_TCPWM0_LINE4)}, - {P1_4, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P1_4_TCPWM0_LINE5)}, - {P2_0, PWM_32b_6, CYHAL_PIN_OUT_FUNCTION(P2_0_TCPWM0_LINE6)}, - {P2_2, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P2_2_TCPWM0_LINE7)}, - {P2_4, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P2_4_TCPWM0_LINE0)}, - {P2_6, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P2_6_TCPWM0_LINE1)}, - {P3_0, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P3_0_TCPWM0_LINE2)}, - {P3_2, PWM_32b_3, CYHAL_PIN_OUT_FUNCTION(P3_2_TCPWM0_LINE3)}, - {P3_4, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P3_4_TCPWM0_LINE4)}, - {P4_0, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P4_0_TCPWM0_LINE5)}, - {P5_0, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P5_0_TCPWM0_LINE4)}, - {P5_2, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P5_2_TCPWM0_LINE5)}, - {P5_4, PWM_32b_6, CYHAL_PIN_OUT_FUNCTION(P5_4_TCPWM0_LINE6)}, - {P5_6, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P5_6_TCPWM0_LINE7)}, - {P6_0, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P6_0_TCPWM0_LINE0)}, - {P6_2, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P6_2_TCPWM0_LINE1)}, - {P6_4, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P6_4_TCPWM0_LINE2)}, - {P6_6, PWM_32b_3, CYHAL_PIN_OUT_FUNCTION(P6_6_TCPWM0_LINE3)}, - {P7_0, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P7_0_TCPWM0_LINE4)}, - {P7_2, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P7_2_TCPWM0_LINE5)}, - {P7_4, PWM_32b_6, CYHAL_PIN_OUT_FUNCTION(P7_4_TCPWM0_LINE6)}, - {P7_6, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P7_6_TCPWM0_LINE7)}, - {P8_0, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P8_0_TCPWM0_LINE0)}, - {P8_2, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P8_2_TCPWM0_LINE1)}, - {P8_4, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P8_4_TCPWM0_LINE2)}, - {P8_6, PWM_32b_3, CYHAL_PIN_OUT_FUNCTION(P8_6_TCPWM0_LINE3)}, - {P9_0, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P9_0_TCPWM0_LINE4)}, - {P9_2, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P9_2_TCPWM0_LINE5)}, - {P9_4, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P9_4_TCPWM0_LINE7)}, - {P9_6, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P9_6_TCPWM0_LINE0)}, - {P10_0, PWM_32b_6, CYHAL_PIN_OUT_FUNCTION(P10_0_TCPWM0_LINE6)}, - {P10_2, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P10_2_TCPWM0_LINE7)}, - {P10_4, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P10_4_TCPWM0_LINE0)}, - {P10_6, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P10_6_TCPWM0_LINE1)}, - {P11_0, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P11_0_TCPWM0_LINE1)}, - {P11_2, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P11_2_TCPWM0_LINE2)}, - {P11_4, PWM_32b_3, CYHAL_PIN_OUT_FUNCTION(P11_4_TCPWM0_LINE3)}, - {P12_0, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P12_0_TCPWM0_LINE4)}, - {P12_2, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P12_2_TCPWM0_LINE5)}, - {P12_4, PWM_32b_6, CYHAL_PIN_OUT_FUNCTION(P12_4_TCPWM0_LINE6)}, - {P12_6, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P12_6_TCPWM0_LINE7)}, - {P13_0, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P13_0_TCPWM0_LINE0)}, - {P13_2, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P13_2_TCPWM0_LINE1)}, - {P13_4, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P13_4_TCPWM0_LINE2)}, - {P13_6, PWM_32b_3, CYHAL_PIN_OUT_FUNCTION(P13_6_TCPWM0_LINE3)}, - // 32-bit PWM inverted outputs - {P0_1, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P0_1_TCPWM0_LINE_COMPL0)}, - {P0_3, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P0_3_TCPWM0_LINE_COMPL1)}, - {P0_5, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P0_5_TCPWM0_LINE_COMPL2)}, - {P1_1, PWM_32b_3, CYHAL_PIN_OUT_FUNCTION(P1_1_TCPWM0_LINE_COMPL3)}, - {P1_3, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P1_3_TCPWM0_LINE_COMPL4)}, - {P1_5, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P1_5_TCPWM0_LINE_COMPL5)}, - {P2_1, PWM_32b_6, CYHAL_PIN_OUT_FUNCTION(P2_1_TCPWM0_LINE_COMPL6)}, - {P2_3, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P2_3_TCPWM0_LINE_COMPL7)}, - {P2_5, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P2_5_TCPWM0_LINE_COMPL0)}, - {P2_7, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P2_7_TCPWM0_LINE_COMPL1)}, - {P3_1, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P3_1_TCPWM0_LINE_COMPL2)}, - {P3_3, PWM_32b_3, CYHAL_PIN_OUT_FUNCTION(P3_3_TCPWM0_LINE_COMPL3)}, - {P3_5, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P3_5_TCPWM0_LINE_COMPL4)}, - {P4_1, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P4_1_TCPWM0_LINE_COMPL5)}, - {P5_1, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P5_1_TCPWM0_LINE_COMPL4)}, - {P5_3, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P5_3_TCPWM0_LINE_COMPL5)}, - {P5_5, PWM_32b_6, CYHAL_PIN_OUT_FUNCTION(P5_5_TCPWM0_LINE_COMPL6)}, - {P5_7, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P5_7_TCPWM0_LINE_COMPL7)}, - {P6_1, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P6_1_TCPWM0_LINE_COMPL0)}, - {P6_3, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P6_3_TCPWM0_LINE_COMPL1)}, - {P6_5, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P6_5_TCPWM0_LINE_COMPL2)}, - {P6_7, PWM_32b_3, CYHAL_PIN_OUT_FUNCTION(P6_7_TCPWM0_LINE_COMPL3)}, - {P7_1, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P7_1_TCPWM0_LINE_COMPL4)}, - {P7_3, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P7_3_TCPWM0_LINE_COMPL5)}, - {P7_5, PWM_32b_6, CYHAL_PIN_OUT_FUNCTION(P7_5_TCPWM0_LINE_COMPL6)}, - {P7_7, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P7_7_TCPWM0_LINE_COMPL7)}, - {P8_1, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P8_1_TCPWM0_LINE_COMPL0)}, - {P8_3, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P8_3_TCPWM0_LINE_COMPL1)}, - {P8_5, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P8_5_TCPWM0_LINE_COMPL2)}, - {P8_7, PWM_32b_3, CYHAL_PIN_OUT_FUNCTION(P8_7_TCPWM0_LINE_COMPL3)}, - {P9_1, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P9_1_TCPWM0_LINE_COMPL4)}, - {P9_3, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P9_3_TCPWM0_LINE_COMPL5)}, - {P9_5, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P9_5_TCPWM0_LINE_COMPL7)}, - {P9_7, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P9_7_TCPWM0_LINE_COMPL0)}, - {P10_1, PWM_32b_6, CYHAL_PIN_OUT_FUNCTION(P10_1_TCPWM0_LINE_COMPL6)}, - {P10_3, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P10_3_TCPWM0_LINE_COMPL7)}, - {P10_5, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P10_5_TCPWM0_LINE_COMPL0)}, - {P10_7, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P10_7_TCPWM0_LINE_COMPL1)}, - {P11_1, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P11_1_TCPWM0_LINE_COMPL1)}, - {P11_3, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P11_3_TCPWM0_LINE_COMPL2)}, - {P11_5, PWM_32b_3, CYHAL_PIN_OUT_FUNCTION(P11_5_TCPWM0_LINE_COMPL3)}, - {P12_1, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P12_1_TCPWM0_LINE_COMPL4)}, - {P12_3, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P12_3_TCPWM0_LINE_COMPL5)}, - {P12_5, PWM_32b_6, CYHAL_PIN_OUT_FUNCTION(P12_5_TCPWM0_LINE_COMPL6)}, - {P12_7, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P12_7_TCPWM0_LINE_COMPL7)}, - {P13_1, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P13_1_TCPWM0_LINE_COMPL0)}, - {P13_3, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P13_3_TCPWM0_LINE_COMPL1)}, - {P13_5, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P13_5_TCPWM0_LINE_COMPL2)}, - {P13_7, PWM_32b_3, CYHAL_PIN_OUT_FUNCTION(P13_7_TCPWM0_LINE_COMPL3)}, - {NC, NC, 0} -}; -#endif // DEVICE_PWMOUT - -#if DEVICE_ANALOGIN -const PinMap PinMap_ADC[] = { - {P10_0, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, - {P10_1, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, - {P10_2, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, - {P10_3, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, - {P10_4, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, - {P10_5, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, - {P10_6, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, - {P10_7, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, - {NC, NC, 0} -}; -#endif // DEVICE_ANALOGIN - -#if DEVICE_QSPI -const PinMap PinMap_QSPI_SCLK[] = { - {P11_7, QSPI_0, CY_GPIO_CFG_CREATE(P11_7_SMIF_SPI_CLK, CY_GPIO_DM_STRONG_IN_OFF)}, - {NC, NC, 0}, -}; -const PinMap PinMap_QSPI_SSEL[] = { - {P11_2, QSPI_0, CY_GPIO_CFG_CREATE(P11_2_SMIF_SPI_SELECT0, CY_GPIO_DM_STRONG_IN_OFF)}, - {NC, NC, 0}, -}; -const PinMap PinMap_QSPI_DATA0[] = { - {P11_6, QSPI_0, CY_GPIO_CFG_CREATE(P11_6_SMIF_SPI_DATA0, CY_GPIO_DM_STRONG)}, - {NC, NC, 0}, -}; -const PinMap PinMap_QSPI_DATA1[] = { - {P11_5, QSPI_0, CY_GPIO_CFG_CREATE(P11_5_SMIF_SPI_DATA1, CY_GPIO_DM_STRONG)}, - {NC, NC, 0}, -}; -const PinMap PinMap_QSPI_DATA2[] = { - {P11_4, QSPI_0, CY_GPIO_CFG_CREATE(P11_4_SMIF_SPI_DATA2, CY_GPIO_DM_STRONG)}, - {NC, NC, 0}, -}; -const PinMap PinMap_QSPI_DATA3[] = { - {P11_3, QSPI_0, CY_GPIO_CFG_CREATE(P11_3_SMIF_SPI_DATA3, CY_GPIO_DM_STRONG)}, - {NC, NC, 0}, -}; -#endif // DEVICE_QSPI diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/cybsp.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/cybsp.c deleted file mode 100644 index 851e751b7a..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/cybsp.c +++ /dev/null @@ -1,128 +0,0 @@ -/***************************************************************************//** -* \file cybsp.c -* -* Description: -* Provides initialization code for starting up the hardware contained on the -* Cypress board. -* -******************************************************************************** -* \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ - -#include -#include "cy_syspm.h" -#include "cy_sysclk.h" -#include "cybsp.h" -#if defined(CY_USING_HAL) -#include "cyhal_hwmgr.h" -#endif - -#if defined(__cplusplus) -extern "C" { -#endif - -/* The sysclk deep sleep callback is recommended to be the last callback that -* is executed before entry into deep sleep mode and the first one upon -* exit the deep sleep mode. -* Doing so minimizes the time spent on low power mode entry and exit. -*/ -#ifndef CYBSP_SYSCLK_PM_CALLBACK_ORDER - #define CYBSP_SYSCLK_PM_CALLBACK_ORDER (255u) -#endif - -#if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL) -static cyhal_sdio_t sdio_obj; - -cyhal_sdio_t* cybsp_get_wifi_sdio_obj(void) -{ - return &sdio_obj; -} -#endif - -/** - * Registers a power management callback that prepares the clock system - * for entering deep sleep mode and restore the clocks upon wakeup from deep sleep. - * NOTE: This is called automatically as part of \ref cybsp_init - */ -static cy_rslt_t cybsp_register_sysclk_pm_callback(void) -{ - cy_rslt_t result = CY_RSLT_SUCCESS; - static cy_stc_syspm_callback_params_t cybsp_sysclk_pm_callback_param = {NULL, NULL}; - static cy_stc_syspm_callback_t cybsp_sysclk_pm_callback = { - .callback = &Cy_SysClk_DeepSleepCallback, - .type = CY_SYSPM_DEEPSLEEP, - .callbackParams = &cybsp_sysclk_pm_callback_param, - .order = CYBSP_SYSCLK_PM_CALLBACK_ORDER - }; - - if (!Cy_SysPm_RegisterCallback(&cybsp_sysclk_pm_callback)) - { - result = CYBSP_RSLT_ERR_SYSCLK_PM_CALLBACK; - } - return result; -} - -cy_rslt_t cybsp_init(void) -{ - /* Setup hardware manager to track resource usage then initialize all system (clock/power) board configuration */ -#if defined(CY_USING_HAL) - cy_rslt_t result = cyhal_hwmgr_init(); -#else - cy_rslt_t result = CY_RSLT_SUCCESS; -#endif - -#if defined(COMPONENT_BSP_DESIGN_MODUS) || defined(COMPONENT_CUSTOM_DESIGN_MODUS) - init_cycfg_all(); -#endif - - if (CY_RSLT_SUCCESS == result) - { - result = cybsp_register_sysclk_pm_callback(); - } - -#if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL) - /* Initialize SDIO interface. This must be done before other HAL API calls as some SDIO implementations require - * specific peripheral instances. - * NOTE: The full WiFi interface still needs to be initialized via cybsp_wifi_init_primary(). This is typically - * done when starting up WiFi. - */ - if (CY_RSLT_SUCCESS == result) - { - /* Reserves: CYBSP_WIFI_SDIO, CYBSP_WIFI_SDIO_D0, CYBSP_WIFI_SDIO_D1, CYBSP_WIFI_SDIO_D2, CYBSP_WIFI_SDIO_D3 - * CYBSP_WIFI_SDIO_CMD and CYBSP_WIFI_SDIO_CLK. - */ - result = cyhal_sdio_init( - &sdio_obj, - CYBSP_WIFI_SDIO_CMD, - CYBSP_WIFI_SDIO_CLK, - CYBSP_WIFI_SDIO_D0, - CYBSP_WIFI_SDIO_D1, - CYBSP_WIFI_SDIO_D2, - CYBSP_WIFI_SDIO_D3); - } -#endif /* defined(CYBSP_WIFI_CAPABLE) */ - - /* CYHAL_HWMGR_RSLT_ERR_INUSE error code could be returned if any needed for BSP resource was reserved by - * user previously. Please review the Device Configurator (design.modus) and the BSP reservation list - * (cyreservedresources.list) to make sure no resources are reserved by both. - */ - return result; -} - -#if defined(__cplusplus) -} -#endif diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/cybsp.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/cybsp.h deleted file mode 100644 index bb83a6b9a8..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/cybsp.h +++ /dev/null @@ -1,76 +0,0 @@ -/***************************************************************************//** -* \file cybsp.h -* -* \brief -* Basic API for setting up boards containing a Cypress MCU. -* -******************************************************************************** -* \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ - -#pragma once - -#include "cy_result.h" -#include "cybsp_types.h" -#if defined(COMPONENT_BSP_DESIGN_MODUS) || defined(COMPONENT_CUSTOM_DESIGN_MODUS) -#include "cycfg.h" -#endif -#if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL) -#include "cyhal_sdio.h" -#endif - -#if defined(__cplusplus) -extern "C" { -#endif - -/** -* \addtogroup group_bsp_macros Macros -* \{ -*/ - -/** Failed to configure sysclk power management callback */ -#define CYBSP_RSLT_ERR_SYSCLK_PM_CALLBACK (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_BSP, 0)) - -/** \} group_bsp_macros */ - -/** -* \addtogroup group_bsp_functions Functions -* \{ -*/ - -/** - * \brief Initialize all hardware on the board - * \returns CY_RSLT_SUCCESS if the board is sucessfully initialized, if there is - * a problem initializing any hardware it returns an error code specific - * to the hardware module that had a problem. - */ -cy_rslt_t cybsp_init(void); - -#if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL) -/** - * \brief Get the initialized sdio object used for communicating with the WiFi Chip. - * \note This function should only be called after cybsp_init(); - * \returns The initialized sdio object. - */ -cyhal_sdio_t* cybsp_get_wifi_sdio_obj(void); -#endif /* defined(CYBSP_WIFI_CAPABLE) */ - -/** \} group_bsp_functions */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/cybsp_types.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/cybsp_types.h deleted file mode 100644 index 275a61dcb1..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/cybsp_types.h +++ /dev/null @@ -1,323 +0,0 @@ -/***************************************************************************//** -* \file CY8CKIT-064S2-4343W/cybsp_types.h -* -* Description: -* Provides APIs for interacting with the hardware contained on the Cypress -* CY8CKIT-064S2-4343W pioneer kit. -* -******************************************************************************** -* \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ - -#pragma once - -#if defined(CY_USING_HAL) -#include "cyhal_pin_package.h" -#endif - -#if defined(__cplusplus) -extern "C" { -#endif - -/** -* \addtogroup group_bsp_settings BSP Settings -* \{ -* -*
Peripheral Default HAL Settings:
-* | Resource | Parameter | Value | Remarks | -* | :------: | :-------: | :---: | :------ | -* | ADC | VREF | 1.2 V | | -* | ^ | Measurement type | Single Ended | | -* | ^ | Input voltage range | 0 to 2.4 V (0 to 2*VREF) | | -* | ^ | Output range | 0x000 to 0x7FF | | -* | DAC | Reference source | VDDA | | -* | ^ | Input range | 0x000 to 0xFFF | | -* | ^ | Output range | 0 to VDDA | | -* | ^ | Output type | Unbuffered output | | -* | I2C | Role | Master | Configurable to slave mode through HAL function | -* | ^ | Data rate | 100 kbps | Configurable through HAL function | -* | ^ | Drive mode of SCL & SDA pins | Open Drain (drives low) | External pull-up resistors are required | -* | LpTimer | Uses WCO (32.768 kHz) as clock source & MCWDT as counter. 1 count = 1/32768 second or 32768 counts = 1 second. ||| -* | SPI | Data rate | 100 kpbs | Configurable through HAL function | -* | ^ | Slave select polarity | Active low | | -* | UART | Flow control | No flow control | Configurable through HAL function | -* | ^ | Data format | 8N1 | Configurable through HAL function | -* | ^ | Baud rate | 115200 | Configurable through HAL function | -*/ -/** \} group_bsp_settings */ - -/** -* \addtogroup group_bsp_pin_state Pin States -* \{ -*/ - -/** Pin state for the LED on. */ -#define CYBSP_LED_STATE_ON (0U) -/** Pin state for the LED off. */ -#define CYBSP_LED_STATE_OFF (1U) - -/** Pin state for when a button is pressed. */ -#define CYBSP_BTN_PRESSED (0U) -/** Pin state for when a button is released. */ -#define CYBSP_BTN_OFF (1U) - -/** \} group_bsp_pin_state */ - -#if defined(CY_USING_HAL) - -/** -* \addtogroup group_bsp_pins Pin Mappings -* \{ -*/ - -/** -* \addtogroup group_bsp_pins_led LED Pins -* \{ -*/ - -/** LED 8; User LED1 */ -#define CYBSP_LED8 (P1_5) -/** LED 9; User LED2 */ -#define CYBSP_LED9 (P11_1) -/** LED 5: RGB LED - Red; User LED3 */ -#define CYBSP_LED_RGB_RED (P1_1) -/** LED 5: RGB LED - Green; User LED4 */ -#define CYBSP_LED_RGB_GREEN (P0_5) -/** LED 5: RGB LED - Blue; User LED5 */ -#define CYBSP_LED_RGB_BLUE (P7_3) - -/** LED 8; User LED1 */ -#define CYBSP_USER_LED1 (CYBSP_LED8) -/** LED 9; User LED2 */ -#define CYBSP_USER_LED2 (CYBSP_LED9) -/** LED 5: RGB LED - Red; User LED3 */ -#define CYBSP_USER_LED3 (CYBSP_LED_RGB_RED) -/** LED 5: RGB LED - Green; User LED4 */ -#define CYBSP_USER_LED4 (CYBSP_LED_RGB_GREEN) -/** LED 5: RGB LED - Blue; User LED5 */ -#define CYBSP_USER_LED5 (CYBSP_LED_RGB_BLUE) -/** LED 8; User LED1 */ -#define CYBSP_USER_LED (CYBSP_USER_LED1) - -/** \} group_bsp_pins_led */ - - -/** -* \addtogroup group_bsp_pins_btn Button Pins -* \{ -*/ - -/** Switch 2; User Button 1 */ -#define CYBSP_SW2 (P0_4) - -/** Switch 2; User Button 1 */ -#define CYBSP_USER_BTN1 (CYBSP_SW2) -/** Switch 2; User Button 1 */ -#define CYBSP_USER_BTN (CYBSP_USER_BTN1) - -/** \} group_bsp_pins_btn */ - - -/** -* \addtogroup group_bsp_pins_comm Communication Pins -* \{ -*/ - -/** Pin: WIFI SDIO D0 */ -#define CYBSP_WIFI_SDIO_D0 (P2_0) -/** Pin: WIFI SDIO D1 */ -#define CYBSP_WIFI_SDIO_D1 (P2_1) -/** Pin: WIFI SDIO D2 */ -#define CYBSP_WIFI_SDIO_D2 (P2_2) -/** Pin: WIFI SDIO D3 */ -#define CYBSP_WIFI_SDIO_D3 (P2_3) -/** Pin: WIFI SDIO CMD */ -#define CYBSP_WIFI_SDIO_CMD (P2_4) -/** Pin: WIFI SDIO CLK */ -#define CYBSP_WIFI_SDIO_CLK (P2_5) -/** Pin: WIFI ON */ -#define CYBSP_WIFI_WL_REG_ON (P2_6) -/** Pin: WIFI Host Wakeup */ -#define CYBSP_WIFI_HOST_WAKE (P4_1) - -/** Pin: BT UART RX */ -#define CYBSP_BT_UART_RX (P3_0) -/** Pin: BT UART TX */ -#define CYBSP_BT_UART_TX (P3_1) -/** Pin: BT UART RTS */ -#define CYBSP_BT_UART_RTS (P3_2) -/** Pin: BT UART CTS */ -#define CYBSP_BT_UART_CTS (P3_3) - -/** Pin: BT Power */ -#define CYBSP_BT_POWER (P3_4) -/** Pin: BT Host Wakeup */ -#define CYBSP_BT_HOST_WAKE (P4_0) -/** Pin: BT Device Wakeup */ -#define CYBSP_BT_DEVICE_WAKE (P3_5) - -/** Pin: UART RX */ -#define CYBSP_DEBUG_UART_RX (P5_0) -/** Pin: UART TX */ -#define CYBSP_DEBUG_UART_TX (P5_1) -/** Pin: UART RX */ -#define CYBSP_DEBUG_UART_RTS (P5_2) -/** Pin: UART TX */ -#define CYBSP_DEBUG_UART_CTS (P5_3) - -/** Pin: I2C SCL */ -#define CYBSP_I2C_SCL (P6_0) -/** Pin: I2C SDA */ -#define CYBSP_I2C_SDA (P6_1) - -/** Pin: SWO */ -#define CYBSP_SWO (P6_4) -/** Pin: SWDIO */ -#define CYBSP_SWDIO (P6_6) -/** Pin: SWDCK */ -#define CYBSP_SWDCK (P6_7) - -/** Pin: QUAD SPI SS */ -#define CYBSP_QSPI_SS (P11_2) -/** Pin: QUAD SPI D3 */ -#define CYBSP_QSPI_D3 (P11_3) -/** Pin: QUAD SPI D2 */ -#define CYBSP_QSPI_D2 (P11_4) -/** Pin: QUAD SPI D1 */ -#define CYBSP_QSPI_D1 (P11_5) -/** Pin: QUAD SPI D0 */ -#define CYBSP_QSPI_D0 (P11_6) -/** Pin: QUAD SPI SCK */ -#define CYBSP_QSPI_SCK (P11_7) - -/** Pin: SPI MOSI */ -#define CYBSP_SPI_MOSI (P12_0) -/** Pin: SPI MISO */ -#define CYBSP_SPI_MISO (P12_1) -/** Pin: SPI CLK */ -#define CYBSP_SPI_CLK (P12_2) -/** Pin: SPI CS */ -#define CYBSP_SPI_CS (P12_4) - -/** Host-wake GPIO drive mode */ -#define CYBSP_WIFI_HOST_WAKE_GPIO_DM (CYHAL_GPIO_DRIVE_ANALOG) -/** Host-wake IRQ event */ -#define CYBSP_WIFI_HOST_WAKE_IRQ_EVENT (CYHAL_GPIO_IRQ_RISE) - -/** \} group_bsp_pins_comm */ - - -/** -* \addtogroup group_bsp_pins_arduino Arduino Header Pins -* \{ -*/ - -/** Arduino A0 */ -#define CYBSP_A0 P10_0 -/** Arduino A1 */ -#define CYBSP_A1 P10_1 -/** Arduino A2 */ -#define CYBSP_A2 P10_2 -/** Arduino A3 */ -#define CYBSP_A3 P10_3 -/** Arduino A4 */ -#define CYBSP_A4 P10_4 -/** Arduino A5 */ -#define CYBSP_A5 P10_5 -/** Arduino D0 */ -#define CYBSP_D0 (P5_0) -/** Arduino D1 */ -#define CYBSP_D1 (P5_1) -/** Arduino D2 */ -#define CYBSP_D2 (P5_2) -/** Arduino D3 */ -#define CYBSP_D3 (P5_3) -/** Arduino D4 */ -#define CYBSP_D4 (P5_4) -/** Arduino D5 */ -#define CYBSP_D5 (P5_5) -/** Arduino D6 */ -#define CYBSP_D6 (P5_6) -/** Arduino D7 */ -#define CYBSP_D7 (P5_7) -/** Arduino D8 */ -#define CYBSP_D8 (P7_5) -/** Arduino D9 */ -#define CYBSP_D9 (P7_6) -/** Arduino D10 */ -#define CYBSP_D10 (P12_3) -/** Arduino D11 */ -#define CYBSP_D11 (P12_0) -/** Arduino D12 */ -#define CYBSP_D12 (P12_1) -/** Arduino D13 */ -#define CYBSP_D13 (P12_2) -/** Arduino D14 */ -#define CYBSP_D14 (P6_1) -/** Arduino D15 */ -#define CYBSP_D15 (P6_0) - -/** \} group_bsp_pins_arduino */ - - -/** -* \addtogroup group_bsp_pins_j2 J2 Header Pins -* \{ -*/ - -/** Cypress J2 Header pin 1 */ -#define CYBSP_J2_1 (CYBSP_A0) -/** Cypress J2 Header pin 2 */ -#define CYBSP_J2_2 (P9_0) -/** Cypress J2 Header pin 3 */ -#define CYBSP_J2_3 (CYBSP_A1) -/** Cypress J2 Header pin 4 */ -#define CYBSP_J2_4 (P9_1) -/** Cypress J2 Header pin 5 */ -#define CYBSP_J2_5 (CYBSP_A2) -/** Cypress J2 Header pin 6 */ -#define CYBSP_J2_6 (P9_2) -/** Cypress J2 Header pin 7 */ -#define CYBSP_J2_7 (CYBSP_A3) -/** Cypress J2 Header pin 8 */ -#define CYBSP_J2_8 (P9_3) -/** Cypress J2 Header pin 9 */ -#define CYBSP_J2_9 (CYBSP_A4) -/** Cypress J2 Header pin 10 */ -#define CYBSP_J2_10 (P9_4) -/** Cypress J2 Header pin 11 */ -#define CYBSP_J2_11 (CYBSP_A5) -/** Cypress J2 Header pin 12 */ -#define CYBSP_J2_12 (P9_5) -/** Cypress J2 Header pin 13 */ -#define CYBSP_J2_13 (P10_6) -/** Cypress J2 Header pin 14 */ -#define CYBSP_J2_14 (P9_6) -/** Cypress J2 Header pin 15 */ -#define CYBSP_J2_15 (P10_7) -/** Cypress J2 Header pin 16 */ -#define CYBSP_J2_16 (P9_7) - -/** \} group_bsp_pins_j2 */ - -/** \} group_bsp_pins */ - -#endif /* defined(CY_USING_HAL) */ - -#if defined(__cplusplus) -} -#endif diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xxa_cm0plus.sct b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xxa_cm0plus.sct deleted file mode 100644 index b451f65c85..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xxa_cm0plus.sct +++ /dev/null @@ -1,307 +0,0 @@ -#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0 -; The first line specifies a preprocessor command that the linker invokes -; to pass a scatter file through a C preprocessor. - -;******************************************************************************* -;* \file cyb06xxa_cm0plus.sct -;* \version 2.70 -;* -;* Linker file for the ARMCC. -;* -;* The main purpose of the linker script is to describe how the sections in the -;* input files should be mapped into the output file, and to control the memory -;* layout of the output file. -;* -;* \note The entry point location is fixed and starts at 0x10000000. The valid -;* application image should be placed there. -;* -;* \note The linker files included with the PDL template projects must be -;* generic and handle all common use cases. Your project may not use every -;* section defined in the linker files. In that case you may see the warnings -;* during the build process: L6314W (no section matches pattern) and/or L6329W -;* (pattern only matches removed unused sections). In your project, you can -;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to -;* the linker, simply comment out or remove the relevant code in the linker -;* file. -;* -;******************************************************************************* -;* \copyright -;* Copyright 2016-2019 Cypress Semiconductor Corporation -;* SPDX-License-Identifier: Apache-2.0 -;* -;* Licensed under the Apache License, Version 2.0 (the "License"); -;* you may not use this file except in compliance with the License. -;* You may obtain a copy of the License at -;* -;* http://www.apache.org/licenses/LICENSE-2.0 -;* -;* Unless required by applicable law or agreed to in writing, software -;* distributed under the License is distributed on an "AS IS" BASIS, -;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -;* See the License for the specific language governing permissions and -;* limitations under the License. -;******************************************************************************/ - -#if !defined(MBED_ROM_START) - #define MBED_ROM_START 0x10000000 -#endif - -;* MBED_APP_START is being used by the bootloader build script and -;* will be calculate by the system. Without bootloader the MBED_APP_START -;* is equal to MBED_ROM_START -;* -#if !defined(MBED_APP_START) - #define MBED_APP_START MBED_ROM_START -#endif - -#if !defined(MBED_ROM_SIZE) - #define MBED_ROM_SIZE 0x80000 -#endif - -;* MBED_APP_SIZE is being used by the bootloader build script and -;* will be calculate by the system. Without bootloader the MBED_APP_SIZE -;* is equal to MBED_ROM_SIZE -;* -#if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE MBED_ROM_SIZE -#endif - -#if !defined(MBED_RAM_START) - #define MBED_RAM_START 0x08000000 -#endif - -#if !defined(MBED_RAM_SIZE) - #define MBED_RAM_SIZE 0x00010000 -#endif - -#if !defined(MBED_PUBLIC_RAM_SIZE) - #define MBED_PUBLIC_RAM_SIZE 0x200 -#endif - -; The size of the stack section at the end of CM0+ SRAM -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -#define STACK_SIZE MBED_BOOT_STACK_SIZE - -#if !defined(MBED_PUBLIC_RAM_START) - #define MBED_PUBLIC_RAM_START (MBED_RAM_START + MBED_RAM_SIZE - STACK_SIZE - MBED_PUBLIC_RAM_SIZE) -#endif - -; The defines below describe the location and size of blocks of memory in the target. -; Use these defines to specify the memory regions available for allocation. - -; The following defines control RAM and flash memory allocation for the CM0+ core. -; You can change the memory allocation by editing the RAM and Flash defines. -; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat', -; where 'xx' is the device group; for example, 'cyb06xx7_cm4_dual.scat'. -; RAM -#define RAM_START MBED_RAM_START -#define RAM_SIZE MBED_RAM_SIZE -; Public RAM -#define PUBLIC_RAM_START MBED_PUBLIC_RAM_START -#define PUBLIC_RAM_SIZE MBED_PUBLIC_RAM_SIZE -; Flash -#define FLASH_START MBED_APP_START -#define FLASH_SIZE MBED_APP_SIZE - -; The size of the MCU boot header area at the start of FLASH -#define BOOT_HEADER_SIZE 0x00000400 - -; The following defines describe a 32K flash region used for EEPROM emulation. -; This region can also be used as the general purpose flash. -; You can assign sections to this memory region for only one of the cores. -; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. -; Therefore, repurposing this memory region will prevent such middleware from operation. -#define EM_EEPROM_START 0x14000000 -#define EM_EEPROM_SIZE 0x8000 - -; The following defines describe device specific memory regions and must not be changed. -; Supervisory flash: User data -#define SFLASH_USER_DATA_START 0x16000800 -#define SFLASH_USER_DATA_SIZE 0x00000800 - -; Supervisory flash: Normal Access Restrictions (NAR) -#define SFLASH_NAR_START 0x16001A00 -#define SFLASH_NAR_SIZE 0x00000200 - -; Supervisory flash: Public Key -#define SFLASH_PUBLIC_KEY_START 0x16005A00 -#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 - -; Supervisory flash: Table of Content # 2 -#define SFLASH_TOC_2_START 0x16007C00 -#define SFLASH_TOC_2_SIZE 0x00000200 - -; Supervisory flash: Table of Content # 2 Copy -#define SFLASH_RTOC_2_START 0x16007E00 -#define SFLASH_RTOC_2_SIZE 0x00000200 - -; External memory -#define XIP_START 0x18000000 -#define XIP_SIZE 0x08000000 - -; eFuse -#define EFUSE_START 0x90700000 -#define EFUSE_SIZE 0x100000 - - -; Cortex-M0+ application flash area -LR_IROM1 (FLASH_START + BOOT_HEADER_SIZE) (FLASH_SIZE - BOOT_HEADER_SIZE - 0x8000) -{ - ER_FLASH_VECTORS +0 - { - * (RESET, +FIRST) - } - - ER_FLASH_CODE +0 FIXED - { - * (InRoot$$Sections) - * (+RO) - } - - ER_RAM_VECTORS RAM_START UNINIT - { - * (RESET_RAM, +FIRST) - } - - RW_RAM_DATA +0 - { - * (.cy_ramfunc) - * (+RW, +ZI) - } - - ; Place variables in the section that should not be initialized during the - ; device startup. - RW_IRAM1 +0 UNINIT - { - * (.noinit) - } - - RW_IRAM2 PUBLIC_RAM_START UNINIT - { - * (.cy_sharedmem) - } - - ; Application heap area (HEAP) - ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM2) - { - } - - ; Stack region growing down - ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE - { - } -} - - -; Emulated EEPROM Flash area -LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE -{ - .cy_em_eeprom +0 - { - * (.cy_em_eeprom) - } -} - -; Supervisory flash: User data -LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE -{ - .cy_sflash_user_data +0 - { - * (.cy_sflash_user_data) - } -} - -; Supervisory flash: Normal Access Restrictions (NAR) -LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE -{ - .cy_sflash_nar +0 - { - * (.cy_sflash_nar) - } -} - -; Supervisory flash: Public Key -LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE -{ - .cy_sflash_public_key +0 - { - * (.cy_sflash_public_key) - } -} - -; Supervisory flash: Table of Content # 2 -LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE -{ - .cy_toc_part2 +0 - { - * (.cy_toc_part2) - } -} - -; Supervisory flash: Table of Content # 2 Copy -LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE -{ - .cy_rtoc_part2 +0 - { - * (.cy_rtoc_part2) - } -} - - -; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. -LR_EROM XIP_START XIP_SIZE -{ - .cy_xip +0 - { - * (.cy_xip) - } -} - - -; eFuse -LR_EFUSE EFUSE_START EFUSE_SIZE -{ - .cy_efuse +0 - { - * (.cy_efuse) - } -} - - -; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. -CYMETA 0x90500000 -{ - .cymeta +0 { * (.cymeta) } -} - -/* The following symbols used by the cymcuelftool. */ -/* Flash */ -#define __cy_memory_0_start 0x10000000 -#define __cy_memory_0_length 0x001D0000 -#define __cy_memory_0_row_size 0x200 - -/* Emulated EEPROM Flash area */ -#define __cy_memory_1_start 0x14000000 -#define __cy_memory_1_length 0x8000 -#define __cy_memory_1_row_size 0x200 - -/* Supervisory Flash */ -#define __cy_memory_2_start 0x16000000 -#define __cy_memory_2_length 0x8000 -#define __cy_memory_2_row_size 0x200 - -/* XIP */ -#define __cy_memory_3_start 0x18000000 -#define __cy_memory_3_length 0x08000000 -#define __cy_memory_3_row_size 0x200 - -/* eFuse */ -#define __cy_memory_4_start 0x90700000 -#define __cy_memory_4_length 0x100000 -#define __cy_memory_4_row_size 1 - - -/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cyb06xxa_cm0plus.ld b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cyb06xxa_cm0plus.ld deleted file mode 100644 index 15f6a886e2..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cyb06xxa_cm0plus.ld +++ /dev/null @@ -1,471 +0,0 @@ -/***************************************************************************//** -* \file cyb06xxa_cm0plus.ld -* \version 2.70 -* -* Linker file for the GNU C compiler. -* -* The main purpose of the linker script is to describe how the sections in the -* input files should be mapped into the output file, and to control the memory -* layout of the output file. -* -* \note The entry point location is fixed and starts at 0x10000000. The valid -* application image should be placed there. -* -* \note The linker files included with the PDL template projects must be generic -* and handle all common use cases. Your project may not use every section -* defined in the linker files. In that case you may see warnings during the -* build process. In your project, you can simply comment out or remove the -* relevant code in the linker file. -* -******************************************************************************** -* \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ - -OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") -SEARCH_DIR(.) -GROUP(-lgcc -lc -lnosys) -ENTRY(Reset_Handler) - -#if !defined(MBED_ROM_START) - #define MBED_ROM_START 0x10000000 -#endif - -/* MBED_APP_START is being used by the bootloader build script and -* will be calculate by the system. Without bootloader the MBED_APP_START -* is equal to MBED_ROM_START -*/ -#if !defined(MBED_APP_START) - #define MBED_APP_START MBED_ROM_START -#endif - -#if !defined(MBED_ROM_SIZE) - #define MBED_ROM_SIZE 0x80000 -#endif - -/* MBED_APP_SIZE is being used by the bootloader build script and -* will be calculate by the system. Without bootloader the MBED_APP_SIZE -* is equal to MBED_ROM_SIZE -*/ -#if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE MBED_ROM_SIZE -#endif - -#if !defined(MBED_RAM_START) - #define MBED_RAM_START 0x08000000 -#endif - -#if !defined(MBED_RAM_SIZE) - #define MBED_RAM_SIZE 0x00010000 -#endif - -#if !defined(MBED_PUBLIC_RAM_SIZE) - #define MBED_PUBLIC_RAM_SIZE 0x200 -#endif - -/* The size of the stack section at the end of CM0+ SRAM */ -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -STACK_SIZE = MBED_BOOT_STACK_SIZE; - -#if !defined(MBED_PUBLIC_RAM_START) - #define MBED_PUBLIC_RAM_START (MBED_RAM_START + MBED_RAM_SIZE - STACK_SIZE - MBED_PUBLIC_RAM_SIZE) -#endif - -/* The size of the MCU boot header area at the start of FLASH */ -BOOT_HEADER_SIZE = 0x400; - -/* Force symbol to be entered in the output file as an undefined symbol. Doing -* this may, for example, trigger linking of additional modules from standard -* libraries. You may list several symbols for each EXTERN, and you may use -* EXTERN multiple times. This command has the same effect as the -u command-line -* option. -*/ -EXTERN(Reset_Handler) - -/* The MEMORY section below describes the location and size of blocks of memory in the target. -* Use this section to specify the memory regions available for allocation. -*/ -MEMORY -{ - /* The ram and flash regions control RAM and flash memory allocation for the CM0+ core. - * You can change the memory allocation by editing the 'ram' and 'flash' regions. - * Your changes must be aligned with the corresponding memory regions for the CM4 core in 'xx_cm4_dual.ld', - * where 'xx' is the device group; for example, 'cyb06xx7_cm4_dual.ld'. - */ - ram (rwx) : ORIGIN = MBED_RAM_START, LENGTH = MBED_RAM_SIZE - public_ram (rw) : ORIGIN = MBED_PUBLIC_RAM_START, LENGTH = MBED_PUBLIC_RAM_SIZE - flash (rx) : ORIGIN = MBED_APP_START, LENGTH = (MBED_APP_SIZE - 0x8000) - - /* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash. - * You can assign sections to this memory region for only one of the cores. - * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. - * Therefore, repurposing this memory region will prevent such middleware from operation. - */ - em_eeprom (rx) : ORIGIN = 0x14000000, LENGTH = 0x8000 /* 32 KB */ - - /* The following regions define device specific memory regions and must not be changed. */ - sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 /* Supervisory flash: User data */ - sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 /* Supervisory flash: Normal Access Restrictions (NAR) */ - sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 /* Supervisory flash: Public Key */ - sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 */ - sflash_rtoc_2 (rx) : ORIGIN = 0x16007E00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 Copy */ - xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */ - efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */ -} - -/* Library configurations */ -GROUP(libgcc.a libc.a libm.a libnosys.a) - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __Vectors_End - * __Vectors_Size - */ - - -SECTIONS -{ - .cy_app_header : - { - KEEP(*(.cy_app_header)) - } > flash - - /* Cortex-M0+ application flash area */ - .text ORIGIN(flash) + BOOT_HEADER_SIZE : - { - . = ALIGN(4); - __Vectors = . ; - KEEP(*(.vectors)) - . = ALIGN(4); - __Vectors_End = .; - __Vectors_Size = __Vectors_End - __Vectors; - __end__ = .; - - . = ALIGN(4); - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - /* Read-only code (constants). */ - *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*) - - KEEP(*(.eh_frame*)) - } > flash - - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > flash - - __exidx_start = .; - - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > flash - __exidx_end = .; - - - /* To copy multiple ROM to RAM sections, - * uncomment .copy.table section and, - * define __STARTUP_COPY_MULTIPLE in startup_psoc6_02_cm0plus.S */ - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - - /* Copy interrupt vectors from flash to RAM */ - LONG (__Vectors) /* From */ - LONG (__ram_vectors_start__) /* To */ - LONG (__Vectors_End - __Vectors) /* Size */ - - /* Copy data section to RAM */ - LONG (__etext) /* From */ - LONG (__data_start__) /* To */ - LONG (__data_end__ - __data_start__) /* Size */ - - __copy_table_end__ = .; - } > flash - - - /* To clear multiple BSS sections, - * uncomment .zero.table section and, - * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_02_cm0plus.S */ - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - LONG (__bss_start__) - LONG (__bss_end__ - __bss_start__) - __zero_table_end__ = .; - } > flash - - __etext = . ; - - - .ramVectors (NOLOAD) : ALIGN(8) - { - __ram_vectors_start__ = .; - KEEP(*(.ram_vectors)) - __ram_vectors_end__ = .; - } > ram - - - .data __ram_vectors_end__ : AT (__etext) - { - __data_start__ = .; - - *(vtable) - *(.data*) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(4); - - KEEP(*(.cy_ramfunc*)) - . = ALIGN(4); - - __data_end__ = .; - - } > ram - - - /* Place variables in the section that should not be initialized during the - * device startup. - */ - .noinit (NOLOAD) : ALIGN(8) - { - KEEP(*(.noinit)) - } > ram - - - /* The uninitialized global or static variables are placed in this section. - * - * The NOLOAD attribute tells linker that .bss section does not consume - * any space in the image. The NOLOAD attribute changes the .bss type to - * NOBITS, and that makes linker to A) not allocate section in memory, and - * A) put information to clear the section with all zeros during application - * loading. - * - * Without the NOLOAD attribute, the .bss section might get PROGBITS type. - * This makes linker to A) allocate zeroed section in memory, and B) copy - * this section to RAM during application loading. - */ - .bss (NOLOAD): - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > ram - - - .heap (NOLOAD): - { - __HeapBase = .; - __end__ = .; - end = __end__; - KEEP(*(.heap*)) - . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE; - __HeapLimit = .; - } > ram - - - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ - .stack_dummy (NOLOAD): - { - KEEP(*(.stack*)) - } > ram - - - /* Public RAM */ - .cy_sharedmem (NOLOAD): - { - . = ALIGN(4); - KEEP(*(.cy_sharedmem)) - } > public_ram - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(ram) + LENGTH(ram); - __StackLimit = __StackTop - STACK_SIZE; - PROVIDE(__stack = __StackTop); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") - - - /* Emulated EEPROM Flash area */ - .cy_em_eeprom : - { - KEEP(*(.cy_em_eeprom)) - } > em_eeprom - - - /* Supervisory Flash: User data */ - .cy_sflash_user_data : - { - KEEP(*(.cy_sflash_user_data)) - } > sflash_user_data - - - /* Supervisory Flash: Normal Access Restrictions (NAR) */ - .cy_sflash_nar : - { - KEEP(*(.cy_sflash_nar)) - } > sflash_nar - - - /* Supervisory Flash: Public Key */ - .cy_sflash_public_key : - { - KEEP(*(.cy_sflash_public_key)) - } > sflash_public_key - - - /* Supervisory Flash: Table of Content # 2 */ - .cy_toc_part2 : - { - KEEP(*(.cy_toc_part2)) - } > sflash_toc_2 - - - /* Supervisory Flash: Table of Content # 2 Copy */ - .cy_rtoc_part2 : - { - KEEP(*(.cy_rtoc_part2)) - } > sflash_rtoc_2 - - - /* Places the code in the Execute in Place (XIP) section. See the smif driver - * documentation for details. - */ - .cy_xip : - { - KEEP(*(.cy_xip)) - } > xip - - - /* eFuse */ - .cy_efuse : - { - KEEP(*(.cy_efuse)) - } > efuse - - - /* These sections are used for additional metadata (silicon revision, - * Silicon/JTAG ID, etc.) storage. - */ - .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE -} - - -/* The following symbols used by the cymcuelftool. */ -/* Flash */ -__cy_memory_0_start = 0x10000000; -__cy_memory_0_length = 0x001D0000; -__cy_memory_0_row_size = 0x200; - -/* Emulated EEPROM Flash area */ -__cy_memory_1_start = 0x14000000; -__cy_memory_1_length = 0x8000; -__cy_memory_1_row_size = 0x200; - -/* Supervisory Flash */ -__cy_memory_2_start = 0x16000000; -__cy_memory_2_length = 0x8000; -__cy_memory_2_row_size = 0x200; - -/* XIP */ -__cy_memory_3_start = 0x18000000; -__cy_memory_3_length = 0x08000000; -__cy_memory_3_row_size = 0x200; - -/* eFuse */ -__cy_memory_4_start = 0x90700000; -__cy_memory_4_length = 0x100000; -__cy_memory_4_row_size = 1; - -/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm0plus.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm0plus.S deleted file mode 100644 index 3fed47b01f..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm0plus.S +++ /dev/null @@ -1,367 +0,0 @@ -/**************************************************************************//** - * @file startup_psoc6_02_cm0plus.S - * @brief CMSIS Core Device Startup File for - * ARMCM0plus Device Series - * @version V5.00 - * @date 02. March 2016 - ******************************************************************************/ -/* - * Copyright (c) 2009-2016 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - - /* Address of the NMI handler */ - #define CY_NMI_HANLDER_ADDR 0x0000000D - - /* The CPU VTOR register */ - #define CY_CPU_VTOR_ADDR 0xE000ED08 - - /* Copy flash vectors and data section to RAM */ - #define __STARTUP_COPY_MULTIPLE - - /* Clear single BSS section */ - #define __STARTUP_CLEAR_BSS - - .syntax unified - .arch armv6-m - - .section .stack - .align 3 -#ifdef __STACK_SIZE - .equ Stack_Size, __STACK_SIZE -#else - .equ Stack_Size, 0x00001000 -#endif - .globl __StackTop - .globl __StackLimit -__StackLimit: - .space Stack_Size - .size __StackLimit, . - __StackLimit -__StackTop: - .size __StackTop, . - __StackTop - - .section .heap - .align 3 -#ifdef __HEAP_SIZE - .equ Heap_Size, __HEAP_SIZE -#else - .equ Heap_Size, 0x00000400 -#endif - .globl __HeapBase - .globl __HeapLimit -__HeapBase: - .if Heap_Size - .space Heap_Size - .endif - .size __HeapBase, . - __HeapBase -__HeapLimit: - .size __HeapLimit, . - __HeapLimit - - .section .vectors - .align 2 - .globl __Vectors -__Vectors: - .long __StackTop /* Top of Stack */ - .long Reset_Handler /* Reset Handler */ - .long CY_NMI_HANLDER_ADDR /* NMI Handler */ - .long HardFault_Handler /* Hard Fault Handler */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long SVC_Handler /* SVCall Handler */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long PendSV_Handler /* PendSV Handler */ - .long SysTick_Handler /* SysTick Handler */ - - /* External interrupts Description */ - .long NvicMux0_IRQHandler /* CPU User Interrupt #0 */ - .long NvicMux1_IRQHandler /* CPU User Interrupt #1 */ - .long NvicMux2_IRQHandler /* CPU User Interrupt #2 */ - .long NvicMux3_IRQHandler /* CPU User Interrupt #3 */ - .long NvicMux4_IRQHandler /* CPU User Interrupt #4 */ - .long NvicMux5_IRQHandler /* CPU User Interrupt #5 */ - .long NvicMux6_IRQHandler /* CPU User Interrupt #6 */ - .long NvicMux7_IRQHandler /* CPU User Interrupt #7 */ - .long Internal0_IRQHandler /* Internal SW Interrupt #0 */ - .long Internal1_IRQHandler /* Internal SW Interrupt #1 */ - .long Internal2_IRQHandler /* Internal SW Interrupt #2 */ - .long Internal3_IRQHandler /* Internal SW Interrupt #3 */ - .long Internal4_IRQHandler /* Internal SW Interrupt #4 */ - .long Internal5_IRQHandler /* Internal SW Interrupt #5 */ - .long Internal6_IRQHandler /* Internal SW Interrupt #6 */ - .long Internal7_IRQHandler /* Internal SW Interrupt #7 */ - - .size __Vectors, . - __Vectors - .equ __VectorsSize, . - __Vectors - - .section .ram_vectors - .align 2 - .globl __ramVectors -__ramVectors: - .space __VectorsSize - .size __ramVectors, . - __ramVectors - - - .text - .thumb - .thumb_func - .align 2 - - /* - * Device startup customization - * - * Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) - * because this function is executed as the first instruction in the ResetHandler. - * The PDL is also not initialized to use the proper register offsets. - * The user of this function is responsible for initializing the PDL and resources before using them. - */ - .weak Cy_OnResetUser - .func Cy_OnResetUser, Cy_OnResetUser - .type Cy_OnResetUser, %function - -Cy_OnResetUser: - bx lr - .size Cy_OnResetUser, . - Cy_OnResetUser - .endfunc - - /* Reset handler */ - .weak Reset_Handler - .type Reset_Handler, %function - -Reset_Handler: - bl Cy_OnResetUser - -/* Firstly it copies data from read only memory to RAM. There are two schemes - * to copy. One can copy more than one sections. Another can only copy - * one section. The former scheme needs more instructions and read-only - * data to implement than the latter. - * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */ - -#ifdef __STARTUP_COPY_MULTIPLE -/* Multiple sections scheme. - * - * Between symbol address __copy_table_start__ and __copy_table_end__, - * there are array of triplets, each of which specify: - * offset 0: LMA of start of a section to copy from - * offset 4: VMA of start of a section to copy to - * offset 8: size of the section to copy. Must be multiply of 4 - * - * All addresses must be aligned to 4 bytes boundary. - */ - ldr r4, =__copy_table_start__ - ldr r5, =__copy_table_end__ - -.L_loop0: - cmp r4, r5 - bge .L_loop0_done - ldr r1, [r4] - ldr r2, [r4, #4] - ldr r3, [r4, #8] - -.L_loop0_0: - subs r3, #4 - blt .L_loop0_0_done - ldr r0, [r1, r3] - str r0, [r2, r3] - b .L_loop0_0 - -.L_loop0_0_done: - adds r4, #12 - b .L_loop0 - -.L_loop0_done: -#else -/* Single section scheme. - * - * The ranges of copy from/to are specified by following symbols - * __etext: LMA of start of the section to copy from. Usually end of text - * __data_start__: VMA of start of the section to copy to - * __data_end__: VMA of end of the section to copy to - * - * All addresses must be aligned to 4 bytes boundary. - */ - ldr r1, =__etext - ldr r2, =__data_start__ - ldr r3, =__data_end__ - - subs r3, r2 - ble .L_loop1_done - -.L_loop1: - subs r3, #4 - ldr r0, [r1,r3] - str r0, [r2,r3] - bgt .L_loop1 - -.L_loop1_done: -#endif /*__STARTUP_COPY_MULTIPLE */ - -/* This part of work usually is done in C library startup code. Otherwise, - * define this macro to enable it in this startup. - * - * There are two schemes too. One can clear multiple BSS sections. Another - * can only clear one section. The former is more size expensive than the - * latter. - * - * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former. - * Otherwise define macro __STARTUP_CLEAR_BSS to choose the later. - */ -#ifdef __STARTUP_CLEAR_BSS_MULTIPLE -/* Multiple sections scheme. - * - * Between symbol address __copy_table_start__ and __copy_table_end__, - * there are array of tuples specifying: - * offset 0: Start of a BSS section - * offset 4: Size of this BSS section. Must be multiply of 4 - */ - ldr r3, =__zero_table_start__ - ldr r4, =__zero_table_end__ - -.L_loop2: - cmp r3, r4 - bge .L_loop2_done - ldr r1, [r3] - ldr r2, [r3, #4] - movs r0, 0 - -.L_loop2_0: - subs r2, #4 - blt .L_loop2_0_done - str r0, [r1, r2] - b .L_loop2_0 -.L_loop2_0_done: - - adds r3, #8 - b .L_loop2 -.L_loop2_done: -#elif defined (__STARTUP_CLEAR_BSS) -/* Single BSS section scheme. - * - * The BSS section is specified by following symbols - * __bss_start__: start of the BSS section. - * __bss_end__: end of the BSS section. - * - * Both addresses must be aligned to 4 bytes boundary. - */ - ldr r1, =__bss_start__ - ldr r2, =__bss_end__ - - movs r0, 0 - - subs r2, r1 - ble .L_loop3_done - -.L_loop3: - subs r2, #4 - str r0, [r1, r2] - bgt .L_loop3 -.L_loop3_done: -#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */ - - /* Update Vector Table Offset Register. */ - ldr r0, =__ramVectors - ldr r1, =CY_CPU_VTOR_ADDR - str r0, [r1] - dsb 0xF - - bl _start - - /* Should never get here */ - b . - - .pool - .size Reset_Handler, . - Reset_Handler - - .align 1 - .thumb_func - .weak Default_Handler - .type Default_Handler, %function -Default_Handler: - b . - .size Default_Handler, . - Default_Handler - .weak Cy_SysLib_FaultHandler - .type Cy_SysLib_FaultHandler, %function - -Cy_SysLib_FaultHandler: - b . - .size Cy_SysLib_FaultHandler, . - Cy_SysLib_FaultHandler - .type Fault_Handler, %function - -Fault_Handler: - /* Storing LR content for Creator call stack trace */ - push {LR} - movs r0, #4 - mov r1, LR - tst r0, r1 - beq .L_MSP - mrs r0, PSP - b .L_API_call -.L_MSP: - mrs r0, MSP -.L_API_call: - /* Compensation of stack pointer address due to pushing 4 bytes of LR */ - adds r0, r0, #4 - bl Cy_SysLib_FaultHandler - b . - .size Fault_Handler, . - Fault_Handler - -.macro def_fault_Handler fault_handler_name - .weak \fault_handler_name - .set \fault_handler_name, Fault_Handler - .endm - -/* Macro to define default handlers. Default handler - * will be weak symbol and just dead loops. They can be - * overwritten by other handlers */ - .macro def_irq_handler handler_name - .weak \handler_name - .set \handler_name, Default_Handler - .endm - - def_irq_handler NMI_Handler - - def_fault_Handler HardFault_Handler - - def_irq_handler SVC_Handler - def_irq_handler PendSV_Handler - def_irq_handler SysTick_Handler - - def_irq_handler NvicMux0_IRQHandler /* CPU User Interrupt #0 */ - def_irq_handler NvicMux1_IRQHandler /* CPU User Interrupt #1 */ - def_irq_handler NvicMux2_IRQHandler /* CPU User Interrupt #2 */ - def_irq_handler NvicMux3_IRQHandler /* CPU User Interrupt #3 */ - def_irq_handler NvicMux4_IRQHandler /* CPU User Interrupt #4 */ - def_irq_handler NvicMux5_IRQHandler /* CPU User Interrupt #5 */ - def_irq_handler NvicMux6_IRQHandler /* CPU User Interrupt #6 */ - def_irq_handler NvicMux7_IRQHandler /* CPU User Interrupt #7 */ - def_irq_handler Internal0_IRQHandler /* Internal SW Interrupt #0 */ - def_irq_handler Internal1_IRQHandler /* Internal SW Interrupt #1 */ - def_irq_handler Internal2_IRQHandler /* Internal SW Interrupt #2 */ - def_irq_handler Internal3_IRQHandler /* Internal SW Interrupt #3 */ - def_irq_handler Internal4_IRQHandler /* Internal SW Interrupt #4 */ - def_irq_handler Internal5_IRQHandler /* Internal SW Interrupt #5 */ - def_irq_handler Internal6_IRQHandler /* Internal SW Interrupt #6 */ - def_irq_handler Internal7_IRQHandler /* Internal SW Interrupt #7 */ - - .end - - -/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cyb06xxa_cm0plus.icf b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cyb06xxa_cm0plus.icf deleted file mode 100644 index 05bbaa0f44..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cyb06xxa_cm0plus.icf +++ /dev/null @@ -1,288 +0,0 @@ -/***************************************************************************//** -* \file cyb06xxa_cm0plus.icf -* \version 2.70 -* -* Linker file for the IAR compiler. -* -* The main purpose of the linker script is to describe how the sections in the -* input files should be mapped into the output file, and to control the memory -* layout of the output file. -* -* \note The entry point is fixed and starts at 0x10000000. The valid application -* image should be placed there. -* -* \note The linker files included with the PDL template projects must be generic -* and handle all common use cases. Your project may not use every section -* defined in the linker files. In that case you may see warnings during the -* build process. In your project, you can simply comment out or remove the -* relevant code in the linker file. -* -******************************************************************************** -* \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ - -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x00000000; - -if (!isdefinedsymbol(MBED_ROM_START)) { - define symbol MBED_ROM_START = 0x10000000; -} - -/* MBED_APP_START is being used by the bootloader build script and - * will be calculate by the system. Without bootloader the MBED_APP_START - * is equal to MBED_ROM_START - */ -if (!isdefinedsymbol(MBED_APP_START)) { - define symbol MBED_APP_START = MBED_ROM_START; -} - -if (!isdefinedsymbol(MBED_ROM_SIZE)) { - define symbol MBED_ROM_SIZE = 0x80000; -} - -/* MBED_APP_SIZE is being used by the bootloader build script and - * will be calculate by the system. Without bootloader the MBED_APP_SIZE - * is equal to MBED_ROM_SIZE - */ -if (!isdefinedsymbol(MBED_APP_SIZE)) { - define symbol MBED_APP_SIZE = MBED_ROM_SIZE; -} - -if (!isdefinedsymbol(MBED_RAM_START)) { - define symbol MBED_RAM_START = 0x08000000; -} - -if (!isdefinedsymbol(MBED_RAM_SIZE)) { - define symbol MBED_RAM_SIZE = 0x00010000; -} - -/*-Sizes-*/ -if (!isdefinedsymbol(MBED_PUBLIC_RAM_SIZE)) { - define symbol MBED_PUBLIC_RAM_SIZE = 0x200; -} -if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) { - - if (!isdefinedsymbol(__STACK_SIZE)) { - define symbol MBED_BOOT_STACK_SIZE = 0x0400; - } else { - define symbol MBED_BOOT_STACK_SIZE = __STACK_SIZE; - } -} - -define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE; - -define symbol __ICFEDIT_size_proc_stack__ = 0x0; - -/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */ -if (!isdefinedsymbol(__HEAP_SIZE)) { - define symbol __ICFEDIT_size_heap__ = 0x0400; -} else { - define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE; -} - -if (!isdefinedsymbol(MBED_PUBLIC_RAM_START)) { - define symbol MBED_PUBLIC_RAM_START = (MBED_RAM_START + MBED_RAM_SIZE - __ICFEDIT_size_cstack__ - MBED_PUBLIC_RAM_SIZE); -} - -/* The symbols below define the location and size of blocks of memory in the target. - * Use these symbols to specify the memory regions available for allocation. - */ - -/* The following symbols control RAM and flash memory allocation for the CM0+ core. - * You can change the memory allocation by editing RAM and Flash symbols. - * Your changes must be aligned with the corresponding symbols for CM4 core in 'xx_cm4_dual.icf', - * where 'xx' is the device group; for example, 'cyb06xx7_cm4_dual.icf'. - */ -/* RAM */ -define symbol __ICFEDIT_region_IRAM1_start__ = MBED_RAM_START; -define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE); -/* Public RAM */ -define symbol __ICFEDIT_region_IRAM2_start__ = MBED_PUBLIC_RAM_START; -define symbol __ICFEDIT_region_IRAM2_end__ = (MBED_PUBLIC_RAM_START + MBED_PUBLIC_RAM_SIZE); -/* Flash */ -define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START; -define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE - 0x8000); - -/* The following symbols define a 32K flash region used for EEPROM emulation. - * This region can also be used as the general purpose flash. - * You can assign sections to this memory region for only one of the cores. - * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. - * Therefore, repurposing this memory region will prevent such middleware from operation. - */ -define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000; -define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF; - -/* The following symbols define device specific memory regions and must not be changed. */ -/* Supervisory FLASH - User Data */ -define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800; -define symbol __ICFEDIT_region_IROM3_end__ = 0x160007FF; - -/* Supervisory FLASH - Normal Access Restrictions (NAR) */ -define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00; -define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF; - -/* Supervisory FLASH - Public Key */ -define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00; -define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF; - -/* Supervisory FLASH - Table of Content # 2 */ -define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00; -define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF; - -/* Supervisory FLASH - Table of Content # 2 Copy */ -define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00; -define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF; - -/* eFuse */ -define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000; -define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF; - -/* XIP */ -define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000; -define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF; - -define symbol __ICFEDIT_region_EROM2_start__ = 0x0; -define symbol __ICFEDIT_region_EROM2_end__ = 0x0; -define symbol __ICFEDIT_region_EROM3_start__ = 0x0; -define symbol __ICFEDIT_region_EROM3_end__ = 0x0; - -define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; -define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; -define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; -define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; -define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; -define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; -/**** End of ICF editor section. ###ICF###*/ - -/* The size of the MCU boot header area at the start of FLASH */ -define symbol BOOT_HEADER_SIZE = 0x400; - - -define memory mem with size = 4G; -define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]; -define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; -define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__]; -define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__]; -define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__]; -define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__]; -define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__]; -define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__]; -define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]; -define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]; -define region IRAM2_region = mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__]; - -define block RAM_DATA {readwrite section .data}; -define block RAM_OTHER {readwrite section * }; -define block RAM_NOINIT {readwrite section .noinit}; -define block RAM_BSS {readwrite section .bss}; -define block RAM with fixed order {block RAM_DATA, block RAM_OTHER, block RAM_NOINIT, block RAM_BSS}; -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { }; -define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { }; -define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK}; -define block RO {first section .intvec, readonly}; - -/*-Initializations-*/ -initialize by copy { readwrite }; -do not initialize { section .noinit, section .intvec_ram }; - -/*-Placement-*/ - -/* Flash - Cortex-M0+ application */ -".cy_app_header" : place at start of IROM1_region { section .cy_app_header }; -place at address (__ICFEDIT_region_IROM1_start__ + BOOT_HEADER_SIZE) { block RO }; - -/* Emulated EEPROM Flash area */ -".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom }; - -/* Supervisory Flash - User Data */ -".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data }; - -/* Supervisory Flash - NAR */ -".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar }; - -/* Supervisory Flash - Public Key */ -".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key }; - -/* Supervisory Flash - TOC2 */ -".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 }; - -/* Supervisory Flash - RTOC2 */ -".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 }; - -/* eFuse */ -".cy_efuse" : place at start of IROM8_region { section .cy_efuse }; - -/* Execute in Place (XIP). See the smif driver documentation for details. */ -".cy_xip" : place at start of EROM1_region { section .cy_xip }; - -/* RAM */ -place at start of IRAM1_region { readwrite section .intvec_ram}; -place in IRAM1_region { block RAM}; -place in IRAM1_region { readwrite section .cy_ramfunc }; -place at end of IRAM1_region { block HSTACK }; - -/* Public RAM */ -place at start of IRAM2_region { section .cy_sharedmem }; - -/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */ -".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; - - -keep { section .cy_app_header, - section .cy_em_eeprom, - section .cy_sflash_user_data, - section .cy_sflash_nar, - section .cy_sflash_public_key, - section .cy_toc_part2, - section .cy_rtoc_part2, - section .cy_efuse, - section .cy_xip, - section .cymeta, - }; - - -/* The following symbols used by the cymcuelftool. */ -/* Flash */ -define exported symbol __cy_memory_0_start = 0x10000000; -define exported symbol __cy_memory_0_length = 0x001D0000; -define exported symbol __cy_memory_0_row_size = 0x200; - -/* Emulated EEPROM Flash area */ -define exported symbol __cy_memory_1_start = 0x14000000; -define exported symbol __cy_memory_1_length = 0x8000; -define exported symbol __cy_memory_1_row_size = 0x200; - -/* Supervisory Flash */ -define exported symbol __cy_memory_2_start = 0x16000000; -define exported symbol __cy_memory_2_length = 0x8000; -define exported symbol __cy_memory_2_row_size = 0x200; - -/* XIP */ -define exported symbol __cy_memory_3_start = 0x18000000; -define exported symbol __cy_memory_3_length = 0x08000000; -define exported symbol __cy_memory_3_row_size = 0x200; - -/* eFuse */ -define exported symbol __cy_memory_4_start = 0x90700000; -define exported symbol __cy_memory_4_length = 0x100000; -define exported symbol __cy_memory_4_row_size = 1; - -/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/device/COMPONENT_CM0P/system_psoc6_cm0plus.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/device/COMPONENT_CM0P/system_psoc6_cm0plus.c deleted file mode 100644 index 18cc197563..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/device/COMPONENT_CM0P/system_psoc6_cm0plus.c +++ /dev/null @@ -1,526 +0,0 @@ -/***************************************************************************//** -* \file system_psoc6_cm0plus.c -* \version 2.70 -* -* The device system-source file. -* -******************************************************************************** -* \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ - -#include -#include "system_psoc6.h" -#include "cy_device.h" -#include "cy_device_headers.h" -#include "cy_syslib.h" -#include "cy_sysclk.h" -#include "cy_wdt.h" - -#if !defined(CY_IPC_DEFAULT_CFG_DISABLE) - #include "cy_ipc_sema.h" - #include "cy_ipc_pipe.h" - #include "cy_ipc_drv.h" - - #if defined(CY_DEVICE_PSOC6ABLE2) - #include "cy_flash.h" - #endif /* defined(CY_DEVICE_PSOC6ABLE2) */ -#endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */ - - -/******************************************************************************* -* SystemCoreClockUpdate() -*******************************************************************************/ - -/** Default HFClk frequency in Hz */ -#define CY_CLK_HFCLK0_FREQ_HZ_DEFAULT (8000000UL) - -/** Default PeriClk frequency in Hz */ -#define CY_CLK_PERICLK_FREQ_HZ_DEFAULT (4000000UL) - -/** Default SlowClk system core frequency in Hz */ -#define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT (4000000UL) - - -/** -* Holds the SlowClk (Cortex-M0+) or FastClk (Cortex-M4) system core clock, -* which is the system clock frequency supplied to the SysTick timer and the -* processor core clock. -* This variable implements CMSIS Core global variable. -* Refer to the [CMSIS documentation] -* (http://www.keil.com/pack/doc/CMSIS/Core/html/group__system__init__gr.html "System and Clock Configuration") -* for more details. -* This variable can be used by debuggers to query the frequency -* of the debug timer or to configure the trace clock speed. -* -* \attention Compilers must be configured to avoid removing this variable in case -* the application program is not using it. Debugging systems require the variable -* to be physically present in memory so that it can be examined to configure the debugger. */ -uint32_t SystemCoreClock = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT; - -/** Holds the HFClk0 clock frequency. Updated by \ref SystemCoreClockUpdate(). */ -uint32_t cy_Hfclk0FreqHz = CY_CLK_HFCLK0_FREQ_HZ_DEFAULT; - -/** Holds the PeriClk clock frequency. Updated by \ref SystemCoreClockUpdate(). */ -uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT; - -/** Holds the Alternate high frequency clock in Hz. Updated by \ref Cy_BLE_EcoConfigure(). */ -uint32_t cy_BleEcoClockFreqHz = 0UL; - - -/******************************************************************************* -* SystemInit() -*******************************************************************************/ - -/* CLK_FLL_CONFIG default values */ -#define CY_FB_CLK_FLL_CONFIG_VALUE (0x01000000u) -#define CY_FB_CLK_FLL_CONFIG2_VALUE (0x00020001u) -#define CY_FB_CLK_FLL_CONFIG3_VALUE (0x00002800u) -#define CY_FB_CLK_FLL_CONFIG4_VALUE (0x000000FFu) - - -/******************************************************************************* -* SystemCoreClockUpdate (void) -*******************************************************************************/ - -/* Do not use these definitions directly in your application */ -#define CY_DELAY_MS_OVERFLOW_THRESHOLD (0x8000u) -#define CY_DELAY_1K_THRESHOLD (1000u) -#define CY_DELAY_1M_THRESHOLD (1000000u) - -uint32_t cy_delayFreqKhz = CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1K_THRESHOLD); - -uint8_t cy_delayFreqMhz = (uint8_t)CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1M_THRESHOLD); - -uint32_t cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * - CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1K_THRESHOLD); - - -/******************************************************************************* -* Cy_SysEnableCM4(), Cy_SysRetainCM4(), and Cy_SysResetCM4() -*******************************************************************************/ -#define CY_SYS_CM4_PWR_CTL_KEY_OPEN (0x05FAUL) -#define CY_SYS_CM4_PWR_CTL_KEY_CLOSE (0xFA05UL) -#define CY_SYS_CM4_VECTOR_TABLE_VALID_ADDR (0x000003FFUL) - - -/******************************************************************************* -* Function Name: SystemInit -****************************************************************************//** -* -* Initializes the system: -* - Restores FLL registers to the default state. -* - Unlocks and disables WDT. -* - Calls Cy_PDL_Init() function to define the driver library. -* - Calls the Cy_SystemInit() function, if compiled from PSoC Creator. -* - Calls \ref SystemCoreClockUpdate(). -* -*******************************************************************************/ -void SystemInit(void) -{ - Cy_PDL_Init(CY_DEVICE_CFG); - - /* Restore FLL registers to the default state as they are not restored by the ROM code */ - uint32_t copy = SRSS->CLK_FLL_CONFIG; - copy &= ~SRSS_CLK_FLL_CONFIG_FLL_ENABLE_Msk; - SRSS->CLK_FLL_CONFIG = copy; - - copy = SRSS->CLK_ROOT_SELECT[0u]; - copy &= ~SRSS_CLK_ROOT_SELECT_ROOT_DIV_Msk; /* Set ROOT_DIV = 0*/ - SRSS->CLK_ROOT_SELECT[0u] = copy; - - SRSS->CLK_FLL_CONFIG = CY_FB_CLK_FLL_CONFIG_VALUE; - SRSS->CLK_FLL_CONFIG2 = CY_FB_CLK_FLL_CONFIG2_VALUE; - SRSS->CLK_FLL_CONFIG3 = CY_FB_CLK_FLL_CONFIG3_VALUE; - SRSS->CLK_FLL_CONFIG4 = CY_FB_CLK_FLL_CONFIG4_VALUE; - - /* Unlock and disable WDT */ - Cy_WDT_Unlock(); - Cy_WDT_Disable(); - - Cy_SystemInit(); - SystemCoreClockUpdate(); - - /* Clear data register of IPC structure #7, reserved for the Deep-Sleep operations. */ - REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = 0UL; - - /* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering. */ - REG_IPC_STRUCT_RELEASE(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = 0UL; - -#if !defined(CY_IPC_DEFAULT_CFG_DISABLE) - /* Allocate and initialize semaphores for the system operations. */ - CY_SECTION(".cy_sharedmem") - static uint32_t ipcSemaArray[CY_IPC_SEMA_COUNT / CY_IPC_SEMA_PER_WORD]; - - (void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, CY_IPC_SEMA_COUNT, ipcSemaArray); - - - /******************************************************************************** - * - * Initializes the system pipes. The system pipes are used by BLE and Flash. - * - * If the default startup file is not used, or SystemInit() is not called in your - * project, call the following three functions prior to executing any flash or - * EmEEPROM write or erase operation: - * -# Cy_IPC_Sema_Init() - * -# Cy_IPC_Pipe_Config() - * -# Cy_IPC_Pipe_Init() - * -# Cy_Flash_Init() - * - *******************************************************************************/ - - /* Create an array of endpoint structures */ - static cy_stc_ipc_pipe_ep_t systemIpcPipeEpArray[CY_IPC_MAX_ENDPOINTS]; - - Cy_IPC_Pipe_Config(systemIpcPipeEpArray); - - static cy_ipc_pipe_callback_ptr_t systemIpcPipeSysCbArray[CY_SYS_CYPIPE_CLIENT_CNT]; - - static const cy_stc_ipc_pipe_config_t systemIpcPipeConfigCm0 = - { - /* .ep0ConfigData */ - { - /* .ipcNotifierNumber */ CY_IPC_INTR_CYPIPE_EP0, - /* .ipcNotifierPriority */ CY_SYS_INTR_CYPIPE_PRIOR_EP0, - /* .ipcNotifierMuxNumber */ CY_SYS_INTR_CYPIPE_MUX_EP0, - /* .epAddress */ CY_IPC_EP_CYPIPE_CM0_ADDR, - /* .epConfig */ CY_SYS_CYPIPE_CONFIG_EP0 - }, - /* .ep1ConfigData */ - { - /* .ipcNotifierNumber */ CY_IPC_INTR_CYPIPE_EP1, - /* .ipcNotifierPriority */ CY_SYS_INTR_CYPIPE_PRIOR_EP1, - /* .ipcNotifierMuxNumber */ 0u, - /* .epAddress */ CY_IPC_EP_CYPIPE_CM4_ADDR, - /* .epConfig */ CY_SYS_CYPIPE_CONFIG_EP1 - }, - /* .endpointClientsCount */ CY_SYS_CYPIPE_CLIENT_CNT, - /* .endpointsCallbacksArray */ systemIpcPipeSysCbArray, - /* .userPipeIsrHandler */ &Cy_SysIpcPipeIsrCm0 - }; - - Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm0); - -#if defined(CY_DEVICE_PSOC6ABLE2) - Cy_Flash_Init(); -#endif /* defined(CY_DEVICE_PSOC6ABLE2) */ - -#endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */ -} - - -/******************************************************************************* -* Function Name: Cy_SystemInit -****************************************************************************//** -* -* The function is called during device startup. Once project compiled as part of -* the PSoC Creator project, the Cy_SystemInit() function is generated by the -* PSoC Creator. -* -* The function generated by PSoC Creator performs all of the necessary device -* configuration based on the design settings. This includes settings from the -* Design Wide Resources (DWR) such as Clocks and Pins as well as any component -* configuration that is necessary. -* -*******************************************************************************/ -__WEAK void Cy_SystemInit(void) -{ - /* Empty weak function. The actual implementation to be in the PSoC Creator - * generated strong function. - */ -} - - -/******************************************************************************* -* Function Name: SystemCoreClockUpdate -****************************************************************************//** -* -* Gets core clock frequency and updates \ref SystemCoreClock. -* -* Updates global variables used by the \ref Cy_SysLib_Delay(), \ref -* Cy_SysLib_DelayUs(), and \ref Cy_SysLib_DelayCycles(). -* -*******************************************************************************/ -void SystemCoreClockUpdate (void) -{ - uint32 locHf0Clock = Cy_SysClk_ClkHfGetFrequency(0UL); - - if (0UL != locHf0Clock) - { - cy_Hfclk0FreqHz = locHf0Clock; - cy_PeriClkFreqHz = locHf0Clock / (1UL + (uint32_t)Cy_SysClk_ClkPeriGetDivider()); - SystemCoreClock = cy_PeriClkFreqHz / (1UL + (uint32_t)Cy_SysClk_ClkSlowGetDivider()); - - /* Sets clock frequency for Delay API */ - cy_delayFreqMhz = (uint8_t)CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1M_THRESHOLD); - cy_delayFreqKhz = CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1K_THRESHOLD); - cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * cy_delayFreqKhz; - } -} - - -#if (CY_SYSTEM_CPU_CM0P == 1UL) || defined(CY_DOXYGEN) -/******************************************************************************* -* Function Name: Cy_SysGetCM4Status -****************************************************************************//** -* -* Returns the Cortex-M4 core power mode. -* -* \return \ref group_system_config_cm4_status_macro -* -*******************************************************************************/ -uint32_t Cy_SysGetCM4Status(void) -{ - uint32_t regValue; - - /* Get current power mode */ - regValue = CPUSS->CM4_PWR_CTL & CPUSS_CM4_PWR_CTL_PWR_MODE_Msk; - - return (regValue); -} - - -/******************************************************************************* -* Function Name: Cy_SysEnableCM4 -****************************************************************************//** -* -* Sets vector table base address and enables the Cortex-M4 core. -* -* \note If the CPU is already enabled, it is reset and then enabled. -* -* \param vectorTableOffset The offset of the vector table base address from -* memory address 0x00000000. The offset should be multiple to 1024 bytes. -* -*******************************************************************************/ -void Cy_SysEnableCM4(uint32_t vectorTableOffset) -{ - uint32_t regValue; - uint32_t interruptState; - uint32_t cpuState; - - CY_ASSERT_L2((vectorTableOffset & CY_SYS_CM4_VECTOR_TABLE_VALID_ADDR) == 0UL); - - interruptState = Cy_SysLib_EnterCriticalSection(); - - cpuState = Cy_SysGetCM4Status(); - if (CY_SYS_CM4_STATUS_ENABLED == cpuState) - { - Cy_SysResetCM4(); - } - - CPUSS->CM4_VECTOR_TABLE_BASE = vectorTableOffset; - - regValue = CPUSS->CM4_PWR_CTL & ~(CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM4_PWR_CTL_PWR_MODE_Msk); - regValue |= _VAL2FLD(CPUSS_CM4_PWR_CTL_VECTKEYSTAT, CY_SYS_CM4_PWR_CTL_KEY_OPEN); - regValue |= CY_SYS_CM4_STATUS_ENABLED; - CPUSS->CM4_PWR_CTL = regValue; - - while((CPUSS->CM4_STATUS & CPUSS_CM4_STATUS_PWR_DONE_Msk) == 0UL) - { - /* Wait for the power mode to take effect */ - } - - Cy_SysLib_ExitCriticalSection(interruptState); -} - - -/******************************************************************************* -* Function Name: Cy_SysDisableCM4 -****************************************************************************//** -* -* Disables the Cortex-M4 core and waits for the mode to take the effect. -* -* \warning Do not call the function while the Cortex-M4 is executing because -* such a call may corrupt/abort a pending bus-transaction by the CPU and cause -* unexpected behavior in the system including a deadlock. Call the function -* while the Cortex-M4 core is in the Sleep or Deep Sleep low-power mode. Use -* the \ref group_syspm Power Management (syspm) API to put the CPU into the -* low-power modes. Use the \ref Cy_SysPm_ReadStatus() to get a status of the -* CPU. -* -*******************************************************************************/ -void Cy_SysDisableCM4(void) -{ - uint32_t interruptState; - uint32_t regValue; - - interruptState = Cy_SysLib_EnterCriticalSection(); - - regValue = CPUSS->CM4_PWR_CTL & ~(CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM4_PWR_CTL_PWR_MODE_Msk); - regValue |= _VAL2FLD(CPUSS_CM4_PWR_CTL_VECTKEYSTAT, CY_SYS_CM4_PWR_CTL_KEY_OPEN); - regValue |= CY_SYS_CM4_STATUS_DISABLED; - CPUSS->CM4_PWR_CTL = regValue; - - while((CPUSS->CM4_STATUS & CPUSS_CM4_STATUS_PWR_DONE_Msk) == 0UL) - { - /* Wait for the power mode to take effect */ - } - - Cy_SysLib_ExitCriticalSection(interruptState); -} - - -/******************************************************************************* -* Function Name: Cy_SysRetainCM4 -****************************************************************************//** -* -* Retains the Cortex-M4 core and exists without waiting for the mode to take -* effect. -* -* \note The retained mode can be entered only from the enabled mode. -* -* \warning Do not call the function while the Cortex-M4 is executing because -* such a call may corrupt/abort a pending bus-transaction by the CPU and cause -* unexpected behavior in the system including a deadlock. Call the function -* while the Cortex-M4 core is in the Sleep or Deep Sleep low-power mode. Use -* the \ref group_syspm Power Management (syspm) API to put the CPU into the -* low-power modes. Use the \ref Cy_SysPm_ReadStatus() to get a status of the CPU. -* -*******************************************************************************/ -void Cy_SysRetainCM4(void) -{ - uint32_t interruptState; - uint32_t regValue; - - interruptState = Cy_SysLib_EnterCriticalSection(); - - regValue = CPUSS->CM4_PWR_CTL & ~(CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM4_PWR_CTL_PWR_MODE_Msk); - regValue |= _VAL2FLD(CPUSS_CM4_PWR_CTL_VECTKEYSTAT, CY_SYS_CM4_PWR_CTL_KEY_OPEN); - regValue |= CY_SYS_CM4_STATUS_RETAINED; - CPUSS->CM4_PWR_CTL = regValue; - - Cy_SysLib_ExitCriticalSection(interruptState); -} - - -/******************************************************************************* -* Function Name: Cy_SysResetCM4 -****************************************************************************//** -* -* Resets the Cortex-M4 core and waits for the mode to take the effect. -* -* \note The reset mode can not be entered from the retained mode. -* -* \warning Do not call the function while the Cortex-M4 is executing because -* such a call may corrupt/abort a pending bus-transaction by the CPU and cause -* unexpected behavior in the system including a deadlock. Call the function -* while the Cortex-M4 core is in the Sleep or Deep Sleep low-power mode. Use -* the \ref group_syspm Power Management (syspm) API to put the CPU into the -* low-power modes. Use the \ref Cy_SysPm_ReadStatus() to get a status of the CPU. -* -*******************************************************************************/ -void Cy_SysResetCM4(void) -{ - uint32_t interruptState; - uint32_t regValue; - - interruptState = Cy_SysLib_EnterCriticalSection(); - - regValue = CPUSS->CM4_PWR_CTL & ~(CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM4_PWR_CTL_PWR_MODE_Msk); - regValue |= _VAL2FLD(CPUSS_CM4_PWR_CTL_VECTKEYSTAT, CY_SYS_CM4_PWR_CTL_KEY_OPEN); - regValue |= CY_SYS_CM4_STATUS_RESET; - CPUSS->CM4_PWR_CTL = regValue; - - while((CPUSS->CM4_STATUS & CPUSS_CM4_STATUS_PWR_DONE_Msk) == 0UL) - { - /* Wait for the power mode to take effect */ - } - - Cy_SysLib_ExitCriticalSection(interruptState); -} -#endif /* #if (CY_SYSTEM_CPU_CM0P == 1UL) || defined(CY_DOXYGEN) */ - -#if !defined(CY_IPC_DEFAULT_CFG_DISABLE) -/******************************************************************************* -* Function Name: Cy_SysIpcPipeIsrCm0 -****************************************************************************//** -* -* This is the interrupt service routine for the system pipe. -* -*******************************************************************************/ -void Cy_SysIpcPipeIsrCm0(void) -{ - Cy_IPC_Pipe_ExecuteCallback(CY_IPC_EP_CYPIPE_CM0_ADDR); -} -#endif - - -/******************************************************************************* -* Function Name: Cy_MemorySymbols -****************************************************************************//** -* -* The intention of the function is to declare boundaries of the memories for the -* MDK compilers. For the rest of the supported compilers, this is done using -* linker configuration files. The following symbols used by the cymcuelftool. -* -*******************************************************************************/ -#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION < 6010050) -__asm void Cy_MemorySymbols(void) -{ - /* Flash */ - EXPORT __cy_memory_0_start - EXPORT __cy_memory_0_length - EXPORT __cy_memory_0_row_size - - /* Working Flash */ - EXPORT __cy_memory_1_start - EXPORT __cy_memory_1_length - EXPORT __cy_memory_1_row_size - - /* Supervisory Flash */ - EXPORT __cy_memory_2_start - EXPORT __cy_memory_2_length - EXPORT __cy_memory_2_row_size - - /* XIP */ - EXPORT __cy_memory_3_start - EXPORT __cy_memory_3_length - EXPORT __cy_memory_3_row_size - - /* eFuse */ - EXPORT __cy_memory_4_start - EXPORT __cy_memory_4_length - EXPORT __cy_memory_4_row_size - - /* Flash */ -__cy_memory_0_start EQU __cpp(CY_FLASH_BASE) -__cy_memory_0_length EQU __cpp(CY_FLASH_SIZE) -__cy_memory_0_row_size EQU 0x200 - - /* Flash region for EEPROM emulation */ -__cy_memory_1_start EQU __cpp(CY_EM_EEPROM_BASE) -__cy_memory_1_length EQU __cpp(CY_EM_EEPROM_SIZE) -__cy_memory_1_row_size EQU 0x200 - - /* Supervisory Flash */ -__cy_memory_2_start EQU __cpp(CY_SFLASH_BASE) -__cy_memory_2_length EQU __cpp(CY_SFLASH_SIZE) -__cy_memory_2_row_size EQU 0x200 - - /* XIP */ -__cy_memory_3_start EQU __cpp(CY_XIP_BASE) -__cy_memory_3_length EQU __cpp(CY_XIP_SIZE) -__cy_memory_3_row_size EQU 0x200 - - /* eFuse */ -__cy_memory_4_start EQU __cpp(0x90700000) -__cy_memory_4_length EQU __cpp(0x100000) -__cy_memory_4_row_size EQU __cpp(1) -} -#endif /* defined (__ARMCC_VERSION) && (__ARMCC_VERSION < 6010050) */ - - -/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xxa_cm4.sct b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xxa_cm4.sct deleted file mode 100644 index 140beae5bf..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xxa_cm4.sct +++ /dev/null @@ -1,296 +0,0 @@ -#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 -; The first line specifies a preprocessor command that the linker invokes -; to pass a scatter file through a C preprocessor. - -;******************************************************************************* -;* \file cyb06xxa_cm4.sct -;* \version 2.70 -;* -;* Linker file for the ARMCC. -;* -;* The main purpose of the linker script is to describe how the sections in the -;* input files should be mapped into the output file, and to control the memory -;* layout of the output file. -;* -;* \note The entry point location is fixed and starts at 0x10000000. The valid -;* application image should be placed there. -;* -;* \note The linker files included with the PDL template projects must be -;* generic and handle all common use cases. Your project may not use every -;* section defined in the linker files. In that case you may see the warnings -;* during the build process: L6314W (no section matches pattern) and/or L6329W -;* (pattern only matches removed unused sections). In your project, you can -;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to -;* the linker, simply comment out or remove the relevant code in the linker -;* file. -;* -;******************************************************************************* -;* \copyright -;* Copyright 2016-2019 Cypress Semiconductor Corporation -;* SPDX-License-Identifier: Apache-2.0 -;* -;* Licensed under the Apache License, Version 2.0 (the "License"); -;* you may not use this file except in compliance with the License. -;* You may obtain a copy of the License at -;* -;* http://www.apache.org/licenses/LICENSE-2.0 -;* -;* Unless required by applicable law or agreed to in writing, software -;* distributed under the License is distributed on an "AS IS" BASIS, -;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -;* See the License for the specific language governing permissions and -;* limitations under the License. -;******************************************************************************/ - -#if !defined(MBED_ROM_START) - #define MBED_ROM_START 0x10000000 -#endif - -;* MBED_APP_START is being used by the bootloader build script and -;* will be calculate by the system. Without bootloader the MBED_APP_START -;* is equal to MBED_ROM_START -;* -#if !defined(MBED_APP_START) - #define MBED_APP_START MBED_ROM_START -#endif - -#if !defined(MBED_ROM_SIZE) - #define MBED_ROM_SIZE 0x001D0000 -#endif - -;* MBED_APP_SIZE is being used by the bootloader build script and -;* will be calculate by the system. Without bootloader the MBED_APP_SIZE -;* is equal to MBED_ROM_SIZE -;* -#if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE MBED_ROM_SIZE -#endif - -#if !defined(MBED_RAM_START) - #define MBED_RAM_START 0x08000000 -#endif - -#if !defined(MBED_RAM_SIZE) - #define MBED_RAM_SIZE 0x000EA000 -#endif - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -; The size of the stack section at the end of CM4 SRAM -#define STACK_SIZE MBED_BOOT_STACK_SIZE - -; The defines below describe the location and size of blocks of memory in the target. -; Use these defines to specify the memory regions available for allocation. - -; The following defines control RAM and flash memory allocation for the CM4 core. -; RAM -#define RAM_START MBED_RAM_START -#define RAM_SIZE MBED_RAM_SIZE -; Flash -#define FLASH_START MBED_APP_START -#define FLASH_SIZE MBED_APP_SIZE - -; The size of the MCU boot header area at the start of FLASH -#define BOOT_HEADER_SIZE 0x00000400 - -; The following defines describe a 32K flash region used for EEPROM emulation. -; This region can also be used as the general purpose flash. -; You can assign sections to this memory region for only one of the cores. -; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. -; Therefore, repurposing this memory region will prevent such middleware from operation. -#define EM_EEPROM_START 0x14000000 -#define EM_EEPROM_SIZE 0x8000 - -; The following defines describe device specific memory regions and must not be changed. -; Supervisory flash: User data -#define SFLASH_USER_DATA_START 0x16000800 -#define SFLASH_USER_DATA_SIZE 0x00000800 - -; Supervisory flash: Normal Access Restrictions (NAR) -#define SFLASH_NAR_START 0x16001A00 -#define SFLASH_NAR_SIZE 0x00000200 - -; Supervisory flash: Public Key -#define SFLASH_PUBLIC_KEY_START 0x16005A00 -#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 - -; Supervisory flash: Table of Content # 2 -#define SFLASH_TOC_2_START 0x16007C00 -#define SFLASH_TOC_2_SIZE 0x00000200 - -; Supervisory flash: Table of Content # 2 Copy -#define SFLASH_RTOC_2_START 0x16007E00 -#define SFLASH_RTOC_2_SIZE 0x00000200 - -; External memory -#define XIP_START 0x18000000 -#define XIP_SIZE 0x08000000 - -; eFuse -#define EFUSE_START 0x90700000 -#define EFUSE_SIZE 0x100000 - - -; Cortex-M4 application flash area -LR_IROM1 (FLASH_START + BOOT_HEADER_SIZE) (FLASH_SIZE - BOOT_HEADER_SIZE) -{ - ER_FLASH_VECTORS +0 - { - * (RESET, +FIRST) - } - - ER_FLASH_CODE +0 FIXED - { - * (InRoot$$Sections) - * (+RO) - } - - ER_RAM_VECTORS RAM_START UNINIT - { - * (RESET_RAM, +FIRST) - } - - RW_RAM_DATA +0 - { - * (.cy_ramfunc) - * (+RW, +ZI) - } - - ; Place variables in the section that should not be initialized during the - ; device startup. - RW_IRAM1 +0 UNINIT - { - * (.noinit) - } - - ; Application heap area (HEAP) - ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM1) - { - } - - ; Stack region growing down - ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE - { - } - - ; Used for the digital signature of the secure application and the - ; Bootloader SDK application. The size of the section depends on the required - ; data size. - .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256 - { - * (.cy_app_signature) - } -} - - -; Emulated EEPROM Flash area -LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE -{ - .cy_em_eeprom +0 - { - * (.cy_em_eeprom) - } -} - -; Supervisory flash: User data -LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE -{ - .cy_sflash_user_data +0 - { - * (.cy_sflash_user_data) - } -} - -; Supervisory flash: Normal Access Restrictions (NAR) -LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE -{ - .cy_sflash_nar +0 - { - * (.cy_sflash_nar) - } -} - -; Supervisory flash: Public Key -LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE -{ - .cy_sflash_public_key +0 - { - * (.cy_sflash_public_key) - } -} - -; Supervisory flash: Table of Content # 2 -LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE -{ - .cy_toc_part2 +0 - { - * (.cy_toc_part2) - } -} - -; Supervisory flash: Table of Content # 2 Copy -LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE -{ - .cy_rtoc_part2 +0 - { - * (.cy_rtoc_part2) - } -} - - -; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. -LR_EROM XIP_START XIP_SIZE -{ - .cy_xip +0 - { - * (.cy_xip) - } -} - - -; eFuse -LR_EFUSE EFUSE_START EFUSE_SIZE -{ - .cy_efuse +0 - { - * (.cy_efuse) - } -} - - -; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. -CYMETA 0x90500000 -{ - .cymeta +0 { * (.cymeta) } -} - -/* The following symbols used by the cymcuelftool. */ -/* Flash */ -#define __cy_memory_0_start 0x10000000 -#define __cy_memory_0_length 0x001D0000 -#define __cy_memory_0_row_size 0x200 - -/* Emulated EEPROM Flash area */ -#define __cy_memory_1_start 0x14000000 -#define __cy_memory_1_length 0x8000 -#define __cy_memory_1_row_size 0x200 - -/* Supervisory Flash */ -#define __cy_memory_2_start 0x16000000 -#define __cy_memory_2_length 0x8000 -#define __cy_memory_2_row_size 0x200 - -/* XIP */ -#define __cy_memory_3_start 0x18000000 -#define __cy_memory_3_length 0x08000000 -#define __cy_memory_3_row_size 0x200 - -/* eFuse */ -#define __cy_memory_4_start 0x90700000 -#define __cy_memory_4_length 0x100000 -#define __cy_memory_4_row_size 1 - - -/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_02_cm4.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_02_cm4.S deleted file mode 100644 index 114d71efb8..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_02_cm4.S +++ /dev/null @@ -1,701 +0,0 @@ -;/**************************************************************************//** -; * @file startup_psoc6_02_cm4.S -; * @brief CMSIS Core Device Startup File for -; * ARMCM4 Device Series -; * @version V5.00 -; * @date 02. March 2016 -; ******************************************************************************/ -;/* -; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. -; * -; * SPDX-License-Identifier: Apache-2.0 -; * -; * Licensed under the Apache License, Version 2.0 (the License); you may -; * not use this file except in compliance with the License. -; * You may obtain a copy of the License at -; * -; * www.apache.org/licenses/LICENSE-2.0 -; * -; * Unless required by applicable law or agreed to in writing, software -; * distributed under the License is distributed on an AS IS BASIS, WITHOUT -; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -; * See the License for the specific language governing permissions and -; * limitations under the License. -; */ - - PRESERVE8 - THUMB - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| - -__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack - DCD Reset_Handler ; Reset Handler - - DCD 0x0000000D ; NMI Handler located at ROM code - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External interrupts Description - DCD ioss_interrupts_gpio_0_IRQHandler ; GPIO Port Interrupt #0 - DCD ioss_interrupts_gpio_1_IRQHandler ; GPIO Port Interrupt #1 - DCD ioss_interrupts_gpio_2_IRQHandler ; GPIO Port Interrupt #2 - DCD ioss_interrupts_gpio_3_IRQHandler ; GPIO Port Interrupt #3 - DCD ioss_interrupts_gpio_4_IRQHandler ; GPIO Port Interrupt #4 - DCD ioss_interrupts_gpio_5_IRQHandler ; GPIO Port Interrupt #5 - DCD ioss_interrupts_gpio_6_IRQHandler ; GPIO Port Interrupt #6 - DCD ioss_interrupts_gpio_7_IRQHandler ; GPIO Port Interrupt #7 - DCD ioss_interrupts_gpio_8_IRQHandler ; GPIO Port Interrupt #8 - DCD ioss_interrupts_gpio_9_IRQHandler ; GPIO Port Interrupt #9 - DCD ioss_interrupts_gpio_10_IRQHandler ; GPIO Port Interrupt #10 - DCD ioss_interrupts_gpio_11_IRQHandler ; GPIO Port Interrupt #11 - DCD ioss_interrupts_gpio_12_IRQHandler ; GPIO Port Interrupt #12 - DCD ioss_interrupts_gpio_13_IRQHandler ; GPIO Port Interrupt #13 - DCD ioss_interrupts_gpio_14_IRQHandler ; GPIO Port Interrupt #14 - DCD ioss_interrupt_gpio_IRQHandler ; GPIO All Ports - DCD ioss_interrupt_vdd_IRQHandler ; GPIO Supply Detect Interrupt - DCD lpcomp_interrupt_IRQHandler ; Low Power Comparator Interrupt - DCD scb_8_interrupt_IRQHandler ; Serial Communication Block #8 (DeepSleep capable) - DCD srss_interrupt_mcwdt_0_IRQHandler ; Multi Counter Watchdog Timer interrupt - DCD srss_interrupt_mcwdt_1_IRQHandler ; Multi Counter Watchdog Timer interrupt - DCD srss_interrupt_backup_IRQHandler ; Backup domain interrupt - DCD srss_interrupt_IRQHandler ; Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) - DCD cpuss_interrupts_ipc_0_IRQHandler ; CPUSS Inter Process Communication Interrupt #0 - DCD cpuss_interrupts_ipc_1_IRQHandler ; CPUSS Inter Process Communication Interrupt #1 - DCD cpuss_interrupts_ipc_2_IRQHandler ; CPUSS Inter Process Communication Interrupt #2 - DCD cpuss_interrupts_ipc_3_IRQHandler ; CPUSS Inter Process Communication Interrupt #3 - DCD cpuss_interrupts_ipc_4_IRQHandler ; CPUSS Inter Process Communication Interrupt #4 - DCD cpuss_interrupts_ipc_5_IRQHandler ; CPUSS Inter Process Communication Interrupt #5 - DCD cpuss_interrupts_ipc_6_IRQHandler ; CPUSS Inter Process Communication Interrupt #6 - DCD cpuss_interrupts_ipc_7_IRQHandler ; CPUSS Inter Process Communication Interrupt #7 - DCD cpuss_interrupts_ipc_8_IRQHandler ; CPUSS Inter Process Communication Interrupt #8 - DCD cpuss_interrupts_ipc_9_IRQHandler ; CPUSS Inter Process Communication Interrupt #9 - DCD cpuss_interrupts_ipc_10_IRQHandler ; CPUSS Inter Process Communication Interrupt #10 - DCD cpuss_interrupts_ipc_11_IRQHandler ; CPUSS Inter Process Communication Interrupt #11 - DCD cpuss_interrupts_ipc_12_IRQHandler ; CPUSS Inter Process Communication Interrupt #12 - DCD cpuss_interrupts_ipc_13_IRQHandler ; CPUSS Inter Process Communication Interrupt #13 - DCD cpuss_interrupts_ipc_14_IRQHandler ; CPUSS Inter Process Communication Interrupt #14 - DCD cpuss_interrupts_ipc_15_IRQHandler ; CPUSS Inter Process Communication Interrupt #15 - DCD scb_0_interrupt_IRQHandler ; Serial Communication Block #0 - DCD scb_1_interrupt_IRQHandler ; Serial Communication Block #1 - DCD scb_2_interrupt_IRQHandler ; Serial Communication Block #2 - DCD scb_3_interrupt_IRQHandler ; Serial Communication Block #3 - DCD scb_4_interrupt_IRQHandler ; Serial Communication Block #4 - DCD scb_5_interrupt_IRQHandler ; Serial Communication Block #5 - DCD scb_6_interrupt_IRQHandler ; Serial Communication Block #6 - DCD scb_7_interrupt_IRQHandler ; Serial Communication Block #7 - DCD scb_9_interrupt_IRQHandler ; Serial Communication Block #9 - DCD scb_10_interrupt_IRQHandler ; Serial Communication Block #10 - DCD scb_11_interrupt_IRQHandler ; Serial Communication Block #11 - DCD scb_12_interrupt_IRQHandler ; Serial Communication Block #12 - DCD csd_interrupt_IRQHandler ; CSD (Capsense) interrupt - DCD cpuss_interrupts_dmac_0_IRQHandler ; CPUSS DMAC, Channel #0 - DCD cpuss_interrupts_dmac_1_IRQHandler ; CPUSS DMAC, Channel #1 - DCD cpuss_interrupts_dmac_2_IRQHandler ; CPUSS DMAC, Channel #2 - DCD cpuss_interrupts_dmac_3_IRQHandler ; CPUSS DMAC, Channel #3 - DCD cpuss_interrupts_dw0_0_IRQHandler ; CPUSS DataWire #0, Channel #0 - DCD cpuss_interrupts_dw0_1_IRQHandler ; CPUSS DataWire #0, Channel #1 - DCD cpuss_interrupts_dw0_2_IRQHandler ; CPUSS DataWire #0, Channel #2 - DCD cpuss_interrupts_dw0_3_IRQHandler ; CPUSS DataWire #0, Channel #3 - DCD cpuss_interrupts_dw0_4_IRQHandler ; CPUSS DataWire #0, Channel #4 - DCD cpuss_interrupts_dw0_5_IRQHandler ; CPUSS DataWire #0, Channel #5 - DCD cpuss_interrupts_dw0_6_IRQHandler ; CPUSS DataWire #0, Channel #6 - DCD cpuss_interrupts_dw0_7_IRQHandler ; CPUSS DataWire #0, Channel #7 - DCD cpuss_interrupts_dw0_8_IRQHandler ; CPUSS DataWire #0, Channel #8 - DCD cpuss_interrupts_dw0_9_IRQHandler ; CPUSS DataWire #0, Channel #9 - DCD cpuss_interrupts_dw0_10_IRQHandler ; CPUSS DataWire #0, Channel #10 - DCD cpuss_interrupts_dw0_11_IRQHandler ; CPUSS DataWire #0, Channel #11 - DCD cpuss_interrupts_dw0_12_IRQHandler ; CPUSS DataWire #0, Channel #12 - DCD cpuss_interrupts_dw0_13_IRQHandler ; CPUSS DataWire #0, Channel #13 - DCD cpuss_interrupts_dw0_14_IRQHandler ; CPUSS DataWire #0, Channel #14 - DCD cpuss_interrupts_dw0_15_IRQHandler ; CPUSS DataWire #0, Channel #15 - DCD cpuss_interrupts_dw0_16_IRQHandler ; CPUSS DataWire #0, Channel #16 - DCD cpuss_interrupts_dw0_17_IRQHandler ; CPUSS DataWire #0, Channel #17 - DCD cpuss_interrupts_dw0_18_IRQHandler ; CPUSS DataWire #0, Channel #18 - DCD cpuss_interrupts_dw0_19_IRQHandler ; CPUSS DataWire #0, Channel #19 - DCD cpuss_interrupts_dw0_20_IRQHandler ; CPUSS DataWire #0, Channel #20 - DCD cpuss_interrupts_dw0_21_IRQHandler ; CPUSS DataWire #0, Channel #21 - DCD cpuss_interrupts_dw0_22_IRQHandler ; CPUSS DataWire #0, Channel #22 - DCD cpuss_interrupts_dw0_23_IRQHandler ; CPUSS DataWire #0, Channel #23 - DCD cpuss_interrupts_dw0_24_IRQHandler ; CPUSS DataWire #0, Channel #24 - DCD cpuss_interrupts_dw0_25_IRQHandler ; CPUSS DataWire #0, Channel #25 - DCD cpuss_interrupts_dw0_26_IRQHandler ; CPUSS DataWire #0, Channel #26 - DCD cpuss_interrupts_dw0_27_IRQHandler ; CPUSS DataWire #0, Channel #27 - DCD cpuss_interrupts_dw0_28_IRQHandler ; CPUSS DataWire #0, Channel #28 - DCD cpuss_interrupts_dw1_0_IRQHandler ; CPUSS DataWire #1, Channel #0 - DCD cpuss_interrupts_dw1_1_IRQHandler ; CPUSS DataWire #1, Channel #1 - DCD cpuss_interrupts_dw1_2_IRQHandler ; CPUSS DataWire #1, Channel #2 - DCD cpuss_interrupts_dw1_3_IRQHandler ; CPUSS DataWire #1, Channel #3 - DCD cpuss_interrupts_dw1_4_IRQHandler ; CPUSS DataWire #1, Channel #4 - DCD cpuss_interrupts_dw1_5_IRQHandler ; CPUSS DataWire #1, Channel #5 - DCD cpuss_interrupts_dw1_6_IRQHandler ; CPUSS DataWire #1, Channel #6 - DCD cpuss_interrupts_dw1_7_IRQHandler ; CPUSS DataWire #1, Channel #7 - DCD cpuss_interrupts_dw1_8_IRQHandler ; CPUSS DataWire #1, Channel #8 - DCD cpuss_interrupts_dw1_9_IRQHandler ; CPUSS DataWire #1, Channel #9 - DCD cpuss_interrupts_dw1_10_IRQHandler ; CPUSS DataWire #1, Channel #10 - DCD cpuss_interrupts_dw1_11_IRQHandler ; CPUSS DataWire #1, Channel #11 - DCD cpuss_interrupts_dw1_12_IRQHandler ; CPUSS DataWire #1, Channel #12 - DCD cpuss_interrupts_dw1_13_IRQHandler ; CPUSS DataWire #1, Channel #13 - DCD cpuss_interrupts_dw1_14_IRQHandler ; CPUSS DataWire #1, Channel #14 - DCD cpuss_interrupts_dw1_15_IRQHandler ; CPUSS DataWire #1, Channel #15 - DCD cpuss_interrupts_dw1_16_IRQHandler ; CPUSS DataWire #1, Channel #16 - DCD cpuss_interrupts_dw1_17_IRQHandler ; CPUSS DataWire #1, Channel #17 - DCD cpuss_interrupts_dw1_18_IRQHandler ; CPUSS DataWire #1, Channel #18 - DCD cpuss_interrupts_dw1_19_IRQHandler ; CPUSS DataWire #1, Channel #19 - DCD cpuss_interrupts_dw1_20_IRQHandler ; CPUSS DataWire #1, Channel #20 - DCD cpuss_interrupts_dw1_21_IRQHandler ; CPUSS DataWire #1, Channel #21 - DCD cpuss_interrupts_dw1_22_IRQHandler ; CPUSS DataWire #1, Channel #22 - DCD cpuss_interrupts_dw1_23_IRQHandler ; CPUSS DataWire #1, Channel #23 - DCD cpuss_interrupts_dw1_24_IRQHandler ; CPUSS DataWire #1, Channel #24 - DCD cpuss_interrupts_dw1_25_IRQHandler ; CPUSS DataWire #1, Channel #25 - DCD cpuss_interrupts_dw1_26_IRQHandler ; CPUSS DataWire #1, Channel #26 - DCD cpuss_interrupts_dw1_27_IRQHandler ; CPUSS DataWire #1, Channel #27 - DCD cpuss_interrupts_dw1_28_IRQHandler ; CPUSS DataWire #1, Channel #28 - DCD cpuss_interrupts_fault_0_IRQHandler ; CPUSS Fault Structure Interrupt #0 - DCD cpuss_interrupts_fault_1_IRQHandler ; CPUSS Fault Structure Interrupt #1 - DCD cpuss_interrupt_crypto_IRQHandler ; CRYPTO Accelerator Interrupt - DCD cpuss_interrupt_fm_IRQHandler ; FLASH Macro Interrupt - DCD cpuss_interrupts_cm4_fp_IRQHandler ; Floating Point operation fault - DCD cpuss_interrupts_cm0_cti_0_IRQHandler ; CM0+ CTI #0 - DCD cpuss_interrupts_cm0_cti_1_IRQHandler ; CM0+ CTI #1 - DCD cpuss_interrupts_cm4_cti_0_IRQHandler ; CM4 CTI #0 - DCD cpuss_interrupts_cm4_cti_1_IRQHandler ; CM4 CTI #1 - DCD tcpwm_0_interrupts_0_IRQHandler ; TCPWM #0, Counter #0 - DCD tcpwm_0_interrupts_1_IRQHandler ; TCPWM #0, Counter #1 - DCD tcpwm_0_interrupts_2_IRQHandler ; TCPWM #0, Counter #2 - DCD tcpwm_0_interrupts_3_IRQHandler ; TCPWM #0, Counter #3 - DCD tcpwm_0_interrupts_4_IRQHandler ; TCPWM #0, Counter #4 - DCD tcpwm_0_interrupts_5_IRQHandler ; TCPWM #0, Counter #5 - DCD tcpwm_0_interrupts_6_IRQHandler ; TCPWM #0, Counter #6 - DCD tcpwm_0_interrupts_7_IRQHandler ; TCPWM #0, Counter #7 - DCD tcpwm_1_interrupts_0_IRQHandler ; TCPWM #1, Counter #0 - DCD tcpwm_1_interrupts_1_IRQHandler ; TCPWM #1, Counter #1 - DCD tcpwm_1_interrupts_2_IRQHandler ; TCPWM #1, Counter #2 - DCD tcpwm_1_interrupts_3_IRQHandler ; TCPWM #1, Counter #3 - DCD tcpwm_1_interrupts_4_IRQHandler ; TCPWM #1, Counter #4 - DCD tcpwm_1_interrupts_5_IRQHandler ; TCPWM #1, Counter #5 - DCD tcpwm_1_interrupts_6_IRQHandler ; TCPWM #1, Counter #6 - DCD tcpwm_1_interrupts_7_IRQHandler ; TCPWM #1, Counter #7 - DCD tcpwm_1_interrupts_8_IRQHandler ; TCPWM #1, Counter #8 - DCD tcpwm_1_interrupts_9_IRQHandler ; TCPWM #1, Counter #9 - DCD tcpwm_1_interrupts_10_IRQHandler ; TCPWM #1, Counter #10 - DCD tcpwm_1_interrupts_11_IRQHandler ; TCPWM #1, Counter #11 - DCD tcpwm_1_interrupts_12_IRQHandler ; TCPWM #1, Counter #12 - DCD tcpwm_1_interrupts_13_IRQHandler ; TCPWM #1, Counter #13 - DCD tcpwm_1_interrupts_14_IRQHandler ; TCPWM #1, Counter #14 - DCD tcpwm_1_interrupts_15_IRQHandler ; TCPWM #1, Counter #15 - DCD tcpwm_1_interrupts_16_IRQHandler ; TCPWM #1, Counter #16 - DCD tcpwm_1_interrupts_17_IRQHandler ; TCPWM #1, Counter #17 - DCD tcpwm_1_interrupts_18_IRQHandler ; TCPWM #1, Counter #18 - DCD tcpwm_1_interrupts_19_IRQHandler ; TCPWM #1, Counter #19 - DCD tcpwm_1_interrupts_20_IRQHandler ; TCPWM #1, Counter #20 - DCD tcpwm_1_interrupts_21_IRQHandler ; TCPWM #1, Counter #21 - DCD tcpwm_1_interrupts_22_IRQHandler ; TCPWM #1, Counter #22 - DCD tcpwm_1_interrupts_23_IRQHandler ; TCPWM #1, Counter #23 - DCD pass_interrupt_sar_IRQHandler ; SAR ADC interrupt - DCD audioss_0_interrupt_i2s_IRQHandler ; I2S0 Audio interrupt - DCD audioss_0_interrupt_pdm_IRQHandler ; PDM0/PCM0 Audio interrupt - DCD audioss_1_interrupt_i2s_IRQHandler ; I2S1 Audio interrupt - DCD profile_interrupt_IRQHandler ; Energy Profiler interrupt - DCD smif_interrupt_IRQHandler ; Serial Memory Interface interrupt - DCD usb_interrupt_hi_IRQHandler ; USB Interrupt - DCD usb_interrupt_med_IRQHandler ; USB Interrupt - DCD usb_interrupt_lo_IRQHandler ; USB Interrupt - DCD sdhc_0_interrupt_wakeup_IRQHandler ; SDIO wakeup interrupt for mxsdhc - DCD sdhc_0_interrupt_general_IRQHandler ; Consolidated interrupt for mxsdhc for everything else - DCD sdhc_1_interrupt_wakeup_IRQHandler ; EEMC wakeup interrupt for mxsdhc, not used - DCD sdhc_1_interrupt_general_IRQHandler ; Consolidated interrupt for mxsdhc for everything else - -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - EXPORT __ramVectors - AREA RESET_RAM, READWRITE, NOINIT -__ramVectors SPACE __Vectors_Size - - - AREA |.text|, CODE, READONLY - - -; Weak function for startup customization -; -; Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) -; because this function is executed as the first instruction in the ResetHandler. -; The PDL is also not initialized to use the proper register offsets. -; The user of this function is responsible for initializing the PDL and resources before using them. -; -Cy_OnResetUser PROC - EXPORT Cy_OnResetUser [WEAK] - BX LR - ENDP - -; Reset Handler -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT Cy_SystemInitFpuEnable - IMPORT __main - - ; Define strong function for startup customization - BL Cy_OnResetUser - - ; Disable global interrupts - CPSID I - - ; Copy vectors from ROM to RAM - LDR r1, =__Vectors - LDR r0, =__ramVectors - LDR r2, =__Vectors_Size -Vectors_Copy - LDR r3, [r1] - STR r3, [r0] - ADDS r0, r0, #4 - ADDS r1, r1, #4 - SUBS r2, r2, #1 - CMP r2, #0 - BNE Vectors_Copy - - ; Update Vector Table Offset Register. */ - LDR r0, =__ramVectors - LDR r1, =0xE000ED08 - STR r0, [r1] - dsb 0xF - - ; Enable the FPU if used - LDR R0, =Cy_SystemInitFpuEnable - BLX R0 - - LDR R0, =__main - BLX R0 - - ; Should never get here - B . - - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP - -Cy_SysLib_FaultHandler PROC - EXPORT Cy_SysLib_FaultHandler [WEAK] - B . - ENDP -HardFault_Wrapper\ - PROC - EXPORT HardFault_Wrapper [WEAK] - movs r0, #4 - mov r1, LR - tst r0, r1 - beq L_MSP - mrs r0, PSP - bl L_API_call -L_MSP - mrs r0, MSP -L_API_call - bl Cy_SysLib_FaultHandler - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B HardFault_Wrapper - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B HardFault_Wrapper - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B HardFault_Wrapper - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B HardFault_Wrapper - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - EXPORT Default_Handler [WEAK] - EXPORT ioss_interrupts_gpio_0_IRQHandler [WEAK] - EXPORT ioss_interrupts_gpio_1_IRQHandler [WEAK] - EXPORT ioss_interrupts_gpio_2_IRQHandler [WEAK] - EXPORT ioss_interrupts_gpio_3_IRQHandler [WEAK] - EXPORT ioss_interrupts_gpio_4_IRQHandler [WEAK] - EXPORT ioss_interrupts_gpio_5_IRQHandler [WEAK] - EXPORT ioss_interrupts_gpio_6_IRQHandler [WEAK] - EXPORT ioss_interrupts_gpio_7_IRQHandler [WEAK] - EXPORT ioss_interrupts_gpio_8_IRQHandler [WEAK] - EXPORT ioss_interrupts_gpio_9_IRQHandler [WEAK] - EXPORT ioss_interrupts_gpio_10_IRQHandler [WEAK] - EXPORT ioss_interrupts_gpio_11_IRQHandler [WEAK] - EXPORT ioss_interrupts_gpio_12_IRQHandler [WEAK] - EXPORT ioss_interrupts_gpio_13_IRQHandler [WEAK] - EXPORT ioss_interrupts_gpio_14_IRQHandler [WEAK] - EXPORT ioss_interrupt_gpio_IRQHandler [WEAK] - EXPORT ioss_interrupt_vdd_IRQHandler [WEAK] - EXPORT lpcomp_interrupt_IRQHandler [WEAK] - EXPORT scb_8_interrupt_IRQHandler [WEAK] - EXPORT srss_interrupt_mcwdt_0_IRQHandler [WEAK] - EXPORT srss_interrupt_mcwdt_1_IRQHandler [WEAK] - EXPORT srss_interrupt_backup_IRQHandler [WEAK] - EXPORT srss_interrupt_IRQHandler [WEAK] - EXPORT cpuss_interrupts_ipc_0_IRQHandler [WEAK] - EXPORT cpuss_interrupts_ipc_1_IRQHandler [WEAK] - EXPORT cpuss_interrupts_ipc_2_IRQHandler [WEAK] - EXPORT cpuss_interrupts_ipc_3_IRQHandler [WEAK] - EXPORT cpuss_interrupts_ipc_4_IRQHandler [WEAK] - EXPORT cpuss_interrupts_ipc_5_IRQHandler [WEAK] - EXPORT cpuss_interrupts_ipc_6_IRQHandler [WEAK] - EXPORT cpuss_interrupts_ipc_7_IRQHandler [WEAK] - EXPORT cpuss_interrupts_ipc_8_IRQHandler [WEAK] - EXPORT cpuss_interrupts_ipc_9_IRQHandler [WEAK] - EXPORT cpuss_interrupts_ipc_10_IRQHandler [WEAK] - EXPORT cpuss_interrupts_ipc_11_IRQHandler [WEAK] - EXPORT cpuss_interrupts_ipc_12_IRQHandler [WEAK] - EXPORT cpuss_interrupts_ipc_13_IRQHandler [WEAK] - EXPORT cpuss_interrupts_ipc_14_IRQHandler [WEAK] - EXPORT cpuss_interrupts_ipc_15_IRQHandler [WEAK] - EXPORT scb_0_interrupt_IRQHandler [WEAK] - EXPORT scb_1_interrupt_IRQHandler [WEAK] - EXPORT scb_2_interrupt_IRQHandler [WEAK] - EXPORT scb_3_interrupt_IRQHandler [WEAK] - EXPORT scb_4_interrupt_IRQHandler [WEAK] - EXPORT scb_5_interrupt_IRQHandler [WEAK] - EXPORT scb_6_interrupt_IRQHandler [WEAK] - EXPORT scb_7_interrupt_IRQHandler [WEAK] - EXPORT scb_9_interrupt_IRQHandler [WEAK] - EXPORT scb_10_interrupt_IRQHandler [WEAK] - EXPORT scb_11_interrupt_IRQHandler [WEAK] - EXPORT scb_12_interrupt_IRQHandler [WEAK] - EXPORT csd_interrupt_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dmac_0_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dmac_1_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dmac_2_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dmac_3_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw0_0_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw0_1_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw0_2_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw0_3_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw0_4_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw0_5_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw0_6_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw0_7_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw0_8_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw0_9_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw0_10_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw0_11_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw0_12_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw0_13_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw0_14_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw0_15_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw0_16_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw0_17_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw0_18_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw0_19_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw0_20_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw0_21_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw0_22_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw0_23_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw0_24_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw0_25_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw0_26_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw0_27_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw0_28_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw1_0_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw1_1_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw1_2_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw1_3_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw1_4_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw1_5_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw1_6_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw1_7_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw1_8_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw1_9_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw1_10_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw1_11_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw1_12_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw1_13_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw1_14_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw1_15_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw1_16_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw1_17_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw1_18_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw1_19_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw1_20_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw1_21_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw1_22_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw1_23_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw1_24_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw1_25_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw1_26_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw1_27_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw1_28_IRQHandler [WEAK] - EXPORT cpuss_interrupts_fault_0_IRQHandler [WEAK] - EXPORT cpuss_interrupts_fault_1_IRQHandler [WEAK] - EXPORT cpuss_interrupt_crypto_IRQHandler [WEAK] - EXPORT cpuss_interrupt_fm_IRQHandler [WEAK] - EXPORT cpuss_interrupts_cm4_fp_IRQHandler [WEAK] - EXPORT cpuss_interrupts_cm0_cti_0_IRQHandler [WEAK] - EXPORT cpuss_interrupts_cm0_cti_1_IRQHandler [WEAK] - EXPORT cpuss_interrupts_cm4_cti_0_IRQHandler [WEAK] - EXPORT cpuss_interrupts_cm4_cti_1_IRQHandler [WEAK] - EXPORT tcpwm_0_interrupts_0_IRQHandler [WEAK] - EXPORT tcpwm_0_interrupts_1_IRQHandler [WEAK] - EXPORT tcpwm_0_interrupts_2_IRQHandler [WEAK] - EXPORT tcpwm_0_interrupts_3_IRQHandler [WEAK] - EXPORT tcpwm_0_interrupts_4_IRQHandler [WEAK] - EXPORT tcpwm_0_interrupts_5_IRQHandler [WEAK] - EXPORT tcpwm_0_interrupts_6_IRQHandler [WEAK] - EXPORT tcpwm_0_interrupts_7_IRQHandler [WEAK] - EXPORT tcpwm_1_interrupts_0_IRQHandler [WEAK] - EXPORT tcpwm_1_interrupts_1_IRQHandler [WEAK] - EXPORT tcpwm_1_interrupts_2_IRQHandler [WEAK] - EXPORT tcpwm_1_interrupts_3_IRQHandler [WEAK] - EXPORT tcpwm_1_interrupts_4_IRQHandler [WEAK] - EXPORT tcpwm_1_interrupts_5_IRQHandler [WEAK] - EXPORT tcpwm_1_interrupts_6_IRQHandler [WEAK] - EXPORT tcpwm_1_interrupts_7_IRQHandler [WEAK] - EXPORT tcpwm_1_interrupts_8_IRQHandler [WEAK] - EXPORT tcpwm_1_interrupts_9_IRQHandler [WEAK] - EXPORT tcpwm_1_interrupts_10_IRQHandler [WEAK] - EXPORT tcpwm_1_interrupts_11_IRQHandler [WEAK] - EXPORT tcpwm_1_interrupts_12_IRQHandler [WEAK] - EXPORT tcpwm_1_interrupts_13_IRQHandler [WEAK] - EXPORT tcpwm_1_interrupts_14_IRQHandler [WEAK] - EXPORT tcpwm_1_interrupts_15_IRQHandler [WEAK] - EXPORT tcpwm_1_interrupts_16_IRQHandler [WEAK] - EXPORT tcpwm_1_interrupts_17_IRQHandler [WEAK] - EXPORT tcpwm_1_interrupts_18_IRQHandler [WEAK] - EXPORT tcpwm_1_interrupts_19_IRQHandler [WEAK] - EXPORT tcpwm_1_interrupts_20_IRQHandler [WEAK] - EXPORT tcpwm_1_interrupts_21_IRQHandler [WEAK] - EXPORT tcpwm_1_interrupts_22_IRQHandler [WEAK] - EXPORT tcpwm_1_interrupts_23_IRQHandler [WEAK] - EXPORT pass_interrupt_sar_IRQHandler [WEAK] - EXPORT audioss_0_interrupt_i2s_IRQHandler [WEAK] - EXPORT audioss_0_interrupt_pdm_IRQHandler [WEAK] - EXPORT audioss_1_interrupt_i2s_IRQHandler [WEAK] - EXPORT profile_interrupt_IRQHandler [WEAK] - EXPORT smif_interrupt_IRQHandler [WEAK] - EXPORT usb_interrupt_hi_IRQHandler [WEAK] - EXPORT usb_interrupt_med_IRQHandler [WEAK] - EXPORT usb_interrupt_lo_IRQHandler [WEAK] - EXPORT sdhc_0_interrupt_wakeup_IRQHandler [WEAK] - EXPORT sdhc_0_interrupt_general_IRQHandler [WEAK] - EXPORT sdhc_1_interrupt_wakeup_IRQHandler [WEAK] - EXPORT sdhc_1_interrupt_general_IRQHandler [WEAK] - -ioss_interrupts_gpio_0_IRQHandler -ioss_interrupts_gpio_1_IRQHandler -ioss_interrupts_gpio_2_IRQHandler -ioss_interrupts_gpio_3_IRQHandler -ioss_interrupts_gpio_4_IRQHandler -ioss_interrupts_gpio_5_IRQHandler -ioss_interrupts_gpio_6_IRQHandler -ioss_interrupts_gpio_7_IRQHandler -ioss_interrupts_gpio_8_IRQHandler -ioss_interrupts_gpio_9_IRQHandler -ioss_interrupts_gpio_10_IRQHandler -ioss_interrupts_gpio_11_IRQHandler -ioss_interrupts_gpio_12_IRQHandler -ioss_interrupts_gpio_13_IRQHandler -ioss_interrupts_gpio_14_IRQHandler -ioss_interrupt_gpio_IRQHandler -ioss_interrupt_vdd_IRQHandler -lpcomp_interrupt_IRQHandler -scb_8_interrupt_IRQHandler -srss_interrupt_mcwdt_0_IRQHandler -srss_interrupt_mcwdt_1_IRQHandler -srss_interrupt_backup_IRQHandler -srss_interrupt_IRQHandler -cpuss_interrupts_ipc_0_IRQHandler -cpuss_interrupts_ipc_1_IRQHandler -cpuss_interrupts_ipc_2_IRQHandler -cpuss_interrupts_ipc_3_IRQHandler -cpuss_interrupts_ipc_4_IRQHandler -cpuss_interrupts_ipc_5_IRQHandler -cpuss_interrupts_ipc_6_IRQHandler -cpuss_interrupts_ipc_7_IRQHandler -cpuss_interrupts_ipc_8_IRQHandler -cpuss_interrupts_ipc_9_IRQHandler -cpuss_interrupts_ipc_10_IRQHandler -cpuss_interrupts_ipc_11_IRQHandler -cpuss_interrupts_ipc_12_IRQHandler -cpuss_interrupts_ipc_13_IRQHandler -cpuss_interrupts_ipc_14_IRQHandler -cpuss_interrupts_ipc_15_IRQHandler -scb_0_interrupt_IRQHandler -scb_1_interrupt_IRQHandler -scb_2_interrupt_IRQHandler -scb_3_interrupt_IRQHandler -scb_4_interrupt_IRQHandler -scb_5_interrupt_IRQHandler -scb_6_interrupt_IRQHandler -scb_7_interrupt_IRQHandler -scb_9_interrupt_IRQHandler -scb_10_interrupt_IRQHandler -scb_11_interrupt_IRQHandler -scb_12_interrupt_IRQHandler -csd_interrupt_IRQHandler -cpuss_interrupts_dmac_0_IRQHandler -cpuss_interrupts_dmac_1_IRQHandler -cpuss_interrupts_dmac_2_IRQHandler -cpuss_interrupts_dmac_3_IRQHandler -cpuss_interrupts_dw0_0_IRQHandler -cpuss_interrupts_dw0_1_IRQHandler -cpuss_interrupts_dw0_2_IRQHandler -cpuss_interrupts_dw0_3_IRQHandler -cpuss_interrupts_dw0_4_IRQHandler -cpuss_interrupts_dw0_5_IRQHandler -cpuss_interrupts_dw0_6_IRQHandler -cpuss_interrupts_dw0_7_IRQHandler -cpuss_interrupts_dw0_8_IRQHandler -cpuss_interrupts_dw0_9_IRQHandler -cpuss_interrupts_dw0_10_IRQHandler -cpuss_interrupts_dw0_11_IRQHandler -cpuss_interrupts_dw0_12_IRQHandler -cpuss_interrupts_dw0_13_IRQHandler -cpuss_interrupts_dw0_14_IRQHandler -cpuss_interrupts_dw0_15_IRQHandler -cpuss_interrupts_dw0_16_IRQHandler -cpuss_interrupts_dw0_17_IRQHandler -cpuss_interrupts_dw0_18_IRQHandler -cpuss_interrupts_dw0_19_IRQHandler -cpuss_interrupts_dw0_20_IRQHandler -cpuss_interrupts_dw0_21_IRQHandler -cpuss_interrupts_dw0_22_IRQHandler -cpuss_interrupts_dw0_23_IRQHandler -cpuss_interrupts_dw0_24_IRQHandler -cpuss_interrupts_dw0_25_IRQHandler -cpuss_interrupts_dw0_26_IRQHandler -cpuss_interrupts_dw0_27_IRQHandler -cpuss_interrupts_dw0_28_IRQHandler -cpuss_interrupts_dw1_0_IRQHandler -cpuss_interrupts_dw1_1_IRQHandler -cpuss_interrupts_dw1_2_IRQHandler -cpuss_interrupts_dw1_3_IRQHandler -cpuss_interrupts_dw1_4_IRQHandler -cpuss_interrupts_dw1_5_IRQHandler -cpuss_interrupts_dw1_6_IRQHandler -cpuss_interrupts_dw1_7_IRQHandler -cpuss_interrupts_dw1_8_IRQHandler -cpuss_interrupts_dw1_9_IRQHandler -cpuss_interrupts_dw1_10_IRQHandler -cpuss_interrupts_dw1_11_IRQHandler -cpuss_interrupts_dw1_12_IRQHandler -cpuss_interrupts_dw1_13_IRQHandler -cpuss_interrupts_dw1_14_IRQHandler -cpuss_interrupts_dw1_15_IRQHandler -cpuss_interrupts_dw1_16_IRQHandler -cpuss_interrupts_dw1_17_IRQHandler -cpuss_interrupts_dw1_18_IRQHandler -cpuss_interrupts_dw1_19_IRQHandler -cpuss_interrupts_dw1_20_IRQHandler -cpuss_interrupts_dw1_21_IRQHandler -cpuss_interrupts_dw1_22_IRQHandler -cpuss_interrupts_dw1_23_IRQHandler -cpuss_interrupts_dw1_24_IRQHandler -cpuss_interrupts_dw1_25_IRQHandler -cpuss_interrupts_dw1_26_IRQHandler -cpuss_interrupts_dw1_27_IRQHandler -cpuss_interrupts_dw1_28_IRQHandler -cpuss_interrupts_fault_0_IRQHandler -cpuss_interrupts_fault_1_IRQHandler -cpuss_interrupt_crypto_IRQHandler -cpuss_interrupt_fm_IRQHandler -cpuss_interrupts_cm4_fp_IRQHandler -cpuss_interrupts_cm0_cti_0_IRQHandler -cpuss_interrupts_cm0_cti_1_IRQHandler -cpuss_interrupts_cm4_cti_0_IRQHandler -cpuss_interrupts_cm4_cti_1_IRQHandler -tcpwm_0_interrupts_0_IRQHandler -tcpwm_0_interrupts_1_IRQHandler -tcpwm_0_interrupts_2_IRQHandler -tcpwm_0_interrupts_3_IRQHandler -tcpwm_0_interrupts_4_IRQHandler -tcpwm_0_interrupts_5_IRQHandler -tcpwm_0_interrupts_6_IRQHandler -tcpwm_0_interrupts_7_IRQHandler -tcpwm_1_interrupts_0_IRQHandler -tcpwm_1_interrupts_1_IRQHandler -tcpwm_1_interrupts_2_IRQHandler -tcpwm_1_interrupts_3_IRQHandler -tcpwm_1_interrupts_4_IRQHandler -tcpwm_1_interrupts_5_IRQHandler -tcpwm_1_interrupts_6_IRQHandler -tcpwm_1_interrupts_7_IRQHandler -tcpwm_1_interrupts_8_IRQHandler -tcpwm_1_interrupts_9_IRQHandler -tcpwm_1_interrupts_10_IRQHandler -tcpwm_1_interrupts_11_IRQHandler -tcpwm_1_interrupts_12_IRQHandler -tcpwm_1_interrupts_13_IRQHandler -tcpwm_1_interrupts_14_IRQHandler -tcpwm_1_interrupts_15_IRQHandler -tcpwm_1_interrupts_16_IRQHandler -tcpwm_1_interrupts_17_IRQHandler -tcpwm_1_interrupts_18_IRQHandler -tcpwm_1_interrupts_19_IRQHandler -tcpwm_1_interrupts_20_IRQHandler -tcpwm_1_interrupts_21_IRQHandler -tcpwm_1_interrupts_22_IRQHandler -tcpwm_1_interrupts_23_IRQHandler -pass_interrupt_sar_IRQHandler -audioss_0_interrupt_i2s_IRQHandler -audioss_0_interrupt_pdm_IRQHandler -audioss_1_interrupt_i2s_IRQHandler -profile_interrupt_IRQHandler -smif_interrupt_IRQHandler -usb_interrupt_hi_IRQHandler -usb_interrupt_med_IRQHandler -usb_interrupt_lo_IRQHandler -sdhc_0_interrupt_wakeup_IRQHandler -sdhc_0_interrupt_general_IRQHandler -sdhc_1_interrupt_wakeup_IRQHandler -sdhc_1_interrupt_general_IRQHandler - - B . - ENDP - - ALIGN - - END - - -; [] END OF FILE diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm4.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm4.S deleted file mode 100644 index 1ebcac39f8..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm4.S +++ /dev/null @@ -1,673 +0,0 @@ -/**************************************************************************//** - * @file startup_psoc6_02_cm4.S - * @brief CMSIS Core Device Startup File for - * ARMCM4 Device Series - * @version V5.00 - * @date 02. March 2016 - ******************************************************************************/ -/* - * Copyright (c) 2009-2016 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - - /* Address of the NMI handler */ - #define CY_NMI_HANLDER_ADDR 0x0000000D - - /* The CPU VTOR register */ - #define CY_CPU_VTOR_ADDR 0xE000ED08 - - /* Copy flash vectors and data section to RAM */ - #define __STARTUP_COPY_MULTIPLE - - /* Clear single BSS section */ - #define __STARTUP_CLEAR_BSS - - .syntax unified - .arch armv7-m - - .section .stack - .align 3 -#ifdef __STACK_SIZE - .equ Stack_Size, __STACK_SIZE -#else - .equ Stack_Size, 0x00001000 -#endif - .globl __StackTop - .globl __StackLimit -__StackLimit: - .space Stack_Size - .size __StackLimit, . - __StackLimit -__StackTop: - .size __StackTop, . - __StackTop - - .section .heap - .align 3 -#ifdef __HEAP_SIZE - .equ Heap_Size, __HEAP_SIZE -#else - .equ Heap_Size, 0x00000400 -#endif - .globl __HeapBase - .globl __HeapLimit -__HeapBase: - .if Heap_Size - .space Heap_Size - .endif - .size __HeapBase, . - __HeapBase -__HeapLimit: - .size __HeapLimit, . - __HeapLimit - - .section .vectors - .align 2 - .globl __Vectors -__Vectors: - .long __StackTop /* Top of Stack */ - .long Reset_Handler /* Reset Handler */ - .long CY_NMI_HANLDER_ADDR /* NMI Handler */ - .long HardFault_Handler /* Hard Fault Handler */ - .long MemManage_Handler /* MPU Fault Handler */ - .long BusFault_Handler /* Bus Fault Handler */ - .long UsageFault_Handler /* Usage Fault Handler */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long SVC_Handler /* SVCall Handler */ - .long DebugMon_Handler /* Debug Monitor Handler */ - .long 0 /* Reserved */ - .long PendSV_Handler /* PendSV Handler */ - .long SysTick_Handler /* SysTick Handler */ - - /* External interrupts Description */ - .long ioss_interrupts_gpio_0_IRQHandler /* GPIO Port Interrupt #0 */ - .long ioss_interrupts_gpio_1_IRQHandler /* GPIO Port Interrupt #1 */ - .long ioss_interrupts_gpio_2_IRQHandler /* GPIO Port Interrupt #2 */ - .long ioss_interrupts_gpio_3_IRQHandler /* GPIO Port Interrupt #3 */ - .long ioss_interrupts_gpio_4_IRQHandler /* GPIO Port Interrupt #4 */ - .long ioss_interrupts_gpio_5_IRQHandler /* GPIO Port Interrupt #5 */ - .long ioss_interrupts_gpio_6_IRQHandler /* GPIO Port Interrupt #6 */ - .long ioss_interrupts_gpio_7_IRQHandler /* GPIO Port Interrupt #7 */ - .long ioss_interrupts_gpio_8_IRQHandler /* GPIO Port Interrupt #8 */ - .long ioss_interrupts_gpio_9_IRQHandler /* GPIO Port Interrupt #9 */ - .long ioss_interrupts_gpio_10_IRQHandler /* GPIO Port Interrupt #10 */ - .long ioss_interrupts_gpio_11_IRQHandler /* GPIO Port Interrupt #11 */ - .long ioss_interrupts_gpio_12_IRQHandler /* GPIO Port Interrupt #12 */ - .long ioss_interrupts_gpio_13_IRQHandler /* GPIO Port Interrupt #13 */ - .long ioss_interrupts_gpio_14_IRQHandler /* GPIO Port Interrupt #14 */ - .long ioss_interrupt_gpio_IRQHandler /* GPIO All Ports */ - .long ioss_interrupt_vdd_IRQHandler /* GPIO Supply Detect Interrupt */ - .long lpcomp_interrupt_IRQHandler /* Low Power Comparator Interrupt */ - .long scb_8_interrupt_IRQHandler /* Serial Communication Block #8 (DeepSleep capable) */ - .long srss_interrupt_mcwdt_0_IRQHandler /* Multi Counter Watchdog Timer interrupt */ - .long srss_interrupt_mcwdt_1_IRQHandler /* Multi Counter Watchdog Timer interrupt */ - .long srss_interrupt_backup_IRQHandler /* Backup domain interrupt */ - .long srss_interrupt_IRQHandler /* Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ - .long cpuss_interrupts_ipc_0_IRQHandler /* CPUSS Inter Process Communication Interrupt #0 */ - .long cpuss_interrupts_ipc_1_IRQHandler /* CPUSS Inter Process Communication Interrupt #1 */ - .long cpuss_interrupts_ipc_2_IRQHandler /* CPUSS Inter Process Communication Interrupt #2 */ - .long cpuss_interrupts_ipc_3_IRQHandler /* CPUSS Inter Process Communication Interrupt #3 */ - .long cpuss_interrupts_ipc_4_IRQHandler /* CPUSS Inter Process Communication Interrupt #4 */ - .long cpuss_interrupts_ipc_5_IRQHandler /* CPUSS Inter Process Communication Interrupt #5 */ - .long cpuss_interrupts_ipc_6_IRQHandler /* CPUSS Inter Process Communication Interrupt #6 */ - .long cpuss_interrupts_ipc_7_IRQHandler /* CPUSS Inter Process Communication Interrupt #7 */ - .long cpuss_interrupts_ipc_8_IRQHandler /* CPUSS Inter Process Communication Interrupt #8 */ - .long cpuss_interrupts_ipc_9_IRQHandler /* CPUSS Inter Process Communication Interrupt #9 */ - .long cpuss_interrupts_ipc_10_IRQHandler /* CPUSS Inter Process Communication Interrupt #10 */ - .long cpuss_interrupts_ipc_11_IRQHandler /* CPUSS Inter Process Communication Interrupt #11 */ - .long cpuss_interrupts_ipc_12_IRQHandler /* CPUSS Inter Process Communication Interrupt #12 */ - .long cpuss_interrupts_ipc_13_IRQHandler /* CPUSS Inter Process Communication Interrupt #13 */ - .long cpuss_interrupts_ipc_14_IRQHandler /* CPUSS Inter Process Communication Interrupt #14 */ - .long cpuss_interrupts_ipc_15_IRQHandler /* CPUSS Inter Process Communication Interrupt #15 */ - .long scb_0_interrupt_IRQHandler /* Serial Communication Block #0 */ - .long scb_1_interrupt_IRQHandler /* Serial Communication Block #1 */ - .long scb_2_interrupt_IRQHandler /* Serial Communication Block #2 */ - .long scb_3_interrupt_IRQHandler /* Serial Communication Block #3 */ - .long scb_4_interrupt_IRQHandler /* Serial Communication Block #4 */ - .long scb_5_interrupt_IRQHandler /* Serial Communication Block #5 */ - .long scb_6_interrupt_IRQHandler /* Serial Communication Block #6 */ - .long scb_7_interrupt_IRQHandler /* Serial Communication Block #7 */ - .long scb_9_interrupt_IRQHandler /* Serial Communication Block #9 */ - .long scb_10_interrupt_IRQHandler /* Serial Communication Block #10 */ - .long scb_11_interrupt_IRQHandler /* Serial Communication Block #11 */ - .long scb_12_interrupt_IRQHandler /* Serial Communication Block #12 */ - .long csd_interrupt_IRQHandler /* CSD (Capsense) interrupt */ - .long cpuss_interrupts_dmac_0_IRQHandler /* CPUSS DMAC, Channel #0 */ - .long cpuss_interrupts_dmac_1_IRQHandler /* CPUSS DMAC, Channel #1 */ - .long cpuss_interrupts_dmac_2_IRQHandler /* CPUSS DMAC, Channel #2 */ - .long cpuss_interrupts_dmac_3_IRQHandler /* CPUSS DMAC, Channel #3 */ - .long cpuss_interrupts_dw0_0_IRQHandler /* CPUSS DataWire #0, Channel #0 */ - .long cpuss_interrupts_dw0_1_IRQHandler /* CPUSS DataWire #0, Channel #1 */ - .long cpuss_interrupts_dw0_2_IRQHandler /* CPUSS DataWire #0, Channel #2 */ - .long cpuss_interrupts_dw0_3_IRQHandler /* CPUSS DataWire #0, Channel #3 */ - .long cpuss_interrupts_dw0_4_IRQHandler /* CPUSS DataWire #0, Channel #4 */ - .long cpuss_interrupts_dw0_5_IRQHandler /* CPUSS DataWire #0, Channel #5 */ - .long cpuss_interrupts_dw0_6_IRQHandler /* CPUSS DataWire #0, Channel #6 */ - .long cpuss_interrupts_dw0_7_IRQHandler /* CPUSS DataWire #0, Channel #7 */ - .long cpuss_interrupts_dw0_8_IRQHandler /* CPUSS DataWire #0, Channel #8 */ - .long cpuss_interrupts_dw0_9_IRQHandler /* CPUSS DataWire #0, Channel #9 */ - .long cpuss_interrupts_dw0_10_IRQHandler /* CPUSS DataWire #0, Channel #10 */ - .long cpuss_interrupts_dw0_11_IRQHandler /* CPUSS DataWire #0, Channel #11 */ - .long cpuss_interrupts_dw0_12_IRQHandler /* CPUSS DataWire #0, Channel #12 */ - .long cpuss_interrupts_dw0_13_IRQHandler /* CPUSS DataWire #0, Channel #13 */ - .long cpuss_interrupts_dw0_14_IRQHandler /* CPUSS DataWire #0, Channel #14 */ - .long cpuss_interrupts_dw0_15_IRQHandler /* CPUSS DataWire #0, Channel #15 */ - .long cpuss_interrupts_dw0_16_IRQHandler /* CPUSS DataWire #0, Channel #16 */ - .long cpuss_interrupts_dw0_17_IRQHandler /* CPUSS DataWire #0, Channel #17 */ - .long cpuss_interrupts_dw0_18_IRQHandler /* CPUSS DataWire #0, Channel #18 */ - .long cpuss_interrupts_dw0_19_IRQHandler /* CPUSS DataWire #0, Channel #19 */ - .long cpuss_interrupts_dw0_20_IRQHandler /* CPUSS DataWire #0, Channel #20 */ - .long cpuss_interrupts_dw0_21_IRQHandler /* CPUSS DataWire #0, Channel #21 */ - .long cpuss_interrupts_dw0_22_IRQHandler /* CPUSS DataWire #0, Channel #22 */ - .long cpuss_interrupts_dw0_23_IRQHandler /* CPUSS DataWire #0, Channel #23 */ - .long cpuss_interrupts_dw0_24_IRQHandler /* CPUSS DataWire #0, Channel #24 */ - .long cpuss_interrupts_dw0_25_IRQHandler /* CPUSS DataWire #0, Channel #25 */ - .long cpuss_interrupts_dw0_26_IRQHandler /* CPUSS DataWire #0, Channel #26 */ - .long cpuss_interrupts_dw0_27_IRQHandler /* CPUSS DataWire #0, Channel #27 */ - .long cpuss_interrupts_dw0_28_IRQHandler /* CPUSS DataWire #0, Channel #28 */ - .long cpuss_interrupts_dw1_0_IRQHandler /* CPUSS DataWire #1, Channel #0 */ - .long cpuss_interrupts_dw1_1_IRQHandler /* CPUSS DataWire #1, Channel #1 */ - .long cpuss_interrupts_dw1_2_IRQHandler /* CPUSS DataWire #1, Channel #2 */ - .long cpuss_interrupts_dw1_3_IRQHandler /* CPUSS DataWire #1, Channel #3 */ - .long cpuss_interrupts_dw1_4_IRQHandler /* CPUSS DataWire #1, Channel #4 */ - .long cpuss_interrupts_dw1_5_IRQHandler /* CPUSS DataWire #1, Channel #5 */ - .long cpuss_interrupts_dw1_6_IRQHandler /* CPUSS DataWire #1, Channel #6 */ - .long cpuss_interrupts_dw1_7_IRQHandler /* CPUSS DataWire #1, Channel #7 */ - .long cpuss_interrupts_dw1_8_IRQHandler /* CPUSS DataWire #1, Channel #8 */ - .long cpuss_interrupts_dw1_9_IRQHandler /* CPUSS DataWire #1, Channel #9 */ - .long cpuss_interrupts_dw1_10_IRQHandler /* CPUSS DataWire #1, Channel #10 */ - .long cpuss_interrupts_dw1_11_IRQHandler /* CPUSS DataWire #1, Channel #11 */ - .long cpuss_interrupts_dw1_12_IRQHandler /* CPUSS DataWire #1, Channel #12 */ - .long cpuss_interrupts_dw1_13_IRQHandler /* CPUSS DataWire #1, Channel #13 */ - .long cpuss_interrupts_dw1_14_IRQHandler /* CPUSS DataWire #1, Channel #14 */ - .long cpuss_interrupts_dw1_15_IRQHandler /* CPUSS DataWire #1, Channel #15 */ - .long cpuss_interrupts_dw1_16_IRQHandler /* CPUSS DataWire #1, Channel #16 */ - .long cpuss_interrupts_dw1_17_IRQHandler /* CPUSS DataWire #1, Channel #17 */ - .long cpuss_interrupts_dw1_18_IRQHandler /* CPUSS DataWire #1, Channel #18 */ - .long cpuss_interrupts_dw1_19_IRQHandler /* CPUSS DataWire #1, Channel #19 */ - .long cpuss_interrupts_dw1_20_IRQHandler /* CPUSS DataWire #1, Channel #20 */ - .long cpuss_interrupts_dw1_21_IRQHandler /* CPUSS DataWire #1, Channel #21 */ - .long cpuss_interrupts_dw1_22_IRQHandler /* CPUSS DataWire #1, Channel #22 */ - .long cpuss_interrupts_dw1_23_IRQHandler /* CPUSS DataWire #1, Channel #23 */ - .long cpuss_interrupts_dw1_24_IRQHandler /* CPUSS DataWire #1, Channel #24 */ - .long cpuss_interrupts_dw1_25_IRQHandler /* CPUSS DataWire #1, Channel #25 */ - .long cpuss_interrupts_dw1_26_IRQHandler /* CPUSS DataWire #1, Channel #26 */ - .long cpuss_interrupts_dw1_27_IRQHandler /* CPUSS DataWire #1, Channel #27 */ - .long cpuss_interrupts_dw1_28_IRQHandler /* CPUSS DataWire #1, Channel #28 */ - .long cpuss_interrupts_fault_0_IRQHandler /* CPUSS Fault Structure Interrupt #0 */ - .long cpuss_interrupts_fault_1_IRQHandler /* CPUSS Fault Structure Interrupt #1 */ - .long cpuss_interrupt_crypto_IRQHandler /* CRYPTO Accelerator Interrupt */ - .long cpuss_interrupt_fm_IRQHandler /* FLASH Macro Interrupt */ - .long cpuss_interrupts_cm4_fp_IRQHandler /* Floating Point operation fault */ - .long cpuss_interrupts_cm0_cti_0_IRQHandler /* CM0+ CTI #0 */ - .long cpuss_interrupts_cm0_cti_1_IRQHandler /* CM0+ CTI #1 */ - .long cpuss_interrupts_cm4_cti_0_IRQHandler /* CM4 CTI #0 */ - .long cpuss_interrupts_cm4_cti_1_IRQHandler /* CM4 CTI #1 */ - .long tcpwm_0_interrupts_0_IRQHandler /* TCPWM #0, Counter #0 */ - .long tcpwm_0_interrupts_1_IRQHandler /* TCPWM #0, Counter #1 */ - .long tcpwm_0_interrupts_2_IRQHandler /* TCPWM #0, Counter #2 */ - .long tcpwm_0_interrupts_3_IRQHandler /* TCPWM #0, Counter #3 */ - .long tcpwm_0_interrupts_4_IRQHandler /* TCPWM #0, Counter #4 */ - .long tcpwm_0_interrupts_5_IRQHandler /* TCPWM #0, Counter #5 */ - .long tcpwm_0_interrupts_6_IRQHandler /* TCPWM #0, Counter #6 */ - .long tcpwm_0_interrupts_7_IRQHandler /* TCPWM #0, Counter #7 */ - .long tcpwm_1_interrupts_0_IRQHandler /* TCPWM #1, Counter #0 */ - .long tcpwm_1_interrupts_1_IRQHandler /* TCPWM #1, Counter #1 */ - .long tcpwm_1_interrupts_2_IRQHandler /* TCPWM #1, Counter #2 */ - .long tcpwm_1_interrupts_3_IRQHandler /* TCPWM #1, Counter #3 */ - .long tcpwm_1_interrupts_4_IRQHandler /* TCPWM #1, Counter #4 */ - .long tcpwm_1_interrupts_5_IRQHandler /* TCPWM #1, Counter #5 */ - .long tcpwm_1_interrupts_6_IRQHandler /* TCPWM #1, Counter #6 */ - .long tcpwm_1_interrupts_7_IRQHandler /* TCPWM #1, Counter #7 */ - .long tcpwm_1_interrupts_8_IRQHandler /* TCPWM #1, Counter #8 */ - .long tcpwm_1_interrupts_9_IRQHandler /* TCPWM #1, Counter #9 */ - .long tcpwm_1_interrupts_10_IRQHandler /* TCPWM #1, Counter #10 */ - .long tcpwm_1_interrupts_11_IRQHandler /* TCPWM #1, Counter #11 */ - .long tcpwm_1_interrupts_12_IRQHandler /* TCPWM #1, Counter #12 */ - .long tcpwm_1_interrupts_13_IRQHandler /* TCPWM #1, Counter #13 */ - .long tcpwm_1_interrupts_14_IRQHandler /* TCPWM #1, Counter #14 */ - .long tcpwm_1_interrupts_15_IRQHandler /* TCPWM #1, Counter #15 */ - .long tcpwm_1_interrupts_16_IRQHandler /* TCPWM #1, Counter #16 */ - .long tcpwm_1_interrupts_17_IRQHandler /* TCPWM #1, Counter #17 */ - .long tcpwm_1_interrupts_18_IRQHandler /* TCPWM #1, Counter #18 */ - .long tcpwm_1_interrupts_19_IRQHandler /* TCPWM #1, Counter #19 */ - .long tcpwm_1_interrupts_20_IRQHandler /* TCPWM #1, Counter #20 */ - .long tcpwm_1_interrupts_21_IRQHandler /* TCPWM #1, Counter #21 */ - .long tcpwm_1_interrupts_22_IRQHandler /* TCPWM #1, Counter #22 */ - .long tcpwm_1_interrupts_23_IRQHandler /* TCPWM #1, Counter #23 */ - .long pass_interrupt_sar_IRQHandler /* SAR ADC interrupt */ - .long audioss_0_interrupt_i2s_IRQHandler /* I2S0 Audio interrupt */ - .long audioss_0_interrupt_pdm_IRQHandler /* PDM0/PCM0 Audio interrupt */ - .long audioss_1_interrupt_i2s_IRQHandler /* I2S1 Audio interrupt */ - .long profile_interrupt_IRQHandler /* Energy Profiler interrupt */ - .long smif_interrupt_IRQHandler /* Serial Memory Interface interrupt */ - .long usb_interrupt_hi_IRQHandler /* USB Interrupt */ - .long usb_interrupt_med_IRQHandler /* USB Interrupt */ - .long usb_interrupt_lo_IRQHandler /* USB Interrupt */ - .long sdhc_0_interrupt_wakeup_IRQHandler /* SDIO wakeup interrupt for mxsdhc */ - .long sdhc_0_interrupt_general_IRQHandler /* Consolidated interrupt for mxsdhc for everything else */ - .long sdhc_1_interrupt_wakeup_IRQHandler /* EEMC wakeup interrupt for mxsdhc, not used */ - .long sdhc_1_interrupt_general_IRQHandler /* Consolidated interrupt for mxsdhc for everything else */ - - - .size __Vectors, . - __Vectors - .equ __VectorsSize, . - __Vectors - - .section .ram_vectors - .align 2 - .globl __ramVectors -__ramVectors: - .space __VectorsSize - .size __ramVectors, . - __ramVectors - - - .text - .thumb - .thumb_func - .align 2 - - /* - * Device startup customization - * - * Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) - * because this function is executed as the first instruction in the ResetHandler. - * The PDL is also not initialized to use the proper register offsets. - * The user of this function is responsible for initializing the PDL and resources before using them. - */ - .weak Cy_OnResetUser - .func Cy_OnResetUser, Cy_OnResetUser - .type Cy_OnResetUser, %function - -Cy_OnResetUser: - bx lr - .size Cy_OnResetUser, . - Cy_OnResetUser - .endfunc - - /* Reset handler */ - .weak Reset_Handler - .type Reset_Handler, %function - -Reset_Handler: - bl Cy_OnResetUser - cpsid i - -/* Firstly it copies data from read only memory to RAM. There are two schemes - * to copy. One can copy more than one sections. Another can only copy - * one section. The former scheme needs more instructions and read-only - * data to implement than the latter. - * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */ - -#ifdef __STARTUP_COPY_MULTIPLE -/* Multiple sections scheme. - * - * Between symbol address __copy_table_start__ and __copy_table_end__, - * there are array of triplets, each of which specify: - * offset 0: LMA of start of a section to copy from - * offset 4: VMA of start of a section to copy to - * offset 8: size of the section to copy. Must be multiply of 4 - * - * All addresses must be aligned to 4 bytes boundary. - */ - ldr r4, =__copy_table_start__ - ldr r5, =__copy_table_end__ - -.L_loop0: - cmp r4, r5 - bge .L_loop0_done - ldr r1, [r4] - ldr r2, [r4, #4] - ldr r3, [r4, #8] - -.L_loop0_0: - subs r3, #4 - ittt ge - ldrge r0, [r1, r3] - strge r0, [r2, r3] - bge .L_loop0_0 - - adds r4, #12 - b .L_loop0 - -.L_loop0_done: -#else -/* Single section scheme. - * - * The ranges of copy from/to are specified by following symbols - * __etext: LMA of start of the section to copy from. Usually end of text - * __data_start__: VMA of start of the section to copy to - * __data_end__: VMA of end of the section to copy to - * - * All addresses must be aligned to 4 bytes boundary. - */ - ldr r1, =__etext - ldr r2, =__data_start__ - ldr r3, =__data_end__ - -.L_loop1: - cmp r2, r3 - ittt lt - ldrlt r0, [r1], #4 - strlt r0, [r2], #4 - blt .L_loop1 -#endif /*__STARTUP_COPY_MULTIPLE */ - -/* This part of work usually is done in C library startup code. Otherwise, - * define this macro to enable it in this startup. - * - * There are two schemes too. One can clear multiple BSS sections. Another - * can only clear one section. The former is more size expensive than the - * latter. - * - * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former. - * Otherwise define macro __STARTUP_CLEAR_BSS to choose the later. - */ -#ifdef __STARTUP_CLEAR_BSS_MULTIPLE -/* Multiple sections scheme. - * - * Between symbol address __copy_table_start__ and __copy_table_end__, - * there are array of tuples specifying: - * offset 0: Start of a BSS section - * offset 4: Size of this BSS section. Must be multiply of 4 - */ - ldr r3, =__zero_table_start__ - ldr r4, =__zero_table_end__ - -.L_loop2: - cmp r3, r4 - bge .L_loop2_done - ldr r1, [r3] - ldr r2, [r3, #4] - movs r0, 0 - -.L_loop2_0: - subs r2, #4 - itt ge - strge r0, [r1, r2] - bge .L_loop2_0 - - adds r3, #8 - b .L_loop2 -.L_loop2_done: -#elif defined (__STARTUP_CLEAR_BSS) -/* Single BSS section scheme. - * - * The BSS section is specified by following symbols - * __bss_start__: start of the BSS section. - * __bss_end__: end of the BSS section. - * - * Both addresses must be aligned to 4 bytes boundary. - */ - ldr r1, =__bss_start__ - ldr r2, =__bss_end__ - - movs r0, 0 -.L_loop3: - cmp r1, r2 - itt lt - strlt r0, [r1], #4 - blt .L_loop3 -#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */ - - /* Update Vector Table Offset Register. */ - ldr r0, =__ramVectors - ldr r1, =CY_CPU_VTOR_ADDR - str r0, [r1] - dsb 0xF - - /* Enable the FPU if used */ - bl Cy_SystemInitFpuEnable - - bl _start - - /* Should never get here */ - b . - - .pool - .size Reset_Handler, . - Reset_Handler - - .align 1 - .thumb_func - .weak Default_Handler - .type Default_Handler, %function - -Default_Handler: - b . - .size Default_Handler, . - Default_Handler - - - .weak Cy_SysLib_FaultHandler - .type Cy_SysLib_FaultHandler, %function - -Cy_SysLib_FaultHandler: - b . - .size Cy_SysLib_FaultHandler, . - Cy_SysLib_FaultHandler - .type Fault_Handler, %function - -Fault_Handler: - /* Storing LR content for Creator call stack trace */ - push {LR} - movs r0, #4 - mov r1, LR - tst r0, r1 - beq .L_MSP - mrs r0, PSP - b .L_API_call -.L_MSP: - mrs r0, MSP -.L_API_call: - /* Compensation of stack pointer address due to pushing 4 bytes of LR */ - adds r0, r0, #4 - bl Cy_SysLib_FaultHandler - b . - .size Fault_Handler, . - Fault_Handler - -.macro def_fault_Handler fault_handler_name - .weak \fault_handler_name - .set \fault_handler_name, Fault_Handler - .endm - -/* Macro to define default handlers. Default handler - * will be weak symbol and just dead loops. They can be - * overwritten by other handlers */ - .macro def_irq_handler handler_name - .weak \handler_name - .set \handler_name, Default_Handler - .endm - - def_irq_handler NMI_Handler - - def_fault_Handler HardFault_Handler - def_fault_Handler MemManage_Handler - def_fault_Handler BusFault_Handler - def_fault_Handler UsageFault_Handler - - def_irq_handler SVC_Handler - def_irq_handler DebugMon_Handler - def_irq_handler PendSV_Handler - def_irq_handler SysTick_Handler - - def_irq_handler ioss_interrupts_gpio_0_IRQHandler /* GPIO Port Interrupt #0 */ - def_irq_handler ioss_interrupts_gpio_1_IRQHandler /* GPIO Port Interrupt #1 */ - def_irq_handler ioss_interrupts_gpio_2_IRQHandler /* GPIO Port Interrupt #2 */ - def_irq_handler ioss_interrupts_gpio_3_IRQHandler /* GPIO Port Interrupt #3 */ - def_irq_handler ioss_interrupts_gpio_4_IRQHandler /* GPIO Port Interrupt #4 */ - def_irq_handler ioss_interrupts_gpio_5_IRQHandler /* GPIO Port Interrupt #5 */ - def_irq_handler ioss_interrupts_gpio_6_IRQHandler /* GPIO Port Interrupt #6 */ - def_irq_handler ioss_interrupts_gpio_7_IRQHandler /* GPIO Port Interrupt #7 */ - def_irq_handler ioss_interrupts_gpio_8_IRQHandler /* GPIO Port Interrupt #8 */ - def_irq_handler ioss_interrupts_gpio_9_IRQHandler /* GPIO Port Interrupt #9 */ - def_irq_handler ioss_interrupts_gpio_10_IRQHandler /* GPIO Port Interrupt #10 */ - def_irq_handler ioss_interrupts_gpio_11_IRQHandler /* GPIO Port Interrupt #11 */ - def_irq_handler ioss_interrupts_gpio_12_IRQHandler /* GPIO Port Interrupt #12 */ - def_irq_handler ioss_interrupts_gpio_13_IRQHandler /* GPIO Port Interrupt #13 */ - def_irq_handler ioss_interrupts_gpio_14_IRQHandler /* GPIO Port Interrupt #14 */ - def_irq_handler ioss_interrupt_gpio_IRQHandler /* GPIO All Ports */ - def_irq_handler ioss_interrupt_vdd_IRQHandler /* GPIO Supply Detect Interrupt */ - def_irq_handler lpcomp_interrupt_IRQHandler /* Low Power Comparator Interrupt */ - def_irq_handler scb_8_interrupt_IRQHandler /* Serial Communication Block #8 (DeepSleep capable) */ - def_irq_handler srss_interrupt_mcwdt_0_IRQHandler /* Multi Counter Watchdog Timer interrupt */ - def_irq_handler srss_interrupt_mcwdt_1_IRQHandler /* Multi Counter Watchdog Timer interrupt */ - def_irq_handler srss_interrupt_backup_IRQHandler /* Backup domain interrupt */ - def_irq_handler srss_interrupt_IRQHandler /* Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ - def_irq_handler cpuss_interrupts_ipc_0_IRQHandler /* CPUSS Inter Process Communication Interrupt #0 */ - def_irq_handler cpuss_interrupts_ipc_1_IRQHandler /* CPUSS Inter Process Communication Interrupt #1 */ - def_irq_handler cpuss_interrupts_ipc_2_IRQHandler /* CPUSS Inter Process Communication Interrupt #2 */ - def_irq_handler cpuss_interrupts_ipc_3_IRQHandler /* CPUSS Inter Process Communication Interrupt #3 */ - def_irq_handler cpuss_interrupts_ipc_4_IRQHandler /* CPUSS Inter Process Communication Interrupt #4 */ - def_irq_handler cpuss_interrupts_ipc_5_IRQHandler /* CPUSS Inter Process Communication Interrupt #5 */ - def_irq_handler cpuss_interrupts_ipc_6_IRQHandler /* CPUSS Inter Process Communication Interrupt #6 */ - def_irq_handler cpuss_interrupts_ipc_7_IRQHandler /* CPUSS Inter Process Communication Interrupt #7 */ - def_irq_handler cpuss_interrupts_ipc_8_IRQHandler /* CPUSS Inter Process Communication Interrupt #8 */ - def_irq_handler cpuss_interrupts_ipc_9_IRQHandler /* CPUSS Inter Process Communication Interrupt #9 */ - def_irq_handler cpuss_interrupts_ipc_10_IRQHandler /* CPUSS Inter Process Communication Interrupt #10 */ - def_irq_handler cpuss_interrupts_ipc_11_IRQHandler /* CPUSS Inter Process Communication Interrupt #11 */ - def_irq_handler cpuss_interrupts_ipc_12_IRQHandler /* CPUSS Inter Process Communication Interrupt #12 */ - def_irq_handler cpuss_interrupts_ipc_13_IRQHandler /* CPUSS Inter Process Communication Interrupt #13 */ - def_irq_handler cpuss_interrupts_ipc_14_IRQHandler /* CPUSS Inter Process Communication Interrupt #14 */ - def_irq_handler cpuss_interrupts_ipc_15_IRQHandler /* CPUSS Inter Process Communication Interrupt #15 */ - def_irq_handler scb_0_interrupt_IRQHandler /* Serial Communication Block #0 */ - def_irq_handler scb_1_interrupt_IRQHandler /* Serial Communication Block #1 */ - def_irq_handler scb_2_interrupt_IRQHandler /* Serial Communication Block #2 */ - def_irq_handler scb_3_interrupt_IRQHandler /* Serial Communication Block #3 */ - def_irq_handler scb_4_interrupt_IRQHandler /* Serial Communication Block #4 */ - def_irq_handler scb_5_interrupt_IRQHandler /* Serial Communication Block #5 */ - def_irq_handler scb_6_interrupt_IRQHandler /* Serial Communication Block #6 */ - def_irq_handler scb_7_interrupt_IRQHandler /* Serial Communication Block #7 */ - def_irq_handler scb_9_interrupt_IRQHandler /* Serial Communication Block #9 */ - def_irq_handler scb_10_interrupt_IRQHandler /* Serial Communication Block #10 */ - def_irq_handler scb_11_interrupt_IRQHandler /* Serial Communication Block #11 */ - def_irq_handler scb_12_interrupt_IRQHandler /* Serial Communication Block #12 */ - def_irq_handler csd_interrupt_IRQHandler /* CSD (Capsense) interrupt */ - def_irq_handler cpuss_interrupts_dmac_0_IRQHandler /* CPUSS DMAC, Channel #0 */ - def_irq_handler cpuss_interrupts_dmac_1_IRQHandler /* CPUSS DMAC, Channel #1 */ - def_irq_handler cpuss_interrupts_dmac_2_IRQHandler /* CPUSS DMAC, Channel #2 */ - def_irq_handler cpuss_interrupts_dmac_3_IRQHandler /* CPUSS DMAC, Channel #3 */ - def_irq_handler cpuss_interrupts_dw0_0_IRQHandler /* CPUSS DataWire #0, Channel #0 */ - def_irq_handler cpuss_interrupts_dw0_1_IRQHandler /* CPUSS DataWire #0, Channel #1 */ - def_irq_handler cpuss_interrupts_dw0_2_IRQHandler /* CPUSS DataWire #0, Channel #2 */ - def_irq_handler cpuss_interrupts_dw0_3_IRQHandler /* CPUSS DataWire #0, Channel #3 */ - def_irq_handler cpuss_interrupts_dw0_4_IRQHandler /* CPUSS DataWire #0, Channel #4 */ - def_irq_handler cpuss_interrupts_dw0_5_IRQHandler /* CPUSS DataWire #0, Channel #5 */ - def_irq_handler cpuss_interrupts_dw0_6_IRQHandler /* CPUSS DataWire #0, Channel #6 */ - def_irq_handler cpuss_interrupts_dw0_7_IRQHandler /* CPUSS DataWire #0, Channel #7 */ - def_irq_handler cpuss_interrupts_dw0_8_IRQHandler /* CPUSS DataWire #0, Channel #8 */ - def_irq_handler cpuss_interrupts_dw0_9_IRQHandler /* CPUSS DataWire #0, Channel #9 */ - def_irq_handler cpuss_interrupts_dw0_10_IRQHandler /* CPUSS DataWire #0, Channel #10 */ - def_irq_handler cpuss_interrupts_dw0_11_IRQHandler /* CPUSS DataWire #0, Channel #11 */ - def_irq_handler cpuss_interrupts_dw0_12_IRQHandler /* CPUSS DataWire #0, Channel #12 */ - def_irq_handler cpuss_interrupts_dw0_13_IRQHandler /* CPUSS DataWire #0, Channel #13 */ - def_irq_handler cpuss_interrupts_dw0_14_IRQHandler /* CPUSS DataWire #0, Channel #14 */ - def_irq_handler cpuss_interrupts_dw0_15_IRQHandler /* CPUSS DataWire #0, Channel #15 */ - def_irq_handler cpuss_interrupts_dw0_16_IRQHandler /* CPUSS DataWire #0, Channel #16 */ - def_irq_handler cpuss_interrupts_dw0_17_IRQHandler /* CPUSS DataWire #0, Channel #17 */ - def_irq_handler cpuss_interrupts_dw0_18_IRQHandler /* CPUSS DataWire #0, Channel #18 */ - def_irq_handler cpuss_interrupts_dw0_19_IRQHandler /* CPUSS DataWire #0, Channel #19 */ - def_irq_handler cpuss_interrupts_dw0_20_IRQHandler /* CPUSS DataWire #0, Channel #20 */ - def_irq_handler cpuss_interrupts_dw0_21_IRQHandler /* CPUSS DataWire #0, Channel #21 */ - def_irq_handler cpuss_interrupts_dw0_22_IRQHandler /* CPUSS DataWire #0, Channel #22 */ - def_irq_handler cpuss_interrupts_dw0_23_IRQHandler /* CPUSS DataWire #0, Channel #23 */ - def_irq_handler cpuss_interrupts_dw0_24_IRQHandler /* CPUSS DataWire #0, Channel #24 */ - def_irq_handler cpuss_interrupts_dw0_25_IRQHandler /* CPUSS DataWire #0, Channel #25 */ - def_irq_handler cpuss_interrupts_dw0_26_IRQHandler /* CPUSS DataWire #0, Channel #26 */ - def_irq_handler cpuss_interrupts_dw0_27_IRQHandler /* CPUSS DataWire #0, Channel #27 */ - def_irq_handler cpuss_interrupts_dw0_28_IRQHandler /* CPUSS DataWire #0, Channel #28 */ - def_irq_handler cpuss_interrupts_dw1_0_IRQHandler /* CPUSS DataWire #1, Channel #0 */ - def_irq_handler cpuss_interrupts_dw1_1_IRQHandler /* CPUSS DataWire #1, Channel #1 */ - def_irq_handler cpuss_interrupts_dw1_2_IRQHandler /* CPUSS DataWire #1, Channel #2 */ - def_irq_handler cpuss_interrupts_dw1_3_IRQHandler /* CPUSS DataWire #1, Channel #3 */ - def_irq_handler cpuss_interrupts_dw1_4_IRQHandler /* CPUSS DataWire #1, Channel #4 */ - def_irq_handler cpuss_interrupts_dw1_5_IRQHandler /* CPUSS DataWire #1, Channel #5 */ - def_irq_handler cpuss_interrupts_dw1_6_IRQHandler /* CPUSS DataWire #1, Channel #6 */ - def_irq_handler cpuss_interrupts_dw1_7_IRQHandler /* CPUSS DataWire #1, Channel #7 */ - def_irq_handler cpuss_interrupts_dw1_8_IRQHandler /* CPUSS DataWire #1, Channel #8 */ - def_irq_handler cpuss_interrupts_dw1_9_IRQHandler /* CPUSS DataWire #1, Channel #9 */ - def_irq_handler cpuss_interrupts_dw1_10_IRQHandler /* CPUSS DataWire #1, Channel #10 */ - def_irq_handler cpuss_interrupts_dw1_11_IRQHandler /* CPUSS DataWire #1, Channel #11 */ - def_irq_handler cpuss_interrupts_dw1_12_IRQHandler /* CPUSS DataWire #1, Channel #12 */ - def_irq_handler cpuss_interrupts_dw1_13_IRQHandler /* CPUSS DataWire #1, Channel #13 */ - def_irq_handler cpuss_interrupts_dw1_14_IRQHandler /* CPUSS DataWire #1, Channel #14 */ - def_irq_handler cpuss_interrupts_dw1_15_IRQHandler /* CPUSS DataWire #1, Channel #15 */ - def_irq_handler cpuss_interrupts_dw1_16_IRQHandler /* CPUSS DataWire #1, Channel #16 */ - def_irq_handler cpuss_interrupts_dw1_17_IRQHandler /* CPUSS DataWire #1, Channel #17 */ - def_irq_handler cpuss_interrupts_dw1_18_IRQHandler /* CPUSS DataWire #1, Channel #18 */ - def_irq_handler cpuss_interrupts_dw1_19_IRQHandler /* CPUSS DataWire #1, Channel #19 */ - def_irq_handler cpuss_interrupts_dw1_20_IRQHandler /* CPUSS DataWire #1, Channel #20 */ - def_irq_handler cpuss_interrupts_dw1_21_IRQHandler /* CPUSS DataWire #1, Channel #21 */ - def_irq_handler cpuss_interrupts_dw1_22_IRQHandler /* CPUSS DataWire #1, Channel #22 */ - def_irq_handler cpuss_interrupts_dw1_23_IRQHandler /* CPUSS DataWire #1, Channel #23 */ - def_irq_handler cpuss_interrupts_dw1_24_IRQHandler /* CPUSS DataWire #1, Channel #24 */ - def_irq_handler cpuss_interrupts_dw1_25_IRQHandler /* CPUSS DataWire #1, Channel #25 */ - def_irq_handler cpuss_interrupts_dw1_26_IRQHandler /* CPUSS DataWire #1, Channel #26 */ - def_irq_handler cpuss_interrupts_dw1_27_IRQHandler /* CPUSS DataWire #1, Channel #27 */ - def_irq_handler cpuss_interrupts_dw1_28_IRQHandler /* CPUSS DataWire #1, Channel #28 */ - def_irq_handler cpuss_interrupts_fault_0_IRQHandler /* CPUSS Fault Structure Interrupt #0 */ - def_irq_handler cpuss_interrupts_fault_1_IRQHandler /* CPUSS Fault Structure Interrupt #1 */ - def_irq_handler cpuss_interrupt_crypto_IRQHandler /* CRYPTO Accelerator Interrupt */ - def_irq_handler cpuss_interrupt_fm_IRQHandler /* FLASH Macro Interrupt */ - def_irq_handler cpuss_interrupts_cm4_fp_IRQHandler /* Floating Point operation fault */ - def_irq_handler cpuss_interrupts_cm0_cti_0_IRQHandler /* CM0+ CTI #0 */ - def_irq_handler cpuss_interrupts_cm0_cti_1_IRQHandler /* CM0+ CTI #1 */ - def_irq_handler cpuss_interrupts_cm4_cti_0_IRQHandler /* CM4 CTI #0 */ - def_irq_handler cpuss_interrupts_cm4_cti_1_IRQHandler /* CM4 CTI #1 */ - def_irq_handler tcpwm_0_interrupts_0_IRQHandler /* TCPWM #0, Counter #0 */ - def_irq_handler tcpwm_0_interrupts_1_IRQHandler /* TCPWM #0, Counter #1 */ - def_irq_handler tcpwm_0_interrupts_2_IRQHandler /* TCPWM #0, Counter #2 */ - def_irq_handler tcpwm_0_interrupts_3_IRQHandler /* TCPWM #0, Counter #3 */ - def_irq_handler tcpwm_0_interrupts_4_IRQHandler /* TCPWM #0, Counter #4 */ - def_irq_handler tcpwm_0_interrupts_5_IRQHandler /* TCPWM #0, Counter #5 */ - def_irq_handler tcpwm_0_interrupts_6_IRQHandler /* TCPWM #0, Counter #6 */ - def_irq_handler tcpwm_0_interrupts_7_IRQHandler /* TCPWM #0, Counter #7 */ - def_irq_handler tcpwm_1_interrupts_0_IRQHandler /* TCPWM #1, Counter #0 */ - def_irq_handler tcpwm_1_interrupts_1_IRQHandler /* TCPWM #1, Counter #1 */ - def_irq_handler tcpwm_1_interrupts_2_IRQHandler /* TCPWM #1, Counter #2 */ - def_irq_handler tcpwm_1_interrupts_3_IRQHandler /* TCPWM #1, Counter #3 */ - def_irq_handler tcpwm_1_interrupts_4_IRQHandler /* TCPWM #1, Counter #4 */ - def_irq_handler tcpwm_1_interrupts_5_IRQHandler /* TCPWM #1, Counter #5 */ - def_irq_handler tcpwm_1_interrupts_6_IRQHandler /* TCPWM #1, Counter #6 */ - def_irq_handler tcpwm_1_interrupts_7_IRQHandler /* TCPWM #1, Counter #7 */ - def_irq_handler tcpwm_1_interrupts_8_IRQHandler /* TCPWM #1, Counter #8 */ - def_irq_handler tcpwm_1_interrupts_9_IRQHandler /* TCPWM #1, Counter #9 */ - def_irq_handler tcpwm_1_interrupts_10_IRQHandler /* TCPWM #1, Counter #10 */ - def_irq_handler tcpwm_1_interrupts_11_IRQHandler /* TCPWM #1, Counter #11 */ - def_irq_handler tcpwm_1_interrupts_12_IRQHandler /* TCPWM #1, Counter #12 */ - def_irq_handler tcpwm_1_interrupts_13_IRQHandler /* TCPWM #1, Counter #13 */ - def_irq_handler tcpwm_1_interrupts_14_IRQHandler /* TCPWM #1, Counter #14 */ - def_irq_handler tcpwm_1_interrupts_15_IRQHandler /* TCPWM #1, Counter #15 */ - def_irq_handler tcpwm_1_interrupts_16_IRQHandler /* TCPWM #1, Counter #16 */ - def_irq_handler tcpwm_1_interrupts_17_IRQHandler /* TCPWM #1, Counter #17 */ - def_irq_handler tcpwm_1_interrupts_18_IRQHandler /* TCPWM #1, Counter #18 */ - def_irq_handler tcpwm_1_interrupts_19_IRQHandler /* TCPWM #1, Counter #19 */ - def_irq_handler tcpwm_1_interrupts_20_IRQHandler /* TCPWM #1, Counter #20 */ - def_irq_handler tcpwm_1_interrupts_21_IRQHandler /* TCPWM #1, Counter #21 */ - def_irq_handler tcpwm_1_interrupts_22_IRQHandler /* TCPWM #1, Counter #22 */ - def_irq_handler tcpwm_1_interrupts_23_IRQHandler /* TCPWM #1, Counter #23 */ - def_irq_handler pass_interrupt_sar_IRQHandler /* SAR ADC interrupt */ - def_irq_handler audioss_0_interrupt_i2s_IRQHandler /* I2S0 Audio interrupt */ - def_irq_handler audioss_0_interrupt_pdm_IRQHandler /* PDM0/PCM0 Audio interrupt */ - def_irq_handler audioss_1_interrupt_i2s_IRQHandler /* I2S1 Audio interrupt */ - def_irq_handler profile_interrupt_IRQHandler /* Energy Profiler interrupt */ - def_irq_handler smif_interrupt_IRQHandler /* Serial Memory Interface interrupt */ - def_irq_handler usb_interrupt_hi_IRQHandler /* USB Interrupt */ - def_irq_handler usb_interrupt_med_IRQHandler /* USB Interrupt */ - def_irq_handler usb_interrupt_lo_IRQHandler /* USB Interrupt */ - def_irq_handler sdhc_0_interrupt_wakeup_IRQHandler /* SDIO wakeup interrupt for mxsdhc */ - def_irq_handler sdhc_0_interrupt_general_IRQHandler /* Consolidated interrupt for mxsdhc for everything else */ - def_irq_handler sdhc_1_interrupt_wakeup_IRQHandler /* EEMC wakeup interrupt for mxsdhc, not used */ - def_irq_handler sdhc_1_interrupt_general_IRQHandler /* Consolidated interrupt for mxsdhc for everything else */ - - .end - - -/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xxa_cm4.icf b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xxa_cm4.icf deleted file mode 100644 index 22ac13a47f..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xxa_cm4.icf +++ /dev/null @@ -1,272 +0,0 @@ -/***************************************************************************//** -* \file cyb06xxa_cm4.icf -* \version 2.70 -* -* Linker file for the IAR compiler. -* -* The main purpose of the linker script is to describe how the sections in the -* input files should be mapped into the output file, and to control the memory -* layout of the output file. -* -* \note The entry point is fixed and starts at 0x10000000. The valid application -* image should be placed there. -* -* \note The linker files included with the PDL template projects must be generic -* and handle all common use cases. Your project may not use every section -* defined in the linker files. In that case you may see warnings during the -* build process. In your project, you can simply comment out or remove the -* relevant code in the linker file. -* -******************************************************************************** -* \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ - -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x00000000; - -if (!isdefinedsymbol(MBED_ROM_START)) { - define symbol MBED_ROM_START = 0x10000000; -} - -/* MBED_APP_START is being used by the bootloader build script and - * will be calculate by the system. Without bootloader the MBED_APP_START - * is equal to MBED_ROM_START - */ -if (!isdefinedsymbol(MBED_APP_START)) { - define symbol MBED_APP_START = MBED_ROM_START; -} - -if (!isdefinedsymbol(MBED_ROM_SIZE)) { - define symbol MBED_ROM_SIZE = 0x001D0000; -} - -/* MBED_APP_SIZE is being used by the bootloader build script and - * will be calculate by the system. Without bootloader the MBED_APP_SIZE - * is equal to MBED_ROM_SIZE - */ -if (!isdefinedsymbol(MBED_APP_SIZE)) { - define symbol MBED_APP_SIZE = MBED_ROM_SIZE; -} - -if (!isdefinedsymbol(MBED_RAM_START)) { - define symbol MBED_RAM_START = 0x08000000; -} - -if (!isdefinedsymbol(MBED_RAM_SIZE)) { - define symbol MBED_RAM_SIZE = 0x000EA000; -} - -if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) { - define symbol MBED_BOOT_STACK_SIZE = 0x400; -} - -/* The symbols below define the location and size of blocks of memory in the target. - * Use these symbols to specify the memory regions available for allocation. - */ - -/* The following symbols control RAM and flash memory allocation for the CM4 core. - */ -/* RAM */ -define symbol __ICFEDIT_region_IRAM1_start__ = MBED_RAM_START; -define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE); -/* Flash */ -define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START; -define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE); - -/* The following symbols define a 32K flash region used for EEPROM emulation. - * This region can also be used as the general purpose flash. - * You can assign sections to this memory region for only one of the cores. - * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. - * Therefore, repurposing this memory region will prevent such middleware from operation. - */ -define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000; -define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF; - -/* The following symbols define device specific memory regions and must not be changed. */ -/* Supervisory FLASH - User Data */ -define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800; -define symbol __ICFEDIT_region_IROM3_end__ = 0x160007FF; - -/* Supervisory FLASH - Normal Access Restrictions (NAR) */ -define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00; -define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF; - -/* Supervisory FLASH - Public Key */ -define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00; -define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF; - -/* Supervisory FLASH - Table of Content # 2 */ -define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00; -define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF; - -/* Supervisory FLASH - Table of Content # 2 Copy */ -define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00; -define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF; - -/* eFuse */ -define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000; -define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF; - -/* XIP */ -define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000; -define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF; - -define symbol __ICFEDIT_region_EROM2_start__ = 0x0; -define symbol __ICFEDIT_region_EROM2_end__ = 0x0; -define symbol __ICFEDIT_region_EROM3_start__ = 0x0; -define symbol __ICFEDIT_region_EROM3_end__ = 0x0; - - -define symbol __ICFEDIT_region_IRAM2_start__ = 0x0; -define symbol __ICFEDIT_region_IRAM2_end__ = 0x0; -define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; -define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; -define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; -define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; -define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; -define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; -/*-Sizes-*/ -if (!isdefinedsymbol(__STACK_SIZE)) { - define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE; -} else { - define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE; -} - -/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */ -if (!isdefinedsymbol(__HEAP_SIZE)) { - define symbol __ICFEDIT_size_heap__ = 0x0400; -} else { - define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE; -} -/**** End of ICF editor section. ###ICF###*/ - -/* The size of the MCU boot header area at the start of FLASH */ -define symbol BOOT_HEADER_SIZE = 0x400; - - -define memory mem with size = 4G; -define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]; -define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; -define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__]; -define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__]; -define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__]; -define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__]; -define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__]; -define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__]; -define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]; -define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]; - -define block RAM_DATA {readwrite section .data}; -define block RAM_OTHER {readwrite section * }; -define block RAM_NOINIT {readwrite section .noinit}; -define block RAM_BSS {readwrite section .bss}; -define block RAM with fixed order {block RAM_DATA, block RAM_OTHER, block RAM_NOINIT, block RAM_BSS}; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { }; - -define block RO {first section .intvec, readonly}; - -/*-Initializations-*/ -initialize by copy { readwrite }; -do not initialize { section .noinit, section .intvec_ram }; - -/*-Placement-*/ - -/* Flash - Cortex-M4 application */ -place at address (__ICFEDIT_region_IROM1_start__ + BOOT_HEADER_SIZE) { block RO }; - -/* Used for the digital signature of the secure application and the Bootloader SDK application. */ -".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature }; - -/* Emulated EEPROM Flash area */ -".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom }; - -/* Supervisory Flash - User Data */ -".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data }; - -/* Supervisory Flash - NAR */ -".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar }; - -/* Supervisory Flash - Public Key */ -".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key }; - -/* Supervisory Flash - TOC2 */ -".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 }; - -/* Supervisory Flash - RTOC2 */ -".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 }; - -/* eFuse */ -".cy_efuse" : place at start of IROM8_region { section .cy_efuse }; - -/* Execute in Place (XIP). See the smif driver documentation for details. */ -".cy_xip" : place at start of EROM1_region { section .cy_xip }; - -/* RAM */ -place at start of IRAM1_region { readwrite section .intvec_ram}; -place in IRAM1_region { block RAM}; -place in IRAM1_region { block HEAP}; -place at end of IRAM1_region { block CSTACK }; - -/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */ -".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; - - -keep { section .cy_app_signature, - section .cy_em_eeprom, - section .cy_sflash_user_data, - section .cy_sflash_nar, - section .cy_sflash_public_key, - section .cy_toc_part2, - section .cy_rtoc_part2, - section .cy_efuse, - section .cy_xip, - section .cymeta, - }; - - -/* The following symbols used by the cymcuelftool. */ -/* Flash */ -define exported symbol __cy_memory_0_start = 0x10000000; -define exported symbol __cy_memory_0_length = 0x001D0000; -define exported symbol __cy_memory_0_row_size = 0x200; - -/* Emulated EEPROM Flash area */ -define exported symbol __cy_memory_1_start = 0x14000000; -define exported symbol __cy_memory_1_length = 0x8000; -define exported symbol __cy_memory_1_row_size = 0x200; - -/* Supervisory Flash */ -define exported symbol __cy_memory_2_start = 0x16000000; -define exported symbol __cy_memory_2_length = 0x8000; -define exported symbol __cy_memory_2_row_size = 0x200; - -/* XIP */ -define exported symbol __cy_memory_3_start = 0x18000000; -define exported symbol __cy_memory_3_length = 0x08000000; -define exported symbol __cy_memory_3_row_size = 0x200; - -/* eFuse */ -define exported symbol __cy_memory_4_start = 0x90700000; -define exported symbol __cy_memory_4_length = 0x100000; -define exported symbol __cy_memory_4_row_size = 1; - -/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_02_cm4.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_02_cm4.S deleted file mode 100644 index 3257b6f20c..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_02_cm4.S +++ /dev/null @@ -1,1263 +0,0 @@ -;/**************************************************************************//** -; * @file startup_psoc6_02_cm4.S -; * @brief CMSIS Core Device Startup File for -; * ARMCM4 Device Series -; * @version V5.00 -; * @date 08. March 2016 -; ******************************************************************************/ -;/* -; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. -; * -; * SPDX-License-Identifier: Apache-2.0 -; * -; * Licensed under the Apache License, Version 2.0 (the License); you may -; * not use this file except in compliance with the License. -; * You may obtain a copy of the License at -; * -; * www.apache.org/licenses/LICENSE-2.0 -; * -; * Unless required by applicable law or agreed to in writing, software -; * distributed under the License is distributed on an AS IS BASIS, WITHOUT -; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -; * See the License for the specific language governing permissions and -; * limitations under the License. -; */ - -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - SECTION .intvec_ram:DATA:NOROOT(2) - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - EXTERN Cy_SystemInitFpuEnable - EXTERN __iar_data_init3 - PUBLIC __vector_table - PUBLIC __vector_table_0x1c - PUBLIC __Vectors - PUBLIC __Vectors_End - PUBLIC __Vectors_Size - PUBLIC __ramVectors - - DATA - -__vector_table - DCD sfe(CSTACK) - DCD Reset_Handler - - DCD 0x0000000D ; NMI_Handler is defined in ROM code - DCD HardFault_Handler - DCD MemManage_Handler - DCD BusFault_Handler - DCD UsageFault_Handler -__vector_table_0x1c - DCD 0 - DCD 0 - DCD 0 - DCD 0 - DCD SVC_Handler - DCD DebugMon_Handler - DCD 0 - DCD PendSV_Handler - DCD SysTick_Handler - - ; External interrupts Description - DCD ioss_interrupts_gpio_0_IRQHandler ; GPIO Port Interrupt #0 - DCD ioss_interrupts_gpio_1_IRQHandler ; GPIO Port Interrupt #1 - DCD ioss_interrupts_gpio_2_IRQHandler ; GPIO Port Interrupt #2 - DCD ioss_interrupts_gpio_3_IRQHandler ; GPIO Port Interrupt #3 - DCD ioss_interrupts_gpio_4_IRQHandler ; GPIO Port Interrupt #4 - DCD ioss_interrupts_gpio_5_IRQHandler ; GPIO Port Interrupt #5 - DCD ioss_interrupts_gpio_6_IRQHandler ; GPIO Port Interrupt #6 - DCD ioss_interrupts_gpio_7_IRQHandler ; GPIO Port Interrupt #7 - DCD ioss_interrupts_gpio_8_IRQHandler ; GPIO Port Interrupt #8 - DCD ioss_interrupts_gpio_9_IRQHandler ; GPIO Port Interrupt #9 - DCD ioss_interrupts_gpio_10_IRQHandler ; GPIO Port Interrupt #10 - DCD ioss_interrupts_gpio_11_IRQHandler ; GPIO Port Interrupt #11 - DCD ioss_interrupts_gpio_12_IRQHandler ; GPIO Port Interrupt #12 - DCD ioss_interrupts_gpio_13_IRQHandler ; GPIO Port Interrupt #13 - DCD ioss_interrupts_gpio_14_IRQHandler ; GPIO Port Interrupt #14 - DCD ioss_interrupt_gpio_IRQHandler ; GPIO All Ports - DCD ioss_interrupt_vdd_IRQHandler ; GPIO Supply Detect Interrupt - DCD lpcomp_interrupt_IRQHandler ; Low Power Comparator Interrupt - DCD scb_8_interrupt_IRQHandler ; Serial Communication Block #8 (DeepSleep capable) - DCD srss_interrupt_mcwdt_0_IRQHandler ; Multi Counter Watchdog Timer interrupt - DCD srss_interrupt_mcwdt_1_IRQHandler ; Multi Counter Watchdog Timer interrupt - DCD srss_interrupt_backup_IRQHandler ; Backup domain interrupt - DCD srss_interrupt_IRQHandler ; Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) - DCD cpuss_interrupts_ipc_0_IRQHandler ; CPUSS Inter Process Communication Interrupt #0 - DCD cpuss_interrupts_ipc_1_IRQHandler ; CPUSS Inter Process Communication Interrupt #1 - DCD cpuss_interrupts_ipc_2_IRQHandler ; CPUSS Inter Process Communication Interrupt #2 - DCD cpuss_interrupts_ipc_3_IRQHandler ; CPUSS Inter Process Communication Interrupt #3 - DCD cpuss_interrupts_ipc_4_IRQHandler ; CPUSS Inter Process Communication Interrupt #4 - DCD cpuss_interrupts_ipc_5_IRQHandler ; CPUSS Inter Process Communication Interrupt #5 - DCD cpuss_interrupts_ipc_6_IRQHandler ; CPUSS Inter Process Communication Interrupt #6 - DCD cpuss_interrupts_ipc_7_IRQHandler ; CPUSS Inter Process Communication Interrupt #7 - DCD cpuss_interrupts_ipc_8_IRQHandler ; CPUSS Inter Process Communication Interrupt #8 - DCD cpuss_interrupts_ipc_9_IRQHandler ; CPUSS Inter Process Communication Interrupt #9 - DCD cpuss_interrupts_ipc_10_IRQHandler ; CPUSS Inter Process Communication Interrupt #10 - DCD cpuss_interrupts_ipc_11_IRQHandler ; CPUSS Inter Process Communication Interrupt #11 - DCD cpuss_interrupts_ipc_12_IRQHandler ; CPUSS Inter Process Communication Interrupt #12 - DCD cpuss_interrupts_ipc_13_IRQHandler ; CPUSS Inter Process Communication Interrupt #13 - DCD cpuss_interrupts_ipc_14_IRQHandler ; CPUSS Inter Process Communication Interrupt #14 - DCD cpuss_interrupts_ipc_15_IRQHandler ; CPUSS Inter Process Communication Interrupt #15 - DCD scb_0_interrupt_IRQHandler ; Serial Communication Block #0 - DCD scb_1_interrupt_IRQHandler ; Serial Communication Block #1 - DCD scb_2_interrupt_IRQHandler ; Serial Communication Block #2 - DCD scb_3_interrupt_IRQHandler ; Serial Communication Block #3 - DCD scb_4_interrupt_IRQHandler ; Serial Communication Block #4 - DCD scb_5_interrupt_IRQHandler ; Serial Communication Block #5 - DCD scb_6_interrupt_IRQHandler ; Serial Communication Block #6 - DCD scb_7_interrupt_IRQHandler ; Serial Communication Block #7 - DCD scb_9_interrupt_IRQHandler ; Serial Communication Block #9 - DCD scb_10_interrupt_IRQHandler ; Serial Communication Block #10 - DCD scb_11_interrupt_IRQHandler ; Serial Communication Block #11 - DCD scb_12_interrupt_IRQHandler ; Serial Communication Block #12 - DCD csd_interrupt_IRQHandler ; CSD (Capsense) interrupt - DCD cpuss_interrupts_dmac_0_IRQHandler ; CPUSS DMAC, Channel #0 - DCD cpuss_interrupts_dmac_1_IRQHandler ; CPUSS DMAC, Channel #1 - DCD cpuss_interrupts_dmac_2_IRQHandler ; CPUSS DMAC, Channel #2 - DCD cpuss_interrupts_dmac_3_IRQHandler ; CPUSS DMAC, Channel #3 - DCD cpuss_interrupts_dw0_0_IRQHandler ; CPUSS DataWire #0, Channel #0 - DCD cpuss_interrupts_dw0_1_IRQHandler ; CPUSS DataWire #0, Channel #1 - DCD cpuss_interrupts_dw0_2_IRQHandler ; CPUSS DataWire #0, Channel #2 - DCD cpuss_interrupts_dw0_3_IRQHandler ; CPUSS DataWire #0, Channel #3 - DCD cpuss_interrupts_dw0_4_IRQHandler ; CPUSS DataWire #0, Channel #4 - DCD cpuss_interrupts_dw0_5_IRQHandler ; CPUSS DataWire #0, Channel #5 - DCD cpuss_interrupts_dw0_6_IRQHandler ; CPUSS DataWire #0, Channel #6 - DCD cpuss_interrupts_dw0_7_IRQHandler ; CPUSS DataWire #0, Channel #7 - DCD cpuss_interrupts_dw0_8_IRQHandler ; CPUSS DataWire #0, Channel #8 - DCD cpuss_interrupts_dw0_9_IRQHandler ; CPUSS DataWire #0, Channel #9 - DCD cpuss_interrupts_dw0_10_IRQHandler ; CPUSS DataWire #0, Channel #10 - DCD cpuss_interrupts_dw0_11_IRQHandler ; CPUSS DataWire #0, Channel #11 - DCD cpuss_interrupts_dw0_12_IRQHandler ; CPUSS DataWire #0, Channel #12 - DCD cpuss_interrupts_dw0_13_IRQHandler ; CPUSS DataWire #0, Channel #13 - DCD cpuss_interrupts_dw0_14_IRQHandler ; CPUSS DataWire #0, Channel #14 - DCD cpuss_interrupts_dw0_15_IRQHandler ; CPUSS DataWire #0, Channel #15 - DCD cpuss_interrupts_dw0_16_IRQHandler ; CPUSS DataWire #0, Channel #16 - DCD cpuss_interrupts_dw0_17_IRQHandler ; CPUSS DataWire #0, Channel #17 - DCD cpuss_interrupts_dw0_18_IRQHandler ; CPUSS DataWire #0, Channel #18 - DCD cpuss_interrupts_dw0_19_IRQHandler ; CPUSS DataWire #0, Channel #19 - DCD cpuss_interrupts_dw0_20_IRQHandler ; CPUSS DataWire #0, Channel #20 - DCD cpuss_interrupts_dw0_21_IRQHandler ; CPUSS DataWire #0, Channel #21 - DCD cpuss_interrupts_dw0_22_IRQHandler ; CPUSS DataWire #0, Channel #22 - DCD cpuss_interrupts_dw0_23_IRQHandler ; CPUSS DataWire #0, Channel #23 - DCD cpuss_interrupts_dw0_24_IRQHandler ; CPUSS DataWire #0, Channel #24 - DCD cpuss_interrupts_dw0_25_IRQHandler ; CPUSS DataWire #0, Channel #25 - DCD cpuss_interrupts_dw0_26_IRQHandler ; CPUSS DataWire #0, Channel #26 - DCD cpuss_interrupts_dw0_27_IRQHandler ; CPUSS DataWire #0, Channel #27 - DCD cpuss_interrupts_dw0_28_IRQHandler ; CPUSS DataWire #0, Channel #28 - DCD cpuss_interrupts_dw1_0_IRQHandler ; CPUSS DataWire #1, Channel #0 - DCD cpuss_interrupts_dw1_1_IRQHandler ; CPUSS DataWire #1, Channel #1 - DCD cpuss_interrupts_dw1_2_IRQHandler ; CPUSS DataWire #1, Channel #2 - DCD cpuss_interrupts_dw1_3_IRQHandler ; CPUSS DataWire #1, Channel #3 - DCD cpuss_interrupts_dw1_4_IRQHandler ; CPUSS DataWire #1, Channel #4 - DCD cpuss_interrupts_dw1_5_IRQHandler ; CPUSS DataWire #1, Channel #5 - DCD cpuss_interrupts_dw1_6_IRQHandler ; CPUSS DataWire #1, Channel #6 - DCD cpuss_interrupts_dw1_7_IRQHandler ; CPUSS DataWire #1, Channel #7 - DCD cpuss_interrupts_dw1_8_IRQHandler ; CPUSS DataWire #1, Channel #8 - DCD cpuss_interrupts_dw1_9_IRQHandler ; CPUSS DataWire #1, Channel #9 - DCD cpuss_interrupts_dw1_10_IRQHandler ; CPUSS DataWire #1, Channel #10 - DCD cpuss_interrupts_dw1_11_IRQHandler ; CPUSS DataWire #1, Channel #11 - DCD cpuss_interrupts_dw1_12_IRQHandler ; CPUSS DataWire #1, Channel #12 - DCD cpuss_interrupts_dw1_13_IRQHandler ; CPUSS DataWire #1, Channel #13 - DCD cpuss_interrupts_dw1_14_IRQHandler ; CPUSS DataWire #1, Channel #14 - DCD cpuss_interrupts_dw1_15_IRQHandler ; CPUSS DataWire #1, Channel #15 - DCD cpuss_interrupts_dw1_16_IRQHandler ; CPUSS DataWire #1, Channel #16 - DCD cpuss_interrupts_dw1_17_IRQHandler ; CPUSS DataWire #1, Channel #17 - DCD cpuss_interrupts_dw1_18_IRQHandler ; CPUSS DataWire #1, Channel #18 - DCD cpuss_interrupts_dw1_19_IRQHandler ; CPUSS DataWire #1, Channel #19 - DCD cpuss_interrupts_dw1_20_IRQHandler ; CPUSS DataWire #1, Channel #20 - DCD cpuss_interrupts_dw1_21_IRQHandler ; CPUSS DataWire #1, Channel #21 - DCD cpuss_interrupts_dw1_22_IRQHandler ; CPUSS DataWire #1, Channel #22 - DCD cpuss_interrupts_dw1_23_IRQHandler ; CPUSS DataWire #1, Channel #23 - DCD cpuss_interrupts_dw1_24_IRQHandler ; CPUSS DataWire #1, Channel #24 - DCD cpuss_interrupts_dw1_25_IRQHandler ; CPUSS DataWire #1, Channel #25 - DCD cpuss_interrupts_dw1_26_IRQHandler ; CPUSS DataWire #1, Channel #26 - DCD cpuss_interrupts_dw1_27_IRQHandler ; CPUSS DataWire #1, Channel #27 - DCD cpuss_interrupts_dw1_28_IRQHandler ; CPUSS DataWire #1, Channel #28 - DCD cpuss_interrupts_fault_0_IRQHandler ; CPUSS Fault Structure Interrupt #0 - DCD cpuss_interrupts_fault_1_IRQHandler ; CPUSS Fault Structure Interrupt #1 - DCD cpuss_interrupt_crypto_IRQHandler ; CRYPTO Accelerator Interrupt - DCD cpuss_interrupt_fm_IRQHandler ; FLASH Macro Interrupt - DCD cpuss_interrupts_cm4_fp_IRQHandler ; Floating Point operation fault - DCD cpuss_interrupts_cm0_cti_0_IRQHandler ; CM0+ CTI #0 - DCD cpuss_interrupts_cm0_cti_1_IRQHandler ; CM0+ CTI #1 - DCD cpuss_interrupts_cm4_cti_0_IRQHandler ; CM4 CTI #0 - DCD cpuss_interrupts_cm4_cti_1_IRQHandler ; CM4 CTI #1 - DCD tcpwm_0_interrupts_0_IRQHandler ; TCPWM #0, Counter #0 - DCD tcpwm_0_interrupts_1_IRQHandler ; TCPWM #0, Counter #1 - DCD tcpwm_0_interrupts_2_IRQHandler ; TCPWM #0, Counter #2 - DCD tcpwm_0_interrupts_3_IRQHandler ; TCPWM #0, Counter #3 - DCD tcpwm_0_interrupts_4_IRQHandler ; TCPWM #0, Counter #4 - DCD tcpwm_0_interrupts_5_IRQHandler ; TCPWM #0, Counter #5 - DCD tcpwm_0_interrupts_6_IRQHandler ; TCPWM #0, Counter #6 - DCD tcpwm_0_interrupts_7_IRQHandler ; TCPWM #0, Counter #7 - DCD tcpwm_1_interrupts_0_IRQHandler ; TCPWM #1, Counter #0 - DCD tcpwm_1_interrupts_1_IRQHandler ; TCPWM #1, Counter #1 - DCD tcpwm_1_interrupts_2_IRQHandler ; TCPWM #1, Counter #2 - DCD tcpwm_1_interrupts_3_IRQHandler ; TCPWM #1, Counter #3 - DCD tcpwm_1_interrupts_4_IRQHandler ; TCPWM #1, Counter #4 - DCD tcpwm_1_interrupts_5_IRQHandler ; TCPWM #1, Counter #5 - DCD tcpwm_1_interrupts_6_IRQHandler ; TCPWM #1, Counter #6 - DCD tcpwm_1_interrupts_7_IRQHandler ; TCPWM #1, Counter #7 - DCD tcpwm_1_interrupts_8_IRQHandler ; TCPWM #1, Counter #8 - DCD tcpwm_1_interrupts_9_IRQHandler ; TCPWM #1, Counter #9 - DCD tcpwm_1_interrupts_10_IRQHandler ; TCPWM #1, Counter #10 - DCD tcpwm_1_interrupts_11_IRQHandler ; TCPWM #1, Counter #11 - DCD tcpwm_1_interrupts_12_IRQHandler ; TCPWM #1, Counter #12 - DCD tcpwm_1_interrupts_13_IRQHandler ; TCPWM #1, Counter #13 - DCD tcpwm_1_interrupts_14_IRQHandler ; TCPWM #1, Counter #14 - DCD tcpwm_1_interrupts_15_IRQHandler ; TCPWM #1, Counter #15 - DCD tcpwm_1_interrupts_16_IRQHandler ; TCPWM #1, Counter #16 - DCD tcpwm_1_interrupts_17_IRQHandler ; TCPWM #1, Counter #17 - DCD tcpwm_1_interrupts_18_IRQHandler ; TCPWM #1, Counter #18 - DCD tcpwm_1_interrupts_19_IRQHandler ; TCPWM #1, Counter #19 - DCD tcpwm_1_interrupts_20_IRQHandler ; TCPWM #1, Counter #20 - DCD tcpwm_1_interrupts_21_IRQHandler ; TCPWM #1, Counter #21 - DCD tcpwm_1_interrupts_22_IRQHandler ; TCPWM #1, Counter #22 - DCD tcpwm_1_interrupts_23_IRQHandler ; TCPWM #1, Counter #23 - DCD pass_interrupt_sar_IRQHandler ; SAR ADC interrupt - DCD audioss_0_interrupt_i2s_IRQHandler ; I2S0 Audio interrupt - DCD audioss_0_interrupt_pdm_IRQHandler ; PDM0/PCM0 Audio interrupt - DCD audioss_1_interrupt_i2s_IRQHandler ; I2S1 Audio interrupt - DCD profile_interrupt_IRQHandler ; Energy Profiler interrupt - DCD smif_interrupt_IRQHandler ; Serial Memory Interface interrupt - DCD usb_interrupt_hi_IRQHandler ; USB Interrupt - DCD usb_interrupt_med_IRQHandler ; USB Interrupt - DCD usb_interrupt_lo_IRQHandler ; USB Interrupt - DCD sdhc_0_interrupt_wakeup_IRQHandler ; SDIO wakeup interrupt for mxsdhc - DCD sdhc_0_interrupt_general_IRQHandler ; Consolidated interrupt for mxsdhc for everything else - DCD sdhc_1_interrupt_wakeup_IRQHandler ; EEMC wakeup interrupt for mxsdhc, not used - DCD sdhc_1_interrupt_general_IRQHandler ; Consolidated interrupt for mxsdhc for everything else - -__Vectors_End - -__Vectors EQU __vector_table -__Vectors_Size EQU __Vectors_End - __Vectors - - SECTION .intvec_ram:DATA:REORDER:NOROOT(2) -__ramVectors - DS32 __Vectors_Size - - - THUMB - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default handlers -;; - PUBWEAK Default_Handler - SECTION .text:CODE:REORDER:NOROOT(2) -Default_Handler - B Default_Handler - - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Weak function for startup customization -;; -;; Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) -;; because this function is executed as the first instruction in the ResetHandler. -;; The PDL is also not initialized to use the proper register offsets. -;; The user of this function is responsible for initializing the PDL and resources before using them. -;; - PUBWEAK Cy_OnResetUser - SECTION .text:CODE:REORDER:NOROOT(2) -Cy_OnResetUser - BX LR - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Define strong version to return zero for -;; __iar_program_start to skip data sections -;; initialization. -;; - PUBLIC __low_level_init - SECTION .text:CODE:REORDER:NOROOT(2) -__low_level_init - MOVS R0, #0 - BX LR - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER:NOROOT(2) -Reset_Handler - - ; Define strong function for startup customization - LDR R0, =Cy_OnResetUser - BLX R0 - - ; Disable global interrupts - CPSID I - - ; Copy vectors from ROM to RAM - LDR r1, =__vector_table - LDR r0, =__ramVectors - LDR r2, =__Vectors_Size -intvec_copy - LDR r3, [r1] - STR r3, [r0] - ADDS r0, r0, #4 - ADDS r1, r1, #4 - SUBS r2, r2, #1 - CMP r2, #0 - BNE intvec_copy - - ; Update Vector Table Offset Register - LDR r0, =__ramVectors - LDR r1, =0xE000ED08 - STR r0, [r1] - dsb - - ; Initialize data sections - LDR R0, =__iar_data_init3 - BLX R0 - - LDR R0, =SystemInit - BLX R0 - - LDR R0, =__iar_program_start - BLX R0 - -; Should never get here -Cy_Main_Exited - B Cy_Main_Exited - - - PUBWEAK NMI_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -NMI_Handler - B NMI_Handler - - - PUBWEAK Cy_SysLib_FaultHandler - SECTION .text:CODE:REORDER:NOROOT(1) -Cy_SysLib_FaultHandler - B Cy_SysLib_FaultHandler - - PUBWEAK HardFault_Wrapper - SECTION .text:CODE:REORDER:NOROOT(1) -HardFault_Wrapper - IMPORT Cy_SysLib_FaultHandler - movs r0, #4 - mov r1, LR - tst r0, r1 - beq L_MSP - mrs r0, PSP - b L_API_call -L_MSP - mrs r0, MSP -L_API_call - ; Storing LR content for Creator call stack trace - push {LR} - bl Cy_SysLib_FaultHandler - - PUBWEAK HardFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -HardFault_Handler - B HardFault_Wrapper - - PUBWEAK MemManage_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -MemManage_Handler - B HardFault_Wrapper - - PUBWEAK BusFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -BusFault_Handler - B HardFault_Wrapper - - PUBWEAK UsageFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -UsageFault_Handler - B HardFault_Wrapper - - PUBWEAK SVC_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SVC_Handler - B SVC_Handler - - PUBWEAK DebugMon_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -DebugMon_Handler - B DebugMon_Handler - - PUBWEAK PendSV_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PendSV_Handler - B PendSV_Handler - - PUBWEAK SysTick_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SysTick_Handler - B SysTick_Handler - - - ; External interrupts - PUBWEAK ioss_interrupts_gpio_0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ioss_interrupts_gpio_0_IRQHandler - B ioss_interrupts_gpio_0_IRQHandler - - PUBWEAK ioss_interrupts_gpio_1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ioss_interrupts_gpio_1_IRQHandler - B ioss_interrupts_gpio_1_IRQHandler - - PUBWEAK ioss_interrupts_gpio_2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ioss_interrupts_gpio_2_IRQHandler - B ioss_interrupts_gpio_2_IRQHandler - - PUBWEAK ioss_interrupts_gpio_3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ioss_interrupts_gpio_3_IRQHandler - B ioss_interrupts_gpio_3_IRQHandler - - PUBWEAK ioss_interrupts_gpio_4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ioss_interrupts_gpio_4_IRQHandler - B ioss_interrupts_gpio_4_IRQHandler - - PUBWEAK ioss_interrupts_gpio_5_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ioss_interrupts_gpio_5_IRQHandler - B ioss_interrupts_gpio_5_IRQHandler - - PUBWEAK ioss_interrupts_gpio_6_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ioss_interrupts_gpio_6_IRQHandler - B ioss_interrupts_gpio_6_IRQHandler - - PUBWEAK ioss_interrupts_gpio_7_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ioss_interrupts_gpio_7_IRQHandler - B ioss_interrupts_gpio_7_IRQHandler - - PUBWEAK ioss_interrupts_gpio_8_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ioss_interrupts_gpio_8_IRQHandler - B ioss_interrupts_gpio_8_IRQHandler - - PUBWEAK ioss_interrupts_gpio_9_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ioss_interrupts_gpio_9_IRQHandler - B ioss_interrupts_gpio_9_IRQHandler - - PUBWEAK ioss_interrupts_gpio_10_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ioss_interrupts_gpio_10_IRQHandler - B ioss_interrupts_gpio_10_IRQHandler - - PUBWEAK ioss_interrupts_gpio_11_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ioss_interrupts_gpio_11_IRQHandler - B ioss_interrupts_gpio_11_IRQHandler - - PUBWEAK ioss_interrupts_gpio_12_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ioss_interrupts_gpio_12_IRQHandler - B ioss_interrupts_gpio_12_IRQHandler - - PUBWEAK ioss_interrupts_gpio_13_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ioss_interrupts_gpio_13_IRQHandler - B ioss_interrupts_gpio_13_IRQHandler - - PUBWEAK ioss_interrupts_gpio_14_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ioss_interrupts_gpio_14_IRQHandler - B ioss_interrupts_gpio_14_IRQHandler - - PUBWEAK ioss_interrupt_gpio_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ioss_interrupt_gpio_IRQHandler - B ioss_interrupt_gpio_IRQHandler - - PUBWEAK ioss_interrupt_vdd_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ioss_interrupt_vdd_IRQHandler - B ioss_interrupt_vdd_IRQHandler - - PUBWEAK lpcomp_interrupt_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -lpcomp_interrupt_IRQHandler - B lpcomp_interrupt_IRQHandler - - PUBWEAK scb_8_interrupt_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -scb_8_interrupt_IRQHandler - B scb_8_interrupt_IRQHandler - - PUBWEAK srss_interrupt_mcwdt_0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -srss_interrupt_mcwdt_0_IRQHandler - B srss_interrupt_mcwdt_0_IRQHandler - - PUBWEAK srss_interrupt_mcwdt_1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -srss_interrupt_mcwdt_1_IRQHandler - B srss_interrupt_mcwdt_1_IRQHandler - - PUBWEAK srss_interrupt_backup_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -srss_interrupt_backup_IRQHandler - B srss_interrupt_backup_IRQHandler - - PUBWEAK srss_interrupt_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -srss_interrupt_IRQHandler - B srss_interrupt_IRQHandler - - PUBWEAK cpuss_interrupts_ipc_0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_ipc_0_IRQHandler - B cpuss_interrupts_ipc_0_IRQHandler - - PUBWEAK cpuss_interrupts_ipc_1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_ipc_1_IRQHandler - B cpuss_interrupts_ipc_1_IRQHandler - - PUBWEAK cpuss_interrupts_ipc_2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_ipc_2_IRQHandler - B cpuss_interrupts_ipc_2_IRQHandler - - PUBWEAK cpuss_interrupts_ipc_3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_ipc_3_IRQHandler - B cpuss_interrupts_ipc_3_IRQHandler - - PUBWEAK cpuss_interrupts_ipc_4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_ipc_4_IRQHandler - B cpuss_interrupts_ipc_4_IRQHandler - - PUBWEAK cpuss_interrupts_ipc_5_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_ipc_5_IRQHandler - B cpuss_interrupts_ipc_5_IRQHandler - - PUBWEAK cpuss_interrupts_ipc_6_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_ipc_6_IRQHandler - B cpuss_interrupts_ipc_6_IRQHandler - - PUBWEAK cpuss_interrupts_ipc_7_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_ipc_7_IRQHandler - B cpuss_interrupts_ipc_7_IRQHandler - - PUBWEAK cpuss_interrupts_ipc_8_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_ipc_8_IRQHandler - B cpuss_interrupts_ipc_8_IRQHandler - - PUBWEAK cpuss_interrupts_ipc_9_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_ipc_9_IRQHandler - B cpuss_interrupts_ipc_9_IRQHandler - - PUBWEAK cpuss_interrupts_ipc_10_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_ipc_10_IRQHandler - B cpuss_interrupts_ipc_10_IRQHandler - - PUBWEAK cpuss_interrupts_ipc_11_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_ipc_11_IRQHandler - B cpuss_interrupts_ipc_11_IRQHandler - - PUBWEAK cpuss_interrupts_ipc_12_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_ipc_12_IRQHandler - B cpuss_interrupts_ipc_12_IRQHandler - - PUBWEAK cpuss_interrupts_ipc_13_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_ipc_13_IRQHandler - B cpuss_interrupts_ipc_13_IRQHandler - - PUBWEAK cpuss_interrupts_ipc_14_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_ipc_14_IRQHandler - B cpuss_interrupts_ipc_14_IRQHandler - - PUBWEAK cpuss_interrupts_ipc_15_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_ipc_15_IRQHandler - B cpuss_interrupts_ipc_15_IRQHandler - - PUBWEAK scb_0_interrupt_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -scb_0_interrupt_IRQHandler - B scb_0_interrupt_IRQHandler - - PUBWEAK scb_1_interrupt_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -scb_1_interrupt_IRQHandler - B scb_1_interrupt_IRQHandler - - PUBWEAK scb_2_interrupt_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -scb_2_interrupt_IRQHandler - B scb_2_interrupt_IRQHandler - - PUBWEAK scb_3_interrupt_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -scb_3_interrupt_IRQHandler - B scb_3_interrupt_IRQHandler - - PUBWEAK scb_4_interrupt_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -scb_4_interrupt_IRQHandler - B scb_4_interrupt_IRQHandler - - PUBWEAK scb_5_interrupt_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -scb_5_interrupt_IRQHandler - B scb_5_interrupt_IRQHandler - - PUBWEAK scb_6_interrupt_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -scb_6_interrupt_IRQHandler - B scb_6_interrupt_IRQHandler - - PUBWEAK scb_7_interrupt_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -scb_7_interrupt_IRQHandler - B scb_7_interrupt_IRQHandler - - PUBWEAK scb_9_interrupt_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -scb_9_interrupt_IRQHandler - B scb_9_interrupt_IRQHandler - - PUBWEAK scb_10_interrupt_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -scb_10_interrupt_IRQHandler - B scb_10_interrupt_IRQHandler - - PUBWEAK scb_11_interrupt_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -scb_11_interrupt_IRQHandler - B scb_11_interrupt_IRQHandler - - PUBWEAK scb_12_interrupt_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -scb_12_interrupt_IRQHandler - B scb_12_interrupt_IRQHandler - - PUBWEAK csd_interrupt_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -csd_interrupt_IRQHandler - B csd_interrupt_IRQHandler - - PUBWEAK cpuss_interrupts_dmac_0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dmac_0_IRQHandler - B cpuss_interrupts_dmac_0_IRQHandler - - PUBWEAK cpuss_interrupts_dmac_1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dmac_1_IRQHandler - B cpuss_interrupts_dmac_1_IRQHandler - - PUBWEAK cpuss_interrupts_dmac_2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dmac_2_IRQHandler - B cpuss_interrupts_dmac_2_IRQHandler - - PUBWEAK cpuss_interrupts_dmac_3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dmac_3_IRQHandler - B cpuss_interrupts_dmac_3_IRQHandler - - PUBWEAK cpuss_interrupts_dw0_0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw0_0_IRQHandler - B cpuss_interrupts_dw0_0_IRQHandler - - PUBWEAK cpuss_interrupts_dw0_1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw0_1_IRQHandler - B cpuss_interrupts_dw0_1_IRQHandler - - PUBWEAK cpuss_interrupts_dw0_2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw0_2_IRQHandler - B cpuss_interrupts_dw0_2_IRQHandler - - PUBWEAK cpuss_interrupts_dw0_3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw0_3_IRQHandler - B cpuss_interrupts_dw0_3_IRQHandler - - PUBWEAK cpuss_interrupts_dw0_4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw0_4_IRQHandler - B cpuss_interrupts_dw0_4_IRQHandler - - PUBWEAK cpuss_interrupts_dw0_5_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw0_5_IRQHandler - B cpuss_interrupts_dw0_5_IRQHandler - - PUBWEAK cpuss_interrupts_dw0_6_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw0_6_IRQHandler - B cpuss_interrupts_dw0_6_IRQHandler - - PUBWEAK cpuss_interrupts_dw0_7_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw0_7_IRQHandler - B cpuss_interrupts_dw0_7_IRQHandler - - PUBWEAK cpuss_interrupts_dw0_8_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw0_8_IRQHandler - B cpuss_interrupts_dw0_8_IRQHandler - - PUBWEAK cpuss_interrupts_dw0_9_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw0_9_IRQHandler - B cpuss_interrupts_dw0_9_IRQHandler - - PUBWEAK cpuss_interrupts_dw0_10_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw0_10_IRQHandler - B cpuss_interrupts_dw0_10_IRQHandler - - PUBWEAK cpuss_interrupts_dw0_11_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw0_11_IRQHandler - B cpuss_interrupts_dw0_11_IRQHandler - - PUBWEAK cpuss_interrupts_dw0_12_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw0_12_IRQHandler - B cpuss_interrupts_dw0_12_IRQHandler - - PUBWEAK cpuss_interrupts_dw0_13_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw0_13_IRQHandler - B cpuss_interrupts_dw0_13_IRQHandler - - PUBWEAK cpuss_interrupts_dw0_14_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw0_14_IRQHandler - B cpuss_interrupts_dw0_14_IRQHandler - - PUBWEAK cpuss_interrupts_dw0_15_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw0_15_IRQHandler - B cpuss_interrupts_dw0_15_IRQHandler - - PUBWEAK cpuss_interrupts_dw0_16_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw0_16_IRQHandler - B cpuss_interrupts_dw0_16_IRQHandler - - PUBWEAK cpuss_interrupts_dw0_17_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw0_17_IRQHandler - B cpuss_interrupts_dw0_17_IRQHandler - - PUBWEAK cpuss_interrupts_dw0_18_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw0_18_IRQHandler - B cpuss_interrupts_dw0_18_IRQHandler - - PUBWEAK cpuss_interrupts_dw0_19_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw0_19_IRQHandler - B cpuss_interrupts_dw0_19_IRQHandler - - PUBWEAK cpuss_interrupts_dw0_20_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw0_20_IRQHandler - B cpuss_interrupts_dw0_20_IRQHandler - - PUBWEAK cpuss_interrupts_dw0_21_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw0_21_IRQHandler - B cpuss_interrupts_dw0_21_IRQHandler - - PUBWEAK cpuss_interrupts_dw0_22_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw0_22_IRQHandler - B cpuss_interrupts_dw0_22_IRQHandler - - PUBWEAK cpuss_interrupts_dw0_23_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw0_23_IRQHandler - B cpuss_interrupts_dw0_23_IRQHandler - - PUBWEAK cpuss_interrupts_dw0_24_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw0_24_IRQHandler - B cpuss_interrupts_dw0_24_IRQHandler - - PUBWEAK cpuss_interrupts_dw0_25_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw0_25_IRQHandler - B cpuss_interrupts_dw0_25_IRQHandler - - PUBWEAK cpuss_interrupts_dw0_26_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw0_26_IRQHandler - B cpuss_interrupts_dw0_26_IRQHandler - - PUBWEAK cpuss_interrupts_dw0_27_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw0_27_IRQHandler - B cpuss_interrupts_dw0_27_IRQHandler - - PUBWEAK cpuss_interrupts_dw0_28_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw0_28_IRQHandler - B cpuss_interrupts_dw0_28_IRQHandler - - PUBWEAK cpuss_interrupts_dw1_0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw1_0_IRQHandler - B cpuss_interrupts_dw1_0_IRQHandler - - PUBWEAK cpuss_interrupts_dw1_1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw1_1_IRQHandler - B cpuss_interrupts_dw1_1_IRQHandler - - PUBWEAK cpuss_interrupts_dw1_2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw1_2_IRQHandler - B cpuss_interrupts_dw1_2_IRQHandler - - PUBWEAK cpuss_interrupts_dw1_3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw1_3_IRQHandler - B cpuss_interrupts_dw1_3_IRQHandler - - PUBWEAK cpuss_interrupts_dw1_4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw1_4_IRQHandler - B cpuss_interrupts_dw1_4_IRQHandler - - PUBWEAK cpuss_interrupts_dw1_5_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw1_5_IRQHandler - B cpuss_interrupts_dw1_5_IRQHandler - - PUBWEAK cpuss_interrupts_dw1_6_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw1_6_IRQHandler - B cpuss_interrupts_dw1_6_IRQHandler - - PUBWEAK cpuss_interrupts_dw1_7_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw1_7_IRQHandler - B cpuss_interrupts_dw1_7_IRQHandler - - PUBWEAK cpuss_interrupts_dw1_8_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw1_8_IRQHandler - B cpuss_interrupts_dw1_8_IRQHandler - - PUBWEAK cpuss_interrupts_dw1_9_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw1_9_IRQHandler - B cpuss_interrupts_dw1_9_IRQHandler - - PUBWEAK cpuss_interrupts_dw1_10_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw1_10_IRQHandler - B cpuss_interrupts_dw1_10_IRQHandler - - PUBWEAK cpuss_interrupts_dw1_11_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw1_11_IRQHandler - B cpuss_interrupts_dw1_11_IRQHandler - - PUBWEAK cpuss_interrupts_dw1_12_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw1_12_IRQHandler - B cpuss_interrupts_dw1_12_IRQHandler - - PUBWEAK cpuss_interrupts_dw1_13_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw1_13_IRQHandler - B cpuss_interrupts_dw1_13_IRQHandler - - PUBWEAK cpuss_interrupts_dw1_14_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw1_14_IRQHandler - B cpuss_interrupts_dw1_14_IRQHandler - - PUBWEAK cpuss_interrupts_dw1_15_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw1_15_IRQHandler - B cpuss_interrupts_dw1_15_IRQHandler - - PUBWEAK cpuss_interrupts_dw1_16_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw1_16_IRQHandler - B cpuss_interrupts_dw1_16_IRQHandler - - PUBWEAK cpuss_interrupts_dw1_17_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw1_17_IRQHandler - B cpuss_interrupts_dw1_17_IRQHandler - - PUBWEAK cpuss_interrupts_dw1_18_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw1_18_IRQHandler - B cpuss_interrupts_dw1_18_IRQHandler - - PUBWEAK cpuss_interrupts_dw1_19_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw1_19_IRQHandler - B cpuss_interrupts_dw1_19_IRQHandler - - PUBWEAK cpuss_interrupts_dw1_20_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw1_20_IRQHandler - B cpuss_interrupts_dw1_20_IRQHandler - - PUBWEAK cpuss_interrupts_dw1_21_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw1_21_IRQHandler - B cpuss_interrupts_dw1_21_IRQHandler - - PUBWEAK cpuss_interrupts_dw1_22_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw1_22_IRQHandler - B cpuss_interrupts_dw1_22_IRQHandler - - PUBWEAK cpuss_interrupts_dw1_23_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw1_23_IRQHandler - B cpuss_interrupts_dw1_23_IRQHandler - - PUBWEAK cpuss_interrupts_dw1_24_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw1_24_IRQHandler - B cpuss_interrupts_dw1_24_IRQHandler - - PUBWEAK cpuss_interrupts_dw1_25_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw1_25_IRQHandler - B cpuss_interrupts_dw1_25_IRQHandler - - PUBWEAK cpuss_interrupts_dw1_26_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw1_26_IRQHandler - B cpuss_interrupts_dw1_26_IRQHandler - - PUBWEAK cpuss_interrupts_dw1_27_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw1_27_IRQHandler - B cpuss_interrupts_dw1_27_IRQHandler - - PUBWEAK cpuss_interrupts_dw1_28_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw1_28_IRQHandler - B cpuss_interrupts_dw1_28_IRQHandler - - PUBWEAK cpuss_interrupts_fault_0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_fault_0_IRQHandler - B cpuss_interrupts_fault_0_IRQHandler - - PUBWEAK cpuss_interrupts_fault_1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_fault_1_IRQHandler - B cpuss_interrupts_fault_1_IRQHandler - - PUBWEAK cpuss_interrupt_crypto_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupt_crypto_IRQHandler - B cpuss_interrupt_crypto_IRQHandler - - PUBWEAK cpuss_interrupt_fm_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupt_fm_IRQHandler - B cpuss_interrupt_fm_IRQHandler - - PUBWEAK cpuss_interrupts_cm4_fp_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_cm4_fp_IRQHandler - B cpuss_interrupts_cm4_fp_IRQHandler - - PUBWEAK cpuss_interrupts_cm0_cti_0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_cm0_cti_0_IRQHandler - B cpuss_interrupts_cm0_cti_0_IRQHandler - - PUBWEAK cpuss_interrupts_cm0_cti_1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_cm0_cti_1_IRQHandler - B cpuss_interrupts_cm0_cti_1_IRQHandler - - PUBWEAK cpuss_interrupts_cm4_cti_0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_cm4_cti_0_IRQHandler - B cpuss_interrupts_cm4_cti_0_IRQHandler - - PUBWEAK cpuss_interrupts_cm4_cti_1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_cm4_cti_1_IRQHandler - B cpuss_interrupts_cm4_cti_1_IRQHandler - - PUBWEAK tcpwm_0_interrupts_0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_0_interrupts_0_IRQHandler - B tcpwm_0_interrupts_0_IRQHandler - - PUBWEAK tcpwm_0_interrupts_1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_0_interrupts_1_IRQHandler - B tcpwm_0_interrupts_1_IRQHandler - - PUBWEAK tcpwm_0_interrupts_2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_0_interrupts_2_IRQHandler - B tcpwm_0_interrupts_2_IRQHandler - - PUBWEAK tcpwm_0_interrupts_3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_0_interrupts_3_IRQHandler - B tcpwm_0_interrupts_3_IRQHandler - - PUBWEAK tcpwm_0_interrupts_4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_0_interrupts_4_IRQHandler - B tcpwm_0_interrupts_4_IRQHandler - - PUBWEAK tcpwm_0_interrupts_5_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_0_interrupts_5_IRQHandler - B tcpwm_0_interrupts_5_IRQHandler - - PUBWEAK tcpwm_0_interrupts_6_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_0_interrupts_6_IRQHandler - B tcpwm_0_interrupts_6_IRQHandler - - PUBWEAK tcpwm_0_interrupts_7_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_0_interrupts_7_IRQHandler - B tcpwm_0_interrupts_7_IRQHandler - - PUBWEAK tcpwm_1_interrupts_0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_1_interrupts_0_IRQHandler - B tcpwm_1_interrupts_0_IRQHandler - - PUBWEAK tcpwm_1_interrupts_1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_1_interrupts_1_IRQHandler - B tcpwm_1_interrupts_1_IRQHandler - - PUBWEAK tcpwm_1_interrupts_2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_1_interrupts_2_IRQHandler - B tcpwm_1_interrupts_2_IRQHandler - - PUBWEAK tcpwm_1_interrupts_3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_1_interrupts_3_IRQHandler - B tcpwm_1_interrupts_3_IRQHandler - - PUBWEAK tcpwm_1_interrupts_4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_1_interrupts_4_IRQHandler - B tcpwm_1_interrupts_4_IRQHandler - - PUBWEAK tcpwm_1_interrupts_5_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_1_interrupts_5_IRQHandler - B tcpwm_1_interrupts_5_IRQHandler - - PUBWEAK tcpwm_1_interrupts_6_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_1_interrupts_6_IRQHandler - B tcpwm_1_interrupts_6_IRQHandler - - PUBWEAK tcpwm_1_interrupts_7_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_1_interrupts_7_IRQHandler - B tcpwm_1_interrupts_7_IRQHandler - - PUBWEAK tcpwm_1_interrupts_8_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_1_interrupts_8_IRQHandler - B tcpwm_1_interrupts_8_IRQHandler - - PUBWEAK tcpwm_1_interrupts_9_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_1_interrupts_9_IRQHandler - B tcpwm_1_interrupts_9_IRQHandler - - PUBWEAK tcpwm_1_interrupts_10_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_1_interrupts_10_IRQHandler - B tcpwm_1_interrupts_10_IRQHandler - - PUBWEAK tcpwm_1_interrupts_11_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_1_interrupts_11_IRQHandler - B tcpwm_1_interrupts_11_IRQHandler - - PUBWEAK tcpwm_1_interrupts_12_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_1_interrupts_12_IRQHandler - B tcpwm_1_interrupts_12_IRQHandler - - PUBWEAK tcpwm_1_interrupts_13_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_1_interrupts_13_IRQHandler - B tcpwm_1_interrupts_13_IRQHandler - - PUBWEAK tcpwm_1_interrupts_14_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_1_interrupts_14_IRQHandler - B tcpwm_1_interrupts_14_IRQHandler - - PUBWEAK tcpwm_1_interrupts_15_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_1_interrupts_15_IRQHandler - B tcpwm_1_interrupts_15_IRQHandler - - PUBWEAK tcpwm_1_interrupts_16_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_1_interrupts_16_IRQHandler - B tcpwm_1_interrupts_16_IRQHandler - - PUBWEAK tcpwm_1_interrupts_17_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_1_interrupts_17_IRQHandler - B tcpwm_1_interrupts_17_IRQHandler - - PUBWEAK tcpwm_1_interrupts_18_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_1_interrupts_18_IRQHandler - B tcpwm_1_interrupts_18_IRQHandler - - PUBWEAK tcpwm_1_interrupts_19_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_1_interrupts_19_IRQHandler - B tcpwm_1_interrupts_19_IRQHandler - - PUBWEAK tcpwm_1_interrupts_20_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_1_interrupts_20_IRQHandler - B tcpwm_1_interrupts_20_IRQHandler - - PUBWEAK tcpwm_1_interrupts_21_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_1_interrupts_21_IRQHandler - B tcpwm_1_interrupts_21_IRQHandler - - PUBWEAK tcpwm_1_interrupts_22_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_1_interrupts_22_IRQHandler - B tcpwm_1_interrupts_22_IRQHandler - - PUBWEAK tcpwm_1_interrupts_23_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_1_interrupts_23_IRQHandler - B tcpwm_1_interrupts_23_IRQHandler - - PUBWEAK pass_interrupt_sar_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -pass_interrupt_sar_IRQHandler - B pass_interrupt_sar_IRQHandler - - PUBWEAK audioss_0_interrupt_i2s_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -audioss_0_interrupt_i2s_IRQHandler - B audioss_0_interrupt_i2s_IRQHandler - - PUBWEAK audioss_0_interrupt_pdm_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -audioss_0_interrupt_pdm_IRQHandler - B audioss_0_interrupt_pdm_IRQHandler - - PUBWEAK audioss_1_interrupt_i2s_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -audioss_1_interrupt_i2s_IRQHandler - B audioss_1_interrupt_i2s_IRQHandler - - PUBWEAK profile_interrupt_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -profile_interrupt_IRQHandler - B profile_interrupt_IRQHandler - - PUBWEAK smif_interrupt_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -smif_interrupt_IRQHandler - B smif_interrupt_IRQHandler - - PUBWEAK usb_interrupt_hi_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -usb_interrupt_hi_IRQHandler - B usb_interrupt_hi_IRQHandler - - PUBWEAK usb_interrupt_med_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -usb_interrupt_med_IRQHandler - B usb_interrupt_med_IRQHandler - - PUBWEAK usb_interrupt_lo_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -usb_interrupt_lo_IRQHandler - B usb_interrupt_lo_IRQHandler - - PUBWEAK sdhc_0_interrupt_wakeup_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -sdhc_0_interrupt_wakeup_IRQHandler - B sdhc_0_interrupt_wakeup_IRQHandler - - PUBWEAK sdhc_0_interrupt_general_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -sdhc_0_interrupt_general_IRQHandler - B sdhc_0_interrupt_general_IRQHandler - - PUBWEAK sdhc_1_interrupt_wakeup_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -sdhc_1_interrupt_wakeup_IRQHandler - B sdhc_1_interrupt_wakeup_IRQHandler - - PUBWEAK sdhc_1_interrupt_general_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -sdhc_1_interrupt_general_IRQHandler - B sdhc_1_interrupt_general_IRQHandler - - - END - - -; [] END OF FILE diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/device/COMPONENT_CM4/system_psoc6_cm4.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/device/COMPONENT_CM4/system_psoc6_cm4.c deleted file mode 100644 index 7800d6b2ef..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/device/COMPONENT_CM4/system_psoc6_cm4.c +++ /dev/null @@ -1,390 +0,0 @@ -/***************************************************************************//** -* \file system_psoc6_cm4.c -* \version 2.70 -* -* The device system-source file. -* -******************************************************************************** -* \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ - -#include -#include "system_psoc6.h" -#include "cy_device.h" -#include "cy_device_headers.h" -#include "cy_syslib.h" -#include "cy_sysclk.h" -#include "cy_wdt.h" - -#if !defined(CY_IPC_DEFAULT_CFG_DISABLE) - #include "cy_ipc_sema.h" - #include "cy_ipc_pipe.h" - #include "cy_ipc_drv.h" - - #if defined(CY_DEVICE_PSOC6ABLE2) - #include "cy_flash.h" - #endif /* defined(CY_DEVICE_PSOC6ABLE2) */ -#endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */ - - -/******************************************************************************* -* SystemCoreClockUpdate() -*******************************************************************************/ - -/** Default HFClk frequency in Hz */ -#define CY_CLK_HFCLK0_FREQ_HZ_DEFAULT (8000000UL) - -/** Default PeriClk frequency in Hz */ -#define CY_CLK_PERICLK_FREQ_HZ_DEFAULT (4000000UL) - -/** Default FastClk system core frequency in Hz */ -#define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT (8000000UL) - - -/** -* Holds the SlowClk (Cortex-M0+) or FastClk (Cortex-M4) system core clock, -* which is the system clock frequency supplied to the SysTick timer and the -* processor core clock. -* This variable implements CMSIS Core global variable. -* Refer to the [CMSIS documentation] -* (http://www.keil.com/pack/doc/CMSIS/Core/html/group__system__init__gr.html "System and Clock Configuration") -* for more details. -* This variable can be used by debuggers to query the frequency -* of the debug timer or to configure the trace clock speed. -* -* \attention Compilers must be configured to avoid removing this variable in case -* the application program is not using it. Debugging systems require the variable -* to be physically present in memory so that it can be examined to configure the debugger. */ -uint32_t SystemCoreClock = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT; - -/** Holds the HFClk0 clock frequency. Updated by \ref SystemCoreClockUpdate(). */ -uint32_t cy_Hfclk0FreqHz = CY_CLK_HFCLK0_FREQ_HZ_DEFAULT; - -/** Holds the PeriClk clock frequency. Updated by \ref SystemCoreClockUpdate(). */ -uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT; - -/** Holds the Alternate high frequency clock in Hz. Updated by \ref Cy_BLE_EcoConfigure(). */ -uint32_t cy_BleEcoClockFreqHz = 0UL; - -/* SCB->CPACR */ -#define SCB_CPACR_CP10_CP11_ENABLE (0xFUL << 20u) - - -/******************************************************************************* -* SystemInit() -*******************************************************************************/ - -/* CLK_FLL_CONFIG default values */ -#define CY_FB_CLK_FLL_CONFIG_VALUE (0x01000000u) -#define CY_FB_CLK_FLL_CONFIG2_VALUE (0x00020001u) -#define CY_FB_CLK_FLL_CONFIG3_VALUE (0x00002800u) -#define CY_FB_CLK_FLL_CONFIG4_VALUE (0x000000FFu) - -/* IPC_STRUCT7->DATA configuration */ -#define CY_STARTUP_CM0_DP_STATE (0x2uL) -#define CY_STARTUP_IPC7_DP_OFFSET (0x28u) - - -/******************************************************************************* -* SystemCoreClockUpdate (void) -*******************************************************************************/ - -/* Do not use these definitions directly in your application */ -#define CY_DELAY_MS_OVERFLOW_THRESHOLD (0x8000u) -#define CY_DELAY_1K_THRESHOLD (1000u) -#define CY_DELAY_1M_THRESHOLD (1000000u) - -uint32_t cy_delayFreqKhz = CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1K_THRESHOLD); - -uint8_t cy_delayFreqMhz = (uint8_t)CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1M_THRESHOLD); - -uint32_t cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * - CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1K_THRESHOLD); - - -/******************************************************************************* -* Function Name: SystemInit -****************************************************************************//** -* \cond -* Initializes the system: -* - Restores FLL registers to the default state for single core devices. -* - Unlocks and disables WDT. -* - Calls Cy_PDL_Init() function to define the driver library. -* - Calls the Cy_SystemInit() function, if compiled from PSoC Creator. -* - Calls \ref SystemCoreClockUpdate(). -* \endcond -*******************************************************************************/ -void SystemInit(void) -{ - Cy_PDL_Init(CY_DEVICE_CFG); - -#ifdef __CM0P_PRESENT - #if (__CM0P_PRESENT == 0) - /* Restore FLL registers to the default state as they are not restored by the ROM code */ - uint32_t copy = SRSS->CLK_FLL_CONFIG; - copy &= ~SRSS_CLK_FLL_CONFIG_FLL_ENABLE_Msk; - SRSS->CLK_FLL_CONFIG = copy; - - copy = SRSS->CLK_ROOT_SELECT[0u]; - copy &= ~SRSS_CLK_ROOT_SELECT_ROOT_DIV_Msk; /* Set ROOT_DIV = 0*/ - SRSS->CLK_ROOT_SELECT[0u] = copy; - - SRSS->CLK_FLL_CONFIG = CY_FB_CLK_FLL_CONFIG_VALUE; - SRSS->CLK_FLL_CONFIG2 = CY_FB_CLK_FLL_CONFIG2_VALUE; - SRSS->CLK_FLL_CONFIG3 = CY_FB_CLK_FLL_CONFIG3_VALUE; - SRSS->CLK_FLL_CONFIG4 = CY_FB_CLK_FLL_CONFIG4_VALUE; - - /* Unlock and disable WDT */ - Cy_WDT_Unlock(); - Cy_WDT_Disable(); - #endif /* (__CM0P_PRESENT == 0) */ -#endif /* __CM0P_PRESENT */ - - Cy_SystemInit(); - SystemCoreClockUpdate(); - -#ifdef __CM0P_PRESENT - #if (__CM0P_PRESENT == 0) - /* Configure data register (as CM0p in deep sleep state) of IPC structure #7, reserved for the Deep-Sleep operations. */ - REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = (CY_STARTUP_CM0_DP_STATE << - CY_STARTUP_IPC7_DP_OFFSET); - - /* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering. */ - REG_IPC_STRUCT_RELEASE(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = 0UL; - #endif /* (__CM0P_PRESENT == 0) */ -#endif /* __CM0P_PRESENT */ - -#if !defined(CY_IPC_DEFAULT_CFG_DISABLE) - -#ifdef __CM0P_PRESENT - #if (__CM0P_PRESENT == 0) - /* Allocate and initialize semaphores for the system operations. */ - static uint32_t ipcSemaArray[CY_IPC_SEMA_COUNT / CY_IPC_SEMA_PER_WORD]; - (void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, CY_IPC_SEMA_COUNT, ipcSemaArray); - #else - (void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, 0ul, NULL); - #endif /* (__CM0P_PRESENT) */ -#else - (void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, 0ul, NULL); -#endif /* __CM0P_PRESENT */ - - - /******************************************************************************** - * - * Initializes the system pipes. The system pipes are used by BLE and Flash. - * - * If the default startup file is not used, or SystemInit() is not called in your - * project, call the following three functions prior to executing any flash or - * EmEEPROM write or erase operation: - * -# Cy_IPC_Sema_Init() - * -# Cy_IPC_Pipe_Config() - * -# Cy_IPC_Pipe_Init() - * -# Cy_Flash_Init() - * - *******************************************************************************/ - /* Create an array of endpoint structures */ - static cy_stc_ipc_pipe_ep_t systemIpcPipeEpArray[CY_IPC_MAX_ENDPOINTS]; - - Cy_IPC_Pipe_Config(systemIpcPipeEpArray); - - static cy_ipc_pipe_callback_ptr_t systemIpcPipeSysCbArray[CY_SYS_CYPIPE_CLIENT_CNT]; - - static const cy_stc_ipc_pipe_config_t systemIpcPipeConfigCm4 = - { - /* .ep0ConfigData */ - { - /* .ipcNotifierNumber */ CY_IPC_INTR_CYPIPE_EP0, - /* .ipcNotifierPriority */ CY_SYS_INTR_CYPIPE_PRIOR_EP0, - /* .ipcNotifierMuxNumber */ CY_SYS_INTR_CYPIPE_MUX_EP0, - /* .epAddress */ CY_IPC_EP_CYPIPE_CM0_ADDR, - /* .epConfig */ CY_SYS_CYPIPE_CONFIG_EP0 - }, - /* .ep1ConfigData */ - { - /* .ipcNotifierNumber */ CY_IPC_INTR_CYPIPE_EP1, - /* .ipcNotifierPriority */ CY_SYS_INTR_CYPIPE_PRIOR_EP1, - /* .ipcNotifierMuxNumber */ 0u, - /* .epAddress */ CY_IPC_EP_CYPIPE_CM4_ADDR, - /* .epConfig */ CY_SYS_CYPIPE_CONFIG_EP1 - }, - /* .endpointClientsCount */ CY_SYS_CYPIPE_CLIENT_CNT, - /* .endpointsCallbacksArray */ systemIpcPipeSysCbArray, - /* .userPipeIsrHandler */ &Cy_SysIpcPipeIsrCm4 - }; - - Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm4); - -#if defined(CY_DEVICE_PSOC6ABLE2) - Cy_Flash_Init(); -#endif /* defined(CY_DEVICE_PSOC6ABLE2) */ - -#endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */ -} - - -/******************************************************************************* -* Function Name: Cy_SystemInit -****************************************************************************//** -* -* The function is called during device startup. Once project compiled as part of -* the PSoC Creator project, the Cy_SystemInit() function is generated by the -* PSoC Creator. -* -* The function generated by PSoC Creator performs all of the necessary device -* configuration based on the design settings. This includes settings from the -* Design Wide Resources (DWR) such as Clocks and Pins as well as any component -* configuration that is necessary. -* -*******************************************************************************/ -__WEAK void Cy_SystemInit(void) -{ - /* Empty weak function. The actual implementation to be in the PSoC Creator - * generated strong function. - */ -} - - -/******************************************************************************* -* Function Name: SystemCoreClockUpdate -****************************************************************************//** -* -* Gets core clock frequency and updates \ref SystemCoreClock, \ref -* cy_Hfclk0FreqHz, and \ref cy_PeriClkFreqHz. -* -* Updates global variables used by the \ref Cy_SysLib_Delay(), \ref -* Cy_SysLib_DelayUs(), and \ref Cy_SysLib_DelayCycles(). -* -*******************************************************************************/ -void SystemCoreClockUpdate (void) -{ - uint32 locHf0Clock = Cy_SysClk_ClkHfGetFrequency(0UL); - - if (0UL != locHf0Clock) - { - cy_Hfclk0FreqHz = locHf0Clock; - cy_PeriClkFreqHz = locHf0Clock / (1UL + (uint32_t)Cy_SysClk_ClkPeriGetDivider()); - SystemCoreClock = locHf0Clock / (1UL + (uint32_t)Cy_SysClk_ClkFastGetDivider()); - - /* Sets clock frequency for Delay API */ - cy_delayFreqMhz = (uint8_t)CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1M_THRESHOLD); - cy_delayFreqKhz = CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1K_THRESHOLD); - cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * cy_delayFreqKhz; - } -} - - -/******************************************************************************* -* Function Name: Cy_SystemInitFpuEnable -****************************************************************************//** -* -* Enables the FPU if it is used. The function is called from the startup file. -* -*******************************************************************************/ -void Cy_SystemInitFpuEnable(void) -{ - #if defined (__FPU_USED) && (__FPU_USED == 1U) - uint32_t interruptState; - interruptState = Cy_SysLib_EnterCriticalSection(); - SCB->CPACR |= SCB_CPACR_CP10_CP11_ENABLE; - __DSB(); - __ISB(); - Cy_SysLib_ExitCriticalSection(interruptState); - #endif /* (__FPU_USED) && (__FPU_USED == 1U) */ -} - - -#if !defined(CY_IPC_DEFAULT_CFG_DISABLE) -/******************************************************************************* -* Function Name: Cy_SysIpcPipeIsrCm4 -****************************************************************************//** -* -* This is the interrupt service routine for the system pipe. -* -*******************************************************************************/ -void Cy_SysIpcPipeIsrCm4(void) -{ - Cy_IPC_Pipe_ExecuteCallback(CY_IPC_EP_CYPIPE_CM4_ADDR); -} -#endif - - -/******************************************************************************* -* Function Name: Cy_MemorySymbols -****************************************************************************//** -* -* The intention of the function is to declare boundaries of the memories for the -* MDK compilers. For the rest of the supported compilers, this is done using -* linker configuration files. The following symbols used by the cymcuelftool. -* -*******************************************************************************/ -#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION < 6010050) -__asm void Cy_MemorySymbols(void) -{ - /* Flash */ - EXPORT __cy_memory_0_start - EXPORT __cy_memory_0_length - EXPORT __cy_memory_0_row_size - - /* Working Flash */ - EXPORT __cy_memory_1_start - EXPORT __cy_memory_1_length - EXPORT __cy_memory_1_row_size - - /* Supervisory Flash */ - EXPORT __cy_memory_2_start - EXPORT __cy_memory_2_length - EXPORT __cy_memory_2_row_size - - /* XIP */ - EXPORT __cy_memory_3_start - EXPORT __cy_memory_3_length - EXPORT __cy_memory_3_row_size - - /* eFuse */ - EXPORT __cy_memory_4_start - EXPORT __cy_memory_4_length - EXPORT __cy_memory_4_row_size - - /* Flash */ -__cy_memory_0_start EQU __cpp(CY_FLASH_BASE) -__cy_memory_0_length EQU __cpp(CY_FLASH_SIZE) -__cy_memory_0_row_size EQU 0x200 - - /* Flash region for EEPROM emulation */ -__cy_memory_1_start EQU __cpp(CY_EM_EEPROM_BASE) -__cy_memory_1_length EQU __cpp(CY_EM_EEPROM_SIZE) -__cy_memory_1_row_size EQU 0x200 - - /* Supervisory Flash */ -__cy_memory_2_start EQU __cpp(CY_SFLASH_BASE) -__cy_memory_2_length EQU __cpp(CY_SFLASH_SIZE) -__cy_memory_2_row_size EQU 0x200 - - /* XIP */ -__cy_memory_3_start EQU __cpp(CY_XIP_BASE) -__cy_memory_3_length EQU __cpp(CY_XIP_SIZE) -__cy_memory_3_row_size EQU 0x200 - - /* eFuse */ -__cy_memory_4_start EQU __cpp(0x90700000) -__cy_memory_4_length EQU __cpp(0x100000) -__cy_memory_4_row_size EQU __cpp(1) -} -#endif /* defined (__ARMCC_VERSION) && (__ARMCC_VERSION < 6010050) */ - - -/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/device/system_psoc6.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/device/system_psoc6.h deleted file mode 100644 index 8dd97ffb7a..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/device/system_psoc6.h +++ /dev/null @@ -1,658 +0,0 @@ -/***************************************************************************//** -* \file system_psoc6.h -* \version 2.70 -* -* \brief Device system header file. -* -******************************************************************************** -* \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ - - -#ifndef _SYSTEM_PSOC6_H_ -#define _SYSTEM_PSOC6_H_ - -/** -* \addtogroup group_system_config -* \{ -* Provides device startup, system configuration, and linker script files. -* The system startup provides the followings features: -* - See \ref group_system_config_device_initialization for the: -* * \ref group_system_config_dual_core_device_initialization -* * \ref group_system_config_single_core_device_initialization -* - \ref group_system_config_device_memory_definition -* - \ref group_system_config_heap_stack_config -* - \ref group_system_config_merge_apps -* - \ref group_system_config_default_handlers -* - \ref group_system_config_device_vector_table -* - \ref group_system_config_cm4_functions -* -* \section group_system_config_configuration Configuration Considerations -* -* \subsection group_system_config_device_memory_definition Device Memory Definition -* The flash and RAM allocation for each CPU is defined by the linker scripts. -* For dual-core devices, the physical flash and RAM memory is shared between the CPU cores. -* 2 KB of RAM (allocated at the end of RAM) are reserved for system use. -* For Single-Core devices the system reserves additional 80 bytes of RAM. -* Using the reserved memory area for other purposes will lead to unexpected behavior. -* -* \note The linker files provided with the PDL are generic and handle all common -* use cases. Your project may not use every section defined in the linker files. -* In that case you may see warnings during the build process. To eliminate build -* warnings in your project, you can simply comment out or remove the relevant -* code in the linker file. -* -* ARM GCC\n -* The flash and RAM sections for the CPU are defined in the linker files: -* 'xx_yy.ld', where 'xx' is the device group, and 'yy' is the target CPU; for example, -* 'cy8c6xx7_cm0plus.ld' and 'cy8c6xx7_cm4_dual.ld'. -* \note If the start of the Cortex-M4 application image is changed, the value -* of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The -* \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the -* Cy_SysEnableCM4() function call. -* -* Change the flash and RAM sizes by editing the macros value in the -* linker files for both CPUs: -* - 'xx_cm0plus.ld', where 'xx' is the device group: -* \code -* flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x00080000 -* ram (rwx) : ORIGIN = 0x08000000, LENGTH = 0x00024000 -* \endcode -* - 'xx_cm4_dual.ld', where 'xx' is the device group: -* \code -* flash (rx) : ORIGIN = 0x10080000, LENGTH = 0x00080000 -* ram (rwx) : ORIGIN = 0x08024000, LENGTH = 0x00023800 -* \endcode -* -* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the rom ORIGIN's -* value in the 'xx_cm4_dual.ld' file, where 'xx' is the device group. Do this -* by either: -* - Passing the following commands to the compiler:\n -* \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode -* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where 'xx' is device family:\n -* \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode -* -* ARM MDK\n -* The flash and RAM sections for the CPU are defined in the linker files: -* 'xx_yy.scat', where 'xx' is the device group, and 'yy' is the target CPU; for example, -* 'cy8c6xx7_cm0plus.scat' and 'cy8c6xx7_cm4_dual.scat'. -* \note If the start of the Cortex-M4 application image is changed, the value -* of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The -* \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the \ref -* Cy_SysEnableCM4() function call. -* -* \note The linker files provided with the PDL are generic and handle all common -* use cases. Your project may not use every section defined in the linker files. -* In that case you may see the warnings during the build process: -* L6314W (no section matches pattern) and/or L6329W -* (pattern only matches removed unused sections). In your project, you can -* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to -* the linker. You can also comment out or remove the relevant code in the linker -* file. -* -* Change the flash and RAM sizes by editing the macros value in the -* linker files for both CPUs: -* - 'xx_cm0plus.scat', where 'xx' is the device group: -* \code -* #define FLASH_START 0x10000000 -* #define FLASH_SIZE 0x00080000 -* #define RAM_START 0x08000000 -* #define RAM_SIZE 0x00024000 -* \endcode -* - 'xx_cm4_dual.scat', where 'xx' is the device group: -* \code -* #define FLASH_START 0x10080000 -* #define FLASH_SIZE 0x00080000 -* #define RAM_START 0x08024000 -* #define RAM_SIZE 0x00023800 -* \endcode -* -* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the FLASH_START -* value in the 'xx_cm4_dual.scat' file, -* where 'xx' is the device group. Do this by either: -* - Passing the following commands to the compiler:\n -* \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode -* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where -* 'xx' is device family:\n -* \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode -* -* IAR\n -* The flash and RAM sections for the CPU are defined in the linker files: -* 'xx_yy.icf', where 'xx' is the device group, and 'yy' is the target CPU; for example, -* 'cy8c6xx7_cm0plus.icf' and 'cy8c6xx7_cm4_dual.icf'. -* \note If the start of the Cortex-M4 application image is changed, the value -* of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The -* \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the \ref -* Cy_SysEnableCM4() function call. -* -* Change the flash and RAM sizes by editing the macros value in the -* linker files for both CPUs: -* - 'xx_cm0plus.icf', where 'xx' is the device group: -* \code -* define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000; -* define symbol __ICFEDIT_region_IROM1_end__ = 0x10080000; -* define symbol __ICFEDIT_region_IRAM1_start__ = 0x08000000; -* define symbol __ICFEDIT_region_IRAM1_end__ = 0x08024000; -* \endcode -* - 'xx_cm4_dual.icf', where 'xx' is the device group: -* \code -* define symbol __ICFEDIT_region_IROM1_start__ = 0x10080000; -* define symbol __ICFEDIT_region_IROM1_end__ = 0x10100000; -* define symbol __ICFEDIT_region_IRAM1_start__ = 0x08024000; -* define symbol __ICFEDIT_region_IRAM1_end__ = 0x08047800; -* \endcode -* -* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the -* __ICFEDIT_region_IROM1_start__ value in the 'xx_cm4_dual.icf' file, where 'xx' -* is the device group. Do this by either: -* - Passing the following commands to the compiler:\n -* \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode -* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where -* 'xx' is device family:\n -* \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode -* -* \subsection group_system_config_device_initialization Device Initialization -* After a power-on-reset (POR), the boot process is handled by the boot code -* from the on-chip ROM that is always executed by the Cortex-M0+ core. The boot -* code passes the control to the Cortex-M0+ startup code located in flash. -* -* \subsubsection group_system_config_dual_core_device_initialization Dual-Core Devices -* The Cortex-M0+ startup code performs the device initialization by a call to -* SystemInit() and then calls the main() function. The Cortex-M4 core is disabled -* by default. Enable the core using the \ref Cy_SysEnableCM4() function. -* See \ref group_system_config_cm4_functions for more details. -* \note Startup code executes SystemInit() function for the both Cortex-M0+ and Cortex-M4 cores. -* The function has a separate implementation on each core. -* Both function implementations unlock and disable the WDT. -* Therefore enable the WDT after both cores have been initialized. -* -* \subsubsection group_system_config_single_core_device_initialization Single-Core Devices -* The Cortex-M0+ core is not user-accessible on these devices. In this case the -* Flash Boot handles setup of the CM0+ core and starts the Cortex-M4 core. -* -* \subsection group_system_config_heap_stack_config Heap and Stack Configuration -* There are two ways to adjust heap and stack configurations: -* -# Editing source code files -* -# Specifying via command line -* -* By default, the stack size is set to 0x00001000 and the heap size is set to 0x00000400. -* -* \subsubsection group_system_config_heap_stack_config_gcc ARM GCC -* - Editing source code files\n -* The heap and stack sizes are defined in the assembler startup files -* (e.g. startup_psoc6_01_cm0plus.S and startup_psoc6_01_cm4.S). -* Change the heap and stack sizes by modifying the following lines:\n -* \code .equ Stack_Size, 0x00001000 \endcode -* \code .equ Heap_Size, 0x00000400 \endcode -* -* - Specifying via command line\n -* Change the heap and stack sizes passing the following commands to the compiler:\n -* \code -D __STACK_SIZE=0x000000400 \endcode -* \code -D __HEAP_SIZE=0x000000100 \endcode -* -* \subsubsection group_system_config_heap_stack_config_mdk ARM MDK -* - Editing source code files\n -* The heap and stack sizes are defined in the assembler startup files -* (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s). -* Change the heap and stack sizes by modifying the following lines:\n -* \code Stack_Size EQU 0x00001000 \endcode -* \code Heap_Size EQU 0x00000400 \endcode -* -* - Specifying via command line\n -* Change the heap and stack sizes passing the following commands to the assembler:\n -* \code "--predefine=___STACK_SIZE SETA 0x000000400" \endcode -* \code "--predefine=__HEAP_SIZE SETA 0x000000100" \endcode -* -* \subsubsection group_system_config_heap_stack_config_iar IAR -* - Editing source code files\n -* The heap and stack sizes are defined in the linker scatter files: 'xx_yy.icf', -* where 'xx' is the device family, and 'yy' is the target CPU; for example, -* cy8c6xx7_cm0plus.icf and cy8c6xx7_cm4_dual.icf. -* Change the heap and stack sizes by modifying the following lines:\n -* \code Stack_Size EQU 0x00001000 \endcode -* \code Heap_Size EQU 0x00000400 \endcode -* -* - Specifying via command line\n -* Change the heap and stack sizes passing the following commands to the -* linker (including quotation marks):\n -* \code --define_symbol __STACK_SIZE=0x000000400 \endcode -* \code --define_symbol __HEAP_SIZE=0x000000100 \endcode -* -* \subsection group_system_config_merge_apps Merging CM0+ and CM4 Executables -* The CM0+ project and linker script build the CM0+ application image. Similarly, -* the CM4 linker script builds the CM4 application image. Each specifies -* locations, sizes, and contents of sections in memory. See -* \ref group_system_config_device_memory_definition for the symbols and default -* values. -* -* The cymcuelftool is invoked by a post-build command. The precise project -* setting is IDE-specific. -* -* The cymcuelftool combines the two executables. The tool examines the -* executables to ensure that memory regions either do not overlap, or contain -* identical bytes (shared). If there are no problems, it creates a new ELF file -* with the merged image, without changing any of the addresses or data. -* -* \subsection group_system_config_default_handlers Default Interrupt Handlers Definition -* The default interrupt handler functions are defined as weak functions to a dummy -* handler in the startup file. The naming convention for the interrupt handler names -* is \_IRQHandler. A default interrupt handler can be overwritten in -* user code by defining the handler function using the same name. For example: -* \code -* void scb_0_interrupt_IRQHandler(void) -*{ -* ... -*} -* \endcode -* -* \subsection group_system_config_device_vector_table Vectors Table Copy from Flash to RAM -* This process uses memory sections defined in the linker script. The startup -* code actually defines the contents of the vector table and performs the copy. -* \subsubsection group_system_config_device_vector_table_gcc ARM GCC -* The linker script file is 'xx_yy.ld', where 'xx' is the device family, and -* 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.ld and cy8c6xx7_cm4_dual.ld. -* It defines sections and locations in memory.\n -* Copy interrupt vectors from flash to RAM: \n -* From: \code LONG (__Vectors) \endcode -* To: \code LONG (__ram_vectors_start__) \endcode -* Size: \code LONG (__Vectors_End - __Vectors) \endcode -* The vector table address (and the vector table itself) are defined in the -* assembler startup files (e.g. startup_psoc6_01_cm0plus.S and startup_psoc6_01_cm4.S). -* The code in these files copies the vector table from Flash to RAM. -* \subsubsection group_system_config_device_vector_table_mdk ARM MDK -* The linker script file is 'xx_yy.scat', where 'xx' is the device family, -* and 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.scat and -* cy8c6xx7_cm4_dual.scat. The linker script specifies that the vector table -* (RESET_RAM) shall be first in the RAM section.\n -* RESET_RAM represents the vector table. It is defined in the assembler startup -* files (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s). -* The code in these files copies the vector table from Flash to RAM. -* -* \subsubsection group_system_config_device_vector_table_iar IAR -* The linker script file is 'xx_yy.icf', where 'xx' is the device family, and -* 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.icf and cy8c6xx7_cm4_dual.icf. -* This file defines the .intvec_ram section and its location. -* \code place at start of IRAM1_region { readwrite section .intvec_ram}; \endcode -* The vector table address (and the vector table itself) are defined in the -* assembler startup files (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s). -* The code in these files copies the vector table from Flash to RAM. -* -* \section group_system_config_more_information More Information -* Refer to the PDL User Guide for the -* more details. -* -* \section group_system_config_MISRA MISRA Compliance -* -* -* -* -* -* -* -* -* -* -* -* -* -* -*
MISRA RuleRule Class (Required/Advisory)Rule DescriptionDescription of Deviation(s)
2.3RThe character sequence // shall not be used within a comment.The comments provide a useful WEB link to the documentation.
-* -* \section group_system_config_changelog Changelog -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -*
VersionChangesReason for Change
2.70Updated \ref SystemCoreClockUpdate() implementation - The SysClk API is reused.Code optimization.
Updated \ref SystemInit() implementation - The IPC7 structure is initialized for both cores.Provided support for SysPM driver updates.
Updated the linker scripts.Reserved FLASH area for the MCU boot headers.
Added System Pipe initialization for all devices. Improved PDL usability according to user experience.
Removed redundant legacy macros: CY_CLK_EXT_FREQ_HZ, CY_CLK_ECO_FREQ_HZ and CY_CLK_ALTHF_FREQ_HZ. -* Use \ref Cy_SysClk_ExtClkSetFrequency, \ref Cy_SysClk_EcoConfigure and \ref Cy_BLE_EcoConfigure functions instead them. Defect fixing.
2.60Updated linker scripts.Provided support for new devices, updated usage of CM0p prebuilt image.
2.50Updated assembler files, C files, linker scripts.Dynamic allocated HEAP size for Arm Compiler 6, IAR 8.
2.40Updated assembler files, C files, linker scripts.Added Arm Compiler 6 support.
2.30Added assembler files, linker scripts for Mbed OS.Added Arm Mbed OS embedded operating system support.
Updated linker scripts to extend the Flash and Ram memories size available for the CM4 core.Enhanced PDL usability.
2.20Moved the Cy_IPC_SystemSemaInit(), Cy_IPC_SystemPipeInit() functions implementation from IPC to Startup.Changed the IPC driver configuration method from compile time to run time.
2.10Added constructor attribute to SystemInit() function declaration for ARM MDK compiler. \n -* Removed $Sub$$main symbol for ARM MDK compiler. -* uVision Debugger support.
Updated description of the Startup behavior for Single-Core Devices. \n -* Added note about WDT disabling by SystemInit() function. -* Documentation improvement.
2.0Added restoring of FLL registers to the default state in SystemInit() API for single core devices. -* Single core device support. -*
Added Normal Access Restrictions, Public Key, TOC part2 and TOC part2 copy to Supervisory flash linker memory regions. \n -* Renamed 'wflash' memory region to 'em_eeprom'. -* Linker scripts usability improvement.
Added Cy_IPC_SystemSemaInit(), Cy_IPC_SystemPipeInit(), Cy_Flash_Init() functions call to SystemInit() API.Reserved system resources for internal operations.
Added clearing and releasing of IPC structure #7 (reserved for the Deep-Sleep operations) to SystemInit() API.To avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering.
1.0Initial version
-* -* -* \defgroup group_system_config_macro Macro -* \{ -* \defgroup group_system_config_system_macro System -* \defgroup group_system_config_cm4_status_macro Cortex-M4 Status -* \defgroup group_system_config_user_settings_macro User Settings -* \} -* \defgroup group_system_config_functions Functions -* \{ -* \defgroup group_system_config_system_functions System -* \defgroup group_system_config_cm4_functions Cortex-M4 Control -* \} -* \defgroup group_system_config_globals Global Variables -* -* \} -*/ - -/** -* \addtogroup group_system_config_system_functions -* \{ -* \details -* The following system functions implement CMSIS Core functions. -* Refer to the [CMSIS documentation] -* (http://www.keil.com/pack/doc/CMSIS/Core/html/group__system__init__gr.html "System and Clock Configuration") -* for more details. -* \} -*/ - -#ifdef __cplusplus -extern "C" { -#endif - - -/******************************************************************************* -* Include files -*******************************************************************************/ -#include - - -/******************************************************************************* -* Global preprocessor symbols/macros ('define') -*******************************************************************************/ -#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ - (defined (__ICCARM__) && (__CORE__ == __ARM6M__)) || \ - (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3))) - #define CY_SYSTEM_CPU_CM0P 1UL -#else - #define CY_SYSTEM_CPU_CM0P 0UL -#endif - - -/******************************************************************************* -* -* START OF USER SETTINGS HERE -* =========================== -* -* All lines with '<<<' can be set by user. -* -*******************************************************************************/ - -/** -* \addtogroup group_system_config_user_settings_macro -* \{ -*/ - - -/***************************************************************************//** -* \brief Start address of the Cortex-M4 application ([address]UL) -* (USER SETTING) -*******************************************************************************/ -#if !defined (CY_CORTEX_M4_APPL_ADDR) - #define CY_CORTEX_M4_APPL_ADDR (CY_FLASH_BASE + 0x2000U) /* <<< 8 kB of flash is reserved for the Cortex-M0+ application */ -#endif /* (CY_CORTEX_M4_APPL_ADDR) */ - - -/***************************************************************************//** -* \brief IPC Semaphores allocation ([value]UL). -* (USER SETTING) -*******************************************************************************/ -#define CY_IPC_SEMA_COUNT (128UL) /* <<< This will allow 128 (4*32) semaphores */ - - -/***************************************************************************//** -* \brief IPC Pipe definitions ([value]UL). -* (USER SETTING) -*******************************************************************************/ -#define CY_IPC_MAX_ENDPOINTS (8UL) /* <<< 8 endpoints */ - - -/******************************************************************************* -* -* END OF USER SETTINGS HERE -* ========================= -* -*******************************************************************************/ - -/** \} group_system_config_user_settings_macro */ - - -/** -* \addtogroup group_system_config_system_macro -* \{ -*/ - -#if (CY_SYSTEM_CPU_CM0P == 1UL) || defined(CY_DOXYGEN) - /** The Cortex-M0+ startup driver identifier */ - #define CY_STARTUP_M0P_ID ((uint32_t)((uint32_t)((0x0EU) & 0x3FFFU) << 18U)) -#endif /* (CY_SYSTEM_CPU_CM0P == 1UL) */ - -#if (CY_SYSTEM_CPU_CM0P != 1UL) || defined(CY_DOXYGEN) - /** The Cortex-M4 startup driver identifier */ - #define CY_STARTUP_M4_ID ((uint32_t)((uint32_t)((0x0FU) & 0x3FFFU) << 18U)) -#endif /* (CY_SYSTEM_CPU_CM0P != 1UL) */ - -/** \} group_system_config_system_macro */ - - -/** -* \addtogroup group_system_config_system_functions -* \{ -*/ -extern void SystemInit(void); - -extern void SystemCoreClockUpdate(void); -/** \} group_system_config_system_functions */ - - -/** -* \addtogroup group_system_config_cm4_functions -* \{ -*/ -extern uint32_t Cy_SysGetCM4Status(void); -extern void Cy_SysEnableCM4(uint32_t vectorTableOffset); -extern void Cy_SysDisableCM4(void); -extern void Cy_SysRetainCM4(void); -extern void Cy_SysResetCM4(void); -/** \} group_system_config_cm4_functions */ - - -/** \cond */ -extern void Default_Handler (void); - -void Cy_SysIpcPipeIsrCm0(void); -void Cy_SysIpcPipeIsrCm4(void); - -extern void Cy_SystemInit(void); -extern void Cy_SystemInitFpuEnable(void); - -extern uint32_t cy_delayFreqKhz; -extern uint8_t cy_delayFreqMhz; -extern uint32_t cy_delay32kMs; -/** \endcond */ - - -#if (CY_SYSTEM_CPU_CM0P == 1UL) || defined(CY_DOXYGEN) -/** -* \addtogroup group_system_config_cm4_status_macro -* \{ -*/ -#define CY_SYS_CM4_STATUS_ENABLED (3U) /**< The Cortex-M4 core is enabled: power on, clock on, no isolate, no reset and no retain. */ -#define CY_SYS_CM4_STATUS_DISABLED (0U) /**< The Cortex-M4 core is disabled: power off, clock off, isolate, reset and no retain. */ -#define CY_SYS_CM4_STATUS_RETAINED (2U) /**< The Cortex-M4 core is retained. power off, clock off, isolate, no reset and retain. */ -#define CY_SYS_CM4_STATUS_RESET (1U) /**< The Cortex-M4 core is in the Reset mode: clock off, no isolated, no retain and reset. */ -/** \} group_system_config_cm4_status_macro */ - -#endif /* (CY_SYSTEM_CPU_CM0P == 1UL) */ - - -/******************************************************************************* -* IPC Configuration -* ========================= -*******************************************************************************/ -/* IPC CY_PIPE default configuration */ -#define CY_SYS_CYPIPE_CLIENT_CNT (8UL) - -#define CY_SYS_INTR_CYPIPE_MUX_EP0 (1UL) /* IPC CYPRESS PIPE */ -#define CY_SYS_INTR_CYPIPE_PRIOR_EP0 (1UL) /* Notifier Priority */ -#define CY_SYS_INTR_CYPIPE_PRIOR_EP1 (1UL) /* Notifier Priority */ - -#define CY_SYS_CYPIPE_CHAN_MASK_EP0 (0x0001UL << CY_IPC_CHAN_CYPIPE_EP0) -#define CY_SYS_CYPIPE_CHAN_MASK_EP1 (0x0001UL << CY_IPC_CHAN_CYPIPE_EP1) - - -/******************************************************************************/ -/* - * The System pipe configuration defines the IPC channel number, interrupt - * number, and the pipe interrupt mask for the endpoint. - * - * The format of the endPoint configuration - * Bits[31:16] Interrupt Mask - * Bits[15:8 ] IPC interrupt - * Bits[ 7:0 ] IPC channel - */ - -/* System Pipe addresses */ -/* CyPipe defines */ - -#define CY_SYS_CYPIPE_INTR_MASK ( CY_SYS_CYPIPE_CHAN_MASK_EP0 | CY_SYS_CYPIPE_CHAN_MASK_EP1 ) - -#define CY_SYS_CYPIPE_CONFIG_EP0 ( (CY_SYS_CYPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \ - | (CY_IPC_INTR_CYPIPE_EP0 << CY_IPC_PIPE_CFG_INTR_Pos) \ - | CY_IPC_CHAN_CYPIPE_EP0) -#define CY_SYS_CYPIPE_CONFIG_EP1 ( (CY_SYS_CYPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \ - | (CY_IPC_INTR_CYPIPE_EP1 << CY_IPC_PIPE_CFG_INTR_Pos) \ - | CY_IPC_CHAN_CYPIPE_EP1) - -/******************************************************************************/ - - -/** \addtogroup group_system_config_globals -* \{ -*/ - -extern uint32_t SystemCoreClock; -extern uint32_t cy_BleEcoClockFreqHz; -extern uint32_t cy_Hfclk0FreqHz; -extern uint32_t cy_PeriClkFreqHz; - -/** \} group_system_config_globals */ - - - -/** \cond INTERNAL */ -/******************************************************************************* -* Backward compatibility macros. The following code is DEPRECATED and must -* not be used in new projects -*******************************************************************************/ - -/* BWC defines for functions related to enter/exit critical section */ -#define Cy_SaveIRQ Cy_SysLib_EnterCriticalSection -#define Cy_RestoreIRQ Cy_SysLib_ExitCriticalSection -#define CY_SYS_INTR_CYPIPE_EP0 (CY_IPC_INTR_CYPIPE_EP0) -#define CY_SYS_INTR_CYPIPE_EP1 (CY_IPC_INTR_CYPIPE_EP1) -#define cy_delayFreqHz (SystemCoreClock) - -/** \endcond */ - -#ifdef __cplusplus -} -#endif - -#endif /* _SYSTEM_PSOC6_H_ */ - - -/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/secure_image_parameters.json b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/secure_image_parameters.json deleted file mode 100644 index bae6642e49..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/secure_image_parameters.json +++ /dev/null @@ -1,17 +0,0 @@ -{ - "boot0" : { - "VERSION" : "0.1", - "ROLLBACK_COUNTER" : "0" - }, - - "boot1" : { - "VERSION" : "0.1", - "ROLLBACK_COUNTER" : "0" - }, - - "sdk_path" : "targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/", - "priv_key_file": "keys/USERAPP_CM4_KEY_PRIV.pem", - "aes_key_file": "keys/image-aes-128.key", - "dev_pub_key_file": "keys/dev_pub_key.pem", - "policy_file": "policy/policy_single_stage_CM4_2m.json" -} diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/COMPONENT_CM0P_BLESS/psoc6_cm0p_bless.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/COMPONENT_CM0P_BLESS/psoc6_cm0p_bless.c index 2873f7bb8e..bed16162d3 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/COMPONENT_CM0P_BLESS/psoc6_cm0p_bless.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/COMPONENT_CM0P_BLESS/psoc6_cm0p_bless.c @@ -40,46 +40,46 @@ const uint8_t cy_m0p_image[] = { 0x89u, 0x01u, 0x00u, 0x10u, 0x89u, 0x01u, 0x00u, 0x10u, 0x89u, 0x01u, 0x00u, 0x10u, 0x89u, 0x01u, 0x00u, 0x10u, 0x89u, 0x01u, 0x00u, 0x10u, 0x89u, 0x01u, 0x00u, 0x10u, 0x89u, 0x01u, 0x00u, 0x10u, 0x89u, 0x01u, 0x00u, 0x10u, 0x10u, 0xb5u, 0x06u, 0x4cu, 0x23u, 0x78u, 0x00u, 0x2bu, 0x07u, 0xd1u, 0x05u, 0x4bu, 0x00u, 0x2bu, 0x02u, 0xd0u, - 0x04u, 0x48u, 0x00u, 0xe0u, 0x00u, 0xbfu, 0x01u, 0x23u, 0x23u, 0x70u, 0x10u, 0xbdu, 0x60u, 0x05u, 0x00u, 0x08u, - 0x00u, 0x00u, 0x00u, 0x00u, 0xb4u, 0x53u, 0x00u, 0x10u, 0x04u, 0x4bu, 0x10u, 0xb5u, 0x00u, 0x2bu, 0x03u, 0xd0u, + 0x04u, 0x48u, 0x00u, 0xe0u, 0x00u, 0xbfu, 0x01u, 0x23u, 0x23u, 0x70u, 0x10u, 0xbdu, 0x70u, 0x05u, 0x00u, 0x08u, + 0x00u, 0x00u, 0x00u, 0x00u, 0xbcu, 0x53u, 0x00u, 0x10u, 0x04u, 0x4bu, 0x10u, 0xb5u, 0x00u, 0x2bu, 0x03u, 0xd0u, 0x03u, 0x49u, 0x04u, 0x48u, 0x00u, 0xe0u, 0x00u, 0xbfu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x64u, 0x05u, 0x00u, 0x08u, 0xb4u, 0x53u, 0x00u, 0x10u, 0x02u, 0x30u, 0x80u, 0x08u, 0x03u, 0xd0u, 0x01u, 0x30u, + 0x74u, 0x05u, 0x00u, 0x08u, 0xbcu, 0x53u, 0x00u, 0x10u, 0x02u, 0x30u, 0x80u, 0x08u, 0x03u, 0xd0u, 0x01u, 0x30u, 0x02u, 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0x00u, 0x08u, 0x00u, 0x00u, 0x00u, 0x08u, 0x08u, 0xedu, 0x00u, 0xe0u, 0xfeu, 0xe7u, 0xfeu, 0xe7u, 0x00u, 0xb5u, 0x04u, 0x20u, 0x71u, 0x46u, 0x08u, 0x42u, 0x02u, 0xd0u, 0xefu, 0xf3u, 0x09u, 0x80u, 0x01u, 0xe0u, 0xefu, 0xf3u, 0x08u, 0x80u, - 0x04u, 0x30u, 0x01u, 0xf0u, 0x11u, 0xffu, 0xfeu, 0xe7u, 0x10u, 0xb5u, 0x00u, 0xf0u, 0x5fu, 0xf8u, 0x10u, 0xbdu, + 0x04u, 0x30u, 0x01u, 0xf0u, 0x15u, 0xffu, 0xfeu, 0xe7u, 0x10u, 0xb5u, 0x00u, 0xf0u, 0x5fu, 0xf8u, 0x10u, 0xbdu, 0x10u, 0xb5u, 0x00u, 0xf0u, 0x2bu, 0xfcu, 0x10u, 0xbdu, 0x10u, 0xb5u, 0x00u, 0xf0u, 0xbfu, 0xf8u, 0x10u, 0xbdu, - 0x10u, 0xb5u, 0x07u, 0xf0u, 0x09u, 0xf8u, 0x10u, 0xbdu, 0x10u, 0xb5u, 0x0du, 0xf0u, 0x99u, 0xfeu, 0x10u, 0xbdu, - 0x10u, 0xb5u, 0x07u, 0xf0u, 0x19u, 0xf8u, 0x10u, 0xbdu, 0x10u, 0xb5u, 0x05u, 0xf0u, 0xd9u, 0xf9u, 0x10u, 0xbdu, + 0x10u, 0xb5u, 0x07u, 0xf0u, 0x0du, 0xf8u, 0x10u, 0xbdu, 0x10u, 0xb5u, 0x0du, 0xf0u, 0x9du, 0xfeu, 0x10u, 0xbdu, + 0x10u, 0xb5u, 0x07u, 0xf0u, 0x1du, 0xf8u, 0x10u, 0xbdu, 0x10u, 0xb5u, 0x05u, 0xf0u, 0xddu, 0xf9u, 0x10u, 0xbdu, 0xf8u, 0xb5u, 0x0fu, 0x00u, 0x01u, 0x29u, 0x03u, 0xd0u, 0x08u, 0x29u, 0x34u, 0xd0u, 0x1cu, 0x48u, 0x17u, 0xe0u, 0x03u, 0x20u, 0x01u, 0xf0u, 0xb9u, 0xfbu, 0x1bu, 0x4bu, 0x98u, 0x42u, 0xf7u, 0xd0u, 0x00u, 0xf0u, 0x3cu, 0xfbu, 0x01u, 0x28u, 0xf3u, 0xd0u, 0x02u, 0x20u, 0xffu, 0xf7u, 0xe7u, 0xffu, 0x06u, 0x00u, 0xffu, 0xf7u, 0x85u, 0xffu, - 0x15u, 0x4du, 0x28u, 0x60u, 0x05u, 0xf0u, 0xc0u, 0xf9u, 0x04u, 0x00u, 0x06u, 0x28u, 0x01u, 0xd1u, 0x00u, 0x20u, + 0x15u, 0x4du, 0x28u, 0x60u, 0x05u, 0xf0u, 0xc4u, 0xf9u, 0x04u, 0x00u, 0x06u, 0x28u, 0x01u, 0xd1u, 0x00u, 0x20u, 0xf8u, 0xbdu, 0x02u, 0x2eu, 0x0du, 0xd1u, 0x03u, 0x3cu, 0xb4u, 0x43u, 0x30u, 0x00u, 0xe4u, 0xb2u, 0xffu, 0xf7u, 0xc7u, 0xffu, 0x00u, 0x2cu, 0x01u, 0xd1u, 0x00u, 0x28u, 0xf1u, 0xd0u, 0x28u, 0x68u, 0xffu, 0xf7u, 0x71u, 0xffu, 0xd4u, 0xe7u, 0x38u, 0x00u, 0xffu, 0xf7u, 0xbcu, 0xffu, 0x02u, 0x2cu, 0xf6u, 0xd0u, 0x00u, 0x28u, 0xf4u, 0xd1u, - 0x02u, 0xf0u, 0xdau, 0xf8u, 0xf1u, 0xe7u, 0x04u, 0x4bu, 0x18u, 0x68u, 0xffu, 0xf7u, 0x62u, 0xffu, 0xdeu, 0xe7u, - 0xffu, 0x00u, 0x42u, 0x00u, 0x01u, 0x01u, 0x88u, 0x00u, 0x88u, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x00u, 0x28u, + 0x02u, 0xf0u, 0xdeu, 0xf8u, 0xf1u, 0xe7u, 0x04u, 0x4bu, 0x18u, 0x68u, 0xffu, 0xf7u, 0x62u, 0xffu, 0xdeu, 0xe7u, + 0xffu, 0x00u, 0x42u, 0x00u, 0x01u, 0x01u, 0x88u, 0x00u, 0x98u, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x00u, 0x28u, 0x05u, 0xd0u, 0x04u, 0x4bu, 0x18u, 0x60u, 0x00u, 0xf0u, 0x0bu, 0xfcu, 0x00u, 0x20u, 0x10u, 0xbdu, 0x02u, 0x48u, - 0xfcu, 0xe7u, 0xc0u, 0x46u, 0x84u, 0x05u, 0x00u, 0x08u, 0x01u, 0x00u, 0x16u, 0x00u, 0x70u, 0xb5u, 0x28u, 0x4du, + 0xfcu, 0xe7u, 0xc0u, 0x46u, 0x94u, 0x05u, 0x00u, 0x08u, 0x01u, 0x00u, 0x16u, 0x00u, 0x70u, 0xb5u, 0x28u, 0x4du, 0x94u, 0xb0u, 0x2eu, 0x68u, 0x00u, 0x2eu, 0x48u, 0xd0u, 0x01u, 0xacu, 0x4cu, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, - 0x04u, 0xf0u, 0xfau, 0xf9u, 0x0au, 0x21u, 0x33u, 0x68u, 0x69u, 0x44u, 0x9au, 0x8au, 0xa2u, 0x81u, 0x5au, 0x89u, + 0x04u, 0xf0u, 0xfeu, 0xf9u, 0x0au, 0x21u, 0x33u, 0x68u, 0x69u, 0x44u, 0x9au, 0x8au, 0xa2u, 0x81u, 0x5au, 0x89u, 0x22u, 0x83u, 0x9au, 0x89u, 0x62u, 0x83u, 0x1fu, 0x4au, 0xa2u, 0x83u, 0x1au, 0x89u, 0xcau, 0x87u, 0x59u, 0x1cu, 0xc8u, 0x7fu, 0x13u, 0xa9u, 0x08u, 0x70u, 0x69u, 0x46u, 0x98u, 0x7fu, 0x05u, 0x31u, 0xc8u, 0x77u, 0x69u, 0x46u, 0xd8u, 0x7fu, 0x06u, 0x31u, 0xc8u, 0x77u, 0x5bu, 0x7fu, 0xe3u, 0x77u, 0xd3u, 0x07u, 0x01u, 0xd5u, 0x05u, 0xf0u, - 0x37u, 0xf9u, 0x2bu, 0x68u, 0x1bu, 0x68u, 0x1bu, 0x89u, 0x9bu, 0x07u, 0x01u, 0xd5u, 0x05u, 0xf0u, 0x38u, 0xf9u, - 0x2bu, 0x68u, 0x1bu, 0x68u, 0x1bu, 0x89u, 0x1bu, 0x07u, 0x01u, 0xd5u, 0x05u, 0xf0u, 0x2du, 0xf9u, 0x07u, 0xa8u, - 0x05u, 0xf0u, 0x7au, 0xf9u, 0x00u, 0x28u, 0x0eu, 0xd1u, 0x2bu, 0x68u, 0x1bu, 0x68u, 0x9au, 0x69u, 0x59u, 0x68u, - 0x62u, 0x60u, 0x00u, 0x29u, 0x04u, 0xd0u, 0x26u, 0x30u, 0x22u, 0x22u, 0x68u, 0x44u, 0x04u, 0xf0u, 0xb3u, 0xf9u, - 0x20u, 0x00u, 0x05u, 0xf0u, 0x3du, 0xf9u, 0x14u, 0xb0u, 0x70u, 0xbdu, 0x03u, 0x48u, 0xfbu, 0xe7u, 0xc0u, 0x46u, - 0x84u, 0x05u, 0x00u, 0x08u, 0x03u, 0x04u, 0x00u, 0x00u, 0xffu, 0x00u, 0x16u, 0x00u, 0x10u, 0xb5u, 0x02u, 0x48u, - 0x01u, 0xf0u, 0xd0u, 0xffu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0xc0u, 0x00u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x52u, 0x4eu, + 0x3bu, 0xf9u, 0x2bu, 0x68u, 0x1bu, 0x68u, 0x1bu, 0x89u, 0x9bu, 0x07u, 0x01u, 0xd5u, 0x05u, 0xf0u, 0x3cu, 0xf9u, + 0x2bu, 0x68u, 0x1bu, 0x68u, 0x1bu, 0x89u, 0x1bu, 0x07u, 0x01u, 0xd5u, 0x05u, 0xf0u, 0x31u, 0xf9u, 0x07u, 0xa8u, + 0x05u, 0xf0u, 0x7eu, 0xf9u, 0x00u, 0x28u, 0x0eu, 0xd1u, 0x2bu, 0x68u, 0x1bu, 0x68u, 0x9au, 0x69u, 0x59u, 0x68u, + 0x62u, 0x60u, 0x00u, 0x29u, 0x04u, 0xd0u, 0x26u, 0x30u, 0x22u, 0x22u, 0x68u, 0x44u, 0x04u, 0xf0u, 0xb7u, 0xf9u, + 0x20u, 0x00u, 0x05u, 0xf0u, 0x41u, 0xf9u, 0x14u, 0xb0u, 0x70u, 0xbdu, 0x03u, 0x48u, 0xfbu, 0xe7u, 0xc0u, 0x46u, + 0x94u, 0x05u, 0x00u, 0x08u, 0x03u, 0x04u, 0x00u, 0x00u, 0xffu, 0x00u, 0x16u, 0x00u, 0x10u, 0xb5u, 0x02u, 0x48u, + 0x01u, 0xf0u, 0xd4u, 0xffu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0xc0u, 0x00u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x52u, 0x4eu, 0x33u, 0x68u, 0x00u, 0x2bu, 0x7du, 0xd0u, 0x9au, 0x68u, 0x00u, 0x2au, 0x7au, 0xd0u, 0x02u, 0x24u, 0x22u, 0x42u, 0x6au, 0xd1u, 0x01u, 0x21u, 0x4du, 0x4du, 0x4eu, 0x4bu, 0xecu, 0x58u, 0x0cu, 0x40u, 0x04u, 0xd0u, 0x14u, 0x00u, 0x7fu, 0x31u, 0x0cu, 0x40u, 0x00u, 0xd0u, 0x0cu, 0x00u, 0xe9u, 0x58u, 0x89u, 0x07u, 0x03u, 0xd5u, 0x04u, 0x21u, @@ -99,46 +99,46 @@ const uint8_t cy_m0p_image[] = { 0xf2u, 0xd1u, 0x70u, 0xbdu, 0xdcu, 0x60u, 0x64u, 0x24u, 0x17u, 0x4bu, 0x31u, 0x68u, 0x1au, 0x68u, 0x08u, 0x7cu, 0x13u, 0x00u, 0xacu, 0x33u, 0x1bu, 0x88u, 0x43u, 0x43u, 0x10u, 0x6au, 0xb0u, 0x32u, 0x12u, 0x68u, 0x1bu, 0x18u, 0x9au, 0x18u, 0x12u, 0x68u, 0x00u, 0x2au, 0x06u, 0xdau, 0x00u, 0x2cu, 0xeau, 0xd0u, 0x01u, 0x20u, 0x01u, 0xf0u, - 0x91u, 0xfdu, 0x01u, 0x3cu, 0xe8u, 0xe7u, 0x00u, 0x2cu, 0xe3u, 0xd0u, 0x80u, 0x22u, 0x49u, 0x7cu, 0x52u, 0x02u, - 0x8au, 0x40u, 0x12u, 0x0cu, 0x9au, 0x60u, 0xdcu, 0xe7u, 0x9cu, 0x05u, 0x00u, 0x08u, 0x00u, 0x00u, 0x3cu, 0x40u, + 0x95u, 0xfdu, 0x01u, 0x3cu, 0xe8u, 0xe7u, 0x00u, 0x2cu, 0xe3u, 0xd0u, 0x80u, 0x22u, 0x49u, 0x7cu, 0x52u, 0x02u, + 0x8au, 0x40u, 0x12u, 0x0cu, 0x9au, 0x60u, 0xdcu, 0xe7u, 0xacu, 0x05u, 0x00u, 0x08u, 0x00u, 0x00u, 0x3cu, 0x40u, 0x68u, 0xf0u, 0x01u, 0x00u, 0x08u, 0x10u, 0x00u, 0x00u, 0xa8u, 0x10u, 0x00u, 0x00u, 0x34u, 0x11u, 0x00u, 0x00u, - 0x38u, 0x10u, 0x00u, 0x00u, 0x94u, 0x05u, 0x00u, 0x08u, 0xc8u, 0x12u, 0x00u, 0x08u, 0x10u, 0xb5u, 0xffu, 0xf7u, + 0x38u, 0x10u, 0x00u, 0x00u, 0xa4u, 0x05u, 0x00u, 0x08u, 0xd8u, 0x12u, 0x00u, 0x08u, 0x10u, 0xb5u, 0xffu, 0xf7u, 0x83u, 0xfeu, 0x04u, 0x4bu, 0x1bu, 0x68u, 0x00u, 0x2bu, 0x02u, 0xd0u, 0x00u, 0x28u, 0x00u, 0xd0u, 0x98u, 0x47u, - 0x10u, 0xbdu, 0xc0u, 0x46u, 0x8cu, 0x05u, 0x00u, 0x08u, 0x00u, 0x28u, 0x05u, 0xdbu, 0x1fu, 0x23u, 0x18u, 0x40u, + 0x10u, 0xbdu, 0xc0u, 0x46u, 0x9cu, 0x05u, 0x00u, 0x08u, 0x00u, 0x28u, 0x05u, 0xdbu, 0x1fu, 0x23u, 0x18u, 0x40u, 0x1eu, 0x3bu, 0x83u, 0x40u, 0x01u, 0x4au, 0x13u, 0x60u, 0x70u, 0x47u, 0xc0u, 0x46u, 0x00u, 0xe1u, 0x00u, 0xe0u, - 0x10u, 0xb5u, 0x02u, 0x4bu, 0x1bu, 0x68u, 0x98u, 0x47u, 0x10u, 0xbdu, 0xc0u, 0x46u, 0x90u, 0x05u, 0x00u, 0x08u, + 0x10u, 0xb5u, 0x02u, 0x4bu, 0x1bu, 0x68u, 0x98u, 0x47u, 0x10u, 0xbdu, 0xc0u, 0x46u, 0xa0u, 0x05u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x04u, 0x1eu, 0x08u, 0xd0u, 0x0cu, 0x4bu, 0x1bu, 0x68u, 0x00u, 0x2bu, 0x04u, 0xd0u, 0x45u, 0x78u, 0x01u, 0x2du, 0x02u, 0xd0u, 0xffu, 0x2du, 0x09u, 0xd0u, 0x70u, 0xbdu, 0x82u, 0x68u, 0x1au, 0x60u, 0x02u, 0xf0u, - 0x8bu, 0xfau, 0xffu, 0xf7u, 0xb3u, 0xfeu, 0x25u, 0x71u, 0xa0u, 0x60u, 0xf5u, 0xe7u, 0x03u, 0x4bu, 0x18u, 0x60u, - 0x01u, 0x23u, 0x03u, 0x71u, 0xf0u, 0xe7u, 0xc0u, 0x46u, 0x98u, 0x05u, 0x00u, 0x08u, 0x9cu, 0x05u, 0x00u, 0x08u, + 0x8fu, 0xfau, 0xffu, 0xf7u, 0xb3u, 0xfeu, 0x25u, 0x71u, 0xa0u, 0x60u, 0xf5u, 0xe7u, 0x03u, 0x4bu, 0x18u, 0x60u, + 0x01u, 0x23u, 0x03u, 0x71u, 0xf0u, 0xe7u, 0xc0u, 0x46u, 0xa8u, 0x05u, 0x00u, 0x08u, 0xacu, 0x05u, 0x00u, 0x08u, 0x1fu, 0x23u, 0x18u, 0x40u, 0x1eu, 0x3bu, 0x83u, 0x40u, 0x03u, 0x4au, 0xd3u, 0x67u, 0xbfu, 0xf3u, 0x4fu, 0x8fu, 0xbfu, 0xf3u, 0x6fu, 0x8fu, 0x70u, 0x47u, 0xc0u, 0x46u, 0x04u, 0xe1u, 0x00u, 0xe0u, 0x10u, 0xb5u, 0x00u, 0xf0u, 0x3du, 0xfbu, 0x02u, 0x21u, 0x05u, 0x4au, 0x06u, 0x4bu, 0xd1u, 0x50u, 0x06u, 0x4bu, 0x1bu, 0x68u, 0x5bu, 0x68u, 0x1bu, 0x68u, 0x00u, 0x20u, 0x18u, 0x5eu, 0xffu, 0xf7u, 0xafu, 0xffu, 0x10u, 0xbdu, 0x00u, 0x00u, 0x3cu, 0x40u, - 0x78u, 0xf0u, 0x01u, 0x00u, 0x98u, 0x05u, 0x00u, 0x08u, 0x04u, 0x20u, 0x70u, 0x47u, 0x13u, 0x4bu, 0x1bu, 0x68u, + 0x78u, 0xf0u, 0x01u, 0x00u, 0xa8u, 0x05u, 0x00u, 0x08u, 0x04u, 0x20u, 0x70u, 0x47u, 0x13u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0x5bu, 0x8cu, 0xd9u, 0xb2u, 0x1bu, 0x0au, 0xdau, 0xb2u, 0x01u, 0x29u, 0x05u, 0xd1u, 0x00u, 0x20u, 0x83u, 0x42u, 0x01u, 0xd0u, 0x74u, 0x2bu, 0x0bu, 0xd1u, 0x70u, 0x47u, 0x02u, 0x29u, 0x0du, 0xd1u, 0x01u, 0x20u, 0x00u, 0x2bu, 0xf9u, 0xd0u, 0x68u, 0x3au, 0x10u, 0x00u, 0x43u, 0x42u, 0x58u, 0x41u, 0xc0u, 0xb2u, 0xf3u, 0xe7u, 0x7cu, 0x3bu, 0x58u, 0x42u, 0x58u, 0x41u, 0x40u, 0x00u, 0xeeu, 0xe7u, 0x00u, 0x20u, 0x81u, 0x42u, 0xebu, 0xd1u, - 0x08u, 0x00u, 0x44u, 0x2bu, 0xe8u, 0xd1u, 0x03u, 0x20u, 0xe6u, 0xe7u, 0xc0u, 0x46u, 0x98u, 0x05u, 0x00u, 0x08u, + 0x08u, 0x00u, 0x44u, 0x2bu, 0xe8u, 0xd1u, 0x03u, 0x20u, 0xe6u, 0xe7u, 0xc0u, 0x46u, 0xa8u, 0x05u, 0x00u, 0x08u, 0x03u, 0x4bu, 0x1bu, 0x68u, 0x18u, 0x1eu, 0x01u, 0xd0u, 0x1bu, 0x68u, 0x18u, 0x78u, 0x70u, 0x47u, 0xc0u, 0x46u, - 0x98u, 0x05u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x91u, 0x4cu, 0xa5u, 0x44u, 0x0bu, 0x93u, 0x90u, 0x4bu, 0x08u, 0x90u, + 0xa8u, 0x05u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x91u, 0x4cu, 0xa5u, 0x44u, 0x0bu, 0x93u, 0x90u, 0x4bu, 0x08u, 0x90u, 0x0cu, 0x00u, 0x0au, 0x92u, 0x99u, 0x42u, 0x00u, 0xd8u, 0x11u, 0xe1u, 0x80u, 0x22u, 0x8du, 0x4bu, 0xd2u, 0x05u, 0x5du, 0x69u, 0x06u, 0x93u, 0x15u, 0x40u, 0x10u, 0xd0u, 0x07u, 0x22u, 0x5bu, 0x69u, 0x13u, 0x40u, 0x02u, 0x2bu, - 0x22u, 0xd1u, 0x05u, 0x20u, 0x01u, 0xf0u, 0xa4u, 0xffu, 0x87u, 0x4bu, 0x05u, 0x00u, 0x98u, 0x42u, 0xf8u, 0xd0u, + 0x22u, 0xd1u, 0x05u, 0x20u, 0x01u, 0xf0u, 0xa8u, 0xffu, 0x87u, 0x4bu, 0x05u, 0x00u, 0x98u, 0x42u, 0xf8u, 0xd0u, 0x01u, 0x23u, 0x04u, 0x93u, 0xdbu, 0x18u, 0x03u, 0x93u, 0x1bu, 0xe0u, 0x06u, 0x9au, 0x83u, 0x4bu, 0xb0u, 0x21u, 0xd3u, 0x58u, 0xe8u, 0x22u, 0x49u, 0x05u, 0xd2u, 0x00u, 0x8au, 0x5cu, 0x1fu, 0x21u, 0x0bu, 0x40u, 0x93u, 0x42u, - 0x36u, 0xd1u, 0x01u, 0x20u, 0x01u, 0xf0u, 0xceu, 0xffu, 0x7bu, 0x4bu, 0x05u, 0x00u, 0x98u, 0x42u, 0xf8u, 0xd0u, + 0x36u, 0xd1u, 0x01u, 0x20u, 0x01u, 0xf0u, 0xd2u, 0xffu, 0x7bu, 0x4bu, 0x05u, 0x00u, 0x98u, 0x42u, 0xf8u, 0xd0u, 0x00u, 0x23u, 0x04u, 0x93u, 0x05u, 0x33u, 0xe6u, 0xe7u, 0xdbu, 0xb2u, 0x03u, 0x93u, 0x01u, 0x23u, 0x00u, 0x25u, 0x04u, 0x93u, 0xf0u, 0x23u, 0x1bu, 0x06u, 0xe3u, 0x18u, 0x5eu, 0x0au, 0x09u, 0x93u, 0x76u, 0x02u, 0x00u, 0x21u, 0x03u, 0x20u, 0x01u, 0xf0u, 0xfdu, 0xf8u, 0x00u, 0x28u, 0xf9u, 0xd1u, 0x0cu, 0xabu, 0x9bu, 0x1bu, 0x02u, 0x93u, 0x05u, 0x90u, 0x02u, 0x00u, 0x00u, 0x90u, 0x04u, 0x00u, 0x00u, 0x2du, 0x42u, 0xd0u, 0x00u, 0x2au, 0x01u, 0xd0u, - 0x01u, 0xf0u, 0x8au, 0xfcu, 0x00u, 0x21u, 0x03u, 0x20u, 0x01u, 0xf0u, 0x24u, 0xf9u, 0x00u, 0x28u, 0xf9u, 0xd1u, + 0x01u, 0xf0u, 0x8eu, 0xfcu, 0x00u, 0x21u, 0x03u, 0x20u, 0x01u, 0xf0u, 0x24u, 0xf9u, 0x00u, 0x28u, 0xf9u, 0xd1u, 0x00u, 0x2du, 0x00u, 0xd1u, 0x8eu, 0xe0u, 0x66u, 0x48u, 0x8du, 0x23u, 0x9bu, 0x00u, 0x9du, 0x44u, 0xf0u, 0xbdu, 0x01u, 0x23u, 0x04u, 0x93u, 0x04u, 0x33u, 0xb6u, 0xe7u, 0x80u, 0x23u, 0x5bu, 0x05u, 0xf3u, 0x18u, 0x1bu, 0x78u, 0x02u, 0x99u, 0x8bu, 0x55u, 0x4du, 0xe0u, 0x5fu, 0x4bu, 0x9cu, 0x42u, 0x00u, 0xd0u, 0xa9u, 0xe0u, 0x00u, 0xf0u, 0x43u, 0xfeu, 0x5du, 0x4bu, 0x04u, 0x00u, 0x98u, 0x42u, 0xf9u, 0xd0u, 0x00u, 0x28u, 0x62u, 0xd1u, 0xc8u, 0x27u, - 0x0cu, 0xa9u, 0x30u, 0x00u, 0x00u, 0xf0u, 0x3cu, 0xfeu, 0x04u, 0x00u, 0x01u, 0x20u, 0x01u, 0xf0u, 0x52u, 0xfcu, + 0x0cu, 0xa9u, 0x30u, 0x00u, 0x00u, 0xf0u, 0x3cu, 0xfeu, 0x04u, 0x00u, 0x01u, 0x20u, 0x01u, 0xf0u, 0x56u, 0xfcu, 0xa4u, 0x23u, 0xa4u, 0x22u, 0xdbu, 0x03u, 0x23u, 0x40u, 0xd2u, 0x03u, 0x93u, 0x42u, 0x52u, 0xd1u, 0x01u, 0x3fu, 0x00u, 0x2fu, 0xedu, 0xd1u, 0x51u, 0x4au, 0x02u, 0x9bu, 0x94u, 0x46u, 0x07u, 0x9eu, 0x63u, 0x44u, 0x01u, 0x9au, 0x02u, 0x93u, 0x00u, 0x2cu, 0xbau, 0xd1u, 0x00u, 0x9bu, 0x0au, 0x99u, 0x8bu, 0x42u, 0xb6u, 0xd2u, 0x80u, 0x23u, @@ -148,14 +148,14 @@ const uint8_t cy_m0p_image[] = { 0x1bu, 0x78u, 0x5bu, 0x1au, 0x59u, 0x1eu, 0x8bu, 0x41u, 0xdbu, 0xb2u, 0x01u, 0x93u, 0x00u, 0x9bu, 0x01u, 0x33u, 0x00u, 0x93u, 0x07u, 0x9bu, 0x01u, 0x36u, 0xb3u, 0x42u, 0xdeu, 0xd1u, 0x01u, 0x9bu, 0x00u, 0x2bu, 0x27u, 0xd0u, 0x05u, 0x9bu, 0x37u, 0x4au, 0x9eu, 0x18u, 0x07u, 0x9bu, 0xf6u, 0x18u, 0x0bu, 0x9bu, 0x00u, 0x2bu, 0x19u, 0xd1u, - 0xc8u, 0x27u, 0x30u, 0x00u, 0x00u, 0xf0u, 0x74u, 0xfdu, 0x04u, 0x00u, 0x01u, 0x20u, 0x01u, 0xf0u, 0x02u, 0xfcu, + 0xc8u, 0x27u, 0x30u, 0x00u, 0x00u, 0xf0u, 0x74u, 0xfdu, 0x04u, 0x00u, 0x01u, 0x20u, 0x01u, 0xf0u, 0x06u, 0xfcu, 0xa4u, 0x23u, 0xa4u, 0x22u, 0xdbu, 0x03u, 0x23u, 0x40u, 0xd2u, 0x03u, 0x93u, 0x42u, 0x93u, 0xd1u, 0x01u, 0x3fu, 0x00u, 0x2fu, 0xeeu, 0xd1u, 0x27u, 0x4bu, 0x9cu, 0x42u, 0xacu, 0xd1u, 0x00u, 0xf0u, 0xd5u, 0xfdu, 0x26u, 0x4bu, 0x04u, 0x00u, 0xf8u, 0xe7u, 0x0cu, 0xa9u, 0x30u, 0x00u, 0x00u, 0xf0u, 0x98u, 0xfdu, 0x04u, 0x00u, 0xa1u, 0xe7u, 0x01u, 0x92u, 0x9fu, 0xe7u, 0x06u, 0x9bu, 0x5bu, 0x69u, 0x5bu, 0x00u, 0x09u, 0xd5u, 0x03u, 0x9bu, 0x02u, 0x2bu, - 0x06u, 0xd1u, 0x02u, 0x20u, 0x01u, 0xf0u, 0xc4u, 0xfeu, 0x17u, 0x4bu, 0x05u, 0x00u, 0x98u, 0x42u, 0xf8u, 0xd0u, + 0x06u, 0xd1u, 0x02u, 0x20u, 0x01u, 0xf0u, 0xc8u, 0xfeu, 0x17u, 0x4bu, 0x05u, 0x00u, 0x98u, 0x42u, 0xf8u, 0xd0u, 0x06u, 0x9bu, 0x1bu, 0x68u, 0x1bu, 0x02u, 0x09u, 0xd4u, 0x04u, 0x9bu, 0x00u, 0x2bu, 0x06u, 0xd1u, 0x00u, 0x20u, - 0x01u, 0xf0u, 0xf8u, 0xfeu, 0x10u, 0x4bu, 0x05u, 0x00u, 0x98u, 0x42u, 0xf8u, 0xd0u, 0x00u, 0x2du, 0x00u, 0xd0u, + 0x01u, 0xf0u, 0xfcu, 0xfeu, 0x10u, 0x4bu, 0x05u, 0x00u, 0x98u, 0x42u, 0xf8u, 0xd0u, 0x00u, 0x2du, 0x00u, 0xd0u, 0x51u, 0xe7u, 0x14u, 0x4bu, 0x9cu, 0x42u, 0x0au, 0xd0u, 0x13u, 0x4bu, 0x9cu, 0x42u, 0x07u, 0xd0u, 0x60u, 0x42u, 0x60u, 0x41u, 0x12u, 0x4cu, 0x40u, 0x42u, 0x12u, 0x4bu, 0x20u, 0x40u, 0xc0u, 0x18u, 0x44u, 0xe7u, 0x11u, 0x48u, 0x42u, 0xe7u, 0x00u, 0x2cu, 0x00u, 0xd0u, 0x6du, 0xe7u, 0x59u, 0xe7u, 0xc0u, 0x46u, 0xccu, 0xfdu, 0xffu, 0xffu, @@ -165,93 +165,93 @@ const uint8_t cy_m0p_image[] = { 0x13u, 0x00u, 0x16u, 0x00u, 0x01u, 0x00u, 0x16u, 0x00u, 0x10u, 0xb5u, 0x00u, 0x24u, 0x08u, 0x4bu, 0x1bu, 0x68u, 0x3au, 0x33u, 0x1bu, 0x78u, 0xa3u, 0x42u, 0x01u, 0xd8u, 0x00u, 0x20u, 0x10u, 0xbdu, 0x20u, 0x00u, 0x01u, 0xf0u, 0xadu, 0xf8u, 0x03u, 0x28u, 0x01u, 0xd0u, 0x01u, 0x34u, 0xf0u, 0xe7u, 0x01u, 0x20u, 0xf5u, 0xe7u, 0xc0u, 0x46u, - 0xc8u, 0x12u, 0x00u, 0x08u, 0x01u, 0x4bu, 0x18u, 0x68u, 0x70u, 0x47u, 0xc0u, 0x46u, 0x34u, 0x06u, 0x00u, 0x08u, + 0xd8u, 0x12u, 0x00u, 0x08u, 0x01u, 0x4bu, 0x18u, 0x68u, 0x70u, 0x47u, 0xc0u, 0x46u, 0x44u, 0x06u, 0x00u, 0x08u, 0xa0u, 0x23u, 0x03u, 0x4au, 0xdbu, 0x00u, 0xd0u, 0x58u, 0x01u, 0x23u, 0x18u, 0x40u, 0x70u, 0x47u, 0xc0u, 0x46u, 0x00u, 0x00u, 0x26u, 0x40u, 0xa0u, 0x23u, 0x03u, 0x4au, 0xdbu, 0x00u, 0xd0u, 0x58u, 0x03u, 0x23u, 0x18u, 0x40u, 0x70u, 0x47u, 0xc0u, 0x46u, 0x00u, 0x00u, 0x26u, 0x40u, 0x02u, 0x4au, 0x03u, 0x4bu, 0xd0u, 0x58u, 0xc0u, 0x0fu, 0x70u, 0x47u, 0xc0u, 0x46u, 0x00u, 0x00u, 0x26u, 0x40u, 0x1cu, 0x05u, 0x00u, 0x00u, 0x10u, 0xb5u, 0x01u, 0xf0u, - 0x45u, 0xfau, 0x10u, 0xbdu, 0x70u, 0xb5u, 0x04u, 0x00u, 0x03u, 0x20u, 0x0du, 0x00u, 0x16u, 0x00u, 0x01u, 0xf0u, + 0x49u, 0xfau, 0x10u, 0xbdu, 0x70u, 0xb5u, 0x04u, 0x00u, 0x03u, 0x20u, 0x0du, 0x00u, 0x16u, 0x00u, 0x01u, 0xf0u, 0x33u, 0xf8u, 0x05u, 0x4bu, 0x98u, 0x42u, 0x05u, 0xd0u, 0x32u, 0x00u, 0x29u, 0x00u, 0x20u, 0x00u, 0x01u, 0xf0u, - 0x7fu, 0xf9u, 0x70u, 0xbdu, 0x01u, 0x48u, 0xfcu, 0xe7u, 0x01u, 0x01u, 0x88u, 0x00u, 0x03u, 0x00u, 0x4au, 0x00u, + 0x83u, 0xf9u, 0x70u, 0xbdu, 0x01u, 0x48u, 0xfcu, 0xe7u, 0x01u, 0x01u, 0x88u, 0x00u, 0x03u, 0x00u, 0x4au, 0x00u, 0xf8u, 0xb5u, 0x0bu, 0x00u, 0x11u, 0x00u, 0xc2u, 0x1au, 0xd5u, 0x17u, 0x54u, 0x19u, 0x6cu, 0x40u, 0x8cu, 0x42u, 0x21u, 0xd3u, 0x12u, 0x4eu, 0x12u, 0x4du, 0x4fu, 0x08u, 0x74u, 0x59u, 0xa4u, 0x05u, 0xa4u, 0x0du, 0x98u, 0x42u, - 0x0fu, 0xd9u, 0xd0u, 0x19u, 0x02u, 0xf0u, 0x5cu, 0xf9u, 0x20u, 0x1au, 0xc3u, 0x43u, 0xdbu, 0x17u, 0x18u, 0x40u, + 0x0fu, 0xd9u, 0xd0u, 0x19u, 0x02u, 0xf0u, 0x60u, 0xf9u, 0x20u, 0x1au, 0xc3u, 0x43u, 0xdbu, 0x17u, 0x18u, 0x40u, 0x73u, 0x59u, 0x82u, 0x05u, 0x9bu, 0x0au, 0x9bu, 0x02u, 0x92u, 0x0du, 0x13u, 0x43u, 0x73u, 0x51u, 0x20u, 0x1au, - 0xf8u, 0xbdu, 0xdbu, 0x19u, 0x18u, 0x1au, 0x02u, 0xf0u, 0x4bu, 0xf9u, 0x06u, 0x4bu, 0x00u, 0x19u, 0x98u, 0x42u, + 0xf8u, 0xbdu, 0xdbu, 0x19u, 0x18u, 0x1au, 0x02u, 0xf0u, 0x4fu, 0xf9u, 0x06u, 0x4bu, 0x00u, 0x19u, 0x98u, 0x42u, 0xeeu, 0xd9u, 0x18u, 0x00u, 0xecu, 0xe7u, 0x00u, 0x24u, 0x20u, 0x00u, 0xf0u, 0xe7u, 0x00u, 0x00u, 0x26u, 0x40u, 0x3cu, 0x05u, 0x00u, 0x00u, 0xffu, 0x03u, 0x00u, 0x00u, 0x80u, 0x21u, 0x10u, 0xb5u, 0x02u, 0x4bu, 0x09u, 0x02u, 0x1au, 0x68u, 0xffu, 0xf7u, 0xc5u, 0xffu, 0x10u, 0xbdu, 0xdcu, 0x00u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x01u, 0xf0u, - 0x01u, 0xfbu, 0x10u, 0xbdu, 0x06u, 0x4bu, 0x10u, 0xb5u, 0x1bu, 0x68u, 0x5bu, 0x68u, 0x00u, 0x2bu, 0x06u, 0xd0u, + 0x05u, 0xfbu, 0x10u, 0xbdu, 0x06u, 0x4bu, 0x10u, 0xb5u, 0x1bu, 0x68u, 0x5bu, 0x68u, 0x00u, 0x2bu, 0x06u, 0xd0u, 0x1bu, 0x68u, 0x00u, 0x2bu, 0x03u, 0xd0u, 0x00u, 0x20u, 0x18u, 0x5eu, 0xffu, 0xf7u, 0x8du, 0xfdu, 0x10u, 0xbdu, - 0x98u, 0x05u, 0x00u, 0x08u, 0x07u, 0x4bu, 0x10u, 0xb5u, 0x1bu, 0x68u, 0x5bu, 0x68u, 0x00u, 0x2bu, 0x08u, 0xd0u, + 0xa8u, 0x05u, 0x00u, 0x08u, 0x07u, 0x4bu, 0x10u, 0xb5u, 0x1bu, 0x68u, 0x5bu, 0x68u, 0x00u, 0x2bu, 0x08u, 0xd0u, 0x1bu, 0x68u, 0x00u, 0x2bu, 0x05u, 0xd0u, 0x00u, 0x20u, 0x18u, 0x5eu, 0x00u, 0x28u, 0x01u, 0xdbu, 0xffu, 0xf7u, - 0xafu, 0xfdu, 0x10u, 0xbdu, 0x98u, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0xffu, 0xf7u, 0x96u, 0xfbu, 0x10u, 0xbdu, - 0x10u, 0xb5u, 0xffu, 0xf7u, 0x96u, 0xfbu, 0x10u, 0xbdu, 0x10u, 0xb5u, 0x01u, 0xf0u, 0x05u, 0xfdu, 0x10u, 0xbdu, - 0x10u, 0xb5u, 0x00u, 0x21u, 0x01u, 0xf0u, 0x50u, 0xfcu, 0x10u, 0xbdu, 0x00u, 0x00u, 0x10u, 0xb5u, 0x03u, 0x22u, + 0xafu, 0xfdu, 0x10u, 0xbdu, 0xa8u, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0xffu, 0xf7u, 0x96u, 0xfbu, 0x10u, 0xbdu, + 0x10u, 0xb5u, 0xffu, 0xf7u, 0x96u, 0xfbu, 0x10u, 0xbdu, 0x10u, 0xb5u, 0x01u, 0xf0u, 0x09u, 0xfdu, 0x10u, 0xbdu, + 0x10u, 0xb5u, 0x00u, 0x21u, 0x01u, 0xf0u, 0x54u, 0xfcu, 0x10u, 0xbdu, 0x00u, 0x00u, 0x10u, 0xb5u, 0x03u, 0x22u, 0x05u, 0x49u, 0x00u, 0x20u, 0x00u, 0xf0u, 0x38u, 0xfeu, 0x43u, 0x1eu, 0x98u, 0x41u, 0x03u, 0x4bu, 0x40u, 0x42u, 0x18u, 0x40u, 0x03u, 0x4bu, 0xc0u, 0x18u, 0x10u, 0xbdu, 0x01u, 0x05u, 0x00u, 0x10u, 0xfeu, 0xffu, 0xe9u, 0xffu, 0x02u, 0x00u, 0x16u, 0x00u, 0x10u, 0xb5u, 0x0au, 0x00u, 0x00u, 0x28u, 0x09u, 0xd0u, 0xfau, 0x23u, 0xffu, 0x33u, 0x99u, 0x42u, 0x05u, 0xd8u, 0xf9u, 0x3bu, 0xffu, 0x3bu, 0x02u, 0x49u, 0xffu, 0xf7u, 0xd3u, 0xfdu, 0x10u, 0xbdu, 0x01u, 0x48u, 0xfcu, 0xe7u, 0x07u, 0x08u, 0x00u, 0x16u, 0x01u, 0x00u, 0x16u, 0x00u, 0x10u, 0xb5u, 0x0au, 0x00u, 0x00u, 0x28u, 0x08u, 0xd0u, 0xfau, 0x23u, 0xffu, 0x33u, 0x99u, 0x42u, 0x04u, 0xd8u, 0x03u, 0x49u, 0x03u, 0xf0u, - 0x0au, 0xfeu, 0x00u, 0x20u, 0x10u, 0xbdu, 0x02u, 0x48u, 0xfcu, 0xe7u, 0xc0u, 0x46u, 0x07u, 0x08u, 0x00u, 0x16u, + 0x0eu, 0xfeu, 0x00u, 0x20u, 0x10u, 0xbdu, 0x02u, 0x48u, 0xfcu, 0xe7u, 0xc0u, 0x46u, 0x07u, 0x08u, 0x00u, 0x16u, 0x01u, 0x00u, 0x16u, 0x00u, 0x10u, 0xb5u, 0x00u, 0x20u, 0x00u, 0xf0u, 0x84u, 0xfeu, 0x10u, 0xbdu, 0x00u, 0x00u, - 0x01u, 0x4bu, 0x18u, 0x60u, 0x70u, 0x47u, 0xc0u, 0x46u, 0x98u, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x00u, 0x20u, + 0x01u, 0x4bu, 0x18u, 0x60u, 0x70u, 0x47u, 0xc0u, 0x46u, 0xa8u, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x00u, 0x20u, 0x00u, 0xf0u, 0x5eu, 0xfeu, 0x10u, 0xbdu, 0x00u, 0x00u, 0x07u, 0x4bu, 0x10u, 0xb5u, 0x01u, 0x22u, 0x19u, 0x60u, 0x01u, 0x00u, 0x00u, 0x20u, 0x00u, 0xf0u, 0xe8u, 0xfdu, 0x00u, 0x28u, 0x03u, 0xd1u, 0x02u, 0x00u, 0x03u, 0x49u, - 0x00u, 0xf0u, 0xe2u, 0xfdu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0x90u, 0x05u, 0x00u, 0x08u, 0xf1u, 0x04u, 0x00u, 0x10u, + 0x00u, 0xf0u, 0xe2u, 0xfdu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0xa0u, 0x05u, 0x00u, 0x08u, 0xf1u, 0x04u, 0x00u, 0x10u, 0x70u, 0xb5u, 0x0bu, 0x00u, 0x15u, 0x00u, 0x00u, 0x21u, 0x02u, 0x00u, 0x01u, 0x20u, 0x00u, 0xf0u, 0xa4u, 0xfdu, 0x04u, 0x1eu, 0x03u, 0xd0u, 0x29u, 0x00u, 0x00u, 0x20u, 0x00u, 0xf0u, 0xe2u, 0xfdu, 0x20u, 0x00u, 0x70u, 0xbdu, 0x03u, 0x88u, 0xaeu, 0x20u, 0x58u, 0x43u, 0x04u, 0x4bu, 0x10u, 0xb5u, 0xc0u, 0x18u, 0x0cu, 0x00u, 0x0au, 0x21u, - 0x02u, 0xf0u, 0x7eu, 0xf8u, 0x20u, 0x80u, 0x10u, 0xbdu, 0x91u, 0xfcu, 0xffu, 0xffu, 0x00u, 0x22u, 0x83u, 0x5eu, - 0x04u, 0x48u, 0x10u, 0xb5u, 0x58u, 0x43u, 0x0cu, 0x00u, 0x03u, 0x49u, 0x02u, 0xf0u, 0xfbu, 0xf8u, 0xbdu, 0x30u, + 0x02u, 0xf0u, 0x82u, 0xf8u, 0x20u, 0x80u, 0x10u, 0xbdu, 0x91u, 0xfcu, 0xffu, 0xffu, 0x00u, 0x22u, 0x83u, 0x5eu, + 0x04u, 0x48u, 0x10u, 0xb5u, 0x58u, 0x43u, 0x0cu, 0x00u, 0x03u, 0x49u, 0x02u, 0xf0u, 0xffu, 0xf8u, 0xbdu, 0x30u, 0x20u, 0x80u, 0x10u, 0xbdu, 0xb5u, 0xd7u, 0xffu, 0xffu, 0x10u, 0x27u, 0x00u, 0x00u, 0xf8u, 0xb5u, 0x80u, 0x23u, 0xfau, 0x27u, 0x0eu, 0x00u, 0x01u, 0x25u, 0x1bu, 0x02u, 0x18u, 0x43u, 0x0cu, 0x4cu, 0x00u, 0x04u, 0xe0u, 0x61u, 0xbfu, 0x00u, 0x23u, 0x6cu, 0x2bu, 0x42u, 0x08u, 0xd1u, 0x00u, 0x2fu, 0x01u, 0xd1u, 0x08u, 0x48u, 0x0cu, 0xe0u, - 0x28u, 0x00u, 0x01u, 0x3fu, 0x01u, 0xf0u, 0x26u, 0xfau, 0xf3u, 0xe7u, 0x00u, 0x2fu, 0xf6u, 0xd0u, 0x00u, 0x20u, + 0x28u, 0x00u, 0x01u, 0x3fu, 0x01u, 0xf0u, 0x2au, 0xfau, 0xf3u, 0xe7u, 0x00u, 0x2fu, 0xf6u, 0xd0u, 0x00u, 0x20u, 0x23u, 0x6cu, 0x1du, 0x43u, 0x25u, 0x64u, 0xe3u, 0x6au, 0x33u, 0x80u, 0xf8u, 0xbdu, 0x00u, 0x00u, 0x3cu, 0x40u, 0x04u, 0x00u, 0x16u, 0x00u, 0x70u, 0xb5u, 0xfau, 0x26u, 0x01u, 0x25u, 0x00u, 0x04u, 0x0bu, 0x4cu, 0x01u, 0x43u, 0xe1u, 0x61u, 0xb6u, 0x00u, 0x23u, 0x6cu, 0x2bu, 0x42u, 0x08u, 0xd1u, 0x00u, 0x2eu, 0x01u, 0xd1u, 0x08u, 0x48u, - 0x0au, 0xe0u, 0x28u, 0x00u, 0x01u, 0x3eu, 0x01u, 0xf0u, 0x05u, 0xfau, 0xf3u, 0xe7u, 0x00u, 0x2eu, 0xf6u, 0xd0u, + 0x0au, 0xe0u, 0x28u, 0x00u, 0x01u, 0x3eu, 0x01u, 0xf0u, 0x09u, 0xfau, 0xf3u, 0xe7u, 0x00u, 0x2eu, 0xf6u, 0xd0u, 0x00u, 0x20u, 0x23u, 0x6cu, 0x1du, 0x43u, 0x25u, 0x64u, 0x70u, 0xbdu, 0xc0u, 0x46u, 0x00u, 0x00u, 0x3cu, 0x40u, 0x04u, 0x00u, 0x16u, 0x00u, 0x10u, 0x23u, 0x04u, 0x49u, 0x04u, 0x4au, 0x88u, 0x58u, 0x03u, 0x43u, 0x8bu, 0x50u, 0x00u, 0x22u, 0x03u, 0x4bu, 0x1au, 0x60u, 0x70u, 0x47u, 0x00u, 0x00u, 0x3cu, 0x40u, 0x70u, 0xf0u, 0x01u, 0x00u, - 0x34u, 0x06u, 0x00u, 0x08u, 0x10u, 0xb5u, 0xffu, 0xf7u, 0xedu, 0xffu, 0x10u, 0xbdu, 0xf0u, 0xb5u, 0x1bu, 0x4bu, + 0x44u, 0x06u, 0x00u, 0x08u, 0x10u, 0xb5u, 0xffu, 0xf7u, 0xedu, 0xffu, 0x10u, 0xbdu, 0xf0u, 0xb5u, 0x1bu, 0x4bu, 0x9du, 0xb0u, 0x01u, 0xa9u, 0x0au, 0x00u, 0x18u, 0x00u, 0x70u, 0xc8u, 0x70u, 0xc2u, 0x70u, 0xc8u, 0x70u, 0xc2u, 0x70u, 0xc8u, 0x70u, 0xc2u, 0x0au, 0xacu, 0x1au, 0x00u, 0x20u, 0x00u, 0x24u, 0x32u, 0xe0u, 0xcau, 0xe0u, 0xc0u, 0xe0u, 0xcau, 0xe0u, 0xc0u, 0xe0u, 0xcau, 0xe0u, 0xc0u, 0x13u, 0xadu, 0x2au, 0x00u, 0x48u, 0x33u, 0xc1u, 0xcbu, 0xc1u, 0xc2u, 0xc1u, 0xcbu, 0xc1u, 0xc2u, 0xc1u, 0xcbu, 0xc1u, 0xc2u, 0x0du, 0x4eu, 0x33u, 0x68u, 0x98u, 0x69u, 0x01u, 0x30u, 0xffu, 0x30u, 0x00u, 0xf0u, 0x02u, 0xfcu, 0x33u, 0x68u, 0x21u, 0x00u, 0x98u, 0x69u, 0x81u, 0x30u, 0xffu, 0x30u, 0x00u, 0xf0u, 0xfbu, 0xfbu, 0x33u, 0x68u, 0x29u, 0x00u, 0x98u, 0x69u, 0x80u, 0x23u, 0x9bu, 0x00u, - 0xc0u, 0x18u, 0x00u, 0xf0u, 0xf3u, 0xfbu, 0x1du, 0xb0u, 0xf0u, 0xbdu, 0xc0u, 0x46u, 0xe0u, 0x46u, 0x00u, 0x10u, - 0xc8u, 0x12u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x89u, 0xb0u, 0x02u, 0x93u, 0x0eu, 0xabu, 0x1bu, 0x78u, 0x03u, 0x90u, + 0xc0u, 0x18u, 0x00u, 0xf0u, 0xf3u, 0xfbu, 0x1du, 0xb0u, 0xf0u, 0xbdu, 0xc0u, 0x46u, 0xe8u, 0x46u, 0x00u, 0x10u, + 0xd8u, 0x12u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x89u, 0xb0u, 0x02u, 0x93u, 0x0eu, 0xabu, 0x1bu, 0x78u, 0x03u, 0x90u, 0x00u, 0x91u, 0x04u, 0x92u, 0x05u, 0x93u, 0x01u, 0x28u, 0x00u, 0xd9u, 0x49u, 0xe1u, 0x03u, 0x29u, 0x00u, 0xd9u, 0x46u, 0xe1u, 0x02u, 0x9bu, 0x0cu, 0x3bu, 0x87u, 0x2bu, 0x00u, 0xd9u, 0x41u, 0xe1u, 0xfbu, 0x2au, 0x00u, 0xd9u, - 0x3eu, 0xe1u, 0xa2u, 0x4cu, 0x63u, 0x68u, 0x9bu, 0x03u, 0x01u, 0xd5u, 0x01u, 0xf0u, 0xf7u, 0xfbu, 0x01u, 0x22u, + 0x3eu, 0xe1u, 0xa2u, 0x4cu, 0x63u, 0x68u, 0x9bu, 0x03u, 0x01u, 0xd5u, 0x01u, 0xf0u, 0xfbu, 0xfbu, 0x01u, 0x22u, 0x9fu, 0x4bu, 0xa0u, 0x49u, 0x1eu, 0x00u, 0x58u, 0x58u, 0x01u, 0x91u, 0x10u, 0x42u, 0x04u, 0xd0u, 0x9eu, 0x49u, 0x5bu, 0x58u, 0x13u, 0x42u, 0x00u, 0xd0u, 0x2du, 0xe1u, 0xffu, 0xf7u, 0x98u, 0xffu, 0x9bu, 0x4bu, 0x9cu, 0x4au, 0xf2u, 0x50u, 0xa0u, 0x23u, 0x02u, 0x9au, 0x1bu, 0x03u, 0x13u, 0x43u, 0x9au, 0x4au, 0xb3u, 0x50u, 0x9au, 0x4bu, 0x9au, 0x4au, 0xf2u, 0x50u, 0x9au, 0x4bu, 0x5au, 0x68u, 0x01u, 0x23u, 0x1au, 0x42u, 0x00u, 0xd0u, 0x1bu, 0xe1u, 0x98u, 0x4au, 0xb0u, 0x58u, 0x08u, 0x22u, 0x10u, 0x40u, 0x4bu, 0xd0u, 0x18u, 0x00u, 0x32u, 0x68u, 0x96u, 0x4bu, 0x40u, 0x03u, 0x18u, 0x43u, 0x80u, 0x25u, 0x02u, 0x43u, 0x32u, 0x60u, 0x63u, 0x69u, 0xedu, 0x05u, 0x2bu, 0x42u, - 0x5bu, 0xd0u, 0x05u, 0x9bu, 0x00u, 0x2bu, 0x58u, 0xd1u, 0x01u, 0x21u, 0x03u, 0x20u, 0x01u, 0xf0u, 0xd4u, 0xfau, - 0x8eu, 0x4bu, 0x62u, 0x69u, 0x1bu, 0x68u, 0x42u, 0x33u, 0x1bu, 0x78u, 0x00u, 0x2bu, 0x04u, 0xd0u, 0x2au, 0x42u, + 0x5bu, 0xd0u, 0x05u, 0x9bu, 0x00u, 0x2bu, 0x58u, 0xd1u, 0x01u, 0x21u, 0x03u, 0x20u, 0x01u, 0xf0u, 0xd8u, 0xfau, + 0x8eu, 0x4bu, 0x62u, 0x69u, 0x1bu, 0x68u, 0x43u, 0x33u, 0x1bu, 0x78u, 0x00u, 0x2bu, 0x04u, 0xd0u, 0x2au, 0x42u, 0x02u, 0xd0u, 0xa3u, 0x69u, 0x1du, 0x43u, 0xa5u, 0x61u, 0x01u, 0x9bu, 0x01u, 0x9au, 0xf7u, 0x58u, 0x88u, 0x4bu, - 0x40u, 0x20u, 0x3bu, 0x43u, 0xb3u, 0x50u, 0x01u, 0xf0u, 0x3du, 0xf9u, 0x01u, 0x23u, 0x85u, 0x4cu, 0x32u, 0x59u, - 0x1au, 0x42u, 0x08u, 0xd1u, 0x33u, 0x51u, 0x40u, 0x20u, 0x01u, 0xf0u, 0x34u, 0xf9u, 0x03u, 0x23u, 0x40u, 0x20u, - 0x33u, 0x51u, 0x01u, 0xf0u, 0x2fu, 0xf9u, 0xfau, 0x25u, 0x7fu, 0x4bu, 0x80u, 0x4cu, 0x1fu, 0x40u, 0x01u, 0x9bu, + 0x40u, 0x20u, 0x3bu, 0x43u, 0xb3u, 0x50u, 0x01u, 0xf0u, 0x41u, 0xf9u, 0x01u, 0x23u, 0x85u, 0x4cu, 0x32u, 0x59u, + 0x1au, 0x42u, 0x08u, 0xd1u, 0x33u, 0x51u, 0x40u, 0x20u, 0x01u, 0xf0u, 0x38u, 0xf9u, 0x03u, 0x23u, 0x40u, 0x20u, + 0x33u, 0x51u, 0x01u, 0xf0u, 0x33u, 0xf9u, 0xfau, 0x25u, 0x7fu, 0x4bu, 0x80u, 0x4cu, 0x1fu, 0x40u, 0x01u, 0x9bu, 0x3cu, 0x43u, 0xf4u, 0x50u, 0xedu, 0x00u, 0x79u, 0x4bu, 0x1bu, 0x68u, 0x9au, 0x69u, 0x7cu, 0x4bu, 0xd3u, 0x58u, 0x10u, 0x22u, 0x13u, 0x42u, 0x2cu, 0xd1u, 0x00u, 0x2du, 0x25u, 0xd1u, 0x7au, 0x4cu, 0x20u, 0x00u, 0x09u, 0xb0u, - 0xf0u, 0xbdu, 0x01u, 0xf0u, 0x5bu, 0xf8u, 0x71u, 0x4bu, 0x1bu, 0x68u, 0x1au, 0x1du, 0xd2u, 0x6fu, 0x1bu, 0x68u, - 0x9bu, 0x18u, 0x19u, 0x68u, 0x09u, 0x0eu, 0x01u, 0x31u, 0x4bu, 0x08u, 0x18u, 0x18u, 0x01u, 0xf0u, 0x38u, 0xffu, - 0x71u, 0x49u, 0x88u, 0x42u, 0x02u, 0xd8u, 0x32u, 0x68u, 0x70u, 0x48u, 0xa3u, 0xe7u, 0x01u, 0xf0u, 0x30u, 0xffu, + 0xf0u, 0xbdu, 0x01u, 0xf0u, 0x5fu, 0xf8u, 0x71u, 0x4bu, 0x1bu, 0x68u, 0x1au, 0x1du, 0xd2u, 0x6fu, 0x1bu, 0x68u, + 0x9bu, 0x18u, 0x19u, 0x68u, 0x09u, 0x0eu, 0x01u, 0x31u, 0x4bu, 0x08u, 0x18u, 0x18u, 0x01u, 0xf0u, 0x3cu, 0xffu, + 0x71u, 0x49u, 0x88u, 0x42u, 0x02u, 0xd8u, 0x32u, 0x68u, 0x70u, 0x48u, 0xa3u, 0xe7u, 0x01u, 0xf0u, 0x34u, 0xffu, 0x01u, 0x38u, 0x32u, 0x68u, 0x00u, 0x28u, 0xf7u, 0xd0u, 0x99u, 0xe7u, 0x03u, 0x23u, 0x6cu, 0x4au, 0xb1u, 0x58u, - 0x0bu, 0x43u, 0xb3u, 0x50u, 0xb0u, 0xe7u, 0x01u, 0x20u, 0x01u, 0x3du, 0x01u, 0xf0u, 0xf3u, 0xf8u, 0xcau, 0xe7u, + 0x0bu, 0x43u, 0xb3u, 0x50u, 0xb0u, 0xe7u, 0x01u, 0x20u, 0x01u, 0x3du, 0x01u, 0xf0u, 0xf7u, 0xf8u, 0xcau, 0xe7u, 0x00u, 0x2du, 0xd2u, 0xd0u, 0x08u, 0x23u, 0x67u, 0x4au, 0x01u, 0x20u, 0xb1u, 0x58u, 0x0bu, 0x43u, 0xb3u, 0x50u, - 0x01u, 0xf0u, 0x4eu, 0xfau, 0x00u, 0x28u, 0x02u, 0xd0u, 0x05u, 0x9bu, 0x01u, 0x2bu, 0x01u, 0xd1u, 0x62u, 0x4cu, + 0x01u, 0xf0u, 0x52u, 0xfau, 0x00u, 0x28u, 0x02u, 0xd0u, 0x05u, 0x9bu, 0x01u, 0x2bu, 0x01u, 0xd1u, 0x62u, 0x4cu, 0x3cu, 0x43u, 0x62u, 0x4bu, 0x01u, 0x9au, 0x23u, 0x40u, 0x01u, 0x24u, 0x61u, 0x4du, 0x23u, 0x43u, 0xb3u, 0x50u, 0x49u, 0x4bu, 0xf3u, 0x58u, 0x23u, 0x42u, 0x00u, 0xd0u, 0xceu, 0xe0u, 0x00u, 0x2du, 0xb5u, 0xd0u, 0x20u, 0x00u, - 0x01u, 0x3du, 0x01u, 0xf0u, 0xcfu, 0xf8u, 0xf3u, 0xe7u, 0x01u, 0x3du, 0x00u, 0x28u, 0x00u, 0xd0u, 0xdau, 0xe0u, + 0x01u, 0x3du, 0x01u, 0xf0u, 0xd3u, 0xf8u, 0xf3u, 0xe7u, 0x01u, 0x3du, 0x00u, 0x28u, 0x00u, 0xd0u, 0xdau, 0xe0u, 0x06u, 0xabu, 0xdbu, 0x88u, 0xbbu, 0x42u, 0x00u, 0xd0u, 0xc4u, 0xe0u, 0x06u, 0xabu, 0x99u, 0x1du, 0x55u, 0x48u, 0xffu, 0xf7u, 0x84u, 0xfeu, 0x04u, 0x1eu, 0x00u, 0xd0u, 0xcdu, 0xe0u, 0x06u, 0xabu, 0xdau, 0x88u, 0x80u, 0x23u, 0xdbu, 0x00u, 0x1au, 0x42u, 0x1bu, 0xd1u, 0x0au, 0x25u, 0x01u, 0x93u, 0x80u, 0x21u, 0x4du, 0x48u, 0xc9u, 0x00u, @@ -270,12 +270,12 @@ const uint8_t cy_m0p_image[] = { 0x22u, 0x4cu, 0x33u, 0xe7u, 0x22u, 0x4cu, 0x31u, 0xe7u, 0x22u, 0x4cu, 0x2fu, 0xe7u, 0x00u, 0x00u, 0x26u, 0x40u, 0x00u, 0x00u, 0x3cu, 0x40u, 0xa0u, 0xf0u, 0x01u, 0x00u, 0xb4u, 0xf0u, 0x01u, 0x00u, 0xa4u, 0xf0u, 0x01u, 0x00u, 0x06u, 0x00u, 0x00u, 0x01u, 0xa8u, 0xf0u, 0x01u, 0x00u, 0xacu, 0xf0u, 0x01u, 0x00u, 0x01u, 0x00u, 0x01u, 0x00u, - 0xfcu, 0x00u, 0x3cu, 0x40u, 0x70u, 0xf0u, 0x01u, 0x00u, 0x04u, 0x1au, 0x00u, 0x80u, 0xc8u, 0x12u, 0x00u, 0x08u, + 0xfcu, 0x00u, 0x3cu, 0x40u, 0x70u, 0xf0u, 0x01u, 0x00u, 0x04u, 0x1au, 0x00u, 0x80u, 0xd8u, 0x12u, 0x00u, 0x08u, 0x30u, 0x00u, 0x03u, 0x00u, 0xb0u, 0xf0u, 0x01u, 0x00u, 0xefu, 0xffu, 0xfeu, 0xffu, 0x20u, 0x00u, 0x02u, 0x00u, 0x10u, 0x40u, 0x00u, 0x00u, 0x04u, 0x00u, 0x16u, 0x00u, 0x00u, 0x09u, 0x3du, 0x00u, 0x04u, 0x0au, 0x00u, 0x80u, 0xc4u, 0xf0u, 0x01u, 0x00u, 0x68u, 0xf0u, 0x01u, 0x00u, 0x28u, 0x00u, 0x02u, 0x00u, 0xffu, 0xffu, 0xfbu, 0xffu, 0xf0u, 0x7eu, 0x0eu, 0x00u, 0x03u, 0x1eu, 0x00u, 0x00u, 0x09u, 0x1eu, 0x00u, 0x00u, 0x00u, 0x48u, 0xe8u, 0x01u, - 0x34u, 0x06u, 0x00u, 0x08u, 0x64u, 0xf0u, 0x01u, 0x00u, 0x00u, 0x24u, 0xf4u, 0x00u, 0x01u, 0x00u, 0x16u, 0x00u, + 0x44u, 0x06u, 0x00u, 0x08u, 0x64u, 0xf0u, 0x01u, 0x00u, 0x00u, 0x24u, 0xf4u, 0x00u, 0x01u, 0x00u, 0x16u, 0x00u, 0x03u, 0x00u, 0x16u, 0x00u, 0x02u, 0x00u, 0x16u, 0x00u, 0x00u, 0x2du, 0x00u, 0xd1u, 0xe5u, 0xe6u, 0xc0u, 0x27u, 0x0au, 0x25u, 0x7fu, 0x01u, 0xc0u, 0x21u, 0x3bu, 0x48u, 0x49u, 0x01u, 0xffu, 0xf7u, 0xe3u, 0xfdu, 0x04u, 0x1eu, 0x6cu, 0xd1u, 0x06u, 0xabu, 0x99u, 0x1du, 0x37u, 0x48u, 0xffu, 0xf7u, 0xb8u, 0xfdu, 0x04u, 0x00u, 0x00u, 0x2du, @@ -291,15 +291,15 @@ const uint8_t cy_m0p_image[] = { 0x93u, 0x43u, 0x19u, 0x43u, 0x31u, 0x80u, 0xffu, 0xf7u, 0x8du, 0xfdu, 0x04u, 0x00u, 0x00u, 0x2cu, 0x00u, 0xd0u, 0x84u, 0xe6u, 0x04u, 0x9bu, 0x12u, 0x49u, 0x5bu, 0x00u, 0x19u, 0x43u, 0x89u, 0xb2u, 0x11u, 0x48u, 0xffu, 0xf7u, 0x81u, 0xfdu, 0x04u, 0x1eu, 0x04u, 0xd1u, 0x10u, 0x49u, 0x10u, 0x48u, 0xffu, 0xf7u, 0x7bu, 0xfdu, 0x04u, 0x00u, - 0x02u, 0x9bu, 0x58u, 0x01u, 0x80u, 0xb2u, 0x00u, 0xf0u, 0x8du, 0xffu, 0x6fu, 0xe6u, 0x00u, 0x2du, 0x99u, 0xd0u, + 0x02u, 0x9bu, 0x58u, 0x01u, 0x80u, 0xb2u, 0x00u, 0xf0u, 0x91u, 0xffu, 0x6fu, 0xe6u, 0x00u, 0x2du, 0x99u, 0xd0u, 0x99u, 0xe7u, 0xc0u, 0x46u, 0x02u, 0x1eu, 0x00u, 0x00u, 0x04u, 0x00u, 0x16u, 0x00u, 0x16u, 0x18u, 0x00u, 0x00u, 0x07u, 0x1eu, 0x00u, 0x00u, 0x7fu, 0xf5u, 0xffu, 0xffu, 0xffu, 0xe7u, 0xffu, 0xffu, 0x06u, 0x1eu, 0x00u, 0x00u, 0x01u, 0x10u, 0x00u, 0x00u, 0x08u, 0x1eu, 0x00u, 0x00u, 0x37u, 0x68u, 0x00u, 0x00u, 0x0fu, 0x1eu, 0x00u, 0x00u, 0x13u, 0xb5u, 0x00u, 0x28u, 0x08u, 0xd0u, 0x00u, 0x24u, 0x03u, 0x78u, 0x42u, 0x78u, 0xc1u, 0x78u, 0x80u, 0x78u, 0x00u, 0x94u, 0xffu, 0xf7u, 0xbfu, 0xfdu, 0x16u, 0xbdu, 0x00u, 0x48u, 0xfcu, 0xe7u, 0x01u, 0x00u, 0x16u, 0x00u, - 0x01u, 0x4bu, 0x18u, 0x60u, 0x70u, 0x47u, 0xc0u, 0x46u, 0xc8u, 0x12u, 0x00u, 0x08u, 0x04u, 0x4bu, 0x1bu, 0x68u, + 0x01u, 0x4bu, 0x18u, 0x60u, 0x70u, 0x47u, 0xc0u, 0x46u, 0xd8u, 0x12u, 0x00u, 0x08u, 0x04u, 0x4bu, 0x1bu, 0x68u, 0x1au, 0x00u, 0xacu, 0x32u, 0x12u, 0x88u, 0x1bu, 0x6au, 0x50u, 0x43u, 0xc0u, 0x18u, 0x70u, 0x47u, 0xc0u, 0x46u, - 0xc8u, 0x12u, 0x00u, 0x08u, 0x1du, 0x4bu, 0x98u, 0x42u, 0x0fu, 0xd0u, 0x10u, 0xd8u, 0x40u, 0x28u, 0x2fu, 0xd0u, + 0xd8u, 0x12u, 0x00u, 0x08u, 0x1du, 0x4bu, 0x98u, 0x42u, 0x0fu, 0xd0u, 0x10u, 0xd8u, 0x40u, 0x28u, 0x2fu, 0xd0u, 0x05u, 0xd8u, 0x00u, 0x28u, 0x30u, 0xd0u, 0x10u, 0x28u, 0x28u, 0xd0u, 0x19u, 0x48u, 0x1eu, 0xe0u, 0x80u, 0x28u, 0x28u, 0xd0u, 0x80u, 0x23u, 0x5bu, 0x00u, 0x98u, 0x42u, 0xf7u, 0xd1u, 0x14u, 0x48u, 0x16u, 0xe0u, 0x15u, 0x4bu, 0x98u, 0x42u, 0x14u, 0xd0u, 0x08u, 0xd8u, 0xa0u, 0x23u, 0x1bu, 0x06u, 0x98u, 0x42u, 0x1cu, 0xd0u, 0x12u, 0x4bu, @@ -310,88 +310,88 @@ const uint8_t cy_m0p_image[] = { 0xffu, 0x00u, 0x52u, 0x00u, 0x01u, 0x00u, 0x00u, 0xf0u, 0x09u, 0x00u, 0x00u, 0xa0u, 0x04u, 0x00u, 0x00u, 0xf0u, 0x05u, 0x00u, 0x00u, 0xf0u, 0x03u, 0x00u, 0x00u, 0xf0u, 0x01u, 0x00u, 0x52u, 0x00u, 0x02u, 0x00u, 0x52u, 0x00u, 0x03u, 0x00u, 0x52u, 0x00u, 0x01u, 0x00u, 0x50u, 0x00u, 0x02u, 0x00u, 0x50u, 0x00u, 0x05u, 0x00u, 0x52u, 0x00u, - 0x10u, 0xb5u, 0x00u, 0x20u, 0x00u, 0xf0u, 0x3au, 0xfeu, 0x0bu, 0x4bu, 0x1bu, 0x68u, 0x1au, 0x1du, 0xd2u, 0x6fu, + 0x10u, 0xb5u, 0x00u, 0x20u, 0x00u, 0xf0u, 0x3eu, 0xfeu, 0x0bu, 0x4bu, 0x1bu, 0x68u, 0x1au, 0x1du, 0xd2u, 0x6fu, 0x1bu, 0x68u, 0x9bu, 0x18u, 0x19u, 0x68u, 0x1cu, 0x68u, 0x09u, 0x0eu, 0x01u, 0x31u, 0x4bu, 0x08u, 0x18u, 0x18u, - 0x01u, 0xf0u, 0x16u, 0xfdu, 0x24u, 0x0au, 0xe4u, 0xb2u, 0x01u, 0x34u, 0x63u, 0x08u, 0xc0u, 0x18u, 0x21u, 0x00u, - 0x01u, 0xf0u, 0x0eu, 0xfdu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0xc8u, 0x12u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x00u, 0x20u, + 0x01u, 0xf0u, 0x1au, 0xfdu, 0x24u, 0x0au, 0xe4u, 0xb2u, 0x01u, 0x34u, 0x63u, 0x08u, 0xc0u, 0x18u, 0x21u, 0x00u, + 0x01u, 0xf0u, 0x12u, 0xfdu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0xd8u, 0x12u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x00u, 0x20u, 0xffu, 0xf7u, 0x7cu, 0xffu, 0x0au, 0x4bu, 0x1cu, 0x68u, 0x23u, 0x00u, 0xb0u, 0x33u, 0x1bu, 0x68u, 0xc0u, 0x18u, 0x03u, 0x68u, 0x00u, 0x2bu, 0x0au, 0xdbu, 0x07u, 0x4bu, 0x18u, 0x68u, 0xffu, 0xf7u, 0x7bu, 0xffu, 0x01u, 0x22u, 0x63u, 0x68u, 0x9au, 0x60u, 0x9au, 0x68u, 0x00u, 0x2au, 0xfcu, 0xd1u, 0x10u, 0xbdu, 0x02u, 0x48u, 0xfcu, 0xe7u, - 0xc8u, 0x12u, 0x00u, 0x08u, 0xa0u, 0x05u, 0x00u, 0x08u, 0x02u, 0x00u, 0x50u, 0x00u, 0x0du, 0x4bu, 0x10u, 0xb5u, + 0xd8u, 0x12u, 0x00u, 0x08u, 0xb0u, 0x05u, 0x00u, 0x08u, 0x02u, 0x00u, 0x50u, 0x00u, 0x0du, 0x4bu, 0x10u, 0xb5u, 0x18u, 0x60u, 0x00u, 0x28u, 0x04u, 0xd0u, 0xfeu, 0x23u, 0x5bu, 0x42u, 0x03u, 0x80u, 0x00u, 0x23u, 0x43u, 0x80u, 0x09u, 0x4bu, 0x1bu, 0x68u, 0x1au, 0x00u, 0x4cu, 0x32u, 0x12u, 0x78u, 0x00u, 0x2au, 0x08u, 0xd0u, 0x4du, 0x33u, 0x1bu, 0x78u, 0x00u, 0x2bu, 0x04u, 0xd0u, 0x02u, 0x22u, 0x04u, 0x49u, 0x00u, 0x20u, 0x00u, 0xf0u, 0x14u, 0xfau, - 0x10u, 0xbdu, 0xc0u, 0x46u, 0xb0u, 0x05u, 0x00u, 0x08u, 0xc8u, 0x12u, 0x00u, 0x08u, 0xadu, 0x02u, 0x00u, 0x08u, - 0x10u, 0xb5u, 0x02u, 0x48u, 0xffu, 0xf7u, 0xdau, 0xffu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0x20u, 0x05u, 0x00u, 0x08u, - 0x10u, 0xb5u, 0xc3u, 0x05u, 0x04u, 0x00u, 0x00u, 0x2bu, 0x29u, 0xd1u, 0x01u, 0xf0u, 0xd5u, 0xfbu, 0xe0u, 0x22u, + 0x10u, 0xbdu, 0xc0u, 0x46u, 0xc0u, 0x05u, 0x00u, 0x08u, 0xd8u, 0x12u, 0x00u, 0x08u, 0xbdu, 0x02u, 0x00u, 0x08u, + 0x10u, 0xb5u, 0x02u, 0x48u, 0xffu, 0xf7u, 0xdau, 0xffu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0x30u, 0x05u, 0x00u, 0x08u, + 0x10u, 0xb5u, 0xc3u, 0x05u, 0x04u, 0x00u, 0x00u, 0x2bu, 0x29u, 0xd1u, 0x01u, 0xf0u, 0xd9u, 0xfbu, 0xe0u, 0x22u, 0x14u, 0x4bu, 0x52u, 0x05u, 0x1au, 0x60u, 0x14u, 0x4au, 0x12u, 0x78u, 0x00u, 0x2au, 0x04u, 0xd0u, 0x80u, 0x22u, 0x19u, 0x68u, 0x52u, 0x00u, 0x0au, 0x43u, 0x1au, 0x60u, 0x5cu, 0x60u, 0x00u, 0x24u, 0x9cu, 0x60u, 0xdcu, 0x60u, 0x0eu, 0x4bu, 0x1bu, 0x68u, 0x50u, 0x33u, 0x18u, 0x78u, 0x01u, 0x00u, 0xa0u, 0x42u, 0x0cu, 0xd0u, 0xffu, 0xf7u, - 0x77u, 0xffu, 0xfau, 0x21u, 0x89u, 0x00u, 0x01u, 0xf0u, 0x9bu, 0xfcu, 0x01u, 0x00u, 0x08u, 0x48u, 0x01u, 0xf0u, - 0x97u, 0xfcu, 0x08u, 0x4bu, 0xc1u, 0x18u, 0x20u, 0x00u, 0x03u, 0xf0u, 0xf2u, 0xf9u, 0x10u, 0xbdu, 0x06u, 0x48u, - 0xfcu, 0xe7u, 0xc0u, 0x46u, 0xa0u, 0x05u, 0x00u, 0x08u, 0x0bu, 0x00u, 0x00u, 0x16u, 0xc8u, 0x12u, 0x00u, 0x08u, + 0x77u, 0xffu, 0xfau, 0x21u, 0x89u, 0x00u, 0x01u, 0xf0u, 0x9fu, 0xfcu, 0x01u, 0x00u, 0x08u, 0x48u, 0x01u, 0xf0u, + 0x9bu, 0xfcu, 0x08u, 0x4bu, 0xc1u, 0x18u, 0x20u, 0x00u, 0x03u, 0xf0u, 0xf6u, 0xf9u, 0x10u, 0xbdu, 0x06u, 0x48u, + 0xfcu, 0xe7u, 0xc0u, 0x46u, 0xb0u, 0x05u, 0x00u, 0x08u, 0x0bu, 0x00u, 0x00u, 0x16u, 0xd8u, 0x12u, 0x00u, 0x08u, 0x60u, 0xf5u, 0x90u, 0x00u, 0x98u, 0x08u, 0x00u, 0x00u, 0x06u, 0x00u, 0x52u, 0x00u, 0x70u, 0xb5u, 0xc4u, 0x05u, - 0x06u, 0x00u, 0x0du, 0x00u, 0xe4u, 0x0du, 0x20u, 0xd1u, 0x00u, 0x29u, 0x1eu, 0xd0u, 0x01u, 0xf0u, 0x94u, 0xfbu, + 0x06u, 0x00u, 0x0du, 0x00u, 0xe4u, 0x0du, 0x20u, 0xd1u, 0x00u, 0x29u, 0x1eu, 0xd0u, 0x01u, 0xf0u, 0x98u, 0xfbu, 0x0fu, 0x4bu, 0x10u, 0x4au, 0x1au, 0x60u, 0x5cu, 0x60u, 0x9eu, 0x60u, 0xddu, 0x60u, 0x0eu, 0x4bu, 0x1bu, 0x68u, 0x4eu, 0x33u, 0x19u, 0x78u, 0x00u, 0x29u, 0x0bu, 0xd0u, 0xffu, 0xf7u, 0x42u, 0xffu, 0xfau, 0x21u, 0x89u, 0x00u, - 0x01u, 0xf0u, 0x66u, 0xfcu, 0x01u, 0x00u, 0x09u, 0x48u, 0x01u, 0xf0u, 0x62u, 0xfcu, 0x08u, 0x4bu, 0xc1u, 0x18u, - 0x80u, 0x20u, 0x40u, 0x00u, 0x03u, 0xf0u, 0xbcu, 0xf9u, 0x70u, 0xbdu, 0x06u, 0x48u, 0xfcu, 0xe7u, 0xc0u, 0x46u, - 0xa0u, 0x05u, 0x00u, 0x08u, 0x00u, 0x01u, 0x00u, 0x05u, 0xc8u, 0x12u, 0x00u, 0x08u, 0xc0u, 0xeau, 0x21u, 0x01u, + 0x01u, 0xf0u, 0x6au, 0xfcu, 0x01u, 0x00u, 0x09u, 0x48u, 0x01u, 0xf0u, 0x66u, 0xfcu, 0x08u, 0x4bu, 0xc1u, 0x18u, + 0x80u, 0x20u, 0x40u, 0x00u, 0x03u, 0xf0u, 0xc0u, 0xf9u, 0x70u, 0xbdu, 0x06u, 0x48u, 0xfcu, 0xe7u, 0xc0u, 0x46u, + 0xb0u, 0x05u, 0x00u, 0x08u, 0x00u, 0x01u, 0x00u, 0x05u, 0xd8u, 0x12u, 0x00u, 0x08u, 0xc0u, 0xeau, 0x21u, 0x01u, 0x48u, 0x26u, 0x00u, 0x00u, 0x06u, 0x00u, 0x52u, 0x00u, 0x10u, 0xb5u, 0xffu, 0xf7u, 0x3fu, 0xffu, 0x10u, 0xbdu, 0x70u, 0xb5u, 0xc3u, 0x05u, 0x05u, 0x00u, 0x0cu, 0x00u, 0x00u, 0x2bu, 0x2au, 0xd1u, 0x00u, 0x29u, 0x28u, 0xd0u, - 0x01u, 0xf0u, 0x5au, 0xfbu, 0xc0u, 0x22u, 0x80u, 0x21u, 0x13u, 0x4bu, 0xd2u, 0x04u, 0x1au, 0x60u, 0x13u, 0x4au, + 0x01u, 0xf0u, 0x5eu, 0xfbu, 0xc0u, 0x22u, 0x80u, 0x21u, 0x13u, 0x4bu, 0xd2u, 0x04u, 0x1au, 0x60u, 0x13u, 0x4au, 0x49u, 0x00u, 0x12u, 0x78u, 0x00u, 0x2au, 0x02u, 0xd0u, 0x1au, 0x68u, 0x0au, 0x43u, 0x1au, 0x60u, 0x59u, 0x60u, 0x9du, 0x60u, 0xdcu, 0x60u, 0x0eu, 0x4bu, 0x1bu, 0x68u, 0x4fu, 0x33u, 0x18u, 0x78u, 0x01u, 0x1eu, 0x0du, 0xd0u, - 0xffu, 0xf7u, 0xfeu, 0xfeu, 0xfau, 0x21u, 0x89u, 0x00u, 0x01u, 0xf0u, 0x22u, 0xfcu, 0x01u, 0x00u, 0x09u, 0x48u, - 0x01u, 0xf0u, 0x1eu, 0xfcu, 0xe1u, 0x23u, 0x9bu, 0x00u, 0xc1u, 0x18u, 0x00u, 0x20u, 0x03u, 0xf0u, 0x78u, 0xf9u, - 0x70u, 0xbdu, 0x05u, 0x48u, 0xfcu, 0xe7u, 0xc0u, 0x46u, 0xa0u, 0x05u, 0x00u, 0x08u, 0x0bu, 0x00u, 0x00u, 0x16u, - 0xc8u, 0x12u, 0x00u, 0x08u, 0x80u, 0x8du, 0x5bu, 0x00u, 0x06u, 0x00u, 0x52u, 0x00u, 0x0eu, 0x4bu, 0x10u, 0xb5u, + 0xffu, 0xf7u, 0xfeu, 0xfeu, 0xfau, 0x21u, 0x89u, 0x00u, 0x01u, 0xf0u, 0x26u, 0xfcu, 0x01u, 0x00u, 0x09u, 0x48u, + 0x01u, 0xf0u, 0x22u, 0xfcu, 0xe1u, 0x23u, 0x9bu, 0x00u, 0xc1u, 0x18u, 0x00u, 0x20u, 0x03u, 0xf0u, 0x7cu, 0xf9u, + 0x70u, 0xbdu, 0x05u, 0x48u, 0xfcu, 0xe7u, 0xc0u, 0x46u, 0xb0u, 0x05u, 0x00u, 0x08u, 0x0bu, 0x00u, 0x00u, 0x16u, + 0xd8u, 0x12u, 0x00u, 0x08u, 0x80u, 0x8du, 0x5bu, 0x00u, 0x06u, 0x00u, 0x52u, 0x00u, 0x0eu, 0x4bu, 0x10u, 0xb5u, 0x1bu, 0x68u, 0x9cu, 0x69u, 0x5bu, 0x69u, 0x00u, 0x1bu, 0xc0u, 0x09u, 0x00u, 0x01u, 0xc0u, 0x18u, 0x1fu, 0x23u, 0x1au, 0x40u, 0x03u, 0x29u, 0x07u, 0xd8u, 0xc9u, 0x00u, 0x8bu, 0x40u, 0x8au, 0x40u, 0x04u, 0x68u, 0x9cu, 0x43u, 0x22u, 0x43u, 0x02u, 0x60u, 0x10u, 0xbdu, 0x04u, 0x39u, 0xc9u, 0x00u, 0x8bu, 0x40u, 0x8au, 0x40u, 0x44u, 0x68u, - 0x9cu, 0x43u, 0x22u, 0x43u, 0x42u, 0x60u, 0xf5u, 0xe7u, 0xc8u, 0x12u, 0x00u, 0x08u, 0x30u, 0xb5u, 0x00u, 0x28u, + 0x9cu, 0x43u, 0x22u, 0x43u, 0x42u, 0x60u, 0xf5u, 0xe7u, 0xd8u, 0x12u, 0x00u, 0x08u, 0x30u, 0xb5u, 0x00u, 0x28u, 0x30u, 0xd0u, 0x00u, 0x29u, 0x2eu, 0xd0u, 0x18u, 0x4bu, 0xcdu, 0x68u, 0x1au, 0x68u, 0x93u, 0x69u, 0x54u, 0x69u, 0xc3u, 0x1au, 0xdbu, 0x09u, 0x1bu, 0x01u, 0x1bu, 0x19u, 0x0cu, 0x68u, 0x04u, 0x60u, 0x14u, 0x00u, 0x79u, 0x34u, 0x24u, 0x78u, 0x24u, 0x18u, 0x25u, 0x60u, 0x14u, 0x00u, 0x7au, 0x34u, 0x24u, 0x78u, 0x0du, 0x69u, 0x24u, 0x18u, 0x25u, 0x60u, 0x14u, 0x00u, 0x7bu, 0x34u, 0x24u, 0x78u, 0x4du, 0x69u, 0x24u, 0x18u, 0x25u, 0x60u, 0x14u, 0x00u, 0x78u, 0x34u, 0x24u, 0x78u, 0x8du, 0x68u, 0x24u, 0x18u, 0x25u, 0x60u, 0x4cu, 0x68u, 0x7cu, 0x32u, 0x84u, 0x61u, 0x12u, 0x78u, 0x10u, 0x18u, 0x8au, 0x69u, 0x02u, 0x60u, 0x00u, 0x20u, 0xcau, 0x69u, 0x1au, 0x60u, 0x0au, 0x6au, - 0x5au, 0x60u, 0x30u, 0xbdu, 0x01u, 0x48u, 0xfcu, 0xe7u, 0xc8u, 0x12u, 0x00u, 0x08u, 0x01u, 0x00u, 0x5au, 0x00u, + 0x5au, 0x60u, 0x30u, 0xbdu, 0x01u, 0x48u, 0xfcu, 0xe7u, 0xd8u, 0x12u, 0x00u, 0x08u, 0x01u, 0x00u, 0x5au, 0x00u, 0xf7u, 0xb5u, 0x01u, 0x26u, 0x37u, 0x00u, 0x8fu, 0x40u, 0x33u, 0x40u, 0x8bu, 0x40u, 0x05u, 0x68u, 0x14u, 0x00u, 0xbdu, 0x43u, 0x0fu, 0x27u, 0x2bu, 0x43u, 0x03u, 0x60u, 0x0au, 0x4bu, 0x08u, 0xaau, 0x12u, 0x78u, 0x1bu, 0x68u, 0x01u, 0x92u, 0x79u, 0x33u, 0x1du, 0x78u, 0x8eu, 0x00u, 0x45u, 0x19u, 0x2bu, 0x68u, 0x3cu, 0x40u, 0x1au, 0x00u, 0x3bu, 0x00u, 0xb3u, 0x40u, 0xb4u, 0x40u, 0x9au, 0x43u, 0x14u, 0x43u, 0x2cu, 0x60u, 0x01u, 0x9au, 0xffu, 0xf7u, - 0x85u, 0xffu, 0xf7u, 0xbdu, 0xc8u, 0x12u, 0x00u, 0x08u, 0x06u, 0x4bu, 0x1bu, 0x68u, 0xb0u, 0x33u, 0x1bu, 0x68u, + 0x85u, 0xffu, 0xf7u, 0xbdu, 0xd8u, 0x12u, 0x00u, 0x08u, 0x06u, 0x4bu, 0x1bu, 0x68u, 0xb0u, 0x33u, 0x1bu, 0x68u, 0xc3u, 0x18u, 0x1bu, 0x68u, 0x00u, 0x2bu, 0x03u, 0xdau, 0x89u, 0xb2u, 0x41u, 0x60u, 0x00u, 0x20u, 0x70u, 0x47u, - 0x01u, 0x48u, 0xfcu, 0xe7u, 0xc8u, 0x12u, 0x00u, 0x08u, 0x01u, 0x00u, 0x8au, 0x00u, 0x03u, 0x68u, 0x00u, 0x2bu, + 0x01u, 0x48u, 0xfcu, 0xe7u, 0xd8u, 0x12u, 0x00u, 0x08u, 0x01u, 0x00u, 0x8au, 0x00u, 0x03u, 0x68u, 0x00u, 0x2bu, 0x04u, 0xdau, 0x89u, 0xb2u, 0xc2u, 0x60u, 0x81u, 0x60u, 0x00u, 0x20u, 0x70u, 0x47u, 0x00u, 0x48u, 0xfcu, 0xe7u, 0x01u, 0x00u, 0x8au, 0x00u, 0x06u, 0x4bu, 0x1bu, 0x68u, 0xb0u, 0x33u, 0x1bu, 0x68u, 0xc3u, 0x18u, 0x1bu, 0x68u, 0x00u, 0x2bu, 0x03u, 0xdau, 0xc3u, 0x68u, 0x00u, 0x20u, 0x0bu, 0x60u, 0x70u, 0x47u, 0x01u, 0x48u, 0xfcu, 0xe7u, - 0xc8u, 0x12u, 0x00u, 0x08u, 0x01u, 0x00u, 0x8au, 0x00u, 0x02u, 0x4bu, 0x1au, 0x68u, 0x00u, 0x2au, 0x00u, 0xd1u, - 0x18u, 0x60u, 0x70u, 0x47u, 0xb4u, 0x05u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x2cu, 0x24u, 0x60u, 0x43u, 0x15u, 0x4cu, + 0xd8u, 0x12u, 0x00u, 0x08u, 0x01u, 0x00u, 0x8au, 0x00u, 0x02u, 0x4bu, 0x1au, 0x68u, 0x00u, 0x2au, 0x00u, 0xd1u, + 0x18u, 0x60u, 0x70u, 0x47u, 0xc4u, 0x05u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x2cu, 0x24u, 0x60u, 0x43u, 0x15u, 0x4cu, 0x1fu, 0x00u, 0x24u, 0x68u, 0x1du, 0x0au, 0x20u, 0x18u, 0xffu, 0x24u, 0x25u, 0x40u, 0x27u, 0x40u, 0x12u, 0x4cu, 0x1bu, 0x0cu, 0x26u, 0x68u, 0x07u, 0x60u, 0x34u, 0x6au, 0x45u, 0x60u, 0x83u, 0x60u, 0xacu, 0x36u, 0x36u, 0x88u, 0x77u, 0x43u, 0x3fu, 0x19u, 0x07u, 0x61u, 0x2fu, 0x00u, 0x80u, 0x37u, 0x6du, 0x01u, 0x7fu, 0x01u, 0xe7u, 0x19u, 0x64u, 0x19u, 0x0au, 0x4du, 0x47u, 0x61u, 0x1fu, 0x04u, 0x3bu, 0x43u, 0x64u, 0x19u, 0x23u, 0x60u, 0x00u, 0x23u, 0x83u, 0x61u, 0x05u, 0x9bu, 0xc2u, 0x61u, 0x01u, 0x62u, 0x00u, 0x2bu, 0x01u, 0xd0u, 0x1bu, 0x88u, 0x83u, 0x81u, - 0xf0u, 0xbdu, 0xc0u, 0x46u, 0xb4u, 0x05u, 0x00u, 0x08u, 0xc8u, 0x12u, 0x00u, 0x08u, 0x08u, 0x10u, 0x00u, 0x00u, + 0xf0u, 0xbdu, 0xc0u, 0x46u, 0xc4u, 0x05u, 0x00u, 0x08u, 0xd8u, 0x12u, 0x00u, 0x08u, 0x08u, 0x10u, 0x00u, 0x00u, 0xf0u, 0xb5u, 0x83u, 0x68u, 0x85u, 0xb0u, 0x02u, 0xadu, 0x2bu, 0x80u, 0x15u, 0x4bu, 0x02u, 0x68u, 0x1bu, 0x68u, 0x06u, 0x6au, 0x9bu, 0x8eu, 0x47u, 0x6au, 0x9bu, 0x18u, 0xabu, 0x70u, 0x43u, 0x68u, 0x00u, 0x95u, 0x82u, 0x6au, 0xc1u, 0x6au, 0x04u, 0x00u, 0x03u, 0x93u, 0x03u, 0x69u, 0xc0u, 0x68u, 0xffu, 0xf7u, 0xb5u, 0xffu, 0x00u, 0x21u, 0x3bu, 0x00u, 0x0au, 0x00u, 0x00u, 0x91u, 0x30u, 0x00u, 0xffu, 0xf7u, 0xaeu, 0xffu, 0x21u, 0x6bu, 0x28u, 0x00u, - 0x00u, 0xf0u, 0x6cu, 0xfcu, 0x00u, 0x22u, 0xabu, 0x5eu, 0x00u, 0x2bu, 0x06u, 0xdbu, 0x1fu, 0x22u, 0x13u, 0x40u, + 0x00u, 0xf0u, 0x70u, 0xfcu, 0x00u, 0x22u, 0xabu, 0x5eu, 0x00u, 0x2bu, 0x06u, 0xdbu, 0x1fu, 0x22u, 0x13u, 0x40u, 0x1eu, 0x3au, 0x9au, 0x40u, 0x13u, 0x00u, 0x03u, 0x4au, 0x13u, 0x60u, 0x05u, 0xb0u, 0xf0u, 0xbdu, 0xc0u, 0x46u, - 0xc8u, 0x12u, 0x00u, 0x08u, 0x00u, 0xe1u, 0x00u, 0xe0u, 0xf7u, 0xb5u, 0x2cu, 0x25u, 0x13u, 0x4cu, 0x68u, 0x43u, + 0xd8u, 0x12u, 0x00u, 0x08u, 0x00u, 0xe1u, 0x00u, 0xe0u, 0xf7u, 0xb5u, 0x2cu, 0x25u, 0x13u, 0x4cu, 0x68u, 0x43u, 0x26u, 0x68u, 0x69u, 0x43u, 0x34u, 0x18u, 0x25u, 0x69u, 0x01u, 0x93u, 0x71u, 0x18u, 0x00u, 0x2du, 0x19u, 0xd0u, 0x88u, 0x69u, 0x00u, 0x28u, 0x18u, 0xd1u, 0x2eu, 0x68u, 0x00u, 0x2eu, 0x15u, 0xdau, 0x67u, 0x68u, 0x01u, 0x24u, 0x26u, 0x00u, 0x4bu, 0x68u, 0x9eu, 0x40u, 0xb4u, 0x46u, 0x13u, 0x68u, 0x9eu, 0xb2u, 0x63u, 0x46u, 0x1bu, 0x04u, 0x1eu, 0x43u, 0x16u, 0x60u, 0xeau, 0x60u, 0x8cu, 0x61u, 0xbcu, 0x40u, 0x01u, 0x9bu, 0xa4u, 0xb2u, 0x4bu, 0x62u, - 0xacu, 0x60u, 0xfeu, 0xbdu, 0x02u, 0x48u, 0xfcu, 0xe7u, 0x02u, 0x48u, 0xfau, 0xe7u, 0xb4u, 0x05u, 0x00u, 0x08u, + 0xacu, 0x60u, 0xfeu, 0xbdu, 0x02u, 0x48u, 0xfcu, 0xe7u, 0x02u, 0x48u, 0xfau, 0xe7u, 0xc4u, 0x05u, 0x00u, 0x08u, 0x04u, 0x02u, 0x8au, 0x00u, 0x07u, 0x02u, 0x8au, 0x00u, 0x2cu, 0x23u, 0x43u, 0x43u, 0x06u, 0x48u, 0x00u, 0x68u, 0xc0u, 0x18u, 0xc3u, 0x69u, 0x93u, 0x42u, 0x04u, 0xd9u, 0x03u, 0x6au, 0x00u, 0x20u, 0x92u, 0x00u, 0xd1u, 0x50u, - 0x70u, 0x47u, 0x02u, 0x48u, 0xfcu, 0xe7u, 0xc0u, 0x46u, 0xb4u, 0x05u, 0x00u, 0x08u, 0x0au, 0x02u, 0x8au, 0x00u, + 0x70u, 0x47u, 0x02u, 0x48u, 0xfcu, 0xe7u, 0xc0u, 0x46u, 0xc4u, 0x05u, 0x00u, 0x08u, 0x0au, 0x02u, 0x8au, 0x00u, 0x2cu, 0x22u, 0x03u, 0x4bu, 0x50u, 0x43u, 0x1bu, 0x68u, 0x18u, 0x18u, 0x81u, 0x62u, 0x70u, 0x47u, 0xc0u, 0x46u, - 0xb4u, 0x05u, 0x00u, 0x08u, 0x73u, 0xb5u, 0x00u, 0x26u, 0x42u, 0x69u, 0x04u, 0x00u, 0xd5u, 0x68u, 0x01u, 0x96u, + 0xc4u, 0x05u, 0x00u, 0x08u, 0x73u, 0xb5u, 0x00u, 0x26u, 0x42u, 0x69u, 0x04u, 0x00u, 0xd5u, 0x68u, 0x01u, 0x96u, 0x2bu, 0x0cu, 0xb3u, 0x42u, 0x21u, 0xd0u, 0x1bu, 0x04u, 0x13u, 0x60u, 0x13u, 0x68u, 0x19u, 0x4bu, 0x00u, 0x69u, 0x1bu, 0x68u, 0xb0u, 0x33u, 0x1bu, 0x68u, 0xc3u, 0x18u, 0x1bu, 0x68u, 0xb3u, 0x42u, 0x15u, 0xdau, 0x01u, 0xa9u, 0xffu, 0xf7u, 0x18u, 0xffu, 0xb0u, 0x42u, 0x0cu, 0xd1u, 0x01u, 0x98u, 0xe2u, 0x69u, 0x03u, 0x68u, 0x1eu, 0x0cu, @@ -399,49 +399,49 @@ const uint8_t cy_m0p_image[] = { 0x98u, 0x47u, 0x31u, 0x00u, 0x20u, 0x69u, 0xffu, 0xf7u, 0xe7u, 0xfeu, 0xadu, 0xb2u, 0x00u, 0x2du, 0x09u, 0xd0u, 0x63u, 0x69u, 0x1du, 0x60u, 0x00u, 0x25u, 0x1bu, 0x68u, 0x63u, 0x6au, 0xabu, 0x42u, 0x05u, 0xd0u, 0x98u, 0x47u, 0x65u, 0x62u, 0xa5u, 0x61u, 0x63u, 0x69u, 0x1bu, 0x68u, 0x73u, 0xbdu, 0xa3u, 0x6au, 0x00u, 0x2bu, 0xf8u, 0xd0u, - 0x98u, 0x47u, 0xf6u, 0xe7u, 0xc8u, 0x12u, 0x00u, 0x08u, 0x2cu, 0x23u, 0x10u, 0xb5u, 0x43u, 0x43u, 0x03u, 0x4au, - 0x10u, 0x68u, 0xc0u, 0x18u, 0xffu, 0xf7u, 0xb6u, 0xffu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0xb4u, 0x05u, 0x00u, 0x08u, + 0x98u, 0x47u, 0xf6u, 0xe7u, 0xd8u, 0x12u, 0x00u, 0x08u, 0x2cu, 0x23u, 0x10u, 0xb5u, 0x43u, 0x43u, 0x03u, 0x4au, + 0x10u, 0x68u, 0xc0u, 0x18u, 0xffu, 0xf7u, 0xb6u, 0xffu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0xc4u, 0x05u, 0x00u, 0x08u, 0x2cu, 0x22u, 0x0au, 0x4bu, 0x50u, 0x43u, 0x1bu, 0x68u, 0x18u, 0x18u, 0x0cu, 0x22u, 0x83u, 0x5eu, 0x00u, 0x2bu, 0x0au, 0xdbu, 0x1fu, 0x22u, 0x13u, 0x40u, 0x1eu, 0x3au, 0x9au, 0x40u, 0x13u, 0x00u, 0x04u, 0x4au, 0xd3u, 0x67u, - 0xbfu, 0xf3u, 0x4fu, 0x8fu, 0xbfu, 0xf3u, 0x6fu, 0x8fu, 0x00u, 0x20u, 0x70u, 0x47u, 0xb4u, 0x05u, 0x00u, 0x08u, + 0xbfu, 0xf3u, 0x4fu, 0x8fu, 0xbfu, 0xf3u, 0x6fu, 0x8fu, 0x00u, 0x20u, 0x70u, 0x47u, 0xc4u, 0x05u, 0x00u, 0x08u, 0x04u, 0xe1u, 0x00u, 0xe0u, 0x2cu, 0x22u, 0x08u, 0x4bu, 0x50u, 0x43u, 0x1bu, 0x68u, 0x18u, 0x18u, 0x0cu, 0x22u, 0x83u, 0x5eu, 0x00u, 0x2bu, 0x06u, 0xdbu, 0x1fu, 0x22u, 0x13u, 0x40u, 0x1eu, 0x3au, 0x9au, 0x40u, 0x13u, 0x00u, - 0x02u, 0x4au, 0x13u, 0x60u, 0x00u, 0x20u, 0x70u, 0x47u, 0xb4u, 0x05u, 0x00u, 0x08u, 0x00u, 0xe1u, 0x00u, 0xe0u, + 0x02u, 0x4au, 0x13u, 0x60u, 0x00u, 0x20u, 0x70u, 0x47u, 0xc4u, 0x05u, 0x00u, 0x08u, 0x00u, 0xe1u, 0x00u, 0xe0u, 0xf8u, 0xb5u, 0x19u, 0x4bu, 0x0fu, 0x00u, 0x1bu, 0x68u, 0x1au, 0x00u, 0x2eu, 0x32u, 0x12u, 0x78u, 0x82u, 0x42u, 0x27u, 0xd9u, 0x00u, 0x29u, 0x25u, 0xd0u, 0x1fu, 0x25u, 0x0au, 0x68u, 0x15u, 0x40u, 0x21u, 0xd1u, 0x19u, 0x00u, 0xacu, 0x31u, 0x0cu, 0x88u, 0x11u, 0x4eu, 0x60u, 0x43u, 0x1cu, 0x6au, 0xd2u, 0x08u, 0x04u, 0x19u, 0x29u, 0x00u, - 0x78u, 0x68u, 0x34u, 0x60u, 0x02u, 0xf0u, 0x50u, 0xffu, 0x29u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x74u, 0xfeu, + 0x78u, 0x68u, 0x34u, 0x60u, 0x02u, 0xf0u, 0x54u, 0xffu, 0x29u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x74u, 0xfeu, 0x3au, 0x00u, 0x29u, 0x00u, 0x30u, 0x68u, 0xffu, 0xf7u, 0x81u, 0xfeu, 0x04u, 0x1eu, 0x07u, 0xd1u, 0x01u, 0x00u, 0x30u, 0x68u, 0xffu, 0xf7u, 0x69u, 0xfeu, 0x03u, 0x00u, 0x20u, 0x00u, 0x00u, 0x2bu, 0x00u, 0xd0u, 0x04u, 0x48u, - 0xf8u, 0xbdu, 0x04u, 0x48u, 0xfcu, 0xe7u, 0xc0u, 0x46u, 0xc8u, 0x12u, 0x00u, 0x08u, 0xb8u, 0x05u, 0x00u, 0x08u, + 0xf8u, 0xbdu, 0x04u, 0x48u, 0xfcu, 0xe7u, 0xc0u, 0x46u, 0xd8u, 0x12u, 0x00u, 0x08u, 0xc8u, 0x05u, 0x00u, 0x08u, 0x01u, 0x01u, 0x8au, 0x00u, 0x03u, 0x01u, 0x8au, 0x00u, 0x10u, 0xb5u, 0x00u, 0x2au, 0x0du, 0xd1u, 0x00u, 0x29u, 0x14u, 0xd1u, 0x0bu, 0x4bu, 0x1au, 0x68u, 0x13u, 0x00u, 0xacu, 0x33u, 0x1bu, 0x88u, 0x58u, 0x43u, 0x13u, 0x6au, 0xc0u, 0x18u, 0x08u, 0x4bu, 0x18u, 0x60u, 0x08u, 0x00u, 0x10u, 0xbdu, 0x00u, 0x29u, 0x06u, 0xd0u, 0x06u, 0x4bu, 0x19u, 0x60u, 0x19u, 0x00u, 0x5au, 0x60u, 0xffu, 0xf7u, 0xabu, 0xffu, 0xf5u, 0xe7u, 0x03u, 0x48u, 0xf3u, 0xe7u, - 0xc8u, 0x12u, 0x00u, 0x08u, 0xb8u, 0x05u, 0x00u, 0x08u, 0x24u, 0x05u, 0x00u, 0x08u, 0x03u, 0x01u, 0x8au, 0x00u, + 0xd8u, 0x12u, 0x00u, 0x08u, 0xc8u, 0x05u, 0x00u, 0x08u, 0x34u, 0x05u, 0x00u, 0x08u, 0x03u, 0x01u, 0x8au, 0x00u, 0xf7u, 0xb5u, 0x18u, 0x4fu, 0x04u, 0x00u, 0x3bu, 0x68u, 0x01u, 0x91u, 0xdeu, 0x68u, 0x33u, 0x68u, 0x83u, 0x42u, 0x26u, 0xd9u, 0x00u, 0x25u, 0xa9u, 0x42u, 0x02u, 0xd1u, 0xfeu, 0xf7u, 0x3fu, 0xfcu, 0x05u, 0x00u, 0x38u, 0x68u, 0x03u, 0x68u, 0x00u, 0x2bu, 0x1au, 0xdau, 0x1fu, 0x22u, 0x01u, 0x23u, 0x22u, 0x40u, 0x93u, 0x40u, 0x64u, 0x09u, 0x72u, 0x68u, 0xa4u, 0x00u, 0x12u, 0x19u, 0x1cu, 0x00u, 0x11u, 0x68u, 0x0cu, 0x40u, 0x0cu, 0xd1u, 0x0bu, 0x43u, 0x13u, 0x60u, 0x00u, 0x21u, 0xffu, 0xf7u, 0x10u, 0xfeu, 0x01u, 0x9bu, 0x00u, 0x2bu, 0x02u, 0xd1u, 0x28u, 0x00u, 0xfeu, 0xf7u, 0x27u, 0xfcu, 0x20u, 0x00u, 0xfeu, 0xbdu, 0x03u, 0x4cu, 0xf2u, 0xe7u, 0x03u, 0x4cu, 0xf3u, 0xe7u, - 0x03u, 0x4cu, 0xf7u, 0xe7u, 0xb8u, 0x05u, 0x00u, 0x08u, 0x02u, 0x01u, 0x88u, 0x00u, 0x03u, 0x01u, 0x88u, 0x00u, + 0x03u, 0x4cu, 0xf7u, 0xe7u, 0xc8u, 0x05u, 0x00u, 0x08u, 0x02u, 0x01u, 0x88u, 0x00u, 0x03u, 0x01u, 0x88u, 0x00u, 0x04u, 0x01u, 0x8au, 0x00u, 0xf7u, 0xb5u, 0x18u, 0x4fu, 0x04u, 0x00u, 0x3bu, 0x68u, 0x01u, 0x91u, 0xdeu, 0x68u, 0x33u, 0x68u, 0x83u, 0x42u, 0x26u, 0xd9u, 0x00u, 0x25u, 0xa9u, 0x42u, 0x02u, 0xd1u, 0xfeu, 0xf7u, 0x05u, 0xfcu, 0x05u, 0x00u, 0x38u, 0x68u, 0x03u, 0x68u, 0x00u, 0x2bu, 0x1au, 0xdau, 0x1fu, 0x22u, 0x01u, 0x23u, 0x22u, 0x40u, 0x93u, 0x40u, 0x64u, 0x09u, 0x72u, 0x68u, 0xa4u, 0x00u, 0x14u, 0x19u, 0x22u, 0x68u, 0x13u, 0x42u, 0x0du, 0xd0u, 0x9au, 0x43u, 0x22u, 0x60u, 0x00u, 0x24u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xd6u, 0xfdu, 0x01u, 0x9bu, 0x00u, 0x2bu, 0x02u, 0xd1u, 0x28u, 0x00u, 0xfeu, 0xf7u, 0xedu, 0xfbu, 0x20u, 0x00u, 0xfeu, 0xbdu, 0x03u, 0x4cu, 0xf2u, 0xe7u, - 0x03u, 0x4cu, 0xf3u, 0xe7u, 0x03u, 0x4cu, 0xf7u, 0xe7u, 0xb8u, 0x05u, 0x00u, 0x08u, 0x02u, 0x01u, 0x88u, 0x00u, + 0x03u, 0x4cu, 0xf3u, 0xe7u, 0x03u, 0x4cu, 0xf7u, 0xe7u, 0xc8u, 0x05u, 0x00u, 0x08u, 0x02u, 0x01u, 0x88u, 0x00u, 0x03u, 0x01u, 0x88u, 0x00u, 0x04u, 0x01u, 0x8au, 0x00u, 0x0au, 0x4bu, 0x1bu, 0x68u, 0xdbu, 0x68u, 0x1au, 0x68u, 0x82u, 0x42u, 0x0du, 0xd9u, 0x59u, 0x68u, 0x1fu, 0x23u, 0x42u, 0x09u, 0x18u, 0x40u, 0x1eu, 0x3bu, 0x83u, 0x40u, 0x92u, 0x00u, 0x50u, 0x58u, 0x18u, 0x40u, 0x43u, 0x1eu, 0x98u, 0x41u, 0x03u, 0x4bu, 0xc0u, 0x18u, 0x70u, 0x47u, - 0x02u, 0x48u, 0xfcu, 0xe7u, 0xb8u, 0x05u, 0x00u, 0x08u, 0x00u, 0x01u, 0x88u, 0x00u, 0x04u, 0x01u, 0x8au, 0x00u, + 0x02u, 0x48u, 0xfcu, 0xe7u, 0xc8u, 0x05u, 0x00u, 0x08u, 0x00u, 0x01u, 0x88u, 0x00u, 0x04u, 0x01u, 0x8au, 0x00u, 0x04u, 0x4bu, 0x10u, 0x30u, 0x1bu, 0x68u, 0x80u, 0x02u, 0x1bu, 0x69u, 0xc0u, 0x58u, 0x0fu, 0x23u, 0x18u, 0x40u, - 0x70u, 0x47u, 0xc0u, 0x46u, 0xc8u, 0x12u, 0x00u, 0x08u, 0xa6u, 0x22u, 0x05u, 0x49u, 0xd2u, 0x00u, 0x8bu, 0x58u, + 0x70u, 0x47u, 0xc0u, 0x46u, 0xd8u, 0x12u, 0x00u, 0x08u, 0xa6u, 0x22u, 0x05u, 0x49u, 0xd2u, 0x00u, 0x8bu, 0x58u, 0x02u, 0x20u, 0xdbu, 0x43u, 0x9bu, 0x07u, 0x02u, 0xd0u, 0x01u, 0x23u, 0x88u, 0x58u, 0x18u, 0x40u, 0x70u, 0x47u, 0x00u, 0x00u, 0x26u, 0x40u, 0x10u, 0xb5u, 0xffu, 0xf7u, 0xefu, 0xffu, 0x00u, 0x23u, 0x02u, 0x28u, 0x01u, 0xd1u, - 0x01u, 0x4bu, 0x1bu, 0x68u, 0x18u, 0x00u, 0x10u, 0xbdu, 0xc4u, 0x05u, 0x00u, 0x08u, 0x09u, 0x4au, 0x83u, 0x00u, + 0x01u, 0x4bu, 0x1bu, 0x68u, 0x18u, 0x00u, 0x10u, 0xbdu, 0xd4u, 0x05u, 0x00u, 0x08u, 0x09u, 0x4au, 0x83u, 0x00u, 0x9bu, 0x18u, 0xd0u, 0x22u, 0x92u, 0x00u, 0x98u, 0x58u, 0x07u, 0x22u, 0x10u, 0x40u, 0x04u, 0x28u, 0x07u, 0xd1u, 0xc0u, 0x22u, 0x92u, 0x00u, 0x98u, 0x58u, 0x1fu, 0x23u, 0x03u, 0x40u, 0x80u, 0x20u, 0x40u, 0x00u, 0x18u, 0x43u, 0x70u, 0x47u, 0xc0u, 0x46u, 0x00u, 0x00u, 0x26u, 0x40u, 0x10u, 0xb5u, 0xffu, 0xf7u, 0xe7u, 0xffu, 0x03u, 0x28u, @@ -451,7 +451,7 @@ const uint8_t cy_m0p_image[] = { 0x00u, 0xe0u, 0x0cu, 0x48u, 0x10u, 0xbdu, 0x0cu, 0x4bu, 0x18u, 0x68u, 0xfbu, 0xe7u, 0x0bu, 0x4bu, 0xfbu, 0xe7u, 0x0bu, 0x4bu, 0x18u, 0x69u, 0x04u, 0x23u, 0x18u, 0x40u, 0xf4u, 0xd0u, 0x80u, 0x20u, 0x00u, 0x02u, 0xf1u, 0xe7u, 0x02u, 0x4au, 0x08u, 0x4bu, 0xe9u, 0xe7u, 0x00u, 0x20u, 0xecu, 0xe7u, 0xc0u, 0x46u, 0x00u, 0x00u, 0x26u, 0x40u, - 0x0cu, 0x05u, 0x00u, 0x00u, 0x00u, 0x12u, 0x7au, 0x00u, 0xc8u, 0x05u, 0x00u, 0x08u, 0x34u, 0x06u, 0x00u, 0x08u, + 0x0cu, 0x05u, 0x00u, 0x00u, 0x00u, 0x12u, 0x7au, 0x00u, 0xd8u, 0x05u, 0x00u, 0x08u, 0x44u, 0x06u, 0x00u, 0x08u, 0x00u, 0x00u, 0x27u, 0x40u, 0x3cu, 0x05u, 0x00u, 0x00u, 0xb0u, 0x23u, 0x15u, 0x4au, 0xdbu, 0x00u, 0xd3u, 0x58u, 0x10u, 0xb5u, 0x99u, 0x03u, 0xdbu, 0x01u, 0xdbu, 0x0fu, 0x89u, 0x0bu, 0xc3u, 0x71u, 0x11u, 0x4bu, 0x01u, 0x60u, 0xd3u, 0x58u, 0x0fu, 0x24u, 0xd9u, 0x04u, 0xdbu, 0x01u, 0xdbu, 0x0du, 0x03u, 0x81u, 0xb1u, 0x23u, 0xdbu, 0x00u, @@ -463,6380 +463,6381 @@ const uint8_t cy_m0p_image[] = { 0x80u, 0x30u, 0xffu, 0x30u, 0x0bu, 0x4bu, 0x80u, 0x00u, 0xc3u, 0x58u, 0x1au, 0x40u, 0x0au, 0x70u, 0x1au, 0x0cu, 0x22u, 0x40u, 0x18u, 0x0au, 0x8au, 0x70u, 0x1au, 0x01u, 0x20u, 0x40u, 0xe2u, 0x40u, 0x48u, 0x70u, 0x00u, 0x20u, 0x9bu, 0x00u, 0x9bu, 0x0fu, 0xcau, 0x70u, 0x0bu, 0x71u, 0x10u, 0xbdu, 0x03u, 0x48u, 0xfcu, 0xe7u, 0xc0u, 0x46u, - 0xc8u, 0x12u, 0x00u, 0x08u, 0x00u, 0x00u, 0x26u, 0x40u, 0x01u, 0x00u, 0x4au, 0x00u, 0xf0u, 0xb5u, 0x87u, 0xb0u, - 0x04u, 0x00u, 0xffu, 0xf7u, 0x61u, 0xffu, 0x06u, 0x00u, 0x00u, 0x2cu, 0x34u, 0xd1u, 0x01u, 0xadu, 0x14u, 0x22u, - 0x21u, 0x00u, 0x28u, 0x00u, 0x02u, 0xf0u, 0x98u, 0xfdu, 0x28u, 0x00u, 0xffu, 0xf7u, 0x95u, 0xffu, 0xb0u, 0x23u, - 0x25u, 0x4au, 0xdbu, 0x00u, 0xd3u, 0x58u, 0x00u, 0x2bu, 0x03u, 0xdau, 0xacu, 0x7bu, 0x02u, 0x3cu, 0x63u, 0x1eu, + 0xd8u, 0x12u, 0x00u, 0x08u, 0x00u, 0x00u, 0x26u, 0x40u, 0x01u, 0x00u, 0x4au, 0x00u, 0xf0u, 0xb5u, 0x87u, 0xb0u, + 0x04u, 0x00u, 0xffu, 0xf7u, 0x61u, 0xffu, 0x06u, 0x00u, 0x00u, 0x2cu, 0x38u, 0xd1u, 0x01u, 0xadu, 0x14u, 0x22u, + 0x21u, 0x00u, 0x28u, 0x00u, 0x02u, 0xf0u, 0x9cu, 0xfdu, 0x28u, 0x00u, 0xffu, 0xf7u, 0x95u, 0xffu, 0xb0u, 0x23u, + 0x27u, 0x4au, 0xdbu, 0x00u, 0xd3u, 0x58u, 0x00u, 0x2bu, 0x03u, 0xdau, 0xacu, 0x7bu, 0x02u, 0x3cu, 0x63u, 0x1eu, 0x9cu, 0x41u, 0xeau, 0x79u, 0x01u, 0x9fu, 0x53u, 0x1eu, 0x9au, 0x41u, 0xa8u, 0x88u, 0x01u, 0x32u, 0x00u, 0x2cu, - 0x16u, 0xd0u, 0x00u, 0x23u, 0x19u, 0x00u, 0x01u, 0xf0u, 0xc9u, 0xf9u, 0x00u, 0x23u, 0x0cu, 0x00u, 0x05u, 0x00u, - 0x3au, 0x00u, 0x30u, 0x00u, 0x19u, 0x00u, 0x01u, 0xf0u, 0xc1u, 0xf9u, 0xe6u, 0x07u, 0x6au, 0x08u, 0x32u, 0x43u, - 0x63u, 0x08u, 0x80u, 0x18u, 0x59u, 0x41u, 0x2au, 0x00u, 0x23u, 0x00u, 0x01u, 0xf0u, 0x97u, 0xf9u, 0x06u, 0x00u, - 0x30u, 0x00u, 0x07u, 0xb0u, 0xf0u, 0xbdu, 0x11u, 0x4bu, 0x1bu, 0x68u, 0x3bu, 0x33u, 0x1bu, 0x78u, 0xa3u, 0x42u, - 0xf6u, 0xd3u, 0x01u, 0xadu, 0x05u, 0x22u, 0x00u, 0x21u, 0x28u, 0x00u, 0x02u, 0xf0u, 0x5du, 0xfdu, 0x20u, 0x00u, - 0x29u, 0x00u, 0x80u, 0x34u, 0xffu, 0xf7u, 0x8au, 0xffu, 0xffu, 0x34u, 0x07u, 0x4bu, 0xa4u, 0x00u, 0xe3u, 0x58u, - 0x00u, 0x24u, 0xa3u, 0x42u, 0x03u, 0xdau, 0x2cu, 0x79u, 0x02u, 0x3cu, 0x63u, 0x1eu, 0x9cu, 0x41u, 0x2fu, 0x78u, - 0x68u, 0x78u, 0xaau, 0x78u, 0xc3u, 0xe7u, 0xc0u, 0x46u, 0x00u, 0x00u, 0x26u, 0x40u, 0xc8u, 0x12u, 0x00u, 0x08u, - 0xf7u, 0xb5u, 0x48u, 0x4bu, 0x00u, 0x91u, 0x15u, 0x00u, 0x98u, 0x42u, 0x00u, 0xd9u, 0x87u, 0xe0u, 0x9au, 0x42u, - 0x00u, 0xd9u, 0x84u, 0xe0u, 0x44u, 0x4bu, 0x99u, 0x42u, 0x00u, 0xd9u, 0x80u, 0xe0u, 0x01u, 0x22u, 0x43u, 0x4bu, - 0x1au, 0x70u, 0xffu, 0x28u, 0x45u, 0xd8u, 0x0fu, 0x23u, 0x07u, 0x26u, 0x1cu, 0x00u, 0x18u, 0x40u, 0xffu, 0x2du, - 0x58u, 0xd8u, 0xffu, 0x22u, 0x2du, 0x01u, 0x15u, 0x40u, 0x28u, 0x43u, 0xf0u, 0x25u, 0xe0u, 0x22u, 0x2cu, 0x43u, - 0xf0u, 0x25u, 0xd2u, 0x02u, 0x32u, 0x43u, 0x2du, 0x03u, 0x2bu, 0x43u, 0x39u, 0x4du, 0x07u, 0x26u, 0x2fu, 0x68u, - 0x3du, 0x00u, 0xacu, 0x35u, 0x2du, 0x88u, 0x6eu, 0x43u, 0x35u, 0x00u, 0x01u, 0x96u, 0x3eu, 0x6au, 0xadu, 0x19u, - 0x2eu, 0x68u, 0x00u, 0x2eu, 0xfcu, 0xdau, 0x33u, 0x4du, 0x2eu, 0x78u, 0x33u, 0x4du, 0x00u, 0x2eu, 0x03u, 0xd0u, - 0x32u, 0x4eu, 0xaeu, 0x59u, 0x00u, 0x2eu, 0x50u, 0xdau, 0x31u, 0x4eu, 0x32u, 0x49u, 0x31u, 0x60u, 0x32u, 0x4eu, - 0x32u, 0x49u, 0x31u, 0x60u, 0xa3u, 0x21u, 0xc9u, 0x00u, 0x6eu, 0x58u, 0xa6u, 0x43u, 0x06u, 0x43u, 0x30u, 0x4cu, - 0x6eu, 0x50u, 0x28u, 0x59u, 0x98u, 0x43u, 0x02u, 0x43u, 0x00u, 0x20u, 0x2au, 0x51u, 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0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, 0x69u, 0x19u, 0x00u, 0x10u, + 0x01u, 0xb4u, 0x02u, 0x48u, 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, 0x0du, 0x15u, 0x00u, 0x10u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, }; #endif /* defined(CY_DEVICE_PSOC6ABLE2) */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/COMPONENT_CM0P_CRYPTO/psoc6_01_cm0p_crypto.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/COMPONENT_CM0P_CRYPTO/psoc6_01_cm0p_crypto.c index 29bc922310..348bc87a7a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/COMPONENT_CM0P_CRYPTO/psoc6_01_cm0p_crypto.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/COMPONENT_CM0P_CRYPTO/psoc6_01_cm0p_crypto.c @@ -40,35 +40,35 @@ const uint8_t cy_m0p_image[] = { 0x89u, 0x01u, 0x00u, 0x10u, 0x89u, 0x01u, 0x00u, 0x10u, 0x89u, 0x01u, 0x00u, 0x10u, 0x89u, 0x01u, 0x00u, 0x10u, 0x89u, 0x01u, 0x00u, 0x10u, 0x89u, 0x01u, 0x00u, 0x10u, 0x89u, 0x01u, 0x00u, 0x10u, 0x89u, 0x01u, 0x00u, 0x10u, 0x10u, 0xb5u, 0x06u, 0x4cu, 0x23u, 0x78u, 0x00u, 0x2bu, 0x07u, 0xd1u, 0x05u, 0x4bu, 0x00u, 0x2bu, 0x02u, 0xd0u, - 0x04u, 0x48u, 0x00u, 0xe0u, 0x00u, 0xbfu, 0x01u, 0x23u, 0x23u, 0x70u, 0x10u, 0xbdu, 0xf8u, 0x03u, 0x00u, 0x08u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x30u, 0x7fu, 0x00u, 0x10u, 0x04u, 0x4bu, 0x10u, 0xb5u, 0x00u, 0x2bu, 0x03u, 0xd0u, + 0x04u, 0x48u, 0x00u, 0xe0u, 0x00u, 0xbfu, 0x01u, 0x23u, 0x23u, 0x70u, 0x10u, 0xbdu, 0x08u, 0x04u, 0x00u, 0x08u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x38u, 0x7fu, 0x00u, 0x10u, 0x04u, 0x4bu, 0x10u, 0xb5u, 0x00u, 0x2bu, 0x03u, 0xd0u, 0x03u, 0x49u, 0x04u, 0x48u, 0x00u, 0xe0u, 0x00u, 0xbfu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0x00u, 0x00u, 0x00u, 0x00u, - 0xfcu, 0x03u, 0x00u, 0x08u, 0x30u, 0x7fu, 0x00u, 0x10u, 0x02u, 0x30u, 0x80u, 0x08u, 0x03u, 0xd0u, 0x01u, 0x30u, + 0x0cu, 0x04u, 0x00u, 0x08u, 0x38u, 0x7fu, 0x00u, 0x10u, 0x02u, 0x30u, 0x80u, 0x08u, 0x03u, 0xd0u, 0x01u, 0x30u, 0x02u, 0x38u, 0xfcu, 0xd1u, 0xc0u, 0x46u, 0xc0u, 0x46u, 0x70u, 0x47u, 0xefu, 0xf3u, 0x10u, 0x80u, 0x72u, 0xb6u, 0x70u, 0x47u, 0x80u, 0xf3u, 0x10u, 0x88u, 0x70u, 0x47u, 0x70u, 0x47u, 0xffu, 0xf7u, 0xfdu, 0xffu, 0x72u, 0xb6u, 0x0fu, 0x4cu, 0x10u, 0x4du, 0xacu, 0x42u, 0x09u, 0xdau, 0x21u, 0x68u, 0x62u, 0x68u, 0xa3u, 0x68u, 0x04u, 0x3bu, 0x02u, 0xdbu, 0xc8u, 0x58u, 0xd0u, 0x50u, 0xfau, 0xe7u, 0x0cu, 0x34u, 0xf3u, 0xe7u, 0x0au, 0x49u, 0x0bu, 0x4au, 0x00u, 0x20u, 0x52u, 0x1au, 0x02u, 0xddu, 0x04u, 0x3au, 0x88u, 0x50u, 0xfcu, 0xdcu, 0x08u, 0x48u, 0x09u, 0x49u, - 0x08u, 0x60u, 0xbfu, 0xf3u, 0x4fu, 0x8fu, 0x06u, 0xf0u, 0xc7u, 0xfdu, 0x06u, 0xf0u, 0x67u, 0xfdu, 0xfeu, 0xe7u, - 0x3cu, 0x7fu, 0x00u, 0x10u, 0x54u, 0x7fu, 0x00u, 0x10u, 0xf8u, 0x03u, 0x00u, 0x08u, 0x58u, 0x06u, 0x00u, 0x08u, + 0x08u, 0x60u, 0xbfu, 0xf3u, 0x4fu, 0x8fu, 0x06u, 0xf0u, 0xcbu, 0xfdu, 0x06u, 0xf0u, 0x6bu, 0xfdu, 0xfeu, 0xe7u, + 0x44u, 0x7fu, 0x00u, 0x10u, 0x5cu, 0x7fu, 0x00u, 0x10u, 0x08u, 0x04u, 0x00u, 0x08u, 0x68u, 0x06u, 0x00u, 0x08u, 0x00u, 0x00u, 0x00u, 0x08u, 0x08u, 0xedu, 0x00u, 0xe0u, 0xfeu, 0xe7u, 0xfeu, 0xe7u, 0x00u, 0xb5u, 0x04u, 0x20u, 0x71u, 0x46u, 0x08u, 0x42u, 0x02u, 0xd0u, 0xefu, 0xf3u, 0x09u, 0x80u, 0x01u, 0xe0u, 0xefu, 0xf3u, 0x08u, 0x80u, - 0x04u, 0x30u, 0x06u, 0xf0u, 0x59u, 0xfbu, 0xfeu, 0xe7u, 0xf7u, 0xb5u, 0x03u, 0x27u, 0x11u, 0x4eu, 0x14u, 0x00u, + 0x04u, 0x30u, 0x06u, 0xf0u, 0x5du, 0xfbu, 0xfeu, 0xe7u, 0xf7u, 0xb5u, 0x03u, 0x27u, 0x11u, 0x4eu, 0x14u, 0x00u, 0x32u, 0x68u, 0x05u, 0x00u, 0x52u, 0x69u, 0x82u, 0x18u, 0x08u, 0x78u, 0x49u, 0x68u, 0x38u, 0x40u, 0x10u, 0x60u, 0x01u, 0x2cu, 0x00u, 0xd1u, 0x20u, 0x31u, 0x28u, 0x00u, 0x08u, 0x9au, 0x01u, 0x3cu, 0x03u, 0xf0u, 0x72u, 0xfdu, 0x0cu, 0x23u, 0x61u, 0x42u, 0x61u, 0x41u, 0x00u, 0x93u, 0x28u, 0x00u, 0x08u, 0x3bu, 0x44u, 0x31u, 0x00u, 0x22u, 0x03u, 0xf0u, 0xd0u, 0xfdu, 0x33u, 0x68u, 0x1bu, 0x68u, 0xedu, 0x18u, 0x01u, 0x23u, 0x2au, 0x68u, 0x1au, 0x42u, - 0xfcu, 0xd1u, 0xf7u, 0xbdu, 0x18u, 0x04u, 0x00u, 0x08u, 0x73u, 0xb5u, 0x04u, 0x00u, 0x08u, 0x00u, 0x03u, 0x26u, + 0xfcu, 0xd1u, 0xf7u, 0xbdu, 0x28u, 0x04u, 0x00u, 0x08u, 0x73u, 0xb5u, 0x04u, 0x00u, 0x08u, 0x00u, 0x03u, 0x26u, 0x0eu, 0x4du, 0x19u, 0x00u, 0x2bu, 0x68u, 0x00u, 0x78u, 0x5bu, 0x69u, 0x30u, 0x40u, 0xe3u, 0x18u, 0x18u, 0x60u, 0x13u, 0x00u, 0x20u, 0x00u, 0x06u, 0x9au, 0x03u, 0xf0u, 0x4du, 0xfdu, 0x08u, 0x23u, 0x20u, 0x00u, 0x00u, 0x93u, 0x00u, 0x22u, 0x04u, 0x3bu, 0x48u, 0x21u, 0x03u, 0xf0u, 0xadu, 0xfdu, 0x2bu, 0x68u, 0x1bu, 0x68u, 0xe4u, 0x18u, - 0x01u, 0x23u, 0x22u, 0x68u, 0x1au, 0x42u, 0xfcu, 0xd1u, 0x73u, 0xbdu, 0xc0u, 0x46u, 0x18u, 0x04u, 0x00u, 0x08u, + 0x01u, 0x23u, 0x22u, 0x68u, 0x1au, 0x42u, 0xfcu, 0xd1u, 0x73u, 0xbdu, 0xc0u, 0x46u, 0x28u, 0x04u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x1du, 0x00u, 0x1au, 0x70u, 0x04u, 0x9bu, 0x02u, 0x32u, 0x6bu, 0x60u, 0xd3u, 0x00u, 0x0au, 0x00u, 0x04u, 0x99u, 0x04u, 0x00u, 0x03u, 0xf0u, 0xceu, 0xfdu, 0x03u, 0x21u, 0x0du, 0x4eu, 0x2au, 0x78u, 0x33u, 0x68u, 0x0au, 0x40u, 0x5bu, 0x69u, 0x69u, 0x68u, 0xe3u, 0x18u, 0x1au, 0x60u, 0x0au, 0x00u, 0x20u, 0x00u, 0x20u, 0x32u, 0x03u, 0xf0u, 0x06u, 0xfdu, 0x08u, 0x23u, 0x20u, 0x00u, 0x00u, 0x22u, 0x46u, 0x21u, 0x03u, 0xf0u, 0x6cu, 0xfdu, 0x33u, 0x68u, 0x1bu, 0x68u, 0xe4u, 0x18u, 0x01u, 0x23u, 0x20u, 0x68u, 0x18u, 0x40u, 0xfcu, 0xd1u, 0x70u, 0xbdu, - 0x18u, 0x04u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x85u, 0xb0u, 0x16u, 0x00u, 0x1au, 0x00u, 0x0au, 0x9bu, 0x05u, 0x00u, + 0x28u, 0x04u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x85u, 0xb0u, 0x16u, 0x00u, 0x1au, 0x00u, 0x0au, 0x9bu, 0x05u, 0x00u, 0x5cu, 0x68u, 0x03u, 0x91u, 0x27u, 0x00u, 0x40u, 0x37u, 0x39u, 0x00u, 0x50u, 0x34u, 0x10u, 0x23u, 0x03u, 0xf0u, 0xa1u, 0xfdu, 0x23u, 0x00u, 0x03u, 0x9au, 0x0au, 0x99u, 0x28u, 0x00u, 0x00u, 0x97u, 0xffu, 0xf7u, 0x74u, 0xffu, 0x28u, 0x00u, 0x10u, 0x23u, 0x22u, 0x00u, 0x31u, 0x00u, 0x03u, 0xf0u, 0x94u, 0xfdu, 0x00u, 0x20u, 0x05u, 0xb0u, @@ -99,7 +99,7 @@ const uint8_t cy_m0p_image[] = { 0xd3u, 0xfeu, 0x10u, 0x23u, 0x2au, 0x00u, 0x07u, 0x99u, 0x30u, 0x00u, 0x03u, 0xf0u, 0xcbu, 0xfcu, 0x10u, 0x3cu, 0xcfu, 0xe7u, 0x01u, 0x48u, 0xdfu, 0xe7u, 0xc0u, 0x46u, 0x02u, 0x00u, 0x32u, 0x00u, 0xf0u, 0xb5u, 0x91u, 0xb0u, 0x19u, 0x9du, 0x04u, 0x00u, 0x06u, 0x91u, 0x0bu, 0x92u, 0x00u, 0x21u, 0x10u, 0x22u, 0x0cu, 0xa8u, 0x07u, 0x93u, - 0x06u, 0xf0u, 0xc5u, 0xfeu, 0x6bu, 0x68u, 0x0cu, 0xa9u, 0x1au, 0x00u, 0x40u, 0x32u, 0x03u, 0x92u, 0x60u, 0x33u, + 0x06u, 0xf0u, 0xc9u, 0xfeu, 0x6bu, 0x68u, 0x0cu, 0xa9u, 0x1au, 0x00u, 0x40u, 0x32u, 0x03u, 0x92u, 0x60u, 0x33u, 0x10u, 0x32u, 0x04u, 0x92u, 0x05u, 0x93u, 0x07u, 0x9au, 0x10u, 0x23u, 0x20u, 0x00u, 0x03u, 0xf0u, 0xaau, 0xfcu, 0x0fu, 0x9bu, 0x1bu, 0xbau, 0x08u, 0x93u, 0x06u, 0x9bu, 0x08u, 0x9eu, 0x1bu, 0x09u, 0x0au, 0x93u, 0x0eu, 0x9bu, 0x1fu, 0xbau, 0x08u, 0x9bu, 0x17u, 0x99u, 0xf3u, 0x1au, 0x1au, 0x01u, 0x89u, 0x18u, 0x09u, 0x91u, 0x18u, 0x99u, @@ -111,32 +111,32 @@ const uint8_t cy_m0p_image[] = { 0x0eu, 0x92u, 0x00u, 0x93u, 0x04u, 0x9au, 0x03u, 0x9bu, 0x29u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x6cu, 0xfeu, 0x10u, 0x23u, 0x04u, 0x9au, 0x09u, 0x99u, 0x20u, 0x00u, 0x03u, 0xf0u, 0x64u, 0xfcu, 0xc1u, 0xe7u, 0x00u, 0x00u, 0x03u, 0x4bu, 0x1bu, 0x68u, 0x9bu, 0x68u, 0xc0u, 0x18u, 0x0fu, 0x23u, 0x00u, 0x68u, 0x18u, 0x40u, 0x70u, 0x47u, - 0x18u, 0x04u, 0x00u, 0x08u, 0x03u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xc0u, 0x18u, 0x03u, 0x68u, 0x00u, 0x2bu, - 0xfcu, 0xd1u, 0x70u, 0x47u, 0x18u, 0x04u, 0x00u, 0x08u, 0xf8u, 0xb5u, 0x04u, 0x00u, 0x0du, 0x00u, 0x17u, 0x00u, + 0x28u, 0x04u, 0x00u, 0x08u, 0x03u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xc0u, 0x18u, 0x03u, 0x68u, 0x00u, 0x2bu, + 0xfcu, 0xd1u, 0x70u, 0x47u, 0x28u, 0x04u, 0x00u, 0x08u, 0xf8u, 0xb5u, 0x04u, 0x00u, 0x0du, 0x00u, 0x17u, 0x00u, 0x1eu, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xe4u, 0xffu, 0x04u, 0x28u, 0xfau, 0xd8u, 0x08u, 0x2du, 0x04u, 0xd0u, 0x0cu, 0x4au, 0xa3u, 0x58u, 0x00u, 0x2bu, 0xfcu, 0xdbu, 0x04u, 0xe0u, 0x86u, 0x22u, 0x52u, 0x01u, 0xa3u, 0x58u, 0x00u, 0x2bu, 0xfcu, 0xdbu, 0xe2u, 0x21u, 0x08u, 0x4bu, 0xc9u, 0x05u, 0x1bu, 0x68u, 0x0du, 0x43u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x15u, 0x60u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x17u, 0x60u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0x26u, 0x60u, - 0xf8u, 0xbdu, 0xc0u, 0x46u, 0xd0u, 0x10u, 0x00u, 0x00u, 0x18u, 0x04u, 0x00u, 0x08u, 0xf8u, 0xb5u, 0x07u, 0x00u, + 0xf8u, 0xbdu, 0xc0u, 0x46u, 0xd0u, 0x10u, 0x00u, 0x00u, 0x28u, 0x04u, 0x00u, 0x08u, 0xf8u, 0xb5u, 0x07u, 0x00u, 0x0cu, 0x00u, 0x16u, 0x00u, 0x1du, 0x00u, 0x38u, 0x00u, 0xffu, 0xf7u, 0xbau, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x06u, 0x4bu, 0x24u, 0x03u, 0x1bu, 0x68u, 0x2du, 0x04u, 0xd8u, 0x68u, 0x80u, 0x23u, 0xdbu, 0x05u, 0x1eu, 0x43u, - 0x34u, 0x43u, 0x38u, 0x18u, 0x2cu, 0x43u, 0x04u, 0x60u, 0xf8u, 0xbdu, 0xc0u, 0x46u, 0x18u, 0x04u, 0x00u, 0x08u, + 0x34u, 0x43u, 0x38u, 0x18u, 0x2cu, 0x43u, 0x04u, 0x60u, 0xf8u, 0xbdu, 0xc0u, 0x46u, 0x28u, 0x04u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x05u, 0x00u, 0x0cu, 0x00u, 0x16u, 0x00u, 0x28u, 0x00u, 0xffu, 0xf7u, 0xa1u, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x05u, 0x4bu, 0x24u, 0x02u, 0x1bu, 0x68u, 0xdbu, 0x68u, 0xedu, 0x18u, 0xd0u, 0x23u, 0xdbu, 0x05u, - 0x1eu, 0x43u, 0x34u, 0x43u, 0x2cu, 0x60u, 0x70u, 0xbdu, 0x18u, 0x04u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, + 0x1eu, 0x43u, 0x34u, 0x43u, 0x2cu, 0x60u, 0x70u, 0xbdu, 0x28u, 0x04u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x8du, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x04u, 0x4bu, 0x1bu, 0x68u, 0xdbu, 0x68u, - 0xe4u, 0x18u, 0xa0u, 0x23u, 0xdbu, 0x05u, 0x23u, 0x60u, 0x10u, 0xbdu, 0xc0u, 0x46u, 0x18u, 0x04u, 0x00u, 0x08u, + 0xe4u, 0x18u, 0xa0u, 0x23u, 0xdbu, 0x05u, 0x23u, 0x60u, 0x10u, 0xbdu, 0xc0u, 0x46u, 0x28u, 0x04u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x7bu, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x04u, 0x4bu, 0x1bu, 0x68u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0xa2u, 0x23u, 0xdbu, 0x05u, 0x23u, 0x60u, 0x10u, 0xbdu, 0xc0u, 0x46u, - 0x18u, 0x04u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x04u, 0x00u, 0x0eu, 0x00u, 0x15u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, + 0x28u, 0x04u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x04u, 0x00u, 0x0eu, 0x00u, 0x15u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x67u, 0xffu, 0x04u, 0x28u, 0xfau, 0xd8u, 0x06u, 0x4bu, 0x06u, 0x49u, 0x1bu, 0x68u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x11u, 0x60u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x16u, 0x60u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0x25u, 0x60u, 0x70u, 0xbdu, - 0x18u, 0x04u, 0x00u, 0x08u, 0x0cu, 0x00u, 0x00u, 0x70u, 0x70u, 0xb5u, 0x05u, 0x00u, 0x0cu, 0x78u, 0x4au, 0x68u, + 0x28u, 0x04u, 0x00u, 0x08u, 0x0cu, 0x00u, 0x00u, 0x70u, 0x70u, 0xb5u, 0x05u, 0x00u, 0x0cu, 0x78u, 0x4au, 0x68u, 0x02u, 0x34u, 0xe4u, 0x00u, 0x23u, 0x00u, 0x0eu, 0x00u, 0x08u, 0x21u, 0xffu, 0xf7u, 0x5du, 0xffu, 0x10u, 0x23u, 0x08u, 0x22u, 0x04u, 0x21u, 0x28u, 0x00u, 0xffu, 0xf7u, 0x81u, 0xffu, 0x23u, 0x00u, 0x10u, 0x3bu, 0x00u, 0x2bu, 0x04u, 0xd0u, 0x08u, 0x22u, 0x05u, 0x21u, 0x28u, 0x00u, 0xffu, 0xf7u, 0x78u, 0xffu, 0x03u, 0x21u, 0x05u, 0x4bu, 0x32u, 0x78u, 0x1bu, 0x68u, 0x0au, 0x40u, 0x5bu, 0x69u, 0x28u, 0x00u, 0xebu, 0x18u, 0x1au, 0x60u, 0xffu, 0xf7u, - 0x39u, 0xffu, 0x70u, 0xbdu, 0x18u, 0x04u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x05u, 0x00u, 0x0bu, 0x78u, 0x02u, 0x33u, + 0x39u, 0xffu, 0x70u, 0xbdu, 0x28u, 0x04u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x05u, 0x00u, 0x0bu, 0x78u, 0x02u, 0x33u, 0xdcu, 0x00u, 0xffu, 0xf7u, 0xd1u, 0xffu, 0x28u, 0x00u, 0xffu, 0xf7u, 0x90u, 0xffu, 0x10u, 0x23u, 0x06u, 0x22u, 0x04u, 0x21u, 0x28u, 0x00u, 0xffu, 0xf7u, 0x5au, 0xffu, 0x23u, 0x00u, 0x10u, 0x3bu, 0x00u, 0x2bu, 0x04u, 0xd0u, 0x07u, 0x22u, 0x05u, 0x21u, 0x28u, 0x00u, 0xffu, 0xf7u, 0x51u, 0xffu, 0x28u, 0x00u, 0xffu, 0xf7u, 0x1au, 0xffu, @@ -164,7 +164,7 @@ const uint8_t cy_m0p_image[] = { 0x00u, 0x21u, 0xffu, 0xf7u, 0xa3u, 0xfeu, 0x20u, 0x00u, 0xffu, 0xf7u, 0xe2u, 0xfeu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x5fu, 0xfeu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x08u, 0x4bu, 0x09u, 0x4au, 0x1bu, 0x68u, 0x02u, 0x21u, 0xdbu, 0x68u, 0x20u, 0x00u, 0xe3u, 0x18u, 0x1au, 0x60u, 0x10u, 0x23u, 0x00u, 0x22u, 0xffu, 0xf7u, 0x8fu, 0xfeu, 0x10u, 0x3du, - 0xdfu, 0xe7u, 0x04u, 0x48u, 0xbfu, 0xe7u, 0xc0u, 0x46u, 0x18u, 0x04u, 0x00u, 0x08u, 0x18u, 0x00u, 0x10u, 0x41u, + 0xdfu, 0xe7u, 0x04u, 0x48u, 0xbfu, 0xe7u, 0xc0u, 0x46u, 0x28u, 0x04u, 0x00u, 0x08u, 0x18u, 0x00u, 0x10u, 0x41u, 0x21u, 0xc0u, 0x10u, 0x41u, 0x02u, 0x00u, 0x32u, 0x00u, 0xf7u, 0xb5u, 0x0fu, 0x26u, 0x04u, 0x00u, 0x01u, 0x91u, 0x15u, 0x00u, 0x1fu, 0x00u, 0x16u, 0x40u, 0x5eu, 0xd1u, 0x0au, 0x99u, 0xffu, 0xf7u, 0xe5u, 0xfeu, 0x10u, 0x23u, 0x3au, 0x00u, 0x09u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x47u, 0xfeu, 0x10u, 0x23u, 0x09u, 0x22u, 0x31u, 0x00u, @@ -178,7 +178,7 @@ const uint8_t cy_m0p_image[] = { 0x1au, 0x60u, 0x10u, 0x23u, 0x00u, 0x22u, 0xffu, 0xf7u, 0x31u, 0xfeu, 0x10u, 0x3du, 0x00u, 0x2du, 0xe8u, 0xd1u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xf7u, 0xfdu, 0x10u, 0x22u, 0x39u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x7au, 0xfeu, 0x10u, 0x23u, 0x00u, 0x22u, 0x0cu, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x20u, 0xfeu, 0x20u, 0x00u, 0xffu, 0xf7u, - 0xe9u, 0xfdu, 0x00u, 0x20u, 0xfeu, 0xbdu, 0x04u, 0x48u, 0xfcu, 0xe7u, 0xc0u, 0x46u, 0x18u, 0x04u, 0x00u, 0x08u, + 0xe9u, 0xfdu, 0x00u, 0x20u, 0xfeu, 0xbdu, 0x04u, 0x48u, 0xfcu, 0xe7u, 0xc0u, 0x46u, 0x28u, 0x04u, 0x00u, 0x08u, 0x01u, 0xc0u, 0x10u, 0x41u, 0x18u, 0x00u, 0x10u, 0x41u, 0x02u, 0x00u, 0x32u, 0x00u, 0xf0u, 0xb5u, 0x1du, 0x00u, 0x8bu, 0xb0u, 0x04u, 0x92u, 0x6au, 0x78u, 0x1bu, 0x78u, 0x12u, 0x02u, 0x1au, 0x43u, 0xabu, 0x78u, 0x04u, 0x00u, 0x1bu, 0x04u, 0x1au, 0x43u, 0xebu, 0x78u, 0x2eu, 0x7au, 0x1bu, 0x06u, 0x13u, 0x43u, 0x6au, 0x79u, 0x06u, 0x93u, @@ -203,7 +203,7 @@ const uint8_t cy_m0p_image[] = { 0xf2u, 0xb2u, 0x0fu, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x83u, 0xfdu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x28u, 0xfdu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x08u, 0x4bu, 0x09u, 0x4au, 0x1bu, 0x68u, 0xdbu, 0x68u, 0xe3u, 0x18u, 0x1au, 0x60u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x1du, 0xfdu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x03u, 0x4bu, 0x04u, 0x4au, 0x1bu, 0x68u, - 0xdbu, 0x68u, 0xe3u, 0x18u, 0x1au, 0x60u, 0xb3u, 0xe7u, 0x18u, 0x04u, 0x00u, 0x08u, 0x10u, 0x10u, 0x00u, 0x66u, + 0xdbu, 0x68u, 0xe3u, 0x18u, 0x1au, 0x60u, 0xb3u, 0xe7u, 0x28u, 0x04u, 0x00u, 0x08u, 0x10u, 0x10u, 0x00u, 0x66u, 0x10u, 0x10u, 0x00u, 0x67u, 0x02u, 0x00u, 0x00u, 0x23u, 0x10u, 0xb5u, 0x0fu, 0x32u, 0x44u, 0x1eu, 0x11u, 0x78u, 0x01u, 0x3au, 0x49u, 0x00u, 0x0bu, 0x43u, 0x53u, 0x70u, 0x1bu, 0x0au, 0x94u, 0x42u, 0xf7u, 0xd1u, 0x00u, 0x2bu, 0x04u, 0xd0u, 0x79u, 0x23u, 0xc2u, 0x7bu, 0x5bu, 0x42u, 0x53u, 0x40u, 0xc3u, 0x73u, 0x10u, 0xbdu, 0xf7u, 0xb5u, @@ -230,34 +230,34 @@ const uint8_t cy_m0p_image[] = { 0xa0u, 0x36u, 0x80u, 0x33u, 0x33u, 0x60u, 0x03u, 0x9bu, 0x90u, 0x34u, 0x73u, 0x60u, 0x32u, 0x00u, 0x0cu, 0x99u, 0x28u, 0x00u, 0xb4u, 0x60u, 0xffu, 0xf7u, 0x53u, 0xffu, 0x02u, 0x9bu, 0x32u, 0x00u, 0x0cu, 0x99u, 0x28u, 0x00u, 0x00u, 0x97u, 0xffu, 0xf7u, 0x61u, 0xffu, 0x28u, 0x00u, 0x0bu, 0x9bu, 0x32u, 0x00u, 0x0cu, 0x99u, 0xffu, 0xf7u, - 0x8du, 0xffu, 0x00u, 0x20u, 0x05u, 0xb0u, 0xf0u, 0xbdu, 0x18u, 0x04u, 0x00u, 0x08u, 0x03u, 0x4bu, 0x1bu, 0x68u, - 0x9bu, 0x68u, 0xc0u, 0x18u, 0x0fu, 0x23u, 0x00u, 0x68u, 0x18u, 0x40u, 0x70u, 0x47u, 0x18u, 0x04u, 0x00u, 0x08u, + 0x8du, 0xffu, 0x00u, 0x20u, 0x05u, 0xb0u, 0xf0u, 0xbdu, 0x28u, 0x04u, 0x00u, 0x08u, 0x03u, 0x4bu, 0x1bu, 0x68u, + 0x9bu, 0x68u, 0xc0u, 0x18u, 0x0fu, 0x23u, 0x00u, 0x68u, 0x18u, 0x40u, 0x70u, 0x47u, 0x28u, 0x04u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xf1u, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x04u, 0x4bu, 0x1bu, 0x68u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0xa0u, 0x23u, 0xdbu, 0x05u, 0x23u, 0x60u, 0x10u, 0xbdu, 0xc0u, 0x46u, - 0x18u, 0x04u, 0x00u, 0x08u, 0x02u, 0x00u, 0x00u, 0x23u, 0x10u, 0xb5u, 0x0fu, 0x32u, 0x44u, 0x1eu, 0x11u, 0x78u, + 0x28u, 0x04u, 0x00u, 0x08u, 0x02u, 0x00u, 0x00u, 0x23u, 0x10u, 0xb5u, 0x0fu, 0x32u, 0x44u, 0x1eu, 0x11u, 0x78u, 0x01u, 0x3au, 0x49u, 0x00u, 0x0bu, 0x43u, 0x53u, 0x70u, 0x1bu, 0x0au, 0x94u, 0x42u, 0xf7u, 0xd1u, 0x00u, 0x2bu, 0x04u, 0xd0u, 0x79u, 0x23u, 0xc2u, 0x7bu, 0x5bu, 0x42u, 0x53u, 0x40u, 0xc3u, 0x73u, 0x10u, 0xbdu, 0x00u, 0x00u, 0x70u, 0xb5u, 0x04u, 0x00u, 0x0eu, 0x00u, 0x15u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xc7u, 0xffu, 0x04u, 0x28u, 0xfau, 0xd8u, 0x86u, 0x22u, 0x52u, 0x01u, 0xa3u, 0x58u, 0x00u, 0x2bu, 0xfcu, 0xdbu, 0x06u, 0x4bu, 0x07u, 0x49u, 0x1bu, 0x68u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x11u, 0x60u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x16u, 0x60u, 0xdbu, 0x68u, - 0xe4u, 0x18u, 0x25u, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u, 0x18u, 0x04u, 0x00u, 0x08u, 0x08u, 0x00u, 0x00u, 0x71u, + 0xe4u, 0x18u, 0x25u, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u, 0x28u, 0x04u, 0x00u, 0x08u, 0x08u, 0x00u, 0x00u, 0x71u, 0x70u, 0xb5u, 0x04u, 0x00u, 0x0du, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa8u, 0xffu, 0x04u, 0x28u, 0xfau, 0xd8u, 0x06u, 0x4bu, 0x07u, 0x49u, 0x1bu, 0x68u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x11u, 0x60u, 0xdau, 0x68u, 0xa2u, 0x18u, - 0x15u, 0x60u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0x10u, 0x23u, 0x23u, 0x60u, 0x70u, 0xbdu, 0x18u, 0x04u, 0x00u, 0x08u, + 0x15u, 0x60u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0x10u, 0x23u, 0x23u, 0x60u, 0x70u, 0xbdu, 0x28u, 0x04u, 0x00u, 0x08u, 0x0cu, 0x00u, 0x00u, 0x70u, 0x00u, 0x23u, 0x70u, 0xb5u, 0x04u, 0x00u, 0x0eu, 0x00u, 0x0bu, 0x60u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x8cu, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x14u, 0x4du, 0x15u, 0x4au, 0x2bu, 0x68u, 0x20u, 0x00u, 0xdbu, 0x68u, 0xe3u, 0x18u, 0x1au, 0x60u, 0xffu, 0xf7u, 0x8bu, 0xffu, 0x71u, 0x68u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xcfu, 0xffu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x7au, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x2au, 0x68u, 0x0du, 0x49u, 0xd3u, 0x68u, 0xe3u, 0x18u, 0x19u, 0x60u, 0x13u, 0x68u, 0xe3u, 0x18u, 0x1au, 0x68u, 0x00u, 0x2au, 0xfcu, 0xd1u, 0x70u, 0x68u, 0xffu, 0xf7u, 0x87u, 0xffu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x68u, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, - 0x2bu, 0x68u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0x04u, 0x4bu, 0x23u, 0x60u, 0x70u, 0xbdu, 0x18u, 0x04u, 0x00u, 0x08u, + 0x2bu, 0x68u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0x04u, 0x4bu, 0x23u, 0x60u, 0x70u, 0xbdu, 0x28u, 0x04u, 0x00u, 0x08u, 0x00u, 0x00u, 0x10u, 0x41u, 0x01u, 0xc0u, 0x10u, 0x40u, 0x11u, 0x10u, 0x10u, 0x41u, 0x70u, 0xb5u, 0x0eu, 0x00u, 0x11u, 0x00u, 0x32u, 0x68u, 0x05u, 0x00u, 0x9cu, 0x18u, 0x1au, 0x00u, 0xffu, 0xf7u, 0x81u, 0xffu, 0x10u, 0x2cu, 0x01u, 0xd8u, 0x34u, 0x60u, 0x70u, 0xbdu, 0x28u, 0x00u, 0xffu, 0xf7u, 0x48u, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x05u, 0x4bu, 0x06u, 0x4au, 0x1bu, 0x68u, 0x28u, 0x00u, 0xdbu, 0x68u, 0x10u, 0x3cu, 0xebu, 0x18u, 0x1au, 0x60u, - 0xffu, 0xf7u, 0x46u, 0xffu, 0xebu, 0xe7u, 0xc0u, 0x46u, 0x18u, 0x04u, 0x00u, 0x08u, 0x18u, 0x00u, 0x10u, 0x41u, + 0xffu, 0xf7u, 0x46u, 0xffu, 0xebu, 0xe7u, 0xc0u, 0x46u, 0x28u, 0x04u, 0x00u, 0x08u, 0x18u, 0x00u, 0x10u, 0x41u, 0xf0u, 0xb5u, 0x10u, 0x25u, 0x87u, 0xb0u, 0x0fu, 0x00u, 0x04u, 0x00u, 0x01u, 0x92u, 0x00u, 0x21u, 0x2au, 0x00u, - 0x02u, 0xa8u, 0x06u, 0xf0u, 0xd4u, 0xf9u, 0x80u, 0x23u, 0x7eu, 0x68u, 0x3fu, 0x68u, 0x02u, 0xaau, 0x13u, 0x70u, + 0x02u, 0xa8u, 0x06u, 0xf0u, 0xd8u, 0xf9u, 0x80u, 0x23u, 0x7eu, 0x68u, 0x3fu, 0x68u, 0x02u, 0xaau, 0x13u, 0x70u, 0x02u, 0xa9u, 0xeau, 0x1bu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x53u, 0xffu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x1eu, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x18u, 0x4du, 0x19u, 0x4au, 0x2bu, 0x68u, 0xdbu, 0x68u, 0xe3u, 0x18u, 0x1au, 0x60u, 0x0fu, 0x2fu, 0x02u, 0xd8u, 0x30u, 0x00u, 0xffu, 0xf7u, 0x2du, 0xffu, 0x10u, 0x22u, 0x31u, 0x00u, 0x20u, 0x00u, @@ -265,10 +265,10 @@ const uint8_t cy_m0p_image[] = { 0x0fu, 0x4au, 0xdbu, 0x68u, 0x20u, 0x00u, 0xe3u, 0x18u, 0x1au, 0x60u, 0xffu, 0xf7u, 0x09u, 0xffu, 0x01u, 0x99u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x4du, 0xffu, 0x20u, 0x00u, 0xffu, 0xf7u, 0xf8u, 0xfeu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x2au, 0x68u, 0x08u, 0x49u, 0xd3u, 0x68u, 0xe3u, 0x18u, 0x19u, 0x60u, 0x13u, 0x68u, 0xe4u, 0x18u, 0x23u, 0x68u, - 0x00u, 0x2bu, 0xfcu, 0xd1u, 0x07u, 0xb0u, 0xf0u, 0xbdu, 0x18u, 0x04u, 0x00u, 0x08u, 0x18u, 0x00u, 0x10u, 0x41u, + 0x00u, 0x2bu, 0xfcu, 0xd1u, 0x07u, 0xb0u, 0xf0u, 0xbdu, 0x28u, 0x04u, 0x00u, 0x08u, 0x18u, 0x00u, 0x10u, 0x41u, 0x08u, 0x00u, 0x10u, 0x41u, 0x01u, 0xc0u, 0x10u, 0x40u, 0xf0u, 0xb5u, 0x04u, 0x00u, 0x1eu, 0x00u, 0xa7u, 0xb0u, 0x2cu, 0xabu, 0x0au, 0xadu, 0x1fu, 0x78u, 0x02u, 0x91u, 0x03u, 0x92u, 0x00u, 0x21u, 0x70u, 0x22u, 0x28u, 0x00u, - 0x06u, 0xf0u, 0x7du, 0xf9u, 0x18u, 0x22u, 0x00u, 0x21u, 0x04u, 0xa8u, 0x06u, 0xf0u, 0x78u, 0xf9u, 0x3au, 0x00u, + 0x06u, 0xf0u, 0x81u, 0xf9u, 0x18u, 0x22u, 0x00u, 0x21u, 0x04u, 0xa8u, 0x06u, 0xf0u, 0x7cu, 0xf9u, 0x3au, 0x00u, 0x2eu, 0x9bu, 0x31u, 0x00u, 0x00u, 0x95u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xf3u, 0xfbu, 0x2eu, 0x99u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xaau, 0xfbu, 0x06u, 0xabu, 0x04u, 0xa9u, 0x20u, 0x00u, 0x05u, 0x93u, 0xffu, 0xf7u, 0x2au, 0xffu, 0x03u, 0x9bu, 0x02u, 0x9au, 0x04u, 0xa9u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x60u, 0xffu, 0x20u, 0x00u, 0x2du, 0x9au, @@ -276,30 +276,30 @@ const uint8_t cy_m0p_image[] = { 0x0cu, 0x4cu, 0x7fu, 0x00u, 0x25u, 0x68u, 0xdbu, 0xb2u, 0x2cu, 0x6au, 0x06u, 0x19u, 0x05u, 0x9cu, 0x24u, 0x02u, 0x3cu, 0x40u, 0xffu, 0x3fu, 0x3au, 0x40u, 0x22u, 0x43u, 0x32u, 0x60u, 0x6au, 0x6au, 0x82u, 0x18u, 0x13u, 0x60u, 0xabu, 0x6au, 0xc3u, 0x18u, 0x19u, 0x60u, 0xebu, 0x6au, 0xc0u, 0x18u, 0x06u, 0x9bu, 0x03u, 0x60u, 0x00u, 0x20u, - 0xf0u, 0xbdu, 0xc0u, 0x46u, 0x18u, 0x04u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x0du, 0x00u, 0x11u, 0x00u, 0x86u, 0x22u, + 0xf0u, 0xbdu, 0xc0u, 0x46u, 0x28u, 0x04u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x0du, 0x00u, 0x11u, 0x00u, 0x86u, 0x22u, 0x04u, 0x00u, 0x04u, 0x98u, 0xd2u, 0x00u, 0xa0u, 0x50u, 0x1au, 0x00u, 0x20u, 0x00u, 0x02u, 0xf0u, 0x68u, 0xfeu, 0x04u, 0x23u, 0x00u, 0x22u, 0x58u, 0x21u, 0x20u, 0x00u, 0x02u, 0xf0u, 0xceu, 0xfeu, 0x08u, 0x21u, 0x06u, 0x4bu, 0x1au, 0x68u, 0x13u, 0x68u, 0xe3u, 0x18u, 0x18u, 0x68u, 0x08u, 0x40u, 0xfcu, 0xd1u, 0x13u, 0x6bu, 0xe4u, 0x18u, - 0x23u, 0x68u, 0x2bu, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u, 0x18u, 0x04u, 0x00u, 0x08u, 0x03u, 0x4bu, 0x1bu, 0x68u, - 0x1bu, 0x68u, 0xc0u, 0x18u, 0x03u, 0x68u, 0x00u, 0x2bu, 0xfcu, 0xd1u, 0x70u, 0x47u, 0x18u, 0x04u, 0x00u, 0x08u, + 0x23u, 0x68u, 0x2bu, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u, 0x28u, 0x04u, 0x00u, 0x08u, 0x03u, 0x4bu, 0x1bu, 0x68u, + 0x1bu, 0x68u, 0xc0u, 0x18u, 0x03u, 0x68u, 0x00u, 0x2bu, 0xfcu, 0xd1u, 0x70u, 0x47u, 0x28u, 0x04u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x0fu, 0x26u, 0x09u, 0x4bu, 0x1bu, 0x68u, 0x9cu, 0x68u, 0x05u, 0x19u, 0x2cu, 0x68u, 0x34u, 0x40u, 0x04u, 0x2cu, 0xfbu, 0xd8u, 0xdcu, 0x68u, 0x06u, 0x4du, 0x04u, 0x19u, 0x25u, 0x60u, 0xdcu, 0x68u, 0x04u, 0x19u, - 0x21u, 0x60u, 0xdbu, 0x68u, 0xc0u, 0x18u, 0x02u, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u, 0x18u, 0x04u, 0x00u, 0x08u, + 0x21u, 0x60u, 0xdbu, 0x68u, 0xc0u, 0x18u, 0x02u, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u, 0x28u, 0x04u, 0x00u, 0x08u, 0x08u, 0x00u, 0x00u, 0x70u, 0x10u, 0xb5u, 0x0fu, 0x24u, 0x06u, 0x4bu, 0x19u, 0x68u, 0x8bu, 0x68u, 0xc2u, 0x18u, 0x13u, 0x68u, 0x23u, 0x40u, 0x06u, 0x2bu, 0xfbu, 0xd8u, 0xcbu, 0x68u, 0xc0u, 0x18u, 0xb0u, 0x23u, 0xdbu, 0x05u, - 0x03u, 0x60u, 0x10u, 0xbdu, 0x18u, 0x04u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x80u, 0x27u, 0x0cu, 0x4cu, 0x7fu, 0x00u, + 0x03u, 0x60u, 0x10u, 0xbdu, 0x28u, 0x04u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x80u, 0x27u, 0x0cu, 0x4cu, 0x7fu, 0x00u, 0x25u, 0x68u, 0xdbu, 0xb2u, 0x2cu, 0x6au, 0x06u, 0x19u, 0x05u, 0x9cu, 0x24u, 0x02u, 0x3cu, 0x40u, 0xffu, 0x3fu, 0x3au, 0x40u, 0x22u, 0x43u, 0x32u, 0x60u, 0x6au, 0x6au, 0x82u, 0x18u, 0x13u, 0x60u, 0xabu, 0x6au, 0xc3u, 0x18u, 0x19u, 0x60u, 0xebu, 0x6au, 0xc0u, 0x18u, 0x06u, 0x9bu, 0x03u, 0x60u, 0x00u, 0x20u, 0xf0u, 0xbdu, 0xc0u, 0x46u, - 0x18u, 0x04u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x0du, 0x00u, 0x11u, 0x00u, 0x1au, 0x00u, 0x04u, 0x00u, 0xffu, 0xf7u, + 0x28u, 0x04u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x0du, 0x00u, 0x11u, 0x00u, 0x1au, 0x00u, 0x04u, 0x00u, 0xffu, 0xf7u, 0xafu, 0xffu, 0x8cu, 0x23u, 0x04u, 0x9au, 0x5bu, 0x01u, 0xe2u, 0x50u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xc2u, 0xffu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x9bu, 0xffu, 0x04u, 0x4bu, 0x00u, 0x20u, 0x1bu, 0x68u, 0x1bu, 0x6bu, 0xe4u, 0x18u, - 0x23u, 0x68u, 0x2bu, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u, 0x18u, 0x04u, 0x00u, 0x08u, 0x7fu, 0xb5u, 0x0du, 0x00u, + 0x23u, 0x68u, 0x2bu, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u, 0x28u, 0x04u, 0x00u, 0x08u, 0x7fu, 0xb5u, 0x0du, 0x00u, 0x19u, 0x00u, 0x0eu, 0x4bu, 0x16u, 0x00u, 0x03u, 0x93u, 0x09u, 0x9au, 0x08u, 0x9bu, 0x04u, 0x00u, 0x02u, 0xf0u, 0xf1u, 0xfdu, 0x03u, 0xabu, 0x69u, 0x00u, 0x59u, 0x18u, 0x08u, 0x23u, 0x89u, 0x5du, 0x20u, 0x00u, 0x00u, 0x93u, 0x00u, 0x22u, 0x04u, 0x3bu, 0x02u, 0xf0u, 0x4eu, 0xfeu, 0x05u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xe4u, 0x18u, 0x02u, 0x23u, 0x22u, 0x68u, 0x1au, 0x42u, 0xfcu, 0xd1u, 0x7fu, 0xbdu, 0xc0u, 0x46u, 0x70u, 0x71u, 0x72u, 0x73u, - 0x18u, 0x04u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x87u, 0xb0u, 0x05u, 0x93u, 0x20u, 0x4bu, 0x05u, 0x00u, 0x1bu, 0x68u, + 0x28u, 0x04u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x87u, 0xb0u, 0x05u, 0x93u, 0x20u, 0x4bu, 0x05u, 0x00u, 0x1bu, 0x68u, 0x04u, 0x91u, 0x03u, 0x92u, 0x1fu, 0x1eu, 0x02u, 0xd0u, 0x9bu, 0x6bu, 0xc3u, 0x18u, 0x1fu, 0x68u, 0x00u, 0x26u, 0x1bu, 0x4bu, 0xf2u, 0x00u, 0xd2u, 0x18u, 0x03u, 0x99u, 0x08u, 0x23u, 0x28u, 0x00u, 0x02u, 0xf0u, 0x9cu, 0xfeu, 0x44u, 0x1eu, 0xa0u, 0x41u, 0x44u, 0x42u, 0x17u, 0x48u, 0x17u, 0x4bu, 0x04u, 0x40u, 0x01u, 0x36u, 0xe4u, 0x18u, @@ -307,8 +307,8 @@ const uint8_t cy_m0p_image[] = { 0x03u, 0x9au, 0x02u, 0x99u, 0x28u, 0x00u, 0x08u, 0x23u, 0x02u, 0xf0u, 0x4cu, 0xfeu, 0x08u, 0x36u, 0x0cu, 0x9au, 0x39u, 0x00u, 0x28u, 0x00u, 0x08u, 0x23u, 0x02u, 0xf0u, 0x45u, 0xfeu, 0x02u, 0x9bu, 0x04u, 0x9au, 0x28u, 0x00u, 0x01u, 0x97u, 0x00u, 0x96u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xa1u, 0xffu, 0x28u, 0x00u, 0x08u, 0x23u, 0x32u, 0x00u, - 0x05u, 0x99u, 0x02u, 0xf0u, 0x37u, 0xfeu, 0x20u, 0x00u, 0x07u, 0xb0u, 0xf0u, 0xbdu, 0x18u, 0x04u, 0x00u, 0x08u, - 0x48u, 0x72u, 0x00u, 0x10u, 0xfdu, 0xffu, 0xceu, 0xffu, 0x03u, 0x00u, 0x31u, 0x00u, 0xf0u, 0xb5u, 0x89u, 0xb0u, + 0x05u, 0x99u, 0x02u, 0xf0u, 0x37u, 0xfeu, 0x20u, 0x00u, 0x07u, 0xb0u, 0xf0u, 0xbdu, 0x28u, 0x04u, 0x00u, 0x08u, + 0x50u, 0x72u, 0x00u, 0x10u, 0xfdu, 0xffu, 0xceu, 0xffu, 0x03u, 0x00u, 0x31u, 0x00u, 0xf0u, 0xb5u, 0x89u, 0xb0u, 0x07u, 0x93u, 0x25u, 0x4bu, 0x04u, 0x00u, 0x1bu, 0x68u, 0x06u, 0x91u, 0x04u, 0x92u, 0x03u, 0x93u, 0x00u, 0x2bu, 0x03u, 0xd0u, 0x9bu, 0x6bu, 0xc3u, 0x18u, 0x1bu, 0x68u, 0x03u, 0x93u, 0x00u, 0x27u, 0x1fu, 0x4bu, 0x04u, 0x9du, 0xfeu, 0x00u, 0xf6u, 0x18u, 0x2bu, 0x00u, 0x10u, 0x33u, 0x05u, 0x93u, 0x08u, 0x23u, 0x32u, 0x00u, 0x29u, 0x00u, @@ -318,20 +318,20 @@ const uint8_t cy_m0p_image[] = { 0x20u, 0x00u, 0x08u, 0x23u, 0x02u, 0xf0u, 0xf6u, 0xfdu, 0x03u, 0x9fu, 0x03u, 0x9bu, 0x08u, 0x37u, 0x01u, 0x93u, 0x06u, 0x9au, 0x33u, 0x00u, 0x20u, 0x00u, 0x00u, 0x97u, 0x01u, 0x21u, 0xffu, 0xf7u, 0x4fu, 0xffu, 0x20u, 0x00u, 0x08u, 0x23u, 0x3au, 0x00u, 0x07u, 0x99u, 0x02u, 0xf0u, 0xe5u, 0xfdu, 0x28u, 0x00u, 0x09u, 0xb0u, 0xf0u, 0xbdu, - 0x08u, 0x35u, 0xcau, 0xe7u, 0x02u, 0x4du, 0xd4u, 0xe7u, 0x18u, 0x04u, 0x00u, 0x08u, 0x48u, 0x72u, 0x00u, 0x10u, + 0x08u, 0x35u, 0xcau, 0xe7u, 0x02u, 0x4du, 0xd4u, 0xe7u, 0x28u, 0x04u, 0x00u, 0x08u, 0x50u, 0x72u, 0x00u, 0x10u, 0x03u, 0x00u, 0x31u, 0x00u, 0x70u, 0xb5u, 0x0fu, 0x26u, 0x0bu, 0x4bu, 0x1bu, 0x68u, 0x9cu, 0x68u, 0x05u, 0x19u, 0x2cu, 0x68u, 0x34u, 0x40u, 0x04u, 0x2cu, 0xfbu, 0xd8u, 0x86u, 0x25u, 0x6du, 0x01u, 0x44u, 0x59u, 0x00u, 0x2cu, 0xfcu, 0xdbu, 0xdcu, 0x68u, 0x05u, 0x4du, 0x04u, 0x19u, 0x25u, 0x60u, 0xdcu, 0x68u, 0x04u, 0x19u, 0x21u, 0x60u, - 0xdbu, 0x68u, 0xc0u, 0x18u, 0x02u, 0x60u, 0x70u, 0xbdu, 0x18u, 0x04u, 0x00u, 0x08u, 0x08u, 0x00u, 0x00u, 0x71u, + 0xdbu, 0x68u, 0xc0u, 0x18u, 0x02u, 0x60u, 0x70u, 0xbdu, 0x28u, 0x04u, 0x00u, 0x08u, 0x08u, 0x00u, 0x00u, 0x71u, 0x30u, 0xb5u, 0x0fu, 0x25u, 0x06u, 0x4bu, 0x1cu, 0x68u, 0xa3u, 0x68u, 0xc2u, 0x18u, 0x13u, 0x68u, 0x2bu, 0x40u, 0x06u, 0x2bu, 0xfbu, 0xd8u, 0xe3u, 0x68u, 0x09u, 0x06u, 0xc0u, 0x18u, 0x01u, 0x60u, 0x30u, 0xbdu, 0xc0u, 0x46u, - 0x18u, 0x04u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x0fu, 0x27u, 0x09u, 0x4cu, 0x26u, 0x68u, 0xb4u, 0x68u, 0x05u, 0x19u, + 0x28u, 0x04u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x0fu, 0x27u, 0x09u, 0x4cu, 0x26u, 0x68u, 0xb4u, 0x68u, 0x05u, 0x19u, 0x2cu, 0x68u, 0x3cu, 0x40u, 0x06u, 0x2cu, 0xfbu, 0xd8u, 0xf4u, 0x68u, 0x09u, 0x03u, 0x00u, 0x19u, 0x80u, 0x24u, 0xe4u, 0x05u, 0x22u, 0x43u, 0x11u, 0x43u, 0x1bu, 0x04u, 0x19u, 0x43u, 0x01u, 0x60u, 0xf0u, 0xbdu, 0xc0u, 0x46u, - 0x18u, 0x04u, 0x00u, 0x08u, 0x30u, 0xb5u, 0x0fu, 0x25u, 0x09u, 0x4bu, 0x1bu, 0x68u, 0x9au, 0x68u, 0x84u, 0x18u, + 0x28u, 0x04u, 0x00u, 0x08u, 0x30u, 0xb5u, 0x0fu, 0x25u, 0x09u, 0x4bu, 0x1bu, 0x68u, 0x9au, 0x68u, 0x84u, 0x18u, 0x22u, 0x68u, 0x2au, 0x40u, 0x04u, 0x2au, 0xfbu, 0xd8u, 0xdau, 0x68u, 0x06u, 0x4cu, 0x82u, 0x18u, 0x14u, 0x60u, 0xdau, 0x68u, 0x82u, 0x18u, 0x11u, 0x60u, 0xdbu, 0x68u, 0xc0u, 0x18u, 0x08u, 0x23u, 0x03u, 0x60u, 0x30u, 0xbdu, - 0x18u, 0x04u, 0x00u, 0x08u, 0x0cu, 0x00u, 0x00u, 0x70u, 0xf7u, 0xb5u, 0x04u, 0x00u, 0x16u, 0x00u, 0x1fu, 0x00u, + 0x28u, 0x04u, 0x00u, 0x08u, 0x0cu, 0x00u, 0x00u, 0x70u, 0xf7u, 0xb5u, 0x04u, 0x00u, 0x16u, 0x00u, 0x1fu, 0x00u, 0x00u, 0x25u, 0x01u, 0x91u, 0x1cu, 0x4bu, 0xeau, 0x00u, 0xd2u, 0x18u, 0x31u, 0x00u, 0x08u, 0x23u, 0x20u, 0x00u, 0x02u, 0xf0u, 0xb2u, 0xfeu, 0x00u, 0x28u, 0x2cu, 0xd0u, 0x01u, 0x35u, 0x10u, 0x2du, 0xf2u, 0xd1u, 0x00u, 0x25u, 0x31u, 0x00u, 0x20u, 0x00u, 0x08u, 0x22u, 0xffu, 0xf7u, 0x85u, 0xffu, 0x08u, 0x23u, 0x20u, 0x00u, 0x1au, 0x00u, @@ -339,7 +339,7 @@ const uint8_t cy_m0p_image[] = { 0x39u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xbeu, 0xffu, 0x08u, 0x23u, 0x20u, 0x00u, 0x1au, 0x00u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xa0u, 0xffu, 0x01u, 0x99u, 0x20u, 0x00u, 0x4bu, 0x1eu, 0x99u, 0x41u, 0x52u, 0x31u, 0xffu, 0xf7u, 0x87u, 0xffu, 0x20u, 0x00u, 0x08u, 0x23u, 0x01u, 0x22u, 0x0cu, 0x21u, 0xffu, 0xf7u, 0x93u, 0xffu, 0x28u, 0x00u, - 0xfeu, 0xbdu, 0x02u, 0x4du, 0xd4u, 0xe7u, 0xc0u, 0x46u, 0xc8u, 0x72u, 0x00u, 0x10u, 0x03u, 0x00u, 0x31u, 0x00u, + 0xfeu, 0xbdu, 0x02u, 0x4du, 0xd4u, 0xe7u, 0xc0u, 0x46u, 0xd0u, 0x72u, 0x00u, 0x10u, 0x03u, 0x00u, 0x31u, 0x00u, 0xf0u, 0xb5u, 0x04u, 0x00u, 0x00u, 0x27u, 0x85u, 0xb0u, 0x02u, 0x91u, 0x00u, 0x92u, 0x03u, 0x93u, 0x26u, 0x4bu, 0x00u, 0x9du, 0xfeu, 0x00u, 0xf6u, 0x18u, 0x2bu, 0x00u, 0x10u, 0x33u, 0x01u, 0x93u, 0x08u, 0x23u, 0x32u, 0x00u, 0x29u, 0x00u, 0x20u, 0x00u, 0x02u, 0xf0u, 0x68u, 0xfeu, 0x00u, 0x28u, 0x04u, 0xd0u, 0x01u, 0x9bu, 0x9du, 0x42u, @@ -350,15 +350,15 @@ const uint8_t cy_m0p_image[] = { 0x20u, 0x00u, 0xffu, 0xf7u, 0x67u, 0xffu, 0x08u, 0x23u, 0x20u, 0x00u, 0x1au, 0x00u, 0x00u, 0x21u, 0xffu, 0xf7u, 0x49u, 0xffu, 0x02u, 0x99u, 0x20u, 0x00u, 0x4bu, 0x1eu, 0x99u, 0x41u, 0x54u, 0x31u, 0xffu, 0xf7u, 0x30u, 0xffu, 0x20u, 0x00u, 0x08u, 0x23u, 0x01u, 0x22u, 0x0cu, 0x21u, 0xffu, 0xf7u, 0x3cu, 0xffu, 0x28u, 0x00u, 0x05u, 0xb0u, - 0xf0u, 0xbdu, 0x08u, 0x35u, 0xbau, 0xe7u, 0xc0u, 0x46u, 0xc8u, 0x72u, 0x00u, 0x10u, 0x03u, 0x00u, 0x31u, 0x00u, + 0xf0u, 0xbdu, 0x08u, 0x35u, 0xbau, 0xe7u, 0xc0u, 0x46u, 0xd0u, 0x72u, 0x00u, 0x10u, 0x03u, 0x00u, 0x31u, 0x00u, 0x42u, 0x1eu, 0x03u, 0x00u, 0x00u, 0x20u, 0x04u, 0x2au, 0x03u, 0xd8u, 0x28u, 0x30u, 0x58u, 0x43u, 0x01u, 0x4bu, - 0xc0u, 0x18u, 0x70u, 0x47u, 0x48u, 0x73u, 0x00u, 0x10u, 0x09u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xc0u, 0x18u, + 0xc0u, 0x18u, 0x70u, 0x47u, 0x50u, 0x73u, 0x00u, 0x10u, 0x09u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xc0u, 0x18u, 0x08u, 0x4bu, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x04u, 0xd8u, 0x80u, 0x23u, 0x02u, 0x68u, 0x1au, 0x42u, 0xfcu, 0xd1u, 0x70u, 0x47u, 0x03u, 0x68u, 0x00u, 0x2bu, 0xfcu, 0xd1u, 0xfau, 0xe7u, 0xc0u, 0x46u, - 0x18u, 0x04u, 0x00u, 0x08u, 0x28u, 0x06u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x0bu, 0x00u, 0x13u, 0x22u, 0x00u, 0x21u, + 0x28u, 0x04u, 0x00u, 0x08u, 0x38u, 0x06u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x0bu, 0x00u, 0x13u, 0x22u, 0x00u, 0x21u, 0x02u, 0xf0u, 0xf2u, 0xf9u, 0x10u, 0xbdu, 0x00u, 0x00u, 0x10u, 0xb5u, 0x13u, 0x00u, 0x07u, 0x4au, 0x12u, 0x68u, 0x29u, 0x32u, 0x14u, 0x78u, 0x0cu, 0x22u, 0x1fu, 0x2cu, 0x00u, 0xd9u, 0x04u, 0x32u, 0x91u, 0x40u, 0x01u, 0x3bu, - 0x0bu, 0x43u, 0x12u, 0x22u, 0x00u, 0x21u, 0x02u, 0xf0u, 0xdfu, 0xf9u, 0x10u, 0xbdu, 0x28u, 0x06u, 0x00u, 0x08u, + 0x0bu, 0x43u, 0x12u, 0x22u, 0x00u, 0x21u, 0x02u, 0xf0u, 0xdfu, 0xf9u, 0x10u, 0xbdu, 0x38u, 0x06u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0xadu, 0xb0u, 0x04u, 0x00u, 0x04u, 0x91u, 0x05u, 0x92u, 0x03u, 0x93u, 0x00u, 0x29u, 0x00u, 0xd1u, 0x15u, 0xe1u, 0x03u, 0x9bu, 0x00u, 0x2bu, 0x00u, 0xd1u, 0x11u, 0xe1u, 0x32u, 0x9bu, 0x00u, 0x2bu, 0x00u, 0xd1u, 0x0du, 0xe1u, 0x33u, 0x9bu, 0x00u, 0x2bu, 0x00u, 0xd1u, 0x09u, 0xe1u, 0x32u, 0x9bu, 0x58u, 0x78u, 0xffu, 0xf7u, @@ -396,7 +396,7 @@ const uint8_t cy_m0p_image[] = { 0x00u, 0x28u, 0x00u, 0xd0u, 0x71u, 0xe7u, 0x03u, 0x9bu, 0xe9u, 0x1du, 0xc9u, 0x08u, 0x59u, 0x18u, 0x0au, 0x22u, 0x2bu, 0x00u, 0x20u, 0x00u, 0x04u, 0xf0u, 0xc4u, 0xf8u, 0x68u, 0xe7u, 0x08u, 0x4eu, 0x6bu, 0xe7u, 0x07u, 0x4eu, 0x6eu, 0xe7u, 0x07u, 0x4eu, 0x6cu, 0xe7u, 0xc0u, 0x46u, 0x09u, 0x80u, 0x00u, 0x00u, 0x01u, 0x00u, 0x32u, 0x00u, - 0x28u, 0x06u, 0x00u, 0x08u, 0xb0u, 0xb0u, 0x00u, 0x00u, 0x0bu, 0x80u, 0x00u, 0x00u, 0x0bu, 0x00u, 0x32u, 0x00u, + 0x38u, 0x06u, 0x00u, 0x08u, 0xb0u, 0xb0u, 0x00u, 0x00u, 0x0bu, 0x80u, 0x00u, 0x00u, 0x0bu, 0x00u, 0x32u, 0x00u, 0x0au, 0x00u, 0x32u, 0x00u, 0xf0u, 0xb5u, 0x87u, 0xb0u, 0x04u, 0x00u, 0x0fu, 0x1eu, 0x04u, 0x92u, 0x03u, 0x93u, 0x00u, 0xd1u, 0x8bu, 0xe1u, 0x00u, 0x2au, 0x00u, 0xd1u, 0x88u, 0xe1u, 0x0cu, 0x9bu, 0x00u, 0x2bu, 0x00u, 0xd1u, 0x84u, 0xe1u, 0x0du, 0x9bu, 0x00u, 0x2bu, 0x00u, 0xd1u, 0x80u, 0xe1u, 0x58u, 0x78u, 0xffu, 0xf7u, 0x78u, 0xfeu, @@ -448,11 +448,11 @@ const uint8_t cy_m0p_image[] = { 0x05u, 0x21u, 0x20u, 0x00u, 0x03u, 0xf0u, 0x7au, 0xffu, 0x00u, 0x28u, 0x09u, 0xd0u, 0x01u, 0x23u, 0x0cu, 0x9au, 0x13u, 0x70u, 0x0eu, 0x49u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x27u, 0xfdu, 0x38u, 0x00u, 0x07u, 0xb0u, 0xf0u, 0xbdu, 0x0cu, 0x9bu, 0x18u, 0x70u, 0xf5u, 0xe7u, 0x04u, 0x4fu, 0x09u, 0x49u, 0xf3u, 0xe7u, 0x02u, 0x4fu, 0xf4u, 0xe7u, - 0x08u, 0x4fu, 0xf2u, 0xe7u, 0xf5u, 0xffu, 0xcdu, 0xffu, 0x0bu, 0x00u, 0x32u, 0x00u, 0x28u, 0x06u, 0x00u, 0x08u, + 0x08u, 0x4fu, 0xf2u, 0xe7u, 0xf5u, 0xffu, 0xcdu, 0xffu, 0x0bu, 0x00u, 0x32u, 0x00u, 0x38u, 0x06u, 0x00u, 0x08u, 0x80u, 0x80u, 0x00u, 0x00u, 0x08u, 0x60u, 0x00u, 0x00u, 0x06u, 0x80u, 0x00u, 0x00u, 0xf1u, 0x7eu, 0x00u, 0x00u, 0x30u, 0x60u, 0x00u, 0x00u, 0x0au, 0x00u, 0x32u, 0x00u, 0x10u, 0xb5u, 0x13u, 0x00u, 0x07u, 0x4au, 0x12u, 0x68u, 0x29u, 0x32u, 0x14u, 0x78u, 0x0cu, 0x22u, 0x1fu, 0x2cu, 0x00u, 0xd9u, 0x04u, 0x32u, 0x91u, 0x40u, 0x01u, 0x3bu, - 0x0bu, 0x43u, 0x12u, 0x22u, 0x00u, 0x21u, 0x01u, 0xf0u, 0xefu, 0xfeu, 0x10u, 0xbdu, 0x28u, 0x06u, 0x00u, 0x08u, + 0x0bu, 0x43u, 0x12u, 0x22u, 0x00u, 0x21u, 0x01u, 0xf0u, 0xefu, 0xfeu, 0x10u, 0xbdu, 0x38u, 0x06u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x04u, 0x00u, 0x85u, 0xb0u, 0x08u, 0x00u, 0x02u, 0x91u, 0x03u, 0x92u, 0x1eu, 0x00u, 0xffu, 0xf7u, 0xc7u, 0xfcu, 0x07u, 0x1eu, 0x00u, 0xd1u, 0x7bu, 0xe0u, 0x03u, 0x9bu, 0x00u, 0x2bu, 0x00u, 0xd1u, 0x77u, 0xe0u, 0x00u, 0x2eu, 0x00u, 0xd1u, 0x74u, 0xe0u, 0x73u, 0x68u, 0x00u, 0x2bu, 0x00u, 0xd1u, 0x70u, 0xe0u, 0xb3u, 0x68u, @@ -476,25 +476,25 @@ const uint8_t cy_m0p_image[] = { 0x12u, 0x01u, 0x13u, 0x43u, 0x09u, 0x03u, 0x0bu, 0x43u, 0x36u, 0x22u, 0x00u, 0x21u, 0x01u, 0xf0u, 0x44u, 0xfeu, 0x10u, 0xbdu, 0x00u, 0x00u, 0x09u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xc0u, 0x18u, 0x08u, 0x4bu, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x04u, 0xd8u, 0x80u, 0x23u, 0x02u, 0x68u, 0x1au, 0x42u, 0xfcu, 0xd1u, - 0x70u, 0x47u, 0x03u, 0x68u, 0x00u, 0x2bu, 0xfcu, 0xd1u, 0xfau, 0xe7u, 0xc0u, 0x46u, 0x18u, 0x04u, 0x00u, 0x08u, - 0x28u, 0x06u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, 0xffu, 0xf7u, 0xe4u, 0xffu, 0x02u, 0x4bu, 0x1bu, 0x68u, - 0xdbu, 0x6bu, 0xe4u, 0x18u, 0x20u, 0x68u, 0x10u, 0xbdu, 0x18u, 0x04u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x0au, 0x4bu, + 0x70u, 0x47u, 0x03u, 0x68u, 0x00u, 0x2bu, 0xfcu, 0xd1u, 0xfau, 0xe7u, 0xc0u, 0x46u, 0x28u, 0x04u, 0x00u, 0x08u, + 0x38u, 0x06u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, 0xffu, 0xf7u, 0xe4u, 0xffu, 0x02u, 0x4bu, 0x1bu, 0x68u, + 0xdbu, 0x6bu, 0xe4u, 0x18u, 0x20u, 0x68u, 0x10u, 0xbdu, 0x28u, 0x04u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x0au, 0x4bu, 0x09u, 0x03u, 0x1bu, 0x68u, 0x12u, 0x01u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x06u, 0xd8u, 0x13u, 0x00u, 0x25u, 0x22u, 0x0bu, 0x43u, 0x00u, 0x21u, 0x01u, 0xf0u, 0x0fu, 0xfeu, 0x10u, 0xbdu, 0x0fu, 0x23u, 0x13u, 0x43u, - 0x0bu, 0x43u, 0x24u, 0x22u, 0xf6u, 0xe7u, 0xc0u, 0x46u, 0x28u, 0x06u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x07u, 0x4bu, + 0x0bu, 0x43u, 0x24u, 0x22u, 0xf6u, 0xe7u, 0xc0u, 0x46u, 0x38u, 0x06u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x07u, 0x4bu, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x05u, 0xd8u, 0x05u, 0x4bu, 0x21u, 0x22u, 0x00u, 0x21u, - 0x01u, 0xf0u, 0xfau, 0xfdu, 0x10u, 0xbdu, 0x03u, 0x4bu, 0xf8u, 0xe7u, 0xc0u, 0x46u, 0x28u, 0x06u, 0x00u, 0x08u, + 0x01u, 0xf0u, 0xfau, 0xfdu, 0x10u, 0xbdu, 0x03u, 0x4bu, 0xf8u, 0xe7u, 0xc0u, 0x46u, 0x38u, 0x06u, 0x00u, 0x08u, 0xc0u, 0xc0u, 0x00u, 0x00u, 0xcfu, 0xc0u, 0x00u, 0x00u, 0x00u, 0x23u, 0x10u, 0xb5u, 0x10u, 0x22u, 0x19u, 0x00u, 0x01u, 0xf0u, 0xeau, 0xfdu, 0x10u, 0xbdu, 0x09u, 0x03u, 0x0bu, 0x00u, 0x13u, 0x43u, 0x00u, 0x22u, 0x10u, 0xb5u, 0x11u, 0x00u, 0x01u, 0xf0u, 0xe1u, 0xfdu, 0x10u, 0xbdu, 0x10u, 0xb5u, 0x13u, 0x00u, 0x07u, 0x4au, 0x12u, 0x68u, 0x29u, 0x32u, 0x14u, 0x78u, 0x0cu, 0x22u, 0x1fu, 0x2cu, 0x00u, 0xd9u, 0x04u, 0x32u, 0x91u, 0x40u, 0x01u, 0x3bu, - 0x0bu, 0x43u, 0x12u, 0x22u, 0x00u, 0x21u, 0x01u, 0xf0u, 0xcfu, 0xfdu, 0x10u, 0xbdu, 0x28u, 0x06u, 0x00u, 0x08u, + 0x0bu, 0x43u, 0x12u, 0x22u, 0x00u, 0x21u, 0x01u, 0xf0u, 0xcfu, 0xfdu, 0x10u, 0xbdu, 0x38u, 0x06u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x1fu, 0x24u, 0x08u, 0x4bu, 0x89u, 0x06u, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x9cu, 0x42u, 0xa4u, 0x41u, 0x13u, 0x00u, 0x64u, 0x42u, 0x0cu, 0x34u, 0xa3u, 0x40u, 0x80u, 0x22u, 0x0bu, 0x43u, 0x00u, 0x21u, - 0x01u, 0xf0u, 0xbau, 0xfdu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0x28u, 0x06u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x14u, 0x00u, + 0x01u, 0xf0u, 0xbau, 0xfdu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0x38u, 0x06u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x14u, 0x00u, 0x07u, 0x4au, 0x15u, 0x68u, 0x24u, 0x22u, 0x29u, 0x35u, 0x2du, 0x78u, 0x1fu, 0x2du, 0x00u, 0xd9u, 0x01u, 0x3au, 0x24u, 0x01u, 0x23u, 0x43u, 0x09u, 0x03u, 0x0bu, 0x43u, 0x00u, 0x21u, 0x01u, 0xf0u, 0xa5u, 0xfdu, 0x70u, 0xbdu, - 0x28u, 0x06u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x0bu, 0x00u, 0x13u, 0x22u, 0x00u, 0x21u, 0x01u, 0xf0u, 0x9cu, 0xfdu, + 0x38u, 0x06u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x0bu, 0x00u, 0x13u, 0x22u, 0x00u, 0x21u, 0x01u, 0xf0u, 0x9cu, 0xfdu, 0x10u, 0xbdu, 0x00u, 0x23u, 0x10u, 0xb5u, 0x11u, 0x22u, 0x19u, 0x00u, 0x01u, 0xf0u, 0x95u, 0xfdu, 0x10u, 0xbdu, 0x70u, 0xb5u, 0x04u, 0x00u, 0x1bu, 0x4du, 0xffu, 0xf7u, 0x9fu, 0xffu, 0x20u, 0x00u, 0x01u, 0x22u, 0x02u, 0x21u, 0xffu, 0xf7u, 0xa1u, 0xffu, 0x20u, 0x00u, 0x00u, 0x22u, 0x03u, 0x21u, 0xffu, 0xf7u, 0x9cu, 0xffu, 0x2au, 0x00u, @@ -527,7 +527,7 @@ const uint8_t cy_m0p_image[] = { 0xffu, 0xf7u, 0x70u, 0xfeu, 0x94u, 0x4bu, 0x1bu, 0x78u, 0x00u, 0x2bu, 0x0bu, 0xd0u, 0x01u, 0x2bu, 0x01u, 0xd1u, 0x00u, 0xf0u, 0x35u, 0xfdu, 0x0eu, 0x9bu, 0x00u, 0x22u, 0x01u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x50u, 0xffu, 0x00u, 0xf0u, 0x24u, 0xfdu, 0x8du, 0x4bu, 0x18u, 0x78u, 0x01u, 0x38u, 0x04u, 0x28u, 0x01u, 0xd9u, 0x00u, 0xf0u, - 0x1du, 0xfdu, 0x04u, 0xf0u, 0x8fu, 0xffu, 0x05u, 0x00u, 0x89u, 0x00u, 0x25u, 0x01u, 0x73u, 0x03u, 0x18u, 0x05u, + 0x1du, 0xfdu, 0x04u, 0xf0u, 0x93u, 0xffu, 0x05u, 0x00u, 0x89u, 0x00u, 0x25u, 0x01u, 0x73u, 0x03u, 0x18u, 0x05u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa1u, 0xfeu, 0x01u, 0x22u, 0x04u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa3u, 0xfeu, 0x00u, 0x22u, 0x05u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x9eu, 0xfeu, 0x80u, 0x22u, 0x02u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa2u, 0xfeu, 0xc0u, 0x22u, 0x03u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x9du, 0xfeu, 0xc0u, 0x22u, @@ -561,7 +561,7 @@ const uint8_t cy_m0p_image[] = { 0x43u, 0xfdu, 0x16u, 0x4bu, 0x36u, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0x01u, 0xf0u, 0x9du, 0xfbu, 0x03u, 0x23u, 0x02u, 0x22u, 0x04u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x4au, 0xfdu, 0x09u, 0x4bu, 0x3du, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0x01u, 0xf0u, 0x91u, 0xfbu, 0x00u, 0x21u, 0x06u, 0x4bu, 0x37u, 0x22u, 0x20u, 0x00u, 0x01u, 0xf0u, - 0x8bu, 0xfbu, 0x0eu, 0x21u, 0x70u, 0xe7u, 0xc0u, 0x46u, 0xc0u, 0x00u, 0x00u, 0x08u, 0x14u, 0x04u, 0x00u, 0x08u, + 0x8bu, 0xfbu, 0x0eu, 0x21u, 0x70u, 0xe7u, 0xc0u, 0x46u, 0xc0u, 0x00u, 0x00u, 0x08u, 0x24u, 0x04u, 0x00u, 0x08u, 0x4eu, 0x00u, 0x40u, 0x00u, 0x4eu, 0x40u, 0x30u, 0x00u, 0x20u, 0x30u, 0x00u, 0x00u, 0x23u, 0x20u, 0x00u, 0x00u, 0x10u, 0x20u, 0x00u, 0x00u, 0x2eu, 0x00u, 0x40u, 0x00u, 0x2eu, 0x20u, 0x30u, 0x00u, 0x2eu, 0x20u, 0x40u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x81u, 0xfdu, 0x01u, 0x22u, 0x0au, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x83u, 0xfdu, @@ -692,7 +692,7 @@ const uint8_t cy_m0p_image[] = { 0x8bu, 0xffu, 0x00u, 0x21u, 0x44u, 0x4bu, 0x37u, 0x22u, 0x20u, 0x00u, 0x00u, 0xf0u, 0x85u, 0xffu, 0xe0u, 0x21u, 0x49u, 0x00u, 0xffu, 0xf7u, 0x69u, 0xfbu, 0x20u, 0x00u, 0xffu, 0xf7u, 0xeau, 0xf9u, 0x01u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xd8u, 0xf9u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xdcu, 0xf9u, 0x09u, 0xb0u, 0xf0u, 0xbdu, 0x42u, 0x4bu, - 0x18u, 0x78u, 0x01u, 0x38u, 0x04u, 0x28u, 0xf1u, 0xd8u, 0x04u, 0xf0u, 0x5au, 0xfau, 0x05u, 0x00u, 0x84u, 0x00u, + 0x18u, 0x78u, 0x01u, 0x38u, 0x04u, 0x28u, 0xf1u, 0xd8u, 0x04u, 0xf0u, 0x5eu, 0xfau, 0x05u, 0x00u, 0x84u, 0x00u, 0xd1u, 0x00u, 0xc7u, 0x01u, 0xedu, 0xffu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x76u, 0xf9u, 0x01u, 0x22u, 0x04u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x78u, 0xf9u, 0x00u, 0x22u, 0x05u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x73u, 0xf9u, 0x02u, 0x22u, 0x00u, 0x21u, 0xffu, 0x32u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x76u, 0xf9u, 0x80u, 0x22u, 0x01u, 0x21u, @@ -708,7 +708,7 @@ const uint8_t cy_m0p_image[] = { 0x0bu, 0xffu, 0x00u, 0x21u, 0x0eu, 0x4bu, 0x37u, 0x22u, 0x20u, 0x00u, 0x00u, 0xf0u, 0x05u, 0xffu, 0x03u, 0x21u, 0xffu, 0xf7u, 0xeau, 0xfau, 0x9eu, 0x00u, 0x40u, 0x00u, 0x9eu, 0x90u, 0x30u, 0x00u, 0x82u, 0x70u, 0x00u, 0x00u, 0x73u, 0x70u, 0x00u, 0x00u, 0x9eu, 0x90u, 0x40u, 0x00u, 0x72u, 0x70u, 0x00u, 0x00u, 0x70u, 0x70u, 0x00u, 0x00u, - 0x71u, 0x70u, 0x00u, 0x00u, 0x60u, 0x70u, 0x00u, 0x00u, 0x14u, 0x04u, 0x00u, 0x08u, 0x12u, 0x10u, 0x00u, 0x00u, + 0x71u, 0x70u, 0x00u, 0x00u, 0x60u, 0x70u, 0x00u, 0x00u, 0x24u, 0x04u, 0x00u, 0x08u, 0x12u, 0x10u, 0x00u, 0x00u, 0x4eu, 0x40u, 0x30u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xf7u, 0xf8u, 0x20u, 0x00u, 0x01u, 0x22u, 0x04u, 0x21u, 0xffu, 0xf7u, 0xf9u, 0xf8u, 0x20u, 0x00u, 0x00u, 0x22u, 0x05u, 0x21u, 0xffu, 0xf7u, 0xf4u, 0xf8u, 0x42u, 0x22u, 0x20u, 0x00u, 0xffu, 0x32u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xf7u, 0xf8u, 0xa0u, 0x22u, 0x20u, 0x00u, 0x52u, 0x00u, @@ -719,7 +719,7 @@ const uint8_t cy_m0p_image[] = { 0x20u, 0x22u, 0x00u, 0x21u, 0x00u, 0xf0u, 0xb0u, 0xfeu, 0x00u, 0x22u, 0x20u, 0x00u, 0x11u, 0x00u, 0x01u, 0x23u, 0xffu, 0xf7u, 0x5du, 0xf8u, 0x20u, 0x00u, 0x03u, 0x23u, 0x00u, 0x22u, 0x01u, 0x21u, 0xffu, 0xf7u, 0xeeu, 0xf8u, 0x01u, 0x23u, 0x00u, 0x22u, 0x04u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x3eu, 0xf8u, 0x7fu, 0xe7u, 0x1cu, 0x22u, - 0xb3u, 0x49u, 0x01u, 0xa8u, 0x04u, 0xf0u, 0x5au, 0xfbu, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa5u, 0xf8u, 0x01u, 0x22u, + 0xb3u, 0x49u, 0x01u, 0xa8u, 0x04u, 0xf0u, 0x5eu, 0xfbu, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa5u, 0xf8u, 0x01u, 0x22u, 0x03u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa7u, 0xf8u, 0x00u, 0x22u, 0x04u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa2u, 0xf8u, 0xe0u, 0x22u, 0x05u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa6u, 0xf8u, 0xf0u, 0x22u, 0x00u, 0x21u, 0x52u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa0u, 0xf8u, 0x80u, 0x22u, 0x01u, 0x21u, 0x52u, 0x00u, 0x20u, 0x00u, @@ -750,7 +750,7 @@ const uint8_t cy_m0p_image[] = { 0x03u, 0x23u, 0x00u, 0x22u, 0x19u, 0x00u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0x69u, 0xffu, 0x3eu, 0x23u, 0x3du, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0x00u, 0xf0u, 0xb0u, 0xfdu, 0x00u, 0x21u, 0x3eu, 0x4bu, 0x37u, 0x22u, 0x20u, 0x00u, 0x00u, 0xf0u, 0xaau, 0xfdu, 0x23u, 0x21u, 0xffu, 0xf7u, 0x8fu, 0xf9u, 0x39u, 0x49u, 0x11u, 0x22u, 0x1cu, 0x31u, - 0x01u, 0xa8u, 0x04u, 0xf0u, 0x63u, 0xfau, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xaeu, 0xffu, 0x01u, 0x22u, 0x04u, 0x21u, + 0x01u, 0xa8u, 0x04u, 0xf0u, 0x67u, 0xfau, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xaeu, 0xffu, 0x01u, 0x22u, 0x04u, 0x21u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xb0u, 0xffu, 0x00u, 0x22u, 0x05u, 0x21u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xabu, 0xffu, 0x31u, 0x4au, 0x00u, 0x21u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xafu, 0xffu, 0xf0u, 0x22u, 0x01u, 0x21u, 0x52u, 0x00u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xa9u, 0xffu, 0x81u, 0x22u, 0x06u, 0x21u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xa4u, 0xffu, @@ -764,7 +764,7 @@ const uint8_t cy_m0p_image[] = { 0x4bu, 0xfdu, 0x04u, 0x23u, 0x00u, 0x22u, 0x19u, 0x00u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xf8u, 0xfeu, 0x4eu, 0x23u, 0x3du, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0x00u, 0xf0u, 0x3fu, 0xfdu, 0x00u, 0x21u, 0x07u, 0x4bu, 0x37u, 0x22u, 0x20u, 0x00u, 0x00u, 0xf0u, 0x39u, 0xfdu, 0x43u, 0x21u, 0xffu, 0xf7u, 0x1eu, 0xf9u, 0x12u, 0x10u, 0x00u, 0x00u, - 0x3du, 0x79u, 0x00u, 0x10u, 0x3eu, 0x30u, 0x30u, 0x00u, 0x01u, 0x02u, 0x00u, 0x00u, 0x4eu, 0x40u, 0x30u, 0x00u, + 0x45u, 0x79u, 0x00u, 0x10u, 0x3eu, 0x30u, 0x30u, 0x00u, 0x01u, 0x02u, 0x00u, 0x00u, 0x4eu, 0x40u, 0x30u, 0x00u, 0x70u, 0xb5u, 0x0cu, 0x00u, 0x05u, 0x00u, 0xfeu, 0xf7u, 0xdau, 0xfeu, 0x09u, 0x4bu, 0x26u, 0x01u, 0x33u, 0x43u, 0x28u, 0x00u, 0x3du, 0x22u, 0x00u, 0x21u, 0x00u, 0xf0u, 0x1fu, 0xfdu, 0x24u, 0x03u, 0x05u, 0x4bu, 0x34u, 0x43u, 0x28u, 0x00u, 0x23u, 0x43u, 0x37u, 0x22u, 0x00u, 0x21u, 0x00u, 0xf0u, 0x16u, 0xfdu, 0x70u, 0xbdu, 0xc0u, 0x46u, @@ -776,7 +776,7 @@ const uint8_t cy_m0p_image[] = { 0xebu, 0xfcu, 0x0bu, 0x4bu, 0x2du, 0x03u, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x07u, 0xd8u, 0x2bu, 0x00u, 0x26u, 0x22u, 0x3bu, 0x43u, 0x30u, 0x00u, 0x00u, 0x21u, 0x00u, 0xf0u, 0xddu, 0xfcu, 0xf8u, 0xbdu, 0x0fu, 0x23u, 0x2bu, 0x43u, 0x3bu, 0x43u, 0x25u, 0x22u, 0xf5u, 0xe7u, 0xc0u, 0x46u, 0x0eu, 0x00u, 0x80u, 0x00u, - 0x28u, 0x06u, 0x00u, 0x08u, 0x07u, 0xb5u, 0x00u, 0x93u, 0x13u, 0x00u, 0xfeu, 0xf7u, 0xf5u, 0xffu, 0x07u, 0xbdu, + 0x38u, 0x06u, 0x00u, 0x08u, 0x07u, 0xb5u, 0x00u, 0x93u, 0x13u, 0x00u, 0xfeu, 0xf7u, 0xf5u, 0xffu, 0x07u, 0xbdu, 0xf8u, 0xb5u, 0x04u, 0x00u, 0x17u, 0x00u, 0x1eu, 0x00u, 0x0du, 0x00u, 0xfeu, 0xf7u, 0xd5u, 0xfeu, 0x3au, 0x00u, 0x07u, 0x21u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xd7u, 0xfeu, 0x32u, 0x00u, 0x08u, 0x21u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xd2u, 0xfeu, 0x2au, 0x00u, 0x0bu, 0x21u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xcdu, 0xfeu, 0x06u, 0x9au, 0x09u, 0x21u, @@ -871,16 +871,16 @@ const uint8_t cy_m0p_image[] = { 0x05u, 0x90u, 0x08u, 0x22u, 0x00u, 0x97u, 0x07u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xd0u, 0xfeu, 0x01u, 0x22u, 0x05u, 0x9bu, 0x13u, 0x42u, 0x0au, 0xd0u, 0x0bu, 0x23u, 0x01u, 0x93u, 0x01u, 0x3bu, 0x00u, 0x93u, 0x02u, 0x97u, 0x01u, 0x3bu, 0x07u, 0x32u, 0x07u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x0eu, 0xfeu, 0x01u, 0x35u, 0xcdu, 0xe7u, - 0x28u, 0x06u, 0x00u, 0x08u, 0xc5u, 0x60u, 0x00u, 0x00u, 0xc6u, 0xc0u, 0x00u, 0x00u, 0x18u, 0x04u, 0x00u, 0x08u, + 0x38u, 0x06u, 0x00u, 0x08u, 0xc5u, 0x60u, 0x00u, 0x00u, 0xc6u, 0xc0u, 0x00u, 0x00u, 0x28u, 0x04u, 0x00u, 0x08u, 0x80u, 0x22u, 0x0du, 0x4bu, 0x52u, 0x00u, 0x90u, 0x42u, 0x11u, 0xd0u, 0x07u, 0xd8u, 0x01u, 0x22u, 0xc0u, 0x28u, 0x0eu, 0xd0u, 0x02u, 0x22u, 0xe0u, 0x28u, 0x0bu, 0xd0u, 0x00u, 0x22u, 0x09u, 0xe0u, 0xc0u, 0x22u, 0x52u, 0x00u, 0x90u, 0x42u, 0x07u, 0xd0u, 0x05u, 0x4au, 0x90u, 0x42u, 0xf6u, 0xd1u, 0x05u, 0x22u, 0x00u, 0xe0u, 0x03u, 0x22u, - 0x1au, 0x70u, 0x70u, 0x47u, 0x04u, 0x22u, 0xfbu, 0xe7u, 0x14u, 0x04u, 0x00u, 0x08u, 0x09u, 0x02u, 0x00u, 0x00u, + 0x1au, 0x70u, 0x70u, 0x47u, 0x04u, 0x22u, 0xfbu, 0xe7u, 0x24u, 0x04u, 0x00u, 0x08u, 0x09u, 0x02u, 0x00u, 0x00u, 0x01u, 0x4bu, 0x18u, 0x70u, 0x70u, 0x47u, 0xc0u, 0x46u, 0xc0u, 0x00u, 0x00u, 0x08u, 0x13u, 0xb5u, 0x04u, 0x00u, 0x05u, 0x98u, 0x00u, 0x90u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x2fu, 0xffu, 0x20u, 0x00u, 0xfeu, 0xf7u, 0x62u, 0xfbu, 0x13u, 0xbdu, 0x00u, 0x00u, 0xf0u, 0xb5u, 0x93u, 0xb0u, 0x05u, 0x93u, 0x1au, 0xabu, 0x1cu, 0x78u, 0x65u, 0x4bu, 0x05u, 0x00u, 0x1bu, 0x68u, 0x03u, 0x91u, 0x04u, 0x92u, 0x1eu, 0x1eu, 0x02u, 0xd0u, 0x9bu, 0x6bu, 0xc3u, 0x18u, - 0x1eu, 0x68u, 0x30u, 0x22u, 0x00u, 0x21u, 0x06u, 0xa8u, 0x03u, 0xf0u, 0x59u, 0xfeu, 0x33u, 0x00u, 0x81u, 0x33u, + 0x1eu, 0x68u, 0x30u, 0x22u, 0x00u, 0x21u, 0x06u, 0xa8u, 0x03u, 0xf0u, 0x5du, 0xfeu, 0x33u, 0x00u, 0x81u, 0x33u, 0x22u, 0x00u, 0xffu, 0x33u, 0x06u, 0xa9u, 0x28u, 0x00u, 0x01u, 0xf0u, 0xfcu, 0xfbu, 0x04u, 0x1eu, 0x00u, 0xd0u, 0x86u, 0xe0u, 0x33u, 0x00u, 0x80u, 0x33u, 0x01u, 0x93u, 0x98u, 0x23u, 0x01u, 0x9au, 0xdbu, 0x00u, 0x77u, 0x1cu, 0xf6u, 0x50u, 0xffu, 0x37u, 0xf3u, 0x18u, 0x5au, 0x60u, 0x9fu, 0x60u, 0x19u, 0x9au, 0x09u, 0x9bu, 0x9au, 0x42u, @@ -904,10 +904,10 @@ const uint8_t cy_m0p_image[] = { 0x28u, 0x00u, 0x00u, 0xf0u, 0xa7u, 0xfbu, 0x02u, 0x9au, 0x09u, 0x9bu, 0x9bu, 0x1au, 0x19u, 0x9au, 0x9bu, 0xb2u, 0xb9u, 0x18u, 0x89u, 0xe7u, 0x02u, 0x9bu, 0x18u, 0x9au, 0x39u, 0x00u, 0x28u, 0x00u, 0x00u, 0xf0u, 0x9au, 0xfbu, 0x86u, 0xe7u, 0xfau, 0x5cu, 0x01u, 0x9cu, 0x4au, 0x40u, 0xf2u, 0x54u, 0xfau, 0x5cu, 0x42u, 0x40u, 0xe2u, 0x54u, - 0x01u, 0x33u, 0x80u, 0xe7u, 0x18u, 0x04u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x66u, 0x4cu, 0x05u, 0x00u, 0xa5u, 0x44u, + 0x01u, 0x33u, 0x80u, 0xe7u, 0x28u, 0x04u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x66u, 0x4cu, 0x05u, 0x00u, 0xa5u, 0x44u, 0x04u, 0x92u, 0x93u, 0x22u, 0x05u, 0x93u, 0x13u, 0xaeu, 0xaeu, 0xabu, 0x1cu, 0x78u, 0x03u, 0x91u, 0x92u, 0x00u, - 0x00u, 0x21u, 0x30u, 0x00u, 0x03u, 0xf0u, 0x8bu, 0xfdu, 0x30u, 0x22u, 0x00u, 0x21u, 0x07u, 0xa8u, 0x03u, 0xf0u, - 0x86u, 0xfdu, 0x22u, 0x00u, 0x73u, 0xabu, 0x07u, 0xa9u, 0x28u, 0x00u, 0x01u, 0xf0u, 0x77u, 0xfdu, 0x04u, 0x1eu, + 0x00u, 0x21u, 0x30u, 0x00u, 0x03u, 0xf0u, 0x8fu, 0xfdu, 0x30u, 0x22u, 0x00u, 0x21u, 0x07u, 0xa8u, 0x03u, 0xf0u, + 0x8au, 0xfdu, 0x22u, 0x00u, 0x73u, 0xabu, 0x07u, 0xa9u, 0x28u, 0x00u, 0x01u, 0xf0u, 0x77u, 0xfdu, 0x04u, 0x1eu, 0x3bu, 0xd1u, 0x90u, 0x23u, 0x9bu, 0x00u, 0xf6u, 0x50u, 0x33u, 0xaau, 0x04u, 0x33u, 0xf2u, 0x50u, 0x0au, 0x9fu, 0x04u, 0x33u, 0x53u, 0xaau, 0xf2u, 0x50u, 0x10u, 0x9bu, 0xbeu, 0xb2u, 0x01u, 0x93u, 0x02u, 0x00u, 0x33u, 0x00u, 0x53u, 0xa9u, 0x28u, 0x00u, 0x00u, 0xf0u, 0x6eu, 0xfcu, 0xadu, 0x9bu, 0xbbu, 0x42u, 0x2eu, 0xd9u, 0x07u, 0xa9u, @@ -937,10 +937,10 @@ const uint8_t cy_m0p_image[] = { 0x13u, 0x43u, 0x33u, 0x60u, 0x00u, 0x2du, 0x01u, 0xd1u, 0x00u, 0x29u, 0x12u, 0xd0u, 0x80u, 0x22u, 0xa3u, 0x68u, 0x52u, 0x02u, 0xc3u, 0x18u, 0x19u, 0x68u, 0x11u, 0x42u, 0xfcu, 0xd0u, 0x23u, 0x68u, 0xc0u, 0x18u, 0x08u, 0x4bu, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x04u, 0xd8u, 0x80u, 0x23u, 0x02u, 0x68u, 0x1au, 0x42u, - 0xfcu, 0xd1u, 0xf7u, 0xbdu, 0x03u, 0x68u, 0x00u, 0x2bu, 0xfcu, 0xd1u, 0xfau, 0xe7u, 0x18u, 0x04u, 0x00u, 0x08u, - 0x28u, 0x06u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x1fu, 0x24u, 0x08u, 0x4bu, 0x89u, 0x06u, 0x1bu, 0x68u, 0x29u, 0x33u, + 0xfcu, 0xd1u, 0xf7u, 0xbdu, 0x03u, 0x68u, 0x00u, 0x2bu, 0xfcu, 0xd1u, 0xfau, 0xe7u, 0x28u, 0x04u, 0x00u, 0x08u, + 0x38u, 0x06u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x1fu, 0x24u, 0x08u, 0x4bu, 0x89u, 0x06u, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x9cu, 0x42u, 0xa4u, 0x41u, 0x13u, 0x00u, 0x64u, 0x42u, 0x0cu, 0x34u, 0xa3u, 0x40u, 0x80u, 0x22u, - 0x0bu, 0x43u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xb0u, 0xffu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0x28u, 0x06u, 0x00u, 0x08u, + 0x0bu, 0x43u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xb0u, 0xffu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0x38u, 0x06u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, 0x00u, 0x22u, 0x0eu, 0x21u, 0xffu, 0xf7u, 0xe4u, 0xffu, 0x20u, 0x00u, 0x00u, 0x22u, 0x0du, 0x21u, 0xffu, 0xf7u, 0xdfu, 0xffu, 0x20u, 0x00u, 0x00u, 0x22u, 0x0cu, 0x21u, 0xffu, 0xf7u, 0xdau, 0xffu, 0x20u, 0x00u, 0x00u, 0x22u, 0x0bu, 0x21u, 0xffu, 0xf7u, 0xd5u, 0xffu, 0x20u, 0x00u, 0x00u, 0x22u, 0x0au, 0x21u, @@ -951,10 +951,10 @@ const uint8_t cy_m0p_image[] = { 0x20u, 0x00u, 0x00u, 0x22u, 0x03u, 0x21u, 0xffu, 0xf7u, 0xadu, 0xffu, 0x20u, 0x00u, 0x00u, 0x22u, 0x02u, 0x21u, 0xffu, 0xf7u, 0xa8u, 0xffu, 0x20u, 0x00u, 0x00u, 0x22u, 0x01u, 0x21u, 0xffu, 0xf7u, 0xa3u, 0xffu, 0x00u, 0x22u, 0x20u, 0x00u, 0x11u, 0x00u, 0xffu, 0xf7u, 0x9eu, 0xffu, 0x03u, 0x4bu, 0x0fu, 0x21u, 0x1au, 0x68u, 0x20u, 0x00u, - 0x92u, 0x08u, 0xffu, 0xf7u, 0x97u, 0xffu, 0x10u, 0xbdu, 0x1cu, 0x04u, 0x00u, 0x08u, 0x05u, 0x4bu, 0x1bu, 0x68u, + 0x92u, 0x08u, 0xffu, 0xf7u, 0x97u, 0xffu, 0x10u, 0xbdu, 0x2cu, 0x04u, 0x00u, 0x08u, 0x05u, 0x4bu, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1au, 0x78u, 0x04u, 0x4bu, 0x1fu, 0x2au, 0x00u, 0xd9u, 0x04u, 0x4bu, 0x04u, 0x4au, 0x13u, 0x60u, - 0x70u, 0x47u, 0xc0u, 0x46u, 0x28u, 0x06u, 0x00u, 0x08u, 0x6cu, 0x79u, 0x00u, 0x10u, 0xc0u, 0x79u, 0x00u, 0x10u, - 0x18u, 0x04u, 0x00u, 0x08u, 0x2fu, 0x4bu, 0x70u, 0xb5u, 0x14u, 0x00u, 0x1au, 0x68u, 0x00u, 0x2au, 0x2cu, 0xd0u, + 0x70u, 0x47u, 0xc0u, 0x46u, 0x38u, 0x06u, 0x00u, 0x08u, 0x74u, 0x79u, 0x00u, 0x10u, 0xc8u, 0x79u, 0x00u, 0x10u, + 0x28u, 0x04u, 0x00u, 0x08u, 0x2fu, 0x4bu, 0x70u, 0xb5u, 0x14u, 0x00u, 0x1au, 0x68u, 0x00u, 0x2au, 0x2cu, 0xd0u, 0x00u, 0x29u, 0x09u, 0xd1u, 0x00u, 0x2cu, 0x28u, 0xd1u, 0x13u, 0x6du, 0xc1u, 0x18u, 0x2au, 0x4bu, 0x1bu, 0x68u, 0x9cu, 0x6cu, 0x00u, 0x29u, 0x21u, 0xd0u, 0xa4u, 0x00u, 0x28u, 0x4bu, 0x65u, 0x1eu, 0x9du, 0x42u, 0x1cu, 0xd8u, 0x80u, 0x23u, 0x1bu, 0x01u, 0x9cu, 0x42u, 0x3eu, 0xd0u, 0x0du, 0xd8u, 0x80u, 0x23u, 0x9bu, 0x00u, 0x9cu, 0x42u, @@ -966,8 +966,8 @@ const uint8_t cy_m0p_image[] = { 0xebu, 0xd1u, 0x1fu, 0x2eu, 0x02u, 0xd9u, 0x10u, 0x4du, 0x1bu, 0x02u, 0x43u, 0x51u, 0x93u, 0x6bu, 0xa2u, 0x08u, 0xc3u, 0x18u, 0x19u, 0x60u, 0x0fu, 0x21u, 0xffu, 0xf7u, 0x2du, 0xffu, 0x00u, 0x20u, 0x0bu, 0x4bu, 0x1cu, 0x60u, 0x70u, 0xbdu, 0x7cu, 0x23u, 0xe4u, 0xe7u, 0x78u, 0x23u, 0xe2u, 0xe7u, 0x60u, 0x23u, 0xe0u, 0xe7u, 0x40u, 0x23u, - 0xdeu, 0xe7u, 0xc0u, 0x46u, 0x18u, 0x04u, 0x00u, 0x08u, 0x28u, 0x06u, 0x00u, 0x08u, 0xffu, 0x7fu, 0x00u, 0x00u, - 0x0bu, 0x00u, 0x32u, 0x00u, 0xffu, 0x3fu, 0x00u, 0x00u, 0x88u, 0x14u, 0x00u, 0x00u, 0x1cu, 0x04u, 0x00u, 0x08u, + 0xdeu, 0xe7u, 0xc0u, 0x46u, 0x28u, 0x04u, 0x00u, 0x08u, 0x38u, 0x06u, 0x00u, 0x08u, 0xffu, 0x7fu, 0x00u, 0x00u, + 0x0bu, 0x00u, 0x32u, 0x00u, 0xffu, 0x3fu, 0x00u, 0x00u, 0x88u, 0x14u, 0x00u, 0x00u, 0x2cu, 0x04u, 0x00u, 0x08u, 0x20u, 0x4bu, 0x21u, 0x49u, 0x1bu, 0x68u, 0x09u, 0x68u, 0x9au, 0x6cu, 0x92u, 0x00u, 0x00u, 0x29u, 0x1cu, 0xd0u, 0x1eu, 0x49u, 0x09u, 0x68u, 0x00u, 0x29u, 0x18u, 0xd0u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x2fu, 0xd9u, 0x1bu, 0x4bu, 0xc3u, 0x58u, 0x5bu, 0x04u, 0x5bu, 0x0eu, 0x70u, 0x2bu, 0x1du, 0xd0u, 0x08u, 0xd8u, 0x40u, 0x2bu, @@ -976,89 +976,89 @@ const uint8_t cy_m0p_image[] = { 0x13u, 0xd0u, 0x7fu, 0x2bu, 0xf9u, 0xd1u, 0x80u, 0x22u, 0x52u, 0x00u, 0xf6u, 0xe7u, 0x80u, 0x22u, 0xd2u, 0x01u, 0xf3u, 0xe7u, 0x80u, 0x22u, 0x92u, 0x01u, 0xf0u, 0xe7u, 0x80u, 0x22u, 0x52u, 0x01u, 0xedu, 0xe7u, 0x80u, 0x22u, 0x12u, 0x01u, 0xeau, 0xe7u, 0x80u, 0x22u, 0xd2u, 0x00u, 0xe7u, 0xe7u, 0x80u, 0x22u, 0x92u, 0x00u, 0xe4u, 0xe7u, - 0x0au, 0x00u, 0xe2u, 0xe7u, 0x28u, 0x06u, 0x00u, 0x08u, 0x18u, 0x04u, 0x00u, 0x08u, 0x1cu, 0x04u, 0x00u, 0x08u, + 0x0au, 0x00u, 0xe2u, 0xe7u, 0x38u, 0x06u, 0x00u, 0x08u, 0x28u, 0x04u, 0x00u, 0x08u, 0x2cu, 0x04u, 0x00u, 0x08u, 0x88u, 0x14u, 0x00u, 0x00u, 0x10u, 0xb5u, 0x04u, 0x00u, 0xffu, 0xf7u, 0x30u, 0xffu, 0x17u, 0x4au, 0x18u, 0x49u, 0x13u, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x17u, 0xd8u, 0x16u, 0x4bu, 0x23u, 0x60u, 0x01u, 0x20u, 0x09u, 0x68u, 0x4bu, 0x6bu, 0xe3u, 0x18u, 0x18u, 0x60u, 0x13u, 0x4bu, 0x1bu, 0x68u, 0x00u, 0x2bu, 0x07u, 0xd1u, 0x13u, 0x68u, 0x09u, 0x6du, 0x9au, 0x6cu, 0x61u, 0x18u, 0x92u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x2au, 0xffu, 0x20u, 0x00u, 0xffu, 0xf7u, 0xbdu, 0xfeu, 0x00u, 0x20u, 0x10u, 0xbdu, 0x23u, 0x68u, 0x0bu, 0x48u, 0x03u, 0x40u, 0x23u, 0x60u, 0x0bu, 0x68u, 0x0au, 0x48u, 0x5bu, 0x68u, 0xe3u, 0x18u, 0x18u, 0x60u, 0x80u, 0x23u, 0x20u, 0x68u, - 0x1bu, 0x06u, 0x03u, 0x43u, 0x23u, 0x60u, 0x03u, 0x23u, 0xa3u, 0x60u, 0xd8u, 0xe7u, 0x28u, 0x06u, 0x00u, 0x08u, - 0x18u, 0x04u, 0x00u, 0x08u, 0x03u, 0x00u, 0x00u, 0x80u, 0x1cu, 0x04u, 0x00u, 0x08u, 0xffu, 0xffu, 0xfeu, 0x7fu, + 0x1bu, 0x06u, 0x03u, 0x43u, 0x23u, 0x60u, 0x03u, 0x23u, 0xa3u, 0x60u, 0xd8u, 0xe7u, 0x38u, 0x06u, 0x00u, 0x08u, + 0x28u, 0x04u, 0x00u, 0x08u, 0x03u, 0x00u, 0x00u, 0x80u, 0x2cu, 0x04u, 0x00u, 0x08u, 0xffu, 0xffu, 0xfeu, 0x7fu, 0x01u, 0x00u, 0x02u, 0x00u, 0x03u, 0x23u, 0x03u, 0x70u, 0x00u, 0x20u, 0x70u, 0x47u, 0x06u, 0x4bu, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1au, 0x78u, 0x00u, 0x23u, 0x03u, 0x60u, 0x1fu, 0x2au, 0x03u, 0xd8u, 0x00u, 0x20u, 0x03u, 0x4bu, - 0x18u, 0x60u, 0x70u, 0x47u, 0x83u, 0x60u, 0xf9u, 0xe7u, 0x28u, 0x06u, 0x00u, 0x08u, 0x1cu, 0x04u, 0x00u, 0x08u, + 0x18u, 0x60u, 0x70u, 0x47u, 0x83u, 0x60u, 0xf9u, 0xe7u, 0x38u, 0x06u, 0x00u, 0x08u, 0x2cu, 0x04u, 0x00u, 0x08u, 0x30u, 0xb5u, 0x01u, 0x29u, 0x0bu, 0xd9u, 0x01u, 0x22u, 0x0au, 0x40u, 0x54u, 0x42u, 0x62u, 0x41u, 0xcbu, 0x0fu, 0x5bu, 0x18u, 0x5bu, 0x10u, 0x9bu, 0x1au, 0x02u, 0x00u, 0x01u, 0x39u, 0x8bu, 0x42u, 0x00u, 0xdbu, 0x30u, 0xbdu, 0x14u, 0x78u, 0x45u, 0x5cu, 0x15u, 0x70u, 0x44u, 0x54u, 0x01u, 0x32u, 0x01u, 0x39u, 0xf5u, 0xe7u, 0x00u, 0x00u, 0x03u, 0x4bu, 0x1bu, 0x68u, 0x9bu, 0x68u, 0xc0u, 0x18u, 0x0fu, 0x23u, 0x00u, 0x68u, 0x18u, 0x40u, 0x70u, 0x47u, - 0x18u, 0x04u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x04u, 0x00u, 0x0du, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xf0u, 0xffu, + 0x28u, 0x04u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x04u, 0x00u, 0x0du, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xf0u, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x80u, 0x21u, 0x05u, 0x4bu, 0xc9u, 0x05u, 0x1au, 0x68u, 0xd3u, 0x68u, 0xe3u, 0x18u, - 0x19u, 0x60u, 0xd3u, 0x68u, 0xe4u, 0x18u, 0x25u, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u, 0x18u, 0x04u, 0x00u, 0x08u, + 0x19u, 0x60u, 0xd3u, 0x68u, 0xe4u, 0x18u, 0x25u, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u, 0x28u, 0x04u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x04u, 0x00u, 0x0eu, 0x00u, 0x15u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xd9u, 0xffu, 0x05u, 0x28u, 0xfau, 0xd8u, 0x06u, 0x4bu, 0x06u, 0x49u, 0x1bu, 0x68u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x11u, 0x60u, 0xdau, 0x68u, - 0xa2u, 0x18u, 0x16u, 0x60u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0x25u, 0x60u, 0x70u, 0xbdu, 0x18u, 0x04u, 0x00u, 0x08u, + 0xa2u, 0x18u, 0x16u, 0x60u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0x25u, 0x60u, 0x70u, 0xbdu, 0x28u, 0x04u, 0x00u, 0x08u, 0x10u, 0x00u, 0x00u, 0x41u, 0xf8u, 0xb5u, 0x04u, 0x00u, 0x0fu, 0x00u, 0x16u, 0x00u, 0x1du, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xbeu, 0xffu, 0x04u, 0x28u, 0xfau, 0xd8u, 0x07u, 0x4bu, 0x08u, 0x49u, 0x1bu, 0x68u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x11u, 0x60u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x17u, 0x60u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x16u, 0x60u, - 0xdbu, 0x68u, 0xe4u, 0x18u, 0x25u, 0x60u, 0xf8u, 0xbdu, 0x18u, 0x04u, 0x00u, 0x08u, 0x10u, 0x02u, 0x00u, 0x42u, + 0xdbu, 0x68u, 0xe4u, 0x18u, 0x25u, 0x60u, 0xf8u, 0xbdu, 0x28u, 0x04u, 0x00u, 0x08u, 0x10u, 0x02u, 0x00u, 0x42u, 0xf8u, 0xb5u, 0x04u, 0x00u, 0x0fu, 0x00u, 0x16u, 0x00u, 0x1du, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa0u, 0xffu, 0x03u, 0x28u, 0xfau, 0xd8u, 0x09u, 0x4bu, 0x0au, 0x49u, 0x1bu, 0x68u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x11u, 0x60u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x17u, 0x60u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x16u, 0x60u, 0xdau, 0x68u, 0xa2u, 0x18u, - 0x15u, 0x60u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0x06u, 0x9bu, 0x23u, 0x60u, 0xf8u, 0xbdu, 0x18u, 0x04u, 0x00u, 0x08u, + 0x15u, 0x60u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0x06u, 0x9bu, 0x23u, 0x60u, 0xf8u, 0xbdu, 0x28u, 0x04u, 0x00u, 0x08u, 0x10u, 0x32u, 0x00u, 0x43u, 0x70u, 0xb5u, 0x04u, 0x00u, 0x0du, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x80u, 0xffu, 0x07u, 0x28u, 0xfau, 0xd8u, 0x03u, 0x4bu, 0x2du, 0x06u, 0x1bu, 0x68u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0x25u, 0x60u, - 0x70u, 0xbdu, 0xc0u, 0x46u, 0x18u, 0x04u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x05u, 0x00u, 0x0cu, 0x00u, 0x1eu, 0x00u, + 0x70u, 0xbdu, 0xc0u, 0x46u, 0x28u, 0x04u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x05u, 0x00u, 0x0cu, 0x00u, 0x1eu, 0x00u, 0x28u, 0x00u, 0xffu, 0xf7u, 0x6du, 0xffu, 0x07u, 0x28u, 0xfau, 0xd8u, 0x05u, 0x4bu, 0x24u, 0x06u, 0x1bu, 0x68u, 0xdbu, 0x68u, 0xedu, 0x18u, 0x01u, 0x23u, 0xb3u, 0x40u, 0x1cu, 0x43u, 0x2cu, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u, - 0x18u, 0x04u, 0x00u, 0x08u, 0xf8u, 0xb5u, 0x07u, 0x00u, 0x0cu, 0x00u, 0x1du, 0x00u, 0x06u, 0xabu, 0x1eu, 0x78u, + 0x28u, 0x04u, 0x00u, 0x08u, 0xf8u, 0xb5u, 0x07u, 0x00u, 0x0cu, 0x00u, 0x1du, 0x00u, 0x06u, 0xabu, 0x1eu, 0x78u, 0x38u, 0x00u, 0xffu, 0xf7u, 0x55u, 0xffu, 0x07u, 0x28u, 0xfau, 0xd8u, 0x06u, 0x4bu, 0x02u, 0x21u, 0x1bu, 0x68u, 0xb1u, 0x40u, 0xd8u, 0x68u, 0x01u, 0x23u, 0xabu, 0x40u, 0x24u, 0x06u, 0x19u, 0x43u, 0x38u, 0x18u, 0x21u, 0x43u, - 0x01u, 0x60u, 0xf8u, 0xbdu, 0x18u, 0x04u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x06u, 0x00u, 0x0cu, 0x00u, 0x1du, 0x00u, + 0x01u, 0x60u, 0xf8u, 0xbdu, 0x28u, 0x04u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x06u, 0x00u, 0x0cu, 0x00u, 0x1du, 0x00u, 0x30u, 0x00u, 0xffu, 0xf7u, 0x3du, 0xffu, 0x07u, 0x28u, 0xfau, 0xd8u, 0x02u, 0x21u, 0x08u, 0x4bu, 0x05u, 0x9au, 0x1bu, 0x68u, 0x24u, 0x06u, 0xd8u, 0x68u, 0x04u, 0x9bu, 0x30u, 0x18u, 0x99u, 0x40u, 0x01u, 0x23u, 0xabu, 0x40u, 0x19u, 0x43u, 0x03u, 0x23u, 0x93u, 0x40u, 0x19u, 0x43u, 0x21u, 0x43u, 0x01u, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u, - 0x18u, 0x04u, 0x00u, 0x08u, 0x13u, 0xb5u, 0x04u, 0x00u, 0x08u, 0x00u, 0x11u, 0x00u, 0x00u, 0x2bu, 0x13u, 0xd0u, + 0x28u, 0x04u, 0x00u, 0x08u, 0x13u, 0xb5u, 0x04u, 0x00u, 0x08u, 0x00u, 0x11u, 0x00u, 0x00u, 0x2bu, 0x13u, 0xd0u, 0x02u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x56u, 0xffu, 0x08u, 0x23u, 0x20u, 0x00u, 0x00u, 0x93u, 0x00u, 0x22u, 0x04u, 0x3bu, 0x50u, 0x21u, 0xffu, 0xf7u, 0xb6u, 0xffu, 0x04u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xe4u, 0x18u, - 0x10u, 0x23u, 0x22u, 0x68u, 0x1au, 0x42u, 0xfcu, 0xd1u, 0x13u, 0xbdu, 0xc0u, 0x46u, 0x18u, 0x04u, 0x00u, 0x08u, + 0x10u, 0x23u, 0x22u, 0x68u, 0x1au, 0x42u, 0xfcu, 0xd1u, 0x13u, 0xbdu, 0xc0u, 0x46u, 0x28u, 0x04u, 0x00u, 0x08u, 0x13u, 0xb5u, 0x04u, 0x00u, 0x10u, 0x00u, 0x1au, 0x1eu, 0x13u, 0xd0u, 0x03u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x39u, 0xffu, 0x0cu, 0x23u, 0x20u, 0x00u, 0x00u, 0x93u, 0x00u, 0x22u, 0x04u, 0x3bu, 0x51u, 0x21u, 0xffu, 0xf7u, 0x99u, 0xffu, 0x04u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xe4u, 0x18u, 0x10u, 0x23u, 0x22u, 0x68u, 0x1au, 0x42u, - 0xfcu, 0xd1u, 0x13u, 0xbdu, 0x18u, 0x04u, 0x00u, 0x08u, 0x13u, 0xb5u, 0x04u, 0x00u, 0x01u, 0x20u, 0x00u, 0x2bu, + 0xfcu, 0xd1u, 0x13u, 0xbdu, 0x28u, 0x04u, 0x00u, 0x08u, 0x13u, 0xb5u, 0x04u, 0x00u, 0x01u, 0x20u, 0x00u, 0x2bu, 0x15u, 0xd0u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x1eu, 0xffu, 0x08u, 0x23u, 0x00u, 0x22u, 0x00u, 0x93u, 0x52u, 0x21u, 0x04u, 0x3bu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x7eu, 0xffu, 0x10u, 0x22u, 0x05u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xe3u, 0x18u, 0x19u, 0x68u, 0x11u, 0x42u, 0xfcu, 0xd1u, 0xc0u, 0x23u, 0x5bu, 0x00u, 0xe0u, 0x58u, 0x16u, 0xbdu, - 0x18u, 0x04u, 0x00u, 0x08u, 0x13u, 0xb5u, 0x04u, 0x00u, 0x08u, 0x00u, 0x11u, 0x00u, 0x1au, 0x00u, 0x04u, 0xabu, + 0x28u, 0x04u, 0x00u, 0x08u, 0x13u, 0xb5u, 0x04u, 0x00u, 0x08u, 0x00u, 0x11u, 0x00u, 0x1au, 0x00u, 0x04u, 0xabu, 0x1bu, 0x88u, 0x00u, 0x2bu, 0x15u, 0xd0u, 0x00u, 0x90u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x19u, 0xffu, 0x0cu, 0x23u, 0x01u, 0x93u, 0x04u, 0x3bu, 0x00u, 0x93u, 0x20u, 0x00u, 0x04u, 0x3bu, 0x00u, 0x22u, 0x53u, 0x21u, 0xffu, 0xf7u, 0x73u, 0xffu, 0x04u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xe4u, 0x18u, 0x10u, 0x23u, 0x22u, 0x68u, 0x1au, 0x42u, - 0xfcu, 0xd1u, 0x13u, 0xbdu, 0x18u, 0x04u, 0x00u, 0x08u, 0x03u, 0x4bu, 0x1bu, 0x68u, 0x9bu, 0x68u, 0xc0u, 0x18u, - 0x0fu, 0x23u, 0x00u, 0x68u, 0x18u, 0x40u, 0x70u, 0x47u, 0x18u, 0x04u, 0x00u, 0x08u, 0x03u, 0x4bu, 0x1bu, 0x68u, - 0x1bu, 0x68u, 0xc0u, 0x18u, 0x03u, 0x68u, 0x00u, 0x2bu, 0xfcu, 0xd1u, 0x70u, 0x47u, 0x18u, 0x04u, 0x00u, 0x08u, + 0xfcu, 0xd1u, 0x13u, 0xbdu, 0x28u, 0x04u, 0x00u, 0x08u, 0x03u, 0x4bu, 0x1bu, 0x68u, 0x9bu, 0x68u, 0xc0u, 0x18u, + 0x0fu, 0x23u, 0x00u, 0x68u, 0x18u, 0x40u, 0x70u, 0x47u, 0x28u, 0x04u, 0x00u, 0x08u, 0x03u, 0x4bu, 0x1bu, 0x68u, + 0x1bu, 0x68u, 0xc0u, 0x18u, 0x03u, 0x68u, 0x00u, 0x2bu, 0xfcu, 0xd1u, 0x70u, 0x47u, 0x28u, 0x04u, 0x00u, 0x08u, 0xf8u, 0xb5u, 0x04u, 0x00u, 0x0du, 0x00u, 0x17u, 0x00u, 0x1eu, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xe4u, 0xffu, 0x04u, 0x28u, 0xfau, 0xd8u, 0x08u, 0x2du, 0x04u, 0xd0u, 0x0cu, 0x4au, 0xa3u, 0x58u, 0x00u, 0x2bu, 0xfcu, 0xdbu, 0x04u, 0xe0u, 0x86u, 0x22u, 0x52u, 0x01u, 0xa3u, 0x58u, 0x00u, 0x2bu, 0xfcu, 0xdbu, 0xe2u, 0x21u, 0x08u, 0x4bu, 0xc9u, 0x05u, 0x1bu, 0x68u, 0x0du, 0x43u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x15u, 0x60u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x17u, 0x60u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0x26u, 0x60u, 0xf8u, 0xbdu, 0xc0u, 0x46u, 0xd0u, 0x10u, 0x00u, 0x00u, - 0x18u, 0x04u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x04u, 0x00u, 0x0eu, 0x00u, 0x15u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, + 0x28u, 0x04u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x04u, 0x00u, 0x0eu, 0x00u, 0x15u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xbbu, 0xffu, 0x04u, 0x28u, 0xfau, 0xd8u, 0x06u, 0x4bu, 0x06u, 0x49u, 0x1bu, 0x68u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x11u, 0x60u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x16u, 0x60u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0x25u, 0x60u, 0x70u, 0xbdu, - 0x18u, 0x04u, 0x00u, 0x08u, 0x0cu, 0x00u, 0x00u, 0x70u, 0x70u, 0xb5u, 0x05u, 0x00u, 0x0cu, 0x00u, 0x1eu, 0x1eu, + 0x28u, 0x04u, 0x00u, 0x08u, 0x0cu, 0x00u, 0x00u, 0x70u, 0x70u, 0xb5u, 0x05u, 0x00u, 0x0cu, 0x00u, 0x1eu, 0x1eu, 0x22u, 0xd0u, 0x08u, 0x21u, 0xffu, 0xf7u, 0xb4u, 0xffu, 0x21u, 0x00u, 0x32u, 0x00u, 0x28u, 0x00u, 0xffu, 0xf7u, 0xd9u, 0xffu, 0x34u, 0x00u, 0x0fu, 0x2cu, 0x18u, 0xd8u, 0x10u, 0x24u, 0x33u, 0x09u, 0x64u, 0x42u, 0x5cu, 0x43u, 0xa4u, 0x19u, 0xa4u, 0xb2u, 0x00u, 0x2cu, 0x0cu, 0xd0u, 0x28u, 0x00u, 0xffu, 0xf7u, 0x8du, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x0du, 0x4bu, 0x0du, 0x4au, 0x1bu, 0x68u, 0x24u, 0x04u, 0xdbu, 0x68u, 0x14u, 0x43u, 0xebu, 0x18u, 0x1cu, 0x60u, 0x28u, 0x00u, 0xffu, 0xf7u, 0x8au, 0xffu, 0x70u, 0xbdu, 0x28u, 0x00u, 0xffu, 0xf7u, 0x7cu, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x04u, 0x4bu, 0x06u, 0x4au, 0x1bu, 0x68u, 0x10u, 0x3cu, 0xdbu, 0x68u, 0xa4u, 0xb2u, - 0xebu, 0x18u, 0x1au, 0x60u, 0xd6u, 0xe7u, 0xc0u, 0x46u, 0x18u, 0x04u, 0x00u, 0x08u, 0x08u, 0xc0u, 0x00u, 0x40u, + 0xebu, 0x18u, 0x1au, 0x60u, 0xd6u, 0xe7u, 0xc0u, 0x46u, 0x28u, 0x04u, 0x00u, 0x08u, 0x08u, 0xc0u, 0x00u, 0x40u, 0x08u, 0xc0u, 0x10u, 0x40u, 0xf8u, 0xb5u, 0x05u, 0x00u, 0x16u, 0x00u, 0x1fu, 0x1eu, 0x1eu, 0xd0u, 0x1au, 0x00u, 0xffu, 0xf7u, 0xa0u, 0xffu, 0x3cu, 0x00u, 0x0fu, 0x2cu, 0x19u, 0xd8u, 0x10u, 0x24u, 0x3bu, 0x09u, 0x64u, 0x42u, 0x5cu, 0x43u, 0xe4u, 0x19u, 0xa4u, 0xb2u, 0x00u, 0x2cu, 0x0du, 0xd0u, 0x28u, 0x00u, 0xffu, 0xf7u, 0x54u, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x0du, 0x4bu, 0x0eu, 0x4au, 0x1bu, 0x68u, 0x32u, 0x43u, 0xdbu, 0x68u, 0x24u, 0x04u, 0xebu, 0x18u, 0x14u, 0x43u, 0x1cu, 0x60u, 0x28u, 0x00u, 0xffu, 0xf7u, 0x50u, 0xffu, 0xf8u, 0xbdu, 0x28u, 0x00u, 0xffu, 0xf7u, 0x42u, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x04u, 0x4bu, 0x06u, 0x4au, 0x1bu, 0x68u, 0x32u, 0x43u, - 0xdbu, 0x68u, 0x10u, 0x3cu, 0xebu, 0x18u, 0x1au, 0x60u, 0xa4u, 0xb2u, 0xd4u, 0xe7u, 0x18u, 0x04u, 0x00u, 0x08u, + 0xdbu, 0x68u, 0x10u, 0x3cu, 0xebu, 0x18u, 0x1au, 0x60u, 0xa4u, 0xb2u, 0xd4u, 0xe7u, 0x28u, 0x04u, 0x00u, 0x08u, 0x00u, 0xc0u, 0x00u, 0x42u, 0x00u, 0xc0u, 0x10u, 0x42u, 0x70u, 0xb5u, 0x05u, 0x00u, 0x14u, 0x00u, 0x1eu, 0x00u, 0x01u, 0x20u, 0x00u, 0x2bu, 0x2du, 0xd0u, 0x8cu, 0x23u, 0x00u, 0x22u, 0x5bu, 0x01u, 0xeau, 0x50u, 0x28u, 0x00u, 0x0au, 0x00u, 0x33u, 0x00u, 0x08u, 0x21u, 0xffu, 0xf7u, 0x33u, 0xffu, 0x22u, 0x00u, 0x33u, 0x00u, 0x09u, 0x21u, @@ -1068,7 +1068,7 @@ const uint8_t cy_m0p_image[] = { 0x14u, 0x43u, 0xebu, 0x18u, 0x1cu, 0x60u, 0x28u, 0x00u, 0xffu, 0xf7u, 0x08u, 0xffu, 0x8cu, 0x23u, 0x5bu, 0x01u, 0xe8u, 0x58u, 0x70u, 0xbdu, 0x28u, 0x00u, 0xffu, 0xf7u, 0xf7u, 0xfeu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x04u, 0x4bu, 0x05u, 0x4au, 0x1bu, 0x68u, 0x10u, 0x3cu, 0xdbu, 0x68u, 0xa4u, 0xb2u, 0xebu, 0x18u, 0x1au, 0x60u, 0xd3u, 0xe7u, - 0x18u, 0x04u, 0x00u, 0x08u, 0x98u, 0x00u, 0x00u, 0x43u, 0x98u, 0x00u, 0x10u, 0x43u, 0xf8u, 0xb5u, 0x1fu, 0x00u, + 0x28u, 0x04u, 0x00u, 0x08u, 0x98u, 0x00u, 0x00u, 0x43u, 0x98u, 0x00u, 0x10u, 0x43u, 0xf8u, 0xb5u, 0x1fu, 0x00u, 0x06u, 0xabu, 0x1eu, 0x88u, 0x05u, 0x00u, 0x0cu, 0x00u, 0x00u, 0x2eu, 0x29u, 0xd0u, 0x33u, 0x00u, 0x08u, 0x21u, 0xffu, 0xf7u, 0xeeu, 0xfeu, 0x33u, 0x00u, 0x3au, 0x00u, 0x09u, 0x21u, 0x28u, 0x00u, 0xffu, 0xf7u, 0xe8u, 0xfeu, 0x21u, 0x00u, 0x32u, 0x00u, 0x28u, 0x00u, 0xffu, 0xf7u, 0x0du, 0xffu, 0x34u, 0x00u, 0x0fu, 0x2cu, 0x18u, 0xd8u, @@ -1077,37 +1077,37 @@ const uint8_t cy_m0p_image[] = { 0x24u, 0x04u, 0xdbu, 0x68u, 0x14u, 0x43u, 0xebu, 0x18u, 0x1cu, 0x60u, 0x28u, 0x00u, 0xffu, 0xf7u, 0xbeu, 0xfeu, 0xf8u, 0xbdu, 0x28u, 0x00u, 0xffu, 0xf7u, 0xb0u, 0xfeu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x04u, 0x4bu, 0x06u, 0x4au, 0x1bu, 0x68u, 0x10u, 0x3cu, 0xdbu, 0x68u, 0xa4u, 0xb2u, 0xebu, 0x18u, 0x1au, 0x60u, 0xd6u, 0xe7u, 0xc0u, 0x46u, - 0x18u, 0x04u, 0x00u, 0x08u, 0x98u, 0xc0u, 0x00u, 0x41u, 0x98u, 0xc0u, 0x10u, 0x41u, 0x10u, 0xb5u, 0x80u, 0x24u, + 0x28u, 0x04u, 0x00u, 0x08u, 0x98u, 0xc0u, 0x00u, 0x41u, 0x98u, 0xc0u, 0x10u, 0x41u, 0x10u, 0xb5u, 0x80u, 0x24u, 0xa4u, 0x00u, 0x01u, 0x51u, 0x81u, 0x21u, 0x52u, 0x00u, 0x52u, 0x08u, 0x89u, 0x00u, 0x42u, 0x50u, 0x82u, 0x22u, 0xdbu, 0x00u, 0xdbu, 0x08u, 0x92u, 0x00u, 0x83u, 0x50u, 0x00u, 0x20u, 0x10u, 0xbdu, 0x70u, 0xb5u, 0x04u, 0x00u, 0x15u, 0x00u, 0xffu, 0xf7u, 0x3fu, 0xfdu, 0x00u, 0x22u, 0x5cu, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xaau, 0xfdu, 0x20u, 0x21u, 0x06u, 0x4bu, 0x1au, 0x68u, 0x13u, 0x68u, 0xe3u, 0x18u, 0x18u, 0x68u, 0x08u, 0x40u, 0xfcu, 0xd1u, - 0x93u, 0x69u, 0xe4u, 0x18u, 0x23u, 0x68u, 0x2bu, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u, 0x18u, 0x04u, 0x00u, 0x08u, + 0x93u, 0x69u, 0xe4u, 0x18u, 0x23u, 0x68u, 0x2bu, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u, 0x28u, 0x04u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x80u, 0x24u, 0xa4u, 0x00u, 0x01u, 0x51u, 0x81u, 0x21u, 0x52u, 0x00u, 0x52u, 0x08u, 0x89u, 0x00u, 0x42u, 0x50u, 0x82u, 0x22u, 0xdbu, 0x00u, 0xdbu, 0x08u, 0x92u, 0x00u, 0x83u, 0x50u, 0x00u, 0x20u, 0x10u, 0xbdu, 0x83u, 0x23u, 0x9bu, 0x00u, 0x10u, 0xb5u, 0xc1u, 0x50u, 0x01u, 0x21u, 0x04u, 0x33u, 0xc1u, 0x50u, 0x06u, 0x4bu, 0x19u, 0x68u, 0x0bu, 0x68u, 0xc3u, 0x18u, 0x1cu, 0x68u, 0x00u, 0x2cu, 0xfcu, 0xdbu, 0x8bu, 0x69u, 0xc0u, 0x18u, - 0x03u, 0x68u, 0x00u, 0x20u, 0x13u, 0x60u, 0x10u, 0xbdu, 0x18u, 0x04u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x06u, 0x4cu, + 0x03u, 0x68u, 0x00u, 0x20u, 0x13u, 0x60u, 0x10u, 0xbdu, 0x28u, 0x04u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x06u, 0x4cu, 0x24u, 0x68u, 0x29u, 0x34u, 0x24u, 0x78u, 0x1fu, 0x2cu, 0x02u, 0xd8u, 0xffu, 0xf7u, 0x05u, 0xfeu, 0x10u, 0xbdu, - 0xffu, 0xf7u, 0x12u, 0xffu, 0xfbu, 0xe7u, 0xc0u, 0x46u, 0x28u, 0x06u, 0x00u, 0x08u, 0x09u, 0x4bu, 0x1bu, 0x68u, + 0xffu, 0xf7u, 0x12u, 0xffu, 0xfbu, 0xe7u, 0xc0u, 0x46u, 0x38u, 0x06u, 0x00u, 0x08u, 0x09u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xc0u, 0x18u, 0x08u, 0x4bu, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x04u, 0xd8u, 0x80u, 0x23u, 0x02u, 0x68u, 0x1au, 0x42u, 0xfcu, 0xd1u, 0x70u, 0x47u, 0x03u, 0x68u, 0x00u, 0x2bu, 0xfcu, 0xd1u, - 0xfau, 0xe7u, 0xc0u, 0x46u, 0x18u, 0x04u, 0x00u, 0x08u, 0x28u, 0x06u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x13u, 0x00u, + 0xfau, 0xe7u, 0xc0u, 0x46u, 0x28u, 0x04u, 0x00u, 0x08u, 0x38u, 0x06u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x13u, 0x00u, 0x06u, 0x4au, 0x14u, 0x68u, 0x29u, 0x34u, 0x22u, 0x78u, 0x1fu, 0x2au, 0x03u, 0xd8u, 0x00u, 0x22u, 0xffu, 0xf7u, - 0xbfu, 0xfdu, 0x10u, 0xbdu, 0x00u, 0x22u, 0xffu, 0xf7u, 0xadu, 0xfeu, 0xfau, 0xe7u, 0x28u, 0x06u, 0x00u, 0x08u, + 0xbfu, 0xfdu, 0x10u, 0xbdu, 0x00u, 0x22u, 0xffu, 0xf7u, 0xadu, 0xfeu, 0xfau, 0xe7u, 0x38u, 0x06u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x0bu, 0x03u, 0x34u, 0x22u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xd6u, 0xfau, 0x10u, 0xbdu, 0x00u, 0x00u, 0x10u, 0xb5u, 0x0au, 0x4bu, 0x09u, 0x03u, 0x1bu, 0x68u, 0x12u, 0x01u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x06u, 0xd8u, 0x13u, 0x00u, 0x25u, 0x22u, 0x0bu, 0x43u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xc5u, 0xfau, 0x10u, 0xbdu, - 0x0fu, 0x23u, 0x13u, 0x43u, 0x0bu, 0x43u, 0x24u, 0x22u, 0xf6u, 0xe7u, 0xc0u, 0x46u, 0x28u, 0x06u, 0x00u, 0x08u, + 0x0fu, 0x23u, 0x13u, 0x43u, 0x0bu, 0x43u, 0x24u, 0x22u, 0xf6u, 0xe7u, 0xc0u, 0x46u, 0x38u, 0x06u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x09u, 0x4bu, 0x09u, 0x03u, 0x1bu, 0x68u, 0x12u, 0x01u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x06u, 0xd8u, 0x13u, 0x00u, 0x0bu, 0x43u, 0x21u, 0x22u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xadu, 0xfau, 0x10u, 0xbdu, - 0x0fu, 0x23u, 0x13u, 0x43u, 0xf6u, 0xe7u, 0xc0u, 0x46u, 0x28u, 0x06u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x0bu, 0x00u, + 0x0fu, 0x23u, 0x13u, 0x43u, 0xf6u, 0xe7u, 0xc0u, 0x46u, 0x38u, 0x06u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x0bu, 0x00u, 0x13u, 0x22u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xa0u, 0xfau, 0x10u, 0xbdu, 0x00u, 0x00u, 0x10u, 0xb5u, 0x13u, 0x00u, 0x07u, 0x4au, 0x12u, 0x68u, 0x29u, 0x32u, 0x14u, 0x78u, 0x0cu, 0x22u, 0x1fu, 0x2cu, 0x00u, 0xd9u, 0x04u, 0x32u, 0x91u, 0x40u, 0x01u, 0x3bu, 0x0bu, 0x43u, 0x12u, 0x22u, 0x00u, 0x21u, 0xffu, 0xf7u, 0x8du, 0xfau, 0x10u, 0xbdu, - 0x28u, 0x06u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x1fu, 0x24u, 0x08u, 0x4bu, 0x89u, 0x06u, 0x1bu, 0x68u, 0x29u, 0x33u, + 0x38u, 0x06u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x1fu, 0x24u, 0x08u, 0x4bu, 0x89u, 0x06u, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x9cu, 0x42u, 0xa4u, 0x41u, 0x13u, 0x00u, 0x64u, 0x42u, 0x0cu, 0x34u, 0xa3u, 0x40u, 0x80u, 0x22u, - 0x0bu, 0x43u, 0x00u, 0x21u, 0xffu, 0xf7u, 0x78u, 0xfau, 0x10u, 0xbdu, 0xc0u, 0x46u, 0x28u, 0x06u, 0x00u, 0x08u, + 0x0bu, 0x43u, 0x00u, 0x21u, 0xffu, 0xf7u, 0x78u, 0xfau, 0x10u, 0xbdu, 0xc0u, 0x46u, 0x38u, 0x06u, 0x00u, 0x08u, 0xf7u, 0xb5u, 0x04u, 0x00u, 0x1du, 0x00u, 0x5eu, 0x1cu, 0x01u, 0x92u, 0x0fu, 0x00u, 0x32u, 0x00u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xccu, 0xffu, 0x32u, 0x00u, 0x01u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xc7u, 0xffu, 0x32u, 0x00u, 0x02u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xc2u, 0xffu, 0x2au, 0x00u, 0x03u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, @@ -1120,7 +1120,7 @@ const uint8_t cy_m0p_image[] = { 0xffu, 0xf7u, 0x2au, 0xfau, 0x0du, 0x4bu, 0x03u, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x24u, 0xfau, 0x33u, 0x00u, 0x3au, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x1eu, 0xfau, 0x00u, 0x22u, 0x20u, 0x00u, 0x11u, 0x00u, 0xffu, 0xf7u, 0x5du, 0xffu, 0x02u, 0x22u, 0x20u, 0x00u, 0x11u, 0x00u, 0xffu, 0xf7u, 0x40u, 0xffu, - 0x01u, 0x3du, 0xd9u, 0xe7u, 0x28u, 0x06u, 0x00u, 0x08u, 0x02u, 0x00u, 0x30u, 0x00u, 0x01u, 0x00u, 0x30u, 0x00u, + 0x01u, 0x3du, 0xd9u, 0xe7u, 0x38u, 0x06u, 0x00u, 0x08u, 0x02u, 0x00u, 0x30u, 0x00u, 0x01u, 0x00u, 0x30u, 0x00u, 0xf7u, 0xb5u, 0x04u, 0x00u, 0x08u, 0x9eu, 0x00u, 0x91u, 0x15u, 0x00u, 0x01u, 0x21u, 0x72u, 0x1cu, 0x77u, 0x00u, 0x01u, 0x93u, 0xffu, 0xf7u, 0x63u, 0xffu, 0x3au, 0x00u, 0x02u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x5eu, 0xffu, 0x3au, 0x00u, 0x03u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x59u, 0xffu, 0x32u, 0x00u, 0x00u, 0x21u, 0x20u, 0x00u, @@ -1142,7 +1142,7 @@ const uint8_t cy_m0p_image[] = { 0x7bu, 0xf9u, 0x20u, 0x00u, 0x10u, 0x4bu, 0x03u, 0x22u, 0x00u, 0x21u, 0xffu, 0xf7u, 0x75u, 0xf9u, 0x00u, 0x9bu, 0x20u, 0x00u, 0x1au, 0x03u, 0x02u, 0x23u, 0x00u, 0x21u, 0x13u, 0x43u, 0x30u, 0x22u, 0xffu, 0xf7u, 0x6cu, 0xf9u, 0x0eu, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xc2u, 0xfeu, 0xf7u, 0xbdu, 0xc0u, 0x46u, 0x3au, 0x10u, 0x00u, 0x00u, - 0x18u, 0x20u, 0x00u, 0x00u, 0x23u, 0x20u, 0x00u, 0x00u, 0x28u, 0x06u, 0x00u, 0x08u, 0x20u, 0x20u, 0x00u, 0x00u, + 0x18u, 0x20u, 0x00u, 0x00u, 0x23u, 0x20u, 0x00u, 0x00u, 0x38u, 0x06u, 0x00u, 0x08u, 0x20u, 0x20u, 0x00u, 0x00u, 0x10u, 0x10u, 0x00u, 0x00u, 0x21u, 0x30u, 0x00u, 0x00u, 0x23u, 0x00u, 0x30u, 0x00u, 0x28u, 0x30u, 0x00u, 0x00u, 0xf7u, 0xb5u, 0x06u, 0x00u, 0x1cu, 0x00u, 0x09u, 0x9bu, 0x01u, 0x91u, 0x5fu, 0x00u, 0x15u, 0x00u, 0x02u, 0x21u, 0x3au, 0x00u, 0xffu, 0xf7u, 0xabu, 0xfeu, 0x3au, 0x00u, 0x03u, 0x21u, 0x30u, 0x00u, 0xffu, 0xf7u, 0xa6u, 0xfeu, @@ -1160,7 +1160,7 @@ const uint8_t cy_m0p_image[] = { 0xebu, 0xf8u, 0x01u, 0x9bu, 0x30u, 0x00u, 0x1cu, 0x03u, 0x0du, 0x4bu, 0x30u, 0x22u, 0x23u, 0x43u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xe2u, 0xf8u, 0xc0u, 0x23u, 0x9bu, 0x03u, 0x30u, 0x00u, 0x23u, 0x43u, 0x30u, 0x22u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xdau, 0xf8u, 0x30u, 0x00u, 0x03u, 0x21u, 0xffu, 0xf7u, 0x30u, 0xfeu, 0xf7u, 0xbdu, 0xc0u, 0x46u, - 0x28u, 0x06u, 0x00u, 0x08u, 0x20u, 0x30u, 0x00u, 0x00u, 0x30u, 0x20u, 0x00u, 0x00u, 0x10u, 0x00u, 0x40u, 0x00u, + 0x38u, 0x06u, 0x00u, 0x08u, 0x20u, 0x30u, 0x00u, 0x00u, 0x30u, 0x20u, 0x00u, 0x00u, 0x10u, 0x00u, 0x40u, 0x00u, 0x01u, 0x00u, 0x40u, 0x00u, 0xf8u, 0xb5u, 0x1du, 0x00u, 0x00u, 0x23u, 0x16u, 0x00u, 0x0fu, 0x00u, 0x10u, 0x22u, 0x19u, 0x00u, 0x04u, 0x00u, 0xffu, 0xf7u, 0xc0u, 0xf8u, 0xe0u, 0x23u, 0x00u, 0x22u, 0x1bu, 0x02u, 0x11u, 0x00u, 0x3bu, 0x43u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xb8u, 0xf8u, 0x90u, 0x23u, 0x00u, 0x22u, 0x1bu, 0x02u, 0x33u, 0x43u, @@ -1183,8 +1183,8 @@ const uint8_t cy_m0p_image[] = { 0x20u, 0x00u, 0x11u, 0x00u, 0xffu, 0xf7u, 0x5cu, 0xfdu, 0x33u, 0x68u, 0x2cu, 0x22u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x00u, 0xd9u, 0x04u, 0x3au, 0x0eu, 0x4bu, 0xa8u, 0xe7u, 0x0eu, 0x4bu, 0x25u, 0x22u, 0xeau, 0xe7u, 0xe0u, 0x21u, 0x20u, 0x00u, 0x89u, 0x01u, 0xffu, 0xf7u, 0x79u, 0xfdu, 0x00u, 0x23u, 0x11u, 0x22u, 0x19u, 0x00u, - 0x20u, 0x00u, 0xffu, 0xf7u, 0x19u, 0xf8u, 0xf8u, 0xbdu, 0x28u, 0x06u, 0x00u, 0x08u, 0x0au, 0xb0u, 0x00u, 0x00u, - 0x09u, 0xc0u, 0x00u, 0x00u, 0x18u, 0x04u, 0x00u, 0x08u, 0xdcu, 0xd0u, 0x00u, 0x00u, 0xd0u, 0xd0u, 0x00u, 0x00u, + 0x20u, 0x00u, 0xffu, 0xf7u, 0x19u, 0xf8u, 0xf8u, 0xbdu, 0x38u, 0x06u, 0x00u, 0x08u, 0x0au, 0xb0u, 0x00u, 0x00u, + 0x09u, 0xc0u, 0x00u, 0x00u, 0x28u, 0x04u, 0x00u, 0x08u, 0xdcu, 0xd0u, 0x00u, 0x00u, 0xd0u, 0xd0u, 0x00u, 0x00u, 0x0au, 0xe0u, 0x00u, 0x00u, 0xdfu, 0xd0u, 0x00u, 0x00u, 0xf0u, 0xb5u, 0x85u, 0xb0u, 0x06u, 0x00u, 0x0fu, 0x00u, 0x02u, 0x93u, 0x0au, 0x9du, 0x0bu, 0x98u, 0x06u, 0x2au, 0x37u, 0xd8u, 0x21u, 0x4bu, 0x91u, 0x00u, 0xc9u, 0x58u, 0x20u, 0x4cu, 0x21u, 0x4bu, 0xa4u, 0x5cu, 0x9bu, 0x5cu, 0x01u, 0x22u, 0x3au, 0x70u, 0x1au, 0x19u, 0x0bu, 0x32u, @@ -1195,7 +1195,7 @@ const uint8_t cy_m0p_image[] = { 0x00u, 0x28u, 0x12u, 0xd1u, 0x00u, 0x9au, 0xa3u, 0xb2u, 0xaau, 0x18u, 0x02u, 0x99u, 0x30u, 0x00u, 0xffu, 0xf7u, 0xb5u, 0xfcu, 0x00u, 0x28u, 0x09u, 0xd1u, 0x38u, 0x70u, 0x07u, 0xe0u, 0x00u, 0x24u, 0x23u, 0x00u, 0x21u, 0x00u, 0xcau, 0xe7u, 0x01u, 0x30u, 0x42u, 0x78u, 0xffu, 0x2au, 0xe0u, 0xd0u, 0x00u, 0x20u, 0x05u, 0xb0u, 0xf0u, 0xbdu, - 0x14u, 0x7au, 0x00u, 0x10u, 0x37u, 0x7au, 0x00u, 0x10u, 0x30u, 0x7au, 0x00u, 0x10u, 0xf0u, 0xb5u, 0x8bu, 0xb0u, + 0x1cu, 0x7au, 0x00u, 0x10u, 0x3fu, 0x7au, 0x00u, 0x10u, 0x38u, 0x7au, 0x00u, 0x10u, 0xf0u, 0xb5u, 0x8bu, 0xb0u, 0x09u, 0x93u, 0x8bu, 0x68u, 0x04u, 0x00u, 0x05u, 0x93u, 0xcbu, 0x68u, 0x08u, 0x92u, 0x06u, 0x93u, 0x0bu, 0x68u, 0x4fu, 0x68u, 0x07u, 0x93u, 0x0bu, 0x69u, 0x8du, 0x69u, 0x03u, 0x93u, 0x4bu, 0x69u, 0x04u, 0x93u, 0xb3u, 0x4bu, 0x1bu, 0x68u, 0x1eu, 0x1eu, 0x02u, 0xd0u, 0x9bu, 0x6bu, 0xc3u, 0x18u, 0x1eu, 0x68u, 0x20u, 0x00u, 0xffu, 0xf7u, @@ -1242,10 +1242,10 @@ const uint8_t cy_m0p_image[] = { 0xffu, 0xf7u, 0x4eu, 0xfcu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x51u, 0xfbu, 0x0du, 0x23u, 0x00u, 0x97u, 0x1au, 0x00u, 0x19u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x44u, 0xfcu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x47u, 0xfbu, 0x01u, 0x3du, 0x93u, 0xe7u, 0x0du, 0x23u, 0x05u, 0x22u, 0x19u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x39u, 0xfcu, 0x20u, 0x00u, - 0xffu, 0xf7u, 0x3cu, 0xfbu, 0x00u, 0x97u, 0x05u, 0x23u, 0xe9u, 0xe7u, 0xc0u, 0x46u, 0x18u, 0x04u, 0x00u, 0x08u, + 0xffu, 0xf7u, 0x3cu, 0xfbu, 0x00u, 0x97u, 0x05u, 0x23u, 0xe9u, 0xe7u, 0xc0u, 0x46u, 0x28u, 0x04u, 0x00u, 0x08u, 0x06u, 0x60u, 0x00u, 0x00u, 0x05u, 0x50u, 0x00u, 0x00u, 0x07u, 0x70u, 0x00u, 0x00u, 0x08u, 0x80u, 0x00u, 0x00u, 0x09u, 0xa0u, 0x00u, 0x00u, 0x0au, 0xc0u, 0x00u, 0x00u, 0x0bu, 0x50u, 0x00u, 0x00u, 0x07u, 0xb0u, 0x00u, 0x00u, - 0x28u, 0x06u, 0x00u, 0x08u, 0xb9u, 0xe0u, 0x00u, 0x00u, 0xbeu, 0xb0u, 0x00u, 0x00u, 0xf0u, 0xb5u, 0x0bu, 0x69u, + 0x38u, 0x06u, 0x00u, 0x08u, 0xb9u, 0xe0u, 0x00u, 0x00u, 0xbeu, 0xb0u, 0x00u, 0x00u, 0xf0u, 0xb5u, 0x0bu, 0x69u, 0x87u, 0xb0u, 0x03u, 0x93u, 0x4bu, 0x69u, 0x04u, 0x00u, 0x04u, 0x93u, 0x8bu, 0x69u, 0x0fu, 0x68u, 0x05u, 0x93u, 0x34u, 0x4bu, 0x4du, 0x68u, 0x1bu, 0x68u, 0x1eu, 0x1eu, 0x02u, 0xd0u, 0x9bu, 0x6bu, 0xc3u, 0x18u, 0x1eu, 0x68u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0x3du, 0xffu, 0x31u, 0x00u, 0x82u, 0xb2u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x1eu, 0xfbu, @@ -1260,13 +1260,13 @@ const uint8_t cy_m0p_image[] = { 0x0eu, 0x22u, 0x00u, 0xf0u, 0xcdu, 0xfdu, 0x2bu, 0x00u, 0x32u, 0x00u, 0x20u, 0x00u, 0x0cu, 0x21u, 0xffu, 0xf7u, 0xf9u, 0xfcu, 0x2bu, 0x00u, 0x0cu, 0x22u, 0x04u, 0x99u, 0x20u, 0x00u, 0x00u, 0xf0u, 0xc1u, 0xfdu, 0xf0u, 0x21u, 0x20u, 0x00u, 0xc9u, 0x01u, 0xffu, 0xf7u, 0x12u, 0xfbu, 0x20u, 0x00u, 0xffu, 0xf7u, 0xafu, 0xfau, 0x00u, 0x20u, - 0x07u, 0xb0u, 0xf0u, 0xbdu, 0x18u, 0x04u, 0x00u, 0x08u, 0x0bu, 0x00u, 0x13u, 0xb5u, 0x11u, 0x00u, 0x07u, 0x22u, + 0x07u, 0xb0u, 0xf0u, 0xbdu, 0x28u, 0x04u, 0x00u, 0x08u, 0x0bu, 0x00u, 0x13u, 0xb5u, 0x11u, 0x00u, 0x07u, 0x22u, 0x04u, 0x00u, 0x58u, 0x68u, 0x02u, 0x40u, 0xc0u, 0x20u, 0x80u, 0x00u, 0x22u, 0x50u, 0x1au, 0x69u, 0x20u, 0x00u, 0x00u, 0x92u, 0x9bu, 0x69u, 0xfeu, 0xf7u, 0xdcu, 0xffu, 0x0cu, 0x23u, 0x01u, 0x93u, 0x04u, 0x3bu, 0x00u, 0x93u, 0x20u, 0x00u, 0x04u, 0x3bu, 0x00u, 0x22u, 0x4cu, 0x21u, 0xffu, 0xf7u, 0x36u, 0xf8u, 0x04u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xe4u, 0x18u, 0x04u, 0x23u, 0x22u, 0x68u, 0x1au, 0x42u, 0xfcu, 0xd1u, 0x13u, 0xbdu, 0xc0u, 0x46u, - 0x18u, 0x04u, 0x00u, 0x08u, 0x00u, 0xb5u, 0x06u, 0x2au, 0x00u, 0xd9u, 0x80u, 0xe0u, 0x10u, 0x00u, 0x8bu, 0x60u, - 0x1au, 0x00u, 0x02u, 0xf0u, 0x63u, 0xf8u, 0x04u, 0x16u, 0x29u, 0x3au, 0x4du, 0x6cu, 0x5cu, 0x00u, 0x54u, 0x33u, + 0x28u, 0x04u, 0x00u, 0x08u, 0x00u, 0xb5u, 0x06u, 0x2au, 0x00u, 0xd9u, 0x80u, 0xe0u, 0x10u, 0x00u, 0x8bu, 0x60u, + 0x1au, 0x00u, 0x02u, 0xf0u, 0x67u, 0xf8u, 0x04u, 0x16u, 0x29u, 0x3au, 0x4du, 0x6cu, 0x5cu, 0x00u, 0x54u, 0x33u, 0x8bu, 0x61u, 0x3cu, 0x4bu, 0x00u, 0x20u, 0xcbu, 0x62u, 0x40u, 0x23u, 0xcbu, 0x60u, 0x2cu, 0x3bu, 0x4bu, 0x61u, 0x4bu, 0x62u, 0x2du, 0x33u, 0x40u, 0x32u, 0xffu, 0x33u, 0x0au, 0x61u, 0x08u, 0x60u, 0x48u, 0x60u, 0xcbu, 0x61u, 0x00u, 0xbdu, 0x60u, 0x33u, 0x8bu, 0x61u, 0x01u, 0x23u, 0x0bu, 0x60u, 0x4bu, 0x60u, 0x32u, 0x4bu, 0x40u, 0x32u, @@ -1282,8 +1282,8 @@ const uint8_t cy_m0p_image[] = { 0x80u, 0x23u, 0xcbu, 0x60u, 0x40u, 0x3bu, 0x4bu, 0x61u, 0x0au, 0x61u, 0x24u, 0x3bu, 0xdcu, 0xe7u, 0xc0u, 0x33u, 0x8bu, 0x61u, 0x05u, 0x23u, 0x0bu, 0x60u, 0x03u, 0x3bu, 0x4bu, 0x60u, 0x0cu, 0x4bu, 0x80u, 0x32u, 0xcbu, 0x62u, 0x80u, 0x23u, 0xcbu, 0x60u, 0x40u, 0x3bu, 0x4bu, 0x61u, 0x0au, 0x61u, 0x20u, 0x3bu, 0xccu, 0xe7u, 0x08u, 0x48u, - 0x96u, 0xe7u, 0xc0u, 0x46u, 0xc0u, 0x7au, 0x00u, 0x10u, 0xd4u, 0x7au, 0x00u, 0x10u, 0xf4u, 0x7au, 0x00u, 0x10u, - 0x14u, 0x7bu, 0x00u, 0x10u, 0x54u, 0x7bu, 0x00u, 0x10u, 0x94u, 0x7bu, 0x00u, 0x10u, 0xd4u, 0x7bu, 0x00u, 0x10u, + 0x96u, 0xe7u, 0xc0u, 0x46u, 0xc8u, 0x7au, 0x00u, 0x10u, 0xdcu, 0x7au, 0x00u, 0x10u, 0xfcu, 0x7au, 0x00u, 0x10u, + 0x1cu, 0x7bu, 0x00u, 0x10u, 0x5cu, 0x7bu, 0x00u, 0x10u, 0x9cu, 0x7bu, 0x00u, 0x10u, 0xdcu, 0x7bu, 0x00u, 0x10u, 0x0bu, 0x00u, 0x32u, 0x00u, 0x10u, 0xb5u, 0x00u, 0x29u, 0x01u, 0xd1u, 0x07u, 0x48u, 0x10u, 0xbdu, 0x00u, 0x24u, 0x4bu, 0x69u, 0x8cu, 0x62u, 0x0cu, 0x62u, 0xa3u, 0x42u, 0xf7u, 0xd0u, 0xcau, 0x6au, 0x9bu, 0xb2u, 0x09u, 0x69u, 0xfeu, 0xf7u, 0xa0u, 0xffu, 0x20u, 0x00u, 0xf1u, 0xe7u, 0x0bu, 0x00u, 0x32u, 0x00u, 0xf7u, 0xb5u, 0x07u, 0x00u, @@ -1313,33 +1313,33 @@ const uint8_t cy_m0p_image[] = { 0x00u, 0x20u, 0x70u, 0xbdu, 0x00u, 0x48u, 0xfcu, 0xe7u, 0x0bu, 0x00u, 0x32u, 0x00u, 0xf0u, 0xb5u, 0x8fu, 0xb0u, 0x01u, 0x93u, 0x14u, 0xabu, 0x1fu, 0x78u, 0x19u, 0x4bu, 0x04u, 0x00u, 0x1bu, 0x68u, 0x00u, 0x91u, 0x16u, 0x00u, 0x1du, 0x1eu, 0x02u, 0xd0u, 0x9bu, 0x6bu, 0xc3u, 0x18u, 0x1du, 0x68u, 0x30u, 0x22u, 0x00u, 0x21u, 0x02u, 0xa8u, - 0x02u, 0xf0u, 0xd5u, 0xf8u, 0x2bu, 0x00u, 0x3au, 0x00u, 0x02u, 0xa9u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x7au, 0xfeu, + 0x02u, 0xf0u, 0xd9u, 0xf8u, 0x2bu, 0x00u, 0x3au, 0x00u, 0x02u, 0xa9u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x7au, 0xfeu, 0x00u, 0x28u, 0x18u, 0xd1u, 0x02u, 0xa9u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x0cu, 0xffu, 0x00u, 0x28u, 0x12u, 0xd1u, 0x33u, 0x00u, 0x00u, 0x9au, 0x02u, 0xa9u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x18u, 0xffu, 0x00u, 0x28u, 0x0au, 0xd1u, 0x01u, 0x9au, 0x02u, 0xa9u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x4fu, 0xffu, 0x00u, 0x28u, 0x03u, 0xd1u, 0x02u, 0xa9u, - 0x20u, 0x00u, 0xffu, 0xf7u, 0xadu, 0xffu, 0x0fu, 0xb0u, 0xf0u, 0xbdu, 0xc0u, 0x46u, 0x18u, 0x04u, 0x00u, 0x08u, + 0x20u, 0x00u, 0xffu, 0xf7u, 0xadu, 0xffu, 0x0fu, 0xb0u, 0xf0u, 0xbdu, 0xc0u, 0x46u, 0x28u, 0x04u, 0x00u, 0x08u, 0x03u, 0x4bu, 0x1bu, 0x68u, 0x9bu, 0x68u, 0xc0u, 0x18u, 0x0fu, 0x23u, 0x00u, 0x68u, 0x18u, 0x40u, 0x70u, 0x47u, - 0x18u, 0x04u, 0x00u, 0x08u, 0x03u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xc0u, 0x18u, 0x03u, 0x68u, 0x00u, 0x2bu, - 0xfcu, 0xd1u, 0x70u, 0x47u, 0x18u, 0x04u, 0x00u, 0x08u, 0xf8u, 0xb5u, 0x04u, 0x00u, 0x0fu, 0x00u, 0x16u, 0x00u, + 0x28u, 0x04u, 0x00u, 0x08u, 0x03u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xc0u, 0x18u, 0x03u, 0x68u, 0x00u, 0x2bu, + 0xfcu, 0xd1u, 0x70u, 0x47u, 0x28u, 0x04u, 0x00u, 0x08u, 0xf8u, 0xb5u, 0x04u, 0x00u, 0x0fu, 0x00u, 0x16u, 0x00u, 0x1du, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xe4u, 0xffu, 0x04u, 0x28u, 0xfau, 0xd8u, 0xe0u, 0x21u, 0x07u, 0x4bu, 0xc9u, 0x05u, 0x1bu, 0x68u, 0x0fu, 0x43u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x17u, 0x60u, 0xdau, 0x68u, 0xa2u, 0x18u, - 0x16u, 0x60u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0x25u, 0x60u, 0xf8u, 0xbdu, 0xc0u, 0x46u, 0x18u, 0x04u, 0x00u, 0x08u, + 0x16u, 0x60u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0x25u, 0x60u, 0xf8u, 0xbdu, 0xc0u, 0x46u, 0x28u, 0x04u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x04u, 0x00u, 0x0du, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xcau, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x03u, 0x4bu, 0x2du, 0x06u, 0x1bu, 0x68u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0x25u, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u, - 0x18u, 0x04u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xb9u, 0xffu, 0x06u, 0x28u, + 0x28u, 0x04u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xb9u, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x04u, 0x4bu, 0x1bu, 0x68u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0xc8u, 0x23u, 0xdbu, 0x05u, 0x23u, 0x60u, - 0x10u, 0xbdu, 0xc0u, 0x46u, 0x18u, 0x04u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, + 0x10u, 0xbdu, 0xc0u, 0x46u, 0x28u, 0x04u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa7u, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x04u, 0x4bu, 0x1bu, 0x68u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0xcau, 0x23u, - 0xdbu, 0x05u, 0x23u, 0x60u, 0x10u, 0xbdu, 0xc0u, 0x46u, 0x18u, 0x04u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x05u, 0x00u, + 0xdbu, 0x05u, 0x23u, 0x60u, 0x10u, 0xbdu, 0xc0u, 0x46u, 0x28u, 0x04u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x05u, 0x00u, 0x0cu, 0x00u, 0x16u, 0x00u, 0x28u, 0x00u, 0xffu, 0xf7u, 0x93u, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x05u, 0x4bu, 0x24u, 0x02u, 0x1bu, 0x68u, 0xdbu, 0x68u, 0xedu, 0x18u, 0xccu, 0x23u, 0xdbu, 0x05u, 0x1eu, 0x43u, 0x34u, 0x43u, - 0x2cu, 0x60u, 0x70u, 0xbdu, 0x18u, 0x04u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x05u, 0x00u, 0x0cu, 0x00u, 0x16u, 0x00u, + 0x2cu, 0x60u, 0x70u, 0xbdu, 0x28u, 0x04u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x05u, 0x00u, 0x0cu, 0x00u, 0x16u, 0x00u, 0x28u, 0x00u, 0xffu, 0xf7u, 0x7du, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x05u, 0x4bu, 0x24u, 0x02u, 0x1bu, 0x68u, 0xdbu, 0x68u, 0xedu, 0x18u, 0xd0u, 0x23u, 0xdbu, 0x05u, 0x1eu, 0x43u, 0x34u, 0x43u, 0x2cu, 0x60u, 0x70u, 0xbdu, - 0x18u, 0x04u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x04u, 0x00u, 0x0du, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x68u, 0xffu, + 0x28u, 0x04u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x04u, 0x00u, 0x0du, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x68u, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0xceu, 0x21u, 0x04u, 0x4bu, 0xc9u, 0x05u, 0x1bu, 0x68u, 0x29u, 0x43u, 0xdbu, 0x68u, - 0xe4u, 0x18u, 0x21u, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u, 0x18u, 0x04u, 0x00u, 0x08u, 0x00u, 0xb5u, 0x06u, 0x2au, - 0x68u, 0xd8u, 0x10u, 0x00u, 0x8bu, 0x60u, 0x01u, 0xf0u, 0x19u, 0xfeu, 0x04u, 0x1fu, 0x12u, 0x3bu, 0x2fu, 0x49u, + 0xe4u, 0x18u, 0x21u, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u, 0x28u, 0x04u, 0x00u, 0x08u, 0x00u, 0xb5u, 0x06u, 0x2au, + 0x68u, 0xd8u, 0x10u, 0x00u, 0x8bu, 0x60u, 0x01u, 0xf0u, 0x1du, 0xfeu, 0x04u, 0x1fu, 0x12u, 0x3bu, 0x2fu, 0x49u, 0x57u, 0x00u, 0x40u, 0x33u, 0x0bu, 0x61u, 0x69u, 0x23u, 0x4bu, 0x60u, 0x2fu, 0x4bu, 0x00u, 0x20u, 0xcbu, 0x62u, 0x40u, 0x23u, 0xcbu, 0x60u, 0x2cu, 0x3bu, 0x08u, 0x60u, 0x4bu, 0x61u, 0x4bu, 0x62u, 0x00u, 0xbdu, 0x40u, 0x33u, 0x0bu, 0x61u, 0x02u, 0x23u, 0x0bu, 0x60u, 0x68u, 0x33u, 0x4bu, 0x60u, 0x28u, 0x4bu, 0xcbu, 0x62u, 0x40u, 0x23u, @@ -1352,9 +1352,9 @@ const uint8_t cy_m0p_image[] = { 0x05u, 0x23u, 0x0bu, 0x60u, 0x66u, 0x33u, 0x4bu, 0x60u, 0x10u, 0x4bu, 0xcbu, 0x62u, 0x80u, 0x23u, 0xcbu, 0x60u, 0x40u, 0x3bu, 0x4bu, 0x61u, 0x20u, 0x3bu, 0xd4u, 0xe7u, 0x80u, 0x33u, 0x0bu, 0x61u, 0x06u, 0x23u, 0x0bu, 0x60u, 0x65u, 0x33u, 0x4bu, 0x60u, 0x0au, 0x4bu, 0xcbu, 0x62u, 0x80u, 0x23u, 0xcbu, 0x60u, 0x40u, 0x3bu, 0x4bu, 0x61u, - 0x24u, 0x3bu, 0xc6u, 0xe7u, 0x07u, 0x48u, 0xa9u, 0xe7u, 0x14u, 0x7cu, 0x00u, 0x10u, 0x48u, 0x7cu, 0x00u, 0x10u, - 0x28u, 0x7cu, 0x00u, 0x10u, 0xa8u, 0x7cu, 0x00u, 0x10u, 0x68u, 0x7cu, 0x00u, 0x10u, 0x28u, 0x7du, 0x00u, 0x10u, - 0xe8u, 0x7cu, 0x00u, 0x10u, 0x0bu, 0x00u, 0x32u, 0x00u, 0x10u, 0xb5u, 0x00u, 0x29u, 0x01u, 0xd1u, 0x07u, 0x48u, + 0x24u, 0x3bu, 0xc6u, 0xe7u, 0x07u, 0x48u, 0xa9u, 0xe7u, 0x1cu, 0x7cu, 0x00u, 0x10u, 0x50u, 0x7cu, 0x00u, 0x10u, + 0x30u, 0x7cu, 0x00u, 0x10u, 0xb0u, 0x7cu, 0x00u, 0x10u, 0x70u, 0x7cu, 0x00u, 0x10u, 0x30u, 0x7du, 0x00u, 0x10u, + 0xf0u, 0x7cu, 0x00u, 0x10u, 0x0bu, 0x00u, 0x32u, 0x00u, 0x10u, 0xb5u, 0x00u, 0x29u, 0x01u, 0xd1u, 0x07u, 0x48u, 0x10u, 0xbdu, 0x00u, 0x24u, 0x4bu, 0x69u, 0x8cu, 0x62u, 0x0cu, 0x62u, 0xa3u, 0x42u, 0xf7u, 0xd0u, 0xcau, 0x6au, 0x9bu, 0xb2u, 0x09u, 0x69u, 0xfeu, 0xf7u, 0x40u, 0xfeu, 0x20u, 0x00u, 0xf1u, 0xe7u, 0x0bu, 0x00u, 0x32u, 0x00u, 0xf0u, 0xb5u, 0x85u, 0xb0u, 0x04u, 0x00u, 0x0du, 0x1eu, 0x03u, 0x92u, 0x01u, 0x93u, 0x00u, 0xd1u, 0x95u, 0xe0u, @@ -1377,7 +1377,7 @@ const uint8_t cy_m0p_image[] = { 0xffu, 0xf7u, 0x92u, 0xfeu, 0x00u, 0x27u, 0x38u, 0x00u, 0x05u, 0xb0u, 0xf0u, 0xbdu, 0x02u, 0x9bu, 0x31u, 0x00u, 0x9fu, 0x1bu, 0x3au, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x99u, 0xfeu, 0x69u, 0x68u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x5fu, 0xfeu, 0x01u, 0x9bu, 0x00u, 0x26u, 0xdbu, 0x1bu, 0x01u, 0x93u, 0xb8u, 0xe7u, 0x02u, 0x4fu, 0xeau, 0xe7u, - 0x18u, 0x04u, 0x00u, 0x08u, 0x08u, 0x00u, 0x00u, 0x71u, 0x0bu, 0x00u, 0x32u, 0x00u, 0xf0u, 0xb5u, 0x85u, 0xb0u, + 0x28u, 0x04u, 0x00u, 0x08u, 0x08u, 0x00u, 0x00u, 0x71u, 0x0bu, 0x00u, 0x32u, 0x00u, 0xf0u, 0xb5u, 0x85u, 0xb0u, 0x04u, 0x00u, 0x0du, 0x1eu, 0x02u, 0x92u, 0x00u, 0xd1u, 0x7bu, 0xe0u, 0x00u, 0x2au, 0x00u, 0xd1u, 0x78u, 0xe0u, 0x8bu, 0x6au, 0x0au, 0x6au, 0x00u, 0x93u, 0x53u, 0x0fu, 0x03u, 0x93u, 0x70u, 0x23u, 0xceu, 0x68u, 0xd7u, 0x00u, 0x01u, 0x93u, 0x80u, 0x2eu, 0x01u, 0xd0u, 0x38u, 0x3bu, 0x01u, 0x93u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x4au, 0xfeu, @@ -1401,7 +1401,7 @@ const uint8_t cy_m0p_image[] = { 0xffu, 0xf7u, 0xc0u, 0xfdu, 0x28u, 0x00u, 0xffu, 0xf7u, 0x85u, 0xfdu, 0x00u, 0x20u, 0x70u, 0xbdu, 0x01u, 0x48u, 0xfcu, 0xe7u, 0xc0u, 0x46u, 0x0bu, 0x00u, 0x32u, 0x00u, 0xf0u, 0xb5u, 0x04u, 0x00u, 0xbfu, 0xb0u, 0x01u, 0x93u, 0x44u, 0xabu, 0x1fu, 0x78u, 0x0du, 0x00u, 0x16u, 0x00u, 0x00u, 0x21u, 0xc0u, 0x22u, 0x0eu, 0xa8u, 0x01u, 0xf0u, - 0x16u, 0xfeu, 0x30u, 0x22u, 0x00u, 0x21u, 0x02u, 0xa8u, 0x01u, 0xf0u, 0x11u, 0xfeu, 0x0eu, 0xabu, 0x3au, 0x00u, + 0x1au, 0xfeu, 0x30u, 0x22u, 0x00u, 0x21u, 0x02u, 0xa8u, 0x01u, 0xf0u, 0x15u, 0xfeu, 0x0eu, 0xabu, 0x3au, 0x00u, 0x02u, 0xa9u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x02u, 0xfeu, 0x00u, 0x28u, 0x18u, 0xd1u, 0x02u, 0xa9u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x7au, 0xfeu, 0x00u, 0x28u, 0x12u, 0xd1u, 0x33u, 0x00u, 0x2au, 0x00u, 0x02u, 0xa9u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x86u, 0xfeu, 0x00u, 0x28u, 0x0au, 0xd1u, 0x01u, 0x9au, 0x02u, 0xa9u, 0x20u, 0x00u, 0xffu, 0xf7u, @@ -1413,7 +1413,7 @@ const uint8_t cy_m0p_image[] = { 0x60u, 0x21u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0x5eu, 0xfbu, 0x40u, 0x21u, 0x0au, 0x4bu, 0x1au, 0x68u, 0x13u, 0x68u, 0xe3u, 0x18u, 0x18u, 0x68u, 0x08u, 0x40u, 0xfcu, 0xd1u, 0xd3u, 0x69u, 0xe3u, 0x18u, 0x1au, 0x68u, 0x04u, 0x9bu, 0x1au, 0x60u, 0xa1u, 0x23u, 0x9bu, 0x00u, 0xe0u, 0x50u, 0x70u, 0xbdu, 0xc0u, 0x46u, 0x00u, 0x00u, 0x03u, 0x31u, - 0x01u, 0x00u, 0x01u, 0x00u, 0x18u, 0x04u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x04u, 0x00u, 0xa0u, 0x20u, 0x1cu, 0x4du, + 0x01u, 0x00u, 0x01u, 0x00u, 0x28u, 0x04u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x04u, 0x00u, 0xa0u, 0x20u, 0x1cu, 0x4du, 0x80u, 0x00u, 0x25u, 0x50u, 0x3fu, 0x25u, 0x04u, 0x30u, 0xb0u, 0x26u, 0x25u, 0x50u, 0x00u, 0x25u, 0xb6u, 0x00u, 0xa5u, 0x51u, 0x08u, 0x36u, 0xa5u, 0x51u, 0x17u, 0x4fu, 0x08u, 0x36u, 0x01u, 0x35u, 0xa5u, 0x51u, 0x10u, 0x36u, 0xa7u, 0x51u, 0x40u, 0x3eu, 0xa1u, 0x51u, 0xa9u, 0x21u, 0x89u, 0x00u, 0x62u, 0x50u, 0xa2u, 0x22u, 0x92u, 0x00u, @@ -1421,20 +1421,20 @@ const uint8_t cy_m0p_image[] = { 0x0du, 0x4bu, 0x1du, 0x68u, 0x2bu, 0x68u, 0xe1u, 0x18u, 0x03u, 0x00u, 0x08u, 0x68u, 0xe6u, 0x58u, 0x16u, 0x42u, 0x07u, 0xd0u, 0xc0u, 0x0fu, 0xf9u, 0xd1u, 0xebu, 0x69u, 0xe3u, 0x18u, 0x1au, 0x68u, 0x05u, 0x9bu, 0x1au, 0x60u, 0x00u, 0xe0u, 0x06u, 0x48u, 0xa1u, 0x23u, 0x00u, 0x22u, 0x9bu, 0x00u, 0xe2u, 0x50u, 0xf0u, 0xbdu, 0xc0u, 0x46u, - 0x00u, 0x00u, 0x03u, 0x31u, 0x01u, 0x00u, 0x01u, 0x00u, 0x18u, 0x04u, 0x00u, 0x08u, 0x01u, 0x00u, 0x32u, 0x00u, + 0x00u, 0x00u, 0x03u, 0x31u, 0x01u, 0x00u, 0x01u, 0x00u, 0x28u, 0x04u, 0x00u, 0x08u, 0x01u, 0x00u, 0x32u, 0x00u, 0x07u, 0x4bu, 0x89u, 0x00u, 0x1au, 0x68u, 0x93u, 0x6bu, 0x12u, 0x69u, 0xc3u, 0x18u, 0x89u, 0x18u, 0x08u, 0x18u, 0x1bu, 0x68u, 0x00u, 0x68u, 0x80u, 0x00u, 0x80u, 0x0cu, 0x80u, 0x00u, 0xc0u, 0x18u, 0x70u, 0x47u, 0xc0u, 0x46u, - 0x18u, 0x04u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x06u, 0x4cu, 0x24u, 0x68u, 0x29u, 0x34u, 0x24u, 0x78u, 0x1fu, 0x2cu, + 0x28u, 0x04u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x06u, 0x4cu, 0x24u, 0x68u, 0x29u, 0x34u, 0x24u, 0x78u, 0x1fu, 0x2cu, 0x02u, 0xd8u, 0xfeu, 0xf7u, 0x47u, 0xfbu, 0x10u, 0xbdu, 0xfeu, 0xf7u, 0x16u, 0xfcu, 0xfbu, 0xe7u, 0xc0u, 0x46u, - 0x28u, 0x06u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x1fu, 0x24u, 0x95u, 0x00u, 0x13u, 0x05u, 0x09u, 0x4au, 0xadu, 0x0cu, + 0x38u, 0x06u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x1fu, 0x24u, 0x95u, 0x00u, 0x13u, 0x05u, 0x09u, 0x4au, 0xadu, 0x0cu, 0x12u, 0x68u, 0x89u, 0x06u, 0x29u, 0x32u, 0x12u, 0x78u, 0x1bu, 0x0du, 0x94u, 0x42u, 0xa4u, 0x41u, 0x64u, 0x42u, 0x0cu, 0x34u, 0xa5u, 0x40u, 0x0bu, 0x43u, 0x2bu, 0x43u, 0x80u, 0x22u, 0x00u, 0x21u, 0xfeu, 0xf7u, 0x6cu, 0xf8u, - 0x70u, 0xbdu, 0xc0u, 0x46u, 0x28u, 0x06u, 0x00u, 0x08u, 0x09u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xc0u, 0x18u, + 0x70u, 0xbdu, 0xc0u, 0x46u, 0x38u, 0x06u, 0x00u, 0x08u, 0x09u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xc0u, 0x18u, 0x08u, 0x4bu, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x04u, 0xd8u, 0x80u, 0x23u, 0x02u, 0x68u, 0x1au, 0x42u, 0xfcu, 0xd1u, 0x70u, 0x47u, 0x03u, 0x68u, 0x00u, 0x2bu, 0xfcu, 0xd1u, 0xfau, 0xe7u, 0xc0u, 0x46u, - 0x18u, 0x04u, 0x00u, 0x08u, 0x28u, 0x06u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x13u, 0x00u, 0x06u, 0x4au, 0x14u, 0x68u, + 0x28u, 0x04u, 0x00u, 0x08u, 0x38u, 0x06u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x13u, 0x00u, 0x06u, 0x4au, 0x14u, 0x68u, 0x29u, 0x34u, 0x22u, 0x78u, 0x1fu, 0x2au, 0x03u, 0xd8u, 0x00u, 0x22u, 0xfeu, 0xf7u, 0x21u, 0xfbu, 0x10u, 0xbdu, - 0x00u, 0x22u, 0xfeu, 0xf7u, 0x0fu, 0xfcu, 0xfau, 0xe7u, 0x28u, 0x06u, 0x00u, 0x08u, 0xf7u, 0xb5u, 0x04u, 0x00u, + 0x00u, 0x22u, 0xfeu, 0xf7u, 0x0fu, 0xfcu, 0xfau, 0xe7u, 0x38u, 0x06u, 0x00u, 0x08u, 0xf7u, 0xb5u, 0x04u, 0x00u, 0x00u, 0x93u, 0x0eu, 0x00u, 0x01u, 0x92u, 0xffu, 0xf7u, 0xcfu, 0xffu, 0x1bu, 0x4bu, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x2du, 0xd8u, 0x19u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x69u, 0xe3u, 0x18u, 0x1fu, 0x68u, 0x5du, 0x68u, 0x31u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x83u, 0xffu, 0x06u, 0x00u, 0x00u, 0x9au, 0x01u, 0x00u, @@ -1442,48 +1442,48 @@ const uint8_t cy_m0p_image[] = { 0x01u, 0x9au, 0x07u, 0x33u, 0xdbu, 0x08u, 0x9bu, 0xb2u, 0x31u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x82u, 0xffu, 0x09u, 0x4bu, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x09u, 0xd8u, 0x3au, 0x00u, 0x00u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x87u, 0xffu, 0x2au, 0x00u, 0x01u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x82u, 0xffu, - 0xf7u, 0xbdu, 0x00u, 0x25u, 0x2fu, 0x00u, 0xd4u, 0xe7u, 0x28u, 0x06u, 0x00u, 0x08u, 0x18u, 0x04u, 0x00u, 0x08u, + 0xf7u, 0xbdu, 0x00u, 0x25u, 0x2fu, 0x00u, 0xd4u, 0xe7u, 0x38u, 0x06u, 0x00u, 0x08u, 0x28u, 0x04u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x85u, 0xb0u, 0x03u, 0x93u, 0x04u, 0x00u, 0x01u, 0x91u, 0x02u, 0x92u, 0xffu, 0xf7u, 0x8cu, 0xffu, 0x16u, 0x4eu, 0x33u, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x23u, 0xd8u, 0x14u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x69u, 0xe3u, 0x18u, 0x1fu, 0x68u, 0x5du, 0x68u, 0x02u, 0x99u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x40u, 0xffu, 0x03u, 0x9bu, 0x02u, 0x00u, 0x07u, 0x33u, 0xdbu, 0x08u, 0x9bu, 0xb2u, 0x01u, 0x99u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x49u, 0xffu, 0x33u, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x09u, 0xd8u, 0x3au, 0x00u, 0x00u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x4fu, 0xffu, 0x2au, 0x00u, 0x01u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x4au, 0xffu, - 0x05u, 0xb0u, 0xf0u, 0xbdu, 0x00u, 0x25u, 0x2fu, 0x00u, 0xdeu, 0xe7u, 0xc0u, 0x46u, 0x28u, 0x06u, 0x00u, 0x08u, - 0x18u, 0x04u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, 0x0bu, 0x00u, 0x3fu, 0x22u, 0x00u, 0x21u, 0xfdu, 0xf7u, + 0x05u, 0xb0u, 0xf0u, 0xbdu, 0x00u, 0x25u, 0x2fu, 0x00u, 0xdeu, 0xe7u, 0xc0u, 0x46u, 0x38u, 0x06u, 0x00u, 0x08u, + 0x28u, 0x04u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, 0x0bu, 0x00u, 0x3fu, 0x22u, 0x00u, 0x21u, 0xfdu, 0xf7u, 0xbbu, 0xffu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x50u, 0xffu, 0x03u, 0x4bu, 0x1bu, 0x68u, 0xdbu, 0x6bu, 0xe4u, 0x18u, - 0x20u, 0x68u, 0x40u, 0x07u, 0xc0u, 0x0fu, 0x10u, 0xbdu, 0x18u, 0x04u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, + 0x20u, 0x68u, 0x40u, 0x07u, 0xc0u, 0x0fu, 0x10u, 0xbdu, 0x28u, 0x04u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, 0x13u, 0x01u, 0x0bu, 0x43u, 0x3du, 0x22u, 0x00u, 0x21u, 0xfdu, 0xf7u, 0xa6u, 0xffu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x3bu, 0xffu, 0x04u, 0x4bu, 0x1bu, 0x68u, 0xdbu, 0x6bu, 0xe4u, 0x18u, 0x20u, 0x68u, 0x40u, 0x07u, 0xc0u, 0x0fu, - 0x10u, 0xbdu, 0xc0u, 0x46u, 0x18u, 0x04u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, 0x13u, 0x01u, 0x0bu, 0x43u, + 0x10u, 0xbdu, 0xc0u, 0x46u, 0x28u, 0x04u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, 0x13u, 0x01u, 0x0bu, 0x43u, 0x3du, 0x22u, 0x00u, 0x21u, 0xfdu, 0xf7u, 0x90u, 0xffu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x25u, 0xffu, 0x04u, 0x4bu, 0x1bu, 0x68u, 0xdbu, 0x6bu, 0xe4u, 0x18u, 0x01u, 0x23u, 0x20u, 0x68u, 0x18u, 0x40u, 0x10u, 0xbdu, 0xc0u, 0x46u, - 0x18u, 0x04u, 0x00u, 0x08u, 0x08u, 0x4bu, 0x10u, 0xb5u, 0x1au, 0x68u, 0x8bu, 0x00u, 0x12u, 0x69u, 0x9bu, 0x18u, + 0x28u, 0x04u, 0x00u, 0x08u, 0x08u, 0x4bu, 0x10u, 0xb5u, 0x1au, 0x68u, 0x8bu, 0x00u, 0x12u, 0x69u, 0x9bu, 0x18u, 0xc3u, 0x18u, 0x1cu, 0x68u, 0xffu, 0xf7u, 0xd4u, 0xfeu, 0xe1u, 0x04u, 0xc9u, 0x0cu, 0x08u, 0x31u, 0xc9u, 0x08u, - 0xfeu, 0xf7u, 0x3eu, 0xf9u, 0x10u, 0xbdu, 0xc0u, 0x46u, 0x18u, 0x04u, 0x00u, 0x08u, 0x00u, 0x28u, 0x07u, 0xdbu, + 0xfeu, 0xf7u, 0x3eu, 0xf9u, 0x10u, 0xbdu, 0xc0u, 0x46u, 0x28u, 0x04u, 0x00u, 0x08u, 0x00u, 0x28u, 0x07u, 0xdbu, 0x1fu, 0x23u, 0xc0u, 0x22u, 0x18u, 0x40u, 0x1eu, 0x3bu, 0x83u, 0x40u, 0x02u, 0x49u, 0x52u, 0x00u, 0x8bu, 0x50u, 0x70u, 0x47u, 0xc0u, 0x46u, 0x00u, 0xe1u, 0x00u, 0xe0u, 0x30u, 0xb5u, 0xf8u, 0x25u, 0x0fu, 0x4bu, 0x10u, 0x4au, 0x18u, 0x68u, 0x14u, 0x68u, 0x43u, 0x6au, 0x22u, 0x6cu, 0x6du, 0x03u, 0x9au, 0x18u, 0x11u, 0x68u, 0x29u, 0x40u, 0x10u, 0xd0u, 0x11u, 0x60u, 0x22u, 0x6cu, 0x9bu, 0x18u, 0x1bu, 0x68u, 0x0au, 0x4bu, 0x1au, 0x68u, 0x53u, 0x1cu, 0xd9u, 0x7fu, 0x00u, 0x29u, 0x07u, 0xd1u, 0x41u, 0x6au, 0x08u, 0x6au, 0x49u, 0x6au, 0x50u, 0x62u, 0x91u, 0x62u, - 0x01u, 0x22u, 0xdau, 0x77u, 0x30u, 0xbdu, 0x00u, 0x22u, 0xfbu, 0xe7u, 0xc0u, 0x46u, 0x28u, 0x06u, 0x00u, 0x08u, - 0x18u, 0x04u, 0x00u, 0x08u, 0x24u, 0x04u, 0x00u, 0x08u, 0x00u, 0x22u, 0x70u, 0xb5u, 0x04u, 0x00u, 0x03u, 0x68u, + 0x01u, 0x22u, 0xdau, 0x77u, 0x30u, 0xbdu, 0x00u, 0x22u, 0xfbu, 0xe7u, 0xc0u, 0x46u, 0x38u, 0x06u, 0x00u, 0x08u, + 0x28u, 0x04u, 0x00u, 0x08u, 0x34u, 0x04u, 0x00u, 0x08u, 0x00u, 0x22u, 0x70u, 0xb5u, 0x04u, 0x00u, 0x03u, 0x68u, 0x0du, 0x00u, 0x0bu, 0x60u, 0x43u, 0x68u, 0x4bu, 0x60u, 0x83u, 0x69u, 0x8bu, 0x60u, 0xc3u, 0x69u, 0xcbu, 0x60u, 0x4bu, 0x1cu, 0xdau, 0x77u, 0x03u, 0x8cu, 0x0bu, 0x82u, 0x03u, 0x8du, 0x0bu, 0x83u, 0xfdu, 0xf7u, 0xceu, 0xffu, - 0xa1u, 0x69u, 0x00u, 0x29u, 0x00u, 0xd1u, 0x20u, 0x49u, 0x20u, 0x00u, 0x20u, 0x30u, 0x00u, 0xf0u, 0xc0u, 0xfeu, + 0xa1u, 0x69u, 0x00u, 0x29u, 0x00u, 0xd1u, 0x20u, 0x49u, 0x20u, 0x00u, 0x20u, 0x30u, 0x00u, 0xf0u, 0xc4u, 0xfeu, 0x20u, 0x22u, 0xa3u, 0x5eu, 0x00u, 0x2bu, 0x06u, 0xdbu, 0x1fu, 0x22u, 0x13u, 0x40u, 0x1eu, 0x3au, 0x9au, 0x40u, 0x13u, 0x00u, 0x1au, 0x4au, 0x13u, 0x60u, 0x80u, 0x22u, 0x21u, 0x68u, 0x52u, 0x02u, 0x8au, 0x40u, 0x18u, 0x4eu, 0x61u, 0x68u, 0x33u, 0x68u, 0x49u, 0x01u, 0x1bu, 0x6au, 0x5bu, 0x18u, 0x16u, 0x49u, 0x5bu, 0x18u, 0xe1u, 0x69u, - 0x1au, 0x60u, 0x00u, 0x29u, 0x00u, 0xd1u, 0x14u, 0x49u, 0x20u, 0x00u, 0x28u, 0x30u, 0x00u, 0xf0u, 0xa0u, 0xfeu, + 0x1au, 0x60u, 0x00u, 0x29u, 0x00u, 0xd1u, 0x14u, 0x49u, 0x20u, 0x00u, 0x28u, 0x30u, 0x00u, 0xf0u, 0xa4u, 0xfeu, 0x28u, 0x23u, 0xe0u, 0x5eu, 0xffu, 0xf7u, 0x8au, 0xffu, 0x28u, 0x22u, 0xa3u, 0x5eu, 0x00u, 0x2bu, 0x06u, 0xdbu, 0x1fu, 0x22u, 0x13u, 0x40u, 0x1eu, 0x3au, 0x9au, 0x40u, 0x13u, 0x00u, 0x08u, 0x4au, 0x13u, 0x60u, 0x0bu, 0x4au, 0x33u, 0x68u, 0x12u, 0x68u, 0x5bu, 0x6au, 0x92u, 0x6cu, 0x00u, 0x20u, 0x9bu, 0x18u, 0xf8u, 0x22u, 0x52u, 0x03u, 0x1au, 0x60u, 0x07u, 0x4bu, 0x1du, 0x60u, 0x70u, 0xbdu, 0x25u, 0x5fu, 0x00u, 0x10u, 0x00u, 0xe1u, 0x00u, 0xe0u, - 0x28u, 0x06u, 0x00u, 0x08u, 0x08u, 0x10u, 0x00u, 0x00u, 0xb9u, 0x59u, 0x00u, 0x10u, 0x18u, 0x04u, 0x00u, 0x08u, - 0x24u, 0x04u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x07u, 0x4bu, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1au, 0x78u, 0x06u, 0x4bu, + 0x38u, 0x06u, 0x00u, 0x08u, 0x08u, 0x10u, 0x00u, 0x00u, 0xb9u, 0x59u, 0x00u, 0x10u, 0x28u, 0x04u, 0x00u, 0x08u, + 0x34u, 0x04u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x07u, 0x4bu, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1au, 0x78u, 0x06u, 0x4bu, 0x1fu, 0x2au, 0x04u, 0xd8u, 0x05u, 0x4au, 0x1au, 0x60u, 0xffu, 0xf7u, 0x8eu, 0xffu, 0x10u, 0xbdu, 0x04u, 0x4au, - 0xf9u, 0xe7u, 0xc0u, 0x46u, 0x28u, 0x06u, 0x00u, 0x08u, 0x20u, 0x04u, 0x00u, 0x08u, 0x68u, 0x7du, 0x00u, 0x10u, - 0xc0u, 0x7du, 0x00u, 0x10u, 0xf0u, 0xb5u, 0xb4u, 0x4bu, 0x85u, 0xb0u, 0x1cu, 0x68u, 0x00u, 0x2cu, 0x1eu, 0xd0u, + 0xf9u, 0xe7u, 0xc0u, 0x46u, 0x38u, 0x06u, 0x00u, 0x08u, 0x30u, 0x04u, 0x00u, 0x08u, 0x70u, 0x7du, 0x00u, 0x10u, + 0xc8u, 0x7du, 0x00u, 0x10u, 0xf0u, 0xb5u, 0xb4u, 0x4bu, 0x85u, 0xb0u, 0x1cu, 0x68u, 0x00u, 0x2cu, 0x1eu, 0xd0u, 0xb2u, 0x4bu, 0xb3u, 0x4du, 0x63u, 0x60u, 0x2bu, 0x68u, 0x5fu, 0x6au, 0x23u, 0x78u, 0x01u, 0x2bu, 0x18u, 0xd1u, 0x38u, 0x00u, 0xfeu, 0xf7u, 0x1fu, 0xf8u, 0x60u, 0x60u, 0x00u, 0x23u, 0xabu, 0x4au, 0xe1u, 0x69u, 0x13u, 0x60u, 0x2bu, 0x68u, 0x1au, 0x00u, 0xacu, 0x32u, 0x10u, 0x88u, 0x22u, 0x69u, 0x1bu, 0x6au, 0x50u, 0x43u, 0xc0u, 0x18u, @@ -1528,9 +1528,9 @@ const uint8_t cy_m0p_image[] = { 0x00u, 0x93u, 0xd3u, 0x69u, 0x40u, 0x6au, 0x52u, 0x69u, 0xb0u, 0x47u, 0x99u, 0xe7u, 0x96u, 0x69u, 0xedu, 0xe7u, 0xd6u, 0x69u, 0x28u, 0x68u, 0x00u, 0x2eu, 0x00u, 0xd1u, 0xedu, 0xe6u, 0xa1u, 0x6au, 0x03u, 0x91u, 0x8bu, 0x6au, 0x02u, 0x93u, 0x4bu, 0x6au, 0x01u, 0x93u, 0x0bu, 0x6au, 0x00u, 0x93u, 0xcbu, 0x69u, 0x8au, 0x69u, 0x40u, 0x6au, - 0x49u, 0x69u, 0xb0u, 0x47u, 0x84u, 0xe7u, 0xc0u, 0x46u, 0x28u, 0x04u, 0x00u, 0x08u, 0x09u, 0x00u, 0x32u, 0x00u, - 0x28u, 0x06u, 0x00u, 0x08u, 0x18u, 0x04u, 0x00u, 0x08u, 0x0au, 0x00u, 0x32u, 0x00u, 0x20u, 0x04u, 0x00u, 0x08u, - 0x24u, 0x04u, 0x00u, 0x08u, 0x01u, 0x00u, 0x32u, 0x00u, 0x56u, 0x6au, 0x28u, 0x68u, 0x00u, 0x2eu, 0x00u, 0xd1u, + 0x49u, 0x69u, 0xb0u, 0x47u, 0x84u, 0xe7u, 0xc0u, 0x46u, 0x38u, 0x04u, 0x00u, 0x08u, 0x09u, 0x00u, 0x32u, 0x00u, + 0x38u, 0x06u, 0x00u, 0x08u, 0x28u, 0x04u, 0x00u, 0x08u, 0x0au, 0x00u, 0x32u, 0x00u, 0x30u, 0x04u, 0x00u, 0x08u, + 0x34u, 0x04u, 0x00u, 0x08u, 0x01u, 0x00u, 0x32u, 0x00u, 0x56u, 0x6au, 0x28u, 0x68u, 0x00u, 0x2eu, 0x00u, 0xd1u, 0xc9u, 0xe6u, 0xa1u, 0x6au, 0x0bu, 0x7bu, 0x00u, 0x93u, 0x8bu, 0x68u, 0x4au, 0x68u, 0x40u, 0x6au, 0x09u, 0x68u, 0xb0u, 0x47u, 0x65u, 0xe7u, 0x96u, 0x6au, 0x28u, 0x68u, 0x00u, 0x2eu, 0x00u, 0xd1u, 0xbbu, 0xe6u, 0xa1u, 0x6au, 0x0bu, 0x7bu, 0x02u, 0x93u, 0x4bu, 0x69u, 0x01u, 0x93u, 0x0bu, 0x69u, 0x00u, 0x93u, 0x4bu, 0x68u, 0x0au, 0x68u, @@ -1554,10 +1554,10 @@ const uint8_t cy_m0p_image[] = { 0x36u, 0x0cu, 0x91u, 0x40u, 0xb1u, 0x42u, 0x13u, 0xd1u, 0x80u, 0x26u, 0x09u, 0x04u, 0x76u, 0x01u, 0x99u, 0x51u, 0xacu, 0x35u, 0x9bu, 0x59u, 0x2bu, 0x88u, 0x0au, 0x49u, 0x5au, 0x43u, 0x10u, 0x18u, 0x00u, 0xf0u, 0xe2u, 0xf8u, 0x00u, 0x28u, 0x05u, 0xd1u, 0x23u, 0x68u, 0x9bu, 0x68u, 0x00u, 0x2bu, 0x01u, 0xd1u, 0xffu, 0xf7u, 0xcau, 0xfdu, - 0x70u, 0xbdu, 0xc0u, 0x46u, 0x24u, 0x04u, 0x00u, 0x08u, 0x28u, 0x06u, 0x00u, 0x08u, 0x0cu, 0x10u, 0x00u, 0x00u, - 0x28u, 0x04u, 0x00u, 0x08u, 0x01u, 0x4bu, 0x18u, 0x60u, 0x70u, 0x47u, 0xc0u, 0x46u, 0x28u, 0x06u, 0x00u, 0x08u, + 0x70u, 0xbdu, 0xc0u, 0x46u, 0x34u, 0x04u, 0x00u, 0x08u, 0x38u, 0x06u, 0x00u, 0x08u, 0x0cu, 0x10u, 0x00u, 0x00u, + 0x38u, 0x04u, 0x00u, 0x08u, 0x01u, 0x4bu, 0x18u, 0x60u, 0x70u, 0x47u, 0xc0u, 0x46u, 0x38u, 0x06u, 0x00u, 0x08u, 0x04u, 0x4bu, 0x1bu, 0x68u, 0x1au, 0x00u, 0xacu, 0x32u, 0x12u, 0x88u, 0x1bu, 0x6au, 0x50u, 0x43u, 0xc0u, 0x18u, - 0x70u, 0x47u, 0xc0u, 0x46u, 0x28u, 0x06u, 0x00u, 0x08u, 0x1du, 0x4bu, 0x98u, 0x42u, 0x0fu, 0xd0u, 0x10u, 0xd8u, + 0x70u, 0x47u, 0xc0u, 0x46u, 0x38u, 0x06u, 0x00u, 0x08u, 0x1du, 0x4bu, 0x98u, 0x42u, 0x0fu, 0xd0u, 0x10u, 0xd8u, 0x40u, 0x28u, 0x2fu, 0xd0u, 0x05u, 0xd8u, 0x00u, 0x28u, 0x30u, 0xd0u, 0x10u, 0x28u, 0x28u, 0xd0u, 0x19u, 0x48u, 0x1eu, 0xe0u, 0x80u, 0x28u, 0x28u, 0xd0u, 0x80u, 0x23u, 0x5bu, 0x00u, 0x98u, 0x42u, 0xf7u, 0xd1u, 0x14u, 0x48u, 0x16u, 0xe0u, 0x15u, 0x4bu, 0x98u, 0x42u, 0x14u, 0xd0u, 0x08u, 0xd8u, 0xa0u, 0x23u, 0x1bu, 0x06u, 0x98u, 0x42u, @@ -1571,41 +1571,41 @@ const uint8_t cy_m0p_image[] = { 0x05u, 0x00u, 0x52u, 0x00u, 0x10u, 0xb5u, 0x00u, 0x20u, 0xffu, 0xf7u, 0x9au, 0xffu, 0x0au, 0x4bu, 0x1cu, 0x68u, 0x23u, 0x00u, 0xb0u, 0x33u, 0x1bu, 0x68u, 0xc0u, 0x18u, 0x03u, 0x68u, 0x00u, 0x2bu, 0x0au, 0xdbu, 0x07u, 0x4bu, 0x18u, 0x68u, 0xffu, 0xf7u, 0x99u, 0xffu, 0x01u, 0x22u, 0x63u, 0x68u, 0x9au, 0x60u, 0x9au, 0x68u, 0x00u, 0x2au, - 0xfcu, 0xd1u, 0x10u, 0xbdu, 0x02u, 0x48u, 0xfcu, 0xe7u, 0x28u, 0x06u, 0x00u, 0x08u, 0x2cu, 0x04u, 0x00u, 0x08u, + 0xfcu, 0xd1u, 0x10u, 0xbdu, 0x02u, 0x48u, 0xfcu, 0xe7u, 0x38u, 0x06u, 0x00u, 0x08u, 0x3cu, 0x04u, 0x00u, 0x08u, 0x02u, 0x00u, 0x50u, 0x00u, 0x0du, 0x4bu, 0x10u, 0xb5u, 0x18u, 0x60u, 0x00u, 0x28u, 0x04u, 0xd0u, 0xfeu, 0x23u, 0x5bu, 0x42u, 0x03u, 0x80u, 0x00u, 0x23u, 0x43u, 0x80u, 0x09u, 0x4bu, 0x1bu, 0x68u, 0x1au, 0x00u, 0x4cu, 0x32u, 0x12u, 0x78u, 0x00u, 0x2au, 0x08u, 0xd0u, 0x4du, 0x33u, 0x1bu, 0x78u, 0x00u, 0x2bu, 0x04u, 0xd0u, 0x02u, 0x22u, - 0x04u, 0x49u, 0x00u, 0x20u, 0x00u, 0xf0u, 0xe0u, 0xf8u, 0x10u, 0xbdu, 0xc0u, 0x46u, 0x3cu, 0x04u, 0x00u, 0x08u, - 0x28u, 0x06u, 0x00u, 0x08u, 0x49u, 0x01u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x02u, 0x48u, 0xffu, 0xf7u, 0xdau, 0xffu, - 0x10u, 0xbdu, 0xc0u, 0x46u, 0xb8u, 0x03u, 0x00u, 0x08u, 0x06u, 0x4bu, 0x1bu, 0x68u, 0xb0u, 0x33u, 0x1bu, 0x68u, + 0x04u, 0x49u, 0x00u, 0x20u, 0x00u, 0xf0u, 0xe0u, 0xf8u, 0x10u, 0xbdu, 0xc0u, 0x46u, 0x4cu, 0x04u, 0x00u, 0x08u, + 0x38u, 0x06u, 0x00u, 0x08u, 0x59u, 0x01u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x02u, 0x48u, 0xffu, 0xf7u, 0xdau, 0xffu, + 0x10u, 0xbdu, 0xc0u, 0x46u, 0xc8u, 0x03u, 0x00u, 0x08u, 0x06u, 0x4bu, 0x1bu, 0x68u, 0xb0u, 0x33u, 0x1bu, 0x68u, 0xc3u, 0x18u, 0x1bu, 0x68u, 0x00u, 0x2bu, 0x03u, 0xdau, 0x89u, 0xb2u, 0x41u, 0x60u, 0x00u, 0x20u, 0x70u, 0x47u, - 0x01u, 0x48u, 0xfcu, 0xe7u, 0x28u, 0x06u, 0x00u, 0x08u, 0x01u, 0x00u, 0x8au, 0x00u, 0x03u, 0x68u, 0x00u, 0x2bu, + 0x01u, 0x48u, 0xfcu, 0xe7u, 0x38u, 0x06u, 0x00u, 0x08u, 0x01u, 0x00u, 0x8au, 0x00u, 0x03u, 0x68u, 0x00u, 0x2bu, 0x04u, 0xdau, 0x89u, 0xb2u, 0xc2u, 0x60u, 0x81u, 0x60u, 0x00u, 0x20u, 0x70u, 0x47u, 0x00u, 0x48u, 0xfcu, 0xe7u, 0x01u, 0x00u, 0x8au, 0x00u, 0x06u, 0x4bu, 0x1bu, 0x68u, 0xb0u, 0x33u, 0x1bu, 0x68u, 0xc3u, 0x18u, 0x1bu, 0x68u, 0x00u, 0x2bu, 0x03u, 0xdau, 0xc3u, 0x68u, 0x00u, 0x20u, 0x0bu, 0x60u, 0x70u, 0x47u, 0x01u, 0x48u, 0xfcu, 0xe7u, - 0x28u, 0x06u, 0x00u, 0x08u, 0x01u, 0x00u, 0x8au, 0x00u, 0x02u, 0x4bu, 0x1au, 0x68u, 0x00u, 0x2au, 0x00u, 0xd1u, - 0x18u, 0x60u, 0x70u, 0x47u, 0x40u, 0x04u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x2cu, 0x24u, 0x60u, 0x43u, 0x15u, 0x4cu, + 0x38u, 0x06u, 0x00u, 0x08u, 0x01u, 0x00u, 0x8au, 0x00u, 0x02u, 0x4bu, 0x1au, 0x68u, 0x00u, 0x2au, 0x00u, 0xd1u, + 0x18u, 0x60u, 0x70u, 0x47u, 0x50u, 0x04u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x2cu, 0x24u, 0x60u, 0x43u, 0x15u, 0x4cu, 0x1fu, 0x00u, 0x24u, 0x68u, 0x1du, 0x0au, 0x20u, 0x18u, 0xffu, 0x24u, 0x25u, 0x40u, 0x27u, 0x40u, 0x12u, 0x4cu, 0x1bu, 0x0cu, 0x26u, 0x68u, 0x07u, 0x60u, 0x34u, 0x6au, 0x45u, 0x60u, 0x83u, 0x60u, 0xacu, 0x36u, 0x36u, 0x88u, 0x77u, 0x43u, 0x3fu, 0x19u, 0x07u, 0x61u, 0x2fu, 0x00u, 0x80u, 0x37u, 0x6du, 0x01u, 0x7fu, 0x01u, 0xe7u, 0x19u, 0x64u, 0x19u, 0x0au, 0x4du, 0x47u, 0x61u, 0x1fu, 0x04u, 0x3bu, 0x43u, 0x64u, 0x19u, 0x23u, 0x60u, 0x00u, 0x23u, 0x83u, 0x61u, 0x05u, 0x9bu, 0xc2u, 0x61u, 0x01u, 0x62u, 0x00u, 0x2bu, 0x01u, 0xd0u, 0x1bu, 0x88u, 0x83u, 0x81u, - 0xf0u, 0xbdu, 0xc0u, 0x46u, 0x40u, 0x04u, 0x00u, 0x08u, 0x28u, 0x06u, 0x00u, 0x08u, 0x08u, 0x10u, 0x00u, 0x00u, + 0xf0u, 0xbdu, 0xc0u, 0x46u, 0x50u, 0x04u, 0x00u, 0x08u, 0x38u, 0x06u, 0x00u, 0x08u, 0x08u, 0x10u, 0x00u, 0x00u, 0xf0u, 0xb5u, 0x83u, 0x68u, 0x85u, 0xb0u, 0x02u, 0xadu, 0x2bu, 0x80u, 0x15u, 0x4bu, 0x02u, 0x68u, 0x1bu, 0x68u, 0x06u, 0x6au, 0x9bu, 0x8eu, 0x47u, 0x6au, 0x9bu, 0x18u, 0xabu, 0x70u, 0x43u, 0x68u, 0x00u, 0x95u, 0x82u, 0x6au, 0xc1u, 0x6au, 0x04u, 0x00u, 0x03u, 0x93u, 0x03u, 0x69u, 0xc0u, 0x68u, 0xffu, 0xf7u, 0xb5u, 0xffu, 0x00u, 0x21u, 0x3bu, 0x00u, 0x0au, 0x00u, 0x00u, 0x91u, 0x30u, 0x00u, 0xffu, 0xf7u, 0xaeu, 0xffu, 0x21u, 0x6bu, 0x28u, 0x00u, - 0x00u, 0xf0u, 0xdeu, 0xfau, 0x00u, 0x22u, 0xabu, 0x5eu, 0x00u, 0x2bu, 0x06u, 0xdbu, 0x1fu, 0x22u, 0x13u, 0x40u, + 0x00u, 0xf0u, 0xe2u, 0xfau, 0x00u, 0x22u, 0xabu, 0x5eu, 0x00u, 0x2bu, 0x06u, 0xdbu, 0x1fu, 0x22u, 0x13u, 0x40u, 0x1eu, 0x3au, 0x9au, 0x40u, 0x13u, 0x00u, 0x03u, 0x4au, 0x13u, 0x60u, 0x05u, 0xb0u, 0xf0u, 0xbdu, 0xc0u, 0x46u, - 0x28u, 0x06u, 0x00u, 0x08u, 0x00u, 0xe1u, 0x00u, 0xe0u, 0xf7u, 0xb5u, 0x2cu, 0x25u, 0x13u, 0x4cu, 0x68u, 0x43u, + 0x38u, 0x06u, 0x00u, 0x08u, 0x00u, 0xe1u, 0x00u, 0xe0u, 0xf7u, 0xb5u, 0x2cu, 0x25u, 0x13u, 0x4cu, 0x68u, 0x43u, 0x26u, 0x68u, 0x69u, 0x43u, 0x34u, 0x18u, 0x25u, 0x69u, 0x01u, 0x93u, 0x71u, 0x18u, 0x00u, 0x2du, 0x19u, 0xd0u, 0x88u, 0x69u, 0x00u, 0x28u, 0x18u, 0xd1u, 0x2eu, 0x68u, 0x00u, 0x2eu, 0x15u, 0xdau, 0x67u, 0x68u, 0x01u, 0x24u, 0x26u, 0x00u, 0x4bu, 0x68u, 0x9eu, 0x40u, 0xb4u, 0x46u, 0x13u, 0x68u, 0x9eu, 0xb2u, 0x63u, 0x46u, 0x1bu, 0x04u, 0x1eu, 0x43u, 0x16u, 0x60u, 0xeau, 0x60u, 0x8cu, 0x61u, 0xbcu, 0x40u, 0x01u, 0x9bu, 0xa4u, 0xb2u, 0x4bu, 0x62u, - 0xacu, 0x60u, 0xfeu, 0xbdu, 0x02u, 0x48u, 0xfcu, 0xe7u, 0x02u, 0x48u, 0xfau, 0xe7u, 0x40u, 0x04u, 0x00u, 0x08u, + 0xacu, 0x60u, 0xfeu, 0xbdu, 0x02u, 0x48u, 0xfcu, 0xe7u, 0x02u, 0x48u, 0xfau, 0xe7u, 0x50u, 0x04u, 0x00u, 0x08u, 0x04u, 0x02u, 0x8au, 0x00u, 0x07u, 0x02u, 0x8au, 0x00u, 0x2cu, 0x23u, 0x43u, 0x43u, 0x06u, 0x48u, 0x00u, 0x68u, 0xc0u, 0x18u, 0xc3u, 0x69u, 0x93u, 0x42u, 0x04u, 0xd9u, 0x03u, 0x6au, 0x00u, 0x20u, 0x92u, 0x00u, 0xd1u, 0x50u, - 0x70u, 0x47u, 0x02u, 0x48u, 0xfcu, 0xe7u, 0xc0u, 0x46u, 0x40u, 0x04u, 0x00u, 0x08u, 0x0au, 0x02u, 0x8au, 0x00u, + 0x70u, 0x47u, 0x02u, 0x48u, 0xfcu, 0xe7u, 0xc0u, 0x46u, 0x50u, 0x04u, 0x00u, 0x08u, 0x0au, 0x02u, 0x8au, 0x00u, 0x73u, 0xb5u, 0x00u, 0x26u, 0x42u, 0x69u, 0x04u, 0x00u, 0xd5u, 0x68u, 0x01u, 0x96u, 0x2bu, 0x0cu, 0xb3u, 0x42u, 0x21u, 0xd0u, 0x1bu, 0x04u, 0x13u, 0x60u, 0x13u, 0x68u, 0x19u, 0x4bu, 0x00u, 0x69u, 0x1bu, 0x68u, 0xb0u, 0x33u, 0x1bu, 0x68u, 0xc3u, 0x18u, 0x1bu, 0x68u, 0xb3u, 0x42u, 0x15u, 0xdau, 0x01u, 0xa9u, 0xffu, 0xf7u, 0x22u, 0xffu, @@ -1614,34 +1614,34 @@ const uint8_t cy_m0p_image[] = { 0x20u, 0x69u, 0xffu, 0xf7u, 0xf1u, 0xfeu, 0xadu, 0xb2u, 0x00u, 0x2du, 0x09u, 0xd0u, 0x63u, 0x69u, 0x1du, 0x60u, 0x00u, 0x25u, 0x1bu, 0x68u, 0x63u, 0x6au, 0xabu, 0x42u, 0x05u, 0xd0u, 0x98u, 0x47u, 0x65u, 0x62u, 0xa5u, 0x61u, 0x63u, 0x69u, 0x1bu, 0x68u, 0x73u, 0xbdu, 0xa3u, 0x6au, 0x00u, 0x2bu, 0xf8u, 0xd0u, 0x98u, 0x47u, 0xf6u, 0xe7u, - 0x28u, 0x06u, 0x00u, 0x08u, 0x2cu, 0x23u, 0x10u, 0xb5u, 0x43u, 0x43u, 0x03u, 0x4au, 0x10u, 0x68u, 0xc0u, 0x18u, - 0xffu, 0xf7u, 0xb6u, 0xffu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0x40u, 0x04u, 0x00u, 0x08u, 0xf8u, 0xb5u, 0x19u, 0x4bu, + 0x38u, 0x06u, 0x00u, 0x08u, 0x2cu, 0x23u, 0x10u, 0xb5u, 0x43u, 0x43u, 0x03u, 0x4au, 0x10u, 0x68u, 0xc0u, 0x18u, + 0xffu, 0xf7u, 0xb6u, 0xffu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0x50u, 0x04u, 0x00u, 0x08u, 0xf8u, 0xb5u, 0x19u, 0x4bu, 0x0fu, 0x00u, 0x1bu, 0x68u, 0x1au, 0x00u, 0x2eu, 0x32u, 0x12u, 0x78u, 0x82u, 0x42u, 0x27u, 0xd9u, 0x00u, 0x29u, 0x25u, 0xd0u, 0x1fu, 0x25u, 0x0au, 0x68u, 0x15u, 0x40u, 0x21u, 0xd1u, 0x19u, 0x00u, 0xacu, 0x31u, 0x0cu, 0x88u, 0x11u, 0x4eu, 0x60u, 0x43u, 0x1cu, 0x6au, 0xd2u, 0x08u, 0x04u, 0x19u, 0x29u, 0x00u, 0x78u, 0x68u, 0x34u, 0x60u, - 0x00u, 0xf0u, 0x45u, 0xffu, 0x29u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xaeu, 0xfeu, 0x3au, 0x00u, 0x29u, 0x00u, + 0x00u, 0xf0u, 0x49u, 0xffu, 0x29u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xaeu, 0xfeu, 0x3au, 0x00u, 0x29u, 0x00u, 0x30u, 0x68u, 0xffu, 0xf7u, 0xbbu, 0xfeu, 0x04u, 0x1eu, 0x07u, 0xd1u, 0x01u, 0x00u, 0x30u, 0x68u, 0xffu, 0xf7u, 0xa3u, 0xfeu, 0x03u, 0x00u, 0x20u, 0x00u, 0x00u, 0x2bu, 0x00u, 0xd0u, 0x04u, 0x48u, 0xf8u, 0xbdu, 0x04u, 0x48u, - 0xfcu, 0xe7u, 0xc0u, 0x46u, 0x28u, 0x06u, 0x00u, 0x08u, 0x44u, 0x04u, 0x00u, 0x08u, 0x01u, 0x01u, 0x8au, 0x00u, + 0xfcu, 0xe7u, 0xc0u, 0x46u, 0x38u, 0x06u, 0x00u, 0x08u, 0x54u, 0x04u, 0x00u, 0x08u, 0x01u, 0x01u, 0x8au, 0x00u, 0x03u, 0x01u, 0x8au, 0x00u, 0x10u, 0xb5u, 0x00u, 0x2au, 0x0du, 0xd1u, 0x00u, 0x29u, 0x14u, 0xd1u, 0x0bu, 0x4bu, 0x1au, 0x68u, 0x13u, 0x00u, 0xacu, 0x33u, 0x1bu, 0x88u, 0x58u, 0x43u, 0x13u, 0x6au, 0xc0u, 0x18u, 0x08u, 0x4bu, 0x18u, 0x60u, 0x08u, 0x00u, 0x10u, 0xbdu, 0x00u, 0x29u, 0x06u, 0xd0u, 0x06u, 0x4bu, 0x19u, 0x60u, 0x19u, 0x00u, - 0x5au, 0x60u, 0xffu, 0xf7u, 0xabu, 0xffu, 0xf5u, 0xe7u, 0x03u, 0x48u, 0xf3u, 0xe7u, 0x28u, 0x06u, 0x00u, 0x08u, - 0x44u, 0x04u, 0x00u, 0x08u, 0xbcu, 0x03u, 0x00u, 0x08u, 0x03u, 0x01u, 0x8au, 0x00u, 0xf7u, 0xb5u, 0x18u, 0x4fu, + 0x5au, 0x60u, 0xffu, 0xf7u, 0xabu, 0xffu, 0xf5u, 0xe7u, 0x03u, 0x48u, 0xf3u, 0xe7u, 0x38u, 0x06u, 0x00u, 0x08u, + 0x54u, 0x04u, 0x00u, 0x08u, 0xccu, 0x03u, 0x00u, 0x08u, 0x03u, 0x01u, 0x8au, 0x00u, 0xf7u, 0xb5u, 0x18u, 0x4fu, 0x04u, 0x00u, 0x3bu, 0x68u, 0x01u, 0x91u, 0xdeu, 0x68u, 0x33u, 0x68u, 0x83u, 0x42u, 0x26u, 0xd9u, 0x00u, 0x25u, 0xa9u, 0x42u, 0x02u, 0xd1u, 0xf9u, 0xf7u, 0x79u, 0xfeu, 0x05u, 0x00u, 0x38u, 0x68u, 0x03u, 0x68u, 0x00u, 0x2bu, 0x1au, 0xdau, 0x1fu, 0x22u, 0x01u, 0x23u, 0x22u, 0x40u, 0x93u, 0x40u, 0x64u, 0x09u, 0x72u, 0x68u, 0xa4u, 0x00u, 0x14u, 0x19u, 0x22u, 0x68u, 0x13u, 0x42u, 0x0du, 0xd0u, 0x9au, 0x43u, 0x22u, 0x60u, 0x00u, 0x24u, 0x00u, 0x21u, 0xffu, 0xf7u, 0x4au, 0xfeu, 0x01u, 0x9bu, 0x00u, 0x2bu, 0x02u, 0xd1u, 0x28u, 0x00u, 0xf9u, 0xf7u, 0x61u, 0xfeu, 0x20u, 0x00u, 0xfeu, 0xbdu, 0x03u, 0x4cu, 0xf2u, 0xe7u, 0x03u, 0x4cu, 0xf3u, 0xe7u, 0x03u, 0x4cu, 0xf7u, 0xe7u, - 0x44u, 0x04u, 0x00u, 0x08u, 0x02u, 0x01u, 0x88u, 0x00u, 0x03u, 0x01u, 0x88u, 0x00u, 0x04u, 0x01u, 0x8au, 0x00u, + 0x54u, 0x04u, 0x00u, 0x08u, 0x02u, 0x01u, 0x88u, 0x00u, 0x03u, 0x01u, 0x88u, 0x00u, 0x04u, 0x01u, 0x8au, 0x00u, 0x0au, 0x4bu, 0x1bu, 0x68u, 0xdbu, 0x68u, 0x1au, 0x68u, 0x82u, 0x42u, 0x0du, 0xd9u, 0x59u, 0x68u, 0x1fu, 0x23u, 0x42u, 0x09u, 0x18u, 0x40u, 0x1eu, 0x3bu, 0x83u, 0x40u, 0x92u, 0x00u, 0x50u, 0x58u, 0x18u, 0x40u, 0x43u, 0x1eu, - 0x98u, 0x41u, 0x03u, 0x4bu, 0xc0u, 0x18u, 0x70u, 0x47u, 0x02u, 0x48u, 0xfcu, 0xe7u, 0x44u, 0x04u, 0x00u, 0x08u, + 0x98u, 0x41u, 0x03u, 0x4bu, 0xc0u, 0x18u, 0x70u, 0x47u, 0x02u, 0x48u, 0xfcu, 0xe7u, 0x54u, 0x04u, 0x00u, 0x08u, 0x00u, 0x01u, 0x88u, 0x00u, 0x04u, 0x01u, 0x8au, 0x00u, 0xa6u, 0x22u, 0x05u, 0x49u, 0xd2u, 0x00u, 0x8bu, 0x58u, 0x02u, 0x20u, 0xdbu, 0x43u, 0x9bu, 0x07u, 0x02u, 0xd0u, 0x01u, 0x23u, 0x88u, 0x58u, 0x18u, 0x40u, 0x70u, 0x47u, 0x00u, 0x00u, 0x26u, 0x40u, 0x10u, 0xb5u, 0xffu, 0xf7u, 0xefu, 0xffu, 0x00u, 0x23u, 0x02u, 0x28u, 0x01u, 0xd1u, - 0x01u, 0x4bu, 0x1bu, 0x68u, 0x18u, 0x00u, 0x10u, 0xbdu, 0x48u, 0x04u, 0x00u, 0x08u, 0x09u, 0x4au, 0x83u, 0x00u, + 0x01u, 0x4bu, 0x1bu, 0x68u, 0x18u, 0x00u, 0x10u, 0xbdu, 0x58u, 0x04u, 0x00u, 0x08u, 0x09u, 0x4au, 0x83u, 0x00u, 0x9bu, 0x18u, 0xd0u, 0x22u, 0x92u, 0x00u, 0x98u, 0x58u, 0x07u, 0x22u, 0x10u, 0x40u, 0x04u, 0x28u, 0x07u, 0xd1u, 0xc0u, 0x22u, 0x92u, 0x00u, 0x98u, 0x58u, 0x1fu, 0x23u, 0x03u, 0x40u, 0x80u, 0x20u, 0x40u, 0x00u, 0x18u, 0x43u, 0x70u, 0x47u, 0xc0u, 0x46u, 0x00u, 0x00u, 0x26u, 0x40u, 0x10u, 0xb5u, 0xffu, 0xf7u, 0xe7u, 0xffu, 0x03u, 0x28u, @@ -1651,7 +1651,7 @@ const uint8_t cy_m0p_image[] = { 0x00u, 0xe0u, 0x0cu, 0x48u, 0x10u, 0xbdu, 0x0cu, 0x4bu, 0x18u, 0x68u, 0xfbu, 0xe7u, 0x0bu, 0x4bu, 0xfbu, 0xe7u, 0x0bu, 0x4bu, 0x18u, 0x69u, 0x04u, 0x23u, 0x18u, 0x40u, 0xf4u, 0xd0u, 0x80u, 0x20u, 0x00u, 0x02u, 0xf1u, 0xe7u, 0x02u, 0x4au, 0x08u, 0x4bu, 0xe9u, 0xe7u, 0x00u, 0x20u, 0xecu, 0xe7u, 0xc0u, 0x46u, 0x00u, 0x00u, 0x26u, 0x40u, - 0x0cu, 0x05u, 0x00u, 0x00u, 0x00u, 0x12u, 0x7au, 0x00u, 0x4cu, 0x04u, 0x00u, 0x08u, 0xa4u, 0x04u, 0x00u, 0x08u, + 0x0cu, 0x05u, 0x00u, 0x00u, 0x00u, 0x12u, 0x7au, 0x00u, 0x5cu, 0x04u, 0x00u, 0x08u, 0xb4u, 0x04u, 0x00u, 0x08u, 0x00u, 0x00u, 0x27u, 0x40u, 0x3cu, 0x05u, 0x00u, 0x00u, 0xb0u, 0x23u, 0x15u, 0x4au, 0xdbu, 0x00u, 0xd3u, 0x58u, 0x10u, 0xb5u, 0x99u, 0x03u, 0xdbu, 0x01u, 0xdbu, 0x0fu, 0x89u, 0x0bu, 0xc3u, 0x71u, 0x11u, 0x4bu, 0x01u, 0x60u, 0xd3u, 0x58u, 0x0fu, 0x24u, 0xd9u, 0x04u, 0xdbu, 0x01u, 0xdbu, 0x0du, 0x03u, 0x81u, 0xb1u, 0x23u, 0xdbu, 0x00u, @@ -1663,457 +1663,458 @@ const uint8_t cy_m0p_image[] = { 0x80u, 0x30u, 0xffu, 0x30u, 0x0bu, 0x4bu, 0x80u, 0x00u, 0xc3u, 0x58u, 0x1au, 0x40u, 0x0au, 0x70u, 0x1au, 0x0cu, 0x22u, 0x40u, 0x18u, 0x0au, 0x8au, 0x70u, 0x1au, 0x01u, 0x20u, 0x40u, 0xe2u, 0x40u, 0x48u, 0x70u, 0x00u, 0x20u, 0x9bu, 0x00u, 0x9bu, 0x0fu, 0xcau, 0x70u, 0x0bu, 0x71u, 0x10u, 0xbdu, 0x03u, 0x48u, 0xfcu, 0xe7u, 0xc0u, 0x46u, - 0x28u, 0x06u, 0x00u, 0x08u, 0x00u, 0x00u, 0x26u, 0x40u, 0x01u, 0x00u, 0x4au, 0x00u, 0xf0u, 0xb5u, 0x87u, 0xb0u, - 0x04u, 0x00u, 0xffu, 0xf7u, 0x61u, 0xffu, 0x06u, 0x00u, 0x00u, 0x2cu, 0x34u, 0xd1u, 0x01u, 0xadu, 0x14u, 0x22u, - 0x21u, 0x00u, 0x28u, 0x00u, 0x00u, 0xf0u, 0xd3u, 0xfdu, 0x28u, 0x00u, 0xffu, 0xf7u, 0x95u, 0xffu, 0xb0u, 0x23u, - 0x25u, 0x4au, 0xdbu, 0x00u, 0xd3u, 0x58u, 0x00u, 0x2bu, 0x03u, 0xdau, 0xacu, 0x7bu, 0x02u, 0x3cu, 0x63u, 0x1eu, + 0x38u, 0x06u, 0x00u, 0x08u, 0x00u, 0x00u, 0x26u, 0x40u, 0x01u, 0x00u, 0x4au, 0x00u, 0xf0u, 0xb5u, 0x87u, 0xb0u, + 0x04u, 0x00u, 0xffu, 0xf7u, 0x61u, 0xffu, 0x06u, 0x00u, 0x00u, 0x2cu, 0x38u, 0xd1u, 0x01u, 0xadu, 0x14u, 0x22u, + 0x21u, 0x00u, 0x28u, 0x00u, 0x00u, 0xf0u, 0xd7u, 0xfdu, 0x28u, 0x00u, 0xffu, 0xf7u, 0x95u, 0xffu, 0xb0u, 0x23u, + 0x27u, 0x4au, 0xdbu, 0x00u, 0xd3u, 0x58u, 0x00u, 0x2bu, 0x03u, 0xdau, 0xacu, 0x7bu, 0x02u, 0x3cu, 0x63u, 0x1eu, 0x9cu, 0x41u, 0xeau, 0x79u, 0x01u, 0x9fu, 0x53u, 0x1eu, 0x9au, 0x41u, 0xa8u, 0x88u, 0x01u, 0x32u, 0x00u, 0x2cu, - 0x16u, 0xd0u, 0x00u, 0x23u, 0x19u, 0x00u, 0x00u, 0xf0u, 0x9bu, 0xfcu, 0x00u, 0x23u, 0x0cu, 0x00u, 0x05u, 0x00u, - 0x3au, 0x00u, 0x30u, 0x00u, 0x19u, 0x00u, 0x00u, 0xf0u, 0x93u, 0xfcu, 0xe6u, 0x07u, 0x6au, 0x08u, 0x32u, 0x43u, - 0x63u, 0x08u, 0x80u, 0x18u, 0x59u, 0x41u, 0x2au, 0x00u, 0x23u, 0x00u, 0x00u, 0xf0u, 0x69u, 0xfcu, 0x06u, 0x00u, - 0x30u, 0x00u, 0x07u, 0xb0u, 0xf0u, 0xbdu, 0x11u, 0x4bu, 0x1bu, 0x68u, 0x3bu, 0x33u, 0x1bu, 0x78u, 0xa3u, 0x42u, - 0xf6u, 0xd3u, 0x01u, 0xadu, 0x05u, 0x22u, 0x00u, 0x21u, 0x28u, 0x00u, 0x00u, 0xf0u, 0x98u, 0xfdu, 0x20u, 0x00u, - 0x29u, 0x00u, 0x80u, 0x34u, 0xffu, 0xf7u, 0x8au, 0xffu, 0xffu, 0x34u, 0x07u, 0x4bu, 0xa4u, 0x00u, 0xe3u, 0x58u, - 0x00u, 0x24u, 0xa3u, 0x42u, 0x03u, 0xdau, 0x2cu, 0x79u, 0x02u, 0x3cu, 0x63u, 0x1eu, 0x9cu, 0x41u, 0x2fu, 0x78u, - 0x68u, 0x78u, 0xaau, 0x78u, 0xc3u, 0xe7u, 0xc0u, 0x46u, 0x00u, 0x00u, 0x26u, 0x40u, 0x28u, 0x06u, 0x00u, 0x08u, - 0xe0u, 0x22u, 0x10u, 0xb5u, 0x01u, 0x24u, 0x09u, 0x4bu, 0x80u, 0x00u, 0x92u, 0x00u, 0xc0u, 0x18u, 0x83u, 0x58u, - 0x80u, 0x58u, 0x9bu, 0x06u, 0x9bu, 0x0fu, 0x9cu, 0x40u, 0x0fu, 0x23u, 0x18u, 0x40u, 0xffu, 0xf7u, 0x8eu, 0xffu, - 0x63u, 0x08u, 0x18u, 0x18u, 0x21u, 0x00u, 0x00u, 0xf0u, 0x9fu, 0xfbu, 0x10u, 0xbdu, 0x00u, 0x00u, 0x26u, 0x40u, - 0x14u, 0x4bu, 0x30u, 0xb5u, 0x1au, 0x68u, 0x07u, 0x24u, 0x13u, 0x00u, 0x28u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, - 0x15u, 0xd8u, 0x83u, 0x08u, 0x1du, 0x00u, 0xa5u, 0x43u, 0x2cu, 0x1eu, 0x0fu, 0xd1u, 0x03u, 0x34u, 0x20u, 0x40u, - 0xa0u, 0x40u, 0x81u, 0x40u, 0x12u, 0x68u, 0x9bu, 0x00u, 0x20u, 0x32u, 0xd3u, 0x18u, 0x0au, 0x00u, 0xffu, 0x21u, - 0x81u, 0x40u, 0x1cu, 0x68u, 0x62u, 0x40u, 0x11u, 0x40u, 0x61u, 0x40u, 0x19u, 0x60u, 0x30u, 0xbdu, 0x80u, 0x23u, - 0x20u, 0x40u, 0x1bu, 0x06u, 0x18u, 0x43u, 0x80u, 0x23u, 0x9bu, 0x01u, 0x12u, 0x68u, 0xc9u, 0x18u, 0x89u, 0x00u, - 0x88u, 0x50u, 0xf3u, 0xe7u, 0x28u, 0x06u, 0x00u, 0x08u, 0x06u, 0x4bu, 0x9au, 0x68u, 0x03u, 0x00u, 0x06u, 0x48u, - 0x10u, 0x33u, 0x9bu, 0x00u, 0x82u, 0x42u, 0x02u, 0xd1u, 0x98u, 0x58u, 0x99u, 0x50u, 0x70u, 0x47u, 0x03u, 0x4au, - 0xd0u, 0x58u, 0xfbu, 0xe7u, 0x00u, 0xedu, 0x00u, 0xe0u, 0x00u, 0x00u, 0x00u, 0x08u, 0x00u, 0x00u, 0x00u, 0x10u, - 0xf8u, 0xb5u, 0x06u, 0x00u, 0x0du, 0x00u, 0x00u, 0x28u, 0x3au, 0xd0u, 0x00u, 0x23u, 0xc0u, 0x5eu, 0x00u, 0x28u, - 0x28u, 0xdbu, 0xb1u, 0x78u, 0xffu, 0xf7u, 0xb4u, 0xffu, 0x00u, 0x24u, 0xffu, 0x22u, 0x03u, 0x27u, 0x94u, 0x46u, - 0x00u, 0x23u, 0xf0u, 0x5eu, 0x71u, 0x68u, 0x83u, 0xb2u, 0x1fu, 0x40u, 0xffu, 0x00u, 0x66u, 0x46u, 0xbau, 0x40u, - 0x89u, 0x01u, 0x31u, 0x40u, 0xd2u, 0x43u, 0xb9u, 0x40u, 0x00u, 0x28u, 0x15u, 0xdbu, 0x11u, 0x4eu, 0x83u, 0x08u, - 0x9bu, 0x00u, 0x9bu, 0x19u, 0xc0u, 0x26u, 0xb6u, 0x00u, 0x9fu, 0x59u, 0x3au, 0x40u, 0x11u, 0x43u, 0x99u, 0x51u, - 0x0du, 0x4bu, 0x9au, 0x68u, 0x0du, 0x4bu, 0x9au, 0x42u, 0x02u, 0xd1u, 0x29u, 0x00u, 0xffu, 0xf7u, 0xbcu, 0xffu, - 0x20u, 0x00u, 0xf8u, 0xbdu, 0x0au, 0x4cu, 0xd8u, 0xe7u, 0x0fu, 0x26u, 0x33u, 0x40u, 0x08u, 0x3bu, 0x06u, 0x4eu, - 0x9bu, 0x08u, 0x9bu, 0x00u, 0x9bu, 0x19u, 0xdeu, 0x69u, 0x32u, 0x40u, 0x11u, 0x43u, 0xd9u, 0x61u, 0xe7u, 0xe7u, - 0x03u, 0x4cu, 0xedu, 0xe7u, 0x00u, 0xe1u, 0x00u, 0xe0u, 0x00u, 0xedu, 0x00u, 0xe0u, 0x00u, 0x00u, 0x00u, 0x08u, - 0x01u, 0x00u, 0x56u, 0x00u, 0xfeu, 0xe7u, 0x00u, 0x00u, 0x02u, 0x68u, 0x0au, 0x4bu, 0x10u, 0xb5u, 0x1au, 0x60u, - 0x42u, 0x68u, 0x5au, 0x60u, 0x82u, 0x68u, 0x9au, 0x60u, 0xc2u, 0x68u, 0xdau, 0x60u, 0x02u, 0x69u, 0x1au, 0x61u, - 0x42u, 0x69u, 0x5au, 0x61u, 0x82u, 0x69u, 0x9au, 0x61u, 0xc2u, 0x69u, 0xdau, 0x61u, 0xffu, 0xf7u, 0xeau, 0xffu, - 0x10u, 0xbdu, 0xc0u, 0x46u, 0xd8u, 0x03u, 0x00u, 0x08u, 0xb0u, 0x23u, 0x5bu, 0x05u, 0x9au, 0x89u, 0x00u, 0x2au, - 0x02u, 0xd0u, 0x98u, 0x89u, 0x80u, 0xb2u, 0x70u, 0x47u, 0x80u, 0x20u, 0x40u, 0x00u, 0xfbu, 0xe7u, 0x00u, 0x00u, - 0x7fu, 0xb5u, 0x27u, 0x4bu, 0x86u, 0x00u, 0x0du, 0x00u, 0xf4u, 0x58u, 0x04u, 0x29u, 0x01u, 0xd0u, 0x01u, 0x29u, - 0x27u, 0xd1u, 0x00u, 0x20u, 0x0fu, 0xe0u, 0xa3u, 0x68u, 0x2bu, 0x42u, 0x0bu, 0xd1u, 0xe3u, 0x68u, 0x29u, 0x00u, - 0x1au, 0x68u, 0x5bu, 0x68u, 0x02u, 0x92u, 0x01u, 0x93u, 0x03u, 0x93u, 0x02u, 0xa8u, 0x23u, 0x68u, 0x98u, 0x47u, - 0x1cu, 0x4bu, 0x1cu, 0x60u, 0x64u, 0x69u, 0x00u, 0x2cu, 0x0bu, 0xd0u, 0x1bu, 0x4bu, 0x98u, 0x42u, 0xeau, 0xd1u, - 0x01u, 0x2du, 0xe8u, 0xd1u, 0x17u, 0x4bu, 0x18u, 0x48u, 0x1au, 0x68u, 0x18u, 0x4bu, 0x9au, 0x51u, 0x04u, 0xb0u, - 0x70u, 0xbdu, 0x01u, 0x2du, 0xfbu, 0xd1u, 0x14u, 0x4bu, 0x98u, 0x42u, 0xf3u, 0xd0u, 0x13u, 0x4bu, 0x9cu, 0x51u, - 0xf5u, 0xe7u, 0x02u, 0x29u, 0x06u, 0xd1u, 0x0fu, 0x4bu, 0x1bu, 0x68u, 0x18u, 0x1eu, 0xefu, 0xd0u, 0x1cu, 0x69u, - 0x03u, 0xe0u, 0x1cu, 0x00u, 0x63u, 0x69u, 0x00u, 0x2bu, 0xfbu, 0xd1u, 0x00u, 0x20u, 0x00u, 0x2cu, 0xe6u, 0xd0u, - 0xa3u, 0x68u, 0x2bu, 0x42u, 0x09u, 0xd1u, 0xe3u, 0x68u, 0x29u, 0x00u, 0x1au, 0x68u, 0x5bu, 0x68u, 0x02u, 0x92u, - 0x01u, 0x93u, 0x03u, 0x93u, 0x02u, 0xa8u, 0x23u, 0x68u, 0x98u, 0x47u, 0x24u, 0x69u, 0xeeu, 0xe7u, 0xc0u, 0x46u, - 0x90u, 0x04u, 0x00u, 0x08u, 0x8cu, 0x04u, 0x00u, 0x08u, 0xffu, 0x00u, 0x42u, 0x00u, 0x78u, 0x04u, 0x00u, 0x08u, - 0x19u, 0x4bu, 0x1bu, 0x68u, 0x19u, 0x00u, 0x04u, 0xc9u, 0xc9u, 0x6fu, 0x51u, 0x18u, 0x09u, 0x68u, 0x01u, 0x62u, - 0x19u, 0x00u, 0x08u, 0x31u, 0xc9u, 0x6fu, 0x52u, 0x18u, 0x12u, 0x68u, 0x42u, 0x62u, 0x1au, 0x00u, 0x41u, 0x32u, - 0x12u, 0x78u, 0x00u, 0x2au, 0x1fu, 0xd0u, 0x9au, 0x68u, 0xe0u, 0x32u, 0x12u, 0x68u, 0xd2u, 0x06u, 0x1au, 0xd5u, - 0xf2u, 0x22u, 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0x00u, 0x08u, 0x05u, 0x00u, 0x52u, 0x00u, 0x01u, 0x01u, 0x88u, 0x00u, 0x4cu, 0x04u, 0x00u, 0x08u, + 0xf0u, 0x49u, 0x02u, 0x00u, 0x01u, 0x00u, 0x50u, 0x00u, 0x18u, 0x4bu, 0xf7u, 0xb5u, 0x1bu, 0x68u, 0x18u, 0x4au, + 0x5cu, 0x68u, 0x04u, 0x23u, 0x11u, 0x69u, 0x0bu, 0x43u, 0x13u, 0x61u, 0x01u, 0x28u, 0x24u, 0xd0u, 0x30u, 0xbfu, + 0x23u, 0x00u, 0xfcu, 0x33u, 0x1bu, 0x69u, 0x00u, 0x2bu, 0x1du, 0xd1u, 0xa3u, 0x20u, 0x11u, 0x4bu, 0x12u, 0x49u, + 0x12u, 0x4au, 0xc0u, 0x00u, 0x0fu, 0x68u, 0x1eu, 0x58u, 0x15u, 0x68u, 0x01u, 0x95u, 0x10u, 0x4du, 0x0du, 0x60u, + 0x06u, 0x25u, 0x1du, 0x50u, 0x3eu, 0x20u, 0x10u, 0x60u, 0x0eu, 0x48u, 0x3eu, 0x35u, 0x1du, 0x50u, 0x1du, 0x58u, + 0x00u, 0x2du, 0xfcu, 0xdau, 0x0cu, 0x48u, 0xfcu, 0x34u, 0x20u, 0x61u, 0x0fu, 0x60u, 0xa3u, 0x21u, 0xc9u, 0x00u, + 0x5eu, 0x50u, 0x01u, 0x9bu, 0x13u, 0x60u, 0xf7u, 0xbdu, 0x20u, 0xbfu, 0xd9u, 0xe7u, 0x38u, 0x06u, 0x00u, 0x08u, + 0x00u, 0xedu, 0x00u, 0xe0u, 0x00u, 0x00u, 0x26u, 0x40u, 0x08u, 0x01u, 0x26u, 0x40u, 0x04u, 0x01u, 0x26u, 0x40u, + 0x1eu, 0x1fu, 0x00u, 0x00u, 0x1cu, 0x05u, 0x00u, 0x00u, 0xaau, 0xaau, 0xaau, 0xaau, 0x01u, 0xb4u, 0x02u, 0x48u, + 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, 0x29u, 0x62u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, + 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, 0x91u, 0x5fu, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, + 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, 0xadu, 0x6du, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, + 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, 0x55u, 0x60u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, + 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, 0x0du, 0x64u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, + 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, 0x1bu, 0x01u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, + 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, 0x81u, 0x64u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, + 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, 0x23u, 0x01u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, + 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, 0x0du, 0x61u, 0x00u, 0x10u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, }; #endif /* defined(CY_DEVICE_PSOC6ABLE2) */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/COMPONENT_CM0P_CRYPTO/psoc6_02_cm0p_crypto.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/COMPONENT_CM0P_CRYPTO/psoc6_02_cm0p_crypto.c index 96de7c86bb..4fced58044 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/COMPONENT_CM0P_CRYPTO/psoc6_02_cm0p_crypto.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/COMPONENT_CM0P_CRYPTO/psoc6_02_cm0p_crypto.c @@ -36,35 +36,35 @@ const uint8_t cy_m0p_image[] = { 0x49u, 0x01u, 0x00u, 0x10u, 0x49u, 0x01u, 0x00u, 0x10u, 0x49u, 0x01u, 0x00u, 0x10u, 0x49u, 0x01u, 0x00u, 0x10u, 0x49u, 0x01u, 0x00u, 0x10u, 0x49u, 0x01u, 0x00u, 0x10u, 0x49u, 0x01u, 0x00u, 0x10u, 0x49u, 0x01u, 0x00u, 0x10u, 0x10u, 0xb5u, 0x06u, 0x4cu, 0x23u, 0x78u, 0x00u, 0x2bu, 0x07u, 0xd1u, 0x05u, 0x4bu, 0x00u, 0x2bu, 0x02u, 0xd0u, - 0x04u, 0x48u, 0x00u, 0xe0u, 0x00u, 0xbfu, 0x01u, 0x23u, 0x23u, 0x70u, 0x10u, 0xbdu, 0xb0u, 0x03u, 0x00u, 0x08u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x48u, 0x7eu, 0x00u, 0x10u, 0x04u, 0x4bu, 0x10u, 0xb5u, 0x00u, 0x2bu, 0x03u, 0xd0u, + 0x04u, 0x48u, 0x00u, 0xe0u, 0x00u, 0xbfu, 0x01u, 0x23u, 0x23u, 0x70u, 0x10u, 0xbdu, 0xc0u, 0x03u, 0x00u, 0x08u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x50u, 0x7eu, 0x00u, 0x10u, 0x04u, 0x4bu, 0x10u, 0xb5u, 0x00u, 0x2bu, 0x03u, 0xd0u, 0x03u, 0x49u, 0x04u, 0x48u, 0x00u, 0xe0u, 0x00u, 0xbfu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0x00u, 0x00u, 0x00u, 0x00u, - 0xb4u, 0x03u, 0x00u, 0x08u, 0x48u, 0x7eu, 0x00u, 0x10u, 0x02u, 0x30u, 0x80u, 0x08u, 0x03u, 0xd0u, 0x01u, 0x30u, + 0xc4u, 0x03u, 0x00u, 0x08u, 0x50u, 0x7eu, 0x00u, 0x10u, 0x02u, 0x30u, 0x80u, 0x08u, 0x03u, 0xd0u, 0x01u, 0x30u, 0x02u, 0x38u, 0xfcu, 0xd1u, 0xc0u, 0x46u, 0xc0u, 0x46u, 0x70u, 0x47u, 0xefu, 0xf3u, 0x10u, 0x80u, 0x72u, 0xb6u, 0x70u, 0x47u, 0x80u, 0xf3u, 0x10u, 0x88u, 0x70u, 0x47u, 0x70u, 0x47u, 0xffu, 0xf7u, 0xfdu, 0xffu, 0x72u, 0xb6u, 0x0fu, 0x4cu, 0x10u, 0x4du, 0xacu, 0x42u, 0x09u, 0xdau, 0x21u, 0x68u, 0x62u, 0x68u, 0xa3u, 0x68u, 0x04u, 0x3bu, 0x02u, 0xdbu, 0xc8u, 0x58u, 0xd0u, 0x50u, 0xfau, 0xe7u, 0x0cu, 0x34u, 0xf3u, 0xe7u, 0x0au, 0x49u, 0x0bu, 0x4au, 0x00u, 0x20u, 0x52u, 0x1au, 0x02u, 0xddu, 0x04u, 0x3au, 0x88u, 0x50u, 0xfcu, 0xdcu, 0x08u, 0x48u, 0x09u, 0x49u, - 0x08u, 0x60u, 0xbfu, 0xf3u, 0x4fu, 0x8fu, 0x06u, 0xf0u, 0x75u, 0xfdu, 0x06u, 0xf0u, 0x15u, 0xfdu, 0xfeu, 0xe7u, - 0x54u, 0x7eu, 0x00u, 0x10u, 0x6cu, 0x7eu, 0x00u, 0x10u, 0xb0u, 0x03u, 0x00u, 0x08u, 0x0cu, 0x06u, 0x00u, 0x08u, + 0x08u, 0x60u, 0xbfu, 0xf3u, 0x4fu, 0x8fu, 0x06u, 0xf0u, 0x79u, 0xfdu, 0x06u, 0xf0u, 0x19u, 0xfdu, 0xfeu, 0xe7u, + 0x5cu, 0x7eu, 0x00u, 0x10u, 0x74u, 0x7eu, 0x00u, 0x10u, 0xc0u, 0x03u, 0x00u, 0x08u, 0x1cu, 0x06u, 0x00u, 0x08u, 0x00u, 0x00u, 0x00u, 0x08u, 0x08u, 0xedu, 0x00u, 0xe0u, 0xfeu, 0xe7u, 0xfeu, 0xe7u, 0x00u, 0xb5u, 0x04u, 0x20u, 0x71u, 0x46u, 0x08u, 0x42u, 0x02u, 0xd0u, 0xefu, 0xf3u, 0x09u, 0x80u, 0x01u, 0xe0u, 0xefu, 0xf3u, 0x08u, 0x80u, - 0x04u, 0x30u, 0x06u, 0xf0u, 0x07u, 0xfbu, 0xfeu, 0xe7u, 0xf7u, 0xb5u, 0x03u, 0x27u, 0x11u, 0x4eu, 0x14u, 0x00u, + 0x04u, 0x30u, 0x06u, 0xf0u, 0x0bu, 0xfbu, 0xfeu, 0xe7u, 0xf7u, 0xb5u, 0x03u, 0x27u, 0x11u, 0x4eu, 0x14u, 0x00u, 0x32u, 0x68u, 0x05u, 0x00u, 0x52u, 0x69u, 0x82u, 0x18u, 0x08u, 0x78u, 0x49u, 0x68u, 0x38u, 0x40u, 0x10u, 0x60u, 0x01u, 0x2cu, 0x00u, 0xd1u, 0x20u, 0x31u, 0x28u, 0x00u, 0x08u, 0x9au, 0x01u, 0x3cu, 0x03u, 0xf0u, 0x72u, 0xfdu, 0x0cu, 0x23u, 0x61u, 0x42u, 0x61u, 0x41u, 0x00u, 0x93u, 0x28u, 0x00u, 0x08u, 0x3bu, 0x44u, 0x31u, 0x00u, 0x22u, 0x03u, 0xf0u, 0xd0u, 0xfdu, 0x33u, 0x68u, 0x1bu, 0x68u, 0xedu, 0x18u, 0x01u, 0x23u, 0x2au, 0x68u, 0x1au, 0x42u, - 0xfcu, 0xd1u, 0xf7u, 0xbdu, 0xd0u, 0x03u, 0x00u, 0x08u, 0x73u, 0xb5u, 0x04u, 0x00u, 0x08u, 0x00u, 0x03u, 0x26u, + 0xfcu, 0xd1u, 0xf7u, 0xbdu, 0xe0u, 0x03u, 0x00u, 0x08u, 0x73u, 0xb5u, 0x04u, 0x00u, 0x08u, 0x00u, 0x03u, 0x26u, 0x0eu, 0x4du, 0x19u, 0x00u, 0x2bu, 0x68u, 0x00u, 0x78u, 0x5bu, 0x69u, 0x30u, 0x40u, 0xe3u, 0x18u, 0x18u, 0x60u, 0x13u, 0x00u, 0x20u, 0x00u, 0x06u, 0x9au, 0x03u, 0xf0u, 0x4du, 0xfdu, 0x08u, 0x23u, 0x20u, 0x00u, 0x00u, 0x93u, 0x00u, 0x22u, 0x04u, 0x3bu, 0x48u, 0x21u, 0x03u, 0xf0u, 0xadu, 0xfdu, 0x2bu, 0x68u, 0x1bu, 0x68u, 0xe4u, 0x18u, - 0x01u, 0x23u, 0x22u, 0x68u, 0x1au, 0x42u, 0xfcu, 0xd1u, 0x73u, 0xbdu, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, + 0x01u, 0x23u, 0x22u, 0x68u, 0x1au, 0x42u, 0xfcu, 0xd1u, 0x73u, 0xbdu, 0xc0u, 0x46u, 0xe0u, 0x03u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x1du, 0x00u, 0x1au, 0x70u, 0x04u, 0x9bu, 0x02u, 0x32u, 0x6bu, 0x60u, 0xd3u, 0x00u, 0x0au, 0x00u, 0x04u, 0x99u, 0x04u, 0x00u, 0x03u, 0xf0u, 0xceu, 0xfdu, 0x03u, 0x21u, 0x0du, 0x4eu, 0x2au, 0x78u, 0x33u, 0x68u, 0x0au, 0x40u, 0x5bu, 0x69u, 0x69u, 0x68u, 0xe3u, 0x18u, 0x1au, 0x60u, 0x0au, 0x00u, 0x20u, 0x00u, 0x20u, 0x32u, 0x03u, 0xf0u, 0x06u, 0xfdu, 0x08u, 0x23u, 0x20u, 0x00u, 0x00u, 0x22u, 0x46u, 0x21u, 0x03u, 0xf0u, 0x6cu, 0xfdu, 0x33u, 0x68u, 0x1bu, 0x68u, 0xe4u, 0x18u, 0x01u, 0x23u, 0x20u, 0x68u, 0x18u, 0x40u, 0xfcu, 0xd1u, 0x70u, 0xbdu, - 0xd0u, 0x03u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x85u, 0xb0u, 0x16u, 0x00u, 0x1au, 0x00u, 0x0au, 0x9bu, 0x05u, 0x00u, + 0xe0u, 0x03u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x85u, 0xb0u, 0x16u, 0x00u, 0x1au, 0x00u, 0x0au, 0x9bu, 0x05u, 0x00u, 0x5cu, 0x68u, 0x03u, 0x91u, 0x27u, 0x00u, 0x40u, 0x37u, 0x39u, 0x00u, 0x50u, 0x34u, 0x10u, 0x23u, 0x03u, 0xf0u, 0xa1u, 0xfdu, 0x23u, 0x00u, 0x03u, 0x9au, 0x0au, 0x99u, 0x28u, 0x00u, 0x00u, 0x97u, 0xffu, 0xf7u, 0x74u, 0xffu, 0x28u, 0x00u, 0x10u, 0x23u, 0x22u, 0x00u, 0x31u, 0x00u, 0x03u, 0xf0u, 0x94u, 0xfdu, 0x00u, 0x20u, 0x05u, 0xb0u, @@ -95,7 +95,7 @@ const uint8_t cy_m0p_image[] = { 0xd3u, 0xfeu, 0x10u, 0x23u, 0x2au, 0x00u, 0x07u, 0x99u, 0x30u, 0x00u, 0x03u, 0xf0u, 0xcbu, 0xfcu, 0x10u, 0x3cu, 0xcfu, 0xe7u, 0x01u, 0x48u, 0xdfu, 0xe7u, 0xc0u, 0x46u, 0x02u, 0x00u, 0x32u, 0x00u, 0xf0u, 0xb5u, 0x91u, 0xb0u, 0x19u, 0x9du, 0x04u, 0x00u, 0x06u, 0x91u, 0x0bu, 0x92u, 0x00u, 0x21u, 0x10u, 0x22u, 0x0cu, 0xa8u, 0x07u, 0x93u, - 0x06u, 0xf0u, 0x6fu, 0xfeu, 0x6bu, 0x68u, 0x0cu, 0xa9u, 0x1au, 0x00u, 0x40u, 0x32u, 0x03u, 0x92u, 0x60u, 0x33u, + 0x06u, 0xf0u, 0x73u, 0xfeu, 0x6bu, 0x68u, 0x0cu, 0xa9u, 0x1au, 0x00u, 0x40u, 0x32u, 0x03u, 0x92u, 0x60u, 0x33u, 0x10u, 0x32u, 0x04u, 0x92u, 0x05u, 0x93u, 0x07u, 0x9au, 0x10u, 0x23u, 0x20u, 0x00u, 0x03u, 0xf0u, 0xaau, 0xfcu, 0x0fu, 0x9bu, 0x1bu, 0xbau, 0x08u, 0x93u, 0x06u, 0x9bu, 0x08u, 0x9eu, 0x1bu, 0x09u, 0x0au, 0x93u, 0x0eu, 0x9bu, 0x1fu, 0xbau, 0x08u, 0x9bu, 0x17u, 0x99u, 0xf3u, 0x1au, 0x1au, 0x01u, 0x89u, 0x18u, 0x09u, 0x91u, 0x18u, 0x99u, @@ -107,32 +107,32 @@ const uint8_t cy_m0p_image[] = { 0x0eu, 0x92u, 0x00u, 0x93u, 0x04u, 0x9au, 0x03u, 0x9bu, 0x29u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x6cu, 0xfeu, 0x10u, 0x23u, 0x04u, 0x9au, 0x09u, 0x99u, 0x20u, 0x00u, 0x03u, 0xf0u, 0x64u, 0xfcu, 0xc1u, 0xe7u, 0x00u, 0x00u, 0x03u, 0x4bu, 0x1bu, 0x68u, 0x9bu, 0x68u, 0xc0u, 0x18u, 0x0fu, 0x23u, 0x00u, 0x68u, 0x18u, 0x40u, 0x70u, 0x47u, - 0xd0u, 0x03u, 0x00u, 0x08u, 0x03u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xc0u, 0x18u, 0x03u, 0x68u, 0x00u, 0x2bu, - 0xfcu, 0xd1u, 0x70u, 0x47u, 0xd0u, 0x03u, 0x00u, 0x08u, 0xf8u, 0xb5u, 0x04u, 0x00u, 0x0du, 0x00u, 0x17u, 0x00u, + 0xe0u, 0x03u, 0x00u, 0x08u, 0x03u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xc0u, 0x18u, 0x03u, 0x68u, 0x00u, 0x2bu, + 0xfcu, 0xd1u, 0x70u, 0x47u, 0xe0u, 0x03u, 0x00u, 0x08u, 0xf8u, 0xb5u, 0x04u, 0x00u, 0x0du, 0x00u, 0x17u, 0x00u, 0x1eu, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xe4u, 0xffu, 0x04u, 0x28u, 0xfau, 0xd8u, 0x08u, 0x2du, 0x04u, 0xd0u, 0x0cu, 0x4au, 0xa3u, 0x58u, 0x00u, 0x2bu, 0xfcu, 0xdbu, 0x04u, 0xe0u, 0x86u, 0x22u, 0x52u, 0x01u, 0xa3u, 0x58u, 0x00u, 0x2bu, 0xfcu, 0xdbu, 0xe2u, 0x21u, 0x08u, 0x4bu, 0xc9u, 0x05u, 0x1bu, 0x68u, 0x0du, 0x43u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x15u, 0x60u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x17u, 0x60u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0x26u, 0x60u, - 0xf8u, 0xbdu, 0xc0u, 0x46u, 0xd0u, 0x10u, 0x00u, 0x00u, 0xd0u, 0x03u, 0x00u, 0x08u, 0xf8u, 0xb5u, 0x07u, 0x00u, + 0xf8u, 0xbdu, 0xc0u, 0x46u, 0xd0u, 0x10u, 0x00u, 0x00u, 0xe0u, 0x03u, 0x00u, 0x08u, 0xf8u, 0xb5u, 0x07u, 0x00u, 0x0cu, 0x00u, 0x16u, 0x00u, 0x1du, 0x00u, 0x38u, 0x00u, 0xffu, 0xf7u, 0xbau, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x06u, 0x4bu, 0x24u, 0x03u, 0x1bu, 0x68u, 0x2du, 0x04u, 0xd8u, 0x68u, 0x80u, 0x23u, 0xdbu, 0x05u, 0x1eu, 0x43u, - 0x34u, 0x43u, 0x38u, 0x18u, 0x2cu, 0x43u, 0x04u, 0x60u, 0xf8u, 0xbdu, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, + 0x34u, 0x43u, 0x38u, 0x18u, 0x2cu, 0x43u, 0x04u, 0x60u, 0xf8u, 0xbdu, 0xc0u, 0x46u, 0xe0u, 0x03u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x05u, 0x00u, 0x0cu, 0x00u, 0x16u, 0x00u, 0x28u, 0x00u, 0xffu, 0xf7u, 0xa1u, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x05u, 0x4bu, 0x24u, 0x02u, 0x1bu, 0x68u, 0xdbu, 0x68u, 0xedu, 0x18u, 0xd0u, 0x23u, 0xdbu, 0x05u, - 0x1eu, 0x43u, 0x34u, 0x43u, 0x2cu, 0x60u, 0x70u, 0xbdu, 0xd0u, 0x03u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, + 0x1eu, 0x43u, 0x34u, 0x43u, 0x2cu, 0x60u, 0x70u, 0xbdu, 0xe0u, 0x03u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x8du, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x04u, 0x4bu, 0x1bu, 0x68u, 0xdbu, 0x68u, - 0xe4u, 0x18u, 0xa0u, 0x23u, 0xdbu, 0x05u, 0x23u, 0x60u, 0x10u, 0xbdu, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, + 0xe4u, 0x18u, 0xa0u, 0x23u, 0xdbu, 0x05u, 0x23u, 0x60u, 0x10u, 0xbdu, 0xc0u, 0x46u, 0xe0u, 0x03u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x7bu, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x04u, 0x4bu, 0x1bu, 0x68u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0xa2u, 0x23u, 0xdbu, 0x05u, 0x23u, 0x60u, 0x10u, 0xbdu, 0xc0u, 0x46u, - 0xd0u, 0x03u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x04u, 0x00u, 0x0eu, 0x00u, 0x15u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, + 0xe0u, 0x03u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x04u, 0x00u, 0x0eu, 0x00u, 0x15u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x67u, 0xffu, 0x04u, 0x28u, 0xfau, 0xd8u, 0x06u, 0x4bu, 0x06u, 0x49u, 0x1bu, 0x68u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x11u, 0x60u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x16u, 0x60u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0x25u, 0x60u, 0x70u, 0xbdu, - 0xd0u, 0x03u, 0x00u, 0x08u, 0x0cu, 0x00u, 0x00u, 0x70u, 0x70u, 0xb5u, 0x05u, 0x00u, 0x0cu, 0x78u, 0x4au, 0x68u, + 0xe0u, 0x03u, 0x00u, 0x08u, 0x0cu, 0x00u, 0x00u, 0x70u, 0x70u, 0xb5u, 0x05u, 0x00u, 0x0cu, 0x78u, 0x4au, 0x68u, 0x02u, 0x34u, 0xe4u, 0x00u, 0x23u, 0x00u, 0x0eu, 0x00u, 0x08u, 0x21u, 0xffu, 0xf7u, 0x5du, 0xffu, 0x10u, 0x23u, 0x08u, 0x22u, 0x04u, 0x21u, 0x28u, 0x00u, 0xffu, 0xf7u, 0x81u, 0xffu, 0x23u, 0x00u, 0x10u, 0x3bu, 0x00u, 0x2bu, 0x04u, 0xd0u, 0x08u, 0x22u, 0x05u, 0x21u, 0x28u, 0x00u, 0xffu, 0xf7u, 0x78u, 0xffu, 0x03u, 0x21u, 0x05u, 0x4bu, 0x32u, 0x78u, 0x1bu, 0x68u, 0x0au, 0x40u, 0x5bu, 0x69u, 0x28u, 0x00u, 0xebu, 0x18u, 0x1au, 0x60u, 0xffu, 0xf7u, - 0x39u, 0xffu, 0x70u, 0xbdu, 0xd0u, 0x03u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x05u, 0x00u, 0x0bu, 0x78u, 0x02u, 0x33u, + 0x39u, 0xffu, 0x70u, 0xbdu, 0xe0u, 0x03u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x05u, 0x00u, 0x0bu, 0x78u, 0x02u, 0x33u, 0xdcu, 0x00u, 0xffu, 0xf7u, 0xd1u, 0xffu, 0x28u, 0x00u, 0xffu, 0xf7u, 0x90u, 0xffu, 0x10u, 0x23u, 0x06u, 0x22u, 0x04u, 0x21u, 0x28u, 0x00u, 0xffu, 0xf7u, 0x5au, 0xffu, 0x23u, 0x00u, 0x10u, 0x3bu, 0x00u, 0x2bu, 0x04u, 0xd0u, 0x07u, 0x22u, 0x05u, 0x21u, 0x28u, 0x00u, 0xffu, 0xf7u, 0x51u, 0xffu, 0x28u, 0x00u, 0xffu, 0xf7u, 0x1au, 0xffu, @@ -160,7 +160,7 @@ const uint8_t cy_m0p_image[] = { 0x00u, 0x21u, 0xffu, 0xf7u, 0xa3u, 0xfeu, 0x20u, 0x00u, 0xffu, 0xf7u, 0xe2u, 0xfeu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x5fu, 0xfeu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x08u, 0x4bu, 0x09u, 0x4au, 0x1bu, 0x68u, 0x02u, 0x21u, 0xdbu, 0x68u, 0x20u, 0x00u, 0xe3u, 0x18u, 0x1au, 0x60u, 0x10u, 0x23u, 0x00u, 0x22u, 0xffu, 0xf7u, 0x8fu, 0xfeu, 0x10u, 0x3du, - 0xdfu, 0xe7u, 0x04u, 0x48u, 0xbfu, 0xe7u, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, 0x18u, 0x00u, 0x10u, 0x41u, + 0xdfu, 0xe7u, 0x04u, 0x48u, 0xbfu, 0xe7u, 0xc0u, 0x46u, 0xe0u, 0x03u, 0x00u, 0x08u, 0x18u, 0x00u, 0x10u, 0x41u, 0x21u, 0xc0u, 0x10u, 0x41u, 0x02u, 0x00u, 0x32u, 0x00u, 0xf7u, 0xb5u, 0x0fu, 0x26u, 0x04u, 0x00u, 0x01u, 0x91u, 0x15u, 0x00u, 0x1fu, 0x00u, 0x16u, 0x40u, 0x5eu, 0xd1u, 0x0au, 0x99u, 0xffu, 0xf7u, 0xe5u, 0xfeu, 0x10u, 0x23u, 0x3au, 0x00u, 0x09u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x47u, 0xfeu, 0x10u, 0x23u, 0x09u, 0x22u, 0x31u, 0x00u, @@ -174,7 +174,7 @@ const uint8_t cy_m0p_image[] = { 0x1au, 0x60u, 0x10u, 0x23u, 0x00u, 0x22u, 0xffu, 0xf7u, 0x31u, 0xfeu, 0x10u, 0x3du, 0x00u, 0x2du, 0xe8u, 0xd1u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xf7u, 0xfdu, 0x10u, 0x22u, 0x39u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x7au, 0xfeu, 0x10u, 0x23u, 0x00u, 0x22u, 0x0cu, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x20u, 0xfeu, 0x20u, 0x00u, 0xffu, 0xf7u, - 0xe9u, 0xfdu, 0x00u, 0x20u, 0xfeu, 0xbdu, 0x04u, 0x48u, 0xfcu, 0xe7u, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, + 0xe9u, 0xfdu, 0x00u, 0x20u, 0xfeu, 0xbdu, 0x04u, 0x48u, 0xfcu, 0xe7u, 0xc0u, 0x46u, 0xe0u, 0x03u, 0x00u, 0x08u, 0x01u, 0xc0u, 0x10u, 0x41u, 0x18u, 0x00u, 0x10u, 0x41u, 0x02u, 0x00u, 0x32u, 0x00u, 0xf0u, 0xb5u, 0x1du, 0x00u, 0x8bu, 0xb0u, 0x04u, 0x92u, 0x6au, 0x78u, 0x1bu, 0x78u, 0x12u, 0x02u, 0x1au, 0x43u, 0xabu, 0x78u, 0x04u, 0x00u, 0x1bu, 0x04u, 0x1au, 0x43u, 0xebu, 0x78u, 0x2eu, 0x7au, 0x1bu, 0x06u, 0x13u, 0x43u, 0x6au, 0x79u, 0x06u, 0x93u, @@ -199,7 +199,7 @@ const uint8_t cy_m0p_image[] = { 0xf2u, 0xb2u, 0x0fu, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x83u, 0xfdu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x28u, 0xfdu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x08u, 0x4bu, 0x09u, 0x4au, 0x1bu, 0x68u, 0xdbu, 0x68u, 0xe3u, 0x18u, 0x1au, 0x60u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x1du, 0xfdu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x03u, 0x4bu, 0x04u, 0x4au, 0x1bu, 0x68u, - 0xdbu, 0x68u, 0xe3u, 0x18u, 0x1au, 0x60u, 0xb3u, 0xe7u, 0xd0u, 0x03u, 0x00u, 0x08u, 0x10u, 0x10u, 0x00u, 0x66u, + 0xdbu, 0x68u, 0xe3u, 0x18u, 0x1au, 0x60u, 0xb3u, 0xe7u, 0xe0u, 0x03u, 0x00u, 0x08u, 0x10u, 0x10u, 0x00u, 0x66u, 0x10u, 0x10u, 0x00u, 0x67u, 0x02u, 0x00u, 0x00u, 0x23u, 0x10u, 0xb5u, 0x0fu, 0x32u, 0x44u, 0x1eu, 0x11u, 0x78u, 0x01u, 0x3au, 0x49u, 0x00u, 0x0bu, 0x43u, 0x53u, 0x70u, 0x1bu, 0x0au, 0x94u, 0x42u, 0xf7u, 0xd1u, 0x00u, 0x2bu, 0x04u, 0xd0u, 0x79u, 0x23u, 0xc2u, 0x7bu, 0x5bu, 0x42u, 0x53u, 0x40u, 0xc3u, 0x73u, 0x10u, 0xbdu, 0xf7u, 0xb5u, @@ -226,34 +226,34 @@ const uint8_t cy_m0p_image[] = { 0xa0u, 0x36u, 0x80u, 0x33u, 0x33u, 0x60u, 0x03u, 0x9bu, 0x90u, 0x34u, 0x73u, 0x60u, 0x32u, 0x00u, 0x0cu, 0x99u, 0x28u, 0x00u, 0xb4u, 0x60u, 0xffu, 0xf7u, 0x53u, 0xffu, 0x02u, 0x9bu, 0x32u, 0x00u, 0x0cu, 0x99u, 0x28u, 0x00u, 0x00u, 0x97u, 0xffu, 0xf7u, 0x61u, 0xffu, 0x28u, 0x00u, 0x0bu, 0x9bu, 0x32u, 0x00u, 0x0cu, 0x99u, 0xffu, 0xf7u, - 0x8du, 0xffu, 0x00u, 0x20u, 0x05u, 0xb0u, 0xf0u, 0xbdu, 0xd0u, 0x03u, 0x00u, 0x08u, 0x03u, 0x4bu, 0x1bu, 0x68u, - 0x9bu, 0x68u, 0xc0u, 0x18u, 0x0fu, 0x23u, 0x00u, 0x68u, 0x18u, 0x40u, 0x70u, 0x47u, 0xd0u, 0x03u, 0x00u, 0x08u, + 0x8du, 0xffu, 0x00u, 0x20u, 0x05u, 0xb0u, 0xf0u, 0xbdu, 0xe0u, 0x03u, 0x00u, 0x08u, 0x03u, 0x4bu, 0x1bu, 0x68u, + 0x9bu, 0x68u, 0xc0u, 0x18u, 0x0fu, 0x23u, 0x00u, 0x68u, 0x18u, 0x40u, 0x70u, 0x47u, 0xe0u, 0x03u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xf1u, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x04u, 0x4bu, 0x1bu, 0x68u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0xa0u, 0x23u, 0xdbu, 0x05u, 0x23u, 0x60u, 0x10u, 0xbdu, 0xc0u, 0x46u, - 0xd0u, 0x03u, 0x00u, 0x08u, 0x02u, 0x00u, 0x00u, 0x23u, 0x10u, 0xb5u, 0x0fu, 0x32u, 0x44u, 0x1eu, 0x11u, 0x78u, + 0xe0u, 0x03u, 0x00u, 0x08u, 0x02u, 0x00u, 0x00u, 0x23u, 0x10u, 0xb5u, 0x0fu, 0x32u, 0x44u, 0x1eu, 0x11u, 0x78u, 0x01u, 0x3au, 0x49u, 0x00u, 0x0bu, 0x43u, 0x53u, 0x70u, 0x1bu, 0x0au, 0x94u, 0x42u, 0xf7u, 0xd1u, 0x00u, 0x2bu, 0x04u, 0xd0u, 0x79u, 0x23u, 0xc2u, 0x7bu, 0x5bu, 0x42u, 0x53u, 0x40u, 0xc3u, 0x73u, 0x10u, 0xbdu, 0x00u, 0x00u, 0x70u, 0xb5u, 0x04u, 0x00u, 0x0eu, 0x00u, 0x15u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xc7u, 0xffu, 0x04u, 0x28u, 0xfau, 0xd8u, 0x86u, 0x22u, 0x52u, 0x01u, 0xa3u, 0x58u, 0x00u, 0x2bu, 0xfcu, 0xdbu, 0x06u, 0x4bu, 0x07u, 0x49u, 0x1bu, 0x68u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x11u, 0x60u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x16u, 0x60u, 0xdbu, 0x68u, - 0xe4u, 0x18u, 0x25u, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, 0x08u, 0x00u, 0x00u, 0x71u, + 0xe4u, 0x18u, 0x25u, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u, 0xe0u, 0x03u, 0x00u, 0x08u, 0x08u, 0x00u, 0x00u, 0x71u, 0x70u, 0xb5u, 0x04u, 0x00u, 0x0du, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa8u, 0xffu, 0x04u, 0x28u, 0xfau, 0xd8u, 0x06u, 0x4bu, 0x07u, 0x49u, 0x1bu, 0x68u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x11u, 0x60u, 0xdau, 0x68u, 0xa2u, 0x18u, - 0x15u, 0x60u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0x10u, 0x23u, 0x23u, 0x60u, 0x70u, 0xbdu, 0xd0u, 0x03u, 0x00u, 0x08u, + 0x15u, 0x60u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0x10u, 0x23u, 0x23u, 0x60u, 0x70u, 0xbdu, 0xe0u, 0x03u, 0x00u, 0x08u, 0x0cu, 0x00u, 0x00u, 0x70u, 0x00u, 0x23u, 0x70u, 0xb5u, 0x04u, 0x00u, 0x0eu, 0x00u, 0x0bu, 0x60u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x8cu, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x14u, 0x4du, 0x15u, 0x4au, 0x2bu, 0x68u, 0x20u, 0x00u, 0xdbu, 0x68u, 0xe3u, 0x18u, 0x1au, 0x60u, 0xffu, 0xf7u, 0x8bu, 0xffu, 0x71u, 0x68u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xcfu, 0xffu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x7au, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x2au, 0x68u, 0x0du, 0x49u, 0xd3u, 0x68u, 0xe3u, 0x18u, 0x19u, 0x60u, 0x13u, 0x68u, 0xe3u, 0x18u, 0x1au, 0x68u, 0x00u, 0x2au, 0xfcu, 0xd1u, 0x70u, 0x68u, 0xffu, 0xf7u, 0x87u, 0xffu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x68u, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, - 0x2bu, 0x68u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0x04u, 0x4bu, 0x23u, 0x60u, 0x70u, 0xbdu, 0xd0u, 0x03u, 0x00u, 0x08u, + 0x2bu, 0x68u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0x04u, 0x4bu, 0x23u, 0x60u, 0x70u, 0xbdu, 0xe0u, 0x03u, 0x00u, 0x08u, 0x00u, 0x00u, 0x10u, 0x41u, 0x01u, 0xc0u, 0x10u, 0x40u, 0x11u, 0x10u, 0x10u, 0x41u, 0x70u, 0xb5u, 0x0eu, 0x00u, 0x11u, 0x00u, 0x32u, 0x68u, 0x05u, 0x00u, 0x9cu, 0x18u, 0x1au, 0x00u, 0xffu, 0xf7u, 0x81u, 0xffu, 0x10u, 0x2cu, 0x01u, 0xd8u, 0x34u, 0x60u, 0x70u, 0xbdu, 0x28u, 0x00u, 0xffu, 0xf7u, 0x48u, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x05u, 0x4bu, 0x06u, 0x4au, 0x1bu, 0x68u, 0x28u, 0x00u, 0xdbu, 0x68u, 0x10u, 0x3cu, 0xebu, 0x18u, 0x1au, 0x60u, - 0xffu, 0xf7u, 0x46u, 0xffu, 0xebu, 0xe7u, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, 0x18u, 0x00u, 0x10u, 0x41u, + 0xffu, 0xf7u, 0x46u, 0xffu, 0xebu, 0xe7u, 0xc0u, 0x46u, 0xe0u, 0x03u, 0x00u, 0x08u, 0x18u, 0x00u, 0x10u, 0x41u, 0xf0u, 0xb5u, 0x10u, 0x25u, 0x87u, 0xb0u, 0x0fu, 0x00u, 0x04u, 0x00u, 0x01u, 0x92u, 0x00u, 0x21u, 0x2au, 0x00u, - 0x02u, 0xa8u, 0x06u, 0xf0u, 0x7eu, 0xf9u, 0x80u, 0x23u, 0x7eu, 0x68u, 0x3fu, 0x68u, 0x02u, 0xaau, 0x13u, 0x70u, + 0x02u, 0xa8u, 0x06u, 0xf0u, 0x82u, 0xf9u, 0x80u, 0x23u, 0x7eu, 0x68u, 0x3fu, 0x68u, 0x02u, 0xaau, 0x13u, 0x70u, 0x02u, 0xa9u, 0xeau, 0x1bu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x53u, 0xffu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x1eu, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x18u, 0x4du, 0x19u, 0x4au, 0x2bu, 0x68u, 0xdbu, 0x68u, 0xe3u, 0x18u, 0x1au, 0x60u, 0x0fu, 0x2fu, 0x02u, 0xd8u, 0x30u, 0x00u, 0xffu, 0xf7u, 0x2du, 0xffu, 0x10u, 0x22u, 0x31u, 0x00u, 0x20u, 0x00u, @@ -261,10 +261,10 @@ const uint8_t cy_m0p_image[] = { 0x0fu, 0x4au, 0xdbu, 0x68u, 0x20u, 0x00u, 0xe3u, 0x18u, 0x1au, 0x60u, 0xffu, 0xf7u, 0x09u, 0xffu, 0x01u, 0x99u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x4du, 0xffu, 0x20u, 0x00u, 0xffu, 0xf7u, 0xf8u, 0xfeu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x2au, 0x68u, 0x08u, 0x49u, 0xd3u, 0x68u, 0xe3u, 0x18u, 0x19u, 0x60u, 0x13u, 0x68u, 0xe4u, 0x18u, 0x23u, 0x68u, - 0x00u, 0x2bu, 0xfcu, 0xd1u, 0x07u, 0xb0u, 0xf0u, 0xbdu, 0xd0u, 0x03u, 0x00u, 0x08u, 0x18u, 0x00u, 0x10u, 0x41u, + 0x00u, 0x2bu, 0xfcu, 0xd1u, 0x07u, 0xb0u, 0xf0u, 0xbdu, 0xe0u, 0x03u, 0x00u, 0x08u, 0x18u, 0x00u, 0x10u, 0x41u, 0x08u, 0x00u, 0x10u, 0x41u, 0x01u, 0xc0u, 0x10u, 0x40u, 0xf0u, 0xb5u, 0x04u, 0x00u, 0x1eu, 0x00u, 0xa7u, 0xb0u, 0x2cu, 0xabu, 0x0au, 0xadu, 0x1fu, 0x78u, 0x02u, 0x91u, 0x03u, 0x92u, 0x00u, 0x21u, 0x70u, 0x22u, 0x28u, 0x00u, - 0x06u, 0xf0u, 0x27u, 0xf9u, 0x18u, 0x22u, 0x00u, 0x21u, 0x04u, 0xa8u, 0x06u, 0xf0u, 0x22u, 0xf9u, 0x3au, 0x00u, + 0x06u, 0xf0u, 0x2bu, 0xf9u, 0x18u, 0x22u, 0x00u, 0x21u, 0x04u, 0xa8u, 0x06u, 0xf0u, 0x26u, 0xf9u, 0x3au, 0x00u, 0x2eu, 0x9bu, 0x31u, 0x00u, 0x00u, 0x95u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xf3u, 0xfbu, 0x2eu, 0x99u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xaau, 0xfbu, 0x06u, 0xabu, 0x04u, 0xa9u, 0x20u, 0x00u, 0x05u, 0x93u, 0xffu, 0xf7u, 0x2au, 0xffu, 0x03u, 0x9bu, 0x02u, 0x9au, 0x04u, 0xa9u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x60u, 0xffu, 0x20u, 0x00u, 0x2du, 0x9au, @@ -272,30 +272,30 @@ const uint8_t cy_m0p_image[] = { 0x0cu, 0x4cu, 0x7fu, 0x00u, 0x25u, 0x68u, 0xdbu, 0xb2u, 0x2cu, 0x6au, 0x06u, 0x19u, 0x05u, 0x9cu, 0x24u, 0x02u, 0x3cu, 0x40u, 0xffu, 0x3fu, 0x3au, 0x40u, 0x22u, 0x43u, 0x32u, 0x60u, 0x6au, 0x6au, 0x82u, 0x18u, 0x13u, 0x60u, 0xabu, 0x6au, 0xc3u, 0x18u, 0x19u, 0x60u, 0xebu, 0x6au, 0xc0u, 0x18u, 0x06u, 0x9bu, 0x03u, 0x60u, 0x00u, 0x20u, - 0xf0u, 0xbdu, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x0du, 0x00u, 0x11u, 0x00u, 0x86u, 0x22u, + 0xf0u, 0xbdu, 0xc0u, 0x46u, 0xe0u, 0x03u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x0du, 0x00u, 0x11u, 0x00u, 0x86u, 0x22u, 0x04u, 0x00u, 0x04u, 0x98u, 0xd2u, 0x00u, 0xa0u, 0x50u, 0x1au, 0x00u, 0x20u, 0x00u, 0x02u, 0xf0u, 0x68u, 0xfeu, 0x04u, 0x23u, 0x00u, 0x22u, 0x58u, 0x21u, 0x20u, 0x00u, 0x02u, 0xf0u, 0xceu, 0xfeu, 0x08u, 0x21u, 0x06u, 0x4bu, 0x1au, 0x68u, 0x13u, 0x68u, 0xe3u, 0x18u, 0x18u, 0x68u, 0x08u, 0x40u, 0xfcu, 0xd1u, 0x13u, 0x6bu, 0xe4u, 0x18u, - 0x23u, 0x68u, 0x2bu, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, 0x03u, 0x4bu, 0x1bu, 0x68u, - 0x1bu, 0x68u, 0xc0u, 0x18u, 0x03u, 0x68u, 0x00u, 0x2bu, 0xfcu, 0xd1u, 0x70u, 0x47u, 0xd0u, 0x03u, 0x00u, 0x08u, + 0x23u, 0x68u, 0x2bu, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u, 0xe0u, 0x03u, 0x00u, 0x08u, 0x03u, 0x4bu, 0x1bu, 0x68u, + 0x1bu, 0x68u, 0xc0u, 0x18u, 0x03u, 0x68u, 0x00u, 0x2bu, 0xfcu, 0xd1u, 0x70u, 0x47u, 0xe0u, 0x03u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x0fu, 0x26u, 0x09u, 0x4bu, 0x1bu, 0x68u, 0x9cu, 0x68u, 0x05u, 0x19u, 0x2cu, 0x68u, 0x34u, 0x40u, 0x04u, 0x2cu, 0xfbu, 0xd8u, 0xdcu, 0x68u, 0x06u, 0x4du, 0x04u, 0x19u, 0x25u, 0x60u, 0xdcu, 0x68u, 0x04u, 0x19u, - 0x21u, 0x60u, 0xdbu, 0x68u, 0xc0u, 0x18u, 0x02u, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, + 0x21u, 0x60u, 0xdbu, 0x68u, 0xc0u, 0x18u, 0x02u, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u, 0xe0u, 0x03u, 0x00u, 0x08u, 0x08u, 0x00u, 0x00u, 0x70u, 0x10u, 0xb5u, 0x0fu, 0x24u, 0x06u, 0x4bu, 0x19u, 0x68u, 0x8bu, 0x68u, 0xc2u, 0x18u, 0x13u, 0x68u, 0x23u, 0x40u, 0x06u, 0x2bu, 0xfbu, 0xd8u, 0xcbu, 0x68u, 0xc0u, 0x18u, 0xb0u, 0x23u, 0xdbu, 0x05u, - 0x03u, 0x60u, 0x10u, 0xbdu, 0xd0u, 0x03u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x80u, 0x27u, 0x0cu, 0x4cu, 0x7fu, 0x00u, + 0x03u, 0x60u, 0x10u, 0xbdu, 0xe0u, 0x03u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x80u, 0x27u, 0x0cu, 0x4cu, 0x7fu, 0x00u, 0x25u, 0x68u, 0xdbu, 0xb2u, 0x2cu, 0x6au, 0x06u, 0x19u, 0x05u, 0x9cu, 0x24u, 0x02u, 0x3cu, 0x40u, 0xffu, 0x3fu, 0x3au, 0x40u, 0x22u, 0x43u, 0x32u, 0x60u, 0x6au, 0x6au, 0x82u, 0x18u, 0x13u, 0x60u, 0xabu, 0x6au, 0xc3u, 0x18u, 0x19u, 0x60u, 0xebu, 0x6au, 0xc0u, 0x18u, 0x06u, 0x9bu, 0x03u, 0x60u, 0x00u, 0x20u, 0xf0u, 0xbdu, 0xc0u, 0x46u, - 0xd0u, 0x03u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x0du, 0x00u, 0x11u, 0x00u, 0x1au, 0x00u, 0x04u, 0x00u, 0xffu, 0xf7u, + 0xe0u, 0x03u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x0du, 0x00u, 0x11u, 0x00u, 0x1au, 0x00u, 0x04u, 0x00u, 0xffu, 0xf7u, 0xafu, 0xffu, 0x8cu, 0x23u, 0x04u, 0x9au, 0x5bu, 0x01u, 0xe2u, 0x50u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xc2u, 0xffu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x9bu, 0xffu, 0x04u, 0x4bu, 0x00u, 0x20u, 0x1bu, 0x68u, 0x1bu, 0x6bu, 0xe4u, 0x18u, - 0x23u, 0x68u, 0x2bu, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, 0x7fu, 0xb5u, 0x0du, 0x00u, + 0x23u, 0x68u, 0x2bu, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u, 0xe0u, 0x03u, 0x00u, 0x08u, 0x7fu, 0xb5u, 0x0du, 0x00u, 0x19u, 0x00u, 0x0eu, 0x4bu, 0x16u, 0x00u, 0x03u, 0x93u, 0x09u, 0x9au, 0x08u, 0x9bu, 0x04u, 0x00u, 0x02u, 0xf0u, 0xf1u, 0xfdu, 0x03u, 0xabu, 0x69u, 0x00u, 0x59u, 0x18u, 0x08u, 0x23u, 0x89u, 0x5du, 0x20u, 0x00u, 0x00u, 0x93u, 0x00u, 0x22u, 0x04u, 0x3bu, 0x02u, 0xf0u, 0x4eu, 0xfeu, 0x05u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xe4u, 0x18u, 0x02u, 0x23u, 0x22u, 0x68u, 0x1au, 0x42u, 0xfcu, 0xd1u, 0x7fu, 0xbdu, 0xc0u, 0x46u, 0x70u, 0x71u, 0x72u, 0x73u, - 0xd0u, 0x03u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x87u, 0xb0u, 0x05u, 0x93u, 0x20u, 0x4bu, 0x05u, 0x00u, 0x1bu, 0x68u, + 0xe0u, 0x03u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x87u, 0xb0u, 0x05u, 0x93u, 0x20u, 0x4bu, 0x05u, 0x00u, 0x1bu, 0x68u, 0x04u, 0x91u, 0x03u, 0x92u, 0x1fu, 0x1eu, 0x02u, 0xd0u, 0x9bu, 0x6bu, 0xc3u, 0x18u, 0x1fu, 0x68u, 0x00u, 0x26u, 0x1bu, 0x4bu, 0xf2u, 0x00u, 0xd2u, 0x18u, 0x03u, 0x99u, 0x08u, 0x23u, 0x28u, 0x00u, 0x02u, 0xf0u, 0x9cu, 0xfeu, 0x44u, 0x1eu, 0xa0u, 0x41u, 0x44u, 0x42u, 0x17u, 0x48u, 0x17u, 0x4bu, 0x04u, 0x40u, 0x01u, 0x36u, 0xe4u, 0x18u, @@ -303,8 +303,8 @@ const uint8_t cy_m0p_image[] = { 0x03u, 0x9au, 0x02u, 0x99u, 0x28u, 0x00u, 0x08u, 0x23u, 0x02u, 0xf0u, 0x4cu, 0xfeu, 0x08u, 0x36u, 0x0cu, 0x9au, 0x39u, 0x00u, 0x28u, 0x00u, 0x08u, 0x23u, 0x02u, 0xf0u, 0x45u, 0xfeu, 0x02u, 0x9bu, 0x04u, 0x9au, 0x28u, 0x00u, 0x01u, 0x97u, 0x00u, 0x96u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xa1u, 0xffu, 0x28u, 0x00u, 0x08u, 0x23u, 0x32u, 0x00u, - 0x05u, 0x99u, 0x02u, 0xf0u, 0x37u, 0xfeu, 0x20u, 0x00u, 0x07u, 0xb0u, 0xf0u, 0xbdu, 0xd0u, 0x03u, 0x00u, 0x08u, - 0x60u, 0x71u, 0x00u, 0x10u, 0xfdu, 0xffu, 0xceu, 0xffu, 0x03u, 0x00u, 0x31u, 0x00u, 0xf0u, 0xb5u, 0x89u, 0xb0u, + 0x05u, 0x99u, 0x02u, 0xf0u, 0x37u, 0xfeu, 0x20u, 0x00u, 0x07u, 0xb0u, 0xf0u, 0xbdu, 0xe0u, 0x03u, 0x00u, 0x08u, + 0x68u, 0x71u, 0x00u, 0x10u, 0xfdu, 0xffu, 0xceu, 0xffu, 0x03u, 0x00u, 0x31u, 0x00u, 0xf0u, 0xb5u, 0x89u, 0xb0u, 0x07u, 0x93u, 0x25u, 0x4bu, 0x04u, 0x00u, 0x1bu, 0x68u, 0x06u, 0x91u, 0x04u, 0x92u, 0x03u, 0x93u, 0x00u, 0x2bu, 0x03u, 0xd0u, 0x9bu, 0x6bu, 0xc3u, 0x18u, 0x1bu, 0x68u, 0x03u, 0x93u, 0x00u, 0x27u, 0x1fu, 0x4bu, 0x04u, 0x9du, 0xfeu, 0x00u, 0xf6u, 0x18u, 0x2bu, 0x00u, 0x10u, 0x33u, 0x05u, 0x93u, 0x08u, 0x23u, 0x32u, 0x00u, 0x29u, 0x00u, @@ -314,20 +314,20 @@ const uint8_t cy_m0p_image[] = { 0x20u, 0x00u, 0x08u, 0x23u, 0x02u, 0xf0u, 0xf6u, 0xfdu, 0x03u, 0x9fu, 0x03u, 0x9bu, 0x08u, 0x37u, 0x01u, 0x93u, 0x06u, 0x9au, 0x33u, 0x00u, 0x20u, 0x00u, 0x00u, 0x97u, 0x01u, 0x21u, 0xffu, 0xf7u, 0x4fu, 0xffu, 0x20u, 0x00u, 0x08u, 0x23u, 0x3au, 0x00u, 0x07u, 0x99u, 0x02u, 0xf0u, 0xe5u, 0xfdu, 0x28u, 0x00u, 0x09u, 0xb0u, 0xf0u, 0xbdu, - 0x08u, 0x35u, 0xcau, 0xe7u, 0x02u, 0x4du, 0xd4u, 0xe7u, 0xd0u, 0x03u, 0x00u, 0x08u, 0x60u, 0x71u, 0x00u, 0x10u, + 0x08u, 0x35u, 0xcau, 0xe7u, 0x02u, 0x4du, 0xd4u, 0xe7u, 0xe0u, 0x03u, 0x00u, 0x08u, 0x68u, 0x71u, 0x00u, 0x10u, 0x03u, 0x00u, 0x31u, 0x00u, 0x70u, 0xb5u, 0x0fu, 0x26u, 0x0bu, 0x4bu, 0x1bu, 0x68u, 0x9cu, 0x68u, 0x05u, 0x19u, 0x2cu, 0x68u, 0x34u, 0x40u, 0x04u, 0x2cu, 0xfbu, 0xd8u, 0x86u, 0x25u, 0x6du, 0x01u, 0x44u, 0x59u, 0x00u, 0x2cu, 0xfcu, 0xdbu, 0xdcu, 0x68u, 0x05u, 0x4du, 0x04u, 0x19u, 0x25u, 0x60u, 0xdcu, 0x68u, 0x04u, 0x19u, 0x21u, 0x60u, - 0xdbu, 0x68u, 0xc0u, 0x18u, 0x02u, 0x60u, 0x70u, 0xbdu, 0xd0u, 0x03u, 0x00u, 0x08u, 0x08u, 0x00u, 0x00u, 0x71u, + 0xdbu, 0x68u, 0xc0u, 0x18u, 0x02u, 0x60u, 0x70u, 0xbdu, 0xe0u, 0x03u, 0x00u, 0x08u, 0x08u, 0x00u, 0x00u, 0x71u, 0x30u, 0xb5u, 0x0fu, 0x25u, 0x06u, 0x4bu, 0x1cu, 0x68u, 0xa3u, 0x68u, 0xc2u, 0x18u, 0x13u, 0x68u, 0x2bu, 0x40u, 0x06u, 0x2bu, 0xfbu, 0xd8u, 0xe3u, 0x68u, 0x09u, 0x06u, 0xc0u, 0x18u, 0x01u, 0x60u, 0x30u, 0xbdu, 0xc0u, 0x46u, - 0xd0u, 0x03u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x0fu, 0x27u, 0x09u, 0x4cu, 0x26u, 0x68u, 0xb4u, 0x68u, 0x05u, 0x19u, + 0xe0u, 0x03u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x0fu, 0x27u, 0x09u, 0x4cu, 0x26u, 0x68u, 0xb4u, 0x68u, 0x05u, 0x19u, 0x2cu, 0x68u, 0x3cu, 0x40u, 0x06u, 0x2cu, 0xfbu, 0xd8u, 0xf4u, 0x68u, 0x09u, 0x03u, 0x00u, 0x19u, 0x80u, 0x24u, 0xe4u, 0x05u, 0x22u, 0x43u, 0x11u, 0x43u, 0x1bu, 0x04u, 0x19u, 0x43u, 0x01u, 0x60u, 0xf0u, 0xbdu, 0xc0u, 0x46u, - 0xd0u, 0x03u, 0x00u, 0x08u, 0x30u, 0xb5u, 0x0fu, 0x25u, 0x09u, 0x4bu, 0x1bu, 0x68u, 0x9au, 0x68u, 0x84u, 0x18u, + 0xe0u, 0x03u, 0x00u, 0x08u, 0x30u, 0xb5u, 0x0fu, 0x25u, 0x09u, 0x4bu, 0x1bu, 0x68u, 0x9au, 0x68u, 0x84u, 0x18u, 0x22u, 0x68u, 0x2au, 0x40u, 0x04u, 0x2au, 0xfbu, 0xd8u, 0xdau, 0x68u, 0x06u, 0x4cu, 0x82u, 0x18u, 0x14u, 0x60u, 0xdau, 0x68u, 0x82u, 0x18u, 0x11u, 0x60u, 0xdbu, 0x68u, 0xc0u, 0x18u, 0x08u, 0x23u, 0x03u, 0x60u, 0x30u, 0xbdu, - 0xd0u, 0x03u, 0x00u, 0x08u, 0x0cu, 0x00u, 0x00u, 0x70u, 0xf7u, 0xb5u, 0x04u, 0x00u, 0x16u, 0x00u, 0x1fu, 0x00u, + 0xe0u, 0x03u, 0x00u, 0x08u, 0x0cu, 0x00u, 0x00u, 0x70u, 0xf7u, 0xb5u, 0x04u, 0x00u, 0x16u, 0x00u, 0x1fu, 0x00u, 0x00u, 0x25u, 0x01u, 0x91u, 0x1cu, 0x4bu, 0xeau, 0x00u, 0xd2u, 0x18u, 0x31u, 0x00u, 0x08u, 0x23u, 0x20u, 0x00u, 0x02u, 0xf0u, 0xb2u, 0xfeu, 0x00u, 0x28u, 0x2cu, 0xd0u, 0x01u, 0x35u, 0x10u, 0x2du, 0xf2u, 0xd1u, 0x00u, 0x25u, 0x31u, 0x00u, 0x20u, 0x00u, 0x08u, 0x22u, 0xffu, 0xf7u, 0x85u, 0xffu, 0x08u, 0x23u, 0x20u, 0x00u, 0x1au, 0x00u, @@ -335,7 +335,7 @@ const uint8_t cy_m0p_image[] = { 0x39u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xbeu, 0xffu, 0x08u, 0x23u, 0x20u, 0x00u, 0x1au, 0x00u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xa0u, 0xffu, 0x01u, 0x99u, 0x20u, 0x00u, 0x4bu, 0x1eu, 0x99u, 0x41u, 0x52u, 0x31u, 0xffu, 0xf7u, 0x87u, 0xffu, 0x20u, 0x00u, 0x08u, 0x23u, 0x01u, 0x22u, 0x0cu, 0x21u, 0xffu, 0xf7u, 0x93u, 0xffu, 0x28u, 0x00u, - 0xfeu, 0xbdu, 0x02u, 0x4du, 0xd4u, 0xe7u, 0xc0u, 0x46u, 0xe0u, 0x71u, 0x00u, 0x10u, 0x03u, 0x00u, 0x31u, 0x00u, + 0xfeu, 0xbdu, 0x02u, 0x4du, 0xd4u, 0xe7u, 0xc0u, 0x46u, 0xe8u, 0x71u, 0x00u, 0x10u, 0x03u, 0x00u, 0x31u, 0x00u, 0xf0u, 0xb5u, 0x04u, 0x00u, 0x00u, 0x27u, 0x85u, 0xb0u, 0x02u, 0x91u, 0x00u, 0x92u, 0x03u, 0x93u, 0x26u, 0x4bu, 0x00u, 0x9du, 0xfeu, 0x00u, 0xf6u, 0x18u, 0x2bu, 0x00u, 0x10u, 0x33u, 0x01u, 0x93u, 0x08u, 0x23u, 0x32u, 0x00u, 0x29u, 0x00u, 0x20u, 0x00u, 0x02u, 0xf0u, 0x68u, 0xfeu, 0x00u, 0x28u, 0x04u, 0xd0u, 0x01u, 0x9bu, 0x9du, 0x42u, @@ -346,15 +346,15 @@ const uint8_t cy_m0p_image[] = { 0x20u, 0x00u, 0xffu, 0xf7u, 0x67u, 0xffu, 0x08u, 0x23u, 0x20u, 0x00u, 0x1au, 0x00u, 0x00u, 0x21u, 0xffu, 0xf7u, 0x49u, 0xffu, 0x02u, 0x99u, 0x20u, 0x00u, 0x4bu, 0x1eu, 0x99u, 0x41u, 0x54u, 0x31u, 0xffu, 0xf7u, 0x30u, 0xffu, 0x20u, 0x00u, 0x08u, 0x23u, 0x01u, 0x22u, 0x0cu, 0x21u, 0xffu, 0xf7u, 0x3cu, 0xffu, 0x28u, 0x00u, 0x05u, 0xb0u, - 0xf0u, 0xbdu, 0x08u, 0x35u, 0xbau, 0xe7u, 0xc0u, 0x46u, 0xe0u, 0x71u, 0x00u, 0x10u, 0x03u, 0x00u, 0x31u, 0x00u, + 0xf0u, 0xbdu, 0x08u, 0x35u, 0xbau, 0xe7u, 0xc0u, 0x46u, 0xe8u, 0x71u, 0x00u, 0x10u, 0x03u, 0x00u, 0x31u, 0x00u, 0x42u, 0x1eu, 0x03u, 0x00u, 0x00u, 0x20u, 0x04u, 0x2au, 0x03u, 0xd8u, 0x28u, 0x30u, 0x58u, 0x43u, 0x01u, 0x4bu, - 0xc0u, 0x18u, 0x70u, 0x47u, 0x60u, 0x72u, 0x00u, 0x10u, 0x09u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xc0u, 0x18u, + 0xc0u, 0x18u, 0x70u, 0x47u, 0x68u, 0x72u, 0x00u, 0x10u, 0x09u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xc0u, 0x18u, 0x08u, 0x4bu, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x04u, 0xd8u, 0x80u, 0x23u, 0x02u, 0x68u, 0x1au, 0x42u, 0xfcu, 0xd1u, 0x70u, 0x47u, 0x03u, 0x68u, 0x00u, 0x2bu, 0xfcu, 0xd1u, 0xfau, 0xe7u, 0xc0u, 0x46u, - 0xd0u, 0x03u, 0x00u, 0x08u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x0bu, 0x00u, 0x13u, 0x22u, 0x00u, 0x21u, + 0xe0u, 0x03u, 0x00u, 0x08u, 0xecu, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x0bu, 0x00u, 0x13u, 0x22u, 0x00u, 0x21u, 0x02u, 0xf0u, 0xf2u, 0xf9u, 0x10u, 0xbdu, 0x00u, 0x00u, 0x10u, 0xb5u, 0x13u, 0x00u, 0x07u, 0x4au, 0x12u, 0x68u, 0x29u, 0x32u, 0x14u, 0x78u, 0x0cu, 0x22u, 0x1fu, 0x2cu, 0x00u, 0xd9u, 0x04u, 0x32u, 0x91u, 0x40u, 0x01u, 0x3bu, - 0x0bu, 0x43u, 0x12u, 0x22u, 0x00u, 0x21u, 0x02u, 0xf0u, 0xdfu, 0xf9u, 0x10u, 0xbdu, 0xdcu, 0x05u, 0x00u, 0x08u, + 0x0bu, 0x43u, 0x12u, 0x22u, 0x00u, 0x21u, 0x02u, 0xf0u, 0xdfu, 0xf9u, 0x10u, 0xbdu, 0xecu, 0x05u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0xadu, 0xb0u, 0x04u, 0x00u, 0x04u, 0x91u, 0x05u, 0x92u, 0x03u, 0x93u, 0x00u, 0x29u, 0x00u, 0xd1u, 0x15u, 0xe1u, 0x03u, 0x9bu, 0x00u, 0x2bu, 0x00u, 0xd1u, 0x11u, 0xe1u, 0x32u, 0x9bu, 0x00u, 0x2bu, 0x00u, 0xd1u, 0x0du, 0xe1u, 0x33u, 0x9bu, 0x00u, 0x2bu, 0x00u, 0xd1u, 0x09u, 0xe1u, 0x32u, 0x9bu, 0x58u, 0x78u, 0xffu, 0xf7u, @@ -392,7 +392,7 @@ const uint8_t cy_m0p_image[] = { 0x00u, 0x28u, 0x00u, 0xd0u, 0x71u, 0xe7u, 0x03u, 0x9bu, 0xe9u, 0x1du, 0xc9u, 0x08u, 0x59u, 0x18u, 0x0au, 0x22u, 0x2bu, 0x00u, 0x20u, 0x00u, 0x04u, 0xf0u, 0xc4u, 0xf8u, 0x68u, 0xe7u, 0x08u, 0x4eu, 0x6bu, 0xe7u, 0x07u, 0x4eu, 0x6eu, 0xe7u, 0x07u, 0x4eu, 0x6cu, 0xe7u, 0xc0u, 0x46u, 0x09u, 0x80u, 0x00u, 0x00u, 0x01u, 0x00u, 0x32u, 0x00u, - 0xdcu, 0x05u, 0x00u, 0x08u, 0xb0u, 0xb0u, 0x00u, 0x00u, 0x0bu, 0x80u, 0x00u, 0x00u, 0x0bu, 0x00u, 0x32u, 0x00u, + 0xecu, 0x05u, 0x00u, 0x08u, 0xb0u, 0xb0u, 0x00u, 0x00u, 0x0bu, 0x80u, 0x00u, 0x00u, 0x0bu, 0x00u, 0x32u, 0x00u, 0x0au, 0x00u, 0x32u, 0x00u, 0xf0u, 0xb5u, 0x87u, 0xb0u, 0x04u, 0x00u, 0x0fu, 0x1eu, 0x04u, 0x92u, 0x03u, 0x93u, 0x00u, 0xd1u, 0x8bu, 0xe1u, 0x00u, 0x2au, 0x00u, 0xd1u, 0x88u, 0xe1u, 0x0cu, 0x9bu, 0x00u, 0x2bu, 0x00u, 0xd1u, 0x84u, 0xe1u, 0x0du, 0x9bu, 0x00u, 0x2bu, 0x00u, 0xd1u, 0x80u, 0xe1u, 0x58u, 0x78u, 0xffu, 0xf7u, 0x78u, 0xfeu, @@ -444,11 +444,11 @@ const uint8_t cy_m0p_image[] = { 0x05u, 0x21u, 0x20u, 0x00u, 0x03u, 0xf0u, 0x7au, 0xffu, 0x00u, 0x28u, 0x09u, 0xd0u, 0x01u, 0x23u, 0x0cu, 0x9au, 0x13u, 0x70u, 0x0eu, 0x49u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x27u, 0xfdu, 0x38u, 0x00u, 0x07u, 0xb0u, 0xf0u, 0xbdu, 0x0cu, 0x9bu, 0x18u, 0x70u, 0xf5u, 0xe7u, 0x04u, 0x4fu, 0x09u, 0x49u, 0xf3u, 0xe7u, 0x02u, 0x4fu, 0xf4u, 0xe7u, - 0x08u, 0x4fu, 0xf2u, 0xe7u, 0xf5u, 0xffu, 0xcdu, 0xffu, 0x0bu, 0x00u, 0x32u, 0x00u, 0xdcu, 0x05u, 0x00u, 0x08u, + 0x08u, 0x4fu, 0xf2u, 0xe7u, 0xf5u, 0xffu, 0xcdu, 0xffu, 0x0bu, 0x00u, 0x32u, 0x00u, 0xecu, 0x05u, 0x00u, 0x08u, 0x80u, 0x80u, 0x00u, 0x00u, 0x08u, 0x60u, 0x00u, 0x00u, 0x06u, 0x80u, 0x00u, 0x00u, 0xf1u, 0x7eu, 0x00u, 0x00u, 0x30u, 0x60u, 0x00u, 0x00u, 0x0au, 0x00u, 0x32u, 0x00u, 0x10u, 0xb5u, 0x13u, 0x00u, 0x07u, 0x4au, 0x12u, 0x68u, 0x29u, 0x32u, 0x14u, 0x78u, 0x0cu, 0x22u, 0x1fu, 0x2cu, 0x00u, 0xd9u, 0x04u, 0x32u, 0x91u, 0x40u, 0x01u, 0x3bu, - 0x0bu, 0x43u, 0x12u, 0x22u, 0x00u, 0x21u, 0x01u, 0xf0u, 0xefu, 0xfeu, 0x10u, 0xbdu, 0xdcu, 0x05u, 0x00u, 0x08u, + 0x0bu, 0x43u, 0x12u, 0x22u, 0x00u, 0x21u, 0x01u, 0xf0u, 0xefu, 0xfeu, 0x10u, 0xbdu, 0xecu, 0x05u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x04u, 0x00u, 0x85u, 0xb0u, 0x08u, 0x00u, 0x02u, 0x91u, 0x03u, 0x92u, 0x1eu, 0x00u, 0xffu, 0xf7u, 0xc7u, 0xfcu, 0x07u, 0x1eu, 0x00u, 0xd1u, 0x7bu, 0xe0u, 0x03u, 0x9bu, 0x00u, 0x2bu, 0x00u, 0xd1u, 0x77u, 0xe0u, 0x00u, 0x2eu, 0x00u, 0xd1u, 0x74u, 0xe0u, 0x73u, 0x68u, 0x00u, 0x2bu, 0x00u, 0xd1u, 0x70u, 0xe0u, 0xb3u, 0x68u, @@ -472,25 +472,25 @@ const uint8_t cy_m0p_image[] = { 0x12u, 0x01u, 0x13u, 0x43u, 0x09u, 0x03u, 0x0bu, 0x43u, 0x36u, 0x22u, 0x00u, 0x21u, 0x01u, 0xf0u, 0x44u, 0xfeu, 0x10u, 0xbdu, 0x00u, 0x00u, 0x09u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xc0u, 0x18u, 0x08u, 0x4bu, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x04u, 0xd8u, 0x80u, 0x23u, 0x02u, 0x68u, 0x1au, 0x42u, 0xfcu, 0xd1u, - 0x70u, 0x47u, 0x03u, 0x68u, 0x00u, 0x2bu, 0xfcu, 0xd1u, 0xfau, 0xe7u, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, - 0xdcu, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, 0xffu, 0xf7u, 0xe4u, 0xffu, 0x02u, 0x4bu, 0x1bu, 0x68u, - 0xdbu, 0x6bu, 0xe4u, 0x18u, 0x20u, 0x68u, 0x10u, 0xbdu, 0xd0u, 0x03u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x0au, 0x4bu, + 0x70u, 0x47u, 0x03u, 0x68u, 0x00u, 0x2bu, 0xfcu, 0xd1u, 0xfau, 0xe7u, 0xc0u, 0x46u, 0xe0u, 0x03u, 0x00u, 0x08u, + 0xecu, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, 0xffu, 0xf7u, 0xe4u, 0xffu, 0x02u, 0x4bu, 0x1bu, 0x68u, + 0xdbu, 0x6bu, 0xe4u, 0x18u, 0x20u, 0x68u, 0x10u, 0xbdu, 0xe0u, 0x03u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x0au, 0x4bu, 0x09u, 0x03u, 0x1bu, 0x68u, 0x12u, 0x01u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x06u, 0xd8u, 0x13u, 0x00u, 0x25u, 0x22u, 0x0bu, 0x43u, 0x00u, 0x21u, 0x01u, 0xf0u, 0x0fu, 0xfeu, 0x10u, 0xbdu, 0x0fu, 0x23u, 0x13u, 0x43u, - 0x0bu, 0x43u, 0x24u, 0x22u, 0xf6u, 0xe7u, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x07u, 0x4bu, + 0x0bu, 0x43u, 0x24u, 0x22u, 0xf6u, 0xe7u, 0xc0u, 0x46u, 0xecu, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x07u, 0x4bu, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x05u, 0xd8u, 0x05u, 0x4bu, 0x21u, 0x22u, 0x00u, 0x21u, - 0x01u, 0xf0u, 0xfau, 0xfdu, 0x10u, 0xbdu, 0x03u, 0x4bu, 0xf8u, 0xe7u, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, + 0x01u, 0xf0u, 0xfau, 0xfdu, 0x10u, 0xbdu, 0x03u, 0x4bu, 0xf8u, 0xe7u, 0xc0u, 0x46u, 0xecu, 0x05u, 0x00u, 0x08u, 0xc0u, 0xc0u, 0x00u, 0x00u, 0xcfu, 0xc0u, 0x00u, 0x00u, 0x00u, 0x23u, 0x10u, 0xb5u, 0x10u, 0x22u, 0x19u, 0x00u, 0x01u, 0xf0u, 0xeau, 0xfdu, 0x10u, 0xbdu, 0x09u, 0x03u, 0x0bu, 0x00u, 0x13u, 0x43u, 0x00u, 0x22u, 0x10u, 0xb5u, 0x11u, 0x00u, 0x01u, 0xf0u, 0xe1u, 0xfdu, 0x10u, 0xbdu, 0x10u, 0xb5u, 0x13u, 0x00u, 0x07u, 0x4au, 0x12u, 0x68u, 0x29u, 0x32u, 0x14u, 0x78u, 0x0cu, 0x22u, 0x1fu, 0x2cu, 0x00u, 0xd9u, 0x04u, 0x32u, 0x91u, 0x40u, 0x01u, 0x3bu, - 0x0bu, 0x43u, 0x12u, 0x22u, 0x00u, 0x21u, 0x01u, 0xf0u, 0xcfu, 0xfdu, 0x10u, 0xbdu, 0xdcu, 0x05u, 0x00u, 0x08u, + 0x0bu, 0x43u, 0x12u, 0x22u, 0x00u, 0x21u, 0x01u, 0xf0u, 0xcfu, 0xfdu, 0x10u, 0xbdu, 0xecu, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x1fu, 0x24u, 0x08u, 0x4bu, 0x89u, 0x06u, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x9cu, 0x42u, 0xa4u, 0x41u, 0x13u, 0x00u, 0x64u, 0x42u, 0x0cu, 0x34u, 0xa3u, 0x40u, 0x80u, 0x22u, 0x0bu, 0x43u, 0x00u, 0x21u, - 0x01u, 0xf0u, 0xbau, 0xfdu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x14u, 0x00u, + 0x01u, 0xf0u, 0xbau, 0xfdu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0xecu, 0x05u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x14u, 0x00u, 0x07u, 0x4au, 0x15u, 0x68u, 0x24u, 0x22u, 0x29u, 0x35u, 0x2du, 0x78u, 0x1fu, 0x2du, 0x00u, 0xd9u, 0x01u, 0x3au, 0x24u, 0x01u, 0x23u, 0x43u, 0x09u, 0x03u, 0x0bu, 0x43u, 0x00u, 0x21u, 0x01u, 0xf0u, 0xa5u, 0xfdu, 0x70u, 0xbdu, - 0xdcu, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x0bu, 0x00u, 0x13u, 0x22u, 0x00u, 0x21u, 0x01u, 0xf0u, 0x9cu, 0xfdu, + 0xecu, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x0bu, 0x00u, 0x13u, 0x22u, 0x00u, 0x21u, 0x01u, 0xf0u, 0x9cu, 0xfdu, 0x10u, 0xbdu, 0x00u, 0x23u, 0x10u, 0xb5u, 0x11u, 0x22u, 0x19u, 0x00u, 0x01u, 0xf0u, 0x95u, 0xfdu, 0x10u, 0xbdu, 0x70u, 0xb5u, 0x04u, 0x00u, 0x1bu, 0x4du, 0xffu, 0xf7u, 0x9fu, 0xffu, 0x20u, 0x00u, 0x01u, 0x22u, 0x02u, 0x21u, 0xffu, 0xf7u, 0xa1u, 0xffu, 0x20u, 0x00u, 0x00u, 0x22u, 0x03u, 0x21u, 0xffu, 0xf7u, 0x9cu, 0xffu, 0x2au, 0x00u, @@ -523,7 +523,7 @@ const uint8_t cy_m0p_image[] = { 0xffu, 0xf7u, 0x70u, 0xfeu, 0x94u, 0x4bu, 0x1bu, 0x78u, 0x00u, 0x2bu, 0x0bu, 0xd0u, 0x01u, 0x2bu, 0x01u, 0xd1u, 0x00u, 0xf0u, 0x35u, 0xfdu, 0x0eu, 0x9bu, 0x00u, 0x22u, 0x01u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x50u, 0xffu, 0x00u, 0xf0u, 0x24u, 0xfdu, 0x8du, 0x4bu, 0x18u, 0x78u, 0x01u, 0x38u, 0x04u, 0x28u, 0x01u, 0xd9u, 0x00u, 0xf0u, - 0x1du, 0xfdu, 0x04u, 0xf0u, 0x39u, 0xffu, 0x05u, 0x00u, 0x89u, 0x00u, 0x25u, 0x01u, 0x73u, 0x03u, 0x18u, 0x05u, + 0x1du, 0xfdu, 0x04u, 0xf0u, 0x3du, 0xffu, 0x05u, 0x00u, 0x89u, 0x00u, 0x25u, 0x01u, 0x73u, 0x03u, 0x18u, 0x05u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa1u, 0xfeu, 0x01u, 0x22u, 0x04u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa3u, 0xfeu, 0x00u, 0x22u, 0x05u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x9eu, 0xfeu, 0x80u, 0x22u, 0x02u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa2u, 0xfeu, 0xc0u, 0x22u, 0x03u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x9du, 0xfeu, 0xc0u, 0x22u, @@ -557,7 +557,7 @@ const uint8_t cy_m0p_image[] = { 0x43u, 0xfdu, 0x16u, 0x4bu, 0x36u, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0x01u, 0xf0u, 0x9du, 0xfbu, 0x03u, 0x23u, 0x02u, 0x22u, 0x04u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x4au, 0xfdu, 0x09u, 0x4bu, 0x3du, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0x01u, 0xf0u, 0x91u, 0xfbu, 0x00u, 0x21u, 0x06u, 0x4bu, 0x37u, 0x22u, 0x20u, 0x00u, 0x01u, 0xf0u, - 0x8bu, 0xfbu, 0x0eu, 0x21u, 0x70u, 0xe7u, 0xc0u, 0x46u, 0x80u, 0x00u, 0x00u, 0x08u, 0xccu, 0x03u, 0x00u, 0x08u, + 0x8bu, 0xfbu, 0x0eu, 0x21u, 0x70u, 0xe7u, 0xc0u, 0x46u, 0x80u, 0x00u, 0x00u, 0x08u, 0xdcu, 0x03u, 0x00u, 0x08u, 0x4eu, 0x00u, 0x40u, 0x00u, 0x4eu, 0x40u, 0x30u, 0x00u, 0x20u, 0x30u, 0x00u, 0x00u, 0x23u, 0x20u, 0x00u, 0x00u, 0x10u, 0x20u, 0x00u, 0x00u, 0x2eu, 0x00u, 0x40u, 0x00u, 0x2eu, 0x20u, 0x30u, 0x00u, 0x2eu, 0x20u, 0x40u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x81u, 0xfdu, 0x01u, 0x22u, 0x0au, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x83u, 0xfdu, @@ -688,7 +688,7 @@ const uint8_t cy_m0p_image[] = { 0x8bu, 0xffu, 0x00u, 0x21u, 0x44u, 0x4bu, 0x37u, 0x22u, 0x20u, 0x00u, 0x00u, 0xf0u, 0x85u, 0xffu, 0xe0u, 0x21u, 0x49u, 0x00u, 0xffu, 0xf7u, 0x69u, 0xfbu, 0x20u, 0x00u, 0xffu, 0xf7u, 0xeau, 0xf9u, 0x01u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xd8u, 0xf9u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xdcu, 0xf9u, 0x09u, 0xb0u, 0xf0u, 0xbdu, 0x42u, 0x4bu, - 0x18u, 0x78u, 0x01u, 0x38u, 0x04u, 0x28u, 0xf1u, 0xd8u, 0x04u, 0xf0u, 0x04u, 0xfau, 0x05u, 0x00u, 0x84u, 0x00u, + 0x18u, 0x78u, 0x01u, 0x38u, 0x04u, 0x28u, 0xf1u, 0xd8u, 0x04u, 0xf0u, 0x08u, 0xfau, 0x05u, 0x00u, 0x84u, 0x00u, 0xd1u, 0x00u, 0xc7u, 0x01u, 0xedu, 0xffu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x76u, 0xf9u, 0x01u, 0x22u, 0x04u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x78u, 0xf9u, 0x00u, 0x22u, 0x05u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x73u, 0xf9u, 0x02u, 0x22u, 0x00u, 0x21u, 0xffu, 0x32u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x76u, 0xf9u, 0x80u, 0x22u, 0x01u, 0x21u, @@ -704,7 +704,7 @@ const uint8_t cy_m0p_image[] = { 0x0bu, 0xffu, 0x00u, 0x21u, 0x0eu, 0x4bu, 0x37u, 0x22u, 0x20u, 0x00u, 0x00u, 0xf0u, 0x05u, 0xffu, 0x03u, 0x21u, 0xffu, 0xf7u, 0xeau, 0xfau, 0x9eu, 0x00u, 0x40u, 0x00u, 0x9eu, 0x90u, 0x30u, 0x00u, 0x82u, 0x70u, 0x00u, 0x00u, 0x73u, 0x70u, 0x00u, 0x00u, 0x9eu, 0x90u, 0x40u, 0x00u, 0x72u, 0x70u, 0x00u, 0x00u, 0x70u, 0x70u, 0x00u, 0x00u, - 0x71u, 0x70u, 0x00u, 0x00u, 0x60u, 0x70u, 0x00u, 0x00u, 0xccu, 0x03u, 0x00u, 0x08u, 0x12u, 0x10u, 0x00u, 0x00u, + 0x71u, 0x70u, 0x00u, 0x00u, 0x60u, 0x70u, 0x00u, 0x00u, 0xdcu, 0x03u, 0x00u, 0x08u, 0x12u, 0x10u, 0x00u, 0x00u, 0x4eu, 0x40u, 0x30u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xf7u, 0xf8u, 0x20u, 0x00u, 0x01u, 0x22u, 0x04u, 0x21u, 0xffu, 0xf7u, 0xf9u, 0xf8u, 0x20u, 0x00u, 0x00u, 0x22u, 0x05u, 0x21u, 0xffu, 0xf7u, 0xf4u, 0xf8u, 0x42u, 0x22u, 0x20u, 0x00u, 0xffu, 0x32u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xf7u, 0xf8u, 0xa0u, 0x22u, 0x20u, 0x00u, 0x52u, 0x00u, @@ -715,7 +715,7 @@ const uint8_t cy_m0p_image[] = { 0x20u, 0x22u, 0x00u, 0x21u, 0x00u, 0xf0u, 0xb0u, 0xfeu, 0x00u, 0x22u, 0x20u, 0x00u, 0x11u, 0x00u, 0x01u, 0x23u, 0xffu, 0xf7u, 0x5du, 0xf8u, 0x20u, 0x00u, 0x03u, 0x23u, 0x00u, 0x22u, 0x01u, 0x21u, 0xffu, 0xf7u, 0xeeu, 0xf8u, 0x01u, 0x23u, 0x00u, 0x22u, 0x04u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x3eu, 0xf8u, 0x7fu, 0xe7u, 0x1cu, 0x22u, - 0xb3u, 0x49u, 0x01u, 0xa8u, 0x04u, 0xf0u, 0x04u, 0xfbu, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa5u, 0xf8u, 0x01u, 0x22u, + 0xb3u, 0x49u, 0x01u, 0xa8u, 0x04u, 0xf0u, 0x08u, 0xfbu, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa5u, 0xf8u, 0x01u, 0x22u, 0x03u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa7u, 0xf8u, 0x00u, 0x22u, 0x04u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa2u, 0xf8u, 0xe0u, 0x22u, 0x05u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa6u, 0xf8u, 0xf0u, 0x22u, 0x00u, 0x21u, 0x52u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa0u, 0xf8u, 0x80u, 0x22u, 0x01u, 0x21u, 0x52u, 0x00u, 0x20u, 0x00u, @@ -746,7 +746,7 @@ const uint8_t cy_m0p_image[] = { 0x03u, 0x23u, 0x00u, 0x22u, 0x19u, 0x00u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0x69u, 0xffu, 0x3eu, 0x23u, 0x3du, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0x00u, 0xf0u, 0xb0u, 0xfdu, 0x00u, 0x21u, 0x3eu, 0x4bu, 0x37u, 0x22u, 0x20u, 0x00u, 0x00u, 0xf0u, 0xaau, 0xfdu, 0x23u, 0x21u, 0xffu, 0xf7u, 0x8fu, 0xf9u, 0x39u, 0x49u, 0x11u, 0x22u, 0x1cu, 0x31u, - 0x01u, 0xa8u, 0x04u, 0xf0u, 0x0du, 0xfau, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xaeu, 0xffu, 0x01u, 0x22u, 0x04u, 0x21u, + 0x01u, 0xa8u, 0x04u, 0xf0u, 0x11u, 0xfau, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xaeu, 0xffu, 0x01u, 0x22u, 0x04u, 0x21u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xb0u, 0xffu, 0x00u, 0x22u, 0x05u, 0x21u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xabu, 0xffu, 0x31u, 0x4au, 0x00u, 0x21u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xafu, 0xffu, 0xf0u, 0x22u, 0x01u, 0x21u, 0x52u, 0x00u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xa9u, 0xffu, 0x81u, 0x22u, 0x06u, 0x21u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xa4u, 0xffu, @@ -760,7 +760,7 @@ const uint8_t cy_m0p_image[] = { 0x4bu, 0xfdu, 0x04u, 0x23u, 0x00u, 0x22u, 0x19u, 0x00u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xf8u, 0xfeu, 0x4eu, 0x23u, 0x3du, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0x00u, 0xf0u, 0x3fu, 0xfdu, 0x00u, 0x21u, 0x07u, 0x4bu, 0x37u, 0x22u, 0x20u, 0x00u, 0x00u, 0xf0u, 0x39u, 0xfdu, 0x43u, 0x21u, 0xffu, 0xf7u, 0x1eu, 0xf9u, 0x12u, 0x10u, 0x00u, 0x00u, - 0x55u, 0x78u, 0x00u, 0x10u, 0x3eu, 0x30u, 0x30u, 0x00u, 0x01u, 0x02u, 0x00u, 0x00u, 0x4eu, 0x40u, 0x30u, 0x00u, + 0x5du, 0x78u, 0x00u, 0x10u, 0x3eu, 0x30u, 0x30u, 0x00u, 0x01u, 0x02u, 0x00u, 0x00u, 0x4eu, 0x40u, 0x30u, 0x00u, 0x70u, 0xb5u, 0x0cu, 0x00u, 0x05u, 0x00u, 0xfeu, 0xf7u, 0xdau, 0xfeu, 0x09u, 0x4bu, 0x26u, 0x01u, 0x33u, 0x43u, 0x28u, 0x00u, 0x3du, 0x22u, 0x00u, 0x21u, 0x00u, 0xf0u, 0x1fu, 0xfdu, 0x24u, 0x03u, 0x05u, 0x4bu, 0x34u, 0x43u, 0x28u, 0x00u, 0x23u, 0x43u, 0x37u, 0x22u, 0x00u, 0x21u, 0x00u, 0xf0u, 0x16u, 0xfdu, 0x70u, 0xbdu, 0xc0u, 0x46u, @@ -772,7 +772,7 @@ const uint8_t cy_m0p_image[] = { 0xebu, 0xfcu, 0x0bu, 0x4bu, 0x2du, 0x03u, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x07u, 0xd8u, 0x2bu, 0x00u, 0x26u, 0x22u, 0x3bu, 0x43u, 0x30u, 0x00u, 0x00u, 0x21u, 0x00u, 0xf0u, 0xddu, 0xfcu, 0xf8u, 0xbdu, 0x0fu, 0x23u, 0x2bu, 0x43u, 0x3bu, 0x43u, 0x25u, 0x22u, 0xf5u, 0xe7u, 0xc0u, 0x46u, 0x0eu, 0x00u, 0x80u, 0x00u, - 0xdcu, 0x05u, 0x00u, 0x08u, 0x07u, 0xb5u, 0x00u, 0x93u, 0x13u, 0x00u, 0xfeu, 0xf7u, 0xf5u, 0xffu, 0x07u, 0xbdu, + 0xecu, 0x05u, 0x00u, 0x08u, 0x07u, 0xb5u, 0x00u, 0x93u, 0x13u, 0x00u, 0xfeu, 0xf7u, 0xf5u, 0xffu, 0x07u, 0xbdu, 0xf8u, 0xb5u, 0x04u, 0x00u, 0x17u, 0x00u, 0x1eu, 0x00u, 0x0du, 0x00u, 0xfeu, 0xf7u, 0xd5u, 0xfeu, 0x3au, 0x00u, 0x07u, 0x21u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xd7u, 0xfeu, 0x32u, 0x00u, 0x08u, 0x21u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xd2u, 0xfeu, 0x2au, 0x00u, 0x0bu, 0x21u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xcdu, 0xfeu, 0x06u, 0x9au, 0x09u, 0x21u, @@ -867,16 +867,16 @@ const uint8_t cy_m0p_image[] = { 0x05u, 0x90u, 0x08u, 0x22u, 0x00u, 0x97u, 0x07u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xd0u, 0xfeu, 0x01u, 0x22u, 0x05u, 0x9bu, 0x13u, 0x42u, 0x0au, 0xd0u, 0x0bu, 0x23u, 0x01u, 0x93u, 0x01u, 0x3bu, 0x00u, 0x93u, 0x02u, 0x97u, 0x01u, 0x3bu, 0x07u, 0x32u, 0x07u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x0eu, 0xfeu, 0x01u, 0x35u, 0xcdu, 0xe7u, - 0xdcu, 0x05u, 0x00u, 0x08u, 0xc5u, 0x60u, 0x00u, 0x00u, 0xc6u, 0xc0u, 0x00u, 0x00u, 0xd0u, 0x03u, 0x00u, 0x08u, + 0xecu, 0x05u, 0x00u, 0x08u, 0xc5u, 0x60u, 0x00u, 0x00u, 0xc6u, 0xc0u, 0x00u, 0x00u, 0xe0u, 0x03u, 0x00u, 0x08u, 0x80u, 0x22u, 0x0du, 0x4bu, 0x52u, 0x00u, 0x90u, 0x42u, 0x11u, 0xd0u, 0x07u, 0xd8u, 0x01u, 0x22u, 0xc0u, 0x28u, 0x0eu, 0xd0u, 0x02u, 0x22u, 0xe0u, 0x28u, 0x0bu, 0xd0u, 0x00u, 0x22u, 0x09u, 0xe0u, 0xc0u, 0x22u, 0x52u, 0x00u, 0x90u, 0x42u, 0x07u, 0xd0u, 0x05u, 0x4au, 0x90u, 0x42u, 0xf6u, 0xd1u, 0x05u, 0x22u, 0x00u, 0xe0u, 0x03u, 0x22u, - 0x1au, 0x70u, 0x70u, 0x47u, 0x04u, 0x22u, 0xfbu, 0xe7u, 0xccu, 0x03u, 0x00u, 0x08u, 0x09u, 0x02u, 0x00u, 0x00u, + 0x1au, 0x70u, 0x70u, 0x47u, 0x04u, 0x22u, 0xfbu, 0xe7u, 0xdcu, 0x03u, 0x00u, 0x08u, 0x09u, 0x02u, 0x00u, 0x00u, 0x01u, 0x4bu, 0x18u, 0x70u, 0x70u, 0x47u, 0xc0u, 0x46u, 0x80u, 0x00u, 0x00u, 0x08u, 0x13u, 0xb5u, 0x04u, 0x00u, 0x05u, 0x98u, 0x00u, 0x90u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x2fu, 0xffu, 0x20u, 0x00u, 0xfeu, 0xf7u, 0x62u, 0xfbu, 0x13u, 0xbdu, 0x00u, 0x00u, 0xf0u, 0xb5u, 0x93u, 0xb0u, 0x05u, 0x93u, 0x1au, 0xabu, 0x1cu, 0x78u, 0x65u, 0x4bu, 0x05u, 0x00u, 0x1bu, 0x68u, 0x03u, 0x91u, 0x04u, 0x92u, 0x1eu, 0x1eu, 0x02u, 0xd0u, 0x9bu, 0x6bu, 0xc3u, 0x18u, - 0x1eu, 0x68u, 0x30u, 0x22u, 0x00u, 0x21u, 0x06u, 0xa8u, 0x03u, 0xf0u, 0x03u, 0xfeu, 0x33u, 0x00u, 0x81u, 0x33u, + 0x1eu, 0x68u, 0x30u, 0x22u, 0x00u, 0x21u, 0x06u, 0xa8u, 0x03u, 0xf0u, 0x07u, 0xfeu, 0x33u, 0x00u, 0x81u, 0x33u, 0x22u, 0x00u, 0xffu, 0x33u, 0x06u, 0xa9u, 0x28u, 0x00u, 0x01u, 0xf0u, 0xfcu, 0xfbu, 0x04u, 0x1eu, 0x00u, 0xd0u, 0x86u, 0xe0u, 0x33u, 0x00u, 0x80u, 0x33u, 0x01u, 0x93u, 0x98u, 0x23u, 0x01u, 0x9au, 0xdbu, 0x00u, 0x77u, 0x1cu, 0xf6u, 0x50u, 0xffu, 0x37u, 0xf3u, 0x18u, 0x5au, 0x60u, 0x9fu, 0x60u, 0x19u, 0x9au, 0x09u, 0x9bu, 0x9au, 0x42u, @@ -900,10 +900,10 @@ const uint8_t cy_m0p_image[] = { 0x28u, 0x00u, 0x00u, 0xf0u, 0xa7u, 0xfbu, 0x02u, 0x9au, 0x09u, 0x9bu, 0x9bu, 0x1au, 0x19u, 0x9au, 0x9bu, 0xb2u, 0xb9u, 0x18u, 0x89u, 0xe7u, 0x02u, 0x9bu, 0x18u, 0x9au, 0x39u, 0x00u, 0x28u, 0x00u, 0x00u, 0xf0u, 0x9au, 0xfbu, 0x86u, 0xe7u, 0xfau, 0x5cu, 0x01u, 0x9cu, 0x4au, 0x40u, 0xf2u, 0x54u, 0xfau, 0x5cu, 0x42u, 0x40u, 0xe2u, 0x54u, - 0x01u, 0x33u, 0x80u, 0xe7u, 0xd0u, 0x03u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x66u, 0x4cu, 0x05u, 0x00u, 0xa5u, 0x44u, + 0x01u, 0x33u, 0x80u, 0xe7u, 0xe0u, 0x03u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x66u, 0x4cu, 0x05u, 0x00u, 0xa5u, 0x44u, 0x04u, 0x92u, 0x93u, 0x22u, 0x05u, 0x93u, 0x13u, 0xaeu, 0xaeu, 0xabu, 0x1cu, 0x78u, 0x03u, 0x91u, 0x92u, 0x00u, - 0x00u, 0x21u, 0x30u, 0x00u, 0x03u, 0xf0u, 0x35u, 0xfdu, 0x30u, 0x22u, 0x00u, 0x21u, 0x07u, 0xa8u, 0x03u, 0xf0u, - 0x30u, 0xfdu, 0x22u, 0x00u, 0x73u, 0xabu, 0x07u, 0xa9u, 0x28u, 0x00u, 0x01u, 0xf0u, 0x77u, 0xfdu, 0x04u, 0x1eu, + 0x00u, 0x21u, 0x30u, 0x00u, 0x03u, 0xf0u, 0x39u, 0xfdu, 0x30u, 0x22u, 0x00u, 0x21u, 0x07u, 0xa8u, 0x03u, 0xf0u, + 0x34u, 0xfdu, 0x22u, 0x00u, 0x73u, 0xabu, 0x07u, 0xa9u, 0x28u, 0x00u, 0x01u, 0xf0u, 0x77u, 0xfdu, 0x04u, 0x1eu, 0x3bu, 0xd1u, 0x90u, 0x23u, 0x9bu, 0x00u, 0xf6u, 0x50u, 0x33u, 0xaau, 0x04u, 0x33u, 0xf2u, 0x50u, 0x0au, 0x9fu, 0x04u, 0x33u, 0x53u, 0xaau, 0xf2u, 0x50u, 0x10u, 0x9bu, 0xbeu, 0xb2u, 0x01u, 0x93u, 0x02u, 0x00u, 0x33u, 0x00u, 0x53u, 0xa9u, 0x28u, 0x00u, 0x00u, 0xf0u, 0x6eu, 0xfcu, 0xadu, 0x9bu, 0xbbu, 0x42u, 0x2eu, 0xd9u, 0x07u, 0xa9u, @@ -933,10 +933,10 @@ const uint8_t cy_m0p_image[] = { 0x13u, 0x43u, 0x33u, 0x60u, 0x00u, 0x2du, 0x01u, 0xd1u, 0x00u, 0x29u, 0x12u, 0xd0u, 0x80u, 0x22u, 0xa3u, 0x68u, 0x52u, 0x02u, 0xc3u, 0x18u, 0x19u, 0x68u, 0x11u, 0x42u, 0xfcu, 0xd0u, 0x23u, 0x68u, 0xc0u, 0x18u, 0x08u, 0x4bu, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x04u, 0xd8u, 0x80u, 0x23u, 0x02u, 0x68u, 0x1au, 0x42u, - 0xfcu, 0xd1u, 0xf7u, 0xbdu, 0x03u, 0x68u, 0x00u, 0x2bu, 0xfcu, 0xd1u, 0xfau, 0xe7u, 0xd0u, 0x03u, 0x00u, 0x08u, - 0xdcu, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x1fu, 0x24u, 0x08u, 0x4bu, 0x89u, 0x06u, 0x1bu, 0x68u, 0x29u, 0x33u, + 0xfcu, 0xd1u, 0xf7u, 0xbdu, 0x03u, 0x68u, 0x00u, 0x2bu, 0xfcu, 0xd1u, 0xfau, 0xe7u, 0xe0u, 0x03u, 0x00u, 0x08u, + 0xecu, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x1fu, 0x24u, 0x08u, 0x4bu, 0x89u, 0x06u, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x9cu, 0x42u, 0xa4u, 0x41u, 0x13u, 0x00u, 0x64u, 0x42u, 0x0cu, 0x34u, 0xa3u, 0x40u, 0x80u, 0x22u, - 0x0bu, 0x43u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xb0u, 0xffu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, + 0x0bu, 0x43u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xb0u, 0xffu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0xecu, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, 0x00u, 0x22u, 0x0eu, 0x21u, 0xffu, 0xf7u, 0xe4u, 0xffu, 0x20u, 0x00u, 0x00u, 0x22u, 0x0du, 0x21u, 0xffu, 0xf7u, 0xdfu, 0xffu, 0x20u, 0x00u, 0x00u, 0x22u, 0x0cu, 0x21u, 0xffu, 0xf7u, 0xdau, 0xffu, 0x20u, 0x00u, 0x00u, 0x22u, 0x0bu, 0x21u, 0xffu, 0xf7u, 0xd5u, 0xffu, 0x20u, 0x00u, 0x00u, 0x22u, 0x0au, 0x21u, @@ -947,10 +947,10 @@ const uint8_t cy_m0p_image[] = { 0x20u, 0x00u, 0x00u, 0x22u, 0x03u, 0x21u, 0xffu, 0xf7u, 0xadu, 0xffu, 0x20u, 0x00u, 0x00u, 0x22u, 0x02u, 0x21u, 0xffu, 0xf7u, 0xa8u, 0xffu, 0x20u, 0x00u, 0x00u, 0x22u, 0x01u, 0x21u, 0xffu, 0xf7u, 0xa3u, 0xffu, 0x00u, 0x22u, 0x20u, 0x00u, 0x11u, 0x00u, 0xffu, 0xf7u, 0x9eu, 0xffu, 0x03u, 0x4bu, 0x0fu, 0x21u, 0x1au, 0x68u, 0x20u, 0x00u, - 0x92u, 0x08u, 0xffu, 0xf7u, 0x97u, 0xffu, 0x10u, 0xbdu, 0xd4u, 0x03u, 0x00u, 0x08u, 0x05u, 0x4bu, 0x1bu, 0x68u, + 0x92u, 0x08u, 0xffu, 0xf7u, 0x97u, 0xffu, 0x10u, 0xbdu, 0xe4u, 0x03u, 0x00u, 0x08u, 0x05u, 0x4bu, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1au, 0x78u, 0x04u, 0x4bu, 0x1fu, 0x2au, 0x00u, 0xd9u, 0x04u, 0x4bu, 0x04u, 0x4au, 0x13u, 0x60u, - 0x70u, 0x47u, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x84u, 0x78u, 0x00u, 0x10u, 0xd8u, 0x78u, 0x00u, 0x10u, - 0xd0u, 0x03u, 0x00u, 0x08u, 0x2fu, 0x4bu, 0x70u, 0xb5u, 0x14u, 0x00u, 0x1au, 0x68u, 0x00u, 0x2au, 0x2cu, 0xd0u, + 0x70u, 0x47u, 0xc0u, 0x46u, 0xecu, 0x05u, 0x00u, 0x08u, 0x8cu, 0x78u, 0x00u, 0x10u, 0xe0u, 0x78u, 0x00u, 0x10u, + 0xe0u, 0x03u, 0x00u, 0x08u, 0x2fu, 0x4bu, 0x70u, 0xb5u, 0x14u, 0x00u, 0x1au, 0x68u, 0x00u, 0x2au, 0x2cu, 0xd0u, 0x00u, 0x29u, 0x09u, 0xd1u, 0x00u, 0x2cu, 0x28u, 0xd1u, 0x13u, 0x6du, 0xc1u, 0x18u, 0x2au, 0x4bu, 0x1bu, 0x68u, 0x9cu, 0x6cu, 0x00u, 0x29u, 0x21u, 0xd0u, 0xa4u, 0x00u, 0x28u, 0x4bu, 0x65u, 0x1eu, 0x9du, 0x42u, 0x1cu, 0xd8u, 0x80u, 0x23u, 0x1bu, 0x01u, 0x9cu, 0x42u, 0x3eu, 0xd0u, 0x0du, 0xd8u, 0x80u, 0x23u, 0x9bu, 0x00u, 0x9cu, 0x42u, @@ -962,8 +962,8 @@ const uint8_t cy_m0p_image[] = { 0xebu, 0xd1u, 0x1fu, 0x2eu, 0x02u, 0xd9u, 0x10u, 0x4du, 0x1bu, 0x02u, 0x43u, 0x51u, 0x93u, 0x6bu, 0xa2u, 0x08u, 0xc3u, 0x18u, 0x19u, 0x60u, 0x0fu, 0x21u, 0xffu, 0xf7u, 0x2du, 0xffu, 0x00u, 0x20u, 0x0bu, 0x4bu, 0x1cu, 0x60u, 0x70u, 0xbdu, 0x7cu, 0x23u, 0xe4u, 0xe7u, 0x78u, 0x23u, 0xe2u, 0xe7u, 0x60u, 0x23u, 0xe0u, 0xe7u, 0x40u, 0x23u, - 0xdeu, 0xe7u, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, 0xdcu, 0x05u, 0x00u, 0x08u, 0xffu, 0x7fu, 0x00u, 0x00u, - 0x0bu, 0x00u, 0x32u, 0x00u, 0xffu, 0x3fu, 0x00u, 0x00u, 0x88u, 0x14u, 0x00u, 0x00u, 0xd4u, 0x03u, 0x00u, 0x08u, + 0xdeu, 0xe7u, 0xc0u, 0x46u, 0xe0u, 0x03u, 0x00u, 0x08u, 0xecu, 0x05u, 0x00u, 0x08u, 0xffu, 0x7fu, 0x00u, 0x00u, + 0x0bu, 0x00u, 0x32u, 0x00u, 0xffu, 0x3fu, 0x00u, 0x00u, 0x88u, 0x14u, 0x00u, 0x00u, 0xe4u, 0x03u, 0x00u, 0x08u, 0x20u, 0x4bu, 0x21u, 0x49u, 0x1bu, 0x68u, 0x09u, 0x68u, 0x9au, 0x6cu, 0x92u, 0x00u, 0x00u, 0x29u, 0x1cu, 0xd0u, 0x1eu, 0x49u, 0x09u, 0x68u, 0x00u, 0x29u, 0x18u, 0xd0u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x2fu, 0xd9u, 0x1bu, 0x4bu, 0xc3u, 0x58u, 0x5bu, 0x04u, 0x5bu, 0x0eu, 0x70u, 0x2bu, 0x1du, 0xd0u, 0x08u, 0xd8u, 0x40u, 0x2bu, @@ -972,89 +972,89 @@ const uint8_t cy_m0p_image[] = { 0x13u, 0xd0u, 0x7fu, 0x2bu, 0xf9u, 0xd1u, 0x80u, 0x22u, 0x52u, 0x00u, 0xf6u, 0xe7u, 0x80u, 0x22u, 0xd2u, 0x01u, 0xf3u, 0xe7u, 0x80u, 0x22u, 0x92u, 0x01u, 0xf0u, 0xe7u, 0x80u, 0x22u, 0x52u, 0x01u, 0xedu, 0xe7u, 0x80u, 0x22u, 0x12u, 0x01u, 0xeau, 0xe7u, 0x80u, 0x22u, 0xd2u, 0x00u, 0xe7u, 0xe7u, 0x80u, 0x22u, 0x92u, 0x00u, 0xe4u, 0xe7u, - 0x0au, 0x00u, 0xe2u, 0xe7u, 0xdcu, 0x05u, 0x00u, 0x08u, 0xd0u, 0x03u, 0x00u, 0x08u, 0xd4u, 0x03u, 0x00u, 0x08u, + 0x0au, 0x00u, 0xe2u, 0xe7u, 0xecu, 0x05u, 0x00u, 0x08u, 0xe0u, 0x03u, 0x00u, 0x08u, 0xe4u, 0x03u, 0x00u, 0x08u, 0x88u, 0x14u, 0x00u, 0x00u, 0x10u, 0xb5u, 0x04u, 0x00u, 0xffu, 0xf7u, 0x30u, 0xffu, 0x17u, 0x4au, 0x18u, 0x49u, 0x13u, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x17u, 0xd8u, 0x16u, 0x4bu, 0x23u, 0x60u, 0x01u, 0x20u, 0x09u, 0x68u, 0x4bu, 0x6bu, 0xe3u, 0x18u, 0x18u, 0x60u, 0x13u, 0x4bu, 0x1bu, 0x68u, 0x00u, 0x2bu, 0x07u, 0xd1u, 0x13u, 0x68u, 0x09u, 0x6du, 0x9au, 0x6cu, 0x61u, 0x18u, 0x92u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x2au, 0xffu, 0x20u, 0x00u, 0xffu, 0xf7u, 0xbdu, 0xfeu, 0x00u, 0x20u, 0x10u, 0xbdu, 0x23u, 0x68u, 0x0bu, 0x48u, 0x03u, 0x40u, 0x23u, 0x60u, 0x0bu, 0x68u, 0x0au, 0x48u, 0x5bu, 0x68u, 0xe3u, 0x18u, 0x18u, 0x60u, 0x80u, 0x23u, 0x20u, 0x68u, - 0x1bu, 0x06u, 0x03u, 0x43u, 0x23u, 0x60u, 0x03u, 0x23u, 0xa3u, 0x60u, 0xd8u, 0xe7u, 0xdcu, 0x05u, 0x00u, 0x08u, - 0xd0u, 0x03u, 0x00u, 0x08u, 0x03u, 0x00u, 0x00u, 0x80u, 0xd4u, 0x03u, 0x00u, 0x08u, 0xffu, 0xffu, 0xfeu, 0x7fu, + 0x1bu, 0x06u, 0x03u, 0x43u, 0x23u, 0x60u, 0x03u, 0x23u, 0xa3u, 0x60u, 0xd8u, 0xe7u, 0xecu, 0x05u, 0x00u, 0x08u, + 0xe0u, 0x03u, 0x00u, 0x08u, 0x03u, 0x00u, 0x00u, 0x80u, 0xe4u, 0x03u, 0x00u, 0x08u, 0xffu, 0xffu, 0xfeu, 0x7fu, 0x01u, 0x00u, 0x02u, 0x00u, 0x03u, 0x23u, 0x03u, 0x70u, 0x00u, 0x20u, 0x70u, 0x47u, 0x06u, 0x4bu, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1au, 0x78u, 0x00u, 0x23u, 0x03u, 0x60u, 0x1fu, 0x2au, 0x03u, 0xd8u, 0x00u, 0x20u, 0x03u, 0x4bu, - 0x18u, 0x60u, 0x70u, 0x47u, 0x83u, 0x60u, 0xf9u, 0xe7u, 0xdcu, 0x05u, 0x00u, 0x08u, 0xd4u, 0x03u, 0x00u, 0x08u, + 0x18u, 0x60u, 0x70u, 0x47u, 0x83u, 0x60u, 0xf9u, 0xe7u, 0xecu, 0x05u, 0x00u, 0x08u, 0xe4u, 0x03u, 0x00u, 0x08u, 0x30u, 0xb5u, 0x01u, 0x29u, 0x0bu, 0xd9u, 0x01u, 0x22u, 0x0au, 0x40u, 0x54u, 0x42u, 0x62u, 0x41u, 0xcbu, 0x0fu, 0x5bu, 0x18u, 0x5bu, 0x10u, 0x9bu, 0x1au, 0x02u, 0x00u, 0x01u, 0x39u, 0x8bu, 0x42u, 0x00u, 0xdbu, 0x30u, 0xbdu, 0x14u, 0x78u, 0x45u, 0x5cu, 0x15u, 0x70u, 0x44u, 0x54u, 0x01u, 0x32u, 0x01u, 0x39u, 0xf5u, 0xe7u, 0x00u, 0x00u, 0x03u, 0x4bu, 0x1bu, 0x68u, 0x9bu, 0x68u, 0xc0u, 0x18u, 0x0fu, 0x23u, 0x00u, 0x68u, 0x18u, 0x40u, 0x70u, 0x47u, - 0xd0u, 0x03u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x04u, 0x00u, 0x0du, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xf0u, 0xffu, + 0xe0u, 0x03u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x04u, 0x00u, 0x0du, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xf0u, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x80u, 0x21u, 0x05u, 0x4bu, 0xc9u, 0x05u, 0x1au, 0x68u, 0xd3u, 0x68u, 0xe3u, 0x18u, - 0x19u, 0x60u, 0xd3u, 0x68u, 0xe4u, 0x18u, 0x25u, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, + 0x19u, 0x60u, 0xd3u, 0x68u, 0xe4u, 0x18u, 0x25u, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u, 0xe0u, 0x03u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x04u, 0x00u, 0x0eu, 0x00u, 0x15u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xd9u, 0xffu, 0x05u, 0x28u, 0xfau, 0xd8u, 0x06u, 0x4bu, 0x06u, 0x49u, 0x1bu, 0x68u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x11u, 0x60u, 0xdau, 0x68u, - 0xa2u, 0x18u, 0x16u, 0x60u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0x25u, 0x60u, 0x70u, 0xbdu, 0xd0u, 0x03u, 0x00u, 0x08u, + 0xa2u, 0x18u, 0x16u, 0x60u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0x25u, 0x60u, 0x70u, 0xbdu, 0xe0u, 0x03u, 0x00u, 0x08u, 0x10u, 0x00u, 0x00u, 0x41u, 0xf8u, 0xb5u, 0x04u, 0x00u, 0x0fu, 0x00u, 0x16u, 0x00u, 0x1du, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xbeu, 0xffu, 0x04u, 0x28u, 0xfau, 0xd8u, 0x07u, 0x4bu, 0x08u, 0x49u, 0x1bu, 0x68u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x11u, 0x60u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x17u, 0x60u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x16u, 0x60u, - 0xdbu, 0x68u, 0xe4u, 0x18u, 0x25u, 0x60u, 0xf8u, 0xbdu, 0xd0u, 0x03u, 0x00u, 0x08u, 0x10u, 0x02u, 0x00u, 0x42u, + 0xdbu, 0x68u, 0xe4u, 0x18u, 0x25u, 0x60u, 0xf8u, 0xbdu, 0xe0u, 0x03u, 0x00u, 0x08u, 0x10u, 0x02u, 0x00u, 0x42u, 0xf8u, 0xb5u, 0x04u, 0x00u, 0x0fu, 0x00u, 0x16u, 0x00u, 0x1du, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa0u, 0xffu, 0x03u, 0x28u, 0xfau, 0xd8u, 0x09u, 0x4bu, 0x0au, 0x49u, 0x1bu, 0x68u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x11u, 0x60u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x17u, 0x60u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x16u, 0x60u, 0xdau, 0x68u, 0xa2u, 0x18u, - 0x15u, 0x60u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0x06u, 0x9bu, 0x23u, 0x60u, 0xf8u, 0xbdu, 0xd0u, 0x03u, 0x00u, 0x08u, + 0x15u, 0x60u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0x06u, 0x9bu, 0x23u, 0x60u, 0xf8u, 0xbdu, 0xe0u, 0x03u, 0x00u, 0x08u, 0x10u, 0x32u, 0x00u, 0x43u, 0x70u, 0xb5u, 0x04u, 0x00u, 0x0du, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x80u, 0xffu, 0x07u, 0x28u, 0xfau, 0xd8u, 0x03u, 0x4bu, 0x2du, 0x06u, 0x1bu, 0x68u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0x25u, 0x60u, - 0x70u, 0xbdu, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x05u, 0x00u, 0x0cu, 0x00u, 0x1eu, 0x00u, + 0x70u, 0xbdu, 0xc0u, 0x46u, 0xe0u, 0x03u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x05u, 0x00u, 0x0cu, 0x00u, 0x1eu, 0x00u, 0x28u, 0x00u, 0xffu, 0xf7u, 0x6du, 0xffu, 0x07u, 0x28u, 0xfau, 0xd8u, 0x05u, 0x4bu, 0x24u, 0x06u, 0x1bu, 0x68u, 0xdbu, 0x68u, 0xedu, 0x18u, 0x01u, 0x23u, 0xb3u, 0x40u, 0x1cu, 0x43u, 0x2cu, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u, - 0xd0u, 0x03u, 0x00u, 0x08u, 0xf8u, 0xb5u, 0x07u, 0x00u, 0x0cu, 0x00u, 0x1du, 0x00u, 0x06u, 0xabu, 0x1eu, 0x78u, + 0xe0u, 0x03u, 0x00u, 0x08u, 0xf8u, 0xb5u, 0x07u, 0x00u, 0x0cu, 0x00u, 0x1du, 0x00u, 0x06u, 0xabu, 0x1eu, 0x78u, 0x38u, 0x00u, 0xffu, 0xf7u, 0x55u, 0xffu, 0x07u, 0x28u, 0xfau, 0xd8u, 0x06u, 0x4bu, 0x02u, 0x21u, 0x1bu, 0x68u, 0xb1u, 0x40u, 0xd8u, 0x68u, 0x01u, 0x23u, 0xabu, 0x40u, 0x24u, 0x06u, 0x19u, 0x43u, 0x38u, 0x18u, 0x21u, 0x43u, - 0x01u, 0x60u, 0xf8u, 0xbdu, 0xd0u, 0x03u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x06u, 0x00u, 0x0cu, 0x00u, 0x1du, 0x00u, + 0x01u, 0x60u, 0xf8u, 0xbdu, 0xe0u, 0x03u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x06u, 0x00u, 0x0cu, 0x00u, 0x1du, 0x00u, 0x30u, 0x00u, 0xffu, 0xf7u, 0x3du, 0xffu, 0x07u, 0x28u, 0xfau, 0xd8u, 0x02u, 0x21u, 0x08u, 0x4bu, 0x05u, 0x9au, 0x1bu, 0x68u, 0x24u, 0x06u, 0xd8u, 0x68u, 0x04u, 0x9bu, 0x30u, 0x18u, 0x99u, 0x40u, 0x01u, 0x23u, 0xabu, 0x40u, 0x19u, 0x43u, 0x03u, 0x23u, 0x93u, 0x40u, 0x19u, 0x43u, 0x21u, 0x43u, 0x01u, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u, - 0xd0u, 0x03u, 0x00u, 0x08u, 0x13u, 0xb5u, 0x04u, 0x00u, 0x08u, 0x00u, 0x11u, 0x00u, 0x00u, 0x2bu, 0x13u, 0xd0u, + 0xe0u, 0x03u, 0x00u, 0x08u, 0x13u, 0xb5u, 0x04u, 0x00u, 0x08u, 0x00u, 0x11u, 0x00u, 0x00u, 0x2bu, 0x13u, 0xd0u, 0x02u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x56u, 0xffu, 0x08u, 0x23u, 0x20u, 0x00u, 0x00u, 0x93u, 0x00u, 0x22u, 0x04u, 0x3bu, 0x50u, 0x21u, 0xffu, 0xf7u, 0xb6u, 0xffu, 0x04u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xe4u, 0x18u, - 0x10u, 0x23u, 0x22u, 0x68u, 0x1au, 0x42u, 0xfcu, 0xd1u, 0x13u, 0xbdu, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, + 0x10u, 0x23u, 0x22u, 0x68u, 0x1au, 0x42u, 0xfcu, 0xd1u, 0x13u, 0xbdu, 0xc0u, 0x46u, 0xe0u, 0x03u, 0x00u, 0x08u, 0x13u, 0xb5u, 0x04u, 0x00u, 0x10u, 0x00u, 0x1au, 0x1eu, 0x13u, 0xd0u, 0x03u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x39u, 0xffu, 0x0cu, 0x23u, 0x20u, 0x00u, 0x00u, 0x93u, 0x00u, 0x22u, 0x04u, 0x3bu, 0x51u, 0x21u, 0xffu, 0xf7u, 0x99u, 0xffu, 0x04u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xe4u, 0x18u, 0x10u, 0x23u, 0x22u, 0x68u, 0x1au, 0x42u, - 0xfcu, 0xd1u, 0x13u, 0xbdu, 0xd0u, 0x03u, 0x00u, 0x08u, 0x13u, 0xb5u, 0x04u, 0x00u, 0x01u, 0x20u, 0x00u, 0x2bu, + 0xfcu, 0xd1u, 0x13u, 0xbdu, 0xe0u, 0x03u, 0x00u, 0x08u, 0x13u, 0xb5u, 0x04u, 0x00u, 0x01u, 0x20u, 0x00u, 0x2bu, 0x15u, 0xd0u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x1eu, 0xffu, 0x08u, 0x23u, 0x00u, 0x22u, 0x00u, 0x93u, 0x52u, 0x21u, 0x04u, 0x3bu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x7eu, 0xffu, 0x10u, 0x22u, 0x05u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xe3u, 0x18u, 0x19u, 0x68u, 0x11u, 0x42u, 0xfcu, 0xd1u, 0xc0u, 0x23u, 0x5bu, 0x00u, 0xe0u, 0x58u, 0x16u, 0xbdu, - 0xd0u, 0x03u, 0x00u, 0x08u, 0x13u, 0xb5u, 0x04u, 0x00u, 0x08u, 0x00u, 0x11u, 0x00u, 0x1au, 0x00u, 0x04u, 0xabu, + 0xe0u, 0x03u, 0x00u, 0x08u, 0x13u, 0xb5u, 0x04u, 0x00u, 0x08u, 0x00u, 0x11u, 0x00u, 0x1au, 0x00u, 0x04u, 0xabu, 0x1bu, 0x88u, 0x00u, 0x2bu, 0x15u, 0xd0u, 0x00u, 0x90u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x19u, 0xffu, 0x0cu, 0x23u, 0x01u, 0x93u, 0x04u, 0x3bu, 0x00u, 0x93u, 0x20u, 0x00u, 0x04u, 0x3bu, 0x00u, 0x22u, 0x53u, 0x21u, 0xffu, 0xf7u, 0x73u, 0xffu, 0x04u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xe4u, 0x18u, 0x10u, 0x23u, 0x22u, 0x68u, 0x1au, 0x42u, - 0xfcu, 0xd1u, 0x13u, 0xbdu, 0xd0u, 0x03u, 0x00u, 0x08u, 0x03u, 0x4bu, 0x1bu, 0x68u, 0x9bu, 0x68u, 0xc0u, 0x18u, - 0x0fu, 0x23u, 0x00u, 0x68u, 0x18u, 0x40u, 0x70u, 0x47u, 0xd0u, 0x03u, 0x00u, 0x08u, 0x03u, 0x4bu, 0x1bu, 0x68u, - 0x1bu, 0x68u, 0xc0u, 0x18u, 0x03u, 0x68u, 0x00u, 0x2bu, 0xfcu, 0xd1u, 0x70u, 0x47u, 0xd0u, 0x03u, 0x00u, 0x08u, + 0xfcu, 0xd1u, 0x13u, 0xbdu, 0xe0u, 0x03u, 0x00u, 0x08u, 0x03u, 0x4bu, 0x1bu, 0x68u, 0x9bu, 0x68u, 0xc0u, 0x18u, + 0x0fu, 0x23u, 0x00u, 0x68u, 0x18u, 0x40u, 0x70u, 0x47u, 0xe0u, 0x03u, 0x00u, 0x08u, 0x03u, 0x4bu, 0x1bu, 0x68u, + 0x1bu, 0x68u, 0xc0u, 0x18u, 0x03u, 0x68u, 0x00u, 0x2bu, 0xfcu, 0xd1u, 0x70u, 0x47u, 0xe0u, 0x03u, 0x00u, 0x08u, 0xf8u, 0xb5u, 0x04u, 0x00u, 0x0du, 0x00u, 0x17u, 0x00u, 0x1eu, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xe4u, 0xffu, 0x04u, 0x28u, 0xfau, 0xd8u, 0x08u, 0x2du, 0x04u, 0xd0u, 0x0cu, 0x4au, 0xa3u, 0x58u, 0x00u, 0x2bu, 0xfcu, 0xdbu, 0x04u, 0xe0u, 0x86u, 0x22u, 0x52u, 0x01u, 0xa3u, 0x58u, 0x00u, 0x2bu, 0xfcu, 0xdbu, 0xe2u, 0x21u, 0x08u, 0x4bu, 0xc9u, 0x05u, 0x1bu, 0x68u, 0x0du, 0x43u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x15u, 0x60u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x17u, 0x60u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0x26u, 0x60u, 0xf8u, 0xbdu, 0xc0u, 0x46u, 0xd0u, 0x10u, 0x00u, 0x00u, - 0xd0u, 0x03u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x04u, 0x00u, 0x0eu, 0x00u, 0x15u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, + 0xe0u, 0x03u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x04u, 0x00u, 0x0eu, 0x00u, 0x15u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xbbu, 0xffu, 0x04u, 0x28u, 0xfau, 0xd8u, 0x06u, 0x4bu, 0x06u, 0x49u, 0x1bu, 0x68u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x11u, 0x60u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x16u, 0x60u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0x25u, 0x60u, 0x70u, 0xbdu, - 0xd0u, 0x03u, 0x00u, 0x08u, 0x0cu, 0x00u, 0x00u, 0x70u, 0x70u, 0xb5u, 0x05u, 0x00u, 0x0cu, 0x00u, 0x1eu, 0x1eu, + 0xe0u, 0x03u, 0x00u, 0x08u, 0x0cu, 0x00u, 0x00u, 0x70u, 0x70u, 0xb5u, 0x05u, 0x00u, 0x0cu, 0x00u, 0x1eu, 0x1eu, 0x22u, 0xd0u, 0x08u, 0x21u, 0xffu, 0xf7u, 0xb4u, 0xffu, 0x21u, 0x00u, 0x32u, 0x00u, 0x28u, 0x00u, 0xffu, 0xf7u, 0xd9u, 0xffu, 0x34u, 0x00u, 0x0fu, 0x2cu, 0x18u, 0xd8u, 0x10u, 0x24u, 0x33u, 0x09u, 0x64u, 0x42u, 0x5cu, 0x43u, 0xa4u, 0x19u, 0xa4u, 0xb2u, 0x00u, 0x2cu, 0x0cu, 0xd0u, 0x28u, 0x00u, 0xffu, 0xf7u, 0x8du, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x0du, 0x4bu, 0x0du, 0x4au, 0x1bu, 0x68u, 0x24u, 0x04u, 0xdbu, 0x68u, 0x14u, 0x43u, 0xebu, 0x18u, 0x1cu, 0x60u, 0x28u, 0x00u, 0xffu, 0xf7u, 0x8au, 0xffu, 0x70u, 0xbdu, 0x28u, 0x00u, 0xffu, 0xf7u, 0x7cu, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x04u, 0x4bu, 0x06u, 0x4au, 0x1bu, 0x68u, 0x10u, 0x3cu, 0xdbu, 0x68u, 0xa4u, 0xb2u, - 0xebu, 0x18u, 0x1au, 0x60u, 0xd6u, 0xe7u, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, 0x08u, 0xc0u, 0x00u, 0x40u, + 0xebu, 0x18u, 0x1au, 0x60u, 0xd6u, 0xe7u, 0xc0u, 0x46u, 0xe0u, 0x03u, 0x00u, 0x08u, 0x08u, 0xc0u, 0x00u, 0x40u, 0x08u, 0xc0u, 0x10u, 0x40u, 0xf8u, 0xb5u, 0x05u, 0x00u, 0x16u, 0x00u, 0x1fu, 0x1eu, 0x1eu, 0xd0u, 0x1au, 0x00u, 0xffu, 0xf7u, 0xa0u, 0xffu, 0x3cu, 0x00u, 0x0fu, 0x2cu, 0x19u, 0xd8u, 0x10u, 0x24u, 0x3bu, 0x09u, 0x64u, 0x42u, 0x5cu, 0x43u, 0xe4u, 0x19u, 0xa4u, 0xb2u, 0x00u, 0x2cu, 0x0du, 0xd0u, 0x28u, 0x00u, 0xffu, 0xf7u, 0x54u, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x0du, 0x4bu, 0x0eu, 0x4au, 0x1bu, 0x68u, 0x32u, 0x43u, 0xdbu, 0x68u, 0x24u, 0x04u, 0xebu, 0x18u, 0x14u, 0x43u, 0x1cu, 0x60u, 0x28u, 0x00u, 0xffu, 0xf7u, 0x50u, 0xffu, 0xf8u, 0xbdu, 0x28u, 0x00u, 0xffu, 0xf7u, 0x42u, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x04u, 0x4bu, 0x06u, 0x4au, 0x1bu, 0x68u, 0x32u, 0x43u, - 0xdbu, 0x68u, 0x10u, 0x3cu, 0xebu, 0x18u, 0x1au, 0x60u, 0xa4u, 0xb2u, 0xd4u, 0xe7u, 0xd0u, 0x03u, 0x00u, 0x08u, + 0xdbu, 0x68u, 0x10u, 0x3cu, 0xebu, 0x18u, 0x1au, 0x60u, 0xa4u, 0xb2u, 0xd4u, 0xe7u, 0xe0u, 0x03u, 0x00u, 0x08u, 0x00u, 0xc0u, 0x00u, 0x42u, 0x00u, 0xc0u, 0x10u, 0x42u, 0x70u, 0xb5u, 0x05u, 0x00u, 0x14u, 0x00u, 0x1eu, 0x00u, 0x01u, 0x20u, 0x00u, 0x2bu, 0x2du, 0xd0u, 0x8cu, 0x23u, 0x00u, 0x22u, 0x5bu, 0x01u, 0xeau, 0x50u, 0x28u, 0x00u, 0x0au, 0x00u, 0x33u, 0x00u, 0x08u, 0x21u, 0xffu, 0xf7u, 0x33u, 0xffu, 0x22u, 0x00u, 0x33u, 0x00u, 0x09u, 0x21u, @@ -1064,7 +1064,7 @@ const uint8_t cy_m0p_image[] = { 0x14u, 0x43u, 0xebu, 0x18u, 0x1cu, 0x60u, 0x28u, 0x00u, 0xffu, 0xf7u, 0x08u, 0xffu, 0x8cu, 0x23u, 0x5bu, 0x01u, 0xe8u, 0x58u, 0x70u, 0xbdu, 0x28u, 0x00u, 0xffu, 0xf7u, 0xf7u, 0xfeu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x04u, 0x4bu, 0x05u, 0x4au, 0x1bu, 0x68u, 0x10u, 0x3cu, 0xdbu, 0x68u, 0xa4u, 0xb2u, 0xebu, 0x18u, 0x1au, 0x60u, 0xd3u, 0xe7u, - 0xd0u, 0x03u, 0x00u, 0x08u, 0x98u, 0x00u, 0x00u, 0x43u, 0x98u, 0x00u, 0x10u, 0x43u, 0xf8u, 0xb5u, 0x1fu, 0x00u, + 0xe0u, 0x03u, 0x00u, 0x08u, 0x98u, 0x00u, 0x00u, 0x43u, 0x98u, 0x00u, 0x10u, 0x43u, 0xf8u, 0xb5u, 0x1fu, 0x00u, 0x06u, 0xabu, 0x1eu, 0x88u, 0x05u, 0x00u, 0x0cu, 0x00u, 0x00u, 0x2eu, 0x29u, 0xd0u, 0x33u, 0x00u, 0x08u, 0x21u, 0xffu, 0xf7u, 0xeeu, 0xfeu, 0x33u, 0x00u, 0x3au, 0x00u, 0x09u, 0x21u, 0x28u, 0x00u, 0xffu, 0xf7u, 0xe8u, 0xfeu, 0x21u, 0x00u, 0x32u, 0x00u, 0x28u, 0x00u, 0xffu, 0xf7u, 0x0du, 0xffu, 0x34u, 0x00u, 0x0fu, 0x2cu, 0x18u, 0xd8u, @@ -1073,37 +1073,37 @@ const uint8_t cy_m0p_image[] = { 0x24u, 0x04u, 0xdbu, 0x68u, 0x14u, 0x43u, 0xebu, 0x18u, 0x1cu, 0x60u, 0x28u, 0x00u, 0xffu, 0xf7u, 0xbeu, 0xfeu, 0xf8u, 0xbdu, 0x28u, 0x00u, 0xffu, 0xf7u, 0xb0u, 0xfeu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x04u, 0x4bu, 0x06u, 0x4au, 0x1bu, 0x68u, 0x10u, 0x3cu, 0xdbu, 0x68u, 0xa4u, 0xb2u, 0xebu, 0x18u, 0x1au, 0x60u, 0xd6u, 0xe7u, 0xc0u, 0x46u, - 0xd0u, 0x03u, 0x00u, 0x08u, 0x98u, 0xc0u, 0x00u, 0x41u, 0x98u, 0xc0u, 0x10u, 0x41u, 0x10u, 0xb5u, 0x80u, 0x24u, + 0xe0u, 0x03u, 0x00u, 0x08u, 0x98u, 0xc0u, 0x00u, 0x41u, 0x98u, 0xc0u, 0x10u, 0x41u, 0x10u, 0xb5u, 0x80u, 0x24u, 0xa4u, 0x00u, 0x01u, 0x51u, 0x81u, 0x21u, 0x52u, 0x00u, 0x52u, 0x08u, 0x89u, 0x00u, 0x42u, 0x50u, 0x82u, 0x22u, 0xdbu, 0x00u, 0xdbu, 0x08u, 0x92u, 0x00u, 0x83u, 0x50u, 0x00u, 0x20u, 0x10u, 0xbdu, 0x70u, 0xb5u, 0x04u, 0x00u, 0x15u, 0x00u, 0xffu, 0xf7u, 0x3fu, 0xfdu, 0x00u, 0x22u, 0x5cu, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xaau, 0xfdu, 0x20u, 0x21u, 0x06u, 0x4bu, 0x1au, 0x68u, 0x13u, 0x68u, 0xe3u, 0x18u, 0x18u, 0x68u, 0x08u, 0x40u, 0xfcu, 0xd1u, - 0x93u, 0x69u, 0xe4u, 0x18u, 0x23u, 0x68u, 0x2bu, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, + 0x93u, 0x69u, 0xe4u, 0x18u, 0x23u, 0x68u, 0x2bu, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u, 0xe0u, 0x03u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x80u, 0x24u, 0xa4u, 0x00u, 0x01u, 0x51u, 0x81u, 0x21u, 0x52u, 0x00u, 0x52u, 0x08u, 0x89u, 0x00u, 0x42u, 0x50u, 0x82u, 0x22u, 0xdbu, 0x00u, 0xdbu, 0x08u, 0x92u, 0x00u, 0x83u, 0x50u, 0x00u, 0x20u, 0x10u, 0xbdu, 0x83u, 0x23u, 0x9bu, 0x00u, 0x10u, 0xb5u, 0xc1u, 0x50u, 0x01u, 0x21u, 0x04u, 0x33u, 0xc1u, 0x50u, 0x06u, 0x4bu, 0x19u, 0x68u, 0x0bu, 0x68u, 0xc3u, 0x18u, 0x1cu, 0x68u, 0x00u, 0x2cu, 0xfcu, 0xdbu, 0x8bu, 0x69u, 0xc0u, 0x18u, - 0x03u, 0x68u, 0x00u, 0x20u, 0x13u, 0x60u, 0x10u, 0xbdu, 0xd0u, 0x03u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x06u, 0x4cu, + 0x03u, 0x68u, 0x00u, 0x20u, 0x13u, 0x60u, 0x10u, 0xbdu, 0xe0u, 0x03u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x06u, 0x4cu, 0x24u, 0x68u, 0x29u, 0x34u, 0x24u, 0x78u, 0x1fu, 0x2cu, 0x02u, 0xd8u, 0xffu, 0xf7u, 0x05u, 0xfeu, 0x10u, 0xbdu, - 0xffu, 0xf7u, 0x12u, 0xffu, 0xfbu, 0xe7u, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x09u, 0x4bu, 0x1bu, 0x68u, + 0xffu, 0xf7u, 0x12u, 0xffu, 0xfbu, 0xe7u, 0xc0u, 0x46u, 0xecu, 0x05u, 0x00u, 0x08u, 0x09u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xc0u, 0x18u, 0x08u, 0x4bu, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x04u, 0xd8u, 0x80u, 0x23u, 0x02u, 0x68u, 0x1au, 0x42u, 0xfcu, 0xd1u, 0x70u, 0x47u, 0x03u, 0x68u, 0x00u, 0x2bu, 0xfcu, 0xd1u, - 0xfau, 0xe7u, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x13u, 0x00u, + 0xfau, 0xe7u, 0xc0u, 0x46u, 0xe0u, 0x03u, 0x00u, 0x08u, 0xecu, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x13u, 0x00u, 0x06u, 0x4au, 0x14u, 0x68u, 0x29u, 0x34u, 0x22u, 0x78u, 0x1fu, 0x2au, 0x03u, 0xd8u, 0x00u, 0x22u, 0xffu, 0xf7u, - 0xbfu, 0xfdu, 0x10u, 0xbdu, 0x00u, 0x22u, 0xffu, 0xf7u, 0xadu, 0xfeu, 0xfau, 0xe7u, 0xdcu, 0x05u, 0x00u, 0x08u, + 0xbfu, 0xfdu, 0x10u, 0xbdu, 0x00u, 0x22u, 0xffu, 0xf7u, 0xadu, 0xfeu, 0xfau, 0xe7u, 0xecu, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x0bu, 0x03u, 0x34u, 0x22u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xd6u, 0xfau, 0x10u, 0xbdu, 0x00u, 0x00u, 0x10u, 0xb5u, 0x0au, 0x4bu, 0x09u, 0x03u, 0x1bu, 0x68u, 0x12u, 0x01u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x06u, 0xd8u, 0x13u, 0x00u, 0x25u, 0x22u, 0x0bu, 0x43u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xc5u, 0xfau, 0x10u, 0xbdu, - 0x0fu, 0x23u, 0x13u, 0x43u, 0x0bu, 0x43u, 0x24u, 0x22u, 0xf6u, 0xe7u, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, + 0x0fu, 0x23u, 0x13u, 0x43u, 0x0bu, 0x43u, 0x24u, 0x22u, 0xf6u, 0xe7u, 0xc0u, 0x46u, 0xecu, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x09u, 0x4bu, 0x09u, 0x03u, 0x1bu, 0x68u, 0x12u, 0x01u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x06u, 0xd8u, 0x13u, 0x00u, 0x0bu, 0x43u, 0x21u, 0x22u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xadu, 0xfau, 0x10u, 0xbdu, - 0x0fu, 0x23u, 0x13u, 0x43u, 0xf6u, 0xe7u, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x0bu, 0x00u, + 0x0fu, 0x23u, 0x13u, 0x43u, 0xf6u, 0xe7u, 0xc0u, 0x46u, 0xecu, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x0bu, 0x00u, 0x13u, 0x22u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xa0u, 0xfau, 0x10u, 0xbdu, 0x00u, 0x00u, 0x10u, 0xb5u, 0x13u, 0x00u, 0x07u, 0x4au, 0x12u, 0x68u, 0x29u, 0x32u, 0x14u, 0x78u, 0x0cu, 0x22u, 0x1fu, 0x2cu, 0x00u, 0xd9u, 0x04u, 0x32u, 0x91u, 0x40u, 0x01u, 0x3bu, 0x0bu, 0x43u, 0x12u, 0x22u, 0x00u, 0x21u, 0xffu, 0xf7u, 0x8du, 0xfau, 0x10u, 0xbdu, - 0xdcu, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x1fu, 0x24u, 0x08u, 0x4bu, 0x89u, 0x06u, 0x1bu, 0x68u, 0x29u, 0x33u, + 0xecu, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x1fu, 0x24u, 0x08u, 0x4bu, 0x89u, 0x06u, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x9cu, 0x42u, 0xa4u, 0x41u, 0x13u, 0x00u, 0x64u, 0x42u, 0x0cu, 0x34u, 0xa3u, 0x40u, 0x80u, 0x22u, - 0x0bu, 0x43u, 0x00u, 0x21u, 0xffu, 0xf7u, 0x78u, 0xfau, 0x10u, 0xbdu, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, + 0x0bu, 0x43u, 0x00u, 0x21u, 0xffu, 0xf7u, 0x78u, 0xfau, 0x10u, 0xbdu, 0xc0u, 0x46u, 0xecu, 0x05u, 0x00u, 0x08u, 0xf7u, 0xb5u, 0x04u, 0x00u, 0x1du, 0x00u, 0x5eu, 0x1cu, 0x01u, 0x92u, 0x0fu, 0x00u, 0x32u, 0x00u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xccu, 0xffu, 0x32u, 0x00u, 0x01u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xc7u, 0xffu, 0x32u, 0x00u, 0x02u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xc2u, 0xffu, 0x2au, 0x00u, 0x03u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, @@ -1116,7 +1116,7 @@ const uint8_t cy_m0p_image[] = { 0xffu, 0xf7u, 0x2au, 0xfau, 0x0du, 0x4bu, 0x03u, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x24u, 0xfau, 0x33u, 0x00u, 0x3au, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x1eu, 0xfau, 0x00u, 0x22u, 0x20u, 0x00u, 0x11u, 0x00u, 0xffu, 0xf7u, 0x5du, 0xffu, 0x02u, 0x22u, 0x20u, 0x00u, 0x11u, 0x00u, 0xffu, 0xf7u, 0x40u, 0xffu, - 0x01u, 0x3du, 0xd9u, 0xe7u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x02u, 0x00u, 0x30u, 0x00u, 0x01u, 0x00u, 0x30u, 0x00u, + 0x01u, 0x3du, 0xd9u, 0xe7u, 0xecu, 0x05u, 0x00u, 0x08u, 0x02u, 0x00u, 0x30u, 0x00u, 0x01u, 0x00u, 0x30u, 0x00u, 0xf7u, 0xb5u, 0x04u, 0x00u, 0x08u, 0x9eu, 0x00u, 0x91u, 0x15u, 0x00u, 0x01u, 0x21u, 0x72u, 0x1cu, 0x77u, 0x00u, 0x01u, 0x93u, 0xffu, 0xf7u, 0x63u, 0xffu, 0x3au, 0x00u, 0x02u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x5eu, 0xffu, 0x3au, 0x00u, 0x03u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x59u, 0xffu, 0x32u, 0x00u, 0x00u, 0x21u, 0x20u, 0x00u, @@ -1138,7 +1138,7 @@ const uint8_t cy_m0p_image[] = { 0x7bu, 0xf9u, 0x20u, 0x00u, 0x10u, 0x4bu, 0x03u, 0x22u, 0x00u, 0x21u, 0xffu, 0xf7u, 0x75u, 0xf9u, 0x00u, 0x9bu, 0x20u, 0x00u, 0x1au, 0x03u, 0x02u, 0x23u, 0x00u, 0x21u, 0x13u, 0x43u, 0x30u, 0x22u, 0xffu, 0xf7u, 0x6cu, 0xf9u, 0x0eu, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xc2u, 0xfeu, 0xf7u, 0xbdu, 0xc0u, 0x46u, 0x3au, 0x10u, 0x00u, 0x00u, - 0x18u, 0x20u, 0x00u, 0x00u, 0x23u, 0x20u, 0x00u, 0x00u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x20u, 0x20u, 0x00u, 0x00u, + 0x18u, 0x20u, 0x00u, 0x00u, 0x23u, 0x20u, 0x00u, 0x00u, 0xecu, 0x05u, 0x00u, 0x08u, 0x20u, 0x20u, 0x00u, 0x00u, 0x10u, 0x10u, 0x00u, 0x00u, 0x21u, 0x30u, 0x00u, 0x00u, 0x23u, 0x00u, 0x30u, 0x00u, 0x28u, 0x30u, 0x00u, 0x00u, 0xf7u, 0xb5u, 0x06u, 0x00u, 0x1cu, 0x00u, 0x09u, 0x9bu, 0x01u, 0x91u, 0x5fu, 0x00u, 0x15u, 0x00u, 0x02u, 0x21u, 0x3au, 0x00u, 0xffu, 0xf7u, 0xabu, 0xfeu, 0x3au, 0x00u, 0x03u, 0x21u, 0x30u, 0x00u, 0xffu, 0xf7u, 0xa6u, 0xfeu, @@ -1156,7 +1156,7 @@ const uint8_t cy_m0p_image[] = { 0xebu, 0xf8u, 0x01u, 0x9bu, 0x30u, 0x00u, 0x1cu, 0x03u, 0x0du, 0x4bu, 0x30u, 0x22u, 0x23u, 0x43u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xe2u, 0xf8u, 0xc0u, 0x23u, 0x9bu, 0x03u, 0x30u, 0x00u, 0x23u, 0x43u, 0x30u, 0x22u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xdau, 0xf8u, 0x30u, 0x00u, 0x03u, 0x21u, 0xffu, 0xf7u, 0x30u, 0xfeu, 0xf7u, 0xbdu, 0xc0u, 0x46u, - 0xdcu, 0x05u, 0x00u, 0x08u, 0x20u, 0x30u, 0x00u, 0x00u, 0x30u, 0x20u, 0x00u, 0x00u, 0x10u, 0x00u, 0x40u, 0x00u, + 0xecu, 0x05u, 0x00u, 0x08u, 0x20u, 0x30u, 0x00u, 0x00u, 0x30u, 0x20u, 0x00u, 0x00u, 0x10u, 0x00u, 0x40u, 0x00u, 0x01u, 0x00u, 0x40u, 0x00u, 0xf8u, 0xb5u, 0x1du, 0x00u, 0x00u, 0x23u, 0x16u, 0x00u, 0x0fu, 0x00u, 0x10u, 0x22u, 0x19u, 0x00u, 0x04u, 0x00u, 0xffu, 0xf7u, 0xc0u, 0xf8u, 0xe0u, 0x23u, 0x00u, 0x22u, 0x1bu, 0x02u, 0x11u, 0x00u, 0x3bu, 0x43u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xb8u, 0xf8u, 0x90u, 0x23u, 0x00u, 0x22u, 0x1bu, 0x02u, 0x33u, 0x43u, @@ -1179,8 +1179,8 @@ const uint8_t cy_m0p_image[] = { 0x20u, 0x00u, 0x11u, 0x00u, 0xffu, 0xf7u, 0x5cu, 0xfdu, 0x33u, 0x68u, 0x2cu, 0x22u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x00u, 0xd9u, 0x04u, 0x3au, 0x0eu, 0x4bu, 0xa8u, 0xe7u, 0x0eu, 0x4bu, 0x25u, 0x22u, 0xeau, 0xe7u, 0xe0u, 0x21u, 0x20u, 0x00u, 0x89u, 0x01u, 0xffu, 0xf7u, 0x79u, 0xfdu, 0x00u, 0x23u, 0x11u, 0x22u, 0x19u, 0x00u, - 0x20u, 0x00u, 0xffu, 0xf7u, 0x19u, 0xf8u, 0xf8u, 0xbdu, 0xdcu, 0x05u, 0x00u, 0x08u, 0x0au, 0xb0u, 0x00u, 0x00u, - 0x09u, 0xc0u, 0x00u, 0x00u, 0xd0u, 0x03u, 0x00u, 0x08u, 0xdcu, 0xd0u, 0x00u, 0x00u, 0xd0u, 0xd0u, 0x00u, 0x00u, + 0x20u, 0x00u, 0xffu, 0xf7u, 0x19u, 0xf8u, 0xf8u, 0xbdu, 0xecu, 0x05u, 0x00u, 0x08u, 0x0au, 0xb0u, 0x00u, 0x00u, + 0x09u, 0xc0u, 0x00u, 0x00u, 0xe0u, 0x03u, 0x00u, 0x08u, 0xdcu, 0xd0u, 0x00u, 0x00u, 0xd0u, 0xd0u, 0x00u, 0x00u, 0x0au, 0xe0u, 0x00u, 0x00u, 0xdfu, 0xd0u, 0x00u, 0x00u, 0xf0u, 0xb5u, 0x85u, 0xb0u, 0x06u, 0x00u, 0x0fu, 0x00u, 0x02u, 0x93u, 0x0au, 0x9du, 0x0bu, 0x98u, 0x06u, 0x2au, 0x37u, 0xd8u, 0x21u, 0x4bu, 0x91u, 0x00u, 0xc9u, 0x58u, 0x20u, 0x4cu, 0x21u, 0x4bu, 0xa4u, 0x5cu, 0x9bu, 0x5cu, 0x01u, 0x22u, 0x3au, 0x70u, 0x1au, 0x19u, 0x0bu, 0x32u, @@ -1191,7 +1191,7 @@ const uint8_t cy_m0p_image[] = { 0x00u, 0x28u, 0x12u, 0xd1u, 0x00u, 0x9au, 0xa3u, 0xb2u, 0xaau, 0x18u, 0x02u, 0x99u, 0x30u, 0x00u, 0xffu, 0xf7u, 0xb5u, 0xfcu, 0x00u, 0x28u, 0x09u, 0xd1u, 0x38u, 0x70u, 0x07u, 0xe0u, 0x00u, 0x24u, 0x23u, 0x00u, 0x21u, 0x00u, 0xcau, 0xe7u, 0x01u, 0x30u, 0x42u, 0x78u, 0xffu, 0x2au, 0xe0u, 0xd0u, 0x00u, 0x20u, 0x05u, 0xb0u, 0xf0u, 0xbdu, - 0x2cu, 0x79u, 0x00u, 0x10u, 0x4fu, 0x79u, 0x00u, 0x10u, 0x48u, 0x79u, 0x00u, 0x10u, 0xf0u, 0xb5u, 0x8bu, 0xb0u, + 0x34u, 0x79u, 0x00u, 0x10u, 0x57u, 0x79u, 0x00u, 0x10u, 0x50u, 0x79u, 0x00u, 0x10u, 0xf0u, 0xb5u, 0x8bu, 0xb0u, 0x09u, 0x93u, 0x8bu, 0x68u, 0x04u, 0x00u, 0x05u, 0x93u, 0xcbu, 0x68u, 0x08u, 0x92u, 0x06u, 0x93u, 0x0bu, 0x68u, 0x4fu, 0x68u, 0x07u, 0x93u, 0x0bu, 0x69u, 0x8du, 0x69u, 0x03u, 0x93u, 0x4bu, 0x69u, 0x04u, 0x93u, 0xb3u, 0x4bu, 0x1bu, 0x68u, 0x1eu, 0x1eu, 0x02u, 0xd0u, 0x9bu, 0x6bu, 0xc3u, 0x18u, 0x1eu, 0x68u, 0x20u, 0x00u, 0xffu, 0xf7u, @@ -1238,10 +1238,10 @@ const uint8_t cy_m0p_image[] = { 0xffu, 0xf7u, 0x4eu, 0xfcu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x51u, 0xfbu, 0x0du, 0x23u, 0x00u, 0x97u, 0x1au, 0x00u, 0x19u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x44u, 0xfcu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x47u, 0xfbu, 0x01u, 0x3du, 0x93u, 0xe7u, 0x0du, 0x23u, 0x05u, 0x22u, 0x19u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x39u, 0xfcu, 0x20u, 0x00u, - 0xffu, 0xf7u, 0x3cu, 0xfbu, 0x00u, 0x97u, 0x05u, 0x23u, 0xe9u, 0xe7u, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, + 0xffu, 0xf7u, 0x3cu, 0xfbu, 0x00u, 0x97u, 0x05u, 0x23u, 0xe9u, 0xe7u, 0xc0u, 0x46u, 0xe0u, 0x03u, 0x00u, 0x08u, 0x06u, 0x60u, 0x00u, 0x00u, 0x05u, 0x50u, 0x00u, 0x00u, 0x07u, 0x70u, 0x00u, 0x00u, 0x08u, 0x80u, 0x00u, 0x00u, 0x09u, 0xa0u, 0x00u, 0x00u, 0x0au, 0xc0u, 0x00u, 0x00u, 0x0bu, 0x50u, 0x00u, 0x00u, 0x07u, 0xb0u, 0x00u, 0x00u, - 0xdcu, 0x05u, 0x00u, 0x08u, 0xb9u, 0xe0u, 0x00u, 0x00u, 0xbeu, 0xb0u, 0x00u, 0x00u, 0xf0u, 0xb5u, 0x0bu, 0x69u, + 0xecu, 0x05u, 0x00u, 0x08u, 0xb9u, 0xe0u, 0x00u, 0x00u, 0xbeu, 0xb0u, 0x00u, 0x00u, 0xf0u, 0xb5u, 0x0bu, 0x69u, 0x87u, 0xb0u, 0x03u, 0x93u, 0x4bu, 0x69u, 0x04u, 0x00u, 0x04u, 0x93u, 0x8bu, 0x69u, 0x0fu, 0x68u, 0x05u, 0x93u, 0x34u, 0x4bu, 0x4du, 0x68u, 0x1bu, 0x68u, 0x1eu, 0x1eu, 0x02u, 0xd0u, 0x9bu, 0x6bu, 0xc3u, 0x18u, 0x1eu, 0x68u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0x3du, 0xffu, 0x31u, 0x00u, 0x82u, 0xb2u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x1eu, 0xfbu, @@ -1256,13 +1256,13 @@ const uint8_t cy_m0p_image[] = { 0x0eu, 0x22u, 0x00u, 0xf0u, 0xcdu, 0xfdu, 0x2bu, 0x00u, 0x32u, 0x00u, 0x20u, 0x00u, 0x0cu, 0x21u, 0xffu, 0xf7u, 0xf9u, 0xfcu, 0x2bu, 0x00u, 0x0cu, 0x22u, 0x04u, 0x99u, 0x20u, 0x00u, 0x00u, 0xf0u, 0xc1u, 0xfdu, 0xf0u, 0x21u, 0x20u, 0x00u, 0xc9u, 0x01u, 0xffu, 0xf7u, 0x12u, 0xfbu, 0x20u, 0x00u, 0xffu, 0xf7u, 0xafu, 0xfau, 0x00u, 0x20u, - 0x07u, 0xb0u, 0xf0u, 0xbdu, 0xd0u, 0x03u, 0x00u, 0x08u, 0x0bu, 0x00u, 0x13u, 0xb5u, 0x11u, 0x00u, 0x07u, 0x22u, + 0x07u, 0xb0u, 0xf0u, 0xbdu, 0xe0u, 0x03u, 0x00u, 0x08u, 0x0bu, 0x00u, 0x13u, 0xb5u, 0x11u, 0x00u, 0x07u, 0x22u, 0x04u, 0x00u, 0x58u, 0x68u, 0x02u, 0x40u, 0xc0u, 0x20u, 0x80u, 0x00u, 0x22u, 0x50u, 0x1au, 0x69u, 0x20u, 0x00u, 0x00u, 0x92u, 0x9bu, 0x69u, 0xfeu, 0xf7u, 0xdcu, 0xffu, 0x0cu, 0x23u, 0x01u, 0x93u, 0x04u, 0x3bu, 0x00u, 0x93u, 0x20u, 0x00u, 0x04u, 0x3bu, 0x00u, 0x22u, 0x4cu, 0x21u, 0xffu, 0xf7u, 0x36u, 0xf8u, 0x04u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xe4u, 0x18u, 0x04u, 0x23u, 0x22u, 0x68u, 0x1au, 0x42u, 0xfcu, 0xd1u, 0x13u, 0xbdu, 0xc0u, 0x46u, - 0xd0u, 0x03u, 0x00u, 0x08u, 0x00u, 0xb5u, 0x06u, 0x2au, 0x00u, 0xd9u, 0x80u, 0xe0u, 0x10u, 0x00u, 0x8bu, 0x60u, - 0x1au, 0x00u, 0x02u, 0xf0u, 0x0du, 0xf8u, 0x04u, 0x16u, 0x29u, 0x3au, 0x4du, 0x6cu, 0x5cu, 0x00u, 0x54u, 0x33u, + 0xe0u, 0x03u, 0x00u, 0x08u, 0x00u, 0xb5u, 0x06u, 0x2au, 0x00u, 0xd9u, 0x80u, 0xe0u, 0x10u, 0x00u, 0x8bu, 0x60u, + 0x1au, 0x00u, 0x02u, 0xf0u, 0x11u, 0xf8u, 0x04u, 0x16u, 0x29u, 0x3au, 0x4du, 0x6cu, 0x5cu, 0x00u, 0x54u, 0x33u, 0x8bu, 0x61u, 0x3cu, 0x4bu, 0x00u, 0x20u, 0xcbu, 0x62u, 0x40u, 0x23u, 0xcbu, 0x60u, 0x2cu, 0x3bu, 0x4bu, 0x61u, 0x4bu, 0x62u, 0x2du, 0x33u, 0x40u, 0x32u, 0xffu, 0x33u, 0x0au, 0x61u, 0x08u, 0x60u, 0x48u, 0x60u, 0xcbu, 0x61u, 0x00u, 0xbdu, 0x60u, 0x33u, 0x8bu, 0x61u, 0x01u, 0x23u, 0x0bu, 0x60u, 0x4bu, 0x60u, 0x32u, 0x4bu, 0x40u, 0x32u, @@ -1278,8 +1278,8 @@ const uint8_t cy_m0p_image[] = { 0x80u, 0x23u, 0xcbu, 0x60u, 0x40u, 0x3bu, 0x4bu, 0x61u, 0x0au, 0x61u, 0x24u, 0x3bu, 0xdcu, 0xe7u, 0xc0u, 0x33u, 0x8bu, 0x61u, 0x05u, 0x23u, 0x0bu, 0x60u, 0x03u, 0x3bu, 0x4bu, 0x60u, 0x0cu, 0x4bu, 0x80u, 0x32u, 0xcbu, 0x62u, 0x80u, 0x23u, 0xcbu, 0x60u, 0x40u, 0x3bu, 0x4bu, 0x61u, 0x0au, 0x61u, 0x20u, 0x3bu, 0xccu, 0xe7u, 0x08u, 0x48u, - 0x96u, 0xe7u, 0xc0u, 0x46u, 0xd8u, 0x79u, 0x00u, 0x10u, 0xecu, 0x79u, 0x00u, 0x10u, 0x0cu, 0x7au, 0x00u, 0x10u, - 0x2cu, 0x7au, 0x00u, 0x10u, 0x6cu, 0x7au, 0x00u, 0x10u, 0xacu, 0x7au, 0x00u, 0x10u, 0xecu, 0x7au, 0x00u, 0x10u, + 0x96u, 0xe7u, 0xc0u, 0x46u, 0xe0u, 0x79u, 0x00u, 0x10u, 0xf4u, 0x79u, 0x00u, 0x10u, 0x14u, 0x7au, 0x00u, 0x10u, + 0x34u, 0x7au, 0x00u, 0x10u, 0x74u, 0x7au, 0x00u, 0x10u, 0xb4u, 0x7au, 0x00u, 0x10u, 0xf4u, 0x7au, 0x00u, 0x10u, 0x0bu, 0x00u, 0x32u, 0x00u, 0x10u, 0xb5u, 0x00u, 0x29u, 0x01u, 0xd1u, 0x07u, 0x48u, 0x10u, 0xbdu, 0x00u, 0x24u, 0x4bu, 0x69u, 0x8cu, 0x62u, 0x0cu, 0x62u, 0xa3u, 0x42u, 0xf7u, 0xd0u, 0xcau, 0x6au, 0x9bu, 0xb2u, 0x09u, 0x69u, 0xfeu, 0xf7u, 0xa0u, 0xffu, 0x20u, 0x00u, 0xf1u, 0xe7u, 0x0bu, 0x00u, 0x32u, 0x00u, 0xf7u, 0xb5u, 0x07u, 0x00u, @@ -1309,33 +1309,33 @@ const uint8_t cy_m0p_image[] = { 0x00u, 0x20u, 0x70u, 0xbdu, 0x00u, 0x48u, 0xfcu, 0xe7u, 0x0bu, 0x00u, 0x32u, 0x00u, 0xf0u, 0xb5u, 0x8fu, 0xb0u, 0x01u, 0x93u, 0x14u, 0xabu, 0x1fu, 0x78u, 0x19u, 0x4bu, 0x04u, 0x00u, 0x1bu, 0x68u, 0x00u, 0x91u, 0x16u, 0x00u, 0x1du, 0x1eu, 0x02u, 0xd0u, 0x9bu, 0x6bu, 0xc3u, 0x18u, 0x1du, 0x68u, 0x30u, 0x22u, 0x00u, 0x21u, 0x02u, 0xa8u, - 0x02u, 0xf0u, 0x7fu, 0xf8u, 0x2bu, 0x00u, 0x3au, 0x00u, 0x02u, 0xa9u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x7au, 0xfeu, + 0x02u, 0xf0u, 0x83u, 0xf8u, 0x2bu, 0x00u, 0x3au, 0x00u, 0x02u, 0xa9u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x7au, 0xfeu, 0x00u, 0x28u, 0x18u, 0xd1u, 0x02u, 0xa9u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x0cu, 0xffu, 0x00u, 0x28u, 0x12u, 0xd1u, 0x33u, 0x00u, 0x00u, 0x9au, 0x02u, 0xa9u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x18u, 0xffu, 0x00u, 0x28u, 0x0au, 0xd1u, 0x01u, 0x9au, 0x02u, 0xa9u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x4fu, 0xffu, 0x00u, 0x28u, 0x03u, 0xd1u, 0x02u, 0xa9u, - 0x20u, 0x00u, 0xffu, 0xf7u, 0xadu, 0xffu, 0x0fu, 0xb0u, 0xf0u, 0xbdu, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, + 0x20u, 0x00u, 0xffu, 0xf7u, 0xadu, 0xffu, 0x0fu, 0xb0u, 0xf0u, 0xbdu, 0xc0u, 0x46u, 0xe0u, 0x03u, 0x00u, 0x08u, 0x03u, 0x4bu, 0x1bu, 0x68u, 0x9bu, 0x68u, 0xc0u, 0x18u, 0x0fu, 0x23u, 0x00u, 0x68u, 0x18u, 0x40u, 0x70u, 0x47u, - 0xd0u, 0x03u, 0x00u, 0x08u, 0x03u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xc0u, 0x18u, 0x03u, 0x68u, 0x00u, 0x2bu, - 0xfcu, 0xd1u, 0x70u, 0x47u, 0xd0u, 0x03u, 0x00u, 0x08u, 0xf8u, 0xb5u, 0x04u, 0x00u, 0x0fu, 0x00u, 0x16u, 0x00u, + 0xe0u, 0x03u, 0x00u, 0x08u, 0x03u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xc0u, 0x18u, 0x03u, 0x68u, 0x00u, 0x2bu, + 0xfcu, 0xd1u, 0x70u, 0x47u, 0xe0u, 0x03u, 0x00u, 0x08u, 0xf8u, 0xb5u, 0x04u, 0x00u, 0x0fu, 0x00u, 0x16u, 0x00u, 0x1du, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xe4u, 0xffu, 0x04u, 0x28u, 0xfau, 0xd8u, 0xe0u, 0x21u, 0x07u, 0x4bu, 0xc9u, 0x05u, 0x1bu, 0x68u, 0x0fu, 0x43u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x17u, 0x60u, 0xdau, 0x68u, 0xa2u, 0x18u, - 0x16u, 0x60u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0x25u, 0x60u, 0xf8u, 0xbdu, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, + 0x16u, 0x60u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0x25u, 0x60u, 0xf8u, 0xbdu, 0xc0u, 0x46u, 0xe0u, 0x03u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x04u, 0x00u, 0x0du, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xcau, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x03u, 0x4bu, 0x2du, 0x06u, 0x1bu, 0x68u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0x25u, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u, - 0xd0u, 0x03u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xb9u, 0xffu, 0x06u, 0x28u, + 0xe0u, 0x03u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xb9u, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x04u, 0x4bu, 0x1bu, 0x68u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0xc8u, 0x23u, 0xdbu, 0x05u, 0x23u, 0x60u, - 0x10u, 0xbdu, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, + 0x10u, 0xbdu, 0xc0u, 0x46u, 0xe0u, 0x03u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa7u, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x04u, 0x4bu, 0x1bu, 0x68u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0xcau, 0x23u, - 0xdbu, 0x05u, 0x23u, 0x60u, 0x10u, 0xbdu, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x05u, 0x00u, + 0xdbu, 0x05u, 0x23u, 0x60u, 0x10u, 0xbdu, 0xc0u, 0x46u, 0xe0u, 0x03u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x05u, 0x00u, 0x0cu, 0x00u, 0x16u, 0x00u, 0x28u, 0x00u, 0xffu, 0xf7u, 0x93u, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x05u, 0x4bu, 0x24u, 0x02u, 0x1bu, 0x68u, 0xdbu, 0x68u, 0xedu, 0x18u, 0xccu, 0x23u, 0xdbu, 0x05u, 0x1eu, 0x43u, 0x34u, 0x43u, - 0x2cu, 0x60u, 0x70u, 0xbdu, 0xd0u, 0x03u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x05u, 0x00u, 0x0cu, 0x00u, 0x16u, 0x00u, + 0x2cu, 0x60u, 0x70u, 0xbdu, 0xe0u, 0x03u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x05u, 0x00u, 0x0cu, 0x00u, 0x16u, 0x00u, 0x28u, 0x00u, 0xffu, 0xf7u, 0x7du, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x05u, 0x4bu, 0x24u, 0x02u, 0x1bu, 0x68u, 0xdbu, 0x68u, 0xedu, 0x18u, 0xd0u, 0x23u, 0xdbu, 0x05u, 0x1eu, 0x43u, 0x34u, 0x43u, 0x2cu, 0x60u, 0x70u, 0xbdu, - 0xd0u, 0x03u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x04u, 0x00u, 0x0du, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x68u, 0xffu, + 0xe0u, 0x03u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x04u, 0x00u, 0x0du, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x68u, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0xceu, 0x21u, 0x04u, 0x4bu, 0xc9u, 0x05u, 0x1bu, 0x68u, 0x29u, 0x43u, 0xdbu, 0x68u, - 0xe4u, 0x18u, 0x21u, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, 0x00u, 0xb5u, 0x06u, 0x2au, - 0x68u, 0xd8u, 0x10u, 0x00u, 0x8bu, 0x60u, 0x01u, 0xf0u, 0xc3u, 0xfdu, 0x04u, 0x1fu, 0x12u, 0x3bu, 0x2fu, 0x49u, + 0xe4u, 0x18u, 0x21u, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u, 0xe0u, 0x03u, 0x00u, 0x08u, 0x00u, 0xb5u, 0x06u, 0x2au, + 0x68u, 0xd8u, 0x10u, 0x00u, 0x8bu, 0x60u, 0x01u, 0xf0u, 0xc7u, 0xfdu, 0x04u, 0x1fu, 0x12u, 0x3bu, 0x2fu, 0x49u, 0x57u, 0x00u, 0x40u, 0x33u, 0x0bu, 0x61u, 0x69u, 0x23u, 0x4bu, 0x60u, 0x2fu, 0x4bu, 0x00u, 0x20u, 0xcbu, 0x62u, 0x40u, 0x23u, 0xcbu, 0x60u, 0x2cu, 0x3bu, 0x08u, 0x60u, 0x4bu, 0x61u, 0x4bu, 0x62u, 0x00u, 0xbdu, 0x40u, 0x33u, 0x0bu, 0x61u, 0x02u, 0x23u, 0x0bu, 0x60u, 0x68u, 0x33u, 0x4bu, 0x60u, 0x28u, 0x4bu, 0xcbu, 0x62u, 0x40u, 0x23u, @@ -1348,9 +1348,9 @@ const uint8_t cy_m0p_image[] = { 0x05u, 0x23u, 0x0bu, 0x60u, 0x66u, 0x33u, 0x4bu, 0x60u, 0x10u, 0x4bu, 0xcbu, 0x62u, 0x80u, 0x23u, 0xcbu, 0x60u, 0x40u, 0x3bu, 0x4bu, 0x61u, 0x20u, 0x3bu, 0xd4u, 0xe7u, 0x80u, 0x33u, 0x0bu, 0x61u, 0x06u, 0x23u, 0x0bu, 0x60u, 0x65u, 0x33u, 0x4bu, 0x60u, 0x0au, 0x4bu, 0xcbu, 0x62u, 0x80u, 0x23u, 0xcbu, 0x60u, 0x40u, 0x3bu, 0x4bu, 0x61u, - 0x24u, 0x3bu, 0xc6u, 0xe7u, 0x07u, 0x48u, 0xa9u, 0xe7u, 0x2cu, 0x7bu, 0x00u, 0x10u, 0x60u, 0x7bu, 0x00u, 0x10u, - 0x40u, 0x7bu, 0x00u, 0x10u, 0xc0u, 0x7bu, 0x00u, 0x10u, 0x80u, 0x7bu, 0x00u, 0x10u, 0x40u, 0x7cu, 0x00u, 0x10u, - 0x00u, 0x7cu, 0x00u, 0x10u, 0x0bu, 0x00u, 0x32u, 0x00u, 0x10u, 0xb5u, 0x00u, 0x29u, 0x01u, 0xd1u, 0x07u, 0x48u, + 0x24u, 0x3bu, 0xc6u, 0xe7u, 0x07u, 0x48u, 0xa9u, 0xe7u, 0x34u, 0x7bu, 0x00u, 0x10u, 0x68u, 0x7bu, 0x00u, 0x10u, + 0x48u, 0x7bu, 0x00u, 0x10u, 0xc8u, 0x7bu, 0x00u, 0x10u, 0x88u, 0x7bu, 0x00u, 0x10u, 0x48u, 0x7cu, 0x00u, 0x10u, + 0x08u, 0x7cu, 0x00u, 0x10u, 0x0bu, 0x00u, 0x32u, 0x00u, 0x10u, 0xb5u, 0x00u, 0x29u, 0x01u, 0xd1u, 0x07u, 0x48u, 0x10u, 0xbdu, 0x00u, 0x24u, 0x4bu, 0x69u, 0x8cu, 0x62u, 0x0cu, 0x62u, 0xa3u, 0x42u, 0xf7u, 0xd0u, 0xcau, 0x6au, 0x9bu, 0xb2u, 0x09u, 0x69u, 0xfeu, 0xf7u, 0x40u, 0xfeu, 0x20u, 0x00u, 0xf1u, 0xe7u, 0x0bu, 0x00u, 0x32u, 0x00u, 0xf0u, 0xb5u, 0x85u, 0xb0u, 0x04u, 0x00u, 0x0du, 0x1eu, 0x03u, 0x92u, 0x01u, 0x93u, 0x00u, 0xd1u, 0x95u, 0xe0u, @@ -1373,7 +1373,7 @@ const uint8_t cy_m0p_image[] = { 0xffu, 0xf7u, 0x92u, 0xfeu, 0x00u, 0x27u, 0x38u, 0x00u, 0x05u, 0xb0u, 0xf0u, 0xbdu, 0x02u, 0x9bu, 0x31u, 0x00u, 0x9fu, 0x1bu, 0x3au, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x99u, 0xfeu, 0x69u, 0x68u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x5fu, 0xfeu, 0x01u, 0x9bu, 0x00u, 0x26u, 0xdbu, 0x1bu, 0x01u, 0x93u, 0xb8u, 0xe7u, 0x02u, 0x4fu, 0xeau, 0xe7u, - 0xd0u, 0x03u, 0x00u, 0x08u, 0x08u, 0x00u, 0x00u, 0x71u, 0x0bu, 0x00u, 0x32u, 0x00u, 0xf0u, 0xb5u, 0x85u, 0xb0u, + 0xe0u, 0x03u, 0x00u, 0x08u, 0x08u, 0x00u, 0x00u, 0x71u, 0x0bu, 0x00u, 0x32u, 0x00u, 0xf0u, 0xb5u, 0x85u, 0xb0u, 0x04u, 0x00u, 0x0du, 0x1eu, 0x02u, 0x92u, 0x00u, 0xd1u, 0x7bu, 0xe0u, 0x00u, 0x2au, 0x00u, 0xd1u, 0x78u, 0xe0u, 0x8bu, 0x6au, 0x0au, 0x6au, 0x00u, 0x93u, 0x53u, 0x0fu, 0x03u, 0x93u, 0x70u, 0x23u, 0xceu, 0x68u, 0xd7u, 0x00u, 0x01u, 0x93u, 0x80u, 0x2eu, 0x01u, 0xd0u, 0x38u, 0x3bu, 0x01u, 0x93u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x4au, 0xfeu, @@ -1397,7 +1397,7 @@ const uint8_t cy_m0p_image[] = { 0xffu, 0xf7u, 0xc0u, 0xfdu, 0x28u, 0x00u, 0xffu, 0xf7u, 0x85u, 0xfdu, 0x00u, 0x20u, 0x70u, 0xbdu, 0x01u, 0x48u, 0xfcu, 0xe7u, 0xc0u, 0x46u, 0x0bu, 0x00u, 0x32u, 0x00u, 0xf0u, 0xb5u, 0x04u, 0x00u, 0xbfu, 0xb0u, 0x01u, 0x93u, 0x44u, 0xabu, 0x1fu, 0x78u, 0x0du, 0x00u, 0x16u, 0x00u, 0x00u, 0x21u, 0xc0u, 0x22u, 0x0eu, 0xa8u, 0x01u, 0xf0u, - 0xc0u, 0xfdu, 0x30u, 0x22u, 0x00u, 0x21u, 0x02u, 0xa8u, 0x01u, 0xf0u, 0xbbu, 0xfdu, 0x0eu, 0xabu, 0x3au, 0x00u, + 0xc4u, 0xfdu, 0x30u, 0x22u, 0x00u, 0x21u, 0x02u, 0xa8u, 0x01u, 0xf0u, 0xbfu, 0xfdu, 0x0eu, 0xabu, 0x3au, 0x00u, 0x02u, 0xa9u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x02u, 0xfeu, 0x00u, 0x28u, 0x18u, 0xd1u, 0x02u, 0xa9u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x7au, 0xfeu, 0x00u, 0x28u, 0x12u, 0xd1u, 0x33u, 0x00u, 0x2au, 0x00u, 0x02u, 0xa9u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x86u, 0xfeu, 0x00u, 0x28u, 0x0au, 0xd1u, 0x01u, 0x9au, 0x02u, 0xa9u, 0x20u, 0x00u, 0xffu, 0xf7u, @@ -1409,7 +1409,7 @@ const uint8_t cy_m0p_image[] = { 0x60u, 0x21u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0x5eu, 0xfbu, 0x40u, 0x21u, 0x0au, 0x4bu, 0x1au, 0x68u, 0x13u, 0x68u, 0xe3u, 0x18u, 0x18u, 0x68u, 0x08u, 0x40u, 0xfcu, 0xd1u, 0xd3u, 0x69u, 0xe3u, 0x18u, 0x1au, 0x68u, 0x04u, 0x9bu, 0x1au, 0x60u, 0xa1u, 0x23u, 0x9bu, 0x00u, 0xe0u, 0x50u, 0x70u, 0xbdu, 0xc0u, 0x46u, 0x00u, 0x00u, 0x03u, 0x31u, - 0x01u, 0x00u, 0x01u, 0x00u, 0xd0u, 0x03u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x04u, 0x00u, 0xa0u, 0x20u, 0x1cu, 0x4du, + 0x01u, 0x00u, 0x01u, 0x00u, 0xe0u, 0x03u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x04u, 0x00u, 0xa0u, 0x20u, 0x1cu, 0x4du, 0x80u, 0x00u, 0x25u, 0x50u, 0x3fu, 0x25u, 0x04u, 0x30u, 0xb0u, 0x26u, 0x25u, 0x50u, 0x00u, 0x25u, 0xb6u, 0x00u, 0xa5u, 0x51u, 0x08u, 0x36u, 0xa5u, 0x51u, 0x17u, 0x4fu, 0x08u, 0x36u, 0x01u, 0x35u, 0xa5u, 0x51u, 0x10u, 0x36u, 0xa7u, 0x51u, 0x40u, 0x3eu, 0xa1u, 0x51u, 0xa9u, 0x21u, 0x89u, 0x00u, 0x62u, 0x50u, 0xa2u, 0x22u, 0x92u, 0x00u, @@ -1417,20 +1417,20 @@ const uint8_t cy_m0p_image[] = { 0x0du, 0x4bu, 0x1du, 0x68u, 0x2bu, 0x68u, 0xe1u, 0x18u, 0x03u, 0x00u, 0x08u, 0x68u, 0xe6u, 0x58u, 0x16u, 0x42u, 0x07u, 0xd0u, 0xc0u, 0x0fu, 0xf9u, 0xd1u, 0xebu, 0x69u, 0xe3u, 0x18u, 0x1au, 0x68u, 0x05u, 0x9bu, 0x1au, 0x60u, 0x00u, 0xe0u, 0x06u, 0x48u, 0xa1u, 0x23u, 0x00u, 0x22u, 0x9bu, 0x00u, 0xe2u, 0x50u, 0xf0u, 0xbdu, 0xc0u, 0x46u, - 0x00u, 0x00u, 0x03u, 0x31u, 0x01u, 0x00u, 0x01u, 0x00u, 0xd0u, 0x03u, 0x00u, 0x08u, 0x01u, 0x00u, 0x32u, 0x00u, + 0x00u, 0x00u, 0x03u, 0x31u, 0x01u, 0x00u, 0x01u, 0x00u, 0xe0u, 0x03u, 0x00u, 0x08u, 0x01u, 0x00u, 0x32u, 0x00u, 0x07u, 0x4bu, 0x89u, 0x00u, 0x1au, 0x68u, 0x93u, 0x6bu, 0x12u, 0x69u, 0xc3u, 0x18u, 0x89u, 0x18u, 0x08u, 0x18u, 0x1bu, 0x68u, 0x00u, 0x68u, 0x80u, 0x00u, 0x80u, 0x0cu, 0x80u, 0x00u, 0xc0u, 0x18u, 0x70u, 0x47u, 0xc0u, 0x46u, - 0xd0u, 0x03u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x06u, 0x4cu, 0x24u, 0x68u, 0x29u, 0x34u, 0x24u, 0x78u, 0x1fu, 0x2cu, + 0xe0u, 0x03u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x06u, 0x4cu, 0x24u, 0x68u, 0x29u, 0x34u, 0x24u, 0x78u, 0x1fu, 0x2cu, 0x02u, 0xd8u, 0xfeu, 0xf7u, 0x47u, 0xfbu, 0x10u, 0xbdu, 0xfeu, 0xf7u, 0x16u, 0xfcu, 0xfbu, 0xe7u, 0xc0u, 0x46u, - 0xdcu, 0x05u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x1fu, 0x24u, 0x95u, 0x00u, 0x13u, 0x05u, 0x09u, 0x4au, 0xadu, 0x0cu, + 0xecu, 0x05u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x1fu, 0x24u, 0x95u, 0x00u, 0x13u, 0x05u, 0x09u, 0x4au, 0xadu, 0x0cu, 0x12u, 0x68u, 0x89u, 0x06u, 0x29u, 0x32u, 0x12u, 0x78u, 0x1bu, 0x0du, 0x94u, 0x42u, 0xa4u, 0x41u, 0x64u, 0x42u, 0x0cu, 0x34u, 0xa5u, 0x40u, 0x0bu, 0x43u, 0x2bu, 0x43u, 0x80u, 0x22u, 0x00u, 0x21u, 0xfeu, 0xf7u, 0x6cu, 0xf8u, - 0x70u, 0xbdu, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x09u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xc0u, 0x18u, + 0x70u, 0xbdu, 0xc0u, 0x46u, 0xecu, 0x05u, 0x00u, 0x08u, 0x09u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xc0u, 0x18u, 0x08u, 0x4bu, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x04u, 0xd8u, 0x80u, 0x23u, 0x02u, 0x68u, 0x1au, 0x42u, 0xfcu, 0xd1u, 0x70u, 0x47u, 0x03u, 0x68u, 0x00u, 0x2bu, 0xfcu, 0xd1u, 0xfau, 0xe7u, 0xc0u, 0x46u, - 0xd0u, 0x03u, 0x00u, 0x08u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x13u, 0x00u, 0x06u, 0x4au, 0x14u, 0x68u, + 0xe0u, 0x03u, 0x00u, 0x08u, 0xecu, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x13u, 0x00u, 0x06u, 0x4au, 0x14u, 0x68u, 0x29u, 0x34u, 0x22u, 0x78u, 0x1fu, 0x2au, 0x03u, 0xd8u, 0x00u, 0x22u, 0xfeu, 0xf7u, 0x21u, 0xfbu, 0x10u, 0xbdu, - 0x00u, 0x22u, 0xfeu, 0xf7u, 0x0fu, 0xfcu, 0xfau, 0xe7u, 0xdcu, 0x05u, 0x00u, 0x08u, 0xf7u, 0xb5u, 0x04u, 0x00u, + 0x00u, 0x22u, 0xfeu, 0xf7u, 0x0fu, 0xfcu, 0xfau, 0xe7u, 0xecu, 0x05u, 0x00u, 0x08u, 0xf7u, 0xb5u, 0x04u, 0x00u, 0x00u, 0x93u, 0x0eu, 0x00u, 0x01u, 0x92u, 0xffu, 0xf7u, 0xcfu, 0xffu, 0x1bu, 0x4bu, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x2du, 0xd8u, 0x19u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x69u, 0xe3u, 0x18u, 0x1fu, 0x68u, 0x5du, 0x68u, 0x31u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x83u, 0xffu, 0x06u, 0x00u, 0x00u, 0x9au, 0x01u, 0x00u, @@ -1438,47 +1438,47 @@ const uint8_t cy_m0p_image[] = { 0x01u, 0x9au, 0x07u, 0x33u, 0xdbu, 0x08u, 0x9bu, 0xb2u, 0x31u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x82u, 0xffu, 0x09u, 0x4bu, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x09u, 0xd8u, 0x3au, 0x00u, 0x00u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x87u, 0xffu, 0x2au, 0x00u, 0x01u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x82u, 0xffu, - 0xf7u, 0xbdu, 0x00u, 0x25u, 0x2fu, 0x00u, 0xd4u, 0xe7u, 0xdcu, 0x05u, 0x00u, 0x08u, 0xd0u, 0x03u, 0x00u, 0x08u, + 0xf7u, 0xbdu, 0x00u, 0x25u, 0x2fu, 0x00u, 0xd4u, 0xe7u, 0xecu, 0x05u, 0x00u, 0x08u, 0xe0u, 0x03u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x85u, 0xb0u, 0x03u, 0x93u, 0x04u, 0x00u, 0x01u, 0x91u, 0x02u, 0x92u, 0xffu, 0xf7u, 0x8cu, 0xffu, 0x16u, 0x4eu, 0x33u, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x23u, 0xd8u, 0x14u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x69u, 0xe3u, 0x18u, 0x1fu, 0x68u, 0x5du, 0x68u, 0x02u, 0x99u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x40u, 0xffu, 0x03u, 0x9bu, 0x02u, 0x00u, 0x07u, 0x33u, 0xdbu, 0x08u, 0x9bu, 0xb2u, 0x01u, 0x99u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x49u, 0xffu, 0x33u, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x09u, 0xd8u, 0x3au, 0x00u, 0x00u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x4fu, 0xffu, 0x2au, 0x00u, 0x01u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x4au, 0xffu, - 0x05u, 0xb0u, 0xf0u, 0xbdu, 0x00u, 0x25u, 0x2fu, 0x00u, 0xdeu, 0xe7u, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, - 0xd0u, 0x03u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, 0x0bu, 0x00u, 0x3fu, 0x22u, 0x00u, 0x21u, 0xfdu, 0xf7u, + 0x05u, 0xb0u, 0xf0u, 0xbdu, 0x00u, 0x25u, 0x2fu, 0x00u, 0xdeu, 0xe7u, 0xc0u, 0x46u, 0xecu, 0x05u, 0x00u, 0x08u, + 0xe0u, 0x03u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, 0x0bu, 0x00u, 0x3fu, 0x22u, 0x00u, 0x21u, 0xfdu, 0xf7u, 0xbbu, 0xffu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x50u, 0xffu, 0x03u, 0x4bu, 0x1bu, 0x68u, 0xdbu, 0x6bu, 0xe4u, 0x18u, - 0x20u, 0x68u, 0x40u, 0x07u, 0xc0u, 0x0fu, 0x10u, 0xbdu, 0xd0u, 0x03u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, + 0x20u, 0x68u, 0x40u, 0x07u, 0xc0u, 0x0fu, 0x10u, 0xbdu, 0xe0u, 0x03u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, 0x13u, 0x01u, 0x0bu, 0x43u, 0x3du, 0x22u, 0x00u, 0x21u, 0xfdu, 0xf7u, 0xa6u, 0xffu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x3bu, 0xffu, 0x04u, 0x4bu, 0x1bu, 0x68u, 0xdbu, 0x6bu, 0xe4u, 0x18u, 0x20u, 0x68u, 0x40u, 0x07u, 0xc0u, 0x0fu, - 0x10u, 0xbdu, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, 0x13u, 0x01u, 0x0bu, 0x43u, + 0x10u, 0xbdu, 0xc0u, 0x46u, 0xe0u, 0x03u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, 0x13u, 0x01u, 0x0bu, 0x43u, 0x3du, 0x22u, 0x00u, 0x21u, 0xfdu, 0xf7u, 0x90u, 0xffu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x25u, 0xffu, 0x04u, 0x4bu, 0x1bu, 0x68u, 0xdbu, 0x6bu, 0xe4u, 0x18u, 0x01u, 0x23u, 0x20u, 0x68u, 0x18u, 0x40u, 0x10u, 0xbdu, 0xc0u, 0x46u, - 0xd0u, 0x03u, 0x00u, 0x08u, 0x08u, 0x4bu, 0x10u, 0xb5u, 0x1au, 0x68u, 0x8bu, 0x00u, 0x12u, 0x69u, 0x9bu, 0x18u, + 0xe0u, 0x03u, 0x00u, 0x08u, 0x08u, 0x4bu, 0x10u, 0xb5u, 0x1au, 0x68u, 0x8bu, 0x00u, 0x12u, 0x69u, 0x9bu, 0x18u, 0xc3u, 0x18u, 0x1cu, 0x68u, 0xffu, 0xf7u, 0xd4u, 0xfeu, 0xe1u, 0x04u, 0xc9u, 0x0cu, 0x08u, 0x31u, 0xc9u, 0x08u, - 0xfeu, 0xf7u, 0x3eu, 0xf9u, 0x10u, 0xbdu, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, 0x00u, 0x28u, 0x07u, 0xdbu, + 0xfeu, 0xf7u, 0x3eu, 0xf9u, 0x10u, 0xbdu, 0xc0u, 0x46u, 0xe0u, 0x03u, 0x00u, 0x08u, 0x00u, 0x28u, 0x07u, 0xdbu, 0x1fu, 0x23u, 0xc0u, 0x22u, 0x18u, 0x40u, 0x1eu, 0x3bu, 0x83u, 0x40u, 0x02u, 0x49u, 0x52u, 0x00u, 0x8bu, 0x50u, 0x70u, 0x47u, 0xc0u, 0x46u, 0x00u, 0xe1u, 0x00u, 0xe0u, 0x30u, 0xb5u, 0xf8u, 0x25u, 0x0fu, 0x4bu, 0x10u, 0x4au, 0x18u, 0x68u, 0x14u, 0x68u, 0x43u, 0x6au, 0x22u, 0x6cu, 0x6du, 0x03u, 0x9au, 0x18u, 0x11u, 0x68u, 0x29u, 0x40u, 0x10u, 0xd0u, 0x11u, 0x60u, 0x22u, 0x6cu, 0x9bu, 0x18u, 0x1bu, 0x68u, 0x0au, 0x4bu, 0x1au, 0x68u, 0x53u, 0x1cu, 0xd9u, 0x7fu, 0x00u, 0x29u, 0x07u, 0xd1u, 0x41u, 0x6au, 0x08u, 0x6au, 0x49u, 0x6au, 0x50u, 0x62u, 0x91u, 0x62u, - 0x01u, 0x22u, 0xdau, 0x77u, 0x30u, 0xbdu, 0x00u, 0x22u, 0xfbu, 0xe7u, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, - 0xd0u, 0x03u, 0x00u, 0x08u, 0xdcu, 0x03u, 0x00u, 0x08u, 0x00u, 0x22u, 0x70u, 0xb5u, 0x04u, 0x00u, 0x03u, 0x68u, + 0x01u, 0x22u, 0xdau, 0x77u, 0x30u, 0xbdu, 0x00u, 0x22u, 0xfbu, 0xe7u, 0xc0u, 0x46u, 0xecu, 0x05u, 0x00u, 0x08u, + 0xe0u, 0x03u, 0x00u, 0x08u, 0xecu, 0x03u, 0x00u, 0x08u, 0x00u, 0x22u, 0x70u, 0xb5u, 0x04u, 0x00u, 0x03u, 0x68u, 0x0du, 0x00u, 0x0bu, 0x60u, 0x43u, 0x68u, 0x4bu, 0x60u, 0x83u, 0x69u, 0x8bu, 0x60u, 0xc3u, 0x69u, 0xcbu, 0x60u, 0x4bu, 0x1cu, 0xdau, 0x77u, 0x03u, 0x8cu, 0x0bu, 0x82u, 0x03u, 0x8du, 0x0bu, 0x83u, 0xfdu, 0xf7u, 0xceu, 0xffu, - 0xa1u, 0x69u, 0x00u, 0x29u, 0x00u, 0xd1u, 0x20u, 0x49u, 0x20u, 0x00u, 0x20u, 0x30u, 0x00u, 0xf0u, 0x6eu, 0xfeu, + 0xa1u, 0x69u, 0x00u, 0x29u, 0x00u, 0xd1u, 0x20u, 0x49u, 0x20u, 0x00u, 0x20u, 0x30u, 0x00u, 0xf0u, 0x72u, 0xfeu, 0x20u, 0x22u, 0xa3u, 0x5eu, 0x00u, 0x2bu, 0x06u, 0xdbu, 0x1fu, 0x22u, 0x13u, 0x40u, 0x1eu, 0x3au, 0x9au, 0x40u, 0x13u, 0x00u, 0x1au, 0x4au, 0x13u, 0x60u, 0x1au, 0x4eu, 0x63u, 0x68u, 0x32u, 0x68u, 0x80u, 0x33u, 0x12u, 0x6au, 0x5bu, 0x01u, 0x9bu, 0x18u, 0x80u, 0x22u, 0x21u, 0x68u, 0x52u, 0x02u, 0x8au, 0x40u, 0xe1u, 0x69u, 0x9au, 0x60u, - 0x00u, 0x29u, 0x00u, 0xd1u, 0x13u, 0x49u, 0x20u, 0x00u, 0x28u, 0x30u, 0x00u, 0xf0u, 0x4fu, 0xfeu, 0x28u, 0x23u, + 0x00u, 0x29u, 0x00u, 0xd1u, 0x13u, 0x49u, 0x20u, 0x00u, 0x28u, 0x30u, 0x00u, 0xf0u, 0x53u, 0xfeu, 0x28u, 0x23u, 0xe0u, 0x5eu, 0xffu, 0xf7u, 0x8bu, 0xffu, 0x28u, 0x22u, 0xa3u, 0x5eu, 0x00u, 0x2bu, 0x06u, 0xdbu, 0x1fu, 0x22u, 0x13u, 0x40u, 0x1eu, 0x3au, 0x9au, 0x40u, 0x13u, 0x00u, 0x08u, 0x4au, 0x13u, 0x60u, 0x0au, 0x4au, 0x33u, 0x68u, 0x12u, 0x68u, 0x5bu, 0x6au, 0x92u, 0x6cu, 0x00u, 0x20u, 0x9bu, 0x18u, 0xf8u, 0x22u, 0x52u, 0x03u, 0x1au, 0x60u, 0x06u, 0x4bu, 0x1du, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u, 0xe1u, 0x5eu, 0x00u, 0x10u, 0x00u, 0xe1u, 0x00u, 0xe0u, - 0xdcu, 0x05u, 0x00u, 0x08u, 0x79u, 0x59u, 0x00u, 0x10u, 0xd0u, 0x03u, 0x00u, 0x08u, 0xdcu, 0x03u, 0x00u, 0x08u, + 0xecu, 0x05u, 0x00u, 0x08u, 0x79u, 0x59u, 0x00u, 0x10u, 0xe0u, 0x03u, 0x00u, 0x08u, 0xecu, 0x03u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x07u, 0x4bu, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1au, 0x78u, 0x06u, 0x4bu, 0x1fu, 0x2au, 0x04u, 0xd8u, 0x05u, 0x4au, 0x1au, 0x60u, 0xffu, 0xf7u, 0x90u, 0xffu, 0x10u, 0xbdu, 0x04u, 0x4au, 0xf9u, 0xe7u, 0xc0u, 0x46u, - 0xdcu, 0x05u, 0x00u, 0x08u, 0xd8u, 0x03u, 0x00u, 0x08u, 0x80u, 0x7cu, 0x00u, 0x10u, 0xd8u, 0x7cu, 0x00u, 0x10u, + 0xecu, 0x05u, 0x00u, 0x08u, 0xe8u, 0x03u, 0x00u, 0x08u, 0x88u, 0x7cu, 0x00u, 0x10u, 0xe0u, 0x7cu, 0x00u, 0x10u, 0xf0u, 0xb5u, 0xb4u, 0x4bu, 0x85u, 0xb0u, 0x1cu, 0x68u, 0x00u, 0x2cu, 0x1eu, 0xd0u, 0xb2u, 0x4bu, 0xb3u, 0x4du, 0x63u, 0x60u, 0x2bu, 0x68u, 0x5fu, 0x6au, 0x23u, 0x78u, 0x01u, 0x2bu, 0x18u, 0xd1u, 0x38u, 0x00u, 0xfeu, 0xf7u, 0x21u, 0xf8u, 0x60u, 0x60u, 0x00u, 0x23u, 0xabu, 0x4au, 0xe1u, 0x69u, 0x13u, 0x60u, 0x2bu, 0x68u, 0x1au, 0x00u, @@ -1524,8 +1524,8 @@ const uint8_t cy_m0p_image[] = { 0x40u, 0x6au, 0x52u, 0x69u, 0xb0u, 0x47u, 0x99u, 0xe7u, 0x96u, 0x69u, 0xedu, 0xe7u, 0xd6u, 0x69u, 0x28u, 0x68u, 0x00u, 0x2eu, 0x00u, 0xd1u, 0xedu, 0xe6u, 0xa1u, 0x6au, 0x03u, 0x91u, 0x8bu, 0x6au, 0x02u, 0x93u, 0x4bu, 0x6au, 0x01u, 0x93u, 0x0bu, 0x6au, 0x00u, 0x93u, 0xcbu, 0x69u, 0x8au, 0x69u, 0x40u, 0x6au, 0x49u, 0x69u, 0xb0u, 0x47u, - 0x84u, 0xe7u, 0xc0u, 0x46u, 0xe0u, 0x03u, 0x00u, 0x08u, 0x09u, 0x00u, 0x32u, 0x00u, 0xdcu, 0x05u, 0x00u, 0x08u, - 0xd0u, 0x03u, 0x00u, 0x08u, 0x0au, 0x00u, 0x32u, 0x00u, 0xd8u, 0x03u, 0x00u, 0x08u, 0xdcu, 0x03u, 0x00u, 0x08u, + 0x84u, 0xe7u, 0xc0u, 0x46u, 0xf0u, 0x03u, 0x00u, 0x08u, 0x09u, 0x00u, 0x32u, 0x00u, 0xecu, 0x05u, 0x00u, 0x08u, + 0xe0u, 0x03u, 0x00u, 0x08u, 0x0au, 0x00u, 0x32u, 0x00u, 0xe8u, 0x03u, 0x00u, 0x08u, 0xecu, 0x03u, 0x00u, 0x08u, 0x01u, 0x00u, 0x32u, 0x00u, 0x56u, 0x6au, 0x28u, 0x68u, 0x00u, 0x2eu, 0x00u, 0xd1u, 0xc9u, 0xe6u, 0xa1u, 0x6au, 0x0bu, 0x7bu, 0x00u, 0x93u, 0x8bu, 0x68u, 0x4au, 0x68u, 0x40u, 0x6au, 0x09u, 0x68u, 0xb0u, 0x47u, 0x65u, 0xe7u, 0x96u, 0x6au, 0x28u, 0x68u, 0x00u, 0x2eu, 0x00u, 0xd1u, 0xbbu, 0xe6u, 0xa1u, 0x6au, 0x0bu, 0x7bu, 0x02u, 0x93u, @@ -1549,10 +1549,10 @@ const uint8_t cy_m0p_image[] = { 0x29u, 0x6au, 0x80u, 0x33u, 0x5bu, 0x01u, 0xcbu, 0x18u, 0xdeu, 0x68u, 0x82u, 0x40u, 0x36u, 0x0cu, 0xb2u, 0x42u, 0x11u, 0xd1u, 0x12u, 0x04u, 0x1au, 0x60u, 0xacu, 0x35u, 0x1bu, 0x68u, 0x2bu, 0x88u, 0x58u, 0x43u, 0x40u, 0x18u, 0x07u, 0x49u, 0x00u, 0xf0u, 0xb5u, 0xf8u, 0x00u, 0x28u, 0x05u, 0xd1u, 0x23u, 0x68u, 0x9bu, 0x68u, 0x00u, 0x2bu, - 0x01u, 0xd1u, 0xffu, 0xf7u, 0xcdu, 0xfdu, 0x70u, 0xbdu, 0xdcu, 0x03u, 0x00u, 0x08u, 0xdcu, 0x05u, 0x00u, 0x08u, - 0xe0u, 0x03u, 0x00u, 0x08u, 0x01u, 0x4bu, 0x18u, 0x60u, 0x70u, 0x47u, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, + 0x01u, 0xd1u, 0xffu, 0xf7u, 0xcdu, 0xfdu, 0x70u, 0xbdu, 0xecu, 0x03u, 0x00u, 0x08u, 0xecu, 0x05u, 0x00u, 0x08u, + 0xf0u, 0x03u, 0x00u, 0x08u, 0x01u, 0x4bu, 0x18u, 0x60u, 0x70u, 0x47u, 0xc0u, 0x46u, 0xecu, 0x05u, 0x00u, 0x08u, 0x04u, 0x4bu, 0x1bu, 0x68u, 0x1au, 0x00u, 0xacu, 0x32u, 0x12u, 0x88u, 0x1bu, 0x6au, 0x50u, 0x43u, 0xc0u, 0x18u, - 0x70u, 0x47u, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x1du, 0x4bu, 0x98u, 0x42u, 0x0fu, 0xd0u, 0x10u, 0xd8u, + 0x70u, 0x47u, 0xc0u, 0x46u, 0xecu, 0x05u, 0x00u, 0x08u, 0x1du, 0x4bu, 0x98u, 0x42u, 0x0fu, 0xd0u, 0x10u, 0xd8u, 0x40u, 0x28u, 0x2fu, 0xd0u, 0x05u, 0xd8u, 0x00u, 0x28u, 0x30u, 0xd0u, 0x10u, 0x28u, 0x28u, 0xd0u, 0x19u, 0x48u, 0x1eu, 0xe0u, 0x80u, 0x28u, 0x28u, 0xd0u, 0x80u, 0x23u, 0x5bu, 0x00u, 0x98u, 0x42u, 0xf7u, 0xd1u, 0x14u, 0x48u, 0x16u, 0xe0u, 0x15u, 0x4bu, 0x98u, 0x42u, 0x14u, 0xd0u, 0x08u, 0xd8u, 0xa0u, 0x23u, 0x1bu, 0x06u, 0x98u, 0x42u, @@ -1566,32 +1566,32 @@ const uint8_t cy_m0p_image[] = { 0x05u, 0x00u, 0x52u, 0x00u, 0x10u, 0xb5u, 0x00u, 0x20u, 0xffu, 0xf7u, 0x9au, 0xffu, 0x0au, 0x4bu, 0x1cu, 0x68u, 0x23u, 0x00u, 0xb0u, 0x33u, 0x1bu, 0x68u, 0xc0u, 0x18u, 0x03u, 0x68u, 0x00u, 0x2bu, 0x0au, 0xdbu, 0x07u, 0x4bu, 0x18u, 0x68u, 0xffu, 0xf7u, 0x99u, 0xffu, 0x01u, 0x22u, 0x63u, 0x68u, 0x9au, 0x60u, 0x9au, 0x68u, 0x00u, 0x2au, - 0xfcu, 0xd1u, 0x10u, 0xbdu, 0x02u, 0x48u, 0xfcu, 0xe7u, 0xdcu, 0x05u, 0x00u, 0x08u, 0xe4u, 0x03u, 0x00u, 0x08u, + 0xfcu, 0xd1u, 0x10u, 0xbdu, 0x02u, 0x48u, 0xfcu, 0xe7u, 0xecu, 0x05u, 0x00u, 0x08u, 0xf4u, 0x03u, 0x00u, 0x08u, 0x02u, 0x00u, 0x50u, 0x00u, 0x06u, 0x4bu, 0x1bu, 0x68u, 0xb0u, 0x33u, 0x1bu, 0x68u, 0xc3u, 0x18u, 0x1bu, 0x68u, 0x00u, 0x2bu, 0x03u, 0xdau, 0x89u, 0xb2u, 0x41u, 0x60u, 0x00u, 0x20u, 0x70u, 0x47u, 0x01u, 0x48u, 0xfcu, 0xe7u, - 0xdcu, 0x05u, 0x00u, 0x08u, 0x01u, 0x00u, 0x8au, 0x00u, 0x03u, 0x68u, 0x00u, 0x2bu, 0x04u, 0xdau, 0x89u, 0xb2u, + 0xecu, 0x05u, 0x00u, 0x08u, 0x01u, 0x00u, 0x8au, 0x00u, 0x03u, 0x68u, 0x00u, 0x2bu, 0x04u, 0xdau, 0x89u, 0xb2u, 0xc2u, 0x60u, 0x81u, 0x60u, 0x00u, 0x20u, 0x70u, 0x47u, 0x00u, 0x48u, 0xfcu, 0xe7u, 0x01u, 0x00u, 0x8au, 0x00u, 0x06u, 0x4bu, 0x1bu, 0x68u, 0xb0u, 0x33u, 0x1bu, 0x68u, 0xc3u, 0x18u, 0x1bu, 0x68u, 0x00u, 0x2bu, 0x03u, 0xdau, - 0xc3u, 0x68u, 0x00u, 0x20u, 0x0bu, 0x60u, 0x70u, 0x47u, 0x01u, 0x48u, 0xfcu, 0xe7u, 0xdcu, 0x05u, 0x00u, 0x08u, + 0xc3u, 0x68u, 0x00u, 0x20u, 0x0bu, 0x60u, 0x70u, 0x47u, 0x01u, 0x48u, 0xfcu, 0xe7u, 0xecu, 0x05u, 0x00u, 0x08u, 0x01u, 0x00u, 0x8au, 0x00u, 0x02u, 0x4bu, 0x1au, 0x68u, 0x00u, 0x2au, 0x00u, 0xd1u, 0x18u, 0x60u, 0x70u, 0x47u, - 0xf8u, 0x03u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x2cu, 0x24u, 0x60u, 0x43u, 0x12u, 0x4cu, 0x1fu, 0x00u, 0x24u, 0x68u, + 0x08u, 0x04u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x2cu, 0x24u, 0x60u, 0x43u, 0x12u, 0x4cu, 0x1fu, 0x00u, 0x24u, 0x68u, 0x1eu, 0x0au, 0x20u, 0x18u, 0xffu, 0x24u, 0x27u, 0x40u, 0x34u, 0x40u, 0x0fu, 0x4eu, 0x1bu, 0x0cu, 0x35u, 0x68u, 0x07u, 0x60u, 0x2eu, 0x6au, 0x44u, 0x60u, 0x83u, 0x60u, 0xacu, 0x35u, 0x2du, 0x88u, 0x80u, 0x34u, 0x6fu, 0x43u, 0x64u, 0x01u, 0x34u, 0x19u, 0xbfu, 0x19u, 0x1eu, 0x04u, 0x33u, 0x43u, 0x07u, 0x61u, 0x44u, 0x61u, 0xa3u, 0x60u, 0x00u, 0x23u, 0x83u, 0x61u, 0x05u, 0x9bu, 0xc2u, 0x61u, 0x01u, 0x62u, 0x00u, 0x2bu, 0x01u, 0xd0u, 0x1bu, 0x88u, - 0x83u, 0x81u, 0xf0u, 0xbdu, 0xf8u, 0x03u, 0x00u, 0x08u, 0xdcu, 0x05u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x83u, 0x68u, + 0x83u, 0x81u, 0xf0u, 0xbdu, 0x08u, 0x04u, 0x00u, 0x08u, 0xecu, 0x05u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x83u, 0x68u, 0x85u, 0xb0u, 0x02u, 0xadu, 0x2bu, 0x80u, 0x15u, 0x4bu, 0x02u, 0x68u, 0x1bu, 0x68u, 0x06u, 0x6au, 0x9bu, 0x8eu, 0x47u, 0x6au, 0x9bu, 0x18u, 0x6bu, 0x80u, 0x43u, 0x68u, 0x00u, 0x95u, 0x82u, 0x6au, 0xc1u, 0x6au, 0x04u, 0x00u, 0x03u, 0x93u, 0x03u, 0x69u, 0xc0u, 0x68u, 0xffu, 0xf7u, 0xbdu, 0xffu, 0x00u, 0x21u, 0x3bu, 0x00u, 0x0au, 0x00u, - 0x00u, 0x91u, 0x30u, 0x00u, 0xffu, 0xf7u, 0xb6u, 0xffu, 0x21u, 0x6bu, 0x28u, 0x00u, 0x00u, 0xf0u, 0xc6u, 0xfau, + 0x00u, 0x91u, 0x30u, 0x00u, 0xffu, 0xf7u, 0xb6u, 0xffu, 0x21u, 0x6bu, 0x28u, 0x00u, 0x00u, 0xf0u, 0xcau, 0xfau, 0x00u, 0x22u, 0xabu, 0x5eu, 0x00u, 0x2bu, 0x06u, 0xdbu, 0x1fu, 0x22u, 0x13u, 0x40u, 0x1eu, 0x3au, 0x9au, 0x40u, - 0x13u, 0x00u, 0x03u, 0x4au, 0x13u, 0x60u, 0x05u, 0xb0u, 0xf0u, 0xbdu, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, + 0x13u, 0x00u, 0x03u, 0x4au, 0x13u, 0x60u, 0x05u, 0xb0u, 0xf0u, 0xbdu, 0xc0u, 0x46u, 0xecu, 0x05u, 0x00u, 0x08u, 0x00u, 0xe1u, 0x00u, 0xe0u, 0xf7u, 0xb5u, 0x2cu, 0x25u, 0x13u, 0x4cu, 0x68u, 0x43u, 0x26u, 0x68u, 0x69u, 0x43u, 0x34u, 0x18u, 0x25u, 0x69u, 0x01u, 0x93u, 0x71u, 0x18u, 0x00u, 0x2du, 0x19u, 0xd0u, 0x88u, 0x69u, 0x00u, 0x28u, 0x18u, 0xd1u, 0x2eu, 0x68u, 0x00u, 0x2eu, 0x15u, 0xdau, 0x67u, 0x68u, 0x01u, 0x24u, 0x26u, 0x00u, 0x4bu, 0x68u, 0x9eu, 0x40u, 0xb4u, 0x46u, 0x13u, 0x68u, 0x9eu, 0xb2u, 0x63u, 0x46u, 0x1bu, 0x04u, 0x1eu, 0x43u, 0x16u, 0x60u, 0xeau, 0x60u, 0x8cu, 0x61u, 0xbcu, 0x40u, 0x01u, 0x9bu, 0xa4u, 0xb2u, 0x4bu, 0x62u, 0xacu, 0x60u, 0xfeu, 0xbdu, - 0x02u, 0x48u, 0xfcu, 0xe7u, 0x02u, 0x48u, 0xfau, 0xe7u, 0xf8u, 0x03u, 0x00u, 0x08u, 0x04u, 0x02u, 0x8au, 0x00u, + 0x02u, 0x48u, 0xfcu, 0xe7u, 0x02u, 0x48u, 0xfau, 0xe7u, 0x08u, 0x04u, 0x00u, 0x08u, 0x04u, 0x02u, 0x8au, 0x00u, 0x07u, 0x02u, 0x8au, 0x00u, 0x73u, 0xb5u, 0x00u, 0x26u, 0x42u, 0x69u, 0x04u, 0x00u, 0xd5u, 0x68u, 0x01u, 0x96u, 0x2bu, 0x0cu, 0xb3u, 0x42u, 0x21u, 0xd0u, 0x1bu, 0x04u, 0x13u, 0x60u, 0x13u, 0x68u, 0x19u, 0x4bu, 0x00u, 0x69u, 0x1bu, 0x68u, 0xb0u, 0x33u, 0x1bu, 0x68u, 0xc3u, 0x18u, 0x1bu, 0x68u, 0xb3u, 0x42u, 0x15u, 0xdau, 0x01u, 0xa9u, @@ -1600,34 +1600,34 @@ const uint8_t cy_m0p_image[] = { 0x98u, 0x47u, 0x31u, 0x00u, 0x20u, 0x69u, 0xffu, 0xf7u, 0x0du, 0xffu, 0xadu, 0xb2u, 0x00u, 0x2du, 0x09u, 0xd0u, 0x63u, 0x69u, 0x1du, 0x60u, 0x00u, 0x25u, 0x1bu, 0x68u, 0x63u, 0x6au, 0xabu, 0x42u, 0x05u, 0xd0u, 0x98u, 0x47u, 0x65u, 0x62u, 0xa5u, 0x61u, 0x63u, 0x69u, 0x1bu, 0x68u, 0x73u, 0xbdu, 0xa3u, 0x6au, 0x00u, 0x2bu, 0xf8u, 0xd0u, - 0x98u, 0x47u, 0xf6u, 0xe7u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x2cu, 0x23u, 0x10u, 0xb5u, 0x43u, 0x43u, 0x03u, 0x4au, - 0x10u, 0x68u, 0xc0u, 0x18u, 0xffu, 0xf7u, 0xb6u, 0xffu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0xf8u, 0x03u, 0x00u, 0x08u, + 0x98u, 0x47u, 0xf6u, 0xe7u, 0xecu, 0x05u, 0x00u, 0x08u, 0x2cu, 0x23u, 0x10u, 0xb5u, 0x43u, 0x43u, 0x03u, 0x4au, + 0x10u, 0x68u, 0xc0u, 0x18u, 0xffu, 0xf7u, 0xb6u, 0xffu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0x08u, 0x04u, 0x00u, 0x08u, 0xf8u, 0xb5u, 0x19u, 0x4bu, 0x0fu, 0x00u, 0x1bu, 0x68u, 0x1au, 0x00u, 0x2eu, 0x32u, 0x12u, 0x78u, 0x82u, 0x42u, 0x27u, 0xd9u, 0x00u, 0x29u, 0x25u, 0xd0u, 0x1fu, 0x25u, 0x0au, 0x68u, 0x15u, 0x40u, 0x21u, 0xd1u, 0x19u, 0x00u, 0xacu, 0x31u, 0x0cu, 0x88u, 0x11u, 0x4eu, 0x60u, 0x43u, 0x1cu, 0x6au, 0xd2u, 0x08u, 0x04u, 0x19u, 0x29u, 0x00u, - 0x78u, 0x68u, 0x34u, 0x60u, 0x00u, 0xf0u, 0x3du, 0xffu, 0x29u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xcau, 0xfeu, + 0x78u, 0x68u, 0x34u, 0x60u, 0x00u, 0xf0u, 0x41u, 0xffu, 0x29u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xcau, 0xfeu, 0x3au, 0x00u, 0x29u, 0x00u, 0x30u, 0x68u, 0xffu, 0xf7u, 0xd7u, 0xfeu, 0x04u, 0x1eu, 0x07u, 0xd1u, 0x01u, 0x00u, 0x30u, 0x68u, 0xffu, 0xf7u, 0xbfu, 0xfeu, 0x03u, 0x00u, 0x20u, 0x00u, 0x00u, 0x2bu, 0x00u, 0xd0u, 0x04u, 0x48u, - 0xf8u, 0xbdu, 0x04u, 0x48u, 0xfcu, 0xe7u, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, 0xfcu, 0x03u, 0x00u, 0x08u, + 0xf8u, 0xbdu, 0x04u, 0x48u, 0xfcu, 0xe7u, 0xc0u, 0x46u, 0xecu, 0x05u, 0x00u, 0x08u, 0x0cu, 0x04u, 0x00u, 0x08u, 0x01u, 0x01u, 0x8au, 0x00u, 0x03u, 0x01u, 0x8au, 0x00u, 0x10u, 0xb5u, 0x00u, 0x2au, 0x0du, 0xd1u, 0x00u, 0x29u, 0x14u, 0xd1u, 0x0bu, 0x4bu, 0x1au, 0x68u, 0x13u, 0x00u, 0xacu, 0x33u, 0x1bu, 0x88u, 0x58u, 0x43u, 0x13u, 0x6au, 0xc0u, 0x18u, 0x08u, 0x4bu, 0x18u, 0x60u, 0x08u, 0x00u, 0x10u, 0xbdu, 0x00u, 0x29u, 0x06u, 0xd0u, 0x06u, 0x4bu, 0x19u, 0x60u, 0x19u, 0x00u, 0x5au, 0x60u, 0xffu, 0xf7u, 0xabu, 0xffu, 0xf5u, 0xe7u, 0x03u, 0x48u, 0xf3u, 0xe7u, - 0xdcu, 0x05u, 0x00u, 0x08u, 0xfcu, 0x03u, 0x00u, 0x08u, 0x78u, 0x03u, 0x00u, 0x08u, 0x03u, 0x01u, 0x8au, 0x00u, + 0xecu, 0x05u, 0x00u, 0x08u, 0x0cu, 0x04u, 0x00u, 0x08u, 0x88u, 0x03u, 0x00u, 0x08u, 0x03u, 0x01u, 0x8au, 0x00u, 0xf7u, 0xb5u, 0x18u, 0x4fu, 0x04u, 0x00u, 0x3bu, 0x68u, 0x01u, 0x91u, 0xdeu, 0x68u, 0x33u, 0x68u, 0x83u, 0x42u, 0x26u, 0xd9u, 0x00u, 0x25u, 0xa9u, 0x42u, 0x02u, 0xd1u, 0xf9u, 0xf7u, 0xc7u, 0xfeu, 0x05u, 0x00u, 0x38u, 0x68u, 0x03u, 0x68u, 0x00u, 0x2bu, 0x1au, 0xdau, 0x1fu, 0x22u, 0x01u, 0x23u, 0x22u, 0x40u, 0x93u, 0x40u, 0x64u, 0x09u, 0x72u, 0x68u, 0xa4u, 0x00u, 0x14u, 0x19u, 0x22u, 0x68u, 0x13u, 0x42u, 0x0du, 0xd0u, 0x9au, 0x43u, 0x22u, 0x60u, 0x00u, 0x24u, 0x00u, 0x21u, 0xffu, 0xf7u, 0x66u, 0xfeu, 0x01u, 0x9bu, 0x00u, 0x2bu, 0x02u, 0xd1u, 0x28u, 0x00u, 0xf9u, 0xf7u, 0xafu, 0xfeu, 0x20u, 0x00u, 0xfeu, 0xbdu, 0x03u, 0x4cu, 0xf2u, 0xe7u, 0x03u, 0x4cu, 0xf3u, 0xe7u, - 0x03u, 0x4cu, 0xf7u, 0xe7u, 0xfcu, 0x03u, 0x00u, 0x08u, 0x02u, 0x01u, 0x88u, 0x00u, 0x03u, 0x01u, 0x88u, 0x00u, + 0x03u, 0x4cu, 0xf7u, 0xe7u, 0x0cu, 0x04u, 0x00u, 0x08u, 0x02u, 0x01u, 0x88u, 0x00u, 0x03u, 0x01u, 0x88u, 0x00u, 0x04u, 0x01u, 0x8au, 0x00u, 0x0au, 0x4bu, 0x1bu, 0x68u, 0xdbu, 0x68u, 0x1au, 0x68u, 0x82u, 0x42u, 0x0du, 0xd9u, 0x59u, 0x68u, 0x1fu, 0x23u, 0x42u, 0x09u, 0x18u, 0x40u, 0x1eu, 0x3bu, 0x83u, 0x40u, 0x92u, 0x00u, 0x50u, 0x58u, 0x18u, 0x40u, 0x43u, 0x1eu, 0x98u, 0x41u, 0x03u, 0x4bu, 0xc0u, 0x18u, 0x70u, 0x47u, 0x02u, 0x48u, 0xfcu, 0xe7u, - 0xfcu, 0x03u, 0x00u, 0x08u, 0x00u, 0x01u, 0x88u, 0x00u, 0x04u, 0x01u, 0x8au, 0x00u, 0xa6u, 0x22u, 0x05u, 0x49u, + 0x0cu, 0x04u, 0x00u, 0x08u, 0x00u, 0x01u, 0x88u, 0x00u, 0x04u, 0x01u, 0x8au, 0x00u, 0xa6u, 0x22u, 0x05u, 0x49u, 0xd2u, 0x00u, 0x8bu, 0x58u, 0x02u, 0x20u, 0xdbu, 0x43u, 0x9bu, 0x07u, 0x02u, 0xd0u, 0x01u, 0x23u, 0x88u, 0x58u, 0x18u, 0x40u, 0x70u, 0x47u, 0x00u, 0x00u, 0x26u, 0x40u, 0x10u, 0xb5u, 0xffu, 0xf7u, 0xefu, 0xffu, 0x00u, 0x23u, - 0x02u, 0x28u, 0x01u, 0xd1u, 0x01u, 0x4bu, 0x1bu, 0x68u, 0x18u, 0x00u, 0x10u, 0xbdu, 0x00u, 0x04u, 0x00u, 0x08u, + 0x02u, 0x28u, 0x01u, 0xd1u, 0x01u, 0x4bu, 0x1bu, 0x68u, 0x18u, 0x00u, 0x10u, 0xbdu, 0x10u, 0x04u, 0x00u, 0x08u, 0x09u, 0x4au, 0x83u, 0x00u, 0x9bu, 0x18u, 0xd0u, 0x22u, 0x92u, 0x00u, 0x98u, 0x58u, 0x07u, 0x22u, 0x10u, 0x40u, 0x04u, 0x28u, 0x07u, 0xd1u, 0xc0u, 0x22u, 0x92u, 0x00u, 0x98u, 0x58u, 0x1fu, 0x23u, 0x03u, 0x40u, 0x80u, 0x20u, 0x40u, 0x00u, 0x18u, 0x43u, 0x70u, 0x47u, 0xc0u, 0x46u, 0x00u, 0x00u, 0x26u, 0x40u, 0x10u, 0xb5u, 0xffu, 0xf7u, @@ -1637,7 +1637,7 @@ const uint8_t cy_m0p_image[] = { 0xc0u, 0x0fu, 0xc0u, 0x03u, 0x00u, 0xe0u, 0x0bu, 0x48u, 0x10u, 0xbdu, 0x0bu, 0x4bu, 0x18u, 0x68u, 0xfbu, 0xe7u, 0xffu, 0xf7u, 0xbau, 0xffu, 0xf8u, 0xe7u, 0x09u, 0x4bu, 0x18u, 0x69u, 0x04u, 0x23u, 0x18u, 0x40u, 0xf3u, 0xd0u, 0x80u, 0x20u, 0x00u, 0x02u, 0xf0u, 0xe7u, 0x01u, 0x4au, 0x05u, 0x4bu, 0xe8u, 0xe7u, 0x00u, 0x00u, 0x26u, 0x40u, - 0x0cu, 0x05u, 0x00u, 0x00u, 0x00u, 0x12u, 0x7au, 0x00u, 0x04u, 0x04u, 0x00u, 0x08u, 0x00u, 0x00u, 0x27u, 0x40u, + 0x0cu, 0x05u, 0x00u, 0x00u, 0x00u, 0x12u, 0x7au, 0x00u, 0x14u, 0x04u, 0x00u, 0x08u, 0x00u, 0x00u, 0x27u, 0x40u, 0x3cu, 0x05u, 0x00u, 0x00u, 0xb0u, 0x23u, 0x15u, 0x4au, 0xdbu, 0x00u, 0xd3u, 0x58u, 0x10u, 0xb5u, 0x99u, 0x03u, 0xdbu, 0x01u, 0xdbu, 0x0fu, 0x89u, 0x0bu, 0xc3u, 0x71u, 0x11u, 0x4bu, 0x01u, 0x60u, 0xd3u, 0x58u, 0x0fu, 0x24u, 0xd9u, 0x04u, 0xdbu, 0x01u, 0xdbu, 0x0du, 0x03u, 0x81u, 0xb1u, 0x23u, 0xdbu, 0x00u, 0xd3u, 0x58u, 0xc9u, 0x0cu, @@ -1648,457 +1648,458 @@ const uint8_t cy_m0p_image[] = { 0x3bu, 0x33u, 0x1bu, 0x78u, 0x93u, 0x42u, 0x16u, 0xd9u, 0x7fu, 0x22u, 0x1fu, 0x24u, 0x80u, 0x30u, 0xffu, 0x30u, 0x0bu, 0x4bu, 0x80u, 0x00u, 0xc3u, 0x58u, 0x1au, 0x40u, 0x0au, 0x70u, 0x1au, 0x0cu, 0x22u, 0x40u, 0x18u, 0x0au, 0x8au, 0x70u, 0x1au, 0x01u, 0x20u, 0x40u, 0xe2u, 0x40u, 0x48u, 0x70u, 0x00u, 0x20u, 0x9bu, 0x00u, 0x9bu, 0x0fu, - 0xcau, 0x70u, 0x0bu, 0x71u, 0x10u, 0xbdu, 0x03u, 0x48u, 0xfcu, 0xe7u, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, + 0xcau, 0x70u, 0x0bu, 0x71u, 0x10u, 0xbdu, 0x03u, 0x48u, 0xfcu, 0xe7u, 0xc0u, 0x46u, 0xecu, 0x05u, 0x00u, 0x08u, 0x00u, 0x00u, 0x26u, 0x40u, 0x01u, 0x00u, 0x4au, 0x00u, 0xf0u, 0xb5u, 0x87u, 0xb0u, 0x04u, 0x00u, 0xffu, 0xf7u, - 0x65u, 0xffu, 0x06u, 0x00u, 0x00u, 0x2cu, 0x34u, 0xd1u, 0x01u, 0xadu, 0x14u, 0x22u, 0x21u, 0x00u, 0x28u, 0x00u, - 0x00u, 0xf0u, 0xcfu, 0xfdu, 0x28u, 0x00u, 0xffu, 0xf7u, 0x95u, 0xffu, 0xb0u, 0x23u, 0x25u, 0x4au, 0xdbu, 0x00u, + 0x65u, 0xffu, 0x06u, 0x00u, 0x00u, 0x2cu, 0x38u, 0xd1u, 0x01u, 0xadu, 0x14u, 0x22u, 0x21u, 0x00u, 0x28u, 0x00u, + 0x00u, 0xf0u, 0xd3u, 0xfdu, 0x28u, 0x00u, 0xffu, 0xf7u, 0x95u, 0xffu, 0xb0u, 0x23u, 0x27u, 0x4au, 0xdbu, 0x00u, 0xd3u, 0x58u, 0x00u, 0x2bu, 0x03u, 0xdau, 0xacu, 0x7bu, 0x02u, 0x3cu, 0x63u, 0x1eu, 0x9cu, 0x41u, 0xeau, 0x79u, - 0x01u, 0x9fu, 0x53u, 0x1eu, 0x9au, 0x41u, 0xa8u, 0x88u, 0x01u, 0x32u, 0x00u, 0x2cu, 0x16u, 0xd0u, 0x00u, 0x23u, - 0x19u, 0x00u, 0x00u, 0xf0u, 0x97u, 0xfcu, 0x00u, 0x23u, 0x0cu, 0x00u, 0x05u, 0x00u, 0x3au, 0x00u, 0x30u, 0x00u, - 0x19u, 0x00u, 0x00u, 0xf0u, 0x8fu, 0xfcu, 0xe6u, 0x07u, 0x6au, 0x08u, 0x32u, 0x43u, 0x63u, 0x08u, 0x80u, 0x18u, - 0x59u, 0x41u, 0x2au, 0x00u, 0x23u, 0x00u, 0x00u, 0xf0u, 0x65u, 0xfcu, 0x06u, 0x00u, 0x30u, 0x00u, 0x07u, 0xb0u, - 0xf0u, 0xbdu, 0x11u, 0x4bu, 0x1bu, 0x68u, 0x3bu, 0x33u, 0x1bu, 0x78u, 0xa3u, 0x42u, 0xf6u, 0xd3u, 0x01u, 0xadu, - 0x05u, 0x22u, 0x00u, 0x21u, 0x28u, 0x00u, 0x00u, 0xf0u, 0x94u, 0xfdu, 0x20u, 0x00u, 0x29u, 0x00u, 0x80u, 0x34u, - 0xffu, 0xf7u, 0x8au, 0xffu, 0xffu, 0x34u, 0x07u, 0x4bu, 0xa4u, 0x00u, 0xe3u, 0x58u, 0x00u, 0x24u, 0xa3u, 0x42u, - 0x03u, 0xdau, 0x2cu, 0x79u, 0x02u, 0x3cu, 0x63u, 0x1eu, 0x9cu, 0x41u, 0x2fu, 0x78u, 0x68u, 0x78u, 0xaau, 0x78u, - 0xc3u, 0xe7u, 0xc0u, 0x46u, 0x00u, 0x00u, 0x26u, 0x40u, 0xdcu, 0x05u, 0x00u, 0x08u, 0xe0u, 0x22u, 0x10u, 0xb5u, - 0x01u, 0x24u, 0x09u, 0x4bu, 0x80u, 0x00u, 0x92u, 0x00u, 0xc0u, 0x18u, 0x83u, 0x58u, 0x80u, 0x58u, 0x9bu, 0x06u, - 0x9bu, 0x0fu, 0x9cu, 0x40u, 0x0fu, 0x23u, 0x18u, 0x40u, 0xffu, 0xf7u, 0x8eu, 0xffu, 0x63u, 0x08u, 0x18u, 0x18u, - 0x21u, 0x00u, 0x00u, 0xf0u, 0x9bu, 0xfbu, 0x10u, 0xbdu, 0x00u, 0x00u, 0x26u, 0x40u, 0x14u, 0x4bu, 0x30u, 0xb5u, - 0x1au, 0x68u, 0x07u, 0x24u, 0x13u, 0x00u, 0x28u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x15u, 0xd8u, 0x83u, 0x08u, - 0x1du, 0x00u, 0xa5u, 0x43u, 0x2cu, 0x1eu, 0x0fu, 0xd1u, 0x03u, 0x34u, 0x20u, 0x40u, 0xa0u, 0x40u, 0x81u, 0x40u, - 0x12u, 0x68u, 0x9bu, 0x00u, 0x20u, 0x32u, 0xd3u, 0x18u, 0x0au, 0x00u, 0xffu, 0x21u, 0x81u, 0x40u, 0x1cu, 0x68u, - 0x62u, 0x40u, 0x11u, 0x40u, 0x61u, 0x40u, 0x19u, 0x60u, 0x30u, 0xbdu, 0x80u, 0x23u, 0x20u, 0x40u, 0x1bu, 0x06u, - 0x18u, 0x43u, 0x80u, 0x23u, 0x9bu, 0x01u, 0x12u, 0x68u, 0xc9u, 0x18u, 0x89u, 0x00u, 0x88u, 0x50u, 0xf3u, 0xe7u, - 0xdcu, 0x05u, 0x00u, 0x08u, 0x06u, 0x4bu, 0x9au, 0x68u, 0x03u, 0x00u, 0x06u, 0x48u, 0x10u, 0x33u, 0x9bu, 0x00u, - 0x82u, 0x42u, 0x02u, 0xd1u, 0x98u, 0x58u, 0x99u, 0x50u, 0x70u, 0x47u, 0x03u, 0x4au, 0xd0u, 0x58u, 0xfbu, 0xe7u, - 0x00u, 0xedu, 0x00u, 0xe0u, 0x00u, 0x00u, 0x00u, 0x08u, 0x00u, 0x00u, 0x00u, 0x10u, 0xf8u, 0xb5u, 0x06u, 0x00u, - 0x0du, 0x00u, 0x00u, 0x28u, 0x3au, 0xd0u, 0x00u, 0x23u, 0xc0u, 0x5eu, 0x00u, 0x28u, 0x28u, 0xdbu, 0x71u, 0x88u, - 0xffu, 0xf7u, 0xb4u, 0xffu, 0x00u, 0x24u, 0xffu, 0x22u, 0x03u, 0x27u, 0x94u, 0x46u, 0x00u, 0x23u, 0xf0u, 0x5eu, - 0x71u, 0x68u, 0x83u, 0xb2u, 0x1fu, 0x40u, 0xffu, 0x00u, 0x66u, 0x46u, 0xbau, 0x40u, 0x89u, 0x01u, 0x31u, 0x40u, - 0xd2u, 0x43u, 0xb9u, 0x40u, 0x00u, 0x28u, 0x15u, 0xdbu, 0x11u, 0x4eu, 0x83u, 0x08u, 0x9bu, 0x00u, 0x9bu, 0x19u, - 0xc0u, 0x26u, 0xb6u, 0x00u, 0x9fu, 0x59u, 0x3au, 0x40u, 0x11u, 0x43u, 0x99u, 0x51u, 0x0du, 0x4bu, 0x9au, 0x68u, - 0x0du, 0x4bu, 0x9au, 0x42u, 0x02u, 0xd1u, 0x29u, 0x00u, 0xffu, 0xf7u, 0xbcu, 0xffu, 0x20u, 0x00u, 0xf8u, 0xbdu, - 0x0au, 0x4cu, 0xd8u, 0xe7u, 0x0fu, 0x26u, 0x33u, 0x40u, 0x08u, 0x3bu, 0x06u, 0x4eu, 0x9bu, 0x08u, 0x9bu, 0x00u, - 0x9bu, 0x19u, 0xdeu, 0x69u, 0x32u, 0x40u, 0x11u, 0x43u, 0xd9u, 0x61u, 0xe7u, 0xe7u, 0x03u, 0x4cu, 0xedu, 0xe7u, - 0x00u, 0xe1u, 0x00u, 0xe0u, 0x00u, 0xedu, 0x00u, 0xe0u, 0x00u, 0x00u, 0x00u, 0x08u, 0x01u, 0x00u, 0x56u, 0x00u, - 0xfeu, 0xe7u, 0x00u, 0x00u, 0x02u, 0x68u, 0x0au, 0x4bu, 0x10u, 0xb5u, 0x1au, 0x60u, 0x42u, 0x68u, 0x5au, 0x60u, - 0x82u, 0x68u, 0x9au, 0x60u, 0xc2u, 0x68u, 0xdau, 0x60u, 0x02u, 0x69u, 0x1au, 0x61u, 0x42u, 0x69u, 0x5au, 0x61u, - 0x82u, 0x69u, 0x9au, 0x61u, 0xc2u, 0x69u, 0xdau, 0x61u, 0xffu, 0xf7u, 0xeau, 0xffu, 0x10u, 0xbdu, 0xc0u, 0x46u, - 0x90u, 0x03u, 0x00u, 0x08u, 0xb0u, 0x23u, 0x5bu, 0x05u, 0x9au, 0x89u, 0x00u, 0x2au, 0x02u, 0xd0u, 0x98u, 0x89u, - 0x80u, 0xb2u, 0x70u, 0x47u, 0x80u, 0x20u, 0x40u, 0x00u, 0xfbu, 0xe7u, 0x00u, 0x00u, 0x7fu, 0xb5u, 0x27u, 0x4bu, - 0x86u, 0x00u, 0x0du, 0x00u, 0xf4u, 0x58u, 0x04u, 0x29u, 0x01u, 0xd0u, 0x01u, 0x29u, 0x27u, 0xd1u, 0x00u, 0x20u, - 0x0fu, 0xe0u, 0xa3u, 0x68u, 0x2bu, 0x42u, 0x0bu, 0xd1u, 0xe3u, 0x68u, 0x29u, 0x00u, 0x1au, 0x68u, 0x5bu, 0x68u, - 0x02u, 0x92u, 0x01u, 0x93u, 0x03u, 0x93u, 0x02u, 0xa8u, 0x23u, 0x68u, 0x98u, 0x47u, 0x1cu, 0x4bu, 0x1cu, 0x60u, - 0x64u, 0x69u, 0x00u, 0x2cu, 0x0bu, 0xd0u, 0x1bu, 0x4bu, 0x98u, 0x42u, 0xeau, 0xd1u, 0x01u, 0x2du, 0xe8u, 0xd1u, - 0x17u, 0x4bu, 0x18u, 0x48u, 0x1au, 0x68u, 0x18u, 0x4bu, 0x9au, 0x51u, 0x04u, 0xb0u, 0x70u, 0xbdu, 0x01u, 0x2du, - 0xfbu, 0xd1u, 0x14u, 0x4bu, 0x98u, 0x42u, 0xf3u, 0xd0u, 0x13u, 0x4bu, 0x9cu, 0x51u, 0xf5u, 0xe7u, 0x02u, 0x29u, - 0x06u, 0xd1u, 0x0fu, 0x4bu, 0x1bu, 0x68u, 0x18u, 0x1eu, 0xefu, 0xd0u, 0x1cu, 0x69u, 0x03u, 0xe0u, 0x1cu, 0x00u, - 0x63u, 0x69u, 0x00u, 0x2bu, 0xfbu, 0xd1u, 0x00u, 0x20u, 0x00u, 0x2cu, 0xe6u, 0xd0u, 0xa3u, 0x68u, 0x2bu, 0x42u, - 0x09u, 0xd1u, 0xe3u, 0x68u, 0x29u, 0x00u, 0x1au, 0x68u, 0x5bu, 0x68u, 0x02u, 0x92u, 0x01u, 0x93u, 0x03u, 0x93u, - 0x02u, 0xa8u, 0x23u, 0x68u, 0x98u, 0x47u, 0x24u, 0x69u, 0xeeu, 0xe7u, 0xc0u, 0x46u, 0x48u, 0x04u, 0x00u, 0x08u, - 0x44u, 0x04u, 0x00u, 0x08u, 0xffu, 0x00u, 0x42u, 0x00u, 0x30u, 0x04u, 0x00u, 0x08u, 0x19u, 0x4bu, 0x1bu, 0x68u, - 0x19u, 0x00u, 0x04u, 0xc9u, 0xc9u, 0x6fu, 0x51u, 0x18u, 0x09u, 0x68u, 0x01u, 0x62u, 0x19u, 0x00u, 0x08u, 0x31u, - 0xc9u, 0x6fu, 0x52u, 0x18u, 0x12u, 0x68u, 0x42u, 0x62u, 0x1au, 0x00u, 0x41u, 0x32u, 0x12u, 0x78u, 0x00u, 0x2au, - 0x1fu, 0xd0u, 0x9au, 0x68u, 0xe0u, 0x32u, 0x12u, 0x68u, 0xd2u, 0x06u, 0x1au, 0xd5u, 0xf2u, 0x22u, 0xdbu, 0x68u, - 0xd2u, 0x01u, 0x9au, 0x58u, 0x02u, 0x60u, 0xf0u, 0x22u, 0xd2u, 0x01u, 0x9au, 0x58u, 0x42u, 0x60u, 0x0au, 0x4au, - 0x9au, 0x58u, 0x82u, 0x60u, 0x09u, 0x4au, 0x9au, 0x58u, 0xc2u, 0x60u, 0x09u, 0x4au, 0x9au, 0x58u, 0x02u, 0x61u, - 0x08u, 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0x68u, 0x1eu, 0x58u, + 0x15u, 0x68u, 0x01u, 0x95u, 0x10u, 0x4du, 0x0du, 0x60u, 0x06u, 0x25u, 0x1du, 0x50u, 0x3eu, 0x20u, 0x10u, 0x60u, + 0x0eu, 0x48u, 0x3eu, 0x35u, 0x1du, 0x50u, 0x1du, 0x58u, 0x00u, 0x2du, 0xfcu, 0xdau, 0x0cu, 0x48u, 0xfcu, 0x34u, + 0x20u, 0x61u, 0x0fu, 0x60u, 0xa3u, 0x21u, 0xc9u, 0x00u, 0x5eu, 0x50u, 0x01u, 0x9bu, 0x13u, 0x60u, 0xf7u, 0xbdu, + 0x20u, 0xbfu, 0xd9u, 0xe7u, 0xecu, 0x05u, 0x00u, 0x08u, 0x00u, 0xedu, 0x00u, 0xe0u, 0x00u, 0x00u, 0x26u, 0x40u, + 0x08u, 0x01u, 0x26u, 0x40u, 0x04u, 0x01u, 0x26u, 0x40u, 0x1eu, 0x1fu, 0x00u, 0x00u, 0x1cu, 0x05u, 0x00u, 0x00u, + 0xaau, 0xaau, 0xaau, 0xaau, 0x01u, 0xb4u, 0x02u, 0x48u, 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, + 0x41u, 0x5fu, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, + 0x05u, 0x60u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, + 0x69u, 0x60u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, + 0x31u, 0x63u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, + 0xdbu, 0x00u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, + 0xc5u, 0x6cu, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, + 0xe3u, 0x00u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, + 0xa5u, 0x63u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, + 0x75u, 0x61u, 0x00u, 0x10u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, }; #endif /* defined(CY_DEVICE_PSOC6A2M) */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/COMPONENT_CM0P_CRYPTO/psoc6_03_cm0p_crypto.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/COMPONENT_CM0P_CRYPTO/psoc6_03_cm0p_crypto.c index 271f571262..bb0aee5ff0 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/COMPONENT_CM0P_CRYPTO/psoc6_03_cm0p_crypto.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/COMPONENT_CM0P_CRYPTO/psoc6_03_cm0p_crypto.c @@ -36,35 +36,35 @@ const uint8_t cy_m0p_image[] = { 0x49u, 0x01u, 0x00u, 0x10u, 0x49u, 0x01u, 0x00u, 0x10u, 0x49u, 0x01u, 0x00u, 0x10u, 0x49u, 0x01u, 0x00u, 0x10u, 0x49u, 0x01u, 0x00u, 0x10u, 0x49u, 0x01u, 0x00u, 0x10u, 0x49u, 0x01u, 0x00u, 0x10u, 0x49u, 0x01u, 0x00u, 0x10u, 0x10u, 0xb5u, 0x06u, 0x4cu, 0x23u, 0x78u, 0x00u, 0x2bu, 0x07u, 0xd1u, 0x05u, 0x4bu, 0x00u, 0x2bu, 0x02u, 0xd0u, - 0x04u, 0x48u, 0x00u, 0xe0u, 0x00u, 0xbfu, 0x01u, 0x23u, 0x23u, 0x70u, 0x10u, 0xbdu, 0xb0u, 0x03u, 0x00u, 0x08u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x48u, 0x7eu, 0x00u, 0x10u, 0x04u, 0x4bu, 0x10u, 0xb5u, 0x00u, 0x2bu, 0x03u, 0xd0u, + 0x04u, 0x48u, 0x00u, 0xe0u, 0x00u, 0xbfu, 0x01u, 0x23u, 0x23u, 0x70u, 0x10u, 0xbdu, 0xc0u, 0x03u, 0x00u, 0x08u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x50u, 0x7eu, 0x00u, 0x10u, 0x04u, 0x4bu, 0x10u, 0xb5u, 0x00u, 0x2bu, 0x03u, 0xd0u, 0x03u, 0x49u, 0x04u, 0x48u, 0x00u, 0xe0u, 0x00u, 0xbfu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0x00u, 0x00u, 0x00u, 0x00u, - 0xb4u, 0x03u, 0x00u, 0x08u, 0x48u, 0x7eu, 0x00u, 0x10u, 0x02u, 0x30u, 0x80u, 0x08u, 0x03u, 0xd0u, 0x01u, 0x30u, + 0xc4u, 0x03u, 0x00u, 0x08u, 0x50u, 0x7eu, 0x00u, 0x10u, 0x02u, 0x30u, 0x80u, 0x08u, 0x03u, 0xd0u, 0x01u, 0x30u, 0x02u, 0x38u, 0xfcu, 0xd1u, 0xc0u, 0x46u, 0xc0u, 0x46u, 0x70u, 0x47u, 0xefu, 0xf3u, 0x10u, 0x80u, 0x72u, 0xb6u, 0x70u, 0x47u, 0x80u, 0xf3u, 0x10u, 0x88u, 0x70u, 0x47u, 0x70u, 0x47u, 0xffu, 0xf7u, 0xfdu, 0xffu, 0x72u, 0xb6u, 0x0fu, 0x4cu, 0x10u, 0x4du, 0xacu, 0x42u, 0x09u, 0xdau, 0x21u, 0x68u, 0x62u, 0x68u, 0xa3u, 0x68u, 0x04u, 0x3bu, 0x02u, 0xdbu, 0xc8u, 0x58u, 0xd0u, 0x50u, 0xfau, 0xe7u, 0x0cu, 0x34u, 0xf3u, 0xe7u, 0x0au, 0x49u, 0x0bu, 0x4au, 0x00u, 0x20u, 0x52u, 0x1au, 0x02u, 0xddu, 0x04u, 0x3au, 0x88u, 0x50u, 0xfcu, 0xdcu, 0x08u, 0x48u, 0x09u, 0x49u, - 0x08u, 0x60u, 0xbfu, 0xf3u, 0x4fu, 0x8fu, 0x06u, 0xf0u, 0x75u, 0xfdu, 0x06u, 0xf0u, 0x15u, 0xfdu, 0xfeu, 0xe7u, - 0x54u, 0x7eu, 0x00u, 0x10u, 0x6cu, 0x7eu, 0x00u, 0x10u, 0xb0u, 0x03u, 0x00u, 0x08u, 0x0cu, 0x06u, 0x00u, 0x08u, + 0x08u, 0x60u, 0xbfu, 0xf3u, 0x4fu, 0x8fu, 0x06u, 0xf0u, 0x79u, 0xfdu, 0x06u, 0xf0u, 0x19u, 0xfdu, 0xfeu, 0xe7u, + 0x5cu, 0x7eu, 0x00u, 0x10u, 0x74u, 0x7eu, 0x00u, 0x10u, 0xc0u, 0x03u, 0x00u, 0x08u, 0x1cu, 0x06u, 0x00u, 0x08u, 0x00u, 0x00u, 0x00u, 0x08u, 0x08u, 0xedu, 0x00u, 0xe0u, 0xfeu, 0xe7u, 0xfeu, 0xe7u, 0x00u, 0xb5u, 0x04u, 0x20u, 0x71u, 0x46u, 0x08u, 0x42u, 0x02u, 0xd0u, 0xefu, 0xf3u, 0x09u, 0x80u, 0x01u, 0xe0u, 0xefu, 0xf3u, 0x08u, 0x80u, - 0x04u, 0x30u, 0x06u, 0xf0u, 0x07u, 0xfbu, 0xfeu, 0xe7u, 0xf7u, 0xb5u, 0x03u, 0x27u, 0x11u, 0x4eu, 0x14u, 0x00u, + 0x04u, 0x30u, 0x06u, 0xf0u, 0x0bu, 0xfbu, 0xfeu, 0xe7u, 0xf7u, 0xb5u, 0x03u, 0x27u, 0x11u, 0x4eu, 0x14u, 0x00u, 0x32u, 0x68u, 0x05u, 0x00u, 0x52u, 0x69u, 0x82u, 0x18u, 0x08u, 0x78u, 0x49u, 0x68u, 0x38u, 0x40u, 0x10u, 0x60u, 0x01u, 0x2cu, 0x00u, 0xd1u, 0x20u, 0x31u, 0x28u, 0x00u, 0x08u, 0x9au, 0x01u, 0x3cu, 0x03u, 0xf0u, 0x72u, 0xfdu, 0x0cu, 0x23u, 0x61u, 0x42u, 0x61u, 0x41u, 0x00u, 0x93u, 0x28u, 0x00u, 0x08u, 0x3bu, 0x44u, 0x31u, 0x00u, 0x22u, 0x03u, 0xf0u, 0xd0u, 0xfdu, 0x33u, 0x68u, 0x1bu, 0x68u, 0xedu, 0x18u, 0x01u, 0x23u, 0x2au, 0x68u, 0x1au, 0x42u, - 0xfcu, 0xd1u, 0xf7u, 0xbdu, 0xd0u, 0x03u, 0x00u, 0x08u, 0x73u, 0xb5u, 0x04u, 0x00u, 0x08u, 0x00u, 0x03u, 0x26u, + 0xfcu, 0xd1u, 0xf7u, 0xbdu, 0xe0u, 0x03u, 0x00u, 0x08u, 0x73u, 0xb5u, 0x04u, 0x00u, 0x08u, 0x00u, 0x03u, 0x26u, 0x0eu, 0x4du, 0x19u, 0x00u, 0x2bu, 0x68u, 0x00u, 0x78u, 0x5bu, 0x69u, 0x30u, 0x40u, 0xe3u, 0x18u, 0x18u, 0x60u, 0x13u, 0x00u, 0x20u, 0x00u, 0x06u, 0x9au, 0x03u, 0xf0u, 0x4du, 0xfdu, 0x08u, 0x23u, 0x20u, 0x00u, 0x00u, 0x93u, 0x00u, 0x22u, 0x04u, 0x3bu, 0x48u, 0x21u, 0x03u, 0xf0u, 0xadu, 0xfdu, 0x2bu, 0x68u, 0x1bu, 0x68u, 0xe4u, 0x18u, - 0x01u, 0x23u, 0x22u, 0x68u, 0x1au, 0x42u, 0xfcu, 0xd1u, 0x73u, 0xbdu, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, + 0x01u, 0x23u, 0x22u, 0x68u, 0x1au, 0x42u, 0xfcu, 0xd1u, 0x73u, 0xbdu, 0xc0u, 0x46u, 0xe0u, 0x03u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x1du, 0x00u, 0x1au, 0x70u, 0x04u, 0x9bu, 0x02u, 0x32u, 0x6bu, 0x60u, 0xd3u, 0x00u, 0x0au, 0x00u, 0x04u, 0x99u, 0x04u, 0x00u, 0x03u, 0xf0u, 0xceu, 0xfdu, 0x03u, 0x21u, 0x0du, 0x4eu, 0x2au, 0x78u, 0x33u, 0x68u, 0x0au, 0x40u, 0x5bu, 0x69u, 0x69u, 0x68u, 0xe3u, 0x18u, 0x1au, 0x60u, 0x0au, 0x00u, 0x20u, 0x00u, 0x20u, 0x32u, 0x03u, 0xf0u, 0x06u, 0xfdu, 0x08u, 0x23u, 0x20u, 0x00u, 0x00u, 0x22u, 0x46u, 0x21u, 0x03u, 0xf0u, 0x6cu, 0xfdu, 0x33u, 0x68u, 0x1bu, 0x68u, 0xe4u, 0x18u, 0x01u, 0x23u, 0x20u, 0x68u, 0x18u, 0x40u, 0xfcu, 0xd1u, 0x70u, 0xbdu, - 0xd0u, 0x03u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x85u, 0xb0u, 0x16u, 0x00u, 0x1au, 0x00u, 0x0au, 0x9bu, 0x05u, 0x00u, + 0xe0u, 0x03u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x85u, 0xb0u, 0x16u, 0x00u, 0x1au, 0x00u, 0x0au, 0x9bu, 0x05u, 0x00u, 0x5cu, 0x68u, 0x03u, 0x91u, 0x27u, 0x00u, 0x40u, 0x37u, 0x39u, 0x00u, 0x50u, 0x34u, 0x10u, 0x23u, 0x03u, 0xf0u, 0xa1u, 0xfdu, 0x23u, 0x00u, 0x03u, 0x9au, 0x0au, 0x99u, 0x28u, 0x00u, 0x00u, 0x97u, 0xffu, 0xf7u, 0x74u, 0xffu, 0x28u, 0x00u, 0x10u, 0x23u, 0x22u, 0x00u, 0x31u, 0x00u, 0x03u, 0xf0u, 0x94u, 0xfdu, 0x00u, 0x20u, 0x05u, 0xb0u, @@ -95,7 +95,7 @@ const uint8_t cy_m0p_image[] = { 0xd3u, 0xfeu, 0x10u, 0x23u, 0x2au, 0x00u, 0x07u, 0x99u, 0x30u, 0x00u, 0x03u, 0xf0u, 0xcbu, 0xfcu, 0x10u, 0x3cu, 0xcfu, 0xe7u, 0x01u, 0x48u, 0xdfu, 0xe7u, 0xc0u, 0x46u, 0x02u, 0x00u, 0x32u, 0x00u, 0xf0u, 0xb5u, 0x91u, 0xb0u, 0x19u, 0x9du, 0x04u, 0x00u, 0x06u, 0x91u, 0x0bu, 0x92u, 0x00u, 0x21u, 0x10u, 0x22u, 0x0cu, 0xa8u, 0x07u, 0x93u, - 0x06u, 0xf0u, 0x6fu, 0xfeu, 0x6bu, 0x68u, 0x0cu, 0xa9u, 0x1au, 0x00u, 0x40u, 0x32u, 0x03u, 0x92u, 0x60u, 0x33u, + 0x06u, 0xf0u, 0x73u, 0xfeu, 0x6bu, 0x68u, 0x0cu, 0xa9u, 0x1au, 0x00u, 0x40u, 0x32u, 0x03u, 0x92u, 0x60u, 0x33u, 0x10u, 0x32u, 0x04u, 0x92u, 0x05u, 0x93u, 0x07u, 0x9au, 0x10u, 0x23u, 0x20u, 0x00u, 0x03u, 0xf0u, 0xaau, 0xfcu, 0x0fu, 0x9bu, 0x1bu, 0xbau, 0x08u, 0x93u, 0x06u, 0x9bu, 0x08u, 0x9eu, 0x1bu, 0x09u, 0x0au, 0x93u, 0x0eu, 0x9bu, 0x1fu, 0xbau, 0x08u, 0x9bu, 0x17u, 0x99u, 0xf3u, 0x1au, 0x1au, 0x01u, 0x89u, 0x18u, 0x09u, 0x91u, 0x18u, 0x99u, @@ -107,32 +107,32 @@ const uint8_t cy_m0p_image[] = { 0x0eu, 0x92u, 0x00u, 0x93u, 0x04u, 0x9au, 0x03u, 0x9bu, 0x29u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x6cu, 0xfeu, 0x10u, 0x23u, 0x04u, 0x9au, 0x09u, 0x99u, 0x20u, 0x00u, 0x03u, 0xf0u, 0x64u, 0xfcu, 0xc1u, 0xe7u, 0x00u, 0x00u, 0x03u, 0x4bu, 0x1bu, 0x68u, 0x9bu, 0x68u, 0xc0u, 0x18u, 0x0fu, 0x23u, 0x00u, 0x68u, 0x18u, 0x40u, 0x70u, 0x47u, - 0xd0u, 0x03u, 0x00u, 0x08u, 0x03u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xc0u, 0x18u, 0x03u, 0x68u, 0x00u, 0x2bu, - 0xfcu, 0xd1u, 0x70u, 0x47u, 0xd0u, 0x03u, 0x00u, 0x08u, 0xf8u, 0xb5u, 0x04u, 0x00u, 0x0du, 0x00u, 0x17u, 0x00u, + 0xe0u, 0x03u, 0x00u, 0x08u, 0x03u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xc0u, 0x18u, 0x03u, 0x68u, 0x00u, 0x2bu, + 0xfcu, 0xd1u, 0x70u, 0x47u, 0xe0u, 0x03u, 0x00u, 0x08u, 0xf8u, 0xb5u, 0x04u, 0x00u, 0x0du, 0x00u, 0x17u, 0x00u, 0x1eu, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xe4u, 0xffu, 0x04u, 0x28u, 0xfau, 0xd8u, 0x08u, 0x2du, 0x04u, 0xd0u, 0x0cu, 0x4au, 0xa3u, 0x58u, 0x00u, 0x2bu, 0xfcu, 0xdbu, 0x04u, 0xe0u, 0x86u, 0x22u, 0x52u, 0x01u, 0xa3u, 0x58u, 0x00u, 0x2bu, 0xfcu, 0xdbu, 0xe2u, 0x21u, 0x08u, 0x4bu, 0xc9u, 0x05u, 0x1bu, 0x68u, 0x0du, 0x43u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x15u, 0x60u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x17u, 0x60u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0x26u, 0x60u, - 0xf8u, 0xbdu, 0xc0u, 0x46u, 0xd0u, 0x10u, 0x00u, 0x00u, 0xd0u, 0x03u, 0x00u, 0x08u, 0xf8u, 0xb5u, 0x07u, 0x00u, + 0xf8u, 0xbdu, 0xc0u, 0x46u, 0xd0u, 0x10u, 0x00u, 0x00u, 0xe0u, 0x03u, 0x00u, 0x08u, 0xf8u, 0xb5u, 0x07u, 0x00u, 0x0cu, 0x00u, 0x16u, 0x00u, 0x1du, 0x00u, 0x38u, 0x00u, 0xffu, 0xf7u, 0xbau, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x06u, 0x4bu, 0x24u, 0x03u, 0x1bu, 0x68u, 0x2du, 0x04u, 0xd8u, 0x68u, 0x80u, 0x23u, 0xdbu, 0x05u, 0x1eu, 0x43u, - 0x34u, 0x43u, 0x38u, 0x18u, 0x2cu, 0x43u, 0x04u, 0x60u, 0xf8u, 0xbdu, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, + 0x34u, 0x43u, 0x38u, 0x18u, 0x2cu, 0x43u, 0x04u, 0x60u, 0xf8u, 0xbdu, 0xc0u, 0x46u, 0xe0u, 0x03u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x05u, 0x00u, 0x0cu, 0x00u, 0x16u, 0x00u, 0x28u, 0x00u, 0xffu, 0xf7u, 0xa1u, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x05u, 0x4bu, 0x24u, 0x02u, 0x1bu, 0x68u, 0xdbu, 0x68u, 0xedu, 0x18u, 0xd0u, 0x23u, 0xdbu, 0x05u, - 0x1eu, 0x43u, 0x34u, 0x43u, 0x2cu, 0x60u, 0x70u, 0xbdu, 0xd0u, 0x03u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, + 0x1eu, 0x43u, 0x34u, 0x43u, 0x2cu, 0x60u, 0x70u, 0xbdu, 0xe0u, 0x03u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x8du, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x04u, 0x4bu, 0x1bu, 0x68u, 0xdbu, 0x68u, - 0xe4u, 0x18u, 0xa0u, 0x23u, 0xdbu, 0x05u, 0x23u, 0x60u, 0x10u, 0xbdu, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, + 0xe4u, 0x18u, 0xa0u, 0x23u, 0xdbu, 0x05u, 0x23u, 0x60u, 0x10u, 0xbdu, 0xc0u, 0x46u, 0xe0u, 0x03u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x7bu, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x04u, 0x4bu, 0x1bu, 0x68u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0xa2u, 0x23u, 0xdbu, 0x05u, 0x23u, 0x60u, 0x10u, 0xbdu, 0xc0u, 0x46u, - 0xd0u, 0x03u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x04u, 0x00u, 0x0eu, 0x00u, 0x15u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, + 0xe0u, 0x03u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x04u, 0x00u, 0x0eu, 0x00u, 0x15u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x67u, 0xffu, 0x04u, 0x28u, 0xfau, 0xd8u, 0x06u, 0x4bu, 0x06u, 0x49u, 0x1bu, 0x68u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x11u, 0x60u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x16u, 0x60u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0x25u, 0x60u, 0x70u, 0xbdu, - 0xd0u, 0x03u, 0x00u, 0x08u, 0x0cu, 0x00u, 0x00u, 0x70u, 0x70u, 0xb5u, 0x05u, 0x00u, 0x0cu, 0x78u, 0x4au, 0x68u, + 0xe0u, 0x03u, 0x00u, 0x08u, 0x0cu, 0x00u, 0x00u, 0x70u, 0x70u, 0xb5u, 0x05u, 0x00u, 0x0cu, 0x78u, 0x4au, 0x68u, 0x02u, 0x34u, 0xe4u, 0x00u, 0x23u, 0x00u, 0x0eu, 0x00u, 0x08u, 0x21u, 0xffu, 0xf7u, 0x5du, 0xffu, 0x10u, 0x23u, 0x08u, 0x22u, 0x04u, 0x21u, 0x28u, 0x00u, 0xffu, 0xf7u, 0x81u, 0xffu, 0x23u, 0x00u, 0x10u, 0x3bu, 0x00u, 0x2bu, 0x04u, 0xd0u, 0x08u, 0x22u, 0x05u, 0x21u, 0x28u, 0x00u, 0xffu, 0xf7u, 0x78u, 0xffu, 0x03u, 0x21u, 0x05u, 0x4bu, 0x32u, 0x78u, 0x1bu, 0x68u, 0x0au, 0x40u, 0x5bu, 0x69u, 0x28u, 0x00u, 0xebu, 0x18u, 0x1au, 0x60u, 0xffu, 0xf7u, - 0x39u, 0xffu, 0x70u, 0xbdu, 0xd0u, 0x03u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x05u, 0x00u, 0x0bu, 0x78u, 0x02u, 0x33u, + 0x39u, 0xffu, 0x70u, 0xbdu, 0xe0u, 0x03u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x05u, 0x00u, 0x0bu, 0x78u, 0x02u, 0x33u, 0xdcu, 0x00u, 0xffu, 0xf7u, 0xd1u, 0xffu, 0x28u, 0x00u, 0xffu, 0xf7u, 0x90u, 0xffu, 0x10u, 0x23u, 0x06u, 0x22u, 0x04u, 0x21u, 0x28u, 0x00u, 0xffu, 0xf7u, 0x5au, 0xffu, 0x23u, 0x00u, 0x10u, 0x3bu, 0x00u, 0x2bu, 0x04u, 0xd0u, 0x07u, 0x22u, 0x05u, 0x21u, 0x28u, 0x00u, 0xffu, 0xf7u, 0x51u, 0xffu, 0x28u, 0x00u, 0xffu, 0xf7u, 0x1au, 0xffu, @@ -160,7 +160,7 @@ const uint8_t cy_m0p_image[] = { 0x00u, 0x21u, 0xffu, 0xf7u, 0xa3u, 0xfeu, 0x20u, 0x00u, 0xffu, 0xf7u, 0xe2u, 0xfeu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x5fu, 0xfeu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x08u, 0x4bu, 0x09u, 0x4au, 0x1bu, 0x68u, 0x02u, 0x21u, 0xdbu, 0x68u, 0x20u, 0x00u, 0xe3u, 0x18u, 0x1au, 0x60u, 0x10u, 0x23u, 0x00u, 0x22u, 0xffu, 0xf7u, 0x8fu, 0xfeu, 0x10u, 0x3du, - 0xdfu, 0xe7u, 0x04u, 0x48u, 0xbfu, 0xe7u, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, 0x18u, 0x00u, 0x10u, 0x41u, + 0xdfu, 0xe7u, 0x04u, 0x48u, 0xbfu, 0xe7u, 0xc0u, 0x46u, 0xe0u, 0x03u, 0x00u, 0x08u, 0x18u, 0x00u, 0x10u, 0x41u, 0x21u, 0xc0u, 0x10u, 0x41u, 0x02u, 0x00u, 0x32u, 0x00u, 0xf7u, 0xb5u, 0x0fu, 0x26u, 0x04u, 0x00u, 0x01u, 0x91u, 0x15u, 0x00u, 0x1fu, 0x00u, 0x16u, 0x40u, 0x5eu, 0xd1u, 0x0au, 0x99u, 0xffu, 0xf7u, 0xe5u, 0xfeu, 0x10u, 0x23u, 0x3au, 0x00u, 0x09u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x47u, 0xfeu, 0x10u, 0x23u, 0x09u, 0x22u, 0x31u, 0x00u, @@ -174,7 +174,7 @@ const uint8_t cy_m0p_image[] = { 0x1au, 0x60u, 0x10u, 0x23u, 0x00u, 0x22u, 0xffu, 0xf7u, 0x31u, 0xfeu, 0x10u, 0x3du, 0x00u, 0x2du, 0xe8u, 0xd1u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xf7u, 0xfdu, 0x10u, 0x22u, 0x39u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x7au, 0xfeu, 0x10u, 0x23u, 0x00u, 0x22u, 0x0cu, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x20u, 0xfeu, 0x20u, 0x00u, 0xffu, 0xf7u, - 0xe9u, 0xfdu, 0x00u, 0x20u, 0xfeu, 0xbdu, 0x04u, 0x48u, 0xfcu, 0xe7u, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, + 0xe9u, 0xfdu, 0x00u, 0x20u, 0xfeu, 0xbdu, 0x04u, 0x48u, 0xfcu, 0xe7u, 0xc0u, 0x46u, 0xe0u, 0x03u, 0x00u, 0x08u, 0x01u, 0xc0u, 0x10u, 0x41u, 0x18u, 0x00u, 0x10u, 0x41u, 0x02u, 0x00u, 0x32u, 0x00u, 0xf0u, 0xb5u, 0x1du, 0x00u, 0x8bu, 0xb0u, 0x04u, 0x92u, 0x6au, 0x78u, 0x1bu, 0x78u, 0x12u, 0x02u, 0x1au, 0x43u, 0xabu, 0x78u, 0x04u, 0x00u, 0x1bu, 0x04u, 0x1au, 0x43u, 0xebu, 0x78u, 0x2eu, 0x7au, 0x1bu, 0x06u, 0x13u, 0x43u, 0x6au, 0x79u, 0x06u, 0x93u, @@ -199,7 +199,7 @@ const uint8_t cy_m0p_image[] = { 0xf2u, 0xb2u, 0x0fu, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x83u, 0xfdu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x28u, 0xfdu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x08u, 0x4bu, 0x09u, 0x4au, 0x1bu, 0x68u, 0xdbu, 0x68u, 0xe3u, 0x18u, 0x1au, 0x60u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x1du, 0xfdu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x03u, 0x4bu, 0x04u, 0x4au, 0x1bu, 0x68u, - 0xdbu, 0x68u, 0xe3u, 0x18u, 0x1au, 0x60u, 0xb3u, 0xe7u, 0xd0u, 0x03u, 0x00u, 0x08u, 0x10u, 0x10u, 0x00u, 0x66u, + 0xdbu, 0x68u, 0xe3u, 0x18u, 0x1au, 0x60u, 0xb3u, 0xe7u, 0xe0u, 0x03u, 0x00u, 0x08u, 0x10u, 0x10u, 0x00u, 0x66u, 0x10u, 0x10u, 0x00u, 0x67u, 0x02u, 0x00u, 0x00u, 0x23u, 0x10u, 0xb5u, 0x0fu, 0x32u, 0x44u, 0x1eu, 0x11u, 0x78u, 0x01u, 0x3au, 0x49u, 0x00u, 0x0bu, 0x43u, 0x53u, 0x70u, 0x1bu, 0x0au, 0x94u, 0x42u, 0xf7u, 0xd1u, 0x00u, 0x2bu, 0x04u, 0xd0u, 0x79u, 0x23u, 0xc2u, 0x7bu, 0x5bu, 0x42u, 0x53u, 0x40u, 0xc3u, 0x73u, 0x10u, 0xbdu, 0xf7u, 0xb5u, @@ -226,34 +226,34 @@ const uint8_t cy_m0p_image[] = { 0xa0u, 0x36u, 0x80u, 0x33u, 0x33u, 0x60u, 0x03u, 0x9bu, 0x90u, 0x34u, 0x73u, 0x60u, 0x32u, 0x00u, 0x0cu, 0x99u, 0x28u, 0x00u, 0xb4u, 0x60u, 0xffu, 0xf7u, 0x53u, 0xffu, 0x02u, 0x9bu, 0x32u, 0x00u, 0x0cu, 0x99u, 0x28u, 0x00u, 0x00u, 0x97u, 0xffu, 0xf7u, 0x61u, 0xffu, 0x28u, 0x00u, 0x0bu, 0x9bu, 0x32u, 0x00u, 0x0cu, 0x99u, 0xffu, 0xf7u, - 0x8du, 0xffu, 0x00u, 0x20u, 0x05u, 0xb0u, 0xf0u, 0xbdu, 0xd0u, 0x03u, 0x00u, 0x08u, 0x03u, 0x4bu, 0x1bu, 0x68u, - 0x9bu, 0x68u, 0xc0u, 0x18u, 0x0fu, 0x23u, 0x00u, 0x68u, 0x18u, 0x40u, 0x70u, 0x47u, 0xd0u, 0x03u, 0x00u, 0x08u, + 0x8du, 0xffu, 0x00u, 0x20u, 0x05u, 0xb0u, 0xf0u, 0xbdu, 0xe0u, 0x03u, 0x00u, 0x08u, 0x03u, 0x4bu, 0x1bu, 0x68u, + 0x9bu, 0x68u, 0xc0u, 0x18u, 0x0fu, 0x23u, 0x00u, 0x68u, 0x18u, 0x40u, 0x70u, 0x47u, 0xe0u, 0x03u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xf1u, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x04u, 0x4bu, 0x1bu, 0x68u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0xa0u, 0x23u, 0xdbu, 0x05u, 0x23u, 0x60u, 0x10u, 0xbdu, 0xc0u, 0x46u, - 0xd0u, 0x03u, 0x00u, 0x08u, 0x02u, 0x00u, 0x00u, 0x23u, 0x10u, 0xb5u, 0x0fu, 0x32u, 0x44u, 0x1eu, 0x11u, 0x78u, + 0xe0u, 0x03u, 0x00u, 0x08u, 0x02u, 0x00u, 0x00u, 0x23u, 0x10u, 0xb5u, 0x0fu, 0x32u, 0x44u, 0x1eu, 0x11u, 0x78u, 0x01u, 0x3au, 0x49u, 0x00u, 0x0bu, 0x43u, 0x53u, 0x70u, 0x1bu, 0x0au, 0x94u, 0x42u, 0xf7u, 0xd1u, 0x00u, 0x2bu, 0x04u, 0xd0u, 0x79u, 0x23u, 0xc2u, 0x7bu, 0x5bu, 0x42u, 0x53u, 0x40u, 0xc3u, 0x73u, 0x10u, 0xbdu, 0x00u, 0x00u, 0x70u, 0xb5u, 0x04u, 0x00u, 0x0eu, 0x00u, 0x15u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xc7u, 0xffu, 0x04u, 0x28u, 0xfau, 0xd8u, 0x86u, 0x22u, 0x52u, 0x01u, 0xa3u, 0x58u, 0x00u, 0x2bu, 0xfcu, 0xdbu, 0x06u, 0x4bu, 0x07u, 0x49u, 0x1bu, 0x68u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x11u, 0x60u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x16u, 0x60u, 0xdbu, 0x68u, - 0xe4u, 0x18u, 0x25u, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, 0x08u, 0x00u, 0x00u, 0x71u, + 0xe4u, 0x18u, 0x25u, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u, 0xe0u, 0x03u, 0x00u, 0x08u, 0x08u, 0x00u, 0x00u, 0x71u, 0x70u, 0xb5u, 0x04u, 0x00u, 0x0du, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa8u, 0xffu, 0x04u, 0x28u, 0xfau, 0xd8u, 0x06u, 0x4bu, 0x07u, 0x49u, 0x1bu, 0x68u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x11u, 0x60u, 0xdau, 0x68u, 0xa2u, 0x18u, - 0x15u, 0x60u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0x10u, 0x23u, 0x23u, 0x60u, 0x70u, 0xbdu, 0xd0u, 0x03u, 0x00u, 0x08u, + 0x15u, 0x60u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0x10u, 0x23u, 0x23u, 0x60u, 0x70u, 0xbdu, 0xe0u, 0x03u, 0x00u, 0x08u, 0x0cu, 0x00u, 0x00u, 0x70u, 0x00u, 0x23u, 0x70u, 0xb5u, 0x04u, 0x00u, 0x0eu, 0x00u, 0x0bu, 0x60u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x8cu, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x14u, 0x4du, 0x15u, 0x4au, 0x2bu, 0x68u, 0x20u, 0x00u, 0xdbu, 0x68u, 0xe3u, 0x18u, 0x1au, 0x60u, 0xffu, 0xf7u, 0x8bu, 0xffu, 0x71u, 0x68u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xcfu, 0xffu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x7au, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x2au, 0x68u, 0x0du, 0x49u, 0xd3u, 0x68u, 0xe3u, 0x18u, 0x19u, 0x60u, 0x13u, 0x68u, 0xe3u, 0x18u, 0x1au, 0x68u, 0x00u, 0x2au, 0xfcu, 0xd1u, 0x70u, 0x68u, 0xffu, 0xf7u, 0x87u, 0xffu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x68u, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, - 0x2bu, 0x68u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0x04u, 0x4bu, 0x23u, 0x60u, 0x70u, 0xbdu, 0xd0u, 0x03u, 0x00u, 0x08u, + 0x2bu, 0x68u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0x04u, 0x4bu, 0x23u, 0x60u, 0x70u, 0xbdu, 0xe0u, 0x03u, 0x00u, 0x08u, 0x00u, 0x00u, 0x10u, 0x41u, 0x01u, 0xc0u, 0x10u, 0x40u, 0x11u, 0x10u, 0x10u, 0x41u, 0x70u, 0xb5u, 0x0eu, 0x00u, 0x11u, 0x00u, 0x32u, 0x68u, 0x05u, 0x00u, 0x9cu, 0x18u, 0x1au, 0x00u, 0xffu, 0xf7u, 0x81u, 0xffu, 0x10u, 0x2cu, 0x01u, 0xd8u, 0x34u, 0x60u, 0x70u, 0xbdu, 0x28u, 0x00u, 0xffu, 0xf7u, 0x48u, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x05u, 0x4bu, 0x06u, 0x4au, 0x1bu, 0x68u, 0x28u, 0x00u, 0xdbu, 0x68u, 0x10u, 0x3cu, 0xebu, 0x18u, 0x1au, 0x60u, - 0xffu, 0xf7u, 0x46u, 0xffu, 0xebu, 0xe7u, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, 0x18u, 0x00u, 0x10u, 0x41u, + 0xffu, 0xf7u, 0x46u, 0xffu, 0xebu, 0xe7u, 0xc0u, 0x46u, 0xe0u, 0x03u, 0x00u, 0x08u, 0x18u, 0x00u, 0x10u, 0x41u, 0xf0u, 0xb5u, 0x10u, 0x25u, 0x87u, 0xb0u, 0x0fu, 0x00u, 0x04u, 0x00u, 0x01u, 0x92u, 0x00u, 0x21u, 0x2au, 0x00u, - 0x02u, 0xa8u, 0x06u, 0xf0u, 0x7eu, 0xf9u, 0x80u, 0x23u, 0x7eu, 0x68u, 0x3fu, 0x68u, 0x02u, 0xaau, 0x13u, 0x70u, + 0x02u, 0xa8u, 0x06u, 0xf0u, 0x82u, 0xf9u, 0x80u, 0x23u, 0x7eu, 0x68u, 0x3fu, 0x68u, 0x02u, 0xaau, 0x13u, 0x70u, 0x02u, 0xa9u, 0xeau, 0x1bu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x53u, 0xffu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x1eu, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x18u, 0x4du, 0x19u, 0x4au, 0x2bu, 0x68u, 0xdbu, 0x68u, 0xe3u, 0x18u, 0x1au, 0x60u, 0x0fu, 0x2fu, 0x02u, 0xd8u, 0x30u, 0x00u, 0xffu, 0xf7u, 0x2du, 0xffu, 0x10u, 0x22u, 0x31u, 0x00u, 0x20u, 0x00u, @@ -261,10 +261,10 @@ const uint8_t cy_m0p_image[] = { 0x0fu, 0x4au, 0xdbu, 0x68u, 0x20u, 0x00u, 0xe3u, 0x18u, 0x1au, 0x60u, 0xffu, 0xf7u, 0x09u, 0xffu, 0x01u, 0x99u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x4du, 0xffu, 0x20u, 0x00u, 0xffu, 0xf7u, 0xf8u, 0xfeu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x2au, 0x68u, 0x08u, 0x49u, 0xd3u, 0x68u, 0xe3u, 0x18u, 0x19u, 0x60u, 0x13u, 0x68u, 0xe4u, 0x18u, 0x23u, 0x68u, - 0x00u, 0x2bu, 0xfcu, 0xd1u, 0x07u, 0xb0u, 0xf0u, 0xbdu, 0xd0u, 0x03u, 0x00u, 0x08u, 0x18u, 0x00u, 0x10u, 0x41u, + 0x00u, 0x2bu, 0xfcu, 0xd1u, 0x07u, 0xb0u, 0xf0u, 0xbdu, 0xe0u, 0x03u, 0x00u, 0x08u, 0x18u, 0x00u, 0x10u, 0x41u, 0x08u, 0x00u, 0x10u, 0x41u, 0x01u, 0xc0u, 0x10u, 0x40u, 0xf0u, 0xb5u, 0x04u, 0x00u, 0x1eu, 0x00u, 0xa7u, 0xb0u, 0x2cu, 0xabu, 0x0au, 0xadu, 0x1fu, 0x78u, 0x02u, 0x91u, 0x03u, 0x92u, 0x00u, 0x21u, 0x70u, 0x22u, 0x28u, 0x00u, - 0x06u, 0xf0u, 0x27u, 0xf9u, 0x18u, 0x22u, 0x00u, 0x21u, 0x04u, 0xa8u, 0x06u, 0xf0u, 0x22u, 0xf9u, 0x3au, 0x00u, + 0x06u, 0xf0u, 0x2bu, 0xf9u, 0x18u, 0x22u, 0x00u, 0x21u, 0x04u, 0xa8u, 0x06u, 0xf0u, 0x26u, 0xf9u, 0x3au, 0x00u, 0x2eu, 0x9bu, 0x31u, 0x00u, 0x00u, 0x95u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xf3u, 0xfbu, 0x2eu, 0x99u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xaau, 0xfbu, 0x06u, 0xabu, 0x04u, 0xa9u, 0x20u, 0x00u, 0x05u, 0x93u, 0xffu, 0xf7u, 0x2au, 0xffu, 0x03u, 0x9bu, 0x02u, 0x9au, 0x04u, 0xa9u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x60u, 0xffu, 0x20u, 0x00u, 0x2du, 0x9au, @@ -272,30 +272,30 @@ const uint8_t cy_m0p_image[] = { 0x0cu, 0x4cu, 0x7fu, 0x00u, 0x25u, 0x68u, 0xdbu, 0xb2u, 0x2cu, 0x6au, 0x06u, 0x19u, 0x05u, 0x9cu, 0x24u, 0x02u, 0x3cu, 0x40u, 0xffu, 0x3fu, 0x3au, 0x40u, 0x22u, 0x43u, 0x32u, 0x60u, 0x6au, 0x6au, 0x82u, 0x18u, 0x13u, 0x60u, 0xabu, 0x6au, 0xc3u, 0x18u, 0x19u, 0x60u, 0xebu, 0x6au, 0xc0u, 0x18u, 0x06u, 0x9bu, 0x03u, 0x60u, 0x00u, 0x20u, - 0xf0u, 0xbdu, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x0du, 0x00u, 0x11u, 0x00u, 0x86u, 0x22u, + 0xf0u, 0xbdu, 0xc0u, 0x46u, 0xe0u, 0x03u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x0du, 0x00u, 0x11u, 0x00u, 0x86u, 0x22u, 0x04u, 0x00u, 0x04u, 0x98u, 0xd2u, 0x00u, 0xa0u, 0x50u, 0x1au, 0x00u, 0x20u, 0x00u, 0x02u, 0xf0u, 0x68u, 0xfeu, 0x04u, 0x23u, 0x00u, 0x22u, 0x58u, 0x21u, 0x20u, 0x00u, 0x02u, 0xf0u, 0xceu, 0xfeu, 0x08u, 0x21u, 0x06u, 0x4bu, 0x1au, 0x68u, 0x13u, 0x68u, 0xe3u, 0x18u, 0x18u, 0x68u, 0x08u, 0x40u, 0xfcu, 0xd1u, 0x13u, 0x6bu, 0xe4u, 0x18u, - 0x23u, 0x68u, 0x2bu, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, 0x03u, 0x4bu, 0x1bu, 0x68u, - 0x1bu, 0x68u, 0xc0u, 0x18u, 0x03u, 0x68u, 0x00u, 0x2bu, 0xfcu, 0xd1u, 0x70u, 0x47u, 0xd0u, 0x03u, 0x00u, 0x08u, + 0x23u, 0x68u, 0x2bu, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u, 0xe0u, 0x03u, 0x00u, 0x08u, 0x03u, 0x4bu, 0x1bu, 0x68u, + 0x1bu, 0x68u, 0xc0u, 0x18u, 0x03u, 0x68u, 0x00u, 0x2bu, 0xfcu, 0xd1u, 0x70u, 0x47u, 0xe0u, 0x03u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x0fu, 0x26u, 0x09u, 0x4bu, 0x1bu, 0x68u, 0x9cu, 0x68u, 0x05u, 0x19u, 0x2cu, 0x68u, 0x34u, 0x40u, 0x04u, 0x2cu, 0xfbu, 0xd8u, 0xdcu, 0x68u, 0x06u, 0x4du, 0x04u, 0x19u, 0x25u, 0x60u, 0xdcu, 0x68u, 0x04u, 0x19u, - 0x21u, 0x60u, 0xdbu, 0x68u, 0xc0u, 0x18u, 0x02u, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, + 0x21u, 0x60u, 0xdbu, 0x68u, 0xc0u, 0x18u, 0x02u, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u, 0xe0u, 0x03u, 0x00u, 0x08u, 0x08u, 0x00u, 0x00u, 0x70u, 0x10u, 0xb5u, 0x0fu, 0x24u, 0x06u, 0x4bu, 0x19u, 0x68u, 0x8bu, 0x68u, 0xc2u, 0x18u, 0x13u, 0x68u, 0x23u, 0x40u, 0x06u, 0x2bu, 0xfbu, 0xd8u, 0xcbu, 0x68u, 0xc0u, 0x18u, 0xb0u, 0x23u, 0xdbu, 0x05u, - 0x03u, 0x60u, 0x10u, 0xbdu, 0xd0u, 0x03u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x80u, 0x27u, 0x0cu, 0x4cu, 0x7fu, 0x00u, + 0x03u, 0x60u, 0x10u, 0xbdu, 0xe0u, 0x03u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x80u, 0x27u, 0x0cu, 0x4cu, 0x7fu, 0x00u, 0x25u, 0x68u, 0xdbu, 0xb2u, 0x2cu, 0x6au, 0x06u, 0x19u, 0x05u, 0x9cu, 0x24u, 0x02u, 0x3cu, 0x40u, 0xffu, 0x3fu, 0x3au, 0x40u, 0x22u, 0x43u, 0x32u, 0x60u, 0x6au, 0x6au, 0x82u, 0x18u, 0x13u, 0x60u, 0xabu, 0x6au, 0xc3u, 0x18u, 0x19u, 0x60u, 0xebu, 0x6au, 0xc0u, 0x18u, 0x06u, 0x9bu, 0x03u, 0x60u, 0x00u, 0x20u, 0xf0u, 0xbdu, 0xc0u, 0x46u, - 0xd0u, 0x03u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x0du, 0x00u, 0x11u, 0x00u, 0x1au, 0x00u, 0x04u, 0x00u, 0xffu, 0xf7u, + 0xe0u, 0x03u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x0du, 0x00u, 0x11u, 0x00u, 0x1au, 0x00u, 0x04u, 0x00u, 0xffu, 0xf7u, 0xafu, 0xffu, 0x8cu, 0x23u, 0x04u, 0x9au, 0x5bu, 0x01u, 0xe2u, 0x50u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xc2u, 0xffu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x9bu, 0xffu, 0x04u, 0x4bu, 0x00u, 0x20u, 0x1bu, 0x68u, 0x1bu, 0x6bu, 0xe4u, 0x18u, - 0x23u, 0x68u, 0x2bu, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, 0x7fu, 0xb5u, 0x0du, 0x00u, + 0x23u, 0x68u, 0x2bu, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u, 0xe0u, 0x03u, 0x00u, 0x08u, 0x7fu, 0xb5u, 0x0du, 0x00u, 0x19u, 0x00u, 0x0eu, 0x4bu, 0x16u, 0x00u, 0x03u, 0x93u, 0x09u, 0x9au, 0x08u, 0x9bu, 0x04u, 0x00u, 0x02u, 0xf0u, 0xf1u, 0xfdu, 0x03u, 0xabu, 0x69u, 0x00u, 0x59u, 0x18u, 0x08u, 0x23u, 0x89u, 0x5du, 0x20u, 0x00u, 0x00u, 0x93u, 0x00u, 0x22u, 0x04u, 0x3bu, 0x02u, 0xf0u, 0x4eu, 0xfeu, 0x05u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xe4u, 0x18u, 0x02u, 0x23u, 0x22u, 0x68u, 0x1au, 0x42u, 0xfcu, 0xd1u, 0x7fu, 0xbdu, 0xc0u, 0x46u, 0x70u, 0x71u, 0x72u, 0x73u, - 0xd0u, 0x03u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x87u, 0xb0u, 0x05u, 0x93u, 0x20u, 0x4bu, 0x05u, 0x00u, 0x1bu, 0x68u, + 0xe0u, 0x03u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x87u, 0xb0u, 0x05u, 0x93u, 0x20u, 0x4bu, 0x05u, 0x00u, 0x1bu, 0x68u, 0x04u, 0x91u, 0x03u, 0x92u, 0x1fu, 0x1eu, 0x02u, 0xd0u, 0x9bu, 0x6bu, 0xc3u, 0x18u, 0x1fu, 0x68u, 0x00u, 0x26u, 0x1bu, 0x4bu, 0xf2u, 0x00u, 0xd2u, 0x18u, 0x03u, 0x99u, 0x08u, 0x23u, 0x28u, 0x00u, 0x02u, 0xf0u, 0x9cu, 0xfeu, 0x44u, 0x1eu, 0xa0u, 0x41u, 0x44u, 0x42u, 0x17u, 0x48u, 0x17u, 0x4bu, 0x04u, 0x40u, 0x01u, 0x36u, 0xe4u, 0x18u, @@ -303,8 +303,8 @@ const uint8_t cy_m0p_image[] = { 0x03u, 0x9au, 0x02u, 0x99u, 0x28u, 0x00u, 0x08u, 0x23u, 0x02u, 0xf0u, 0x4cu, 0xfeu, 0x08u, 0x36u, 0x0cu, 0x9au, 0x39u, 0x00u, 0x28u, 0x00u, 0x08u, 0x23u, 0x02u, 0xf0u, 0x45u, 0xfeu, 0x02u, 0x9bu, 0x04u, 0x9au, 0x28u, 0x00u, 0x01u, 0x97u, 0x00u, 0x96u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xa1u, 0xffu, 0x28u, 0x00u, 0x08u, 0x23u, 0x32u, 0x00u, - 0x05u, 0x99u, 0x02u, 0xf0u, 0x37u, 0xfeu, 0x20u, 0x00u, 0x07u, 0xb0u, 0xf0u, 0xbdu, 0xd0u, 0x03u, 0x00u, 0x08u, - 0x60u, 0x71u, 0x00u, 0x10u, 0xfdu, 0xffu, 0xceu, 0xffu, 0x03u, 0x00u, 0x31u, 0x00u, 0xf0u, 0xb5u, 0x89u, 0xb0u, + 0x05u, 0x99u, 0x02u, 0xf0u, 0x37u, 0xfeu, 0x20u, 0x00u, 0x07u, 0xb0u, 0xf0u, 0xbdu, 0xe0u, 0x03u, 0x00u, 0x08u, + 0x68u, 0x71u, 0x00u, 0x10u, 0xfdu, 0xffu, 0xceu, 0xffu, 0x03u, 0x00u, 0x31u, 0x00u, 0xf0u, 0xb5u, 0x89u, 0xb0u, 0x07u, 0x93u, 0x25u, 0x4bu, 0x04u, 0x00u, 0x1bu, 0x68u, 0x06u, 0x91u, 0x04u, 0x92u, 0x03u, 0x93u, 0x00u, 0x2bu, 0x03u, 0xd0u, 0x9bu, 0x6bu, 0xc3u, 0x18u, 0x1bu, 0x68u, 0x03u, 0x93u, 0x00u, 0x27u, 0x1fu, 0x4bu, 0x04u, 0x9du, 0xfeu, 0x00u, 0xf6u, 0x18u, 0x2bu, 0x00u, 0x10u, 0x33u, 0x05u, 0x93u, 0x08u, 0x23u, 0x32u, 0x00u, 0x29u, 0x00u, @@ -314,20 +314,20 @@ const uint8_t cy_m0p_image[] = { 0x20u, 0x00u, 0x08u, 0x23u, 0x02u, 0xf0u, 0xf6u, 0xfdu, 0x03u, 0x9fu, 0x03u, 0x9bu, 0x08u, 0x37u, 0x01u, 0x93u, 0x06u, 0x9au, 0x33u, 0x00u, 0x20u, 0x00u, 0x00u, 0x97u, 0x01u, 0x21u, 0xffu, 0xf7u, 0x4fu, 0xffu, 0x20u, 0x00u, 0x08u, 0x23u, 0x3au, 0x00u, 0x07u, 0x99u, 0x02u, 0xf0u, 0xe5u, 0xfdu, 0x28u, 0x00u, 0x09u, 0xb0u, 0xf0u, 0xbdu, - 0x08u, 0x35u, 0xcau, 0xe7u, 0x02u, 0x4du, 0xd4u, 0xe7u, 0xd0u, 0x03u, 0x00u, 0x08u, 0x60u, 0x71u, 0x00u, 0x10u, + 0x08u, 0x35u, 0xcau, 0xe7u, 0x02u, 0x4du, 0xd4u, 0xe7u, 0xe0u, 0x03u, 0x00u, 0x08u, 0x68u, 0x71u, 0x00u, 0x10u, 0x03u, 0x00u, 0x31u, 0x00u, 0x70u, 0xb5u, 0x0fu, 0x26u, 0x0bu, 0x4bu, 0x1bu, 0x68u, 0x9cu, 0x68u, 0x05u, 0x19u, 0x2cu, 0x68u, 0x34u, 0x40u, 0x04u, 0x2cu, 0xfbu, 0xd8u, 0x86u, 0x25u, 0x6du, 0x01u, 0x44u, 0x59u, 0x00u, 0x2cu, 0xfcu, 0xdbu, 0xdcu, 0x68u, 0x05u, 0x4du, 0x04u, 0x19u, 0x25u, 0x60u, 0xdcu, 0x68u, 0x04u, 0x19u, 0x21u, 0x60u, - 0xdbu, 0x68u, 0xc0u, 0x18u, 0x02u, 0x60u, 0x70u, 0xbdu, 0xd0u, 0x03u, 0x00u, 0x08u, 0x08u, 0x00u, 0x00u, 0x71u, + 0xdbu, 0x68u, 0xc0u, 0x18u, 0x02u, 0x60u, 0x70u, 0xbdu, 0xe0u, 0x03u, 0x00u, 0x08u, 0x08u, 0x00u, 0x00u, 0x71u, 0x30u, 0xb5u, 0x0fu, 0x25u, 0x06u, 0x4bu, 0x1cu, 0x68u, 0xa3u, 0x68u, 0xc2u, 0x18u, 0x13u, 0x68u, 0x2bu, 0x40u, 0x06u, 0x2bu, 0xfbu, 0xd8u, 0xe3u, 0x68u, 0x09u, 0x06u, 0xc0u, 0x18u, 0x01u, 0x60u, 0x30u, 0xbdu, 0xc0u, 0x46u, - 0xd0u, 0x03u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x0fu, 0x27u, 0x09u, 0x4cu, 0x26u, 0x68u, 0xb4u, 0x68u, 0x05u, 0x19u, + 0xe0u, 0x03u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x0fu, 0x27u, 0x09u, 0x4cu, 0x26u, 0x68u, 0xb4u, 0x68u, 0x05u, 0x19u, 0x2cu, 0x68u, 0x3cu, 0x40u, 0x06u, 0x2cu, 0xfbu, 0xd8u, 0xf4u, 0x68u, 0x09u, 0x03u, 0x00u, 0x19u, 0x80u, 0x24u, 0xe4u, 0x05u, 0x22u, 0x43u, 0x11u, 0x43u, 0x1bu, 0x04u, 0x19u, 0x43u, 0x01u, 0x60u, 0xf0u, 0xbdu, 0xc0u, 0x46u, - 0xd0u, 0x03u, 0x00u, 0x08u, 0x30u, 0xb5u, 0x0fu, 0x25u, 0x09u, 0x4bu, 0x1bu, 0x68u, 0x9au, 0x68u, 0x84u, 0x18u, + 0xe0u, 0x03u, 0x00u, 0x08u, 0x30u, 0xb5u, 0x0fu, 0x25u, 0x09u, 0x4bu, 0x1bu, 0x68u, 0x9au, 0x68u, 0x84u, 0x18u, 0x22u, 0x68u, 0x2au, 0x40u, 0x04u, 0x2au, 0xfbu, 0xd8u, 0xdau, 0x68u, 0x06u, 0x4cu, 0x82u, 0x18u, 0x14u, 0x60u, 0xdau, 0x68u, 0x82u, 0x18u, 0x11u, 0x60u, 0xdbu, 0x68u, 0xc0u, 0x18u, 0x08u, 0x23u, 0x03u, 0x60u, 0x30u, 0xbdu, - 0xd0u, 0x03u, 0x00u, 0x08u, 0x0cu, 0x00u, 0x00u, 0x70u, 0xf7u, 0xb5u, 0x04u, 0x00u, 0x16u, 0x00u, 0x1fu, 0x00u, + 0xe0u, 0x03u, 0x00u, 0x08u, 0x0cu, 0x00u, 0x00u, 0x70u, 0xf7u, 0xb5u, 0x04u, 0x00u, 0x16u, 0x00u, 0x1fu, 0x00u, 0x00u, 0x25u, 0x01u, 0x91u, 0x1cu, 0x4bu, 0xeau, 0x00u, 0xd2u, 0x18u, 0x31u, 0x00u, 0x08u, 0x23u, 0x20u, 0x00u, 0x02u, 0xf0u, 0xb2u, 0xfeu, 0x00u, 0x28u, 0x2cu, 0xd0u, 0x01u, 0x35u, 0x10u, 0x2du, 0xf2u, 0xd1u, 0x00u, 0x25u, 0x31u, 0x00u, 0x20u, 0x00u, 0x08u, 0x22u, 0xffu, 0xf7u, 0x85u, 0xffu, 0x08u, 0x23u, 0x20u, 0x00u, 0x1au, 0x00u, @@ -335,7 +335,7 @@ const uint8_t cy_m0p_image[] = { 0x39u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xbeu, 0xffu, 0x08u, 0x23u, 0x20u, 0x00u, 0x1au, 0x00u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xa0u, 0xffu, 0x01u, 0x99u, 0x20u, 0x00u, 0x4bu, 0x1eu, 0x99u, 0x41u, 0x52u, 0x31u, 0xffu, 0xf7u, 0x87u, 0xffu, 0x20u, 0x00u, 0x08u, 0x23u, 0x01u, 0x22u, 0x0cu, 0x21u, 0xffu, 0xf7u, 0x93u, 0xffu, 0x28u, 0x00u, - 0xfeu, 0xbdu, 0x02u, 0x4du, 0xd4u, 0xe7u, 0xc0u, 0x46u, 0xe0u, 0x71u, 0x00u, 0x10u, 0x03u, 0x00u, 0x31u, 0x00u, + 0xfeu, 0xbdu, 0x02u, 0x4du, 0xd4u, 0xe7u, 0xc0u, 0x46u, 0xe8u, 0x71u, 0x00u, 0x10u, 0x03u, 0x00u, 0x31u, 0x00u, 0xf0u, 0xb5u, 0x04u, 0x00u, 0x00u, 0x27u, 0x85u, 0xb0u, 0x02u, 0x91u, 0x00u, 0x92u, 0x03u, 0x93u, 0x26u, 0x4bu, 0x00u, 0x9du, 0xfeu, 0x00u, 0xf6u, 0x18u, 0x2bu, 0x00u, 0x10u, 0x33u, 0x01u, 0x93u, 0x08u, 0x23u, 0x32u, 0x00u, 0x29u, 0x00u, 0x20u, 0x00u, 0x02u, 0xf0u, 0x68u, 0xfeu, 0x00u, 0x28u, 0x04u, 0xd0u, 0x01u, 0x9bu, 0x9du, 0x42u, @@ -346,15 +346,15 @@ const uint8_t cy_m0p_image[] = { 0x20u, 0x00u, 0xffu, 0xf7u, 0x67u, 0xffu, 0x08u, 0x23u, 0x20u, 0x00u, 0x1au, 0x00u, 0x00u, 0x21u, 0xffu, 0xf7u, 0x49u, 0xffu, 0x02u, 0x99u, 0x20u, 0x00u, 0x4bu, 0x1eu, 0x99u, 0x41u, 0x54u, 0x31u, 0xffu, 0xf7u, 0x30u, 0xffu, 0x20u, 0x00u, 0x08u, 0x23u, 0x01u, 0x22u, 0x0cu, 0x21u, 0xffu, 0xf7u, 0x3cu, 0xffu, 0x28u, 0x00u, 0x05u, 0xb0u, - 0xf0u, 0xbdu, 0x08u, 0x35u, 0xbau, 0xe7u, 0xc0u, 0x46u, 0xe0u, 0x71u, 0x00u, 0x10u, 0x03u, 0x00u, 0x31u, 0x00u, + 0xf0u, 0xbdu, 0x08u, 0x35u, 0xbau, 0xe7u, 0xc0u, 0x46u, 0xe8u, 0x71u, 0x00u, 0x10u, 0x03u, 0x00u, 0x31u, 0x00u, 0x42u, 0x1eu, 0x03u, 0x00u, 0x00u, 0x20u, 0x04u, 0x2au, 0x03u, 0xd8u, 0x28u, 0x30u, 0x58u, 0x43u, 0x01u, 0x4bu, - 0xc0u, 0x18u, 0x70u, 0x47u, 0x60u, 0x72u, 0x00u, 0x10u, 0x09u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xc0u, 0x18u, + 0xc0u, 0x18u, 0x70u, 0x47u, 0x68u, 0x72u, 0x00u, 0x10u, 0x09u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xc0u, 0x18u, 0x08u, 0x4bu, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x04u, 0xd8u, 0x80u, 0x23u, 0x02u, 0x68u, 0x1au, 0x42u, 0xfcu, 0xd1u, 0x70u, 0x47u, 0x03u, 0x68u, 0x00u, 0x2bu, 0xfcu, 0xd1u, 0xfau, 0xe7u, 0xc0u, 0x46u, - 0xd0u, 0x03u, 0x00u, 0x08u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x0bu, 0x00u, 0x13u, 0x22u, 0x00u, 0x21u, + 0xe0u, 0x03u, 0x00u, 0x08u, 0xecu, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x0bu, 0x00u, 0x13u, 0x22u, 0x00u, 0x21u, 0x02u, 0xf0u, 0xf2u, 0xf9u, 0x10u, 0xbdu, 0x00u, 0x00u, 0x10u, 0xb5u, 0x13u, 0x00u, 0x07u, 0x4au, 0x12u, 0x68u, 0x29u, 0x32u, 0x14u, 0x78u, 0x0cu, 0x22u, 0x1fu, 0x2cu, 0x00u, 0xd9u, 0x04u, 0x32u, 0x91u, 0x40u, 0x01u, 0x3bu, - 0x0bu, 0x43u, 0x12u, 0x22u, 0x00u, 0x21u, 0x02u, 0xf0u, 0xdfu, 0xf9u, 0x10u, 0xbdu, 0xdcu, 0x05u, 0x00u, 0x08u, + 0x0bu, 0x43u, 0x12u, 0x22u, 0x00u, 0x21u, 0x02u, 0xf0u, 0xdfu, 0xf9u, 0x10u, 0xbdu, 0xecu, 0x05u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0xadu, 0xb0u, 0x04u, 0x00u, 0x04u, 0x91u, 0x05u, 0x92u, 0x03u, 0x93u, 0x00u, 0x29u, 0x00u, 0xd1u, 0x15u, 0xe1u, 0x03u, 0x9bu, 0x00u, 0x2bu, 0x00u, 0xd1u, 0x11u, 0xe1u, 0x32u, 0x9bu, 0x00u, 0x2bu, 0x00u, 0xd1u, 0x0du, 0xe1u, 0x33u, 0x9bu, 0x00u, 0x2bu, 0x00u, 0xd1u, 0x09u, 0xe1u, 0x32u, 0x9bu, 0x58u, 0x78u, 0xffu, 0xf7u, @@ -392,7 +392,7 @@ const uint8_t cy_m0p_image[] = { 0x00u, 0x28u, 0x00u, 0xd0u, 0x71u, 0xe7u, 0x03u, 0x9bu, 0xe9u, 0x1du, 0xc9u, 0x08u, 0x59u, 0x18u, 0x0au, 0x22u, 0x2bu, 0x00u, 0x20u, 0x00u, 0x04u, 0xf0u, 0xc4u, 0xf8u, 0x68u, 0xe7u, 0x08u, 0x4eu, 0x6bu, 0xe7u, 0x07u, 0x4eu, 0x6eu, 0xe7u, 0x07u, 0x4eu, 0x6cu, 0xe7u, 0xc0u, 0x46u, 0x09u, 0x80u, 0x00u, 0x00u, 0x01u, 0x00u, 0x32u, 0x00u, - 0xdcu, 0x05u, 0x00u, 0x08u, 0xb0u, 0xb0u, 0x00u, 0x00u, 0x0bu, 0x80u, 0x00u, 0x00u, 0x0bu, 0x00u, 0x32u, 0x00u, + 0xecu, 0x05u, 0x00u, 0x08u, 0xb0u, 0xb0u, 0x00u, 0x00u, 0x0bu, 0x80u, 0x00u, 0x00u, 0x0bu, 0x00u, 0x32u, 0x00u, 0x0au, 0x00u, 0x32u, 0x00u, 0xf0u, 0xb5u, 0x87u, 0xb0u, 0x04u, 0x00u, 0x0fu, 0x1eu, 0x04u, 0x92u, 0x03u, 0x93u, 0x00u, 0xd1u, 0x8bu, 0xe1u, 0x00u, 0x2au, 0x00u, 0xd1u, 0x88u, 0xe1u, 0x0cu, 0x9bu, 0x00u, 0x2bu, 0x00u, 0xd1u, 0x84u, 0xe1u, 0x0du, 0x9bu, 0x00u, 0x2bu, 0x00u, 0xd1u, 0x80u, 0xe1u, 0x58u, 0x78u, 0xffu, 0xf7u, 0x78u, 0xfeu, @@ -444,11 +444,11 @@ const uint8_t cy_m0p_image[] = { 0x05u, 0x21u, 0x20u, 0x00u, 0x03u, 0xf0u, 0x7au, 0xffu, 0x00u, 0x28u, 0x09u, 0xd0u, 0x01u, 0x23u, 0x0cu, 0x9au, 0x13u, 0x70u, 0x0eu, 0x49u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x27u, 0xfdu, 0x38u, 0x00u, 0x07u, 0xb0u, 0xf0u, 0xbdu, 0x0cu, 0x9bu, 0x18u, 0x70u, 0xf5u, 0xe7u, 0x04u, 0x4fu, 0x09u, 0x49u, 0xf3u, 0xe7u, 0x02u, 0x4fu, 0xf4u, 0xe7u, - 0x08u, 0x4fu, 0xf2u, 0xe7u, 0xf5u, 0xffu, 0xcdu, 0xffu, 0x0bu, 0x00u, 0x32u, 0x00u, 0xdcu, 0x05u, 0x00u, 0x08u, + 0x08u, 0x4fu, 0xf2u, 0xe7u, 0xf5u, 0xffu, 0xcdu, 0xffu, 0x0bu, 0x00u, 0x32u, 0x00u, 0xecu, 0x05u, 0x00u, 0x08u, 0x80u, 0x80u, 0x00u, 0x00u, 0x08u, 0x60u, 0x00u, 0x00u, 0x06u, 0x80u, 0x00u, 0x00u, 0xf1u, 0x7eu, 0x00u, 0x00u, 0x30u, 0x60u, 0x00u, 0x00u, 0x0au, 0x00u, 0x32u, 0x00u, 0x10u, 0xb5u, 0x13u, 0x00u, 0x07u, 0x4au, 0x12u, 0x68u, 0x29u, 0x32u, 0x14u, 0x78u, 0x0cu, 0x22u, 0x1fu, 0x2cu, 0x00u, 0xd9u, 0x04u, 0x32u, 0x91u, 0x40u, 0x01u, 0x3bu, - 0x0bu, 0x43u, 0x12u, 0x22u, 0x00u, 0x21u, 0x01u, 0xf0u, 0xefu, 0xfeu, 0x10u, 0xbdu, 0xdcu, 0x05u, 0x00u, 0x08u, + 0x0bu, 0x43u, 0x12u, 0x22u, 0x00u, 0x21u, 0x01u, 0xf0u, 0xefu, 0xfeu, 0x10u, 0xbdu, 0xecu, 0x05u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x04u, 0x00u, 0x85u, 0xb0u, 0x08u, 0x00u, 0x02u, 0x91u, 0x03u, 0x92u, 0x1eu, 0x00u, 0xffu, 0xf7u, 0xc7u, 0xfcu, 0x07u, 0x1eu, 0x00u, 0xd1u, 0x7bu, 0xe0u, 0x03u, 0x9bu, 0x00u, 0x2bu, 0x00u, 0xd1u, 0x77u, 0xe0u, 0x00u, 0x2eu, 0x00u, 0xd1u, 0x74u, 0xe0u, 0x73u, 0x68u, 0x00u, 0x2bu, 0x00u, 0xd1u, 0x70u, 0xe0u, 0xb3u, 0x68u, @@ -472,25 +472,25 @@ const uint8_t cy_m0p_image[] = { 0x12u, 0x01u, 0x13u, 0x43u, 0x09u, 0x03u, 0x0bu, 0x43u, 0x36u, 0x22u, 0x00u, 0x21u, 0x01u, 0xf0u, 0x44u, 0xfeu, 0x10u, 0xbdu, 0x00u, 0x00u, 0x09u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xc0u, 0x18u, 0x08u, 0x4bu, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x04u, 0xd8u, 0x80u, 0x23u, 0x02u, 0x68u, 0x1au, 0x42u, 0xfcu, 0xd1u, - 0x70u, 0x47u, 0x03u, 0x68u, 0x00u, 0x2bu, 0xfcu, 0xd1u, 0xfau, 0xe7u, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, - 0xdcu, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, 0xffu, 0xf7u, 0xe4u, 0xffu, 0x02u, 0x4bu, 0x1bu, 0x68u, - 0xdbu, 0x6bu, 0xe4u, 0x18u, 0x20u, 0x68u, 0x10u, 0xbdu, 0xd0u, 0x03u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x0au, 0x4bu, + 0x70u, 0x47u, 0x03u, 0x68u, 0x00u, 0x2bu, 0xfcu, 0xd1u, 0xfau, 0xe7u, 0xc0u, 0x46u, 0xe0u, 0x03u, 0x00u, 0x08u, + 0xecu, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, 0xffu, 0xf7u, 0xe4u, 0xffu, 0x02u, 0x4bu, 0x1bu, 0x68u, + 0xdbu, 0x6bu, 0xe4u, 0x18u, 0x20u, 0x68u, 0x10u, 0xbdu, 0xe0u, 0x03u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x0au, 0x4bu, 0x09u, 0x03u, 0x1bu, 0x68u, 0x12u, 0x01u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x06u, 0xd8u, 0x13u, 0x00u, 0x25u, 0x22u, 0x0bu, 0x43u, 0x00u, 0x21u, 0x01u, 0xf0u, 0x0fu, 0xfeu, 0x10u, 0xbdu, 0x0fu, 0x23u, 0x13u, 0x43u, - 0x0bu, 0x43u, 0x24u, 0x22u, 0xf6u, 0xe7u, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x07u, 0x4bu, + 0x0bu, 0x43u, 0x24u, 0x22u, 0xf6u, 0xe7u, 0xc0u, 0x46u, 0xecu, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x07u, 0x4bu, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x05u, 0xd8u, 0x05u, 0x4bu, 0x21u, 0x22u, 0x00u, 0x21u, - 0x01u, 0xf0u, 0xfau, 0xfdu, 0x10u, 0xbdu, 0x03u, 0x4bu, 0xf8u, 0xe7u, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, + 0x01u, 0xf0u, 0xfau, 0xfdu, 0x10u, 0xbdu, 0x03u, 0x4bu, 0xf8u, 0xe7u, 0xc0u, 0x46u, 0xecu, 0x05u, 0x00u, 0x08u, 0xc0u, 0xc0u, 0x00u, 0x00u, 0xcfu, 0xc0u, 0x00u, 0x00u, 0x00u, 0x23u, 0x10u, 0xb5u, 0x10u, 0x22u, 0x19u, 0x00u, 0x01u, 0xf0u, 0xeau, 0xfdu, 0x10u, 0xbdu, 0x09u, 0x03u, 0x0bu, 0x00u, 0x13u, 0x43u, 0x00u, 0x22u, 0x10u, 0xb5u, 0x11u, 0x00u, 0x01u, 0xf0u, 0xe1u, 0xfdu, 0x10u, 0xbdu, 0x10u, 0xb5u, 0x13u, 0x00u, 0x07u, 0x4au, 0x12u, 0x68u, 0x29u, 0x32u, 0x14u, 0x78u, 0x0cu, 0x22u, 0x1fu, 0x2cu, 0x00u, 0xd9u, 0x04u, 0x32u, 0x91u, 0x40u, 0x01u, 0x3bu, - 0x0bu, 0x43u, 0x12u, 0x22u, 0x00u, 0x21u, 0x01u, 0xf0u, 0xcfu, 0xfdu, 0x10u, 0xbdu, 0xdcu, 0x05u, 0x00u, 0x08u, + 0x0bu, 0x43u, 0x12u, 0x22u, 0x00u, 0x21u, 0x01u, 0xf0u, 0xcfu, 0xfdu, 0x10u, 0xbdu, 0xecu, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x1fu, 0x24u, 0x08u, 0x4bu, 0x89u, 0x06u, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x9cu, 0x42u, 0xa4u, 0x41u, 0x13u, 0x00u, 0x64u, 0x42u, 0x0cu, 0x34u, 0xa3u, 0x40u, 0x80u, 0x22u, 0x0bu, 0x43u, 0x00u, 0x21u, - 0x01u, 0xf0u, 0xbau, 0xfdu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x14u, 0x00u, + 0x01u, 0xf0u, 0xbau, 0xfdu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0xecu, 0x05u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x14u, 0x00u, 0x07u, 0x4au, 0x15u, 0x68u, 0x24u, 0x22u, 0x29u, 0x35u, 0x2du, 0x78u, 0x1fu, 0x2du, 0x00u, 0xd9u, 0x01u, 0x3au, 0x24u, 0x01u, 0x23u, 0x43u, 0x09u, 0x03u, 0x0bu, 0x43u, 0x00u, 0x21u, 0x01u, 0xf0u, 0xa5u, 0xfdu, 0x70u, 0xbdu, - 0xdcu, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x0bu, 0x00u, 0x13u, 0x22u, 0x00u, 0x21u, 0x01u, 0xf0u, 0x9cu, 0xfdu, + 0xecu, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x0bu, 0x00u, 0x13u, 0x22u, 0x00u, 0x21u, 0x01u, 0xf0u, 0x9cu, 0xfdu, 0x10u, 0xbdu, 0x00u, 0x23u, 0x10u, 0xb5u, 0x11u, 0x22u, 0x19u, 0x00u, 0x01u, 0xf0u, 0x95u, 0xfdu, 0x10u, 0xbdu, 0x70u, 0xb5u, 0x04u, 0x00u, 0x1bu, 0x4du, 0xffu, 0xf7u, 0x9fu, 0xffu, 0x20u, 0x00u, 0x01u, 0x22u, 0x02u, 0x21u, 0xffu, 0xf7u, 0xa1u, 0xffu, 0x20u, 0x00u, 0x00u, 0x22u, 0x03u, 0x21u, 0xffu, 0xf7u, 0x9cu, 0xffu, 0x2au, 0x00u, @@ -523,7 +523,7 @@ const uint8_t cy_m0p_image[] = { 0xffu, 0xf7u, 0x70u, 0xfeu, 0x94u, 0x4bu, 0x1bu, 0x78u, 0x00u, 0x2bu, 0x0bu, 0xd0u, 0x01u, 0x2bu, 0x01u, 0xd1u, 0x00u, 0xf0u, 0x35u, 0xfdu, 0x0eu, 0x9bu, 0x00u, 0x22u, 0x01u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x50u, 0xffu, 0x00u, 0xf0u, 0x24u, 0xfdu, 0x8du, 0x4bu, 0x18u, 0x78u, 0x01u, 0x38u, 0x04u, 0x28u, 0x01u, 0xd9u, 0x00u, 0xf0u, - 0x1du, 0xfdu, 0x04u, 0xf0u, 0x39u, 0xffu, 0x05u, 0x00u, 0x89u, 0x00u, 0x25u, 0x01u, 0x73u, 0x03u, 0x18u, 0x05u, + 0x1du, 0xfdu, 0x04u, 0xf0u, 0x3du, 0xffu, 0x05u, 0x00u, 0x89u, 0x00u, 0x25u, 0x01u, 0x73u, 0x03u, 0x18u, 0x05u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa1u, 0xfeu, 0x01u, 0x22u, 0x04u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa3u, 0xfeu, 0x00u, 0x22u, 0x05u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x9eu, 0xfeu, 0x80u, 0x22u, 0x02u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa2u, 0xfeu, 0xc0u, 0x22u, 0x03u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x9du, 0xfeu, 0xc0u, 0x22u, @@ -557,7 +557,7 @@ const uint8_t cy_m0p_image[] = { 0x43u, 0xfdu, 0x16u, 0x4bu, 0x36u, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0x01u, 0xf0u, 0x9du, 0xfbu, 0x03u, 0x23u, 0x02u, 0x22u, 0x04u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x4au, 0xfdu, 0x09u, 0x4bu, 0x3du, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0x01u, 0xf0u, 0x91u, 0xfbu, 0x00u, 0x21u, 0x06u, 0x4bu, 0x37u, 0x22u, 0x20u, 0x00u, 0x01u, 0xf0u, - 0x8bu, 0xfbu, 0x0eu, 0x21u, 0x70u, 0xe7u, 0xc0u, 0x46u, 0x80u, 0x00u, 0x00u, 0x08u, 0xccu, 0x03u, 0x00u, 0x08u, + 0x8bu, 0xfbu, 0x0eu, 0x21u, 0x70u, 0xe7u, 0xc0u, 0x46u, 0x80u, 0x00u, 0x00u, 0x08u, 0xdcu, 0x03u, 0x00u, 0x08u, 0x4eu, 0x00u, 0x40u, 0x00u, 0x4eu, 0x40u, 0x30u, 0x00u, 0x20u, 0x30u, 0x00u, 0x00u, 0x23u, 0x20u, 0x00u, 0x00u, 0x10u, 0x20u, 0x00u, 0x00u, 0x2eu, 0x00u, 0x40u, 0x00u, 0x2eu, 0x20u, 0x30u, 0x00u, 0x2eu, 0x20u, 0x40u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x81u, 0xfdu, 0x01u, 0x22u, 0x0au, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x83u, 0xfdu, @@ -688,7 +688,7 @@ const uint8_t cy_m0p_image[] = { 0x8bu, 0xffu, 0x00u, 0x21u, 0x44u, 0x4bu, 0x37u, 0x22u, 0x20u, 0x00u, 0x00u, 0xf0u, 0x85u, 0xffu, 0xe0u, 0x21u, 0x49u, 0x00u, 0xffu, 0xf7u, 0x69u, 0xfbu, 0x20u, 0x00u, 0xffu, 0xf7u, 0xeau, 0xf9u, 0x01u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xd8u, 0xf9u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xdcu, 0xf9u, 0x09u, 0xb0u, 0xf0u, 0xbdu, 0x42u, 0x4bu, - 0x18u, 0x78u, 0x01u, 0x38u, 0x04u, 0x28u, 0xf1u, 0xd8u, 0x04u, 0xf0u, 0x04u, 0xfau, 0x05u, 0x00u, 0x84u, 0x00u, + 0x18u, 0x78u, 0x01u, 0x38u, 0x04u, 0x28u, 0xf1u, 0xd8u, 0x04u, 0xf0u, 0x08u, 0xfau, 0x05u, 0x00u, 0x84u, 0x00u, 0xd1u, 0x00u, 0xc7u, 0x01u, 0xedu, 0xffu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x76u, 0xf9u, 0x01u, 0x22u, 0x04u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x78u, 0xf9u, 0x00u, 0x22u, 0x05u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x73u, 0xf9u, 0x02u, 0x22u, 0x00u, 0x21u, 0xffu, 0x32u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x76u, 0xf9u, 0x80u, 0x22u, 0x01u, 0x21u, @@ -704,7 +704,7 @@ const uint8_t cy_m0p_image[] = { 0x0bu, 0xffu, 0x00u, 0x21u, 0x0eu, 0x4bu, 0x37u, 0x22u, 0x20u, 0x00u, 0x00u, 0xf0u, 0x05u, 0xffu, 0x03u, 0x21u, 0xffu, 0xf7u, 0xeau, 0xfau, 0x9eu, 0x00u, 0x40u, 0x00u, 0x9eu, 0x90u, 0x30u, 0x00u, 0x82u, 0x70u, 0x00u, 0x00u, 0x73u, 0x70u, 0x00u, 0x00u, 0x9eu, 0x90u, 0x40u, 0x00u, 0x72u, 0x70u, 0x00u, 0x00u, 0x70u, 0x70u, 0x00u, 0x00u, - 0x71u, 0x70u, 0x00u, 0x00u, 0x60u, 0x70u, 0x00u, 0x00u, 0xccu, 0x03u, 0x00u, 0x08u, 0x12u, 0x10u, 0x00u, 0x00u, + 0x71u, 0x70u, 0x00u, 0x00u, 0x60u, 0x70u, 0x00u, 0x00u, 0xdcu, 0x03u, 0x00u, 0x08u, 0x12u, 0x10u, 0x00u, 0x00u, 0x4eu, 0x40u, 0x30u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xf7u, 0xf8u, 0x20u, 0x00u, 0x01u, 0x22u, 0x04u, 0x21u, 0xffu, 0xf7u, 0xf9u, 0xf8u, 0x20u, 0x00u, 0x00u, 0x22u, 0x05u, 0x21u, 0xffu, 0xf7u, 0xf4u, 0xf8u, 0x42u, 0x22u, 0x20u, 0x00u, 0xffu, 0x32u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xf7u, 0xf8u, 0xa0u, 0x22u, 0x20u, 0x00u, 0x52u, 0x00u, @@ -715,7 +715,7 @@ const uint8_t cy_m0p_image[] = { 0x20u, 0x22u, 0x00u, 0x21u, 0x00u, 0xf0u, 0xb0u, 0xfeu, 0x00u, 0x22u, 0x20u, 0x00u, 0x11u, 0x00u, 0x01u, 0x23u, 0xffu, 0xf7u, 0x5du, 0xf8u, 0x20u, 0x00u, 0x03u, 0x23u, 0x00u, 0x22u, 0x01u, 0x21u, 0xffu, 0xf7u, 0xeeu, 0xf8u, 0x01u, 0x23u, 0x00u, 0x22u, 0x04u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x3eu, 0xf8u, 0x7fu, 0xe7u, 0x1cu, 0x22u, - 0xb3u, 0x49u, 0x01u, 0xa8u, 0x04u, 0xf0u, 0x04u, 0xfbu, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa5u, 0xf8u, 0x01u, 0x22u, + 0xb3u, 0x49u, 0x01u, 0xa8u, 0x04u, 0xf0u, 0x08u, 0xfbu, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa5u, 0xf8u, 0x01u, 0x22u, 0x03u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa7u, 0xf8u, 0x00u, 0x22u, 0x04u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa2u, 0xf8u, 0xe0u, 0x22u, 0x05u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa6u, 0xf8u, 0xf0u, 0x22u, 0x00u, 0x21u, 0x52u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa0u, 0xf8u, 0x80u, 0x22u, 0x01u, 0x21u, 0x52u, 0x00u, 0x20u, 0x00u, @@ -746,7 +746,7 @@ const uint8_t cy_m0p_image[] = { 0x03u, 0x23u, 0x00u, 0x22u, 0x19u, 0x00u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0x69u, 0xffu, 0x3eu, 0x23u, 0x3du, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0x00u, 0xf0u, 0xb0u, 0xfdu, 0x00u, 0x21u, 0x3eu, 0x4bu, 0x37u, 0x22u, 0x20u, 0x00u, 0x00u, 0xf0u, 0xaau, 0xfdu, 0x23u, 0x21u, 0xffu, 0xf7u, 0x8fu, 0xf9u, 0x39u, 0x49u, 0x11u, 0x22u, 0x1cu, 0x31u, - 0x01u, 0xa8u, 0x04u, 0xf0u, 0x0du, 0xfau, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xaeu, 0xffu, 0x01u, 0x22u, 0x04u, 0x21u, + 0x01u, 0xa8u, 0x04u, 0xf0u, 0x11u, 0xfau, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xaeu, 0xffu, 0x01u, 0x22u, 0x04u, 0x21u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xb0u, 0xffu, 0x00u, 0x22u, 0x05u, 0x21u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xabu, 0xffu, 0x31u, 0x4au, 0x00u, 0x21u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xafu, 0xffu, 0xf0u, 0x22u, 0x01u, 0x21u, 0x52u, 0x00u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xa9u, 0xffu, 0x81u, 0x22u, 0x06u, 0x21u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xa4u, 0xffu, @@ -760,7 +760,7 @@ const uint8_t cy_m0p_image[] = { 0x4bu, 0xfdu, 0x04u, 0x23u, 0x00u, 0x22u, 0x19u, 0x00u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xf8u, 0xfeu, 0x4eu, 0x23u, 0x3du, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0x00u, 0xf0u, 0x3fu, 0xfdu, 0x00u, 0x21u, 0x07u, 0x4bu, 0x37u, 0x22u, 0x20u, 0x00u, 0x00u, 0xf0u, 0x39u, 0xfdu, 0x43u, 0x21u, 0xffu, 0xf7u, 0x1eu, 0xf9u, 0x12u, 0x10u, 0x00u, 0x00u, - 0x55u, 0x78u, 0x00u, 0x10u, 0x3eu, 0x30u, 0x30u, 0x00u, 0x01u, 0x02u, 0x00u, 0x00u, 0x4eu, 0x40u, 0x30u, 0x00u, + 0x5du, 0x78u, 0x00u, 0x10u, 0x3eu, 0x30u, 0x30u, 0x00u, 0x01u, 0x02u, 0x00u, 0x00u, 0x4eu, 0x40u, 0x30u, 0x00u, 0x70u, 0xb5u, 0x0cu, 0x00u, 0x05u, 0x00u, 0xfeu, 0xf7u, 0xdau, 0xfeu, 0x09u, 0x4bu, 0x26u, 0x01u, 0x33u, 0x43u, 0x28u, 0x00u, 0x3du, 0x22u, 0x00u, 0x21u, 0x00u, 0xf0u, 0x1fu, 0xfdu, 0x24u, 0x03u, 0x05u, 0x4bu, 0x34u, 0x43u, 0x28u, 0x00u, 0x23u, 0x43u, 0x37u, 0x22u, 0x00u, 0x21u, 0x00u, 0xf0u, 0x16u, 0xfdu, 0x70u, 0xbdu, 0xc0u, 0x46u, @@ -772,7 +772,7 @@ const uint8_t cy_m0p_image[] = { 0xebu, 0xfcu, 0x0bu, 0x4bu, 0x2du, 0x03u, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x07u, 0xd8u, 0x2bu, 0x00u, 0x26u, 0x22u, 0x3bu, 0x43u, 0x30u, 0x00u, 0x00u, 0x21u, 0x00u, 0xf0u, 0xddu, 0xfcu, 0xf8u, 0xbdu, 0x0fu, 0x23u, 0x2bu, 0x43u, 0x3bu, 0x43u, 0x25u, 0x22u, 0xf5u, 0xe7u, 0xc0u, 0x46u, 0x0eu, 0x00u, 0x80u, 0x00u, - 0xdcu, 0x05u, 0x00u, 0x08u, 0x07u, 0xb5u, 0x00u, 0x93u, 0x13u, 0x00u, 0xfeu, 0xf7u, 0xf5u, 0xffu, 0x07u, 0xbdu, + 0xecu, 0x05u, 0x00u, 0x08u, 0x07u, 0xb5u, 0x00u, 0x93u, 0x13u, 0x00u, 0xfeu, 0xf7u, 0xf5u, 0xffu, 0x07u, 0xbdu, 0xf8u, 0xb5u, 0x04u, 0x00u, 0x17u, 0x00u, 0x1eu, 0x00u, 0x0du, 0x00u, 0xfeu, 0xf7u, 0xd5u, 0xfeu, 0x3au, 0x00u, 0x07u, 0x21u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xd7u, 0xfeu, 0x32u, 0x00u, 0x08u, 0x21u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xd2u, 0xfeu, 0x2au, 0x00u, 0x0bu, 0x21u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xcdu, 0xfeu, 0x06u, 0x9au, 0x09u, 0x21u, @@ -867,16 +867,16 @@ const uint8_t cy_m0p_image[] = { 0x05u, 0x90u, 0x08u, 0x22u, 0x00u, 0x97u, 0x07u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xd0u, 0xfeu, 0x01u, 0x22u, 0x05u, 0x9bu, 0x13u, 0x42u, 0x0au, 0xd0u, 0x0bu, 0x23u, 0x01u, 0x93u, 0x01u, 0x3bu, 0x00u, 0x93u, 0x02u, 0x97u, 0x01u, 0x3bu, 0x07u, 0x32u, 0x07u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x0eu, 0xfeu, 0x01u, 0x35u, 0xcdu, 0xe7u, - 0xdcu, 0x05u, 0x00u, 0x08u, 0xc5u, 0x60u, 0x00u, 0x00u, 0xc6u, 0xc0u, 0x00u, 0x00u, 0xd0u, 0x03u, 0x00u, 0x08u, + 0xecu, 0x05u, 0x00u, 0x08u, 0xc5u, 0x60u, 0x00u, 0x00u, 0xc6u, 0xc0u, 0x00u, 0x00u, 0xe0u, 0x03u, 0x00u, 0x08u, 0x80u, 0x22u, 0x0du, 0x4bu, 0x52u, 0x00u, 0x90u, 0x42u, 0x11u, 0xd0u, 0x07u, 0xd8u, 0x01u, 0x22u, 0xc0u, 0x28u, 0x0eu, 0xd0u, 0x02u, 0x22u, 0xe0u, 0x28u, 0x0bu, 0xd0u, 0x00u, 0x22u, 0x09u, 0xe0u, 0xc0u, 0x22u, 0x52u, 0x00u, 0x90u, 0x42u, 0x07u, 0xd0u, 0x05u, 0x4au, 0x90u, 0x42u, 0xf6u, 0xd1u, 0x05u, 0x22u, 0x00u, 0xe0u, 0x03u, 0x22u, - 0x1au, 0x70u, 0x70u, 0x47u, 0x04u, 0x22u, 0xfbu, 0xe7u, 0xccu, 0x03u, 0x00u, 0x08u, 0x09u, 0x02u, 0x00u, 0x00u, + 0x1au, 0x70u, 0x70u, 0x47u, 0x04u, 0x22u, 0xfbu, 0xe7u, 0xdcu, 0x03u, 0x00u, 0x08u, 0x09u, 0x02u, 0x00u, 0x00u, 0x01u, 0x4bu, 0x18u, 0x70u, 0x70u, 0x47u, 0xc0u, 0x46u, 0x80u, 0x00u, 0x00u, 0x08u, 0x13u, 0xb5u, 0x04u, 0x00u, 0x05u, 0x98u, 0x00u, 0x90u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x2fu, 0xffu, 0x20u, 0x00u, 0xfeu, 0xf7u, 0x62u, 0xfbu, 0x13u, 0xbdu, 0x00u, 0x00u, 0xf0u, 0xb5u, 0x93u, 0xb0u, 0x05u, 0x93u, 0x1au, 0xabu, 0x1cu, 0x78u, 0x65u, 0x4bu, 0x05u, 0x00u, 0x1bu, 0x68u, 0x03u, 0x91u, 0x04u, 0x92u, 0x1eu, 0x1eu, 0x02u, 0xd0u, 0x9bu, 0x6bu, 0xc3u, 0x18u, - 0x1eu, 0x68u, 0x30u, 0x22u, 0x00u, 0x21u, 0x06u, 0xa8u, 0x03u, 0xf0u, 0x03u, 0xfeu, 0x33u, 0x00u, 0x81u, 0x33u, + 0x1eu, 0x68u, 0x30u, 0x22u, 0x00u, 0x21u, 0x06u, 0xa8u, 0x03u, 0xf0u, 0x07u, 0xfeu, 0x33u, 0x00u, 0x81u, 0x33u, 0x22u, 0x00u, 0xffu, 0x33u, 0x06u, 0xa9u, 0x28u, 0x00u, 0x01u, 0xf0u, 0xfcu, 0xfbu, 0x04u, 0x1eu, 0x00u, 0xd0u, 0x86u, 0xe0u, 0x33u, 0x00u, 0x80u, 0x33u, 0x01u, 0x93u, 0x98u, 0x23u, 0x01u, 0x9au, 0xdbu, 0x00u, 0x77u, 0x1cu, 0xf6u, 0x50u, 0xffu, 0x37u, 0xf3u, 0x18u, 0x5au, 0x60u, 0x9fu, 0x60u, 0x19u, 0x9au, 0x09u, 0x9bu, 0x9au, 0x42u, @@ -900,10 +900,10 @@ const uint8_t cy_m0p_image[] = { 0x28u, 0x00u, 0x00u, 0xf0u, 0xa7u, 0xfbu, 0x02u, 0x9au, 0x09u, 0x9bu, 0x9bu, 0x1au, 0x19u, 0x9au, 0x9bu, 0xb2u, 0xb9u, 0x18u, 0x89u, 0xe7u, 0x02u, 0x9bu, 0x18u, 0x9au, 0x39u, 0x00u, 0x28u, 0x00u, 0x00u, 0xf0u, 0x9au, 0xfbu, 0x86u, 0xe7u, 0xfau, 0x5cu, 0x01u, 0x9cu, 0x4au, 0x40u, 0xf2u, 0x54u, 0xfau, 0x5cu, 0x42u, 0x40u, 0xe2u, 0x54u, - 0x01u, 0x33u, 0x80u, 0xe7u, 0xd0u, 0x03u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x66u, 0x4cu, 0x05u, 0x00u, 0xa5u, 0x44u, + 0x01u, 0x33u, 0x80u, 0xe7u, 0xe0u, 0x03u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x66u, 0x4cu, 0x05u, 0x00u, 0xa5u, 0x44u, 0x04u, 0x92u, 0x93u, 0x22u, 0x05u, 0x93u, 0x13u, 0xaeu, 0xaeu, 0xabu, 0x1cu, 0x78u, 0x03u, 0x91u, 0x92u, 0x00u, - 0x00u, 0x21u, 0x30u, 0x00u, 0x03u, 0xf0u, 0x35u, 0xfdu, 0x30u, 0x22u, 0x00u, 0x21u, 0x07u, 0xa8u, 0x03u, 0xf0u, - 0x30u, 0xfdu, 0x22u, 0x00u, 0x73u, 0xabu, 0x07u, 0xa9u, 0x28u, 0x00u, 0x01u, 0xf0u, 0x77u, 0xfdu, 0x04u, 0x1eu, + 0x00u, 0x21u, 0x30u, 0x00u, 0x03u, 0xf0u, 0x39u, 0xfdu, 0x30u, 0x22u, 0x00u, 0x21u, 0x07u, 0xa8u, 0x03u, 0xf0u, + 0x34u, 0xfdu, 0x22u, 0x00u, 0x73u, 0xabu, 0x07u, 0xa9u, 0x28u, 0x00u, 0x01u, 0xf0u, 0x77u, 0xfdu, 0x04u, 0x1eu, 0x3bu, 0xd1u, 0x90u, 0x23u, 0x9bu, 0x00u, 0xf6u, 0x50u, 0x33u, 0xaau, 0x04u, 0x33u, 0xf2u, 0x50u, 0x0au, 0x9fu, 0x04u, 0x33u, 0x53u, 0xaau, 0xf2u, 0x50u, 0x10u, 0x9bu, 0xbeu, 0xb2u, 0x01u, 0x93u, 0x02u, 0x00u, 0x33u, 0x00u, 0x53u, 0xa9u, 0x28u, 0x00u, 0x00u, 0xf0u, 0x6eu, 0xfcu, 0xadu, 0x9bu, 0xbbu, 0x42u, 0x2eu, 0xd9u, 0x07u, 0xa9u, @@ -933,10 +933,10 @@ const uint8_t cy_m0p_image[] = { 0x13u, 0x43u, 0x33u, 0x60u, 0x00u, 0x2du, 0x01u, 0xd1u, 0x00u, 0x29u, 0x12u, 0xd0u, 0x80u, 0x22u, 0xa3u, 0x68u, 0x52u, 0x02u, 0xc3u, 0x18u, 0x19u, 0x68u, 0x11u, 0x42u, 0xfcu, 0xd0u, 0x23u, 0x68u, 0xc0u, 0x18u, 0x08u, 0x4bu, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x04u, 0xd8u, 0x80u, 0x23u, 0x02u, 0x68u, 0x1au, 0x42u, - 0xfcu, 0xd1u, 0xf7u, 0xbdu, 0x03u, 0x68u, 0x00u, 0x2bu, 0xfcu, 0xd1u, 0xfau, 0xe7u, 0xd0u, 0x03u, 0x00u, 0x08u, - 0xdcu, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x1fu, 0x24u, 0x08u, 0x4bu, 0x89u, 0x06u, 0x1bu, 0x68u, 0x29u, 0x33u, + 0xfcu, 0xd1u, 0xf7u, 0xbdu, 0x03u, 0x68u, 0x00u, 0x2bu, 0xfcu, 0xd1u, 0xfau, 0xe7u, 0xe0u, 0x03u, 0x00u, 0x08u, + 0xecu, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x1fu, 0x24u, 0x08u, 0x4bu, 0x89u, 0x06u, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x9cu, 0x42u, 0xa4u, 0x41u, 0x13u, 0x00u, 0x64u, 0x42u, 0x0cu, 0x34u, 0xa3u, 0x40u, 0x80u, 0x22u, - 0x0bu, 0x43u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xb0u, 0xffu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, + 0x0bu, 0x43u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xb0u, 0xffu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0xecu, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, 0x00u, 0x22u, 0x0eu, 0x21u, 0xffu, 0xf7u, 0xe4u, 0xffu, 0x20u, 0x00u, 0x00u, 0x22u, 0x0du, 0x21u, 0xffu, 0xf7u, 0xdfu, 0xffu, 0x20u, 0x00u, 0x00u, 0x22u, 0x0cu, 0x21u, 0xffu, 0xf7u, 0xdau, 0xffu, 0x20u, 0x00u, 0x00u, 0x22u, 0x0bu, 0x21u, 0xffu, 0xf7u, 0xd5u, 0xffu, 0x20u, 0x00u, 0x00u, 0x22u, 0x0au, 0x21u, @@ -947,10 +947,10 @@ const uint8_t cy_m0p_image[] = { 0x20u, 0x00u, 0x00u, 0x22u, 0x03u, 0x21u, 0xffu, 0xf7u, 0xadu, 0xffu, 0x20u, 0x00u, 0x00u, 0x22u, 0x02u, 0x21u, 0xffu, 0xf7u, 0xa8u, 0xffu, 0x20u, 0x00u, 0x00u, 0x22u, 0x01u, 0x21u, 0xffu, 0xf7u, 0xa3u, 0xffu, 0x00u, 0x22u, 0x20u, 0x00u, 0x11u, 0x00u, 0xffu, 0xf7u, 0x9eu, 0xffu, 0x03u, 0x4bu, 0x0fu, 0x21u, 0x1au, 0x68u, 0x20u, 0x00u, - 0x92u, 0x08u, 0xffu, 0xf7u, 0x97u, 0xffu, 0x10u, 0xbdu, 0xd4u, 0x03u, 0x00u, 0x08u, 0x05u, 0x4bu, 0x1bu, 0x68u, + 0x92u, 0x08u, 0xffu, 0xf7u, 0x97u, 0xffu, 0x10u, 0xbdu, 0xe4u, 0x03u, 0x00u, 0x08u, 0x05u, 0x4bu, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1au, 0x78u, 0x04u, 0x4bu, 0x1fu, 0x2au, 0x00u, 0xd9u, 0x04u, 0x4bu, 0x04u, 0x4au, 0x13u, 0x60u, - 0x70u, 0x47u, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x84u, 0x78u, 0x00u, 0x10u, 0xd8u, 0x78u, 0x00u, 0x10u, - 0xd0u, 0x03u, 0x00u, 0x08u, 0x2fu, 0x4bu, 0x70u, 0xb5u, 0x14u, 0x00u, 0x1au, 0x68u, 0x00u, 0x2au, 0x2cu, 0xd0u, + 0x70u, 0x47u, 0xc0u, 0x46u, 0xecu, 0x05u, 0x00u, 0x08u, 0x8cu, 0x78u, 0x00u, 0x10u, 0xe0u, 0x78u, 0x00u, 0x10u, + 0xe0u, 0x03u, 0x00u, 0x08u, 0x2fu, 0x4bu, 0x70u, 0xb5u, 0x14u, 0x00u, 0x1au, 0x68u, 0x00u, 0x2au, 0x2cu, 0xd0u, 0x00u, 0x29u, 0x09u, 0xd1u, 0x00u, 0x2cu, 0x28u, 0xd1u, 0x13u, 0x6du, 0xc1u, 0x18u, 0x2au, 0x4bu, 0x1bu, 0x68u, 0x9cu, 0x6cu, 0x00u, 0x29u, 0x21u, 0xd0u, 0xa4u, 0x00u, 0x28u, 0x4bu, 0x65u, 0x1eu, 0x9du, 0x42u, 0x1cu, 0xd8u, 0x80u, 0x23u, 0x1bu, 0x01u, 0x9cu, 0x42u, 0x3eu, 0xd0u, 0x0du, 0xd8u, 0x80u, 0x23u, 0x9bu, 0x00u, 0x9cu, 0x42u, @@ -962,8 +962,8 @@ const uint8_t cy_m0p_image[] = { 0xebu, 0xd1u, 0x1fu, 0x2eu, 0x02u, 0xd9u, 0x10u, 0x4du, 0x1bu, 0x02u, 0x43u, 0x51u, 0x93u, 0x6bu, 0xa2u, 0x08u, 0xc3u, 0x18u, 0x19u, 0x60u, 0x0fu, 0x21u, 0xffu, 0xf7u, 0x2du, 0xffu, 0x00u, 0x20u, 0x0bu, 0x4bu, 0x1cu, 0x60u, 0x70u, 0xbdu, 0x7cu, 0x23u, 0xe4u, 0xe7u, 0x78u, 0x23u, 0xe2u, 0xe7u, 0x60u, 0x23u, 0xe0u, 0xe7u, 0x40u, 0x23u, - 0xdeu, 0xe7u, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, 0xdcu, 0x05u, 0x00u, 0x08u, 0xffu, 0x7fu, 0x00u, 0x00u, - 0x0bu, 0x00u, 0x32u, 0x00u, 0xffu, 0x3fu, 0x00u, 0x00u, 0x88u, 0x14u, 0x00u, 0x00u, 0xd4u, 0x03u, 0x00u, 0x08u, + 0xdeu, 0xe7u, 0xc0u, 0x46u, 0xe0u, 0x03u, 0x00u, 0x08u, 0xecu, 0x05u, 0x00u, 0x08u, 0xffu, 0x7fu, 0x00u, 0x00u, + 0x0bu, 0x00u, 0x32u, 0x00u, 0xffu, 0x3fu, 0x00u, 0x00u, 0x88u, 0x14u, 0x00u, 0x00u, 0xe4u, 0x03u, 0x00u, 0x08u, 0x20u, 0x4bu, 0x21u, 0x49u, 0x1bu, 0x68u, 0x09u, 0x68u, 0x9au, 0x6cu, 0x92u, 0x00u, 0x00u, 0x29u, 0x1cu, 0xd0u, 0x1eu, 0x49u, 0x09u, 0x68u, 0x00u, 0x29u, 0x18u, 0xd0u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x2fu, 0xd9u, 0x1bu, 0x4bu, 0xc3u, 0x58u, 0x5bu, 0x04u, 0x5bu, 0x0eu, 0x70u, 0x2bu, 0x1du, 0xd0u, 0x08u, 0xd8u, 0x40u, 0x2bu, @@ -972,89 +972,89 @@ const uint8_t cy_m0p_image[] = { 0x13u, 0xd0u, 0x7fu, 0x2bu, 0xf9u, 0xd1u, 0x80u, 0x22u, 0x52u, 0x00u, 0xf6u, 0xe7u, 0x80u, 0x22u, 0xd2u, 0x01u, 0xf3u, 0xe7u, 0x80u, 0x22u, 0x92u, 0x01u, 0xf0u, 0xe7u, 0x80u, 0x22u, 0x52u, 0x01u, 0xedu, 0xe7u, 0x80u, 0x22u, 0x12u, 0x01u, 0xeau, 0xe7u, 0x80u, 0x22u, 0xd2u, 0x00u, 0xe7u, 0xe7u, 0x80u, 0x22u, 0x92u, 0x00u, 0xe4u, 0xe7u, - 0x0au, 0x00u, 0xe2u, 0xe7u, 0xdcu, 0x05u, 0x00u, 0x08u, 0xd0u, 0x03u, 0x00u, 0x08u, 0xd4u, 0x03u, 0x00u, 0x08u, + 0x0au, 0x00u, 0xe2u, 0xe7u, 0xecu, 0x05u, 0x00u, 0x08u, 0xe0u, 0x03u, 0x00u, 0x08u, 0xe4u, 0x03u, 0x00u, 0x08u, 0x88u, 0x14u, 0x00u, 0x00u, 0x10u, 0xb5u, 0x04u, 0x00u, 0xffu, 0xf7u, 0x30u, 0xffu, 0x17u, 0x4au, 0x18u, 0x49u, 0x13u, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x17u, 0xd8u, 0x16u, 0x4bu, 0x23u, 0x60u, 0x01u, 0x20u, 0x09u, 0x68u, 0x4bu, 0x6bu, 0xe3u, 0x18u, 0x18u, 0x60u, 0x13u, 0x4bu, 0x1bu, 0x68u, 0x00u, 0x2bu, 0x07u, 0xd1u, 0x13u, 0x68u, 0x09u, 0x6du, 0x9au, 0x6cu, 0x61u, 0x18u, 0x92u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x2au, 0xffu, 0x20u, 0x00u, 0xffu, 0xf7u, 0xbdu, 0xfeu, 0x00u, 0x20u, 0x10u, 0xbdu, 0x23u, 0x68u, 0x0bu, 0x48u, 0x03u, 0x40u, 0x23u, 0x60u, 0x0bu, 0x68u, 0x0au, 0x48u, 0x5bu, 0x68u, 0xe3u, 0x18u, 0x18u, 0x60u, 0x80u, 0x23u, 0x20u, 0x68u, - 0x1bu, 0x06u, 0x03u, 0x43u, 0x23u, 0x60u, 0x03u, 0x23u, 0xa3u, 0x60u, 0xd8u, 0xe7u, 0xdcu, 0x05u, 0x00u, 0x08u, - 0xd0u, 0x03u, 0x00u, 0x08u, 0x03u, 0x00u, 0x00u, 0x80u, 0xd4u, 0x03u, 0x00u, 0x08u, 0xffu, 0xffu, 0xfeu, 0x7fu, + 0x1bu, 0x06u, 0x03u, 0x43u, 0x23u, 0x60u, 0x03u, 0x23u, 0xa3u, 0x60u, 0xd8u, 0xe7u, 0xecu, 0x05u, 0x00u, 0x08u, + 0xe0u, 0x03u, 0x00u, 0x08u, 0x03u, 0x00u, 0x00u, 0x80u, 0xe4u, 0x03u, 0x00u, 0x08u, 0xffu, 0xffu, 0xfeu, 0x7fu, 0x01u, 0x00u, 0x02u, 0x00u, 0x03u, 0x23u, 0x03u, 0x70u, 0x00u, 0x20u, 0x70u, 0x47u, 0x06u, 0x4bu, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1au, 0x78u, 0x00u, 0x23u, 0x03u, 0x60u, 0x1fu, 0x2au, 0x03u, 0xd8u, 0x00u, 0x20u, 0x03u, 0x4bu, - 0x18u, 0x60u, 0x70u, 0x47u, 0x83u, 0x60u, 0xf9u, 0xe7u, 0xdcu, 0x05u, 0x00u, 0x08u, 0xd4u, 0x03u, 0x00u, 0x08u, + 0x18u, 0x60u, 0x70u, 0x47u, 0x83u, 0x60u, 0xf9u, 0xe7u, 0xecu, 0x05u, 0x00u, 0x08u, 0xe4u, 0x03u, 0x00u, 0x08u, 0x30u, 0xb5u, 0x01u, 0x29u, 0x0bu, 0xd9u, 0x01u, 0x22u, 0x0au, 0x40u, 0x54u, 0x42u, 0x62u, 0x41u, 0xcbu, 0x0fu, 0x5bu, 0x18u, 0x5bu, 0x10u, 0x9bu, 0x1au, 0x02u, 0x00u, 0x01u, 0x39u, 0x8bu, 0x42u, 0x00u, 0xdbu, 0x30u, 0xbdu, 0x14u, 0x78u, 0x45u, 0x5cu, 0x15u, 0x70u, 0x44u, 0x54u, 0x01u, 0x32u, 0x01u, 0x39u, 0xf5u, 0xe7u, 0x00u, 0x00u, 0x03u, 0x4bu, 0x1bu, 0x68u, 0x9bu, 0x68u, 0xc0u, 0x18u, 0x0fu, 0x23u, 0x00u, 0x68u, 0x18u, 0x40u, 0x70u, 0x47u, - 0xd0u, 0x03u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x04u, 0x00u, 0x0du, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xf0u, 0xffu, + 0xe0u, 0x03u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x04u, 0x00u, 0x0du, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xf0u, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x80u, 0x21u, 0x05u, 0x4bu, 0xc9u, 0x05u, 0x1au, 0x68u, 0xd3u, 0x68u, 0xe3u, 0x18u, - 0x19u, 0x60u, 0xd3u, 0x68u, 0xe4u, 0x18u, 0x25u, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, + 0x19u, 0x60u, 0xd3u, 0x68u, 0xe4u, 0x18u, 0x25u, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u, 0xe0u, 0x03u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x04u, 0x00u, 0x0eu, 0x00u, 0x15u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xd9u, 0xffu, 0x05u, 0x28u, 0xfau, 0xd8u, 0x06u, 0x4bu, 0x06u, 0x49u, 0x1bu, 0x68u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x11u, 0x60u, 0xdau, 0x68u, - 0xa2u, 0x18u, 0x16u, 0x60u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0x25u, 0x60u, 0x70u, 0xbdu, 0xd0u, 0x03u, 0x00u, 0x08u, + 0xa2u, 0x18u, 0x16u, 0x60u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0x25u, 0x60u, 0x70u, 0xbdu, 0xe0u, 0x03u, 0x00u, 0x08u, 0x10u, 0x00u, 0x00u, 0x41u, 0xf8u, 0xb5u, 0x04u, 0x00u, 0x0fu, 0x00u, 0x16u, 0x00u, 0x1du, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xbeu, 0xffu, 0x04u, 0x28u, 0xfau, 0xd8u, 0x07u, 0x4bu, 0x08u, 0x49u, 0x1bu, 0x68u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x11u, 0x60u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x17u, 0x60u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x16u, 0x60u, - 0xdbu, 0x68u, 0xe4u, 0x18u, 0x25u, 0x60u, 0xf8u, 0xbdu, 0xd0u, 0x03u, 0x00u, 0x08u, 0x10u, 0x02u, 0x00u, 0x42u, + 0xdbu, 0x68u, 0xe4u, 0x18u, 0x25u, 0x60u, 0xf8u, 0xbdu, 0xe0u, 0x03u, 0x00u, 0x08u, 0x10u, 0x02u, 0x00u, 0x42u, 0xf8u, 0xb5u, 0x04u, 0x00u, 0x0fu, 0x00u, 0x16u, 0x00u, 0x1du, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa0u, 0xffu, 0x03u, 0x28u, 0xfau, 0xd8u, 0x09u, 0x4bu, 0x0au, 0x49u, 0x1bu, 0x68u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x11u, 0x60u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x17u, 0x60u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x16u, 0x60u, 0xdau, 0x68u, 0xa2u, 0x18u, - 0x15u, 0x60u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0x06u, 0x9bu, 0x23u, 0x60u, 0xf8u, 0xbdu, 0xd0u, 0x03u, 0x00u, 0x08u, + 0x15u, 0x60u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0x06u, 0x9bu, 0x23u, 0x60u, 0xf8u, 0xbdu, 0xe0u, 0x03u, 0x00u, 0x08u, 0x10u, 0x32u, 0x00u, 0x43u, 0x70u, 0xb5u, 0x04u, 0x00u, 0x0du, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x80u, 0xffu, 0x07u, 0x28u, 0xfau, 0xd8u, 0x03u, 0x4bu, 0x2du, 0x06u, 0x1bu, 0x68u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0x25u, 0x60u, - 0x70u, 0xbdu, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x05u, 0x00u, 0x0cu, 0x00u, 0x1eu, 0x00u, + 0x70u, 0xbdu, 0xc0u, 0x46u, 0xe0u, 0x03u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x05u, 0x00u, 0x0cu, 0x00u, 0x1eu, 0x00u, 0x28u, 0x00u, 0xffu, 0xf7u, 0x6du, 0xffu, 0x07u, 0x28u, 0xfau, 0xd8u, 0x05u, 0x4bu, 0x24u, 0x06u, 0x1bu, 0x68u, 0xdbu, 0x68u, 0xedu, 0x18u, 0x01u, 0x23u, 0xb3u, 0x40u, 0x1cu, 0x43u, 0x2cu, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u, - 0xd0u, 0x03u, 0x00u, 0x08u, 0xf8u, 0xb5u, 0x07u, 0x00u, 0x0cu, 0x00u, 0x1du, 0x00u, 0x06u, 0xabu, 0x1eu, 0x78u, + 0xe0u, 0x03u, 0x00u, 0x08u, 0xf8u, 0xb5u, 0x07u, 0x00u, 0x0cu, 0x00u, 0x1du, 0x00u, 0x06u, 0xabu, 0x1eu, 0x78u, 0x38u, 0x00u, 0xffu, 0xf7u, 0x55u, 0xffu, 0x07u, 0x28u, 0xfau, 0xd8u, 0x06u, 0x4bu, 0x02u, 0x21u, 0x1bu, 0x68u, 0xb1u, 0x40u, 0xd8u, 0x68u, 0x01u, 0x23u, 0xabu, 0x40u, 0x24u, 0x06u, 0x19u, 0x43u, 0x38u, 0x18u, 0x21u, 0x43u, - 0x01u, 0x60u, 0xf8u, 0xbdu, 0xd0u, 0x03u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x06u, 0x00u, 0x0cu, 0x00u, 0x1du, 0x00u, + 0x01u, 0x60u, 0xf8u, 0xbdu, 0xe0u, 0x03u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x06u, 0x00u, 0x0cu, 0x00u, 0x1du, 0x00u, 0x30u, 0x00u, 0xffu, 0xf7u, 0x3du, 0xffu, 0x07u, 0x28u, 0xfau, 0xd8u, 0x02u, 0x21u, 0x08u, 0x4bu, 0x05u, 0x9au, 0x1bu, 0x68u, 0x24u, 0x06u, 0xd8u, 0x68u, 0x04u, 0x9bu, 0x30u, 0x18u, 0x99u, 0x40u, 0x01u, 0x23u, 0xabu, 0x40u, 0x19u, 0x43u, 0x03u, 0x23u, 0x93u, 0x40u, 0x19u, 0x43u, 0x21u, 0x43u, 0x01u, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u, - 0xd0u, 0x03u, 0x00u, 0x08u, 0x13u, 0xb5u, 0x04u, 0x00u, 0x08u, 0x00u, 0x11u, 0x00u, 0x00u, 0x2bu, 0x13u, 0xd0u, + 0xe0u, 0x03u, 0x00u, 0x08u, 0x13u, 0xb5u, 0x04u, 0x00u, 0x08u, 0x00u, 0x11u, 0x00u, 0x00u, 0x2bu, 0x13u, 0xd0u, 0x02u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x56u, 0xffu, 0x08u, 0x23u, 0x20u, 0x00u, 0x00u, 0x93u, 0x00u, 0x22u, 0x04u, 0x3bu, 0x50u, 0x21u, 0xffu, 0xf7u, 0xb6u, 0xffu, 0x04u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xe4u, 0x18u, - 0x10u, 0x23u, 0x22u, 0x68u, 0x1au, 0x42u, 0xfcu, 0xd1u, 0x13u, 0xbdu, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, + 0x10u, 0x23u, 0x22u, 0x68u, 0x1au, 0x42u, 0xfcu, 0xd1u, 0x13u, 0xbdu, 0xc0u, 0x46u, 0xe0u, 0x03u, 0x00u, 0x08u, 0x13u, 0xb5u, 0x04u, 0x00u, 0x10u, 0x00u, 0x1au, 0x1eu, 0x13u, 0xd0u, 0x03u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x39u, 0xffu, 0x0cu, 0x23u, 0x20u, 0x00u, 0x00u, 0x93u, 0x00u, 0x22u, 0x04u, 0x3bu, 0x51u, 0x21u, 0xffu, 0xf7u, 0x99u, 0xffu, 0x04u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xe4u, 0x18u, 0x10u, 0x23u, 0x22u, 0x68u, 0x1au, 0x42u, - 0xfcu, 0xd1u, 0x13u, 0xbdu, 0xd0u, 0x03u, 0x00u, 0x08u, 0x13u, 0xb5u, 0x04u, 0x00u, 0x01u, 0x20u, 0x00u, 0x2bu, + 0xfcu, 0xd1u, 0x13u, 0xbdu, 0xe0u, 0x03u, 0x00u, 0x08u, 0x13u, 0xb5u, 0x04u, 0x00u, 0x01u, 0x20u, 0x00u, 0x2bu, 0x15u, 0xd0u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x1eu, 0xffu, 0x08u, 0x23u, 0x00u, 0x22u, 0x00u, 0x93u, 0x52u, 0x21u, 0x04u, 0x3bu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x7eu, 0xffu, 0x10u, 0x22u, 0x05u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xe3u, 0x18u, 0x19u, 0x68u, 0x11u, 0x42u, 0xfcu, 0xd1u, 0xc0u, 0x23u, 0x5bu, 0x00u, 0xe0u, 0x58u, 0x16u, 0xbdu, - 0xd0u, 0x03u, 0x00u, 0x08u, 0x13u, 0xb5u, 0x04u, 0x00u, 0x08u, 0x00u, 0x11u, 0x00u, 0x1au, 0x00u, 0x04u, 0xabu, + 0xe0u, 0x03u, 0x00u, 0x08u, 0x13u, 0xb5u, 0x04u, 0x00u, 0x08u, 0x00u, 0x11u, 0x00u, 0x1au, 0x00u, 0x04u, 0xabu, 0x1bu, 0x88u, 0x00u, 0x2bu, 0x15u, 0xd0u, 0x00u, 0x90u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x19u, 0xffu, 0x0cu, 0x23u, 0x01u, 0x93u, 0x04u, 0x3bu, 0x00u, 0x93u, 0x20u, 0x00u, 0x04u, 0x3bu, 0x00u, 0x22u, 0x53u, 0x21u, 0xffu, 0xf7u, 0x73u, 0xffu, 0x04u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xe4u, 0x18u, 0x10u, 0x23u, 0x22u, 0x68u, 0x1au, 0x42u, - 0xfcu, 0xd1u, 0x13u, 0xbdu, 0xd0u, 0x03u, 0x00u, 0x08u, 0x03u, 0x4bu, 0x1bu, 0x68u, 0x9bu, 0x68u, 0xc0u, 0x18u, - 0x0fu, 0x23u, 0x00u, 0x68u, 0x18u, 0x40u, 0x70u, 0x47u, 0xd0u, 0x03u, 0x00u, 0x08u, 0x03u, 0x4bu, 0x1bu, 0x68u, - 0x1bu, 0x68u, 0xc0u, 0x18u, 0x03u, 0x68u, 0x00u, 0x2bu, 0xfcu, 0xd1u, 0x70u, 0x47u, 0xd0u, 0x03u, 0x00u, 0x08u, + 0xfcu, 0xd1u, 0x13u, 0xbdu, 0xe0u, 0x03u, 0x00u, 0x08u, 0x03u, 0x4bu, 0x1bu, 0x68u, 0x9bu, 0x68u, 0xc0u, 0x18u, + 0x0fu, 0x23u, 0x00u, 0x68u, 0x18u, 0x40u, 0x70u, 0x47u, 0xe0u, 0x03u, 0x00u, 0x08u, 0x03u, 0x4bu, 0x1bu, 0x68u, + 0x1bu, 0x68u, 0xc0u, 0x18u, 0x03u, 0x68u, 0x00u, 0x2bu, 0xfcu, 0xd1u, 0x70u, 0x47u, 0xe0u, 0x03u, 0x00u, 0x08u, 0xf8u, 0xb5u, 0x04u, 0x00u, 0x0du, 0x00u, 0x17u, 0x00u, 0x1eu, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xe4u, 0xffu, 0x04u, 0x28u, 0xfau, 0xd8u, 0x08u, 0x2du, 0x04u, 0xd0u, 0x0cu, 0x4au, 0xa3u, 0x58u, 0x00u, 0x2bu, 0xfcu, 0xdbu, 0x04u, 0xe0u, 0x86u, 0x22u, 0x52u, 0x01u, 0xa3u, 0x58u, 0x00u, 0x2bu, 0xfcu, 0xdbu, 0xe2u, 0x21u, 0x08u, 0x4bu, 0xc9u, 0x05u, 0x1bu, 0x68u, 0x0du, 0x43u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x15u, 0x60u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x17u, 0x60u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0x26u, 0x60u, 0xf8u, 0xbdu, 0xc0u, 0x46u, 0xd0u, 0x10u, 0x00u, 0x00u, - 0xd0u, 0x03u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x04u, 0x00u, 0x0eu, 0x00u, 0x15u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, + 0xe0u, 0x03u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x04u, 0x00u, 0x0eu, 0x00u, 0x15u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xbbu, 0xffu, 0x04u, 0x28u, 0xfau, 0xd8u, 0x06u, 0x4bu, 0x06u, 0x49u, 0x1bu, 0x68u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x11u, 0x60u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x16u, 0x60u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0x25u, 0x60u, 0x70u, 0xbdu, - 0xd0u, 0x03u, 0x00u, 0x08u, 0x0cu, 0x00u, 0x00u, 0x70u, 0x70u, 0xb5u, 0x05u, 0x00u, 0x0cu, 0x00u, 0x1eu, 0x1eu, + 0xe0u, 0x03u, 0x00u, 0x08u, 0x0cu, 0x00u, 0x00u, 0x70u, 0x70u, 0xb5u, 0x05u, 0x00u, 0x0cu, 0x00u, 0x1eu, 0x1eu, 0x22u, 0xd0u, 0x08u, 0x21u, 0xffu, 0xf7u, 0xb4u, 0xffu, 0x21u, 0x00u, 0x32u, 0x00u, 0x28u, 0x00u, 0xffu, 0xf7u, 0xd9u, 0xffu, 0x34u, 0x00u, 0x0fu, 0x2cu, 0x18u, 0xd8u, 0x10u, 0x24u, 0x33u, 0x09u, 0x64u, 0x42u, 0x5cu, 0x43u, 0xa4u, 0x19u, 0xa4u, 0xb2u, 0x00u, 0x2cu, 0x0cu, 0xd0u, 0x28u, 0x00u, 0xffu, 0xf7u, 0x8du, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x0du, 0x4bu, 0x0du, 0x4au, 0x1bu, 0x68u, 0x24u, 0x04u, 0xdbu, 0x68u, 0x14u, 0x43u, 0xebu, 0x18u, 0x1cu, 0x60u, 0x28u, 0x00u, 0xffu, 0xf7u, 0x8au, 0xffu, 0x70u, 0xbdu, 0x28u, 0x00u, 0xffu, 0xf7u, 0x7cu, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x04u, 0x4bu, 0x06u, 0x4au, 0x1bu, 0x68u, 0x10u, 0x3cu, 0xdbu, 0x68u, 0xa4u, 0xb2u, - 0xebu, 0x18u, 0x1au, 0x60u, 0xd6u, 0xe7u, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, 0x08u, 0xc0u, 0x00u, 0x40u, + 0xebu, 0x18u, 0x1au, 0x60u, 0xd6u, 0xe7u, 0xc0u, 0x46u, 0xe0u, 0x03u, 0x00u, 0x08u, 0x08u, 0xc0u, 0x00u, 0x40u, 0x08u, 0xc0u, 0x10u, 0x40u, 0xf8u, 0xb5u, 0x05u, 0x00u, 0x16u, 0x00u, 0x1fu, 0x1eu, 0x1eu, 0xd0u, 0x1au, 0x00u, 0xffu, 0xf7u, 0xa0u, 0xffu, 0x3cu, 0x00u, 0x0fu, 0x2cu, 0x19u, 0xd8u, 0x10u, 0x24u, 0x3bu, 0x09u, 0x64u, 0x42u, 0x5cu, 0x43u, 0xe4u, 0x19u, 0xa4u, 0xb2u, 0x00u, 0x2cu, 0x0du, 0xd0u, 0x28u, 0x00u, 0xffu, 0xf7u, 0x54u, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x0du, 0x4bu, 0x0eu, 0x4au, 0x1bu, 0x68u, 0x32u, 0x43u, 0xdbu, 0x68u, 0x24u, 0x04u, 0xebu, 0x18u, 0x14u, 0x43u, 0x1cu, 0x60u, 0x28u, 0x00u, 0xffu, 0xf7u, 0x50u, 0xffu, 0xf8u, 0xbdu, 0x28u, 0x00u, 0xffu, 0xf7u, 0x42u, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x04u, 0x4bu, 0x06u, 0x4au, 0x1bu, 0x68u, 0x32u, 0x43u, - 0xdbu, 0x68u, 0x10u, 0x3cu, 0xebu, 0x18u, 0x1au, 0x60u, 0xa4u, 0xb2u, 0xd4u, 0xe7u, 0xd0u, 0x03u, 0x00u, 0x08u, + 0xdbu, 0x68u, 0x10u, 0x3cu, 0xebu, 0x18u, 0x1au, 0x60u, 0xa4u, 0xb2u, 0xd4u, 0xe7u, 0xe0u, 0x03u, 0x00u, 0x08u, 0x00u, 0xc0u, 0x00u, 0x42u, 0x00u, 0xc0u, 0x10u, 0x42u, 0x70u, 0xb5u, 0x05u, 0x00u, 0x14u, 0x00u, 0x1eu, 0x00u, 0x01u, 0x20u, 0x00u, 0x2bu, 0x2du, 0xd0u, 0x8cu, 0x23u, 0x00u, 0x22u, 0x5bu, 0x01u, 0xeau, 0x50u, 0x28u, 0x00u, 0x0au, 0x00u, 0x33u, 0x00u, 0x08u, 0x21u, 0xffu, 0xf7u, 0x33u, 0xffu, 0x22u, 0x00u, 0x33u, 0x00u, 0x09u, 0x21u, @@ -1064,7 +1064,7 @@ const uint8_t cy_m0p_image[] = { 0x14u, 0x43u, 0xebu, 0x18u, 0x1cu, 0x60u, 0x28u, 0x00u, 0xffu, 0xf7u, 0x08u, 0xffu, 0x8cu, 0x23u, 0x5bu, 0x01u, 0xe8u, 0x58u, 0x70u, 0xbdu, 0x28u, 0x00u, 0xffu, 0xf7u, 0xf7u, 0xfeu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x04u, 0x4bu, 0x05u, 0x4au, 0x1bu, 0x68u, 0x10u, 0x3cu, 0xdbu, 0x68u, 0xa4u, 0xb2u, 0xebu, 0x18u, 0x1au, 0x60u, 0xd3u, 0xe7u, - 0xd0u, 0x03u, 0x00u, 0x08u, 0x98u, 0x00u, 0x00u, 0x43u, 0x98u, 0x00u, 0x10u, 0x43u, 0xf8u, 0xb5u, 0x1fu, 0x00u, + 0xe0u, 0x03u, 0x00u, 0x08u, 0x98u, 0x00u, 0x00u, 0x43u, 0x98u, 0x00u, 0x10u, 0x43u, 0xf8u, 0xb5u, 0x1fu, 0x00u, 0x06u, 0xabu, 0x1eu, 0x88u, 0x05u, 0x00u, 0x0cu, 0x00u, 0x00u, 0x2eu, 0x29u, 0xd0u, 0x33u, 0x00u, 0x08u, 0x21u, 0xffu, 0xf7u, 0xeeu, 0xfeu, 0x33u, 0x00u, 0x3au, 0x00u, 0x09u, 0x21u, 0x28u, 0x00u, 0xffu, 0xf7u, 0xe8u, 0xfeu, 0x21u, 0x00u, 0x32u, 0x00u, 0x28u, 0x00u, 0xffu, 0xf7u, 0x0du, 0xffu, 0x34u, 0x00u, 0x0fu, 0x2cu, 0x18u, 0xd8u, @@ -1073,37 +1073,37 @@ const uint8_t cy_m0p_image[] = { 0x24u, 0x04u, 0xdbu, 0x68u, 0x14u, 0x43u, 0xebu, 0x18u, 0x1cu, 0x60u, 0x28u, 0x00u, 0xffu, 0xf7u, 0xbeu, 0xfeu, 0xf8u, 0xbdu, 0x28u, 0x00u, 0xffu, 0xf7u, 0xb0u, 0xfeu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x04u, 0x4bu, 0x06u, 0x4au, 0x1bu, 0x68u, 0x10u, 0x3cu, 0xdbu, 0x68u, 0xa4u, 0xb2u, 0xebu, 0x18u, 0x1au, 0x60u, 0xd6u, 0xe7u, 0xc0u, 0x46u, - 0xd0u, 0x03u, 0x00u, 0x08u, 0x98u, 0xc0u, 0x00u, 0x41u, 0x98u, 0xc0u, 0x10u, 0x41u, 0x10u, 0xb5u, 0x80u, 0x24u, + 0xe0u, 0x03u, 0x00u, 0x08u, 0x98u, 0xc0u, 0x00u, 0x41u, 0x98u, 0xc0u, 0x10u, 0x41u, 0x10u, 0xb5u, 0x80u, 0x24u, 0xa4u, 0x00u, 0x01u, 0x51u, 0x81u, 0x21u, 0x52u, 0x00u, 0x52u, 0x08u, 0x89u, 0x00u, 0x42u, 0x50u, 0x82u, 0x22u, 0xdbu, 0x00u, 0xdbu, 0x08u, 0x92u, 0x00u, 0x83u, 0x50u, 0x00u, 0x20u, 0x10u, 0xbdu, 0x70u, 0xb5u, 0x04u, 0x00u, 0x15u, 0x00u, 0xffu, 0xf7u, 0x3fu, 0xfdu, 0x00u, 0x22u, 0x5cu, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xaau, 0xfdu, 0x20u, 0x21u, 0x06u, 0x4bu, 0x1au, 0x68u, 0x13u, 0x68u, 0xe3u, 0x18u, 0x18u, 0x68u, 0x08u, 0x40u, 0xfcu, 0xd1u, - 0x93u, 0x69u, 0xe4u, 0x18u, 0x23u, 0x68u, 0x2bu, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, + 0x93u, 0x69u, 0xe4u, 0x18u, 0x23u, 0x68u, 0x2bu, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u, 0xe0u, 0x03u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x80u, 0x24u, 0xa4u, 0x00u, 0x01u, 0x51u, 0x81u, 0x21u, 0x52u, 0x00u, 0x52u, 0x08u, 0x89u, 0x00u, 0x42u, 0x50u, 0x82u, 0x22u, 0xdbu, 0x00u, 0xdbu, 0x08u, 0x92u, 0x00u, 0x83u, 0x50u, 0x00u, 0x20u, 0x10u, 0xbdu, 0x83u, 0x23u, 0x9bu, 0x00u, 0x10u, 0xb5u, 0xc1u, 0x50u, 0x01u, 0x21u, 0x04u, 0x33u, 0xc1u, 0x50u, 0x06u, 0x4bu, 0x19u, 0x68u, 0x0bu, 0x68u, 0xc3u, 0x18u, 0x1cu, 0x68u, 0x00u, 0x2cu, 0xfcu, 0xdbu, 0x8bu, 0x69u, 0xc0u, 0x18u, - 0x03u, 0x68u, 0x00u, 0x20u, 0x13u, 0x60u, 0x10u, 0xbdu, 0xd0u, 0x03u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x06u, 0x4cu, + 0x03u, 0x68u, 0x00u, 0x20u, 0x13u, 0x60u, 0x10u, 0xbdu, 0xe0u, 0x03u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x06u, 0x4cu, 0x24u, 0x68u, 0x29u, 0x34u, 0x24u, 0x78u, 0x1fu, 0x2cu, 0x02u, 0xd8u, 0xffu, 0xf7u, 0x05u, 0xfeu, 0x10u, 0xbdu, - 0xffu, 0xf7u, 0x12u, 0xffu, 0xfbu, 0xe7u, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x09u, 0x4bu, 0x1bu, 0x68u, + 0xffu, 0xf7u, 0x12u, 0xffu, 0xfbu, 0xe7u, 0xc0u, 0x46u, 0xecu, 0x05u, 0x00u, 0x08u, 0x09u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xc0u, 0x18u, 0x08u, 0x4bu, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x04u, 0xd8u, 0x80u, 0x23u, 0x02u, 0x68u, 0x1au, 0x42u, 0xfcu, 0xd1u, 0x70u, 0x47u, 0x03u, 0x68u, 0x00u, 0x2bu, 0xfcu, 0xd1u, - 0xfau, 0xe7u, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x13u, 0x00u, + 0xfau, 0xe7u, 0xc0u, 0x46u, 0xe0u, 0x03u, 0x00u, 0x08u, 0xecu, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x13u, 0x00u, 0x06u, 0x4au, 0x14u, 0x68u, 0x29u, 0x34u, 0x22u, 0x78u, 0x1fu, 0x2au, 0x03u, 0xd8u, 0x00u, 0x22u, 0xffu, 0xf7u, - 0xbfu, 0xfdu, 0x10u, 0xbdu, 0x00u, 0x22u, 0xffu, 0xf7u, 0xadu, 0xfeu, 0xfau, 0xe7u, 0xdcu, 0x05u, 0x00u, 0x08u, + 0xbfu, 0xfdu, 0x10u, 0xbdu, 0x00u, 0x22u, 0xffu, 0xf7u, 0xadu, 0xfeu, 0xfau, 0xe7u, 0xecu, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x0bu, 0x03u, 0x34u, 0x22u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xd6u, 0xfau, 0x10u, 0xbdu, 0x00u, 0x00u, 0x10u, 0xb5u, 0x0au, 0x4bu, 0x09u, 0x03u, 0x1bu, 0x68u, 0x12u, 0x01u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x06u, 0xd8u, 0x13u, 0x00u, 0x25u, 0x22u, 0x0bu, 0x43u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xc5u, 0xfau, 0x10u, 0xbdu, - 0x0fu, 0x23u, 0x13u, 0x43u, 0x0bu, 0x43u, 0x24u, 0x22u, 0xf6u, 0xe7u, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, + 0x0fu, 0x23u, 0x13u, 0x43u, 0x0bu, 0x43u, 0x24u, 0x22u, 0xf6u, 0xe7u, 0xc0u, 0x46u, 0xecu, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x09u, 0x4bu, 0x09u, 0x03u, 0x1bu, 0x68u, 0x12u, 0x01u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x06u, 0xd8u, 0x13u, 0x00u, 0x0bu, 0x43u, 0x21u, 0x22u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xadu, 0xfau, 0x10u, 0xbdu, - 0x0fu, 0x23u, 0x13u, 0x43u, 0xf6u, 0xe7u, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x0bu, 0x00u, + 0x0fu, 0x23u, 0x13u, 0x43u, 0xf6u, 0xe7u, 0xc0u, 0x46u, 0xecu, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x0bu, 0x00u, 0x13u, 0x22u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xa0u, 0xfau, 0x10u, 0xbdu, 0x00u, 0x00u, 0x10u, 0xb5u, 0x13u, 0x00u, 0x07u, 0x4au, 0x12u, 0x68u, 0x29u, 0x32u, 0x14u, 0x78u, 0x0cu, 0x22u, 0x1fu, 0x2cu, 0x00u, 0xd9u, 0x04u, 0x32u, 0x91u, 0x40u, 0x01u, 0x3bu, 0x0bu, 0x43u, 0x12u, 0x22u, 0x00u, 0x21u, 0xffu, 0xf7u, 0x8du, 0xfau, 0x10u, 0xbdu, - 0xdcu, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x1fu, 0x24u, 0x08u, 0x4bu, 0x89u, 0x06u, 0x1bu, 0x68u, 0x29u, 0x33u, + 0xecu, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x1fu, 0x24u, 0x08u, 0x4bu, 0x89u, 0x06u, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x9cu, 0x42u, 0xa4u, 0x41u, 0x13u, 0x00u, 0x64u, 0x42u, 0x0cu, 0x34u, 0xa3u, 0x40u, 0x80u, 0x22u, - 0x0bu, 0x43u, 0x00u, 0x21u, 0xffu, 0xf7u, 0x78u, 0xfau, 0x10u, 0xbdu, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, + 0x0bu, 0x43u, 0x00u, 0x21u, 0xffu, 0xf7u, 0x78u, 0xfau, 0x10u, 0xbdu, 0xc0u, 0x46u, 0xecu, 0x05u, 0x00u, 0x08u, 0xf7u, 0xb5u, 0x04u, 0x00u, 0x1du, 0x00u, 0x5eu, 0x1cu, 0x01u, 0x92u, 0x0fu, 0x00u, 0x32u, 0x00u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xccu, 0xffu, 0x32u, 0x00u, 0x01u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xc7u, 0xffu, 0x32u, 0x00u, 0x02u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xc2u, 0xffu, 0x2au, 0x00u, 0x03u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, @@ -1116,7 +1116,7 @@ const uint8_t cy_m0p_image[] = { 0xffu, 0xf7u, 0x2au, 0xfau, 0x0du, 0x4bu, 0x03u, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x24u, 0xfau, 0x33u, 0x00u, 0x3au, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x1eu, 0xfau, 0x00u, 0x22u, 0x20u, 0x00u, 0x11u, 0x00u, 0xffu, 0xf7u, 0x5du, 0xffu, 0x02u, 0x22u, 0x20u, 0x00u, 0x11u, 0x00u, 0xffu, 0xf7u, 0x40u, 0xffu, - 0x01u, 0x3du, 0xd9u, 0xe7u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x02u, 0x00u, 0x30u, 0x00u, 0x01u, 0x00u, 0x30u, 0x00u, + 0x01u, 0x3du, 0xd9u, 0xe7u, 0xecu, 0x05u, 0x00u, 0x08u, 0x02u, 0x00u, 0x30u, 0x00u, 0x01u, 0x00u, 0x30u, 0x00u, 0xf7u, 0xb5u, 0x04u, 0x00u, 0x08u, 0x9eu, 0x00u, 0x91u, 0x15u, 0x00u, 0x01u, 0x21u, 0x72u, 0x1cu, 0x77u, 0x00u, 0x01u, 0x93u, 0xffu, 0xf7u, 0x63u, 0xffu, 0x3au, 0x00u, 0x02u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x5eu, 0xffu, 0x3au, 0x00u, 0x03u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x59u, 0xffu, 0x32u, 0x00u, 0x00u, 0x21u, 0x20u, 0x00u, @@ -1138,7 +1138,7 @@ const uint8_t cy_m0p_image[] = { 0x7bu, 0xf9u, 0x20u, 0x00u, 0x10u, 0x4bu, 0x03u, 0x22u, 0x00u, 0x21u, 0xffu, 0xf7u, 0x75u, 0xf9u, 0x00u, 0x9bu, 0x20u, 0x00u, 0x1au, 0x03u, 0x02u, 0x23u, 0x00u, 0x21u, 0x13u, 0x43u, 0x30u, 0x22u, 0xffu, 0xf7u, 0x6cu, 0xf9u, 0x0eu, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xc2u, 0xfeu, 0xf7u, 0xbdu, 0xc0u, 0x46u, 0x3au, 0x10u, 0x00u, 0x00u, - 0x18u, 0x20u, 0x00u, 0x00u, 0x23u, 0x20u, 0x00u, 0x00u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x20u, 0x20u, 0x00u, 0x00u, + 0x18u, 0x20u, 0x00u, 0x00u, 0x23u, 0x20u, 0x00u, 0x00u, 0xecu, 0x05u, 0x00u, 0x08u, 0x20u, 0x20u, 0x00u, 0x00u, 0x10u, 0x10u, 0x00u, 0x00u, 0x21u, 0x30u, 0x00u, 0x00u, 0x23u, 0x00u, 0x30u, 0x00u, 0x28u, 0x30u, 0x00u, 0x00u, 0xf7u, 0xb5u, 0x06u, 0x00u, 0x1cu, 0x00u, 0x09u, 0x9bu, 0x01u, 0x91u, 0x5fu, 0x00u, 0x15u, 0x00u, 0x02u, 0x21u, 0x3au, 0x00u, 0xffu, 0xf7u, 0xabu, 0xfeu, 0x3au, 0x00u, 0x03u, 0x21u, 0x30u, 0x00u, 0xffu, 0xf7u, 0xa6u, 0xfeu, @@ -1156,7 +1156,7 @@ const uint8_t cy_m0p_image[] = { 0xebu, 0xf8u, 0x01u, 0x9bu, 0x30u, 0x00u, 0x1cu, 0x03u, 0x0du, 0x4bu, 0x30u, 0x22u, 0x23u, 0x43u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xe2u, 0xf8u, 0xc0u, 0x23u, 0x9bu, 0x03u, 0x30u, 0x00u, 0x23u, 0x43u, 0x30u, 0x22u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xdau, 0xf8u, 0x30u, 0x00u, 0x03u, 0x21u, 0xffu, 0xf7u, 0x30u, 0xfeu, 0xf7u, 0xbdu, 0xc0u, 0x46u, - 0xdcu, 0x05u, 0x00u, 0x08u, 0x20u, 0x30u, 0x00u, 0x00u, 0x30u, 0x20u, 0x00u, 0x00u, 0x10u, 0x00u, 0x40u, 0x00u, + 0xecu, 0x05u, 0x00u, 0x08u, 0x20u, 0x30u, 0x00u, 0x00u, 0x30u, 0x20u, 0x00u, 0x00u, 0x10u, 0x00u, 0x40u, 0x00u, 0x01u, 0x00u, 0x40u, 0x00u, 0xf8u, 0xb5u, 0x1du, 0x00u, 0x00u, 0x23u, 0x16u, 0x00u, 0x0fu, 0x00u, 0x10u, 0x22u, 0x19u, 0x00u, 0x04u, 0x00u, 0xffu, 0xf7u, 0xc0u, 0xf8u, 0xe0u, 0x23u, 0x00u, 0x22u, 0x1bu, 0x02u, 0x11u, 0x00u, 0x3bu, 0x43u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xb8u, 0xf8u, 0x90u, 0x23u, 0x00u, 0x22u, 0x1bu, 0x02u, 0x33u, 0x43u, @@ -1179,8 +1179,8 @@ const uint8_t cy_m0p_image[] = { 0x20u, 0x00u, 0x11u, 0x00u, 0xffu, 0xf7u, 0x5cu, 0xfdu, 0x33u, 0x68u, 0x2cu, 0x22u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x00u, 0xd9u, 0x04u, 0x3au, 0x0eu, 0x4bu, 0xa8u, 0xe7u, 0x0eu, 0x4bu, 0x25u, 0x22u, 0xeau, 0xe7u, 0xe0u, 0x21u, 0x20u, 0x00u, 0x89u, 0x01u, 0xffu, 0xf7u, 0x79u, 0xfdu, 0x00u, 0x23u, 0x11u, 0x22u, 0x19u, 0x00u, - 0x20u, 0x00u, 0xffu, 0xf7u, 0x19u, 0xf8u, 0xf8u, 0xbdu, 0xdcu, 0x05u, 0x00u, 0x08u, 0x0au, 0xb0u, 0x00u, 0x00u, - 0x09u, 0xc0u, 0x00u, 0x00u, 0xd0u, 0x03u, 0x00u, 0x08u, 0xdcu, 0xd0u, 0x00u, 0x00u, 0xd0u, 0xd0u, 0x00u, 0x00u, + 0x20u, 0x00u, 0xffu, 0xf7u, 0x19u, 0xf8u, 0xf8u, 0xbdu, 0xecu, 0x05u, 0x00u, 0x08u, 0x0au, 0xb0u, 0x00u, 0x00u, + 0x09u, 0xc0u, 0x00u, 0x00u, 0xe0u, 0x03u, 0x00u, 0x08u, 0xdcu, 0xd0u, 0x00u, 0x00u, 0xd0u, 0xd0u, 0x00u, 0x00u, 0x0au, 0xe0u, 0x00u, 0x00u, 0xdfu, 0xd0u, 0x00u, 0x00u, 0xf0u, 0xb5u, 0x85u, 0xb0u, 0x06u, 0x00u, 0x0fu, 0x00u, 0x02u, 0x93u, 0x0au, 0x9du, 0x0bu, 0x98u, 0x06u, 0x2au, 0x37u, 0xd8u, 0x21u, 0x4bu, 0x91u, 0x00u, 0xc9u, 0x58u, 0x20u, 0x4cu, 0x21u, 0x4bu, 0xa4u, 0x5cu, 0x9bu, 0x5cu, 0x01u, 0x22u, 0x3au, 0x70u, 0x1au, 0x19u, 0x0bu, 0x32u, @@ -1191,7 +1191,7 @@ const uint8_t cy_m0p_image[] = { 0x00u, 0x28u, 0x12u, 0xd1u, 0x00u, 0x9au, 0xa3u, 0xb2u, 0xaau, 0x18u, 0x02u, 0x99u, 0x30u, 0x00u, 0xffu, 0xf7u, 0xb5u, 0xfcu, 0x00u, 0x28u, 0x09u, 0xd1u, 0x38u, 0x70u, 0x07u, 0xe0u, 0x00u, 0x24u, 0x23u, 0x00u, 0x21u, 0x00u, 0xcau, 0xe7u, 0x01u, 0x30u, 0x42u, 0x78u, 0xffu, 0x2au, 0xe0u, 0xd0u, 0x00u, 0x20u, 0x05u, 0xb0u, 0xf0u, 0xbdu, - 0x2cu, 0x79u, 0x00u, 0x10u, 0x4fu, 0x79u, 0x00u, 0x10u, 0x48u, 0x79u, 0x00u, 0x10u, 0xf0u, 0xb5u, 0x8bu, 0xb0u, + 0x34u, 0x79u, 0x00u, 0x10u, 0x57u, 0x79u, 0x00u, 0x10u, 0x50u, 0x79u, 0x00u, 0x10u, 0xf0u, 0xb5u, 0x8bu, 0xb0u, 0x09u, 0x93u, 0x8bu, 0x68u, 0x04u, 0x00u, 0x05u, 0x93u, 0xcbu, 0x68u, 0x08u, 0x92u, 0x06u, 0x93u, 0x0bu, 0x68u, 0x4fu, 0x68u, 0x07u, 0x93u, 0x0bu, 0x69u, 0x8du, 0x69u, 0x03u, 0x93u, 0x4bu, 0x69u, 0x04u, 0x93u, 0xb3u, 0x4bu, 0x1bu, 0x68u, 0x1eu, 0x1eu, 0x02u, 0xd0u, 0x9bu, 0x6bu, 0xc3u, 0x18u, 0x1eu, 0x68u, 0x20u, 0x00u, 0xffu, 0xf7u, @@ -1238,10 +1238,10 @@ const uint8_t cy_m0p_image[] = { 0xffu, 0xf7u, 0x4eu, 0xfcu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x51u, 0xfbu, 0x0du, 0x23u, 0x00u, 0x97u, 0x1au, 0x00u, 0x19u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x44u, 0xfcu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x47u, 0xfbu, 0x01u, 0x3du, 0x93u, 0xe7u, 0x0du, 0x23u, 0x05u, 0x22u, 0x19u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x39u, 0xfcu, 0x20u, 0x00u, - 0xffu, 0xf7u, 0x3cu, 0xfbu, 0x00u, 0x97u, 0x05u, 0x23u, 0xe9u, 0xe7u, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, + 0xffu, 0xf7u, 0x3cu, 0xfbu, 0x00u, 0x97u, 0x05u, 0x23u, 0xe9u, 0xe7u, 0xc0u, 0x46u, 0xe0u, 0x03u, 0x00u, 0x08u, 0x06u, 0x60u, 0x00u, 0x00u, 0x05u, 0x50u, 0x00u, 0x00u, 0x07u, 0x70u, 0x00u, 0x00u, 0x08u, 0x80u, 0x00u, 0x00u, 0x09u, 0xa0u, 0x00u, 0x00u, 0x0au, 0xc0u, 0x00u, 0x00u, 0x0bu, 0x50u, 0x00u, 0x00u, 0x07u, 0xb0u, 0x00u, 0x00u, - 0xdcu, 0x05u, 0x00u, 0x08u, 0xb9u, 0xe0u, 0x00u, 0x00u, 0xbeu, 0xb0u, 0x00u, 0x00u, 0xf0u, 0xb5u, 0x0bu, 0x69u, + 0xecu, 0x05u, 0x00u, 0x08u, 0xb9u, 0xe0u, 0x00u, 0x00u, 0xbeu, 0xb0u, 0x00u, 0x00u, 0xf0u, 0xb5u, 0x0bu, 0x69u, 0x87u, 0xb0u, 0x03u, 0x93u, 0x4bu, 0x69u, 0x04u, 0x00u, 0x04u, 0x93u, 0x8bu, 0x69u, 0x0fu, 0x68u, 0x05u, 0x93u, 0x34u, 0x4bu, 0x4du, 0x68u, 0x1bu, 0x68u, 0x1eu, 0x1eu, 0x02u, 0xd0u, 0x9bu, 0x6bu, 0xc3u, 0x18u, 0x1eu, 0x68u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0x3du, 0xffu, 0x31u, 0x00u, 0x82u, 0xb2u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x1eu, 0xfbu, @@ -1256,13 +1256,13 @@ const uint8_t cy_m0p_image[] = { 0x0eu, 0x22u, 0x00u, 0xf0u, 0xcdu, 0xfdu, 0x2bu, 0x00u, 0x32u, 0x00u, 0x20u, 0x00u, 0x0cu, 0x21u, 0xffu, 0xf7u, 0xf9u, 0xfcu, 0x2bu, 0x00u, 0x0cu, 0x22u, 0x04u, 0x99u, 0x20u, 0x00u, 0x00u, 0xf0u, 0xc1u, 0xfdu, 0xf0u, 0x21u, 0x20u, 0x00u, 0xc9u, 0x01u, 0xffu, 0xf7u, 0x12u, 0xfbu, 0x20u, 0x00u, 0xffu, 0xf7u, 0xafu, 0xfau, 0x00u, 0x20u, - 0x07u, 0xb0u, 0xf0u, 0xbdu, 0xd0u, 0x03u, 0x00u, 0x08u, 0x0bu, 0x00u, 0x13u, 0xb5u, 0x11u, 0x00u, 0x07u, 0x22u, + 0x07u, 0xb0u, 0xf0u, 0xbdu, 0xe0u, 0x03u, 0x00u, 0x08u, 0x0bu, 0x00u, 0x13u, 0xb5u, 0x11u, 0x00u, 0x07u, 0x22u, 0x04u, 0x00u, 0x58u, 0x68u, 0x02u, 0x40u, 0xc0u, 0x20u, 0x80u, 0x00u, 0x22u, 0x50u, 0x1au, 0x69u, 0x20u, 0x00u, 0x00u, 0x92u, 0x9bu, 0x69u, 0xfeu, 0xf7u, 0xdcu, 0xffu, 0x0cu, 0x23u, 0x01u, 0x93u, 0x04u, 0x3bu, 0x00u, 0x93u, 0x20u, 0x00u, 0x04u, 0x3bu, 0x00u, 0x22u, 0x4cu, 0x21u, 0xffu, 0xf7u, 0x36u, 0xf8u, 0x04u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xe4u, 0x18u, 0x04u, 0x23u, 0x22u, 0x68u, 0x1au, 0x42u, 0xfcu, 0xd1u, 0x13u, 0xbdu, 0xc0u, 0x46u, - 0xd0u, 0x03u, 0x00u, 0x08u, 0x00u, 0xb5u, 0x06u, 0x2au, 0x00u, 0xd9u, 0x80u, 0xe0u, 0x10u, 0x00u, 0x8bu, 0x60u, - 0x1au, 0x00u, 0x02u, 0xf0u, 0x0du, 0xf8u, 0x04u, 0x16u, 0x29u, 0x3au, 0x4du, 0x6cu, 0x5cu, 0x00u, 0x54u, 0x33u, + 0xe0u, 0x03u, 0x00u, 0x08u, 0x00u, 0xb5u, 0x06u, 0x2au, 0x00u, 0xd9u, 0x80u, 0xe0u, 0x10u, 0x00u, 0x8bu, 0x60u, + 0x1au, 0x00u, 0x02u, 0xf0u, 0x11u, 0xf8u, 0x04u, 0x16u, 0x29u, 0x3au, 0x4du, 0x6cu, 0x5cu, 0x00u, 0x54u, 0x33u, 0x8bu, 0x61u, 0x3cu, 0x4bu, 0x00u, 0x20u, 0xcbu, 0x62u, 0x40u, 0x23u, 0xcbu, 0x60u, 0x2cu, 0x3bu, 0x4bu, 0x61u, 0x4bu, 0x62u, 0x2du, 0x33u, 0x40u, 0x32u, 0xffu, 0x33u, 0x0au, 0x61u, 0x08u, 0x60u, 0x48u, 0x60u, 0xcbu, 0x61u, 0x00u, 0xbdu, 0x60u, 0x33u, 0x8bu, 0x61u, 0x01u, 0x23u, 0x0bu, 0x60u, 0x4bu, 0x60u, 0x32u, 0x4bu, 0x40u, 0x32u, @@ -1278,8 +1278,8 @@ const uint8_t cy_m0p_image[] = { 0x80u, 0x23u, 0xcbu, 0x60u, 0x40u, 0x3bu, 0x4bu, 0x61u, 0x0au, 0x61u, 0x24u, 0x3bu, 0xdcu, 0xe7u, 0xc0u, 0x33u, 0x8bu, 0x61u, 0x05u, 0x23u, 0x0bu, 0x60u, 0x03u, 0x3bu, 0x4bu, 0x60u, 0x0cu, 0x4bu, 0x80u, 0x32u, 0xcbu, 0x62u, 0x80u, 0x23u, 0xcbu, 0x60u, 0x40u, 0x3bu, 0x4bu, 0x61u, 0x0au, 0x61u, 0x20u, 0x3bu, 0xccu, 0xe7u, 0x08u, 0x48u, - 0x96u, 0xe7u, 0xc0u, 0x46u, 0xd8u, 0x79u, 0x00u, 0x10u, 0xecu, 0x79u, 0x00u, 0x10u, 0x0cu, 0x7au, 0x00u, 0x10u, - 0x2cu, 0x7au, 0x00u, 0x10u, 0x6cu, 0x7au, 0x00u, 0x10u, 0xacu, 0x7au, 0x00u, 0x10u, 0xecu, 0x7au, 0x00u, 0x10u, + 0x96u, 0xe7u, 0xc0u, 0x46u, 0xe0u, 0x79u, 0x00u, 0x10u, 0xf4u, 0x79u, 0x00u, 0x10u, 0x14u, 0x7au, 0x00u, 0x10u, + 0x34u, 0x7au, 0x00u, 0x10u, 0x74u, 0x7au, 0x00u, 0x10u, 0xb4u, 0x7au, 0x00u, 0x10u, 0xf4u, 0x7au, 0x00u, 0x10u, 0x0bu, 0x00u, 0x32u, 0x00u, 0x10u, 0xb5u, 0x00u, 0x29u, 0x01u, 0xd1u, 0x07u, 0x48u, 0x10u, 0xbdu, 0x00u, 0x24u, 0x4bu, 0x69u, 0x8cu, 0x62u, 0x0cu, 0x62u, 0xa3u, 0x42u, 0xf7u, 0xd0u, 0xcau, 0x6au, 0x9bu, 0xb2u, 0x09u, 0x69u, 0xfeu, 0xf7u, 0xa0u, 0xffu, 0x20u, 0x00u, 0xf1u, 0xe7u, 0x0bu, 0x00u, 0x32u, 0x00u, 0xf7u, 0xb5u, 0x07u, 0x00u, @@ -1309,33 +1309,33 @@ const uint8_t cy_m0p_image[] = { 0x00u, 0x20u, 0x70u, 0xbdu, 0x00u, 0x48u, 0xfcu, 0xe7u, 0x0bu, 0x00u, 0x32u, 0x00u, 0xf0u, 0xb5u, 0x8fu, 0xb0u, 0x01u, 0x93u, 0x14u, 0xabu, 0x1fu, 0x78u, 0x19u, 0x4bu, 0x04u, 0x00u, 0x1bu, 0x68u, 0x00u, 0x91u, 0x16u, 0x00u, 0x1du, 0x1eu, 0x02u, 0xd0u, 0x9bu, 0x6bu, 0xc3u, 0x18u, 0x1du, 0x68u, 0x30u, 0x22u, 0x00u, 0x21u, 0x02u, 0xa8u, - 0x02u, 0xf0u, 0x7fu, 0xf8u, 0x2bu, 0x00u, 0x3au, 0x00u, 0x02u, 0xa9u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x7au, 0xfeu, + 0x02u, 0xf0u, 0x83u, 0xf8u, 0x2bu, 0x00u, 0x3au, 0x00u, 0x02u, 0xa9u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x7au, 0xfeu, 0x00u, 0x28u, 0x18u, 0xd1u, 0x02u, 0xa9u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x0cu, 0xffu, 0x00u, 0x28u, 0x12u, 0xd1u, 0x33u, 0x00u, 0x00u, 0x9au, 0x02u, 0xa9u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x18u, 0xffu, 0x00u, 0x28u, 0x0au, 0xd1u, 0x01u, 0x9au, 0x02u, 0xa9u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x4fu, 0xffu, 0x00u, 0x28u, 0x03u, 0xd1u, 0x02u, 0xa9u, - 0x20u, 0x00u, 0xffu, 0xf7u, 0xadu, 0xffu, 0x0fu, 0xb0u, 0xf0u, 0xbdu, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, + 0x20u, 0x00u, 0xffu, 0xf7u, 0xadu, 0xffu, 0x0fu, 0xb0u, 0xf0u, 0xbdu, 0xc0u, 0x46u, 0xe0u, 0x03u, 0x00u, 0x08u, 0x03u, 0x4bu, 0x1bu, 0x68u, 0x9bu, 0x68u, 0xc0u, 0x18u, 0x0fu, 0x23u, 0x00u, 0x68u, 0x18u, 0x40u, 0x70u, 0x47u, - 0xd0u, 0x03u, 0x00u, 0x08u, 0x03u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xc0u, 0x18u, 0x03u, 0x68u, 0x00u, 0x2bu, - 0xfcu, 0xd1u, 0x70u, 0x47u, 0xd0u, 0x03u, 0x00u, 0x08u, 0xf8u, 0xb5u, 0x04u, 0x00u, 0x0fu, 0x00u, 0x16u, 0x00u, + 0xe0u, 0x03u, 0x00u, 0x08u, 0x03u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xc0u, 0x18u, 0x03u, 0x68u, 0x00u, 0x2bu, + 0xfcu, 0xd1u, 0x70u, 0x47u, 0xe0u, 0x03u, 0x00u, 0x08u, 0xf8u, 0xb5u, 0x04u, 0x00u, 0x0fu, 0x00u, 0x16u, 0x00u, 0x1du, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xe4u, 0xffu, 0x04u, 0x28u, 0xfau, 0xd8u, 0xe0u, 0x21u, 0x07u, 0x4bu, 0xc9u, 0x05u, 0x1bu, 0x68u, 0x0fu, 0x43u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x17u, 0x60u, 0xdau, 0x68u, 0xa2u, 0x18u, - 0x16u, 0x60u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0x25u, 0x60u, 0xf8u, 0xbdu, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, + 0x16u, 0x60u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0x25u, 0x60u, 0xf8u, 0xbdu, 0xc0u, 0x46u, 0xe0u, 0x03u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x04u, 0x00u, 0x0du, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xcau, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x03u, 0x4bu, 0x2du, 0x06u, 0x1bu, 0x68u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0x25u, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u, - 0xd0u, 0x03u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xb9u, 0xffu, 0x06u, 0x28u, + 0xe0u, 0x03u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xb9u, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x04u, 0x4bu, 0x1bu, 0x68u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0xc8u, 0x23u, 0xdbu, 0x05u, 0x23u, 0x60u, - 0x10u, 0xbdu, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, + 0x10u, 0xbdu, 0xc0u, 0x46u, 0xe0u, 0x03u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa7u, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x04u, 0x4bu, 0x1bu, 0x68u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0xcau, 0x23u, - 0xdbu, 0x05u, 0x23u, 0x60u, 0x10u, 0xbdu, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x05u, 0x00u, + 0xdbu, 0x05u, 0x23u, 0x60u, 0x10u, 0xbdu, 0xc0u, 0x46u, 0xe0u, 0x03u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x05u, 0x00u, 0x0cu, 0x00u, 0x16u, 0x00u, 0x28u, 0x00u, 0xffu, 0xf7u, 0x93u, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x05u, 0x4bu, 0x24u, 0x02u, 0x1bu, 0x68u, 0xdbu, 0x68u, 0xedu, 0x18u, 0xccu, 0x23u, 0xdbu, 0x05u, 0x1eu, 0x43u, 0x34u, 0x43u, - 0x2cu, 0x60u, 0x70u, 0xbdu, 0xd0u, 0x03u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x05u, 0x00u, 0x0cu, 0x00u, 0x16u, 0x00u, + 0x2cu, 0x60u, 0x70u, 0xbdu, 0xe0u, 0x03u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x05u, 0x00u, 0x0cu, 0x00u, 0x16u, 0x00u, 0x28u, 0x00u, 0xffu, 0xf7u, 0x7du, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x05u, 0x4bu, 0x24u, 0x02u, 0x1bu, 0x68u, 0xdbu, 0x68u, 0xedu, 0x18u, 0xd0u, 0x23u, 0xdbu, 0x05u, 0x1eu, 0x43u, 0x34u, 0x43u, 0x2cu, 0x60u, 0x70u, 0xbdu, - 0xd0u, 0x03u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x04u, 0x00u, 0x0du, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x68u, 0xffu, + 0xe0u, 0x03u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x04u, 0x00u, 0x0du, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x68u, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0xceu, 0x21u, 0x04u, 0x4bu, 0xc9u, 0x05u, 0x1bu, 0x68u, 0x29u, 0x43u, 0xdbu, 0x68u, - 0xe4u, 0x18u, 0x21u, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, 0x00u, 0xb5u, 0x06u, 0x2au, - 0x68u, 0xd8u, 0x10u, 0x00u, 0x8bu, 0x60u, 0x01u, 0xf0u, 0xc3u, 0xfdu, 0x04u, 0x1fu, 0x12u, 0x3bu, 0x2fu, 0x49u, + 0xe4u, 0x18u, 0x21u, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u, 0xe0u, 0x03u, 0x00u, 0x08u, 0x00u, 0xb5u, 0x06u, 0x2au, + 0x68u, 0xd8u, 0x10u, 0x00u, 0x8bu, 0x60u, 0x01u, 0xf0u, 0xc7u, 0xfdu, 0x04u, 0x1fu, 0x12u, 0x3bu, 0x2fu, 0x49u, 0x57u, 0x00u, 0x40u, 0x33u, 0x0bu, 0x61u, 0x69u, 0x23u, 0x4bu, 0x60u, 0x2fu, 0x4bu, 0x00u, 0x20u, 0xcbu, 0x62u, 0x40u, 0x23u, 0xcbu, 0x60u, 0x2cu, 0x3bu, 0x08u, 0x60u, 0x4bu, 0x61u, 0x4bu, 0x62u, 0x00u, 0xbdu, 0x40u, 0x33u, 0x0bu, 0x61u, 0x02u, 0x23u, 0x0bu, 0x60u, 0x68u, 0x33u, 0x4bu, 0x60u, 0x28u, 0x4bu, 0xcbu, 0x62u, 0x40u, 0x23u, @@ -1348,9 +1348,9 @@ const uint8_t cy_m0p_image[] = { 0x05u, 0x23u, 0x0bu, 0x60u, 0x66u, 0x33u, 0x4bu, 0x60u, 0x10u, 0x4bu, 0xcbu, 0x62u, 0x80u, 0x23u, 0xcbu, 0x60u, 0x40u, 0x3bu, 0x4bu, 0x61u, 0x20u, 0x3bu, 0xd4u, 0xe7u, 0x80u, 0x33u, 0x0bu, 0x61u, 0x06u, 0x23u, 0x0bu, 0x60u, 0x65u, 0x33u, 0x4bu, 0x60u, 0x0au, 0x4bu, 0xcbu, 0x62u, 0x80u, 0x23u, 0xcbu, 0x60u, 0x40u, 0x3bu, 0x4bu, 0x61u, - 0x24u, 0x3bu, 0xc6u, 0xe7u, 0x07u, 0x48u, 0xa9u, 0xe7u, 0x2cu, 0x7bu, 0x00u, 0x10u, 0x60u, 0x7bu, 0x00u, 0x10u, - 0x40u, 0x7bu, 0x00u, 0x10u, 0xc0u, 0x7bu, 0x00u, 0x10u, 0x80u, 0x7bu, 0x00u, 0x10u, 0x40u, 0x7cu, 0x00u, 0x10u, - 0x00u, 0x7cu, 0x00u, 0x10u, 0x0bu, 0x00u, 0x32u, 0x00u, 0x10u, 0xb5u, 0x00u, 0x29u, 0x01u, 0xd1u, 0x07u, 0x48u, + 0x24u, 0x3bu, 0xc6u, 0xe7u, 0x07u, 0x48u, 0xa9u, 0xe7u, 0x34u, 0x7bu, 0x00u, 0x10u, 0x68u, 0x7bu, 0x00u, 0x10u, + 0x48u, 0x7bu, 0x00u, 0x10u, 0xc8u, 0x7bu, 0x00u, 0x10u, 0x88u, 0x7bu, 0x00u, 0x10u, 0x48u, 0x7cu, 0x00u, 0x10u, + 0x08u, 0x7cu, 0x00u, 0x10u, 0x0bu, 0x00u, 0x32u, 0x00u, 0x10u, 0xb5u, 0x00u, 0x29u, 0x01u, 0xd1u, 0x07u, 0x48u, 0x10u, 0xbdu, 0x00u, 0x24u, 0x4bu, 0x69u, 0x8cu, 0x62u, 0x0cu, 0x62u, 0xa3u, 0x42u, 0xf7u, 0xd0u, 0xcau, 0x6au, 0x9bu, 0xb2u, 0x09u, 0x69u, 0xfeu, 0xf7u, 0x40u, 0xfeu, 0x20u, 0x00u, 0xf1u, 0xe7u, 0x0bu, 0x00u, 0x32u, 0x00u, 0xf0u, 0xb5u, 0x85u, 0xb0u, 0x04u, 0x00u, 0x0du, 0x1eu, 0x03u, 0x92u, 0x01u, 0x93u, 0x00u, 0xd1u, 0x95u, 0xe0u, @@ -1373,7 +1373,7 @@ const uint8_t cy_m0p_image[] = { 0xffu, 0xf7u, 0x92u, 0xfeu, 0x00u, 0x27u, 0x38u, 0x00u, 0x05u, 0xb0u, 0xf0u, 0xbdu, 0x02u, 0x9bu, 0x31u, 0x00u, 0x9fu, 0x1bu, 0x3au, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x99u, 0xfeu, 0x69u, 0x68u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x5fu, 0xfeu, 0x01u, 0x9bu, 0x00u, 0x26u, 0xdbu, 0x1bu, 0x01u, 0x93u, 0xb8u, 0xe7u, 0x02u, 0x4fu, 0xeau, 0xe7u, - 0xd0u, 0x03u, 0x00u, 0x08u, 0x08u, 0x00u, 0x00u, 0x71u, 0x0bu, 0x00u, 0x32u, 0x00u, 0xf0u, 0xb5u, 0x85u, 0xb0u, + 0xe0u, 0x03u, 0x00u, 0x08u, 0x08u, 0x00u, 0x00u, 0x71u, 0x0bu, 0x00u, 0x32u, 0x00u, 0xf0u, 0xb5u, 0x85u, 0xb0u, 0x04u, 0x00u, 0x0du, 0x1eu, 0x02u, 0x92u, 0x00u, 0xd1u, 0x7bu, 0xe0u, 0x00u, 0x2au, 0x00u, 0xd1u, 0x78u, 0xe0u, 0x8bu, 0x6au, 0x0au, 0x6au, 0x00u, 0x93u, 0x53u, 0x0fu, 0x03u, 0x93u, 0x70u, 0x23u, 0xceu, 0x68u, 0xd7u, 0x00u, 0x01u, 0x93u, 0x80u, 0x2eu, 0x01u, 0xd0u, 0x38u, 0x3bu, 0x01u, 0x93u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x4au, 0xfeu, @@ -1397,7 +1397,7 @@ const uint8_t cy_m0p_image[] = { 0xffu, 0xf7u, 0xc0u, 0xfdu, 0x28u, 0x00u, 0xffu, 0xf7u, 0x85u, 0xfdu, 0x00u, 0x20u, 0x70u, 0xbdu, 0x01u, 0x48u, 0xfcu, 0xe7u, 0xc0u, 0x46u, 0x0bu, 0x00u, 0x32u, 0x00u, 0xf0u, 0xb5u, 0x04u, 0x00u, 0xbfu, 0xb0u, 0x01u, 0x93u, 0x44u, 0xabu, 0x1fu, 0x78u, 0x0du, 0x00u, 0x16u, 0x00u, 0x00u, 0x21u, 0xc0u, 0x22u, 0x0eu, 0xa8u, 0x01u, 0xf0u, - 0xc0u, 0xfdu, 0x30u, 0x22u, 0x00u, 0x21u, 0x02u, 0xa8u, 0x01u, 0xf0u, 0xbbu, 0xfdu, 0x0eu, 0xabu, 0x3au, 0x00u, + 0xc4u, 0xfdu, 0x30u, 0x22u, 0x00u, 0x21u, 0x02u, 0xa8u, 0x01u, 0xf0u, 0xbfu, 0xfdu, 0x0eu, 0xabu, 0x3au, 0x00u, 0x02u, 0xa9u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x02u, 0xfeu, 0x00u, 0x28u, 0x18u, 0xd1u, 0x02u, 0xa9u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x7au, 0xfeu, 0x00u, 0x28u, 0x12u, 0xd1u, 0x33u, 0x00u, 0x2au, 0x00u, 0x02u, 0xa9u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x86u, 0xfeu, 0x00u, 0x28u, 0x0au, 0xd1u, 0x01u, 0x9au, 0x02u, 0xa9u, 0x20u, 0x00u, 0xffu, 0xf7u, @@ -1409,7 +1409,7 @@ const uint8_t cy_m0p_image[] = { 0x60u, 0x21u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0x5eu, 0xfbu, 0x40u, 0x21u, 0x0au, 0x4bu, 0x1au, 0x68u, 0x13u, 0x68u, 0xe3u, 0x18u, 0x18u, 0x68u, 0x08u, 0x40u, 0xfcu, 0xd1u, 0xd3u, 0x69u, 0xe3u, 0x18u, 0x1au, 0x68u, 0x04u, 0x9bu, 0x1au, 0x60u, 0xa1u, 0x23u, 0x9bu, 0x00u, 0xe0u, 0x50u, 0x70u, 0xbdu, 0xc0u, 0x46u, 0x00u, 0x00u, 0x03u, 0x31u, - 0x01u, 0x00u, 0x01u, 0x00u, 0xd0u, 0x03u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x04u, 0x00u, 0xa0u, 0x20u, 0x1cu, 0x4du, + 0x01u, 0x00u, 0x01u, 0x00u, 0xe0u, 0x03u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x04u, 0x00u, 0xa0u, 0x20u, 0x1cu, 0x4du, 0x80u, 0x00u, 0x25u, 0x50u, 0x3fu, 0x25u, 0x04u, 0x30u, 0xb0u, 0x26u, 0x25u, 0x50u, 0x00u, 0x25u, 0xb6u, 0x00u, 0xa5u, 0x51u, 0x08u, 0x36u, 0xa5u, 0x51u, 0x17u, 0x4fu, 0x08u, 0x36u, 0x01u, 0x35u, 0xa5u, 0x51u, 0x10u, 0x36u, 0xa7u, 0x51u, 0x40u, 0x3eu, 0xa1u, 0x51u, 0xa9u, 0x21u, 0x89u, 0x00u, 0x62u, 0x50u, 0xa2u, 0x22u, 0x92u, 0x00u, @@ -1417,20 +1417,20 @@ const uint8_t cy_m0p_image[] = { 0x0du, 0x4bu, 0x1du, 0x68u, 0x2bu, 0x68u, 0xe1u, 0x18u, 0x03u, 0x00u, 0x08u, 0x68u, 0xe6u, 0x58u, 0x16u, 0x42u, 0x07u, 0xd0u, 0xc0u, 0x0fu, 0xf9u, 0xd1u, 0xebu, 0x69u, 0xe3u, 0x18u, 0x1au, 0x68u, 0x05u, 0x9bu, 0x1au, 0x60u, 0x00u, 0xe0u, 0x06u, 0x48u, 0xa1u, 0x23u, 0x00u, 0x22u, 0x9bu, 0x00u, 0xe2u, 0x50u, 0xf0u, 0xbdu, 0xc0u, 0x46u, - 0x00u, 0x00u, 0x03u, 0x31u, 0x01u, 0x00u, 0x01u, 0x00u, 0xd0u, 0x03u, 0x00u, 0x08u, 0x01u, 0x00u, 0x32u, 0x00u, + 0x00u, 0x00u, 0x03u, 0x31u, 0x01u, 0x00u, 0x01u, 0x00u, 0xe0u, 0x03u, 0x00u, 0x08u, 0x01u, 0x00u, 0x32u, 0x00u, 0x07u, 0x4bu, 0x89u, 0x00u, 0x1au, 0x68u, 0x93u, 0x6bu, 0x12u, 0x69u, 0xc3u, 0x18u, 0x89u, 0x18u, 0x08u, 0x18u, 0x1bu, 0x68u, 0x00u, 0x68u, 0x80u, 0x00u, 0x80u, 0x0cu, 0x80u, 0x00u, 0xc0u, 0x18u, 0x70u, 0x47u, 0xc0u, 0x46u, - 0xd0u, 0x03u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x06u, 0x4cu, 0x24u, 0x68u, 0x29u, 0x34u, 0x24u, 0x78u, 0x1fu, 0x2cu, + 0xe0u, 0x03u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x06u, 0x4cu, 0x24u, 0x68u, 0x29u, 0x34u, 0x24u, 0x78u, 0x1fu, 0x2cu, 0x02u, 0xd8u, 0xfeu, 0xf7u, 0x47u, 0xfbu, 0x10u, 0xbdu, 0xfeu, 0xf7u, 0x16u, 0xfcu, 0xfbu, 0xe7u, 0xc0u, 0x46u, - 0xdcu, 0x05u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x1fu, 0x24u, 0x95u, 0x00u, 0x13u, 0x05u, 0x09u, 0x4au, 0xadu, 0x0cu, + 0xecu, 0x05u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x1fu, 0x24u, 0x95u, 0x00u, 0x13u, 0x05u, 0x09u, 0x4au, 0xadu, 0x0cu, 0x12u, 0x68u, 0x89u, 0x06u, 0x29u, 0x32u, 0x12u, 0x78u, 0x1bu, 0x0du, 0x94u, 0x42u, 0xa4u, 0x41u, 0x64u, 0x42u, 0x0cu, 0x34u, 0xa5u, 0x40u, 0x0bu, 0x43u, 0x2bu, 0x43u, 0x80u, 0x22u, 0x00u, 0x21u, 0xfeu, 0xf7u, 0x6cu, 0xf8u, - 0x70u, 0xbdu, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x09u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xc0u, 0x18u, + 0x70u, 0xbdu, 0xc0u, 0x46u, 0xecu, 0x05u, 0x00u, 0x08u, 0x09u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xc0u, 0x18u, 0x08u, 0x4bu, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x04u, 0xd8u, 0x80u, 0x23u, 0x02u, 0x68u, 0x1au, 0x42u, 0xfcu, 0xd1u, 0x70u, 0x47u, 0x03u, 0x68u, 0x00u, 0x2bu, 0xfcu, 0xd1u, 0xfau, 0xe7u, 0xc0u, 0x46u, - 0xd0u, 0x03u, 0x00u, 0x08u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x13u, 0x00u, 0x06u, 0x4au, 0x14u, 0x68u, + 0xe0u, 0x03u, 0x00u, 0x08u, 0xecu, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x13u, 0x00u, 0x06u, 0x4au, 0x14u, 0x68u, 0x29u, 0x34u, 0x22u, 0x78u, 0x1fu, 0x2au, 0x03u, 0xd8u, 0x00u, 0x22u, 0xfeu, 0xf7u, 0x21u, 0xfbu, 0x10u, 0xbdu, - 0x00u, 0x22u, 0xfeu, 0xf7u, 0x0fu, 0xfcu, 0xfau, 0xe7u, 0xdcu, 0x05u, 0x00u, 0x08u, 0xf7u, 0xb5u, 0x04u, 0x00u, + 0x00u, 0x22u, 0xfeu, 0xf7u, 0x0fu, 0xfcu, 0xfau, 0xe7u, 0xecu, 0x05u, 0x00u, 0x08u, 0xf7u, 0xb5u, 0x04u, 0x00u, 0x00u, 0x93u, 0x0eu, 0x00u, 0x01u, 0x92u, 0xffu, 0xf7u, 0xcfu, 0xffu, 0x1bu, 0x4bu, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x2du, 0xd8u, 0x19u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x69u, 0xe3u, 0x18u, 0x1fu, 0x68u, 0x5du, 0x68u, 0x31u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x83u, 0xffu, 0x06u, 0x00u, 0x00u, 0x9au, 0x01u, 0x00u, @@ -1438,47 +1438,47 @@ const uint8_t cy_m0p_image[] = { 0x01u, 0x9au, 0x07u, 0x33u, 0xdbu, 0x08u, 0x9bu, 0xb2u, 0x31u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x82u, 0xffu, 0x09u, 0x4bu, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x09u, 0xd8u, 0x3au, 0x00u, 0x00u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x87u, 0xffu, 0x2au, 0x00u, 0x01u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x82u, 0xffu, - 0xf7u, 0xbdu, 0x00u, 0x25u, 0x2fu, 0x00u, 0xd4u, 0xe7u, 0xdcu, 0x05u, 0x00u, 0x08u, 0xd0u, 0x03u, 0x00u, 0x08u, + 0xf7u, 0xbdu, 0x00u, 0x25u, 0x2fu, 0x00u, 0xd4u, 0xe7u, 0xecu, 0x05u, 0x00u, 0x08u, 0xe0u, 0x03u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x85u, 0xb0u, 0x03u, 0x93u, 0x04u, 0x00u, 0x01u, 0x91u, 0x02u, 0x92u, 0xffu, 0xf7u, 0x8cu, 0xffu, 0x16u, 0x4eu, 0x33u, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x23u, 0xd8u, 0x14u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x69u, 0xe3u, 0x18u, 0x1fu, 0x68u, 0x5du, 0x68u, 0x02u, 0x99u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x40u, 0xffu, 0x03u, 0x9bu, 0x02u, 0x00u, 0x07u, 0x33u, 0xdbu, 0x08u, 0x9bu, 0xb2u, 0x01u, 0x99u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x49u, 0xffu, 0x33u, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x09u, 0xd8u, 0x3au, 0x00u, 0x00u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x4fu, 0xffu, 0x2au, 0x00u, 0x01u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x4au, 0xffu, - 0x05u, 0xb0u, 0xf0u, 0xbdu, 0x00u, 0x25u, 0x2fu, 0x00u, 0xdeu, 0xe7u, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, - 0xd0u, 0x03u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, 0x0bu, 0x00u, 0x3fu, 0x22u, 0x00u, 0x21u, 0xfdu, 0xf7u, + 0x05u, 0xb0u, 0xf0u, 0xbdu, 0x00u, 0x25u, 0x2fu, 0x00u, 0xdeu, 0xe7u, 0xc0u, 0x46u, 0xecu, 0x05u, 0x00u, 0x08u, + 0xe0u, 0x03u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, 0x0bu, 0x00u, 0x3fu, 0x22u, 0x00u, 0x21u, 0xfdu, 0xf7u, 0xbbu, 0xffu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x50u, 0xffu, 0x03u, 0x4bu, 0x1bu, 0x68u, 0xdbu, 0x6bu, 0xe4u, 0x18u, - 0x20u, 0x68u, 0x40u, 0x07u, 0xc0u, 0x0fu, 0x10u, 0xbdu, 0xd0u, 0x03u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, + 0x20u, 0x68u, 0x40u, 0x07u, 0xc0u, 0x0fu, 0x10u, 0xbdu, 0xe0u, 0x03u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, 0x13u, 0x01u, 0x0bu, 0x43u, 0x3du, 0x22u, 0x00u, 0x21u, 0xfdu, 0xf7u, 0xa6u, 0xffu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x3bu, 0xffu, 0x04u, 0x4bu, 0x1bu, 0x68u, 0xdbu, 0x6bu, 0xe4u, 0x18u, 0x20u, 0x68u, 0x40u, 0x07u, 0xc0u, 0x0fu, - 0x10u, 0xbdu, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, 0x13u, 0x01u, 0x0bu, 0x43u, + 0x10u, 0xbdu, 0xc0u, 0x46u, 0xe0u, 0x03u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, 0x13u, 0x01u, 0x0bu, 0x43u, 0x3du, 0x22u, 0x00u, 0x21u, 0xfdu, 0xf7u, 0x90u, 0xffu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x25u, 0xffu, 0x04u, 0x4bu, 0x1bu, 0x68u, 0xdbu, 0x6bu, 0xe4u, 0x18u, 0x01u, 0x23u, 0x20u, 0x68u, 0x18u, 0x40u, 0x10u, 0xbdu, 0xc0u, 0x46u, - 0xd0u, 0x03u, 0x00u, 0x08u, 0x08u, 0x4bu, 0x10u, 0xb5u, 0x1au, 0x68u, 0x8bu, 0x00u, 0x12u, 0x69u, 0x9bu, 0x18u, + 0xe0u, 0x03u, 0x00u, 0x08u, 0x08u, 0x4bu, 0x10u, 0xb5u, 0x1au, 0x68u, 0x8bu, 0x00u, 0x12u, 0x69u, 0x9bu, 0x18u, 0xc3u, 0x18u, 0x1cu, 0x68u, 0xffu, 0xf7u, 0xd4u, 0xfeu, 0xe1u, 0x04u, 0xc9u, 0x0cu, 0x08u, 0x31u, 0xc9u, 0x08u, - 0xfeu, 0xf7u, 0x3eu, 0xf9u, 0x10u, 0xbdu, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, 0x00u, 0x28u, 0x07u, 0xdbu, + 0xfeu, 0xf7u, 0x3eu, 0xf9u, 0x10u, 0xbdu, 0xc0u, 0x46u, 0xe0u, 0x03u, 0x00u, 0x08u, 0x00u, 0x28u, 0x07u, 0xdbu, 0x1fu, 0x23u, 0xc0u, 0x22u, 0x18u, 0x40u, 0x1eu, 0x3bu, 0x83u, 0x40u, 0x02u, 0x49u, 0x52u, 0x00u, 0x8bu, 0x50u, 0x70u, 0x47u, 0xc0u, 0x46u, 0x00u, 0xe1u, 0x00u, 0xe0u, 0x30u, 0xb5u, 0xf8u, 0x25u, 0x0fu, 0x4bu, 0x10u, 0x4au, 0x18u, 0x68u, 0x14u, 0x68u, 0x43u, 0x6au, 0x22u, 0x6cu, 0x6du, 0x03u, 0x9au, 0x18u, 0x11u, 0x68u, 0x29u, 0x40u, 0x10u, 0xd0u, 0x11u, 0x60u, 0x22u, 0x6cu, 0x9bu, 0x18u, 0x1bu, 0x68u, 0x0au, 0x4bu, 0x1au, 0x68u, 0x53u, 0x1cu, 0xd9u, 0x7fu, 0x00u, 0x29u, 0x07u, 0xd1u, 0x41u, 0x6au, 0x08u, 0x6au, 0x49u, 0x6au, 0x50u, 0x62u, 0x91u, 0x62u, - 0x01u, 0x22u, 0xdau, 0x77u, 0x30u, 0xbdu, 0x00u, 0x22u, 0xfbu, 0xe7u, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, - 0xd0u, 0x03u, 0x00u, 0x08u, 0xdcu, 0x03u, 0x00u, 0x08u, 0x00u, 0x22u, 0x70u, 0xb5u, 0x04u, 0x00u, 0x03u, 0x68u, + 0x01u, 0x22u, 0xdau, 0x77u, 0x30u, 0xbdu, 0x00u, 0x22u, 0xfbu, 0xe7u, 0xc0u, 0x46u, 0xecu, 0x05u, 0x00u, 0x08u, + 0xe0u, 0x03u, 0x00u, 0x08u, 0xecu, 0x03u, 0x00u, 0x08u, 0x00u, 0x22u, 0x70u, 0xb5u, 0x04u, 0x00u, 0x03u, 0x68u, 0x0du, 0x00u, 0x0bu, 0x60u, 0x43u, 0x68u, 0x4bu, 0x60u, 0x83u, 0x69u, 0x8bu, 0x60u, 0xc3u, 0x69u, 0xcbu, 0x60u, 0x4bu, 0x1cu, 0xdau, 0x77u, 0x03u, 0x8cu, 0x0bu, 0x82u, 0x03u, 0x8du, 0x0bu, 0x83u, 0xfdu, 0xf7u, 0xceu, 0xffu, - 0xa1u, 0x69u, 0x00u, 0x29u, 0x00u, 0xd1u, 0x20u, 0x49u, 0x20u, 0x00u, 0x20u, 0x30u, 0x00u, 0xf0u, 0x6eu, 0xfeu, + 0xa1u, 0x69u, 0x00u, 0x29u, 0x00u, 0xd1u, 0x20u, 0x49u, 0x20u, 0x00u, 0x20u, 0x30u, 0x00u, 0xf0u, 0x72u, 0xfeu, 0x20u, 0x22u, 0xa3u, 0x5eu, 0x00u, 0x2bu, 0x06u, 0xdbu, 0x1fu, 0x22u, 0x13u, 0x40u, 0x1eu, 0x3au, 0x9au, 0x40u, 0x13u, 0x00u, 0x1au, 0x4au, 0x13u, 0x60u, 0x1au, 0x4eu, 0x63u, 0x68u, 0x32u, 0x68u, 0x80u, 0x33u, 0x12u, 0x6au, 0x5bu, 0x01u, 0x9bu, 0x18u, 0x80u, 0x22u, 0x21u, 0x68u, 0x52u, 0x02u, 0x8au, 0x40u, 0xe1u, 0x69u, 0x9au, 0x60u, - 0x00u, 0x29u, 0x00u, 0xd1u, 0x13u, 0x49u, 0x20u, 0x00u, 0x28u, 0x30u, 0x00u, 0xf0u, 0x4fu, 0xfeu, 0x28u, 0x23u, + 0x00u, 0x29u, 0x00u, 0xd1u, 0x13u, 0x49u, 0x20u, 0x00u, 0x28u, 0x30u, 0x00u, 0xf0u, 0x53u, 0xfeu, 0x28u, 0x23u, 0xe0u, 0x5eu, 0xffu, 0xf7u, 0x8bu, 0xffu, 0x28u, 0x22u, 0xa3u, 0x5eu, 0x00u, 0x2bu, 0x06u, 0xdbu, 0x1fu, 0x22u, 0x13u, 0x40u, 0x1eu, 0x3au, 0x9au, 0x40u, 0x13u, 0x00u, 0x08u, 0x4au, 0x13u, 0x60u, 0x0au, 0x4au, 0x33u, 0x68u, 0x12u, 0x68u, 0x5bu, 0x6au, 0x92u, 0x6cu, 0x00u, 0x20u, 0x9bu, 0x18u, 0xf8u, 0x22u, 0x52u, 0x03u, 0x1au, 0x60u, 0x06u, 0x4bu, 0x1du, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u, 0xe1u, 0x5eu, 0x00u, 0x10u, 0x00u, 0xe1u, 0x00u, 0xe0u, - 0xdcu, 0x05u, 0x00u, 0x08u, 0x79u, 0x59u, 0x00u, 0x10u, 0xd0u, 0x03u, 0x00u, 0x08u, 0xdcu, 0x03u, 0x00u, 0x08u, + 0xecu, 0x05u, 0x00u, 0x08u, 0x79u, 0x59u, 0x00u, 0x10u, 0xe0u, 0x03u, 0x00u, 0x08u, 0xecu, 0x03u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x07u, 0x4bu, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1au, 0x78u, 0x06u, 0x4bu, 0x1fu, 0x2au, 0x04u, 0xd8u, 0x05u, 0x4au, 0x1au, 0x60u, 0xffu, 0xf7u, 0x90u, 0xffu, 0x10u, 0xbdu, 0x04u, 0x4au, 0xf9u, 0xe7u, 0xc0u, 0x46u, - 0xdcu, 0x05u, 0x00u, 0x08u, 0xd8u, 0x03u, 0x00u, 0x08u, 0x80u, 0x7cu, 0x00u, 0x10u, 0xd8u, 0x7cu, 0x00u, 0x10u, + 0xecu, 0x05u, 0x00u, 0x08u, 0xe8u, 0x03u, 0x00u, 0x08u, 0x88u, 0x7cu, 0x00u, 0x10u, 0xe0u, 0x7cu, 0x00u, 0x10u, 0xf0u, 0xb5u, 0xb4u, 0x4bu, 0x85u, 0xb0u, 0x1cu, 0x68u, 0x00u, 0x2cu, 0x1eu, 0xd0u, 0xb2u, 0x4bu, 0xb3u, 0x4du, 0x63u, 0x60u, 0x2bu, 0x68u, 0x5fu, 0x6au, 0x23u, 0x78u, 0x01u, 0x2bu, 0x18u, 0xd1u, 0x38u, 0x00u, 0xfeu, 0xf7u, 0x21u, 0xf8u, 0x60u, 0x60u, 0x00u, 0x23u, 0xabu, 0x4au, 0xe1u, 0x69u, 0x13u, 0x60u, 0x2bu, 0x68u, 0x1au, 0x00u, @@ -1524,8 +1524,8 @@ const uint8_t cy_m0p_image[] = { 0x40u, 0x6au, 0x52u, 0x69u, 0xb0u, 0x47u, 0x99u, 0xe7u, 0x96u, 0x69u, 0xedu, 0xe7u, 0xd6u, 0x69u, 0x28u, 0x68u, 0x00u, 0x2eu, 0x00u, 0xd1u, 0xedu, 0xe6u, 0xa1u, 0x6au, 0x03u, 0x91u, 0x8bu, 0x6au, 0x02u, 0x93u, 0x4bu, 0x6au, 0x01u, 0x93u, 0x0bu, 0x6au, 0x00u, 0x93u, 0xcbu, 0x69u, 0x8au, 0x69u, 0x40u, 0x6au, 0x49u, 0x69u, 0xb0u, 0x47u, - 0x84u, 0xe7u, 0xc0u, 0x46u, 0xe0u, 0x03u, 0x00u, 0x08u, 0x09u, 0x00u, 0x32u, 0x00u, 0xdcu, 0x05u, 0x00u, 0x08u, - 0xd0u, 0x03u, 0x00u, 0x08u, 0x0au, 0x00u, 0x32u, 0x00u, 0xd8u, 0x03u, 0x00u, 0x08u, 0xdcu, 0x03u, 0x00u, 0x08u, + 0x84u, 0xe7u, 0xc0u, 0x46u, 0xf0u, 0x03u, 0x00u, 0x08u, 0x09u, 0x00u, 0x32u, 0x00u, 0xecu, 0x05u, 0x00u, 0x08u, + 0xe0u, 0x03u, 0x00u, 0x08u, 0x0au, 0x00u, 0x32u, 0x00u, 0xe8u, 0x03u, 0x00u, 0x08u, 0xecu, 0x03u, 0x00u, 0x08u, 0x01u, 0x00u, 0x32u, 0x00u, 0x56u, 0x6au, 0x28u, 0x68u, 0x00u, 0x2eu, 0x00u, 0xd1u, 0xc9u, 0xe6u, 0xa1u, 0x6au, 0x0bu, 0x7bu, 0x00u, 0x93u, 0x8bu, 0x68u, 0x4au, 0x68u, 0x40u, 0x6au, 0x09u, 0x68u, 0xb0u, 0x47u, 0x65u, 0xe7u, 0x96u, 0x6au, 0x28u, 0x68u, 0x00u, 0x2eu, 0x00u, 0xd1u, 0xbbu, 0xe6u, 0xa1u, 0x6au, 0x0bu, 0x7bu, 0x02u, 0x93u, @@ -1549,10 +1549,10 @@ const uint8_t cy_m0p_image[] = { 0x29u, 0x6au, 0x80u, 0x33u, 0x5bu, 0x01u, 0xcbu, 0x18u, 0xdeu, 0x68u, 0x82u, 0x40u, 0x36u, 0x0cu, 0xb2u, 0x42u, 0x11u, 0xd1u, 0x12u, 0x04u, 0x1au, 0x60u, 0xacu, 0x35u, 0x1bu, 0x68u, 0x2bu, 0x88u, 0x58u, 0x43u, 0x40u, 0x18u, 0x07u, 0x49u, 0x00u, 0xf0u, 0xb5u, 0xf8u, 0x00u, 0x28u, 0x05u, 0xd1u, 0x23u, 0x68u, 0x9bu, 0x68u, 0x00u, 0x2bu, - 0x01u, 0xd1u, 0xffu, 0xf7u, 0xcdu, 0xfdu, 0x70u, 0xbdu, 0xdcu, 0x03u, 0x00u, 0x08u, 0xdcu, 0x05u, 0x00u, 0x08u, - 0xe0u, 0x03u, 0x00u, 0x08u, 0x01u, 0x4bu, 0x18u, 0x60u, 0x70u, 0x47u, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, + 0x01u, 0xd1u, 0xffu, 0xf7u, 0xcdu, 0xfdu, 0x70u, 0xbdu, 0xecu, 0x03u, 0x00u, 0x08u, 0xecu, 0x05u, 0x00u, 0x08u, + 0xf0u, 0x03u, 0x00u, 0x08u, 0x01u, 0x4bu, 0x18u, 0x60u, 0x70u, 0x47u, 0xc0u, 0x46u, 0xecu, 0x05u, 0x00u, 0x08u, 0x04u, 0x4bu, 0x1bu, 0x68u, 0x1au, 0x00u, 0xacu, 0x32u, 0x12u, 0x88u, 0x1bu, 0x6au, 0x50u, 0x43u, 0xc0u, 0x18u, - 0x70u, 0x47u, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x1du, 0x4bu, 0x98u, 0x42u, 0x0fu, 0xd0u, 0x10u, 0xd8u, + 0x70u, 0x47u, 0xc0u, 0x46u, 0xecu, 0x05u, 0x00u, 0x08u, 0x1du, 0x4bu, 0x98u, 0x42u, 0x0fu, 0xd0u, 0x10u, 0xd8u, 0x40u, 0x28u, 0x2fu, 0xd0u, 0x05u, 0xd8u, 0x00u, 0x28u, 0x30u, 0xd0u, 0x10u, 0x28u, 0x28u, 0xd0u, 0x19u, 0x48u, 0x1eu, 0xe0u, 0x80u, 0x28u, 0x28u, 0xd0u, 0x80u, 0x23u, 0x5bu, 0x00u, 0x98u, 0x42u, 0xf7u, 0xd1u, 0x14u, 0x48u, 0x16u, 0xe0u, 0x15u, 0x4bu, 0x98u, 0x42u, 0x14u, 0xd0u, 0x08u, 0xd8u, 0xa0u, 0x23u, 0x1bu, 0x06u, 0x98u, 0x42u, @@ -1566,32 +1566,32 @@ const uint8_t cy_m0p_image[] = { 0x05u, 0x00u, 0x52u, 0x00u, 0x10u, 0xb5u, 0x00u, 0x20u, 0xffu, 0xf7u, 0x9au, 0xffu, 0x0au, 0x4bu, 0x1cu, 0x68u, 0x23u, 0x00u, 0xb0u, 0x33u, 0x1bu, 0x68u, 0xc0u, 0x18u, 0x03u, 0x68u, 0x00u, 0x2bu, 0x0au, 0xdbu, 0x07u, 0x4bu, 0x18u, 0x68u, 0xffu, 0xf7u, 0x99u, 0xffu, 0x01u, 0x22u, 0x63u, 0x68u, 0x9au, 0x60u, 0x9au, 0x68u, 0x00u, 0x2au, - 0xfcu, 0xd1u, 0x10u, 0xbdu, 0x02u, 0x48u, 0xfcu, 0xe7u, 0xdcu, 0x05u, 0x00u, 0x08u, 0xe4u, 0x03u, 0x00u, 0x08u, + 0xfcu, 0xd1u, 0x10u, 0xbdu, 0x02u, 0x48u, 0xfcu, 0xe7u, 0xecu, 0x05u, 0x00u, 0x08u, 0xf4u, 0x03u, 0x00u, 0x08u, 0x02u, 0x00u, 0x50u, 0x00u, 0x06u, 0x4bu, 0x1bu, 0x68u, 0xb0u, 0x33u, 0x1bu, 0x68u, 0xc3u, 0x18u, 0x1bu, 0x68u, 0x00u, 0x2bu, 0x03u, 0xdau, 0x89u, 0xb2u, 0x41u, 0x60u, 0x00u, 0x20u, 0x70u, 0x47u, 0x01u, 0x48u, 0xfcu, 0xe7u, - 0xdcu, 0x05u, 0x00u, 0x08u, 0x01u, 0x00u, 0x8au, 0x00u, 0x03u, 0x68u, 0x00u, 0x2bu, 0x04u, 0xdau, 0x89u, 0xb2u, + 0xecu, 0x05u, 0x00u, 0x08u, 0x01u, 0x00u, 0x8au, 0x00u, 0x03u, 0x68u, 0x00u, 0x2bu, 0x04u, 0xdau, 0x89u, 0xb2u, 0xc2u, 0x60u, 0x81u, 0x60u, 0x00u, 0x20u, 0x70u, 0x47u, 0x00u, 0x48u, 0xfcu, 0xe7u, 0x01u, 0x00u, 0x8au, 0x00u, 0x06u, 0x4bu, 0x1bu, 0x68u, 0xb0u, 0x33u, 0x1bu, 0x68u, 0xc3u, 0x18u, 0x1bu, 0x68u, 0x00u, 0x2bu, 0x03u, 0xdau, - 0xc3u, 0x68u, 0x00u, 0x20u, 0x0bu, 0x60u, 0x70u, 0x47u, 0x01u, 0x48u, 0xfcu, 0xe7u, 0xdcu, 0x05u, 0x00u, 0x08u, + 0xc3u, 0x68u, 0x00u, 0x20u, 0x0bu, 0x60u, 0x70u, 0x47u, 0x01u, 0x48u, 0xfcu, 0xe7u, 0xecu, 0x05u, 0x00u, 0x08u, 0x01u, 0x00u, 0x8au, 0x00u, 0x02u, 0x4bu, 0x1au, 0x68u, 0x00u, 0x2au, 0x00u, 0xd1u, 0x18u, 0x60u, 0x70u, 0x47u, - 0xf8u, 0x03u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x2cu, 0x24u, 0x60u, 0x43u, 0x12u, 0x4cu, 0x1fu, 0x00u, 0x24u, 0x68u, + 0x08u, 0x04u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x2cu, 0x24u, 0x60u, 0x43u, 0x12u, 0x4cu, 0x1fu, 0x00u, 0x24u, 0x68u, 0x1eu, 0x0au, 0x20u, 0x18u, 0xffu, 0x24u, 0x27u, 0x40u, 0x34u, 0x40u, 0x0fu, 0x4eu, 0x1bu, 0x0cu, 0x35u, 0x68u, 0x07u, 0x60u, 0x2eu, 0x6au, 0x44u, 0x60u, 0x83u, 0x60u, 0xacu, 0x35u, 0x2du, 0x88u, 0x80u, 0x34u, 0x6fu, 0x43u, 0x64u, 0x01u, 0x34u, 0x19u, 0xbfu, 0x19u, 0x1eu, 0x04u, 0x33u, 0x43u, 0x07u, 0x61u, 0x44u, 0x61u, 0xa3u, 0x60u, 0x00u, 0x23u, 0x83u, 0x61u, 0x05u, 0x9bu, 0xc2u, 0x61u, 0x01u, 0x62u, 0x00u, 0x2bu, 0x01u, 0xd0u, 0x1bu, 0x88u, - 0x83u, 0x81u, 0xf0u, 0xbdu, 0xf8u, 0x03u, 0x00u, 0x08u, 0xdcu, 0x05u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x83u, 0x68u, + 0x83u, 0x81u, 0xf0u, 0xbdu, 0x08u, 0x04u, 0x00u, 0x08u, 0xecu, 0x05u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x83u, 0x68u, 0x85u, 0xb0u, 0x02u, 0xadu, 0x2bu, 0x80u, 0x15u, 0x4bu, 0x02u, 0x68u, 0x1bu, 0x68u, 0x06u, 0x6au, 0x9bu, 0x8eu, 0x47u, 0x6au, 0x9bu, 0x18u, 0x6bu, 0x80u, 0x43u, 0x68u, 0x00u, 0x95u, 0x82u, 0x6au, 0xc1u, 0x6au, 0x04u, 0x00u, 0x03u, 0x93u, 0x03u, 0x69u, 0xc0u, 0x68u, 0xffu, 0xf7u, 0xbdu, 0xffu, 0x00u, 0x21u, 0x3bu, 0x00u, 0x0au, 0x00u, - 0x00u, 0x91u, 0x30u, 0x00u, 0xffu, 0xf7u, 0xb6u, 0xffu, 0x21u, 0x6bu, 0x28u, 0x00u, 0x00u, 0xf0u, 0xc6u, 0xfau, + 0x00u, 0x91u, 0x30u, 0x00u, 0xffu, 0xf7u, 0xb6u, 0xffu, 0x21u, 0x6bu, 0x28u, 0x00u, 0x00u, 0xf0u, 0xcau, 0xfau, 0x00u, 0x22u, 0xabu, 0x5eu, 0x00u, 0x2bu, 0x06u, 0xdbu, 0x1fu, 0x22u, 0x13u, 0x40u, 0x1eu, 0x3au, 0x9au, 0x40u, - 0x13u, 0x00u, 0x03u, 0x4au, 0x13u, 0x60u, 0x05u, 0xb0u, 0xf0u, 0xbdu, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, + 0x13u, 0x00u, 0x03u, 0x4au, 0x13u, 0x60u, 0x05u, 0xb0u, 0xf0u, 0xbdu, 0xc0u, 0x46u, 0xecu, 0x05u, 0x00u, 0x08u, 0x00u, 0xe1u, 0x00u, 0xe0u, 0xf7u, 0xb5u, 0x2cu, 0x25u, 0x13u, 0x4cu, 0x68u, 0x43u, 0x26u, 0x68u, 0x69u, 0x43u, 0x34u, 0x18u, 0x25u, 0x69u, 0x01u, 0x93u, 0x71u, 0x18u, 0x00u, 0x2du, 0x19u, 0xd0u, 0x88u, 0x69u, 0x00u, 0x28u, 0x18u, 0xd1u, 0x2eu, 0x68u, 0x00u, 0x2eu, 0x15u, 0xdau, 0x67u, 0x68u, 0x01u, 0x24u, 0x26u, 0x00u, 0x4bu, 0x68u, 0x9eu, 0x40u, 0xb4u, 0x46u, 0x13u, 0x68u, 0x9eu, 0xb2u, 0x63u, 0x46u, 0x1bu, 0x04u, 0x1eu, 0x43u, 0x16u, 0x60u, 0xeau, 0x60u, 0x8cu, 0x61u, 0xbcu, 0x40u, 0x01u, 0x9bu, 0xa4u, 0xb2u, 0x4bu, 0x62u, 0xacu, 0x60u, 0xfeu, 0xbdu, - 0x02u, 0x48u, 0xfcu, 0xe7u, 0x02u, 0x48u, 0xfau, 0xe7u, 0xf8u, 0x03u, 0x00u, 0x08u, 0x04u, 0x02u, 0x8au, 0x00u, + 0x02u, 0x48u, 0xfcu, 0xe7u, 0x02u, 0x48u, 0xfau, 0xe7u, 0x08u, 0x04u, 0x00u, 0x08u, 0x04u, 0x02u, 0x8au, 0x00u, 0x07u, 0x02u, 0x8au, 0x00u, 0x73u, 0xb5u, 0x00u, 0x26u, 0x42u, 0x69u, 0x04u, 0x00u, 0xd5u, 0x68u, 0x01u, 0x96u, 0x2bu, 0x0cu, 0xb3u, 0x42u, 0x21u, 0xd0u, 0x1bu, 0x04u, 0x13u, 0x60u, 0x13u, 0x68u, 0x19u, 0x4bu, 0x00u, 0x69u, 0x1bu, 0x68u, 0xb0u, 0x33u, 0x1bu, 0x68u, 0xc3u, 0x18u, 0x1bu, 0x68u, 0xb3u, 0x42u, 0x15u, 0xdau, 0x01u, 0xa9u, @@ -1600,34 +1600,34 @@ const uint8_t cy_m0p_image[] = { 0x98u, 0x47u, 0x31u, 0x00u, 0x20u, 0x69u, 0xffu, 0xf7u, 0x0du, 0xffu, 0xadu, 0xb2u, 0x00u, 0x2du, 0x09u, 0xd0u, 0x63u, 0x69u, 0x1du, 0x60u, 0x00u, 0x25u, 0x1bu, 0x68u, 0x63u, 0x6au, 0xabu, 0x42u, 0x05u, 0xd0u, 0x98u, 0x47u, 0x65u, 0x62u, 0xa5u, 0x61u, 0x63u, 0x69u, 0x1bu, 0x68u, 0x73u, 0xbdu, 0xa3u, 0x6au, 0x00u, 0x2bu, 0xf8u, 0xd0u, - 0x98u, 0x47u, 0xf6u, 0xe7u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x2cu, 0x23u, 0x10u, 0xb5u, 0x43u, 0x43u, 0x03u, 0x4au, - 0x10u, 0x68u, 0xc0u, 0x18u, 0xffu, 0xf7u, 0xb6u, 0xffu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0xf8u, 0x03u, 0x00u, 0x08u, + 0x98u, 0x47u, 0xf6u, 0xe7u, 0xecu, 0x05u, 0x00u, 0x08u, 0x2cu, 0x23u, 0x10u, 0xb5u, 0x43u, 0x43u, 0x03u, 0x4au, + 0x10u, 0x68u, 0xc0u, 0x18u, 0xffu, 0xf7u, 0xb6u, 0xffu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0x08u, 0x04u, 0x00u, 0x08u, 0xf8u, 0xb5u, 0x19u, 0x4bu, 0x0fu, 0x00u, 0x1bu, 0x68u, 0x1au, 0x00u, 0x2eu, 0x32u, 0x12u, 0x78u, 0x82u, 0x42u, 0x27u, 0xd9u, 0x00u, 0x29u, 0x25u, 0xd0u, 0x1fu, 0x25u, 0x0au, 0x68u, 0x15u, 0x40u, 0x21u, 0xd1u, 0x19u, 0x00u, 0xacu, 0x31u, 0x0cu, 0x88u, 0x11u, 0x4eu, 0x60u, 0x43u, 0x1cu, 0x6au, 0xd2u, 0x08u, 0x04u, 0x19u, 0x29u, 0x00u, - 0x78u, 0x68u, 0x34u, 0x60u, 0x00u, 0xf0u, 0x3du, 0xffu, 0x29u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xcau, 0xfeu, + 0x78u, 0x68u, 0x34u, 0x60u, 0x00u, 0xf0u, 0x41u, 0xffu, 0x29u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xcau, 0xfeu, 0x3au, 0x00u, 0x29u, 0x00u, 0x30u, 0x68u, 0xffu, 0xf7u, 0xd7u, 0xfeu, 0x04u, 0x1eu, 0x07u, 0xd1u, 0x01u, 0x00u, 0x30u, 0x68u, 0xffu, 0xf7u, 0xbfu, 0xfeu, 0x03u, 0x00u, 0x20u, 0x00u, 0x00u, 0x2bu, 0x00u, 0xd0u, 0x04u, 0x48u, - 0xf8u, 0xbdu, 0x04u, 0x48u, 0xfcu, 0xe7u, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, 0xfcu, 0x03u, 0x00u, 0x08u, + 0xf8u, 0xbdu, 0x04u, 0x48u, 0xfcu, 0xe7u, 0xc0u, 0x46u, 0xecu, 0x05u, 0x00u, 0x08u, 0x0cu, 0x04u, 0x00u, 0x08u, 0x01u, 0x01u, 0x8au, 0x00u, 0x03u, 0x01u, 0x8au, 0x00u, 0x10u, 0xb5u, 0x00u, 0x2au, 0x0du, 0xd1u, 0x00u, 0x29u, 0x14u, 0xd1u, 0x0bu, 0x4bu, 0x1au, 0x68u, 0x13u, 0x00u, 0xacu, 0x33u, 0x1bu, 0x88u, 0x58u, 0x43u, 0x13u, 0x6au, 0xc0u, 0x18u, 0x08u, 0x4bu, 0x18u, 0x60u, 0x08u, 0x00u, 0x10u, 0xbdu, 0x00u, 0x29u, 0x06u, 0xd0u, 0x06u, 0x4bu, 0x19u, 0x60u, 0x19u, 0x00u, 0x5au, 0x60u, 0xffu, 0xf7u, 0xabu, 0xffu, 0xf5u, 0xe7u, 0x03u, 0x48u, 0xf3u, 0xe7u, - 0xdcu, 0x05u, 0x00u, 0x08u, 0xfcu, 0x03u, 0x00u, 0x08u, 0x78u, 0x03u, 0x00u, 0x08u, 0x03u, 0x01u, 0x8au, 0x00u, + 0xecu, 0x05u, 0x00u, 0x08u, 0x0cu, 0x04u, 0x00u, 0x08u, 0x88u, 0x03u, 0x00u, 0x08u, 0x03u, 0x01u, 0x8au, 0x00u, 0xf7u, 0xb5u, 0x18u, 0x4fu, 0x04u, 0x00u, 0x3bu, 0x68u, 0x01u, 0x91u, 0xdeu, 0x68u, 0x33u, 0x68u, 0x83u, 0x42u, 0x26u, 0xd9u, 0x00u, 0x25u, 0xa9u, 0x42u, 0x02u, 0xd1u, 0xf9u, 0xf7u, 0xc7u, 0xfeu, 0x05u, 0x00u, 0x38u, 0x68u, 0x03u, 0x68u, 0x00u, 0x2bu, 0x1au, 0xdau, 0x1fu, 0x22u, 0x01u, 0x23u, 0x22u, 0x40u, 0x93u, 0x40u, 0x64u, 0x09u, 0x72u, 0x68u, 0xa4u, 0x00u, 0x14u, 0x19u, 0x22u, 0x68u, 0x13u, 0x42u, 0x0du, 0xd0u, 0x9au, 0x43u, 0x22u, 0x60u, 0x00u, 0x24u, 0x00u, 0x21u, 0xffu, 0xf7u, 0x66u, 0xfeu, 0x01u, 0x9bu, 0x00u, 0x2bu, 0x02u, 0xd1u, 0x28u, 0x00u, 0xf9u, 0xf7u, 0xafu, 0xfeu, 0x20u, 0x00u, 0xfeu, 0xbdu, 0x03u, 0x4cu, 0xf2u, 0xe7u, 0x03u, 0x4cu, 0xf3u, 0xe7u, - 0x03u, 0x4cu, 0xf7u, 0xe7u, 0xfcu, 0x03u, 0x00u, 0x08u, 0x02u, 0x01u, 0x88u, 0x00u, 0x03u, 0x01u, 0x88u, 0x00u, + 0x03u, 0x4cu, 0xf7u, 0xe7u, 0x0cu, 0x04u, 0x00u, 0x08u, 0x02u, 0x01u, 0x88u, 0x00u, 0x03u, 0x01u, 0x88u, 0x00u, 0x04u, 0x01u, 0x8au, 0x00u, 0x0au, 0x4bu, 0x1bu, 0x68u, 0xdbu, 0x68u, 0x1au, 0x68u, 0x82u, 0x42u, 0x0du, 0xd9u, 0x59u, 0x68u, 0x1fu, 0x23u, 0x42u, 0x09u, 0x18u, 0x40u, 0x1eu, 0x3bu, 0x83u, 0x40u, 0x92u, 0x00u, 0x50u, 0x58u, 0x18u, 0x40u, 0x43u, 0x1eu, 0x98u, 0x41u, 0x03u, 0x4bu, 0xc0u, 0x18u, 0x70u, 0x47u, 0x02u, 0x48u, 0xfcu, 0xe7u, - 0xfcu, 0x03u, 0x00u, 0x08u, 0x00u, 0x01u, 0x88u, 0x00u, 0x04u, 0x01u, 0x8au, 0x00u, 0xa6u, 0x22u, 0x05u, 0x49u, + 0x0cu, 0x04u, 0x00u, 0x08u, 0x00u, 0x01u, 0x88u, 0x00u, 0x04u, 0x01u, 0x8au, 0x00u, 0xa6u, 0x22u, 0x05u, 0x49u, 0xd2u, 0x00u, 0x8bu, 0x58u, 0x02u, 0x20u, 0xdbu, 0x43u, 0x9bu, 0x07u, 0x02u, 0xd0u, 0x01u, 0x23u, 0x88u, 0x58u, 0x18u, 0x40u, 0x70u, 0x47u, 0x00u, 0x00u, 0x26u, 0x40u, 0x10u, 0xb5u, 0xffu, 0xf7u, 0xefu, 0xffu, 0x00u, 0x23u, - 0x02u, 0x28u, 0x01u, 0xd1u, 0x01u, 0x4bu, 0x1bu, 0x68u, 0x18u, 0x00u, 0x10u, 0xbdu, 0x00u, 0x04u, 0x00u, 0x08u, + 0x02u, 0x28u, 0x01u, 0xd1u, 0x01u, 0x4bu, 0x1bu, 0x68u, 0x18u, 0x00u, 0x10u, 0xbdu, 0x10u, 0x04u, 0x00u, 0x08u, 0x09u, 0x4au, 0x83u, 0x00u, 0x9bu, 0x18u, 0xd0u, 0x22u, 0x92u, 0x00u, 0x98u, 0x58u, 0x07u, 0x22u, 0x10u, 0x40u, 0x04u, 0x28u, 0x07u, 0xd1u, 0xc0u, 0x22u, 0x92u, 0x00u, 0x98u, 0x58u, 0x1fu, 0x23u, 0x03u, 0x40u, 0x80u, 0x20u, 0x40u, 0x00u, 0x18u, 0x43u, 0x70u, 0x47u, 0xc0u, 0x46u, 0x00u, 0x00u, 0x26u, 0x40u, 0x10u, 0xb5u, 0xffu, 0xf7u, @@ -1637,7 +1637,7 @@ const uint8_t cy_m0p_image[] = { 0xc0u, 0x0fu, 0xc0u, 0x03u, 0x00u, 0xe0u, 0x0bu, 0x48u, 0x10u, 0xbdu, 0x0bu, 0x4bu, 0x18u, 0x68u, 0xfbu, 0xe7u, 0xffu, 0xf7u, 0xbau, 0xffu, 0xf8u, 0xe7u, 0x09u, 0x4bu, 0x18u, 0x69u, 0x04u, 0x23u, 0x18u, 0x40u, 0xf3u, 0xd0u, 0x80u, 0x20u, 0x00u, 0x02u, 0xf0u, 0xe7u, 0x01u, 0x4au, 0x05u, 0x4bu, 0xe8u, 0xe7u, 0x00u, 0x00u, 0x26u, 0x40u, - 0x0cu, 0x05u, 0x00u, 0x00u, 0x00u, 0x12u, 0x7au, 0x00u, 0x04u, 0x04u, 0x00u, 0x08u, 0x00u, 0x00u, 0x27u, 0x40u, + 0x0cu, 0x05u, 0x00u, 0x00u, 0x00u, 0x12u, 0x7au, 0x00u, 0x14u, 0x04u, 0x00u, 0x08u, 0x00u, 0x00u, 0x27u, 0x40u, 0x3cu, 0x05u, 0x00u, 0x00u, 0xb0u, 0x23u, 0x15u, 0x4au, 0xdbu, 0x00u, 0xd3u, 0x58u, 0x10u, 0xb5u, 0x99u, 0x03u, 0xdbu, 0x01u, 0xdbu, 0x0fu, 0x89u, 0x0bu, 0xc3u, 0x71u, 0x11u, 0x4bu, 0x01u, 0x60u, 0xd3u, 0x58u, 0x0fu, 0x24u, 0xd9u, 0x04u, 0xdbu, 0x01u, 0xdbu, 0x0du, 0x03u, 0x81u, 0xb1u, 0x23u, 0xdbu, 0x00u, 0xd3u, 0x58u, 0xc9u, 0x0cu, @@ -1648,457 +1648,458 @@ const uint8_t cy_m0p_image[] = { 0x3bu, 0x33u, 0x1bu, 0x78u, 0x93u, 0x42u, 0x16u, 0xd9u, 0x7fu, 0x22u, 0x1fu, 0x24u, 0x80u, 0x30u, 0xffu, 0x30u, 0x0bu, 0x4bu, 0x80u, 0x00u, 0xc3u, 0x58u, 0x1au, 0x40u, 0x0au, 0x70u, 0x1au, 0x0cu, 0x22u, 0x40u, 0x18u, 0x0au, 0x8au, 0x70u, 0x1au, 0x01u, 0x20u, 0x40u, 0xe2u, 0x40u, 0x48u, 0x70u, 0x00u, 0x20u, 0x9bu, 0x00u, 0x9bu, 0x0fu, - 0xcau, 0x70u, 0x0bu, 0x71u, 0x10u, 0xbdu, 0x03u, 0x48u, 0xfcu, 0xe7u, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, + 0xcau, 0x70u, 0x0bu, 0x71u, 0x10u, 0xbdu, 0x03u, 0x48u, 0xfcu, 0xe7u, 0xc0u, 0x46u, 0xecu, 0x05u, 0x00u, 0x08u, 0x00u, 0x00u, 0x26u, 0x40u, 0x01u, 0x00u, 0x4au, 0x00u, 0xf0u, 0xb5u, 0x87u, 0xb0u, 0x04u, 0x00u, 0xffu, 0xf7u, - 0x65u, 0xffu, 0x06u, 0x00u, 0x00u, 0x2cu, 0x34u, 0xd1u, 0x01u, 0xadu, 0x14u, 0x22u, 0x21u, 0x00u, 0x28u, 0x00u, - 0x00u, 0xf0u, 0xcfu, 0xfdu, 0x28u, 0x00u, 0xffu, 0xf7u, 0x95u, 0xffu, 0xb0u, 0x23u, 0x25u, 0x4au, 0xdbu, 0x00u, + 0x65u, 0xffu, 0x06u, 0x00u, 0x00u, 0x2cu, 0x38u, 0xd1u, 0x01u, 0xadu, 0x14u, 0x22u, 0x21u, 0x00u, 0x28u, 0x00u, + 0x00u, 0xf0u, 0xd3u, 0xfdu, 0x28u, 0x00u, 0xffu, 0xf7u, 0x95u, 0xffu, 0xb0u, 0x23u, 0x27u, 0x4au, 0xdbu, 0x00u, 0xd3u, 0x58u, 0x00u, 0x2bu, 0x03u, 0xdau, 0xacu, 0x7bu, 0x02u, 0x3cu, 0x63u, 0x1eu, 0x9cu, 0x41u, 0xeau, 0x79u, - 0x01u, 0x9fu, 0x53u, 0x1eu, 0x9au, 0x41u, 0xa8u, 0x88u, 0x01u, 0x32u, 0x00u, 0x2cu, 0x16u, 0xd0u, 0x00u, 0x23u, - 0x19u, 0x00u, 0x00u, 0xf0u, 0x97u, 0xfcu, 0x00u, 0x23u, 0x0cu, 0x00u, 0x05u, 0x00u, 0x3au, 0x00u, 0x30u, 0x00u, - 0x19u, 0x00u, 0x00u, 0xf0u, 0x8fu, 0xfcu, 0xe6u, 0x07u, 0x6au, 0x08u, 0x32u, 0x43u, 0x63u, 0x08u, 0x80u, 0x18u, - 0x59u, 0x41u, 0x2au, 0x00u, 0x23u, 0x00u, 0x00u, 0xf0u, 0x65u, 0xfcu, 0x06u, 0x00u, 0x30u, 0x00u, 0x07u, 0xb0u, - 0xf0u, 0xbdu, 0x11u, 0x4bu, 0x1bu, 0x68u, 0x3bu, 0x33u, 0x1bu, 0x78u, 0xa3u, 0x42u, 0xf6u, 0xd3u, 0x01u, 0xadu, - 0x05u, 0x22u, 0x00u, 0x21u, 0x28u, 0x00u, 0x00u, 0xf0u, 0x94u, 0xfdu, 0x20u, 0x00u, 0x29u, 0x00u, 0x80u, 0x34u, - 0xffu, 0xf7u, 0x8au, 0xffu, 0xffu, 0x34u, 0x07u, 0x4bu, 0xa4u, 0x00u, 0xe3u, 0x58u, 0x00u, 0x24u, 0xa3u, 0x42u, - 0x03u, 0xdau, 0x2cu, 0x79u, 0x02u, 0x3cu, 0x63u, 0x1eu, 0x9cu, 0x41u, 0x2fu, 0x78u, 0x68u, 0x78u, 0xaau, 0x78u, - 0xc3u, 0xe7u, 0xc0u, 0x46u, 0x00u, 0x00u, 0x26u, 0x40u, 0xdcu, 0x05u, 0x00u, 0x08u, 0xe0u, 0x22u, 0x10u, 0xb5u, - 0x01u, 0x24u, 0x09u, 0x4bu, 0x80u, 0x00u, 0x92u, 0x00u, 0xc0u, 0x18u, 0x83u, 0x58u, 0x80u, 0x58u, 0x9bu, 0x06u, - 0x9bu, 0x0fu, 0x9cu, 0x40u, 0x0fu, 0x23u, 0x18u, 0x40u, 0xffu, 0xf7u, 0x8eu, 0xffu, 0x63u, 0x08u, 0x18u, 0x18u, - 0x21u, 0x00u, 0x00u, 0xf0u, 0x9bu, 0xfbu, 0x10u, 0xbdu, 0x00u, 0x00u, 0x26u, 0x40u, 0x14u, 0x4bu, 0x30u, 0xb5u, - 0x1au, 0x68u, 0x07u, 0x24u, 0x13u, 0x00u, 0x28u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x15u, 0xd8u, 0x83u, 0x08u, - 0x1du, 0x00u, 0xa5u, 0x43u, 0x2cu, 0x1eu, 0x0fu, 0xd1u, 0x03u, 0x34u, 0x20u, 0x40u, 0xa0u, 0x40u, 0x81u, 0x40u, - 0x12u, 0x68u, 0x9bu, 0x00u, 0x20u, 0x32u, 0xd3u, 0x18u, 0x0au, 0x00u, 0xffu, 0x21u, 0x81u, 0x40u, 0x1cu, 0x68u, - 0x62u, 0x40u, 0x11u, 0x40u, 0x61u, 0x40u, 0x19u, 0x60u, 0x30u, 0xbdu, 0x80u, 0x23u, 0x20u, 0x40u, 0x1bu, 0x06u, - 0x18u, 0x43u, 0x80u, 0x23u, 0x9bu, 0x01u, 0x12u, 0x68u, 0xc9u, 0x18u, 0x89u, 0x00u, 0x88u, 0x50u, 0xf3u, 0xe7u, - 0xdcu, 0x05u, 0x00u, 0x08u, 0x06u, 0x4bu, 0x9au, 0x68u, 0x03u, 0x00u, 0x06u, 0x48u, 0x10u, 0x33u, 0x9bu, 0x00u, - 0x82u, 0x42u, 0x02u, 0xd1u, 0x98u, 0x58u, 0x99u, 0x50u, 0x70u, 0x47u, 0x03u, 0x4au, 0xd0u, 0x58u, 0xfbu, 0xe7u, - 0x00u, 0xedu, 0x00u, 0xe0u, 0x00u, 0x00u, 0x00u, 0x08u, 0x00u, 0x00u, 0x00u, 0x10u, 0xf8u, 0xb5u, 0x06u, 0x00u, - 0x0du, 0x00u, 0x00u, 0x28u, 0x3au, 0xd0u, 0x00u, 0x23u, 0xc0u, 0x5eu, 0x00u, 0x28u, 0x28u, 0xdbu, 0x71u, 0x88u, - 0xffu, 0xf7u, 0xb4u, 0xffu, 0x00u, 0x24u, 0xffu, 0x22u, 0x03u, 0x27u, 0x94u, 0x46u, 0x00u, 0x23u, 0xf0u, 0x5eu, - 0x71u, 0x68u, 0x83u, 0xb2u, 0x1fu, 0x40u, 0xffu, 0x00u, 0x66u, 0x46u, 0xbau, 0x40u, 0x89u, 0x01u, 0x31u, 0x40u, - 0xd2u, 0x43u, 0xb9u, 0x40u, 0x00u, 0x28u, 0x15u, 0xdbu, 0x11u, 0x4eu, 0x83u, 0x08u, 0x9bu, 0x00u, 0x9bu, 0x19u, - 0xc0u, 0x26u, 0xb6u, 0x00u, 0x9fu, 0x59u, 0x3au, 0x40u, 0x11u, 0x43u, 0x99u, 0x51u, 0x0du, 0x4bu, 0x9au, 0x68u, - 0x0du, 0x4bu, 0x9au, 0x42u, 0x02u, 0xd1u, 0x29u, 0x00u, 0xffu, 0xf7u, 0xbcu, 0xffu, 0x20u, 0x00u, 0xf8u, 0xbdu, - 0x0au, 0x4cu, 0xd8u, 0xe7u, 0x0fu, 0x26u, 0x33u, 0x40u, 0x08u, 0x3bu, 0x06u, 0x4eu, 0x9bu, 0x08u, 0x9bu, 0x00u, - 0x9bu, 0x19u, 0xdeu, 0x69u, 0x32u, 0x40u, 0x11u, 0x43u, 0xd9u, 0x61u, 0xe7u, 0xe7u, 0x03u, 0x4cu, 0xedu, 0xe7u, - 0x00u, 0xe1u, 0x00u, 0xe0u, 0x00u, 0xedu, 0x00u, 0xe0u, 0x00u, 0x00u, 0x00u, 0x08u, 0x01u, 0x00u, 0x56u, 0x00u, - 0xfeu, 0xe7u, 0x00u, 0x00u, 0x02u, 0x68u, 0x0au, 0x4bu, 0x10u, 0xb5u, 0x1au, 0x60u, 0x42u, 0x68u, 0x5au, 0x60u, - 0x82u, 0x68u, 0x9au, 0x60u, 0xc2u, 0x68u, 0xdau, 0x60u, 0x02u, 0x69u, 0x1au, 0x61u, 0x42u, 0x69u, 0x5au, 0x61u, - 0x82u, 0x69u, 0x9au, 0x61u, 0xc2u, 0x69u, 0xdau, 0x61u, 0xffu, 0xf7u, 0xeau, 0xffu, 0x10u, 0xbdu, 0xc0u, 0x46u, - 0x90u, 0x03u, 0x00u, 0x08u, 0xb0u, 0x23u, 0x5bu, 0x05u, 0x9au, 0x89u, 0x00u, 0x2au, 0x02u, 0xd0u, 0x98u, 0x89u, - 0x80u, 0xb2u, 0x70u, 0x47u, 0x80u, 0x20u, 0x40u, 0x00u, 0xfbu, 0xe7u, 0x00u, 0x00u, 0x7fu, 0xb5u, 0x27u, 0x4bu, - 0x86u, 0x00u, 0x0du, 0x00u, 0xf4u, 0x58u, 0x04u, 0x29u, 0x01u, 0xd0u, 0x01u, 0x29u, 0x27u, 0xd1u, 0x00u, 0x20u, - 0x0fu, 0xe0u, 0xa3u, 0x68u, 0x2bu, 0x42u, 0x0bu, 0xd1u, 0xe3u, 0x68u, 0x29u, 0x00u, 0x1au, 0x68u, 0x5bu, 0x68u, - 0x02u, 0x92u, 0x01u, 0x93u, 0x03u, 0x93u, 0x02u, 0xa8u, 0x23u, 0x68u, 0x98u, 0x47u, 0x1cu, 0x4bu, 0x1cu, 0x60u, - 0x64u, 0x69u, 0x00u, 0x2cu, 0x0bu, 0xd0u, 0x1bu, 0x4bu, 0x98u, 0x42u, 0xeau, 0xd1u, 0x01u, 0x2du, 0xe8u, 0xd1u, - 0x17u, 0x4bu, 0x18u, 0x48u, 0x1au, 0x68u, 0x18u, 0x4bu, 0x9au, 0x51u, 0x04u, 0xb0u, 0x70u, 0xbdu, 0x01u, 0x2du, - 0xfbu, 0xd1u, 0x14u, 0x4bu, 0x98u, 0x42u, 0xf3u, 0xd0u, 0x13u, 0x4bu, 0x9cu, 0x51u, 0xf5u, 0xe7u, 0x02u, 0x29u, - 0x06u, 0xd1u, 0x0fu, 0x4bu, 0x1bu, 0x68u, 0x18u, 0x1eu, 0xefu, 0xd0u, 0x1cu, 0x69u, 0x03u, 0xe0u, 0x1cu, 0x00u, - 0x63u, 0x69u, 0x00u, 0x2bu, 0xfbu, 0xd1u, 0x00u, 0x20u, 0x00u, 0x2cu, 0xe6u, 0xd0u, 0xa3u, 0x68u, 0x2bu, 0x42u, - 0x09u, 0xd1u, 0xe3u, 0x68u, 0x29u, 0x00u, 0x1au, 0x68u, 0x5bu, 0x68u, 0x02u, 0x92u, 0x01u, 0x93u, 0x03u, 0x93u, - 0x02u, 0xa8u, 0x23u, 0x68u, 0x98u, 0x47u, 0x24u, 0x69u, 0xeeu, 0xe7u, 0xc0u, 0x46u, 0x48u, 0x04u, 0x00u, 0x08u, - 0x44u, 0x04u, 0x00u, 0x08u, 0xffu, 0x00u, 0x42u, 0x00u, 0x30u, 0x04u, 0x00u, 0x08u, 0x19u, 0x4bu, 0x1bu, 0x68u, - 0x19u, 0x00u, 0x04u, 0xc9u, 0xc9u, 0x6fu, 0x51u, 0x18u, 0x09u, 0x68u, 0x01u, 0x62u, 0x19u, 0x00u, 0x08u, 0x31u, - 0xc9u, 0x6fu, 0x52u, 0x18u, 0x12u, 0x68u, 0x42u, 0x62u, 0x1au, 0x00u, 0x41u, 0x32u, 0x12u, 0x78u, 0x00u, 0x2au, - 0x1fu, 0xd0u, 0x9au, 0x68u, 0xe0u, 0x32u, 0x12u, 0x68u, 0xd2u, 0x06u, 0x1au, 0xd5u, 0xf2u, 0x22u, 0xdbu, 0x68u, - 0xd2u, 0x01u, 0x9au, 0x58u, 0x02u, 0x60u, 0xf0u, 0x22u, 0xd2u, 0x01u, 0x9au, 0x58u, 0x42u, 0x60u, 0x0au, 0x4au, - 0x9au, 0x58u, 0x82u, 0x60u, 0x09u, 0x4au, 0x9au, 0x58u, 0xc2u, 0x60u, 0x09u, 0x4au, 0x9au, 0x58u, 0x02u, 0x61u, - 0x08u, 0x4au, 0x9au, 0x58u, 0x42u, 0x61u, 0x08u, 0x4au, 0x9au, 0x58u, 0x82u, 0x61u, 0x07u, 0x4au, 0x9bu, 0x58u, - 0xc3u, 0x61u, 0x70u, 0x47u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x04u, 0x78u, 0x00u, 0x00u, 0x08u, 0x78u, 0x00u, 0x00u, - 0x0cu, 0x78u, 0x00u, 0x00u, 0x10u, 0x78u, 0x00u, 0x00u, 0x14u, 0x78u, 0x00u, 0x00u, 0x18u, 0x78u, 0x00u, 0x00u, - 0x19u, 0x4bu, 0x1bu, 0x68u, 0x1au, 0x1du, 0x19u, 0x68u, 0xd2u, 0x6fu, 0x8au, 0x18u, 0x01u, 0x6au, 0x11u, 0x60u, - 0x1au, 0x00u, 0x08u, 0x32u, 0x19u, 0x68u, 0xd2u, 0x6fu, 0x8au, 0x18u, 0x41u, 0x6au, 0x11u, 0x60u, 0x1au, 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0x00u, 0x00u, 0x1cu, 0x05u, 0x00u, 0x00u, + 0xaau, 0xaau, 0xaau, 0xaau, 0x01u, 0xb4u, 0x02u, 0x48u, 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, + 0x75u, 0x61u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, + 0x69u, 0x60u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, + 0x05u, 0x60u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, + 0x41u, 0x5fu, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, + 0xc5u, 0x6cu, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, + 0xdbu, 0x00u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, + 0xa5u, 0x63u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, + 0x31u, 0x63u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, + 0xe3u, 0x00u, 0x00u, 0x10u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, }; #endif /* defined(CY_DEVICE_PSOC6A512K) */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/COMPONENT_CM0P_CRYPTO/psoc6_04_cm0p_crypto.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/COMPONENT_CM0P_CRYPTO/psoc6_04_cm0p_crypto.c index 51159fdfd4..9e7fe7135f 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/COMPONENT_CM0P_CRYPTO/psoc6_04_cm0p_crypto.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/COMPONENT_CM0P_CRYPTO/psoc6_04_cm0p_crypto.c @@ -36,35 +36,35 @@ const uint8_t cy_m0p_image[] = { 0x49u, 0x01u, 0x00u, 0x10u, 0x49u, 0x01u, 0x00u, 0x10u, 0x49u, 0x01u, 0x00u, 0x10u, 0x49u, 0x01u, 0x00u, 0x10u, 0x49u, 0x01u, 0x00u, 0x10u, 0x49u, 0x01u, 0x00u, 0x10u, 0x49u, 0x01u, 0x00u, 0x10u, 0x49u, 0x01u, 0x00u, 0x10u, 0x10u, 0xb5u, 0x06u, 0x4cu, 0x23u, 0x78u, 0x00u, 0x2bu, 0x07u, 0xd1u, 0x05u, 0x4bu, 0x00u, 0x2bu, 0x02u, 0xd0u, - 0x04u, 0x48u, 0x00u, 0xe0u, 0x00u, 0xbfu, 0x01u, 0x23u, 0x23u, 0x70u, 0x10u, 0xbdu, 0xb0u, 0x03u, 0x00u, 0x08u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x48u, 0x7eu, 0x00u, 0x10u, 0x04u, 0x4bu, 0x10u, 0xb5u, 0x00u, 0x2bu, 0x03u, 0xd0u, + 0x04u, 0x48u, 0x00u, 0xe0u, 0x00u, 0xbfu, 0x01u, 0x23u, 0x23u, 0x70u, 0x10u, 0xbdu, 0xc0u, 0x03u, 0x00u, 0x08u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x50u, 0x7eu, 0x00u, 0x10u, 0x04u, 0x4bu, 0x10u, 0xb5u, 0x00u, 0x2bu, 0x03u, 0xd0u, 0x03u, 0x49u, 0x04u, 0x48u, 0x00u, 0xe0u, 0x00u, 0xbfu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0x00u, 0x00u, 0x00u, 0x00u, - 0xb4u, 0x03u, 0x00u, 0x08u, 0x48u, 0x7eu, 0x00u, 0x10u, 0x02u, 0x30u, 0x80u, 0x08u, 0x03u, 0xd0u, 0x01u, 0x30u, + 0xc4u, 0x03u, 0x00u, 0x08u, 0x50u, 0x7eu, 0x00u, 0x10u, 0x02u, 0x30u, 0x80u, 0x08u, 0x03u, 0xd0u, 0x01u, 0x30u, 0x02u, 0x38u, 0xfcu, 0xd1u, 0xc0u, 0x46u, 0xc0u, 0x46u, 0x70u, 0x47u, 0xefu, 0xf3u, 0x10u, 0x80u, 0x72u, 0xb6u, 0x70u, 0x47u, 0x80u, 0xf3u, 0x10u, 0x88u, 0x70u, 0x47u, 0x70u, 0x47u, 0xffu, 0xf7u, 0xfdu, 0xffu, 0x72u, 0xb6u, 0x0fu, 0x4cu, 0x10u, 0x4du, 0xacu, 0x42u, 0x09u, 0xdau, 0x21u, 0x68u, 0x62u, 0x68u, 0xa3u, 0x68u, 0x04u, 0x3bu, 0x02u, 0xdbu, 0xc8u, 0x58u, 0xd0u, 0x50u, 0xfau, 0xe7u, 0x0cu, 0x34u, 0xf3u, 0xe7u, 0x0au, 0x49u, 0x0bu, 0x4au, 0x00u, 0x20u, 0x52u, 0x1au, 0x02u, 0xddu, 0x04u, 0x3au, 0x88u, 0x50u, 0xfcu, 0xdcu, 0x08u, 0x48u, 0x09u, 0x49u, - 0x08u, 0x60u, 0xbfu, 0xf3u, 0x4fu, 0x8fu, 0x06u, 0xf0u, 0x75u, 0xfdu, 0x06u, 0xf0u, 0x15u, 0xfdu, 0xfeu, 0xe7u, - 0x54u, 0x7eu, 0x00u, 0x10u, 0x6cu, 0x7eu, 0x00u, 0x10u, 0xb0u, 0x03u, 0x00u, 0x08u, 0x0cu, 0x06u, 0x00u, 0x08u, + 0x08u, 0x60u, 0xbfu, 0xf3u, 0x4fu, 0x8fu, 0x06u, 0xf0u, 0x79u, 0xfdu, 0x06u, 0xf0u, 0x19u, 0xfdu, 0xfeu, 0xe7u, + 0x5cu, 0x7eu, 0x00u, 0x10u, 0x74u, 0x7eu, 0x00u, 0x10u, 0xc0u, 0x03u, 0x00u, 0x08u, 0x1cu, 0x06u, 0x00u, 0x08u, 0x00u, 0x00u, 0x00u, 0x08u, 0x08u, 0xedu, 0x00u, 0xe0u, 0xfeu, 0xe7u, 0xfeu, 0xe7u, 0x00u, 0xb5u, 0x04u, 0x20u, 0x71u, 0x46u, 0x08u, 0x42u, 0x02u, 0xd0u, 0xefu, 0xf3u, 0x09u, 0x80u, 0x01u, 0xe0u, 0xefu, 0xf3u, 0x08u, 0x80u, - 0x04u, 0x30u, 0x06u, 0xf0u, 0x07u, 0xfbu, 0xfeu, 0xe7u, 0xf7u, 0xb5u, 0x03u, 0x27u, 0x11u, 0x4eu, 0x14u, 0x00u, + 0x04u, 0x30u, 0x06u, 0xf0u, 0x0bu, 0xfbu, 0xfeu, 0xe7u, 0xf7u, 0xb5u, 0x03u, 0x27u, 0x11u, 0x4eu, 0x14u, 0x00u, 0x32u, 0x68u, 0x05u, 0x00u, 0x52u, 0x69u, 0x82u, 0x18u, 0x08u, 0x78u, 0x49u, 0x68u, 0x38u, 0x40u, 0x10u, 0x60u, 0x01u, 0x2cu, 0x00u, 0xd1u, 0x20u, 0x31u, 0x28u, 0x00u, 0x08u, 0x9au, 0x01u, 0x3cu, 0x03u, 0xf0u, 0x72u, 0xfdu, 0x0cu, 0x23u, 0x61u, 0x42u, 0x61u, 0x41u, 0x00u, 0x93u, 0x28u, 0x00u, 0x08u, 0x3bu, 0x44u, 0x31u, 0x00u, 0x22u, 0x03u, 0xf0u, 0xd0u, 0xfdu, 0x33u, 0x68u, 0x1bu, 0x68u, 0xedu, 0x18u, 0x01u, 0x23u, 0x2au, 0x68u, 0x1au, 0x42u, - 0xfcu, 0xd1u, 0xf7u, 0xbdu, 0xd0u, 0x03u, 0x00u, 0x08u, 0x73u, 0xb5u, 0x04u, 0x00u, 0x08u, 0x00u, 0x03u, 0x26u, + 0xfcu, 0xd1u, 0xf7u, 0xbdu, 0xe0u, 0x03u, 0x00u, 0x08u, 0x73u, 0xb5u, 0x04u, 0x00u, 0x08u, 0x00u, 0x03u, 0x26u, 0x0eu, 0x4du, 0x19u, 0x00u, 0x2bu, 0x68u, 0x00u, 0x78u, 0x5bu, 0x69u, 0x30u, 0x40u, 0xe3u, 0x18u, 0x18u, 0x60u, 0x13u, 0x00u, 0x20u, 0x00u, 0x06u, 0x9au, 0x03u, 0xf0u, 0x4du, 0xfdu, 0x08u, 0x23u, 0x20u, 0x00u, 0x00u, 0x93u, 0x00u, 0x22u, 0x04u, 0x3bu, 0x48u, 0x21u, 0x03u, 0xf0u, 0xadu, 0xfdu, 0x2bu, 0x68u, 0x1bu, 0x68u, 0xe4u, 0x18u, - 0x01u, 0x23u, 0x22u, 0x68u, 0x1au, 0x42u, 0xfcu, 0xd1u, 0x73u, 0xbdu, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, + 0x01u, 0x23u, 0x22u, 0x68u, 0x1au, 0x42u, 0xfcu, 0xd1u, 0x73u, 0xbdu, 0xc0u, 0x46u, 0xe0u, 0x03u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x1du, 0x00u, 0x1au, 0x70u, 0x04u, 0x9bu, 0x02u, 0x32u, 0x6bu, 0x60u, 0xd3u, 0x00u, 0x0au, 0x00u, 0x04u, 0x99u, 0x04u, 0x00u, 0x03u, 0xf0u, 0xceu, 0xfdu, 0x03u, 0x21u, 0x0du, 0x4eu, 0x2au, 0x78u, 0x33u, 0x68u, 0x0au, 0x40u, 0x5bu, 0x69u, 0x69u, 0x68u, 0xe3u, 0x18u, 0x1au, 0x60u, 0x0au, 0x00u, 0x20u, 0x00u, 0x20u, 0x32u, 0x03u, 0xf0u, 0x06u, 0xfdu, 0x08u, 0x23u, 0x20u, 0x00u, 0x00u, 0x22u, 0x46u, 0x21u, 0x03u, 0xf0u, 0x6cu, 0xfdu, 0x33u, 0x68u, 0x1bu, 0x68u, 0xe4u, 0x18u, 0x01u, 0x23u, 0x20u, 0x68u, 0x18u, 0x40u, 0xfcu, 0xd1u, 0x70u, 0xbdu, - 0xd0u, 0x03u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x85u, 0xb0u, 0x16u, 0x00u, 0x1au, 0x00u, 0x0au, 0x9bu, 0x05u, 0x00u, + 0xe0u, 0x03u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x85u, 0xb0u, 0x16u, 0x00u, 0x1au, 0x00u, 0x0au, 0x9bu, 0x05u, 0x00u, 0x5cu, 0x68u, 0x03u, 0x91u, 0x27u, 0x00u, 0x40u, 0x37u, 0x39u, 0x00u, 0x50u, 0x34u, 0x10u, 0x23u, 0x03u, 0xf0u, 0xa1u, 0xfdu, 0x23u, 0x00u, 0x03u, 0x9au, 0x0au, 0x99u, 0x28u, 0x00u, 0x00u, 0x97u, 0xffu, 0xf7u, 0x74u, 0xffu, 0x28u, 0x00u, 0x10u, 0x23u, 0x22u, 0x00u, 0x31u, 0x00u, 0x03u, 0xf0u, 0x94u, 0xfdu, 0x00u, 0x20u, 0x05u, 0xb0u, @@ -95,7 +95,7 @@ const uint8_t cy_m0p_image[] = { 0xd3u, 0xfeu, 0x10u, 0x23u, 0x2au, 0x00u, 0x07u, 0x99u, 0x30u, 0x00u, 0x03u, 0xf0u, 0xcbu, 0xfcu, 0x10u, 0x3cu, 0xcfu, 0xe7u, 0x01u, 0x48u, 0xdfu, 0xe7u, 0xc0u, 0x46u, 0x02u, 0x00u, 0x32u, 0x00u, 0xf0u, 0xb5u, 0x91u, 0xb0u, 0x19u, 0x9du, 0x04u, 0x00u, 0x06u, 0x91u, 0x0bu, 0x92u, 0x00u, 0x21u, 0x10u, 0x22u, 0x0cu, 0xa8u, 0x07u, 0x93u, - 0x06u, 0xf0u, 0x6fu, 0xfeu, 0x6bu, 0x68u, 0x0cu, 0xa9u, 0x1au, 0x00u, 0x40u, 0x32u, 0x03u, 0x92u, 0x60u, 0x33u, + 0x06u, 0xf0u, 0x73u, 0xfeu, 0x6bu, 0x68u, 0x0cu, 0xa9u, 0x1au, 0x00u, 0x40u, 0x32u, 0x03u, 0x92u, 0x60u, 0x33u, 0x10u, 0x32u, 0x04u, 0x92u, 0x05u, 0x93u, 0x07u, 0x9au, 0x10u, 0x23u, 0x20u, 0x00u, 0x03u, 0xf0u, 0xaau, 0xfcu, 0x0fu, 0x9bu, 0x1bu, 0xbau, 0x08u, 0x93u, 0x06u, 0x9bu, 0x08u, 0x9eu, 0x1bu, 0x09u, 0x0au, 0x93u, 0x0eu, 0x9bu, 0x1fu, 0xbau, 0x08u, 0x9bu, 0x17u, 0x99u, 0xf3u, 0x1au, 0x1au, 0x01u, 0x89u, 0x18u, 0x09u, 0x91u, 0x18u, 0x99u, @@ -107,32 +107,32 @@ const uint8_t cy_m0p_image[] = { 0x0eu, 0x92u, 0x00u, 0x93u, 0x04u, 0x9au, 0x03u, 0x9bu, 0x29u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x6cu, 0xfeu, 0x10u, 0x23u, 0x04u, 0x9au, 0x09u, 0x99u, 0x20u, 0x00u, 0x03u, 0xf0u, 0x64u, 0xfcu, 0xc1u, 0xe7u, 0x00u, 0x00u, 0x03u, 0x4bu, 0x1bu, 0x68u, 0x9bu, 0x68u, 0xc0u, 0x18u, 0x0fu, 0x23u, 0x00u, 0x68u, 0x18u, 0x40u, 0x70u, 0x47u, - 0xd0u, 0x03u, 0x00u, 0x08u, 0x03u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xc0u, 0x18u, 0x03u, 0x68u, 0x00u, 0x2bu, - 0xfcu, 0xd1u, 0x70u, 0x47u, 0xd0u, 0x03u, 0x00u, 0x08u, 0xf8u, 0xb5u, 0x04u, 0x00u, 0x0du, 0x00u, 0x17u, 0x00u, + 0xe0u, 0x03u, 0x00u, 0x08u, 0x03u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xc0u, 0x18u, 0x03u, 0x68u, 0x00u, 0x2bu, + 0xfcu, 0xd1u, 0x70u, 0x47u, 0xe0u, 0x03u, 0x00u, 0x08u, 0xf8u, 0xb5u, 0x04u, 0x00u, 0x0du, 0x00u, 0x17u, 0x00u, 0x1eu, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xe4u, 0xffu, 0x04u, 0x28u, 0xfau, 0xd8u, 0x08u, 0x2du, 0x04u, 0xd0u, 0x0cu, 0x4au, 0xa3u, 0x58u, 0x00u, 0x2bu, 0xfcu, 0xdbu, 0x04u, 0xe0u, 0x86u, 0x22u, 0x52u, 0x01u, 0xa3u, 0x58u, 0x00u, 0x2bu, 0xfcu, 0xdbu, 0xe2u, 0x21u, 0x08u, 0x4bu, 0xc9u, 0x05u, 0x1bu, 0x68u, 0x0du, 0x43u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x15u, 0x60u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x17u, 0x60u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0x26u, 0x60u, - 0xf8u, 0xbdu, 0xc0u, 0x46u, 0xd0u, 0x10u, 0x00u, 0x00u, 0xd0u, 0x03u, 0x00u, 0x08u, 0xf8u, 0xb5u, 0x07u, 0x00u, + 0xf8u, 0xbdu, 0xc0u, 0x46u, 0xd0u, 0x10u, 0x00u, 0x00u, 0xe0u, 0x03u, 0x00u, 0x08u, 0xf8u, 0xb5u, 0x07u, 0x00u, 0x0cu, 0x00u, 0x16u, 0x00u, 0x1du, 0x00u, 0x38u, 0x00u, 0xffu, 0xf7u, 0xbau, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x06u, 0x4bu, 0x24u, 0x03u, 0x1bu, 0x68u, 0x2du, 0x04u, 0xd8u, 0x68u, 0x80u, 0x23u, 0xdbu, 0x05u, 0x1eu, 0x43u, - 0x34u, 0x43u, 0x38u, 0x18u, 0x2cu, 0x43u, 0x04u, 0x60u, 0xf8u, 0xbdu, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, + 0x34u, 0x43u, 0x38u, 0x18u, 0x2cu, 0x43u, 0x04u, 0x60u, 0xf8u, 0xbdu, 0xc0u, 0x46u, 0xe0u, 0x03u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x05u, 0x00u, 0x0cu, 0x00u, 0x16u, 0x00u, 0x28u, 0x00u, 0xffu, 0xf7u, 0xa1u, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x05u, 0x4bu, 0x24u, 0x02u, 0x1bu, 0x68u, 0xdbu, 0x68u, 0xedu, 0x18u, 0xd0u, 0x23u, 0xdbu, 0x05u, - 0x1eu, 0x43u, 0x34u, 0x43u, 0x2cu, 0x60u, 0x70u, 0xbdu, 0xd0u, 0x03u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, + 0x1eu, 0x43u, 0x34u, 0x43u, 0x2cu, 0x60u, 0x70u, 0xbdu, 0xe0u, 0x03u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x8du, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x04u, 0x4bu, 0x1bu, 0x68u, 0xdbu, 0x68u, - 0xe4u, 0x18u, 0xa0u, 0x23u, 0xdbu, 0x05u, 0x23u, 0x60u, 0x10u, 0xbdu, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, + 0xe4u, 0x18u, 0xa0u, 0x23u, 0xdbu, 0x05u, 0x23u, 0x60u, 0x10u, 0xbdu, 0xc0u, 0x46u, 0xe0u, 0x03u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x7bu, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x04u, 0x4bu, 0x1bu, 0x68u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0xa2u, 0x23u, 0xdbu, 0x05u, 0x23u, 0x60u, 0x10u, 0xbdu, 0xc0u, 0x46u, - 0xd0u, 0x03u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x04u, 0x00u, 0x0eu, 0x00u, 0x15u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, + 0xe0u, 0x03u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x04u, 0x00u, 0x0eu, 0x00u, 0x15u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x67u, 0xffu, 0x04u, 0x28u, 0xfau, 0xd8u, 0x06u, 0x4bu, 0x06u, 0x49u, 0x1bu, 0x68u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x11u, 0x60u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x16u, 0x60u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0x25u, 0x60u, 0x70u, 0xbdu, - 0xd0u, 0x03u, 0x00u, 0x08u, 0x0cu, 0x00u, 0x00u, 0x70u, 0x70u, 0xb5u, 0x05u, 0x00u, 0x0cu, 0x78u, 0x4au, 0x68u, + 0xe0u, 0x03u, 0x00u, 0x08u, 0x0cu, 0x00u, 0x00u, 0x70u, 0x70u, 0xb5u, 0x05u, 0x00u, 0x0cu, 0x78u, 0x4au, 0x68u, 0x02u, 0x34u, 0xe4u, 0x00u, 0x23u, 0x00u, 0x0eu, 0x00u, 0x08u, 0x21u, 0xffu, 0xf7u, 0x5du, 0xffu, 0x10u, 0x23u, 0x08u, 0x22u, 0x04u, 0x21u, 0x28u, 0x00u, 0xffu, 0xf7u, 0x81u, 0xffu, 0x23u, 0x00u, 0x10u, 0x3bu, 0x00u, 0x2bu, 0x04u, 0xd0u, 0x08u, 0x22u, 0x05u, 0x21u, 0x28u, 0x00u, 0xffu, 0xf7u, 0x78u, 0xffu, 0x03u, 0x21u, 0x05u, 0x4bu, 0x32u, 0x78u, 0x1bu, 0x68u, 0x0au, 0x40u, 0x5bu, 0x69u, 0x28u, 0x00u, 0xebu, 0x18u, 0x1au, 0x60u, 0xffu, 0xf7u, - 0x39u, 0xffu, 0x70u, 0xbdu, 0xd0u, 0x03u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x05u, 0x00u, 0x0bu, 0x78u, 0x02u, 0x33u, + 0x39u, 0xffu, 0x70u, 0xbdu, 0xe0u, 0x03u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x05u, 0x00u, 0x0bu, 0x78u, 0x02u, 0x33u, 0xdcu, 0x00u, 0xffu, 0xf7u, 0xd1u, 0xffu, 0x28u, 0x00u, 0xffu, 0xf7u, 0x90u, 0xffu, 0x10u, 0x23u, 0x06u, 0x22u, 0x04u, 0x21u, 0x28u, 0x00u, 0xffu, 0xf7u, 0x5au, 0xffu, 0x23u, 0x00u, 0x10u, 0x3bu, 0x00u, 0x2bu, 0x04u, 0xd0u, 0x07u, 0x22u, 0x05u, 0x21u, 0x28u, 0x00u, 0xffu, 0xf7u, 0x51u, 0xffu, 0x28u, 0x00u, 0xffu, 0xf7u, 0x1au, 0xffu, @@ -160,7 +160,7 @@ const uint8_t cy_m0p_image[] = { 0x00u, 0x21u, 0xffu, 0xf7u, 0xa3u, 0xfeu, 0x20u, 0x00u, 0xffu, 0xf7u, 0xe2u, 0xfeu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x5fu, 0xfeu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x08u, 0x4bu, 0x09u, 0x4au, 0x1bu, 0x68u, 0x02u, 0x21u, 0xdbu, 0x68u, 0x20u, 0x00u, 0xe3u, 0x18u, 0x1au, 0x60u, 0x10u, 0x23u, 0x00u, 0x22u, 0xffu, 0xf7u, 0x8fu, 0xfeu, 0x10u, 0x3du, - 0xdfu, 0xe7u, 0x04u, 0x48u, 0xbfu, 0xe7u, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, 0x18u, 0x00u, 0x10u, 0x41u, + 0xdfu, 0xe7u, 0x04u, 0x48u, 0xbfu, 0xe7u, 0xc0u, 0x46u, 0xe0u, 0x03u, 0x00u, 0x08u, 0x18u, 0x00u, 0x10u, 0x41u, 0x21u, 0xc0u, 0x10u, 0x41u, 0x02u, 0x00u, 0x32u, 0x00u, 0xf7u, 0xb5u, 0x0fu, 0x26u, 0x04u, 0x00u, 0x01u, 0x91u, 0x15u, 0x00u, 0x1fu, 0x00u, 0x16u, 0x40u, 0x5eu, 0xd1u, 0x0au, 0x99u, 0xffu, 0xf7u, 0xe5u, 0xfeu, 0x10u, 0x23u, 0x3au, 0x00u, 0x09u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x47u, 0xfeu, 0x10u, 0x23u, 0x09u, 0x22u, 0x31u, 0x00u, @@ -174,7 +174,7 @@ const uint8_t cy_m0p_image[] = { 0x1au, 0x60u, 0x10u, 0x23u, 0x00u, 0x22u, 0xffu, 0xf7u, 0x31u, 0xfeu, 0x10u, 0x3du, 0x00u, 0x2du, 0xe8u, 0xd1u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xf7u, 0xfdu, 0x10u, 0x22u, 0x39u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x7au, 0xfeu, 0x10u, 0x23u, 0x00u, 0x22u, 0x0cu, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x20u, 0xfeu, 0x20u, 0x00u, 0xffu, 0xf7u, - 0xe9u, 0xfdu, 0x00u, 0x20u, 0xfeu, 0xbdu, 0x04u, 0x48u, 0xfcu, 0xe7u, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, + 0xe9u, 0xfdu, 0x00u, 0x20u, 0xfeu, 0xbdu, 0x04u, 0x48u, 0xfcu, 0xe7u, 0xc0u, 0x46u, 0xe0u, 0x03u, 0x00u, 0x08u, 0x01u, 0xc0u, 0x10u, 0x41u, 0x18u, 0x00u, 0x10u, 0x41u, 0x02u, 0x00u, 0x32u, 0x00u, 0xf0u, 0xb5u, 0x1du, 0x00u, 0x8bu, 0xb0u, 0x04u, 0x92u, 0x6au, 0x78u, 0x1bu, 0x78u, 0x12u, 0x02u, 0x1au, 0x43u, 0xabu, 0x78u, 0x04u, 0x00u, 0x1bu, 0x04u, 0x1au, 0x43u, 0xebu, 0x78u, 0x2eu, 0x7au, 0x1bu, 0x06u, 0x13u, 0x43u, 0x6au, 0x79u, 0x06u, 0x93u, @@ -199,7 +199,7 @@ const uint8_t cy_m0p_image[] = { 0xf2u, 0xb2u, 0x0fu, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x83u, 0xfdu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x28u, 0xfdu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x08u, 0x4bu, 0x09u, 0x4au, 0x1bu, 0x68u, 0xdbu, 0x68u, 0xe3u, 0x18u, 0x1au, 0x60u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x1du, 0xfdu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x03u, 0x4bu, 0x04u, 0x4au, 0x1bu, 0x68u, - 0xdbu, 0x68u, 0xe3u, 0x18u, 0x1au, 0x60u, 0xb3u, 0xe7u, 0xd0u, 0x03u, 0x00u, 0x08u, 0x10u, 0x10u, 0x00u, 0x66u, + 0xdbu, 0x68u, 0xe3u, 0x18u, 0x1au, 0x60u, 0xb3u, 0xe7u, 0xe0u, 0x03u, 0x00u, 0x08u, 0x10u, 0x10u, 0x00u, 0x66u, 0x10u, 0x10u, 0x00u, 0x67u, 0x02u, 0x00u, 0x00u, 0x23u, 0x10u, 0xb5u, 0x0fu, 0x32u, 0x44u, 0x1eu, 0x11u, 0x78u, 0x01u, 0x3au, 0x49u, 0x00u, 0x0bu, 0x43u, 0x53u, 0x70u, 0x1bu, 0x0au, 0x94u, 0x42u, 0xf7u, 0xd1u, 0x00u, 0x2bu, 0x04u, 0xd0u, 0x79u, 0x23u, 0xc2u, 0x7bu, 0x5bu, 0x42u, 0x53u, 0x40u, 0xc3u, 0x73u, 0x10u, 0xbdu, 0xf7u, 0xb5u, @@ -226,34 +226,34 @@ const uint8_t cy_m0p_image[] = { 0xa0u, 0x36u, 0x80u, 0x33u, 0x33u, 0x60u, 0x03u, 0x9bu, 0x90u, 0x34u, 0x73u, 0x60u, 0x32u, 0x00u, 0x0cu, 0x99u, 0x28u, 0x00u, 0xb4u, 0x60u, 0xffu, 0xf7u, 0x53u, 0xffu, 0x02u, 0x9bu, 0x32u, 0x00u, 0x0cu, 0x99u, 0x28u, 0x00u, 0x00u, 0x97u, 0xffu, 0xf7u, 0x61u, 0xffu, 0x28u, 0x00u, 0x0bu, 0x9bu, 0x32u, 0x00u, 0x0cu, 0x99u, 0xffu, 0xf7u, - 0x8du, 0xffu, 0x00u, 0x20u, 0x05u, 0xb0u, 0xf0u, 0xbdu, 0xd0u, 0x03u, 0x00u, 0x08u, 0x03u, 0x4bu, 0x1bu, 0x68u, - 0x9bu, 0x68u, 0xc0u, 0x18u, 0x0fu, 0x23u, 0x00u, 0x68u, 0x18u, 0x40u, 0x70u, 0x47u, 0xd0u, 0x03u, 0x00u, 0x08u, + 0x8du, 0xffu, 0x00u, 0x20u, 0x05u, 0xb0u, 0xf0u, 0xbdu, 0xe0u, 0x03u, 0x00u, 0x08u, 0x03u, 0x4bu, 0x1bu, 0x68u, + 0x9bu, 0x68u, 0xc0u, 0x18u, 0x0fu, 0x23u, 0x00u, 0x68u, 0x18u, 0x40u, 0x70u, 0x47u, 0xe0u, 0x03u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xf1u, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x04u, 0x4bu, 0x1bu, 0x68u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0xa0u, 0x23u, 0xdbu, 0x05u, 0x23u, 0x60u, 0x10u, 0xbdu, 0xc0u, 0x46u, - 0xd0u, 0x03u, 0x00u, 0x08u, 0x02u, 0x00u, 0x00u, 0x23u, 0x10u, 0xb5u, 0x0fu, 0x32u, 0x44u, 0x1eu, 0x11u, 0x78u, + 0xe0u, 0x03u, 0x00u, 0x08u, 0x02u, 0x00u, 0x00u, 0x23u, 0x10u, 0xb5u, 0x0fu, 0x32u, 0x44u, 0x1eu, 0x11u, 0x78u, 0x01u, 0x3au, 0x49u, 0x00u, 0x0bu, 0x43u, 0x53u, 0x70u, 0x1bu, 0x0au, 0x94u, 0x42u, 0xf7u, 0xd1u, 0x00u, 0x2bu, 0x04u, 0xd0u, 0x79u, 0x23u, 0xc2u, 0x7bu, 0x5bu, 0x42u, 0x53u, 0x40u, 0xc3u, 0x73u, 0x10u, 0xbdu, 0x00u, 0x00u, 0x70u, 0xb5u, 0x04u, 0x00u, 0x0eu, 0x00u, 0x15u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xc7u, 0xffu, 0x04u, 0x28u, 0xfau, 0xd8u, 0x86u, 0x22u, 0x52u, 0x01u, 0xa3u, 0x58u, 0x00u, 0x2bu, 0xfcu, 0xdbu, 0x06u, 0x4bu, 0x07u, 0x49u, 0x1bu, 0x68u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x11u, 0x60u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x16u, 0x60u, 0xdbu, 0x68u, - 0xe4u, 0x18u, 0x25u, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, 0x08u, 0x00u, 0x00u, 0x71u, + 0xe4u, 0x18u, 0x25u, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u, 0xe0u, 0x03u, 0x00u, 0x08u, 0x08u, 0x00u, 0x00u, 0x71u, 0x70u, 0xb5u, 0x04u, 0x00u, 0x0du, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa8u, 0xffu, 0x04u, 0x28u, 0xfau, 0xd8u, 0x06u, 0x4bu, 0x07u, 0x49u, 0x1bu, 0x68u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x11u, 0x60u, 0xdau, 0x68u, 0xa2u, 0x18u, - 0x15u, 0x60u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0x10u, 0x23u, 0x23u, 0x60u, 0x70u, 0xbdu, 0xd0u, 0x03u, 0x00u, 0x08u, + 0x15u, 0x60u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0x10u, 0x23u, 0x23u, 0x60u, 0x70u, 0xbdu, 0xe0u, 0x03u, 0x00u, 0x08u, 0x0cu, 0x00u, 0x00u, 0x70u, 0x00u, 0x23u, 0x70u, 0xb5u, 0x04u, 0x00u, 0x0eu, 0x00u, 0x0bu, 0x60u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x8cu, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x14u, 0x4du, 0x15u, 0x4au, 0x2bu, 0x68u, 0x20u, 0x00u, 0xdbu, 0x68u, 0xe3u, 0x18u, 0x1au, 0x60u, 0xffu, 0xf7u, 0x8bu, 0xffu, 0x71u, 0x68u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xcfu, 0xffu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x7au, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x2au, 0x68u, 0x0du, 0x49u, 0xd3u, 0x68u, 0xe3u, 0x18u, 0x19u, 0x60u, 0x13u, 0x68u, 0xe3u, 0x18u, 0x1au, 0x68u, 0x00u, 0x2au, 0xfcu, 0xd1u, 0x70u, 0x68u, 0xffu, 0xf7u, 0x87u, 0xffu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x68u, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, - 0x2bu, 0x68u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0x04u, 0x4bu, 0x23u, 0x60u, 0x70u, 0xbdu, 0xd0u, 0x03u, 0x00u, 0x08u, + 0x2bu, 0x68u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0x04u, 0x4bu, 0x23u, 0x60u, 0x70u, 0xbdu, 0xe0u, 0x03u, 0x00u, 0x08u, 0x00u, 0x00u, 0x10u, 0x41u, 0x01u, 0xc0u, 0x10u, 0x40u, 0x11u, 0x10u, 0x10u, 0x41u, 0x70u, 0xb5u, 0x0eu, 0x00u, 0x11u, 0x00u, 0x32u, 0x68u, 0x05u, 0x00u, 0x9cu, 0x18u, 0x1au, 0x00u, 0xffu, 0xf7u, 0x81u, 0xffu, 0x10u, 0x2cu, 0x01u, 0xd8u, 0x34u, 0x60u, 0x70u, 0xbdu, 0x28u, 0x00u, 0xffu, 0xf7u, 0x48u, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x05u, 0x4bu, 0x06u, 0x4au, 0x1bu, 0x68u, 0x28u, 0x00u, 0xdbu, 0x68u, 0x10u, 0x3cu, 0xebu, 0x18u, 0x1au, 0x60u, - 0xffu, 0xf7u, 0x46u, 0xffu, 0xebu, 0xe7u, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, 0x18u, 0x00u, 0x10u, 0x41u, + 0xffu, 0xf7u, 0x46u, 0xffu, 0xebu, 0xe7u, 0xc0u, 0x46u, 0xe0u, 0x03u, 0x00u, 0x08u, 0x18u, 0x00u, 0x10u, 0x41u, 0xf0u, 0xb5u, 0x10u, 0x25u, 0x87u, 0xb0u, 0x0fu, 0x00u, 0x04u, 0x00u, 0x01u, 0x92u, 0x00u, 0x21u, 0x2au, 0x00u, - 0x02u, 0xa8u, 0x06u, 0xf0u, 0x7eu, 0xf9u, 0x80u, 0x23u, 0x7eu, 0x68u, 0x3fu, 0x68u, 0x02u, 0xaau, 0x13u, 0x70u, + 0x02u, 0xa8u, 0x06u, 0xf0u, 0x82u, 0xf9u, 0x80u, 0x23u, 0x7eu, 0x68u, 0x3fu, 0x68u, 0x02u, 0xaau, 0x13u, 0x70u, 0x02u, 0xa9u, 0xeau, 0x1bu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x53u, 0xffu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x1eu, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x18u, 0x4du, 0x19u, 0x4au, 0x2bu, 0x68u, 0xdbu, 0x68u, 0xe3u, 0x18u, 0x1au, 0x60u, 0x0fu, 0x2fu, 0x02u, 0xd8u, 0x30u, 0x00u, 0xffu, 0xf7u, 0x2du, 0xffu, 0x10u, 0x22u, 0x31u, 0x00u, 0x20u, 0x00u, @@ -261,10 +261,10 @@ const uint8_t cy_m0p_image[] = { 0x0fu, 0x4au, 0xdbu, 0x68u, 0x20u, 0x00u, 0xe3u, 0x18u, 0x1au, 0x60u, 0xffu, 0xf7u, 0x09u, 0xffu, 0x01u, 0x99u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x4du, 0xffu, 0x20u, 0x00u, 0xffu, 0xf7u, 0xf8u, 0xfeu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x2au, 0x68u, 0x08u, 0x49u, 0xd3u, 0x68u, 0xe3u, 0x18u, 0x19u, 0x60u, 0x13u, 0x68u, 0xe4u, 0x18u, 0x23u, 0x68u, - 0x00u, 0x2bu, 0xfcu, 0xd1u, 0x07u, 0xb0u, 0xf0u, 0xbdu, 0xd0u, 0x03u, 0x00u, 0x08u, 0x18u, 0x00u, 0x10u, 0x41u, + 0x00u, 0x2bu, 0xfcu, 0xd1u, 0x07u, 0xb0u, 0xf0u, 0xbdu, 0xe0u, 0x03u, 0x00u, 0x08u, 0x18u, 0x00u, 0x10u, 0x41u, 0x08u, 0x00u, 0x10u, 0x41u, 0x01u, 0xc0u, 0x10u, 0x40u, 0xf0u, 0xb5u, 0x04u, 0x00u, 0x1eu, 0x00u, 0xa7u, 0xb0u, 0x2cu, 0xabu, 0x0au, 0xadu, 0x1fu, 0x78u, 0x02u, 0x91u, 0x03u, 0x92u, 0x00u, 0x21u, 0x70u, 0x22u, 0x28u, 0x00u, - 0x06u, 0xf0u, 0x27u, 0xf9u, 0x18u, 0x22u, 0x00u, 0x21u, 0x04u, 0xa8u, 0x06u, 0xf0u, 0x22u, 0xf9u, 0x3au, 0x00u, + 0x06u, 0xf0u, 0x2bu, 0xf9u, 0x18u, 0x22u, 0x00u, 0x21u, 0x04u, 0xa8u, 0x06u, 0xf0u, 0x26u, 0xf9u, 0x3au, 0x00u, 0x2eu, 0x9bu, 0x31u, 0x00u, 0x00u, 0x95u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xf3u, 0xfbu, 0x2eu, 0x99u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xaau, 0xfbu, 0x06u, 0xabu, 0x04u, 0xa9u, 0x20u, 0x00u, 0x05u, 0x93u, 0xffu, 0xf7u, 0x2au, 0xffu, 0x03u, 0x9bu, 0x02u, 0x9au, 0x04u, 0xa9u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x60u, 0xffu, 0x20u, 0x00u, 0x2du, 0x9au, @@ -272,30 +272,30 @@ const uint8_t cy_m0p_image[] = { 0x0cu, 0x4cu, 0x7fu, 0x00u, 0x25u, 0x68u, 0xdbu, 0xb2u, 0x2cu, 0x6au, 0x06u, 0x19u, 0x05u, 0x9cu, 0x24u, 0x02u, 0x3cu, 0x40u, 0xffu, 0x3fu, 0x3au, 0x40u, 0x22u, 0x43u, 0x32u, 0x60u, 0x6au, 0x6au, 0x82u, 0x18u, 0x13u, 0x60u, 0xabu, 0x6au, 0xc3u, 0x18u, 0x19u, 0x60u, 0xebu, 0x6au, 0xc0u, 0x18u, 0x06u, 0x9bu, 0x03u, 0x60u, 0x00u, 0x20u, - 0xf0u, 0xbdu, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x0du, 0x00u, 0x11u, 0x00u, 0x86u, 0x22u, + 0xf0u, 0xbdu, 0xc0u, 0x46u, 0xe0u, 0x03u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x0du, 0x00u, 0x11u, 0x00u, 0x86u, 0x22u, 0x04u, 0x00u, 0x04u, 0x98u, 0xd2u, 0x00u, 0xa0u, 0x50u, 0x1au, 0x00u, 0x20u, 0x00u, 0x02u, 0xf0u, 0x68u, 0xfeu, 0x04u, 0x23u, 0x00u, 0x22u, 0x58u, 0x21u, 0x20u, 0x00u, 0x02u, 0xf0u, 0xceu, 0xfeu, 0x08u, 0x21u, 0x06u, 0x4bu, 0x1au, 0x68u, 0x13u, 0x68u, 0xe3u, 0x18u, 0x18u, 0x68u, 0x08u, 0x40u, 0xfcu, 0xd1u, 0x13u, 0x6bu, 0xe4u, 0x18u, - 0x23u, 0x68u, 0x2bu, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, 0x03u, 0x4bu, 0x1bu, 0x68u, - 0x1bu, 0x68u, 0xc0u, 0x18u, 0x03u, 0x68u, 0x00u, 0x2bu, 0xfcu, 0xd1u, 0x70u, 0x47u, 0xd0u, 0x03u, 0x00u, 0x08u, + 0x23u, 0x68u, 0x2bu, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u, 0xe0u, 0x03u, 0x00u, 0x08u, 0x03u, 0x4bu, 0x1bu, 0x68u, + 0x1bu, 0x68u, 0xc0u, 0x18u, 0x03u, 0x68u, 0x00u, 0x2bu, 0xfcu, 0xd1u, 0x70u, 0x47u, 0xe0u, 0x03u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x0fu, 0x26u, 0x09u, 0x4bu, 0x1bu, 0x68u, 0x9cu, 0x68u, 0x05u, 0x19u, 0x2cu, 0x68u, 0x34u, 0x40u, 0x04u, 0x2cu, 0xfbu, 0xd8u, 0xdcu, 0x68u, 0x06u, 0x4du, 0x04u, 0x19u, 0x25u, 0x60u, 0xdcu, 0x68u, 0x04u, 0x19u, - 0x21u, 0x60u, 0xdbu, 0x68u, 0xc0u, 0x18u, 0x02u, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, + 0x21u, 0x60u, 0xdbu, 0x68u, 0xc0u, 0x18u, 0x02u, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u, 0xe0u, 0x03u, 0x00u, 0x08u, 0x08u, 0x00u, 0x00u, 0x70u, 0x10u, 0xb5u, 0x0fu, 0x24u, 0x06u, 0x4bu, 0x19u, 0x68u, 0x8bu, 0x68u, 0xc2u, 0x18u, 0x13u, 0x68u, 0x23u, 0x40u, 0x06u, 0x2bu, 0xfbu, 0xd8u, 0xcbu, 0x68u, 0xc0u, 0x18u, 0xb0u, 0x23u, 0xdbu, 0x05u, - 0x03u, 0x60u, 0x10u, 0xbdu, 0xd0u, 0x03u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x80u, 0x27u, 0x0cu, 0x4cu, 0x7fu, 0x00u, + 0x03u, 0x60u, 0x10u, 0xbdu, 0xe0u, 0x03u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x80u, 0x27u, 0x0cu, 0x4cu, 0x7fu, 0x00u, 0x25u, 0x68u, 0xdbu, 0xb2u, 0x2cu, 0x6au, 0x06u, 0x19u, 0x05u, 0x9cu, 0x24u, 0x02u, 0x3cu, 0x40u, 0xffu, 0x3fu, 0x3au, 0x40u, 0x22u, 0x43u, 0x32u, 0x60u, 0x6au, 0x6au, 0x82u, 0x18u, 0x13u, 0x60u, 0xabu, 0x6au, 0xc3u, 0x18u, 0x19u, 0x60u, 0xebu, 0x6au, 0xc0u, 0x18u, 0x06u, 0x9bu, 0x03u, 0x60u, 0x00u, 0x20u, 0xf0u, 0xbdu, 0xc0u, 0x46u, - 0xd0u, 0x03u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x0du, 0x00u, 0x11u, 0x00u, 0x1au, 0x00u, 0x04u, 0x00u, 0xffu, 0xf7u, + 0xe0u, 0x03u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x0du, 0x00u, 0x11u, 0x00u, 0x1au, 0x00u, 0x04u, 0x00u, 0xffu, 0xf7u, 0xafu, 0xffu, 0x8cu, 0x23u, 0x04u, 0x9au, 0x5bu, 0x01u, 0xe2u, 0x50u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xc2u, 0xffu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x9bu, 0xffu, 0x04u, 0x4bu, 0x00u, 0x20u, 0x1bu, 0x68u, 0x1bu, 0x6bu, 0xe4u, 0x18u, - 0x23u, 0x68u, 0x2bu, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, 0x7fu, 0xb5u, 0x0du, 0x00u, + 0x23u, 0x68u, 0x2bu, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u, 0xe0u, 0x03u, 0x00u, 0x08u, 0x7fu, 0xb5u, 0x0du, 0x00u, 0x19u, 0x00u, 0x0eu, 0x4bu, 0x16u, 0x00u, 0x03u, 0x93u, 0x09u, 0x9au, 0x08u, 0x9bu, 0x04u, 0x00u, 0x02u, 0xf0u, 0xf1u, 0xfdu, 0x03u, 0xabu, 0x69u, 0x00u, 0x59u, 0x18u, 0x08u, 0x23u, 0x89u, 0x5du, 0x20u, 0x00u, 0x00u, 0x93u, 0x00u, 0x22u, 0x04u, 0x3bu, 0x02u, 0xf0u, 0x4eu, 0xfeu, 0x05u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xe4u, 0x18u, 0x02u, 0x23u, 0x22u, 0x68u, 0x1au, 0x42u, 0xfcu, 0xd1u, 0x7fu, 0xbdu, 0xc0u, 0x46u, 0x70u, 0x71u, 0x72u, 0x73u, - 0xd0u, 0x03u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x87u, 0xb0u, 0x05u, 0x93u, 0x20u, 0x4bu, 0x05u, 0x00u, 0x1bu, 0x68u, + 0xe0u, 0x03u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x87u, 0xb0u, 0x05u, 0x93u, 0x20u, 0x4bu, 0x05u, 0x00u, 0x1bu, 0x68u, 0x04u, 0x91u, 0x03u, 0x92u, 0x1fu, 0x1eu, 0x02u, 0xd0u, 0x9bu, 0x6bu, 0xc3u, 0x18u, 0x1fu, 0x68u, 0x00u, 0x26u, 0x1bu, 0x4bu, 0xf2u, 0x00u, 0xd2u, 0x18u, 0x03u, 0x99u, 0x08u, 0x23u, 0x28u, 0x00u, 0x02u, 0xf0u, 0x9cu, 0xfeu, 0x44u, 0x1eu, 0xa0u, 0x41u, 0x44u, 0x42u, 0x17u, 0x48u, 0x17u, 0x4bu, 0x04u, 0x40u, 0x01u, 0x36u, 0xe4u, 0x18u, @@ -303,8 +303,8 @@ const uint8_t cy_m0p_image[] = { 0x03u, 0x9au, 0x02u, 0x99u, 0x28u, 0x00u, 0x08u, 0x23u, 0x02u, 0xf0u, 0x4cu, 0xfeu, 0x08u, 0x36u, 0x0cu, 0x9au, 0x39u, 0x00u, 0x28u, 0x00u, 0x08u, 0x23u, 0x02u, 0xf0u, 0x45u, 0xfeu, 0x02u, 0x9bu, 0x04u, 0x9au, 0x28u, 0x00u, 0x01u, 0x97u, 0x00u, 0x96u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xa1u, 0xffu, 0x28u, 0x00u, 0x08u, 0x23u, 0x32u, 0x00u, - 0x05u, 0x99u, 0x02u, 0xf0u, 0x37u, 0xfeu, 0x20u, 0x00u, 0x07u, 0xb0u, 0xf0u, 0xbdu, 0xd0u, 0x03u, 0x00u, 0x08u, - 0x60u, 0x71u, 0x00u, 0x10u, 0xfdu, 0xffu, 0xceu, 0xffu, 0x03u, 0x00u, 0x31u, 0x00u, 0xf0u, 0xb5u, 0x89u, 0xb0u, + 0x05u, 0x99u, 0x02u, 0xf0u, 0x37u, 0xfeu, 0x20u, 0x00u, 0x07u, 0xb0u, 0xf0u, 0xbdu, 0xe0u, 0x03u, 0x00u, 0x08u, + 0x68u, 0x71u, 0x00u, 0x10u, 0xfdu, 0xffu, 0xceu, 0xffu, 0x03u, 0x00u, 0x31u, 0x00u, 0xf0u, 0xb5u, 0x89u, 0xb0u, 0x07u, 0x93u, 0x25u, 0x4bu, 0x04u, 0x00u, 0x1bu, 0x68u, 0x06u, 0x91u, 0x04u, 0x92u, 0x03u, 0x93u, 0x00u, 0x2bu, 0x03u, 0xd0u, 0x9bu, 0x6bu, 0xc3u, 0x18u, 0x1bu, 0x68u, 0x03u, 0x93u, 0x00u, 0x27u, 0x1fu, 0x4bu, 0x04u, 0x9du, 0xfeu, 0x00u, 0xf6u, 0x18u, 0x2bu, 0x00u, 0x10u, 0x33u, 0x05u, 0x93u, 0x08u, 0x23u, 0x32u, 0x00u, 0x29u, 0x00u, @@ -314,20 +314,20 @@ const uint8_t cy_m0p_image[] = { 0x20u, 0x00u, 0x08u, 0x23u, 0x02u, 0xf0u, 0xf6u, 0xfdu, 0x03u, 0x9fu, 0x03u, 0x9bu, 0x08u, 0x37u, 0x01u, 0x93u, 0x06u, 0x9au, 0x33u, 0x00u, 0x20u, 0x00u, 0x00u, 0x97u, 0x01u, 0x21u, 0xffu, 0xf7u, 0x4fu, 0xffu, 0x20u, 0x00u, 0x08u, 0x23u, 0x3au, 0x00u, 0x07u, 0x99u, 0x02u, 0xf0u, 0xe5u, 0xfdu, 0x28u, 0x00u, 0x09u, 0xb0u, 0xf0u, 0xbdu, - 0x08u, 0x35u, 0xcau, 0xe7u, 0x02u, 0x4du, 0xd4u, 0xe7u, 0xd0u, 0x03u, 0x00u, 0x08u, 0x60u, 0x71u, 0x00u, 0x10u, + 0x08u, 0x35u, 0xcau, 0xe7u, 0x02u, 0x4du, 0xd4u, 0xe7u, 0xe0u, 0x03u, 0x00u, 0x08u, 0x68u, 0x71u, 0x00u, 0x10u, 0x03u, 0x00u, 0x31u, 0x00u, 0x70u, 0xb5u, 0x0fu, 0x26u, 0x0bu, 0x4bu, 0x1bu, 0x68u, 0x9cu, 0x68u, 0x05u, 0x19u, 0x2cu, 0x68u, 0x34u, 0x40u, 0x04u, 0x2cu, 0xfbu, 0xd8u, 0x86u, 0x25u, 0x6du, 0x01u, 0x44u, 0x59u, 0x00u, 0x2cu, 0xfcu, 0xdbu, 0xdcu, 0x68u, 0x05u, 0x4du, 0x04u, 0x19u, 0x25u, 0x60u, 0xdcu, 0x68u, 0x04u, 0x19u, 0x21u, 0x60u, - 0xdbu, 0x68u, 0xc0u, 0x18u, 0x02u, 0x60u, 0x70u, 0xbdu, 0xd0u, 0x03u, 0x00u, 0x08u, 0x08u, 0x00u, 0x00u, 0x71u, + 0xdbu, 0x68u, 0xc0u, 0x18u, 0x02u, 0x60u, 0x70u, 0xbdu, 0xe0u, 0x03u, 0x00u, 0x08u, 0x08u, 0x00u, 0x00u, 0x71u, 0x30u, 0xb5u, 0x0fu, 0x25u, 0x06u, 0x4bu, 0x1cu, 0x68u, 0xa3u, 0x68u, 0xc2u, 0x18u, 0x13u, 0x68u, 0x2bu, 0x40u, 0x06u, 0x2bu, 0xfbu, 0xd8u, 0xe3u, 0x68u, 0x09u, 0x06u, 0xc0u, 0x18u, 0x01u, 0x60u, 0x30u, 0xbdu, 0xc0u, 0x46u, - 0xd0u, 0x03u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x0fu, 0x27u, 0x09u, 0x4cu, 0x26u, 0x68u, 0xb4u, 0x68u, 0x05u, 0x19u, + 0xe0u, 0x03u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x0fu, 0x27u, 0x09u, 0x4cu, 0x26u, 0x68u, 0xb4u, 0x68u, 0x05u, 0x19u, 0x2cu, 0x68u, 0x3cu, 0x40u, 0x06u, 0x2cu, 0xfbu, 0xd8u, 0xf4u, 0x68u, 0x09u, 0x03u, 0x00u, 0x19u, 0x80u, 0x24u, 0xe4u, 0x05u, 0x22u, 0x43u, 0x11u, 0x43u, 0x1bu, 0x04u, 0x19u, 0x43u, 0x01u, 0x60u, 0xf0u, 0xbdu, 0xc0u, 0x46u, - 0xd0u, 0x03u, 0x00u, 0x08u, 0x30u, 0xb5u, 0x0fu, 0x25u, 0x09u, 0x4bu, 0x1bu, 0x68u, 0x9au, 0x68u, 0x84u, 0x18u, + 0xe0u, 0x03u, 0x00u, 0x08u, 0x30u, 0xb5u, 0x0fu, 0x25u, 0x09u, 0x4bu, 0x1bu, 0x68u, 0x9au, 0x68u, 0x84u, 0x18u, 0x22u, 0x68u, 0x2au, 0x40u, 0x04u, 0x2au, 0xfbu, 0xd8u, 0xdau, 0x68u, 0x06u, 0x4cu, 0x82u, 0x18u, 0x14u, 0x60u, 0xdau, 0x68u, 0x82u, 0x18u, 0x11u, 0x60u, 0xdbu, 0x68u, 0xc0u, 0x18u, 0x08u, 0x23u, 0x03u, 0x60u, 0x30u, 0xbdu, - 0xd0u, 0x03u, 0x00u, 0x08u, 0x0cu, 0x00u, 0x00u, 0x70u, 0xf7u, 0xb5u, 0x04u, 0x00u, 0x16u, 0x00u, 0x1fu, 0x00u, + 0xe0u, 0x03u, 0x00u, 0x08u, 0x0cu, 0x00u, 0x00u, 0x70u, 0xf7u, 0xb5u, 0x04u, 0x00u, 0x16u, 0x00u, 0x1fu, 0x00u, 0x00u, 0x25u, 0x01u, 0x91u, 0x1cu, 0x4bu, 0xeau, 0x00u, 0xd2u, 0x18u, 0x31u, 0x00u, 0x08u, 0x23u, 0x20u, 0x00u, 0x02u, 0xf0u, 0xb2u, 0xfeu, 0x00u, 0x28u, 0x2cu, 0xd0u, 0x01u, 0x35u, 0x10u, 0x2du, 0xf2u, 0xd1u, 0x00u, 0x25u, 0x31u, 0x00u, 0x20u, 0x00u, 0x08u, 0x22u, 0xffu, 0xf7u, 0x85u, 0xffu, 0x08u, 0x23u, 0x20u, 0x00u, 0x1au, 0x00u, @@ -335,7 +335,7 @@ const uint8_t cy_m0p_image[] = { 0x39u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xbeu, 0xffu, 0x08u, 0x23u, 0x20u, 0x00u, 0x1au, 0x00u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xa0u, 0xffu, 0x01u, 0x99u, 0x20u, 0x00u, 0x4bu, 0x1eu, 0x99u, 0x41u, 0x52u, 0x31u, 0xffu, 0xf7u, 0x87u, 0xffu, 0x20u, 0x00u, 0x08u, 0x23u, 0x01u, 0x22u, 0x0cu, 0x21u, 0xffu, 0xf7u, 0x93u, 0xffu, 0x28u, 0x00u, - 0xfeu, 0xbdu, 0x02u, 0x4du, 0xd4u, 0xe7u, 0xc0u, 0x46u, 0xe0u, 0x71u, 0x00u, 0x10u, 0x03u, 0x00u, 0x31u, 0x00u, + 0xfeu, 0xbdu, 0x02u, 0x4du, 0xd4u, 0xe7u, 0xc0u, 0x46u, 0xe8u, 0x71u, 0x00u, 0x10u, 0x03u, 0x00u, 0x31u, 0x00u, 0xf0u, 0xb5u, 0x04u, 0x00u, 0x00u, 0x27u, 0x85u, 0xb0u, 0x02u, 0x91u, 0x00u, 0x92u, 0x03u, 0x93u, 0x26u, 0x4bu, 0x00u, 0x9du, 0xfeu, 0x00u, 0xf6u, 0x18u, 0x2bu, 0x00u, 0x10u, 0x33u, 0x01u, 0x93u, 0x08u, 0x23u, 0x32u, 0x00u, 0x29u, 0x00u, 0x20u, 0x00u, 0x02u, 0xf0u, 0x68u, 0xfeu, 0x00u, 0x28u, 0x04u, 0xd0u, 0x01u, 0x9bu, 0x9du, 0x42u, @@ -346,15 +346,15 @@ const uint8_t cy_m0p_image[] = { 0x20u, 0x00u, 0xffu, 0xf7u, 0x67u, 0xffu, 0x08u, 0x23u, 0x20u, 0x00u, 0x1au, 0x00u, 0x00u, 0x21u, 0xffu, 0xf7u, 0x49u, 0xffu, 0x02u, 0x99u, 0x20u, 0x00u, 0x4bu, 0x1eu, 0x99u, 0x41u, 0x54u, 0x31u, 0xffu, 0xf7u, 0x30u, 0xffu, 0x20u, 0x00u, 0x08u, 0x23u, 0x01u, 0x22u, 0x0cu, 0x21u, 0xffu, 0xf7u, 0x3cu, 0xffu, 0x28u, 0x00u, 0x05u, 0xb0u, - 0xf0u, 0xbdu, 0x08u, 0x35u, 0xbau, 0xe7u, 0xc0u, 0x46u, 0xe0u, 0x71u, 0x00u, 0x10u, 0x03u, 0x00u, 0x31u, 0x00u, + 0xf0u, 0xbdu, 0x08u, 0x35u, 0xbau, 0xe7u, 0xc0u, 0x46u, 0xe8u, 0x71u, 0x00u, 0x10u, 0x03u, 0x00u, 0x31u, 0x00u, 0x42u, 0x1eu, 0x03u, 0x00u, 0x00u, 0x20u, 0x04u, 0x2au, 0x03u, 0xd8u, 0x28u, 0x30u, 0x58u, 0x43u, 0x01u, 0x4bu, - 0xc0u, 0x18u, 0x70u, 0x47u, 0x60u, 0x72u, 0x00u, 0x10u, 0x09u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xc0u, 0x18u, + 0xc0u, 0x18u, 0x70u, 0x47u, 0x68u, 0x72u, 0x00u, 0x10u, 0x09u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xc0u, 0x18u, 0x08u, 0x4bu, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x04u, 0xd8u, 0x80u, 0x23u, 0x02u, 0x68u, 0x1au, 0x42u, 0xfcu, 0xd1u, 0x70u, 0x47u, 0x03u, 0x68u, 0x00u, 0x2bu, 0xfcu, 0xd1u, 0xfau, 0xe7u, 0xc0u, 0x46u, - 0xd0u, 0x03u, 0x00u, 0x08u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x0bu, 0x00u, 0x13u, 0x22u, 0x00u, 0x21u, + 0xe0u, 0x03u, 0x00u, 0x08u, 0xecu, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x0bu, 0x00u, 0x13u, 0x22u, 0x00u, 0x21u, 0x02u, 0xf0u, 0xf2u, 0xf9u, 0x10u, 0xbdu, 0x00u, 0x00u, 0x10u, 0xb5u, 0x13u, 0x00u, 0x07u, 0x4au, 0x12u, 0x68u, 0x29u, 0x32u, 0x14u, 0x78u, 0x0cu, 0x22u, 0x1fu, 0x2cu, 0x00u, 0xd9u, 0x04u, 0x32u, 0x91u, 0x40u, 0x01u, 0x3bu, - 0x0bu, 0x43u, 0x12u, 0x22u, 0x00u, 0x21u, 0x02u, 0xf0u, 0xdfu, 0xf9u, 0x10u, 0xbdu, 0xdcu, 0x05u, 0x00u, 0x08u, + 0x0bu, 0x43u, 0x12u, 0x22u, 0x00u, 0x21u, 0x02u, 0xf0u, 0xdfu, 0xf9u, 0x10u, 0xbdu, 0xecu, 0x05u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0xadu, 0xb0u, 0x04u, 0x00u, 0x04u, 0x91u, 0x05u, 0x92u, 0x03u, 0x93u, 0x00u, 0x29u, 0x00u, 0xd1u, 0x15u, 0xe1u, 0x03u, 0x9bu, 0x00u, 0x2bu, 0x00u, 0xd1u, 0x11u, 0xe1u, 0x32u, 0x9bu, 0x00u, 0x2bu, 0x00u, 0xd1u, 0x0du, 0xe1u, 0x33u, 0x9bu, 0x00u, 0x2bu, 0x00u, 0xd1u, 0x09u, 0xe1u, 0x32u, 0x9bu, 0x58u, 0x78u, 0xffu, 0xf7u, @@ -392,7 +392,7 @@ const uint8_t cy_m0p_image[] = { 0x00u, 0x28u, 0x00u, 0xd0u, 0x71u, 0xe7u, 0x03u, 0x9bu, 0xe9u, 0x1du, 0xc9u, 0x08u, 0x59u, 0x18u, 0x0au, 0x22u, 0x2bu, 0x00u, 0x20u, 0x00u, 0x04u, 0xf0u, 0xc4u, 0xf8u, 0x68u, 0xe7u, 0x08u, 0x4eu, 0x6bu, 0xe7u, 0x07u, 0x4eu, 0x6eu, 0xe7u, 0x07u, 0x4eu, 0x6cu, 0xe7u, 0xc0u, 0x46u, 0x09u, 0x80u, 0x00u, 0x00u, 0x01u, 0x00u, 0x32u, 0x00u, - 0xdcu, 0x05u, 0x00u, 0x08u, 0xb0u, 0xb0u, 0x00u, 0x00u, 0x0bu, 0x80u, 0x00u, 0x00u, 0x0bu, 0x00u, 0x32u, 0x00u, + 0xecu, 0x05u, 0x00u, 0x08u, 0xb0u, 0xb0u, 0x00u, 0x00u, 0x0bu, 0x80u, 0x00u, 0x00u, 0x0bu, 0x00u, 0x32u, 0x00u, 0x0au, 0x00u, 0x32u, 0x00u, 0xf0u, 0xb5u, 0x87u, 0xb0u, 0x04u, 0x00u, 0x0fu, 0x1eu, 0x04u, 0x92u, 0x03u, 0x93u, 0x00u, 0xd1u, 0x8bu, 0xe1u, 0x00u, 0x2au, 0x00u, 0xd1u, 0x88u, 0xe1u, 0x0cu, 0x9bu, 0x00u, 0x2bu, 0x00u, 0xd1u, 0x84u, 0xe1u, 0x0du, 0x9bu, 0x00u, 0x2bu, 0x00u, 0xd1u, 0x80u, 0xe1u, 0x58u, 0x78u, 0xffu, 0xf7u, 0x78u, 0xfeu, @@ -444,11 +444,11 @@ const uint8_t cy_m0p_image[] = { 0x05u, 0x21u, 0x20u, 0x00u, 0x03u, 0xf0u, 0x7au, 0xffu, 0x00u, 0x28u, 0x09u, 0xd0u, 0x01u, 0x23u, 0x0cu, 0x9au, 0x13u, 0x70u, 0x0eu, 0x49u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x27u, 0xfdu, 0x38u, 0x00u, 0x07u, 0xb0u, 0xf0u, 0xbdu, 0x0cu, 0x9bu, 0x18u, 0x70u, 0xf5u, 0xe7u, 0x04u, 0x4fu, 0x09u, 0x49u, 0xf3u, 0xe7u, 0x02u, 0x4fu, 0xf4u, 0xe7u, - 0x08u, 0x4fu, 0xf2u, 0xe7u, 0xf5u, 0xffu, 0xcdu, 0xffu, 0x0bu, 0x00u, 0x32u, 0x00u, 0xdcu, 0x05u, 0x00u, 0x08u, + 0x08u, 0x4fu, 0xf2u, 0xe7u, 0xf5u, 0xffu, 0xcdu, 0xffu, 0x0bu, 0x00u, 0x32u, 0x00u, 0xecu, 0x05u, 0x00u, 0x08u, 0x80u, 0x80u, 0x00u, 0x00u, 0x08u, 0x60u, 0x00u, 0x00u, 0x06u, 0x80u, 0x00u, 0x00u, 0xf1u, 0x7eu, 0x00u, 0x00u, 0x30u, 0x60u, 0x00u, 0x00u, 0x0au, 0x00u, 0x32u, 0x00u, 0x10u, 0xb5u, 0x13u, 0x00u, 0x07u, 0x4au, 0x12u, 0x68u, 0x29u, 0x32u, 0x14u, 0x78u, 0x0cu, 0x22u, 0x1fu, 0x2cu, 0x00u, 0xd9u, 0x04u, 0x32u, 0x91u, 0x40u, 0x01u, 0x3bu, - 0x0bu, 0x43u, 0x12u, 0x22u, 0x00u, 0x21u, 0x01u, 0xf0u, 0xefu, 0xfeu, 0x10u, 0xbdu, 0xdcu, 0x05u, 0x00u, 0x08u, + 0x0bu, 0x43u, 0x12u, 0x22u, 0x00u, 0x21u, 0x01u, 0xf0u, 0xefu, 0xfeu, 0x10u, 0xbdu, 0xecu, 0x05u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x04u, 0x00u, 0x85u, 0xb0u, 0x08u, 0x00u, 0x02u, 0x91u, 0x03u, 0x92u, 0x1eu, 0x00u, 0xffu, 0xf7u, 0xc7u, 0xfcu, 0x07u, 0x1eu, 0x00u, 0xd1u, 0x7bu, 0xe0u, 0x03u, 0x9bu, 0x00u, 0x2bu, 0x00u, 0xd1u, 0x77u, 0xe0u, 0x00u, 0x2eu, 0x00u, 0xd1u, 0x74u, 0xe0u, 0x73u, 0x68u, 0x00u, 0x2bu, 0x00u, 0xd1u, 0x70u, 0xe0u, 0xb3u, 0x68u, @@ -472,25 +472,25 @@ const uint8_t cy_m0p_image[] = { 0x12u, 0x01u, 0x13u, 0x43u, 0x09u, 0x03u, 0x0bu, 0x43u, 0x36u, 0x22u, 0x00u, 0x21u, 0x01u, 0xf0u, 0x44u, 0xfeu, 0x10u, 0xbdu, 0x00u, 0x00u, 0x09u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xc0u, 0x18u, 0x08u, 0x4bu, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x04u, 0xd8u, 0x80u, 0x23u, 0x02u, 0x68u, 0x1au, 0x42u, 0xfcu, 0xd1u, - 0x70u, 0x47u, 0x03u, 0x68u, 0x00u, 0x2bu, 0xfcu, 0xd1u, 0xfau, 0xe7u, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, - 0xdcu, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, 0xffu, 0xf7u, 0xe4u, 0xffu, 0x02u, 0x4bu, 0x1bu, 0x68u, - 0xdbu, 0x6bu, 0xe4u, 0x18u, 0x20u, 0x68u, 0x10u, 0xbdu, 0xd0u, 0x03u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x0au, 0x4bu, + 0x70u, 0x47u, 0x03u, 0x68u, 0x00u, 0x2bu, 0xfcu, 0xd1u, 0xfau, 0xe7u, 0xc0u, 0x46u, 0xe0u, 0x03u, 0x00u, 0x08u, + 0xecu, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, 0xffu, 0xf7u, 0xe4u, 0xffu, 0x02u, 0x4bu, 0x1bu, 0x68u, + 0xdbu, 0x6bu, 0xe4u, 0x18u, 0x20u, 0x68u, 0x10u, 0xbdu, 0xe0u, 0x03u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x0au, 0x4bu, 0x09u, 0x03u, 0x1bu, 0x68u, 0x12u, 0x01u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x06u, 0xd8u, 0x13u, 0x00u, 0x25u, 0x22u, 0x0bu, 0x43u, 0x00u, 0x21u, 0x01u, 0xf0u, 0x0fu, 0xfeu, 0x10u, 0xbdu, 0x0fu, 0x23u, 0x13u, 0x43u, - 0x0bu, 0x43u, 0x24u, 0x22u, 0xf6u, 0xe7u, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x07u, 0x4bu, + 0x0bu, 0x43u, 0x24u, 0x22u, 0xf6u, 0xe7u, 0xc0u, 0x46u, 0xecu, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x07u, 0x4bu, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x05u, 0xd8u, 0x05u, 0x4bu, 0x21u, 0x22u, 0x00u, 0x21u, - 0x01u, 0xf0u, 0xfau, 0xfdu, 0x10u, 0xbdu, 0x03u, 0x4bu, 0xf8u, 0xe7u, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, + 0x01u, 0xf0u, 0xfau, 0xfdu, 0x10u, 0xbdu, 0x03u, 0x4bu, 0xf8u, 0xe7u, 0xc0u, 0x46u, 0xecu, 0x05u, 0x00u, 0x08u, 0xc0u, 0xc0u, 0x00u, 0x00u, 0xcfu, 0xc0u, 0x00u, 0x00u, 0x00u, 0x23u, 0x10u, 0xb5u, 0x10u, 0x22u, 0x19u, 0x00u, 0x01u, 0xf0u, 0xeau, 0xfdu, 0x10u, 0xbdu, 0x09u, 0x03u, 0x0bu, 0x00u, 0x13u, 0x43u, 0x00u, 0x22u, 0x10u, 0xb5u, 0x11u, 0x00u, 0x01u, 0xf0u, 0xe1u, 0xfdu, 0x10u, 0xbdu, 0x10u, 0xb5u, 0x13u, 0x00u, 0x07u, 0x4au, 0x12u, 0x68u, 0x29u, 0x32u, 0x14u, 0x78u, 0x0cu, 0x22u, 0x1fu, 0x2cu, 0x00u, 0xd9u, 0x04u, 0x32u, 0x91u, 0x40u, 0x01u, 0x3bu, - 0x0bu, 0x43u, 0x12u, 0x22u, 0x00u, 0x21u, 0x01u, 0xf0u, 0xcfu, 0xfdu, 0x10u, 0xbdu, 0xdcu, 0x05u, 0x00u, 0x08u, + 0x0bu, 0x43u, 0x12u, 0x22u, 0x00u, 0x21u, 0x01u, 0xf0u, 0xcfu, 0xfdu, 0x10u, 0xbdu, 0xecu, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x1fu, 0x24u, 0x08u, 0x4bu, 0x89u, 0x06u, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x9cu, 0x42u, 0xa4u, 0x41u, 0x13u, 0x00u, 0x64u, 0x42u, 0x0cu, 0x34u, 0xa3u, 0x40u, 0x80u, 0x22u, 0x0bu, 0x43u, 0x00u, 0x21u, - 0x01u, 0xf0u, 0xbau, 0xfdu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x14u, 0x00u, + 0x01u, 0xf0u, 0xbau, 0xfdu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0xecu, 0x05u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x14u, 0x00u, 0x07u, 0x4au, 0x15u, 0x68u, 0x24u, 0x22u, 0x29u, 0x35u, 0x2du, 0x78u, 0x1fu, 0x2du, 0x00u, 0xd9u, 0x01u, 0x3au, 0x24u, 0x01u, 0x23u, 0x43u, 0x09u, 0x03u, 0x0bu, 0x43u, 0x00u, 0x21u, 0x01u, 0xf0u, 0xa5u, 0xfdu, 0x70u, 0xbdu, - 0xdcu, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x0bu, 0x00u, 0x13u, 0x22u, 0x00u, 0x21u, 0x01u, 0xf0u, 0x9cu, 0xfdu, + 0xecu, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x0bu, 0x00u, 0x13u, 0x22u, 0x00u, 0x21u, 0x01u, 0xf0u, 0x9cu, 0xfdu, 0x10u, 0xbdu, 0x00u, 0x23u, 0x10u, 0xb5u, 0x11u, 0x22u, 0x19u, 0x00u, 0x01u, 0xf0u, 0x95u, 0xfdu, 0x10u, 0xbdu, 0x70u, 0xb5u, 0x04u, 0x00u, 0x1bu, 0x4du, 0xffu, 0xf7u, 0x9fu, 0xffu, 0x20u, 0x00u, 0x01u, 0x22u, 0x02u, 0x21u, 0xffu, 0xf7u, 0xa1u, 0xffu, 0x20u, 0x00u, 0x00u, 0x22u, 0x03u, 0x21u, 0xffu, 0xf7u, 0x9cu, 0xffu, 0x2au, 0x00u, @@ -523,7 +523,7 @@ const uint8_t cy_m0p_image[] = { 0xffu, 0xf7u, 0x70u, 0xfeu, 0x94u, 0x4bu, 0x1bu, 0x78u, 0x00u, 0x2bu, 0x0bu, 0xd0u, 0x01u, 0x2bu, 0x01u, 0xd1u, 0x00u, 0xf0u, 0x35u, 0xfdu, 0x0eu, 0x9bu, 0x00u, 0x22u, 0x01u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x50u, 0xffu, 0x00u, 0xf0u, 0x24u, 0xfdu, 0x8du, 0x4bu, 0x18u, 0x78u, 0x01u, 0x38u, 0x04u, 0x28u, 0x01u, 0xd9u, 0x00u, 0xf0u, - 0x1du, 0xfdu, 0x04u, 0xf0u, 0x39u, 0xffu, 0x05u, 0x00u, 0x89u, 0x00u, 0x25u, 0x01u, 0x73u, 0x03u, 0x18u, 0x05u, + 0x1du, 0xfdu, 0x04u, 0xf0u, 0x3du, 0xffu, 0x05u, 0x00u, 0x89u, 0x00u, 0x25u, 0x01u, 0x73u, 0x03u, 0x18u, 0x05u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa1u, 0xfeu, 0x01u, 0x22u, 0x04u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa3u, 0xfeu, 0x00u, 0x22u, 0x05u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x9eu, 0xfeu, 0x80u, 0x22u, 0x02u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa2u, 0xfeu, 0xc0u, 0x22u, 0x03u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x9du, 0xfeu, 0xc0u, 0x22u, @@ -557,7 +557,7 @@ const uint8_t cy_m0p_image[] = { 0x43u, 0xfdu, 0x16u, 0x4bu, 0x36u, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0x01u, 0xf0u, 0x9du, 0xfbu, 0x03u, 0x23u, 0x02u, 0x22u, 0x04u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x4au, 0xfdu, 0x09u, 0x4bu, 0x3du, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0x01u, 0xf0u, 0x91u, 0xfbu, 0x00u, 0x21u, 0x06u, 0x4bu, 0x37u, 0x22u, 0x20u, 0x00u, 0x01u, 0xf0u, - 0x8bu, 0xfbu, 0x0eu, 0x21u, 0x70u, 0xe7u, 0xc0u, 0x46u, 0x80u, 0x00u, 0x00u, 0x08u, 0xccu, 0x03u, 0x00u, 0x08u, + 0x8bu, 0xfbu, 0x0eu, 0x21u, 0x70u, 0xe7u, 0xc0u, 0x46u, 0x80u, 0x00u, 0x00u, 0x08u, 0xdcu, 0x03u, 0x00u, 0x08u, 0x4eu, 0x00u, 0x40u, 0x00u, 0x4eu, 0x40u, 0x30u, 0x00u, 0x20u, 0x30u, 0x00u, 0x00u, 0x23u, 0x20u, 0x00u, 0x00u, 0x10u, 0x20u, 0x00u, 0x00u, 0x2eu, 0x00u, 0x40u, 0x00u, 0x2eu, 0x20u, 0x30u, 0x00u, 0x2eu, 0x20u, 0x40u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x81u, 0xfdu, 0x01u, 0x22u, 0x0au, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x83u, 0xfdu, @@ -688,7 +688,7 @@ const uint8_t cy_m0p_image[] = { 0x8bu, 0xffu, 0x00u, 0x21u, 0x44u, 0x4bu, 0x37u, 0x22u, 0x20u, 0x00u, 0x00u, 0xf0u, 0x85u, 0xffu, 0xe0u, 0x21u, 0x49u, 0x00u, 0xffu, 0xf7u, 0x69u, 0xfbu, 0x20u, 0x00u, 0xffu, 0xf7u, 0xeau, 0xf9u, 0x01u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xd8u, 0xf9u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xdcu, 0xf9u, 0x09u, 0xb0u, 0xf0u, 0xbdu, 0x42u, 0x4bu, - 0x18u, 0x78u, 0x01u, 0x38u, 0x04u, 0x28u, 0xf1u, 0xd8u, 0x04u, 0xf0u, 0x04u, 0xfau, 0x05u, 0x00u, 0x84u, 0x00u, + 0x18u, 0x78u, 0x01u, 0x38u, 0x04u, 0x28u, 0xf1u, 0xd8u, 0x04u, 0xf0u, 0x08u, 0xfau, 0x05u, 0x00u, 0x84u, 0x00u, 0xd1u, 0x00u, 0xc7u, 0x01u, 0xedu, 0xffu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x76u, 0xf9u, 0x01u, 0x22u, 0x04u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x78u, 0xf9u, 0x00u, 0x22u, 0x05u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x73u, 0xf9u, 0x02u, 0x22u, 0x00u, 0x21u, 0xffu, 0x32u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x76u, 0xf9u, 0x80u, 0x22u, 0x01u, 0x21u, @@ -704,7 +704,7 @@ const uint8_t cy_m0p_image[] = { 0x0bu, 0xffu, 0x00u, 0x21u, 0x0eu, 0x4bu, 0x37u, 0x22u, 0x20u, 0x00u, 0x00u, 0xf0u, 0x05u, 0xffu, 0x03u, 0x21u, 0xffu, 0xf7u, 0xeau, 0xfau, 0x9eu, 0x00u, 0x40u, 0x00u, 0x9eu, 0x90u, 0x30u, 0x00u, 0x82u, 0x70u, 0x00u, 0x00u, 0x73u, 0x70u, 0x00u, 0x00u, 0x9eu, 0x90u, 0x40u, 0x00u, 0x72u, 0x70u, 0x00u, 0x00u, 0x70u, 0x70u, 0x00u, 0x00u, - 0x71u, 0x70u, 0x00u, 0x00u, 0x60u, 0x70u, 0x00u, 0x00u, 0xccu, 0x03u, 0x00u, 0x08u, 0x12u, 0x10u, 0x00u, 0x00u, + 0x71u, 0x70u, 0x00u, 0x00u, 0x60u, 0x70u, 0x00u, 0x00u, 0xdcu, 0x03u, 0x00u, 0x08u, 0x12u, 0x10u, 0x00u, 0x00u, 0x4eu, 0x40u, 0x30u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xf7u, 0xf8u, 0x20u, 0x00u, 0x01u, 0x22u, 0x04u, 0x21u, 0xffu, 0xf7u, 0xf9u, 0xf8u, 0x20u, 0x00u, 0x00u, 0x22u, 0x05u, 0x21u, 0xffu, 0xf7u, 0xf4u, 0xf8u, 0x42u, 0x22u, 0x20u, 0x00u, 0xffu, 0x32u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xf7u, 0xf8u, 0xa0u, 0x22u, 0x20u, 0x00u, 0x52u, 0x00u, @@ -715,7 +715,7 @@ const uint8_t cy_m0p_image[] = { 0x20u, 0x22u, 0x00u, 0x21u, 0x00u, 0xf0u, 0xb0u, 0xfeu, 0x00u, 0x22u, 0x20u, 0x00u, 0x11u, 0x00u, 0x01u, 0x23u, 0xffu, 0xf7u, 0x5du, 0xf8u, 0x20u, 0x00u, 0x03u, 0x23u, 0x00u, 0x22u, 0x01u, 0x21u, 0xffu, 0xf7u, 0xeeu, 0xf8u, 0x01u, 0x23u, 0x00u, 0x22u, 0x04u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x3eu, 0xf8u, 0x7fu, 0xe7u, 0x1cu, 0x22u, - 0xb3u, 0x49u, 0x01u, 0xa8u, 0x04u, 0xf0u, 0x04u, 0xfbu, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa5u, 0xf8u, 0x01u, 0x22u, + 0xb3u, 0x49u, 0x01u, 0xa8u, 0x04u, 0xf0u, 0x08u, 0xfbu, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa5u, 0xf8u, 0x01u, 0x22u, 0x03u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa7u, 0xf8u, 0x00u, 0x22u, 0x04u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa2u, 0xf8u, 0xe0u, 0x22u, 0x05u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa6u, 0xf8u, 0xf0u, 0x22u, 0x00u, 0x21u, 0x52u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa0u, 0xf8u, 0x80u, 0x22u, 0x01u, 0x21u, 0x52u, 0x00u, 0x20u, 0x00u, @@ -746,7 +746,7 @@ const uint8_t cy_m0p_image[] = { 0x03u, 0x23u, 0x00u, 0x22u, 0x19u, 0x00u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0x69u, 0xffu, 0x3eu, 0x23u, 0x3du, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0x00u, 0xf0u, 0xb0u, 0xfdu, 0x00u, 0x21u, 0x3eu, 0x4bu, 0x37u, 0x22u, 0x20u, 0x00u, 0x00u, 0xf0u, 0xaau, 0xfdu, 0x23u, 0x21u, 0xffu, 0xf7u, 0x8fu, 0xf9u, 0x39u, 0x49u, 0x11u, 0x22u, 0x1cu, 0x31u, - 0x01u, 0xa8u, 0x04u, 0xf0u, 0x0du, 0xfau, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xaeu, 0xffu, 0x01u, 0x22u, 0x04u, 0x21u, + 0x01u, 0xa8u, 0x04u, 0xf0u, 0x11u, 0xfau, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xaeu, 0xffu, 0x01u, 0x22u, 0x04u, 0x21u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xb0u, 0xffu, 0x00u, 0x22u, 0x05u, 0x21u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xabu, 0xffu, 0x31u, 0x4au, 0x00u, 0x21u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xafu, 0xffu, 0xf0u, 0x22u, 0x01u, 0x21u, 0x52u, 0x00u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xa9u, 0xffu, 0x81u, 0x22u, 0x06u, 0x21u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xa4u, 0xffu, @@ -760,7 +760,7 @@ const uint8_t cy_m0p_image[] = { 0x4bu, 0xfdu, 0x04u, 0x23u, 0x00u, 0x22u, 0x19u, 0x00u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xf8u, 0xfeu, 0x4eu, 0x23u, 0x3du, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0x00u, 0xf0u, 0x3fu, 0xfdu, 0x00u, 0x21u, 0x07u, 0x4bu, 0x37u, 0x22u, 0x20u, 0x00u, 0x00u, 0xf0u, 0x39u, 0xfdu, 0x43u, 0x21u, 0xffu, 0xf7u, 0x1eu, 0xf9u, 0x12u, 0x10u, 0x00u, 0x00u, - 0x55u, 0x78u, 0x00u, 0x10u, 0x3eu, 0x30u, 0x30u, 0x00u, 0x01u, 0x02u, 0x00u, 0x00u, 0x4eu, 0x40u, 0x30u, 0x00u, + 0x5du, 0x78u, 0x00u, 0x10u, 0x3eu, 0x30u, 0x30u, 0x00u, 0x01u, 0x02u, 0x00u, 0x00u, 0x4eu, 0x40u, 0x30u, 0x00u, 0x70u, 0xb5u, 0x0cu, 0x00u, 0x05u, 0x00u, 0xfeu, 0xf7u, 0xdau, 0xfeu, 0x09u, 0x4bu, 0x26u, 0x01u, 0x33u, 0x43u, 0x28u, 0x00u, 0x3du, 0x22u, 0x00u, 0x21u, 0x00u, 0xf0u, 0x1fu, 0xfdu, 0x24u, 0x03u, 0x05u, 0x4bu, 0x34u, 0x43u, 0x28u, 0x00u, 0x23u, 0x43u, 0x37u, 0x22u, 0x00u, 0x21u, 0x00u, 0xf0u, 0x16u, 0xfdu, 0x70u, 0xbdu, 0xc0u, 0x46u, @@ -772,7 +772,7 @@ const uint8_t cy_m0p_image[] = { 0xebu, 0xfcu, 0x0bu, 0x4bu, 0x2du, 0x03u, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x07u, 0xd8u, 0x2bu, 0x00u, 0x26u, 0x22u, 0x3bu, 0x43u, 0x30u, 0x00u, 0x00u, 0x21u, 0x00u, 0xf0u, 0xddu, 0xfcu, 0xf8u, 0xbdu, 0x0fu, 0x23u, 0x2bu, 0x43u, 0x3bu, 0x43u, 0x25u, 0x22u, 0xf5u, 0xe7u, 0xc0u, 0x46u, 0x0eu, 0x00u, 0x80u, 0x00u, - 0xdcu, 0x05u, 0x00u, 0x08u, 0x07u, 0xb5u, 0x00u, 0x93u, 0x13u, 0x00u, 0xfeu, 0xf7u, 0xf5u, 0xffu, 0x07u, 0xbdu, + 0xecu, 0x05u, 0x00u, 0x08u, 0x07u, 0xb5u, 0x00u, 0x93u, 0x13u, 0x00u, 0xfeu, 0xf7u, 0xf5u, 0xffu, 0x07u, 0xbdu, 0xf8u, 0xb5u, 0x04u, 0x00u, 0x17u, 0x00u, 0x1eu, 0x00u, 0x0du, 0x00u, 0xfeu, 0xf7u, 0xd5u, 0xfeu, 0x3au, 0x00u, 0x07u, 0x21u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xd7u, 0xfeu, 0x32u, 0x00u, 0x08u, 0x21u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xd2u, 0xfeu, 0x2au, 0x00u, 0x0bu, 0x21u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xcdu, 0xfeu, 0x06u, 0x9au, 0x09u, 0x21u, @@ -867,16 +867,16 @@ const uint8_t cy_m0p_image[] = { 0x05u, 0x90u, 0x08u, 0x22u, 0x00u, 0x97u, 0x07u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xd0u, 0xfeu, 0x01u, 0x22u, 0x05u, 0x9bu, 0x13u, 0x42u, 0x0au, 0xd0u, 0x0bu, 0x23u, 0x01u, 0x93u, 0x01u, 0x3bu, 0x00u, 0x93u, 0x02u, 0x97u, 0x01u, 0x3bu, 0x07u, 0x32u, 0x07u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x0eu, 0xfeu, 0x01u, 0x35u, 0xcdu, 0xe7u, - 0xdcu, 0x05u, 0x00u, 0x08u, 0xc5u, 0x60u, 0x00u, 0x00u, 0xc6u, 0xc0u, 0x00u, 0x00u, 0xd0u, 0x03u, 0x00u, 0x08u, + 0xecu, 0x05u, 0x00u, 0x08u, 0xc5u, 0x60u, 0x00u, 0x00u, 0xc6u, 0xc0u, 0x00u, 0x00u, 0xe0u, 0x03u, 0x00u, 0x08u, 0x80u, 0x22u, 0x0du, 0x4bu, 0x52u, 0x00u, 0x90u, 0x42u, 0x11u, 0xd0u, 0x07u, 0xd8u, 0x01u, 0x22u, 0xc0u, 0x28u, 0x0eu, 0xd0u, 0x02u, 0x22u, 0xe0u, 0x28u, 0x0bu, 0xd0u, 0x00u, 0x22u, 0x09u, 0xe0u, 0xc0u, 0x22u, 0x52u, 0x00u, 0x90u, 0x42u, 0x07u, 0xd0u, 0x05u, 0x4au, 0x90u, 0x42u, 0xf6u, 0xd1u, 0x05u, 0x22u, 0x00u, 0xe0u, 0x03u, 0x22u, - 0x1au, 0x70u, 0x70u, 0x47u, 0x04u, 0x22u, 0xfbu, 0xe7u, 0xccu, 0x03u, 0x00u, 0x08u, 0x09u, 0x02u, 0x00u, 0x00u, + 0x1au, 0x70u, 0x70u, 0x47u, 0x04u, 0x22u, 0xfbu, 0xe7u, 0xdcu, 0x03u, 0x00u, 0x08u, 0x09u, 0x02u, 0x00u, 0x00u, 0x01u, 0x4bu, 0x18u, 0x70u, 0x70u, 0x47u, 0xc0u, 0x46u, 0x80u, 0x00u, 0x00u, 0x08u, 0x13u, 0xb5u, 0x04u, 0x00u, 0x05u, 0x98u, 0x00u, 0x90u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x2fu, 0xffu, 0x20u, 0x00u, 0xfeu, 0xf7u, 0x62u, 0xfbu, 0x13u, 0xbdu, 0x00u, 0x00u, 0xf0u, 0xb5u, 0x93u, 0xb0u, 0x05u, 0x93u, 0x1au, 0xabu, 0x1cu, 0x78u, 0x65u, 0x4bu, 0x05u, 0x00u, 0x1bu, 0x68u, 0x03u, 0x91u, 0x04u, 0x92u, 0x1eu, 0x1eu, 0x02u, 0xd0u, 0x9bu, 0x6bu, 0xc3u, 0x18u, - 0x1eu, 0x68u, 0x30u, 0x22u, 0x00u, 0x21u, 0x06u, 0xa8u, 0x03u, 0xf0u, 0x03u, 0xfeu, 0x33u, 0x00u, 0x81u, 0x33u, + 0x1eu, 0x68u, 0x30u, 0x22u, 0x00u, 0x21u, 0x06u, 0xa8u, 0x03u, 0xf0u, 0x07u, 0xfeu, 0x33u, 0x00u, 0x81u, 0x33u, 0x22u, 0x00u, 0xffu, 0x33u, 0x06u, 0xa9u, 0x28u, 0x00u, 0x01u, 0xf0u, 0xfcu, 0xfbu, 0x04u, 0x1eu, 0x00u, 0xd0u, 0x86u, 0xe0u, 0x33u, 0x00u, 0x80u, 0x33u, 0x01u, 0x93u, 0x98u, 0x23u, 0x01u, 0x9au, 0xdbu, 0x00u, 0x77u, 0x1cu, 0xf6u, 0x50u, 0xffu, 0x37u, 0xf3u, 0x18u, 0x5au, 0x60u, 0x9fu, 0x60u, 0x19u, 0x9au, 0x09u, 0x9bu, 0x9au, 0x42u, @@ -900,10 +900,10 @@ const uint8_t cy_m0p_image[] = { 0x28u, 0x00u, 0x00u, 0xf0u, 0xa7u, 0xfbu, 0x02u, 0x9au, 0x09u, 0x9bu, 0x9bu, 0x1au, 0x19u, 0x9au, 0x9bu, 0xb2u, 0xb9u, 0x18u, 0x89u, 0xe7u, 0x02u, 0x9bu, 0x18u, 0x9au, 0x39u, 0x00u, 0x28u, 0x00u, 0x00u, 0xf0u, 0x9au, 0xfbu, 0x86u, 0xe7u, 0xfau, 0x5cu, 0x01u, 0x9cu, 0x4au, 0x40u, 0xf2u, 0x54u, 0xfau, 0x5cu, 0x42u, 0x40u, 0xe2u, 0x54u, - 0x01u, 0x33u, 0x80u, 0xe7u, 0xd0u, 0x03u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x66u, 0x4cu, 0x05u, 0x00u, 0xa5u, 0x44u, + 0x01u, 0x33u, 0x80u, 0xe7u, 0xe0u, 0x03u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x66u, 0x4cu, 0x05u, 0x00u, 0xa5u, 0x44u, 0x04u, 0x92u, 0x93u, 0x22u, 0x05u, 0x93u, 0x13u, 0xaeu, 0xaeu, 0xabu, 0x1cu, 0x78u, 0x03u, 0x91u, 0x92u, 0x00u, - 0x00u, 0x21u, 0x30u, 0x00u, 0x03u, 0xf0u, 0x35u, 0xfdu, 0x30u, 0x22u, 0x00u, 0x21u, 0x07u, 0xa8u, 0x03u, 0xf0u, - 0x30u, 0xfdu, 0x22u, 0x00u, 0x73u, 0xabu, 0x07u, 0xa9u, 0x28u, 0x00u, 0x01u, 0xf0u, 0x77u, 0xfdu, 0x04u, 0x1eu, + 0x00u, 0x21u, 0x30u, 0x00u, 0x03u, 0xf0u, 0x39u, 0xfdu, 0x30u, 0x22u, 0x00u, 0x21u, 0x07u, 0xa8u, 0x03u, 0xf0u, + 0x34u, 0xfdu, 0x22u, 0x00u, 0x73u, 0xabu, 0x07u, 0xa9u, 0x28u, 0x00u, 0x01u, 0xf0u, 0x77u, 0xfdu, 0x04u, 0x1eu, 0x3bu, 0xd1u, 0x90u, 0x23u, 0x9bu, 0x00u, 0xf6u, 0x50u, 0x33u, 0xaau, 0x04u, 0x33u, 0xf2u, 0x50u, 0x0au, 0x9fu, 0x04u, 0x33u, 0x53u, 0xaau, 0xf2u, 0x50u, 0x10u, 0x9bu, 0xbeu, 0xb2u, 0x01u, 0x93u, 0x02u, 0x00u, 0x33u, 0x00u, 0x53u, 0xa9u, 0x28u, 0x00u, 0x00u, 0xf0u, 0x6eu, 0xfcu, 0xadu, 0x9bu, 0xbbu, 0x42u, 0x2eu, 0xd9u, 0x07u, 0xa9u, @@ -933,10 +933,10 @@ const uint8_t cy_m0p_image[] = { 0x13u, 0x43u, 0x33u, 0x60u, 0x00u, 0x2du, 0x01u, 0xd1u, 0x00u, 0x29u, 0x12u, 0xd0u, 0x80u, 0x22u, 0xa3u, 0x68u, 0x52u, 0x02u, 0xc3u, 0x18u, 0x19u, 0x68u, 0x11u, 0x42u, 0xfcu, 0xd0u, 0x23u, 0x68u, 0xc0u, 0x18u, 0x08u, 0x4bu, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x04u, 0xd8u, 0x80u, 0x23u, 0x02u, 0x68u, 0x1au, 0x42u, - 0xfcu, 0xd1u, 0xf7u, 0xbdu, 0x03u, 0x68u, 0x00u, 0x2bu, 0xfcu, 0xd1u, 0xfau, 0xe7u, 0xd0u, 0x03u, 0x00u, 0x08u, - 0xdcu, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x1fu, 0x24u, 0x08u, 0x4bu, 0x89u, 0x06u, 0x1bu, 0x68u, 0x29u, 0x33u, + 0xfcu, 0xd1u, 0xf7u, 0xbdu, 0x03u, 0x68u, 0x00u, 0x2bu, 0xfcu, 0xd1u, 0xfau, 0xe7u, 0xe0u, 0x03u, 0x00u, 0x08u, + 0xecu, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x1fu, 0x24u, 0x08u, 0x4bu, 0x89u, 0x06u, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x9cu, 0x42u, 0xa4u, 0x41u, 0x13u, 0x00u, 0x64u, 0x42u, 0x0cu, 0x34u, 0xa3u, 0x40u, 0x80u, 0x22u, - 0x0bu, 0x43u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xb0u, 0xffu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, + 0x0bu, 0x43u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xb0u, 0xffu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0xecu, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, 0x00u, 0x22u, 0x0eu, 0x21u, 0xffu, 0xf7u, 0xe4u, 0xffu, 0x20u, 0x00u, 0x00u, 0x22u, 0x0du, 0x21u, 0xffu, 0xf7u, 0xdfu, 0xffu, 0x20u, 0x00u, 0x00u, 0x22u, 0x0cu, 0x21u, 0xffu, 0xf7u, 0xdau, 0xffu, 0x20u, 0x00u, 0x00u, 0x22u, 0x0bu, 0x21u, 0xffu, 0xf7u, 0xd5u, 0xffu, 0x20u, 0x00u, 0x00u, 0x22u, 0x0au, 0x21u, @@ -947,10 +947,10 @@ const uint8_t cy_m0p_image[] = { 0x20u, 0x00u, 0x00u, 0x22u, 0x03u, 0x21u, 0xffu, 0xf7u, 0xadu, 0xffu, 0x20u, 0x00u, 0x00u, 0x22u, 0x02u, 0x21u, 0xffu, 0xf7u, 0xa8u, 0xffu, 0x20u, 0x00u, 0x00u, 0x22u, 0x01u, 0x21u, 0xffu, 0xf7u, 0xa3u, 0xffu, 0x00u, 0x22u, 0x20u, 0x00u, 0x11u, 0x00u, 0xffu, 0xf7u, 0x9eu, 0xffu, 0x03u, 0x4bu, 0x0fu, 0x21u, 0x1au, 0x68u, 0x20u, 0x00u, - 0x92u, 0x08u, 0xffu, 0xf7u, 0x97u, 0xffu, 0x10u, 0xbdu, 0xd4u, 0x03u, 0x00u, 0x08u, 0x05u, 0x4bu, 0x1bu, 0x68u, + 0x92u, 0x08u, 0xffu, 0xf7u, 0x97u, 0xffu, 0x10u, 0xbdu, 0xe4u, 0x03u, 0x00u, 0x08u, 0x05u, 0x4bu, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1au, 0x78u, 0x04u, 0x4bu, 0x1fu, 0x2au, 0x00u, 0xd9u, 0x04u, 0x4bu, 0x04u, 0x4au, 0x13u, 0x60u, - 0x70u, 0x47u, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x84u, 0x78u, 0x00u, 0x10u, 0xd8u, 0x78u, 0x00u, 0x10u, - 0xd0u, 0x03u, 0x00u, 0x08u, 0x2fu, 0x4bu, 0x70u, 0xb5u, 0x14u, 0x00u, 0x1au, 0x68u, 0x00u, 0x2au, 0x2cu, 0xd0u, + 0x70u, 0x47u, 0xc0u, 0x46u, 0xecu, 0x05u, 0x00u, 0x08u, 0x8cu, 0x78u, 0x00u, 0x10u, 0xe0u, 0x78u, 0x00u, 0x10u, + 0xe0u, 0x03u, 0x00u, 0x08u, 0x2fu, 0x4bu, 0x70u, 0xb5u, 0x14u, 0x00u, 0x1au, 0x68u, 0x00u, 0x2au, 0x2cu, 0xd0u, 0x00u, 0x29u, 0x09u, 0xd1u, 0x00u, 0x2cu, 0x28u, 0xd1u, 0x13u, 0x6du, 0xc1u, 0x18u, 0x2au, 0x4bu, 0x1bu, 0x68u, 0x9cu, 0x6cu, 0x00u, 0x29u, 0x21u, 0xd0u, 0xa4u, 0x00u, 0x28u, 0x4bu, 0x65u, 0x1eu, 0x9du, 0x42u, 0x1cu, 0xd8u, 0x80u, 0x23u, 0x1bu, 0x01u, 0x9cu, 0x42u, 0x3eu, 0xd0u, 0x0du, 0xd8u, 0x80u, 0x23u, 0x9bu, 0x00u, 0x9cu, 0x42u, @@ -962,8 +962,8 @@ const uint8_t cy_m0p_image[] = { 0xebu, 0xd1u, 0x1fu, 0x2eu, 0x02u, 0xd9u, 0x10u, 0x4du, 0x1bu, 0x02u, 0x43u, 0x51u, 0x93u, 0x6bu, 0xa2u, 0x08u, 0xc3u, 0x18u, 0x19u, 0x60u, 0x0fu, 0x21u, 0xffu, 0xf7u, 0x2du, 0xffu, 0x00u, 0x20u, 0x0bu, 0x4bu, 0x1cu, 0x60u, 0x70u, 0xbdu, 0x7cu, 0x23u, 0xe4u, 0xe7u, 0x78u, 0x23u, 0xe2u, 0xe7u, 0x60u, 0x23u, 0xe0u, 0xe7u, 0x40u, 0x23u, - 0xdeu, 0xe7u, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, 0xdcu, 0x05u, 0x00u, 0x08u, 0xffu, 0x7fu, 0x00u, 0x00u, - 0x0bu, 0x00u, 0x32u, 0x00u, 0xffu, 0x3fu, 0x00u, 0x00u, 0x88u, 0x14u, 0x00u, 0x00u, 0xd4u, 0x03u, 0x00u, 0x08u, + 0xdeu, 0xe7u, 0xc0u, 0x46u, 0xe0u, 0x03u, 0x00u, 0x08u, 0xecu, 0x05u, 0x00u, 0x08u, 0xffu, 0x7fu, 0x00u, 0x00u, + 0x0bu, 0x00u, 0x32u, 0x00u, 0xffu, 0x3fu, 0x00u, 0x00u, 0x88u, 0x14u, 0x00u, 0x00u, 0xe4u, 0x03u, 0x00u, 0x08u, 0x20u, 0x4bu, 0x21u, 0x49u, 0x1bu, 0x68u, 0x09u, 0x68u, 0x9au, 0x6cu, 0x92u, 0x00u, 0x00u, 0x29u, 0x1cu, 0xd0u, 0x1eu, 0x49u, 0x09u, 0x68u, 0x00u, 0x29u, 0x18u, 0xd0u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x2fu, 0xd9u, 0x1bu, 0x4bu, 0xc3u, 0x58u, 0x5bu, 0x04u, 0x5bu, 0x0eu, 0x70u, 0x2bu, 0x1du, 0xd0u, 0x08u, 0xd8u, 0x40u, 0x2bu, @@ -972,89 +972,89 @@ const uint8_t cy_m0p_image[] = { 0x13u, 0xd0u, 0x7fu, 0x2bu, 0xf9u, 0xd1u, 0x80u, 0x22u, 0x52u, 0x00u, 0xf6u, 0xe7u, 0x80u, 0x22u, 0xd2u, 0x01u, 0xf3u, 0xe7u, 0x80u, 0x22u, 0x92u, 0x01u, 0xf0u, 0xe7u, 0x80u, 0x22u, 0x52u, 0x01u, 0xedu, 0xe7u, 0x80u, 0x22u, 0x12u, 0x01u, 0xeau, 0xe7u, 0x80u, 0x22u, 0xd2u, 0x00u, 0xe7u, 0xe7u, 0x80u, 0x22u, 0x92u, 0x00u, 0xe4u, 0xe7u, - 0x0au, 0x00u, 0xe2u, 0xe7u, 0xdcu, 0x05u, 0x00u, 0x08u, 0xd0u, 0x03u, 0x00u, 0x08u, 0xd4u, 0x03u, 0x00u, 0x08u, + 0x0au, 0x00u, 0xe2u, 0xe7u, 0xecu, 0x05u, 0x00u, 0x08u, 0xe0u, 0x03u, 0x00u, 0x08u, 0xe4u, 0x03u, 0x00u, 0x08u, 0x88u, 0x14u, 0x00u, 0x00u, 0x10u, 0xb5u, 0x04u, 0x00u, 0xffu, 0xf7u, 0x30u, 0xffu, 0x17u, 0x4au, 0x18u, 0x49u, 0x13u, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x17u, 0xd8u, 0x16u, 0x4bu, 0x23u, 0x60u, 0x01u, 0x20u, 0x09u, 0x68u, 0x4bu, 0x6bu, 0xe3u, 0x18u, 0x18u, 0x60u, 0x13u, 0x4bu, 0x1bu, 0x68u, 0x00u, 0x2bu, 0x07u, 0xd1u, 0x13u, 0x68u, 0x09u, 0x6du, 0x9au, 0x6cu, 0x61u, 0x18u, 0x92u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x2au, 0xffu, 0x20u, 0x00u, 0xffu, 0xf7u, 0xbdu, 0xfeu, 0x00u, 0x20u, 0x10u, 0xbdu, 0x23u, 0x68u, 0x0bu, 0x48u, 0x03u, 0x40u, 0x23u, 0x60u, 0x0bu, 0x68u, 0x0au, 0x48u, 0x5bu, 0x68u, 0xe3u, 0x18u, 0x18u, 0x60u, 0x80u, 0x23u, 0x20u, 0x68u, - 0x1bu, 0x06u, 0x03u, 0x43u, 0x23u, 0x60u, 0x03u, 0x23u, 0xa3u, 0x60u, 0xd8u, 0xe7u, 0xdcu, 0x05u, 0x00u, 0x08u, - 0xd0u, 0x03u, 0x00u, 0x08u, 0x03u, 0x00u, 0x00u, 0x80u, 0xd4u, 0x03u, 0x00u, 0x08u, 0xffu, 0xffu, 0xfeu, 0x7fu, + 0x1bu, 0x06u, 0x03u, 0x43u, 0x23u, 0x60u, 0x03u, 0x23u, 0xa3u, 0x60u, 0xd8u, 0xe7u, 0xecu, 0x05u, 0x00u, 0x08u, + 0xe0u, 0x03u, 0x00u, 0x08u, 0x03u, 0x00u, 0x00u, 0x80u, 0xe4u, 0x03u, 0x00u, 0x08u, 0xffu, 0xffu, 0xfeu, 0x7fu, 0x01u, 0x00u, 0x02u, 0x00u, 0x03u, 0x23u, 0x03u, 0x70u, 0x00u, 0x20u, 0x70u, 0x47u, 0x06u, 0x4bu, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1au, 0x78u, 0x00u, 0x23u, 0x03u, 0x60u, 0x1fu, 0x2au, 0x03u, 0xd8u, 0x00u, 0x20u, 0x03u, 0x4bu, - 0x18u, 0x60u, 0x70u, 0x47u, 0x83u, 0x60u, 0xf9u, 0xe7u, 0xdcu, 0x05u, 0x00u, 0x08u, 0xd4u, 0x03u, 0x00u, 0x08u, + 0x18u, 0x60u, 0x70u, 0x47u, 0x83u, 0x60u, 0xf9u, 0xe7u, 0xecu, 0x05u, 0x00u, 0x08u, 0xe4u, 0x03u, 0x00u, 0x08u, 0x30u, 0xb5u, 0x01u, 0x29u, 0x0bu, 0xd9u, 0x01u, 0x22u, 0x0au, 0x40u, 0x54u, 0x42u, 0x62u, 0x41u, 0xcbu, 0x0fu, 0x5bu, 0x18u, 0x5bu, 0x10u, 0x9bu, 0x1au, 0x02u, 0x00u, 0x01u, 0x39u, 0x8bu, 0x42u, 0x00u, 0xdbu, 0x30u, 0xbdu, 0x14u, 0x78u, 0x45u, 0x5cu, 0x15u, 0x70u, 0x44u, 0x54u, 0x01u, 0x32u, 0x01u, 0x39u, 0xf5u, 0xe7u, 0x00u, 0x00u, 0x03u, 0x4bu, 0x1bu, 0x68u, 0x9bu, 0x68u, 0xc0u, 0x18u, 0x0fu, 0x23u, 0x00u, 0x68u, 0x18u, 0x40u, 0x70u, 0x47u, - 0xd0u, 0x03u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x04u, 0x00u, 0x0du, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xf0u, 0xffu, + 0xe0u, 0x03u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x04u, 0x00u, 0x0du, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xf0u, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x80u, 0x21u, 0x05u, 0x4bu, 0xc9u, 0x05u, 0x1au, 0x68u, 0xd3u, 0x68u, 0xe3u, 0x18u, - 0x19u, 0x60u, 0xd3u, 0x68u, 0xe4u, 0x18u, 0x25u, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, + 0x19u, 0x60u, 0xd3u, 0x68u, 0xe4u, 0x18u, 0x25u, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u, 0xe0u, 0x03u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x04u, 0x00u, 0x0eu, 0x00u, 0x15u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xd9u, 0xffu, 0x05u, 0x28u, 0xfau, 0xd8u, 0x06u, 0x4bu, 0x06u, 0x49u, 0x1bu, 0x68u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x11u, 0x60u, 0xdau, 0x68u, - 0xa2u, 0x18u, 0x16u, 0x60u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0x25u, 0x60u, 0x70u, 0xbdu, 0xd0u, 0x03u, 0x00u, 0x08u, + 0xa2u, 0x18u, 0x16u, 0x60u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0x25u, 0x60u, 0x70u, 0xbdu, 0xe0u, 0x03u, 0x00u, 0x08u, 0x10u, 0x00u, 0x00u, 0x41u, 0xf8u, 0xb5u, 0x04u, 0x00u, 0x0fu, 0x00u, 0x16u, 0x00u, 0x1du, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xbeu, 0xffu, 0x04u, 0x28u, 0xfau, 0xd8u, 0x07u, 0x4bu, 0x08u, 0x49u, 0x1bu, 0x68u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x11u, 0x60u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x17u, 0x60u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x16u, 0x60u, - 0xdbu, 0x68u, 0xe4u, 0x18u, 0x25u, 0x60u, 0xf8u, 0xbdu, 0xd0u, 0x03u, 0x00u, 0x08u, 0x10u, 0x02u, 0x00u, 0x42u, + 0xdbu, 0x68u, 0xe4u, 0x18u, 0x25u, 0x60u, 0xf8u, 0xbdu, 0xe0u, 0x03u, 0x00u, 0x08u, 0x10u, 0x02u, 0x00u, 0x42u, 0xf8u, 0xb5u, 0x04u, 0x00u, 0x0fu, 0x00u, 0x16u, 0x00u, 0x1du, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa0u, 0xffu, 0x03u, 0x28u, 0xfau, 0xd8u, 0x09u, 0x4bu, 0x0au, 0x49u, 0x1bu, 0x68u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x11u, 0x60u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x17u, 0x60u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x16u, 0x60u, 0xdau, 0x68u, 0xa2u, 0x18u, - 0x15u, 0x60u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0x06u, 0x9bu, 0x23u, 0x60u, 0xf8u, 0xbdu, 0xd0u, 0x03u, 0x00u, 0x08u, + 0x15u, 0x60u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0x06u, 0x9bu, 0x23u, 0x60u, 0xf8u, 0xbdu, 0xe0u, 0x03u, 0x00u, 0x08u, 0x10u, 0x32u, 0x00u, 0x43u, 0x70u, 0xb5u, 0x04u, 0x00u, 0x0du, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x80u, 0xffu, 0x07u, 0x28u, 0xfau, 0xd8u, 0x03u, 0x4bu, 0x2du, 0x06u, 0x1bu, 0x68u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0x25u, 0x60u, - 0x70u, 0xbdu, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x05u, 0x00u, 0x0cu, 0x00u, 0x1eu, 0x00u, + 0x70u, 0xbdu, 0xc0u, 0x46u, 0xe0u, 0x03u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x05u, 0x00u, 0x0cu, 0x00u, 0x1eu, 0x00u, 0x28u, 0x00u, 0xffu, 0xf7u, 0x6du, 0xffu, 0x07u, 0x28u, 0xfau, 0xd8u, 0x05u, 0x4bu, 0x24u, 0x06u, 0x1bu, 0x68u, 0xdbu, 0x68u, 0xedu, 0x18u, 0x01u, 0x23u, 0xb3u, 0x40u, 0x1cu, 0x43u, 0x2cu, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u, - 0xd0u, 0x03u, 0x00u, 0x08u, 0xf8u, 0xb5u, 0x07u, 0x00u, 0x0cu, 0x00u, 0x1du, 0x00u, 0x06u, 0xabu, 0x1eu, 0x78u, + 0xe0u, 0x03u, 0x00u, 0x08u, 0xf8u, 0xb5u, 0x07u, 0x00u, 0x0cu, 0x00u, 0x1du, 0x00u, 0x06u, 0xabu, 0x1eu, 0x78u, 0x38u, 0x00u, 0xffu, 0xf7u, 0x55u, 0xffu, 0x07u, 0x28u, 0xfau, 0xd8u, 0x06u, 0x4bu, 0x02u, 0x21u, 0x1bu, 0x68u, 0xb1u, 0x40u, 0xd8u, 0x68u, 0x01u, 0x23u, 0xabu, 0x40u, 0x24u, 0x06u, 0x19u, 0x43u, 0x38u, 0x18u, 0x21u, 0x43u, - 0x01u, 0x60u, 0xf8u, 0xbdu, 0xd0u, 0x03u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x06u, 0x00u, 0x0cu, 0x00u, 0x1du, 0x00u, + 0x01u, 0x60u, 0xf8u, 0xbdu, 0xe0u, 0x03u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x06u, 0x00u, 0x0cu, 0x00u, 0x1du, 0x00u, 0x30u, 0x00u, 0xffu, 0xf7u, 0x3du, 0xffu, 0x07u, 0x28u, 0xfau, 0xd8u, 0x02u, 0x21u, 0x08u, 0x4bu, 0x05u, 0x9au, 0x1bu, 0x68u, 0x24u, 0x06u, 0xd8u, 0x68u, 0x04u, 0x9bu, 0x30u, 0x18u, 0x99u, 0x40u, 0x01u, 0x23u, 0xabu, 0x40u, 0x19u, 0x43u, 0x03u, 0x23u, 0x93u, 0x40u, 0x19u, 0x43u, 0x21u, 0x43u, 0x01u, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u, - 0xd0u, 0x03u, 0x00u, 0x08u, 0x13u, 0xb5u, 0x04u, 0x00u, 0x08u, 0x00u, 0x11u, 0x00u, 0x00u, 0x2bu, 0x13u, 0xd0u, + 0xe0u, 0x03u, 0x00u, 0x08u, 0x13u, 0xb5u, 0x04u, 0x00u, 0x08u, 0x00u, 0x11u, 0x00u, 0x00u, 0x2bu, 0x13u, 0xd0u, 0x02u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x56u, 0xffu, 0x08u, 0x23u, 0x20u, 0x00u, 0x00u, 0x93u, 0x00u, 0x22u, 0x04u, 0x3bu, 0x50u, 0x21u, 0xffu, 0xf7u, 0xb6u, 0xffu, 0x04u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xe4u, 0x18u, - 0x10u, 0x23u, 0x22u, 0x68u, 0x1au, 0x42u, 0xfcu, 0xd1u, 0x13u, 0xbdu, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, + 0x10u, 0x23u, 0x22u, 0x68u, 0x1au, 0x42u, 0xfcu, 0xd1u, 0x13u, 0xbdu, 0xc0u, 0x46u, 0xe0u, 0x03u, 0x00u, 0x08u, 0x13u, 0xb5u, 0x04u, 0x00u, 0x10u, 0x00u, 0x1au, 0x1eu, 0x13u, 0xd0u, 0x03u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x39u, 0xffu, 0x0cu, 0x23u, 0x20u, 0x00u, 0x00u, 0x93u, 0x00u, 0x22u, 0x04u, 0x3bu, 0x51u, 0x21u, 0xffu, 0xf7u, 0x99u, 0xffu, 0x04u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xe4u, 0x18u, 0x10u, 0x23u, 0x22u, 0x68u, 0x1au, 0x42u, - 0xfcu, 0xd1u, 0x13u, 0xbdu, 0xd0u, 0x03u, 0x00u, 0x08u, 0x13u, 0xb5u, 0x04u, 0x00u, 0x01u, 0x20u, 0x00u, 0x2bu, + 0xfcu, 0xd1u, 0x13u, 0xbdu, 0xe0u, 0x03u, 0x00u, 0x08u, 0x13u, 0xb5u, 0x04u, 0x00u, 0x01u, 0x20u, 0x00u, 0x2bu, 0x15u, 0xd0u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x1eu, 0xffu, 0x08u, 0x23u, 0x00u, 0x22u, 0x00u, 0x93u, 0x52u, 0x21u, 0x04u, 0x3bu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x7eu, 0xffu, 0x10u, 0x22u, 0x05u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xe3u, 0x18u, 0x19u, 0x68u, 0x11u, 0x42u, 0xfcu, 0xd1u, 0xc0u, 0x23u, 0x5bu, 0x00u, 0xe0u, 0x58u, 0x16u, 0xbdu, - 0xd0u, 0x03u, 0x00u, 0x08u, 0x13u, 0xb5u, 0x04u, 0x00u, 0x08u, 0x00u, 0x11u, 0x00u, 0x1au, 0x00u, 0x04u, 0xabu, + 0xe0u, 0x03u, 0x00u, 0x08u, 0x13u, 0xb5u, 0x04u, 0x00u, 0x08u, 0x00u, 0x11u, 0x00u, 0x1au, 0x00u, 0x04u, 0xabu, 0x1bu, 0x88u, 0x00u, 0x2bu, 0x15u, 0xd0u, 0x00u, 0x90u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x19u, 0xffu, 0x0cu, 0x23u, 0x01u, 0x93u, 0x04u, 0x3bu, 0x00u, 0x93u, 0x20u, 0x00u, 0x04u, 0x3bu, 0x00u, 0x22u, 0x53u, 0x21u, 0xffu, 0xf7u, 0x73u, 0xffu, 0x04u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xe4u, 0x18u, 0x10u, 0x23u, 0x22u, 0x68u, 0x1au, 0x42u, - 0xfcu, 0xd1u, 0x13u, 0xbdu, 0xd0u, 0x03u, 0x00u, 0x08u, 0x03u, 0x4bu, 0x1bu, 0x68u, 0x9bu, 0x68u, 0xc0u, 0x18u, - 0x0fu, 0x23u, 0x00u, 0x68u, 0x18u, 0x40u, 0x70u, 0x47u, 0xd0u, 0x03u, 0x00u, 0x08u, 0x03u, 0x4bu, 0x1bu, 0x68u, - 0x1bu, 0x68u, 0xc0u, 0x18u, 0x03u, 0x68u, 0x00u, 0x2bu, 0xfcu, 0xd1u, 0x70u, 0x47u, 0xd0u, 0x03u, 0x00u, 0x08u, + 0xfcu, 0xd1u, 0x13u, 0xbdu, 0xe0u, 0x03u, 0x00u, 0x08u, 0x03u, 0x4bu, 0x1bu, 0x68u, 0x9bu, 0x68u, 0xc0u, 0x18u, + 0x0fu, 0x23u, 0x00u, 0x68u, 0x18u, 0x40u, 0x70u, 0x47u, 0xe0u, 0x03u, 0x00u, 0x08u, 0x03u, 0x4bu, 0x1bu, 0x68u, + 0x1bu, 0x68u, 0xc0u, 0x18u, 0x03u, 0x68u, 0x00u, 0x2bu, 0xfcu, 0xd1u, 0x70u, 0x47u, 0xe0u, 0x03u, 0x00u, 0x08u, 0xf8u, 0xb5u, 0x04u, 0x00u, 0x0du, 0x00u, 0x17u, 0x00u, 0x1eu, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xe4u, 0xffu, 0x04u, 0x28u, 0xfau, 0xd8u, 0x08u, 0x2du, 0x04u, 0xd0u, 0x0cu, 0x4au, 0xa3u, 0x58u, 0x00u, 0x2bu, 0xfcu, 0xdbu, 0x04u, 0xe0u, 0x86u, 0x22u, 0x52u, 0x01u, 0xa3u, 0x58u, 0x00u, 0x2bu, 0xfcu, 0xdbu, 0xe2u, 0x21u, 0x08u, 0x4bu, 0xc9u, 0x05u, 0x1bu, 0x68u, 0x0du, 0x43u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x15u, 0x60u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x17u, 0x60u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0x26u, 0x60u, 0xf8u, 0xbdu, 0xc0u, 0x46u, 0xd0u, 0x10u, 0x00u, 0x00u, - 0xd0u, 0x03u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x04u, 0x00u, 0x0eu, 0x00u, 0x15u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, + 0xe0u, 0x03u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x04u, 0x00u, 0x0eu, 0x00u, 0x15u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xbbu, 0xffu, 0x04u, 0x28u, 0xfau, 0xd8u, 0x06u, 0x4bu, 0x06u, 0x49u, 0x1bu, 0x68u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x11u, 0x60u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x16u, 0x60u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0x25u, 0x60u, 0x70u, 0xbdu, - 0xd0u, 0x03u, 0x00u, 0x08u, 0x0cu, 0x00u, 0x00u, 0x70u, 0x70u, 0xb5u, 0x05u, 0x00u, 0x0cu, 0x00u, 0x1eu, 0x1eu, + 0xe0u, 0x03u, 0x00u, 0x08u, 0x0cu, 0x00u, 0x00u, 0x70u, 0x70u, 0xb5u, 0x05u, 0x00u, 0x0cu, 0x00u, 0x1eu, 0x1eu, 0x22u, 0xd0u, 0x08u, 0x21u, 0xffu, 0xf7u, 0xb4u, 0xffu, 0x21u, 0x00u, 0x32u, 0x00u, 0x28u, 0x00u, 0xffu, 0xf7u, 0xd9u, 0xffu, 0x34u, 0x00u, 0x0fu, 0x2cu, 0x18u, 0xd8u, 0x10u, 0x24u, 0x33u, 0x09u, 0x64u, 0x42u, 0x5cu, 0x43u, 0xa4u, 0x19u, 0xa4u, 0xb2u, 0x00u, 0x2cu, 0x0cu, 0xd0u, 0x28u, 0x00u, 0xffu, 0xf7u, 0x8du, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x0du, 0x4bu, 0x0du, 0x4au, 0x1bu, 0x68u, 0x24u, 0x04u, 0xdbu, 0x68u, 0x14u, 0x43u, 0xebu, 0x18u, 0x1cu, 0x60u, 0x28u, 0x00u, 0xffu, 0xf7u, 0x8au, 0xffu, 0x70u, 0xbdu, 0x28u, 0x00u, 0xffu, 0xf7u, 0x7cu, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x04u, 0x4bu, 0x06u, 0x4au, 0x1bu, 0x68u, 0x10u, 0x3cu, 0xdbu, 0x68u, 0xa4u, 0xb2u, - 0xebu, 0x18u, 0x1au, 0x60u, 0xd6u, 0xe7u, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, 0x08u, 0xc0u, 0x00u, 0x40u, + 0xebu, 0x18u, 0x1au, 0x60u, 0xd6u, 0xe7u, 0xc0u, 0x46u, 0xe0u, 0x03u, 0x00u, 0x08u, 0x08u, 0xc0u, 0x00u, 0x40u, 0x08u, 0xc0u, 0x10u, 0x40u, 0xf8u, 0xb5u, 0x05u, 0x00u, 0x16u, 0x00u, 0x1fu, 0x1eu, 0x1eu, 0xd0u, 0x1au, 0x00u, 0xffu, 0xf7u, 0xa0u, 0xffu, 0x3cu, 0x00u, 0x0fu, 0x2cu, 0x19u, 0xd8u, 0x10u, 0x24u, 0x3bu, 0x09u, 0x64u, 0x42u, 0x5cu, 0x43u, 0xe4u, 0x19u, 0xa4u, 0xb2u, 0x00u, 0x2cu, 0x0du, 0xd0u, 0x28u, 0x00u, 0xffu, 0xf7u, 0x54u, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x0du, 0x4bu, 0x0eu, 0x4au, 0x1bu, 0x68u, 0x32u, 0x43u, 0xdbu, 0x68u, 0x24u, 0x04u, 0xebu, 0x18u, 0x14u, 0x43u, 0x1cu, 0x60u, 0x28u, 0x00u, 0xffu, 0xf7u, 0x50u, 0xffu, 0xf8u, 0xbdu, 0x28u, 0x00u, 0xffu, 0xf7u, 0x42u, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x04u, 0x4bu, 0x06u, 0x4au, 0x1bu, 0x68u, 0x32u, 0x43u, - 0xdbu, 0x68u, 0x10u, 0x3cu, 0xebu, 0x18u, 0x1au, 0x60u, 0xa4u, 0xb2u, 0xd4u, 0xe7u, 0xd0u, 0x03u, 0x00u, 0x08u, + 0xdbu, 0x68u, 0x10u, 0x3cu, 0xebu, 0x18u, 0x1au, 0x60u, 0xa4u, 0xb2u, 0xd4u, 0xe7u, 0xe0u, 0x03u, 0x00u, 0x08u, 0x00u, 0xc0u, 0x00u, 0x42u, 0x00u, 0xc0u, 0x10u, 0x42u, 0x70u, 0xb5u, 0x05u, 0x00u, 0x14u, 0x00u, 0x1eu, 0x00u, 0x01u, 0x20u, 0x00u, 0x2bu, 0x2du, 0xd0u, 0x8cu, 0x23u, 0x00u, 0x22u, 0x5bu, 0x01u, 0xeau, 0x50u, 0x28u, 0x00u, 0x0au, 0x00u, 0x33u, 0x00u, 0x08u, 0x21u, 0xffu, 0xf7u, 0x33u, 0xffu, 0x22u, 0x00u, 0x33u, 0x00u, 0x09u, 0x21u, @@ -1064,7 +1064,7 @@ const uint8_t cy_m0p_image[] = { 0x14u, 0x43u, 0xebu, 0x18u, 0x1cu, 0x60u, 0x28u, 0x00u, 0xffu, 0xf7u, 0x08u, 0xffu, 0x8cu, 0x23u, 0x5bu, 0x01u, 0xe8u, 0x58u, 0x70u, 0xbdu, 0x28u, 0x00u, 0xffu, 0xf7u, 0xf7u, 0xfeu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x04u, 0x4bu, 0x05u, 0x4au, 0x1bu, 0x68u, 0x10u, 0x3cu, 0xdbu, 0x68u, 0xa4u, 0xb2u, 0xebu, 0x18u, 0x1au, 0x60u, 0xd3u, 0xe7u, - 0xd0u, 0x03u, 0x00u, 0x08u, 0x98u, 0x00u, 0x00u, 0x43u, 0x98u, 0x00u, 0x10u, 0x43u, 0xf8u, 0xb5u, 0x1fu, 0x00u, + 0xe0u, 0x03u, 0x00u, 0x08u, 0x98u, 0x00u, 0x00u, 0x43u, 0x98u, 0x00u, 0x10u, 0x43u, 0xf8u, 0xb5u, 0x1fu, 0x00u, 0x06u, 0xabu, 0x1eu, 0x88u, 0x05u, 0x00u, 0x0cu, 0x00u, 0x00u, 0x2eu, 0x29u, 0xd0u, 0x33u, 0x00u, 0x08u, 0x21u, 0xffu, 0xf7u, 0xeeu, 0xfeu, 0x33u, 0x00u, 0x3au, 0x00u, 0x09u, 0x21u, 0x28u, 0x00u, 0xffu, 0xf7u, 0xe8u, 0xfeu, 0x21u, 0x00u, 0x32u, 0x00u, 0x28u, 0x00u, 0xffu, 0xf7u, 0x0du, 0xffu, 0x34u, 0x00u, 0x0fu, 0x2cu, 0x18u, 0xd8u, @@ -1073,37 +1073,37 @@ const uint8_t cy_m0p_image[] = { 0x24u, 0x04u, 0xdbu, 0x68u, 0x14u, 0x43u, 0xebu, 0x18u, 0x1cu, 0x60u, 0x28u, 0x00u, 0xffu, 0xf7u, 0xbeu, 0xfeu, 0xf8u, 0xbdu, 0x28u, 0x00u, 0xffu, 0xf7u, 0xb0u, 0xfeu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x04u, 0x4bu, 0x06u, 0x4au, 0x1bu, 0x68u, 0x10u, 0x3cu, 0xdbu, 0x68u, 0xa4u, 0xb2u, 0xebu, 0x18u, 0x1au, 0x60u, 0xd6u, 0xe7u, 0xc0u, 0x46u, - 0xd0u, 0x03u, 0x00u, 0x08u, 0x98u, 0xc0u, 0x00u, 0x41u, 0x98u, 0xc0u, 0x10u, 0x41u, 0x10u, 0xb5u, 0x80u, 0x24u, + 0xe0u, 0x03u, 0x00u, 0x08u, 0x98u, 0xc0u, 0x00u, 0x41u, 0x98u, 0xc0u, 0x10u, 0x41u, 0x10u, 0xb5u, 0x80u, 0x24u, 0xa4u, 0x00u, 0x01u, 0x51u, 0x81u, 0x21u, 0x52u, 0x00u, 0x52u, 0x08u, 0x89u, 0x00u, 0x42u, 0x50u, 0x82u, 0x22u, 0xdbu, 0x00u, 0xdbu, 0x08u, 0x92u, 0x00u, 0x83u, 0x50u, 0x00u, 0x20u, 0x10u, 0xbdu, 0x70u, 0xb5u, 0x04u, 0x00u, 0x15u, 0x00u, 0xffu, 0xf7u, 0x3fu, 0xfdu, 0x00u, 0x22u, 0x5cu, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xaau, 0xfdu, 0x20u, 0x21u, 0x06u, 0x4bu, 0x1au, 0x68u, 0x13u, 0x68u, 0xe3u, 0x18u, 0x18u, 0x68u, 0x08u, 0x40u, 0xfcu, 0xd1u, - 0x93u, 0x69u, 0xe4u, 0x18u, 0x23u, 0x68u, 0x2bu, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, + 0x93u, 0x69u, 0xe4u, 0x18u, 0x23u, 0x68u, 0x2bu, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u, 0xe0u, 0x03u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x80u, 0x24u, 0xa4u, 0x00u, 0x01u, 0x51u, 0x81u, 0x21u, 0x52u, 0x00u, 0x52u, 0x08u, 0x89u, 0x00u, 0x42u, 0x50u, 0x82u, 0x22u, 0xdbu, 0x00u, 0xdbu, 0x08u, 0x92u, 0x00u, 0x83u, 0x50u, 0x00u, 0x20u, 0x10u, 0xbdu, 0x83u, 0x23u, 0x9bu, 0x00u, 0x10u, 0xb5u, 0xc1u, 0x50u, 0x01u, 0x21u, 0x04u, 0x33u, 0xc1u, 0x50u, 0x06u, 0x4bu, 0x19u, 0x68u, 0x0bu, 0x68u, 0xc3u, 0x18u, 0x1cu, 0x68u, 0x00u, 0x2cu, 0xfcu, 0xdbu, 0x8bu, 0x69u, 0xc0u, 0x18u, - 0x03u, 0x68u, 0x00u, 0x20u, 0x13u, 0x60u, 0x10u, 0xbdu, 0xd0u, 0x03u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x06u, 0x4cu, + 0x03u, 0x68u, 0x00u, 0x20u, 0x13u, 0x60u, 0x10u, 0xbdu, 0xe0u, 0x03u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x06u, 0x4cu, 0x24u, 0x68u, 0x29u, 0x34u, 0x24u, 0x78u, 0x1fu, 0x2cu, 0x02u, 0xd8u, 0xffu, 0xf7u, 0x05u, 0xfeu, 0x10u, 0xbdu, - 0xffu, 0xf7u, 0x12u, 0xffu, 0xfbu, 0xe7u, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x09u, 0x4bu, 0x1bu, 0x68u, + 0xffu, 0xf7u, 0x12u, 0xffu, 0xfbu, 0xe7u, 0xc0u, 0x46u, 0xecu, 0x05u, 0x00u, 0x08u, 0x09u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xc0u, 0x18u, 0x08u, 0x4bu, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x04u, 0xd8u, 0x80u, 0x23u, 0x02u, 0x68u, 0x1au, 0x42u, 0xfcu, 0xd1u, 0x70u, 0x47u, 0x03u, 0x68u, 0x00u, 0x2bu, 0xfcu, 0xd1u, - 0xfau, 0xe7u, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x13u, 0x00u, + 0xfau, 0xe7u, 0xc0u, 0x46u, 0xe0u, 0x03u, 0x00u, 0x08u, 0xecu, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x13u, 0x00u, 0x06u, 0x4au, 0x14u, 0x68u, 0x29u, 0x34u, 0x22u, 0x78u, 0x1fu, 0x2au, 0x03u, 0xd8u, 0x00u, 0x22u, 0xffu, 0xf7u, - 0xbfu, 0xfdu, 0x10u, 0xbdu, 0x00u, 0x22u, 0xffu, 0xf7u, 0xadu, 0xfeu, 0xfau, 0xe7u, 0xdcu, 0x05u, 0x00u, 0x08u, + 0xbfu, 0xfdu, 0x10u, 0xbdu, 0x00u, 0x22u, 0xffu, 0xf7u, 0xadu, 0xfeu, 0xfau, 0xe7u, 0xecu, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x0bu, 0x03u, 0x34u, 0x22u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xd6u, 0xfau, 0x10u, 0xbdu, 0x00u, 0x00u, 0x10u, 0xb5u, 0x0au, 0x4bu, 0x09u, 0x03u, 0x1bu, 0x68u, 0x12u, 0x01u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x06u, 0xd8u, 0x13u, 0x00u, 0x25u, 0x22u, 0x0bu, 0x43u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xc5u, 0xfau, 0x10u, 0xbdu, - 0x0fu, 0x23u, 0x13u, 0x43u, 0x0bu, 0x43u, 0x24u, 0x22u, 0xf6u, 0xe7u, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, + 0x0fu, 0x23u, 0x13u, 0x43u, 0x0bu, 0x43u, 0x24u, 0x22u, 0xf6u, 0xe7u, 0xc0u, 0x46u, 0xecu, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x09u, 0x4bu, 0x09u, 0x03u, 0x1bu, 0x68u, 0x12u, 0x01u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x06u, 0xd8u, 0x13u, 0x00u, 0x0bu, 0x43u, 0x21u, 0x22u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xadu, 0xfau, 0x10u, 0xbdu, - 0x0fu, 0x23u, 0x13u, 0x43u, 0xf6u, 0xe7u, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x0bu, 0x00u, + 0x0fu, 0x23u, 0x13u, 0x43u, 0xf6u, 0xe7u, 0xc0u, 0x46u, 0xecu, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x0bu, 0x00u, 0x13u, 0x22u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xa0u, 0xfau, 0x10u, 0xbdu, 0x00u, 0x00u, 0x10u, 0xb5u, 0x13u, 0x00u, 0x07u, 0x4au, 0x12u, 0x68u, 0x29u, 0x32u, 0x14u, 0x78u, 0x0cu, 0x22u, 0x1fu, 0x2cu, 0x00u, 0xd9u, 0x04u, 0x32u, 0x91u, 0x40u, 0x01u, 0x3bu, 0x0bu, 0x43u, 0x12u, 0x22u, 0x00u, 0x21u, 0xffu, 0xf7u, 0x8du, 0xfau, 0x10u, 0xbdu, - 0xdcu, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x1fu, 0x24u, 0x08u, 0x4bu, 0x89u, 0x06u, 0x1bu, 0x68u, 0x29u, 0x33u, + 0xecu, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x1fu, 0x24u, 0x08u, 0x4bu, 0x89u, 0x06u, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x9cu, 0x42u, 0xa4u, 0x41u, 0x13u, 0x00u, 0x64u, 0x42u, 0x0cu, 0x34u, 0xa3u, 0x40u, 0x80u, 0x22u, - 0x0bu, 0x43u, 0x00u, 0x21u, 0xffu, 0xf7u, 0x78u, 0xfau, 0x10u, 0xbdu, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, + 0x0bu, 0x43u, 0x00u, 0x21u, 0xffu, 0xf7u, 0x78u, 0xfau, 0x10u, 0xbdu, 0xc0u, 0x46u, 0xecu, 0x05u, 0x00u, 0x08u, 0xf7u, 0xb5u, 0x04u, 0x00u, 0x1du, 0x00u, 0x5eu, 0x1cu, 0x01u, 0x92u, 0x0fu, 0x00u, 0x32u, 0x00u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xccu, 0xffu, 0x32u, 0x00u, 0x01u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xc7u, 0xffu, 0x32u, 0x00u, 0x02u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xc2u, 0xffu, 0x2au, 0x00u, 0x03u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, @@ -1116,7 +1116,7 @@ const uint8_t cy_m0p_image[] = { 0xffu, 0xf7u, 0x2au, 0xfau, 0x0du, 0x4bu, 0x03u, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x24u, 0xfau, 0x33u, 0x00u, 0x3au, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x1eu, 0xfau, 0x00u, 0x22u, 0x20u, 0x00u, 0x11u, 0x00u, 0xffu, 0xf7u, 0x5du, 0xffu, 0x02u, 0x22u, 0x20u, 0x00u, 0x11u, 0x00u, 0xffu, 0xf7u, 0x40u, 0xffu, - 0x01u, 0x3du, 0xd9u, 0xe7u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x02u, 0x00u, 0x30u, 0x00u, 0x01u, 0x00u, 0x30u, 0x00u, + 0x01u, 0x3du, 0xd9u, 0xe7u, 0xecu, 0x05u, 0x00u, 0x08u, 0x02u, 0x00u, 0x30u, 0x00u, 0x01u, 0x00u, 0x30u, 0x00u, 0xf7u, 0xb5u, 0x04u, 0x00u, 0x08u, 0x9eu, 0x00u, 0x91u, 0x15u, 0x00u, 0x01u, 0x21u, 0x72u, 0x1cu, 0x77u, 0x00u, 0x01u, 0x93u, 0xffu, 0xf7u, 0x63u, 0xffu, 0x3au, 0x00u, 0x02u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x5eu, 0xffu, 0x3au, 0x00u, 0x03u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x59u, 0xffu, 0x32u, 0x00u, 0x00u, 0x21u, 0x20u, 0x00u, @@ -1138,7 +1138,7 @@ const uint8_t cy_m0p_image[] = { 0x7bu, 0xf9u, 0x20u, 0x00u, 0x10u, 0x4bu, 0x03u, 0x22u, 0x00u, 0x21u, 0xffu, 0xf7u, 0x75u, 0xf9u, 0x00u, 0x9bu, 0x20u, 0x00u, 0x1au, 0x03u, 0x02u, 0x23u, 0x00u, 0x21u, 0x13u, 0x43u, 0x30u, 0x22u, 0xffu, 0xf7u, 0x6cu, 0xf9u, 0x0eu, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xc2u, 0xfeu, 0xf7u, 0xbdu, 0xc0u, 0x46u, 0x3au, 0x10u, 0x00u, 0x00u, - 0x18u, 0x20u, 0x00u, 0x00u, 0x23u, 0x20u, 0x00u, 0x00u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x20u, 0x20u, 0x00u, 0x00u, + 0x18u, 0x20u, 0x00u, 0x00u, 0x23u, 0x20u, 0x00u, 0x00u, 0xecu, 0x05u, 0x00u, 0x08u, 0x20u, 0x20u, 0x00u, 0x00u, 0x10u, 0x10u, 0x00u, 0x00u, 0x21u, 0x30u, 0x00u, 0x00u, 0x23u, 0x00u, 0x30u, 0x00u, 0x28u, 0x30u, 0x00u, 0x00u, 0xf7u, 0xb5u, 0x06u, 0x00u, 0x1cu, 0x00u, 0x09u, 0x9bu, 0x01u, 0x91u, 0x5fu, 0x00u, 0x15u, 0x00u, 0x02u, 0x21u, 0x3au, 0x00u, 0xffu, 0xf7u, 0xabu, 0xfeu, 0x3au, 0x00u, 0x03u, 0x21u, 0x30u, 0x00u, 0xffu, 0xf7u, 0xa6u, 0xfeu, @@ -1156,7 +1156,7 @@ const uint8_t cy_m0p_image[] = { 0xebu, 0xf8u, 0x01u, 0x9bu, 0x30u, 0x00u, 0x1cu, 0x03u, 0x0du, 0x4bu, 0x30u, 0x22u, 0x23u, 0x43u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xe2u, 0xf8u, 0xc0u, 0x23u, 0x9bu, 0x03u, 0x30u, 0x00u, 0x23u, 0x43u, 0x30u, 0x22u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xdau, 0xf8u, 0x30u, 0x00u, 0x03u, 0x21u, 0xffu, 0xf7u, 0x30u, 0xfeu, 0xf7u, 0xbdu, 0xc0u, 0x46u, - 0xdcu, 0x05u, 0x00u, 0x08u, 0x20u, 0x30u, 0x00u, 0x00u, 0x30u, 0x20u, 0x00u, 0x00u, 0x10u, 0x00u, 0x40u, 0x00u, + 0xecu, 0x05u, 0x00u, 0x08u, 0x20u, 0x30u, 0x00u, 0x00u, 0x30u, 0x20u, 0x00u, 0x00u, 0x10u, 0x00u, 0x40u, 0x00u, 0x01u, 0x00u, 0x40u, 0x00u, 0xf8u, 0xb5u, 0x1du, 0x00u, 0x00u, 0x23u, 0x16u, 0x00u, 0x0fu, 0x00u, 0x10u, 0x22u, 0x19u, 0x00u, 0x04u, 0x00u, 0xffu, 0xf7u, 0xc0u, 0xf8u, 0xe0u, 0x23u, 0x00u, 0x22u, 0x1bu, 0x02u, 0x11u, 0x00u, 0x3bu, 0x43u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xb8u, 0xf8u, 0x90u, 0x23u, 0x00u, 0x22u, 0x1bu, 0x02u, 0x33u, 0x43u, @@ -1179,8 +1179,8 @@ const uint8_t cy_m0p_image[] = { 0x20u, 0x00u, 0x11u, 0x00u, 0xffu, 0xf7u, 0x5cu, 0xfdu, 0x33u, 0x68u, 0x2cu, 0x22u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x00u, 0xd9u, 0x04u, 0x3au, 0x0eu, 0x4bu, 0xa8u, 0xe7u, 0x0eu, 0x4bu, 0x25u, 0x22u, 0xeau, 0xe7u, 0xe0u, 0x21u, 0x20u, 0x00u, 0x89u, 0x01u, 0xffu, 0xf7u, 0x79u, 0xfdu, 0x00u, 0x23u, 0x11u, 0x22u, 0x19u, 0x00u, - 0x20u, 0x00u, 0xffu, 0xf7u, 0x19u, 0xf8u, 0xf8u, 0xbdu, 0xdcu, 0x05u, 0x00u, 0x08u, 0x0au, 0xb0u, 0x00u, 0x00u, - 0x09u, 0xc0u, 0x00u, 0x00u, 0xd0u, 0x03u, 0x00u, 0x08u, 0xdcu, 0xd0u, 0x00u, 0x00u, 0xd0u, 0xd0u, 0x00u, 0x00u, + 0x20u, 0x00u, 0xffu, 0xf7u, 0x19u, 0xf8u, 0xf8u, 0xbdu, 0xecu, 0x05u, 0x00u, 0x08u, 0x0au, 0xb0u, 0x00u, 0x00u, + 0x09u, 0xc0u, 0x00u, 0x00u, 0xe0u, 0x03u, 0x00u, 0x08u, 0xdcu, 0xd0u, 0x00u, 0x00u, 0xd0u, 0xd0u, 0x00u, 0x00u, 0x0au, 0xe0u, 0x00u, 0x00u, 0xdfu, 0xd0u, 0x00u, 0x00u, 0xf0u, 0xb5u, 0x85u, 0xb0u, 0x06u, 0x00u, 0x0fu, 0x00u, 0x02u, 0x93u, 0x0au, 0x9du, 0x0bu, 0x98u, 0x06u, 0x2au, 0x37u, 0xd8u, 0x21u, 0x4bu, 0x91u, 0x00u, 0xc9u, 0x58u, 0x20u, 0x4cu, 0x21u, 0x4bu, 0xa4u, 0x5cu, 0x9bu, 0x5cu, 0x01u, 0x22u, 0x3au, 0x70u, 0x1au, 0x19u, 0x0bu, 0x32u, @@ -1191,7 +1191,7 @@ const uint8_t cy_m0p_image[] = { 0x00u, 0x28u, 0x12u, 0xd1u, 0x00u, 0x9au, 0xa3u, 0xb2u, 0xaau, 0x18u, 0x02u, 0x99u, 0x30u, 0x00u, 0xffu, 0xf7u, 0xb5u, 0xfcu, 0x00u, 0x28u, 0x09u, 0xd1u, 0x38u, 0x70u, 0x07u, 0xe0u, 0x00u, 0x24u, 0x23u, 0x00u, 0x21u, 0x00u, 0xcau, 0xe7u, 0x01u, 0x30u, 0x42u, 0x78u, 0xffu, 0x2au, 0xe0u, 0xd0u, 0x00u, 0x20u, 0x05u, 0xb0u, 0xf0u, 0xbdu, - 0x2cu, 0x79u, 0x00u, 0x10u, 0x4fu, 0x79u, 0x00u, 0x10u, 0x48u, 0x79u, 0x00u, 0x10u, 0xf0u, 0xb5u, 0x8bu, 0xb0u, + 0x34u, 0x79u, 0x00u, 0x10u, 0x57u, 0x79u, 0x00u, 0x10u, 0x50u, 0x79u, 0x00u, 0x10u, 0xf0u, 0xb5u, 0x8bu, 0xb0u, 0x09u, 0x93u, 0x8bu, 0x68u, 0x04u, 0x00u, 0x05u, 0x93u, 0xcbu, 0x68u, 0x08u, 0x92u, 0x06u, 0x93u, 0x0bu, 0x68u, 0x4fu, 0x68u, 0x07u, 0x93u, 0x0bu, 0x69u, 0x8du, 0x69u, 0x03u, 0x93u, 0x4bu, 0x69u, 0x04u, 0x93u, 0xb3u, 0x4bu, 0x1bu, 0x68u, 0x1eu, 0x1eu, 0x02u, 0xd0u, 0x9bu, 0x6bu, 0xc3u, 0x18u, 0x1eu, 0x68u, 0x20u, 0x00u, 0xffu, 0xf7u, @@ -1238,10 +1238,10 @@ const uint8_t cy_m0p_image[] = { 0xffu, 0xf7u, 0x4eu, 0xfcu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x51u, 0xfbu, 0x0du, 0x23u, 0x00u, 0x97u, 0x1au, 0x00u, 0x19u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x44u, 0xfcu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x47u, 0xfbu, 0x01u, 0x3du, 0x93u, 0xe7u, 0x0du, 0x23u, 0x05u, 0x22u, 0x19u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x39u, 0xfcu, 0x20u, 0x00u, - 0xffu, 0xf7u, 0x3cu, 0xfbu, 0x00u, 0x97u, 0x05u, 0x23u, 0xe9u, 0xe7u, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, + 0xffu, 0xf7u, 0x3cu, 0xfbu, 0x00u, 0x97u, 0x05u, 0x23u, 0xe9u, 0xe7u, 0xc0u, 0x46u, 0xe0u, 0x03u, 0x00u, 0x08u, 0x06u, 0x60u, 0x00u, 0x00u, 0x05u, 0x50u, 0x00u, 0x00u, 0x07u, 0x70u, 0x00u, 0x00u, 0x08u, 0x80u, 0x00u, 0x00u, 0x09u, 0xa0u, 0x00u, 0x00u, 0x0au, 0xc0u, 0x00u, 0x00u, 0x0bu, 0x50u, 0x00u, 0x00u, 0x07u, 0xb0u, 0x00u, 0x00u, - 0xdcu, 0x05u, 0x00u, 0x08u, 0xb9u, 0xe0u, 0x00u, 0x00u, 0xbeu, 0xb0u, 0x00u, 0x00u, 0xf0u, 0xb5u, 0x0bu, 0x69u, + 0xecu, 0x05u, 0x00u, 0x08u, 0xb9u, 0xe0u, 0x00u, 0x00u, 0xbeu, 0xb0u, 0x00u, 0x00u, 0xf0u, 0xb5u, 0x0bu, 0x69u, 0x87u, 0xb0u, 0x03u, 0x93u, 0x4bu, 0x69u, 0x04u, 0x00u, 0x04u, 0x93u, 0x8bu, 0x69u, 0x0fu, 0x68u, 0x05u, 0x93u, 0x34u, 0x4bu, 0x4du, 0x68u, 0x1bu, 0x68u, 0x1eu, 0x1eu, 0x02u, 0xd0u, 0x9bu, 0x6bu, 0xc3u, 0x18u, 0x1eu, 0x68u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0x3du, 0xffu, 0x31u, 0x00u, 0x82u, 0xb2u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x1eu, 0xfbu, @@ -1256,13 +1256,13 @@ const uint8_t cy_m0p_image[] = { 0x0eu, 0x22u, 0x00u, 0xf0u, 0xcdu, 0xfdu, 0x2bu, 0x00u, 0x32u, 0x00u, 0x20u, 0x00u, 0x0cu, 0x21u, 0xffu, 0xf7u, 0xf9u, 0xfcu, 0x2bu, 0x00u, 0x0cu, 0x22u, 0x04u, 0x99u, 0x20u, 0x00u, 0x00u, 0xf0u, 0xc1u, 0xfdu, 0xf0u, 0x21u, 0x20u, 0x00u, 0xc9u, 0x01u, 0xffu, 0xf7u, 0x12u, 0xfbu, 0x20u, 0x00u, 0xffu, 0xf7u, 0xafu, 0xfau, 0x00u, 0x20u, - 0x07u, 0xb0u, 0xf0u, 0xbdu, 0xd0u, 0x03u, 0x00u, 0x08u, 0x0bu, 0x00u, 0x13u, 0xb5u, 0x11u, 0x00u, 0x07u, 0x22u, + 0x07u, 0xb0u, 0xf0u, 0xbdu, 0xe0u, 0x03u, 0x00u, 0x08u, 0x0bu, 0x00u, 0x13u, 0xb5u, 0x11u, 0x00u, 0x07u, 0x22u, 0x04u, 0x00u, 0x58u, 0x68u, 0x02u, 0x40u, 0xc0u, 0x20u, 0x80u, 0x00u, 0x22u, 0x50u, 0x1au, 0x69u, 0x20u, 0x00u, 0x00u, 0x92u, 0x9bu, 0x69u, 0xfeu, 0xf7u, 0xdcu, 0xffu, 0x0cu, 0x23u, 0x01u, 0x93u, 0x04u, 0x3bu, 0x00u, 0x93u, 0x20u, 0x00u, 0x04u, 0x3bu, 0x00u, 0x22u, 0x4cu, 0x21u, 0xffu, 0xf7u, 0x36u, 0xf8u, 0x04u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xe4u, 0x18u, 0x04u, 0x23u, 0x22u, 0x68u, 0x1au, 0x42u, 0xfcu, 0xd1u, 0x13u, 0xbdu, 0xc0u, 0x46u, - 0xd0u, 0x03u, 0x00u, 0x08u, 0x00u, 0xb5u, 0x06u, 0x2au, 0x00u, 0xd9u, 0x80u, 0xe0u, 0x10u, 0x00u, 0x8bu, 0x60u, - 0x1au, 0x00u, 0x02u, 0xf0u, 0x0du, 0xf8u, 0x04u, 0x16u, 0x29u, 0x3au, 0x4du, 0x6cu, 0x5cu, 0x00u, 0x54u, 0x33u, + 0xe0u, 0x03u, 0x00u, 0x08u, 0x00u, 0xb5u, 0x06u, 0x2au, 0x00u, 0xd9u, 0x80u, 0xe0u, 0x10u, 0x00u, 0x8bu, 0x60u, + 0x1au, 0x00u, 0x02u, 0xf0u, 0x11u, 0xf8u, 0x04u, 0x16u, 0x29u, 0x3au, 0x4du, 0x6cu, 0x5cu, 0x00u, 0x54u, 0x33u, 0x8bu, 0x61u, 0x3cu, 0x4bu, 0x00u, 0x20u, 0xcbu, 0x62u, 0x40u, 0x23u, 0xcbu, 0x60u, 0x2cu, 0x3bu, 0x4bu, 0x61u, 0x4bu, 0x62u, 0x2du, 0x33u, 0x40u, 0x32u, 0xffu, 0x33u, 0x0au, 0x61u, 0x08u, 0x60u, 0x48u, 0x60u, 0xcbu, 0x61u, 0x00u, 0xbdu, 0x60u, 0x33u, 0x8bu, 0x61u, 0x01u, 0x23u, 0x0bu, 0x60u, 0x4bu, 0x60u, 0x32u, 0x4bu, 0x40u, 0x32u, @@ -1278,8 +1278,8 @@ const uint8_t cy_m0p_image[] = { 0x80u, 0x23u, 0xcbu, 0x60u, 0x40u, 0x3bu, 0x4bu, 0x61u, 0x0au, 0x61u, 0x24u, 0x3bu, 0xdcu, 0xe7u, 0xc0u, 0x33u, 0x8bu, 0x61u, 0x05u, 0x23u, 0x0bu, 0x60u, 0x03u, 0x3bu, 0x4bu, 0x60u, 0x0cu, 0x4bu, 0x80u, 0x32u, 0xcbu, 0x62u, 0x80u, 0x23u, 0xcbu, 0x60u, 0x40u, 0x3bu, 0x4bu, 0x61u, 0x0au, 0x61u, 0x20u, 0x3bu, 0xccu, 0xe7u, 0x08u, 0x48u, - 0x96u, 0xe7u, 0xc0u, 0x46u, 0xd8u, 0x79u, 0x00u, 0x10u, 0xecu, 0x79u, 0x00u, 0x10u, 0x0cu, 0x7au, 0x00u, 0x10u, - 0x2cu, 0x7au, 0x00u, 0x10u, 0x6cu, 0x7au, 0x00u, 0x10u, 0xacu, 0x7au, 0x00u, 0x10u, 0xecu, 0x7au, 0x00u, 0x10u, + 0x96u, 0xe7u, 0xc0u, 0x46u, 0xe0u, 0x79u, 0x00u, 0x10u, 0xf4u, 0x79u, 0x00u, 0x10u, 0x14u, 0x7au, 0x00u, 0x10u, + 0x34u, 0x7au, 0x00u, 0x10u, 0x74u, 0x7au, 0x00u, 0x10u, 0xb4u, 0x7au, 0x00u, 0x10u, 0xf4u, 0x7au, 0x00u, 0x10u, 0x0bu, 0x00u, 0x32u, 0x00u, 0x10u, 0xb5u, 0x00u, 0x29u, 0x01u, 0xd1u, 0x07u, 0x48u, 0x10u, 0xbdu, 0x00u, 0x24u, 0x4bu, 0x69u, 0x8cu, 0x62u, 0x0cu, 0x62u, 0xa3u, 0x42u, 0xf7u, 0xd0u, 0xcau, 0x6au, 0x9bu, 0xb2u, 0x09u, 0x69u, 0xfeu, 0xf7u, 0xa0u, 0xffu, 0x20u, 0x00u, 0xf1u, 0xe7u, 0x0bu, 0x00u, 0x32u, 0x00u, 0xf7u, 0xb5u, 0x07u, 0x00u, @@ -1309,33 +1309,33 @@ const uint8_t cy_m0p_image[] = { 0x00u, 0x20u, 0x70u, 0xbdu, 0x00u, 0x48u, 0xfcu, 0xe7u, 0x0bu, 0x00u, 0x32u, 0x00u, 0xf0u, 0xb5u, 0x8fu, 0xb0u, 0x01u, 0x93u, 0x14u, 0xabu, 0x1fu, 0x78u, 0x19u, 0x4bu, 0x04u, 0x00u, 0x1bu, 0x68u, 0x00u, 0x91u, 0x16u, 0x00u, 0x1du, 0x1eu, 0x02u, 0xd0u, 0x9bu, 0x6bu, 0xc3u, 0x18u, 0x1du, 0x68u, 0x30u, 0x22u, 0x00u, 0x21u, 0x02u, 0xa8u, - 0x02u, 0xf0u, 0x7fu, 0xf8u, 0x2bu, 0x00u, 0x3au, 0x00u, 0x02u, 0xa9u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x7au, 0xfeu, + 0x02u, 0xf0u, 0x83u, 0xf8u, 0x2bu, 0x00u, 0x3au, 0x00u, 0x02u, 0xa9u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x7au, 0xfeu, 0x00u, 0x28u, 0x18u, 0xd1u, 0x02u, 0xa9u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x0cu, 0xffu, 0x00u, 0x28u, 0x12u, 0xd1u, 0x33u, 0x00u, 0x00u, 0x9au, 0x02u, 0xa9u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x18u, 0xffu, 0x00u, 0x28u, 0x0au, 0xd1u, 0x01u, 0x9au, 0x02u, 0xa9u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x4fu, 0xffu, 0x00u, 0x28u, 0x03u, 0xd1u, 0x02u, 0xa9u, - 0x20u, 0x00u, 0xffu, 0xf7u, 0xadu, 0xffu, 0x0fu, 0xb0u, 0xf0u, 0xbdu, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, + 0x20u, 0x00u, 0xffu, 0xf7u, 0xadu, 0xffu, 0x0fu, 0xb0u, 0xf0u, 0xbdu, 0xc0u, 0x46u, 0xe0u, 0x03u, 0x00u, 0x08u, 0x03u, 0x4bu, 0x1bu, 0x68u, 0x9bu, 0x68u, 0xc0u, 0x18u, 0x0fu, 0x23u, 0x00u, 0x68u, 0x18u, 0x40u, 0x70u, 0x47u, - 0xd0u, 0x03u, 0x00u, 0x08u, 0x03u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xc0u, 0x18u, 0x03u, 0x68u, 0x00u, 0x2bu, - 0xfcu, 0xd1u, 0x70u, 0x47u, 0xd0u, 0x03u, 0x00u, 0x08u, 0xf8u, 0xb5u, 0x04u, 0x00u, 0x0fu, 0x00u, 0x16u, 0x00u, + 0xe0u, 0x03u, 0x00u, 0x08u, 0x03u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xc0u, 0x18u, 0x03u, 0x68u, 0x00u, 0x2bu, + 0xfcu, 0xd1u, 0x70u, 0x47u, 0xe0u, 0x03u, 0x00u, 0x08u, 0xf8u, 0xb5u, 0x04u, 0x00u, 0x0fu, 0x00u, 0x16u, 0x00u, 0x1du, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xe4u, 0xffu, 0x04u, 0x28u, 0xfau, 0xd8u, 0xe0u, 0x21u, 0x07u, 0x4bu, 0xc9u, 0x05u, 0x1bu, 0x68u, 0x0fu, 0x43u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x17u, 0x60u, 0xdau, 0x68u, 0xa2u, 0x18u, - 0x16u, 0x60u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0x25u, 0x60u, 0xf8u, 0xbdu, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, + 0x16u, 0x60u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0x25u, 0x60u, 0xf8u, 0xbdu, 0xc0u, 0x46u, 0xe0u, 0x03u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x04u, 0x00u, 0x0du, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xcau, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x03u, 0x4bu, 0x2du, 0x06u, 0x1bu, 0x68u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0x25u, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u, - 0xd0u, 0x03u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xb9u, 0xffu, 0x06u, 0x28u, + 0xe0u, 0x03u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xb9u, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x04u, 0x4bu, 0x1bu, 0x68u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0xc8u, 0x23u, 0xdbu, 0x05u, 0x23u, 0x60u, - 0x10u, 0xbdu, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, + 0x10u, 0xbdu, 0xc0u, 0x46u, 0xe0u, 0x03u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa7u, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x04u, 0x4bu, 0x1bu, 0x68u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0xcau, 0x23u, - 0xdbu, 0x05u, 0x23u, 0x60u, 0x10u, 0xbdu, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x05u, 0x00u, + 0xdbu, 0x05u, 0x23u, 0x60u, 0x10u, 0xbdu, 0xc0u, 0x46u, 0xe0u, 0x03u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x05u, 0x00u, 0x0cu, 0x00u, 0x16u, 0x00u, 0x28u, 0x00u, 0xffu, 0xf7u, 0x93u, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x05u, 0x4bu, 0x24u, 0x02u, 0x1bu, 0x68u, 0xdbu, 0x68u, 0xedu, 0x18u, 0xccu, 0x23u, 0xdbu, 0x05u, 0x1eu, 0x43u, 0x34u, 0x43u, - 0x2cu, 0x60u, 0x70u, 0xbdu, 0xd0u, 0x03u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x05u, 0x00u, 0x0cu, 0x00u, 0x16u, 0x00u, + 0x2cu, 0x60u, 0x70u, 0xbdu, 0xe0u, 0x03u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x05u, 0x00u, 0x0cu, 0x00u, 0x16u, 0x00u, 0x28u, 0x00u, 0xffu, 0xf7u, 0x7du, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x05u, 0x4bu, 0x24u, 0x02u, 0x1bu, 0x68u, 0xdbu, 0x68u, 0xedu, 0x18u, 0xd0u, 0x23u, 0xdbu, 0x05u, 0x1eu, 0x43u, 0x34u, 0x43u, 0x2cu, 0x60u, 0x70u, 0xbdu, - 0xd0u, 0x03u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x04u, 0x00u, 0x0du, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x68u, 0xffu, + 0xe0u, 0x03u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x04u, 0x00u, 0x0du, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x68u, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0xceu, 0x21u, 0x04u, 0x4bu, 0xc9u, 0x05u, 0x1bu, 0x68u, 0x29u, 0x43u, 0xdbu, 0x68u, - 0xe4u, 0x18u, 0x21u, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, 0x00u, 0xb5u, 0x06u, 0x2au, - 0x68u, 0xd8u, 0x10u, 0x00u, 0x8bu, 0x60u, 0x01u, 0xf0u, 0xc3u, 0xfdu, 0x04u, 0x1fu, 0x12u, 0x3bu, 0x2fu, 0x49u, + 0xe4u, 0x18u, 0x21u, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u, 0xe0u, 0x03u, 0x00u, 0x08u, 0x00u, 0xb5u, 0x06u, 0x2au, + 0x68u, 0xd8u, 0x10u, 0x00u, 0x8bu, 0x60u, 0x01u, 0xf0u, 0xc7u, 0xfdu, 0x04u, 0x1fu, 0x12u, 0x3bu, 0x2fu, 0x49u, 0x57u, 0x00u, 0x40u, 0x33u, 0x0bu, 0x61u, 0x69u, 0x23u, 0x4bu, 0x60u, 0x2fu, 0x4bu, 0x00u, 0x20u, 0xcbu, 0x62u, 0x40u, 0x23u, 0xcbu, 0x60u, 0x2cu, 0x3bu, 0x08u, 0x60u, 0x4bu, 0x61u, 0x4bu, 0x62u, 0x00u, 0xbdu, 0x40u, 0x33u, 0x0bu, 0x61u, 0x02u, 0x23u, 0x0bu, 0x60u, 0x68u, 0x33u, 0x4bu, 0x60u, 0x28u, 0x4bu, 0xcbu, 0x62u, 0x40u, 0x23u, @@ -1348,9 +1348,9 @@ const uint8_t cy_m0p_image[] = { 0x05u, 0x23u, 0x0bu, 0x60u, 0x66u, 0x33u, 0x4bu, 0x60u, 0x10u, 0x4bu, 0xcbu, 0x62u, 0x80u, 0x23u, 0xcbu, 0x60u, 0x40u, 0x3bu, 0x4bu, 0x61u, 0x20u, 0x3bu, 0xd4u, 0xe7u, 0x80u, 0x33u, 0x0bu, 0x61u, 0x06u, 0x23u, 0x0bu, 0x60u, 0x65u, 0x33u, 0x4bu, 0x60u, 0x0au, 0x4bu, 0xcbu, 0x62u, 0x80u, 0x23u, 0xcbu, 0x60u, 0x40u, 0x3bu, 0x4bu, 0x61u, - 0x24u, 0x3bu, 0xc6u, 0xe7u, 0x07u, 0x48u, 0xa9u, 0xe7u, 0x2cu, 0x7bu, 0x00u, 0x10u, 0x60u, 0x7bu, 0x00u, 0x10u, - 0x40u, 0x7bu, 0x00u, 0x10u, 0xc0u, 0x7bu, 0x00u, 0x10u, 0x80u, 0x7bu, 0x00u, 0x10u, 0x40u, 0x7cu, 0x00u, 0x10u, - 0x00u, 0x7cu, 0x00u, 0x10u, 0x0bu, 0x00u, 0x32u, 0x00u, 0x10u, 0xb5u, 0x00u, 0x29u, 0x01u, 0xd1u, 0x07u, 0x48u, + 0x24u, 0x3bu, 0xc6u, 0xe7u, 0x07u, 0x48u, 0xa9u, 0xe7u, 0x34u, 0x7bu, 0x00u, 0x10u, 0x68u, 0x7bu, 0x00u, 0x10u, + 0x48u, 0x7bu, 0x00u, 0x10u, 0xc8u, 0x7bu, 0x00u, 0x10u, 0x88u, 0x7bu, 0x00u, 0x10u, 0x48u, 0x7cu, 0x00u, 0x10u, + 0x08u, 0x7cu, 0x00u, 0x10u, 0x0bu, 0x00u, 0x32u, 0x00u, 0x10u, 0xb5u, 0x00u, 0x29u, 0x01u, 0xd1u, 0x07u, 0x48u, 0x10u, 0xbdu, 0x00u, 0x24u, 0x4bu, 0x69u, 0x8cu, 0x62u, 0x0cu, 0x62u, 0xa3u, 0x42u, 0xf7u, 0xd0u, 0xcau, 0x6au, 0x9bu, 0xb2u, 0x09u, 0x69u, 0xfeu, 0xf7u, 0x40u, 0xfeu, 0x20u, 0x00u, 0xf1u, 0xe7u, 0x0bu, 0x00u, 0x32u, 0x00u, 0xf0u, 0xb5u, 0x85u, 0xb0u, 0x04u, 0x00u, 0x0du, 0x1eu, 0x03u, 0x92u, 0x01u, 0x93u, 0x00u, 0xd1u, 0x95u, 0xe0u, @@ -1373,7 +1373,7 @@ const uint8_t cy_m0p_image[] = { 0xffu, 0xf7u, 0x92u, 0xfeu, 0x00u, 0x27u, 0x38u, 0x00u, 0x05u, 0xb0u, 0xf0u, 0xbdu, 0x02u, 0x9bu, 0x31u, 0x00u, 0x9fu, 0x1bu, 0x3au, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x99u, 0xfeu, 0x69u, 0x68u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x5fu, 0xfeu, 0x01u, 0x9bu, 0x00u, 0x26u, 0xdbu, 0x1bu, 0x01u, 0x93u, 0xb8u, 0xe7u, 0x02u, 0x4fu, 0xeau, 0xe7u, - 0xd0u, 0x03u, 0x00u, 0x08u, 0x08u, 0x00u, 0x00u, 0x71u, 0x0bu, 0x00u, 0x32u, 0x00u, 0xf0u, 0xb5u, 0x85u, 0xb0u, + 0xe0u, 0x03u, 0x00u, 0x08u, 0x08u, 0x00u, 0x00u, 0x71u, 0x0bu, 0x00u, 0x32u, 0x00u, 0xf0u, 0xb5u, 0x85u, 0xb0u, 0x04u, 0x00u, 0x0du, 0x1eu, 0x02u, 0x92u, 0x00u, 0xd1u, 0x7bu, 0xe0u, 0x00u, 0x2au, 0x00u, 0xd1u, 0x78u, 0xe0u, 0x8bu, 0x6au, 0x0au, 0x6au, 0x00u, 0x93u, 0x53u, 0x0fu, 0x03u, 0x93u, 0x70u, 0x23u, 0xceu, 0x68u, 0xd7u, 0x00u, 0x01u, 0x93u, 0x80u, 0x2eu, 0x01u, 0xd0u, 0x38u, 0x3bu, 0x01u, 0x93u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x4au, 0xfeu, @@ -1397,7 +1397,7 @@ const uint8_t cy_m0p_image[] = { 0xffu, 0xf7u, 0xc0u, 0xfdu, 0x28u, 0x00u, 0xffu, 0xf7u, 0x85u, 0xfdu, 0x00u, 0x20u, 0x70u, 0xbdu, 0x01u, 0x48u, 0xfcu, 0xe7u, 0xc0u, 0x46u, 0x0bu, 0x00u, 0x32u, 0x00u, 0xf0u, 0xb5u, 0x04u, 0x00u, 0xbfu, 0xb0u, 0x01u, 0x93u, 0x44u, 0xabu, 0x1fu, 0x78u, 0x0du, 0x00u, 0x16u, 0x00u, 0x00u, 0x21u, 0xc0u, 0x22u, 0x0eu, 0xa8u, 0x01u, 0xf0u, - 0xc0u, 0xfdu, 0x30u, 0x22u, 0x00u, 0x21u, 0x02u, 0xa8u, 0x01u, 0xf0u, 0xbbu, 0xfdu, 0x0eu, 0xabu, 0x3au, 0x00u, + 0xc4u, 0xfdu, 0x30u, 0x22u, 0x00u, 0x21u, 0x02u, 0xa8u, 0x01u, 0xf0u, 0xbfu, 0xfdu, 0x0eu, 0xabu, 0x3au, 0x00u, 0x02u, 0xa9u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x02u, 0xfeu, 0x00u, 0x28u, 0x18u, 0xd1u, 0x02u, 0xa9u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x7au, 0xfeu, 0x00u, 0x28u, 0x12u, 0xd1u, 0x33u, 0x00u, 0x2au, 0x00u, 0x02u, 0xa9u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x86u, 0xfeu, 0x00u, 0x28u, 0x0au, 0xd1u, 0x01u, 0x9au, 0x02u, 0xa9u, 0x20u, 0x00u, 0xffu, 0xf7u, @@ -1409,7 +1409,7 @@ const uint8_t cy_m0p_image[] = { 0x60u, 0x21u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0x5eu, 0xfbu, 0x40u, 0x21u, 0x0au, 0x4bu, 0x1au, 0x68u, 0x13u, 0x68u, 0xe3u, 0x18u, 0x18u, 0x68u, 0x08u, 0x40u, 0xfcu, 0xd1u, 0xd3u, 0x69u, 0xe3u, 0x18u, 0x1au, 0x68u, 0x04u, 0x9bu, 0x1au, 0x60u, 0xa1u, 0x23u, 0x9bu, 0x00u, 0xe0u, 0x50u, 0x70u, 0xbdu, 0xc0u, 0x46u, 0x00u, 0x00u, 0x03u, 0x31u, - 0x01u, 0x00u, 0x01u, 0x00u, 0xd0u, 0x03u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x04u, 0x00u, 0xa0u, 0x20u, 0x1cu, 0x4du, + 0x01u, 0x00u, 0x01u, 0x00u, 0xe0u, 0x03u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x04u, 0x00u, 0xa0u, 0x20u, 0x1cu, 0x4du, 0x80u, 0x00u, 0x25u, 0x50u, 0x3fu, 0x25u, 0x04u, 0x30u, 0xb0u, 0x26u, 0x25u, 0x50u, 0x00u, 0x25u, 0xb6u, 0x00u, 0xa5u, 0x51u, 0x08u, 0x36u, 0xa5u, 0x51u, 0x17u, 0x4fu, 0x08u, 0x36u, 0x01u, 0x35u, 0xa5u, 0x51u, 0x10u, 0x36u, 0xa7u, 0x51u, 0x40u, 0x3eu, 0xa1u, 0x51u, 0xa9u, 0x21u, 0x89u, 0x00u, 0x62u, 0x50u, 0xa2u, 0x22u, 0x92u, 0x00u, @@ -1417,20 +1417,20 @@ const uint8_t cy_m0p_image[] = { 0x0du, 0x4bu, 0x1du, 0x68u, 0x2bu, 0x68u, 0xe1u, 0x18u, 0x03u, 0x00u, 0x08u, 0x68u, 0xe6u, 0x58u, 0x16u, 0x42u, 0x07u, 0xd0u, 0xc0u, 0x0fu, 0xf9u, 0xd1u, 0xebu, 0x69u, 0xe3u, 0x18u, 0x1au, 0x68u, 0x05u, 0x9bu, 0x1au, 0x60u, 0x00u, 0xe0u, 0x06u, 0x48u, 0xa1u, 0x23u, 0x00u, 0x22u, 0x9bu, 0x00u, 0xe2u, 0x50u, 0xf0u, 0xbdu, 0xc0u, 0x46u, - 0x00u, 0x00u, 0x03u, 0x31u, 0x01u, 0x00u, 0x01u, 0x00u, 0xd0u, 0x03u, 0x00u, 0x08u, 0x01u, 0x00u, 0x32u, 0x00u, + 0x00u, 0x00u, 0x03u, 0x31u, 0x01u, 0x00u, 0x01u, 0x00u, 0xe0u, 0x03u, 0x00u, 0x08u, 0x01u, 0x00u, 0x32u, 0x00u, 0x07u, 0x4bu, 0x89u, 0x00u, 0x1au, 0x68u, 0x93u, 0x6bu, 0x12u, 0x69u, 0xc3u, 0x18u, 0x89u, 0x18u, 0x08u, 0x18u, 0x1bu, 0x68u, 0x00u, 0x68u, 0x80u, 0x00u, 0x80u, 0x0cu, 0x80u, 0x00u, 0xc0u, 0x18u, 0x70u, 0x47u, 0xc0u, 0x46u, - 0xd0u, 0x03u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x06u, 0x4cu, 0x24u, 0x68u, 0x29u, 0x34u, 0x24u, 0x78u, 0x1fu, 0x2cu, + 0xe0u, 0x03u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x06u, 0x4cu, 0x24u, 0x68u, 0x29u, 0x34u, 0x24u, 0x78u, 0x1fu, 0x2cu, 0x02u, 0xd8u, 0xfeu, 0xf7u, 0x47u, 0xfbu, 0x10u, 0xbdu, 0xfeu, 0xf7u, 0x16u, 0xfcu, 0xfbu, 0xe7u, 0xc0u, 0x46u, - 0xdcu, 0x05u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x1fu, 0x24u, 0x95u, 0x00u, 0x13u, 0x05u, 0x09u, 0x4au, 0xadu, 0x0cu, + 0xecu, 0x05u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x1fu, 0x24u, 0x95u, 0x00u, 0x13u, 0x05u, 0x09u, 0x4au, 0xadu, 0x0cu, 0x12u, 0x68u, 0x89u, 0x06u, 0x29u, 0x32u, 0x12u, 0x78u, 0x1bu, 0x0du, 0x94u, 0x42u, 0xa4u, 0x41u, 0x64u, 0x42u, 0x0cu, 0x34u, 0xa5u, 0x40u, 0x0bu, 0x43u, 0x2bu, 0x43u, 0x80u, 0x22u, 0x00u, 0x21u, 0xfeu, 0xf7u, 0x6cu, 0xf8u, - 0x70u, 0xbdu, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x09u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xc0u, 0x18u, + 0x70u, 0xbdu, 0xc0u, 0x46u, 0xecu, 0x05u, 0x00u, 0x08u, 0x09u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xc0u, 0x18u, 0x08u, 0x4bu, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x04u, 0xd8u, 0x80u, 0x23u, 0x02u, 0x68u, 0x1au, 0x42u, 0xfcu, 0xd1u, 0x70u, 0x47u, 0x03u, 0x68u, 0x00u, 0x2bu, 0xfcu, 0xd1u, 0xfau, 0xe7u, 0xc0u, 0x46u, - 0xd0u, 0x03u, 0x00u, 0x08u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x13u, 0x00u, 0x06u, 0x4au, 0x14u, 0x68u, + 0xe0u, 0x03u, 0x00u, 0x08u, 0xecu, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x13u, 0x00u, 0x06u, 0x4au, 0x14u, 0x68u, 0x29u, 0x34u, 0x22u, 0x78u, 0x1fu, 0x2au, 0x03u, 0xd8u, 0x00u, 0x22u, 0xfeu, 0xf7u, 0x21u, 0xfbu, 0x10u, 0xbdu, - 0x00u, 0x22u, 0xfeu, 0xf7u, 0x0fu, 0xfcu, 0xfau, 0xe7u, 0xdcu, 0x05u, 0x00u, 0x08u, 0xf7u, 0xb5u, 0x04u, 0x00u, + 0x00u, 0x22u, 0xfeu, 0xf7u, 0x0fu, 0xfcu, 0xfau, 0xe7u, 0xecu, 0x05u, 0x00u, 0x08u, 0xf7u, 0xb5u, 0x04u, 0x00u, 0x00u, 0x93u, 0x0eu, 0x00u, 0x01u, 0x92u, 0xffu, 0xf7u, 0xcfu, 0xffu, 0x1bu, 0x4bu, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x2du, 0xd8u, 0x19u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x69u, 0xe3u, 0x18u, 0x1fu, 0x68u, 0x5du, 0x68u, 0x31u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x83u, 0xffu, 0x06u, 0x00u, 0x00u, 0x9au, 0x01u, 0x00u, @@ -1438,47 +1438,47 @@ const uint8_t cy_m0p_image[] = { 0x01u, 0x9au, 0x07u, 0x33u, 0xdbu, 0x08u, 0x9bu, 0xb2u, 0x31u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x82u, 0xffu, 0x09u, 0x4bu, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x09u, 0xd8u, 0x3au, 0x00u, 0x00u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x87u, 0xffu, 0x2au, 0x00u, 0x01u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x82u, 0xffu, - 0xf7u, 0xbdu, 0x00u, 0x25u, 0x2fu, 0x00u, 0xd4u, 0xe7u, 0xdcu, 0x05u, 0x00u, 0x08u, 0xd0u, 0x03u, 0x00u, 0x08u, + 0xf7u, 0xbdu, 0x00u, 0x25u, 0x2fu, 0x00u, 0xd4u, 0xe7u, 0xecu, 0x05u, 0x00u, 0x08u, 0xe0u, 0x03u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x85u, 0xb0u, 0x03u, 0x93u, 0x04u, 0x00u, 0x01u, 0x91u, 0x02u, 0x92u, 0xffu, 0xf7u, 0x8cu, 0xffu, 0x16u, 0x4eu, 0x33u, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x23u, 0xd8u, 0x14u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x69u, 0xe3u, 0x18u, 0x1fu, 0x68u, 0x5du, 0x68u, 0x02u, 0x99u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x40u, 0xffu, 0x03u, 0x9bu, 0x02u, 0x00u, 0x07u, 0x33u, 0xdbu, 0x08u, 0x9bu, 0xb2u, 0x01u, 0x99u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x49u, 0xffu, 0x33u, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x09u, 0xd8u, 0x3au, 0x00u, 0x00u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x4fu, 0xffu, 0x2au, 0x00u, 0x01u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x4au, 0xffu, - 0x05u, 0xb0u, 0xf0u, 0xbdu, 0x00u, 0x25u, 0x2fu, 0x00u, 0xdeu, 0xe7u, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, - 0xd0u, 0x03u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, 0x0bu, 0x00u, 0x3fu, 0x22u, 0x00u, 0x21u, 0xfdu, 0xf7u, + 0x05u, 0xb0u, 0xf0u, 0xbdu, 0x00u, 0x25u, 0x2fu, 0x00u, 0xdeu, 0xe7u, 0xc0u, 0x46u, 0xecu, 0x05u, 0x00u, 0x08u, + 0xe0u, 0x03u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, 0x0bu, 0x00u, 0x3fu, 0x22u, 0x00u, 0x21u, 0xfdu, 0xf7u, 0xbbu, 0xffu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x50u, 0xffu, 0x03u, 0x4bu, 0x1bu, 0x68u, 0xdbu, 0x6bu, 0xe4u, 0x18u, - 0x20u, 0x68u, 0x40u, 0x07u, 0xc0u, 0x0fu, 0x10u, 0xbdu, 0xd0u, 0x03u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, + 0x20u, 0x68u, 0x40u, 0x07u, 0xc0u, 0x0fu, 0x10u, 0xbdu, 0xe0u, 0x03u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, 0x13u, 0x01u, 0x0bu, 0x43u, 0x3du, 0x22u, 0x00u, 0x21u, 0xfdu, 0xf7u, 0xa6u, 0xffu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x3bu, 0xffu, 0x04u, 0x4bu, 0x1bu, 0x68u, 0xdbu, 0x6bu, 0xe4u, 0x18u, 0x20u, 0x68u, 0x40u, 0x07u, 0xc0u, 0x0fu, - 0x10u, 0xbdu, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, 0x13u, 0x01u, 0x0bu, 0x43u, + 0x10u, 0xbdu, 0xc0u, 0x46u, 0xe0u, 0x03u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, 0x13u, 0x01u, 0x0bu, 0x43u, 0x3du, 0x22u, 0x00u, 0x21u, 0xfdu, 0xf7u, 0x90u, 0xffu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x25u, 0xffu, 0x04u, 0x4bu, 0x1bu, 0x68u, 0xdbu, 0x6bu, 0xe4u, 0x18u, 0x01u, 0x23u, 0x20u, 0x68u, 0x18u, 0x40u, 0x10u, 0xbdu, 0xc0u, 0x46u, - 0xd0u, 0x03u, 0x00u, 0x08u, 0x08u, 0x4bu, 0x10u, 0xb5u, 0x1au, 0x68u, 0x8bu, 0x00u, 0x12u, 0x69u, 0x9bu, 0x18u, + 0xe0u, 0x03u, 0x00u, 0x08u, 0x08u, 0x4bu, 0x10u, 0xb5u, 0x1au, 0x68u, 0x8bu, 0x00u, 0x12u, 0x69u, 0x9bu, 0x18u, 0xc3u, 0x18u, 0x1cu, 0x68u, 0xffu, 0xf7u, 0xd4u, 0xfeu, 0xe1u, 0x04u, 0xc9u, 0x0cu, 0x08u, 0x31u, 0xc9u, 0x08u, - 0xfeu, 0xf7u, 0x3eu, 0xf9u, 0x10u, 0xbdu, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, 0x00u, 0x28u, 0x07u, 0xdbu, + 0xfeu, 0xf7u, 0x3eu, 0xf9u, 0x10u, 0xbdu, 0xc0u, 0x46u, 0xe0u, 0x03u, 0x00u, 0x08u, 0x00u, 0x28u, 0x07u, 0xdbu, 0x1fu, 0x23u, 0xc0u, 0x22u, 0x18u, 0x40u, 0x1eu, 0x3bu, 0x83u, 0x40u, 0x02u, 0x49u, 0x52u, 0x00u, 0x8bu, 0x50u, 0x70u, 0x47u, 0xc0u, 0x46u, 0x00u, 0xe1u, 0x00u, 0xe0u, 0x30u, 0xb5u, 0xf8u, 0x25u, 0x0fu, 0x4bu, 0x10u, 0x4au, 0x18u, 0x68u, 0x14u, 0x68u, 0x43u, 0x6au, 0x22u, 0x6cu, 0x6du, 0x03u, 0x9au, 0x18u, 0x11u, 0x68u, 0x29u, 0x40u, 0x10u, 0xd0u, 0x11u, 0x60u, 0x22u, 0x6cu, 0x9bu, 0x18u, 0x1bu, 0x68u, 0x0au, 0x4bu, 0x1au, 0x68u, 0x53u, 0x1cu, 0xd9u, 0x7fu, 0x00u, 0x29u, 0x07u, 0xd1u, 0x41u, 0x6au, 0x08u, 0x6au, 0x49u, 0x6au, 0x50u, 0x62u, 0x91u, 0x62u, - 0x01u, 0x22u, 0xdau, 0x77u, 0x30u, 0xbdu, 0x00u, 0x22u, 0xfbu, 0xe7u, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, - 0xd0u, 0x03u, 0x00u, 0x08u, 0xdcu, 0x03u, 0x00u, 0x08u, 0x00u, 0x22u, 0x70u, 0xb5u, 0x04u, 0x00u, 0x03u, 0x68u, + 0x01u, 0x22u, 0xdau, 0x77u, 0x30u, 0xbdu, 0x00u, 0x22u, 0xfbu, 0xe7u, 0xc0u, 0x46u, 0xecu, 0x05u, 0x00u, 0x08u, + 0xe0u, 0x03u, 0x00u, 0x08u, 0xecu, 0x03u, 0x00u, 0x08u, 0x00u, 0x22u, 0x70u, 0xb5u, 0x04u, 0x00u, 0x03u, 0x68u, 0x0du, 0x00u, 0x0bu, 0x60u, 0x43u, 0x68u, 0x4bu, 0x60u, 0x83u, 0x69u, 0x8bu, 0x60u, 0xc3u, 0x69u, 0xcbu, 0x60u, 0x4bu, 0x1cu, 0xdau, 0x77u, 0x03u, 0x8cu, 0x0bu, 0x82u, 0x03u, 0x8du, 0x0bu, 0x83u, 0xfdu, 0xf7u, 0xceu, 0xffu, - 0xa1u, 0x69u, 0x00u, 0x29u, 0x00u, 0xd1u, 0x20u, 0x49u, 0x20u, 0x00u, 0x20u, 0x30u, 0x00u, 0xf0u, 0x6eu, 0xfeu, + 0xa1u, 0x69u, 0x00u, 0x29u, 0x00u, 0xd1u, 0x20u, 0x49u, 0x20u, 0x00u, 0x20u, 0x30u, 0x00u, 0xf0u, 0x72u, 0xfeu, 0x20u, 0x22u, 0xa3u, 0x5eu, 0x00u, 0x2bu, 0x06u, 0xdbu, 0x1fu, 0x22u, 0x13u, 0x40u, 0x1eu, 0x3au, 0x9au, 0x40u, 0x13u, 0x00u, 0x1au, 0x4au, 0x13u, 0x60u, 0x1au, 0x4eu, 0x63u, 0x68u, 0x32u, 0x68u, 0x80u, 0x33u, 0x12u, 0x6au, 0x5bu, 0x01u, 0x9bu, 0x18u, 0x80u, 0x22u, 0x21u, 0x68u, 0x52u, 0x02u, 0x8au, 0x40u, 0xe1u, 0x69u, 0x9au, 0x60u, - 0x00u, 0x29u, 0x00u, 0xd1u, 0x13u, 0x49u, 0x20u, 0x00u, 0x28u, 0x30u, 0x00u, 0xf0u, 0x4fu, 0xfeu, 0x28u, 0x23u, + 0x00u, 0x29u, 0x00u, 0xd1u, 0x13u, 0x49u, 0x20u, 0x00u, 0x28u, 0x30u, 0x00u, 0xf0u, 0x53u, 0xfeu, 0x28u, 0x23u, 0xe0u, 0x5eu, 0xffu, 0xf7u, 0x8bu, 0xffu, 0x28u, 0x22u, 0xa3u, 0x5eu, 0x00u, 0x2bu, 0x06u, 0xdbu, 0x1fu, 0x22u, 0x13u, 0x40u, 0x1eu, 0x3au, 0x9au, 0x40u, 0x13u, 0x00u, 0x08u, 0x4au, 0x13u, 0x60u, 0x0au, 0x4au, 0x33u, 0x68u, 0x12u, 0x68u, 0x5bu, 0x6au, 0x92u, 0x6cu, 0x00u, 0x20u, 0x9bu, 0x18u, 0xf8u, 0x22u, 0x52u, 0x03u, 0x1au, 0x60u, 0x06u, 0x4bu, 0x1du, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u, 0xe1u, 0x5eu, 0x00u, 0x10u, 0x00u, 0xe1u, 0x00u, 0xe0u, - 0xdcu, 0x05u, 0x00u, 0x08u, 0x79u, 0x59u, 0x00u, 0x10u, 0xd0u, 0x03u, 0x00u, 0x08u, 0xdcu, 0x03u, 0x00u, 0x08u, + 0xecu, 0x05u, 0x00u, 0x08u, 0x79u, 0x59u, 0x00u, 0x10u, 0xe0u, 0x03u, 0x00u, 0x08u, 0xecu, 0x03u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x07u, 0x4bu, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1au, 0x78u, 0x06u, 0x4bu, 0x1fu, 0x2au, 0x04u, 0xd8u, 0x05u, 0x4au, 0x1au, 0x60u, 0xffu, 0xf7u, 0x90u, 0xffu, 0x10u, 0xbdu, 0x04u, 0x4au, 0xf9u, 0xe7u, 0xc0u, 0x46u, - 0xdcu, 0x05u, 0x00u, 0x08u, 0xd8u, 0x03u, 0x00u, 0x08u, 0x80u, 0x7cu, 0x00u, 0x10u, 0xd8u, 0x7cu, 0x00u, 0x10u, + 0xecu, 0x05u, 0x00u, 0x08u, 0xe8u, 0x03u, 0x00u, 0x08u, 0x88u, 0x7cu, 0x00u, 0x10u, 0xe0u, 0x7cu, 0x00u, 0x10u, 0xf0u, 0xb5u, 0xb4u, 0x4bu, 0x85u, 0xb0u, 0x1cu, 0x68u, 0x00u, 0x2cu, 0x1eu, 0xd0u, 0xb2u, 0x4bu, 0xb3u, 0x4du, 0x63u, 0x60u, 0x2bu, 0x68u, 0x5fu, 0x6au, 0x23u, 0x78u, 0x01u, 0x2bu, 0x18u, 0xd1u, 0x38u, 0x00u, 0xfeu, 0xf7u, 0x21u, 0xf8u, 0x60u, 0x60u, 0x00u, 0x23u, 0xabu, 0x4au, 0xe1u, 0x69u, 0x13u, 0x60u, 0x2bu, 0x68u, 0x1au, 0x00u, @@ -1524,8 +1524,8 @@ const uint8_t cy_m0p_image[] = { 0x40u, 0x6au, 0x52u, 0x69u, 0xb0u, 0x47u, 0x99u, 0xe7u, 0x96u, 0x69u, 0xedu, 0xe7u, 0xd6u, 0x69u, 0x28u, 0x68u, 0x00u, 0x2eu, 0x00u, 0xd1u, 0xedu, 0xe6u, 0xa1u, 0x6au, 0x03u, 0x91u, 0x8bu, 0x6au, 0x02u, 0x93u, 0x4bu, 0x6au, 0x01u, 0x93u, 0x0bu, 0x6au, 0x00u, 0x93u, 0xcbu, 0x69u, 0x8au, 0x69u, 0x40u, 0x6au, 0x49u, 0x69u, 0xb0u, 0x47u, - 0x84u, 0xe7u, 0xc0u, 0x46u, 0xe0u, 0x03u, 0x00u, 0x08u, 0x09u, 0x00u, 0x32u, 0x00u, 0xdcu, 0x05u, 0x00u, 0x08u, - 0xd0u, 0x03u, 0x00u, 0x08u, 0x0au, 0x00u, 0x32u, 0x00u, 0xd8u, 0x03u, 0x00u, 0x08u, 0xdcu, 0x03u, 0x00u, 0x08u, + 0x84u, 0xe7u, 0xc0u, 0x46u, 0xf0u, 0x03u, 0x00u, 0x08u, 0x09u, 0x00u, 0x32u, 0x00u, 0xecu, 0x05u, 0x00u, 0x08u, + 0xe0u, 0x03u, 0x00u, 0x08u, 0x0au, 0x00u, 0x32u, 0x00u, 0xe8u, 0x03u, 0x00u, 0x08u, 0xecu, 0x03u, 0x00u, 0x08u, 0x01u, 0x00u, 0x32u, 0x00u, 0x56u, 0x6au, 0x28u, 0x68u, 0x00u, 0x2eu, 0x00u, 0xd1u, 0xc9u, 0xe6u, 0xa1u, 0x6au, 0x0bu, 0x7bu, 0x00u, 0x93u, 0x8bu, 0x68u, 0x4au, 0x68u, 0x40u, 0x6au, 0x09u, 0x68u, 0xb0u, 0x47u, 0x65u, 0xe7u, 0x96u, 0x6au, 0x28u, 0x68u, 0x00u, 0x2eu, 0x00u, 0xd1u, 0xbbu, 0xe6u, 0xa1u, 0x6au, 0x0bu, 0x7bu, 0x02u, 0x93u, @@ -1549,10 +1549,10 @@ const uint8_t cy_m0p_image[] = { 0x29u, 0x6au, 0x80u, 0x33u, 0x5bu, 0x01u, 0xcbu, 0x18u, 0xdeu, 0x68u, 0x82u, 0x40u, 0x36u, 0x0cu, 0xb2u, 0x42u, 0x11u, 0xd1u, 0x12u, 0x04u, 0x1au, 0x60u, 0xacu, 0x35u, 0x1bu, 0x68u, 0x2bu, 0x88u, 0x58u, 0x43u, 0x40u, 0x18u, 0x07u, 0x49u, 0x00u, 0xf0u, 0xb5u, 0xf8u, 0x00u, 0x28u, 0x05u, 0xd1u, 0x23u, 0x68u, 0x9bu, 0x68u, 0x00u, 0x2bu, - 0x01u, 0xd1u, 0xffu, 0xf7u, 0xcdu, 0xfdu, 0x70u, 0xbdu, 0xdcu, 0x03u, 0x00u, 0x08u, 0xdcu, 0x05u, 0x00u, 0x08u, - 0xe0u, 0x03u, 0x00u, 0x08u, 0x01u, 0x4bu, 0x18u, 0x60u, 0x70u, 0x47u, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, + 0x01u, 0xd1u, 0xffu, 0xf7u, 0xcdu, 0xfdu, 0x70u, 0xbdu, 0xecu, 0x03u, 0x00u, 0x08u, 0xecu, 0x05u, 0x00u, 0x08u, + 0xf0u, 0x03u, 0x00u, 0x08u, 0x01u, 0x4bu, 0x18u, 0x60u, 0x70u, 0x47u, 0xc0u, 0x46u, 0xecu, 0x05u, 0x00u, 0x08u, 0x04u, 0x4bu, 0x1bu, 0x68u, 0x1au, 0x00u, 0xacu, 0x32u, 0x12u, 0x88u, 0x1bu, 0x6au, 0x50u, 0x43u, 0xc0u, 0x18u, - 0x70u, 0x47u, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x1du, 0x4bu, 0x98u, 0x42u, 0x0fu, 0xd0u, 0x10u, 0xd8u, + 0x70u, 0x47u, 0xc0u, 0x46u, 0xecu, 0x05u, 0x00u, 0x08u, 0x1du, 0x4bu, 0x98u, 0x42u, 0x0fu, 0xd0u, 0x10u, 0xd8u, 0x40u, 0x28u, 0x2fu, 0xd0u, 0x05u, 0xd8u, 0x00u, 0x28u, 0x30u, 0xd0u, 0x10u, 0x28u, 0x28u, 0xd0u, 0x19u, 0x48u, 0x1eu, 0xe0u, 0x80u, 0x28u, 0x28u, 0xd0u, 0x80u, 0x23u, 0x5bu, 0x00u, 0x98u, 0x42u, 0xf7u, 0xd1u, 0x14u, 0x48u, 0x16u, 0xe0u, 0x15u, 0x4bu, 0x98u, 0x42u, 0x14u, 0xd0u, 0x08u, 0xd8u, 0xa0u, 0x23u, 0x1bu, 0x06u, 0x98u, 0x42u, @@ -1566,32 +1566,32 @@ const uint8_t cy_m0p_image[] = { 0x05u, 0x00u, 0x52u, 0x00u, 0x10u, 0xb5u, 0x00u, 0x20u, 0xffu, 0xf7u, 0x9au, 0xffu, 0x0au, 0x4bu, 0x1cu, 0x68u, 0x23u, 0x00u, 0xb0u, 0x33u, 0x1bu, 0x68u, 0xc0u, 0x18u, 0x03u, 0x68u, 0x00u, 0x2bu, 0x0au, 0xdbu, 0x07u, 0x4bu, 0x18u, 0x68u, 0xffu, 0xf7u, 0x99u, 0xffu, 0x01u, 0x22u, 0x63u, 0x68u, 0x9au, 0x60u, 0x9au, 0x68u, 0x00u, 0x2au, - 0xfcu, 0xd1u, 0x10u, 0xbdu, 0x02u, 0x48u, 0xfcu, 0xe7u, 0xdcu, 0x05u, 0x00u, 0x08u, 0xe4u, 0x03u, 0x00u, 0x08u, + 0xfcu, 0xd1u, 0x10u, 0xbdu, 0x02u, 0x48u, 0xfcu, 0xe7u, 0xecu, 0x05u, 0x00u, 0x08u, 0xf4u, 0x03u, 0x00u, 0x08u, 0x02u, 0x00u, 0x50u, 0x00u, 0x06u, 0x4bu, 0x1bu, 0x68u, 0xb0u, 0x33u, 0x1bu, 0x68u, 0xc3u, 0x18u, 0x1bu, 0x68u, 0x00u, 0x2bu, 0x03u, 0xdau, 0x89u, 0xb2u, 0x41u, 0x60u, 0x00u, 0x20u, 0x70u, 0x47u, 0x01u, 0x48u, 0xfcu, 0xe7u, - 0xdcu, 0x05u, 0x00u, 0x08u, 0x01u, 0x00u, 0x8au, 0x00u, 0x03u, 0x68u, 0x00u, 0x2bu, 0x04u, 0xdau, 0x89u, 0xb2u, + 0xecu, 0x05u, 0x00u, 0x08u, 0x01u, 0x00u, 0x8au, 0x00u, 0x03u, 0x68u, 0x00u, 0x2bu, 0x04u, 0xdau, 0x89u, 0xb2u, 0xc2u, 0x60u, 0x81u, 0x60u, 0x00u, 0x20u, 0x70u, 0x47u, 0x00u, 0x48u, 0xfcu, 0xe7u, 0x01u, 0x00u, 0x8au, 0x00u, 0x06u, 0x4bu, 0x1bu, 0x68u, 0xb0u, 0x33u, 0x1bu, 0x68u, 0xc3u, 0x18u, 0x1bu, 0x68u, 0x00u, 0x2bu, 0x03u, 0xdau, - 0xc3u, 0x68u, 0x00u, 0x20u, 0x0bu, 0x60u, 0x70u, 0x47u, 0x01u, 0x48u, 0xfcu, 0xe7u, 0xdcu, 0x05u, 0x00u, 0x08u, + 0xc3u, 0x68u, 0x00u, 0x20u, 0x0bu, 0x60u, 0x70u, 0x47u, 0x01u, 0x48u, 0xfcu, 0xe7u, 0xecu, 0x05u, 0x00u, 0x08u, 0x01u, 0x00u, 0x8au, 0x00u, 0x02u, 0x4bu, 0x1au, 0x68u, 0x00u, 0x2au, 0x00u, 0xd1u, 0x18u, 0x60u, 0x70u, 0x47u, - 0xf8u, 0x03u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x2cu, 0x24u, 0x60u, 0x43u, 0x12u, 0x4cu, 0x1fu, 0x00u, 0x24u, 0x68u, + 0x08u, 0x04u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x2cu, 0x24u, 0x60u, 0x43u, 0x12u, 0x4cu, 0x1fu, 0x00u, 0x24u, 0x68u, 0x1eu, 0x0au, 0x20u, 0x18u, 0xffu, 0x24u, 0x27u, 0x40u, 0x34u, 0x40u, 0x0fu, 0x4eu, 0x1bu, 0x0cu, 0x35u, 0x68u, 0x07u, 0x60u, 0x2eu, 0x6au, 0x44u, 0x60u, 0x83u, 0x60u, 0xacu, 0x35u, 0x2du, 0x88u, 0x80u, 0x34u, 0x6fu, 0x43u, 0x64u, 0x01u, 0x34u, 0x19u, 0xbfu, 0x19u, 0x1eu, 0x04u, 0x33u, 0x43u, 0x07u, 0x61u, 0x44u, 0x61u, 0xa3u, 0x60u, 0x00u, 0x23u, 0x83u, 0x61u, 0x05u, 0x9bu, 0xc2u, 0x61u, 0x01u, 0x62u, 0x00u, 0x2bu, 0x01u, 0xd0u, 0x1bu, 0x88u, - 0x83u, 0x81u, 0xf0u, 0xbdu, 0xf8u, 0x03u, 0x00u, 0x08u, 0xdcu, 0x05u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x83u, 0x68u, + 0x83u, 0x81u, 0xf0u, 0xbdu, 0x08u, 0x04u, 0x00u, 0x08u, 0xecu, 0x05u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x83u, 0x68u, 0x85u, 0xb0u, 0x02u, 0xadu, 0x2bu, 0x80u, 0x15u, 0x4bu, 0x02u, 0x68u, 0x1bu, 0x68u, 0x06u, 0x6au, 0x9bu, 0x8eu, 0x47u, 0x6au, 0x9bu, 0x18u, 0x6bu, 0x80u, 0x43u, 0x68u, 0x00u, 0x95u, 0x82u, 0x6au, 0xc1u, 0x6au, 0x04u, 0x00u, 0x03u, 0x93u, 0x03u, 0x69u, 0xc0u, 0x68u, 0xffu, 0xf7u, 0xbdu, 0xffu, 0x00u, 0x21u, 0x3bu, 0x00u, 0x0au, 0x00u, - 0x00u, 0x91u, 0x30u, 0x00u, 0xffu, 0xf7u, 0xb6u, 0xffu, 0x21u, 0x6bu, 0x28u, 0x00u, 0x00u, 0xf0u, 0xc6u, 0xfau, + 0x00u, 0x91u, 0x30u, 0x00u, 0xffu, 0xf7u, 0xb6u, 0xffu, 0x21u, 0x6bu, 0x28u, 0x00u, 0x00u, 0xf0u, 0xcau, 0xfau, 0x00u, 0x22u, 0xabu, 0x5eu, 0x00u, 0x2bu, 0x06u, 0xdbu, 0x1fu, 0x22u, 0x13u, 0x40u, 0x1eu, 0x3au, 0x9au, 0x40u, - 0x13u, 0x00u, 0x03u, 0x4au, 0x13u, 0x60u, 0x05u, 0xb0u, 0xf0u, 0xbdu, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, + 0x13u, 0x00u, 0x03u, 0x4au, 0x13u, 0x60u, 0x05u, 0xb0u, 0xf0u, 0xbdu, 0xc0u, 0x46u, 0xecu, 0x05u, 0x00u, 0x08u, 0x00u, 0xe1u, 0x00u, 0xe0u, 0xf7u, 0xb5u, 0x2cu, 0x25u, 0x13u, 0x4cu, 0x68u, 0x43u, 0x26u, 0x68u, 0x69u, 0x43u, 0x34u, 0x18u, 0x25u, 0x69u, 0x01u, 0x93u, 0x71u, 0x18u, 0x00u, 0x2du, 0x19u, 0xd0u, 0x88u, 0x69u, 0x00u, 0x28u, 0x18u, 0xd1u, 0x2eu, 0x68u, 0x00u, 0x2eu, 0x15u, 0xdau, 0x67u, 0x68u, 0x01u, 0x24u, 0x26u, 0x00u, 0x4bu, 0x68u, 0x9eu, 0x40u, 0xb4u, 0x46u, 0x13u, 0x68u, 0x9eu, 0xb2u, 0x63u, 0x46u, 0x1bu, 0x04u, 0x1eu, 0x43u, 0x16u, 0x60u, 0xeau, 0x60u, 0x8cu, 0x61u, 0xbcu, 0x40u, 0x01u, 0x9bu, 0xa4u, 0xb2u, 0x4bu, 0x62u, 0xacu, 0x60u, 0xfeu, 0xbdu, - 0x02u, 0x48u, 0xfcu, 0xe7u, 0x02u, 0x48u, 0xfau, 0xe7u, 0xf8u, 0x03u, 0x00u, 0x08u, 0x04u, 0x02u, 0x8au, 0x00u, + 0x02u, 0x48u, 0xfcu, 0xe7u, 0x02u, 0x48u, 0xfau, 0xe7u, 0x08u, 0x04u, 0x00u, 0x08u, 0x04u, 0x02u, 0x8au, 0x00u, 0x07u, 0x02u, 0x8au, 0x00u, 0x73u, 0xb5u, 0x00u, 0x26u, 0x42u, 0x69u, 0x04u, 0x00u, 0xd5u, 0x68u, 0x01u, 0x96u, 0x2bu, 0x0cu, 0xb3u, 0x42u, 0x21u, 0xd0u, 0x1bu, 0x04u, 0x13u, 0x60u, 0x13u, 0x68u, 0x19u, 0x4bu, 0x00u, 0x69u, 0x1bu, 0x68u, 0xb0u, 0x33u, 0x1bu, 0x68u, 0xc3u, 0x18u, 0x1bu, 0x68u, 0xb3u, 0x42u, 0x15u, 0xdau, 0x01u, 0xa9u, @@ -1600,34 +1600,34 @@ const uint8_t cy_m0p_image[] = { 0x98u, 0x47u, 0x31u, 0x00u, 0x20u, 0x69u, 0xffu, 0xf7u, 0x0du, 0xffu, 0xadu, 0xb2u, 0x00u, 0x2du, 0x09u, 0xd0u, 0x63u, 0x69u, 0x1du, 0x60u, 0x00u, 0x25u, 0x1bu, 0x68u, 0x63u, 0x6au, 0xabu, 0x42u, 0x05u, 0xd0u, 0x98u, 0x47u, 0x65u, 0x62u, 0xa5u, 0x61u, 0x63u, 0x69u, 0x1bu, 0x68u, 0x73u, 0xbdu, 0xa3u, 0x6au, 0x00u, 0x2bu, 0xf8u, 0xd0u, - 0x98u, 0x47u, 0xf6u, 0xe7u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x2cu, 0x23u, 0x10u, 0xb5u, 0x43u, 0x43u, 0x03u, 0x4au, - 0x10u, 0x68u, 0xc0u, 0x18u, 0xffu, 0xf7u, 0xb6u, 0xffu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0xf8u, 0x03u, 0x00u, 0x08u, + 0x98u, 0x47u, 0xf6u, 0xe7u, 0xecu, 0x05u, 0x00u, 0x08u, 0x2cu, 0x23u, 0x10u, 0xb5u, 0x43u, 0x43u, 0x03u, 0x4au, + 0x10u, 0x68u, 0xc0u, 0x18u, 0xffu, 0xf7u, 0xb6u, 0xffu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0x08u, 0x04u, 0x00u, 0x08u, 0xf8u, 0xb5u, 0x19u, 0x4bu, 0x0fu, 0x00u, 0x1bu, 0x68u, 0x1au, 0x00u, 0x2eu, 0x32u, 0x12u, 0x78u, 0x82u, 0x42u, 0x27u, 0xd9u, 0x00u, 0x29u, 0x25u, 0xd0u, 0x1fu, 0x25u, 0x0au, 0x68u, 0x15u, 0x40u, 0x21u, 0xd1u, 0x19u, 0x00u, 0xacu, 0x31u, 0x0cu, 0x88u, 0x11u, 0x4eu, 0x60u, 0x43u, 0x1cu, 0x6au, 0xd2u, 0x08u, 0x04u, 0x19u, 0x29u, 0x00u, - 0x78u, 0x68u, 0x34u, 0x60u, 0x00u, 0xf0u, 0x3du, 0xffu, 0x29u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xcau, 0xfeu, + 0x78u, 0x68u, 0x34u, 0x60u, 0x00u, 0xf0u, 0x41u, 0xffu, 0x29u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xcau, 0xfeu, 0x3au, 0x00u, 0x29u, 0x00u, 0x30u, 0x68u, 0xffu, 0xf7u, 0xd7u, 0xfeu, 0x04u, 0x1eu, 0x07u, 0xd1u, 0x01u, 0x00u, 0x30u, 0x68u, 0xffu, 0xf7u, 0xbfu, 0xfeu, 0x03u, 0x00u, 0x20u, 0x00u, 0x00u, 0x2bu, 0x00u, 0xd0u, 0x04u, 0x48u, - 0xf8u, 0xbdu, 0x04u, 0x48u, 0xfcu, 0xe7u, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, 0xfcu, 0x03u, 0x00u, 0x08u, + 0xf8u, 0xbdu, 0x04u, 0x48u, 0xfcu, 0xe7u, 0xc0u, 0x46u, 0xecu, 0x05u, 0x00u, 0x08u, 0x0cu, 0x04u, 0x00u, 0x08u, 0x01u, 0x01u, 0x8au, 0x00u, 0x03u, 0x01u, 0x8au, 0x00u, 0x10u, 0xb5u, 0x00u, 0x2au, 0x0du, 0xd1u, 0x00u, 0x29u, 0x14u, 0xd1u, 0x0bu, 0x4bu, 0x1au, 0x68u, 0x13u, 0x00u, 0xacu, 0x33u, 0x1bu, 0x88u, 0x58u, 0x43u, 0x13u, 0x6au, 0xc0u, 0x18u, 0x08u, 0x4bu, 0x18u, 0x60u, 0x08u, 0x00u, 0x10u, 0xbdu, 0x00u, 0x29u, 0x06u, 0xd0u, 0x06u, 0x4bu, 0x19u, 0x60u, 0x19u, 0x00u, 0x5au, 0x60u, 0xffu, 0xf7u, 0xabu, 0xffu, 0xf5u, 0xe7u, 0x03u, 0x48u, 0xf3u, 0xe7u, - 0xdcu, 0x05u, 0x00u, 0x08u, 0xfcu, 0x03u, 0x00u, 0x08u, 0x78u, 0x03u, 0x00u, 0x08u, 0x03u, 0x01u, 0x8au, 0x00u, + 0xecu, 0x05u, 0x00u, 0x08u, 0x0cu, 0x04u, 0x00u, 0x08u, 0x88u, 0x03u, 0x00u, 0x08u, 0x03u, 0x01u, 0x8au, 0x00u, 0xf7u, 0xb5u, 0x18u, 0x4fu, 0x04u, 0x00u, 0x3bu, 0x68u, 0x01u, 0x91u, 0xdeu, 0x68u, 0x33u, 0x68u, 0x83u, 0x42u, 0x26u, 0xd9u, 0x00u, 0x25u, 0xa9u, 0x42u, 0x02u, 0xd1u, 0xf9u, 0xf7u, 0xc7u, 0xfeu, 0x05u, 0x00u, 0x38u, 0x68u, 0x03u, 0x68u, 0x00u, 0x2bu, 0x1au, 0xdau, 0x1fu, 0x22u, 0x01u, 0x23u, 0x22u, 0x40u, 0x93u, 0x40u, 0x64u, 0x09u, 0x72u, 0x68u, 0xa4u, 0x00u, 0x14u, 0x19u, 0x22u, 0x68u, 0x13u, 0x42u, 0x0du, 0xd0u, 0x9au, 0x43u, 0x22u, 0x60u, 0x00u, 0x24u, 0x00u, 0x21u, 0xffu, 0xf7u, 0x66u, 0xfeu, 0x01u, 0x9bu, 0x00u, 0x2bu, 0x02u, 0xd1u, 0x28u, 0x00u, 0xf9u, 0xf7u, 0xafu, 0xfeu, 0x20u, 0x00u, 0xfeu, 0xbdu, 0x03u, 0x4cu, 0xf2u, 0xe7u, 0x03u, 0x4cu, 0xf3u, 0xe7u, - 0x03u, 0x4cu, 0xf7u, 0xe7u, 0xfcu, 0x03u, 0x00u, 0x08u, 0x02u, 0x01u, 0x88u, 0x00u, 0x03u, 0x01u, 0x88u, 0x00u, + 0x03u, 0x4cu, 0xf7u, 0xe7u, 0x0cu, 0x04u, 0x00u, 0x08u, 0x02u, 0x01u, 0x88u, 0x00u, 0x03u, 0x01u, 0x88u, 0x00u, 0x04u, 0x01u, 0x8au, 0x00u, 0x0au, 0x4bu, 0x1bu, 0x68u, 0xdbu, 0x68u, 0x1au, 0x68u, 0x82u, 0x42u, 0x0du, 0xd9u, 0x59u, 0x68u, 0x1fu, 0x23u, 0x42u, 0x09u, 0x18u, 0x40u, 0x1eu, 0x3bu, 0x83u, 0x40u, 0x92u, 0x00u, 0x50u, 0x58u, 0x18u, 0x40u, 0x43u, 0x1eu, 0x98u, 0x41u, 0x03u, 0x4bu, 0xc0u, 0x18u, 0x70u, 0x47u, 0x02u, 0x48u, 0xfcu, 0xe7u, - 0xfcu, 0x03u, 0x00u, 0x08u, 0x00u, 0x01u, 0x88u, 0x00u, 0x04u, 0x01u, 0x8au, 0x00u, 0xa6u, 0x22u, 0x05u, 0x49u, + 0x0cu, 0x04u, 0x00u, 0x08u, 0x00u, 0x01u, 0x88u, 0x00u, 0x04u, 0x01u, 0x8au, 0x00u, 0xa6u, 0x22u, 0x05u, 0x49u, 0xd2u, 0x00u, 0x8bu, 0x58u, 0x02u, 0x20u, 0xdbu, 0x43u, 0x9bu, 0x07u, 0x02u, 0xd0u, 0x01u, 0x23u, 0x88u, 0x58u, 0x18u, 0x40u, 0x70u, 0x47u, 0x00u, 0x00u, 0x26u, 0x40u, 0x10u, 0xb5u, 0xffu, 0xf7u, 0xefu, 0xffu, 0x00u, 0x23u, - 0x02u, 0x28u, 0x01u, 0xd1u, 0x01u, 0x4bu, 0x1bu, 0x68u, 0x18u, 0x00u, 0x10u, 0xbdu, 0x00u, 0x04u, 0x00u, 0x08u, + 0x02u, 0x28u, 0x01u, 0xd1u, 0x01u, 0x4bu, 0x1bu, 0x68u, 0x18u, 0x00u, 0x10u, 0xbdu, 0x10u, 0x04u, 0x00u, 0x08u, 0x09u, 0x4au, 0x83u, 0x00u, 0x9bu, 0x18u, 0xd0u, 0x22u, 0x92u, 0x00u, 0x98u, 0x58u, 0x07u, 0x22u, 0x10u, 0x40u, 0x04u, 0x28u, 0x07u, 0xd1u, 0xc0u, 0x22u, 0x92u, 0x00u, 0x98u, 0x58u, 0x1fu, 0x23u, 0x03u, 0x40u, 0x80u, 0x20u, 0x40u, 0x00u, 0x18u, 0x43u, 0x70u, 0x47u, 0xc0u, 0x46u, 0x00u, 0x00u, 0x26u, 0x40u, 0x10u, 0xb5u, 0xffu, 0xf7u, @@ -1637,7 +1637,7 @@ const uint8_t cy_m0p_image[] = { 0xc0u, 0x0fu, 0xc0u, 0x03u, 0x00u, 0xe0u, 0x0bu, 0x48u, 0x10u, 0xbdu, 0x0bu, 0x4bu, 0x18u, 0x68u, 0xfbu, 0xe7u, 0xffu, 0xf7u, 0xbau, 0xffu, 0xf8u, 0xe7u, 0x09u, 0x4bu, 0x18u, 0x69u, 0x04u, 0x23u, 0x18u, 0x40u, 0xf3u, 0xd0u, 0x80u, 0x20u, 0x00u, 0x02u, 0xf0u, 0xe7u, 0x01u, 0x4au, 0x05u, 0x4bu, 0xe8u, 0xe7u, 0x00u, 0x00u, 0x26u, 0x40u, - 0x0cu, 0x05u, 0x00u, 0x00u, 0x00u, 0x12u, 0x7au, 0x00u, 0x04u, 0x04u, 0x00u, 0x08u, 0x00u, 0x00u, 0x27u, 0x40u, + 0x0cu, 0x05u, 0x00u, 0x00u, 0x00u, 0x12u, 0x7au, 0x00u, 0x14u, 0x04u, 0x00u, 0x08u, 0x00u, 0x00u, 0x27u, 0x40u, 0x3cu, 0x05u, 0x00u, 0x00u, 0xb0u, 0x23u, 0x15u, 0x4au, 0xdbu, 0x00u, 0xd3u, 0x58u, 0x10u, 0xb5u, 0x99u, 0x03u, 0xdbu, 0x01u, 0xdbu, 0x0fu, 0x89u, 0x0bu, 0xc3u, 0x71u, 0x11u, 0x4bu, 0x01u, 0x60u, 0xd3u, 0x58u, 0x0fu, 0x24u, 0xd9u, 0x04u, 0xdbu, 0x01u, 0xdbu, 0x0du, 0x03u, 0x81u, 0xb1u, 0x23u, 0xdbu, 0x00u, 0xd3u, 0x58u, 0xc9u, 0x0cu, @@ -1648,457 +1648,458 @@ const uint8_t cy_m0p_image[] = { 0x3bu, 0x33u, 0x1bu, 0x78u, 0x93u, 0x42u, 0x16u, 0xd9u, 0x7fu, 0x22u, 0x1fu, 0x24u, 0x80u, 0x30u, 0xffu, 0x30u, 0x0bu, 0x4bu, 0x80u, 0x00u, 0xc3u, 0x58u, 0x1au, 0x40u, 0x0au, 0x70u, 0x1au, 0x0cu, 0x22u, 0x40u, 0x18u, 0x0au, 0x8au, 0x70u, 0x1au, 0x01u, 0x20u, 0x40u, 0xe2u, 0x40u, 0x48u, 0x70u, 0x00u, 0x20u, 0x9bu, 0x00u, 0x9bu, 0x0fu, - 0xcau, 0x70u, 0x0bu, 0x71u, 0x10u, 0xbdu, 0x03u, 0x48u, 0xfcu, 0xe7u, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, + 0xcau, 0x70u, 0x0bu, 0x71u, 0x10u, 0xbdu, 0x03u, 0x48u, 0xfcu, 0xe7u, 0xc0u, 0x46u, 0xecu, 0x05u, 0x00u, 0x08u, 0x00u, 0x00u, 0x26u, 0x40u, 0x01u, 0x00u, 0x4au, 0x00u, 0xf0u, 0xb5u, 0x87u, 0xb0u, 0x04u, 0x00u, 0xffu, 0xf7u, - 0x65u, 0xffu, 0x06u, 0x00u, 0x00u, 0x2cu, 0x34u, 0xd1u, 0x01u, 0xadu, 0x14u, 0x22u, 0x21u, 0x00u, 0x28u, 0x00u, - 0x00u, 0xf0u, 0xcfu, 0xfdu, 0x28u, 0x00u, 0xffu, 0xf7u, 0x95u, 0xffu, 0xb0u, 0x23u, 0x25u, 0x4au, 0xdbu, 0x00u, + 0x65u, 0xffu, 0x06u, 0x00u, 0x00u, 0x2cu, 0x38u, 0xd1u, 0x01u, 0xadu, 0x14u, 0x22u, 0x21u, 0x00u, 0x28u, 0x00u, + 0x00u, 0xf0u, 0xd3u, 0xfdu, 0x28u, 0x00u, 0xffu, 0xf7u, 0x95u, 0xffu, 0xb0u, 0x23u, 0x27u, 0x4au, 0xdbu, 0x00u, 0xd3u, 0x58u, 0x00u, 0x2bu, 0x03u, 0xdau, 0xacu, 0x7bu, 0x02u, 0x3cu, 0x63u, 0x1eu, 0x9cu, 0x41u, 0xeau, 0x79u, - 0x01u, 0x9fu, 0x53u, 0x1eu, 0x9au, 0x41u, 0xa8u, 0x88u, 0x01u, 0x32u, 0x00u, 0x2cu, 0x16u, 0xd0u, 0x00u, 0x23u, - 0x19u, 0x00u, 0x00u, 0xf0u, 0x97u, 0xfcu, 0x00u, 0x23u, 0x0cu, 0x00u, 0x05u, 0x00u, 0x3au, 0x00u, 0x30u, 0x00u, - 0x19u, 0x00u, 0x00u, 0xf0u, 0x8fu, 0xfcu, 0xe6u, 0x07u, 0x6au, 0x08u, 0x32u, 0x43u, 0x63u, 0x08u, 0x80u, 0x18u, - 0x59u, 0x41u, 0x2au, 0x00u, 0x23u, 0x00u, 0x00u, 0xf0u, 0x65u, 0xfcu, 0x06u, 0x00u, 0x30u, 0x00u, 0x07u, 0xb0u, - 0xf0u, 0xbdu, 0x11u, 0x4bu, 0x1bu, 0x68u, 0x3bu, 0x33u, 0x1bu, 0x78u, 0xa3u, 0x42u, 0xf6u, 0xd3u, 0x01u, 0xadu, - 0x05u, 0x22u, 0x00u, 0x21u, 0x28u, 0x00u, 0x00u, 0xf0u, 0x94u, 0xfdu, 0x20u, 0x00u, 0x29u, 0x00u, 0x80u, 0x34u, - 0xffu, 0xf7u, 0x8au, 0xffu, 0xffu, 0x34u, 0x07u, 0x4bu, 0xa4u, 0x00u, 0xe3u, 0x58u, 0x00u, 0x24u, 0xa3u, 0x42u, - 0x03u, 0xdau, 0x2cu, 0x79u, 0x02u, 0x3cu, 0x63u, 0x1eu, 0x9cu, 0x41u, 0x2fu, 0x78u, 0x68u, 0x78u, 0xaau, 0x78u, - 0xc3u, 0xe7u, 0xc0u, 0x46u, 0x00u, 0x00u, 0x26u, 0x40u, 0xdcu, 0x05u, 0x00u, 0x08u, 0xe0u, 0x22u, 0x10u, 0xb5u, - 0x01u, 0x24u, 0x09u, 0x4bu, 0x80u, 0x00u, 0x92u, 0x00u, 0xc0u, 0x18u, 0x83u, 0x58u, 0x80u, 0x58u, 0x9bu, 0x06u, - 0x9bu, 0x0fu, 0x9cu, 0x40u, 0x0fu, 0x23u, 0x18u, 0x40u, 0xffu, 0xf7u, 0x8eu, 0xffu, 0x63u, 0x08u, 0x18u, 0x18u, - 0x21u, 0x00u, 0x00u, 0xf0u, 0x9bu, 0xfbu, 0x10u, 0xbdu, 0x00u, 0x00u, 0x26u, 0x40u, 0x14u, 0x4bu, 0x30u, 0xb5u, - 0x1au, 0x68u, 0x07u, 0x24u, 0x13u, 0x00u, 0x28u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x15u, 0xd8u, 0x83u, 0x08u, - 0x1du, 0x00u, 0xa5u, 0x43u, 0x2cu, 0x1eu, 0x0fu, 0xd1u, 0x03u, 0x34u, 0x20u, 0x40u, 0xa0u, 0x40u, 0x81u, 0x40u, - 0x12u, 0x68u, 0x9bu, 0x00u, 0x20u, 0x32u, 0xd3u, 0x18u, 0x0au, 0x00u, 0xffu, 0x21u, 0x81u, 0x40u, 0x1cu, 0x68u, - 0x62u, 0x40u, 0x11u, 0x40u, 0x61u, 0x40u, 0x19u, 0x60u, 0x30u, 0xbdu, 0x80u, 0x23u, 0x20u, 0x40u, 0x1bu, 0x06u, - 0x18u, 0x43u, 0x80u, 0x23u, 0x9bu, 0x01u, 0x12u, 0x68u, 0xc9u, 0x18u, 0x89u, 0x00u, 0x88u, 0x50u, 0xf3u, 0xe7u, - 0xdcu, 0x05u, 0x00u, 0x08u, 0x06u, 0x4bu, 0x9au, 0x68u, 0x03u, 0x00u, 0x06u, 0x48u, 0x10u, 0x33u, 0x9bu, 0x00u, - 0x82u, 0x42u, 0x02u, 0xd1u, 0x98u, 0x58u, 0x99u, 0x50u, 0x70u, 0x47u, 0x03u, 0x4au, 0xd0u, 0x58u, 0xfbu, 0xe7u, - 0x00u, 0xedu, 0x00u, 0xe0u, 0x00u, 0x00u, 0x00u, 0x08u, 0x00u, 0x00u, 0x00u, 0x10u, 0xf8u, 0xb5u, 0x06u, 0x00u, - 0x0du, 0x00u, 0x00u, 0x28u, 0x3au, 0xd0u, 0x00u, 0x23u, 0xc0u, 0x5eu, 0x00u, 0x28u, 0x28u, 0xdbu, 0x71u, 0x88u, - 0xffu, 0xf7u, 0xb4u, 0xffu, 0x00u, 0x24u, 0xffu, 0x22u, 0x03u, 0x27u, 0x94u, 0x46u, 0x00u, 0x23u, 0xf0u, 0x5eu, - 0x71u, 0x68u, 0x83u, 0xb2u, 0x1fu, 0x40u, 0xffu, 0x00u, 0x66u, 0x46u, 0xbau, 0x40u, 0x89u, 0x01u, 0x31u, 0x40u, - 0xd2u, 0x43u, 0xb9u, 0x40u, 0x00u, 0x28u, 0x15u, 0xdbu, 0x11u, 0x4eu, 0x83u, 0x08u, 0x9bu, 0x00u, 0x9bu, 0x19u, - 0xc0u, 0x26u, 0xb6u, 0x00u, 0x9fu, 0x59u, 0x3au, 0x40u, 0x11u, 0x43u, 0x99u, 0x51u, 0x0du, 0x4bu, 0x9au, 0x68u, - 0x0du, 0x4bu, 0x9au, 0x42u, 0x02u, 0xd1u, 0x29u, 0x00u, 0xffu, 0xf7u, 0xbcu, 0xffu, 0x20u, 0x00u, 0xf8u, 0xbdu, - 0x0au, 0x4cu, 0xd8u, 0xe7u, 0x0fu, 0x26u, 0x33u, 0x40u, 0x08u, 0x3bu, 0x06u, 0x4eu, 0x9bu, 0x08u, 0x9bu, 0x00u, - 0x9bu, 0x19u, 0xdeu, 0x69u, 0x32u, 0x40u, 0x11u, 0x43u, 0xd9u, 0x61u, 0xe7u, 0xe7u, 0x03u, 0x4cu, 0xedu, 0xe7u, - 0x00u, 0xe1u, 0x00u, 0xe0u, 0x00u, 0xedu, 0x00u, 0xe0u, 0x00u, 0x00u, 0x00u, 0x08u, 0x01u, 0x00u, 0x56u, 0x00u, - 0xfeu, 0xe7u, 0x00u, 0x00u, 0x02u, 0x68u, 0x0au, 0x4bu, 0x10u, 0xb5u, 0x1au, 0x60u, 0x42u, 0x68u, 0x5au, 0x60u, - 0x82u, 0x68u, 0x9au, 0x60u, 0xc2u, 0x68u, 0xdau, 0x60u, 0x02u, 0x69u, 0x1au, 0x61u, 0x42u, 0x69u, 0x5au, 0x61u, - 0x82u, 0x69u, 0x9au, 0x61u, 0xc2u, 0x69u, 0xdau, 0x61u, 0xffu, 0xf7u, 0xeau, 0xffu, 0x10u, 0xbdu, 0xc0u, 0x46u, - 0x90u, 0x03u, 0x00u, 0x08u, 0xb0u, 0x23u, 0x5bu, 0x05u, 0x9au, 0x89u, 0x00u, 0x2au, 0x02u, 0xd0u, 0x98u, 0x89u, - 0x80u, 0xb2u, 0x70u, 0x47u, 0x80u, 0x20u, 0x40u, 0x00u, 0xfbu, 0xe7u, 0x00u, 0x00u, 0x7fu, 0xb5u, 0x27u, 0x4bu, - 0x86u, 0x00u, 0x0du, 0x00u, 0xf4u, 0x58u, 0x04u, 0x29u, 0x01u, 0xd0u, 0x01u, 0x29u, 0x27u, 0xd1u, 0x00u, 0x20u, - 0x0fu, 0xe0u, 0xa3u, 0x68u, 0x2bu, 0x42u, 0x0bu, 0xd1u, 0xe3u, 0x68u, 0x29u, 0x00u, 0x1au, 0x68u, 0x5bu, 0x68u, - 0x02u, 0x92u, 0x01u, 0x93u, 0x03u, 0x93u, 0x02u, 0xa8u, 0x23u, 0x68u, 0x98u, 0x47u, 0x1cu, 0x4bu, 0x1cu, 0x60u, - 0x64u, 0x69u, 0x00u, 0x2cu, 0x0bu, 0xd0u, 0x1bu, 0x4bu, 0x98u, 0x42u, 0xeau, 0xd1u, 0x01u, 0x2du, 0xe8u, 0xd1u, - 0x17u, 0x4bu, 0x18u, 0x48u, 0x1au, 0x68u, 0x18u, 0x4bu, 0x9au, 0x51u, 0x04u, 0xb0u, 0x70u, 0xbdu, 0x01u, 0x2du, - 0xfbu, 0xd1u, 0x14u, 0x4bu, 0x98u, 0x42u, 0xf3u, 0xd0u, 0x13u, 0x4bu, 0x9cu, 0x51u, 0xf5u, 0xe7u, 0x02u, 0x29u, - 0x06u, 0xd1u, 0x0fu, 0x4bu, 0x1bu, 0x68u, 0x18u, 0x1eu, 0xefu, 0xd0u, 0x1cu, 0x69u, 0x03u, 0xe0u, 0x1cu, 0x00u, - 0x63u, 0x69u, 0x00u, 0x2bu, 0xfbu, 0xd1u, 0x00u, 0x20u, 0x00u, 0x2cu, 0xe6u, 0xd0u, 0xa3u, 0x68u, 0x2bu, 0x42u, - 0x09u, 0xd1u, 0xe3u, 0x68u, 0x29u, 0x00u, 0x1au, 0x68u, 0x5bu, 0x68u, 0x02u, 0x92u, 0x01u, 0x93u, 0x03u, 0x93u, - 0x02u, 0xa8u, 0x23u, 0x68u, 0x98u, 0x47u, 0x24u, 0x69u, 0xeeu, 0xe7u, 0xc0u, 0x46u, 0x48u, 0x04u, 0x00u, 0x08u, - 0x44u, 0x04u, 0x00u, 0x08u, 0xffu, 0x00u, 0x42u, 0x00u, 0x30u, 0x04u, 0x00u, 0x08u, 0x19u, 0x4bu, 0x1bu, 0x68u, - 0x19u, 0x00u, 0x04u, 0xc9u, 0xc9u, 0x6fu, 0x51u, 0x18u, 0x09u, 0x68u, 0x01u, 0x62u, 0x19u, 0x00u, 0x08u, 0x31u, - 0xc9u, 0x6fu, 0x52u, 0x18u, 0x12u, 0x68u, 0x42u, 0x62u, 0x1au, 0x00u, 0x41u, 0x32u, 0x12u, 0x78u, 0x00u, 0x2au, - 0x1fu, 0xd0u, 0x9au, 0x68u, 0xe0u, 0x32u, 0x12u, 0x68u, 0xd2u, 0x06u, 0x1au, 0xd5u, 0xf2u, 0x22u, 0xdbu, 0x68u, - 0xd2u, 0x01u, 0x9au, 0x58u, 0x02u, 0x60u, 0xf0u, 0x22u, 0xd2u, 0x01u, 0x9au, 0x58u, 0x42u, 0x60u, 0x0au, 0x4au, - 0x9au, 0x58u, 0x82u, 0x60u, 0x09u, 0x4au, 0x9au, 0x58u, 0xc2u, 0x60u, 0x09u, 0x4au, 0x9au, 0x58u, 0x02u, 0x61u, - 0x08u, 0x4au, 0x9au, 0x58u, 0x42u, 0x61u, 0x08u, 0x4au, 0x9au, 0x58u, 0x82u, 0x61u, 0x07u, 0x4au, 0x9bu, 0x58u, - 0xc3u, 0x61u, 0x70u, 0x47u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x04u, 0x78u, 0x00u, 0x00u, 0x08u, 0x78u, 0x00u, 0x00u, - 0x0cu, 0x78u, 0x00u, 0x00u, 0x10u, 0x78u, 0x00u, 0x00u, 0x14u, 0x78u, 0x00u, 0x00u, 0x18u, 0x78u, 0x00u, 0x00u, - 0x19u, 0x4bu, 0x1bu, 0x68u, 0x1au, 0x1du, 0x19u, 0x68u, 0xd2u, 0x6fu, 0x8au, 0x18u, 0x01u, 0x6au, 0x11u, 0x60u, - 0x1au, 0x00u, 0x08u, 0x32u, 0x19u, 0x68u, 0xd2u, 0x6fu, 0x8au, 0x18u, 0x41u, 0x6au, 0x11u, 0x60u, 0x1au, 0x00u, - 0x41u, 0x32u, 0x12u, 0x78u, 0x00u, 0x2au, 0x1eu, 0xd0u, 0x9au, 0x68u, 0xe0u, 0x32u, 0x12u, 0x68u, 0xd2u, 0x06u, - 0x19u, 0xd5u, 0xf0u, 0x22u, 0x41u, 0x68u, 0xdbu, 0x68u, 0xd2u, 0x01u, 0x99u, 0x50u, 0x81u, 0x68u, 0x0bu, 0x4au, - 0x99u, 0x50u, 0xc1u, 0x68u, 0x0au, 0x4au, 0x99u, 0x50u, 0x01u, 0x69u, 0x0au, 0x4au, 0x99u, 0x50u, 0x41u, 0x69u, - 0x09u, 0x4au, 0x99u, 0x50u, 0x81u, 0x69u, 0x09u, 0x4au, 0x99u, 0x50u, 0xc1u, 0x69u, 0x08u, 0x4au, 0x99u, 0x50u, - 0x01u, 0x68u, 0xe8u, 0x32u, 0x99u, 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0x41u, 0x5fu, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, + 0xc5u, 0x6cu, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, + 0xe3u, 0x00u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, + 0xdbu, 0x00u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, + 0x05u, 0x60u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, + 0x31u, 0x63u, 0x00u, 0x10u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, }; #endif /* defined(CY_DEVICE_PSOC6A256K) */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/COMPONENT_CM0P_SECURE/README.md b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/COMPONENT_CM0P_SECURE/README.md new file mode 100644 index 0000000000..de7423dc81 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/COMPONENT_CM0P_SECURE/README.md @@ -0,0 +1,25 @@ +# PSoC 64 Cortex M0+ Secure prebuilt image (CM0P_SECURE) + +### Overview + +Secure prebuilt application image is required to be executed on the Cortex M0+ core of the PSoC 64 dual-core MCU. + +Users of PSoC 64 Secure Boot devices have multi image boot scheme. In this case the Bootloader assumes 2 images are present in system - CM0p and CM4 in MCUBoot compatible format. + +All applications developed for CM4 need to be combined with Secure CM0p prebuild image. This is a requirement of Secure Boot system architecture. + +Secure prebuilt image executes the following steps: +- Enable/Disable CM4 access port per provisioning details acquired from Secure Flashboot +- Implement acquire procedure to enable programming and debugging if needed +- Implement acquire window time adjustment per provisioning details +- Set protection context to correspond User Application on CM4 level (per SAS on Secure Flashboot) +- Starts the CM4 core from the default address of image ID 16's BOOT section as found in default device family policy file provided by `cysecuretools` package + +### Usage + +This image is used by default by all Cypress BSPs that target PSoC 64 Dual-Core MCU. + +This image is integrated with development environments which support PSoC 64 chips. + +--- +Copyright (c) Cypress Semiconductor Corporation, 2020. diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/COMPONENT_CM0P_SECURE/psoc6_02_cm0p_secure.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/COMPONENT_CM0P_SECURE/psoc6_02_cm0p_secure.c new file mode 100644 index 0000000000..58b528ee8d --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/COMPONENT_CM0P_SECURE/psoc6_02_cm0p_secure.c @@ -0,0 +1,1815 @@ +/***************************************************************************//** +* \file psoc6_02_cm0p_secure.c +* +* \brief +* Cortex-M0+ prebuilt application image. +* +******************************************************************************** +* \copyright +* Copyright (c) 2018-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: LicenseRef-PBL +* +* Licensed under the Permissive Binary License +*******************************************************************************/ + +#include +#include "cy_device_headers.h" + +#if defined(CY_DEVICE_PSOC6A2M) + +#if defined(__APPLE__) && defined(__clang__) +__attribute__ ((__section__("__CY_M0P_IMAGE,__cy_m0p_image"), used)) +#elif defined(__GNUC__) || defined(__ARMCC_VERSION) +__attribute__ ((__section__(".cy_m0p_image"), used)) +#elif defined(__ICCARM__) +#pragma location=".cy_m0p_image" +#else +#error "An unsupported toolchain" +#endif +const uint8_t cy_m0p_image[] = { + 0x00u, 0xc0u, 0x0eu, 0x08u, 0xebu, 0x04u, 0x00u, 0x10u, 0x0du, 0x00u, 0x00u, 0x00u, 0x4du, 0x05u, 0x00u, 0x10u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x49u, 0x05u, 0x00u, 0x10u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x49u, 0x05u, 0x00u, 0x10u, 0x49u, 0x05u, 0x00u, 0x10u, + 0x49u, 0x05u, 0x00u, 0x10u, 0x49u, 0x05u, 0x00u, 0x10u, 0x49u, 0x05u, 0x00u, 0x10u, 0x49u, 0x05u, 0x00u, 0x10u, + 0x49u, 0x05u, 0x00u, 0x10u, 0x49u, 0x05u, 0x00u, 0x10u, 0x49u, 0x05u, 0x00u, 0x10u, 0x49u, 0x05u, 0x00u, 0x10u, + 0x49u, 0x05u, 0x00u, 0x10u, 0x49u, 0x05u, 0x00u, 0x10u, 0x49u, 0x05u, 0x00u, 0x10u, 0x49u, 0x05u, 0x00u, 0x10u, + 0x49u, 0x05u, 0x00u, 0x10u, 0x49u, 0x05u, 0x00u, 0x10u, 0x49u, 0x05u, 0x00u, 0x10u, 0x49u, 0x05u, 0x00u, 0x10u, + 0x10u, 0xb5u, 0x06u, 0x4cu, 0x23u, 0x78u, 0x00u, 0x2bu, 0x07u, 0xd1u, 0x05u, 0x4bu, 0x00u, 0x2bu, 0x02u, 0xd0u, + 0x04u, 0x48u, 0x00u, 0xe0u, 0x00u, 0xbfu, 0x01u, 0x23u, 0x23u, 0x70u, 0x10u, 0xbdu, 0xf8u, 0x05u, 0x0eu, 0x08u, + 0x00u, 0x00u, 0x00u, 0x00u, 0xecu, 0x6du, 0x00u, 0x10u, 0x04u, 0x4bu, 0x10u, 0xb5u, 0x00u, 0x2bu, 0x03u, 0xd0u, + 0x03u, 0x49u, 0x04u, 0x48u, 0x00u, 0xe0u, 0x00u, 0xbfu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0x00u, 0x00u, 0x00u, 0x00u, + 0xfcu, 0x05u, 0x0eu, 0x08u, 0xecu, 0x6du, 0x00u, 0x10u, 0x02u, 0x30u, 0x80u, 0x08u, 0x03u, 0xd0u, 0x01u, 0x30u, + 0x02u, 0x38u, 0xfcu, 0xd1u, 0xc0u, 0x46u, 0xc0u, 0x46u, 0x70u, 0x47u, 0xefu, 0xf3u, 0x10u, 0x80u, 0x72u, 0xb6u, + 0x70u, 0x47u, 0x80u, 0xf3u, 0x10u, 0x88u, 0x70u, 0x47u, 0x70u, 0x47u, 0xffu, 0xf7u, 0xfdu, 0xffu, 0x72u, 0xb6u, + 0x0fu, 0x4cu, 0x10u, 0x4du, 0xacu, 0x42u, 0x09u, 0xdau, 0x21u, 0x68u, 0x62u, 0x68u, 0xa3u, 0x68u, 0x04u, 0x3bu, + 0x02u, 0xdbu, 0xc8u, 0x58u, 0xd0u, 0x50u, 0xfau, 0xe7u, 0x0cu, 0x34u, 0xf3u, 0xe7u, 0x0au, 0x49u, 0x0bu, 0x4au, + 0x00u, 0x20u, 0x52u, 0x1au, 0x02u, 0xddu, 0x04u, 0x3au, 0x88u, 0x50u, 0xfcu, 0xdcu, 0x08u, 0x48u, 0x09u, 0x49u, + 0x08u, 0x60u, 0xbfu, 0xf3u, 0x4fu, 0x8fu, 0x05u, 0xf0u, 0x69u, 0xfdu, 0x05u, 0xf0u, 0xf3u, 0xfcu, 0xfeu, 0xe7u, + 0xf8u, 0x6du, 0x00u, 0x10u, 0x10u, 0x6eu, 0x00u, 0x10u, 0xf8u, 0x05u, 0x0eu, 0x08u, 0x30u, 0x0bu, 0x0eu, 0x08u, + 0x00u, 0x00u, 0x0eu, 0x08u, 0x08u, 0xedu, 0x00u, 0xe0u, 0xfeu, 0xe7u, 0xfeu, 0xe7u, 0x00u, 0xb5u, 0x04u, 0x20u, + 0x71u, 0x46u, 0x08u, 0x42u, 0x02u, 0xd0u, 0xefu, 0xf3u, 0x09u, 0x80u, 0x01u, 0xe0u, 0xefu, 0xf3u, 0x08u, 0x80u, + 0x04u, 0x30u, 0x04u, 0xf0u, 0x31u, 0xffu, 0xfeu, 0xe7u, 0x03u, 0x00u, 0x09u, 0x3bu, 0x01u, 0x22u, 0x04u, 0x2bu, + 0x02u, 0xd9u, 0x20u, 0x38u, 0x42u, 0x42u, 0x42u, 0x41u, 0x10u, 0x00u, 0x70u, 0x47u, 0xf0u, 0xb5u, 0x00u, 0x25u, + 0x17u, 0x00u, 0x06u, 0x00u, 0x2cu, 0x00u, 0x89u, 0xb0u, 0x03u, 0x93u, 0x0eu, 0x9bu, 0x02u, 0x90u, 0x1bu, 0x0cu, + 0xdbu, 0xb2u, 0x04u, 0x93u, 0x0eu, 0x9bu, 0x00u, 0x91u, 0x1bu, 0x0au, 0xdbu, 0xb2u, 0x05u, 0x93u, 0x0eu, 0x9bu, + 0xdbu, 0xb2u, 0x07u, 0x93u, 0x73u, 0x1cu, 0x06u, 0x93u, 0x33u, 0x78u, 0x01u, 0x93u, 0x00u, 0x2bu, 0x08u, 0xd0u, + 0x00u, 0x9bu, 0x00u, 0x2bu, 0x22u, 0xdbu, 0x02u, 0x9au, 0x73u, 0x1cu, 0x9bu, 0x1au, 0x00u, 0x9au, 0x9au, 0x42u, + 0x1cu, 0xdau, 0x0eu, 0x9bu, 0xdbu, 0xb2u, 0x00u, 0x2bu, 0x00u, 0xd1u, 0xb4u, 0xe0u, 0x01u, 0x9au, 0x9au, 0x42u, + 0x00u, 0xd0u, 0xaeu, 0xe0u, 0x00u, 0x9bu, 0x00u, 0x2bu, 0x06u, 0xdbu, 0x02u, 0x9au, 0x73u, 0x1cu, 0x9bu, 0x1au, + 0x00u, 0x9au, 0x93u, 0x42u, 0x00u, 0xddu, 0xa4u, 0xe0u, 0xb3u, 0x1cu, 0x76u, 0x78u, 0x03u, 0x2du, 0x00u, 0xd9u, + 0xa1u, 0xe0u, 0x28u, 0x00u, 0x05u, 0xf0u, 0xa2u, 0xfdu, 0x89u, 0x89u, 0x63u, 0x7bu, 0x01u, 0x98u, 0xffu, 0xf7u, + 0xb3u, 0xffu, 0x00u, 0x28u, 0x39u, 0xd1u, 0x07u, 0x9bu, 0x01u, 0x9au, 0x93u, 0x42u, 0xd9u, 0xd0u, 0x4fu, 0x4eu, + 0x11u, 0x00u, 0x30u, 0x00u, 0x06u, 0xf0u, 0x5eu, 0xf8u, 0x03u, 0x1eu, 0x08u, 0xd1u, 0x04u, 0x9bu, 0x01u, 0x9au, + 0x93u, 0x42u, 0x0bu, 0xd0u, 0x05u, 0x9bu, 0x93u, 0x42u, 0x6fu, 0xd1u, 0x33u, 0x00u, 0x3fu, 0x33u, 0x03u, 0x2du, + 0x23u, 0xd8u, 0x28u, 0x00u, 0x05u, 0xf0u, 0x82u, 0xfdu, 0x05u, 0x10u, 0x23u, 0x35u, 0x33u, 0x00u, 0x3eu, 0x33u, + 0xf5u, 0xe7u, 0x00u, 0x2fu, 0x06u, 0xd0u, 0x03u, 0x9au, 0x94u, 0x42u, 0x5eu, 0xd2u, 0x3fu, 0x4au, 0x9bu, 0x1au, + 0x9bu, 0x00u, 0x3bu, 0x55u, 0x01u, 0x25u, 0x10u, 0xe0u, 0x62u, 0x1cu, 0x00u, 0x2fu, 0x0bu, 0xd0u, 0x03u, 0x99u, + 0x8au, 0x42u, 0x52u, 0xd2u, 0x39u, 0x49u, 0x3cu, 0x19u, 0x5bu, 0x1au, 0x21u, 0x78u, 0x18u, 0x11u, 0x01u, 0x43u, + 0x1bu, 0x01u, 0x21u, 0x70u, 0xbbu, 0x54u, 0x14u, 0x00u, 0x02u, 0x25u, 0x06u, 0x9eu, 0x92u, 0xe7u, 0x62u, 0x1cu, + 0x00u, 0x2fu, 0x0bu, 0xd0u, 0x03u, 0x99u, 0x8au, 0x42u, 0x3fu, 0xd2u, 0x30u, 0x49u, 0x3cu, 0x19u, 0x5bu, 0x1au, + 0x21u, 0x78u, 0x98u, 0x10u, 0x01u, 0x43u, 0x9bu, 0x01u, 0x21u, 0x70u, 0xbbu, 0x54u, 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+}; +#endif /* defined(CY_DEVICE_PSOC6A2M) */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/COMPONENT_CM0P_SECURE/psoc6_02_cm0p_secure.hex b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/COMPONENT_CM0P_SECURE/psoc6_02_cm0p_secure.hex new file mode 100644 index 0000000000..15915e2e27 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/COMPONENT_CM0P_SECURE/psoc6_02_cm0p_secure.hex @@ -0,0 +1,1788 @@ +:020000041000EA +:1004000000C00E08EB0400100D0000004D050010A8 +:1004100000000000000000000000000000000000DC +:10042000000000000000000000000000490500106E +:100430000000000000000000490500104905001000 +:100440004905001049050010490500104905001034 +:100450004905001049050010490500104905001024 +:100460004905001049050010490500104905001014 +:100470004905001049050010490500104905001004 +:1004800010B5064C2378002B07D1054B002B02D06A +:10049000044800E000BF0123237010BDF8050E08DA +:1004A00000000000EC6D0010044B10B5002B03D0D1 +:1004B0000349044800E000BF10BDC0460000000032 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+/***************************************************************************//** +* \file psoc6_03_cm0p_secure.c +* +* \brief +* Cortex-M0+ prebuilt application image. +* +******************************************************************************** +* \copyright +* Copyright (c) 2018-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: LicenseRef-PBL +* +* Licensed under the Permissive Binary License +*******************************************************************************/ + +#include +#include "cy_device_headers.h" + +#if defined(CY_DEVICE_PSOC6A512K) + +#if defined(__APPLE__) && defined(__clang__) +__attribute__ ((__section__("__CY_M0P_IMAGE,__cy_m0p_image"), used)) +#elif defined(__GNUC__) || defined(__ARMCC_VERSION) +__attribute__ ((__section__(".cy_m0p_image"), used)) +#elif defined(__ICCARM__) +#pragma location=".cy_m0p_image" +#else +#error "An unsupported toolchain" +#endif +const uint8_t cy_m0p_image[] = { + 0x00u, 0xc0u, 0x02u, 0x08u, 0xebu, 0x04u, 0x00u, 0x10u, 0x0du, 0x00u, 0x00u, 0x00u, 0x4du, 0x05u, 0x00u, 0x10u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x49u, 0x05u, 0x00u, 0x10u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x49u, 0x05u, 0x00u, 0x10u, 0x49u, 0x05u, 0x00u, 0x10u, + 0x49u, 0x05u, 0x00u, 0x10u, 0x49u, 0x05u, 0x00u, 0x10u, 0x49u, 0x05u, 0x00u, 0x10u, 0x49u, 0x05u, 0x00u, 0x10u, + 0x49u, 0x05u, 0x00u, 0x10u, 0x49u, 0x05u, 0x00u, 0x10u, 0x49u, 0x05u, 0x00u, 0x10u, 0x49u, 0x05u, 0x00u, 0x10u, + 0x49u, 0x05u, 0x00u, 0x10u, 0x49u, 0x05u, 0x00u, 0x10u, 0x49u, 0x05u, 0x00u, 0x10u, 0x49u, 0x05u, 0x00u, 0x10u, + 0x49u, 0x05u, 0x00u, 0x10u, 0x49u, 0x05u, 0x00u, 0x10u, 0x49u, 0x05u, 0x00u, 0x10u, 0x49u, 0x05u, 0x00u, 0x10u, + 0x10u, 0xb5u, 0x06u, 0x4cu, 0x23u, 0x78u, 0x00u, 0x2bu, 0x07u, 0xd1u, 0x05u, 0x4bu, 0x00u, 0x2bu, 0x02u, 0xd0u, + 0x04u, 0x48u, 0x00u, 0xe0u, 0x00u, 0xbfu, 0x01u, 0x23u, 0x23u, 0x70u, 0x10u, 0xbdu, 0xf8u, 0x05u, 0x02u, 0x08u, + 0x00u, 0x00u, 0x00u, 0x00u, 0xecu, 0x6du, 0x00u, 0x10u, 0x04u, 0x4bu, 0x10u, 0xb5u, 0x00u, 0x2bu, 0x03u, 0xd0u, + 0x03u, 0x49u, 0x04u, 0x48u, 0x00u, 0xe0u, 0x00u, 0xbfu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0x00u, 0x00u, 0x00u, 0x00u, + 0xfcu, 0x05u, 0x02u, 0x08u, 0xecu, 0x6du, 0x00u, 0x10u, 0x02u, 0x30u, 0x80u, 0x08u, 0x03u, 0xd0u, 0x01u, 0x30u, + 0x02u, 0x38u, 0xfcu, 0xd1u, 0xc0u, 0x46u, 0xc0u, 0x46u, 0x70u, 0x47u, 0xefu, 0xf3u, 0x10u, 0x80u, 0x72u, 0xb6u, + 0x70u, 0x47u, 0x80u, 0xf3u, 0x10u, 0x88u, 0x70u, 0x47u, 0x70u, 0x47u, 0xffu, 0xf7u, 0xfdu, 0xffu, 0x72u, 0xb6u, + 0x0fu, 0x4cu, 0x10u, 0x4du, 0xacu, 0x42u, 0x09u, 0xdau, 0x21u, 0x68u, 0x62u, 0x68u, 0xa3u, 0x68u, 0x04u, 0x3bu, + 0x02u, 0xdbu, 0xc8u, 0x58u, 0xd0u, 0x50u, 0xfau, 0xe7u, 0x0cu, 0x34u, 0xf3u, 0xe7u, 0x0au, 0x49u, 0x0bu, 0x4au, + 0x00u, 0x20u, 0x52u, 0x1au, 0x02u, 0xddu, 0x04u, 0x3au, 0x88u, 0x50u, 0xfcu, 0xdcu, 0x08u, 0x48u, 0x09u, 0x49u, + 0x08u, 0x60u, 0xbfu, 0xf3u, 0x4fu, 0x8fu, 0x05u, 0xf0u, 0x69u, 0xfdu, 0x05u, 0xf0u, 0xf3u, 0xfcu, 0xfeu, 0xe7u, + 0xf8u, 0x6du, 0x00u, 0x10u, 0x10u, 0x6eu, 0x00u, 0x10u, 0xf8u, 0x05u, 0x02u, 0x08u, 0x30u, 0x0bu, 0x02u, 0x08u, + 0x00u, 0x00u, 0x02u, 0x08u, 0x08u, 0xedu, 0x00u, 0xe0u, 0xfeu, 0xe7u, 0xfeu, 0xe7u, 0x00u, 0xb5u, 0x04u, 0x20u, + 0x71u, 0x46u, 0x08u, 0x42u, 0x02u, 0xd0u, 0xefu, 0xf3u, 0x09u, 0x80u, 0x01u, 0xe0u, 0xefu, 0xf3u, 0x08u, 0x80u, + 0x04u, 0x30u, 0x04u, 0xf0u, 0x31u, 0xffu, 0xfeu, 0xe7u, 0x03u, 0x00u, 0x09u, 0x3bu, 0x01u, 0x22u, 0x04u, 0x2bu, + 0x02u, 0xd9u, 0x20u, 0x38u, 0x42u, 0x42u, 0x42u, 0x41u, 0x10u, 0x00u, 0x70u, 0x47u, 0xf0u, 0xb5u, 0x00u, 0x25u, + 0x17u, 0x00u, 0x06u, 0x00u, 0x2cu, 0x00u, 0x89u, 0xb0u, 0x03u, 0x93u, 0x0eu, 0x9bu, 0x02u, 0x90u, 0x1bu, 0x0cu, + 0xdbu, 0xb2u, 0x04u, 0x93u, 0x0eu, 0x9bu, 0x00u, 0x91u, 0x1bu, 0x0au, 0xdbu, 0xb2u, 0x05u, 0x93u, 0x0eu, 0x9bu, + 0xdbu, 0xb2u, 0x07u, 0x93u, 0x73u, 0x1cu, 0x06u, 0x93u, 0x33u, 0x78u, 0x01u, 0x93u, 0x00u, 0x2bu, 0x08u, 0xd0u, + 0x00u, 0x9bu, 0x00u, 0x2bu, 0x22u, 0xdbu, 0x02u, 0x9au, 0x73u, 0x1cu, 0x9bu, 0x1au, 0x00u, 0x9au, 0x9au, 0x42u, + 0x1cu, 0xdau, 0x0eu, 0x9bu, 0xdbu, 0xb2u, 0x00u, 0x2bu, 0x00u, 0xd1u, 0xb4u, 0xe0u, 0x01u, 0x9au, 0x9au, 0x42u, + 0x00u, 0xd0u, 0xaeu, 0xe0u, 0x00u, 0x9bu, 0x00u, 0x2bu, 0x06u, 0xdbu, 0x02u, 0x9au, 0x73u, 0x1cu, 0x9bu, 0x1au, + 0x00u, 0x9au, 0x93u, 0x42u, 0x00u, 0xddu, 0xa4u, 0xe0u, 0xb3u, 0x1cu, 0x76u, 0x78u, 0x03u, 0x2du, 0x00u, 0xd9u, + 0xa1u, 0xe0u, 0x28u, 0x00u, 0x05u, 0xf0u, 0xa2u, 0xfdu, 0x89u, 0x89u, 0x63u, 0x7bu, 0x01u, 0x98u, 0xffu, 0xf7u, + 0xb3u, 0xffu, 0x00u, 0x28u, 0x39u, 0xd1u, 0x07u, 0x9bu, 0x01u, 0x9au, 0x93u, 0x42u, 0xd9u, 0xd0u, 0x4fu, 0x4eu, + 0x11u, 0x00u, 0x30u, 0x00u, 0x06u, 0xf0u, 0x5eu, 0xf8u, 0x03u, 0x1eu, 0x08u, 0xd1u, 0x04u, 0x9bu, 0x01u, 0x9au, + 0x93u, 0x42u, 0x0bu, 0xd0u, 0x05u, 0x9bu, 0x93u, 0x42u, 0x6fu, 0xd1u, 0x33u, 0x00u, 0x3fu, 0x33u, 0x03u, 0x2du, + 0x23u, 0xd8u, 0x28u, 0x00u, 0x05u, 0xf0u, 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index 0000000000..b4ddd00479 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/COMPONENT_CM0P_SECURE/psoc6_03_cm0p_secure.hex @@ -0,0 +1,1788 @@ +:020000041000EA +:1004000000C00208EB0400100D0000004D050010B4 +:1004100000000000000000000000000000000000DC +:10042000000000000000000000000000490500106E +:100430000000000000000000490500104905001000 +:100440004905001049050010490500104905001034 +:100450004905001049050010490500104905001024 +:100460004905001049050010490500104905001014 +:100470004905001049050010490500104905001004 +:1004800010B5064C2378002B07D1054B002B02D06A +:10049000044800E000BF0123237010BDF8050208E6 +:1004A00000000000EC6D0010044B10B5002B03D0D1 +:1004B0000349044800E000BF10BDC0460000000032 +:1004C000FC050208EC6D00100230800803D00130FA +:1004D0000238FCD1C046C0467047EFF3108072B6B8 +:1004E000704780F3108870477047FFF7FDFF72B6C2 +:1004F0000F4C104DAC4209DA21686268A368043BD6 +:1005000002DBC858D050FAE70C34F3E70A490B4A2B +:100510000020521A02DD043A8850FCDC08480949E0 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+:10731800604700BFB949001001B40248844601BC67 +:10732800604700BFA960001001B40248844601BC50 +:10733800604700BFD51E001001B40248844601BC56 +:10734800604700BFE149001001B40248844601BC0F +:10735800604700BFDB04001001B40248844601BC4A +:08736800604700BFC91D0010C1 +:04000005100004EBF8 +:00000001FF diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/COMPONENT_CM0P_SLEEP/psoc6_01_cm0p_sleep.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/COMPONENT_CM0P_SLEEP/psoc6_01_cm0p_sleep.c index e1204782e9..46036b6dcd 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/COMPONENT_CM0P_SLEEP/psoc6_01_cm0p_sleep.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/COMPONENT_CM0P_SLEEP/psoc6_01_cm0p_sleep.c @@ -40,22 +40,22 @@ const uint8_t cy_m0p_image[] = { 0x89u, 0x01u, 0x00u, 0x10u, 0x89u, 0x01u, 0x00u, 0x10u, 0x89u, 0x01u, 0x00u, 0x10u, 0x89u, 0x01u, 0x00u, 0x10u, 0x89u, 0x01u, 0x00u, 0x10u, 0x89u, 0x01u, 0x00u, 0x10u, 0x89u, 0x01u, 0x00u, 0x10u, 0x89u, 0x01u, 0x00u, 0x10u, 0x10u, 0xb5u, 0x06u, 0x4cu, 0x23u, 0x78u, 0x00u, 0x2bu, 0x07u, 0xd1u, 0x05u, 0x4bu, 0x00u, 0x2bu, 0x02u, 0xd0u, - 0x04u, 0x48u, 0x00u, 0xe0u, 0x00u, 0xbfu, 0x01u, 0x23u, 0x23u, 0x70u, 0x10u, 0xbdu, 0xf8u, 0x03u, 0x00u, 0x08u, - 0x00u, 0x00u, 0x00u, 0x00u, 0xf0u, 0x14u, 0x00u, 0x10u, 0x04u, 0x4bu, 0x10u, 0xb5u, 0x00u, 0x2bu, 0x03u, 0xd0u, + 0x04u, 0x48u, 0x00u, 0xe0u, 0x00u, 0xbfu, 0x01u, 0x23u, 0x23u, 0x70u, 0x10u, 0xbdu, 0x08u, 0x04u, 0x00u, 0x08u, + 0x00u, 0x00u, 0x00u, 0x00u, 0xf8u, 0x14u, 0x00u, 0x10u, 0x04u, 0x4bu, 0x10u, 0xb5u, 0x00u, 0x2bu, 0x03u, 0xd0u, 0x03u, 0x49u, 0x04u, 0x48u, 0x00u, 0xe0u, 0x00u, 0xbfu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0x00u, 0x00u, 0x00u, 0x00u, - 0xfcu, 0x03u, 0x00u, 0x08u, 0xf0u, 0x14u, 0x00u, 0x10u, 0x02u, 0x30u, 0x80u, 0x08u, 0x03u, 0xd0u, 0x01u, 0x30u, + 0x0cu, 0x04u, 0x00u, 0x08u, 0xf8u, 0x14u, 0x00u, 0x10u, 0x02u, 0x30u, 0x80u, 0x08u, 0x03u, 0xd0u, 0x01u, 0x30u, 0x02u, 0x38u, 0xfcu, 0xd1u, 0xc0u, 0x46u, 0xc0u, 0x46u, 0x70u, 0x47u, 0xefu, 0xf3u, 0x10u, 0x80u, 0x72u, 0xb6u, 0x70u, 0x47u, 0x80u, 0xf3u, 0x10u, 0x88u, 0x70u, 0x47u, 0x70u, 0x47u, 0xffu, 0xf7u, 0xfdu, 0xffu, 0x72u, 0xb6u, 0x0fu, 0x4cu, 0x10u, 0x4du, 0xacu, 0x42u, 0x09u, 0xdau, 0x21u, 0x68u, 0x62u, 0x68u, 0xa3u, 0x68u, 0x04u, 0x3bu, 0x02u, 0xdbu, 0xc8u, 0x58u, 0xd0u, 0x50u, 0xfau, 0xe7u, 0x0cu, 0x34u, 0xf3u, 0xe7u, 0x0au, 0x49u, 0x0bu, 0x4au, 0x00u, 0x20u, 0x52u, 0x1au, 0x02u, 0xddu, 0x04u, 0x3au, 0x88u, 0x50u, 0xfcu, 0xdcu, 0x08u, 0x48u, 0x09u, 0x49u, - 0x08u, 0x60u, 0xbfu, 0xf3u, 0x4fu, 0x8fu, 0x00u, 0xf0u, 0xcfu, 0xfeu, 0x00u, 0xf0u, 0x79u, 0xfeu, 0xfeu, 0xe7u, - 0xfcu, 0x14u, 0x00u, 0x10u, 0x14u, 0x15u, 0x00u, 0x10u, 0xf8u, 0x03u, 0x00u, 0x08u, 0x14u, 0x06u, 0x00u, 0x08u, + 0x08u, 0x60u, 0xbfu, 0xf3u, 0x4fu, 0x8fu, 0x00u, 0xf0u, 0xd3u, 0xfeu, 0x00u, 0xf0u, 0x7du, 0xfeu, 0xfeu, 0xe7u, + 0x04u, 0x15u, 0x00u, 0x10u, 0x1cu, 0x15u, 0x00u, 0x10u, 0x08u, 0x04u, 0x00u, 0x08u, 0x24u, 0x06u, 0x00u, 0x08u, 0x00u, 0x00u, 0x00u, 0x08u, 0x08u, 0xedu, 0x00u, 0xe0u, 0xfeu, 0xe7u, 0xfeu, 0xe7u, 0x00u, 0xb5u, 0x04u, 0x20u, 0x71u, 0x46u, 0x08u, 0x42u, 0x02u, 0xd0u, 0xefu, 0xf3u, 0x09u, 0x80u, 0x01u, 0xe0u, 0xefu, 0xf3u, 0x08u, 0x80u, - 0x04u, 0x30u, 0x00u, 0xf0u, 0x6bu, 0xfcu, 0xfeu, 0xe7u, 0x01u, 0x4bu, 0x18u, 0x60u, 0x70u, 0x47u, 0xc0u, 0x46u, - 0x10u, 0x06u, 0x00u, 0x08u, 0x04u, 0x4bu, 0x1bu, 0x68u, 0x1au, 0x00u, 0xacu, 0x32u, 0x12u, 0x88u, 0x1bu, 0x6au, - 0x50u, 0x43u, 0xc0u, 0x18u, 0x70u, 0x47u, 0xc0u, 0x46u, 0x10u, 0x06u, 0x00u, 0x08u, 0x1du, 0x4bu, 0x98u, 0x42u, + 0x04u, 0x30u, 0x00u, 0xf0u, 0x6fu, 0xfcu, 0xfeu, 0xe7u, 0x01u, 0x4bu, 0x18u, 0x60u, 0x70u, 0x47u, 0xc0u, 0x46u, + 0x20u, 0x06u, 0x00u, 0x08u, 0x04u, 0x4bu, 0x1bu, 0x68u, 0x1au, 0x00u, 0xacu, 0x32u, 0x12u, 0x88u, 0x1bu, 0x6au, + 0x50u, 0x43u, 0xc0u, 0x18u, 0x70u, 0x47u, 0xc0u, 0x46u, 0x20u, 0x06u, 0x00u, 0x08u, 0x1du, 0x4bu, 0x98u, 0x42u, 0x0fu, 0xd0u, 0x10u, 0xd8u, 0x40u, 0x28u, 0x2fu, 0xd0u, 0x05u, 0xd8u, 0x00u, 0x28u, 0x30u, 0xd0u, 0x10u, 0x28u, 0x28u, 0xd0u, 0x19u, 0x48u, 0x1eu, 0xe0u, 0x80u, 0x28u, 0x28u, 0xd0u, 0x80u, 0x23u, 0x5bu, 0x00u, 0x98u, 0x42u, 0xf7u, 0xd1u, 0x14u, 0x48u, 0x16u, 0xe0u, 0x15u, 0x4bu, 0x98u, 0x42u, 0x14u, 0xd0u, 0x08u, 0xd8u, 0xa0u, 0x23u, @@ -69,41 +69,41 @@ const uint8_t cy_m0p_image[] = { 0x02u, 0x00u, 0x50u, 0x00u, 0x05u, 0x00u, 0x52u, 0x00u, 0x10u, 0xb5u, 0x00u, 0x20u, 0xffu, 0xf7u, 0x9au, 0xffu, 0x0au, 0x4bu, 0x1cu, 0x68u, 0x23u, 0x00u, 0xb0u, 0x33u, 0x1bu, 0x68u, 0xc0u, 0x18u, 0x03u, 0x68u, 0x00u, 0x2bu, 0x0au, 0xdbu, 0x07u, 0x4bu, 0x18u, 0x68u, 0xffu, 0xf7u, 0x99u, 0xffu, 0x01u, 0x22u, 0x63u, 0x68u, 0x9au, 0x60u, - 0x9au, 0x68u, 0x00u, 0x2au, 0xfcu, 0xd1u, 0x10u, 0xbdu, 0x02u, 0x48u, 0xfcu, 0xe7u, 0x10u, 0x06u, 0x00u, 0x08u, - 0x14u, 0x04u, 0x00u, 0x08u, 0x02u, 0x00u, 0x50u, 0x00u, 0x0du, 0x4bu, 0x10u, 0xb5u, 0x18u, 0x60u, 0x00u, 0x28u, + 0x9au, 0x68u, 0x00u, 0x2au, 0xfcu, 0xd1u, 0x10u, 0xbdu, 0x02u, 0x48u, 0xfcu, 0xe7u, 0x20u, 0x06u, 0x00u, 0x08u, + 0x24u, 0x04u, 0x00u, 0x08u, 0x02u, 0x00u, 0x50u, 0x00u, 0x0du, 0x4bu, 0x10u, 0xb5u, 0x18u, 0x60u, 0x00u, 0x28u, 0x04u, 0xd0u, 0xfeu, 0x23u, 0x5bu, 0x42u, 0x03u, 0x80u, 0x00u, 0x23u, 0x43u, 0x80u, 0x09u, 0x4bu, 0x1bu, 0x68u, 0x1au, 0x00u, 0x4cu, 0x32u, 0x12u, 0x78u, 0x00u, 0x2au, 0x08u, 0xd0u, 0x4du, 0x33u, 0x1bu, 0x78u, 0x00u, 0x2bu, 0x04u, 0xd0u, 0x02u, 0x22u, 0x04u, 0x49u, 0x00u, 0x20u, 0x00u, 0xf0u, 0xe0u, 0xf8u, 0x10u, 0xbdu, 0xc0u, 0x46u, - 0x24u, 0x04u, 0x00u, 0x08u, 0x10u, 0x06u, 0x00u, 0x08u, 0x45u, 0x01u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x02u, 0x48u, - 0xffu, 0xf7u, 0xdau, 0xffu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0xb8u, 0x03u, 0x00u, 0x08u, 0x06u, 0x4bu, 0x1bu, 0x68u, + 0x34u, 0x04u, 0x00u, 0x08u, 0x20u, 0x06u, 0x00u, 0x08u, 0x55u, 0x01u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x02u, 0x48u, + 0xffu, 0xf7u, 0xdau, 0xffu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0xc8u, 0x03u, 0x00u, 0x08u, 0x06u, 0x4bu, 0x1bu, 0x68u, 0xb0u, 0x33u, 0x1bu, 0x68u, 0xc3u, 0x18u, 0x1bu, 0x68u, 0x00u, 0x2bu, 0x03u, 0xdau, 0x89u, 0xb2u, 0x41u, 0x60u, - 0x00u, 0x20u, 0x70u, 0x47u, 0x01u, 0x48u, 0xfcu, 0xe7u, 0x10u, 0x06u, 0x00u, 0x08u, 0x01u, 0x00u, 0x8au, 0x00u, + 0x00u, 0x20u, 0x70u, 0x47u, 0x01u, 0x48u, 0xfcu, 0xe7u, 0x20u, 0x06u, 0x00u, 0x08u, 0x01u, 0x00u, 0x8au, 0x00u, 0x03u, 0x68u, 0x00u, 0x2bu, 0x04u, 0xdau, 0x89u, 0xb2u, 0xc2u, 0x60u, 0x81u, 0x60u, 0x00u, 0x20u, 0x70u, 0x47u, 0x00u, 0x48u, 0xfcu, 0xe7u, 0x01u, 0x00u, 0x8au, 0x00u, 0x06u, 0x4bu, 0x1bu, 0x68u, 0xb0u, 0x33u, 0x1bu, 0x68u, 0xc3u, 0x18u, 0x1bu, 0x68u, 0x00u, 0x2bu, 0x03u, 0xdau, 0xc3u, 0x68u, 0x00u, 0x20u, 0x0bu, 0x60u, 0x70u, 0x47u, - 0x01u, 0x48u, 0xfcu, 0xe7u, 0x10u, 0x06u, 0x00u, 0x08u, 0x01u, 0x00u, 0x8au, 0x00u, 0x02u, 0x4bu, 0x1au, 0x68u, - 0x00u, 0x2au, 0x00u, 0xd1u, 0x18u, 0x60u, 0x70u, 0x47u, 0x28u, 0x04u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x2cu, 0x24u, + 0x01u, 0x48u, 0xfcu, 0xe7u, 0x20u, 0x06u, 0x00u, 0x08u, 0x01u, 0x00u, 0x8au, 0x00u, 0x02u, 0x4bu, 0x1au, 0x68u, + 0x00u, 0x2au, 0x00u, 0xd1u, 0x18u, 0x60u, 0x70u, 0x47u, 0x38u, 0x04u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x2cu, 0x24u, 0x60u, 0x43u, 0x15u, 0x4cu, 0x1fu, 0x00u, 0x24u, 0x68u, 0x1du, 0x0au, 0x20u, 0x18u, 0xffu, 0x24u, 0x25u, 0x40u, 0x27u, 0x40u, 0x12u, 0x4cu, 0x1bu, 0x0cu, 0x26u, 0x68u, 0x07u, 0x60u, 0x34u, 0x6au, 0x45u, 0x60u, 0x83u, 0x60u, 0xacu, 0x36u, 0x36u, 0x88u, 0x77u, 0x43u, 0x3fu, 0x19u, 0x07u, 0x61u, 0x2fu, 0x00u, 0x80u, 0x37u, 0x6du, 0x01u, 0x7fu, 0x01u, 0xe7u, 0x19u, 0x64u, 0x19u, 0x0au, 0x4du, 0x47u, 0x61u, 0x1fu, 0x04u, 0x3bu, 0x43u, 0x64u, 0x19u, 0x23u, 0x60u, 0x00u, 0x23u, 0x83u, 0x61u, 0x05u, 0x9bu, 0xc2u, 0x61u, 0x01u, 0x62u, 0x00u, 0x2bu, 0x01u, 0xd0u, - 0x1bu, 0x88u, 0x83u, 0x81u, 0xf0u, 0xbdu, 0xc0u, 0x46u, 0x28u, 0x04u, 0x00u, 0x08u, 0x10u, 0x06u, 0x00u, 0x08u, + 0x1bu, 0x88u, 0x83u, 0x81u, 0xf0u, 0xbdu, 0xc0u, 0x46u, 0x38u, 0x04u, 0x00u, 0x08u, 0x20u, 0x06u, 0x00u, 0x08u, 0x08u, 0x10u, 0x00u, 0x00u, 0xf0u, 0xb5u, 0x83u, 0x68u, 0x85u, 0xb0u, 0x02u, 0xadu, 0x2bu, 0x80u, 0x15u, 0x4bu, 0x02u, 0x68u, 0x1bu, 0x68u, 0x06u, 0x6au, 0x9bu, 0x8eu, 0x47u, 0x6au, 0x9bu, 0x18u, 0xabu, 0x70u, 0x43u, 0x68u, 0x00u, 0x95u, 0x82u, 0x6au, 0xc1u, 0x6au, 0x04u, 0x00u, 0x03u, 0x93u, 0x03u, 0x69u, 0xc0u, 0x68u, 0xffu, 0xf7u, 0xb5u, 0xffu, 0x00u, 0x21u, 0x3bu, 0x00u, 0x0au, 0x00u, 0x00u, 0x91u, 0x30u, 0x00u, 0xffu, 0xf7u, 0xaeu, 0xffu, - 0x21u, 0x6bu, 0x28u, 0x00u, 0x00u, 0xf0u, 0xdeu, 0xfau, 0x00u, 0x22u, 0xabu, 0x5eu, 0x00u, 0x2bu, 0x06u, 0xdbu, + 0x21u, 0x6bu, 0x28u, 0x00u, 0x00u, 0xf0u, 0xe2u, 0xfau, 0x00u, 0x22u, 0xabu, 0x5eu, 0x00u, 0x2bu, 0x06u, 0xdbu, 0x1fu, 0x22u, 0x13u, 0x40u, 0x1eu, 0x3au, 0x9au, 0x40u, 0x13u, 0x00u, 0x03u, 0x4au, 0x13u, 0x60u, 0x05u, 0xb0u, - 0xf0u, 0xbdu, 0xc0u, 0x46u, 0x10u, 0x06u, 0x00u, 0x08u, 0x00u, 0xe1u, 0x00u, 0xe0u, 0xf7u, 0xb5u, 0x2cu, 0x25u, + 0xf0u, 0xbdu, 0xc0u, 0x46u, 0x20u, 0x06u, 0x00u, 0x08u, 0x00u, 0xe1u, 0x00u, 0xe0u, 0xf7u, 0xb5u, 0x2cu, 0x25u, 0x13u, 0x4cu, 0x68u, 0x43u, 0x26u, 0x68u, 0x69u, 0x43u, 0x34u, 0x18u, 0x25u, 0x69u, 0x01u, 0x93u, 0x71u, 0x18u, 0x00u, 0x2du, 0x19u, 0xd0u, 0x88u, 0x69u, 0x00u, 0x28u, 0x18u, 0xd1u, 0x2eu, 0x68u, 0x00u, 0x2eu, 0x15u, 0xdau, 0x67u, 0x68u, 0x01u, 0x24u, 0x26u, 0x00u, 0x4bu, 0x68u, 0x9eu, 0x40u, 0xb4u, 0x46u, 0x13u, 0x68u, 0x9eu, 0xb2u, 0x63u, 0x46u, 0x1bu, 0x04u, 0x1eu, 0x43u, 0x16u, 0x60u, 0xeau, 0x60u, 0x8cu, 0x61u, 0xbcu, 0x40u, 0x01u, 0x9bu, 0xa4u, 0xb2u, 0x4bu, 0x62u, 0xacu, 0x60u, 0xfeu, 0xbdu, 0x02u, 0x48u, 0xfcu, 0xe7u, 0x02u, 0x48u, 0xfau, 0xe7u, - 0x28u, 0x04u, 0x00u, 0x08u, 0x04u, 0x02u, 0x8au, 0x00u, 0x07u, 0x02u, 0x8au, 0x00u, 0x2cu, 0x23u, 0x43u, 0x43u, + 0x38u, 0x04u, 0x00u, 0x08u, 0x04u, 0x02u, 0x8au, 0x00u, 0x07u, 0x02u, 0x8au, 0x00u, 0x2cu, 0x23u, 0x43u, 0x43u, 0x06u, 0x48u, 0x00u, 0x68u, 0xc0u, 0x18u, 0xc3u, 0x69u, 0x93u, 0x42u, 0x04u, 0xd9u, 0x03u, 0x6au, 0x00u, 0x20u, - 0x92u, 0x00u, 0xd1u, 0x50u, 0x70u, 0x47u, 0x02u, 0x48u, 0xfcu, 0xe7u, 0xc0u, 0x46u, 0x28u, 0x04u, 0x00u, 0x08u, + 0x92u, 0x00u, 0xd1u, 0x50u, 0x70u, 0x47u, 0x02u, 0x48u, 0xfcu, 0xe7u, 0xc0u, 0x46u, 0x38u, 0x04u, 0x00u, 0x08u, 0x0au, 0x02u, 0x8au, 0x00u, 0x73u, 0xb5u, 0x00u, 0x26u, 0x42u, 0x69u, 0x04u, 0x00u, 0xd5u, 0x68u, 0x01u, 0x96u, 0x2bu, 0x0cu, 0xb3u, 0x42u, 0x21u, 0xd0u, 0x1bu, 0x04u, 0x13u, 0x60u, 0x13u, 0x68u, 0x19u, 0x4bu, 0x00u, 0x69u, 0x1bu, 0x68u, 0xb0u, 0x33u, 0x1bu, 0x68u, 0xc3u, 0x18u, 0x1bu, 0x68u, 0xb3u, 0x42u, 0x15u, 0xdau, 0x01u, 0xa9u, @@ -112,34 +112,34 @@ const uint8_t cy_m0p_image[] = { 0x98u, 0x47u, 0x31u, 0x00u, 0x20u, 0x69u, 0xffu, 0xf7u, 0xf1u, 0xfeu, 0xadu, 0xb2u, 0x00u, 0x2du, 0x09u, 0xd0u, 0x63u, 0x69u, 0x1du, 0x60u, 0x00u, 0x25u, 0x1bu, 0x68u, 0x63u, 0x6au, 0xabu, 0x42u, 0x05u, 0xd0u, 0x98u, 0x47u, 0x65u, 0x62u, 0xa5u, 0x61u, 0x63u, 0x69u, 0x1bu, 0x68u, 0x73u, 0xbdu, 0xa3u, 0x6au, 0x00u, 0x2bu, 0xf8u, 0xd0u, - 0x98u, 0x47u, 0xf6u, 0xe7u, 0x10u, 0x06u, 0x00u, 0x08u, 0x2cu, 0x23u, 0x10u, 0xb5u, 0x43u, 0x43u, 0x03u, 0x4au, - 0x10u, 0x68u, 0xc0u, 0x18u, 0xffu, 0xf7u, 0xb6u, 0xffu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0x28u, 0x04u, 0x00u, 0x08u, + 0x98u, 0x47u, 0xf6u, 0xe7u, 0x20u, 0x06u, 0x00u, 0x08u, 0x2cu, 0x23u, 0x10u, 0xb5u, 0x43u, 0x43u, 0x03u, 0x4au, + 0x10u, 0x68u, 0xc0u, 0x18u, 0xffu, 0xf7u, 0xb6u, 0xffu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0x38u, 0x04u, 0x00u, 0x08u, 0xf8u, 0xb5u, 0x19u, 0x4bu, 0x0fu, 0x00u, 0x1bu, 0x68u, 0x1au, 0x00u, 0x2eu, 0x32u, 0x12u, 0x78u, 0x82u, 0x42u, 0x27u, 0xd9u, 0x00u, 0x29u, 0x25u, 0xd0u, 0x1fu, 0x25u, 0x0au, 0x68u, 0x15u, 0x40u, 0x21u, 0xd1u, 0x19u, 0x00u, 0xacu, 0x31u, 0x0cu, 0x88u, 0x11u, 0x4eu, 0x60u, 0x43u, 0x1cu, 0x6au, 0xd2u, 0x08u, 0x04u, 0x19u, 0x29u, 0x00u, - 0x78u, 0x68u, 0x34u, 0x60u, 0x00u, 0xf0u, 0x14u, 0xffu, 0x29u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xaeu, 0xfeu, + 0x78u, 0x68u, 0x34u, 0x60u, 0x00u, 0xf0u, 0x18u, 0xffu, 0x29u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xaeu, 0xfeu, 0x3au, 0x00u, 0x29u, 0x00u, 0x30u, 0x68u, 0xffu, 0xf7u, 0xbbu, 0xfeu, 0x04u, 0x1eu, 0x07u, 0xd1u, 0x01u, 0x00u, 0x30u, 0x68u, 0xffu, 0xf7u, 0xa3u, 0xfeu, 0x03u, 0x00u, 0x20u, 0x00u, 0x00u, 0x2bu, 0x00u, 0xd0u, 0x04u, 0x48u, - 0xf8u, 0xbdu, 0x04u, 0x48u, 0xfcu, 0xe7u, 0xc0u, 0x46u, 0x10u, 0x06u, 0x00u, 0x08u, 0x2cu, 0x04u, 0x00u, 0x08u, + 0xf8u, 0xbdu, 0x04u, 0x48u, 0xfcu, 0xe7u, 0xc0u, 0x46u, 0x20u, 0x06u, 0x00u, 0x08u, 0x3cu, 0x04u, 0x00u, 0x08u, 0x01u, 0x01u, 0x8au, 0x00u, 0x03u, 0x01u, 0x8au, 0x00u, 0x10u, 0xb5u, 0x00u, 0x2au, 0x0du, 0xd1u, 0x00u, 0x29u, 0x14u, 0xd1u, 0x0bu, 0x4bu, 0x1au, 0x68u, 0x13u, 0x00u, 0xacu, 0x33u, 0x1bu, 0x88u, 0x58u, 0x43u, 0x13u, 0x6au, 0xc0u, 0x18u, 0x08u, 0x4bu, 0x18u, 0x60u, 0x08u, 0x00u, 0x10u, 0xbdu, 0x00u, 0x29u, 0x06u, 0xd0u, 0x06u, 0x4bu, 0x19u, 0x60u, 0x19u, 0x00u, 0x5au, 0x60u, 0xffu, 0xf7u, 0xabu, 0xffu, 0xf5u, 0xe7u, 0x03u, 0x48u, 0xf3u, 0xe7u, - 0x10u, 0x06u, 0x00u, 0x08u, 0x2cu, 0x04u, 0x00u, 0x08u, 0xbcu, 0x03u, 0x00u, 0x08u, 0x03u, 0x01u, 0x8au, 0x00u, + 0x20u, 0x06u, 0x00u, 0x08u, 0x3cu, 0x04u, 0x00u, 0x08u, 0xccu, 0x03u, 0x00u, 0x08u, 0x03u, 0x01u, 0x8au, 0x00u, 0xf7u, 0xb5u, 0x18u, 0x4fu, 0x04u, 0x00u, 0x3bu, 0x68u, 0x01u, 0x91u, 0xdeu, 0x68u, 0x33u, 0x68u, 0x83u, 0x42u, 0x26u, 0xd9u, 0x00u, 0x25u, 0xa9u, 0x42u, 0x02u, 0xd1u, 0xffu, 0xf7u, 0x67u, 0xfdu, 0x05u, 0x00u, 0x38u, 0x68u, 0x03u, 0x68u, 0x00u, 0x2bu, 0x1au, 0xdau, 0x1fu, 0x22u, 0x01u, 0x23u, 0x22u, 0x40u, 0x93u, 0x40u, 0x64u, 0x09u, 0x72u, 0x68u, 0xa4u, 0x00u, 0x14u, 0x19u, 0x22u, 0x68u, 0x13u, 0x42u, 0x0du, 0xd0u, 0x9au, 0x43u, 0x22u, 0x60u, 0x00u, 0x24u, 0x00u, 0x21u, 0xffu, 0xf7u, 0x4au, 0xfeu, 0x01u, 0x9bu, 0x00u, 0x2bu, 0x02u, 0xd1u, 0x28u, 0x00u, 0xffu, 0xf7u, 0x4fu, 0xfdu, 0x20u, 0x00u, 0xfeu, 0xbdu, 0x03u, 0x4cu, 0xf2u, 0xe7u, 0x03u, 0x4cu, 0xf3u, 0xe7u, - 0x03u, 0x4cu, 0xf7u, 0xe7u, 0x2cu, 0x04u, 0x00u, 0x08u, 0x02u, 0x01u, 0x88u, 0x00u, 0x03u, 0x01u, 0x88u, 0x00u, + 0x03u, 0x4cu, 0xf7u, 0xe7u, 0x3cu, 0x04u, 0x00u, 0x08u, 0x02u, 0x01u, 0x88u, 0x00u, 0x03u, 0x01u, 0x88u, 0x00u, 0x04u, 0x01u, 0x8au, 0x00u, 0x0au, 0x4bu, 0x1bu, 0x68u, 0xdbu, 0x68u, 0x1au, 0x68u, 0x82u, 0x42u, 0x0du, 0xd9u, 0x59u, 0x68u, 0x1fu, 0x23u, 0x42u, 0x09u, 0x18u, 0x40u, 0x1eu, 0x3bu, 0x83u, 0x40u, 0x92u, 0x00u, 0x50u, 0x58u, 0x18u, 0x40u, 0x43u, 0x1eu, 0x98u, 0x41u, 0x03u, 0x4bu, 0xc0u, 0x18u, 0x70u, 0x47u, 0x02u, 0x48u, 0xfcu, 0xe7u, - 0x2cu, 0x04u, 0x00u, 0x08u, 0x00u, 0x01u, 0x88u, 0x00u, 0x04u, 0x01u, 0x8au, 0x00u, 0xa6u, 0x22u, 0x05u, 0x49u, + 0x3cu, 0x04u, 0x00u, 0x08u, 0x00u, 0x01u, 0x88u, 0x00u, 0x04u, 0x01u, 0x8au, 0x00u, 0xa6u, 0x22u, 0x05u, 0x49u, 0xd2u, 0x00u, 0x8bu, 0x58u, 0x02u, 0x20u, 0xdbu, 0x43u, 0x9bu, 0x07u, 0x02u, 0xd0u, 0x01u, 0x23u, 0x88u, 0x58u, 0x18u, 0x40u, 0x70u, 0x47u, 0x00u, 0x00u, 0x26u, 0x40u, 0x10u, 0xb5u, 0xffu, 0xf7u, 0xefu, 0xffu, 0x00u, 0x23u, - 0x02u, 0x28u, 0x01u, 0xd1u, 0x01u, 0x4bu, 0x1bu, 0x68u, 0x18u, 0x00u, 0x10u, 0xbdu, 0x30u, 0x04u, 0x00u, 0x08u, + 0x02u, 0x28u, 0x01u, 0xd1u, 0x01u, 0x4bu, 0x1bu, 0x68u, 0x18u, 0x00u, 0x10u, 0xbdu, 0x40u, 0x04u, 0x00u, 0x08u, 0x09u, 0x4au, 0x83u, 0x00u, 0x9bu, 0x18u, 0xd0u, 0x22u, 0x92u, 0x00u, 0x98u, 0x58u, 0x07u, 0x22u, 0x10u, 0x40u, 0x04u, 0x28u, 0x07u, 0xd1u, 0xc0u, 0x22u, 0x92u, 0x00u, 0x98u, 0x58u, 0x1fu, 0x23u, 0x03u, 0x40u, 0x80u, 0x20u, 0x40u, 0x00u, 0x18u, 0x43u, 0x70u, 0x47u, 0xc0u, 0x46u, 0x00u, 0x00u, 0x26u, 0x40u, 0x10u, 0xb5u, 0xffu, 0xf7u, @@ -149,8 +149,8 @@ const uint8_t cy_m0p_image[] = { 0xc0u, 0x0fu, 0xc0u, 0x03u, 0x00u, 0xe0u, 0x0cu, 0x48u, 0x10u, 0xbdu, 0x0cu, 0x4bu, 0x18u, 0x68u, 0xfbu, 0xe7u, 0x0bu, 0x4bu, 0xfbu, 0xe7u, 0x0bu, 0x4bu, 0x18u, 0x69u, 0x04u, 0x23u, 0x18u, 0x40u, 0xf4u, 0xd0u, 0x80u, 0x20u, 0x00u, 0x02u, 0xf1u, 0xe7u, 0x02u, 0x4au, 0x08u, 0x4bu, 0xe9u, 0xe7u, 0x00u, 0x20u, 0xecu, 0xe7u, 0xc0u, 0x46u, - 0x00u, 0x00u, 0x26u, 0x40u, 0x0cu, 0x05u, 0x00u, 0x00u, 0x00u, 0x12u, 0x7au, 0x00u, 0x34u, 0x04u, 0x00u, 0x08u, - 0x8cu, 0x04u, 0x00u, 0x08u, 0x00u, 0x00u, 0x27u, 0x40u, 0x3cu, 0x05u, 0x00u, 0x00u, 0xb0u, 0x23u, 0x15u, 0x4au, + 0x00u, 0x00u, 0x26u, 0x40u, 0x0cu, 0x05u, 0x00u, 0x00u, 0x00u, 0x12u, 0x7au, 0x00u, 0x44u, 0x04u, 0x00u, 0x08u, + 0x9cu, 0x04u, 0x00u, 0x08u, 0x00u, 0x00u, 0x27u, 0x40u, 0x3cu, 0x05u, 0x00u, 0x00u, 0xb0u, 0x23u, 0x15u, 0x4au, 0xdbu, 0x00u, 0xd3u, 0x58u, 0x10u, 0xb5u, 0x99u, 0x03u, 0xdbu, 0x01u, 0xdbu, 0x0fu, 0x89u, 0x0bu, 0xc3u, 0x71u, 0x11u, 0x4bu, 0x01u, 0x60u, 0xd3u, 0x58u, 0x0fu, 0x24u, 0xd9u, 0x04u, 0xdbu, 0x01u, 0xdbu, 0x0du, 0x03u, 0x81u, 0xb1u, 0x23u, 0xdbu, 0x00u, 0xd3u, 0x58u, 0xc9u, 0x0cu, 0x81u, 0x80u, 0x19u, 0x00u, 0x21u, 0x40u, 0x81u, 0x72u, @@ -161,259 +161,260 @@ const uint8_t cy_m0p_image[] = { 0x7fu, 0x22u, 0x1fu, 0x24u, 0x80u, 0x30u, 0xffu, 0x30u, 0x0bu, 0x4bu, 0x80u, 0x00u, 0xc3u, 0x58u, 0x1au, 0x40u, 0x0au, 0x70u, 0x1au, 0x0cu, 0x22u, 0x40u, 0x18u, 0x0au, 0x8au, 0x70u, 0x1au, 0x01u, 0x20u, 0x40u, 0xe2u, 0x40u, 0x48u, 0x70u, 0x00u, 0x20u, 0x9bu, 0x00u, 0x9bu, 0x0fu, 0xcau, 0x70u, 0x0bu, 0x71u, 0x10u, 0xbdu, 0x03u, 0x48u, - 0xfcu, 0xe7u, 0xc0u, 0x46u, 0x10u, 0x06u, 0x00u, 0x08u, 0x00u, 0x00u, 0x26u, 0x40u, 0x01u, 0x00u, 0x4au, 0x00u, - 0xf0u, 0xb5u, 0x87u, 0xb0u, 0x04u, 0x00u, 0xffu, 0xf7u, 0x61u, 0xffu, 0x06u, 0x00u, 0x00u, 0x2cu, 0x34u, 0xd1u, - 0x01u, 0xadu, 0x14u, 0x22u, 0x21u, 0x00u, 0x28u, 0x00u, 0x00u, 0xf0u, 0xa2u, 0xfdu, 0x28u, 0x00u, 0xffu, 0xf7u, - 0x95u, 0xffu, 0xb0u, 0x23u, 0x25u, 0x4au, 0xdbu, 0x00u, 0xd3u, 0x58u, 0x00u, 0x2bu, 0x03u, 0xdau, 0xacu, 0x7bu, + 0xfcu, 0xe7u, 0xc0u, 0x46u, 0x20u, 0x06u, 0x00u, 0x08u, 0x00u, 0x00u, 0x26u, 0x40u, 0x01u, 0x00u, 0x4au, 0x00u, + 0xf0u, 0xb5u, 0x87u, 0xb0u, 0x04u, 0x00u, 0xffu, 0xf7u, 0x61u, 0xffu, 0x06u, 0x00u, 0x00u, 0x2cu, 0x38u, 0xd1u, + 0x01u, 0xadu, 0x14u, 0x22u, 0x21u, 0x00u, 0x28u, 0x00u, 0x00u, 0xf0u, 0xa6u, 0xfdu, 0x28u, 0x00u, 0xffu, 0xf7u, + 0x95u, 0xffu, 0xb0u, 0x23u, 0x27u, 0x4au, 0xdbu, 0x00u, 0xd3u, 0x58u, 0x00u, 0x2bu, 0x03u, 0xdau, 0xacu, 0x7bu, 0x02u, 0x3cu, 0x63u, 0x1eu, 0x9cu, 0x41u, 0xeau, 0x79u, 0x01u, 0x9fu, 0x53u, 0x1eu, 0x9au, 0x41u, 0xa8u, 0x88u, - 0x01u, 0x32u, 0x00u, 0x2cu, 0x16u, 0xd0u, 0x00u, 0x23u, 0x19u, 0x00u, 0x00u, 0xf0u, 0x73u, 0xfcu, 0x00u, 0x23u, - 0x0cu, 0x00u, 0x05u, 0x00u, 0x3au, 0x00u, 0x30u, 0x00u, 0x19u, 0x00u, 0x00u, 0xf0u, 0x6bu, 0xfcu, 0xe6u, 0x07u, - 0x6au, 0x08u, 0x32u, 0x43u, 0x63u, 0x08u, 0x80u, 0x18u, 0x59u, 0x41u, 0x2au, 0x00u, 0x23u, 0x00u, 0x00u, 0xf0u, - 0x41u, 0xfcu, 0x06u, 0x00u, 0x30u, 0x00u, 0x07u, 0xb0u, 0xf0u, 0xbdu, 0x11u, 0x4bu, 0x1bu, 0x68u, 0x3bu, 0x33u, - 0x1bu, 0x78u, 0xa3u, 0x42u, 0xf6u, 0xd3u, 0x01u, 0xadu, 0x05u, 0x22u, 0x00u, 0x21u, 0x28u, 0x00u, 0x00u, 0xf0u, - 0x67u, 0xfdu, 0x20u, 0x00u, 0x29u, 0x00u, 0x80u, 0x34u, 0xffu, 0xf7u, 0x8au, 0xffu, 0xffu, 0x34u, 0x07u, 0x4bu, - 0xa4u, 0x00u, 0xe3u, 0x58u, 0x00u, 0x24u, 0xa3u, 0x42u, 0x03u, 0xdau, 0x2cu, 0x79u, 0x02u, 0x3cu, 0x63u, 0x1eu, - 0x9cu, 0x41u, 0x2fu, 0x78u, 0x68u, 0x78u, 0xaau, 0x78u, 0xc3u, 0xe7u, 0xc0u, 0x46u, 0x00u, 0x00u, 0x26u, 0x40u, - 0x10u, 0x06u, 0x00u, 0x08u, 0xe0u, 0x22u, 0x10u, 0xb5u, 0x01u, 0x24u, 0x09u, 0x4bu, 0x80u, 0x00u, 0x92u, 0x00u, - 0xc0u, 0x18u, 0x83u, 0x58u, 0x80u, 0x58u, 0x9bu, 0x06u, 0x9bu, 0x0fu, 0x9cu, 0x40u, 0x0fu, 0x23u, 0x18u, 0x40u, - 0xffu, 0xf7u, 0x8eu, 0xffu, 0x63u, 0x08u, 0x18u, 0x18u, 0x21u, 0x00u, 0x00u, 0xf0u, 0x77u, 0xfbu, 0x10u, 0xbdu, - 0x00u, 0x00u, 0x26u, 0x40u, 0x14u, 0x4bu, 0x30u, 0xb5u, 0x1au, 0x68u, 0x07u, 0x24u, 0x13u, 0x00u, 0x28u, 0x33u, - 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x15u, 0xd8u, 0x83u, 0x08u, 0x1du, 0x00u, 0xa5u, 0x43u, 0x2cu, 0x1eu, 0x0fu, 0xd1u, - 0x03u, 0x34u, 0x20u, 0x40u, 0xa0u, 0x40u, 0x81u, 0x40u, 0x12u, 0x68u, 0x9bu, 0x00u, 0x20u, 0x32u, 0xd3u, 0x18u, - 0x0au, 0x00u, 0xffu, 0x21u, 0x81u, 0x40u, 0x1cu, 0x68u, 0x62u, 0x40u, 0x11u, 0x40u, 0x61u, 0x40u, 0x19u, 0x60u, - 0x30u, 0xbdu, 0x80u, 0x23u, 0x20u, 0x40u, 0x1bu, 0x06u, 0x18u, 0x43u, 0x80u, 0x23u, 0x9bu, 0x01u, 0x12u, 0x68u, - 0xc9u, 0x18u, 0x89u, 0x00u, 0x88u, 0x50u, 0xf3u, 0xe7u, 0x10u, 0x06u, 0x00u, 0x08u, 0x06u, 0x4bu, 0x9au, 0x68u, - 0x03u, 0x00u, 0x06u, 0x48u, 0x10u, 0x33u, 0x9bu, 0x00u, 0x82u, 0x42u, 0x02u, 0xd1u, 0x98u, 0x58u, 0x99u, 0x50u, - 0x70u, 0x47u, 0x03u, 0x4au, 0xd0u, 0x58u, 0xfbu, 0xe7u, 0x00u, 0xedu, 0x00u, 0xe0u, 0x00u, 0x00u, 0x00u, 0x08u, - 0x00u, 0x00u, 0x00u, 0x10u, 0xf8u, 0xb5u, 0x06u, 0x00u, 0x0du, 0x00u, 0x00u, 0x28u, 0x3au, 0xd0u, 0x00u, 0x23u, - 0xc0u, 0x5eu, 0x00u, 0x28u, 0x28u, 0xdbu, 0xb1u, 0x78u, 0xffu, 0xf7u, 0xb4u, 0xffu, 0x00u, 0x24u, 0xffu, 0x22u, - 0x03u, 0x27u, 0x94u, 0x46u, 0x00u, 0x23u, 0xf0u, 0x5eu, 0x71u, 0x68u, 0x83u, 0xb2u, 0x1fu, 0x40u, 0xffu, 0x00u, - 0x66u, 0x46u, 0xbau, 0x40u, 0x89u, 0x01u, 0x31u, 0x40u, 0xd2u, 0x43u, 0xb9u, 0x40u, 0x00u, 0x28u, 0x15u, 0xdbu, - 0x11u, 0x4eu, 0x83u, 0x08u, 0x9bu, 0x00u, 0x9bu, 0x19u, 0xc0u, 0x26u, 0xb6u, 0x00u, 0x9fu, 0x59u, 0x3au, 0x40u, - 0x11u, 0x43u, 0x99u, 0x51u, 0x0du, 0x4bu, 0x9au, 0x68u, 0x0du, 0x4bu, 0x9au, 0x42u, 0x02u, 0xd1u, 0x29u, 0x00u, - 0xffu, 0xf7u, 0xbcu, 0xffu, 0x20u, 0x00u, 0xf8u, 0xbdu, 0x0au, 0x4cu, 0xd8u, 0xe7u, 0x0fu, 0x26u, 0x33u, 0x40u, - 0x08u, 0x3bu, 0x06u, 0x4eu, 0x9bu, 0x08u, 0x9bu, 0x00u, 0x9bu, 0x19u, 0xdeu, 0x69u, 0x32u, 0x40u, 0x11u, 0x43u, - 0xd9u, 0x61u, 0xe7u, 0xe7u, 0x03u, 0x4cu, 0xedu, 0xe7u, 0x00u, 0xe1u, 0x00u, 0xe0u, 0x00u, 0xedu, 0x00u, 0xe0u, - 0x00u, 0x00u, 0x00u, 0x08u, 0x01u, 0x00u, 0x56u, 0x00u, 0xfeu, 0xe7u, 0x00u, 0x00u, 0x02u, 0x68u, 0x0au, 0x4bu, - 0x10u, 0xb5u, 0x1au, 0x60u, 0x42u, 0x68u, 0x5au, 0x60u, 0x82u, 0x68u, 0x9au, 0x60u, 0xc2u, 0x68u, 0xdau, 0x60u, - 0x02u, 0x69u, 0x1au, 0x61u, 0x42u, 0x69u, 0x5au, 0x61u, 0x82u, 0x69u, 0x9au, 0x61u, 0xc2u, 0x69u, 0xdau, 0x61u, - 0xffu, 0xf7u, 0xeau, 0xffu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0xd8u, 0x03u, 0x00u, 0x08u, 0xb0u, 0x23u, 0x5bu, 0x05u, - 0x9au, 0x89u, 0x00u, 0x2au, 0x02u, 0xd0u, 0x98u, 0x89u, 0x80u, 0xb2u, 0x70u, 0x47u, 0x80u, 0x20u, 0x40u, 0x00u, - 0xfbu, 0xe7u, 0x00u, 0x00u, 0x7fu, 0xb5u, 0x27u, 0x4bu, 0x86u, 0x00u, 0x0du, 0x00u, 0xf4u, 0x58u, 0x04u, 0x29u, - 0x01u, 0xd0u, 0x01u, 0x29u, 0x27u, 0xd1u, 0x00u, 0x20u, 0x0fu, 0xe0u, 0xa3u, 0x68u, 0x2bu, 0x42u, 0x0bu, 0xd1u, - 0xe3u, 0x68u, 0x29u, 0x00u, 0x1au, 0x68u, 0x5bu, 0x68u, 0x02u, 0x92u, 0x01u, 0x93u, 0x03u, 0x93u, 0x02u, 0xa8u, - 0x23u, 0x68u, 0x98u, 0x47u, 0x1cu, 0x4bu, 0x1cu, 0x60u, 0x64u, 0x69u, 0x00u, 0x2cu, 0x0bu, 0xd0u, 0x1bu, 0x4bu, - 0x98u, 0x42u, 0xeau, 0xd1u, 0x01u, 0x2du, 0xe8u, 0xd1u, 0x17u, 0x4bu, 0x18u, 0x48u, 0x1au, 0x68u, 0x18u, 0x4bu, - 0x9au, 0x51u, 0x04u, 0xb0u, 0x70u, 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0x00u, 0x20u, 0xd0u, 0x10u, 0x4bu, 0x07u, 0x22u, + 0x1cu, 0x68u, 0x23u, 0x00u, 0xacu, 0x33u, 0x1bu, 0x88u, 0x5au, 0x43u, 0x23u, 0x6au, 0xd3u, 0x18u, 0x19u, 0x68u, + 0x00u, 0x29u, 0xfcu, 0xdau, 0x3eu, 0x21u, 0x0bu, 0x4bu, 0x06u, 0x25u, 0x19u, 0x60u, 0x0au, 0x4bu, 0x0bu, 0x49u, + 0x19u, 0x60u, 0xa3u, 0x21u, 0x0au, 0x4bu, 0xc9u, 0x00u, 0x5du, 0x50u, 0x0au, 0x49u, 0x58u, 0x50u, 0x58u, 0x58u, + 0x20u, 0x6au, 0x12u, 0x18u, 0x00u, 0x20u, 0x50u, 0x60u, 0x5au, 0x58u, 0x00u, 0x2au, 0xfcu, 0xdau, 0x30u, 0xbdu, + 0x20u, 0x06u, 0x00u, 0x08u, 0x04u, 0x01u, 0x26u, 0x40u, 0x08u, 0x01u, 0x26u, 0x40u, 0x1eu, 0x1fu, 0x00u, 0x00u, + 0x00u, 0x00u, 0x26u, 0x40u, 0x1cu, 0x05u, 0x00u, 0x00u, 0x10u, 0xb5u, 0x43u, 0x78u, 0xffu, 0x2bu, 0x11u, 0xd1u, + 0x00u, 0xf0u, 0x14u, 0xf9u, 0x04u, 0x00u, 0x03u, 0x20u, 0x00u, 0xf0u, 0xf0u, 0xf8u, 0xc3u, 0x68u, 0x5au, 0x68u, + 0x01u, 0x23u, 0x11u, 0x68u, 0x19u, 0x43u, 0x11u, 0x60u, 0x11u, 0x68u, 0x19u, 0x42u, 0xfcu, 0xd1u, 0x20u, 0x00u, + 0x00u, 0xf0u, 0x14u, 0xf9u, 0x10u, 0xbdu, 0xf7u, 0xb5u, 0x00u, 0x90u, 0x00u, 0x20u, 0x01u, 0x91u, 0x00u, 0xf0u, + 0xddu, 0xf8u, 0x3fu, 0x4du, 0x06u, 0x00u, 0x2bu, 0x68u, 0x1au, 0x00u, 0x4cu, 0x33u, 0xb0u, 0x32u, 0x14u, 0x68u, + 0x1bu, 0x78u, 0x04u, 0x19u, 0x00u, 0x2bu, 0x5au, 0xd0u, 0x00u, 0xf0u, 0xd8u, 0xf8u, 0x07u, 0x00u, 0x03u, 0x28u, + 0x1bu, 0xd0u, 0x00u, 0xf0u, 0xebu, 0xf8u, 0x37u, 0x4au, 0x37u, 0x4bu, 0x05u, 0x00u, 0xd3u, 0x58u, 0x00u, 0x2bu, + 0x3eu, 0xdau, 0x36u, 0x4au, 0x01u, 0x21u, 0x30u, 0x00u, 0x00u, 0xf0u, 0xf8u, 0xf8u, 0x00u, 0x28u, 0x37u, 0xd1u, + 0x01u, 0x98u, 0xffu, 0xf7u, 0x8fu, 0xffu, 0x00u, 0x9bu, 0x00u, 0x2bu, 0x3eu, 0xd0u, 0x23u, 0x68u, 0x00u, 0x2bu, + 0xfcu, 0xdbu, 0x00u, 0xf0u, 0xc3u, 0xf8u, 0x04u, 0x00u, 0x2bu, 0xe0u, 0x06u, 0x20u, 0x00u, 0xf0u, 0xaeu, 0xf8u, + 0x2bu, 0x68u, 0xb0u, 0x33u, 0x1bu, 0x68u, 0xc0u, 0x18u, 0x03u, 0x68u, 0x00u, 0x2bu, 0x02u, 0xdau, 0x28u, 0x4cu, + 0x20u, 0x00u, 0xfeu, 0xbdu, 0x00u, 0x20u, 0x00u, 0xf0u, 0xc9u, 0xf8u, 0x26u, 0x4bu, 0x98u, 0x42u, 0xf6u, 0xd0u, + 0x00u, 0x23u, 0x25u, 0x4au, 0x19u, 0x00u, 0x12u, 0x68u, 0x01u, 0x20u, 0x00u, 0xf0u, 0x8fu, 0xf8u, 0x00u, 0x25u, + 0xa8u, 0x42u, 0xecu, 0xd1u, 0x00u, 0x20u, 0x00u, 0xf0u, 0xb9u, 0xf8u, 0x1eu, 0x4au, 0x1fu, 0x4bu, 0x90u, 0x42u, + 0x03u, 0xd0u, 0x9du, 0x42u, 0xe3u, 0xd0u, 0x01u, 0x35u, 0xf4u, 0xe7u, 0x9du, 0x42u, 0xb9u, 0xd1u, 0xdeu, 0xe7u, + 0x17u, 0x4cu, 0x03u, 0x2fu, 0x05u, 0xd1u, 0x01u, 0x21u, 0x00u, 0x20u, 0x00u, 0xf0u, 0x97u, 0xf8u, 0x00u, 0x28u, + 0xf9u, 0xd1u, 0x28u, 0x00u, 0x00u, 0xf0u, 0xaau, 0xf8u, 0xd2u, 0xe7u, 0x15u, 0x4cu, 0xf1u, 0xe7u, 0x00u, 0xf0u, + 0x95u, 0xf8u, 0x0eu, 0x4au, 0x05u, 0x00u, 0x01u, 0x21u, 0x30u, 0x00u, 0x00u, 0xf0u, 0xa7u, 0xf8u, 0x00u, 0x28u, + 0x09u, 0xd1u, 0x00u, 0x9bu, 0x00u, 0x2bu, 0x08u, 0xd0u, 0x23u, 0x68u, 0x00u, 0x2bu, 0xfcu, 0xdbu, 0x00u, 0xf0u, + 0x75u, 0xf8u, 0x04u, 0x00u, 0xe5u, 0xe7u, 0x06u, 0x4cu, 0xe3u, 0xe7u, 0x09u, 0x4cu, 0xe1u, 0xe7u, 0xc0u, 0x46u, + 0x20u, 0x06u, 0x00u, 0x08u, 0x00u, 0x00u, 0x26u, 0x40u, 0x1cu, 0x05u, 0x00u, 0x00u, 0x24u, 0x04u, 0x00u, 0x08u, + 0x05u, 0x00u, 0x52u, 0x00u, 0x01u, 0x01u, 0x88u, 0x00u, 0x34u, 0x04u, 0x00u, 0x08u, 0xf0u, 0x49u, 0x02u, 0x00u, + 0x01u, 0x00u, 0x50u, 0x00u, 0x18u, 0x4bu, 0xf7u, 0xb5u, 0x1bu, 0x68u, 0x18u, 0x4au, 0x5cu, 0x68u, 0x04u, 0x23u, + 0x11u, 0x69u, 0x0bu, 0x43u, 0x13u, 0x61u, 0x01u, 0x28u, 0x24u, 0xd0u, 0x30u, 0xbfu, 0x23u, 0x00u, 0xfcu, 0x33u, + 0x1bu, 0x69u, 0x00u, 0x2bu, 0x1du, 0xd1u, 0xa3u, 0x20u, 0x11u, 0x4bu, 0x12u, 0x49u, 0x12u, 0x4au, 0xc0u, 0x00u, + 0x0fu, 0x68u, 0x1eu, 0x58u, 0x15u, 0x68u, 0x01u, 0x95u, 0x10u, 0x4du, 0x0du, 0x60u, 0x06u, 0x25u, 0x1du, 0x50u, + 0x3eu, 0x20u, 0x10u, 0x60u, 0x0eu, 0x48u, 0x3eu, 0x35u, 0x1du, 0x50u, 0x1du, 0x58u, 0x00u, 0x2du, 0xfcu, 0xdau, + 0x0cu, 0x48u, 0xfcu, 0x34u, 0x20u, 0x61u, 0x0fu, 0x60u, 0xa3u, 0x21u, 0xc9u, 0x00u, 0x5eu, 0x50u, 0x01u, 0x9bu, + 0x13u, 0x60u, 0xf7u, 0xbdu, 0x20u, 0xbfu, 0xd9u, 0xe7u, 0x20u, 0x06u, 0x00u, 0x08u, 0x00u, 0xedu, 0x00u, 0xe0u, + 0x00u, 0x00u, 0x26u, 0x40u, 0x08u, 0x01u, 0x26u, 0x40u, 0x04u, 0x01u, 0x26u, 0x40u, 0x1eu, 0x1fu, 0x00u, 0x00u, + 0x1cu, 0x05u, 0x00u, 0x00u, 0xaau, 0xaau, 0xaau, 0xaau, 0x00u, 0x00u, 0x00u, 0x00u, 0x01u, 0xb4u, 0x02u, 0x48u, + 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, 0x4du, 0x04u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, + 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, 0xb5u, 0x01u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, + 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, 0xbdu, 0x0fu, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, + 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, 0x79u, 0x02u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, + 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, 0x31u, 0x06u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, + 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, 0x1bu, 0x01u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, + 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, 0xa5u, 0x06u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, + 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, 0x23u, 0x01u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, + 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, 0x31u, 0x03u, 0x00u, 0x10u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, }; #endif /* defined(CY_DEVICE_PSOC6ABLE2) */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/COMPONENT_CM0P_SLEEP/psoc6_02_cm0p_sleep.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/COMPONENT_CM0P_SLEEP/psoc6_02_cm0p_sleep.c index 5ab97070c6..f3c7422d02 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/COMPONENT_CM0P_SLEEP/psoc6_02_cm0p_sleep.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/COMPONENT_CM0P_SLEEP/psoc6_02_cm0p_sleep.c @@ -36,22 +36,22 @@ const uint8_t cy_m0p_image[] = { 0x49u, 0x01u, 0x00u, 0x10u, 0x49u, 0x01u, 0x00u, 0x10u, 0x49u, 0x01u, 0x00u, 0x10u, 0x49u, 0x01u, 0x00u, 0x10u, 0x49u, 0x01u, 0x00u, 0x10u, 0x49u, 0x01u, 0x00u, 0x10u, 0x49u, 0x01u, 0x00u, 0x10u, 0x49u, 0x01u, 0x00u, 0x10u, 0x10u, 0xb5u, 0x06u, 0x4cu, 0x23u, 0x78u, 0x00u, 0x2bu, 0x07u, 0xd1u, 0x05u, 0x4bu, 0x00u, 0x2bu, 0x02u, 0xd0u, - 0x04u, 0x48u, 0x00u, 0xe0u, 0x00u, 0xbfu, 0x01u, 0x23u, 0x23u, 0x70u, 0x10u, 0xbdu, 0xb0u, 0x03u, 0x00u, 0x08u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x18u, 0x14u, 0x00u, 0x10u, 0x04u, 0x4bu, 0x10u, 0xb5u, 0x00u, 0x2bu, 0x03u, 0xd0u, + 0x04u, 0x48u, 0x00u, 0xe0u, 0x00u, 0xbfu, 0x01u, 0x23u, 0x23u, 0x70u, 0x10u, 0xbdu, 0xc0u, 0x03u, 0x00u, 0x08u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x20u, 0x14u, 0x00u, 0x10u, 0x04u, 0x4bu, 0x10u, 0xb5u, 0x00u, 0x2bu, 0x03u, 0xd0u, 0x03u, 0x49u, 0x04u, 0x48u, 0x00u, 0xe0u, 0x00u, 0xbfu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0x00u, 0x00u, 0x00u, 0x00u, - 0xb4u, 0x03u, 0x00u, 0x08u, 0x18u, 0x14u, 0x00u, 0x10u, 0x02u, 0x30u, 0x80u, 0x08u, 0x03u, 0xd0u, 0x01u, 0x30u, + 0xc4u, 0x03u, 0x00u, 0x08u, 0x20u, 0x14u, 0x00u, 0x10u, 0x02u, 0x30u, 0x80u, 0x08u, 0x03u, 0xd0u, 0x01u, 0x30u, 0x02u, 0x38u, 0xfcu, 0xd1u, 0xc0u, 0x46u, 0xc0u, 0x46u, 0x70u, 0x47u, 0xefu, 0xf3u, 0x10u, 0x80u, 0x72u, 0xb6u, 0x70u, 0x47u, 0x80u, 0xf3u, 0x10u, 0x88u, 0x70u, 0x47u, 0x70u, 0x47u, 0xffu, 0xf7u, 0xfdu, 0xffu, 0x72u, 0xb6u, 0x0fu, 0x4cu, 0x10u, 0x4du, 0xacu, 0x42u, 0x09u, 0xdau, 0x21u, 0x68u, 0x62u, 0x68u, 0xa3u, 0x68u, 0x04u, 0x3bu, 0x02u, 0xdbu, 0xc8u, 0x58u, 0xd0u, 0x50u, 0xfau, 0xe7u, 0x0cu, 0x34u, 0xf3u, 0xe7u, 0x0au, 0x49u, 0x0bu, 0x4au, 0x00u, 0x20u, 0x52u, 0x1au, 0x02u, 0xddu, 0x04u, 0x3au, 0x88u, 0x50u, 0xfcu, 0xdcu, 0x08u, 0x48u, 0x09u, 0x49u, - 0x08u, 0x60u, 0xbfu, 0xf3u, 0x4fu, 0x8fu, 0x00u, 0xf0u, 0x85u, 0xfeu, 0x00u, 0xf0u, 0x2fu, 0xfeu, 0xfeu, 0xe7u, - 0x24u, 0x14u, 0x00u, 0x10u, 0x3cu, 0x14u, 0x00u, 0x10u, 0xb0u, 0x03u, 0x00u, 0x08u, 0xc8u, 0x05u, 0x00u, 0x08u, + 0x08u, 0x60u, 0xbfu, 0xf3u, 0x4fu, 0x8fu, 0x00u, 0xf0u, 0x89u, 0xfeu, 0x00u, 0xf0u, 0x33u, 0xfeu, 0xfeu, 0xe7u, + 0x2cu, 0x14u, 0x00u, 0x10u, 0x44u, 0x14u, 0x00u, 0x10u, 0xc0u, 0x03u, 0x00u, 0x08u, 0xd8u, 0x05u, 0x00u, 0x08u, 0x00u, 0x00u, 0x00u, 0x08u, 0x08u, 0xedu, 0x00u, 0xe0u, 0xfeu, 0xe7u, 0xfeu, 0xe7u, 0x00u, 0xb5u, 0x04u, 0x20u, 0x71u, 0x46u, 0x08u, 0x42u, 0x02u, 0xd0u, 0xefu, 0xf3u, 0x09u, 0x80u, 0x01u, 0xe0u, 0xefu, 0xf3u, 0x08u, 0x80u, - 0x04u, 0x30u, 0x00u, 0xf0u, 0x21u, 0xfcu, 0xfeu, 0xe7u, 0x01u, 0x4bu, 0x18u, 0x60u, 0x70u, 0x47u, 0xc0u, 0x46u, - 0xc4u, 0x05u, 0x00u, 0x08u, 0x04u, 0x4bu, 0x1bu, 0x68u, 0x1au, 0x00u, 0xacu, 0x32u, 0x12u, 0x88u, 0x1bu, 0x6au, - 0x50u, 0x43u, 0xc0u, 0x18u, 0x70u, 0x47u, 0xc0u, 0x46u, 0xc4u, 0x05u, 0x00u, 0x08u, 0x1du, 0x4bu, 0x98u, 0x42u, + 0x04u, 0x30u, 0x00u, 0xf0u, 0x25u, 0xfcu, 0xfeu, 0xe7u, 0x01u, 0x4bu, 0x18u, 0x60u, 0x70u, 0x47u, 0xc0u, 0x46u, + 0xd4u, 0x05u, 0x00u, 0x08u, 0x04u, 0x4bu, 0x1bu, 0x68u, 0x1au, 0x00u, 0xacu, 0x32u, 0x12u, 0x88u, 0x1bu, 0x6au, + 0x50u, 0x43u, 0xc0u, 0x18u, 0x70u, 0x47u, 0xc0u, 0x46u, 0xd4u, 0x05u, 0x00u, 0x08u, 0x1du, 0x4bu, 0x98u, 0x42u, 0x0fu, 0xd0u, 0x10u, 0xd8u, 0x40u, 0x28u, 0x2fu, 0xd0u, 0x05u, 0xd8u, 0x00u, 0x28u, 0x30u, 0xd0u, 0x10u, 0x28u, 0x28u, 0xd0u, 0x19u, 0x48u, 0x1eu, 0xe0u, 0x80u, 0x28u, 0x28u, 0xd0u, 0x80u, 0x23u, 0x5bu, 0x00u, 0x98u, 0x42u, 0xf7u, 0xd1u, 0x14u, 0x48u, 0x16u, 0xe0u, 0x15u, 0x4bu, 0x98u, 0x42u, 0x14u, 0xd0u, 0x08u, 0xd8u, 0xa0u, 0x23u, @@ -65,32 +65,32 @@ const uint8_t cy_m0p_image[] = { 0x02u, 0x00u, 0x50u, 0x00u, 0x05u, 0x00u, 0x52u, 0x00u, 0x10u, 0xb5u, 0x00u, 0x20u, 0xffu, 0xf7u, 0x9au, 0xffu, 0x0au, 0x4bu, 0x1cu, 0x68u, 0x23u, 0x00u, 0xb0u, 0x33u, 0x1bu, 0x68u, 0xc0u, 0x18u, 0x03u, 0x68u, 0x00u, 0x2bu, 0x0au, 0xdbu, 0x07u, 0x4bu, 0x18u, 0x68u, 0xffu, 0xf7u, 0x99u, 0xffu, 0x01u, 0x22u, 0x63u, 0x68u, 0x9au, 0x60u, - 0x9au, 0x68u, 0x00u, 0x2au, 0xfcu, 0xd1u, 0x10u, 0xbdu, 0x02u, 0x48u, 0xfcu, 0xe7u, 0xc4u, 0x05u, 0x00u, 0x08u, - 0xccu, 0x03u, 0x00u, 0x08u, 0x02u, 0x00u, 0x50u, 0x00u, 0x06u, 0x4bu, 0x1bu, 0x68u, 0xb0u, 0x33u, 0x1bu, 0x68u, + 0x9au, 0x68u, 0x00u, 0x2au, 0xfcu, 0xd1u, 0x10u, 0xbdu, 0x02u, 0x48u, 0xfcu, 0xe7u, 0xd4u, 0x05u, 0x00u, 0x08u, + 0xdcu, 0x03u, 0x00u, 0x08u, 0x02u, 0x00u, 0x50u, 0x00u, 0x06u, 0x4bu, 0x1bu, 0x68u, 0xb0u, 0x33u, 0x1bu, 0x68u, 0xc3u, 0x18u, 0x1bu, 0x68u, 0x00u, 0x2bu, 0x03u, 0xdau, 0x89u, 0xb2u, 0x41u, 0x60u, 0x00u, 0x20u, 0x70u, 0x47u, - 0x01u, 0x48u, 0xfcu, 0xe7u, 0xc4u, 0x05u, 0x00u, 0x08u, 0x01u, 0x00u, 0x8au, 0x00u, 0x03u, 0x68u, 0x00u, 0x2bu, + 0x01u, 0x48u, 0xfcu, 0xe7u, 0xd4u, 0x05u, 0x00u, 0x08u, 0x01u, 0x00u, 0x8au, 0x00u, 0x03u, 0x68u, 0x00u, 0x2bu, 0x04u, 0xdau, 0x89u, 0xb2u, 0xc2u, 0x60u, 0x81u, 0x60u, 0x00u, 0x20u, 0x70u, 0x47u, 0x00u, 0x48u, 0xfcu, 0xe7u, 0x01u, 0x00u, 0x8au, 0x00u, 0x06u, 0x4bu, 0x1bu, 0x68u, 0xb0u, 0x33u, 0x1bu, 0x68u, 0xc3u, 0x18u, 0x1bu, 0x68u, 0x00u, 0x2bu, 0x03u, 0xdau, 0xc3u, 0x68u, 0x00u, 0x20u, 0x0bu, 0x60u, 0x70u, 0x47u, 0x01u, 0x48u, 0xfcu, 0xe7u, - 0xc4u, 0x05u, 0x00u, 0x08u, 0x01u, 0x00u, 0x8au, 0x00u, 0x02u, 0x4bu, 0x1au, 0x68u, 0x00u, 0x2au, 0x00u, 0xd1u, - 0x18u, 0x60u, 0x70u, 0x47u, 0xe0u, 0x03u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x2cu, 0x24u, 0x60u, 0x43u, 0x12u, 0x4cu, + 0xd4u, 0x05u, 0x00u, 0x08u, 0x01u, 0x00u, 0x8au, 0x00u, 0x02u, 0x4bu, 0x1au, 0x68u, 0x00u, 0x2au, 0x00u, 0xd1u, + 0x18u, 0x60u, 0x70u, 0x47u, 0xf0u, 0x03u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x2cu, 0x24u, 0x60u, 0x43u, 0x12u, 0x4cu, 0x1fu, 0x00u, 0x24u, 0x68u, 0x1eu, 0x0au, 0x20u, 0x18u, 0xffu, 0x24u, 0x27u, 0x40u, 0x34u, 0x40u, 0x0fu, 0x4eu, 0x1bu, 0x0cu, 0x35u, 0x68u, 0x07u, 0x60u, 0x2eu, 0x6au, 0x44u, 0x60u, 0x83u, 0x60u, 0xacu, 0x35u, 0x2du, 0x88u, 0x80u, 0x34u, 0x6fu, 0x43u, 0x64u, 0x01u, 0x34u, 0x19u, 0xbfu, 0x19u, 0x1eu, 0x04u, 0x33u, 0x43u, 0x07u, 0x61u, 0x44u, 0x61u, 0xa3u, 0x60u, 0x00u, 0x23u, 0x83u, 0x61u, 0x05u, 0x9bu, 0xc2u, 0x61u, 0x01u, 0x62u, 0x00u, 0x2bu, - 0x01u, 0xd0u, 0x1bu, 0x88u, 0x83u, 0x81u, 0xf0u, 0xbdu, 0xe0u, 0x03u, 0x00u, 0x08u, 0xc4u, 0x05u, 0x00u, 0x08u, + 0x01u, 0xd0u, 0x1bu, 0x88u, 0x83u, 0x81u, 0xf0u, 0xbdu, 0xf0u, 0x03u, 0x00u, 0x08u, 0xd4u, 0x05u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x83u, 0x68u, 0x85u, 0xb0u, 0x02u, 0xadu, 0x2bu, 0x80u, 0x15u, 0x4bu, 0x02u, 0x68u, 0x1bu, 0x68u, 0x06u, 0x6au, 0x9bu, 0x8eu, 0x47u, 0x6au, 0x9bu, 0x18u, 0x6bu, 0x80u, 0x43u, 0x68u, 0x00u, 0x95u, 0x82u, 0x6au, 0xc1u, 0x6au, 0x04u, 0x00u, 0x03u, 0x93u, 0x03u, 0x69u, 0xc0u, 0x68u, 0xffu, 0xf7u, 0xbdu, 0xffu, 0x00u, 0x21u, 0x3bu, 0x00u, 0x0au, 0x00u, 0x00u, 0x91u, 0x30u, 0x00u, 0xffu, 0xf7u, 0xb6u, 0xffu, 0x21u, 0x6bu, 0x28u, 0x00u, - 0x00u, 0xf0u, 0xc6u, 0xfau, 0x00u, 0x22u, 0xabu, 0x5eu, 0x00u, 0x2bu, 0x06u, 0xdbu, 0x1fu, 0x22u, 0x13u, 0x40u, + 0x00u, 0xf0u, 0xcau, 0xfau, 0x00u, 0x22u, 0xabu, 0x5eu, 0x00u, 0x2bu, 0x06u, 0xdbu, 0x1fu, 0x22u, 0x13u, 0x40u, 0x1eu, 0x3au, 0x9au, 0x40u, 0x13u, 0x00u, 0x03u, 0x4au, 0x13u, 0x60u, 0x05u, 0xb0u, 0xf0u, 0xbdu, 0xc0u, 0x46u, - 0xc4u, 0x05u, 0x00u, 0x08u, 0x00u, 0xe1u, 0x00u, 0xe0u, 0xf7u, 0xb5u, 0x2cu, 0x25u, 0x13u, 0x4cu, 0x68u, 0x43u, + 0xd4u, 0x05u, 0x00u, 0x08u, 0x00u, 0xe1u, 0x00u, 0xe0u, 0xf7u, 0xb5u, 0x2cu, 0x25u, 0x13u, 0x4cu, 0x68u, 0x43u, 0x26u, 0x68u, 0x69u, 0x43u, 0x34u, 0x18u, 0x25u, 0x69u, 0x01u, 0x93u, 0x71u, 0x18u, 0x00u, 0x2du, 0x19u, 0xd0u, 0x88u, 0x69u, 0x00u, 0x28u, 0x18u, 0xd1u, 0x2eu, 0x68u, 0x00u, 0x2eu, 0x15u, 0xdau, 0x67u, 0x68u, 0x01u, 0x24u, 0x26u, 0x00u, 0x4bu, 0x68u, 0x9eu, 0x40u, 0xb4u, 0x46u, 0x13u, 0x68u, 0x9eu, 0xb2u, 0x63u, 0x46u, 0x1bu, 0x04u, 0x1eu, 0x43u, 0x16u, 0x60u, 0xeau, 0x60u, 0x8cu, 0x61u, 0xbcu, 0x40u, 0x01u, 0x9bu, 0xa4u, 0xb2u, 0x4bu, 0x62u, - 0xacu, 0x60u, 0xfeu, 0xbdu, 0x02u, 0x48u, 0xfcu, 0xe7u, 0x02u, 0x48u, 0xfau, 0xe7u, 0xe0u, 0x03u, 0x00u, 0x08u, + 0xacu, 0x60u, 0xfeu, 0xbdu, 0x02u, 0x48u, 0xfcu, 0xe7u, 0x02u, 0x48u, 0xfau, 0xe7u, 0xf0u, 0x03u, 0x00u, 0x08u, 0x04u, 0x02u, 0x8au, 0x00u, 0x07u, 0x02u, 0x8au, 0x00u, 0x73u, 0xb5u, 0x00u, 0x26u, 0x42u, 0x69u, 0x04u, 0x00u, 0xd5u, 0x68u, 0x01u, 0x96u, 0x2bu, 0x0cu, 0xb3u, 0x42u, 0x21u, 0xd0u, 0x1bu, 0x04u, 0x13u, 0x60u, 0x13u, 0x68u, 0x19u, 0x4bu, 0x00u, 0x69u, 0x1bu, 0x68u, 0xb0u, 0x33u, 0x1bu, 0x68u, 0xc3u, 0x18u, 0x1bu, 0x68u, 0xb3u, 0x42u, @@ -99,35 +99,35 @@ const uint8_t cy_m0p_image[] = { 0x00u, 0x2bu, 0x00u, 0xd0u, 0x98u, 0x47u, 0x31u, 0x00u, 0x20u, 0x69u, 0xffu, 0xf7u, 0x0du, 0xffu, 0xadu, 0xb2u, 0x00u, 0x2du, 0x09u, 0xd0u, 0x63u, 0x69u, 0x1du, 0x60u, 0x00u, 0x25u, 0x1bu, 0x68u, 0x63u, 0x6au, 0xabu, 0x42u, 0x05u, 0xd0u, 0x98u, 0x47u, 0x65u, 0x62u, 0xa5u, 0x61u, 0x63u, 0x69u, 0x1bu, 0x68u, 0x73u, 0xbdu, 0xa3u, 0x6au, - 0x00u, 0x2bu, 0xf8u, 0xd0u, 0x98u, 0x47u, 0xf6u, 0xe7u, 0xc4u, 0x05u, 0x00u, 0x08u, 0x2cu, 0x23u, 0x10u, 0xb5u, + 0x00u, 0x2bu, 0xf8u, 0xd0u, 0x98u, 0x47u, 0xf6u, 0xe7u, 0xd4u, 0x05u, 0x00u, 0x08u, 0x2cu, 0x23u, 0x10u, 0xb5u, 0x43u, 0x43u, 0x03u, 0x4au, 0x10u, 0x68u, 0xc0u, 0x18u, 0xffu, 0xf7u, 0xb6u, 0xffu, 0x10u, 0xbdu, 0xc0u, 0x46u, - 0xe0u, 0x03u, 0x00u, 0x08u, 0xf8u, 0xb5u, 0x19u, 0x4bu, 0x0fu, 0x00u, 0x1bu, 0x68u, 0x1au, 0x00u, 0x2eu, 0x32u, + 0xf0u, 0x03u, 0x00u, 0x08u, 0xf8u, 0xb5u, 0x19u, 0x4bu, 0x0fu, 0x00u, 0x1bu, 0x68u, 0x1au, 0x00u, 0x2eu, 0x32u, 0x12u, 0x78u, 0x82u, 0x42u, 0x27u, 0xd9u, 0x00u, 0x29u, 0x25u, 0xd0u, 0x1fu, 0x25u, 0x0au, 0x68u, 0x15u, 0x40u, 0x21u, 0xd1u, 0x19u, 0x00u, 0xacu, 0x31u, 0x0cu, 0x88u, 0x11u, 0x4eu, 0x60u, 0x43u, 0x1cu, 0x6au, 0xd2u, 0x08u, - 0x04u, 0x19u, 0x29u, 0x00u, 0x78u, 0x68u, 0x34u, 0x60u, 0x00u, 0xf0u, 0x0cu, 0xffu, 0x29u, 0x00u, 0x20u, 0x00u, + 0x04u, 0x19u, 0x29u, 0x00u, 0x78u, 0x68u, 0x34u, 0x60u, 0x00u, 0xf0u, 0x10u, 0xffu, 0x29u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xcau, 0xfeu, 0x3au, 0x00u, 0x29u, 0x00u, 0x30u, 0x68u, 0xffu, 0xf7u, 0xd7u, 0xfeu, 0x04u, 0x1eu, 0x07u, 0xd1u, 0x01u, 0x00u, 0x30u, 0x68u, 0xffu, 0xf7u, 0xbfu, 0xfeu, 0x03u, 0x00u, 0x20u, 0x00u, 0x00u, 0x2bu, - 0x00u, 0xd0u, 0x04u, 0x48u, 0xf8u, 0xbdu, 0x04u, 0x48u, 0xfcu, 0xe7u, 0xc0u, 0x46u, 0xc4u, 0x05u, 0x00u, 0x08u, - 0xe4u, 0x03u, 0x00u, 0x08u, 0x01u, 0x01u, 0x8au, 0x00u, 0x03u, 0x01u, 0x8au, 0x00u, 0x10u, 0xb5u, 0x00u, 0x2au, + 0x00u, 0xd0u, 0x04u, 0x48u, 0xf8u, 0xbdu, 0x04u, 0x48u, 0xfcu, 0xe7u, 0xc0u, 0x46u, 0xd4u, 0x05u, 0x00u, 0x08u, + 0xf4u, 0x03u, 0x00u, 0x08u, 0x01u, 0x01u, 0x8au, 0x00u, 0x03u, 0x01u, 0x8au, 0x00u, 0x10u, 0xb5u, 0x00u, 0x2au, 0x0du, 0xd1u, 0x00u, 0x29u, 0x14u, 0xd1u, 0x0bu, 0x4bu, 0x1au, 0x68u, 0x13u, 0x00u, 0xacu, 0x33u, 0x1bu, 0x88u, 0x58u, 0x43u, 0x13u, 0x6au, 0xc0u, 0x18u, 0x08u, 0x4bu, 0x18u, 0x60u, 0x08u, 0x00u, 0x10u, 0xbdu, 0x00u, 0x29u, 0x06u, 0xd0u, 0x06u, 0x4bu, 0x19u, 0x60u, 0x19u, 0x00u, 0x5au, 0x60u, 0xffu, 0xf7u, 0xabu, 0xffu, 0xf5u, 0xe7u, - 0x03u, 0x48u, 0xf3u, 0xe7u, 0xc4u, 0x05u, 0x00u, 0x08u, 0xe4u, 0x03u, 0x00u, 0x08u, 0x78u, 0x03u, 0x00u, 0x08u, + 0x03u, 0x48u, 0xf3u, 0xe7u, 0xd4u, 0x05u, 0x00u, 0x08u, 0xf4u, 0x03u, 0x00u, 0x08u, 0x88u, 0x03u, 0x00u, 0x08u, 0x03u, 0x01u, 0x8au, 0x00u, 0xf7u, 0xb5u, 0x18u, 0x4fu, 0x04u, 0x00u, 0x3bu, 0x68u, 0x01u, 0x91u, 0xdeu, 0x68u, 0x33u, 0x68u, 0x83u, 0x42u, 0x26u, 0xd9u, 0x00u, 0x25u, 0xa9u, 0x42u, 0x02u, 0xd1u, 0xffu, 0xf7u, 0xadu, 0xfdu, 0x05u, 0x00u, 0x38u, 0x68u, 0x03u, 0x68u, 0x00u, 0x2bu, 0x1au, 0xdau, 0x1fu, 0x22u, 0x01u, 0x23u, 0x22u, 0x40u, 0x93u, 0x40u, 0x64u, 0x09u, 0x72u, 0x68u, 0xa4u, 0x00u, 0x14u, 0x19u, 0x22u, 0x68u, 0x13u, 0x42u, 0x0du, 0xd0u, 0x9au, 0x43u, 0x22u, 0x60u, 0x00u, 0x24u, 0x00u, 0x21u, 0xffu, 0xf7u, 0x66u, 0xfeu, 0x01u, 0x9bu, 0x00u, 0x2bu, 0x02u, 0xd1u, 0x28u, 0x00u, 0xffu, 0xf7u, 0x95u, 0xfdu, 0x20u, 0x00u, 0xfeu, 0xbdu, 0x03u, 0x4cu, 0xf2u, 0xe7u, - 0x03u, 0x4cu, 0xf3u, 0xe7u, 0x03u, 0x4cu, 0xf7u, 0xe7u, 0xe4u, 0x03u, 0x00u, 0x08u, 0x02u, 0x01u, 0x88u, 0x00u, + 0x03u, 0x4cu, 0xf3u, 0xe7u, 0x03u, 0x4cu, 0xf7u, 0xe7u, 0xf4u, 0x03u, 0x00u, 0x08u, 0x02u, 0x01u, 0x88u, 0x00u, 0x03u, 0x01u, 0x88u, 0x00u, 0x04u, 0x01u, 0x8au, 0x00u, 0x0au, 0x4bu, 0x1bu, 0x68u, 0xdbu, 0x68u, 0x1au, 0x68u, 0x82u, 0x42u, 0x0du, 0xd9u, 0x59u, 0x68u, 0x1fu, 0x23u, 0x42u, 0x09u, 0x18u, 0x40u, 0x1eu, 0x3bu, 0x83u, 0x40u, 0x92u, 0x00u, 0x50u, 0x58u, 0x18u, 0x40u, 0x43u, 0x1eu, 0x98u, 0x41u, 0x03u, 0x4bu, 0xc0u, 0x18u, 0x70u, 0x47u, - 0x02u, 0x48u, 0xfcu, 0xe7u, 0xe4u, 0x03u, 0x00u, 0x08u, 0x00u, 0x01u, 0x88u, 0x00u, 0x04u, 0x01u, 0x8au, 0x00u, + 0x02u, 0x48u, 0xfcu, 0xe7u, 0xf4u, 0x03u, 0x00u, 0x08u, 0x00u, 0x01u, 0x88u, 0x00u, 0x04u, 0x01u, 0x8au, 0x00u, 0xa6u, 0x22u, 0x05u, 0x49u, 0xd2u, 0x00u, 0x8bu, 0x58u, 0x02u, 0x20u, 0xdbu, 0x43u, 0x9bu, 0x07u, 0x02u, 0xd0u, 0x01u, 0x23u, 0x88u, 0x58u, 0x18u, 0x40u, 0x70u, 0x47u, 0x00u, 0x00u, 0x26u, 0x40u, 0x10u, 0xb5u, 0xffu, 0xf7u, 0xefu, 0xffu, 0x00u, 0x23u, 0x02u, 0x28u, 0x01u, 0xd1u, 0x01u, 0x4bu, 0x1bu, 0x68u, 0x18u, 0x00u, 0x10u, 0xbdu, - 0xe8u, 0x03u, 0x00u, 0x08u, 0x09u, 0x4au, 0x83u, 0x00u, 0x9bu, 0x18u, 0xd0u, 0x22u, 0x92u, 0x00u, 0x98u, 0x58u, + 0xf8u, 0x03u, 0x00u, 0x08u, 0x09u, 0x4au, 0x83u, 0x00u, 0x9bu, 0x18u, 0xd0u, 0x22u, 0x92u, 0x00u, 0x98u, 0x58u, 0x07u, 0x22u, 0x10u, 0x40u, 0x04u, 0x28u, 0x07u, 0xd1u, 0xc0u, 0x22u, 0x92u, 0x00u, 0x98u, 0x58u, 0x1fu, 0x23u, 0x03u, 0x40u, 0x80u, 0x20u, 0x40u, 0x00u, 0x18u, 0x43u, 0x70u, 0x47u, 0xc0u, 0x46u, 0x00u, 0x00u, 0x26u, 0x40u, 0x10u, 0xb5u, 0xffu, 0xf7u, 0xe7u, 0xffu, 0x02u, 0x28u, 0x1cu, 0xd0u, 0x05u, 0xd8u, 0x00u, 0x28u, 0x14u, 0xd0u, @@ -136,7 +136,7 @@ const uint8_t cy_m0p_image[] = { 0x0cu, 0x4bu, 0xd0u, 0x58u, 0xc0u, 0x0fu, 0xc0u, 0x03u, 0x00u, 0xe0u, 0x0bu, 0x48u, 0x10u, 0xbdu, 0x0bu, 0x4bu, 0x18u, 0x68u, 0xfbu, 0xe7u, 0xffu, 0xf7u, 0xbau, 0xffu, 0xf8u, 0xe7u, 0x09u, 0x4bu, 0x18u, 0x69u, 0x04u, 0x23u, 0x18u, 0x40u, 0xf3u, 0xd0u, 0x80u, 0x20u, 0x00u, 0x02u, 0xf0u, 0xe7u, 0x01u, 0x4au, 0x05u, 0x4bu, 0xe8u, 0xe7u, - 0x00u, 0x00u, 0x26u, 0x40u, 0x0cu, 0x05u, 0x00u, 0x00u, 0x00u, 0x12u, 0x7au, 0x00u, 0xecu, 0x03u, 0x00u, 0x08u, + 0x00u, 0x00u, 0x26u, 0x40u, 0x0cu, 0x05u, 0x00u, 0x00u, 0x00u, 0x12u, 0x7au, 0x00u, 0xfcu, 0x03u, 0x00u, 0x08u, 0x00u, 0x00u, 0x27u, 0x40u, 0x3cu, 0x05u, 0x00u, 0x00u, 0xb0u, 0x23u, 0x15u, 0x4au, 0xdbu, 0x00u, 0xd3u, 0x58u, 0x10u, 0xb5u, 0x99u, 0x03u, 0xdbu, 0x01u, 0xdbu, 0x0fu, 0x89u, 0x0bu, 0xc3u, 0x71u, 0x11u, 0x4bu, 0x01u, 0x60u, 0xd3u, 0x58u, 0x0fu, 0x24u, 0xd9u, 0x04u, 0xdbu, 0x01u, 0xdbu, 0x0du, 0x03u, 0x81u, 0xb1u, 0x23u, 0xdbu, 0x00u, @@ -148,258 +148,259 @@ const uint8_t cy_m0p_image[] = { 0x80u, 0x30u, 0xffu, 0x30u, 0x0bu, 0x4bu, 0x80u, 0x00u, 0xc3u, 0x58u, 0x1au, 0x40u, 0x0au, 0x70u, 0x1au, 0x0cu, 0x22u, 0x40u, 0x18u, 0x0au, 0x8au, 0x70u, 0x1au, 0x01u, 0x20u, 0x40u, 0xe2u, 0x40u, 0x48u, 0x70u, 0x00u, 0x20u, 0x9bu, 0x00u, 0x9bu, 0x0fu, 0xcau, 0x70u, 0x0bu, 0x71u, 0x10u, 0xbdu, 0x03u, 0x48u, 0xfcu, 0xe7u, 0xc0u, 0x46u, - 0xc4u, 0x05u, 0x00u, 0x08u, 0x00u, 0x00u, 0x26u, 0x40u, 0x01u, 0x00u, 0x4au, 0x00u, 0xf0u, 0xb5u, 0x87u, 0xb0u, - 0x04u, 0x00u, 0xffu, 0xf7u, 0x65u, 0xffu, 0x06u, 0x00u, 0x00u, 0x2cu, 0x34u, 0xd1u, 0x01u, 0xadu, 0x14u, 0x22u, - 0x21u, 0x00u, 0x28u, 0x00u, 0x00u, 0xf0u, 0x9eu, 0xfdu, 0x28u, 0x00u, 0xffu, 0xf7u, 0x95u, 0xffu, 0xb0u, 0x23u, - 0x25u, 0x4au, 0xdbu, 0x00u, 0xd3u, 0x58u, 0x00u, 0x2bu, 0x03u, 0xdau, 0xacu, 0x7bu, 0x02u, 0x3cu, 0x63u, 0x1eu, + 0xd4u, 0x05u, 0x00u, 0x08u, 0x00u, 0x00u, 0x26u, 0x40u, 0x01u, 0x00u, 0x4au, 0x00u, 0xf0u, 0xb5u, 0x87u, 0xb0u, + 0x04u, 0x00u, 0xffu, 0xf7u, 0x65u, 0xffu, 0x06u, 0x00u, 0x00u, 0x2cu, 0x38u, 0xd1u, 0x01u, 0xadu, 0x14u, 0x22u, + 0x21u, 0x00u, 0x28u, 0x00u, 0x00u, 0xf0u, 0xa2u, 0xfdu, 0x28u, 0x00u, 0xffu, 0xf7u, 0x95u, 0xffu, 0xb0u, 0x23u, + 0x27u, 0x4au, 0xdbu, 0x00u, 0xd3u, 0x58u, 0x00u, 0x2bu, 0x03u, 0xdau, 0xacu, 0x7bu, 0x02u, 0x3cu, 0x63u, 0x1eu, 0x9cu, 0x41u, 0xeau, 0x79u, 0x01u, 0x9fu, 0x53u, 0x1eu, 0x9au, 0x41u, 0xa8u, 0x88u, 0x01u, 0x32u, 0x00u, 0x2cu, - 0x16u, 0xd0u, 0x00u, 0x23u, 0x19u, 0x00u, 0x00u, 0xf0u, 0x6fu, 0xfcu, 0x00u, 0x23u, 0x0cu, 0x00u, 0x05u, 0x00u, - 0x3au, 0x00u, 0x30u, 0x00u, 0x19u, 0x00u, 0x00u, 0xf0u, 0x67u, 0xfcu, 0xe6u, 0x07u, 0x6au, 0x08u, 0x32u, 0x43u, - 0x63u, 0x08u, 0x80u, 0x18u, 0x59u, 0x41u, 0x2au, 0x00u, 0x23u, 0x00u, 0x00u, 0xf0u, 0x3du, 0xfcu, 0x06u, 0x00u, - 0x30u, 0x00u, 0x07u, 0xb0u, 0xf0u, 0xbdu, 0x11u, 0x4bu, 0x1bu, 0x68u, 0x3bu, 0x33u, 0x1bu, 0x78u, 0xa3u, 0x42u, - 0xf6u, 0xd3u, 0x01u, 0xadu, 0x05u, 0x22u, 0x00u, 0x21u, 0x28u, 0x00u, 0x00u, 0xf0u, 0x63u, 0xfdu, 0x20u, 0x00u, - 0x29u, 0x00u, 0x80u, 0x34u, 0xffu, 0xf7u, 0x8au, 0xffu, 0xffu, 0x34u, 0x07u, 0x4bu, 0xa4u, 0x00u, 0xe3u, 0x58u, - 0x00u, 0x24u, 0xa3u, 0x42u, 0x03u, 0xdau, 0x2cu, 0x79u, 0x02u, 0x3cu, 0x63u, 0x1eu, 0x9cu, 0x41u, 0x2fu, 0x78u, - 0x68u, 0x78u, 0xaau, 0x78u, 0xc3u, 0xe7u, 0xc0u, 0x46u, 0x00u, 0x00u, 0x26u, 0x40u, 0xc4u, 0x05u, 0x00u, 0x08u, - 0xe0u, 0x22u, 0x10u, 0xb5u, 0x01u, 0x24u, 0x09u, 0x4bu, 0x80u, 0x00u, 0x92u, 0x00u, 0xc0u, 0x18u, 0x83u, 0x58u, - 0x80u, 0x58u, 0x9bu, 0x06u, 0x9bu, 0x0fu, 0x9cu, 0x40u, 0x0fu, 0x23u, 0x18u, 0x40u, 0xffu, 0xf7u, 0x8eu, 0xffu, - 0x63u, 0x08u, 0x18u, 0x18u, 0x21u, 0x00u, 0x00u, 0xf0u, 0x73u, 0xfbu, 0x10u, 0xbdu, 0x00u, 0x00u, 0x26u, 0x40u, - 0x14u, 0x4bu, 0x30u, 0xb5u, 0x1au, 0x68u, 0x07u, 0x24u, 0x13u, 0x00u, 0x28u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, - 0x15u, 0xd8u, 0x83u, 0x08u, 0x1du, 0x00u, 0xa5u, 0x43u, 0x2cu, 0x1eu, 0x0fu, 0xd1u, 0x03u, 0x34u, 0x20u, 0x40u, - 0xa0u, 0x40u, 0x81u, 0x40u, 0x12u, 0x68u, 0x9bu, 0x00u, 0x20u, 0x32u, 0xd3u, 0x18u, 0x0au, 0x00u, 0xffu, 0x21u, - 0x81u, 0x40u, 0x1cu, 0x68u, 0x62u, 0x40u, 0x11u, 0x40u, 0x61u, 0x40u, 0x19u, 0x60u, 0x30u, 0xbdu, 0x80u, 0x23u, - 0x20u, 0x40u, 0x1bu, 0x06u, 0x18u, 0x43u, 0x80u, 0x23u, 0x9bu, 0x01u, 0x12u, 0x68u, 0xc9u, 0x18u, 0x89u, 0x00u, - 0x88u, 0x50u, 0xf3u, 0xe7u, 0xc4u, 0x05u, 0x00u, 0x08u, 0x06u, 0x4bu, 0x9au, 0x68u, 0x03u, 0x00u, 0x06u, 0x48u, - 0x10u, 0x33u, 0x9bu, 0x00u, 0x82u, 0x42u, 0x02u, 0xd1u, 0x98u, 0x58u, 0x99u, 0x50u, 0x70u, 0x47u, 0x03u, 0x4au, - 0xd0u, 0x58u, 0xfbu, 0xe7u, 0x00u, 0xedu, 0x00u, 0xe0u, 0x00u, 0x00u, 0x00u, 0x08u, 0x00u, 0x00u, 0x00u, 0x10u, - 0xf8u, 0xb5u, 0x06u, 0x00u, 0x0du, 0x00u, 0x00u, 0x28u, 0x3au, 0xd0u, 0x00u, 0x23u, 0xc0u, 0x5eu, 0x00u, 0x28u, - 0x28u, 0xdbu, 0x71u, 0x88u, 0xffu, 0xf7u, 0xb4u, 0xffu, 0x00u, 0x24u, 0xffu, 0x22u, 0x03u, 0x27u, 0x94u, 0x46u, - 0x00u, 0x23u, 0xf0u, 0x5eu, 0x71u, 0x68u, 0x83u, 0xb2u, 0x1fu, 0x40u, 0xffu, 0x00u, 0x66u, 0x46u, 0xbau, 0x40u, - 0x89u, 0x01u, 0x31u, 0x40u, 0xd2u, 0x43u, 0xb9u, 0x40u, 0x00u, 0x28u, 0x15u, 0xdbu, 0x11u, 0x4eu, 0x83u, 0x08u, - 0x9bu, 0x00u, 0x9bu, 0x19u, 0xc0u, 0x26u, 0xb6u, 0x00u, 0x9fu, 0x59u, 0x3au, 0x40u, 0x11u, 0x43u, 0x99u, 0x51u, - 0x0du, 0x4bu, 0x9au, 0x68u, 0x0du, 0x4bu, 0x9au, 0x42u, 0x02u, 0xd1u, 0x29u, 0x00u, 0xffu, 0xf7u, 0xbcu, 0xffu, - 0x20u, 0x00u, 0xf8u, 0xbdu, 0x0au, 0x4cu, 0xd8u, 0xe7u, 0x0fu, 0x26u, 0x33u, 0x40u, 0x08u, 0x3bu, 0x06u, 0x4eu, - 0x9bu, 0x08u, 0x9bu, 0x00u, 0x9bu, 0x19u, 0xdeu, 0x69u, 0x32u, 0x40u, 0x11u, 0x43u, 0xd9u, 0x61u, 0xe7u, 0xe7u, - 0x03u, 0x4cu, 0xedu, 0xe7u, 0x00u, 0xe1u, 0x00u, 0xe0u, 0x00u, 0xedu, 0x00u, 0xe0u, 0x00u, 0x00u, 0x00u, 0x08u, - 0x01u, 0x00u, 0x56u, 0x00u, 0xfeu, 0xe7u, 0x00u, 0x00u, 0x02u, 0x68u, 0x0au, 0x4bu, 0x10u, 0xb5u, 0x1au, 0x60u, - 0x42u, 0x68u, 0x5au, 0x60u, 0x82u, 0x68u, 0x9au, 0x60u, 0xc2u, 0x68u, 0xdau, 0x60u, 0x02u, 0x69u, 0x1au, 0x61u, - 0x42u, 0x69u, 0x5au, 0x61u, 0x82u, 0x69u, 0x9au, 0x61u, 0xc2u, 0x69u, 0xdau, 0x61u, 0xffu, 0xf7u, 0xeau, 0xffu, - 0x10u, 0xbdu, 0xc0u, 0x46u, 0x90u, 0x03u, 0x00u, 0x08u, 0xb0u, 0x23u, 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0x00u, 0x08u, 0xadu, 0x0du, 0x00u, 0x10u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0xfdu, 0xffu, 0x7fu, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x10u, + 0x00u, 0x00u, 0x00u, 0x08u, 0x80u, 0x00u, 0x00u, 0x00u, 0x4cu, 0x14u, 0x00u, 0x10u, 0x80u, 0x00u, 0x00u, 0x08u, + 0x08u, 0x03u, 0x00u, 0x00u, 0xc0u, 0x03u, 0x00u, 0x08u, 0x18u, 0x02u, 0x00u, 0x00u, 0x00u, 0x09u, 0x3du, 0x00u, + 0x00u, 0x12u, 0x7au, 0x00u, 0x00u, 0x09u, 0x3du, 0x00u, 0x00u, 0x00u, 0xd0u, 0x07u, 0xa0u, 0x0fu, 0x00u, 0x00u, + 0x04u, 0x00u, 0x00u, 0x00u, 0xa9u, 0x00u, 0x00u, 0x10u, 0x81u, 0x00u, 0x00u, 0x10u, 0x02u, 0x4au, 0x13u, 0x68u, + 0x00u, 0x2bu, 0xfcu, 0xdbu, 0x70u, 0x47u, 0xc0u, 0x46u, 0x00u, 0x01u, 0x26u, 0x40u, 0x80u, 0xb2u, 0x30u, 0xb5u, + 0xc0u, 0x00u, 0x20u, 0xd0u, 0x10u, 0x4bu, 0x07u, 0x22u, 0x1cu, 0x68u, 0x23u, 0x00u, 0xacu, 0x33u, 0x1bu, 0x88u, + 0x5au, 0x43u, 0x23u, 0x6au, 0xd3u, 0x18u, 0x19u, 0x68u, 0x00u, 0x29u, 0xfcu, 0xdau, 0x3eu, 0x21u, 0x0bu, 0x4bu, + 0x06u, 0x25u, 0x19u, 0x60u, 0x0au, 0x4bu, 0x0bu, 0x49u, 0x19u, 0x60u, 0xa3u, 0x21u, 0x0au, 0x4bu, 0xc9u, 0x00u, + 0x5du, 0x50u, 0x0au, 0x49u, 0x58u, 0x50u, 0x58u, 0x58u, 0x20u, 0x6au, 0x12u, 0x18u, 0x00u, 0x20u, 0x50u, 0x60u, + 0x5au, 0x58u, 0x00u, 0x2au, 0xfcu, 0xdau, 0x30u, 0xbdu, 0xd4u, 0x05u, 0x00u, 0x08u, 0x04u, 0x01u, 0x26u, 0x40u, + 0x08u, 0x01u, 0x26u, 0x40u, 0x1eu, 0x1fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x26u, 0x40u, 0x1cu, 0x05u, 0x00u, 0x00u, + 0x10u, 0xb5u, 0x43u, 0x78u, 0xffu, 0x2bu, 0x11u, 0xd1u, 0x00u, 0xf0u, 0x0cu, 0xf9u, 0x04u, 0x00u, 0x03u, 0x20u, + 0x00u, 0xf0u, 0xe8u, 0xf8u, 0xc3u, 0x68u, 0x5au, 0x68u, 0x01u, 0x23u, 0x11u, 0x68u, 0x19u, 0x43u, 0x11u, 0x60u, + 0x11u, 0x68u, 0x19u, 0x42u, 0xfcu, 0xd1u, 0x20u, 0x00u, 0x00u, 0xf0u, 0x0cu, 0xf9u, 0x10u, 0xbdu, 0xf7u, 0xb5u, + 0x00u, 0x90u, 0x00u, 0x20u, 0x01u, 0x91u, 0x00u, 0xf0u, 0xd5u, 0xf8u, 0x3fu, 0x4du, 0x06u, 0x00u, 0x2bu, 0x68u, + 0x1au, 0x00u, 0x4cu, 0x33u, 0xb0u, 0x32u, 0x14u, 0x68u, 0x1bu, 0x78u, 0x04u, 0x19u, 0x00u, 0x2bu, 0x5au, 0xd0u, + 0x00u, 0xf0u, 0xf0u, 0xf8u, 0x07u, 0x00u, 0x03u, 0x28u, 0x1bu, 0xd0u, 0x00u, 0xf0u, 0xe3u, 0xf8u, 0x37u, 0x4au, + 0x37u, 0x4bu, 0x05u, 0x00u, 0xd3u, 0x58u, 0x00u, 0x2bu, 0x3eu, 0xdau, 0x36u, 0x4au, 0x01u, 0x21u, 0x30u, 0x00u, + 0x00u, 0xf0u, 0xc8u, 0xf8u, 0x00u, 0x28u, 0x37u, 0xd1u, 0x01u, 0x98u, 0xffu, 0xf7u, 0x8fu, 0xffu, 0x00u, 0x9bu, + 0x00u, 0x2bu, 0x3eu, 0xd0u, 0x23u, 0x68u, 0x00u, 0x2bu, 0xfcu, 0xdbu, 0x00u, 0xf0u, 0xb3u, 0xf8u, 0x04u, 0x00u, + 0x2bu, 0xe0u, 0x06u, 0x20u, 0x00u, 0xf0u, 0xa6u, 0xf8u, 0x2bu, 0x68u, 0xb0u, 0x33u, 0x1bu, 0x68u, 0xc0u, 0x18u, + 0x03u, 0x68u, 0x00u, 0x2bu, 0x02u, 0xdau, 0x28u, 0x4cu, 0x20u, 0x00u, 0xfeu, 0xbdu, 0x00u, 0x20u, 0x00u, 0xf0u, + 0xd1u, 0xf8u, 0x26u, 0x4bu, 0x98u, 0x42u, 0xf6u, 0xd0u, 0x00u, 0x23u, 0x25u, 0x4au, 0x19u, 0x00u, 0x12u, 0x68u, + 0x01u, 0x20u, 0x00u, 0xf0u, 0xcfu, 0xf8u, 0x00u, 0x25u, 0xa8u, 0x42u, 0xecu, 0xd1u, 0x00u, 0x20u, 0x00u, 0xf0u, + 0xc1u, 0xf8u, 0x1eu, 0x4au, 0x1fu, 0x4bu, 0x90u, 0x42u, 0x03u, 0xd0u, 0x9du, 0x42u, 0xe3u, 0xd0u, 0x01u, 0x35u, + 0xf4u, 0xe7u, 0x9du, 0x42u, 0xb9u, 0xd1u, 0xdeu, 0xe7u, 0x17u, 0x4cu, 0x03u, 0x2fu, 0x05u, 0xd1u, 0x01u, 0x21u, + 0x00u, 0x20u, 0x00u, 0xf0u, 0x8fu, 0xf8u, 0x00u, 0x28u, 0xf9u, 0xd1u, 0x28u, 0x00u, 0x00u, 0xf0u, 0xa2u, 0xf8u, + 0xd2u, 0xe7u, 0x15u, 0x4cu, 0xf1u, 0xe7u, 0x00u, 0xf0u, 0x8du, 0xf8u, 0x0eu, 0x4au, 0x05u, 0x00u, 0x01u, 0x21u, + 0x30u, 0x00u, 0x00u, 0xf0u, 0x77u, 0xf8u, 0x00u, 0x28u, 0x09u, 0xd1u, 0x00u, 0x9bu, 0x00u, 0x2bu, 0x08u, 0xd0u, + 0x23u, 0x68u, 0x00u, 0x2bu, 0xfcu, 0xdbu, 0x00u, 0xf0u, 0x65u, 0xf8u, 0x04u, 0x00u, 0xe5u, 0xe7u, 0x06u, 0x4cu, + 0xe3u, 0xe7u, 0x09u, 0x4cu, 0xe1u, 0xe7u, 0xc0u, 0x46u, 0xd4u, 0x05u, 0x00u, 0x08u, 0x00u, 0x00u, 0x26u, 0x40u, + 0x1cu, 0x05u, 0x00u, 0x00u, 0xdcu, 0x03u, 0x00u, 0x08u, 0x05u, 0x00u, 0x52u, 0x00u, 0x01u, 0x01u, 0x88u, 0x00u, + 0xecu, 0x03u, 0x00u, 0x08u, 0xf0u, 0x49u, 0x02u, 0x00u, 0x01u, 0x00u, 0x50u, 0x00u, 0x18u, 0x4bu, 0xf7u, 0xb5u, + 0x1bu, 0x68u, 0x18u, 0x4au, 0x5cu, 0x68u, 0x04u, 0x23u, 0x11u, 0x69u, 0x0bu, 0x43u, 0x13u, 0x61u, 0x01u, 0x28u, + 0x24u, 0xd0u, 0x30u, 0xbfu, 0x23u, 0x00u, 0xfcu, 0x33u, 0x1bu, 0x69u, 0x00u, 0x2bu, 0x1du, 0xd1u, 0xa3u, 0x20u, + 0x11u, 0x4bu, 0x12u, 0x49u, 0x12u, 0x4au, 0xc0u, 0x00u, 0x0fu, 0x68u, 0x1eu, 0x58u, 0x15u, 0x68u, 0x01u, 0x95u, + 0x10u, 0x4du, 0x0du, 0x60u, 0x06u, 0x25u, 0x1du, 0x50u, 0x3eu, 0x20u, 0x10u, 0x60u, 0x0eu, 0x48u, 0x3eu, 0x35u, + 0x1du, 0x50u, 0x1du, 0x58u, 0x00u, 0x2du, 0xfcu, 0xdau, 0x0cu, 0x48u, 0xfcu, 0x34u, 0x20u, 0x61u, 0x0fu, 0x60u, + 0xa3u, 0x21u, 0xc9u, 0x00u, 0x5eu, 0x50u, 0x01u, 0x9bu, 0x13u, 0x60u, 0xf7u, 0xbdu, 0x20u, 0xbfu, 0xd9u, 0xe7u, + 0xd4u, 0x05u, 0x00u, 0x08u, 0x00u, 0xedu, 0x00u, 0xe0u, 0x00u, 0x00u, 0x26u, 0x40u, 0x08u, 0x01u, 0x26u, 0x40u, + 0x04u, 0x01u, 0x26u, 0x40u, 0x1eu, 0x1fu, 0x00u, 0x00u, 0x1cu, 0x05u, 0x00u, 0x00u, 0xaau, 0xaau, 0xaau, 0xaau, + 0x00u, 0x00u, 0x00u, 0x00u, 0x01u, 0xb4u, 0x02u, 0x48u, 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, + 0x75u, 0x01u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, + 0x39u, 0x02u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, + 0x9du, 0x02u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, + 0x65u, 0x05u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, + 0xdbu, 0x00u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, + 0xe5u, 0x0eu, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, + 0xe3u, 0x00u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, + 0xd9u, 0x05u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, + 0xa9u, 0x03u, 0x00u, 0x10u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, }; #endif /* defined(CY_DEVICE_PSOC6A2M) */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/COMPONENT_CM0P_SLEEP/psoc6_03_cm0p_sleep.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/COMPONENT_CM0P_SLEEP/psoc6_03_cm0p_sleep.c index de4c30d0ef..057ed82cd1 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/COMPONENT_CM0P_SLEEP/psoc6_03_cm0p_sleep.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/COMPONENT_CM0P_SLEEP/psoc6_03_cm0p_sleep.c @@ -36,22 +36,22 @@ const uint8_t cy_m0p_image[] = { 0x49u, 0x01u, 0x00u, 0x10u, 0x49u, 0x01u, 0x00u, 0x10u, 0x49u, 0x01u, 0x00u, 0x10u, 0x49u, 0x01u, 0x00u, 0x10u, 0x49u, 0x01u, 0x00u, 0x10u, 0x49u, 0x01u, 0x00u, 0x10u, 0x49u, 0x01u, 0x00u, 0x10u, 0x49u, 0x01u, 0x00u, 0x10u, 0x10u, 0xb5u, 0x06u, 0x4cu, 0x23u, 0x78u, 0x00u, 0x2bu, 0x07u, 0xd1u, 0x05u, 0x4bu, 0x00u, 0x2bu, 0x02u, 0xd0u, - 0x04u, 0x48u, 0x00u, 0xe0u, 0x00u, 0xbfu, 0x01u, 0x23u, 0x23u, 0x70u, 0x10u, 0xbdu, 0xb0u, 0x03u, 0x00u, 0x08u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x18u, 0x14u, 0x00u, 0x10u, 0x04u, 0x4bu, 0x10u, 0xb5u, 0x00u, 0x2bu, 0x03u, 0xd0u, + 0x04u, 0x48u, 0x00u, 0xe0u, 0x00u, 0xbfu, 0x01u, 0x23u, 0x23u, 0x70u, 0x10u, 0xbdu, 0xc0u, 0x03u, 0x00u, 0x08u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x20u, 0x14u, 0x00u, 0x10u, 0x04u, 0x4bu, 0x10u, 0xb5u, 0x00u, 0x2bu, 0x03u, 0xd0u, 0x03u, 0x49u, 0x04u, 0x48u, 0x00u, 0xe0u, 0x00u, 0xbfu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0x00u, 0x00u, 0x00u, 0x00u, - 0xb4u, 0x03u, 0x00u, 0x08u, 0x18u, 0x14u, 0x00u, 0x10u, 0x02u, 0x30u, 0x80u, 0x08u, 0x03u, 0xd0u, 0x01u, 0x30u, + 0xc4u, 0x03u, 0x00u, 0x08u, 0x20u, 0x14u, 0x00u, 0x10u, 0x02u, 0x30u, 0x80u, 0x08u, 0x03u, 0xd0u, 0x01u, 0x30u, 0x02u, 0x38u, 0xfcu, 0xd1u, 0xc0u, 0x46u, 0xc0u, 0x46u, 0x70u, 0x47u, 0xefu, 0xf3u, 0x10u, 0x80u, 0x72u, 0xb6u, 0x70u, 0x47u, 0x80u, 0xf3u, 0x10u, 0x88u, 0x70u, 0x47u, 0x70u, 0x47u, 0xffu, 0xf7u, 0xfdu, 0xffu, 0x72u, 0xb6u, 0x0fu, 0x4cu, 0x10u, 0x4du, 0xacu, 0x42u, 0x09u, 0xdau, 0x21u, 0x68u, 0x62u, 0x68u, 0xa3u, 0x68u, 0x04u, 0x3bu, 0x02u, 0xdbu, 0xc8u, 0x58u, 0xd0u, 0x50u, 0xfau, 0xe7u, 0x0cu, 0x34u, 0xf3u, 0xe7u, 0x0au, 0x49u, 0x0bu, 0x4au, 0x00u, 0x20u, 0x52u, 0x1au, 0x02u, 0xddu, 0x04u, 0x3au, 0x88u, 0x50u, 0xfcu, 0xdcu, 0x08u, 0x48u, 0x09u, 0x49u, - 0x08u, 0x60u, 0xbfu, 0xf3u, 0x4fu, 0x8fu, 0x00u, 0xf0u, 0x85u, 0xfeu, 0x00u, 0xf0u, 0x2fu, 0xfeu, 0xfeu, 0xe7u, - 0x24u, 0x14u, 0x00u, 0x10u, 0x3cu, 0x14u, 0x00u, 0x10u, 0xb0u, 0x03u, 0x00u, 0x08u, 0xc8u, 0x05u, 0x00u, 0x08u, + 0x08u, 0x60u, 0xbfu, 0xf3u, 0x4fu, 0x8fu, 0x00u, 0xf0u, 0x89u, 0xfeu, 0x00u, 0xf0u, 0x33u, 0xfeu, 0xfeu, 0xe7u, + 0x2cu, 0x14u, 0x00u, 0x10u, 0x44u, 0x14u, 0x00u, 0x10u, 0xc0u, 0x03u, 0x00u, 0x08u, 0xd8u, 0x05u, 0x00u, 0x08u, 0x00u, 0x00u, 0x00u, 0x08u, 0x08u, 0xedu, 0x00u, 0xe0u, 0xfeu, 0xe7u, 0xfeu, 0xe7u, 0x00u, 0xb5u, 0x04u, 0x20u, 0x71u, 0x46u, 0x08u, 0x42u, 0x02u, 0xd0u, 0xefu, 0xf3u, 0x09u, 0x80u, 0x01u, 0xe0u, 0xefu, 0xf3u, 0x08u, 0x80u, - 0x04u, 0x30u, 0x00u, 0xf0u, 0x21u, 0xfcu, 0xfeu, 0xe7u, 0x01u, 0x4bu, 0x18u, 0x60u, 0x70u, 0x47u, 0xc0u, 0x46u, - 0xc4u, 0x05u, 0x00u, 0x08u, 0x04u, 0x4bu, 0x1bu, 0x68u, 0x1au, 0x00u, 0xacu, 0x32u, 0x12u, 0x88u, 0x1bu, 0x6au, - 0x50u, 0x43u, 0xc0u, 0x18u, 0x70u, 0x47u, 0xc0u, 0x46u, 0xc4u, 0x05u, 0x00u, 0x08u, 0x1du, 0x4bu, 0x98u, 0x42u, + 0x04u, 0x30u, 0x00u, 0xf0u, 0x25u, 0xfcu, 0xfeu, 0xe7u, 0x01u, 0x4bu, 0x18u, 0x60u, 0x70u, 0x47u, 0xc0u, 0x46u, + 0xd4u, 0x05u, 0x00u, 0x08u, 0x04u, 0x4bu, 0x1bu, 0x68u, 0x1au, 0x00u, 0xacu, 0x32u, 0x12u, 0x88u, 0x1bu, 0x6au, + 0x50u, 0x43u, 0xc0u, 0x18u, 0x70u, 0x47u, 0xc0u, 0x46u, 0xd4u, 0x05u, 0x00u, 0x08u, 0x1du, 0x4bu, 0x98u, 0x42u, 0x0fu, 0xd0u, 0x10u, 0xd8u, 0x40u, 0x28u, 0x2fu, 0xd0u, 0x05u, 0xd8u, 0x00u, 0x28u, 0x30u, 0xd0u, 0x10u, 0x28u, 0x28u, 0xd0u, 0x19u, 0x48u, 0x1eu, 0xe0u, 0x80u, 0x28u, 0x28u, 0xd0u, 0x80u, 0x23u, 0x5bu, 0x00u, 0x98u, 0x42u, 0xf7u, 0xd1u, 0x14u, 0x48u, 0x16u, 0xe0u, 0x15u, 0x4bu, 0x98u, 0x42u, 0x14u, 0xd0u, 0x08u, 0xd8u, 0xa0u, 0x23u, @@ -65,32 +65,32 @@ const uint8_t cy_m0p_image[] = { 0x02u, 0x00u, 0x50u, 0x00u, 0x05u, 0x00u, 0x52u, 0x00u, 0x10u, 0xb5u, 0x00u, 0x20u, 0xffu, 0xf7u, 0x9au, 0xffu, 0x0au, 0x4bu, 0x1cu, 0x68u, 0x23u, 0x00u, 0xb0u, 0x33u, 0x1bu, 0x68u, 0xc0u, 0x18u, 0x03u, 0x68u, 0x00u, 0x2bu, 0x0au, 0xdbu, 0x07u, 0x4bu, 0x18u, 0x68u, 0xffu, 0xf7u, 0x99u, 0xffu, 0x01u, 0x22u, 0x63u, 0x68u, 0x9au, 0x60u, - 0x9au, 0x68u, 0x00u, 0x2au, 0xfcu, 0xd1u, 0x10u, 0xbdu, 0x02u, 0x48u, 0xfcu, 0xe7u, 0xc4u, 0x05u, 0x00u, 0x08u, - 0xccu, 0x03u, 0x00u, 0x08u, 0x02u, 0x00u, 0x50u, 0x00u, 0x06u, 0x4bu, 0x1bu, 0x68u, 0xb0u, 0x33u, 0x1bu, 0x68u, + 0x9au, 0x68u, 0x00u, 0x2au, 0xfcu, 0xd1u, 0x10u, 0xbdu, 0x02u, 0x48u, 0xfcu, 0xe7u, 0xd4u, 0x05u, 0x00u, 0x08u, + 0xdcu, 0x03u, 0x00u, 0x08u, 0x02u, 0x00u, 0x50u, 0x00u, 0x06u, 0x4bu, 0x1bu, 0x68u, 0xb0u, 0x33u, 0x1bu, 0x68u, 0xc3u, 0x18u, 0x1bu, 0x68u, 0x00u, 0x2bu, 0x03u, 0xdau, 0x89u, 0xb2u, 0x41u, 0x60u, 0x00u, 0x20u, 0x70u, 0x47u, - 0x01u, 0x48u, 0xfcu, 0xe7u, 0xc4u, 0x05u, 0x00u, 0x08u, 0x01u, 0x00u, 0x8au, 0x00u, 0x03u, 0x68u, 0x00u, 0x2bu, + 0x01u, 0x48u, 0xfcu, 0xe7u, 0xd4u, 0x05u, 0x00u, 0x08u, 0x01u, 0x00u, 0x8au, 0x00u, 0x03u, 0x68u, 0x00u, 0x2bu, 0x04u, 0xdau, 0x89u, 0xb2u, 0xc2u, 0x60u, 0x81u, 0x60u, 0x00u, 0x20u, 0x70u, 0x47u, 0x00u, 0x48u, 0xfcu, 0xe7u, 0x01u, 0x00u, 0x8au, 0x00u, 0x06u, 0x4bu, 0x1bu, 0x68u, 0xb0u, 0x33u, 0x1bu, 0x68u, 0xc3u, 0x18u, 0x1bu, 0x68u, 0x00u, 0x2bu, 0x03u, 0xdau, 0xc3u, 0x68u, 0x00u, 0x20u, 0x0bu, 0x60u, 0x70u, 0x47u, 0x01u, 0x48u, 0xfcu, 0xe7u, - 0xc4u, 0x05u, 0x00u, 0x08u, 0x01u, 0x00u, 0x8au, 0x00u, 0x02u, 0x4bu, 0x1au, 0x68u, 0x00u, 0x2au, 0x00u, 0xd1u, - 0x18u, 0x60u, 0x70u, 0x47u, 0xe0u, 0x03u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x2cu, 0x24u, 0x60u, 0x43u, 0x12u, 0x4cu, + 0xd4u, 0x05u, 0x00u, 0x08u, 0x01u, 0x00u, 0x8au, 0x00u, 0x02u, 0x4bu, 0x1au, 0x68u, 0x00u, 0x2au, 0x00u, 0xd1u, + 0x18u, 0x60u, 0x70u, 0x47u, 0xf0u, 0x03u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x2cu, 0x24u, 0x60u, 0x43u, 0x12u, 0x4cu, 0x1fu, 0x00u, 0x24u, 0x68u, 0x1eu, 0x0au, 0x20u, 0x18u, 0xffu, 0x24u, 0x27u, 0x40u, 0x34u, 0x40u, 0x0fu, 0x4eu, 0x1bu, 0x0cu, 0x35u, 0x68u, 0x07u, 0x60u, 0x2eu, 0x6au, 0x44u, 0x60u, 0x83u, 0x60u, 0xacu, 0x35u, 0x2du, 0x88u, 0x80u, 0x34u, 0x6fu, 0x43u, 0x64u, 0x01u, 0x34u, 0x19u, 0xbfu, 0x19u, 0x1eu, 0x04u, 0x33u, 0x43u, 0x07u, 0x61u, 0x44u, 0x61u, 0xa3u, 0x60u, 0x00u, 0x23u, 0x83u, 0x61u, 0x05u, 0x9bu, 0xc2u, 0x61u, 0x01u, 0x62u, 0x00u, 0x2bu, - 0x01u, 0xd0u, 0x1bu, 0x88u, 0x83u, 0x81u, 0xf0u, 0xbdu, 0xe0u, 0x03u, 0x00u, 0x08u, 0xc4u, 0x05u, 0x00u, 0x08u, + 0x01u, 0xd0u, 0x1bu, 0x88u, 0x83u, 0x81u, 0xf0u, 0xbdu, 0xf0u, 0x03u, 0x00u, 0x08u, 0xd4u, 0x05u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x83u, 0x68u, 0x85u, 0xb0u, 0x02u, 0xadu, 0x2bu, 0x80u, 0x15u, 0x4bu, 0x02u, 0x68u, 0x1bu, 0x68u, 0x06u, 0x6au, 0x9bu, 0x8eu, 0x47u, 0x6au, 0x9bu, 0x18u, 0x6bu, 0x80u, 0x43u, 0x68u, 0x00u, 0x95u, 0x82u, 0x6au, 0xc1u, 0x6au, 0x04u, 0x00u, 0x03u, 0x93u, 0x03u, 0x69u, 0xc0u, 0x68u, 0xffu, 0xf7u, 0xbdu, 0xffu, 0x00u, 0x21u, 0x3bu, 0x00u, 0x0au, 0x00u, 0x00u, 0x91u, 0x30u, 0x00u, 0xffu, 0xf7u, 0xb6u, 0xffu, 0x21u, 0x6bu, 0x28u, 0x00u, - 0x00u, 0xf0u, 0xc6u, 0xfau, 0x00u, 0x22u, 0xabu, 0x5eu, 0x00u, 0x2bu, 0x06u, 0xdbu, 0x1fu, 0x22u, 0x13u, 0x40u, + 0x00u, 0xf0u, 0xcau, 0xfau, 0x00u, 0x22u, 0xabu, 0x5eu, 0x00u, 0x2bu, 0x06u, 0xdbu, 0x1fu, 0x22u, 0x13u, 0x40u, 0x1eu, 0x3au, 0x9au, 0x40u, 0x13u, 0x00u, 0x03u, 0x4au, 0x13u, 0x60u, 0x05u, 0xb0u, 0xf0u, 0xbdu, 0xc0u, 0x46u, - 0xc4u, 0x05u, 0x00u, 0x08u, 0x00u, 0xe1u, 0x00u, 0xe0u, 0xf7u, 0xb5u, 0x2cu, 0x25u, 0x13u, 0x4cu, 0x68u, 0x43u, + 0xd4u, 0x05u, 0x00u, 0x08u, 0x00u, 0xe1u, 0x00u, 0xe0u, 0xf7u, 0xb5u, 0x2cu, 0x25u, 0x13u, 0x4cu, 0x68u, 0x43u, 0x26u, 0x68u, 0x69u, 0x43u, 0x34u, 0x18u, 0x25u, 0x69u, 0x01u, 0x93u, 0x71u, 0x18u, 0x00u, 0x2du, 0x19u, 0xd0u, 0x88u, 0x69u, 0x00u, 0x28u, 0x18u, 0xd1u, 0x2eu, 0x68u, 0x00u, 0x2eu, 0x15u, 0xdau, 0x67u, 0x68u, 0x01u, 0x24u, 0x26u, 0x00u, 0x4bu, 0x68u, 0x9eu, 0x40u, 0xb4u, 0x46u, 0x13u, 0x68u, 0x9eu, 0xb2u, 0x63u, 0x46u, 0x1bu, 0x04u, 0x1eu, 0x43u, 0x16u, 0x60u, 0xeau, 0x60u, 0x8cu, 0x61u, 0xbcu, 0x40u, 0x01u, 0x9bu, 0xa4u, 0xb2u, 0x4bu, 0x62u, - 0xacu, 0x60u, 0xfeu, 0xbdu, 0x02u, 0x48u, 0xfcu, 0xe7u, 0x02u, 0x48u, 0xfau, 0xe7u, 0xe0u, 0x03u, 0x00u, 0x08u, + 0xacu, 0x60u, 0xfeu, 0xbdu, 0x02u, 0x48u, 0xfcu, 0xe7u, 0x02u, 0x48u, 0xfau, 0xe7u, 0xf0u, 0x03u, 0x00u, 0x08u, 0x04u, 0x02u, 0x8au, 0x00u, 0x07u, 0x02u, 0x8au, 0x00u, 0x73u, 0xb5u, 0x00u, 0x26u, 0x42u, 0x69u, 0x04u, 0x00u, 0xd5u, 0x68u, 0x01u, 0x96u, 0x2bu, 0x0cu, 0xb3u, 0x42u, 0x21u, 0xd0u, 0x1bu, 0x04u, 0x13u, 0x60u, 0x13u, 0x68u, 0x19u, 0x4bu, 0x00u, 0x69u, 0x1bu, 0x68u, 0xb0u, 0x33u, 0x1bu, 0x68u, 0xc3u, 0x18u, 0x1bu, 0x68u, 0xb3u, 0x42u, @@ -99,35 +99,35 @@ const uint8_t cy_m0p_image[] = { 0x00u, 0x2bu, 0x00u, 0xd0u, 0x98u, 0x47u, 0x31u, 0x00u, 0x20u, 0x69u, 0xffu, 0xf7u, 0x0du, 0xffu, 0xadu, 0xb2u, 0x00u, 0x2du, 0x09u, 0xd0u, 0x63u, 0x69u, 0x1du, 0x60u, 0x00u, 0x25u, 0x1bu, 0x68u, 0x63u, 0x6au, 0xabu, 0x42u, 0x05u, 0xd0u, 0x98u, 0x47u, 0x65u, 0x62u, 0xa5u, 0x61u, 0x63u, 0x69u, 0x1bu, 0x68u, 0x73u, 0xbdu, 0xa3u, 0x6au, - 0x00u, 0x2bu, 0xf8u, 0xd0u, 0x98u, 0x47u, 0xf6u, 0xe7u, 0xc4u, 0x05u, 0x00u, 0x08u, 0x2cu, 0x23u, 0x10u, 0xb5u, + 0x00u, 0x2bu, 0xf8u, 0xd0u, 0x98u, 0x47u, 0xf6u, 0xe7u, 0xd4u, 0x05u, 0x00u, 0x08u, 0x2cu, 0x23u, 0x10u, 0xb5u, 0x43u, 0x43u, 0x03u, 0x4au, 0x10u, 0x68u, 0xc0u, 0x18u, 0xffu, 0xf7u, 0xb6u, 0xffu, 0x10u, 0xbdu, 0xc0u, 0x46u, - 0xe0u, 0x03u, 0x00u, 0x08u, 0xf8u, 0xb5u, 0x19u, 0x4bu, 0x0fu, 0x00u, 0x1bu, 0x68u, 0x1au, 0x00u, 0x2eu, 0x32u, + 0xf0u, 0x03u, 0x00u, 0x08u, 0xf8u, 0xb5u, 0x19u, 0x4bu, 0x0fu, 0x00u, 0x1bu, 0x68u, 0x1au, 0x00u, 0x2eu, 0x32u, 0x12u, 0x78u, 0x82u, 0x42u, 0x27u, 0xd9u, 0x00u, 0x29u, 0x25u, 0xd0u, 0x1fu, 0x25u, 0x0au, 0x68u, 0x15u, 0x40u, 0x21u, 0xd1u, 0x19u, 0x00u, 0xacu, 0x31u, 0x0cu, 0x88u, 0x11u, 0x4eu, 0x60u, 0x43u, 0x1cu, 0x6au, 0xd2u, 0x08u, - 0x04u, 0x19u, 0x29u, 0x00u, 0x78u, 0x68u, 0x34u, 0x60u, 0x00u, 0xf0u, 0x0cu, 0xffu, 0x29u, 0x00u, 0x20u, 0x00u, + 0x04u, 0x19u, 0x29u, 0x00u, 0x78u, 0x68u, 0x34u, 0x60u, 0x00u, 0xf0u, 0x10u, 0xffu, 0x29u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xcau, 0xfeu, 0x3au, 0x00u, 0x29u, 0x00u, 0x30u, 0x68u, 0xffu, 0xf7u, 0xd7u, 0xfeu, 0x04u, 0x1eu, 0x07u, 0xd1u, 0x01u, 0x00u, 0x30u, 0x68u, 0xffu, 0xf7u, 0xbfu, 0xfeu, 0x03u, 0x00u, 0x20u, 0x00u, 0x00u, 0x2bu, - 0x00u, 0xd0u, 0x04u, 0x48u, 0xf8u, 0xbdu, 0x04u, 0x48u, 0xfcu, 0xe7u, 0xc0u, 0x46u, 0xc4u, 0x05u, 0x00u, 0x08u, - 0xe4u, 0x03u, 0x00u, 0x08u, 0x01u, 0x01u, 0x8au, 0x00u, 0x03u, 0x01u, 0x8au, 0x00u, 0x10u, 0xb5u, 0x00u, 0x2au, + 0x00u, 0xd0u, 0x04u, 0x48u, 0xf8u, 0xbdu, 0x04u, 0x48u, 0xfcu, 0xe7u, 0xc0u, 0x46u, 0xd4u, 0x05u, 0x00u, 0x08u, + 0xf4u, 0x03u, 0x00u, 0x08u, 0x01u, 0x01u, 0x8au, 0x00u, 0x03u, 0x01u, 0x8au, 0x00u, 0x10u, 0xb5u, 0x00u, 0x2au, 0x0du, 0xd1u, 0x00u, 0x29u, 0x14u, 0xd1u, 0x0bu, 0x4bu, 0x1au, 0x68u, 0x13u, 0x00u, 0xacu, 0x33u, 0x1bu, 0x88u, 0x58u, 0x43u, 0x13u, 0x6au, 0xc0u, 0x18u, 0x08u, 0x4bu, 0x18u, 0x60u, 0x08u, 0x00u, 0x10u, 0xbdu, 0x00u, 0x29u, 0x06u, 0xd0u, 0x06u, 0x4bu, 0x19u, 0x60u, 0x19u, 0x00u, 0x5au, 0x60u, 0xffu, 0xf7u, 0xabu, 0xffu, 0xf5u, 0xe7u, - 0x03u, 0x48u, 0xf3u, 0xe7u, 0xc4u, 0x05u, 0x00u, 0x08u, 0xe4u, 0x03u, 0x00u, 0x08u, 0x78u, 0x03u, 0x00u, 0x08u, + 0x03u, 0x48u, 0xf3u, 0xe7u, 0xd4u, 0x05u, 0x00u, 0x08u, 0xf4u, 0x03u, 0x00u, 0x08u, 0x88u, 0x03u, 0x00u, 0x08u, 0x03u, 0x01u, 0x8au, 0x00u, 0xf7u, 0xb5u, 0x18u, 0x4fu, 0x04u, 0x00u, 0x3bu, 0x68u, 0x01u, 0x91u, 0xdeu, 0x68u, 0x33u, 0x68u, 0x83u, 0x42u, 0x26u, 0xd9u, 0x00u, 0x25u, 0xa9u, 0x42u, 0x02u, 0xd1u, 0xffu, 0xf7u, 0xadu, 0xfdu, 0x05u, 0x00u, 0x38u, 0x68u, 0x03u, 0x68u, 0x00u, 0x2bu, 0x1au, 0xdau, 0x1fu, 0x22u, 0x01u, 0x23u, 0x22u, 0x40u, 0x93u, 0x40u, 0x64u, 0x09u, 0x72u, 0x68u, 0xa4u, 0x00u, 0x14u, 0x19u, 0x22u, 0x68u, 0x13u, 0x42u, 0x0du, 0xd0u, 0x9au, 0x43u, 0x22u, 0x60u, 0x00u, 0x24u, 0x00u, 0x21u, 0xffu, 0xf7u, 0x66u, 0xfeu, 0x01u, 0x9bu, 0x00u, 0x2bu, 0x02u, 0xd1u, 0x28u, 0x00u, 0xffu, 0xf7u, 0x95u, 0xfdu, 0x20u, 0x00u, 0xfeu, 0xbdu, 0x03u, 0x4cu, 0xf2u, 0xe7u, - 0x03u, 0x4cu, 0xf3u, 0xe7u, 0x03u, 0x4cu, 0xf7u, 0xe7u, 0xe4u, 0x03u, 0x00u, 0x08u, 0x02u, 0x01u, 0x88u, 0x00u, + 0x03u, 0x4cu, 0xf3u, 0xe7u, 0x03u, 0x4cu, 0xf7u, 0xe7u, 0xf4u, 0x03u, 0x00u, 0x08u, 0x02u, 0x01u, 0x88u, 0x00u, 0x03u, 0x01u, 0x88u, 0x00u, 0x04u, 0x01u, 0x8au, 0x00u, 0x0au, 0x4bu, 0x1bu, 0x68u, 0xdbu, 0x68u, 0x1au, 0x68u, 0x82u, 0x42u, 0x0du, 0xd9u, 0x59u, 0x68u, 0x1fu, 0x23u, 0x42u, 0x09u, 0x18u, 0x40u, 0x1eu, 0x3bu, 0x83u, 0x40u, 0x92u, 0x00u, 0x50u, 0x58u, 0x18u, 0x40u, 0x43u, 0x1eu, 0x98u, 0x41u, 0x03u, 0x4bu, 0xc0u, 0x18u, 0x70u, 0x47u, - 0x02u, 0x48u, 0xfcu, 0xe7u, 0xe4u, 0x03u, 0x00u, 0x08u, 0x00u, 0x01u, 0x88u, 0x00u, 0x04u, 0x01u, 0x8au, 0x00u, + 0x02u, 0x48u, 0xfcu, 0xe7u, 0xf4u, 0x03u, 0x00u, 0x08u, 0x00u, 0x01u, 0x88u, 0x00u, 0x04u, 0x01u, 0x8au, 0x00u, 0xa6u, 0x22u, 0x05u, 0x49u, 0xd2u, 0x00u, 0x8bu, 0x58u, 0x02u, 0x20u, 0xdbu, 0x43u, 0x9bu, 0x07u, 0x02u, 0xd0u, 0x01u, 0x23u, 0x88u, 0x58u, 0x18u, 0x40u, 0x70u, 0x47u, 0x00u, 0x00u, 0x26u, 0x40u, 0x10u, 0xb5u, 0xffu, 0xf7u, 0xefu, 0xffu, 0x00u, 0x23u, 0x02u, 0x28u, 0x01u, 0xd1u, 0x01u, 0x4bu, 0x1bu, 0x68u, 0x18u, 0x00u, 0x10u, 0xbdu, - 0xe8u, 0x03u, 0x00u, 0x08u, 0x09u, 0x4au, 0x83u, 0x00u, 0x9bu, 0x18u, 0xd0u, 0x22u, 0x92u, 0x00u, 0x98u, 0x58u, + 0xf8u, 0x03u, 0x00u, 0x08u, 0x09u, 0x4au, 0x83u, 0x00u, 0x9bu, 0x18u, 0xd0u, 0x22u, 0x92u, 0x00u, 0x98u, 0x58u, 0x07u, 0x22u, 0x10u, 0x40u, 0x04u, 0x28u, 0x07u, 0xd1u, 0xc0u, 0x22u, 0x92u, 0x00u, 0x98u, 0x58u, 0x1fu, 0x23u, 0x03u, 0x40u, 0x80u, 0x20u, 0x40u, 0x00u, 0x18u, 0x43u, 0x70u, 0x47u, 0xc0u, 0x46u, 0x00u, 0x00u, 0x26u, 0x40u, 0x10u, 0xb5u, 0xffu, 0xf7u, 0xe7u, 0xffu, 0x02u, 0x28u, 0x1cu, 0xd0u, 0x05u, 0xd8u, 0x00u, 0x28u, 0x14u, 0xd0u, @@ -136,7 +136,7 @@ const uint8_t cy_m0p_image[] = { 0x0cu, 0x4bu, 0xd0u, 0x58u, 0xc0u, 0x0fu, 0xc0u, 0x03u, 0x00u, 0xe0u, 0x0bu, 0x48u, 0x10u, 0xbdu, 0x0bu, 0x4bu, 0x18u, 0x68u, 0xfbu, 0xe7u, 0xffu, 0xf7u, 0xbau, 0xffu, 0xf8u, 0xe7u, 0x09u, 0x4bu, 0x18u, 0x69u, 0x04u, 0x23u, 0x18u, 0x40u, 0xf3u, 0xd0u, 0x80u, 0x20u, 0x00u, 0x02u, 0xf0u, 0xe7u, 0x01u, 0x4au, 0x05u, 0x4bu, 0xe8u, 0xe7u, - 0x00u, 0x00u, 0x26u, 0x40u, 0x0cu, 0x05u, 0x00u, 0x00u, 0x00u, 0x12u, 0x7au, 0x00u, 0xecu, 0x03u, 0x00u, 0x08u, + 0x00u, 0x00u, 0x26u, 0x40u, 0x0cu, 0x05u, 0x00u, 0x00u, 0x00u, 0x12u, 0x7au, 0x00u, 0xfcu, 0x03u, 0x00u, 0x08u, 0x00u, 0x00u, 0x27u, 0x40u, 0x3cu, 0x05u, 0x00u, 0x00u, 0xb0u, 0x23u, 0x15u, 0x4au, 0xdbu, 0x00u, 0xd3u, 0x58u, 0x10u, 0xb5u, 0x99u, 0x03u, 0xdbu, 0x01u, 0xdbu, 0x0fu, 0x89u, 0x0bu, 0xc3u, 0x71u, 0x11u, 0x4bu, 0x01u, 0x60u, 0xd3u, 0x58u, 0x0fu, 0x24u, 0xd9u, 0x04u, 0xdbu, 0x01u, 0xdbu, 0x0du, 0x03u, 0x81u, 0xb1u, 0x23u, 0xdbu, 0x00u, @@ -148,258 +148,259 @@ const uint8_t cy_m0p_image[] = { 0x80u, 0x30u, 0xffu, 0x30u, 0x0bu, 0x4bu, 0x80u, 0x00u, 0xc3u, 0x58u, 0x1au, 0x40u, 0x0au, 0x70u, 0x1au, 0x0cu, 0x22u, 0x40u, 0x18u, 0x0au, 0x8au, 0x70u, 0x1au, 0x01u, 0x20u, 0x40u, 0xe2u, 0x40u, 0x48u, 0x70u, 0x00u, 0x20u, 0x9bu, 0x00u, 0x9bu, 0x0fu, 0xcau, 0x70u, 0x0bu, 0x71u, 0x10u, 0xbdu, 0x03u, 0x48u, 0xfcu, 0xe7u, 0xc0u, 0x46u, - 0xc4u, 0x05u, 0x00u, 0x08u, 0x00u, 0x00u, 0x26u, 0x40u, 0x01u, 0x00u, 0x4au, 0x00u, 0xf0u, 0xb5u, 0x87u, 0xb0u, - 0x04u, 0x00u, 0xffu, 0xf7u, 0x65u, 0xffu, 0x06u, 0x00u, 0x00u, 0x2cu, 0x34u, 0xd1u, 0x01u, 0xadu, 0x14u, 0x22u, - 0x21u, 0x00u, 0x28u, 0x00u, 0x00u, 0xf0u, 0x9eu, 0xfdu, 0x28u, 0x00u, 0xffu, 0xf7u, 0x95u, 0xffu, 0xb0u, 0x23u, - 0x25u, 0x4au, 0xdbu, 0x00u, 0xd3u, 0x58u, 0x00u, 0x2bu, 0x03u, 0xdau, 0xacu, 0x7bu, 0x02u, 0x3cu, 0x63u, 0x1eu, + 0xd4u, 0x05u, 0x00u, 0x08u, 0x00u, 0x00u, 0x26u, 0x40u, 0x01u, 0x00u, 0x4au, 0x00u, 0xf0u, 0xb5u, 0x87u, 0xb0u, + 0x04u, 0x00u, 0xffu, 0xf7u, 0x65u, 0xffu, 0x06u, 0x00u, 0x00u, 0x2cu, 0x38u, 0xd1u, 0x01u, 0xadu, 0x14u, 0x22u, + 0x21u, 0x00u, 0x28u, 0x00u, 0x00u, 0xf0u, 0xa2u, 0xfdu, 0x28u, 0x00u, 0xffu, 0xf7u, 0x95u, 0xffu, 0xb0u, 0x23u, + 0x27u, 0x4au, 0xdbu, 0x00u, 0xd3u, 0x58u, 0x00u, 0x2bu, 0x03u, 0xdau, 0xacu, 0x7bu, 0x02u, 0x3cu, 0x63u, 0x1eu, 0x9cu, 0x41u, 0xeau, 0x79u, 0x01u, 0x9fu, 0x53u, 0x1eu, 0x9au, 0x41u, 0xa8u, 0x88u, 0x01u, 0x32u, 0x00u, 0x2cu, - 0x16u, 0xd0u, 0x00u, 0x23u, 0x19u, 0x00u, 0x00u, 0xf0u, 0x6fu, 0xfcu, 0x00u, 0x23u, 0x0cu, 0x00u, 0x05u, 0x00u, - 0x3au, 0x00u, 0x30u, 0x00u, 0x19u, 0x00u, 0x00u, 0xf0u, 0x67u, 0xfcu, 0xe6u, 0x07u, 0x6au, 0x08u, 0x32u, 0x43u, - 0x63u, 0x08u, 0x80u, 0x18u, 0x59u, 0x41u, 0x2au, 0x00u, 0x23u, 0x00u, 0x00u, 0xf0u, 0x3du, 0xfcu, 0x06u, 0x00u, - 0x30u, 0x00u, 0x07u, 0xb0u, 0xf0u, 0xbdu, 0x11u, 0x4bu, 0x1bu, 0x68u, 0x3bu, 0x33u, 0x1bu, 0x78u, 0xa3u, 0x42u, - 0xf6u, 0xd3u, 0x01u, 0xadu, 0x05u, 0x22u, 0x00u, 0x21u, 0x28u, 0x00u, 0x00u, 0xf0u, 0x63u, 0xfdu, 0x20u, 0x00u, - 0x29u, 0x00u, 0x80u, 0x34u, 0xffu, 0xf7u, 0x8au, 0xffu, 0xffu, 0x34u, 0x07u, 0x4bu, 0xa4u, 0x00u, 0xe3u, 0x58u, - 0x00u, 0x24u, 0xa3u, 0x42u, 0x03u, 0xdau, 0x2cu, 0x79u, 0x02u, 0x3cu, 0x63u, 0x1eu, 0x9cu, 0x41u, 0x2fu, 0x78u, - 0x68u, 0x78u, 0xaau, 0x78u, 0xc3u, 0xe7u, 0xc0u, 0x46u, 0x00u, 0x00u, 0x26u, 0x40u, 0xc4u, 0x05u, 0x00u, 0x08u, - 0xe0u, 0x22u, 0x10u, 0xb5u, 0x01u, 0x24u, 0x09u, 0x4bu, 0x80u, 0x00u, 0x92u, 0x00u, 0xc0u, 0x18u, 0x83u, 0x58u, - 0x80u, 0x58u, 0x9bu, 0x06u, 0x9bu, 0x0fu, 0x9cu, 0x40u, 0x0fu, 0x23u, 0x18u, 0x40u, 0xffu, 0xf7u, 0x8eu, 0xffu, - 0x63u, 0x08u, 0x18u, 0x18u, 0x21u, 0x00u, 0x00u, 0xf0u, 0x73u, 0xfbu, 0x10u, 0xbdu, 0x00u, 0x00u, 0x26u, 0x40u, - 0x14u, 0x4bu, 0x30u, 0xb5u, 0x1au, 0x68u, 0x07u, 0x24u, 0x13u, 0x00u, 0x28u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, - 0x15u, 0xd8u, 0x83u, 0x08u, 0x1du, 0x00u, 0xa5u, 0x43u, 0x2cu, 0x1eu, 0x0fu, 0xd1u, 0x03u, 0x34u, 0x20u, 0x40u, - 0xa0u, 0x40u, 0x81u, 0x40u, 0x12u, 0x68u, 0x9bu, 0x00u, 0x20u, 0x32u, 0xd3u, 0x18u, 0x0au, 0x00u, 0xffu, 0x21u, - 0x81u, 0x40u, 0x1cu, 0x68u, 0x62u, 0x40u, 0x11u, 0x40u, 0x61u, 0x40u, 0x19u, 0x60u, 0x30u, 0xbdu, 0x80u, 0x23u, - 0x20u, 0x40u, 0x1bu, 0x06u, 0x18u, 0x43u, 0x80u, 0x23u, 0x9bu, 0x01u, 0x12u, 0x68u, 0xc9u, 0x18u, 0x89u, 0x00u, - 0x88u, 0x50u, 0xf3u, 0xe7u, 0xc4u, 0x05u, 0x00u, 0x08u, 0x06u, 0x4bu, 0x9au, 0x68u, 0x03u, 0x00u, 0x06u, 0x48u, - 0x10u, 0x33u, 0x9bu, 0x00u, 0x82u, 0x42u, 0x02u, 0xd1u, 0x98u, 0x58u, 0x99u, 0x50u, 0x70u, 0x47u, 0x03u, 0x4au, - 0xd0u, 0x58u, 0xfbu, 0xe7u, 0x00u, 0xedu, 0x00u, 0xe0u, 0x00u, 0x00u, 0x00u, 0x08u, 0x00u, 0x00u, 0x00u, 0x10u, - 0xf8u, 0xb5u, 0x06u, 0x00u, 0x0du, 0x00u, 0x00u, 0x28u, 0x3au, 0xd0u, 0x00u, 0x23u, 0xc0u, 0x5eu, 0x00u, 0x28u, - 0x28u, 0xdbu, 0x71u, 0x88u, 0xffu, 0xf7u, 0xb4u, 0xffu, 0x00u, 0x24u, 0xffu, 0x22u, 0x03u, 0x27u, 0x94u, 0x46u, - 0x00u, 0x23u, 0xf0u, 0x5eu, 0x71u, 0x68u, 0x83u, 0xb2u, 0x1fu, 0x40u, 0xffu, 0x00u, 0x66u, 0x46u, 0xbau, 0x40u, - 0x89u, 0x01u, 0x31u, 0x40u, 0xd2u, 0x43u, 0xb9u, 0x40u, 0x00u, 0x28u, 0x15u, 0xdbu, 0x11u, 0x4eu, 0x83u, 0x08u, - 0x9bu, 0x00u, 0x9bu, 0x19u, 0xc0u, 0x26u, 0xb6u, 0x00u, 0x9fu, 0x59u, 0x3au, 0x40u, 0x11u, 0x43u, 0x99u, 0x51u, - 0x0du, 0x4bu, 0x9au, 0x68u, 0x0du, 0x4bu, 0x9au, 0x42u, 0x02u, 0xd1u, 0x29u, 0x00u, 0xffu, 0xf7u, 0xbcu, 0xffu, - 0x20u, 0x00u, 0xf8u, 0xbdu, 0x0au, 0x4cu, 0xd8u, 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0x00u, 0x08u, 0x10u, 0x00u, 0x00u, 0x08u, 0x00u, 0x00u, 0x00u, + 0x04u, 0x00u, 0x00u, 0x00u, 0x04u, 0x10u, 0x00u, 0x00u, 0x00u, 0x12u, 0x00u, 0x00u, 0x04u, 0x21u, 0x00u, 0x00u, + 0x00u, 0x21u, 0x00u, 0x00u, 0x00u, 0x16u, 0x00u, 0x00u, 0x40u, 0x11u, 0x40u, 0x02u, 0xc4u, 0x13u, 0x00u, 0x13u, + 0x80u, 0x13u, 0xa0u, 0x13u, 0x20u, 0x00u, 0x00u, 0x00u, 0x1cu, 0x00u, 0x00u, 0x00u, 0x03u, 0x00u, 0x00u, 0x00u, + 0x01u, 0x00u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x05u, 0x03u, 0x60u, 0x00u, + 0x04u, 0x00u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0x00u, + 0x06u, 0x04u, 0x60u, 0x00u, 0x08u, 0x00u, 0x00u, 0x00u, 0xb4u, 0x05u, 0x00u, 0x08u, 0xadu, 0x0du, 0x00u, 0x10u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0xfdu, 0xffu, 0x7fu, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x10u, + 0x00u, 0x00u, 0x00u, 0x08u, 0x80u, 0x00u, 0x00u, 0x00u, 0x4cu, 0x14u, 0x00u, 0x10u, 0x80u, 0x00u, 0x00u, 0x08u, + 0x08u, 0x03u, 0x00u, 0x00u, 0xc0u, 0x03u, 0x00u, 0x08u, 0x18u, 0x02u, 0x00u, 0x00u, 0x00u, 0x09u, 0x3du, 0x00u, + 0x00u, 0x12u, 0x7au, 0x00u, 0x00u, 0x09u, 0x3du, 0x00u, 0x00u, 0x00u, 0xd0u, 0x07u, 0xa0u, 0x0fu, 0x00u, 0x00u, + 0x04u, 0x00u, 0x00u, 0x00u, 0xa9u, 0x00u, 0x00u, 0x10u, 0x81u, 0x00u, 0x00u, 0x10u, 0x02u, 0x4au, 0x13u, 0x68u, + 0x00u, 0x2bu, 0xfcu, 0xdbu, 0x70u, 0x47u, 0xc0u, 0x46u, 0x00u, 0x01u, 0x26u, 0x40u, 0x80u, 0xb2u, 0x30u, 0xb5u, + 0xc0u, 0x00u, 0x20u, 0xd0u, 0x10u, 0x4bu, 0x07u, 0x22u, 0x1cu, 0x68u, 0x23u, 0x00u, 0xacu, 0x33u, 0x1bu, 0x88u, + 0x5au, 0x43u, 0x23u, 0x6au, 0xd3u, 0x18u, 0x19u, 0x68u, 0x00u, 0x29u, 0xfcu, 0xdau, 0x3eu, 0x21u, 0x0bu, 0x4bu, + 0x06u, 0x25u, 0x19u, 0x60u, 0x0au, 0x4bu, 0x0bu, 0x49u, 0x19u, 0x60u, 0xa3u, 0x21u, 0x0au, 0x4bu, 0xc9u, 0x00u, + 0x5du, 0x50u, 0x0au, 0x49u, 0x58u, 0x50u, 0x58u, 0x58u, 0x20u, 0x6au, 0x12u, 0x18u, 0x00u, 0x20u, 0x50u, 0x60u, + 0x5au, 0x58u, 0x00u, 0x2au, 0xfcu, 0xdau, 0x30u, 0xbdu, 0xd4u, 0x05u, 0x00u, 0x08u, 0x04u, 0x01u, 0x26u, 0x40u, + 0x08u, 0x01u, 0x26u, 0x40u, 0x1eu, 0x1fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x26u, 0x40u, 0x1cu, 0x05u, 0x00u, 0x00u, + 0x10u, 0xb5u, 0x43u, 0x78u, 0xffu, 0x2bu, 0x11u, 0xd1u, 0x00u, 0xf0u, 0x14u, 0xf9u, 0x04u, 0x00u, 0x03u, 0x20u, + 0x00u, 0xf0u, 0x00u, 0xf9u, 0xc3u, 0x68u, 0x5au, 0x68u, 0x01u, 0x23u, 0x11u, 0x68u, 0x19u, 0x43u, 0x11u, 0x60u, + 0x11u, 0x68u, 0x19u, 0x42u, 0xfcu, 0xd1u, 0x20u, 0x00u, 0x00u, 0xf0u, 0x1cu, 0xf9u, 0x10u, 0xbdu, 0xf7u, 0xb5u, + 0x00u, 0x90u, 0x00u, 0x20u, 0x01u, 0x91u, 0x00u, 0xf0u, 0xedu, 0xf8u, 0x3fu, 0x4du, 0x06u, 0x00u, 0x2bu, 0x68u, + 0x1au, 0x00u, 0x4cu, 0x33u, 0xb0u, 0x32u, 0x14u, 0x68u, 0x1bu, 0x78u, 0x04u, 0x19u, 0x00u, 0x2bu, 0x5au, 0xd0u, + 0x00u, 0xf0u, 0xe8u, 0xf8u, 0x07u, 0x00u, 0x03u, 0x28u, 0x1bu, 0xd0u, 0x00u, 0xf0u, 0xebu, 0xf8u, 0x37u, 0x4au, + 0x37u, 0x4bu, 0x05u, 0x00u, 0xd3u, 0x58u, 0x00u, 0x2bu, 0x3eu, 0xdau, 0x36u, 0x4au, 0x01u, 0x21u, 0x30u, 0x00u, + 0x00u, 0xf0u, 0xc0u, 0xf8u, 0x00u, 0x28u, 0x37u, 0xd1u, 0x01u, 0x98u, 0xffu, 0xf7u, 0x8fu, 0xffu, 0x00u, 0x9bu, + 0x00u, 0x2bu, 0x3eu, 0xd0u, 0x23u, 0x68u, 0x00u, 0x2bu, 0xfcu, 0xdbu, 0x00u, 0xf0u, 0xbbu, 0xf8u, 0x04u, 0x00u, + 0x2bu, 0xe0u, 0x06u, 0x20u, 0x00u, 0xf0u, 0xbeu, 0xf8u, 0x2bu, 0x68u, 0xb0u, 0x33u, 0x1bu, 0x68u, 0xc0u, 0x18u, + 0x03u, 0x68u, 0x00u, 0x2bu, 0x02u, 0xdau, 0x28u, 0x4cu, 0x20u, 0x00u, 0xfeu, 0xbdu, 0x00u, 0x20u, 0x00u, 0xf0u, + 0xc9u, 0xf8u, 0x26u, 0x4bu, 0x98u, 0x42u, 0xf6u, 0xd0u, 0x00u, 0x23u, 0x25u, 0x4au, 0x19u, 0x00u, 0x12u, 0x68u, + 0x01u, 0x20u, 0x00u, 0xf0u, 0x8fu, 0xf8u, 0x00u, 0x25u, 0xa8u, 0x42u, 0xecu, 0xd1u, 0x00u, 0x20u, 0x00u, 0xf0u, + 0xb9u, 0xf8u, 0x1eu, 0x4au, 0x1fu, 0x4bu, 0x90u, 0x42u, 0x03u, 0xd0u, 0x9du, 0x42u, 0xe3u, 0xd0u, 0x01u, 0x35u, + 0xf4u, 0xe7u, 0x9du, 0x42u, 0xb9u, 0xd1u, 0xdeu, 0xe7u, 0x17u, 0x4cu, 0x03u, 0x2fu, 0x05u, 0xd1u, 0x01u, 0x21u, + 0x00u, 0x20u, 0x00u, 0xf0u, 0xafu, 0xf8u, 0x00u, 0x28u, 0xf9u, 0xd1u, 0x28u, 0x00u, 0x00u, 0xf0u, 0xb2u, 0xf8u, + 0xd2u, 0xe7u, 0x15u, 0x4cu, 0xf1u, 0xe7u, 0x00u, 0xf0u, 0x95u, 0xf8u, 0x0eu, 0x4au, 0x05u, 0x00u, 0x01u, 0x21u, + 0x30u, 0x00u, 0x00u, 0xf0u, 0x6fu, 0xf8u, 0x00u, 0x28u, 0x09u, 0xd1u, 0x00u, 0x9bu, 0x00u, 0x2bu, 0x08u, 0xd0u, + 0x23u, 0x68u, 0x00u, 0x2bu, 0xfcu, 0xdbu, 0x00u, 0xf0u, 0x6du, 0xf8u, 0x04u, 0x00u, 0xe5u, 0xe7u, 0x06u, 0x4cu, + 0xe3u, 0xe7u, 0x09u, 0x4cu, 0xe1u, 0xe7u, 0xc0u, 0x46u, 0xd4u, 0x05u, 0x00u, 0x08u, 0x00u, 0x00u, 0x26u, 0x40u, + 0x1cu, 0x05u, 0x00u, 0x00u, 0xdcu, 0x03u, 0x00u, 0x08u, 0x05u, 0x00u, 0x52u, 0x00u, 0x01u, 0x01u, 0x88u, 0x00u, + 0xecu, 0x03u, 0x00u, 0x08u, 0xf0u, 0x49u, 0x02u, 0x00u, 0x01u, 0x00u, 0x50u, 0x00u, 0x18u, 0x4bu, 0xf7u, 0xb5u, + 0x1bu, 0x68u, 0x18u, 0x4au, 0x5cu, 0x68u, 0x04u, 0x23u, 0x11u, 0x69u, 0x0bu, 0x43u, 0x13u, 0x61u, 0x01u, 0x28u, + 0x24u, 0xd0u, 0x30u, 0xbfu, 0x23u, 0x00u, 0xfcu, 0x33u, 0x1bu, 0x69u, 0x00u, 0x2bu, 0x1du, 0xd1u, 0xa3u, 0x20u, + 0x11u, 0x4bu, 0x12u, 0x49u, 0x12u, 0x4au, 0xc0u, 0x00u, 0x0fu, 0x68u, 0x1eu, 0x58u, 0x15u, 0x68u, 0x01u, 0x95u, + 0x10u, 0x4du, 0x0du, 0x60u, 0x06u, 0x25u, 0x1du, 0x50u, 0x3eu, 0x20u, 0x10u, 0x60u, 0x0eu, 0x48u, 0x3eu, 0x35u, + 0x1du, 0x50u, 0x1du, 0x58u, 0x00u, 0x2du, 0xfcu, 0xdau, 0x0cu, 0x48u, 0xfcu, 0x34u, 0x20u, 0x61u, 0x0fu, 0x60u, + 0xa3u, 0x21u, 0xc9u, 0x00u, 0x5eu, 0x50u, 0x01u, 0x9bu, 0x13u, 0x60u, 0xf7u, 0xbdu, 0x20u, 0xbfu, 0xd9u, 0xe7u, + 0xd4u, 0x05u, 0x00u, 0x08u, 0x00u, 0xedu, 0x00u, 0xe0u, 0x00u, 0x00u, 0x26u, 0x40u, 0x08u, 0x01u, 0x26u, 0x40u, + 0x04u, 0x01u, 0x26u, 0x40u, 0x1eu, 0x1fu, 0x00u, 0x00u, 0x1cu, 0x05u, 0x00u, 0x00u, 0xaau, 0xaau, 0xaau, 0xaau, + 0x00u, 0x00u, 0x00u, 0x00u, 0x01u, 0xb4u, 0x02u, 0x48u, 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, + 0xa9u, 0x03u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, + 0x9du, 0x02u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, + 0x39u, 0x02u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, + 0x75u, 0x01u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, + 0xe5u, 0x0eu, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, + 0xdbu, 0x00u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, + 0xd9u, 0x05u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, + 0x65u, 0x05u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, + 0xe3u, 0x00u, 0x00u, 0x10u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, }; #endif /* defined(CY_DEVICE_PSOC6A512K) */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/COMPONENT_CM0P_SLEEP/psoc6_04_cm0p_sleep.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/COMPONENT_CM0P_SLEEP/psoc6_04_cm0p_sleep.c index 2fb1162ab3..e6a541dec6 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/COMPONENT_CM0P_SLEEP/psoc6_04_cm0p_sleep.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/COMPONENT_CM0P_SLEEP/psoc6_04_cm0p_sleep.c @@ -36,22 +36,22 @@ const uint8_t cy_m0p_image[] = { 0x49u, 0x01u, 0x00u, 0x10u, 0x49u, 0x01u, 0x00u, 0x10u, 0x49u, 0x01u, 0x00u, 0x10u, 0x49u, 0x01u, 0x00u, 0x10u, 0x49u, 0x01u, 0x00u, 0x10u, 0x49u, 0x01u, 0x00u, 0x10u, 0x49u, 0x01u, 0x00u, 0x10u, 0x49u, 0x01u, 0x00u, 0x10u, 0x10u, 0xb5u, 0x06u, 0x4cu, 0x23u, 0x78u, 0x00u, 0x2bu, 0x07u, 0xd1u, 0x05u, 0x4bu, 0x00u, 0x2bu, 0x02u, 0xd0u, - 0x04u, 0x48u, 0x00u, 0xe0u, 0x00u, 0xbfu, 0x01u, 0x23u, 0x23u, 0x70u, 0x10u, 0xbdu, 0xb0u, 0x03u, 0x00u, 0x08u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x18u, 0x14u, 0x00u, 0x10u, 0x04u, 0x4bu, 0x10u, 0xb5u, 0x00u, 0x2bu, 0x03u, 0xd0u, + 0x04u, 0x48u, 0x00u, 0xe0u, 0x00u, 0xbfu, 0x01u, 0x23u, 0x23u, 0x70u, 0x10u, 0xbdu, 0xc0u, 0x03u, 0x00u, 0x08u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x20u, 0x14u, 0x00u, 0x10u, 0x04u, 0x4bu, 0x10u, 0xb5u, 0x00u, 0x2bu, 0x03u, 0xd0u, 0x03u, 0x49u, 0x04u, 0x48u, 0x00u, 0xe0u, 0x00u, 0xbfu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0x00u, 0x00u, 0x00u, 0x00u, - 0xb4u, 0x03u, 0x00u, 0x08u, 0x18u, 0x14u, 0x00u, 0x10u, 0x02u, 0x30u, 0x80u, 0x08u, 0x03u, 0xd0u, 0x01u, 0x30u, + 0xc4u, 0x03u, 0x00u, 0x08u, 0x20u, 0x14u, 0x00u, 0x10u, 0x02u, 0x30u, 0x80u, 0x08u, 0x03u, 0xd0u, 0x01u, 0x30u, 0x02u, 0x38u, 0xfcu, 0xd1u, 0xc0u, 0x46u, 0xc0u, 0x46u, 0x70u, 0x47u, 0xefu, 0xf3u, 0x10u, 0x80u, 0x72u, 0xb6u, 0x70u, 0x47u, 0x80u, 0xf3u, 0x10u, 0x88u, 0x70u, 0x47u, 0x70u, 0x47u, 0xffu, 0xf7u, 0xfdu, 0xffu, 0x72u, 0xb6u, 0x0fu, 0x4cu, 0x10u, 0x4du, 0xacu, 0x42u, 0x09u, 0xdau, 0x21u, 0x68u, 0x62u, 0x68u, 0xa3u, 0x68u, 0x04u, 0x3bu, 0x02u, 0xdbu, 0xc8u, 0x58u, 0xd0u, 0x50u, 0xfau, 0xe7u, 0x0cu, 0x34u, 0xf3u, 0xe7u, 0x0au, 0x49u, 0x0bu, 0x4au, 0x00u, 0x20u, 0x52u, 0x1au, 0x02u, 0xddu, 0x04u, 0x3au, 0x88u, 0x50u, 0xfcu, 0xdcu, 0x08u, 0x48u, 0x09u, 0x49u, - 0x08u, 0x60u, 0xbfu, 0xf3u, 0x4fu, 0x8fu, 0x00u, 0xf0u, 0x85u, 0xfeu, 0x00u, 0xf0u, 0x2fu, 0xfeu, 0xfeu, 0xe7u, - 0x24u, 0x14u, 0x00u, 0x10u, 0x3cu, 0x14u, 0x00u, 0x10u, 0xb0u, 0x03u, 0x00u, 0x08u, 0xc8u, 0x05u, 0x00u, 0x08u, + 0x08u, 0x60u, 0xbfu, 0xf3u, 0x4fu, 0x8fu, 0x00u, 0xf0u, 0x89u, 0xfeu, 0x00u, 0xf0u, 0x33u, 0xfeu, 0xfeu, 0xe7u, + 0x2cu, 0x14u, 0x00u, 0x10u, 0x44u, 0x14u, 0x00u, 0x10u, 0xc0u, 0x03u, 0x00u, 0x08u, 0xd8u, 0x05u, 0x00u, 0x08u, 0x00u, 0x00u, 0x00u, 0x08u, 0x08u, 0xedu, 0x00u, 0xe0u, 0xfeu, 0xe7u, 0xfeu, 0xe7u, 0x00u, 0xb5u, 0x04u, 0x20u, 0x71u, 0x46u, 0x08u, 0x42u, 0x02u, 0xd0u, 0xefu, 0xf3u, 0x09u, 0x80u, 0x01u, 0xe0u, 0xefu, 0xf3u, 0x08u, 0x80u, - 0x04u, 0x30u, 0x00u, 0xf0u, 0x21u, 0xfcu, 0xfeu, 0xe7u, 0x01u, 0x4bu, 0x18u, 0x60u, 0x70u, 0x47u, 0xc0u, 0x46u, - 0xc4u, 0x05u, 0x00u, 0x08u, 0x04u, 0x4bu, 0x1bu, 0x68u, 0x1au, 0x00u, 0xacu, 0x32u, 0x12u, 0x88u, 0x1bu, 0x6au, - 0x50u, 0x43u, 0xc0u, 0x18u, 0x70u, 0x47u, 0xc0u, 0x46u, 0xc4u, 0x05u, 0x00u, 0x08u, 0x1du, 0x4bu, 0x98u, 0x42u, + 0x04u, 0x30u, 0x00u, 0xf0u, 0x25u, 0xfcu, 0xfeu, 0xe7u, 0x01u, 0x4bu, 0x18u, 0x60u, 0x70u, 0x47u, 0xc0u, 0x46u, + 0xd4u, 0x05u, 0x00u, 0x08u, 0x04u, 0x4bu, 0x1bu, 0x68u, 0x1au, 0x00u, 0xacu, 0x32u, 0x12u, 0x88u, 0x1bu, 0x6au, + 0x50u, 0x43u, 0xc0u, 0x18u, 0x70u, 0x47u, 0xc0u, 0x46u, 0xd4u, 0x05u, 0x00u, 0x08u, 0x1du, 0x4bu, 0x98u, 0x42u, 0x0fu, 0xd0u, 0x10u, 0xd8u, 0x40u, 0x28u, 0x2fu, 0xd0u, 0x05u, 0xd8u, 0x00u, 0x28u, 0x30u, 0xd0u, 0x10u, 0x28u, 0x28u, 0xd0u, 0x19u, 0x48u, 0x1eu, 0xe0u, 0x80u, 0x28u, 0x28u, 0xd0u, 0x80u, 0x23u, 0x5bu, 0x00u, 0x98u, 0x42u, 0xf7u, 0xd1u, 0x14u, 0x48u, 0x16u, 0xe0u, 0x15u, 0x4bu, 0x98u, 0x42u, 0x14u, 0xd0u, 0x08u, 0xd8u, 0xa0u, 0x23u, @@ -65,32 +65,32 @@ const uint8_t cy_m0p_image[] = { 0x02u, 0x00u, 0x50u, 0x00u, 0x05u, 0x00u, 0x52u, 0x00u, 0x10u, 0xb5u, 0x00u, 0x20u, 0xffu, 0xf7u, 0x9au, 0xffu, 0x0au, 0x4bu, 0x1cu, 0x68u, 0x23u, 0x00u, 0xb0u, 0x33u, 0x1bu, 0x68u, 0xc0u, 0x18u, 0x03u, 0x68u, 0x00u, 0x2bu, 0x0au, 0xdbu, 0x07u, 0x4bu, 0x18u, 0x68u, 0xffu, 0xf7u, 0x99u, 0xffu, 0x01u, 0x22u, 0x63u, 0x68u, 0x9au, 0x60u, - 0x9au, 0x68u, 0x00u, 0x2au, 0xfcu, 0xd1u, 0x10u, 0xbdu, 0x02u, 0x48u, 0xfcu, 0xe7u, 0xc4u, 0x05u, 0x00u, 0x08u, - 0xccu, 0x03u, 0x00u, 0x08u, 0x02u, 0x00u, 0x50u, 0x00u, 0x06u, 0x4bu, 0x1bu, 0x68u, 0xb0u, 0x33u, 0x1bu, 0x68u, + 0x9au, 0x68u, 0x00u, 0x2au, 0xfcu, 0xd1u, 0x10u, 0xbdu, 0x02u, 0x48u, 0xfcu, 0xe7u, 0xd4u, 0x05u, 0x00u, 0x08u, + 0xdcu, 0x03u, 0x00u, 0x08u, 0x02u, 0x00u, 0x50u, 0x00u, 0x06u, 0x4bu, 0x1bu, 0x68u, 0xb0u, 0x33u, 0x1bu, 0x68u, 0xc3u, 0x18u, 0x1bu, 0x68u, 0x00u, 0x2bu, 0x03u, 0xdau, 0x89u, 0xb2u, 0x41u, 0x60u, 0x00u, 0x20u, 0x70u, 0x47u, - 0x01u, 0x48u, 0xfcu, 0xe7u, 0xc4u, 0x05u, 0x00u, 0x08u, 0x01u, 0x00u, 0x8au, 0x00u, 0x03u, 0x68u, 0x00u, 0x2bu, + 0x01u, 0x48u, 0xfcu, 0xe7u, 0xd4u, 0x05u, 0x00u, 0x08u, 0x01u, 0x00u, 0x8au, 0x00u, 0x03u, 0x68u, 0x00u, 0x2bu, 0x04u, 0xdau, 0x89u, 0xb2u, 0xc2u, 0x60u, 0x81u, 0x60u, 0x00u, 0x20u, 0x70u, 0x47u, 0x00u, 0x48u, 0xfcu, 0xe7u, 0x01u, 0x00u, 0x8au, 0x00u, 0x06u, 0x4bu, 0x1bu, 0x68u, 0xb0u, 0x33u, 0x1bu, 0x68u, 0xc3u, 0x18u, 0x1bu, 0x68u, 0x00u, 0x2bu, 0x03u, 0xdau, 0xc3u, 0x68u, 0x00u, 0x20u, 0x0bu, 0x60u, 0x70u, 0x47u, 0x01u, 0x48u, 0xfcu, 0xe7u, - 0xc4u, 0x05u, 0x00u, 0x08u, 0x01u, 0x00u, 0x8au, 0x00u, 0x02u, 0x4bu, 0x1au, 0x68u, 0x00u, 0x2au, 0x00u, 0xd1u, - 0x18u, 0x60u, 0x70u, 0x47u, 0xe0u, 0x03u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x2cu, 0x24u, 0x60u, 0x43u, 0x12u, 0x4cu, + 0xd4u, 0x05u, 0x00u, 0x08u, 0x01u, 0x00u, 0x8au, 0x00u, 0x02u, 0x4bu, 0x1au, 0x68u, 0x00u, 0x2au, 0x00u, 0xd1u, + 0x18u, 0x60u, 0x70u, 0x47u, 0xf0u, 0x03u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x2cu, 0x24u, 0x60u, 0x43u, 0x12u, 0x4cu, 0x1fu, 0x00u, 0x24u, 0x68u, 0x1eu, 0x0au, 0x20u, 0x18u, 0xffu, 0x24u, 0x27u, 0x40u, 0x34u, 0x40u, 0x0fu, 0x4eu, 0x1bu, 0x0cu, 0x35u, 0x68u, 0x07u, 0x60u, 0x2eu, 0x6au, 0x44u, 0x60u, 0x83u, 0x60u, 0xacu, 0x35u, 0x2du, 0x88u, 0x80u, 0x34u, 0x6fu, 0x43u, 0x64u, 0x01u, 0x34u, 0x19u, 0xbfu, 0x19u, 0x1eu, 0x04u, 0x33u, 0x43u, 0x07u, 0x61u, 0x44u, 0x61u, 0xa3u, 0x60u, 0x00u, 0x23u, 0x83u, 0x61u, 0x05u, 0x9bu, 0xc2u, 0x61u, 0x01u, 0x62u, 0x00u, 0x2bu, - 0x01u, 0xd0u, 0x1bu, 0x88u, 0x83u, 0x81u, 0xf0u, 0xbdu, 0xe0u, 0x03u, 0x00u, 0x08u, 0xc4u, 0x05u, 0x00u, 0x08u, + 0x01u, 0xd0u, 0x1bu, 0x88u, 0x83u, 0x81u, 0xf0u, 0xbdu, 0xf0u, 0x03u, 0x00u, 0x08u, 0xd4u, 0x05u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x83u, 0x68u, 0x85u, 0xb0u, 0x02u, 0xadu, 0x2bu, 0x80u, 0x15u, 0x4bu, 0x02u, 0x68u, 0x1bu, 0x68u, 0x06u, 0x6au, 0x9bu, 0x8eu, 0x47u, 0x6au, 0x9bu, 0x18u, 0x6bu, 0x80u, 0x43u, 0x68u, 0x00u, 0x95u, 0x82u, 0x6au, 0xc1u, 0x6au, 0x04u, 0x00u, 0x03u, 0x93u, 0x03u, 0x69u, 0xc0u, 0x68u, 0xffu, 0xf7u, 0xbdu, 0xffu, 0x00u, 0x21u, 0x3bu, 0x00u, 0x0au, 0x00u, 0x00u, 0x91u, 0x30u, 0x00u, 0xffu, 0xf7u, 0xb6u, 0xffu, 0x21u, 0x6bu, 0x28u, 0x00u, - 0x00u, 0xf0u, 0xc6u, 0xfau, 0x00u, 0x22u, 0xabu, 0x5eu, 0x00u, 0x2bu, 0x06u, 0xdbu, 0x1fu, 0x22u, 0x13u, 0x40u, + 0x00u, 0xf0u, 0xcau, 0xfau, 0x00u, 0x22u, 0xabu, 0x5eu, 0x00u, 0x2bu, 0x06u, 0xdbu, 0x1fu, 0x22u, 0x13u, 0x40u, 0x1eu, 0x3au, 0x9au, 0x40u, 0x13u, 0x00u, 0x03u, 0x4au, 0x13u, 0x60u, 0x05u, 0xb0u, 0xf0u, 0xbdu, 0xc0u, 0x46u, - 0xc4u, 0x05u, 0x00u, 0x08u, 0x00u, 0xe1u, 0x00u, 0xe0u, 0xf7u, 0xb5u, 0x2cu, 0x25u, 0x13u, 0x4cu, 0x68u, 0x43u, + 0xd4u, 0x05u, 0x00u, 0x08u, 0x00u, 0xe1u, 0x00u, 0xe0u, 0xf7u, 0xb5u, 0x2cu, 0x25u, 0x13u, 0x4cu, 0x68u, 0x43u, 0x26u, 0x68u, 0x69u, 0x43u, 0x34u, 0x18u, 0x25u, 0x69u, 0x01u, 0x93u, 0x71u, 0x18u, 0x00u, 0x2du, 0x19u, 0xd0u, 0x88u, 0x69u, 0x00u, 0x28u, 0x18u, 0xd1u, 0x2eu, 0x68u, 0x00u, 0x2eu, 0x15u, 0xdau, 0x67u, 0x68u, 0x01u, 0x24u, 0x26u, 0x00u, 0x4bu, 0x68u, 0x9eu, 0x40u, 0xb4u, 0x46u, 0x13u, 0x68u, 0x9eu, 0xb2u, 0x63u, 0x46u, 0x1bu, 0x04u, 0x1eu, 0x43u, 0x16u, 0x60u, 0xeau, 0x60u, 0x8cu, 0x61u, 0xbcu, 0x40u, 0x01u, 0x9bu, 0xa4u, 0xb2u, 0x4bu, 0x62u, - 0xacu, 0x60u, 0xfeu, 0xbdu, 0x02u, 0x48u, 0xfcu, 0xe7u, 0x02u, 0x48u, 0xfau, 0xe7u, 0xe0u, 0x03u, 0x00u, 0x08u, + 0xacu, 0x60u, 0xfeu, 0xbdu, 0x02u, 0x48u, 0xfcu, 0xe7u, 0x02u, 0x48u, 0xfau, 0xe7u, 0xf0u, 0x03u, 0x00u, 0x08u, 0x04u, 0x02u, 0x8au, 0x00u, 0x07u, 0x02u, 0x8au, 0x00u, 0x73u, 0xb5u, 0x00u, 0x26u, 0x42u, 0x69u, 0x04u, 0x00u, 0xd5u, 0x68u, 0x01u, 0x96u, 0x2bu, 0x0cu, 0xb3u, 0x42u, 0x21u, 0xd0u, 0x1bu, 0x04u, 0x13u, 0x60u, 0x13u, 0x68u, 0x19u, 0x4bu, 0x00u, 0x69u, 0x1bu, 0x68u, 0xb0u, 0x33u, 0x1bu, 0x68u, 0xc3u, 0x18u, 0x1bu, 0x68u, 0xb3u, 0x42u, @@ -99,35 +99,35 @@ const uint8_t cy_m0p_image[] = { 0x00u, 0x2bu, 0x00u, 0xd0u, 0x98u, 0x47u, 0x31u, 0x00u, 0x20u, 0x69u, 0xffu, 0xf7u, 0x0du, 0xffu, 0xadu, 0xb2u, 0x00u, 0x2du, 0x09u, 0xd0u, 0x63u, 0x69u, 0x1du, 0x60u, 0x00u, 0x25u, 0x1bu, 0x68u, 0x63u, 0x6au, 0xabu, 0x42u, 0x05u, 0xd0u, 0x98u, 0x47u, 0x65u, 0x62u, 0xa5u, 0x61u, 0x63u, 0x69u, 0x1bu, 0x68u, 0x73u, 0xbdu, 0xa3u, 0x6au, - 0x00u, 0x2bu, 0xf8u, 0xd0u, 0x98u, 0x47u, 0xf6u, 0xe7u, 0xc4u, 0x05u, 0x00u, 0x08u, 0x2cu, 0x23u, 0x10u, 0xb5u, + 0x00u, 0x2bu, 0xf8u, 0xd0u, 0x98u, 0x47u, 0xf6u, 0xe7u, 0xd4u, 0x05u, 0x00u, 0x08u, 0x2cu, 0x23u, 0x10u, 0xb5u, 0x43u, 0x43u, 0x03u, 0x4au, 0x10u, 0x68u, 0xc0u, 0x18u, 0xffu, 0xf7u, 0xb6u, 0xffu, 0x10u, 0xbdu, 0xc0u, 0x46u, - 0xe0u, 0x03u, 0x00u, 0x08u, 0xf8u, 0xb5u, 0x19u, 0x4bu, 0x0fu, 0x00u, 0x1bu, 0x68u, 0x1au, 0x00u, 0x2eu, 0x32u, + 0xf0u, 0x03u, 0x00u, 0x08u, 0xf8u, 0xb5u, 0x19u, 0x4bu, 0x0fu, 0x00u, 0x1bu, 0x68u, 0x1au, 0x00u, 0x2eu, 0x32u, 0x12u, 0x78u, 0x82u, 0x42u, 0x27u, 0xd9u, 0x00u, 0x29u, 0x25u, 0xd0u, 0x1fu, 0x25u, 0x0au, 0x68u, 0x15u, 0x40u, 0x21u, 0xd1u, 0x19u, 0x00u, 0xacu, 0x31u, 0x0cu, 0x88u, 0x11u, 0x4eu, 0x60u, 0x43u, 0x1cu, 0x6au, 0xd2u, 0x08u, - 0x04u, 0x19u, 0x29u, 0x00u, 0x78u, 0x68u, 0x34u, 0x60u, 0x00u, 0xf0u, 0x0cu, 0xffu, 0x29u, 0x00u, 0x20u, 0x00u, + 0x04u, 0x19u, 0x29u, 0x00u, 0x78u, 0x68u, 0x34u, 0x60u, 0x00u, 0xf0u, 0x10u, 0xffu, 0x29u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xcau, 0xfeu, 0x3au, 0x00u, 0x29u, 0x00u, 0x30u, 0x68u, 0xffu, 0xf7u, 0xd7u, 0xfeu, 0x04u, 0x1eu, 0x07u, 0xd1u, 0x01u, 0x00u, 0x30u, 0x68u, 0xffu, 0xf7u, 0xbfu, 0xfeu, 0x03u, 0x00u, 0x20u, 0x00u, 0x00u, 0x2bu, - 0x00u, 0xd0u, 0x04u, 0x48u, 0xf8u, 0xbdu, 0x04u, 0x48u, 0xfcu, 0xe7u, 0xc0u, 0x46u, 0xc4u, 0x05u, 0x00u, 0x08u, - 0xe4u, 0x03u, 0x00u, 0x08u, 0x01u, 0x01u, 0x8au, 0x00u, 0x03u, 0x01u, 0x8au, 0x00u, 0x10u, 0xb5u, 0x00u, 0x2au, + 0x00u, 0xd0u, 0x04u, 0x48u, 0xf8u, 0xbdu, 0x04u, 0x48u, 0xfcu, 0xe7u, 0xc0u, 0x46u, 0xd4u, 0x05u, 0x00u, 0x08u, + 0xf4u, 0x03u, 0x00u, 0x08u, 0x01u, 0x01u, 0x8au, 0x00u, 0x03u, 0x01u, 0x8au, 0x00u, 0x10u, 0xb5u, 0x00u, 0x2au, 0x0du, 0xd1u, 0x00u, 0x29u, 0x14u, 0xd1u, 0x0bu, 0x4bu, 0x1au, 0x68u, 0x13u, 0x00u, 0xacu, 0x33u, 0x1bu, 0x88u, 0x58u, 0x43u, 0x13u, 0x6au, 0xc0u, 0x18u, 0x08u, 0x4bu, 0x18u, 0x60u, 0x08u, 0x00u, 0x10u, 0xbdu, 0x00u, 0x29u, 0x06u, 0xd0u, 0x06u, 0x4bu, 0x19u, 0x60u, 0x19u, 0x00u, 0x5au, 0x60u, 0xffu, 0xf7u, 0xabu, 0xffu, 0xf5u, 0xe7u, - 0x03u, 0x48u, 0xf3u, 0xe7u, 0xc4u, 0x05u, 0x00u, 0x08u, 0xe4u, 0x03u, 0x00u, 0x08u, 0x78u, 0x03u, 0x00u, 0x08u, + 0x03u, 0x48u, 0xf3u, 0xe7u, 0xd4u, 0x05u, 0x00u, 0x08u, 0xf4u, 0x03u, 0x00u, 0x08u, 0x88u, 0x03u, 0x00u, 0x08u, 0x03u, 0x01u, 0x8au, 0x00u, 0xf7u, 0xb5u, 0x18u, 0x4fu, 0x04u, 0x00u, 0x3bu, 0x68u, 0x01u, 0x91u, 0xdeu, 0x68u, 0x33u, 0x68u, 0x83u, 0x42u, 0x26u, 0xd9u, 0x00u, 0x25u, 0xa9u, 0x42u, 0x02u, 0xd1u, 0xffu, 0xf7u, 0xadu, 0xfdu, 0x05u, 0x00u, 0x38u, 0x68u, 0x03u, 0x68u, 0x00u, 0x2bu, 0x1au, 0xdau, 0x1fu, 0x22u, 0x01u, 0x23u, 0x22u, 0x40u, 0x93u, 0x40u, 0x64u, 0x09u, 0x72u, 0x68u, 0xa4u, 0x00u, 0x14u, 0x19u, 0x22u, 0x68u, 0x13u, 0x42u, 0x0du, 0xd0u, 0x9au, 0x43u, 0x22u, 0x60u, 0x00u, 0x24u, 0x00u, 0x21u, 0xffu, 0xf7u, 0x66u, 0xfeu, 0x01u, 0x9bu, 0x00u, 0x2bu, 0x02u, 0xd1u, 0x28u, 0x00u, 0xffu, 0xf7u, 0x95u, 0xfdu, 0x20u, 0x00u, 0xfeu, 0xbdu, 0x03u, 0x4cu, 0xf2u, 0xe7u, - 0x03u, 0x4cu, 0xf3u, 0xe7u, 0x03u, 0x4cu, 0xf7u, 0xe7u, 0xe4u, 0x03u, 0x00u, 0x08u, 0x02u, 0x01u, 0x88u, 0x00u, + 0x03u, 0x4cu, 0xf3u, 0xe7u, 0x03u, 0x4cu, 0xf7u, 0xe7u, 0xf4u, 0x03u, 0x00u, 0x08u, 0x02u, 0x01u, 0x88u, 0x00u, 0x03u, 0x01u, 0x88u, 0x00u, 0x04u, 0x01u, 0x8au, 0x00u, 0x0au, 0x4bu, 0x1bu, 0x68u, 0xdbu, 0x68u, 0x1au, 0x68u, 0x82u, 0x42u, 0x0du, 0xd9u, 0x59u, 0x68u, 0x1fu, 0x23u, 0x42u, 0x09u, 0x18u, 0x40u, 0x1eu, 0x3bu, 0x83u, 0x40u, 0x92u, 0x00u, 0x50u, 0x58u, 0x18u, 0x40u, 0x43u, 0x1eu, 0x98u, 0x41u, 0x03u, 0x4bu, 0xc0u, 0x18u, 0x70u, 0x47u, - 0x02u, 0x48u, 0xfcu, 0xe7u, 0xe4u, 0x03u, 0x00u, 0x08u, 0x00u, 0x01u, 0x88u, 0x00u, 0x04u, 0x01u, 0x8au, 0x00u, + 0x02u, 0x48u, 0xfcu, 0xe7u, 0xf4u, 0x03u, 0x00u, 0x08u, 0x00u, 0x01u, 0x88u, 0x00u, 0x04u, 0x01u, 0x8au, 0x00u, 0xa6u, 0x22u, 0x05u, 0x49u, 0xd2u, 0x00u, 0x8bu, 0x58u, 0x02u, 0x20u, 0xdbu, 0x43u, 0x9bu, 0x07u, 0x02u, 0xd0u, 0x01u, 0x23u, 0x88u, 0x58u, 0x18u, 0x40u, 0x70u, 0x47u, 0x00u, 0x00u, 0x26u, 0x40u, 0x10u, 0xb5u, 0xffu, 0xf7u, 0xefu, 0xffu, 0x00u, 0x23u, 0x02u, 0x28u, 0x01u, 0xd1u, 0x01u, 0x4bu, 0x1bu, 0x68u, 0x18u, 0x00u, 0x10u, 0xbdu, - 0xe8u, 0x03u, 0x00u, 0x08u, 0x09u, 0x4au, 0x83u, 0x00u, 0x9bu, 0x18u, 0xd0u, 0x22u, 0x92u, 0x00u, 0x98u, 0x58u, + 0xf8u, 0x03u, 0x00u, 0x08u, 0x09u, 0x4au, 0x83u, 0x00u, 0x9bu, 0x18u, 0xd0u, 0x22u, 0x92u, 0x00u, 0x98u, 0x58u, 0x07u, 0x22u, 0x10u, 0x40u, 0x04u, 0x28u, 0x07u, 0xd1u, 0xc0u, 0x22u, 0x92u, 0x00u, 0x98u, 0x58u, 0x1fu, 0x23u, 0x03u, 0x40u, 0x80u, 0x20u, 0x40u, 0x00u, 0x18u, 0x43u, 0x70u, 0x47u, 0xc0u, 0x46u, 0x00u, 0x00u, 0x26u, 0x40u, 0x10u, 0xb5u, 0xffu, 0xf7u, 0xe7u, 0xffu, 0x02u, 0x28u, 0x1cu, 0xd0u, 0x05u, 0xd8u, 0x00u, 0x28u, 0x14u, 0xd0u, @@ -136,7 +136,7 @@ const uint8_t cy_m0p_image[] = { 0x0cu, 0x4bu, 0xd0u, 0x58u, 0xc0u, 0x0fu, 0xc0u, 0x03u, 0x00u, 0xe0u, 0x0bu, 0x48u, 0x10u, 0xbdu, 0x0bu, 0x4bu, 0x18u, 0x68u, 0xfbu, 0xe7u, 0xffu, 0xf7u, 0xbau, 0xffu, 0xf8u, 0xe7u, 0x09u, 0x4bu, 0x18u, 0x69u, 0x04u, 0x23u, 0x18u, 0x40u, 0xf3u, 0xd0u, 0x80u, 0x20u, 0x00u, 0x02u, 0xf0u, 0xe7u, 0x01u, 0x4au, 0x05u, 0x4bu, 0xe8u, 0xe7u, - 0x00u, 0x00u, 0x26u, 0x40u, 0x0cu, 0x05u, 0x00u, 0x00u, 0x00u, 0x12u, 0x7au, 0x00u, 0xecu, 0x03u, 0x00u, 0x08u, + 0x00u, 0x00u, 0x26u, 0x40u, 0x0cu, 0x05u, 0x00u, 0x00u, 0x00u, 0x12u, 0x7au, 0x00u, 0xfcu, 0x03u, 0x00u, 0x08u, 0x00u, 0x00u, 0x27u, 0x40u, 0x3cu, 0x05u, 0x00u, 0x00u, 0xb0u, 0x23u, 0x15u, 0x4au, 0xdbu, 0x00u, 0xd3u, 0x58u, 0x10u, 0xb5u, 0x99u, 0x03u, 0xdbu, 0x01u, 0xdbu, 0x0fu, 0x89u, 0x0bu, 0xc3u, 0x71u, 0x11u, 0x4bu, 0x01u, 0x60u, 0xd3u, 0x58u, 0x0fu, 0x24u, 0xd9u, 0x04u, 0xdbu, 0x01u, 0xdbu, 0x0du, 0x03u, 0x81u, 0xb1u, 0x23u, 0xdbu, 0x00u, @@ -148,258 +148,259 @@ const uint8_t cy_m0p_image[] = { 0x80u, 0x30u, 0xffu, 0x30u, 0x0bu, 0x4bu, 0x80u, 0x00u, 0xc3u, 0x58u, 0x1au, 0x40u, 0x0au, 0x70u, 0x1au, 0x0cu, 0x22u, 0x40u, 0x18u, 0x0au, 0x8au, 0x70u, 0x1au, 0x01u, 0x20u, 0x40u, 0xe2u, 0x40u, 0x48u, 0x70u, 0x00u, 0x20u, 0x9bu, 0x00u, 0x9bu, 0x0fu, 0xcau, 0x70u, 0x0bu, 0x71u, 0x10u, 0xbdu, 0x03u, 0x48u, 0xfcu, 0xe7u, 0xc0u, 0x46u, - 0xc4u, 0x05u, 0x00u, 0x08u, 0x00u, 0x00u, 0x26u, 0x40u, 0x01u, 0x00u, 0x4au, 0x00u, 0xf0u, 0xb5u, 0x87u, 0xb0u, - 0x04u, 0x00u, 0xffu, 0xf7u, 0x65u, 0xffu, 0x06u, 0x00u, 0x00u, 0x2cu, 0x34u, 0xd1u, 0x01u, 0xadu, 0x14u, 0x22u, - 0x21u, 0x00u, 0x28u, 0x00u, 0x00u, 0xf0u, 0x9eu, 0xfdu, 0x28u, 0x00u, 0xffu, 0xf7u, 0x95u, 0xffu, 0xb0u, 0x23u, - 0x25u, 0x4au, 0xdbu, 0x00u, 0xd3u, 0x58u, 0x00u, 0x2bu, 0x03u, 0xdau, 0xacu, 0x7bu, 0x02u, 0x3cu, 0x63u, 0x1eu, + 0xd4u, 0x05u, 0x00u, 0x08u, 0x00u, 0x00u, 0x26u, 0x40u, 0x01u, 0x00u, 0x4au, 0x00u, 0xf0u, 0xb5u, 0x87u, 0xb0u, + 0x04u, 0x00u, 0xffu, 0xf7u, 0x65u, 0xffu, 0x06u, 0x00u, 0x00u, 0x2cu, 0x38u, 0xd1u, 0x01u, 0xadu, 0x14u, 0x22u, + 0x21u, 0x00u, 0x28u, 0x00u, 0x00u, 0xf0u, 0xa2u, 0xfdu, 0x28u, 0x00u, 0xffu, 0xf7u, 0x95u, 0xffu, 0xb0u, 0x23u, + 0x27u, 0x4au, 0xdbu, 0x00u, 0xd3u, 0x58u, 0x00u, 0x2bu, 0x03u, 0xdau, 0xacu, 0x7bu, 0x02u, 0x3cu, 0x63u, 0x1eu, 0x9cu, 0x41u, 0xeau, 0x79u, 0x01u, 0x9fu, 0x53u, 0x1eu, 0x9au, 0x41u, 0xa8u, 0x88u, 0x01u, 0x32u, 0x00u, 0x2cu, - 0x16u, 0xd0u, 0x00u, 0x23u, 0x19u, 0x00u, 0x00u, 0xf0u, 0x6fu, 0xfcu, 0x00u, 0x23u, 0x0cu, 0x00u, 0x05u, 0x00u, - 0x3au, 0x00u, 0x30u, 0x00u, 0x19u, 0x00u, 0x00u, 0xf0u, 0x67u, 0xfcu, 0xe6u, 0x07u, 0x6au, 0x08u, 0x32u, 0x43u, - 0x63u, 0x08u, 0x80u, 0x18u, 0x59u, 0x41u, 0x2au, 0x00u, 0x23u, 0x00u, 0x00u, 0xf0u, 0x3du, 0xfcu, 0x06u, 0x00u, - 0x30u, 0x00u, 0x07u, 0xb0u, 0xf0u, 0xbdu, 0x11u, 0x4bu, 0x1bu, 0x68u, 0x3bu, 0x33u, 0x1bu, 0x78u, 0xa3u, 0x42u, - 0xf6u, 0xd3u, 0x01u, 0xadu, 0x05u, 0x22u, 0x00u, 0x21u, 0x28u, 0x00u, 0x00u, 0xf0u, 0x63u, 0xfdu, 0x20u, 0x00u, - 0x29u, 0x00u, 0x80u, 0x34u, 0xffu, 0xf7u, 0x8au, 0xffu, 0xffu, 0x34u, 0x07u, 0x4bu, 0xa4u, 0x00u, 0xe3u, 0x58u, - 0x00u, 0x24u, 0xa3u, 0x42u, 0x03u, 0xdau, 0x2cu, 0x79u, 0x02u, 0x3cu, 0x63u, 0x1eu, 0x9cu, 0x41u, 0x2fu, 0x78u, - 0x68u, 0x78u, 0xaau, 0x78u, 0xc3u, 0xe7u, 0xc0u, 0x46u, 0x00u, 0x00u, 0x26u, 0x40u, 0xc4u, 0x05u, 0x00u, 0x08u, - 0xe0u, 0x22u, 0x10u, 0xb5u, 0x01u, 0x24u, 0x09u, 0x4bu, 0x80u, 0x00u, 0x92u, 0x00u, 0xc0u, 0x18u, 0x83u, 0x58u, - 0x80u, 0x58u, 0x9bu, 0x06u, 0x9bu, 0x0fu, 0x9cu, 0x40u, 0x0fu, 0x23u, 0x18u, 0x40u, 0xffu, 0xf7u, 0x8eu, 0xffu, - 0x63u, 0x08u, 0x18u, 0x18u, 0x21u, 0x00u, 0x00u, 0xf0u, 0x73u, 0xfbu, 0x10u, 0xbdu, 0x00u, 0x00u, 0x26u, 0x40u, - 0x14u, 0x4bu, 0x30u, 0xb5u, 0x1au, 0x68u, 0x07u, 0x24u, 0x13u, 0x00u, 0x28u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, - 0x15u, 0xd8u, 0x83u, 0x08u, 0x1du, 0x00u, 0xa5u, 0x43u, 0x2cu, 0x1eu, 0x0fu, 0xd1u, 0x03u, 0x34u, 0x20u, 0x40u, - 0xa0u, 0x40u, 0x81u, 0x40u, 0x12u, 0x68u, 0x9bu, 0x00u, 0x20u, 0x32u, 0xd3u, 0x18u, 0x0au, 0x00u, 0xffu, 0x21u, - 0x81u, 0x40u, 0x1cu, 0x68u, 0x62u, 0x40u, 0x11u, 0x40u, 0x61u, 0x40u, 0x19u, 0x60u, 0x30u, 0xbdu, 0x80u, 0x23u, - 0x20u, 0x40u, 0x1bu, 0x06u, 0x18u, 0x43u, 0x80u, 0x23u, 0x9bu, 0x01u, 0x12u, 0x68u, 0xc9u, 0x18u, 0x89u, 0x00u, - 0x88u, 0x50u, 0xf3u, 0xe7u, 0xc4u, 0x05u, 0x00u, 0x08u, 0x06u, 0x4bu, 0x9au, 0x68u, 0x03u, 0x00u, 0x06u, 0x48u, - 0x10u, 0x33u, 0x9bu, 0x00u, 0x82u, 0x42u, 0x02u, 0xd1u, 0x98u, 0x58u, 0x99u, 0x50u, 0x70u, 0x47u, 0x03u, 0x4au, - 0xd0u, 0x58u, 0xfbu, 0xe7u, 0x00u, 0xedu, 0x00u, 0xe0u, 0x00u, 0x00u, 0x00u, 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0xbfu, + 0xe3u, 0x00u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, + 0xdbu, 0x00u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, + 0x39u, 0x02u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, + 0x65u, 0x05u, 0x00u, 0x10u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, }; #endif /* defined(CY_DEVICE_PSOC6A256K) */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/README.md b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/README.md index 6f8d7eef8f..bfb082126a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/README.md +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/README.md @@ -30,10 +30,17 @@ to specify a particular image. starts CM4 core at CY_CORTEX_M4_APPL_ADDR=0x10020000 and puts CM0+ core into a deep sleep mode. +* [COMPONENT_CM0P_SECURE](./COMPONENT_CM0P_SECURE/README.md) + + This image starts CM4 core at address corresponding + to Secure Boot policy, sets required security settings, + initializes and executes code of Protected Register Access + driver, puts CM0+ core into a deep sleep mode. + ### More information Use the following links for more information, as needed: -* [Cypress](http://www.cypress.com) +* [Cypress Semiconductor, an Infineon Technologies Company](http://www.cypress.com) * [ModusToolbox](https://www.cypress.com/products/modustoolbox-software-environment) --- -Copyright (c) Cypress Semiconductor Corporation, 2019. +Copyright (c) Cypress Semiconductor Corporation, 2020. diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/version.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/version.xml index 4f4f056cff..610f91b941 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/version.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/version.xml @@ -1 +1 @@ -1.1.2.73 +1.2.0.237 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/RELEASE.md b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/RELEASE.md index 9251ec00f6..3b624c4758 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/RELEASE.md +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/RELEASE.md @@ -1,4 +1,4 @@ -# PSoC 6 Peripheral Driver Library v1.5.2 +# PSoC 6 Peripheral Driver Library v1.6.0 Please refer to the [README.md](./README.md) and the [PDL API Reference Manual](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/index.html) @@ -6,22 +6,75 @@ for a complete description of the Peripheral Driver Library. ## New Features -* No new features +* Added support for the PSoC 64 Secure MCU devices. +Limitations for the secure devices are described as a part of the [PRA](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__pra.html) driver. + ## Updated Personalities +* Power - Added possibility to select the Normal/Minimum Current for the both LDO and BUCK Core regulators. -* WiFi - Fix build warning in the generated code. Minor parameter name updates. +## Personalities with patch version updates + + Minor updates to support the PSoC 64 Secure MCU devices + +* Wco +* TimerClk +* TickClk +* SysClock +* SlowClk +* PumpClk +* Pll +* Pin +* Pilo +* PeriClk +* PathMux +* LfClk +* HvIlo +* HfClk +* Fll +* FastClk +* ExtClk +* Eco +* BakClk +* AltHf_BleEco + +## Added Drivers + +* [PRA 1.0](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__pra.html) ## Updated Drivers -* [SD Host 1.50](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__sd__host.html) -* [CTB 1.10.2](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__ctb.html) -* [SysLib 2.50.3](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__syslib.html) +* [Startup 2.80](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__system__config.html) +* [WDT 1.30](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__wdt.html) +* [SysTick 1.20](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__arm__system__timer.html) +* [SysPm 5.10](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__syspm.html) +* [SysLib 2.60](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__syslib.html) +* [SysClk 2.10](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__sysclk.html) +* [SCB 2.50](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__scb.html) +* [LVD 1.20](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__lvd.html) +* [Flash 3.40](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__flash.html) +* [CTB 1.20](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__ctb.html) + +### Drivers with patch version updates + +Minor documentation changes: + +* USBFS 2.20.1 +* TrigMux 1.20.2 +* Tcpwm 1.10.2 +* SysInt 1.30.1 +* SysAnalog 1.10.1 +* SMIF 1.50.1 +* Smart I/O 1.0.1 +* Sd_host 1.50.1 +* Sar 1.20.3 +* Rtc 2.30.1 +* Prot 1.30.3 +* Profiler 1.20.1 ## Known Issues -See the Known Issues section of -[SysLib](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__syslib.html) +[SysClk](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__sysclk.html) driver. ## Defect Fixes diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245w_s3d72.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c4588azi_h675.h similarity index 91% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245w_s3d72.h rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c4588azi_h675.h index 45cc953c17..f8940c6917 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245w_s3d72.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c4588azi_h675.h @@ -1,15 +1,15 @@ /***************************************************************************//** -* \file cy8c6245w_s3d72.h +* \file cy8c4588azi_h675.h * * \brief -* CY8C6245W-S3D72 device header +* CY8C4588AZI-H675 device header * * \note -* Generator version: 1.5.0.1292 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -25,11 +25,11 @@ * limitations under the License. *******************************************************************************/ -#ifndef _CY8C6245W_S3D72_H_ -#define _CY8C6245W_S3D72_H_ +#ifndef _CY8C4588AZI_H675_H_ +#define _CY8C4588AZI_H675_H_ /** -* \addtogroup group_device CY8C6245W-S3D72 +* \addtogroup group_device CY8C4588AZI-H675 * \{ */ @@ -54,7 +54,7 @@ typedef enum { SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ SysTick_IRQn = -1, /*!< -1 System Tick Timer */ - /* CY8C6245W-S3D72 User Interrupt Numbers */ + /* CY8C4588AZI-H675 User Interrupt Numbers */ NvicMux0_IRQn = 0, /*!< 0 [DeepSleep] CPU User Interrupt #0 */ NvicMux1_IRQn = 1, /*!< 1 [DeepSleep] CPU User Interrupt #1 */ NvicMux2_IRQn = 2, /*!< 2 [DeepSleep] CPU User Interrupt #2 */ @@ -63,7 +63,7 @@ typedef enum { NvicMux5_IRQn = 5, /*!< 5 [DeepSleep] CPU User Interrupt #5 */ NvicMux6_IRQn = 6, /*!< 6 [DeepSleep] CPU User Interrupt #6 */ NvicMux7_IRQn = 7, /*!< 7 [DeepSleep] CPU User Interrupt #7 */ - /* CY8C6245W-S3D72 Internal SW Interrupt Numbers */ + /* CY8C4588AZI-H675 Internal SW Interrupt Numbers */ Internal0_IRQn = 8, /*!< 8 [Active] Internal SW Interrupt #0 */ Internal1_IRQn = 9, /*!< 9 [Active] Internal SW Interrupt #1 */ Internal2_IRQn = 10, /*!< 10 [Active] Internal SW Interrupt #2 */ @@ -85,7 +85,7 @@ typedef enum { DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ SysTick_IRQn = -1, /*!< -1 System Tick Timer */ - /* CY8C6245W-S3D72 Peripheral Interrupt Numbers */ + /* CY8C4588AZI-H675 Peripheral Interrupt Numbers */ ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ @@ -122,12 +122,16 @@ typedef enum { cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ - scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ - scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ - scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ - scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ - scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ - scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + pass_interrupt_sar_0_IRQn = 39, /*!< 39 [DeepSleep] SAR ADC0 interrupt */ + pass_interrupt_sar_1_IRQn = 40, /*!< 40 [DeepSleep] SAR ADC1 interrupt */ + pass_interrupt_ctb_IRQn = 41, /*!< 41 [DeepSleep] individual interrupt per CTB */ + pass_interrupt_fifo_0_IRQn = 43, /*!< 43 [DeepSleep] PASS FIFO0 */ + pass_interrupt_fifo_1_IRQn = 44, /*!< 44 [DeepSleep] PASS FIFO1 */ + scb_0_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #2 */ + scb_4_interrupt_IRQn = 49, /*!< 49 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 50, /*!< 50 [Active] Serial Communication Block #5 */ csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ @@ -202,27 +206,26 @@ typedef enum { tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ - tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ - tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ - tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ - tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ - tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ - tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ - tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ - tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ - pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + tcpwm_0_interrupts_256_IRQn = 131, /*!< 131 [Active] TCPWM #0, Counter #256 */ + tcpwm_0_interrupts_257_IRQn = 132, /*!< 132 [Active] TCPWM #0, Counter #257 */ + tcpwm_0_interrupts_258_IRQn = 133, /*!< 133 [Active] TCPWM #0, Counter #258 */ + tcpwm_0_interrupts_259_IRQn = 134, /*!< 134 [Active] TCPWM #0, Counter #259 */ + tcpwm_0_interrupts_260_IRQn = 135, /*!< 135 [Active] TCPWM #0, Counter #260 */ + tcpwm_0_interrupts_261_IRQn = 136, /*!< 136 [Active] TCPWM #0, Counter #261 */ + tcpwm_0_interrupts_262_IRQn = 137, /*!< 137 [Active] TCPWM #0, Counter #262 */ + tcpwm_0_interrupts_263_IRQn = 138, /*!< 138 [Active] TCPWM #0, Counter #263 */ + pass_interrupt_dacs_IRQn = 146, /*!< 146 [Active] Consolidated interrrupt for all DACs */ smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ - sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ - sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ canfd_0_interrupt0_IRQn = 168, /*!< 168 [Active] Can #0, Consolidated interrupt #0 */ canfd_0_interrupts0_0_IRQn = 169, /*!< 169 [Active] CAN #0, Interrupt #0, Channel #0 */ canfd_0_interrupts1_0_IRQn = 170, /*!< 170 [Active] CAN #0, Interrupt #1, Channel #0 */ cpuss_interrupts_dw1_29_IRQn = 171, /*!< 171 [Active] CPUSS DataWire #1, Channel #29 */ cpuss_interrupts_dw1_30_IRQn = 172, /*!< 172 [Active] CPUSS DataWire #1, Channel #30 */ cpuss_interrupts_dw1_31_IRQn = 173, /*!< 173 [Active] CPUSS DataWire #1, Channel #31 */ + cpuss_interrupts_dw0_29_IRQn = 174, /*!< 174 [Active] CPUSS DataWire #0, Channel #29 */ unconnected_IRQn =1023 /*!< 1023 Unconnected */ #endif } IRQn_Type; @@ -233,7 +236,7 @@ typedef enum { (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) -/* CY8C6245W-S3D72 interrupts that can be routed to the CM0+ NVIC */ +/* CY8C4588AZI-H675 interrupts that can be routed to the CM0+ NVIC */ typedef enum { ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ @@ -271,12 +274,16 @@ typedef enum { cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ - scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ - scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ - scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ - scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ - scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ - scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + pass_interrupt_sar_0_IRQn = 39, /*!< 39 [DeepSleep] SAR ADC0 interrupt */ + pass_interrupt_sar_1_IRQn = 40, /*!< 40 [DeepSleep] SAR ADC1 interrupt */ + pass_interrupt_ctb_IRQn = 41, /*!< 41 [DeepSleep] individual interrupt per CTB */ + pass_interrupt_fifo_0_IRQn = 43, /*!< 43 [DeepSleep] PASS FIFO0 */ + pass_interrupt_fifo_1_IRQn = 44, /*!< 44 [DeepSleep] PASS FIFO1 */ + scb_0_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #2 */ + scb_4_interrupt_IRQn = 49, /*!< 49 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 50, /*!< 50 [Active] Serial Communication Block #5 */ csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ @@ -351,27 +358,26 @@ typedef enum { tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ - tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ - tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ - tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ - tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ - tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ - tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ - tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ - tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ - pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + tcpwm_0_interrupts_256_IRQn = 131, /*!< 131 [Active] TCPWM #0, Counter #256 */ + tcpwm_0_interrupts_257_IRQn = 132, /*!< 132 [Active] TCPWM #0, Counter #257 */ + tcpwm_0_interrupts_258_IRQn = 133, /*!< 133 [Active] TCPWM #0, Counter #258 */ + tcpwm_0_interrupts_259_IRQn = 134, /*!< 134 [Active] TCPWM #0, Counter #259 */ + tcpwm_0_interrupts_260_IRQn = 135, /*!< 135 [Active] TCPWM #0, Counter #260 */ + tcpwm_0_interrupts_261_IRQn = 136, /*!< 136 [Active] TCPWM #0, Counter #261 */ + tcpwm_0_interrupts_262_IRQn = 137, /*!< 137 [Active] TCPWM #0, Counter #262 */ + tcpwm_0_interrupts_263_IRQn = 138, /*!< 138 [Active] TCPWM #0, Counter #263 */ + pass_interrupt_dacs_IRQn = 146, /*!< 146 [Active] Consolidated interrrupt for all DACs */ smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ - sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ - sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ canfd_0_interrupt0_IRQn = 168, /*!< 168 [Active] Can #0, Consolidated interrupt #0 */ canfd_0_interrupts0_0_IRQn = 169, /*!< 169 [Active] CAN #0, Interrupt #0, Channel #0 */ canfd_0_interrupts1_0_IRQn = 170, /*!< 170 [Active] CAN #0, Interrupt #1, Channel #0 */ cpuss_interrupts_dw1_29_IRQn = 171, /*!< 171 [Active] CPUSS DataWire #1, Channel #29 */ cpuss_interrupts_dw1_30_IRQn = 172, /*!< 172 [Active] CPUSS DataWire #1, Channel #30 */ cpuss_interrupts_dw1_31_IRQn = 173, /*!< 173 [Active] CPUSS DataWire #1, Channel #31 */ + cpuss_interrupts_dw0_29_IRQn = 174, /*!< 174 [Active] CPUSS DataWire #0, Channel #29 */ disconnected_IRQn =1023 /*!< 1023 Disconnected */ } cy_en_intr_t; @@ -421,50 +427,26 @@ typedef enum { #define CY_ROM_BASE 0x00000000UL #define CY_ROM_SIZE 0x00010000UL #define CY_SRAM_BASE 0x08000000UL -#define CY_SRAM_SIZE 0x00040000UL +#define CY_SRAM_SIZE 0x00020000UL #define CY_FLASH_BASE 0x10000000UL -#define CY_FLASH_SIZE 0x00080000UL +#define CY_FLASH_SIZE 0x00040000UL #define CY_EM_EEPROM_BASE 0x14000000UL -#define CY_EM_EEPROM_SIZE 0x00008000UL -#define CY_XIP_BASE 0x18000000UL -#define CY_XIP_SIZE 0x08000000UL -#define CY_CAN0MRAM_BASE 0x40530000UL -#define CY_CAN0MRAM_SIZE 0x00010000UL +#define CY_EM_EEPROM_SIZE 0x00000000UL #define CY_SFLASH_BASE 0x16000000UL #define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL #define CY_EFUSE_BASE 0x402C0800UL #define CY_EFUSE_SIZE 0x00000200UL +#define CY_CAN0MRAM_BASE 0x40530000UL +#define CY_CAN0MRAM_SIZE 0x00010000UL #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 2u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 7u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 2u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXTTCANFD 1u +#define CY_IP_MXTTCANFD_INSTANCES 1u +#define CY_IP_MXTTCANFD_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 2u @@ -474,42 +456,48 @@ typedef enum { #define CY_IP_M4CPUSS_DMA 1u #define CY_IP_M4CPUSS_DMA_INSTANCES 2u #define CY_IP_M4CPUSS_DMA_VERSION 2u -#define CY_IP_MXCRYPTO 1u -#define CY_IP_MXCRYPTO_INSTANCES 1u -#define CY_IP_MXCRYPTO_VERSION 2u -#define CY_IP_MXSDHC 1u -#define CY_IP_MXSDHC_INSTANCES 1u -#define CY_IP_MXSDHC_VERSION 1u -#define CY_IP_MXTTCANFD 1u -#define CY_IP_MXTTCANFD_INSTANCES 1u -#define CY_IP_MXTTCANFD_VERSION 1u -#define CY_IP_MXLPCOMP 1u -#define CY_IP_MXLPCOMP_INSTANCES 1u -#define CY_IP_MXLPCOMP_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 2u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u -#define CY_IP_MXS40PASS 1u -#define CY_IP_MXS40PASS_INSTANCES 1u -#define CY_IP_MXS40PASS_VERSION 1u -#define CY_IP_MXS40PASS_SAR 1u -#define CY_IP_MXS40PASS_SAR_INSTANCES 1u -#define CY_IP_MXS40PASS_SAR_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u #define CY_IP_MXEFUSE 1u #define CY_IP_MXEFUSE_INSTANCES 1u #define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 2u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 6u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#include "psoc6_03_config.h" -#include "gpio_psoc6_03_100_tqfp.h" +#include "psoc6_04_config.h" +#include "gpio_psoc6_04_64_tqfp.h" -#define CY_DEVICE_PSOC6A512K -#define CY_SILICON_ID 0xE70E1105UL +#define CY_DEVICE_PSOC6A256K +#define CY_SILICON_ID 0xEAFD110EUL #define CY_HF_CLK_MAX_FREQ 150000000UL #define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL @@ -546,6 +534,7 @@ typedef enum { #define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ #define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ #define PERI_TR_GR10 ((PERI_TR_GR_Type*) &PERI->TR_GR[10]) /* 0x4000A800 */ +#define PERI_TR_GR11 ((PERI_TR_GR_Type*) &PERI->TR_GR[11]) /* 0x4000AC00 */ #define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ #define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ #define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ @@ -554,6 +543,7 @@ typedef enum { #define PERI_TR_1TO1_GR5 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[5]) /* 0x4000D400 */ #define PERI_TR_1TO1_GR6 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[6]) /* 0x4000D800 */ #define PERI_TR_1TO1_GR7 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[7]) /* 0x4000DC00 */ +#define PERI_TR_1TO1_GR8 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[8]) /* 0x4000E000 */ /******************************************************************************* * PERI_MS @@ -626,176 +616,175 @@ typedef enum { #define PERI_MS_PPU_FX_IPC_INTR_STRUCT15_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[54]) /* 0x40011580 */ #define PERI_MS_PPU_FX_PROT_SMPU_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[55]) /* 0x400115C0 */ #define PERI_MS_PPU_FX_PROT_MPU0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[56]) /* 0x40011600 */ -#define PERI_MS_PPU_FX_PROT_MPU5_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[57]) /* 0x40011640 */ -#define PERI_MS_PPU_FX_PROT_MPU14_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[58]) /* 0x40011680 */ -#define PERI_MS_PPU_FX_PROT_MPU15_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[59]) /* 0x400116C0 */ -#define PERI_MS_PPU_FX_FLASHC_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[60]) /* 0x40011700 */ -#define PERI_MS_PPU_FX_FLASHC_CMD ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[61]) /* 0x40011740 */ -#define PERI_MS_PPU_FX_FLASHC_DFT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[62]) /* 0x40011780 */ -#define PERI_MS_PPU_FX_FLASHC_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[63]) /* 0x400117C0 */ -#define PERI_MS_PPU_FX_FLASHC_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[64]) /* 0x40011800 */ -#define PERI_MS_PPU_FX_FLASHC_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[65]) /* 0x40011840 */ -#define PERI_MS_PPU_FX_FLASHC_DW0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[66]) /* 0x40011880 */ -#define PERI_MS_PPU_FX_FLASHC_DW1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[67]) /* 0x400118C0 */ -#define PERI_MS_PPU_FX_FLASHC_DMAC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[68]) /* 0x40011900 */ -#define PERI_MS_PPU_FX_FLASHC_EXT_MS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[69]) /* 0x40011940 */ -#define PERI_MS_PPU_FX_FLASHC_FM ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[70]) /* 0x40011980 */ -#define PERI_MS_PPU_FX_SRSS_MAIN1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[71]) /* 0x400119C0 */ -#define PERI_MS_PPU_FX_SRSS_MAIN2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[72]) /* 0x40011A00 */ -#define PERI_MS_PPU_FX_WDT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[73]) /* 0x40011A40 */ -#define PERI_MS_PPU_FX_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[74]) /* 0x40011A80 */ -#define PERI_MS_PPU_FX_SRSS_MAIN3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[75]) /* 0x40011AC0 */ -#define PERI_MS_PPU_FX_SRSS_MAIN4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[76]) /* 0x40011B00 */ -#define PERI_MS_PPU_FX_SRSS_MAIN5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[77]) /* 0x40011B40 */ -#define PERI_MS_PPU_FX_SRSS_MAIN6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[78]) /* 0x40011B80 */ -#define PERI_MS_PPU_FX_SRSS_MAIN7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[79]) /* 0x40011BC0 */ -#define PERI_MS_PPU_FX_BACKUP_BACKUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[80]) /* 0x40011C00 */ -#define PERI_MS_PPU_FX_DW0_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[81]) /* 0x40011C40 */ -#define PERI_MS_PPU_FX_DW1_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[82]) /* 0x40011C80 */ -#define PERI_MS_PPU_FX_DW0_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[83]) /* 0x40011CC0 */ -#define PERI_MS_PPU_FX_DW1_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[84]) /* 0x40011D00 */ -#define PERI_MS_PPU_FX_DW0_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[85]) /* 0x40011D40 */ -#define PERI_MS_PPU_FX_DW0_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[86]) /* 0x40011D80 */ -#define PERI_MS_PPU_FX_DW0_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[87]) /* 0x40011DC0 */ -#define PERI_MS_PPU_FX_DW0_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[88]) /* 0x40011E00 */ -#define PERI_MS_PPU_FX_DW0_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[89]) /* 0x40011E40 */ -#define PERI_MS_PPU_FX_DW0_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[90]) /* 0x40011E80 */ -#define PERI_MS_PPU_FX_DW0_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[91]) /* 0x40011EC0 */ -#define PERI_MS_PPU_FX_DW0_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[92]) /* 0x40011F00 */ -#define PERI_MS_PPU_FX_DW0_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[93]) /* 0x40011F40 */ -#define PERI_MS_PPU_FX_DW0_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[94]) /* 0x40011F80 */ -#define PERI_MS_PPU_FX_DW0_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[95]) /* 0x40011FC0 */ -#define PERI_MS_PPU_FX_DW0_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[96]) /* 0x40012000 */ -#define PERI_MS_PPU_FX_DW0_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[97]) /* 0x40012040 */ -#define PERI_MS_PPU_FX_DW0_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[98]) /* 0x40012080 */ -#define PERI_MS_PPU_FX_DW0_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[99]) /* 0x400120C0 */ -#define PERI_MS_PPU_FX_DW0_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[100]) /* 0x40012100 */ -#define PERI_MS_PPU_FX_DW0_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[101]) /* 0x40012140 */ -#define PERI_MS_PPU_FX_DW0_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[102]) /* 0x40012180 */ -#define PERI_MS_PPU_FX_DW0_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[103]) /* 0x400121C0 */ -#define PERI_MS_PPU_FX_DW0_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[104]) /* 0x40012200 */ -#define PERI_MS_PPU_FX_DW0_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[105]) /* 0x40012240 */ -#define PERI_MS_PPU_FX_DW0_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[106]) /* 0x40012280 */ -#define PERI_MS_PPU_FX_DW0_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[107]) /* 0x400122C0 */ -#define PERI_MS_PPU_FX_DW0_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[108]) /* 0x40012300 */ -#define PERI_MS_PPU_FX_DW0_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[109]) /* 0x40012340 */ -#define PERI_MS_PPU_FX_DW0_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[110]) /* 0x40012380 */ -#define PERI_MS_PPU_FX_DW0_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[111]) /* 0x400123C0 */ -#define PERI_MS_PPU_FX_DW0_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[112]) /* 0x40012400 */ -#define PERI_MS_PPU_FX_DW0_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[113]) /* 0x40012440 */ -#define PERI_MS_PPU_FX_DW1_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[114]) /* 0x40012480 */ -#define PERI_MS_PPU_FX_DW1_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[115]) /* 0x400124C0 */ -#define PERI_MS_PPU_FX_DW1_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[116]) /* 0x40012500 */ -#define PERI_MS_PPU_FX_DW1_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[117]) /* 0x40012540 */ -#define PERI_MS_PPU_FX_DW1_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[118]) /* 0x40012580 */ -#define PERI_MS_PPU_FX_DW1_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[119]) /* 0x400125C0 */ -#define PERI_MS_PPU_FX_DW1_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[120]) /* 0x40012600 */ -#define PERI_MS_PPU_FX_DW1_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[121]) /* 0x40012640 */ -#define PERI_MS_PPU_FX_DW1_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[122]) /* 0x40012680 */ -#define PERI_MS_PPU_FX_DW1_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[123]) /* 0x400126C0 */ -#define PERI_MS_PPU_FX_DW1_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[124]) /* 0x40012700 */ -#define PERI_MS_PPU_FX_DW1_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[125]) /* 0x40012740 */ -#define PERI_MS_PPU_FX_DW1_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[126]) /* 0x40012780 */ -#define PERI_MS_PPU_FX_DW1_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[127]) /* 0x400127C0 */ -#define PERI_MS_PPU_FX_DW1_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[128]) /* 0x40012800 */ -#define PERI_MS_PPU_FX_DW1_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[129]) /* 0x40012840 */ -#define PERI_MS_PPU_FX_DW1_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[130]) /* 0x40012880 */ -#define PERI_MS_PPU_FX_DW1_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[131]) /* 0x400128C0 */ -#define PERI_MS_PPU_FX_DW1_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[132]) /* 0x40012900 */ -#define PERI_MS_PPU_FX_DW1_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[133]) /* 0x40012940 */ -#define PERI_MS_PPU_FX_DW1_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[134]) /* 0x40012980 */ -#define PERI_MS_PPU_FX_DW1_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[135]) /* 0x400129C0 */ -#define PERI_MS_PPU_FX_DW1_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[136]) /* 0x40012A00 */ -#define PERI_MS_PPU_FX_DW1_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[137]) /* 0x40012A40 */ -#define PERI_MS_PPU_FX_DW1_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[138]) /* 0x40012A80 */ -#define PERI_MS_PPU_FX_DW1_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[139]) /* 0x40012AC0 */ -#define PERI_MS_PPU_FX_DW1_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[140]) /* 0x40012B00 */ -#define PERI_MS_PPU_FX_DW1_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[141]) /* 0x40012B40 */ -#define PERI_MS_PPU_FX_DW1_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[142]) /* 0x40012B80 */ -#define PERI_MS_PPU_FX_DW1_CH_STRUCT29_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[143]) /* 0x40012BC0 */ -#define PERI_MS_PPU_FX_DW1_CH_STRUCT30_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[144]) /* 0x40012C00 */ -#define PERI_MS_PPU_FX_DW1_CH_STRUCT31_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[145]) /* 0x40012C40 */ -#define PERI_MS_PPU_FX_DMAC_TOP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[146]) /* 0x40012C80 */ -#define PERI_MS_PPU_FX_DMAC_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[147]) /* 0x40012CC0 */ -#define PERI_MS_PPU_FX_DMAC_CH1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[148]) /* 0x40012D00 */ -#define PERI_MS_PPU_FX_EFUSE_CTL ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[149]) /* 0x40012D40 */ -#define PERI_MS_PPU_FX_EFUSE_DATA ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[150]) /* 0x40012D80 */ -#define PERI_MS_PPU_FX_HSIOM_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[151]) /* 0x40012DC0 */ -#define PERI_MS_PPU_FX_HSIOM_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[152]) /* 0x40012E00 */ -#define PERI_MS_PPU_FX_HSIOM_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[153]) /* 0x40012E40 */ -#define PERI_MS_PPU_FX_HSIOM_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[154]) /* 0x40012E80 */ -#define PERI_MS_PPU_FX_HSIOM_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[155]) /* 0x40012EC0 */ -#define PERI_MS_PPU_FX_HSIOM_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[156]) /* 0x40012F00 */ -#define PERI_MS_PPU_FX_HSIOM_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[157]) /* 0x40012F40 */ -#define PERI_MS_PPU_FX_HSIOM_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[158]) /* 0x40012F80 */ -#define PERI_MS_PPU_FX_HSIOM_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[159]) /* 0x40012FC0 */ -#define PERI_MS_PPU_FX_HSIOM_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[160]) /* 0x40013000 */ -#define PERI_MS_PPU_FX_HSIOM_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[161]) /* 0x40013040 */ -#define PERI_MS_PPU_FX_HSIOM_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[162]) /* 0x40013080 */ -#define PERI_MS_PPU_FX_HSIOM_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[163]) /* 0x400130C0 */ -#define PERI_MS_PPU_FX_HSIOM_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[164]) /* 0x40013100 */ -#define PERI_MS_PPU_FX_HSIOM_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[165]) /* 0x40013140 */ -#define PERI_MS_PPU_FX_HSIOM_AMUX ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[166]) /* 0x40013180 */ -#define PERI_MS_PPU_FX_HSIOM_MON ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[167]) /* 0x400131C0 */ -#define PERI_MS_PPU_FX_GPIO_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[168]) /* 0x40013200 */ -#define PERI_MS_PPU_FX_GPIO_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[169]) /* 0x40013240 */ -#define PERI_MS_PPU_FX_GPIO_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[170]) /* 0x40013280 */ -#define PERI_MS_PPU_FX_GPIO_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[171]) /* 0x400132C0 */ -#define PERI_MS_PPU_FX_GPIO_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[172]) /* 0x40013300 */ -#define PERI_MS_PPU_FX_GPIO_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[173]) /* 0x40013340 */ -#define PERI_MS_PPU_FX_GPIO_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[174]) /* 0x40013380 */ -#define PERI_MS_PPU_FX_GPIO_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[175]) /* 0x400133C0 */ -#define PERI_MS_PPU_FX_GPIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[176]) /* 0x40013400 */ -#define PERI_MS_PPU_FX_GPIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[177]) /* 0x40013440 */ -#define PERI_MS_PPU_FX_GPIO_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[178]) /* 0x40013480 */ -#define PERI_MS_PPU_FX_GPIO_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[179]) /* 0x400134C0 */ -#define PERI_MS_PPU_FX_GPIO_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[180]) /* 0x40013500 */ -#define PERI_MS_PPU_FX_GPIO_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[181]) /* 0x40013540 */ -#define PERI_MS_PPU_FX_GPIO_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[182]) /* 0x40013580 */ -#define PERI_MS_PPU_FX_GPIO_PRT0_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[183]) /* 0x400135C0 */ -#define PERI_MS_PPU_FX_GPIO_PRT1_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[184]) /* 0x40013600 */ -#define PERI_MS_PPU_FX_GPIO_PRT2_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[185]) /* 0x40013640 */ -#define PERI_MS_PPU_FX_GPIO_PRT3_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[186]) /* 0x40013680 */ -#define PERI_MS_PPU_FX_GPIO_PRT4_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[187]) /* 0x400136C0 */ -#define PERI_MS_PPU_FX_GPIO_PRT5_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[188]) /* 0x40013700 */ -#define PERI_MS_PPU_FX_GPIO_PRT6_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[189]) /* 0x40013740 */ -#define PERI_MS_PPU_FX_GPIO_PRT7_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[190]) /* 0x40013780 */ -#define PERI_MS_PPU_FX_GPIO_PRT8_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[191]) /* 0x400137C0 */ -#define PERI_MS_PPU_FX_GPIO_PRT9_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[192]) /* 0x40013800 */ -#define PERI_MS_PPU_FX_GPIO_PRT10_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[193]) /* 0x40013840 */ -#define PERI_MS_PPU_FX_GPIO_PRT11_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[194]) /* 0x40013880 */ -#define PERI_MS_PPU_FX_GPIO_PRT12_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[195]) /* 0x400138C0 */ -#define PERI_MS_PPU_FX_GPIO_PRT13_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[196]) /* 0x40013900 */ -#define PERI_MS_PPU_FX_GPIO_PRT14_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[197]) /* 0x40013940 */ -#define PERI_MS_PPU_FX_GPIO_GPIO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[198]) /* 0x40013980 */ -#define PERI_MS_PPU_FX_GPIO_TEST ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[199]) /* 0x400139C0 */ -#define PERI_MS_PPU_FX_SMARTIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[200]) /* 0x40013A00 */ -#define PERI_MS_PPU_FX_SMARTIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[201]) /* 0x40013A40 */ -#define PERI_MS_PPU_FX_LPCOMP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[202]) /* 0x40013A80 */ -#define PERI_MS_PPU_FX_CSD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[203]) /* 0x40013AC0 */ -#define PERI_MS_PPU_FX_TCPWM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[204]) /* 0x40013B00 */ -#define PERI_MS_PPU_FX_TCPWM1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[205]) /* 0x40013B40 */ -#define PERI_MS_PPU_FX_LCD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[206]) /* 0x40013B80 */ -#define PERI_MS_PPU_FX_USBFS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[207]) /* 0x40013BC0 */ -#define PERI_MS_PPU_FX_SMIF0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[208]) /* 0x40013C00 */ -#define PERI_MS_PPU_FX_SDHC0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[209]) /* 0x40013C40 */ -#define PERI_MS_PPU_FX_CANFD0_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[210]) /* 0x40013C80 */ -#define PERI_MS_PPU_FX_CANFD0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[211]) /* 0x40013CC0 */ -#define PERI_MS_PPU_FX_CANFD0_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[212]) /* 0x40013D00 */ -#define PERI_MS_PPU_FX_SCB0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[213]) /* 0x40013D40 */ -#define PERI_MS_PPU_FX_SCB1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[214]) /* 0x40013D80 */ -#define PERI_MS_PPU_FX_SCB2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[215]) /* 0x40013DC0 */ -#define PERI_MS_PPU_FX_SCB3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[216]) /* 0x40013E00 */ -#define PERI_MS_PPU_FX_SCB4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[217]) /* 0x40013E40 */ -#define PERI_MS_PPU_FX_SCB5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[218]) /* 0x40013E80 */ -#define PERI_MS_PPU_FX_SCB6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[219]) /* 0x40013EC0 */ - -/******************************************************************************* -* CRYPTO -*******************************************************************************/ - -#define CRYPTO_BASE 0x40100000UL -#define CRYPTO ((CRYPTO_Type*) CRYPTO_BASE) /* 0x40100000 */ +#define PERI_MS_PPU_FX_PROT_MPU14_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[57]) /* 0x40011640 */ +#define PERI_MS_PPU_FX_PROT_MPU15_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[58]) /* 0x40011680 */ +#define PERI_MS_PPU_FX_FLASHC_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[59]) /* 0x400116C0 */ +#define PERI_MS_PPU_FX_FLASHC_CMD ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[60]) /* 0x40011700 */ +#define PERI_MS_PPU_FX_FLASHC_DFT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[61]) /* 0x40011740 */ +#define PERI_MS_PPU_FX_FLASHC_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[62]) /* 0x40011780 */ +#define PERI_MS_PPU_FX_FLASHC_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[63]) /* 0x400117C0 */ +#define PERI_MS_PPU_FX_FLASHC_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[64]) /* 0x40011800 */ +#define PERI_MS_PPU_FX_FLASHC_DW0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[65]) /* 0x40011840 */ +#define PERI_MS_PPU_FX_FLASHC_DW1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[66]) /* 0x40011880 */ +#define PERI_MS_PPU_FX_FLASHC_DMAC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[67]) /* 0x400118C0 */ +#define PERI_MS_PPU_FX_FLASHC_FM ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[68]) /* 0x40011900 */ +#define PERI_MS_PPU_FX_SRSS_MAIN1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[69]) /* 0x40011940 */ +#define PERI_MS_PPU_FX_SRSS_MAIN2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[70]) /* 0x40011980 */ +#define PERI_MS_PPU_FX_WDT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[71]) /* 0x400119C0 */ +#define PERI_MS_PPU_FX_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[72]) /* 0x40011A00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[73]) /* 0x40011A40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[74]) /* 0x40011A80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[75]) /* 0x40011AC0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[76]) /* 0x40011B00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[77]) /* 0x40011B40 */ +#define PERI_MS_PPU_FX_BACKUP_BACKUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[78]) /* 0x40011B80 */ +#define PERI_MS_PPU_FX_DW0_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[79]) /* 0x40011BC0 */ +#define PERI_MS_PPU_FX_DW1_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[80]) /* 0x40011C00 */ +#define PERI_MS_PPU_FX_DW0_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[81]) /* 0x40011C40 */ +#define PERI_MS_PPU_FX_DW1_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[82]) /* 0x40011C80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[83]) /* 0x40011CC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[84]) /* 0x40011D00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[85]) /* 0x40011D40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[86]) /* 0x40011D80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[87]) /* 0x40011DC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[88]) /* 0x40011E00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[89]) /* 0x40011E40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[90]) /* 0x40011E80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[91]) /* 0x40011EC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[92]) /* 0x40011F00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[93]) /* 0x40011F40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[94]) /* 0x40011F80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[95]) /* 0x40011FC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[96]) /* 0x40012000 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[97]) /* 0x40012040 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[98]) /* 0x40012080 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[99]) /* 0x400120C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[100]) /* 0x40012100 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[101]) /* 0x40012140 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[102]) /* 0x40012180 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[103]) /* 0x400121C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[104]) /* 0x40012200 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[105]) /* 0x40012240 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[106]) /* 0x40012280 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[107]) /* 0x400122C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[108]) /* 0x40012300 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[109]) /* 0x40012340 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[110]) /* 0x40012380 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[111]) /* 0x400123C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT29_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[112]) /* 0x40012400 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[113]) /* 0x40012440 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[114]) /* 0x40012480 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[115]) /* 0x400124C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[116]) /* 0x40012500 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[117]) /* 0x40012540 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[118]) /* 0x40012580 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[119]) /* 0x400125C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[120]) /* 0x40012600 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[121]) /* 0x40012640 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[122]) /* 0x40012680 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[123]) /* 0x400126C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[124]) /* 0x40012700 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[125]) /* 0x40012740 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[126]) /* 0x40012780 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[127]) /* 0x400127C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[128]) /* 0x40012800 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[129]) /* 0x40012840 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[130]) /* 0x40012880 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[131]) /* 0x400128C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[132]) /* 0x40012900 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[133]) /* 0x40012940 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[134]) /* 0x40012980 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[135]) /* 0x400129C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[136]) /* 0x40012A00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[137]) /* 0x40012A40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[138]) /* 0x40012A80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[139]) /* 0x40012AC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[140]) /* 0x40012B00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[141]) /* 0x40012B40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT29_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[142]) /* 0x40012B80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT30_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[143]) /* 0x40012BC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT31_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[144]) /* 0x40012C00 */ +#define PERI_MS_PPU_FX_DMAC_TOP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[145]) /* 0x40012C40 */ +#define PERI_MS_PPU_FX_DMAC_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[146]) /* 0x40012C80 */ +#define PERI_MS_PPU_FX_DMAC_CH1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[147]) /* 0x40012CC0 */ +#define PERI_MS_PPU_FX_EFUSE_CTL ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[148]) /* 0x40012D00 */ +#define PERI_MS_PPU_FX_EFUSE_DATA ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[149]) /* 0x40012D40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[150]) /* 0x40012D80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[151]) /* 0x40012DC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[152]) /* 0x40012E00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[153]) /* 0x40012E40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[154]) /* 0x40012E80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[155]) /* 0x40012EC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[156]) /* 0x40012F00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[157]) /* 0x40012F40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[158]) /* 0x40012F80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[159]) /* 0x40012FC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[160]) /* 0x40013000 */ +#define PERI_MS_PPU_FX_HSIOM_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[161]) /* 0x40013040 */ +#define PERI_MS_PPU_FX_HSIOM_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[162]) /* 0x40013080 */ +#define PERI_MS_PPU_FX_HSIOM_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[163]) /* 0x400130C0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[164]) /* 0x40013100 */ +#define PERI_MS_PPU_FX_HSIOM_AMUX ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[165]) /* 0x40013140 */ +#define PERI_MS_PPU_FX_HSIOM_MON ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[166]) /* 0x40013180 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[167]) /* 0x400131C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[168]) /* 0x40013200 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[169]) /* 0x40013240 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[170]) /* 0x40013280 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[171]) /* 0x400132C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[172]) /* 0x40013300 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[173]) /* 0x40013340 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[174]) /* 0x40013380 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[175]) /* 0x400133C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[176]) /* 0x40013400 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[177]) /* 0x40013440 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[178]) /* 0x40013480 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[179]) /* 0x400134C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[180]) /* 0x40013500 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[181]) /* 0x40013540 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[182]) /* 0x40013580 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[183]) /* 0x400135C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[184]) /* 0x40013600 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[185]) /* 0x40013640 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[186]) /* 0x40013680 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[187]) /* 0x400136C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[188]) /* 0x40013700 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[189]) /* 0x40013740 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[190]) /* 0x40013780 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[191]) /* 0x400137C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[192]) /* 0x40013800 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[193]) /* 0x40013840 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[194]) /* 0x40013880 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[195]) /* 0x400138C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[196]) /* 0x40013900 */ +#define PERI_MS_PPU_FX_GPIO_GPIO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[197]) /* 0x40013940 */ +#define PERI_MS_PPU_FX_GPIO_TEST ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[198]) /* 0x40013980 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[199]) /* 0x400139C0 */ +#define PERI_MS_PPU_FX_LPCOMP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[200]) /* 0x40013A00 */ +#define PERI_MS_PPU_FX_CSD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[201]) /* 0x40013A40 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT0_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[202]) /* 0x40013A80 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT1_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[203]) /* 0x40013AC0 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT2_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[204]) /* 0x40013B00 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT3_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[205]) /* 0x40013B40 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT0_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[206]) /* 0x40013B80 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT1_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[207]) /* 0x40013BC0 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT2_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[208]) /* 0x40013C00 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT3_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[209]) /* 0x40013C40 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT4_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[210]) /* 0x40013C80 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT5_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[211]) /* 0x40013CC0 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT6_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[212]) /* 0x40013D00 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT7_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[213]) /* 0x40013D40 */ +#define PERI_MS_PPU_FX_LCD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[214]) /* 0x40013D80 */ +#define PERI_MS_PPU_FX_USBFS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[215]) /* 0x40013DC0 */ +#define PERI_MS_PPU_FX_SMIF0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[216]) /* 0x40013E00 */ +#define PERI_MS_PPU_FX_CANFD0_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[217]) /* 0x40013E40 */ +#define PERI_MS_PPU_FX_CANFD0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[218]) /* 0x40013E80 */ +#define PERI_MS_PPU_FX_CANFD0_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[219]) /* 0x40013EC0 */ +#define PERI_MS_PPU_FX_SCB0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[220]) /* 0x40013F00 */ +#define PERI_MS_PPU_FX_SCB1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[221]) /* 0x40013F40 */ +#define PERI_MS_PPU_FX_SCB2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[222]) /* 0x40013F80 */ +#define PERI_MS_PPU_FX_SCB4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[223]) /* 0x40013FC0 */ +#define PERI_MS_PPU_FX_SCB5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[224]) /* 0x40014000 */ +#define PERI_MS_PPU_FX_SCB6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[225]) /* 0x40014040 */ /******************************************************************************* * CPUSS @@ -858,6 +847,7 @@ typedef enum { #define PROT_BASE 0x40230000UL #define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ #define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ #define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ #define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ @@ -874,23 +864,6 @@ typedef enum { #define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ #define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ #define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ -#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ -#define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ -#define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ -#define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ -#define PROT_MPU5_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[3]) /* 0x40235660 */ -#define PROT_MPU5_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[4]) /* 0x40235680 */ -#define PROT_MPU5_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[5]) /* 0x402356A0 */ -#define PROT_MPU5_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[6]) /* 0x402356C0 */ -#define PROT_MPU5_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[7]) /* 0x402356E0 */ -#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ -#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ -#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ -#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ -#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ -#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ -#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ -#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ #define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ #define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ #define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ @@ -907,6 +880,14 @@ typedef enum { #define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ #define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ #define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ /******************************************************************************* * FLASHC @@ -969,6 +950,7 @@ typedef enum { #define DW0_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[26]) /* 0x40288680 */ #define DW0_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[27]) /* 0x402886C0 */ #define DW0_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[28]) /* 0x40288700 */ +#define DW0_CH_STRUCT29 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[29]) /* 0x40288740 */ #define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40298000 */ #define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40298040 */ #define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40298080 */ @@ -1068,7 +1050,6 @@ typedef enum { #define SMARTIO_BASE 0x40320000UL #define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40320000 */ -#define SMARTIO_PRT8 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[8]) /* 0x40320800 */ #define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40320900 */ /******************************************************************************* @@ -1090,21 +1071,21 @@ typedef enum { *******************************************************************************/ #define TCPWM0_BASE 0x40380000UL -#define TCPWM1_BASE 0x40390000UL #define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ -#define TCPWM1 ((TCPWM_Type*) TCPWM1_BASE) /* 0x40390000 */ -#define TCPWM0_CNT0 ((TCPWM_CNT_Type*) &TCPWM0->CNT[0]) /* 0x40380100 */ -#define TCPWM0_CNT1 ((TCPWM_CNT_Type*) &TCPWM0->CNT[1]) /* 0x40380140 */ -#define TCPWM0_CNT2 ((TCPWM_CNT_Type*) &TCPWM0->CNT[2]) /* 0x40380180 */ -#define TCPWM0_CNT3 ((TCPWM_CNT_Type*) &TCPWM0->CNT[3]) /* 0x403801C0 */ -#define TCPWM1_CNT0 ((TCPWM_CNT_Type*) &TCPWM1->CNT[0]) /* 0x40390100 */ -#define TCPWM1_CNT1 ((TCPWM_CNT_Type*) &TCPWM1->CNT[1]) /* 0x40390140 */ -#define TCPWM1_CNT2 ((TCPWM_CNT_Type*) &TCPWM1->CNT[2]) /* 0x40390180 */ -#define TCPWM1_CNT3 ((TCPWM_CNT_Type*) &TCPWM1->CNT[3]) /* 0x403901C0 */ -#define TCPWM1_CNT4 ((TCPWM_CNT_Type*) &TCPWM1->CNT[4]) /* 0x40390200 */ -#define TCPWM1_CNT5 ((TCPWM_CNT_Type*) &TCPWM1->CNT[5]) /* 0x40390240 */ -#define TCPWM1_CNT6 ((TCPWM_CNT_Type*) &TCPWM1->CNT[6]) /* 0x40390280 */ -#define TCPWM1_CNT7 ((TCPWM_CNT_Type*) &TCPWM1->CNT[7]) /* 0x403902C0 */ +#define TCPWM0_GRP0 ((TCPWM_GRP_Type*) &TCPWM0->GRP[0]) /* 0x40380000 */ +#define TCPWM0_GRP1 ((TCPWM_GRP_Type*) &TCPWM0->GRP[1]) /* 0x40388000 */ +#define TCPWM0_GRP0_CNT0 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[0]) /* 0x40380000 */ +#define TCPWM0_GRP0_CNT1 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[1]) /* 0x40380080 */ +#define TCPWM0_GRP0_CNT2 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[2]) /* 0x40380100 */ +#define TCPWM0_GRP0_CNT3 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[3]) /* 0x40380180 */ +#define TCPWM0_GRP1_CNT0 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[0]) /* 0x40388000 */ +#define TCPWM0_GRP1_CNT1 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[1]) /* 0x40388080 */ +#define TCPWM0_GRP1_CNT2 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[2]) /* 0x40388100 */ +#define TCPWM0_GRP1_CNT3 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[3]) /* 0x40388180 */ +#define TCPWM0_GRP1_CNT4 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[4]) /* 0x40388200 */ +#define TCPWM0_GRP1_CNT5 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[5]) /* 0x40388280 */ +#define TCPWM0_GRP1_CNT6 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[6]) /* 0x40388300 */ +#define TCPWM0_GRP1_CNT7 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[7]) /* 0x40388380 */ /******************************************************************************* * LCD @@ -1113,16 +1094,6 @@ typedef enum { #define LCD0_BASE 0x403B0000UL #define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ -/******************************************************************************* -* USBFS -*******************************************************************************/ - -#define USBFS0_BASE 0x403F0000UL -#define USBFS0 ((USBFS_Type*) USBFS0_BASE) /* 0x403F0000 */ -#define USBFS0_USBDEV ((USBFS_USBDEV_Type*) &USBFS0->USBDEV) /* 0x403F0000 */ -#define USBFS0_USBLPM ((USBFS_USBLPM_Type*) &USBFS0->USBLPM) /* 0x403F2000 */ -#define USBFS0_USBHOST ((USBFS_USBHOST_Type*) &USBFS0->USBHOST) /* 0x403F4000 */ - /******************************************************************************* * SMIF *******************************************************************************/ @@ -1133,23 +1104,14 @@ typedef enum { #define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ #define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ -/******************************************************************************* -* SDHC -*******************************************************************************/ - -#define SDHC0_BASE 0x40460000UL -#define SDHC0 ((SDHC_Type*) SDHC0_BASE) /* 0x40460000 */ -#define SDHC0_WRAP ((SDHC_WRAP_Type*) &SDHC0->WRAP) /* 0x40460000 */ -#define SDHC0_CORE ((SDHC_CORE_Type*) &SDHC0->CORE) /* 0x40461000 */ - /******************************************************************************* * CANFD *******************************************************************************/ #define CANFD0_BASE 0x40520000UL #define CANFD0 ((CANFD_Type*) CANFD0_BASE) /* 0x40520000 */ -#define CANFD0_CH0_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[0].M_TTCAN) /* 0x40520000 */ #define CANFD0_CH0 ((CANFD_CH_Type*) &CANFD0->CH[0]) /* 0x40520000 */ +#define CANFD0_CH0_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[0].M_TTCAN) /* 0x40520000 */ /******************************************************************************* * SCB @@ -1158,24 +1120,38 @@ typedef enum { #define SCB0_BASE 0x40600000UL #define SCB1_BASE 0x40610000UL #define SCB2_BASE 0x40620000UL -#define SCB3_BASE 0x40630000UL #define SCB4_BASE 0x40640000UL #define SCB5_BASE 0x40650000UL #define SCB6_BASE 0x40660000UL #define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40600000 */ #define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40610000 */ #define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40620000 */ -#define SCB3 ((CySCB_Type*) SCB3_BASE) /* 0x40630000 */ #define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40640000 */ #define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40650000 */ #define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40660000 */ +/******************************************************************************* +* CTBM +*******************************************************************************/ + +#define CTBM0_BASE 0x40900000UL +#define CTBM0 ((CTBM_Type*) CTBM0_BASE) /* 0x40900000 */ + +/******************************************************************************* +* CTDAC +*******************************************************************************/ + +#define CTDAC0_BASE 0x40940000UL +#define CTDAC0 ((CTDAC_Type*) CTDAC0_BASE) /* 0x40940000 */ + /******************************************************************************* * SAR *******************************************************************************/ -#define SAR_BASE 0x409D0000UL -#define SAR ((SAR_Type*) SAR_BASE) /* 0x409D0000 */ +#define SAR0_BASE 0x409B0000UL +#define SAR1_BASE 0x409C0000UL +#define SAR0 ((SAR_Type*) SAR0_BASE) /* 0x409B0000 */ +#define SAR1 ((SAR_Type*) SAR1_BASE) /* 0x409C0000 */ /******************************************************************************* * PASS @@ -1183,11 +1159,15 @@ typedef enum { #define PASS_BASE 0x409F0000UL #define PASS ((PASS_Type*) PASS_BASE) /* 0x409F0000 */ -#define PASS_AREF ((PASS_AREF_Type*) &PASS->AREF) /* 0x409F0E00 */ +#define PASS_TIMER ((PASS_TIMER_Type*) &PASS->TIMER) /* 0x409F0100 */ +#define PASS_LPOSC ((PASS_LPOSC_Type*) &PASS->LPOSC) /* 0x409F0200 */ +#define PASS_FIFO0 ((PASS_FIFO_Type*) &PASS->FIFO[0]) /* 0x409F0300 */ +#define PASS_FIFO1 ((PASS_FIFO_Type*) &PASS->FIFO[1]) /* 0x409F0400 */ +#define PASS_AREFV2 ((PASS_AREFV2_Type*) &PASS->AREFV2) /* 0x409F0E00 */ -/** \} CY8C6245W-S3D72 */ +/** \} CY8C4588AZI-H675 */ -#endif /* _CY8C6245W_S3D72_H_ */ +#endif /* _CY8C4588AZI_H675_H_ */ /* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c4588azi_h676.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c4588azi_h676.h new file mode 100644 index 0000000000..4841dfd3c4 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c4588azi_h676.h @@ -0,0 +1,1173 @@ +/***************************************************************************//** +* \file cy8c4588azi_h676.h +* +* \brief +* CY8C4588AZI-H676 device header +* +* \note +* Generator version: 1.6.0.225 +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CY8C4588AZI_H676_H_ +#define _CY8C4588AZI_H676_H_ + +/** +* \addtogroup group_device CY8C4588AZI-H676 +* \{ +*/ + +/** +* \addtogroup Configuration_of_CMSIS +* \{ +*/ + +/******************************************************************************* +* Interrupt Number Definition +*******************************************************************************/ + +typedef enum { +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + /* ARM Cortex-M0+ Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C4588AZI-H676 User Interrupt Numbers */ + NvicMux0_IRQn = 0, /*!< 0 [DeepSleep] CPU User Interrupt #0 */ + NvicMux1_IRQn = 1, /*!< 1 [DeepSleep] CPU User Interrupt #1 */ + NvicMux2_IRQn = 2, /*!< 2 [DeepSleep] CPU User Interrupt #2 */ + NvicMux3_IRQn = 3, /*!< 3 [DeepSleep] CPU User Interrupt #3 */ + NvicMux4_IRQn = 4, /*!< 4 [DeepSleep] CPU User Interrupt #4 */ + NvicMux5_IRQn = 5, /*!< 5 [DeepSleep] CPU User Interrupt #5 */ + NvicMux6_IRQn = 6, /*!< 6 [DeepSleep] CPU User Interrupt #6 */ + NvicMux7_IRQn = 7, /*!< 7 [DeepSleep] CPU User Interrupt #7 */ + /* CY8C4588AZI-H676 Internal SW Interrupt Numbers */ + Internal0_IRQn = 8, /*!< 8 [Active] Internal SW Interrupt #0 */ + Internal1_IRQn = 9, /*!< 9 [Active] Internal SW Interrupt #1 */ + Internal2_IRQn = 10, /*!< 10 [Active] Internal SW Interrupt #2 */ + Internal3_IRQn = 11, /*!< 11 [Active] Internal SW Interrupt #3 */ + Internal4_IRQn = 12, /*!< 12 [Active] Internal SW Interrupt #4 */ + Internal5_IRQn = 13, /*!< 13 [Active] Internal SW Interrupt #5 */ + Internal6_IRQn = 14, /*!< 14 [Active] Internal SW Interrupt #6 */ + Internal7_IRQn = 15, /*!< 15 [Active] Internal SW Interrupt #7 */ + unconnected_IRQn =1023 /*!< 1023 Unconnected */ +#else + /* ARM Cortex-M4 Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C4588AZI-H676 Peripheral Interrupt Numbers */ + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_6_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #6 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + pass_interrupt_sar_0_IRQn = 39, /*!< 39 [DeepSleep] SAR ADC0 interrupt */ + pass_interrupt_sar_1_IRQn = 40, /*!< 40 [DeepSleep] SAR ADC1 interrupt */ + pass_interrupt_ctb_IRQn = 41, /*!< 41 [DeepSleep] individual interrupt per CTB */ + pass_interrupt_fifo_0_IRQn = 43, /*!< 43 [DeepSleep] PASS FIFO0 */ + pass_interrupt_fifo_1_IRQn = 44, /*!< 44 [DeepSleep] PASS FIFO1 */ + scb_0_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #2 */ + scb_4_interrupt_IRQn = 49, /*!< 49 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 50, /*!< 50 [Active] Serial Communication Block #5 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_0_interrupts_256_IRQn = 131, /*!< 131 [Active] TCPWM #0, Counter #256 */ + tcpwm_0_interrupts_257_IRQn = 132, /*!< 132 [Active] TCPWM #0, Counter #257 */ + tcpwm_0_interrupts_258_IRQn = 133, /*!< 133 [Active] TCPWM #0, Counter #258 */ + tcpwm_0_interrupts_259_IRQn = 134, /*!< 134 [Active] TCPWM #0, Counter #259 */ + tcpwm_0_interrupts_260_IRQn = 135, /*!< 135 [Active] TCPWM #0, Counter #260 */ + tcpwm_0_interrupts_261_IRQn = 136, /*!< 136 [Active] TCPWM #0, Counter #261 */ + tcpwm_0_interrupts_262_IRQn = 137, /*!< 137 [Active] TCPWM #0, Counter #262 */ + tcpwm_0_interrupts_263_IRQn = 138, /*!< 138 [Active] TCPWM #0, Counter #263 */ + pass_interrupt_dacs_IRQn = 146, /*!< 146 [Active] Consolidated interrrupt for all DACs */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + canfd_0_interrupt0_IRQn = 168, /*!< 168 [Active] Can #0, Consolidated interrupt #0 */ + canfd_0_interrupts0_0_IRQn = 169, /*!< 169 [Active] CAN #0, Interrupt #0, Channel #0 */ + canfd_0_interrupts1_0_IRQn = 170, /*!< 170 [Active] CAN #0, Interrupt #1, Channel #0 */ + cpuss_interrupts_dw1_29_IRQn = 171, /*!< 171 [Active] CPUSS DataWire #1, Channel #29 */ + cpuss_interrupts_dw1_30_IRQn = 172, /*!< 172 [Active] CPUSS DataWire #1, Channel #30 */ + cpuss_interrupts_dw1_31_IRQn = 173, /*!< 173 [Active] CPUSS DataWire #1, Channel #31 */ + cpuss_interrupts_dw0_29_IRQn = 174, /*!< 174 [Active] CPUSS DataWire #0, Channel #29 */ + unconnected_IRQn =1023 /*!< 1023 Unconnected */ +#endif +} IRQn_Type; + + +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + +/* CY8C4588AZI-H676 interrupts that can be routed to the CM0+ NVIC */ +typedef enum { + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_6_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #6 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + pass_interrupt_sar_0_IRQn = 39, /*!< 39 [DeepSleep] SAR ADC0 interrupt */ + pass_interrupt_sar_1_IRQn = 40, /*!< 40 [DeepSleep] SAR ADC1 interrupt */ + pass_interrupt_ctb_IRQn = 41, /*!< 41 [DeepSleep] individual interrupt per CTB */ + pass_interrupt_fifo_0_IRQn = 43, /*!< 43 [DeepSleep] PASS FIFO0 */ + pass_interrupt_fifo_1_IRQn = 44, /*!< 44 [DeepSleep] PASS FIFO1 */ + scb_0_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #2 */ + scb_4_interrupt_IRQn = 49, /*!< 49 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 50, /*!< 50 [Active] Serial Communication Block #5 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_0_interrupts_256_IRQn = 131, /*!< 131 [Active] TCPWM #0, Counter #256 */ + tcpwm_0_interrupts_257_IRQn = 132, /*!< 132 [Active] TCPWM #0, Counter #257 */ + tcpwm_0_interrupts_258_IRQn = 133, /*!< 133 [Active] TCPWM #0, Counter #258 */ + tcpwm_0_interrupts_259_IRQn = 134, /*!< 134 [Active] TCPWM #0, Counter #259 */ + tcpwm_0_interrupts_260_IRQn = 135, /*!< 135 [Active] TCPWM #0, Counter #260 */ + tcpwm_0_interrupts_261_IRQn = 136, /*!< 136 [Active] TCPWM #0, Counter #261 */ + tcpwm_0_interrupts_262_IRQn = 137, /*!< 137 [Active] TCPWM #0, Counter #262 */ + tcpwm_0_interrupts_263_IRQn = 138, /*!< 138 [Active] TCPWM #0, Counter #263 */ + pass_interrupt_dacs_IRQn = 146, /*!< 146 [Active] Consolidated interrrupt for all DACs */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + canfd_0_interrupt0_IRQn = 168, /*!< 168 [Active] Can #0, Consolidated interrupt #0 */ + canfd_0_interrupts0_0_IRQn = 169, /*!< 169 [Active] CAN #0, Interrupt #0, Channel #0 */ + canfd_0_interrupts1_0_IRQn = 170, /*!< 170 [Active] CAN #0, Interrupt #1, Channel #0 */ + cpuss_interrupts_dw1_29_IRQn = 171, /*!< 171 [Active] CPUSS DataWire #1, Channel #29 */ + cpuss_interrupts_dw1_30_IRQn = 172, /*!< 172 [Active] CPUSS DataWire #1, Channel #30 */ + cpuss_interrupts_dw1_31_IRQn = 173, /*!< 173 [Active] CPUSS DataWire #1, Channel #31 */ + cpuss_interrupts_dw0_29_IRQn = 174, /*!< 174 [Active] CPUSS DataWire #0, Channel #29 */ + disconnected_IRQn =1023 /*!< 1023 Disconnected */ +} cy_en_intr_t; + +#endif + +/******************************************************************************* +* Processor and Core Peripheral Section +*******************************************************************************/ + +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + +/* Configuration of the ARM Cortex-M0+ Processor and Core Peripherals */ +#define __CM0PLUS_REV 0x0001U /*!< CM0PLUS Core Revision */ +#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm0plus.h" /*!< ARM Cortex-M0+ processor and core peripherals */ + +#else + +/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __CM0P_PRESENT 1 /*!< CM0P present or not */ +#define __DTCM_PRESENT 0 /*!< DTCM present or not */ +#define __ICACHE_PRESENT 0 /*!< ICACHE present or not */ +#define __DCACHE_PRESENT 0 /*!< DCACHE present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + +#endif + +/* Memory Blocks */ +#define CY_ROM_BASE 0x00000000UL +#define CY_ROM_SIZE 0x00010000UL +#define CY_SRAM_BASE 0x08000000UL +#define CY_SRAM_SIZE 0x00020000UL +#define CY_FLASH_BASE 0x10000000UL +#define CY_FLASH_SIZE 0x00040000UL +#define CY_EM_EEPROM_BASE 0x14000000UL +#define CY_EM_EEPROM_SIZE 0x00000000UL +#define CY_SFLASH_BASE 0x16000000UL +#define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL +#define CY_EFUSE_BASE 0x402C0800UL +#define CY_EFUSE_SIZE 0x00000200UL +#define CY_CAN0MRAM_BASE 0x40530000UL +#define CY_CAN0MRAM_SIZE 0x00010000UL + +#include "system_psoc6.h" /*!< PSoC 6 System */ + +/* IP List */ +#define CY_IP_MXTTCANFD 1u +#define CY_IP_MXTTCANFD_INSTANCES 1u +#define CY_IP_MXTTCANFD_VERSION 1u +#define CY_IP_M4CPUSS 1u +#define CY_IP_M4CPUSS_INSTANCES 1u +#define CY_IP_M4CPUSS_VERSION 2u +#define CY_IP_M4CPUSS_DMAC 1u +#define CY_IP_M4CPUSS_DMAC_INSTANCES 1u +#define CY_IP_M4CPUSS_DMAC_VERSION 2u +#define CY_IP_M4CPUSS_DMA 1u +#define CY_IP_M4CPUSS_DMA_INSTANCES 2u +#define CY_IP_M4CPUSS_DMA_VERSION 2u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 2u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 6u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u + +#include "psoc6_04_config.h" +#include "gpio_psoc6_04_80_tqfp.h" + +#define CY_DEVICE_PSOC6A256K +#define CY_SILICON_ID 0xEAFC110EUL +#define CY_HF_CLK_MAX_FREQ 150000000UL + +#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL + +/******************************************************************************* +* SFLASH +*******************************************************************************/ + +#define SFLASH_BASE 0x16000000UL +#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */ + +/******************************************************************************* +* PERI +*******************************************************************************/ + +#define PERI_BASE 0x40000000UL +#define PERI ((PERI_Type*) PERI_BASE) /* 0x40000000 */ +#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40004000 */ +#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40004020 */ +#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40004040 */ +#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x40004060 */ +#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40004080 */ +#define PERI_GR5 ((PERI_GR_Type*) &PERI->GR[5]) /* 0x400040A0 */ +#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x400040C0 */ +#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40004120 */ +#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40008000 */ +#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40008400 */ +#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40008800 */ +#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40008C00 */ +#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40009000 */ +#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40009400 */ +#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40009800 */ +#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40009C00 */ +#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ +#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ +#define PERI_TR_GR10 ((PERI_TR_GR_Type*) &PERI->TR_GR[10]) /* 0x4000A800 */ +#define PERI_TR_GR11 ((PERI_TR_GR_Type*) &PERI->TR_GR[11]) /* 0x4000AC00 */ +#define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ +#define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ +#define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ +#define PERI_TR_1TO1_GR3 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[3]) /* 0x4000CC00 */ +#define PERI_TR_1TO1_GR4 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[4]) /* 0x4000D000 */ +#define PERI_TR_1TO1_GR5 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[5]) /* 0x4000D400 */ +#define PERI_TR_1TO1_GR6 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[6]) /* 0x4000D800 */ +#define PERI_TR_1TO1_GR7 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[7]) /* 0x4000DC00 */ +#define PERI_TR_1TO1_GR8 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[8]) /* 0x4000E000 */ + +/******************************************************************************* +* PERI_MS +*******************************************************************************/ + +#define PERI_MS_BASE 0x40010000UL +#define PERI_MS ((PERI_MS_Type*) PERI_MS_BASE) /* 0x40010000 */ +#define PERI_MS_PPU_PR0 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[0]) /* 0x40010000 */ +#define PERI_MS_PPU_PR1 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[1]) /* 0x40010040 */ +#define PERI_MS_PPU_PR2 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[2]) /* 0x40010080 */ +#define PERI_MS_PPU_PR3 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[3]) /* 0x400100C0 */ +#define PERI_MS_PPU_PR4 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[4]) /* 0x40010100 */ +#define PERI_MS_PPU_PR5 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[5]) /* 0x40010140 */ +#define PERI_MS_PPU_PR6 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[6]) /* 0x40010180 */ +#define PERI_MS_PPU_PR7 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[7]) /* 0x400101C0 */ +#define PERI_MS_PPU_FX_PERI_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[0]) /* 0x40010800 */ +#define PERI_MS_PPU_FX_PERI_GR0_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[1]) /* 0x40010840 */ +#define PERI_MS_PPU_FX_PERI_GR1_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[2]) /* 0x40010880 */ +#define PERI_MS_PPU_FX_PERI_GR2_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[3]) /* 0x400108C0 */ +#define PERI_MS_PPU_FX_PERI_GR3_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[4]) /* 0x40010900 */ +#define PERI_MS_PPU_FX_PERI_GR4_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[5]) /* 0x40010940 */ +#define PERI_MS_PPU_FX_PERI_GR5_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[6]) /* 0x40010980 */ +#define PERI_MS_PPU_FX_PERI_GR6_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[7]) /* 0x400109C0 */ +#define PERI_MS_PPU_FX_PERI_GR9_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[8]) /* 0x40010A00 */ +#define PERI_MS_PPU_FX_PERI_TR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[9]) /* 0x40010A40 */ +#define PERI_MS_PPU_FX_CRYPTO_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[10]) /* 0x40010A80 */ +#define PERI_MS_PPU_FX_CRYPTO_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[11]) /* 0x40010AC0 */ +#define PERI_MS_PPU_FX_CRYPTO_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[12]) /* 0x40010B00 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[13]) /* 0x40010B40 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[14]) /* 0x40010B80 */ +#define PERI_MS_PPU_FX_CRYPTO_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[15]) /* 0x40010BC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[16]) /* 0x40010C00 */ +#define PERI_MS_PPU_FX_CPUSS_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[17]) /* 0x40010C40 */ +#define PERI_MS_PPU_FX_CPUSS_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[18]) /* 0x40010C80 */ +#define PERI_MS_PPU_FX_CPUSS_CM0_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[19]) /* 0x40010CC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[20]) /* 0x40010D00 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[21]) /* 0x40010D40 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT1_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[22]) /* 0x40010D80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT0_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[23]) /* 0x40010DC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT1_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[24]) /* 0x40010E00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT2_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[25]) /* 0x40010E40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT3_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[26]) /* 0x40010E80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT4_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[27]) /* 0x40010EC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT5_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[28]) /* 0x40010F00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT6_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[29]) /* 0x40010F40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT7_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[30]) /* 0x40010F80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT8_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[31]) /* 0x40010FC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT9_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[32]) /* 0x40011000 */ +#define PERI_MS_PPU_FX_IPC_STRUCT10_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[33]) /* 0x40011040 */ +#define PERI_MS_PPU_FX_IPC_STRUCT11_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[34]) /* 0x40011080 */ +#define PERI_MS_PPU_FX_IPC_STRUCT12_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[35]) /* 0x400110C0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT13_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[36]) /* 0x40011100 */ +#define PERI_MS_PPU_FX_IPC_STRUCT14_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[37]) /* 0x40011140 */ +#define PERI_MS_PPU_FX_IPC_STRUCT15_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[38]) /* 0x40011180 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT0_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[39]) /* 0x400111C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT1_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[40]) /* 0x40011200 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT2_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[41]) /* 0x40011240 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT3_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[42]) /* 0x40011280 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT4_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[43]) /* 0x400112C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT5_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[44]) /* 0x40011300 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT6_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[45]) /* 0x40011340 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT7_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[46]) /* 0x40011380 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT8_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[47]) /* 0x400113C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT9_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[48]) /* 0x40011400 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT10_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[49]) /* 0x40011440 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT11_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[50]) /* 0x40011480 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT12_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[51]) /* 0x400114C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT13_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[52]) /* 0x40011500 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT14_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[53]) /* 0x40011540 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT15_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[54]) /* 0x40011580 */ +#define PERI_MS_PPU_FX_PROT_SMPU_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[55]) /* 0x400115C0 */ +#define PERI_MS_PPU_FX_PROT_MPU0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[56]) /* 0x40011600 */ +#define PERI_MS_PPU_FX_PROT_MPU14_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[57]) /* 0x40011640 */ +#define PERI_MS_PPU_FX_PROT_MPU15_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[58]) /* 0x40011680 */ +#define PERI_MS_PPU_FX_FLASHC_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[59]) /* 0x400116C0 */ +#define PERI_MS_PPU_FX_FLASHC_CMD ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[60]) /* 0x40011700 */ +#define PERI_MS_PPU_FX_FLASHC_DFT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[61]) /* 0x40011740 */ +#define PERI_MS_PPU_FX_FLASHC_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[62]) /* 0x40011780 */ +#define PERI_MS_PPU_FX_FLASHC_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[63]) /* 0x400117C0 */ +#define PERI_MS_PPU_FX_FLASHC_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[64]) /* 0x40011800 */ +#define PERI_MS_PPU_FX_FLASHC_DW0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[65]) /* 0x40011840 */ +#define PERI_MS_PPU_FX_FLASHC_DW1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[66]) /* 0x40011880 */ +#define PERI_MS_PPU_FX_FLASHC_DMAC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[67]) /* 0x400118C0 */ +#define PERI_MS_PPU_FX_FLASHC_FM ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[68]) /* 0x40011900 */ +#define PERI_MS_PPU_FX_SRSS_MAIN1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[69]) /* 0x40011940 */ +#define PERI_MS_PPU_FX_SRSS_MAIN2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[70]) /* 0x40011980 */ +#define PERI_MS_PPU_FX_WDT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[71]) /* 0x400119C0 */ +#define PERI_MS_PPU_FX_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[72]) /* 0x40011A00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[73]) /* 0x40011A40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[74]) /* 0x40011A80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[75]) /* 0x40011AC0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[76]) /* 0x40011B00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[77]) /* 0x40011B40 */ +#define PERI_MS_PPU_FX_BACKUP_BACKUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[78]) /* 0x40011B80 */ +#define PERI_MS_PPU_FX_DW0_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[79]) /* 0x40011BC0 */ +#define PERI_MS_PPU_FX_DW1_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[80]) /* 0x40011C00 */ +#define PERI_MS_PPU_FX_DW0_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[81]) /* 0x40011C40 */ +#define PERI_MS_PPU_FX_DW1_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[82]) /* 0x40011C80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[83]) /* 0x40011CC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[84]) /* 0x40011D00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[85]) /* 0x40011D40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[86]) /* 0x40011D80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[87]) /* 0x40011DC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[88]) /* 0x40011E00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[89]) /* 0x40011E40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[90]) /* 0x40011E80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[91]) /* 0x40011EC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[92]) /* 0x40011F00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[93]) /* 0x40011F40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[94]) /* 0x40011F80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[95]) /* 0x40011FC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[96]) /* 0x40012000 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[97]) /* 0x40012040 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[98]) /* 0x40012080 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[99]) /* 0x400120C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[100]) /* 0x40012100 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[101]) /* 0x40012140 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[102]) /* 0x40012180 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[103]) /* 0x400121C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[104]) /* 0x40012200 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[105]) /* 0x40012240 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[106]) /* 0x40012280 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[107]) /* 0x400122C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[108]) /* 0x40012300 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[109]) /* 0x40012340 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[110]) /* 0x40012380 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[111]) /* 0x400123C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT29_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[112]) /* 0x40012400 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[113]) /* 0x40012440 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[114]) /* 0x40012480 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[115]) /* 0x400124C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[116]) /* 0x40012500 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[117]) /* 0x40012540 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[118]) /* 0x40012580 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[119]) /* 0x400125C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[120]) /* 0x40012600 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[121]) /* 0x40012640 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[122]) /* 0x40012680 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[123]) /* 0x400126C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[124]) /* 0x40012700 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[125]) /* 0x40012740 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[126]) /* 0x40012780 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[127]) /* 0x400127C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[128]) /* 0x40012800 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[129]) /* 0x40012840 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[130]) /* 0x40012880 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[131]) /* 0x400128C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[132]) /* 0x40012900 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[133]) /* 0x40012940 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[134]) /* 0x40012980 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[135]) /* 0x400129C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[136]) /* 0x40012A00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[137]) /* 0x40012A40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[138]) /* 0x40012A80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[139]) /* 0x40012AC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[140]) /* 0x40012B00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[141]) /* 0x40012B40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT29_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[142]) /* 0x40012B80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT30_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[143]) /* 0x40012BC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT31_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[144]) /* 0x40012C00 */ +#define PERI_MS_PPU_FX_DMAC_TOP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[145]) /* 0x40012C40 */ +#define PERI_MS_PPU_FX_DMAC_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[146]) /* 0x40012C80 */ +#define PERI_MS_PPU_FX_DMAC_CH1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[147]) /* 0x40012CC0 */ +#define PERI_MS_PPU_FX_EFUSE_CTL ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[148]) /* 0x40012D00 */ +#define PERI_MS_PPU_FX_EFUSE_DATA ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[149]) /* 0x40012D40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[150]) /* 0x40012D80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[151]) /* 0x40012DC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[152]) /* 0x40012E00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[153]) /* 0x40012E40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[154]) /* 0x40012E80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[155]) /* 0x40012EC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[156]) /* 0x40012F00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[157]) /* 0x40012F40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[158]) /* 0x40012F80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[159]) /* 0x40012FC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[160]) /* 0x40013000 */ +#define PERI_MS_PPU_FX_HSIOM_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[161]) /* 0x40013040 */ +#define PERI_MS_PPU_FX_HSIOM_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[162]) /* 0x40013080 */ +#define PERI_MS_PPU_FX_HSIOM_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[163]) /* 0x400130C0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[164]) /* 0x40013100 */ +#define PERI_MS_PPU_FX_HSIOM_AMUX ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[165]) /* 0x40013140 */ +#define PERI_MS_PPU_FX_HSIOM_MON ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[166]) /* 0x40013180 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[167]) /* 0x400131C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[168]) /* 0x40013200 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[169]) /* 0x40013240 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[170]) /* 0x40013280 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[171]) /* 0x400132C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[172]) /* 0x40013300 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[173]) /* 0x40013340 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[174]) /* 0x40013380 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[175]) /* 0x400133C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[176]) /* 0x40013400 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[177]) /* 0x40013440 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[178]) /* 0x40013480 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[179]) /* 0x400134C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[180]) /* 0x40013500 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[181]) /* 0x40013540 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[182]) /* 0x40013580 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[183]) /* 0x400135C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[184]) /* 0x40013600 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[185]) /* 0x40013640 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[186]) /* 0x40013680 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[187]) /* 0x400136C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[188]) /* 0x40013700 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[189]) /* 0x40013740 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[190]) /* 0x40013780 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[191]) /* 0x400137C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[192]) /* 0x40013800 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[193]) /* 0x40013840 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[194]) /* 0x40013880 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[195]) /* 0x400138C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[196]) /* 0x40013900 */ +#define PERI_MS_PPU_FX_GPIO_GPIO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[197]) /* 0x40013940 */ +#define PERI_MS_PPU_FX_GPIO_TEST ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[198]) /* 0x40013980 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[199]) /* 0x400139C0 */ +#define PERI_MS_PPU_FX_LPCOMP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[200]) /* 0x40013A00 */ +#define PERI_MS_PPU_FX_CSD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[201]) /* 0x40013A40 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT0_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[202]) /* 0x40013A80 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT1_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[203]) /* 0x40013AC0 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT2_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[204]) /* 0x40013B00 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT3_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[205]) /* 0x40013B40 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT0_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[206]) /* 0x40013B80 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT1_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[207]) /* 0x40013BC0 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT2_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[208]) /* 0x40013C00 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT3_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[209]) /* 0x40013C40 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT4_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[210]) /* 0x40013C80 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT5_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[211]) /* 0x40013CC0 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT6_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[212]) /* 0x40013D00 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT7_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[213]) /* 0x40013D40 */ +#define PERI_MS_PPU_FX_LCD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[214]) /* 0x40013D80 */ +#define PERI_MS_PPU_FX_USBFS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[215]) /* 0x40013DC0 */ +#define PERI_MS_PPU_FX_SMIF0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[216]) /* 0x40013E00 */ +#define PERI_MS_PPU_FX_CANFD0_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[217]) /* 0x40013E40 */ +#define PERI_MS_PPU_FX_CANFD0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[218]) /* 0x40013E80 */ +#define PERI_MS_PPU_FX_CANFD0_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[219]) /* 0x40013EC0 */ +#define PERI_MS_PPU_FX_SCB0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[220]) /* 0x40013F00 */ +#define PERI_MS_PPU_FX_SCB1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[221]) /* 0x40013F40 */ +#define PERI_MS_PPU_FX_SCB2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[222]) /* 0x40013F80 */ +#define PERI_MS_PPU_FX_SCB4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[223]) /* 0x40013FC0 */ +#define PERI_MS_PPU_FX_SCB5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[224]) /* 0x40014000 */ +#define PERI_MS_PPU_FX_SCB6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[225]) /* 0x40014040 */ + +/******************************************************************************* +* CPUSS +*******************************************************************************/ + +#define CPUSS_BASE 0x40200000UL +#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40200000 */ + +/******************************************************************************* +* FAULT +*******************************************************************************/ + +#define FAULT_BASE 0x40210000UL +#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40210000 */ +#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40210000 */ +#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40210100 */ + +/******************************************************************************* +* IPC +*******************************************************************************/ + +#define IPC_BASE 0x40220000UL +#define IPC ((IPC_Type*) IPC_BASE) /* 0x40220000 */ +#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40220000 */ +#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40220020 */ +#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40220040 */ +#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40220060 */ +#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40220080 */ +#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402200A0 */ +#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402200C0 */ +#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402200E0 */ +#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40220100 */ +#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40220120 */ +#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40220140 */ +#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40220160 */ +#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40220180 */ +#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402201A0 */ +#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402201C0 */ +#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402201E0 */ +#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40221000 */ +#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40221020 */ +#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40221040 */ +#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40221060 */ +#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40221080 */ +#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402210A0 */ +#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402210C0 */ +#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402210E0 */ +#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40221100 */ +#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40221120 */ +#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40221140 */ +#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40221160 */ +#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40221180 */ +#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402211A0 */ +#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402211C0 */ +#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402211E0 */ + +/******************************************************************************* +* PROT +*******************************************************************************/ + +#define PROT_BASE 0x40230000UL +#define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ +#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ +#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ +#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402320C0 */ +#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40232100 */ +#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40232140 */ +#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40232180 */ +#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402321C0 */ +#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40232200 */ +#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40232240 */ +#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40232280 */ +#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402322C0 */ +#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40232300 */ +#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ +#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ +#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ + +/******************************************************************************* +* FLASHC +*******************************************************************************/ + +#define FLASHC_BASE 0x40240000UL +#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40240000 */ +#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4024F000 */ + +/******************************************************************************* +* SRSS +*******************************************************************************/ + +#define SRSS_BASE 0x40260000UL +#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ +#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */ +#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */ + +/******************************************************************************* +* BACKUP +*******************************************************************************/ + +#define BACKUP_BASE 0x40270000UL +#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ + +/******************************************************************************* +* DW +*******************************************************************************/ + +#define DW0_BASE 0x40280000UL +#define DW1_BASE 0x40290000UL +#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ +#define DW1 ((DW_Type*) DW1_BASE) /* 0x40290000 */ +#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40288000 */ +#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40288040 */ +#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40288080 */ +#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x402880C0 */ +#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40288100 */ +#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x40288140 */ +#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x40288180 */ +#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402881C0 */ +#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40288200 */ +#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40288240 */ +#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40288280 */ +#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x402882C0 */ +#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40288300 */ +#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x40288340 */ +#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x40288380 */ +#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402883C0 */ +#define DW0_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[16]) /* 0x40288400 */ +#define DW0_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[17]) /* 0x40288440 */ +#define DW0_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[18]) /* 0x40288480 */ +#define DW0_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[19]) /* 0x402884C0 */ +#define DW0_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[20]) /* 0x40288500 */ +#define DW0_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[21]) /* 0x40288540 */ +#define DW0_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[22]) /* 0x40288580 */ +#define DW0_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[23]) /* 0x402885C0 */ +#define DW0_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[24]) /* 0x40288600 */ +#define DW0_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[25]) /* 0x40288640 */ +#define DW0_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[26]) /* 0x40288680 */ +#define DW0_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[27]) /* 0x402886C0 */ +#define DW0_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[28]) /* 0x40288700 */ +#define DW0_CH_STRUCT29 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[29]) /* 0x40288740 */ +#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40298000 */ +#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40298040 */ +#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40298080 */ +#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x402980C0 */ +#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40298100 */ +#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x40298140 */ +#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x40298180 */ +#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402981C0 */ +#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40298200 */ +#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40298240 */ +#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40298280 */ +#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x402982C0 */ +#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40298300 */ +#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x40298340 */ +#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x40298380 */ +#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402983C0 */ +#define DW1_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[16]) /* 0x40298400 */ +#define DW1_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[17]) /* 0x40298440 */ +#define DW1_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[18]) /* 0x40298480 */ +#define DW1_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[19]) /* 0x402984C0 */ +#define DW1_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[20]) /* 0x40298500 */ +#define DW1_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[21]) /* 0x40298540 */ +#define DW1_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[22]) /* 0x40298580 */ +#define DW1_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[23]) /* 0x402985C0 */ +#define DW1_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[24]) /* 0x40298600 */ +#define DW1_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[25]) /* 0x40298640 */ +#define DW1_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[26]) /* 0x40298680 */ +#define DW1_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[27]) /* 0x402986C0 */ +#define DW1_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[28]) /* 0x40298700 */ +#define DW1_CH_STRUCT29 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[29]) /* 0x40298740 */ +#define DW1_CH_STRUCT30 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[30]) /* 0x40298780 */ +#define DW1_CH_STRUCT31 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[31]) /* 0x402987C0 */ + +/******************************************************************************* +* DMAC +*******************************************************************************/ + +#define DMAC_BASE 0x402A0000UL +#define DMAC ((DMAC_Type*) DMAC_BASE) /* 0x402A0000 */ +#define DMAC_CH0 ((DMAC_CH_Type*) &DMAC->CH[0]) /* 0x402A1000 */ +#define DMAC_CH1 ((DMAC_CH_Type*) &DMAC->CH[1]) /* 0x402A1100 */ + +/******************************************************************************* +* EFUSE +*******************************************************************************/ + +#define EFUSE_BASE 0x402C0000UL +#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ + +/******************************************************************************* +* HSIOM +*******************************************************************************/ + +#define HSIOM_BASE 0x40300000UL +#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40300000 */ +#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40300000 */ +#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40300010 */ +#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40300020 */ +#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40300030 */ +#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40300040 */ +#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40300050 */ +#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40300060 */ +#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40300070 */ +#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40300080 */ +#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40300090 */ +#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403000A0 */ +#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403000B0 */ +#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403000C0 */ +#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403000D0 */ +#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403000E0 */ + +/******************************************************************************* +* GPIO +*******************************************************************************/ + +#define GPIO_BASE 0x40310000UL +#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40310000 */ +#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40310000 */ +#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40310080 */ +#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40310100 */ +#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40310180 */ +#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40310200 */ +#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40310280 */ +#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40310300 */ +#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40310380 */ +#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40310400 */ +#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40310480 */ +#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40310500 */ +#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40310580 */ +#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40310600 */ +#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40310680 */ +#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40310700 */ + +/******************************************************************************* +* SMARTIO +*******************************************************************************/ + +#define SMARTIO_BASE 0x40320000UL +#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40320000 */ +#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40320900 */ + +/******************************************************************************* +* LPCOMP +*******************************************************************************/ + +#define LPCOMP_BASE 0x40350000UL +#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */ + +/******************************************************************************* +* CSD +*******************************************************************************/ + +#define CSD0_BASE 0x40360000UL +#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */ + +/******************************************************************************* +* TCPWM +*******************************************************************************/ + +#define TCPWM0_BASE 0x40380000UL +#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM0_GRP0 ((TCPWM_GRP_Type*) &TCPWM0->GRP[0]) /* 0x40380000 */ +#define TCPWM0_GRP1 ((TCPWM_GRP_Type*) &TCPWM0->GRP[1]) /* 0x40388000 */ +#define TCPWM0_GRP0_CNT0 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[0]) /* 0x40380000 */ +#define TCPWM0_GRP0_CNT1 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[1]) /* 0x40380080 */ +#define TCPWM0_GRP0_CNT2 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[2]) /* 0x40380100 */ +#define TCPWM0_GRP0_CNT3 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[3]) /* 0x40380180 */ +#define TCPWM0_GRP1_CNT0 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[0]) /* 0x40388000 */ +#define TCPWM0_GRP1_CNT1 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[1]) /* 0x40388080 */ +#define TCPWM0_GRP1_CNT2 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[2]) /* 0x40388100 */ +#define TCPWM0_GRP1_CNT3 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[3]) /* 0x40388180 */ +#define TCPWM0_GRP1_CNT4 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[4]) /* 0x40388200 */ +#define TCPWM0_GRP1_CNT5 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[5]) /* 0x40388280 */ +#define TCPWM0_GRP1_CNT6 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[6]) /* 0x40388300 */ +#define TCPWM0_GRP1_CNT7 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[7]) /* 0x40388380 */ + +/******************************************************************************* +* LCD +*******************************************************************************/ + +#define LCD0_BASE 0x403B0000UL +#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ + +/******************************************************************************* +* SMIF +*******************************************************************************/ + +#define SMIF0_BASE 0x40420000UL +#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ +#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ +#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ +#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ + +/******************************************************************************* +* CANFD +*******************************************************************************/ + +#define CANFD0_BASE 0x40520000UL +#define CANFD0 ((CANFD_Type*) CANFD0_BASE) /* 0x40520000 */ +#define CANFD0_CH0 ((CANFD_CH_Type*) &CANFD0->CH[0]) /* 0x40520000 */ +#define CANFD0_CH0_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[0].M_TTCAN) /* 0x40520000 */ + +/******************************************************************************* +* SCB +*******************************************************************************/ + +#define SCB0_BASE 0x40600000UL +#define SCB1_BASE 0x40610000UL +#define SCB2_BASE 0x40620000UL +#define SCB4_BASE 0x40640000UL +#define SCB5_BASE 0x40650000UL +#define SCB6_BASE 0x40660000UL +#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40600000 */ +#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40610000 */ +#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40620000 */ +#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40640000 */ +#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40650000 */ +#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40660000 */ + +/******************************************************************************* +* CTBM +*******************************************************************************/ + +#define CTBM0_BASE 0x40900000UL +#define CTBM0 ((CTBM_Type*) CTBM0_BASE) /* 0x40900000 */ + +/******************************************************************************* +* CTDAC +*******************************************************************************/ + +#define CTDAC0_BASE 0x40940000UL +#define CTDAC0 ((CTDAC_Type*) CTDAC0_BASE) /* 0x40940000 */ + +/******************************************************************************* +* SAR +*******************************************************************************/ + +#define SAR0_BASE 0x409B0000UL +#define SAR1_BASE 0x409C0000UL +#define SAR0 ((SAR_Type*) SAR0_BASE) /* 0x409B0000 */ +#define SAR1 ((SAR_Type*) SAR1_BASE) /* 0x409C0000 */ + +/******************************************************************************* +* PASS +*******************************************************************************/ + +#define PASS_BASE 0x409F0000UL +#define PASS ((PASS_Type*) PASS_BASE) /* 0x409F0000 */ +#define PASS_TIMER ((PASS_TIMER_Type*) &PASS->TIMER) /* 0x409F0100 */ +#define PASS_LPOSC ((PASS_LPOSC_Type*) &PASS->LPOSC) /* 0x409F0200 */ +#define PASS_FIFO0 ((PASS_FIFO_Type*) &PASS->FIFO[0]) /* 0x409F0300 */ +#define PASS_FIFO1 ((PASS_FIFO_Type*) &PASS->FIFO[1]) /* 0x409F0400 */ +#define PASS_AREFV2 ((PASS_AREFV2_Type*) &PASS->AREFV2) /* 0x409F0E00 */ + +/** \} CY8C4588AZI-H676 */ + +#endif /* _CY8C4588AZI_H676_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c4588azi_h685.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c4588azi_h685.h new file mode 100644 index 0000000000..d029c664c6 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c4588azi_h685.h @@ -0,0 +1,1173 @@ +/***************************************************************************//** +* \file cy8c4588azi_h685.h +* +* \brief +* CY8C4588AZI-H685 device header +* +* \note +* Generator version: 1.6.0.225 +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CY8C4588AZI_H685_H_ +#define _CY8C4588AZI_H685_H_ + +/** +* \addtogroup group_device CY8C4588AZI-H685 +* \{ +*/ + +/** +* \addtogroup Configuration_of_CMSIS +* \{ +*/ + +/******************************************************************************* +* Interrupt Number Definition +*******************************************************************************/ + +typedef enum { +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + /* ARM Cortex-M0+ Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C4588AZI-H685 User Interrupt Numbers */ + NvicMux0_IRQn = 0, /*!< 0 [DeepSleep] CPU User Interrupt #0 */ + NvicMux1_IRQn = 1, /*!< 1 [DeepSleep] CPU User Interrupt #1 */ + NvicMux2_IRQn = 2, /*!< 2 [DeepSleep] CPU User Interrupt #2 */ + NvicMux3_IRQn = 3, /*!< 3 [DeepSleep] CPU User Interrupt #3 */ + NvicMux4_IRQn = 4, /*!< 4 [DeepSleep] CPU User Interrupt #4 */ + NvicMux5_IRQn = 5, /*!< 5 [DeepSleep] CPU User Interrupt #5 */ + NvicMux6_IRQn = 6, /*!< 6 [DeepSleep] CPU User Interrupt #6 */ + NvicMux7_IRQn = 7, /*!< 7 [DeepSleep] CPU User Interrupt #7 */ + /* CY8C4588AZI-H685 Internal SW Interrupt Numbers */ + Internal0_IRQn = 8, /*!< 8 [Active] Internal SW Interrupt #0 */ + Internal1_IRQn = 9, /*!< 9 [Active] Internal SW Interrupt #1 */ + Internal2_IRQn = 10, /*!< 10 [Active] Internal SW Interrupt #2 */ + Internal3_IRQn = 11, /*!< 11 [Active] Internal SW Interrupt #3 */ + Internal4_IRQn = 12, /*!< 12 [Active] Internal SW Interrupt #4 */ + Internal5_IRQn = 13, /*!< 13 [Active] Internal SW Interrupt #5 */ + Internal6_IRQn = 14, /*!< 14 [Active] Internal SW Interrupt #6 */ + Internal7_IRQn = 15, /*!< 15 [Active] Internal SW Interrupt #7 */ + unconnected_IRQn =1023 /*!< 1023 Unconnected */ +#else + /* ARM Cortex-M4 Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C4588AZI-H685 Peripheral Interrupt Numbers */ + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_6_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #6 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + pass_interrupt_sar_0_IRQn = 39, /*!< 39 [DeepSleep] SAR ADC0 interrupt */ + pass_interrupt_sar_1_IRQn = 40, /*!< 40 [DeepSleep] SAR ADC1 interrupt */ + pass_interrupt_ctb_IRQn = 41, /*!< 41 [DeepSleep] individual interrupt per CTB */ + pass_interrupt_fifo_0_IRQn = 43, /*!< 43 [DeepSleep] PASS FIFO0 */ + pass_interrupt_fifo_1_IRQn = 44, /*!< 44 [DeepSleep] PASS FIFO1 */ + scb_0_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #2 */ + scb_4_interrupt_IRQn = 49, /*!< 49 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 50, /*!< 50 [Active] Serial Communication Block #5 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_0_interrupts_256_IRQn = 131, /*!< 131 [Active] TCPWM #0, Counter #256 */ + tcpwm_0_interrupts_257_IRQn = 132, /*!< 132 [Active] TCPWM #0, Counter #257 */ + tcpwm_0_interrupts_258_IRQn = 133, /*!< 133 [Active] TCPWM #0, Counter #258 */ + tcpwm_0_interrupts_259_IRQn = 134, /*!< 134 [Active] TCPWM #0, Counter #259 */ + tcpwm_0_interrupts_260_IRQn = 135, /*!< 135 [Active] TCPWM #0, Counter #260 */ + tcpwm_0_interrupts_261_IRQn = 136, /*!< 136 [Active] TCPWM #0, Counter #261 */ + tcpwm_0_interrupts_262_IRQn = 137, /*!< 137 [Active] TCPWM #0, Counter #262 */ + tcpwm_0_interrupts_263_IRQn = 138, /*!< 138 [Active] TCPWM #0, Counter #263 */ + pass_interrupt_dacs_IRQn = 146, /*!< 146 [Active] Consolidated interrrupt for all DACs */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + canfd_0_interrupt0_IRQn = 168, /*!< 168 [Active] Can #0, Consolidated interrupt #0 */ + canfd_0_interrupts0_0_IRQn = 169, /*!< 169 [Active] CAN #0, Interrupt #0, Channel #0 */ + canfd_0_interrupts1_0_IRQn = 170, /*!< 170 [Active] CAN #0, Interrupt #1, Channel #0 */ + cpuss_interrupts_dw1_29_IRQn = 171, /*!< 171 [Active] CPUSS DataWire #1, Channel #29 */ + cpuss_interrupts_dw1_30_IRQn = 172, /*!< 172 [Active] CPUSS DataWire #1, Channel #30 */ + cpuss_interrupts_dw1_31_IRQn = 173, /*!< 173 [Active] CPUSS DataWire #1, Channel #31 */ + cpuss_interrupts_dw0_29_IRQn = 174, /*!< 174 [Active] CPUSS DataWire #0, Channel #29 */ + unconnected_IRQn =1023 /*!< 1023 Unconnected */ +#endif +} IRQn_Type; + + +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + +/* CY8C4588AZI-H685 interrupts that can be routed to the CM0+ NVIC */ +typedef enum { + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_6_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #6 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + pass_interrupt_sar_0_IRQn = 39, /*!< 39 [DeepSleep] SAR ADC0 interrupt */ + pass_interrupt_sar_1_IRQn = 40, /*!< 40 [DeepSleep] SAR ADC1 interrupt */ + pass_interrupt_ctb_IRQn = 41, /*!< 41 [DeepSleep] individual interrupt per CTB */ + pass_interrupt_fifo_0_IRQn = 43, /*!< 43 [DeepSleep] PASS FIFO0 */ + pass_interrupt_fifo_1_IRQn = 44, /*!< 44 [DeepSleep] PASS FIFO1 */ + scb_0_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #2 */ + scb_4_interrupt_IRQn = 49, /*!< 49 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 50, /*!< 50 [Active] Serial Communication Block #5 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_0_interrupts_256_IRQn = 131, /*!< 131 [Active] TCPWM #0, Counter #256 */ + tcpwm_0_interrupts_257_IRQn = 132, /*!< 132 [Active] TCPWM #0, Counter #257 */ + tcpwm_0_interrupts_258_IRQn = 133, /*!< 133 [Active] TCPWM #0, Counter #258 */ + tcpwm_0_interrupts_259_IRQn = 134, /*!< 134 [Active] TCPWM #0, Counter #259 */ + tcpwm_0_interrupts_260_IRQn = 135, /*!< 135 [Active] TCPWM #0, Counter #260 */ + tcpwm_0_interrupts_261_IRQn = 136, /*!< 136 [Active] TCPWM #0, Counter #261 */ + tcpwm_0_interrupts_262_IRQn = 137, /*!< 137 [Active] TCPWM #0, Counter #262 */ + tcpwm_0_interrupts_263_IRQn = 138, /*!< 138 [Active] TCPWM #0, Counter #263 */ + pass_interrupt_dacs_IRQn = 146, /*!< 146 [Active] Consolidated interrrupt for all DACs */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + canfd_0_interrupt0_IRQn = 168, /*!< 168 [Active] Can #0, Consolidated interrupt #0 */ + canfd_0_interrupts0_0_IRQn = 169, /*!< 169 [Active] CAN #0, Interrupt #0, Channel #0 */ + canfd_0_interrupts1_0_IRQn = 170, /*!< 170 [Active] CAN #0, Interrupt #1, Channel #0 */ + cpuss_interrupts_dw1_29_IRQn = 171, /*!< 171 [Active] CPUSS DataWire #1, Channel #29 */ + cpuss_interrupts_dw1_30_IRQn = 172, /*!< 172 [Active] CPUSS DataWire #1, Channel #30 */ + cpuss_interrupts_dw1_31_IRQn = 173, /*!< 173 [Active] CPUSS DataWire #1, Channel #31 */ + cpuss_interrupts_dw0_29_IRQn = 174, /*!< 174 [Active] CPUSS DataWire #0, Channel #29 */ + disconnected_IRQn =1023 /*!< 1023 Disconnected */ +} cy_en_intr_t; + +#endif + +/******************************************************************************* +* Processor and Core Peripheral Section +*******************************************************************************/ + +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + +/* Configuration of the ARM Cortex-M0+ Processor and Core Peripherals */ +#define __CM0PLUS_REV 0x0001U /*!< CM0PLUS Core Revision */ +#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm0plus.h" /*!< ARM Cortex-M0+ processor and core peripherals */ + +#else + +/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __CM0P_PRESENT 1 /*!< CM0P present or not */ +#define __DTCM_PRESENT 0 /*!< DTCM present or not */ +#define __ICACHE_PRESENT 0 /*!< ICACHE present or not */ +#define __DCACHE_PRESENT 0 /*!< DCACHE present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + +#endif + +/* Memory Blocks */ +#define CY_ROM_BASE 0x00000000UL +#define CY_ROM_SIZE 0x00010000UL +#define CY_SRAM_BASE 0x08000000UL +#define CY_SRAM_SIZE 0x00020000UL +#define CY_FLASH_BASE 0x10000000UL +#define CY_FLASH_SIZE 0x00040000UL +#define CY_EM_EEPROM_BASE 0x14000000UL +#define CY_EM_EEPROM_SIZE 0x00000000UL +#define CY_SFLASH_BASE 0x16000000UL +#define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL +#define CY_EFUSE_BASE 0x402C0800UL +#define CY_EFUSE_SIZE 0x00000200UL +#define CY_CAN0MRAM_BASE 0x40530000UL +#define CY_CAN0MRAM_SIZE 0x00010000UL + +#include "system_psoc6.h" /*!< PSoC 6 System */ + +/* IP List */ +#define CY_IP_MXTTCANFD 1u +#define CY_IP_MXTTCANFD_INSTANCES 1u +#define CY_IP_MXTTCANFD_VERSION 1u +#define CY_IP_M4CPUSS 1u +#define CY_IP_M4CPUSS_INSTANCES 1u +#define CY_IP_M4CPUSS_VERSION 2u +#define CY_IP_M4CPUSS_DMAC 1u +#define CY_IP_M4CPUSS_DMAC_INSTANCES 1u +#define CY_IP_M4CPUSS_DMAC_VERSION 2u +#define CY_IP_M4CPUSS_DMA 1u +#define CY_IP_M4CPUSS_DMA_INSTANCES 2u +#define CY_IP_M4CPUSS_DMA_VERSION 2u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 2u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 6u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u + +#include "psoc6_04_config.h" +#include "gpio_psoc6_04_64_tqfp.h" + +#define CY_DEVICE_PSOC6A256K +#define CY_SILICON_ID 0xEAFF110EUL +#define CY_HF_CLK_MAX_FREQ 150000000UL + +#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL + +/******************************************************************************* +* SFLASH +*******************************************************************************/ + +#define SFLASH_BASE 0x16000000UL +#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */ + +/******************************************************************************* +* PERI +*******************************************************************************/ + +#define PERI_BASE 0x40000000UL +#define PERI ((PERI_Type*) PERI_BASE) /* 0x40000000 */ +#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40004000 */ +#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40004020 */ +#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40004040 */ +#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x40004060 */ +#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40004080 */ +#define PERI_GR5 ((PERI_GR_Type*) &PERI->GR[5]) /* 0x400040A0 */ +#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x400040C0 */ +#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40004120 */ +#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40008000 */ +#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40008400 */ +#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40008800 */ +#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40008C00 */ +#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40009000 */ +#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40009400 */ +#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40009800 */ +#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40009C00 */ +#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ +#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ +#define PERI_TR_GR10 ((PERI_TR_GR_Type*) &PERI->TR_GR[10]) /* 0x4000A800 */ +#define PERI_TR_GR11 ((PERI_TR_GR_Type*) &PERI->TR_GR[11]) /* 0x4000AC00 */ +#define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ +#define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ +#define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ +#define PERI_TR_1TO1_GR3 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[3]) /* 0x4000CC00 */ +#define PERI_TR_1TO1_GR4 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[4]) /* 0x4000D000 */ +#define PERI_TR_1TO1_GR5 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[5]) /* 0x4000D400 */ +#define PERI_TR_1TO1_GR6 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[6]) /* 0x4000D800 */ +#define PERI_TR_1TO1_GR7 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[7]) /* 0x4000DC00 */ +#define PERI_TR_1TO1_GR8 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[8]) /* 0x4000E000 */ + +/******************************************************************************* +* PERI_MS +*******************************************************************************/ + +#define PERI_MS_BASE 0x40010000UL +#define PERI_MS ((PERI_MS_Type*) PERI_MS_BASE) /* 0x40010000 */ +#define PERI_MS_PPU_PR0 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[0]) /* 0x40010000 */ +#define PERI_MS_PPU_PR1 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[1]) /* 0x40010040 */ +#define PERI_MS_PPU_PR2 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[2]) /* 0x40010080 */ +#define PERI_MS_PPU_PR3 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[3]) /* 0x400100C0 */ +#define PERI_MS_PPU_PR4 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[4]) /* 0x40010100 */ +#define PERI_MS_PPU_PR5 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[5]) /* 0x40010140 */ +#define PERI_MS_PPU_PR6 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[6]) /* 0x40010180 */ +#define PERI_MS_PPU_PR7 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[7]) /* 0x400101C0 */ +#define PERI_MS_PPU_FX_PERI_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[0]) /* 0x40010800 */ +#define PERI_MS_PPU_FX_PERI_GR0_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[1]) /* 0x40010840 */ +#define PERI_MS_PPU_FX_PERI_GR1_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[2]) /* 0x40010880 */ +#define PERI_MS_PPU_FX_PERI_GR2_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[3]) /* 0x400108C0 */ +#define PERI_MS_PPU_FX_PERI_GR3_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[4]) /* 0x40010900 */ +#define PERI_MS_PPU_FX_PERI_GR4_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[5]) /* 0x40010940 */ +#define PERI_MS_PPU_FX_PERI_GR5_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[6]) /* 0x40010980 */ +#define PERI_MS_PPU_FX_PERI_GR6_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[7]) /* 0x400109C0 */ +#define PERI_MS_PPU_FX_PERI_GR9_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[8]) /* 0x40010A00 */ +#define PERI_MS_PPU_FX_PERI_TR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[9]) /* 0x40010A40 */ +#define PERI_MS_PPU_FX_CRYPTO_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[10]) /* 0x40010A80 */ +#define PERI_MS_PPU_FX_CRYPTO_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[11]) /* 0x40010AC0 */ +#define PERI_MS_PPU_FX_CRYPTO_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[12]) /* 0x40010B00 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[13]) /* 0x40010B40 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[14]) /* 0x40010B80 */ +#define PERI_MS_PPU_FX_CRYPTO_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[15]) /* 0x40010BC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[16]) /* 0x40010C00 */ +#define PERI_MS_PPU_FX_CPUSS_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[17]) /* 0x40010C40 */ +#define PERI_MS_PPU_FX_CPUSS_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[18]) /* 0x40010C80 */ +#define PERI_MS_PPU_FX_CPUSS_CM0_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[19]) /* 0x40010CC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[20]) /* 0x40010D00 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[21]) /* 0x40010D40 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT1_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[22]) /* 0x40010D80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT0_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[23]) /* 0x40010DC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT1_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[24]) /* 0x40010E00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT2_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[25]) /* 0x40010E40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT3_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[26]) /* 0x40010E80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT4_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[27]) /* 0x40010EC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT5_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[28]) /* 0x40010F00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT6_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[29]) /* 0x40010F40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT7_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[30]) /* 0x40010F80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT8_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[31]) /* 0x40010FC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT9_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[32]) /* 0x40011000 */ +#define PERI_MS_PPU_FX_IPC_STRUCT10_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[33]) /* 0x40011040 */ +#define PERI_MS_PPU_FX_IPC_STRUCT11_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[34]) /* 0x40011080 */ +#define PERI_MS_PPU_FX_IPC_STRUCT12_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[35]) /* 0x400110C0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT13_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[36]) /* 0x40011100 */ +#define PERI_MS_PPU_FX_IPC_STRUCT14_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[37]) /* 0x40011140 */ +#define PERI_MS_PPU_FX_IPC_STRUCT15_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[38]) /* 0x40011180 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT0_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[39]) /* 0x400111C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT1_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[40]) /* 0x40011200 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT2_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[41]) /* 0x40011240 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT3_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[42]) /* 0x40011280 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT4_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[43]) /* 0x400112C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT5_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[44]) /* 0x40011300 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT6_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[45]) /* 0x40011340 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT7_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[46]) /* 0x40011380 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT8_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[47]) /* 0x400113C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT9_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[48]) /* 0x40011400 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT10_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[49]) /* 0x40011440 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT11_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[50]) /* 0x40011480 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT12_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[51]) /* 0x400114C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT13_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[52]) /* 0x40011500 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT14_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[53]) /* 0x40011540 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT15_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[54]) /* 0x40011580 */ +#define PERI_MS_PPU_FX_PROT_SMPU_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[55]) /* 0x400115C0 */ +#define PERI_MS_PPU_FX_PROT_MPU0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[56]) /* 0x40011600 */ +#define PERI_MS_PPU_FX_PROT_MPU14_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[57]) /* 0x40011640 */ +#define PERI_MS_PPU_FX_PROT_MPU15_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[58]) /* 0x40011680 */ +#define PERI_MS_PPU_FX_FLASHC_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[59]) /* 0x400116C0 */ +#define PERI_MS_PPU_FX_FLASHC_CMD ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[60]) /* 0x40011700 */ +#define PERI_MS_PPU_FX_FLASHC_DFT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[61]) /* 0x40011740 */ +#define PERI_MS_PPU_FX_FLASHC_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[62]) /* 0x40011780 */ +#define PERI_MS_PPU_FX_FLASHC_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[63]) /* 0x400117C0 */ +#define PERI_MS_PPU_FX_FLASHC_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[64]) /* 0x40011800 */ +#define PERI_MS_PPU_FX_FLASHC_DW0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[65]) /* 0x40011840 */ +#define PERI_MS_PPU_FX_FLASHC_DW1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[66]) /* 0x40011880 */ +#define PERI_MS_PPU_FX_FLASHC_DMAC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[67]) /* 0x400118C0 */ +#define PERI_MS_PPU_FX_FLASHC_FM ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[68]) /* 0x40011900 */ +#define PERI_MS_PPU_FX_SRSS_MAIN1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[69]) /* 0x40011940 */ +#define PERI_MS_PPU_FX_SRSS_MAIN2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[70]) /* 0x40011980 */ +#define PERI_MS_PPU_FX_WDT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[71]) /* 0x400119C0 */ +#define PERI_MS_PPU_FX_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[72]) /* 0x40011A00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[73]) /* 0x40011A40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[74]) /* 0x40011A80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[75]) /* 0x40011AC0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[76]) /* 0x40011B00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[77]) /* 0x40011B40 */ +#define PERI_MS_PPU_FX_BACKUP_BACKUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[78]) /* 0x40011B80 */ +#define PERI_MS_PPU_FX_DW0_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[79]) /* 0x40011BC0 */ +#define PERI_MS_PPU_FX_DW1_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[80]) /* 0x40011C00 */ +#define PERI_MS_PPU_FX_DW0_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[81]) /* 0x40011C40 */ +#define PERI_MS_PPU_FX_DW1_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[82]) /* 0x40011C80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[83]) /* 0x40011CC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[84]) /* 0x40011D00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[85]) /* 0x40011D40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[86]) /* 0x40011D80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[87]) /* 0x40011DC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[88]) /* 0x40011E00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[89]) /* 0x40011E40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[90]) /* 0x40011E80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[91]) /* 0x40011EC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[92]) /* 0x40011F00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[93]) /* 0x40011F40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[94]) /* 0x40011F80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[95]) /* 0x40011FC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[96]) /* 0x40012000 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[97]) /* 0x40012040 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[98]) /* 0x40012080 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[99]) /* 0x400120C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[100]) /* 0x40012100 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[101]) /* 0x40012140 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[102]) /* 0x40012180 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[103]) /* 0x400121C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[104]) /* 0x40012200 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[105]) /* 0x40012240 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[106]) /* 0x40012280 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[107]) /* 0x400122C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[108]) /* 0x40012300 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[109]) /* 0x40012340 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[110]) /* 0x40012380 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[111]) /* 0x400123C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT29_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[112]) /* 0x40012400 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[113]) /* 0x40012440 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[114]) /* 0x40012480 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[115]) /* 0x400124C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[116]) /* 0x40012500 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[117]) /* 0x40012540 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[118]) /* 0x40012580 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[119]) /* 0x400125C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[120]) /* 0x40012600 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[121]) /* 0x40012640 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[122]) /* 0x40012680 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[123]) /* 0x400126C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[124]) /* 0x40012700 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[125]) /* 0x40012740 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[126]) /* 0x40012780 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[127]) /* 0x400127C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[128]) /* 0x40012800 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[129]) /* 0x40012840 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[130]) /* 0x40012880 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[131]) /* 0x400128C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[132]) /* 0x40012900 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[133]) /* 0x40012940 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[134]) /* 0x40012980 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[135]) /* 0x400129C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[136]) /* 0x40012A00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[137]) /* 0x40012A40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[138]) /* 0x40012A80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[139]) /* 0x40012AC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[140]) /* 0x40012B00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[141]) /* 0x40012B40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT29_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[142]) /* 0x40012B80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT30_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[143]) /* 0x40012BC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT31_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[144]) /* 0x40012C00 */ +#define PERI_MS_PPU_FX_DMAC_TOP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[145]) /* 0x40012C40 */ +#define PERI_MS_PPU_FX_DMAC_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[146]) /* 0x40012C80 */ +#define PERI_MS_PPU_FX_DMAC_CH1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[147]) /* 0x40012CC0 */ +#define PERI_MS_PPU_FX_EFUSE_CTL ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[148]) /* 0x40012D00 */ +#define PERI_MS_PPU_FX_EFUSE_DATA ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[149]) /* 0x40012D40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[150]) /* 0x40012D80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[151]) /* 0x40012DC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[152]) /* 0x40012E00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[153]) /* 0x40012E40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[154]) /* 0x40012E80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[155]) /* 0x40012EC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[156]) /* 0x40012F00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[157]) /* 0x40012F40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[158]) /* 0x40012F80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[159]) /* 0x40012FC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[160]) /* 0x40013000 */ +#define PERI_MS_PPU_FX_HSIOM_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[161]) /* 0x40013040 */ +#define PERI_MS_PPU_FX_HSIOM_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[162]) /* 0x40013080 */ +#define PERI_MS_PPU_FX_HSIOM_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[163]) /* 0x400130C0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[164]) /* 0x40013100 */ +#define PERI_MS_PPU_FX_HSIOM_AMUX ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[165]) /* 0x40013140 */ +#define PERI_MS_PPU_FX_HSIOM_MON ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[166]) /* 0x40013180 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[167]) /* 0x400131C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[168]) /* 0x40013200 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[169]) /* 0x40013240 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[170]) /* 0x40013280 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[171]) /* 0x400132C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[172]) /* 0x40013300 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[173]) /* 0x40013340 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[174]) /* 0x40013380 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[175]) /* 0x400133C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[176]) /* 0x40013400 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[177]) /* 0x40013440 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[178]) /* 0x40013480 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[179]) /* 0x400134C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[180]) /* 0x40013500 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[181]) /* 0x40013540 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[182]) /* 0x40013580 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[183]) /* 0x400135C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[184]) /* 0x40013600 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[185]) /* 0x40013640 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[186]) /* 0x40013680 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[187]) /* 0x400136C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[188]) /* 0x40013700 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[189]) /* 0x40013740 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[190]) /* 0x40013780 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[191]) /* 0x400137C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[192]) /* 0x40013800 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[193]) /* 0x40013840 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[194]) /* 0x40013880 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[195]) /* 0x400138C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[196]) /* 0x40013900 */ +#define PERI_MS_PPU_FX_GPIO_GPIO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[197]) /* 0x40013940 */ +#define PERI_MS_PPU_FX_GPIO_TEST ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[198]) /* 0x40013980 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[199]) /* 0x400139C0 */ +#define PERI_MS_PPU_FX_LPCOMP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[200]) /* 0x40013A00 */ +#define PERI_MS_PPU_FX_CSD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[201]) /* 0x40013A40 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT0_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[202]) /* 0x40013A80 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT1_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[203]) /* 0x40013AC0 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT2_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[204]) /* 0x40013B00 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT3_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[205]) /* 0x40013B40 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT0_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[206]) /* 0x40013B80 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT1_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[207]) /* 0x40013BC0 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT2_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[208]) /* 0x40013C00 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT3_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[209]) /* 0x40013C40 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT4_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[210]) /* 0x40013C80 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT5_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[211]) /* 0x40013CC0 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT6_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[212]) /* 0x40013D00 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT7_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[213]) /* 0x40013D40 */ +#define PERI_MS_PPU_FX_LCD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[214]) /* 0x40013D80 */ +#define PERI_MS_PPU_FX_USBFS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[215]) /* 0x40013DC0 */ +#define PERI_MS_PPU_FX_SMIF0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[216]) /* 0x40013E00 */ +#define PERI_MS_PPU_FX_CANFD0_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[217]) /* 0x40013E40 */ +#define PERI_MS_PPU_FX_CANFD0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[218]) /* 0x40013E80 */ +#define PERI_MS_PPU_FX_CANFD0_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[219]) /* 0x40013EC0 */ +#define PERI_MS_PPU_FX_SCB0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[220]) /* 0x40013F00 */ +#define PERI_MS_PPU_FX_SCB1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[221]) /* 0x40013F40 */ +#define PERI_MS_PPU_FX_SCB2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[222]) /* 0x40013F80 */ +#define PERI_MS_PPU_FX_SCB4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[223]) /* 0x40013FC0 */ +#define PERI_MS_PPU_FX_SCB5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[224]) /* 0x40014000 */ +#define PERI_MS_PPU_FX_SCB6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[225]) /* 0x40014040 */ + +/******************************************************************************* +* CPUSS +*******************************************************************************/ + +#define CPUSS_BASE 0x40200000UL +#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40200000 */ + +/******************************************************************************* +* FAULT +*******************************************************************************/ + +#define FAULT_BASE 0x40210000UL +#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40210000 */ +#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40210000 */ +#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40210100 */ + +/******************************************************************************* +* IPC +*******************************************************************************/ + +#define IPC_BASE 0x40220000UL +#define IPC ((IPC_Type*) IPC_BASE) /* 0x40220000 */ +#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40220000 */ +#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40220020 */ +#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40220040 */ +#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40220060 */ +#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40220080 */ +#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402200A0 */ +#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402200C0 */ +#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402200E0 */ +#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40220100 */ +#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40220120 */ +#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40220140 */ +#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40220160 */ +#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40220180 */ +#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402201A0 */ +#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402201C0 */ +#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402201E0 */ +#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40221000 */ +#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40221020 */ +#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40221040 */ +#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40221060 */ +#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40221080 */ +#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402210A0 */ +#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402210C0 */ +#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402210E0 */ +#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40221100 */ +#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40221120 */ +#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40221140 */ +#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40221160 */ +#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40221180 */ +#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402211A0 */ +#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402211C0 */ +#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402211E0 */ + +/******************************************************************************* +* PROT +*******************************************************************************/ + +#define PROT_BASE 0x40230000UL +#define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ +#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ +#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ +#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402320C0 */ +#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40232100 */ +#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40232140 */ +#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40232180 */ +#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402321C0 */ +#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40232200 */ +#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40232240 */ +#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40232280 */ +#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402322C0 */ +#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40232300 */ +#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ +#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ +#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ + +/******************************************************************************* +* FLASHC +*******************************************************************************/ + +#define FLASHC_BASE 0x40240000UL +#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40240000 */ +#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4024F000 */ + +/******************************************************************************* +* SRSS +*******************************************************************************/ + +#define SRSS_BASE 0x40260000UL +#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ +#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */ +#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */ + +/******************************************************************************* +* BACKUP +*******************************************************************************/ + +#define BACKUP_BASE 0x40270000UL +#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ + +/******************************************************************************* +* DW +*******************************************************************************/ + +#define DW0_BASE 0x40280000UL +#define DW1_BASE 0x40290000UL +#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ +#define DW1 ((DW_Type*) DW1_BASE) /* 0x40290000 */ +#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40288000 */ +#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40288040 */ +#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40288080 */ +#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x402880C0 */ +#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40288100 */ +#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x40288140 */ +#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x40288180 */ +#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402881C0 */ +#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40288200 */ +#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40288240 */ +#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40288280 */ +#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x402882C0 */ +#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40288300 */ +#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x40288340 */ +#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x40288380 */ +#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402883C0 */ +#define DW0_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[16]) /* 0x40288400 */ +#define DW0_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[17]) /* 0x40288440 */ +#define DW0_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[18]) /* 0x40288480 */ +#define DW0_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[19]) /* 0x402884C0 */ +#define DW0_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[20]) /* 0x40288500 */ +#define DW0_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[21]) /* 0x40288540 */ +#define DW0_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[22]) /* 0x40288580 */ +#define DW0_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[23]) /* 0x402885C0 */ +#define DW0_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[24]) /* 0x40288600 */ +#define DW0_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[25]) /* 0x40288640 */ +#define DW0_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[26]) /* 0x40288680 */ +#define DW0_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[27]) /* 0x402886C0 */ +#define DW0_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[28]) /* 0x40288700 */ +#define DW0_CH_STRUCT29 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[29]) /* 0x40288740 */ +#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40298000 */ +#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40298040 */ +#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40298080 */ +#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x402980C0 */ +#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40298100 */ +#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x40298140 */ +#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x40298180 */ +#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402981C0 */ +#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40298200 */ +#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40298240 */ +#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40298280 */ +#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x402982C0 */ +#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40298300 */ +#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x40298340 */ +#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x40298380 */ +#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402983C0 */ +#define DW1_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[16]) /* 0x40298400 */ +#define DW1_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[17]) /* 0x40298440 */ +#define DW1_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[18]) /* 0x40298480 */ +#define DW1_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[19]) /* 0x402984C0 */ +#define DW1_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[20]) /* 0x40298500 */ +#define DW1_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[21]) /* 0x40298540 */ +#define DW1_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[22]) /* 0x40298580 */ +#define DW1_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[23]) /* 0x402985C0 */ +#define DW1_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[24]) /* 0x40298600 */ +#define DW1_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[25]) /* 0x40298640 */ +#define DW1_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[26]) /* 0x40298680 */ +#define DW1_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[27]) /* 0x402986C0 */ +#define DW1_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[28]) /* 0x40298700 */ +#define DW1_CH_STRUCT29 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[29]) /* 0x40298740 */ +#define DW1_CH_STRUCT30 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[30]) /* 0x40298780 */ +#define DW1_CH_STRUCT31 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[31]) /* 0x402987C0 */ + +/******************************************************************************* +* DMAC +*******************************************************************************/ + +#define DMAC_BASE 0x402A0000UL +#define DMAC ((DMAC_Type*) DMAC_BASE) /* 0x402A0000 */ +#define DMAC_CH0 ((DMAC_CH_Type*) &DMAC->CH[0]) /* 0x402A1000 */ +#define DMAC_CH1 ((DMAC_CH_Type*) &DMAC->CH[1]) /* 0x402A1100 */ + +/******************************************************************************* +* EFUSE +*******************************************************************************/ + +#define EFUSE_BASE 0x402C0000UL +#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ + +/******************************************************************************* +* HSIOM +*******************************************************************************/ + +#define HSIOM_BASE 0x40300000UL +#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40300000 */ +#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40300000 */ +#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40300010 */ +#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40300020 */ +#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40300030 */ +#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40300040 */ +#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40300050 */ +#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40300060 */ +#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40300070 */ +#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40300080 */ +#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40300090 */ +#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403000A0 */ +#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403000B0 */ +#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403000C0 */ +#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403000D0 */ +#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403000E0 */ + +/******************************************************************************* +* GPIO +*******************************************************************************/ + +#define GPIO_BASE 0x40310000UL +#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40310000 */ +#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40310000 */ +#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40310080 */ +#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40310100 */ +#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40310180 */ +#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40310200 */ +#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40310280 */ +#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40310300 */ +#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40310380 */ +#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40310400 */ +#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40310480 */ +#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40310500 */ +#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40310580 */ +#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40310600 */ +#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40310680 */ +#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40310700 */ + +/******************************************************************************* +* SMARTIO +*******************************************************************************/ + +#define SMARTIO_BASE 0x40320000UL +#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40320000 */ +#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40320900 */ + +/******************************************************************************* +* LPCOMP +*******************************************************************************/ + +#define LPCOMP_BASE 0x40350000UL +#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */ + +/******************************************************************************* +* CSD +*******************************************************************************/ + +#define CSD0_BASE 0x40360000UL +#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */ + +/******************************************************************************* +* TCPWM +*******************************************************************************/ + +#define TCPWM0_BASE 0x40380000UL +#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM0_GRP0 ((TCPWM_GRP_Type*) &TCPWM0->GRP[0]) /* 0x40380000 */ +#define TCPWM0_GRP1 ((TCPWM_GRP_Type*) &TCPWM0->GRP[1]) /* 0x40388000 */ +#define TCPWM0_GRP0_CNT0 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[0]) /* 0x40380000 */ +#define TCPWM0_GRP0_CNT1 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[1]) /* 0x40380080 */ +#define TCPWM0_GRP0_CNT2 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[2]) /* 0x40380100 */ +#define TCPWM0_GRP0_CNT3 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[3]) /* 0x40380180 */ +#define TCPWM0_GRP1_CNT0 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[0]) /* 0x40388000 */ +#define TCPWM0_GRP1_CNT1 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[1]) /* 0x40388080 */ +#define TCPWM0_GRP1_CNT2 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[2]) /* 0x40388100 */ +#define TCPWM0_GRP1_CNT3 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[3]) /* 0x40388180 */ +#define TCPWM0_GRP1_CNT4 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[4]) /* 0x40388200 */ +#define TCPWM0_GRP1_CNT5 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[5]) /* 0x40388280 */ +#define TCPWM0_GRP1_CNT6 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[6]) /* 0x40388300 */ +#define TCPWM0_GRP1_CNT7 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[7]) /* 0x40388380 */ + +/******************************************************************************* +* LCD +*******************************************************************************/ + +#define LCD0_BASE 0x403B0000UL +#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ + +/******************************************************************************* +* SMIF +*******************************************************************************/ + +#define SMIF0_BASE 0x40420000UL +#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ +#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ +#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ +#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ + +/******************************************************************************* +* CANFD +*******************************************************************************/ + +#define CANFD0_BASE 0x40520000UL +#define CANFD0 ((CANFD_Type*) CANFD0_BASE) /* 0x40520000 */ +#define CANFD0_CH0 ((CANFD_CH_Type*) &CANFD0->CH[0]) /* 0x40520000 */ +#define CANFD0_CH0_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[0].M_TTCAN) /* 0x40520000 */ + +/******************************************************************************* +* SCB +*******************************************************************************/ + +#define SCB0_BASE 0x40600000UL +#define SCB1_BASE 0x40610000UL +#define SCB2_BASE 0x40620000UL +#define SCB4_BASE 0x40640000UL +#define SCB5_BASE 0x40650000UL +#define SCB6_BASE 0x40660000UL +#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40600000 */ +#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40610000 */ +#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40620000 */ +#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40640000 */ +#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40650000 */ +#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40660000 */ + +/******************************************************************************* +* CTBM +*******************************************************************************/ + +#define CTBM0_BASE 0x40900000UL +#define CTBM0 ((CTBM_Type*) CTBM0_BASE) /* 0x40900000 */ + +/******************************************************************************* +* CTDAC +*******************************************************************************/ + +#define CTDAC0_BASE 0x40940000UL +#define CTDAC0 ((CTDAC_Type*) CTDAC0_BASE) /* 0x40940000 */ + +/******************************************************************************* +* SAR +*******************************************************************************/ + +#define SAR0_BASE 0x409B0000UL +#define SAR1_BASE 0x409C0000UL +#define SAR0 ((SAR_Type*) SAR0_BASE) /* 0x409B0000 */ +#define SAR1 ((SAR_Type*) SAR1_BASE) /* 0x409C0000 */ + +/******************************************************************************* +* PASS +*******************************************************************************/ + +#define PASS_BASE 0x409F0000UL +#define PASS ((PASS_Type*) PASS_BASE) /* 0x409F0000 */ +#define PASS_TIMER ((PASS_TIMER_Type*) &PASS->TIMER) /* 0x409F0100 */ +#define PASS_LPOSC ((PASS_LPOSC_Type*) &PASS->LPOSC) /* 0x409F0200 */ +#define PASS_FIFO0 ((PASS_FIFO_Type*) &PASS->FIFO[0]) /* 0x409F0300 */ +#define PASS_FIFO1 ((PASS_FIFO_Type*) &PASS->FIFO[1]) /* 0x409F0400 */ +#define PASS_AREFV2 ((PASS_AREFV2_Type*) &PASS->AREFV2) /* 0x409F0E00 */ + +/** \} CY8C4588AZI-H685 */ + +#endif /* _CY8C4588AZI_H685_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c4588azi_h686.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c4588azi_h686.h new file mode 100644 index 0000000000..a9e030aeda --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c4588azi_h686.h @@ -0,0 +1,1173 @@ +/***************************************************************************//** +* \file cy8c4588azi_h686.h +* +* \brief +* CY8C4588AZI-H686 device header +* +* \note +* Generator version: 1.6.0.225 +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CY8C4588AZI_H686_H_ +#define _CY8C4588AZI_H686_H_ + +/** +* \addtogroup group_device CY8C4588AZI-H686 +* \{ +*/ + +/** +* \addtogroup Configuration_of_CMSIS +* \{ +*/ + +/******************************************************************************* +* Interrupt Number Definition +*******************************************************************************/ + +typedef enum { +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + /* ARM Cortex-M0+ Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C4588AZI-H686 User Interrupt Numbers */ + NvicMux0_IRQn = 0, /*!< 0 [DeepSleep] CPU User Interrupt #0 */ + NvicMux1_IRQn = 1, /*!< 1 [DeepSleep] CPU User Interrupt #1 */ + NvicMux2_IRQn = 2, /*!< 2 [DeepSleep] CPU User Interrupt #2 */ + NvicMux3_IRQn = 3, /*!< 3 [DeepSleep] CPU User Interrupt #3 */ + NvicMux4_IRQn = 4, /*!< 4 [DeepSleep] CPU User Interrupt #4 */ + NvicMux5_IRQn = 5, /*!< 5 [DeepSleep] CPU User Interrupt #5 */ + NvicMux6_IRQn = 6, /*!< 6 [DeepSleep] CPU User Interrupt #6 */ + NvicMux7_IRQn = 7, /*!< 7 [DeepSleep] CPU User Interrupt #7 */ + /* CY8C4588AZI-H686 Internal SW Interrupt Numbers */ + Internal0_IRQn = 8, /*!< 8 [Active] Internal SW Interrupt #0 */ + Internal1_IRQn = 9, /*!< 9 [Active] Internal SW Interrupt #1 */ + Internal2_IRQn = 10, /*!< 10 [Active] Internal SW Interrupt #2 */ + Internal3_IRQn = 11, /*!< 11 [Active] Internal SW Interrupt #3 */ + Internal4_IRQn = 12, /*!< 12 [Active] Internal SW Interrupt #4 */ + Internal5_IRQn = 13, /*!< 13 [Active] Internal SW Interrupt #5 */ + Internal6_IRQn = 14, /*!< 14 [Active] Internal SW Interrupt #6 */ + Internal7_IRQn = 15, /*!< 15 [Active] Internal SW Interrupt #7 */ + unconnected_IRQn =1023 /*!< 1023 Unconnected */ +#else + /* ARM Cortex-M4 Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C4588AZI-H686 Peripheral Interrupt Numbers */ + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_6_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #6 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + pass_interrupt_sar_0_IRQn = 39, /*!< 39 [DeepSleep] SAR ADC0 interrupt */ + pass_interrupt_sar_1_IRQn = 40, /*!< 40 [DeepSleep] SAR ADC1 interrupt */ + pass_interrupt_ctb_IRQn = 41, /*!< 41 [DeepSleep] individual interrupt per CTB */ + pass_interrupt_fifo_0_IRQn = 43, /*!< 43 [DeepSleep] PASS FIFO0 */ + pass_interrupt_fifo_1_IRQn = 44, /*!< 44 [DeepSleep] PASS FIFO1 */ + scb_0_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #2 */ + scb_4_interrupt_IRQn = 49, /*!< 49 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 50, /*!< 50 [Active] Serial Communication Block #5 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_0_interrupts_256_IRQn = 131, /*!< 131 [Active] TCPWM #0, Counter #256 */ + tcpwm_0_interrupts_257_IRQn = 132, /*!< 132 [Active] TCPWM #0, Counter #257 */ + tcpwm_0_interrupts_258_IRQn = 133, /*!< 133 [Active] TCPWM #0, Counter #258 */ + tcpwm_0_interrupts_259_IRQn = 134, /*!< 134 [Active] TCPWM #0, Counter #259 */ + tcpwm_0_interrupts_260_IRQn = 135, /*!< 135 [Active] TCPWM #0, Counter #260 */ + tcpwm_0_interrupts_261_IRQn = 136, /*!< 136 [Active] TCPWM #0, Counter #261 */ + tcpwm_0_interrupts_262_IRQn = 137, /*!< 137 [Active] TCPWM #0, Counter #262 */ + tcpwm_0_interrupts_263_IRQn = 138, /*!< 138 [Active] TCPWM #0, Counter #263 */ + pass_interrupt_dacs_IRQn = 146, /*!< 146 [Active] Consolidated interrrupt for all DACs */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + canfd_0_interrupt0_IRQn = 168, /*!< 168 [Active] Can #0, Consolidated interrupt #0 */ + canfd_0_interrupts0_0_IRQn = 169, /*!< 169 [Active] CAN #0, Interrupt #0, Channel #0 */ + canfd_0_interrupts1_0_IRQn = 170, /*!< 170 [Active] CAN #0, Interrupt #1, Channel #0 */ + cpuss_interrupts_dw1_29_IRQn = 171, /*!< 171 [Active] CPUSS DataWire #1, Channel #29 */ + cpuss_interrupts_dw1_30_IRQn = 172, /*!< 172 [Active] CPUSS DataWire #1, Channel #30 */ + cpuss_interrupts_dw1_31_IRQn = 173, /*!< 173 [Active] CPUSS DataWire #1, Channel #31 */ + cpuss_interrupts_dw0_29_IRQn = 174, /*!< 174 [Active] CPUSS DataWire #0, Channel #29 */ + unconnected_IRQn =1023 /*!< 1023 Unconnected */ +#endif +} IRQn_Type; + + +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + +/* CY8C4588AZI-H686 interrupts that can be routed to the CM0+ NVIC */ +typedef enum { + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_6_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #6 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + pass_interrupt_sar_0_IRQn = 39, /*!< 39 [DeepSleep] SAR ADC0 interrupt */ + pass_interrupt_sar_1_IRQn = 40, /*!< 40 [DeepSleep] SAR ADC1 interrupt */ + pass_interrupt_ctb_IRQn = 41, /*!< 41 [DeepSleep] individual interrupt per CTB */ + pass_interrupt_fifo_0_IRQn = 43, /*!< 43 [DeepSleep] PASS FIFO0 */ + pass_interrupt_fifo_1_IRQn = 44, /*!< 44 [DeepSleep] PASS FIFO1 */ + scb_0_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #2 */ + scb_4_interrupt_IRQn = 49, /*!< 49 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 50, /*!< 50 [Active] Serial Communication Block #5 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_0_interrupts_256_IRQn = 131, /*!< 131 [Active] TCPWM #0, Counter #256 */ + tcpwm_0_interrupts_257_IRQn = 132, /*!< 132 [Active] TCPWM #0, Counter #257 */ + tcpwm_0_interrupts_258_IRQn = 133, /*!< 133 [Active] TCPWM #0, Counter #258 */ + tcpwm_0_interrupts_259_IRQn = 134, /*!< 134 [Active] TCPWM #0, Counter #259 */ + tcpwm_0_interrupts_260_IRQn = 135, /*!< 135 [Active] TCPWM #0, Counter #260 */ + tcpwm_0_interrupts_261_IRQn = 136, /*!< 136 [Active] TCPWM #0, Counter #261 */ + tcpwm_0_interrupts_262_IRQn = 137, /*!< 137 [Active] TCPWM #0, Counter #262 */ + tcpwm_0_interrupts_263_IRQn = 138, /*!< 138 [Active] TCPWM #0, Counter #263 */ + pass_interrupt_dacs_IRQn = 146, /*!< 146 [Active] Consolidated interrrupt for all DACs */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + canfd_0_interrupt0_IRQn = 168, /*!< 168 [Active] Can #0, Consolidated interrupt #0 */ + canfd_0_interrupts0_0_IRQn = 169, /*!< 169 [Active] CAN #0, Interrupt #0, Channel #0 */ + canfd_0_interrupts1_0_IRQn = 170, /*!< 170 [Active] CAN #0, Interrupt #1, Channel #0 */ + cpuss_interrupts_dw1_29_IRQn = 171, /*!< 171 [Active] CPUSS DataWire #1, Channel #29 */ + cpuss_interrupts_dw1_30_IRQn = 172, /*!< 172 [Active] CPUSS DataWire #1, Channel #30 */ + cpuss_interrupts_dw1_31_IRQn = 173, /*!< 173 [Active] CPUSS DataWire #1, Channel #31 */ + cpuss_interrupts_dw0_29_IRQn = 174, /*!< 174 [Active] CPUSS DataWire #0, Channel #29 */ + disconnected_IRQn =1023 /*!< 1023 Disconnected */ +} cy_en_intr_t; + +#endif + +/******************************************************************************* +* Processor and Core Peripheral Section +*******************************************************************************/ + +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + +/* Configuration of the ARM Cortex-M0+ Processor and Core Peripherals */ +#define __CM0PLUS_REV 0x0001U /*!< CM0PLUS Core Revision */ +#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm0plus.h" /*!< ARM Cortex-M0+ processor and core peripherals */ + +#else + +/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __CM0P_PRESENT 1 /*!< CM0P present or not */ +#define __DTCM_PRESENT 0 /*!< DTCM present or not */ +#define __ICACHE_PRESENT 0 /*!< ICACHE present or not */ +#define __DCACHE_PRESENT 0 /*!< DCACHE present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + +#endif + +/* Memory Blocks */ +#define CY_ROM_BASE 0x00000000UL +#define CY_ROM_SIZE 0x00010000UL +#define CY_SRAM_BASE 0x08000000UL +#define CY_SRAM_SIZE 0x00020000UL +#define CY_FLASH_BASE 0x10000000UL +#define CY_FLASH_SIZE 0x00040000UL +#define CY_EM_EEPROM_BASE 0x14000000UL +#define CY_EM_EEPROM_SIZE 0x00000000UL +#define CY_SFLASH_BASE 0x16000000UL +#define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL +#define CY_EFUSE_BASE 0x402C0800UL +#define CY_EFUSE_SIZE 0x00000200UL +#define CY_CAN0MRAM_BASE 0x40530000UL +#define CY_CAN0MRAM_SIZE 0x00010000UL + +#include "system_psoc6.h" /*!< PSoC 6 System */ + +/* IP List */ +#define CY_IP_MXTTCANFD 1u +#define CY_IP_MXTTCANFD_INSTANCES 1u +#define CY_IP_MXTTCANFD_VERSION 1u +#define CY_IP_M4CPUSS 1u +#define CY_IP_M4CPUSS_INSTANCES 1u +#define CY_IP_M4CPUSS_VERSION 2u +#define CY_IP_M4CPUSS_DMAC 1u +#define CY_IP_M4CPUSS_DMAC_INSTANCES 1u +#define CY_IP_M4CPUSS_DMAC_VERSION 2u +#define CY_IP_M4CPUSS_DMA 1u +#define CY_IP_M4CPUSS_DMA_INSTANCES 2u +#define CY_IP_M4CPUSS_DMA_VERSION 2u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 2u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 6u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u + +#include "psoc6_04_config.h" +#include "gpio_psoc6_04_80_tqfp.h" + +#define CY_DEVICE_PSOC6A256K +#define CY_SILICON_ID 0xEAFE110EUL +#define CY_HF_CLK_MAX_FREQ 150000000UL + +#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL + +/******************************************************************************* +* SFLASH +*******************************************************************************/ + +#define SFLASH_BASE 0x16000000UL +#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */ + +/******************************************************************************* +* PERI +*******************************************************************************/ + +#define PERI_BASE 0x40000000UL +#define PERI ((PERI_Type*) PERI_BASE) /* 0x40000000 */ +#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40004000 */ +#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40004020 */ +#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40004040 */ +#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x40004060 */ +#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40004080 */ +#define PERI_GR5 ((PERI_GR_Type*) &PERI->GR[5]) /* 0x400040A0 */ +#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x400040C0 */ +#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40004120 */ +#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40008000 */ +#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40008400 */ +#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40008800 */ +#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40008C00 */ +#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40009000 */ +#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40009400 */ +#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40009800 */ +#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40009C00 */ +#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ +#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ +#define PERI_TR_GR10 ((PERI_TR_GR_Type*) &PERI->TR_GR[10]) /* 0x4000A800 */ +#define PERI_TR_GR11 ((PERI_TR_GR_Type*) &PERI->TR_GR[11]) /* 0x4000AC00 */ +#define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ +#define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ +#define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ +#define PERI_TR_1TO1_GR3 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[3]) /* 0x4000CC00 */ +#define PERI_TR_1TO1_GR4 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[4]) /* 0x4000D000 */ +#define PERI_TR_1TO1_GR5 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[5]) /* 0x4000D400 */ +#define PERI_TR_1TO1_GR6 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[6]) /* 0x4000D800 */ +#define PERI_TR_1TO1_GR7 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[7]) /* 0x4000DC00 */ +#define PERI_TR_1TO1_GR8 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[8]) /* 0x4000E000 */ + +/******************************************************************************* +* PERI_MS +*******************************************************************************/ + +#define PERI_MS_BASE 0x40010000UL +#define PERI_MS ((PERI_MS_Type*) PERI_MS_BASE) /* 0x40010000 */ +#define PERI_MS_PPU_PR0 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[0]) /* 0x40010000 */ +#define PERI_MS_PPU_PR1 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[1]) /* 0x40010040 */ +#define PERI_MS_PPU_PR2 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[2]) /* 0x40010080 */ +#define PERI_MS_PPU_PR3 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[3]) /* 0x400100C0 */ +#define PERI_MS_PPU_PR4 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[4]) /* 0x40010100 */ +#define PERI_MS_PPU_PR5 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[5]) /* 0x40010140 */ +#define PERI_MS_PPU_PR6 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[6]) /* 0x40010180 */ +#define PERI_MS_PPU_PR7 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[7]) /* 0x400101C0 */ +#define PERI_MS_PPU_FX_PERI_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[0]) /* 0x40010800 */ +#define PERI_MS_PPU_FX_PERI_GR0_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[1]) /* 0x40010840 */ +#define PERI_MS_PPU_FX_PERI_GR1_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[2]) /* 0x40010880 */ +#define PERI_MS_PPU_FX_PERI_GR2_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[3]) /* 0x400108C0 */ +#define PERI_MS_PPU_FX_PERI_GR3_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[4]) /* 0x40010900 */ +#define PERI_MS_PPU_FX_PERI_GR4_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[5]) /* 0x40010940 */ +#define PERI_MS_PPU_FX_PERI_GR5_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[6]) /* 0x40010980 */ +#define PERI_MS_PPU_FX_PERI_GR6_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[7]) /* 0x400109C0 */ +#define PERI_MS_PPU_FX_PERI_GR9_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[8]) /* 0x40010A00 */ +#define PERI_MS_PPU_FX_PERI_TR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[9]) /* 0x40010A40 */ +#define PERI_MS_PPU_FX_CRYPTO_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[10]) /* 0x40010A80 */ +#define PERI_MS_PPU_FX_CRYPTO_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[11]) /* 0x40010AC0 */ +#define PERI_MS_PPU_FX_CRYPTO_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[12]) /* 0x40010B00 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[13]) /* 0x40010B40 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[14]) /* 0x40010B80 */ +#define PERI_MS_PPU_FX_CRYPTO_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[15]) /* 0x40010BC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[16]) /* 0x40010C00 */ +#define PERI_MS_PPU_FX_CPUSS_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[17]) /* 0x40010C40 */ +#define PERI_MS_PPU_FX_CPUSS_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[18]) /* 0x40010C80 */ +#define PERI_MS_PPU_FX_CPUSS_CM0_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[19]) /* 0x40010CC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[20]) /* 0x40010D00 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[21]) /* 0x40010D40 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT1_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[22]) /* 0x40010D80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT0_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[23]) /* 0x40010DC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT1_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[24]) /* 0x40010E00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT2_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[25]) /* 0x40010E40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT3_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[26]) /* 0x40010E80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT4_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[27]) /* 0x40010EC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT5_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[28]) /* 0x40010F00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT6_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[29]) /* 0x40010F40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT7_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[30]) /* 0x40010F80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT8_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[31]) /* 0x40010FC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT9_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[32]) /* 0x40011000 */ +#define PERI_MS_PPU_FX_IPC_STRUCT10_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[33]) /* 0x40011040 */ +#define PERI_MS_PPU_FX_IPC_STRUCT11_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[34]) /* 0x40011080 */ +#define PERI_MS_PPU_FX_IPC_STRUCT12_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[35]) /* 0x400110C0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT13_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[36]) /* 0x40011100 */ +#define PERI_MS_PPU_FX_IPC_STRUCT14_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[37]) /* 0x40011140 */ +#define PERI_MS_PPU_FX_IPC_STRUCT15_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[38]) /* 0x40011180 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT0_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[39]) /* 0x400111C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT1_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[40]) /* 0x40011200 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT2_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[41]) /* 0x40011240 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT3_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[42]) /* 0x40011280 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT4_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[43]) /* 0x400112C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT5_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[44]) /* 0x40011300 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT6_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[45]) /* 0x40011340 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT7_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[46]) /* 0x40011380 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT8_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[47]) /* 0x400113C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT9_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[48]) /* 0x40011400 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT10_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[49]) /* 0x40011440 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT11_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[50]) /* 0x40011480 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT12_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[51]) /* 0x400114C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT13_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[52]) /* 0x40011500 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT14_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[53]) /* 0x40011540 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT15_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[54]) /* 0x40011580 */ +#define PERI_MS_PPU_FX_PROT_SMPU_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[55]) /* 0x400115C0 */ +#define PERI_MS_PPU_FX_PROT_MPU0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[56]) /* 0x40011600 */ +#define PERI_MS_PPU_FX_PROT_MPU14_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[57]) /* 0x40011640 */ +#define PERI_MS_PPU_FX_PROT_MPU15_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[58]) /* 0x40011680 */ +#define PERI_MS_PPU_FX_FLASHC_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[59]) /* 0x400116C0 */ +#define PERI_MS_PPU_FX_FLASHC_CMD ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[60]) /* 0x40011700 */ +#define PERI_MS_PPU_FX_FLASHC_DFT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[61]) /* 0x40011740 */ +#define PERI_MS_PPU_FX_FLASHC_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[62]) /* 0x40011780 */ +#define PERI_MS_PPU_FX_FLASHC_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[63]) /* 0x400117C0 */ +#define PERI_MS_PPU_FX_FLASHC_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[64]) /* 0x40011800 */ +#define PERI_MS_PPU_FX_FLASHC_DW0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[65]) /* 0x40011840 */ +#define PERI_MS_PPU_FX_FLASHC_DW1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[66]) /* 0x40011880 */ +#define PERI_MS_PPU_FX_FLASHC_DMAC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[67]) /* 0x400118C0 */ +#define PERI_MS_PPU_FX_FLASHC_FM ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[68]) /* 0x40011900 */ +#define PERI_MS_PPU_FX_SRSS_MAIN1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[69]) /* 0x40011940 */ +#define PERI_MS_PPU_FX_SRSS_MAIN2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[70]) /* 0x40011980 */ +#define PERI_MS_PPU_FX_WDT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[71]) /* 0x400119C0 */ +#define PERI_MS_PPU_FX_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[72]) /* 0x40011A00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[73]) /* 0x40011A40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[74]) /* 0x40011A80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[75]) /* 0x40011AC0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[76]) /* 0x40011B00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[77]) /* 0x40011B40 */ +#define PERI_MS_PPU_FX_BACKUP_BACKUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[78]) /* 0x40011B80 */ +#define PERI_MS_PPU_FX_DW0_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[79]) /* 0x40011BC0 */ +#define PERI_MS_PPU_FX_DW1_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[80]) /* 0x40011C00 */ +#define PERI_MS_PPU_FX_DW0_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[81]) /* 0x40011C40 */ +#define PERI_MS_PPU_FX_DW1_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[82]) /* 0x40011C80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[83]) /* 0x40011CC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[84]) /* 0x40011D00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[85]) /* 0x40011D40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[86]) /* 0x40011D80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[87]) /* 0x40011DC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[88]) /* 0x40011E00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[89]) /* 0x40011E40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[90]) /* 0x40011E80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[91]) /* 0x40011EC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[92]) /* 0x40011F00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[93]) /* 0x40011F40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[94]) /* 0x40011F80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[95]) /* 0x40011FC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[96]) /* 0x40012000 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[97]) /* 0x40012040 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[98]) /* 0x40012080 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[99]) /* 0x400120C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[100]) /* 0x40012100 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[101]) /* 0x40012140 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[102]) /* 0x40012180 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[103]) /* 0x400121C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[104]) /* 0x40012200 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[105]) /* 0x40012240 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[106]) /* 0x40012280 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[107]) /* 0x400122C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[108]) /* 0x40012300 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[109]) /* 0x40012340 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[110]) /* 0x40012380 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[111]) /* 0x400123C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT29_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[112]) /* 0x40012400 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[113]) /* 0x40012440 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[114]) /* 0x40012480 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[115]) /* 0x400124C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[116]) /* 0x40012500 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[117]) /* 0x40012540 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[118]) /* 0x40012580 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[119]) /* 0x400125C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[120]) /* 0x40012600 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[121]) /* 0x40012640 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[122]) /* 0x40012680 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[123]) /* 0x400126C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[124]) /* 0x40012700 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[125]) /* 0x40012740 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[126]) /* 0x40012780 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[127]) /* 0x400127C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[128]) /* 0x40012800 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[129]) /* 0x40012840 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[130]) /* 0x40012880 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[131]) /* 0x400128C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[132]) /* 0x40012900 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[133]) /* 0x40012940 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[134]) /* 0x40012980 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[135]) /* 0x400129C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[136]) /* 0x40012A00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[137]) /* 0x40012A40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[138]) /* 0x40012A80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[139]) /* 0x40012AC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[140]) /* 0x40012B00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[141]) /* 0x40012B40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT29_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[142]) /* 0x40012B80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT30_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[143]) /* 0x40012BC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT31_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[144]) /* 0x40012C00 */ +#define PERI_MS_PPU_FX_DMAC_TOP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[145]) /* 0x40012C40 */ +#define PERI_MS_PPU_FX_DMAC_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[146]) /* 0x40012C80 */ +#define PERI_MS_PPU_FX_DMAC_CH1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[147]) /* 0x40012CC0 */ +#define PERI_MS_PPU_FX_EFUSE_CTL ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[148]) /* 0x40012D00 */ +#define PERI_MS_PPU_FX_EFUSE_DATA ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[149]) /* 0x40012D40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[150]) /* 0x40012D80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[151]) /* 0x40012DC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[152]) /* 0x40012E00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[153]) /* 0x40012E40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[154]) /* 0x40012E80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[155]) /* 0x40012EC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[156]) /* 0x40012F00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[157]) /* 0x40012F40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[158]) /* 0x40012F80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[159]) /* 0x40012FC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[160]) /* 0x40013000 */ +#define PERI_MS_PPU_FX_HSIOM_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[161]) /* 0x40013040 */ +#define PERI_MS_PPU_FX_HSIOM_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[162]) /* 0x40013080 */ +#define PERI_MS_PPU_FX_HSIOM_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[163]) /* 0x400130C0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[164]) /* 0x40013100 */ +#define PERI_MS_PPU_FX_HSIOM_AMUX ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[165]) /* 0x40013140 */ +#define PERI_MS_PPU_FX_HSIOM_MON ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[166]) /* 0x40013180 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[167]) /* 0x400131C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[168]) /* 0x40013200 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[169]) /* 0x40013240 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[170]) /* 0x40013280 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[171]) /* 0x400132C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[172]) /* 0x40013300 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[173]) /* 0x40013340 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[174]) /* 0x40013380 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[175]) /* 0x400133C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[176]) /* 0x40013400 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[177]) /* 0x40013440 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[178]) /* 0x40013480 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[179]) /* 0x400134C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[180]) /* 0x40013500 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[181]) /* 0x40013540 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[182]) /* 0x40013580 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[183]) /* 0x400135C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[184]) /* 0x40013600 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[185]) /* 0x40013640 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[186]) /* 0x40013680 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[187]) /* 0x400136C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[188]) /* 0x40013700 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[189]) /* 0x40013740 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[190]) /* 0x40013780 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[191]) /* 0x400137C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[192]) /* 0x40013800 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[193]) /* 0x40013840 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[194]) /* 0x40013880 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[195]) /* 0x400138C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[196]) /* 0x40013900 */ +#define PERI_MS_PPU_FX_GPIO_GPIO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[197]) /* 0x40013940 */ +#define PERI_MS_PPU_FX_GPIO_TEST ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[198]) /* 0x40013980 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[199]) /* 0x400139C0 */ +#define PERI_MS_PPU_FX_LPCOMP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[200]) /* 0x40013A00 */ +#define PERI_MS_PPU_FX_CSD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[201]) /* 0x40013A40 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT0_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[202]) /* 0x40013A80 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT1_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[203]) /* 0x40013AC0 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT2_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[204]) /* 0x40013B00 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT3_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[205]) /* 0x40013B40 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT0_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[206]) /* 0x40013B80 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT1_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[207]) /* 0x40013BC0 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT2_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[208]) /* 0x40013C00 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT3_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[209]) /* 0x40013C40 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT4_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[210]) /* 0x40013C80 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT5_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[211]) /* 0x40013CC0 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT6_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[212]) /* 0x40013D00 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT7_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[213]) /* 0x40013D40 */ +#define PERI_MS_PPU_FX_LCD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[214]) /* 0x40013D80 */ +#define PERI_MS_PPU_FX_USBFS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[215]) /* 0x40013DC0 */ +#define PERI_MS_PPU_FX_SMIF0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[216]) /* 0x40013E00 */ +#define PERI_MS_PPU_FX_CANFD0_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[217]) /* 0x40013E40 */ +#define PERI_MS_PPU_FX_CANFD0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[218]) /* 0x40013E80 */ +#define PERI_MS_PPU_FX_CANFD0_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[219]) /* 0x40013EC0 */ +#define PERI_MS_PPU_FX_SCB0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[220]) /* 0x40013F00 */ +#define PERI_MS_PPU_FX_SCB1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[221]) /* 0x40013F40 */ +#define PERI_MS_PPU_FX_SCB2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[222]) /* 0x40013F80 */ +#define PERI_MS_PPU_FX_SCB4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[223]) /* 0x40013FC0 */ +#define PERI_MS_PPU_FX_SCB5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[224]) /* 0x40014000 */ +#define PERI_MS_PPU_FX_SCB6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[225]) /* 0x40014040 */ + +/******************************************************************************* +* CPUSS +*******************************************************************************/ + +#define CPUSS_BASE 0x40200000UL +#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40200000 */ + +/******************************************************************************* +* FAULT +*******************************************************************************/ + +#define FAULT_BASE 0x40210000UL +#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40210000 */ +#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40210000 */ +#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40210100 */ + +/******************************************************************************* +* IPC +*******************************************************************************/ + +#define IPC_BASE 0x40220000UL +#define IPC ((IPC_Type*) IPC_BASE) /* 0x40220000 */ +#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40220000 */ +#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40220020 */ +#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40220040 */ +#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40220060 */ +#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40220080 */ +#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402200A0 */ +#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402200C0 */ +#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402200E0 */ +#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40220100 */ +#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40220120 */ +#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40220140 */ +#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40220160 */ +#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40220180 */ +#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402201A0 */ +#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402201C0 */ +#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402201E0 */ +#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40221000 */ +#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40221020 */ +#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40221040 */ +#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40221060 */ +#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40221080 */ +#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402210A0 */ +#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402210C0 */ +#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402210E0 */ +#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40221100 */ +#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40221120 */ +#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40221140 */ +#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40221160 */ +#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40221180 */ +#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402211A0 */ +#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402211C0 */ +#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402211E0 */ + +/******************************************************************************* +* PROT +*******************************************************************************/ + +#define PROT_BASE 0x40230000UL +#define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ +#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ +#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ +#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402320C0 */ +#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40232100 */ +#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40232140 */ +#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40232180 */ +#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402321C0 */ +#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40232200 */ +#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40232240 */ +#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40232280 */ +#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402322C0 */ +#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40232300 */ +#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ +#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ +#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ + +/******************************************************************************* +* FLASHC +*******************************************************************************/ + +#define FLASHC_BASE 0x40240000UL +#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40240000 */ +#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4024F000 */ + +/******************************************************************************* +* SRSS +*******************************************************************************/ + +#define SRSS_BASE 0x40260000UL +#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ +#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */ +#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */ + +/******************************************************************************* +* BACKUP +*******************************************************************************/ + +#define BACKUP_BASE 0x40270000UL +#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ + +/******************************************************************************* +* DW +*******************************************************************************/ + +#define DW0_BASE 0x40280000UL +#define DW1_BASE 0x40290000UL +#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ +#define DW1 ((DW_Type*) DW1_BASE) /* 0x40290000 */ +#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40288000 */ +#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40288040 */ +#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40288080 */ +#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x402880C0 */ +#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40288100 */ +#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x40288140 */ +#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x40288180 */ +#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402881C0 */ +#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40288200 */ +#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40288240 */ +#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40288280 */ +#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x402882C0 */ +#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40288300 */ +#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x40288340 */ +#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x40288380 */ +#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402883C0 */ +#define DW0_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[16]) /* 0x40288400 */ +#define DW0_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[17]) /* 0x40288440 */ +#define DW0_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[18]) /* 0x40288480 */ +#define DW0_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[19]) /* 0x402884C0 */ +#define DW0_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[20]) /* 0x40288500 */ +#define DW0_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[21]) /* 0x40288540 */ +#define DW0_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[22]) /* 0x40288580 */ +#define DW0_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[23]) /* 0x402885C0 */ +#define DW0_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[24]) /* 0x40288600 */ +#define DW0_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[25]) /* 0x40288640 */ +#define DW0_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[26]) /* 0x40288680 */ +#define DW0_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[27]) /* 0x402886C0 */ +#define DW0_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[28]) /* 0x40288700 */ +#define DW0_CH_STRUCT29 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[29]) /* 0x40288740 */ +#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40298000 */ +#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40298040 */ +#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40298080 */ +#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x402980C0 */ +#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40298100 */ +#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x40298140 */ +#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x40298180 */ +#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402981C0 */ +#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40298200 */ +#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40298240 */ +#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40298280 */ +#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x402982C0 */ +#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40298300 */ +#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x40298340 */ +#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x40298380 */ +#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402983C0 */ +#define DW1_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[16]) /* 0x40298400 */ +#define DW1_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[17]) /* 0x40298440 */ +#define DW1_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[18]) /* 0x40298480 */ +#define DW1_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[19]) /* 0x402984C0 */ +#define DW1_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[20]) /* 0x40298500 */ +#define DW1_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[21]) /* 0x40298540 */ +#define DW1_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[22]) /* 0x40298580 */ +#define DW1_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[23]) /* 0x402985C0 */ +#define DW1_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[24]) /* 0x40298600 */ +#define DW1_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[25]) /* 0x40298640 */ +#define DW1_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[26]) /* 0x40298680 */ +#define DW1_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[27]) /* 0x402986C0 */ +#define DW1_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[28]) /* 0x40298700 */ +#define DW1_CH_STRUCT29 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[29]) /* 0x40298740 */ +#define DW1_CH_STRUCT30 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[30]) /* 0x40298780 */ +#define DW1_CH_STRUCT31 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[31]) /* 0x402987C0 */ + +/******************************************************************************* +* DMAC +*******************************************************************************/ + +#define DMAC_BASE 0x402A0000UL +#define DMAC ((DMAC_Type*) DMAC_BASE) /* 0x402A0000 */ +#define DMAC_CH0 ((DMAC_CH_Type*) &DMAC->CH[0]) /* 0x402A1000 */ +#define DMAC_CH1 ((DMAC_CH_Type*) &DMAC->CH[1]) /* 0x402A1100 */ + +/******************************************************************************* +* EFUSE +*******************************************************************************/ + +#define EFUSE_BASE 0x402C0000UL +#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ + +/******************************************************************************* +* HSIOM +*******************************************************************************/ + +#define HSIOM_BASE 0x40300000UL +#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40300000 */ +#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40300000 */ +#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40300010 */ +#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40300020 */ +#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40300030 */ +#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40300040 */ +#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40300050 */ +#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40300060 */ +#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40300070 */ +#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40300080 */ +#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40300090 */ +#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403000A0 */ +#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403000B0 */ +#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403000C0 */ +#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403000D0 */ +#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403000E0 */ + +/******************************************************************************* +* GPIO +*******************************************************************************/ + +#define GPIO_BASE 0x40310000UL +#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40310000 */ +#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40310000 */ +#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40310080 */ +#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40310100 */ +#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40310180 */ +#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40310200 */ +#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40310280 */ +#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40310300 */ +#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40310380 */ +#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40310400 */ +#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40310480 */ +#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40310500 */ +#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40310580 */ +#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40310600 */ +#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40310680 */ +#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40310700 */ + +/******************************************************************************* +* SMARTIO +*******************************************************************************/ + +#define SMARTIO_BASE 0x40320000UL +#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40320000 */ +#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40320900 */ + +/******************************************************************************* +* LPCOMP +*******************************************************************************/ + +#define LPCOMP_BASE 0x40350000UL +#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */ + +/******************************************************************************* +* CSD +*******************************************************************************/ + +#define CSD0_BASE 0x40360000UL +#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */ + +/******************************************************************************* +* TCPWM +*******************************************************************************/ + +#define TCPWM0_BASE 0x40380000UL +#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM0_GRP0 ((TCPWM_GRP_Type*) &TCPWM0->GRP[0]) /* 0x40380000 */ +#define TCPWM0_GRP1 ((TCPWM_GRP_Type*) &TCPWM0->GRP[1]) /* 0x40388000 */ +#define TCPWM0_GRP0_CNT0 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[0]) /* 0x40380000 */ +#define TCPWM0_GRP0_CNT1 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[1]) /* 0x40380080 */ +#define TCPWM0_GRP0_CNT2 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[2]) /* 0x40380100 */ +#define TCPWM0_GRP0_CNT3 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[3]) /* 0x40380180 */ +#define TCPWM0_GRP1_CNT0 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[0]) /* 0x40388000 */ +#define TCPWM0_GRP1_CNT1 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[1]) /* 0x40388080 */ +#define TCPWM0_GRP1_CNT2 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[2]) /* 0x40388100 */ +#define TCPWM0_GRP1_CNT3 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[3]) /* 0x40388180 */ +#define TCPWM0_GRP1_CNT4 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[4]) /* 0x40388200 */ +#define TCPWM0_GRP1_CNT5 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[5]) /* 0x40388280 */ +#define TCPWM0_GRP1_CNT6 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[6]) /* 0x40388300 */ +#define TCPWM0_GRP1_CNT7 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[7]) /* 0x40388380 */ + +/******************************************************************************* +* LCD +*******************************************************************************/ + +#define LCD0_BASE 0x403B0000UL +#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ + +/******************************************************************************* +* SMIF +*******************************************************************************/ + +#define SMIF0_BASE 0x40420000UL +#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ +#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ +#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ +#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ + +/******************************************************************************* +* CANFD +*******************************************************************************/ + +#define CANFD0_BASE 0x40520000UL +#define CANFD0 ((CANFD_Type*) CANFD0_BASE) /* 0x40520000 */ +#define CANFD0_CH0 ((CANFD_CH_Type*) &CANFD0->CH[0]) /* 0x40520000 */ +#define CANFD0_CH0_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[0].M_TTCAN) /* 0x40520000 */ + +/******************************************************************************* +* SCB +*******************************************************************************/ + +#define SCB0_BASE 0x40600000UL +#define SCB1_BASE 0x40610000UL +#define SCB2_BASE 0x40620000UL +#define SCB4_BASE 0x40640000UL +#define SCB5_BASE 0x40650000UL +#define SCB6_BASE 0x40660000UL +#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40600000 */ +#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40610000 */ +#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40620000 */ +#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40640000 */ +#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40650000 */ +#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40660000 */ + +/******************************************************************************* +* CTBM +*******************************************************************************/ + +#define CTBM0_BASE 0x40900000UL +#define CTBM0 ((CTBM_Type*) CTBM0_BASE) /* 0x40900000 */ + +/******************************************************************************* +* CTDAC +*******************************************************************************/ + +#define CTDAC0_BASE 0x40940000UL +#define CTDAC0 ((CTDAC_Type*) CTDAC0_BASE) /* 0x40940000 */ + +/******************************************************************************* +* SAR +*******************************************************************************/ + +#define SAR0_BASE 0x409B0000UL +#define SAR1_BASE 0x409C0000UL +#define SAR0 ((SAR_Type*) SAR0_BASE) /* 0x409B0000 */ +#define SAR1 ((SAR_Type*) SAR1_BASE) /* 0x409C0000 */ + +/******************************************************************************* +* PASS +*******************************************************************************/ + +#define PASS_BASE 0x409F0000UL +#define PASS ((PASS_Type*) PASS_BASE) /* 0x409F0000 */ +#define PASS_TIMER ((PASS_TIMER_Type*) &PASS->TIMER) /* 0x409F0100 */ +#define PASS_LPOSC ((PASS_LPOSC_Type*) &PASS->LPOSC) /* 0x409F0200 */ +#define PASS_FIFO0 ((PASS_FIFO_Type*) &PASS->FIFO[0]) /* 0x409F0300 */ +#define PASS_FIFO1 ((PASS_FIFO_Type*) &PASS->FIFO[1]) /* 0x409F0400 */ +#define PASS_AREFV2 ((PASS_AREFV2_Type*) &PASS->AREFV2) /* 0x409F0E00 */ + +/** \} CY8C4588AZI-H686 */ + +#endif /* _CY8C4588AZI_H686_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6016bzi_f04.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6016bzi_f04.h index 973f464be0..30c137b9b1 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6016bzi_f04.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6016bzi_f04.h @@ -5,11 +5,11 @@ * CY8C6016BZI-F04 device header * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -236,52 +236,37 @@ typedef enum { #define CY_FLASH_SIZE 0x00080000UL #define CY_EM_EEPROM_BASE 0x14000000UL #define CY_EM_EEPROM_SIZE 0x00008000UL -#define CY_XIP_BASE 0x18000000UL -#define CY_XIP_SIZE 0x08000000UL #define CY_SFLASH_BASE 0x16000000UL #define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL #define CY_EFUSE_BASE 0x402C0800UL #define CY_EFUSE_SIZE 0x00000200UL #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u #define CY_IP_M4CPUSS_DMA 1u #define CY_IP_M4CPUSS_DMA_INSTANCES 2u #define CY_IP_M4CPUSS_DMA_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -294,21 +279,36 @@ typedef enum { #define CY_IP_MXS40PASS_CTDAC 1u #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u #define CY_IP_MXS40PASS_CTDAC_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_124_bga.h" @@ -601,6 +601,7 @@ typedef enum { #define PROT_BASE 0x40240000UL #define PROT ((PROT_Type*) PROT_BASE) /* 0x40240000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ #define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40242000 */ #define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40242040 */ #define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40242080 */ @@ -617,23 +618,6 @@ typedef enum { #define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40242340 */ #define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40242380 */ #define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402423C0 */ -#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ -#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ -#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ -#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ -#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ -#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ -#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ -#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ -#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ -#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ -#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ -#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ -#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ -#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ -#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ -#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ -#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ #define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40244000 */ #define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40244400 */ #define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40244800 */ @@ -650,6 +634,22 @@ typedef enum { #define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40247400 */ #define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40247800 */ #define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40247C00 */ +#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ +#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ +#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ +#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ +#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ +#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ +#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ +#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ /******************************************************************************* * FLASHC diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6036bzi_f04.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6036bzi_f04.h index 2b8499cacd..080d4312ea 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6036bzi_f04.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6036bzi_f04.h @@ -5,11 +5,11 @@ * CY8C6036BZI-F04 device header * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -236,52 +236,37 @@ typedef enum { #define CY_FLASH_SIZE 0x00080000UL #define CY_EM_EEPROM_BASE 0x14000000UL #define CY_EM_EEPROM_SIZE 0x00008000UL -#define CY_XIP_BASE 0x18000000UL -#define CY_XIP_SIZE 0x08000000UL #define CY_SFLASH_BASE 0x16000000UL #define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL #define CY_EFUSE_BASE 0x402C0800UL #define CY_EFUSE_SIZE 0x00000200UL #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u #define CY_IP_M4CPUSS_DMA 1u #define CY_IP_M4CPUSS_DMA_INSTANCES 2u #define CY_IP_M4CPUSS_DMA_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -294,21 +279,36 @@ typedef enum { #define CY_IP_MXS40PASS_CTDAC 1u #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u #define CY_IP_MXS40PASS_CTDAC_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_124_bga.h" @@ -601,6 +601,7 @@ typedef enum { #define PROT_BASE 0x40240000UL #define PROT ((PROT_Type*) PROT_BASE) /* 0x40240000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ #define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40242000 */ #define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40242040 */ #define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40242080 */ @@ -617,23 +618,6 @@ typedef enum { #define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40242340 */ #define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40242380 */ #define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402423C0 */ -#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ -#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ -#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ -#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ -#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ -#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ -#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ -#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ -#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ -#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ -#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ -#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ -#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ -#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ -#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ -#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ -#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ #define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40244000 */ #define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40244400 */ #define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40244800 */ @@ -650,6 +634,22 @@ typedef enum { #define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40247400 */ #define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40247800 */ #define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40247C00 */ +#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ +#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ +#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ +#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ +#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ +#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ +#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ +#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ /******************************************************************************* * FLASHC diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6116bzi_f54.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6116bzi_f54.h index 3f181e90ef..b668986672 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6116bzi_f54.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6116bzi_f54.h @@ -5,11 +5,11 @@ * CY8C6116BZI-F54 device header * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -236,43 +236,19 @@ typedef enum { #define CY_FLASH_SIZE 0x00080000UL #define CY_EM_EEPROM_BASE 0x14000000UL #define CY_EM_EEPROM_SIZE 0x00008000UL -#define CY_XIP_BASE 0x18000000UL -#define CY_XIP_SIZE 0x08000000UL #define CY_SFLASH_BASE 0x16000000UL #define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL #define CY_EFUSE_BASE 0x402C0800UL #define CY_EFUSE_SIZE 0x00000200UL #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u @@ -282,9 +258,18 @@ typedef enum { #define CY_IP_MXCRYPTO 1u #define CY_IP_MXCRYPTO_INSTANCES 1u #define CY_IP_MXCRYPTO_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -300,24 +285,39 @@ typedef enum { #define CY_IP_MXS40PASS_CTB 1u #define CY_IP_MXS40PASS_CTB_INSTANCES 1u #define CY_IP_MXS40PASS_CTB_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u -#define CY_IP_MXUDB 1u -#define CY_IP_MXUDB_INSTANCES 1u -#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUDB 1u +#define CY_IP_MXUDB_INSTANCES 1u +#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_124_bga.h" @@ -617,6 +617,7 @@ typedef enum { #define PROT_BASE 0x40240000UL #define PROT ((PROT_Type*) PROT_BASE) /* 0x40240000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ #define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40242000 */ #define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40242040 */ #define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40242080 */ @@ -633,23 +634,6 @@ typedef enum { #define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40242340 */ #define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40242380 */ #define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402423C0 */ -#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ -#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ -#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ -#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ -#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ -#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ -#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ -#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ -#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ -#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ -#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ -#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ -#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ -#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ -#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ -#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ -#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ #define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40244000 */ #define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40244400 */ #define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40244800 */ @@ -666,6 +650,22 @@ typedef enum { #define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40247400 */ #define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40247800 */ #define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40247C00 */ +#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ +#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ +#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ +#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ +#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ +#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ +#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ +#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ /******************************************************************************* * FLASHC @@ -815,6 +815,12 @@ typedef enum { #define UDB ((UDB_Type*) UDB_BASE) /* 0x40340000 */ #define UDB_WRKONE ((UDB_WRKONE_Type*) &UDB->WRKONE) /* 0x40340000 */ #define UDB_WRKMULT ((UDB_WRKMULT_Type*) &UDB->WRKMULT) /* 0x40341000 */ +#define UDB_UDBPAIR0 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[0]) /* 0x40342000 */ +#define UDB_UDBPAIR1 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[1]) /* 0x40342200 */ +#define UDB_UDBPAIR2 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[2]) /* 0x40342400 */ +#define UDB_UDBPAIR3 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[3]) /* 0x40342600 */ +#define UDB_UDBPAIR4 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[4]) /* 0x40342800 */ +#define UDB_UDBPAIR5 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[5]) /* 0x40342A00 */ #define UDB_UDBPAIR0_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[0].UDBSNG[0]) /* 0x40342000 */ #define UDB_UDBPAIR0_UDBSNG1 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[0].UDBSNG[1]) /* 0x40342080 */ #define UDB_UDBPAIR1_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[1].UDBSNG[0]) /* 0x40342200 */ @@ -833,12 +839,6 @@ typedef enum { #define UDB_UDBPAIR3_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[3].ROUTE) /* 0x40342700 */ #define UDB_UDBPAIR4_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[4].ROUTE) /* 0x40342900 */ #define UDB_UDBPAIR5_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[5].ROUTE) /* 0x40342B00 */ -#define UDB_UDBPAIR0 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[0]) /* 0x40342000 */ -#define UDB_UDBPAIR1 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[1]) /* 0x40342200 */ -#define UDB_UDBPAIR2 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[2]) /* 0x40342400 */ -#define UDB_UDBPAIR3 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[3]) /* 0x40342600 */ -#define UDB_UDBPAIR4 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[4]) /* 0x40342800 */ -#define UDB_UDBPAIR5 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[5]) /* 0x40342A00 */ #define UDB_DSI0 ((UDB_DSI_Type*) &UDB->DSI[0]) /* 0x40346000 */ #define UDB_DSI1 ((UDB_DSI_Type*) &UDB->DSI[1]) /* 0x40346080 */ #define UDB_DSI2 ((UDB_DSI_Type*) &UDB->DSI[2]) /* 0x40346100 */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6117bzi_f34.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6117bzi_f34.h index b04b854119..9dfb2c587c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6117bzi_f34.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6117bzi_f34.h @@ -5,11 +5,11 @@ * CY8C6117BZI-F34 device header * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -236,52 +236,37 @@ typedef enum { #define CY_FLASH_SIZE 0x00100000UL #define CY_EM_EEPROM_BASE 0x14000000UL #define CY_EM_EEPROM_SIZE 0x00008000UL -#define CY_XIP_BASE 0x18000000UL -#define CY_XIP_SIZE 0x08000000UL #define CY_SFLASH_BASE 0x16000000UL #define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL #define CY_EFUSE_BASE 0x402C0800UL #define CY_EFUSE_SIZE 0x00000200UL #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u #define CY_IP_M4CPUSS_DMA 1u #define CY_IP_M4CPUSS_DMA_INSTANCES 2u #define CY_IP_M4CPUSS_DMA_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -297,24 +282,39 @@ typedef enum { #define CY_IP_MXS40PASS_CTB 1u #define CY_IP_MXS40PASS_CTB_INSTANCES 1u #define CY_IP_MXS40PASS_CTB_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u -#define CY_IP_MXUDB 1u -#define CY_IP_MXUDB_INSTANCES 1u -#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUDB 1u +#define CY_IP_MXUDB_INSTANCES 1u +#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_124_bga.h" @@ -607,6 +607,7 @@ typedef enum { #define PROT_BASE 0x40240000UL #define PROT ((PROT_Type*) PROT_BASE) /* 0x40240000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ #define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40242000 */ #define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40242040 */ #define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40242080 */ @@ -623,23 +624,6 @@ typedef enum { #define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40242340 */ #define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40242380 */ #define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402423C0 */ -#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ -#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ -#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ -#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ -#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ -#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ -#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ -#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ -#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ -#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ -#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ -#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ -#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ -#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ -#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ -#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ -#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ #define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40244000 */ #define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40244400 */ #define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40244800 */ @@ -656,6 +640,22 @@ typedef enum { #define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40247400 */ #define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40247800 */ #define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40247C00 */ +#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ +#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ +#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ +#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ +#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ +#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ +#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ +#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ /******************************************************************************* * FLASHC @@ -805,6 +805,12 @@ typedef enum { #define UDB ((UDB_Type*) UDB_BASE) /* 0x40340000 */ #define UDB_WRKONE ((UDB_WRKONE_Type*) &UDB->WRKONE) /* 0x40340000 */ #define UDB_WRKMULT ((UDB_WRKMULT_Type*) &UDB->WRKMULT) /* 0x40341000 */ +#define UDB_UDBPAIR0 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[0]) /* 0x40342000 */ +#define UDB_UDBPAIR1 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[1]) /* 0x40342200 */ +#define UDB_UDBPAIR2 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[2]) /* 0x40342400 */ +#define UDB_UDBPAIR3 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[3]) /* 0x40342600 */ +#define UDB_UDBPAIR4 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[4]) /* 0x40342800 */ +#define UDB_UDBPAIR5 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[5]) /* 0x40342A00 */ #define UDB_UDBPAIR0_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[0].UDBSNG[0]) /* 0x40342000 */ #define UDB_UDBPAIR0_UDBSNG1 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[0].UDBSNG[1]) /* 0x40342080 */ #define UDB_UDBPAIR1_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[1].UDBSNG[0]) /* 0x40342200 */ @@ -823,12 +829,6 @@ typedef enum { #define UDB_UDBPAIR3_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[3].ROUTE) /* 0x40342700 */ #define UDB_UDBPAIR4_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[4].ROUTE) /* 0x40342900 */ #define UDB_UDBPAIR5_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[5].ROUTE) /* 0x40342B00 */ -#define UDB_UDBPAIR0 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[0]) /* 0x40342000 */ -#define UDB_UDBPAIR1 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[1]) /* 0x40342200 */ -#define UDB_UDBPAIR2 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[2]) /* 0x40342400 */ -#define UDB_UDBPAIR3 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[3]) /* 0x40342600 */ -#define UDB_UDBPAIR4 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[4]) /* 0x40342800 */ -#define UDB_UDBPAIR5 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[5]) /* 0x40342A00 */ #define UDB_DSI0 ((UDB_DSI_Type*) &UDB->DSI[0]) /* 0x40346000 */ #define UDB_DSI1 ((UDB_DSI_Type*) &UDB->DSI[1]) /* 0x40346080 */ #define UDB_DSI2 ((UDB_DSI_Type*) &UDB->DSI[2]) /* 0x40346100 */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6117fdi_f02.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6117fdi_f02.h index 01bb1c687a..52d470f531 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6117fdi_f02.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6117fdi_f02.h @@ -5,11 +5,11 @@ * CY8C6117FDI-F02 device header * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -236,52 +236,37 @@ typedef enum { #define CY_FLASH_SIZE 0x00100000UL #define CY_EM_EEPROM_BASE 0x14000000UL #define CY_EM_EEPROM_SIZE 0x00008000UL -#define CY_XIP_BASE 0x18000000UL -#define CY_XIP_SIZE 0x08000000UL #define CY_SFLASH_BASE 0x16000000UL #define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL #define CY_EFUSE_BASE 0x402C0800UL #define CY_EFUSE_SIZE 0x00000200UL #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u #define CY_IP_M4CPUSS_DMA 1u #define CY_IP_M4CPUSS_DMA_INSTANCES 2u #define CY_IP_M4CPUSS_DMA_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -294,21 +279,36 @@ typedef enum { #define CY_IP_MXS40PASS_CTDAC 1u #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u #define CY_IP_MXS40PASS_CTDAC_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_80_wlcsp.h" @@ -601,6 +601,7 @@ typedef enum { #define PROT_BASE 0x40240000UL #define PROT ((PROT_Type*) PROT_BASE) /* 0x40240000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ #define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40242000 */ #define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40242040 */ #define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40242080 */ @@ -617,23 +618,6 @@ typedef enum { #define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40242340 */ #define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40242380 */ #define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402423C0 */ -#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ -#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ -#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ -#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ -#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ -#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ -#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ -#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ -#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ -#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ -#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ -#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ -#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ -#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ -#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ -#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ -#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ #define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40244000 */ #define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40244400 */ #define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40244800 */ @@ -650,6 +634,22 @@ typedef enum { #define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40247400 */ #define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40247800 */ #define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40247C00 */ +#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ +#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ +#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ +#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ +#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ +#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ +#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ +#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ /******************************************************************************* * FLASHC diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6117wi_f34.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6117wi_f34.h index 96353e9080..29f84cf61e 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6117wi_f34.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6117wi_f34.h @@ -5,11 +5,11 @@ * CY8C6117WI-F34 device header * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -236,52 +236,37 @@ typedef enum { #define CY_FLASH_SIZE 0x00100000UL #define CY_EM_EEPROM_BASE 0x14000000UL #define CY_EM_EEPROM_SIZE 0x00008000UL -#define CY_XIP_BASE 0x18000000UL -#define CY_XIP_SIZE 0x08000000UL #define CY_SFLASH_BASE 0x16000000UL #define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL #define CY_EFUSE_BASE 0x402C0800UL #define CY_EFUSE_SIZE 0x00000200UL #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u #define CY_IP_M4CPUSS_DMA 1u #define CY_IP_M4CPUSS_DMA_INSTANCES 2u #define CY_IP_M4CPUSS_DMA_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -297,24 +282,39 @@ typedef enum { #define CY_IP_MXS40PASS_CTB 1u #define CY_IP_MXS40PASS_CTB_INSTANCES 1u #define CY_IP_MXS40PASS_CTB_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u -#define CY_IP_MXUDB 1u -#define CY_IP_MXUDB_INSTANCES 1u -#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUDB 1u +#define CY_IP_MXUDB_INSTANCES 1u +#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_124_bga.h" @@ -607,6 +607,7 @@ typedef enum { #define PROT_BASE 0x40240000UL #define PROT ((PROT_Type*) PROT_BASE) /* 0x40240000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ #define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40242000 */ #define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40242040 */ #define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40242080 */ @@ -623,23 +624,6 @@ typedef enum { #define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40242340 */ #define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40242380 */ #define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402423C0 */ -#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ -#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ -#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ -#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ -#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ -#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ -#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ -#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ -#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ -#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ -#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ -#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ -#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ -#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ -#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ -#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ -#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ #define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40244000 */ #define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40244400 */ #define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40244800 */ @@ -656,6 +640,22 @@ typedef enum { #define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40247400 */ #define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40247800 */ #define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40247C00 */ +#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ +#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ +#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ +#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ +#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ +#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ +#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ +#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ /******************************************************************************* * FLASHC @@ -805,6 +805,12 @@ typedef enum { #define UDB ((UDB_Type*) UDB_BASE) /* 0x40340000 */ #define UDB_WRKONE ((UDB_WRKONE_Type*) &UDB->WRKONE) /* 0x40340000 */ #define UDB_WRKMULT ((UDB_WRKMULT_Type*) &UDB->WRKMULT) /* 0x40341000 */ +#define UDB_UDBPAIR0 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[0]) /* 0x40342000 */ +#define UDB_UDBPAIR1 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[1]) /* 0x40342200 */ +#define UDB_UDBPAIR2 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[2]) /* 0x40342400 */ +#define UDB_UDBPAIR3 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[3]) /* 0x40342600 */ +#define UDB_UDBPAIR4 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[4]) /* 0x40342800 */ +#define UDB_UDBPAIR5 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[5]) /* 0x40342A00 */ #define UDB_UDBPAIR0_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[0].UDBSNG[0]) /* 0x40342000 */ #define UDB_UDBPAIR0_UDBSNG1 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[0].UDBSNG[1]) /* 0x40342080 */ #define UDB_UDBPAIR1_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[1].UDBSNG[0]) /* 0x40342200 */ @@ -823,12 +829,6 @@ typedef enum { #define UDB_UDBPAIR3_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[3].ROUTE) /* 0x40342700 */ #define UDB_UDBPAIR4_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[4].ROUTE) /* 0x40342900 */ #define UDB_UDBPAIR5_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[5].ROUTE) /* 0x40342B00 */ -#define UDB_UDBPAIR0 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[0]) /* 0x40342000 */ -#define UDB_UDBPAIR1 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[1]) /* 0x40342200 */ -#define UDB_UDBPAIR2 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[2]) /* 0x40342400 */ -#define UDB_UDBPAIR3 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[3]) /* 0x40342600 */ -#define UDB_UDBPAIR4 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[4]) /* 0x40342800 */ -#define UDB_UDBPAIR5 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[5]) /* 0x40342A00 */ #define UDB_DSI0 ((UDB_DSI_Type*) &UDB->DSI[0]) /* 0x40346000 */ #define UDB_DSI1 ((UDB_DSI_Type*) &UDB->DSI[1]) /* 0x40346080 */ #define UDB_DSI2 ((UDB_DSI_Type*) &UDB->DSI[2]) /* 0x40346100 */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6136bzi_f14.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6136bzi_f14.h index f58b6413da..83b74cba7e 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6136bzi_f14.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6136bzi_f14.h @@ -5,11 +5,11 @@ * CY8C6136BZI-F14 device header * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -236,52 +236,37 @@ typedef enum { #define CY_FLASH_SIZE 0x00080000UL #define CY_EM_EEPROM_BASE 0x14000000UL #define CY_EM_EEPROM_SIZE 0x00008000UL -#define CY_XIP_BASE 0x18000000UL -#define CY_XIP_SIZE 0x08000000UL #define CY_SFLASH_BASE 0x16000000UL #define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL #define CY_EFUSE_BASE 0x402C0800UL #define CY_EFUSE_SIZE 0x00000200UL #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u #define CY_IP_M4CPUSS_DMA 1u #define CY_IP_M4CPUSS_DMA_INSTANCES 2u #define CY_IP_M4CPUSS_DMA_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -294,21 +279,36 @@ typedef enum { #define CY_IP_MXS40PASS_CTDAC 1u #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u #define CY_IP_MXS40PASS_CTDAC_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_124_bga.h" @@ -601,6 +601,7 @@ typedef enum { #define PROT_BASE 0x40240000UL #define PROT ((PROT_Type*) PROT_BASE) /* 0x40240000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ #define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40242000 */ #define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40242040 */ #define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40242080 */ @@ -617,23 +618,6 @@ typedef enum { #define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40242340 */ #define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40242380 */ #define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402423C0 */ -#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ -#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ -#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ -#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ -#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ -#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ -#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ -#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ -#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ -#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ -#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ -#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ -#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ -#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ -#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ -#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ -#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ #define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40244000 */ #define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40244400 */ #define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40244800 */ @@ -650,6 +634,22 @@ typedef enum { #define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40247400 */ #define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40247800 */ #define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40247C00 */ +#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ +#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ +#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ +#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ +#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ +#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ +#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ +#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ /******************************************************************************* * FLASHC diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6136bzi_f34.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6136bzi_f34.h index 4c0afb44a0..740a126213 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6136bzi_f34.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6136bzi_f34.h @@ -5,11 +5,11 @@ * CY8C6136BZI-F34 device header * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -236,52 +236,37 @@ typedef enum { #define CY_FLASH_SIZE 0x00080000UL #define CY_EM_EEPROM_BASE 0x14000000UL #define CY_EM_EEPROM_SIZE 0x00008000UL -#define CY_XIP_BASE 0x18000000UL -#define CY_XIP_SIZE 0x08000000UL #define CY_SFLASH_BASE 0x16000000UL #define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL #define CY_EFUSE_BASE 0x402C0800UL #define CY_EFUSE_SIZE 0x00000200UL #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u #define CY_IP_M4CPUSS_DMA 1u #define CY_IP_M4CPUSS_DMA_INSTANCES 2u #define CY_IP_M4CPUSS_DMA_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -297,24 +282,39 @@ typedef enum { #define CY_IP_MXS40PASS_CTB 1u #define CY_IP_MXS40PASS_CTB_INSTANCES 1u #define CY_IP_MXS40PASS_CTB_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u -#define CY_IP_MXUDB 1u -#define CY_IP_MXUDB_INSTANCES 1u -#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUDB 1u +#define CY_IP_MXUDB_INSTANCES 1u +#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_124_bga.h" @@ -607,6 +607,7 @@ typedef enum { #define PROT_BASE 0x40240000UL #define PROT ((PROT_Type*) PROT_BASE) /* 0x40240000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ #define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40242000 */ #define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40242040 */ #define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40242080 */ @@ -623,23 +624,6 @@ typedef enum { #define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40242340 */ #define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40242380 */ #define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402423C0 */ -#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ -#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ -#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ -#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ -#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ -#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ -#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ -#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ -#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ -#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ -#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ -#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ -#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ -#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ -#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ -#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ -#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ #define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40244000 */ #define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40244400 */ #define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40244800 */ @@ -656,6 +640,22 @@ typedef enum { #define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40247400 */ #define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40247800 */ #define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40247C00 */ +#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ +#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ +#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ +#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ +#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ +#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ +#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ +#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ /******************************************************************************* * FLASHC @@ -805,6 +805,12 @@ typedef enum { #define UDB ((UDB_Type*) UDB_BASE) /* 0x40340000 */ #define UDB_WRKONE ((UDB_WRKONE_Type*) &UDB->WRKONE) /* 0x40340000 */ #define UDB_WRKMULT ((UDB_WRKMULT_Type*) &UDB->WRKMULT) /* 0x40341000 */ +#define UDB_UDBPAIR0 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[0]) /* 0x40342000 */ +#define UDB_UDBPAIR1 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[1]) /* 0x40342200 */ +#define UDB_UDBPAIR2 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[2]) /* 0x40342400 */ +#define UDB_UDBPAIR3 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[3]) /* 0x40342600 */ +#define UDB_UDBPAIR4 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[4]) /* 0x40342800 */ +#define UDB_UDBPAIR5 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[5]) /* 0x40342A00 */ #define UDB_UDBPAIR0_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[0].UDBSNG[0]) /* 0x40342000 */ #define UDB_UDBPAIR0_UDBSNG1 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[0].UDBSNG[1]) /* 0x40342080 */ #define UDB_UDBPAIR1_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[1].UDBSNG[0]) /* 0x40342200 */ @@ -823,12 +829,6 @@ typedef enum { #define UDB_UDBPAIR3_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[3].ROUTE) /* 0x40342700 */ #define UDB_UDBPAIR4_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[4].ROUTE) /* 0x40342900 */ #define UDB_UDBPAIR5_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[5].ROUTE) /* 0x40342B00 */ -#define UDB_UDBPAIR0 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[0]) /* 0x40342000 */ -#define UDB_UDBPAIR1 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[1]) /* 0x40342200 */ -#define UDB_UDBPAIR2 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[2]) /* 0x40342400 */ -#define UDB_UDBPAIR3 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[3]) /* 0x40342600 */ -#define UDB_UDBPAIR4 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[4]) /* 0x40342800 */ -#define UDB_UDBPAIR5 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[5]) /* 0x40342A00 */ #define UDB_DSI0 ((UDB_DSI_Type*) &UDB->DSI[0]) /* 0x40346000 */ #define UDB_DSI1 ((UDB_DSI_Type*) &UDB->DSI[1]) /* 0x40346080 */ #define UDB_DSI2 ((UDB_DSI_Type*) &UDB->DSI[2]) /* 0x40346100 */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6136fdi_f42.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6136fdi_f42.h index 20e788b1d0..700f72e079 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6136fdi_f42.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6136fdi_f42.h @@ -5,11 +5,11 @@ * CY8C6136FDI-F42 device header * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -236,43 +236,19 @@ typedef enum { #define CY_FLASH_SIZE 0x00080000UL #define CY_EM_EEPROM_BASE 0x14000000UL #define CY_EM_EEPROM_SIZE 0x00008000UL -#define CY_XIP_BASE 0x18000000UL -#define CY_XIP_SIZE 0x08000000UL #define CY_SFLASH_BASE 0x16000000UL #define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL #define CY_EFUSE_BASE 0x402C0800UL #define CY_EFUSE_SIZE 0x00000200UL #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u @@ -282,9 +258,18 @@ typedef enum { #define CY_IP_MXCRYPTO 1u #define CY_IP_MXCRYPTO_INSTANCES 1u #define CY_IP_MXCRYPTO_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -297,21 +282,36 @@ typedef enum { #define CY_IP_MXS40PASS_CTDAC 1u #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u #define CY_IP_MXS40PASS_CTDAC_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_80_wlcsp.h" @@ -611,6 +611,7 @@ typedef enum { #define PROT_BASE 0x40240000UL #define PROT ((PROT_Type*) PROT_BASE) /* 0x40240000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ #define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40242000 */ #define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40242040 */ #define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40242080 */ @@ -627,23 +628,6 @@ typedef enum { #define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40242340 */ #define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40242380 */ #define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402423C0 */ -#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ -#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ -#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ -#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ -#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ -#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ -#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ -#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ -#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ -#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ -#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ -#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ -#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ -#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ -#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ -#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ -#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ #define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40244000 */ #define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40244400 */ #define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40244800 */ @@ -660,6 +644,22 @@ typedef enum { #define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40247400 */ #define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40247800 */ #define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40247C00 */ +#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ +#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ +#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ +#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ +#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ +#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ +#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ +#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ /******************************************************************************* * FLASHC diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6136fti_f42.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6136fti_f42.h index 36141d96e8..6018cb0b34 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6136fti_f42.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6136fti_f42.h @@ -5,11 +5,11 @@ * CY8C6136FTI-F42 device header * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -236,43 +236,19 @@ typedef enum { #define CY_FLASH_SIZE 0x00080000UL #define CY_EM_EEPROM_BASE 0x14000000UL #define CY_EM_EEPROM_SIZE 0x00008000UL -#define CY_XIP_BASE 0x18000000UL -#define CY_XIP_SIZE 0x08000000UL #define CY_SFLASH_BASE 0x16000000UL #define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL #define CY_EFUSE_BASE 0x402C0800UL #define CY_EFUSE_SIZE 0x00000200UL #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u @@ -282,9 +258,18 @@ typedef enum { #define CY_IP_MXCRYPTO 1u #define CY_IP_MXCRYPTO_INSTANCES 1u #define CY_IP_MXCRYPTO_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -297,21 +282,36 @@ typedef enum { #define CY_IP_MXS40PASS_CTDAC 1u #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u #define CY_IP_MXS40PASS_CTDAC_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_80_wlcsp.h" @@ -611,6 +611,7 @@ typedef enum { #define PROT_BASE 0x40240000UL #define PROT ((PROT_Type*) PROT_BASE) /* 0x40240000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ #define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40242000 */ #define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40242040 */ #define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40242080 */ @@ -627,23 +628,6 @@ typedef enum { #define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40242340 */ #define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40242380 */ #define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402423C0 */ -#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ -#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ -#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ -#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ -#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ -#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ -#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ -#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ -#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ -#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ -#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ -#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ -#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ -#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ -#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ -#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ -#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ #define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40244000 */ #define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40244400 */ #define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40244800 */ @@ -660,6 +644,22 @@ typedef enum { #define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40247400 */ #define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40247800 */ #define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40247C00 */ +#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ +#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ +#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ +#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ +#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ +#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ +#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ +#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ /******************************************************************************* * FLASHC diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6137bzi_f14.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6137bzi_f14.h index f8b8578f66..6493e472b3 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6137bzi_f14.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6137bzi_f14.h @@ -5,11 +5,11 @@ * CY8C6137BZI-F14 device header * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -236,52 +236,37 @@ typedef enum { #define CY_FLASH_SIZE 0x00100000UL #define CY_EM_EEPROM_BASE 0x14000000UL #define CY_EM_EEPROM_SIZE 0x00008000UL -#define CY_XIP_BASE 0x18000000UL -#define CY_XIP_SIZE 0x08000000UL #define CY_SFLASH_BASE 0x16000000UL #define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL #define CY_EFUSE_BASE 0x402C0800UL #define CY_EFUSE_SIZE 0x00000200UL #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u #define CY_IP_M4CPUSS_DMA 1u #define CY_IP_M4CPUSS_DMA_INSTANCES 2u #define CY_IP_M4CPUSS_DMA_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -294,21 +279,36 @@ typedef enum { #define CY_IP_MXS40PASS_CTDAC 1u #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u #define CY_IP_MXS40PASS_CTDAC_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_124_bga.h" @@ -601,6 +601,7 @@ typedef enum { #define PROT_BASE 0x40240000UL #define PROT ((PROT_Type*) PROT_BASE) /* 0x40240000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ #define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40242000 */ #define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40242040 */ #define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40242080 */ @@ -617,23 +618,6 @@ typedef enum { #define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40242340 */ #define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40242380 */ #define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402423C0 */ -#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ -#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ -#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ -#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ -#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ -#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ -#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ -#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ -#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ -#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ -#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ -#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ -#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ -#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ -#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ -#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ -#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ #define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40244000 */ #define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40244400 */ #define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40244800 */ @@ -650,6 +634,22 @@ typedef enum { #define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40247400 */ #define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40247800 */ #define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40247C00 */ +#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ +#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ +#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ +#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ +#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ +#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ +#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ +#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ /******************************************************************************* * FLASHC diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6137bzi_f34.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6137bzi_f34.h index f9d9b39f3a..68b3a21370 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6137bzi_f34.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6137bzi_f34.h @@ -5,11 +5,11 @@ * CY8C6137BZI-F34 device header * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -236,52 +236,37 @@ typedef enum { #define CY_FLASH_SIZE 0x00100000UL #define CY_EM_EEPROM_BASE 0x14000000UL #define CY_EM_EEPROM_SIZE 0x00008000UL -#define CY_XIP_BASE 0x18000000UL -#define CY_XIP_SIZE 0x08000000UL #define CY_SFLASH_BASE 0x16000000UL #define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL #define CY_EFUSE_BASE 0x402C0800UL #define CY_EFUSE_SIZE 0x00000200UL #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u #define CY_IP_M4CPUSS_DMA 1u #define CY_IP_M4CPUSS_DMA_INSTANCES 2u #define CY_IP_M4CPUSS_DMA_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -297,24 +282,39 @@ typedef enum { #define CY_IP_MXS40PASS_CTB 1u #define CY_IP_MXS40PASS_CTB_INSTANCES 1u #define CY_IP_MXS40PASS_CTB_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u -#define CY_IP_MXUDB 1u -#define CY_IP_MXUDB_INSTANCES 1u -#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUDB 1u +#define CY_IP_MXUDB_INSTANCES 1u +#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_124_bga.h" @@ -607,6 +607,7 @@ typedef enum { #define PROT_BASE 0x40240000UL #define PROT ((PROT_Type*) PROT_BASE) /* 0x40240000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ #define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40242000 */ #define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40242040 */ #define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40242080 */ @@ -623,23 +624,6 @@ typedef enum { #define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40242340 */ #define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40242380 */ #define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402423C0 */ -#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ -#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ -#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ -#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ -#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ -#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ -#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ -#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ -#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ -#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ -#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ -#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ -#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ -#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ -#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ -#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ -#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ #define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40244000 */ #define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40244400 */ #define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40244800 */ @@ -656,6 +640,22 @@ typedef enum { #define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40247400 */ #define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40247800 */ #define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40247C00 */ +#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ +#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ +#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ +#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ +#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ +#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ +#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ +#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ /******************************************************************************* * FLASHC @@ -805,6 +805,12 @@ typedef enum { #define UDB ((UDB_Type*) UDB_BASE) /* 0x40340000 */ #define UDB_WRKONE ((UDB_WRKONE_Type*) &UDB->WRKONE) /* 0x40340000 */ #define UDB_WRKMULT ((UDB_WRKMULT_Type*) &UDB->WRKMULT) /* 0x40341000 */ +#define UDB_UDBPAIR0 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[0]) /* 0x40342000 */ +#define UDB_UDBPAIR1 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[1]) /* 0x40342200 */ +#define UDB_UDBPAIR2 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[2]) /* 0x40342400 */ +#define UDB_UDBPAIR3 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[3]) /* 0x40342600 */ +#define UDB_UDBPAIR4 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[4]) /* 0x40342800 */ +#define UDB_UDBPAIR5 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[5]) /* 0x40342A00 */ #define UDB_UDBPAIR0_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[0].UDBSNG[0]) /* 0x40342000 */ #define UDB_UDBPAIR0_UDBSNG1 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[0].UDBSNG[1]) /* 0x40342080 */ #define UDB_UDBPAIR1_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[1].UDBSNG[0]) /* 0x40342200 */ @@ -823,12 +829,6 @@ typedef enum { #define UDB_UDBPAIR3_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[3].ROUTE) /* 0x40342700 */ #define UDB_UDBPAIR4_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[4].ROUTE) /* 0x40342900 */ #define UDB_UDBPAIR5_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[5].ROUTE) /* 0x40342B00 */ -#define UDB_UDBPAIR0 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[0]) /* 0x40342000 */ -#define UDB_UDBPAIR1 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[1]) /* 0x40342200 */ -#define UDB_UDBPAIR2 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[2]) /* 0x40342400 */ -#define UDB_UDBPAIR3 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[3]) /* 0x40342600 */ -#define UDB_UDBPAIR4 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[4]) /* 0x40342800 */ -#define UDB_UDBPAIR5 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[5]) /* 0x40342A00 */ #define UDB_DSI0 ((UDB_DSI_Type*) &UDB->DSI[0]) /* 0x40346000 */ #define UDB_DSI1 ((UDB_DSI_Type*) &UDB->DSI[1]) /* 0x40346080 */ #define UDB_DSI2 ((UDB_DSI_Type*) &UDB->DSI[2]) /* 0x40346100 */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6137bzi_f54.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6137bzi_f54.h index 426bca6c57..d0da1c19ec 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6137bzi_f54.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6137bzi_f54.h @@ -5,11 +5,11 @@ * CY8C6137BZI-F54 device header * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -236,43 +236,19 @@ typedef enum { #define CY_FLASH_SIZE 0x00100000UL #define CY_EM_EEPROM_BASE 0x14000000UL #define CY_EM_EEPROM_SIZE 0x00008000UL -#define CY_XIP_BASE 0x18000000UL -#define CY_XIP_SIZE 0x08000000UL #define CY_SFLASH_BASE 0x16000000UL #define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL #define CY_EFUSE_BASE 0x402C0800UL #define CY_EFUSE_SIZE 0x00000200UL #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u @@ -282,9 +258,18 @@ typedef enum { #define CY_IP_MXCRYPTO 1u #define CY_IP_MXCRYPTO_INSTANCES 1u #define CY_IP_MXCRYPTO_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -300,24 +285,39 @@ typedef enum { #define CY_IP_MXS40PASS_CTB 1u #define CY_IP_MXS40PASS_CTB_INSTANCES 1u #define CY_IP_MXS40PASS_CTB_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u -#define CY_IP_MXUDB 1u -#define CY_IP_MXUDB_INSTANCES 1u -#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUDB 1u +#define CY_IP_MXUDB_INSTANCES 1u +#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_124_bga.h" @@ -617,6 +617,7 @@ typedef enum { #define PROT_BASE 0x40240000UL #define PROT ((PROT_Type*) PROT_BASE) /* 0x40240000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ #define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40242000 */ #define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40242040 */ #define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40242080 */ @@ -633,23 +634,6 @@ typedef enum { #define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40242340 */ #define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40242380 */ #define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402423C0 */ -#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ -#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ -#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ -#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ -#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ -#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ -#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ -#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ -#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ -#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ -#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ -#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ -#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ -#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ -#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ -#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ -#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ #define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40244000 */ #define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40244400 */ #define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40244800 */ @@ -666,6 +650,22 @@ typedef enum { #define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40247400 */ #define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40247800 */ #define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40247C00 */ +#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ +#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ +#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ +#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ +#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ +#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ +#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ +#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ /******************************************************************************* * FLASHC @@ -815,6 +815,12 @@ typedef enum { #define UDB ((UDB_Type*) UDB_BASE) /* 0x40340000 */ #define UDB_WRKONE ((UDB_WRKONE_Type*) &UDB->WRKONE) /* 0x40340000 */ #define UDB_WRKMULT ((UDB_WRKMULT_Type*) &UDB->WRKMULT) /* 0x40341000 */ +#define UDB_UDBPAIR0 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[0]) /* 0x40342000 */ +#define UDB_UDBPAIR1 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[1]) /* 0x40342200 */ +#define UDB_UDBPAIR2 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[2]) /* 0x40342400 */ +#define UDB_UDBPAIR3 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[3]) /* 0x40342600 */ +#define UDB_UDBPAIR4 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[4]) /* 0x40342800 */ +#define UDB_UDBPAIR5 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[5]) /* 0x40342A00 */ #define UDB_UDBPAIR0_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[0].UDBSNG[0]) /* 0x40342000 */ #define UDB_UDBPAIR0_UDBSNG1 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[0].UDBSNG[1]) /* 0x40342080 */ #define UDB_UDBPAIR1_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[1].UDBSNG[0]) /* 0x40342200 */ @@ -833,12 +839,6 @@ typedef enum { #define UDB_UDBPAIR3_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[3].ROUTE) /* 0x40342700 */ #define UDB_UDBPAIR4_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[4].ROUTE) /* 0x40342900 */ #define UDB_UDBPAIR5_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[5].ROUTE) /* 0x40342B00 */ -#define UDB_UDBPAIR0 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[0]) /* 0x40342000 */ -#define UDB_UDBPAIR1 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[1]) /* 0x40342200 */ -#define UDB_UDBPAIR2 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[2]) /* 0x40342400 */ -#define UDB_UDBPAIR3 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[3]) /* 0x40342600 */ -#define UDB_UDBPAIR4 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[4]) /* 0x40342800 */ -#define UDB_UDBPAIR5 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[5]) /* 0x40342A00 */ #define UDB_DSI0 ((UDB_DSI_Type*) &UDB->DSI[0]) /* 0x40346000 */ #define UDB_DSI1 ((UDB_DSI_Type*) &UDB->DSI[1]) /* 0x40346080 */ #define UDB_DSI2 ((UDB_DSI_Type*) &UDB->DSI[2]) /* 0x40346100 */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6137fdi_f02.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6137fdi_f02.h index 5f399b6363..be6928993b 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6137fdi_f02.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6137fdi_f02.h @@ -5,11 +5,11 @@ * CY8C6137FDI-F02 device header * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -236,52 +236,37 @@ typedef enum { #define CY_FLASH_SIZE 0x00100000UL #define CY_EM_EEPROM_BASE 0x14000000UL #define CY_EM_EEPROM_SIZE 0x00008000UL -#define CY_XIP_BASE 0x18000000UL -#define CY_XIP_SIZE 0x08000000UL #define CY_SFLASH_BASE 0x16000000UL #define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL #define CY_EFUSE_BASE 0x402C0800UL #define CY_EFUSE_SIZE 0x00000200UL #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u #define CY_IP_M4CPUSS_DMA 1u #define CY_IP_M4CPUSS_DMA_INSTANCES 2u #define CY_IP_M4CPUSS_DMA_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -294,21 +279,36 @@ typedef enum { #define CY_IP_MXS40PASS_CTDAC 1u #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u #define CY_IP_MXS40PASS_CTDAC_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_80_wlcsp.h" @@ -601,6 +601,7 @@ typedef enum { #define PROT_BASE 0x40240000UL #define PROT ((PROT_Type*) PROT_BASE) /* 0x40240000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ #define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40242000 */ #define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40242040 */ #define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40242080 */ @@ -617,23 +618,6 @@ typedef enum { #define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40242340 */ #define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40242380 */ #define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402423C0 */ -#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ -#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ -#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ -#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ -#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ -#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ -#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ -#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ -#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ -#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ -#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ -#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ -#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ -#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ -#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ -#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ -#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ #define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40244000 */ #define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40244400 */ #define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40244800 */ @@ -650,6 +634,22 @@ typedef enum { #define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40247400 */ #define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40247800 */ #define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40247C00 */ +#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ +#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ +#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ +#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ +#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ +#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ +#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ +#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ /******************************************************************************* * FLASHC diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6137wi_f54.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6137wi_f54.h index cbd86dec54..8438299d9d 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6137wi_f54.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6137wi_f54.h @@ -5,11 +5,11 @@ * CY8C6137WI-F54 device header * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -236,43 +236,19 @@ typedef enum { #define CY_FLASH_SIZE 0x00100000UL #define CY_EM_EEPROM_BASE 0x14000000UL #define CY_EM_EEPROM_SIZE 0x00008000UL -#define CY_XIP_BASE 0x18000000UL -#define CY_XIP_SIZE 0x08000000UL #define CY_SFLASH_BASE 0x16000000UL #define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL #define CY_EFUSE_BASE 0x402C0800UL #define CY_EFUSE_SIZE 0x00000200UL #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u @@ -282,9 +258,18 @@ typedef enum { #define CY_IP_MXCRYPTO 1u #define CY_IP_MXCRYPTO_INSTANCES 1u #define CY_IP_MXCRYPTO_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -300,24 +285,39 @@ typedef enum { #define CY_IP_MXS40PASS_CTB 1u #define CY_IP_MXS40PASS_CTB_INSTANCES 1u #define CY_IP_MXS40PASS_CTB_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u -#define CY_IP_MXUDB 1u -#define CY_IP_MXUDB_INSTANCES 1u -#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUDB 1u +#define CY_IP_MXUDB_INSTANCES 1u +#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_124_bga.h" @@ -617,6 +617,7 @@ typedef enum { #define PROT_BASE 0x40240000UL #define PROT ((PROT_Type*) PROT_BASE) /* 0x40240000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ #define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40242000 */ #define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40242040 */ #define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40242080 */ @@ -633,23 +634,6 @@ typedef enum { #define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40242340 */ #define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40242380 */ #define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402423C0 */ -#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ -#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ -#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ -#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ -#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ -#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ -#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ -#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ -#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ -#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ -#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ -#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ -#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ -#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ -#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ -#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ -#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ #define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40244000 */ #define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40244400 */ #define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40244800 */ @@ -666,6 +650,22 @@ typedef enum { #define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40247400 */ #define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40247800 */ #define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40247C00 */ +#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ +#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ +#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ +#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ +#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ +#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ +#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ +#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ /******************************************************************************* * FLASHC @@ -815,6 +815,12 @@ typedef enum { #define UDB ((UDB_Type*) UDB_BASE) /* 0x40340000 */ #define UDB_WRKONE ((UDB_WRKONE_Type*) &UDB->WRKONE) /* 0x40340000 */ #define UDB_WRKMULT ((UDB_WRKMULT_Type*) &UDB->WRKMULT) /* 0x40341000 */ +#define UDB_UDBPAIR0 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[0]) /* 0x40342000 */ +#define UDB_UDBPAIR1 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[1]) /* 0x40342200 */ +#define UDB_UDBPAIR2 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[2]) /* 0x40342400 */ +#define UDB_UDBPAIR3 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[3]) /* 0x40342600 */ +#define UDB_UDBPAIR4 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[4]) /* 0x40342800 */ +#define UDB_UDBPAIR5 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[5]) /* 0x40342A00 */ #define UDB_UDBPAIR0_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[0].UDBSNG[0]) /* 0x40342000 */ #define UDB_UDBPAIR0_UDBSNG1 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[0].UDBSNG[1]) /* 0x40342080 */ #define UDB_UDBPAIR1_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[1].UDBSNG[0]) /* 0x40342200 */ @@ -833,12 +839,6 @@ typedef enum { #define UDB_UDBPAIR3_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[3].ROUTE) /* 0x40342700 */ #define UDB_UDBPAIR4_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[4].ROUTE) /* 0x40342900 */ #define UDB_UDBPAIR5_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[5].ROUTE) /* 0x40342B00 */ -#define UDB_UDBPAIR0 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[0]) /* 0x40342000 */ -#define UDB_UDBPAIR1 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[1]) /* 0x40342200 */ -#define UDB_UDBPAIR2 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[2]) /* 0x40342400 */ -#define UDB_UDBPAIR3 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[3]) /* 0x40342600 */ -#define UDB_UDBPAIR4 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[4]) /* 0x40342800 */ -#define UDB_UDBPAIR5 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[5]) /* 0x40342A00 */ #define UDB_DSI0 ((UDB_DSI_Type*) &UDB->DSI[0]) /* 0x40346000 */ #define UDB_DSI1 ((UDB_DSI_Type*) &UDB->DSI[1]) /* 0x40346080 */ #define UDB_DSI2 ((UDB_DSI_Type*) &UDB->DSI[2]) /* 0x40346100 */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6144azi_s4f12.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6144azi_s4f12.h new file mode 100644 index 0000000000..28e9c5d10f --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6144azi_s4f12.h @@ -0,0 +1,968 @@ +/***************************************************************************//** +* \file cy8c6144azi_s4f12.h +* +* \brief +* CY8C6144AZI-S4F12 device header +* +* \note +* Generator version: 1.6.0.225 +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CY8C6144AZI_S4F12_H_ +#define _CY8C6144AZI_S4F12_H_ + +/** +* \addtogroup group_device CY8C6144AZI-S4F12 +* \{ +*/ + +/** +* \addtogroup Configuration_of_CMSIS +* \{ +*/ + +/******************************************************************************* +* Interrupt Number Definition +*******************************************************************************/ + +typedef enum { + /* ARM Cortex-M4 Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C6144AZI-S4F12 Peripheral Interrupt Numbers */ + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_6_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #6 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + pass_interrupt_sar_0_IRQn = 39, /*!< 39 [DeepSleep] SAR ADC0 interrupt */ + pass_interrupt_sar_1_IRQn = 40, /*!< 40 [DeepSleep] SAR ADC1 interrupt */ + pass_interrupt_ctb_IRQn = 41, /*!< 41 [DeepSleep] individual interrupt per CTB */ + pass_interrupt_fifo_0_IRQn = 43, /*!< 43 [DeepSleep] PASS FIFO0 */ + pass_interrupt_fifo_1_IRQn = 44, /*!< 44 [DeepSleep] PASS FIFO1 */ + scb_0_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #2 */ + scb_4_interrupt_IRQn = 49, /*!< 49 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 50, /*!< 50 [Active] Serial Communication Block #5 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_0_interrupts_256_IRQn = 131, /*!< 131 [Active] TCPWM #0, Counter #256 */ + tcpwm_0_interrupts_257_IRQn = 132, /*!< 132 [Active] TCPWM #0, Counter #257 */ + tcpwm_0_interrupts_258_IRQn = 133, /*!< 133 [Active] TCPWM #0, Counter #258 */ + tcpwm_0_interrupts_259_IRQn = 134, /*!< 134 [Active] TCPWM #0, Counter #259 */ + tcpwm_0_interrupts_260_IRQn = 135, /*!< 135 [Active] TCPWM #0, Counter #260 */ + tcpwm_0_interrupts_261_IRQn = 136, /*!< 136 [Active] TCPWM #0, Counter #261 */ + tcpwm_0_interrupts_262_IRQn = 137, /*!< 137 [Active] TCPWM #0, Counter #262 */ + tcpwm_0_interrupts_263_IRQn = 138, /*!< 138 [Active] TCPWM #0, Counter #263 */ + pass_interrupt_dacs_IRQn = 146, /*!< 146 [Active] Consolidated interrrupt for all DACs */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + canfd_0_interrupt0_IRQn = 168, /*!< 168 [Active] Can #0, Consolidated interrupt #0 */ + canfd_0_interrupts0_0_IRQn = 169, /*!< 169 [Active] CAN #0, Interrupt #0, Channel #0 */ + canfd_0_interrupts1_0_IRQn = 170, /*!< 170 [Active] CAN #0, Interrupt #1, Channel #0 */ + cpuss_interrupts_dw1_29_IRQn = 171, /*!< 171 [Active] CPUSS DataWire #1, Channel #29 */ + cpuss_interrupts_dw1_30_IRQn = 172, /*!< 172 [Active] CPUSS DataWire #1, Channel #30 */ + cpuss_interrupts_dw1_31_IRQn = 173, /*!< 173 [Active] CPUSS DataWire #1, Channel #31 */ + cpuss_interrupts_dw0_29_IRQn = 174, /*!< 174 [Active] CPUSS DataWire #0, Channel #29 */ + unconnected_IRQn = 240 /*!< 240 Unconnected */ +} IRQn_Type; + + +/******************************************************************************* +* Processor and Core Peripheral Section +*******************************************************************************/ + +/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __CM0P_PRESENT 0 /*!< CM0P present or not */ +#define __DTCM_PRESENT 0 /*!< DTCM present or not */ +#define __ICACHE_PRESENT 0 /*!< ICACHE present or not */ +#define __DCACHE_PRESENT 0 /*!< DCACHE present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + + +/* Memory Blocks */ +#define CY_ROM_BASE 0x00000000UL +#define CY_ROM_SIZE 0x00010000UL +#define CY_SRAM_BASE 0x08000000UL +#define CY_SRAM_SIZE 0x00020000UL +#define CY_FLASH_BASE 0x10000000UL +#define CY_FLASH_SIZE 0x00040000UL +#define CY_EM_EEPROM_BASE 0x14000000UL +#define CY_EM_EEPROM_SIZE 0x00000000UL +#define CY_SFLASH_BASE 0x16000000UL +#define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL +#define CY_EFUSE_BASE 0x402C0800UL +#define CY_EFUSE_SIZE 0x00000200UL +#define CY_CAN0MRAM_BASE 0x40530000UL +#define CY_CAN0MRAM_SIZE 0x00010000UL + +#include "system_psoc6.h" /*!< PSoC 6 System */ + +/* IP List */ +#define CY_IP_MXTTCANFD 1u +#define CY_IP_MXTTCANFD_INSTANCES 1u +#define CY_IP_MXTTCANFD_VERSION 1u +#define CY_IP_M4CPUSS 1u +#define CY_IP_M4CPUSS_INSTANCES 1u +#define CY_IP_M4CPUSS_VERSION 2u +#define CY_IP_M4CPUSS_DMAC 1u +#define CY_IP_M4CPUSS_DMAC_INSTANCES 1u +#define CY_IP_M4CPUSS_DMAC_VERSION 2u +#define CY_IP_M4CPUSS_DMA 1u +#define CY_IP_M4CPUSS_DMA_INSTANCES 2u +#define CY_IP_M4CPUSS_DMA_VERSION 2u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 2u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 6u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u + +#include "psoc6_04_config.h" +#include "gpio_psoc6_04_64_tqfp.h" + +#define CY_DEVICE_PSOC6A256K +#define CY_SILICON_ID 0xEAD2110EUL +#define CY_HF_CLK_MAX_FREQ 150000000UL + +#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL + +/******************************************************************************* +* SFLASH +*******************************************************************************/ + +#define SFLASH_BASE 0x16000000UL +#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */ + +/******************************************************************************* +* PERI +*******************************************************************************/ + +#define PERI_BASE 0x40000000UL +#define PERI ((PERI_Type*) PERI_BASE) /* 0x40000000 */ +#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40004000 */ +#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40004020 */ +#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40004040 */ +#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x40004060 */ +#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40004080 */ +#define PERI_GR5 ((PERI_GR_Type*) &PERI->GR[5]) /* 0x400040A0 */ +#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x400040C0 */ +#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40004120 */ +#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40008000 */ +#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40008400 */ +#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40008800 */ +#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40008C00 */ +#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40009000 */ +#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40009400 */ +#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40009800 */ +#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40009C00 */ +#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ +#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ +#define PERI_TR_GR10 ((PERI_TR_GR_Type*) &PERI->TR_GR[10]) /* 0x4000A800 */ +#define PERI_TR_GR11 ((PERI_TR_GR_Type*) &PERI->TR_GR[11]) /* 0x4000AC00 */ +#define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ +#define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ +#define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ +#define PERI_TR_1TO1_GR3 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[3]) /* 0x4000CC00 */ +#define PERI_TR_1TO1_GR4 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[4]) /* 0x4000D000 */ +#define PERI_TR_1TO1_GR5 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[5]) /* 0x4000D400 */ +#define PERI_TR_1TO1_GR6 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[6]) /* 0x4000D800 */ +#define PERI_TR_1TO1_GR7 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[7]) /* 0x4000DC00 */ +#define PERI_TR_1TO1_GR8 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[8]) /* 0x4000E000 */ + +/******************************************************************************* +* PERI_MS +*******************************************************************************/ + +#define PERI_MS_BASE 0x40010000UL +#define PERI_MS ((PERI_MS_Type*) PERI_MS_BASE) /* 0x40010000 */ +#define PERI_MS_PPU_PR0 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[0]) /* 0x40010000 */ +#define PERI_MS_PPU_PR1 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[1]) /* 0x40010040 */ +#define PERI_MS_PPU_PR2 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[2]) /* 0x40010080 */ +#define PERI_MS_PPU_PR3 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[3]) /* 0x400100C0 */ +#define PERI_MS_PPU_PR4 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[4]) /* 0x40010100 */ +#define PERI_MS_PPU_PR5 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[5]) /* 0x40010140 */ +#define PERI_MS_PPU_PR6 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[6]) /* 0x40010180 */ +#define PERI_MS_PPU_PR7 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[7]) /* 0x400101C0 */ +#define PERI_MS_PPU_FX_PERI_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[0]) /* 0x40010800 */ +#define PERI_MS_PPU_FX_PERI_GR0_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[1]) /* 0x40010840 */ +#define PERI_MS_PPU_FX_PERI_GR1_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[2]) /* 0x40010880 */ +#define PERI_MS_PPU_FX_PERI_GR2_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[3]) /* 0x400108C0 */ +#define PERI_MS_PPU_FX_PERI_GR3_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[4]) /* 0x40010900 */ +#define PERI_MS_PPU_FX_PERI_GR4_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[5]) /* 0x40010940 */ +#define PERI_MS_PPU_FX_PERI_GR5_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[6]) /* 0x40010980 */ +#define PERI_MS_PPU_FX_PERI_GR6_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[7]) /* 0x400109C0 */ +#define PERI_MS_PPU_FX_PERI_GR9_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[8]) /* 0x40010A00 */ +#define PERI_MS_PPU_FX_PERI_TR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[9]) /* 0x40010A40 */ +#define PERI_MS_PPU_FX_CRYPTO_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[10]) /* 0x40010A80 */ +#define PERI_MS_PPU_FX_CRYPTO_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[11]) /* 0x40010AC0 */ +#define PERI_MS_PPU_FX_CRYPTO_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[12]) /* 0x40010B00 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[13]) /* 0x40010B40 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[14]) /* 0x40010B80 */ +#define PERI_MS_PPU_FX_CRYPTO_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[15]) /* 0x40010BC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[16]) /* 0x40010C00 */ +#define PERI_MS_PPU_FX_CPUSS_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[17]) /* 0x40010C40 */ +#define PERI_MS_PPU_FX_CPUSS_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[18]) /* 0x40010C80 */ +#define PERI_MS_PPU_FX_CPUSS_CM0_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[19]) /* 0x40010CC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[20]) /* 0x40010D00 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[21]) /* 0x40010D40 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT1_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[22]) /* 0x40010D80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT0_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[23]) /* 0x40010DC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT1_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[24]) /* 0x40010E00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT2_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[25]) /* 0x40010E40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT3_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[26]) /* 0x40010E80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT4_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[27]) /* 0x40010EC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT5_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[28]) /* 0x40010F00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT6_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[29]) /* 0x40010F40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT7_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[30]) /* 0x40010F80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT8_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[31]) /* 0x40010FC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT9_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[32]) /* 0x40011000 */ +#define PERI_MS_PPU_FX_IPC_STRUCT10_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[33]) /* 0x40011040 */ +#define PERI_MS_PPU_FX_IPC_STRUCT11_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[34]) /* 0x40011080 */ +#define PERI_MS_PPU_FX_IPC_STRUCT12_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[35]) /* 0x400110C0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT13_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[36]) /* 0x40011100 */ +#define PERI_MS_PPU_FX_IPC_STRUCT14_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[37]) /* 0x40011140 */ +#define PERI_MS_PPU_FX_IPC_STRUCT15_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[38]) /* 0x40011180 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT0_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[39]) /* 0x400111C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT1_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[40]) /* 0x40011200 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT2_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[41]) /* 0x40011240 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT3_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[42]) /* 0x40011280 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT4_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[43]) /* 0x400112C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT5_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[44]) /* 0x40011300 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT6_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[45]) /* 0x40011340 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT7_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[46]) /* 0x40011380 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT8_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[47]) /* 0x400113C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT9_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[48]) /* 0x40011400 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT10_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[49]) /* 0x40011440 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT11_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[50]) /* 0x40011480 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT12_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[51]) /* 0x400114C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT13_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[52]) /* 0x40011500 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT14_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[53]) /* 0x40011540 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT15_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[54]) /* 0x40011580 */ +#define PERI_MS_PPU_FX_PROT_SMPU_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[55]) /* 0x400115C0 */ +#define PERI_MS_PPU_FX_PROT_MPU0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[56]) /* 0x40011600 */ +#define PERI_MS_PPU_FX_PROT_MPU14_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[57]) /* 0x40011640 */ +#define PERI_MS_PPU_FX_PROT_MPU15_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[58]) /* 0x40011680 */ +#define PERI_MS_PPU_FX_FLASHC_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[59]) /* 0x400116C0 */ +#define PERI_MS_PPU_FX_FLASHC_CMD ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[60]) /* 0x40011700 */ +#define PERI_MS_PPU_FX_FLASHC_DFT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[61]) /* 0x40011740 */ +#define PERI_MS_PPU_FX_FLASHC_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[62]) /* 0x40011780 */ +#define PERI_MS_PPU_FX_FLASHC_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[63]) /* 0x400117C0 */ +#define PERI_MS_PPU_FX_FLASHC_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[64]) /* 0x40011800 */ +#define PERI_MS_PPU_FX_FLASHC_DW0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[65]) /* 0x40011840 */ +#define PERI_MS_PPU_FX_FLASHC_DW1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[66]) /* 0x40011880 */ +#define PERI_MS_PPU_FX_FLASHC_DMAC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[67]) /* 0x400118C0 */ +#define PERI_MS_PPU_FX_FLASHC_FM ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[68]) /* 0x40011900 */ +#define PERI_MS_PPU_FX_SRSS_MAIN1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[69]) /* 0x40011940 */ +#define PERI_MS_PPU_FX_SRSS_MAIN2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[70]) /* 0x40011980 */ +#define PERI_MS_PPU_FX_WDT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[71]) /* 0x400119C0 */ +#define PERI_MS_PPU_FX_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[72]) /* 0x40011A00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[73]) /* 0x40011A40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[74]) /* 0x40011A80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[75]) /* 0x40011AC0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[76]) /* 0x40011B00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[77]) /* 0x40011B40 */ +#define PERI_MS_PPU_FX_BACKUP_BACKUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[78]) /* 0x40011B80 */ +#define PERI_MS_PPU_FX_DW0_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[79]) /* 0x40011BC0 */ +#define PERI_MS_PPU_FX_DW1_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[80]) /* 0x40011C00 */ +#define PERI_MS_PPU_FX_DW0_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[81]) /* 0x40011C40 */ +#define PERI_MS_PPU_FX_DW1_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[82]) /* 0x40011C80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[83]) /* 0x40011CC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[84]) /* 0x40011D00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[85]) /* 0x40011D40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[86]) /* 0x40011D80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[87]) /* 0x40011DC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[88]) /* 0x40011E00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[89]) /* 0x40011E40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[90]) /* 0x40011E80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[91]) /* 0x40011EC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[92]) /* 0x40011F00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[93]) /* 0x40011F40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[94]) /* 0x40011F80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[95]) /* 0x40011FC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[96]) /* 0x40012000 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[97]) /* 0x40012040 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[98]) /* 0x40012080 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[99]) /* 0x400120C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[100]) /* 0x40012100 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[101]) /* 0x40012140 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[102]) /* 0x40012180 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[103]) /* 0x400121C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[104]) /* 0x40012200 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[105]) /* 0x40012240 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[106]) /* 0x40012280 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[107]) /* 0x400122C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[108]) /* 0x40012300 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[109]) /* 0x40012340 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[110]) /* 0x40012380 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[111]) /* 0x400123C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT29_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[112]) /* 0x40012400 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[113]) /* 0x40012440 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[114]) /* 0x40012480 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[115]) /* 0x400124C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[116]) /* 0x40012500 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[117]) /* 0x40012540 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[118]) /* 0x40012580 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[119]) /* 0x400125C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[120]) /* 0x40012600 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[121]) /* 0x40012640 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[122]) /* 0x40012680 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[123]) /* 0x400126C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[124]) /* 0x40012700 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[125]) /* 0x40012740 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[126]) /* 0x40012780 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[127]) /* 0x400127C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[128]) /* 0x40012800 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[129]) /* 0x40012840 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[130]) /* 0x40012880 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[131]) /* 0x400128C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[132]) /* 0x40012900 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[133]) /* 0x40012940 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[134]) /* 0x40012980 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[135]) /* 0x400129C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[136]) /* 0x40012A00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[137]) /* 0x40012A40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[138]) /* 0x40012A80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[139]) /* 0x40012AC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[140]) /* 0x40012B00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[141]) /* 0x40012B40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT29_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[142]) /* 0x40012B80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT30_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[143]) /* 0x40012BC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT31_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[144]) /* 0x40012C00 */ +#define PERI_MS_PPU_FX_DMAC_TOP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[145]) /* 0x40012C40 */ +#define PERI_MS_PPU_FX_DMAC_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[146]) /* 0x40012C80 */ +#define PERI_MS_PPU_FX_DMAC_CH1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[147]) /* 0x40012CC0 */ +#define PERI_MS_PPU_FX_EFUSE_CTL ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[148]) /* 0x40012D00 */ +#define PERI_MS_PPU_FX_EFUSE_DATA ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[149]) /* 0x40012D40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[150]) /* 0x40012D80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[151]) /* 0x40012DC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[152]) /* 0x40012E00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[153]) /* 0x40012E40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[154]) /* 0x40012E80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[155]) /* 0x40012EC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[156]) /* 0x40012F00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[157]) /* 0x40012F40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[158]) /* 0x40012F80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[159]) /* 0x40012FC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[160]) /* 0x40013000 */ +#define PERI_MS_PPU_FX_HSIOM_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[161]) /* 0x40013040 */ +#define PERI_MS_PPU_FX_HSIOM_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[162]) /* 0x40013080 */ +#define PERI_MS_PPU_FX_HSIOM_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[163]) /* 0x400130C0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[164]) /* 0x40013100 */ +#define PERI_MS_PPU_FX_HSIOM_AMUX ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[165]) /* 0x40013140 */ +#define PERI_MS_PPU_FX_HSIOM_MON ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[166]) /* 0x40013180 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[167]) /* 0x400131C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[168]) /* 0x40013200 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[169]) /* 0x40013240 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[170]) /* 0x40013280 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[171]) /* 0x400132C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[172]) /* 0x40013300 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[173]) /* 0x40013340 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[174]) /* 0x40013380 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[175]) /* 0x400133C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[176]) /* 0x40013400 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[177]) /* 0x40013440 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[178]) /* 0x40013480 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[179]) /* 0x400134C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[180]) /* 0x40013500 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[181]) /* 0x40013540 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[182]) /* 0x40013580 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[183]) /* 0x400135C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[184]) /* 0x40013600 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[185]) /* 0x40013640 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[186]) /* 0x40013680 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[187]) /* 0x400136C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[188]) /* 0x40013700 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[189]) /* 0x40013740 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[190]) /* 0x40013780 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[191]) /* 0x400137C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[192]) /* 0x40013800 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[193]) /* 0x40013840 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[194]) /* 0x40013880 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[195]) /* 0x400138C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[196]) /* 0x40013900 */ +#define PERI_MS_PPU_FX_GPIO_GPIO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[197]) /* 0x40013940 */ +#define PERI_MS_PPU_FX_GPIO_TEST ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[198]) /* 0x40013980 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[199]) /* 0x400139C0 */ +#define PERI_MS_PPU_FX_LPCOMP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[200]) /* 0x40013A00 */ +#define PERI_MS_PPU_FX_CSD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[201]) /* 0x40013A40 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT0_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[202]) /* 0x40013A80 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT1_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[203]) /* 0x40013AC0 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT2_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[204]) /* 0x40013B00 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT3_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[205]) /* 0x40013B40 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT0_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[206]) /* 0x40013B80 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT1_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[207]) /* 0x40013BC0 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT2_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[208]) /* 0x40013C00 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT3_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[209]) /* 0x40013C40 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT4_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[210]) /* 0x40013C80 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT5_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[211]) /* 0x40013CC0 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT6_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[212]) /* 0x40013D00 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT7_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[213]) /* 0x40013D40 */ +#define PERI_MS_PPU_FX_LCD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[214]) /* 0x40013D80 */ +#define PERI_MS_PPU_FX_USBFS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[215]) /* 0x40013DC0 */ +#define PERI_MS_PPU_FX_SMIF0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[216]) /* 0x40013E00 */ +#define PERI_MS_PPU_FX_CANFD0_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[217]) /* 0x40013E40 */ +#define PERI_MS_PPU_FX_CANFD0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[218]) /* 0x40013E80 */ +#define PERI_MS_PPU_FX_CANFD0_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[219]) /* 0x40013EC0 */ +#define PERI_MS_PPU_FX_SCB0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[220]) /* 0x40013F00 */ +#define PERI_MS_PPU_FX_SCB1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[221]) /* 0x40013F40 */ +#define PERI_MS_PPU_FX_SCB2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[222]) /* 0x40013F80 */ +#define PERI_MS_PPU_FX_SCB4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[223]) /* 0x40013FC0 */ +#define PERI_MS_PPU_FX_SCB5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[224]) /* 0x40014000 */ +#define PERI_MS_PPU_FX_SCB6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[225]) /* 0x40014040 */ + +/******************************************************************************* +* CPUSS +*******************************************************************************/ + +#define CPUSS_BASE 0x40200000UL +#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40200000 */ + +/******************************************************************************* +* FAULT +*******************************************************************************/ + +#define FAULT_BASE 0x40210000UL +#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40210000 */ +#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40210000 */ +#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40210100 */ + +/******************************************************************************* +* IPC +*******************************************************************************/ + +#define IPC_BASE 0x40220000UL +#define IPC ((IPC_Type*) IPC_BASE) /* 0x40220000 */ +#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40220000 */ +#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40220020 */ +#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40220040 */ +#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40220060 */ +#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40220080 */ +#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402200A0 */ +#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402200C0 */ +#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402200E0 */ +#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40220100 */ +#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40220120 */ +#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40220140 */ +#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40220160 */ +#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40220180 */ +#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402201A0 */ +#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402201C0 */ +#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402201E0 */ +#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40221000 */ +#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40221020 */ +#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40221040 */ +#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40221060 */ +#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40221080 */ +#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402210A0 */ +#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402210C0 */ +#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402210E0 */ +#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40221100 */ +#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40221120 */ +#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40221140 */ +#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40221160 */ +#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40221180 */ +#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402211A0 */ +#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402211C0 */ +#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402211E0 */ + +/******************************************************************************* +* PROT +*******************************************************************************/ + +#define PROT_BASE 0x40230000UL +#define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ +#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ +#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ +#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402320C0 */ +#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40232100 */ +#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40232140 */ +#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40232180 */ +#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402321C0 */ +#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40232200 */ +#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40232240 */ +#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40232280 */ +#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402322C0 */ +#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40232300 */ +#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ +#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ +#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ + +/******************************************************************************* +* FLASHC +*******************************************************************************/ + +#define FLASHC_BASE 0x40240000UL +#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40240000 */ +#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4024F000 */ + +/******************************************************************************* +* SRSS +*******************************************************************************/ + +#define SRSS_BASE 0x40260000UL +#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ +#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */ +#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */ + +/******************************************************************************* +* BACKUP +*******************************************************************************/ + +#define BACKUP_BASE 0x40270000UL +#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ + +/******************************************************************************* +* DW +*******************************************************************************/ + +#define DW0_BASE 0x40280000UL +#define DW1_BASE 0x40290000UL +#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ +#define DW1 ((DW_Type*) DW1_BASE) /* 0x40290000 */ +#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40288000 */ +#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40288040 */ +#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40288080 */ +#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x402880C0 */ +#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40288100 */ +#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x40288140 */ +#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x40288180 */ +#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402881C0 */ +#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40288200 */ +#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40288240 */ +#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40288280 */ +#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x402882C0 */ +#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40288300 */ +#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x40288340 */ +#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x40288380 */ +#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402883C0 */ +#define DW0_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[16]) /* 0x40288400 */ +#define DW0_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[17]) /* 0x40288440 */ +#define DW0_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[18]) /* 0x40288480 */ +#define DW0_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[19]) /* 0x402884C0 */ +#define DW0_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[20]) /* 0x40288500 */ +#define DW0_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[21]) /* 0x40288540 */ +#define DW0_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[22]) /* 0x40288580 */ +#define DW0_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[23]) /* 0x402885C0 */ +#define DW0_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[24]) /* 0x40288600 */ +#define DW0_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[25]) /* 0x40288640 */ +#define DW0_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[26]) /* 0x40288680 */ +#define DW0_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[27]) /* 0x402886C0 */ +#define DW0_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[28]) /* 0x40288700 */ +#define DW0_CH_STRUCT29 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[29]) /* 0x40288740 */ +#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40298000 */ +#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40298040 */ +#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40298080 */ +#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x402980C0 */ +#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40298100 */ +#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x40298140 */ +#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x40298180 */ +#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402981C0 */ +#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40298200 */ +#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40298240 */ +#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40298280 */ +#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x402982C0 */ +#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40298300 */ +#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x40298340 */ +#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x40298380 */ +#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402983C0 */ +#define DW1_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[16]) /* 0x40298400 */ +#define DW1_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[17]) /* 0x40298440 */ +#define DW1_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[18]) /* 0x40298480 */ +#define DW1_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[19]) /* 0x402984C0 */ +#define DW1_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[20]) /* 0x40298500 */ +#define DW1_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[21]) /* 0x40298540 */ +#define DW1_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[22]) /* 0x40298580 */ +#define DW1_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[23]) /* 0x402985C0 */ +#define DW1_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[24]) /* 0x40298600 */ +#define DW1_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[25]) /* 0x40298640 */ +#define DW1_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[26]) /* 0x40298680 */ +#define DW1_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[27]) /* 0x402986C0 */ +#define DW1_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[28]) /* 0x40298700 */ +#define DW1_CH_STRUCT29 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[29]) /* 0x40298740 */ +#define DW1_CH_STRUCT30 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[30]) /* 0x40298780 */ +#define DW1_CH_STRUCT31 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[31]) /* 0x402987C0 */ + +/******************************************************************************* +* DMAC +*******************************************************************************/ + +#define DMAC_BASE 0x402A0000UL +#define DMAC ((DMAC_Type*) DMAC_BASE) /* 0x402A0000 */ +#define DMAC_CH0 ((DMAC_CH_Type*) &DMAC->CH[0]) /* 0x402A1000 */ +#define DMAC_CH1 ((DMAC_CH_Type*) &DMAC->CH[1]) /* 0x402A1100 */ + +/******************************************************************************* +* EFUSE +*******************************************************************************/ + +#define EFUSE_BASE 0x402C0000UL +#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ + +/******************************************************************************* +* HSIOM +*******************************************************************************/ + +#define HSIOM_BASE 0x40300000UL +#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40300000 */ +#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40300000 */ +#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40300010 */ +#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40300020 */ +#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40300030 */ +#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40300040 */ +#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40300050 */ +#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40300060 */ +#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40300070 */ +#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40300080 */ +#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40300090 */ +#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403000A0 */ +#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403000B0 */ +#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403000C0 */ +#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403000D0 */ +#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403000E0 */ + +/******************************************************************************* +* GPIO +*******************************************************************************/ + +#define GPIO_BASE 0x40310000UL +#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40310000 */ +#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40310000 */ +#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40310080 */ +#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40310100 */ +#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40310180 */ +#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40310200 */ +#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40310280 */ +#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40310300 */ +#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40310380 */ +#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40310400 */ +#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40310480 */ +#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40310500 */ +#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40310580 */ +#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40310600 */ +#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40310680 */ +#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40310700 */ + +/******************************************************************************* +* SMARTIO +*******************************************************************************/ + +#define SMARTIO_BASE 0x40320000UL +#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40320000 */ +#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40320900 */ + +/******************************************************************************* +* LPCOMP +*******************************************************************************/ + +#define LPCOMP_BASE 0x40350000UL +#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */ + +/******************************************************************************* +* CSD +*******************************************************************************/ + +#define CSD0_BASE 0x40360000UL +#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */ + +/******************************************************************************* +* TCPWM +*******************************************************************************/ + +#define TCPWM0_BASE 0x40380000UL +#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM0_GRP0 ((TCPWM_GRP_Type*) &TCPWM0->GRP[0]) /* 0x40380000 */ +#define TCPWM0_GRP1 ((TCPWM_GRP_Type*) &TCPWM0->GRP[1]) /* 0x40388000 */ +#define TCPWM0_GRP0_CNT0 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[0]) /* 0x40380000 */ +#define TCPWM0_GRP0_CNT1 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[1]) /* 0x40380080 */ +#define TCPWM0_GRP0_CNT2 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[2]) /* 0x40380100 */ +#define TCPWM0_GRP0_CNT3 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[3]) /* 0x40380180 */ +#define TCPWM0_GRP1_CNT0 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[0]) /* 0x40388000 */ +#define TCPWM0_GRP1_CNT1 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[1]) /* 0x40388080 */ +#define TCPWM0_GRP1_CNT2 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[2]) /* 0x40388100 */ +#define TCPWM0_GRP1_CNT3 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[3]) /* 0x40388180 */ +#define TCPWM0_GRP1_CNT4 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[4]) /* 0x40388200 */ +#define TCPWM0_GRP1_CNT5 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[5]) /* 0x40388280 */ +#define TCPWM0_GRP1_CNT6 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[6]) /* 0x40388300 */ +#define TCPWM0_GRP1_CNT7 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[7]) /* 0x40388380 */ + +/******************************************************************************* +* LCD +*******************************************************************************/ + +#define LCD0_BASE 0x403B0000UL +#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ + +/******************************************************************************* +* SMIF +*******************************************************************************/ + +#define SMIF0_BASE 0x40420000UL +#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ +#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ +#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ +#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ + +/******************************************************************************* +* CANFD +*******************************************************************************/ + +#define CANFD0_BASE 0x40520000UL +#define CANFD0 ((CANFD_Type*) CANFD0_BASE) /* 0x40520000 */ +#define CANFD0_CH0 ((CANFD_CH_Type*) &CANFD0->CH[0]) /* 0x40520000 */ +#define CANFD0_CH0_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[0].M_TTCAN) /* 0x40520000 */ + +/******************************************************************************* +* SCB +*******************************************************************************/ + +#define SCB0_BASE 0x40600000UL +#define SCB1_BASE 0x40610000UL +#define SCB2_BASE 0x40620000UL +#define SCB4_BASE 0x40640000UL +#define SCB5_BASE 0x40650000UL +#define SCB6_BASE 0x40660000UL +#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40600000 */ +#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40610000 */ +#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40620000 */ +#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40640000 */ +#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40650000 */ +#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40660000 */ + +/******************************************************************************* +* CTBM +*******************************************************************************/ + +#define CTBM0_BASE 0x40900000UL +#define CTBM0 ((CTBM_Type*) CTBM0_BASE) /* 0x40900000 */ + +/******************************************************************************* +* CTDAC +*******************************************************************************/ + +#define CTDAC0_BASE 0x40940000UL +#define CTDAC0 ((CTDAC_Type*) CTDAC0_BASE) /* 0x40940000 */ + +/******************************************************************************* +* SAR +*******************************************************************************/ + +#define SAR0_BASE 0x409B0000UL +#define SAR0 ((SAR_Type*) SAR0_BASE) /* 0x409B0000 */ + +/******************************************************************************* +* PASS +*******************************************************************************/ + +#define PASS_BASE 0x409F0000UL +#define PASS ((PASS_Type*) PASS_BASE) /* 0x409F0000 */ +#define PASS_TIMER ((PASS_TIMER_Type*) &PASS->TIMER) /* 0x409F0100 */ +#define PASS_LPOSC ((PASS_LPOSC_Type*) &PASS->LPOSC) /* 0x409F0200 */ +#define PASS_FIFO0 ((PASS_FIFO_Type*) &PASS->FIFO[0]) /* 0x409F0300 */ +#define PASS_FIFO1 ((PASS_FIFO_Type*) &PASS->FIFO[1]) /* 0x409F0400 */ +#define PASS_AREFV2 ((PASS_AREFV2_Type*) &PASS->AREFV2) /* 0x409F0E00 */ + +/** \} CY8C6144AZI-S4F12 */ + +#endif /* _CY8C6144AZI_S4F12_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6144azi_s4f62.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6144azi_s4f62.h new file mode 100644 index 0000000000..753a7435d5 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6144azi_s4f62.h @@ -0,0 +1,968 @@ +/***************************************************************************//** +* \file cy8c6144azi_s4f62.h +* +* \brief +* CY8C6144AZI-S4F62 device header +* +* \note +* Generator version: 1.6.0.225 +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CY8C6144AZI_S4F62_H_ +#define _CY8C6144AZI_S4F62_H_ + +/** +* \addtogroup group_device CY8C6144AZI-S4F62 +* \{ +*/ + +/** +* \addtogroup Configuration_of_CMSIS +* \{ +*/ + +/******************************************************************************* +* Interrupt Number Definition +*******************************************************************************/ + +typedef enum { + /* ARM Cortex-M4 Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C6144AZI-S4F62 Peripheral Interrupt Numbers */ + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_6_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #6 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + pass_interrupt_sar_0_IRQn = 39, /*!< 39 [DeepSleep] SAR ADC0 interrupt */ + pass_interrupt_sar_1_IRQn = 40, /*!< 40 [DeepSleep] SAR ADC1 interrupt */ + pass_interrupt_ctb_IRQn = 41, /*!< 41 [DeepSleep] individual interrupt per CTB */ + pass_interrupt_fifo_0_IRQn = 43, /*!< 43 [DeepSleep] PASS FIFO0 */ + pass_interrupt_fifo_1_IRQn = 44, /*!< 44 [DeepSleep] PASS FIFO1 */ + scb_0_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #2 */ + scb_4_interrupt_IRQn = 49, /*!< 49 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 50, /*!< 50 [Active] Serial Communication Block #5 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_0_interrupts_256_IRQn = 131, /*!< 131 [Active] TCPWM #0, Counter #256 */ + tcpwm_0_interrupts_257_IRQn = 132, /*!< 132 [Active] TCPWM #0, Counter #257 */ + tcpwm_0_interrupts_258_IRQn = 133, /*!< 133 [Active] TCPWM #0, Counter #258 */ + tcpwm_0_interrupts_259_IRQn = 134, /*!< 134 [Active] TCPWM #0, Counter #259 */ + tcpwm_0_interrupts_260_IRQn = 135, /*!< 135 [Active] TCPWM #0, Counter #260 */ + tcpwm_0_interrupts_261_IRQn = 136, /*!< 136 [Active] TCPWM #0, Counter #261 */ + tcpwm_0_interrupts_262_IRQn = 137, /*!< 137 [Active] TCPWM #0, Counter #262 */ + tcpwm_0_interrupts_263_IRQn = 138, /*!< 138 [Active] TCPWM #0, Counter #263 */ + pass_interrupt_dacs_IRQn = 146, /*!< 146 [Active] Consolidated interrrupt for all DACs */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + canfd_0_interrupt0_IRQn = 168, /*!< 168 [Active] Can #0, Consolidated interrupt #0 */ + canfd_0_interrupts0_0_IRQn = 169, /*!< 169 [Active] CAN #0, Interrupt #0, Channel #0 */ + canfd_0_interrupts1_0_IRQn = 170, /*!< 170 [Active] CAN #0, Interrupt #1, Channel #0 */ + cpuss_interrupts_dw1_29_IRQn = 171, /*!< 171 [Active] CPUSS DataWire #1, Channel #29 */ + cpuss_interrupts_dw1_30_IRQn = 172, /*!< 172 [Active] CPUSS DataWire #1, Channel #30 */ + cpuss_interrupts_dw1_31_IRQn = 173, /*!< 173 [Active] CPUSS DataWire #1, Channel #31 */ + cpuss_interrupts_dw0_29_IRQn = 174, /*!< 174 [Active] CPUSS DataWire #0, Channel #29 */ + unconnected_IRQn = 240 /*!< 240 Unconnected */ +} IRQn_Type; + + +/******************************************************************************* +* Processor and Core Peripheral Section +*******************************************************************************/ + +/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __CM0P_PRESENT 0 /*!< CM0P present or not */ +#define __DTCM_PRESENT 0 /*!< DTCM present or not */ +#define __ICACHE_PRESENT 0 /*!< ICACHE present or not */ +#define __DCACHE_PRESENT 0 /*!< DCACHE present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + + +/* Memory Blocks */ +#define CY_ROM_BASE 0x00000000UL +#define CY_ROM_SIZE 0x00010000UL +#define CY_SRAM_BASE 0x08000000UL +#define CY_SRAM_SIZE 0x00020000UL +#define CY_FLASH_BASE 0x10000000UL +#define CY_FLASH_SIZE 0x00040000UL +#define CY_EM_EEPROM_BASE 0x14000000UL +#define CY_EM_EEPROM_SIZE 0x00000000UL +#define CY_SFLASH_BASE 0x16000000UL +#define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL +#define CY_EFUSE_BASE 0x402C0800UL +#define CY_EFUSE_SIZE 0x00000200UL +#define CY_CAN0MRAM_BASE 0x40530000UL +#define CY_CAN0MRAM_SIZE 0x00010000UL + +#include "system_psoc6.h" /*!< PSoC 6 System */ + +/* IP List */ +#define CY_IP_MXTTCANFD 1u +#define CY_IP_MXTTCANFD_INSTANCES 1u +#define CY_IP_MXTTCANFD_VERSION 1u +#define CY_IP_M4CPUSS 1u +#define CY_IP_M4CPUSS_INSTANCES 1u +#define CY_IP_M4CPUSS_VERSION 2u +#define CY_IP_M4CPUSS_DMAC 1u +#define CY_IP_M4CPUSS_DMAC_INSTANCES 1u +#define CY_IP_M4CPUSS_DMAC_VERSION 2u +#define CY_IP_M4CPUSS_DMA 1u +#define CY_IP_M4CPUSS_DMA_INSTANCES 2u +#define CY_IP_M4CPUSS_DMA_VERSION 2u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 2u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 6u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u + +#include "psoc6_04_config.h" +#include "gpio_psoc6_04_64_tqfp.h" + +#define CY_DEVICE_PSOC6A256K +#define CY_SILICON_ID 0xEAD0110EUL +#define CY_HF_CLK_MAX_FREQ 150000000UL + +#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL + +/******************************************************************************* +* SFLASH +*******************************************************************************/ + +#define SFLASH_BASE 0x16000000UL +#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */ + +/******************************************************************************* +* PERI +*******************************************************************************/ + +#define PERI_BASE 0x40000000UL +#define PERI ((PERI_Type*) PERI_BASE) /* 0x40000000 */ +#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40004000 */ +#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40004020 */ +#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40004040 */ +#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x40004060 */ +#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40004080 */ +#define PERI_GR5 ((PERI_GR_Type*) &PERI->GR[5]) /* 0x400040A0 */ +#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x400040C0 */ +#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40004120 */ +#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40008000 */ +#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40008400 */ +#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40008800 */ +#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40008C00 */ +#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40009000 */ +#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40009400 */ +#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40009800 */ +#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40009C00 */ +#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ +#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ +#define PERI_TR_GR10 ((PERI_TR_GR_Type*) &PERI->TR_GR[10]) /* 0x4000A800 */ +#define PERI_TR_GR11 ((PERI_TR_GR_Type*) &PERI->TR_GR[11]) /* 0x4000AC00 */ +#define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ +#define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ +#define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ +#define PERI_TR_1TO1_GR3 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[3]) /* 0x4000CC00 */ +#define PERI_TR_1TO1_GR4 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[4]) /* 0x4000D000 */ +#define PERI_TR_1TO1_GR5 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[5]) /* 0x4000D400 */ +#define PERI_TR_1TO1_GR6 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[6]) /* 0x4000D800 */ +#define PERI_TR_1TO1_GR7 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[7]) /* 0x4000DC00 */ +#define PERI_TR_1TO1_GR8 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[8]) /* 0x4000E000 */ + +/******************************************************************************* +* PERI_MS +*******************************************************************************/ + +#define PERI_MS_BASE 0x40010000UL +#define PERI_MS ((PERI_MS_Type*) PERI_MS_BASE) /* 0x40010000 */ +#define PERI_MS_PPU_PR0 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[0]) /* 0x40010000 */ +#define PERI_MS_PPU_PR1 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[1]) /* 0x40010040 */ +#define PERI_MS_PPU_PR2 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[2]) /* 0x40010080 */ +#define PERI_MS_PPU_PR3 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[3]) /* 0x400100C0 */ +#define PERI_MS_PPU_PR4 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[4]) /* 0x40010100 */ +#define PERI_MS_PPU_PR5 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[5]) /* 0x40010140 */ +#define PERI_MS_PPU_PR6 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[6]) /* 0x40010180 */ +#define PERI_MS_PPU_PR7 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[7]) /* 0x400101C0 */ +#define PERI_MS_PPU_FX_PERI_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[0]) /* 0x40010800 */ +#define PERI_MS_PPU_FX_PERI_GR0_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[1]) /* 0x40010840 */ +#define PERI_MS_PPU_FX_PERI_GR1_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[2]) /* 0x40010880 */ +#define PERI_MS_PPU_FX_PERI_GR2_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[3]) /* 0x400108C0 */ +#define PERI_MS_PPU_FX_PERI_GR3_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[4]) /* 0x40010900 */ +#define PERI_MS_PPU_FX_PERI_GR4_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[5]) /* 0x40010940 */ +#define PERI_MS_PPU_FX_PERI_GR5_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[6]) /* 0x40010980 */ +#define PERI_MS_PPU_FX_PERI_GR6_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[7]) /* 0x400109C0 */ +#define PERI_MS_PPU_FX_PERI_GR9_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[8]) /* 0x40010A00 */ +#define PERI_MS_PPU_FX_PERI_TR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[9]) /* 0x40010A40 */ +#define PERI_MS_PPU_FX_CRYPTO_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[10]) /* 0x40010A80 */ +#define PERI_MS_PPU_FX_CRYPTO_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[11]) /* 0x40010AC0 */ +#define PERI_MS_PPU_FX_CRYPTO_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[12]) /* 0x40010B00 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[13]) /* 0x40010B40 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[14]) /* 0x40010B80 */ +#define PERI_MS_PPU_FX_CRYPTO_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[15]) /* 0x40010BC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[16]) /* 0x40010C00 */ +#define PERI_MS_PPU_FX_CPUSS_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[17]) /* 0x40010C40 */ +#define PERI_MS_PPU_FX_CPUSS_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[18]) /* 0x40010C80 */ +#define PERI_MS_PPU_FX_CPUSS_CM0_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[19]) /* 0x40010CC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[20]) /* 0x40010D00 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[21]) /* 0x40010D40 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT1_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[22]) /* 0x40010D80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT0_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[23]) /* 0x40010DC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT1_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[24]) /* 0x40010E00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT2_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[25]) /* 0x40010E40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT3_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[26]) /* 0x40010E80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT4_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[27]) /* 0x40010EC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT5_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[28]) /* 0x40010F00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT6_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[29]) /* 0x40010F40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT7_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[30]) /* 0x40010F80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT8_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[31]) /* 0x40010FC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT9_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[32]) /* 0x40011000 */ +#define PERI_MS_PPU_FX_IPC_STRUCT10_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[33]) /* 0x40011040 */ +#define PERI_MS_PPU_FX_IPC_STRUCT11_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[34]) /* 0x40011080 */ +#define PERI_MS_PPU_FX_IPC_STRUCT12_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[35]) /* 0x400110C0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT13_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[36]) /* 0x40011100 */ +#define PERI_MS_PPU_FX_IPC_STRUCT14_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[37]) /* 0x40011140 */ +#define PERI_MS_PPU_FX_IPC_STRUCT15_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[38]) /* 0x40011180 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT0_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[39]) /* 0x400111C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT1_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[40]) /* 0x40011200 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT2_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[41]) /* 0x40011240 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT3_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[42]) /* 0x40011280 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT4_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[43]) /* 0x400112C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT5_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[44]) /* 0x40011300 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT6_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[45]) /* 0x40011340 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT7_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[46]) /* 0x40011380 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT8_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[47]) /* 0x400113C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT9_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[48]) /* 0x40011400 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT10_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[49]) /* 0x40011440 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT11_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[50]) /* 0x40011480 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT12_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[51]) /* 0x400114C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT13_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[52]) /* 0x40011500 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT14_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[53]) /* 0x40011540 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT15_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[54]) /* 0x40011580 */ +#define PERI_MS_PPU_FX_PROT_SMPU_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[55]) /* 0x400115C0 */ +#define PERI_MS_PPU_FX_PROT_MPU0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[56]) /* 0x40011600 */ +#define PERI_MS_PPU_FX_PROT_MPU14_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[57]) /* 0x40011640 */ +#define PERI_MS_PPU_FX_PROT_MPU15_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[58]) /* 0x40011680 */ +#define PERI_MS_PPU_FX_FLASHC_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[59]) /* 0x400116C0 */ +#define PERI_MS_PPU_FX_FLASHC_CMD ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[60]) /* 0x40011700 */ +#define PERI_MS_PPU_FX_FLASHC_DFT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[61]) /* 0x40011740 */ +#define PERI_MS_PPU_FX_FLASHC_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[62]) /* 0x40011780 */ +#define PERI_MS_PPU_FX_FLASHC_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[63]) /* 0x400117C0 */ +#define PERI_MS_PPU_FX_FLASHC_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[64]) /* 0x40011800 */ +#define PERI_MS_PPU_FX_FLASHC_DW0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[65]) /* 0x40011840 */ +#define PERI_MS_PPU_FX_FLASHC_DW1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[66]) /* 0x40011880 */ +#define PERI_MS_PPU_FX_FLASHC_DMAC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[67]) /* 0x400118C0 */ +#define PERI_MS_PPU_FX_FLASHC_FM ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[68]) /* 0x40011900 */ +#define PERI_MS_PPU_FX_SRSS_MAIN1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[69]) /* 0x40011940 */ +#define PERI_MS_PPU_FX_SRSS_MAIN2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[70]) /* 0x40011980 */ +#define PERI_MS_PPU_FX_WDT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[71]) /* 0x400119C0 */ +#define PERI_MS_PPU_FX_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[72]) /* 0x40011A00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[73]) /* 0x40011A40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[74]) /* 0x40011A80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[75]) /* 0x40011AC0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[76]) /* 0x40011B00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[77]) /* 0x40011B40 */ +#define PERI_MS_PPU_FX_BACKUP_BACKUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[78]) /* 0x40011B80 */ +#define PERI_MS_PPU_FX_DW0_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[79]) /* 0x40011BC0 */ +#define PERI_MS_PPU_FX_DW1_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[80]) /* 0x40011C00 */ +#define PERI_MS_PPU_FX_DW0_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[81]) /* 0x40011C40 */ +#define PERI_MS_PPU_FX_DW1_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[82]) /* 0x40011C80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[83]) /* 0x40011CC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[84]) /* 0x40011D00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[85]) /* 0x40011D40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[86]) /* 0x40011D80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[87]) /* 0x40011DC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[88]) /* 0x40011E00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[89]) /* 0x40011E40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[90]) /* 0x40011E80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[91]) /* 0x40011EC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[92]) /* 0x40011F00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[93]) /* 0x40011F40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[94]) /* 0x40011F80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[95]) /* 0x40011FC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[96]) /* 0x40012000 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[97]) /* 0x40012040 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[98]) /* 0x40012080 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[99]) /* 0x400120C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[100]) /* 0x40012100 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[101]) /* 0x40012140 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[102]) /* 0x40012180 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[103]) /* 0x400121C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[104]) /* 0x40012200 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[105]) /* 0x40012240 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[106]) /* 0x40012280 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[107]) /* 0x400122C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[108]) /* 0x40012300 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[109]) /* 0x40012340 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[110]) /* 0x40012380 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[111]) /* 0x400123C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT29_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[112]) /* 0x40012400 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[113]) /* 0x40012440 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[114]) /* 0x40012480 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[115]) /* 0x400124C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[116]) /* 0x40012500 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[117]) /* 0x40012540 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[118]) /* 0x40012580 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[119]) /* 0x400125C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[120]) /* 0x40012600 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[121]) /* 0x40012640 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[122]) /* 0x40012680 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[123]) /* 0x400126C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[124]) /* 0x40012700 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[125]) /* 0x40012740 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[126]) /* 0x40012780 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[127]) /* 0x400127C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[128]) /* 0x40012800 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[129]) /* 0x40012840 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[130]) /* 0x40012880 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[131]) /* 0x400128C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[132]) /* 0x40012900 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[133]) /* 0x40012940 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[134]) /* 0x40012980 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[135]) /* 0x400129C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[136]) /* 0x40012A00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[137]) /* 0x40012A40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[138]) /* 0x40012A80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[139]) /* 0x40012AC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[140]) /* 0x40012B00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[141]) /* 0x40012B40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT29_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[142]) /* 0x40012B80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT30_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[143]) /* 0x40012BC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT31_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[144]) /* 0x40012C00 */ +#define PERI_MS_PPU_FX_DMAC_TOP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[145]) /* 0x40012C40 */ +#define PERI_MS_PPU_FX_DMAC_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[146]) /* 0x40012C80 */ +#define PERI_MS_PPU_FX_DMAC_CH1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[147]) /* 0x40012CC0 */ +#define PERI_MS_PPU_FX_EFUSE_CTL ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[148]) /* 0x40012D00 */ +#define PERI_MS_PPU_FX_EFUSE_DATA ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[149]) /* 0x40012D40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[150]) /* 0x40012D80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[151]) /* 0x40012DC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[152]) /* 0x40012E00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[153]) /* 0x40012E40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[154]) /* 0x40012E80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[155]) /* 0x40012EC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[156]) /* 0x40012F00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[157]) /* 0x40012F40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[158]) /* 0x40012F80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[159]) /* 0x40012FC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[160]) /* 0x40013000 */ +#define PERI_MS_PPU_FX_HSIOM_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[161]) /* 0x40013040 */ +#define PERI_MS_PPU_FX_HSIOM_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[162]) /* 0x40013080 */ +#define PERI_MS_PPU_FX_HSIOM_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[163]) /* 0x400130C0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[164]) /* 0x40013100 */ +#define PERI_MS_PPU_FX_HSIOM_AMUX ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[165]) /* 0x40013140 */ +#define PERI_MS_PPU_FX_HSIOM_MON ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[166]) /* 0x40013180 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[167]) /* 0x400131C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[168]) /* 0x40013200 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[169]) /* 0x40013240 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[170]) /* 0x40013280 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[171]) /* 0x400132C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[172]) /* 0x40013300 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[173]) /* 0x40013340 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[174]) /* 0x40013380 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[175]) /* 0x400133C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[176]) /* 0x40013400 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[177]) /* 0x40013440 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[178]) /* 0x40013480 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[179]) /* 0x400134C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[180]) /* 0x40013500 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[181]) /* 0x40013540 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[182]) /* 0x40013580 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[183]) /* 0x400135C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[184]) /* 0x40013600 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[185]) /* 0x40013640 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[186]) /* 0x40013680 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[187]) /* 0x400136C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[188]) /* 0x40013700 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[189]) /* 0x40013740 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[190]) /* 0x40013780 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[191]) /* 0x400137C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[192]) /* 0x40013800 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[193]) /* 0x40013840 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[194]) /* 0x40013880 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[195]) /* 0x400138C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[196]) /* 0x40013900 */ +#define PERI_MS_PPU_FX_GPIO_GPIO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[197]) /* 0x40013940 */ +#define PERI_MS_PPU_FX_GPIO_TEST ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[198]) /* 0x40013980 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[199]) /* 0x400139C0 */ +#define PERI_MS_PPU_FX_LPCOMP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[200]) /* 0x40013A00 */ +#define PERI_MS_PPU_FX_CSD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[201]) /* 0x40013A40 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT0_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[202]) /* 0x40013A80 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT1_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[203]) /* 0x40013AC0 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT2_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[204]) /* 0x40013B00 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT3_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[205]) /* 0x40013B40 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT0_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[206]) /* 0x40013B80 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT1_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[207]) /* 0x40013BC0 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT2_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[208]) /* 0x40013C00 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT3_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[209]) /* 0x40013C40 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT4_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[210]) /* 0x40013C80 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT5_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[211]) /* 0x40013CC0 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT6_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[212]) /* 0x40013D00 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT7_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[213]) /* 0x40013D40 */ +#define PERI_MS_PPU_FX_LCD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[214]) /* 0x40013D80 */ +#define PERI_MS_PPU_FX_USBFS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[215]) /* 0x40013DC0 */ +#define PERI_MS_PPU_FX_SMIF0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[216]) /* 0x40013E00 */ +#define PERI_MS_PPU_FX_CANFD0_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[217]) /* 0x40013E40 */ +#define PERI_MS_PPU_FX_CANFD0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[218]) /* 0x40013E80 */ +#define PERI_MS_PPU_FX_CANFD0_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[219]) /* 0x40013EC0 */ +#define PERI_MS_PPU_FX_SCB0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[220]) /* 0x40013F00 */ +#define PERI_MS_PPU_FX_SCB1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[221]) /* 0x40013F40 */ +#define PERI_MS_PPU_FX_SCB2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[222]) /* 0x40013F80 */ +#define PERI_MS_PPU_FX_SCB4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[223]) /* 0x40013FC0 */ +#define PERI_MS_PPU_FX_SCB5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[224]) /* 0x40014000 */ +#define PERI_MS_PPU_FX_SCB6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[225]) /* 0x40014040 */ + +/******************************************************************************* +* CPUSS +*******************************************************************************/ + +#define CPUSS_BASE 0x40200000UL +#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40200000 */ + +/******************************************************************************* +* FAULT +*******************************************************************************/ + +#define FAULT_BASE 0x40210000UL +#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40210000 */ +#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40210000 */ +#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40210100 */ + +/******************************************************************************* +* IPC +*******************************************************************************/ + +#define IPC_BASE 0x40220000UL +#define IPC ((IPC_Type*) IPC_BASE) /* 0x40220000 */ +#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40220000 */ +#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40220020 */ +#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40220040 */ +#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40220060 */ +#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40220080 */ +#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402200A0 */ +#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402200C0 */ +#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402200E0 */ +#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40220100 */ +#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40220120 */ +#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40220140 */ +#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40220160 */ +#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40220180 */ +#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402201A0 */ +#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402201C0 */ +#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402201E0 */ +#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40221000 */ +#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40221020 */ +#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40221040 */ +#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40221060 */ +#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40221080 */ +#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402210A0 */ +#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402210C0 */ +#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402210E0 */ +#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40221100 */ +#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40221120 */ +#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40221140 */ +#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40221160 */ +#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40221180 */ +#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402211A0 */ +#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402211C0 */ +#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402211E0 */ + +/******************************************************************************* +* PROT +*******************************************************************************/ + +#define PROT_BASE 0x40230000UL +#define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ +#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ +#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ +#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402320C0 */ +#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40232100 */ +#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40232140 */ +#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40232180 */ +#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402321C0 */ +#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40232200 */ +#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40232240 */ +#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40232280 */ +#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402322C0 */ +#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40232300 */ +#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ +#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ +#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ + +/******************************************************************************* +* FLASHC +*******************************************************************************/ + +#define FLASHC_BASE 0x40240000UL +#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40240000 */ +#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4024F000 */ + +/******************************************************************************* +* SRSS +*******************************************************************************/ + +#define SRSS_BASE 0x40260000UL +#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ +#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */ +#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */ + +/******************************************************************************* +* BACKUP +*******************************************************************************/ + +#define BACKUP_BASE 0x40270000UL +#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ + +/******************************************************************************* +* DW +*******************************************************************************/ + +#define DW0_BASE 0x40280000UL +#define DW1_BASE 0x40290000UL +#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ +#define DW1 ((DW_Type*) DW1_BASE) /* 0x40290000 */ +#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40288000 */ +#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40288040 */ +#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40288080 */ +#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x402880C0 */ +#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40288100 */ +#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x40288140 */ +#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x40288180 */ +#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402881C0 */ +#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40288200 */ +#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40288240 */ +#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40288280 */ +#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x402882C0 */ +#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40288300 */ +#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x40288340 */ +#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x40288380 */ +#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402883C0 */ +#define DW0_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[16]) /* 0x40288400 */ +#define DW0_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[17]) /* 0x40288440 */ +#define DW0_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[18]) /* 0x40288480 */ +#define DW0_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[19]) /* 0x402884C0 */ +#define DW0_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[20]) /* 0x40288500 */ +#define DW0_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[21]) /* 0x40288540 */ +#define DW0_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[22]) /* 0x40288580 */ +#define DW0_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[23]) /* 0x402885C0 */ +#define DW0_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[24]) /* 0x40288600 */ +#define DW0_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[25]) /* 0x40288640 */ +#define DW0_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[26]) /* 0x40288680 */ +#define DW0_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[27]) /* 0x402886C0 */ +#define DW0_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[28]) /* 0x40288700 */ +#define DW0_CH_STRUCT29 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[29]) /* 0x40288740 */ +#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40298000 */ +#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40298040 */ +#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40298080 */ +#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x402980C0 */ +#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40298100 */ +#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x40298140 */ +#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x40298180 */ +#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402981C0 */ +#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40298200 */ +#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40298240 */ +#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40298280 */ +#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x402982C0 */ +#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40298300 */ +#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x40298340 */ +#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x40298380 */ +#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402983C0 */ +#define DW1_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[16]) /* 0x40298400 */ +#define DW1_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[17]) /* 0x40298440 */ +#define DW1_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[18]) /* 0x40298480 */ +#define DW1_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[19]) /* 0x402984C0 */ +#define DW1_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[20]) /* 0x40298500 */ +#define DW1_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[21]) /* 0x40298540 */ +#define DW1_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[22]) /* 0x40298580 */ +#define DW1_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[23]) /* 0x402985C0 */ +#define DW1_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[24]) /* 0x40298600 */ +#define DW1_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[25]) /* 0x40298640 */ +#define DW1_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[26]) /* 0x40298680 */ +#define DW1_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[27]) /* 0x402986C0 */ +#define DW1_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[28]) /* 0x40298700 */ +#define DW1_CH_STRUCT29 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[29]) /* 0x40298740 */ +#define DW1_CH_STRUCT30 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[30]) /* 0x40298780 */ +#define DW1_CH_STRUCT31 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[31]) /* 0x402987C0 */ + +/******************************************************************************* +* DMAC +*******************************************************************************/ + +#define DMAC_BASE 0x402A0000UL +#define DMAC ((DMAC_Type*) DMAC_BASE) /* 0x402A0000 */ +#define DMAC_CH0 ((DMAC_CH_Type*) &DMAC->CH[0]) /* 0x402A1000 */ +#define DMAC_CH1 ((DMAC_CH_Type*) &DMAC->CH[1]) /* 0x402A1100 */ + +/******************************************************************************* +* EFUSE +*******************************************************************************/ + +#define EFUSE_BASE 0x402C0000UL +#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ + +/******************************************************************************* +* HSIOM +*******************************************************************************/ + +#define HSIOM_BASE 0x40300000UL +#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40300000 */ +#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40300000 */ +#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40300010 */ +#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40300020 */ +#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40300030 */ +#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40300040 */ +#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40300050 */ +#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40300060 */ +#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40300070 */ +#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40300080 */ +#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40300090 */ +#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403000A0 */ +#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403000B0 */ +#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403000C0 */ +#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403000D0 */ +#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403000E0 */ + +/******************************************************************************* +* GPIO +*******************************************************************************/ + +#define GPIO_BASE 0x40310000UL +#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40310000 */ +#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40310000 */ +#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40310080 */ +#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40310100 */ +#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40310180 */ +#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40310200 */ +#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40310280 */ +#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40310300 */ +#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40310380 */ +#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40310400 */ +#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40310480 */ +#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40310500 */ +#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40310580 */ +#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40310600 */ +#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40310680 */ +#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40310700 */ + +/******************************************************************************* +* SMARTIO +*******************************************************************************/ + +#define SMARTIO_BASE 0x40320000UL +#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40320000 */ +#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40320900 */ + +/******************************************************************************* +* LPCOMP +*******************************************************************************/ + +#define LPCOMP_BASE 0x40350000UL +#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */ + +/******************************************************************************* +* CSD +*******************************************************************************/ + +#define CSD0_BASE 0x40360000UL +#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */ + +/******************************************************************************* +* TCPWM +*******************************************************************************/ + +#define TCPWM0_BASE 0x40380000UL +#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM0_GRP0 ((TCPWM_GRP_Type*) &TCPWM0->GRP[0]) /* 0x40380000 */ +#define TCPWM0_GRP1 ((TCPWM_GRP_Type*) &TCPWM0->GRP[1]) /* 0x40388000 */ +#define TCPWM0_GRP0_CNT0 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[0]) /* 0x40380000 */ +#define TCPWM0_GRP0_CNT1 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[1]) /* 0x40380080 */ +#define TCPWM0_GRP0_CNT2 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[2]) /* 0x40380100 */ +#define TCPWM0_GRP0_CNT3 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[3]) /* 0x40380180 */ +#define TCPWM0_GRP1_CNT0 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[0]) /* 0x40388000 */ +#define TCPWM0_GRP1_CNT1 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[1]) /* 0x40388080 */ +#define TCPWM0_GRP1_CNT2 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[2]) /* 0x40388100 */ +#define TCPWM0_GRP1_CNT3 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[3]) /* 0x40388180 */ +#define TCPWM0_GRP1_CNT4 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[4]) /* 0x40388200 */ +#define TCPWM0_GRP1_CNT5 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[5]) /* 0x40388280 */ +#define TCPWM0_GRP1_CNT6 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[6]) /* 0x40388300 */ +#define TCPWM0_GRP1_CNT7 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[7]) /* 0x40388380 */ + +/******************************************************************************* +* LCD +*******************************************************************************/ + +#define LCD0_BASE 0x403B0000UL +#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ + +/******************************************************************************* +* SMIF +*******************************************************************************/ + +#define SMIF0_BASE 0x40420000UL +#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ +#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ +#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ +#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ + +/******************************************************************************* +* CANFD +*******************************************************************************/ + +#define CANFD0_BASE 0x40520000UL +#define CANFD0 ((CANFD_Type*) CANFD0_BASE) /* 0x40520000 */ +#define CANFD0_CH0 ((CANFD_CH_Type*) &CANFD0->CH[0]) /* 0x40520000 */ +#define CANFD0_CH0_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[0].M_TTCAN) /* 0x40520000 */ + +/******************************************************************************* +* SCB +*******************************************************************************/ + +#define SCB0_BASE 0x40600000UL +#define SCB1_BASE 0x40610000UL +#define SCB2_BASE 0x40620000UL +#define SCB4_BASE 0x40640000UL +#define SCB5_BASE 0x40650000UL +#define SCB6_BASE 0x40660000UL +#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40600000 */ +#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40610000 */ +#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40620000 */ +#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40640000 */ +#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40650000 */ +#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40660000 */ + +/******************************************************************************* +* CTBM +*******************************************************************************/ + +#define CTBM0_BASE 0x40900000UL +#define CTBM0 ((CTBM_Type*) CTBM0_BASE) /* 0x40900000 */ + +/******************************************************************************* +* CTDAC +*******************************************************************************/ + +#define CTDAC0_BASE 0x40940000UL +#define CTDAC0 ((CTDAC_Type*) CTDAC0_BASE) /* 0x40940000 */ + +/******************************************************************************* +* SAR +*******************************************************************************/ + +#define SAR0_BASE 0x409B0000UL +#define SAR0 ((SAR_Type*) SAR0_BASE) /* 0x409B0000 */ + +/******************************************************************************* +* PASS +*******************************************************************************/ + +#define PASS_BASE 0x409F0000UL +#define PASS ((PASS_Type*) PASS_BASE) /* 0x409F0000 */ +#define PASS_TIMER ((PASS_TIMER_Type*) &PASS->TIMER) /* 0x409F0100 */ +#define PASS_LPOSC ((PASS_LPOSC_Type*) &PASS->LPOSC) /* 0x409F0200 */ +#define PASS_FIFO0 ((PASS_FIFO_Type*) &PASS->FIFO[0]) /* 0x409F0300 */ +#define PASS_FIFO1 ((PASS_FIFO_Type*) &PASS->FIFO[1]) /* 0x409F0400 */ +#define PASS_AREFV2 ((PASS_AREFV2_Type*) &PASS->AREFV2) /* 0x409F0E00 */ + +/** \} CY8C6144AZI-S4F62 */ + +#endif /* _CY8C6144AZI_S4F62_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6144azi_s4f82.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6144azi_s4f82.h new file mode 100644 index 0000000000..af9b146ac2 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6144azi_s4f82.h @@ -0,0 +1,980 @@ +/***************************************************************************//** +* \file cy8c6144azi_s4f82.h +* +* \brief +* CY8C6144AZI-S4F82 device header +* +* \note +* Generator version: 1.6.0.225 +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CY8C6144AZI_S4F82_H_ +#define _CY8C6144AZI_S4F82_H_ + +/** +* \addtogroup group_device CY8C6144AZI-S4F82 +* \{ +*/ + +/** +* \addtogroup Configuration_of_CMSIS +* \{ +*/ + +/******************************************************************************* +* Interrupt Number Definition +*******************************************************************************/ + +typedef enum { + /* ARM Cortex-M4 Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C6144AZI-S4F82 Peripheral Interrupt Numbers */ + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_6_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #6 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + pass_interrupt_sar_0_IRQn = 39, /*!< 39 [DeepSleep] SAR ADC0 interrupt */ + pass_interrupt_sar_1_IRQn = 40, /*!< 40 [DeepSleep] SAR ADC1 interrupt */ + pass_interrupt_ctb_IRQn = 41, /*!< 41 [DeepSleep] individual interrupt per CTB */ + pass_interrupt_fifo_0_IRQn = 43, /*!< 43 [DeepSleep] PASS FIFO0 */ + pass_interrupt_fifo_1_IRQn = 44, /*!< 44 [DeepSleep] PASS FIFO1 */ + scb_0_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #2 */ + scb_4_interrupt_IRQn = 49, /*!< 49 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 50, /*!< 50 [Active] Serial Communication Block #5 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_0_interrupts_256_IRQn = 131, /*!< 131 [Active] TCPWM #0, Counter #256 */ + tcpwm_0_interrupts_257_IRQn = 132, /*!< 132 [Active] TCPWM #0, Counter #257 */ + tcpwm_0_interrupts_258_IRQn = 133, /*!< 133 [Active] TCPWM #0, Counter #258 */ + tcpwm_0_interrupts_259_IRQn = 134, /*!< 134 [Active] TCPWM #0, Counter #259 */ + tcpwm_0_interrupts_260_IRQn = 135, /*!< 135 [Active] TCPWM #0, Counter #260 */ + tcpwm_0_interrupts_261_IRQn = 136, /*!< 136 [Active] TCPWM #0, Counter #261 */ + tcpwm_0_interrupts_262_IRQn = 137, /*!< 137 [Active] TCPWM #0, Counter #262 */ + tcpwm_0_interrupts_263_IRQn = 138, /*!< 138 [Active] TCPWM #0, Counter #263 */ + pass_interrupt_dacs_IRQn = 146, /*!< 146 [Active] Consolidated interrrupt for all DACs */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + canfd_0_interrupt0_IRQn = 168, /*!< 168 [Active] Can #0, Consolidated interrupt #0 */ + canfd_0_interrupts0_0_IRQn = 169, /*!< 169 [Active] CAN #0, Interrupt #0, Channel #0 */ + canfd_0_interrupts1_0_IRQn = 170, /*!< 170 [Active] CAN #0, Interrupt #1, Channel #0 */ + cpuss_interrupts_dw1_29_IRQn = 171, /*!< 171 [Active] CPUSS DataWire #1, Channel #29 */ + cpuss_interrupts_dw1_30_IRQn = 172, /*!< 172 [Active] CPUSS DataWire #1, Channel #30 */ + cpuss_interrupts_dw1_31_IRQn = 173, /*!< 173 [Active] CPUSS DataWire #1, Channel #31 */ + cpuss_interrupts_dw0_29_IRQn = 174, /*!< 174 [Active] CPUSS DataWire #0, Channel #29 */ + unconnected_IRQn = 240 /*!< 240 Unconnected */ +} IRQn_Type; + + +/******************************************************************************* +* Processor and Core Peripheral Section +*******************************************************************************/ + +/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __CM0P_PRESENT 0 /*!< CM0P present or not */ +#define __DTCM_PRESENT 0 /*!< DTCM present or not */ +#define __ICACHE_PRESENT 0 /*!< ICACHE present or not */ +#define __DCACHE_PRESENT 0 /*!< DCACHE present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + + +/* Memory Blocks */ +#define CY_ROM_BASE 0x00000000UL +#define CY_ROM_SIZE 0x00010000UL +#define CY_SRAM_BASE 0x08000000UL +#define CY_SRAM_SIZE 0x00020000UL +#define CY_FLASH_BASE 0x10000000UL +#define CY_FLASH_SIZE 0x00040000UL +#define CY_EM_EEPROM_BASE 0x14000000UL +#define CY_EM_EEPROM_SIZE 0x00000000UL +#define CY_SFLASH_BASE 0x16000000UL +#define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL +#define CY_EFUSE_BASE 0x402C0800UL +#define CY_EFUSE_SIZE 0x00000200UL +#define CY_CAN0MRAM_BASE 0x40530000UL +#define CY_CAN0MRAM_SIZE 0x00010000UL + +#include "system_psoc6.h" /*!< PSoC 6 System */ + +/* IP List */ +#define CY_IP_MXTTCANFD 1u +#define CY_IP_MXTTCANFD_INSTANCES 1u +#define CY_IP_MXTTCANFD_VERSION 1u +#define CY_IP_M4CPUSS 1u +#define CY_IP_M4CPUSS_INSTANCES 1u +#define CY_IP_M4CPUSS_VERSION 2u +#define CY_IP_M4CPUSS_DMAC 1u +#define CY_IP_M4CPUSS_DMAC_INSTANCES 1u +#define CY_IP_M4CPUSS_DMAC_VERSION 2u +#define CY_IP_M4CPUSS_DMA 1u +#define CY_IP_M4CPUSS_DMA_INSTANCES 2u +#define CY_IP_M4CPUSS_DMA_VERSION 2u +#define CY_IP_MXCRYPTO 1u +#define CY_IP_MXCRYPTO_INSTANCES 1u +#define CY_IP_MXCRYPTO_VERSION 2u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 2u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 6u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u + +#include "psoc6_04_config.h" +#include "gpio_psoc6_04_64_tqfp.h" + +#define CY_DEVICE_PSOC6A256K +#define CY_SILICON_ID 0xEACD110EUL +#define CY_HF_CLK_MAX_FREQ 150000000UL + +#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL + +/******************************************************************************* +* SFLASH +*******************************************************************************/ + +#define SFLASH_BASE 0x16000000UL +#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */ + +/******************************************************************************* +* PERI +*******************************************************************************/ + +#define PERI_BASE 0x40000000UL +#define PERI ((PERI_Type*) PERI_BASE) /* 0x40000000 */ +#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40004000 */ +#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40004020 */ +#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40004040 */ +#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x40004060 */ +#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40004080 */ +#define PERI_GR5 ((PERI_GR_Type*) &PERI->GR[5]) /* 0x400040A0 */ +#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x400040C0 */ +#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40004120 */ +#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40008000 */ +#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40008400 */ +#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40008800 */ +#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40008C00 */ +#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40009000 */ +#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40009400 */ +#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40009800 */ +#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40009C00 */ +#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ +#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ +#define PERI_TR_GR10 ((PERI_TR_GR_Type*) &PERI->TR_GR[10]) /* 0x4000A800 */ +#define PERI_TR_GR11 ((PERI_TR_GR_Type*) &PERI->TR_GR[11]) /* 0x4000AC00 */ +#define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ +#define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ +#define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ +#define PERI_TR_1TO1_GR3 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[3]) /* 0x4000CC00 */ +#define PERI_TR_1TO1_GR4 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[4]) /* 0x4000D000 */ +#define PERI_TR_1TO1_GR5 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[5]) /* 0x4000D400 */ +#define PERI_TR_1TO1_GR6 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[6]) /* 0x4000D800 */ +#define PERI_TR_1TO1_GR7 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[7]) /* 0x4000DC00 */ +#define PERI_TR_1TO1_GR8 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[8]) /* 0x4000E000 */ + +/******************************************************************************* +* PERI_MS +*******************************************************************************/ + +#define PERI_MS_BASE 0x40010000UL +#define PERI_MS ((PERI_MS_Type*) PERI_MS_BASE) /* 0x40010000 */ +#define PERI_MS_PPU_PR0 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[0]) /* 0x40010000 */ +#define PERI_MS_PPU_PR1 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[1]) /* 0x40010040 */ +#define PERI_MS_PPU_PR2 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[2]) /* 0x40010080 */ +#define PERI_MS_PPU_PR3 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[3]) /* 0x400100C0 */ +#define PERI_MS_PPU_PR4 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[4]) /* 0x40010100 */ +#define PERI_MS_PPU_PR5 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[5]) /* 0x40010140 */ +#define PERI_MS_PPU_PR6 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[6]) /* 0x40010180 */ +#define PERI_MS_PPU_PR7 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[7]) /* 0x400101C0 */ +#define PERI_MS_PPU_FX_PERI_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[0]) /* 0x40010800 */ +#define PERI_MS_PPU_FX_PERI_GR0_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[1]) /* 0x40010840 */ +#define PERI_MS_PPU_FX_PERI_GR1_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[2]) /* 0x40010880 */ +#define PERI_MS_PPU_FX_PERI_GR2_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[3]) /* 0x400108C0 */ +#define PERI_MS_PPU_FX_PERI_GR3_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[4]) /* 0x40010900 */ +#define PERI_MS_PPU_FX_PERI_GR4_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[5]) /* 0x40010940 */ +#define PERI_MS_PPU_FX_PERI_GR5_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[6]) /* 0x40010980 */ +#define PERI_MS_PPU_FX_PERI_GR6_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[7]) /* 0x400109C0 */ +#define PERI_MS_PPU_FX_PERI_GR9_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[8]) /* 0x40010A00 */ +#define PERI_MS_PPU_FX_PERI_TR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[9]) /* 0x40010A40 */ +#define PERI_MS_PPU_FX_CRYPTO_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[10]) /* 0x40010A80 */ +#define PERI_MS_PPU_FX_CRYPTO_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[11]) /* 0x40010AC0 */ +#define PERI_MS_PPU_FX_CRYPTO_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[12]) /* 0x40010B00 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[13]) /* 0x40010B40 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[14]) /* 0x40010B80 */ +#define PERI_MS_PPU_FX_CRYPTO_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[15]) /* 0x40010BC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[16]) /* 0x40010C00 */ +#define PERI_MS_PPU_FX_CPUSS_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[17]) /* 0x40010C40 */ +#define PERI_MS_PPU_FX_CPUSS_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[18]) /* 0x40010C80 */ +#define PERI_MS_PPU_FX_CPUSS_CM0_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[19]) /* 0x40010CC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[20]) /* 0x40010D00 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[21]) /* 0x40010D40 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT1_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[22]) /* 0x40010D80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT0_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[23]) /* 0x40010DC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT1_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[24]) /* 0x40010E00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT2_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[25]) /* 0x40010E40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT3_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[26]) /* 0x40010E80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT4_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[27]) /* 0x40010EC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT5_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[28]) /* 0x40010F00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT6_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[29]) /* 0x40010F40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT7_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[30]) /* 0x40010F80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT8_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[31]) /* 0x40010FC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT9_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[32]) /* 0x40011000 */ +#define PERI_MS_PPU_FX_IPC_STRUCT10_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[33]) /* 0x40011040 */ +#define PERI_MS_PPU_FX_IPC_STRUCT11_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[34]) /* 0x40011080 */ +#define PERI_MS_PPU_FX_IPC_STRUCT12_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[35]) /* 0x400110C0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT13_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[36]) /* 0x40011100 */ +#define PERI_MS_PPU_FX_IPC_STRUCT14_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[37]) /* 0x40011140 */ +#define PERI_MS_PPU_FX_IPC_STRUCT15_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[38]) /* 0x40011180 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT0_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[39]) /* 0x400111C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT1_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[40]) /* 0x40011200 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT2_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[41]) /* 0x40011240 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT3_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[42]) /* 0x40011280 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT4_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[43]) /* 0x400112C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT5_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[44]) /* 0x40011300 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT6_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[45]) /* 0x40011340 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT7_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[46]) /* 0x40011380 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT8_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[47]) /* 0x400113C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT9_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[48]) /* 0x40011400 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT10_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[49]) /* 0x40011440 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT11_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[50]) /* 0x40011480 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT12_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[51]) /* 0x400114C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT13_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[52]) /* 0x40011500 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT14_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[53]) /* 0x40011540 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT15_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[54]) /* 0x40011580 */ +#define PERI_MS_PPU_FX_PROT_SMPU_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[55]) /* 0x400115C0 */ +#define PERI_MS_PPU_FX_PROT_MPU0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[56]) /* 0x40011600 */ +#define PERI_MS_PPU_FX_PROT_MPU14_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[57]) /* 0x40011640 */ +#define PERI_MS_PPU_FX_PROT_MPU15_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[58]) /* 0x40011680 */ +#define PERI_MS_PPU_FX_FLASHC_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[59]) /* 0x400116C0 */ +#define PERI_MS_PPU_FX_FLASHC_CMD ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[60]) /* 0x40011700 */ +#define PERI_MS_PPU_FX_FLASHC_DFT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[61]) /* 0x40011740 */ +#define PERI_MS_PPU_FX_FLASHC_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[62]) /* 0x40011780 */ +#define PERI_MS_PPU_FX_FLASHC_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[63]) /* 0x400117C0 */ +#define PERI_MS_PPU_FX_FLASHC_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[64]) /* 0x40011800 */ +#define PERI_MS_PPU_FX_FLASHC_DW0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[65]) /* 0x40011840 */ +#define PERI_MS_PPU_FX_FLASHC_DW1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[66]) /* 0x40011880 */ +#define PERI_MS_PPU_FX_FLASHC_DMAC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[67]) /* 0x400118C0 */ +#define PERI_MS_PPU_FX_FLASHC_FM ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[68]) /* 0x40011900 */ +#define PERI_MS_PPU_FX_SRSS_MAIN1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[69]) /* 0x40011940 */ +#define PERI_MS_PPU_FX_SRSS_MAIN2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[70]) /* 0x40011980 */ +#define PERI_MS_PPU_FX_WDT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[71]) /* 0x400119C0 */ +#define PERI_MS_PPU_FX_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[72]) /* 0x40011A00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[73]) /* 0x40011A40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[74]) /* 0x40011A80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[75]) /* 0x40011AC0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[76]) /* 0x40011B00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[77]) /* 0x40011B40 */ +#define PERI_MS_PPU_FX_BACKUP_BACKUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[78]) /* 0x40011B80 */ +#define PERI_MS_PPU_FX_DW0_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[79]) /* 0x40011BC0 */ +#define PERI_MS_PPU_FX_DW1_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[80]) /* 0x40011C00 */ +#define PERI_MS_PPU_FX_DW0_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[81]) /* 0x40011C40 */ +#define PERI_MS_PPU_FX_DW1_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[82]) /* 0x40011C80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[83]) /* 0x40011CC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[84]) /* 0x40011D00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[85]) /* 0x40011D40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[86]) /* 0x40011D80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[87]) /* 0x40011DC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[88]) /* 0x40011E00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[89]) /* 0x40011E40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[90]) /* 0x40011E80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[91]) /* 0x40011EC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[92]) /* 0x40011F00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[93]) /* 0x40011F40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[94]) /* 0x40011F80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[95]) /* 0x40011FC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[96]) /* 0x40012000 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[97]) /* 0x40012040 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[98]) /* 0x40012080 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[99]) /* 0x400120C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[100]) /* 0x40012100 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[101]) /* 0x40012140 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[102]) /* 0x40012180 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[103]) /* 0x400121C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[104]) /* 0x40012200 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[105]) /* 0x40012240 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[106]) /* 0x40012280 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[107]) /* 0x400122C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[108]) /* 0x40012300 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[109]) /* 0x40012340 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[110]) /* 0x40012380 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[111]) /* 0x400123C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT29_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[112]) /* 0x40012400 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[113]) /* 0x40012440 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[114]) /* 0x40012480 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[115]) /* 0x400124C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[116]) /* 0x40012500 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[117]) /* 0x40012540 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[118]) /* 0x40012580 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[119]) /* 0x400125C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[120]) /* 0x40012600 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[121]) /* 0x40012640 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[122]) /* 0x40012680 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[123]) /* 0x400126C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[124]) /* 0x40012700 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[125]) /* 0x40012740 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[126]) /* 0x40012780 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[127]) /* 0x400127C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[128]) /* 0x40012800 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[129]) /* 0x40012840 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[130]) /* 0x40012880 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[131]) /* 0x400128C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[132]) /* 0x40012900 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[133]) /* 0x40012940 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[134]) /* 0x40012980 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[135]) /* 0x400129C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[136]) /* 0x40012A00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[137]) /* 0x40012A40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[138]) /* 0x40012A80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[139]) /* 0x40012AC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[140]) /* 0x40012B00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[141]) /* 0x40012B40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT29_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[142]) /* 0x40012B80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT30_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[143]) /* 0x40012BC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT31_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[144]) /* 0x40012C00 */ +#define PERI_MS_PPU_FX_DMAC_TOP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[145]) /* 0x40012C40 */ +#define PERI_MS_PPU_FX_DMAC_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[146]) /* 0x40012C80 */ +#define PERI_MS_PPU_FX_DMAC_CH1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[147]) /* 0x40012CC0 */ +#define PERI_MS_PPU_FX_EFUSE_CTL ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[148]) /* 0x40012D00 */ +#define PERI_MS_PPU_FX_EFUSE_DATA ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[149]) /* 0x40012D40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[150]) /* 0x40012D80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[151]) /* 0x40012DC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[152]) /* 0x40012E00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[153]) /* 0x40012E40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[154]) /* 0x40012E80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[155]) /* 0x40012EC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[156]) /* 0x40012F00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[157]) /* 0x40012F40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[158]) /* 0x40012F80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[159]) /* 0x40012FC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[160]) /* 0x40013000 */ +#define PERI_MS_PPU_FX_HSIOM_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[161]) /* 0x40013040 */ +#define PERI_MS_PPU_FX_HSIOM_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[162]) /* 0x40013080 */ +#define PERI_MS_PPU_FX_HSIOM_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[163]) /* 0x400130C0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[164]) /* 0x40013100 */ +#define PERI_MS_PPU_FX_HSIOM_AMUX ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[165]) /* 0x40013140 */ +#define PERI_MS_PPU_FX_HSIOM_MON ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[166]) /* 0x40013180 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[167]) /* 0x400131C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[168]) /* 0x40013200 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[169]) /* 0x40013240 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[170]) /* 0x40013280 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[171]) /* 0x400132C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[172]) /* 0x40013300 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[173]) /* 0x40013340 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[174]) /* 0x40013380 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[175]) /* 0x400133C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[176]) /* 0x40013400 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[177]) /* 0x40013440 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[178]) /* 0x40013480 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[179]) /* 0x400134C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[180]) /* 0x40013500 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[181]) /* 0x40013540 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[182]) /* 0x40013580 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[183]) /* 0x400135C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[184]) /* 0x40013600 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[185]) /* 0x40013640 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[186]) /* 0x40013680 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[187]) /* 0x400136C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[188]) /* 0x40013700 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[189]) /* 0x40013740 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[190]) /* 0x40013780 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[191]) /* 0x400137C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[192]) /* 0x40013800 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[193]) /* 0x40013840 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[194]) /* 0x40013880 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[195]) /* 0x400138C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[196]) /* 0x40013900 */ +#define PERI_MS_PPU_FX_GPIO_GPIO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[197]) /* 0x40013940 */ +#define PERI_MS_PPU_FX_GPIO_TEST ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[198]) /* 0x40013980 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[199]) /* 0x400139C0 */ +#define PERI_MS_PPU_FX_LPCOMP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[200]) /* 0x40013A00 */ +#define PERI_MS_PPU_FX_CSD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[201]) /* 0x40013A40 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT0_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[202]) /* 0x40013A80 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT1_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[203]) /* 0x40013AC0 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT2_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[204]) /* 0x40013B00 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT3_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[205]) /* 0x40013B40 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT0_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[206]) /* 0x40013B80 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT1_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[207]) /* 0x40013BC0 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT2_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[208]) /* 0x40013C00 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT3_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[209]) /* 0x40013C40 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT4_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[210]) /* 0x40013C80 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT5_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[211]) /* 0x40013CC0 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT6_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[212]) /* 0x40013D00 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT7_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[213]) /* 0x40013D40 */ +#define PERI_MS_PPU_FX_LCD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[214]) /* 0x40013D80 */ +#define PERI_MS_PPU_FX_USBFS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[215]) /* 0x40013DC0 */ +#define PERI_MS_PPU_FX_SMIF0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[216]) /* 0x40013E00 */ +#define PERI_MS_PPU_FX_CANFD0_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[217]) /* 0x40013E40 */ +#define PERI_MS_PPU_FX_CANFD0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[218]) /* 0x40013E80 */ +#define PERI_MS_PPU_FX_CANFD0_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[219]) /* 0x40013EC0 */ +#define PERI_MS_PPU_FX_SCB0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[220]) /* 0x40013F00 */ +#define PERI_MS_PPU_FX_SCB1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[221]) /* 0x40013F40 */ +#define PERI_MS_PPU_FX_SCB2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[222]) /* 0x40013F80 */ +#define PERI_MS_PPU_FX_SCB4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[223]) /* 0x40013FC0 */ +#define PERI_MS_PPU_FX_SCB5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[224]) /* 0x40014000 */ +#define PERI_MS_PPU_FX_SCB6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[225]) /* 0x40014040 */ + +/******************************************************************************* +* CRYPTO +*******************************************************************************/ + +#define CRYPTO_BASE 0x40100000UL +#define CRYPTO ((CRYPTO_Type*) CRYPTO_BASE) /* 0x40100000 */ + +/******************************************************************************* +* CPUSS +*******************************************************************************/ + +#define CPUSS_BASE 0x40200000UL +#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40200000 */ + +/******************************************************************************* +* FAULT +*******************************************************************************/ + +#define FAULT_BASE 0x40210000UL +#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40210000 */ +#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40210000 */ +#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40210100 */ + +/******************************************************************************* +* IPC +*******************************************************************************/ + +#define IPC_BASE 0x40220000UL +#define IPC ((IPC_Type*) IPC_BASE) /* 0x40220000 */ +#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40220000 */ +#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40220020 */ +#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40220040 */ +#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40220060 */ +#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40220080 */ +#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402200A0 */ +#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402200C0 */ +#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402200E0 */ +#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40220100 */ +#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40220120 */ +#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40220140 */ +#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40220160 */ +#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40220180 */ +#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402201A0 */ +#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402201C0 */ +#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402201E0 */ +#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40221000 */ +#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40221020 */ +#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40221040 */ +#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40221060 */ +#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40221080 */ +#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402210A0 */ +#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402210C0 */ +#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402210E0 */ +#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40221100 */ +#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40221120 */ +#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40221140 */ +#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40221160 */ +#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40221180 */ +#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402211A0 */ +#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402211C0 */ +#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402211E0 */ + +/******************************************************************************* +* PROT +*******************************************************************************/ + +#define PROT_BASE 0x40230000UL +#define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ +#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ +#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ +#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402320C0 */ +#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40232100 */ +#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40232140 */ +#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40232180 */ +#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402321C0 */ +#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40232200 */ +#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40232240 */ +#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40232280 */ +#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402322C0 */ +#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40232300 */ +#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ +#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ +#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ + +/******************************************************************************* +* FLASHC +*******************************************************************************/ + +#define FLASHC_BASE 0x40240000UL +#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40240000 */ +#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4024F000 */ + +/******************************************************************************* +* SRSS +*******************************************************************************/ + +#define SRSS_BASE 0x40260000UL +#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ +#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */ +#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */ + +/******************************************************************************* +* BACKUP +*******************************************************************************/ + +#define BACKUP_BASE 0x40270000UL +#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ + +/******************************************************************************* +* DW +*******************************************************************************/ + +#define DW0_BASE 0x40280000UL +#define DW1_BASE 0x40290000UL +#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ +#define DW1 ((DW_Type*) DW1_BASE) /* 0x40290000 */ +#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40288000 */ +#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40288040 */ +#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40288080 */ +#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x402880C0 */ +#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40288100 */ +#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x40288140 */ +#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x40288180 */ +#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402881C0 */ +#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40288200 */ +#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40288240 */ +#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40288280 */ +#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x402882C0 */ +#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40288300 */ +#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x40288340 */ +#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x40288380 */ +#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402883C0 */ +#define DW0_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[16]) /* 0x40288400 */ +#define DW0_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[17]) /* 0x40288440 */ +#define DW0_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[18]) /* 0x40288480 */ +#define DW0_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[19]) /* 0x402884C0 */ +#define DW0_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[20]) /* 0x40288500 */ +#define DW0_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[21]) /* 0x40288540 */ +#define DW0_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[22]) /* 0x40288580 */ +#define DW0_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[23]) /* 0x402885C0 */ +#define DW0_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[24]) /* 0x40288600 */ +#define DW0_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[25]) /* 0x40288640 */ +#define DW0_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[26]) /* 0x40288680 */ +#define DW0_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[27]) /* 0x402886C0 */ +#define DW0_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[28]) /* 0x40288700 */ +#define DW0_CH_STRUCT29 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[29]) /* 0x40288740 */ +#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40298000 */ +#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40298040 */ +#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40298080 */ +#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x402980C0 */ +#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40298100 */ +#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x40298140 */ +#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x40298180 */ +#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402981C0 */ +#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40298200 */ +#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40298240 */ +#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40298280 */ +#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x402982C0 */ +#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40298300 */ +#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x40298340 */ +#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x40298380 */ +#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402983C0 */ +#define DW1_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[16]) /* 0x40298400 */ +#define DW1_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[17]) /* 0x40298440 */ +#define DW1_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[18]) /* 0x40298480 */ +#define DW1_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[19]) /* 0x402984C0 */ +#define DW1_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[20]) /* 0x40298500 */ +#define DW1_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[21]) /* 0x40298540 */ +#define DW1_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[22]) /* 0x40298580 */ +#define DW1_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[23]) /* 0x402985C0 */ +#define DW1_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[24]) /* 0x40298600 */ +#define DW1_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[25]) /* 0x40298640 */ +#define DW1_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[26]) /* 0x40298680 */ +#define DW1_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[27]) /* 0x402986C0 */ +#define DW1_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[28]) /* 0x40298700 */ +#define DW1_CH_STRUCT29 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[29]) /* 0x40298740 */ +#define DW1_CH_STRUCT30 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[30]) /* 0x40298780 */ +#define DW1_CH_STRUCT31 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[31]) /* 0x402987C0 */ + +/******************************************************************************* +* DMAC +*******************************************************************************/ + +#define DMAC_BASE 0x402A0000UL +#define DMAC ((DMAC_Type*) DMAC_BASE) /* 0x402A0000 */ +#define DMAC_CH0 ((DMAC_CH_Type*) &DMAC->CH[0]) /* 0x402A1000 */ +#define DMAC_CH1 ((DMAC_CH_Type*) &DMAC->CH[1]) /* 0x402A1100 */ + +/******************************************************************************* +* EFUSE +*******************************************************************************/ + +#define EFUSE_BASE 0x402C0000UL +#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ + +/******************************************************************************* +* HSIOM +*******************************************************************************/ + +#define HSIOM_BASE 0x40300000UL +#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40300000 */ +#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40300000 */ +#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40300010 */ +#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40300020 */ +#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40300030 */ +#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40300040 */ +#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40300050 */ +#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40300060 */ +#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40300070 */ +#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40300080 */ +#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40300090 */ +#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403000A0 */ +#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403000B0 */ +#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403000C0 */ +#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403000D0 */ +#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403000E0 */ + +/******************************************************************************* +* GPIO +*******************************************************************************/ + +#define GPIO_BASE 0x40310000UL +#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40310000 */ +#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40310000 */ +#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40310080 */ +#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40310100 */ +#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40310180 */ +#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40310200 */ +#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40310280 */ +#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40310300 */ +#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40310380 */ +#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40310400 */ +#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40310480 */ +#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40310500 */ +#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40310580 */ +#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40310600 */ +#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40310680 */ +#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40310700 */ + +/******************************************************************************* +* SMARTIO +*******************************************************************************/ + +#define SMARTIO_BASE 0x40320000UL +#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40320000 */ +#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40320900 */ + +/******************************************************************************* +* LPCOMP +*******************************************************************************/ + +#define LPCOMP_BASE 0x40350000UL +#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */ + +/******************************************************************************* +* CSD +*******************************************************************************/ + +#define CSD0_BASE 0x40360000UL +#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */ + +/******************************************************************************* +* TCPWM +*******************************************************************************/ + +#define TCPWM0_BASE 0x40380000UL +#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM0_GRP0 ((TCPWM_GRP_Type*) &TCPWM0->GRP[0]) /* 0x40380000 */ +#define TCPWM0_GRP1 ((TCPWM_GRP_Type*) &TCPWM0->GRP[1]) /* 0x40388000 */ +#define TCPWM0_GRP0_CNT0 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[0]) /* 0x40380000 */ +#define TCPWM0_GRP0_CNT1 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[1]) /* 0x40380080 */ +#define TCPWM0_GRP0_CNT2 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[2]) /* 0x40380100 */ +#define TCPWM0_GRP0_CNT3 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[3]) /* 0x40380180 */ +#define TCPWM0_GRP1_CNT0 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[0]) /* 0x40388000 */ +#define TCPWM0_GRP1_CNT1 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[1]) /* 0x40388080 */ +#define TCPWM0_GRP1_CNT2 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[2]) /* 0x40388100 */ +#define TCPWM0_GRP1_CNT3 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[3]) /* 0x40388180 */ +#define TCPWM0_GRP1_CNT4 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[4]) /* 0x40388200 */ +#define TCPWM0_GRP1_CNT5 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[5]) /* 0x40388280 */ +#define TCPWM0_GRP1_CNT6 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[6]) /* 0x40388300 */ +#define TCPWM0_GRP1_CNT7 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[7]) /* 0x40388380 */ + +/******************************************************************************* +* LCD +*******************************************************************************/ + +#define LCD0_BASE 0x403B0000UL +#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ + +/******************************************************************************* +* SMIF +*******************************************************************************/ + +#define SMIF0_BASE 0x40420000UL +#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ +#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ +#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ +#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ + +/******************************************************************************* +* CANFD +*******************************************************************************/ + +#define CANFD0_BASE 0x40520000UL +#define CANFD0 ((CANFD_Type*) CANFD0_BASE) /* 0x40520000 */ +#define CANFD0_CH0 ((CANFD_CH_Type*) &CANFD0->CH[0]) /* 0x40520000 */ +#define CANFD0_CH0_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[0].M_TTCAN) /* 0x40520000 */ + +/******************************************************************************* +* SCB +*******************************************************************************/ + +#define SCB0_BASE 0x40600000UL +#define SCB1_BASE 0x40610000UL +#define SCB2_BASE 0x40620000UL +#define SCB4_BASE 0x40640000UL +#define SCB5_BASE 0x40650000UL +#define SCB6_BASE 0x40660000UL +#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40600000 */ +#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40610000 */ +#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40620000 */ +#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40640000 */ +#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40650000 */ +#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40660000 */ + +/******************************************************************************* +* CTBM +*******************************************************************************/ + +#define CTBM0_BASE 0x40900000UL +#define CTBM0 ((CTBM_Type*) CTBM0_BASE) /* 0x40900000 */ + +/******************************************************************************* +* CTDAC +*******************************************************************************/ + +#define CTDAC0_BASE 0x40940000UL +#define CTDAC0 ((CTDAC_Type*) CTDAC0_BASE) /* 0x40940000 */ + +/******************************************************************************* +* SAR +*******************************************************************************/ + +#define SAR0_BASE 0x409B0000UL +#define SAR1_BASE 0x409C0000UL +#define SAR0 ((SAR_Type*) SAR0_BASE) /* 0x409B0000 */ +#define SAR1 ((SAR_Type*) SAR1_BASE) /* 0x409C0000 */ + +/******************************************************************************* +* PASS +*******************************************************************************/ + +#define PASS_BASE 0x409F0000UL +#define PASS ((PASS_Type*) PASS_BASE) /* 0x409F0000 */ +#define PASS_TIMER ((PASS_TIMER_Type*) &PASS->TIMER) /* 0x409F0100 */ +#define PASS_LPOSC ((PASS_LPOSC_Type*) &PASS->LPOSC) /* 0x409F0200 */ +#define PASS_FIFO0 ((PASS_FIFO_Type*) &PASS->FIFO[0]) /* 0x409F0300 */ +#define PASS_FIFO1 ((PASS_FIFO_Type*) &PASS->FIFO[1]) /* 0x409F0400 */ +#define PASS_AREFV2 ((PASS_AREFV2_Type*) &PASS->AREFV2) /* 0x409F0E00 */ + +/** \} CY8C6144AZI-S4F82 */ + +#endif /* _CY8C6144AZI_S4F82_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6144azi_s4f83.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6144azi_s4f83.h new file mode 100644 index 0000000000..18c8aeb1d1 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6144azi_s4f83.h @@ -0,0 +1,980 @@ +/***************************************************************************//** +* \file cy8c6144azi_s4f83.h +* +* \brief +* CY8C6144AZI-S4F83 device header +* +* \note +* Generator version: 1.6.0.225 +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CY8C6144AZI_S4F83_H_ +#define _CY8C6144AZI_S4F83_H_ + +/** +* \addtogroup group_device CY8C6144AZI-S4F83 +* \{ +*/ + +/** +* \addtogroup Configuration_of_CMSIS +* \{ +*/ + +/******************************************************************************* +* Interrupt Number Definition +*******************************************************************************/ + +typedef enum { + /* ARM Cortex-M4 Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C6144AZI-S4F83 Peripheral Interrupt Numbers */ + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_6_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #6 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + pass_interrupt_sar_0_IRQn = 39, /*!< 39 [DeepSleep] SAR ADC0 interrupt */ + pass_interrupt_sar_1_IRQn = 40, /*!< 40 [DeepSleep] SAR ADC1 interrupt */ + pass_interrupt_ctb_IRQn = 41, /*!< 41 [DeepSleep] individual interrupt per CTB */ + pass_interrupt_fifo_0_IRQn = 43, /*!< 43 [DeepSleep] PASS FIFO0 */ + pass_interrupt_fifo_1_IRQn = 44, /*!< 44 [DeepSleep] PASS FIFO1 */ + scb_0_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #2 */ + scb_4_interrupt_IRQn = 49, /*!< 49 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 50, /*!< 50 [Active] Serial Communication Block #5 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_0_interrupts_256_IRQn = 131, /*!< 131 [Active] TCPWM #0, Counter #256 */ + tcpwm_0_interrupts_257_IRQn = 132, /*!< 132 [Active] TCPWM #0, Counter #257 */ + tcpwm_0_interrupts_258_IRQn = 133, /*!< 133 [Active] TCPWM #0, Counter #258 */ + tcpwm_0_interrupts_259_IRQn = 134, /*!< 134 [Active] TCPWM #0, Counter #259 */ + tcpwm_0_interrupts_260_IRQn = 135, /*!< 135 [Active] TCPWM #0, Counter #260 */ + tcpwm_0_interrupts_261_IRQn = 136, /*!< 136 [Active] TCPWM #0, Counter #261 */ + tcpwm_0_interrupts_262_IRQn = 137, /*!< 137 [Active] TCPWM #0, Counter #262 */ + tcpwm_0_interrupts_263_IRQn = 138, /*!< 138 [Active] TCPWM #0, Counter #263 */ + pass_interrupt_dacs_IRQn = 146, /*!< 146 [Active] Consolidated interrrupt for all DACs */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + canfd_0_interrupt0_IRQn = 168, /*!< 168 [Active] Can #0, Consolidated interrupt #0 */ + canfd_0_interrupts0_0_IRQn = 169, /*!< 169 [Active] CAN #0, Interrupt #0, Channel #0 */ + canfd_0_interrupts1_0_IRQn = 170, /*!< 170 [Active] CAN #0, Interrupt #1, Channel #0 */ + cpuss_interrupts_dw1_29_IRQn = 171, /*!< 171 [Active] CPUSS DataWire #1, Channel #29 */ + cpuss_interrupts_dw1_30_IRQn = 172, /*!< 172 [Active] CPUSS DataWire #1, Channel #30 */ + cpuss_interrupts_dw1_31_IRQn = 173, /*!< 173 [Active] CPUSS DataWire #1, Channel #31 */ + cpuss_interrupts_dw0_29_IRQn = 174, /*!< 174 [Active] CPUSS DataWire #0, Channel #29 */ + unconnected_IRQn = 240 /*!< 240 Unconnected */ +} IRQn_Type; + + +/******************************************************************************* +* Processor and Core Peripheral Section +*******************************************************************************/ + +/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __CM0P_PRESENT 0 /*!< CM0P present or not */ +#define __DTCM_PRESENT 0 /*!< DTCM present or not */ +#define __ICACHE_PRESENT 0 /*!< ICACHE present or not */ +#define __DCACHE_PRESENT 0 /*!< DCACHE present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + + +/* Memory Blocks */ +#define CY_ROM_BASE 0x00000000UL +#define CY_ROM_SIZE 0x00010000UL +#define CY_SRAM_BASE 0x08000000UL +#define CY_SRAM_SIZE 0x00020000UL +#define CY_FLASH_BASE 0x10000000UL +#define CY_FLASH_SIZE 0x00040000UL +#define CY_EM_EEPROM_BASE 0x14000000UL +#define CY_EM_EEPROM_SIZE 0x00000000UL +#define CY_SFLASH_BASE 0x16000000UL +#define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL +#define CY_EFUSE_BASE 0x402C0800UL +#define CY_EFUSE_SIZE 0x00000200UL +#define CY_CAN0MRAM_BASE 0x40530000UL +#define CY_CAN0MRAM_SIZE 0x00010000UL + +#include "system_psoc6.h" /*!< PSoC 6 System */ + +/* IP List */ +#define CY_IP_MXTTCANFD 1u +#define CY_IP_MXTTCANFD_INSTANCES 1u +#define CY_IP_MXTTCANFD_VERSION 1u +#define CY_IP_M4CPUSS 1u +#define CY_IP_M4CPUSS_INSTANCES 1u +#define CY_IP_M4CPUSS_VERSION 2u +#define CY_IP_M4CPUSS_DMAC 1u +#define CY_IP_M4CPUSS_DMAC_INSTANCES 1u +#define CY_IP_M4CPUSS_DMAC_VERSION 2u +#define CY_IP_M4CPUSS_DMA 1u +#define CY_IP_M4CPUSS_DMA_INSTANCES 2u +#define CY_IP_M4CPUSS_DMA_VERSION 2u +#define CY_IP_MXCRYPTO 1u +#define CY_IP_MXCRYPTO_INSTANCES 1u +#define CY_IP_MXCRYPTO_VERSION 2u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 2u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 6u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u + +#include "psoc6_04_config.h" +#include "gpio_psoc6_04_80_tqfp.h" + +#define CY_DEVICE_PSOC6A256K +#define CY_SILICON_ID 0xEACF110EUL +#define CY_HF_CLK_MAX_FREQ 150000000UL + +#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL + +/******************************************************************************* +* SFLASH +*******************************************************************************/ + +#define SFLASH_BASE 0x16000000UL +#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */ + +/******************************************************************************* +* PERI +*******************************************************************************/ + +#define PERI_BASE 0x40000000UL +#define PERI ((PERI_Type*) PERI_BASE) /* 0x40000000 */ +#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40004000 */ +#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40004020 */ +#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40004040 */ +#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x40004060 */ +#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40004080 */ +#define PERI_GR5 ((PERI_GR_Type*) &PERI->GR[5]) /* 0x400040A0 */ +#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x400040C0 */ +#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40004120 */ +#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40008000 */ +#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40008400 */ +#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40008800 */ +#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40008C00 */ +#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40009000 */ +#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40009400 */ +#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40009800 */ +#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40009C00 */ +#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ +#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ +#define PERI_TR_GR10 ((PERI_TR_GR_Type*) &PERI->TR_GR[10]) /* 0x4000A800 */ +#define PERI_TR_GR11 ((PERI_TR_GR_Type*) &PERI->TR_GR[11]) /* 0x4000AC00 */ +#define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ +#define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ +#define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ +#define PERI_TR_1TO1_GR3 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[3]) /* 0x4000CC00 */ +#define PERI_TR_1TO1_GR4 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[4]) /* 0x4000D000 */ +#define PERI_TR_1TO1_GR5 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[5]) /* 0x4000D400 */ +#define PERI_TR_1TO1_GR6 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[6]) /* 0x4000D800 */ +#define PERI_TR_1TO1_GR7 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[7]) /* 0x4000DC00 */ +#define PERI_TR_1TO1_GR8 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[8]) /* 0x4000E000 */ + +/******************************************************************************* +* PERI_MS +*******************************************************************************/ + +#define PERI_MS_BASE 0x40010000UL +#define PERI_MS ((PERI_MS_Type*) PERI_MS_BASE) /* 0x40010000 */ +#define PERI_MS_PPU_PR0 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[0]) /* 0x40010000 */ +#define PERI_MS_PPU_PR1 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[1]) /* 0x40010040 */ +#define PERI_MS_PPU_PR2 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[2]) /* 0x40010080 */ +#define PERI_MS_PPU_PR3 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[3]) /* 0x400100C0 */ +#define PERI_MS_PPU_PR4 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[4]) /* 0x40010100 */ +#define PERI_MS_PPU_PR5 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[5]) /* 0x40010140 */ +#define PERI_MS_PPU_PR6 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[6]) /* 0x40010180 */ +#define PERI_MS_PPU_PR7 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[7]) /* 0x400101C0 */ +#define PERI_MS_PPU_FX_PERI_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[0]) /* 0x40010800 */ +#define PERI_MS_PPU_FX_PERI_GR0_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[1]) /* 0x40010840 */ +#define PERI_MS_PPU_FX_PERI_GR1_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[2]) /* 0x40010880 */ +#define PERI_MS_PPU_FX_PERI_GR2_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[3]) /* 0x400108C0 */ +#define PERI_MS_PPU_FX_PERI_GR3_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[4]) /* 0x40010900 */ +#define PERI_MS_PPU_FX_PERI_GR4_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[5]) /* 0x40010940 */ +#define PERI_MS_PPU_FX_PERI_GR5_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[6]) /* 0x40010980 */ +#define PERI_MS_PPU_FX_PERI_GR6_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[7]) /* 0x400109C0 */ +#define PERI_MS_PPU_FX_PERI_GR9_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[8]) /* 0x40010A00 */ +#define PERI_MS_PPU_FX_PERI_TR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[9]) /* 0x40010A40 */ +#define PERI_MS_PPU_FX_CRYPTO_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[10]) /* 0x40010A80 */ +#define PERI_MS_PPU_FX_CRYPTO_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[11]) /* 0x40010AC0 */ +#define PERI_MS_PPU_FX_CRYPTO_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[12]) /* 0x40010B00 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[13]) /* 0x40010B40 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[14]) /* 0x40010B80 */ +#define PERI_MS_PPU_FX_CRYPTO_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[15]) /* 0x40010BC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[16]) /* 0x40010C00 */ +#define PERI_MS_PPU_FX_CPUSS_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[17]) /* 0x40010C40 */ +#define PERI_MS_PPU_FX_CPUSS_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[18]) /* 0x40010C80 */ +#define PERI_MS_PPU_FX_CPUSS_CM0_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[19]) /* 0x40010CC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[20]) /* 0x40010D00 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[21]) /* 0x40010D40 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT1_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[22]) /* 0x40010D80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT0_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[23]) /* 0x40010DC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT1_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[24]) /* 0x40010E00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT2_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[25]) /* 0x40010E40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT3_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[26]) /* 0x40010E80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT4_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[27]) /* 0x40010EC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT5_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[28]) /* 0x40010F00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT6_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[29]) /* 0x40010F40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT7_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[30]) /* 0x40010F80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT8_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[31]) /* 0x40010FC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT9_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[32]) /* 0x40011000 */ +#define PERI_MS_PPU_FX_IPC_STRUCT10_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[33]) /* 0x40011040 */ +#define PERI_MS_PPU_FX_IPC_STRUCT11_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[34]) /* 0x40011080 */ +#define PERI_MS_PPU_FX_IPC_STRUCT12_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[35]) /* 0x400110C0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT13_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[36]) /* 0x40011100 */ +#define PERI_MS_PPU_FX_IPC_STRUCT14_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[37]) /* 0x40011140 */ +#define PERI_MS_PPU_FX_IPC_STRUCT15_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[38]) /* 0x40011180 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT0_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[39]) /* 0x400111C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT1_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[40]) /* 0x40011200 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT2_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[41]) /* 0x40011240 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT3_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[42]) /* 0x40011280 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT4_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[43]) /* 0x400112C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT5_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[44]) /* 0x40011300 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT6_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[45]) /* 0x40011340 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT7_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[46]) /* 0x40011380 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT8_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[47]) /* 0x400113C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT9_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[48]) /* 0x40011400 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT10_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[49]) /* 0x40011440 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT11_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[50]) /* 0x40011480 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT12_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[51]) /* 0x400114C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT13_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[52]) /* 0x40011500 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT14_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[53]) /* 0x40011540 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT15_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[54]) /* 0x40011580 */ +#define PERI_MS_PPU_FX_PROT_SMPU_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[55]) /* 0x400115C0 */ +#define PERI_MS_PPU_FX_PROT_MPU0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[56]) /* 0x40011600 */ +#define PERI_MS_PPU_FX_PROT_MPU14_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[57]) /* 0x40011640 */ +#define PERI_MS_PPU_FX_PROT_MPU15_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[58]) /* 0x40011680 */ +#define PERI_MS_PPU_FX_FLASHC_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[59]) /* 0x400116C0 */ +#define PERI_MS_PPU_FX_FLASHC_CMD ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[60]) /* 0x40011700 */ +#define PERI_MS_PPU_FX_FLASHC_DFT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[61]) /* 0x40011740 */ +#define PERI_MS_PPU_FX_FLASHC_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[62]) /* 0x40011780 */ +#define PERI_MS_PPU_FX_FLASHC_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[63]) /* 0x400117C0 */ +#define PERI_MS_PPU_FX_FLASHC_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[64]) /* 0x40011800 */ +#define PERI_MS_PPU_FX_FLASHC_DW0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[65]) /* 0x40011840 */ +#define PERI_MS_PPU_FX_FLASHC_DW1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[66]) /* 0x40011880 */ +#define PERI_MS_PPU_FX_FLASHC_DMAC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[67]) /* 0x400118C0 */ +#define PERI_MS_PPU_FX_FLASHC_FM ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[68]) /* 0x40011900 */ +#define PERI_MS_PPU_FX_SRSS_MAIN1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[69]) /* 0x40011940 */ +#define PERI_MS_PPU_FX_SRSS_MAIN2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[70]) /* 0x40011980 */ +#define PERI_MS_PPU_FX_WDT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[71]) /* 0x400119C0 */ +#define PERI_MS_PPU_FX_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[72]) /* 0x40011A00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[73]) /* 0x40011A40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[74]) /* 0x40011A80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[75]) /* 0x40011AC0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[76]) /* 0x40011B00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[77]) /* 0x40011B40 */ +#define PERI_MS_PPU_FX_BACKUP_BACKUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[78]) /* 0x40011B80 */ +#define PERI_MS_PPU_FX_DW0_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[79]) /* 0x40011BC0 */ +#define PERI_MS_PPU_FX_DW1_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[80]) /* 0x40011C00 */ +#define PERI_MS_PPU_FX_DW0_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[81]) /* 0x40011C40 */ +#define PERI_MS_PPU_FX_DW1_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[82]) /* 0x40011C80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[83]) /* 0x40011CC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[84]) /* 0x40011D00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[85]) /* 0x40011D40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[86]) /* 0x40011D80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[87]) /* 0x40011DC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[88]) /* 0x40011E00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[89]) /* 0x40011E40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[90]) /* 0x40011E80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[91]) /* 0x40011EC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[92]) /* 0x40011F00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[93]) /* 0x40011F40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[94]) /* 0x40011F80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[95]) /* 0x40011FC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[96]) /* 0x40012000 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[97]) /* 0x40012040 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[98]) /* 0x40012080 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[99]) /* 0x400120C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[100]) /* 0x40012100 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[101]) /* 0x40012140 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[102]) /* 0x40012180 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[103]) /* 0x400121C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[104]) /* 0x40012200 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[105]) /* 0x40012240 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[106]) /* 0x40012280 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[107]) /* 0x400122C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[108]) /* 0x40012300 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[109]) /* 0x40012340 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[110]) /* 0x40012380 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[111]) /* 0x400123C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT29_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[112]) /* 0x40012400 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[113]) /* 0x40012440 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[114]) /* 0x40012480 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[115]) /* 0x400124C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[116]) /* 0x40012500 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[117]) /* 0x40012540 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[118]) /* 0x40012580 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[119]) /* 0x400125C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[120]) /* 0x40012600 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[121]) /* 0x40012640 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[122]) /* 0x40012680 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[123]) /* 0x400126C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[124]) /* 0x40012700 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[125]) /* 0x40012740 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[126]) /* 0x40012780 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[127]) /* 0x400127C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[128]) /* 0x40012800 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[129]) /* 0x40012840 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[130]) /* 0x40012880 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[131]) /* 0x400128C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[132]) /* 0x40012900 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[133]) /* 0x40012940 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[134]) /* 0x40012980 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[135]) /* 0x400129C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[136]) /* 0x40012A00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[137]) /* 0x40012A40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[138]) /* 0x40012A80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[139]) /* 0x40012AC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[140]) /* 0x40012B00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[141]) /* 0x40012B40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT29_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[142]) /* 0x40012B80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT30_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[143]) /* 0x40012BC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT31_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[144]) /* 0x40012C00 */ +#define PERI_MS_PPU_FX_DMAC_TOP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[145]) /* 0x40012C40 */ +#define PERI_MS_PPU_FX_DMAC_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[146]) /* 0x40012C80 */ +#define PERI_MS_PPU_FX_DMAC_CH1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[147]) /* 0x40012CC0 */ +#define PERI_MS_PPU_FX_EFUSE_CTL ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[148]) /* 0x40012D00 */ +#define PERI_MS_PPU_FX_EFUSE_DATA ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[149]) /* 0x40012D40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[150]) /* 0x40012D80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[151]) /* 0x40012DC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[152]) /* 0x40012E00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[153]) /* 0x40012E40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[154]) /* 0x40012E80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[155]) /* 0x40012EC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[156]) /* 0x40012F00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[157]) /* 0x40012F40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[158]) /* 0x40012F80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[159]) /* 0x40012FC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[160]) /* 0x40013000 */ +#define PERI_MS_PPU_FX_HSIOM_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[161]) /* 0x40013040 */ +#define PERI_MS_PPU_FX_HSIOM_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[162]) /* 0x40013080 */ +#define PERI_MS_PPU_FX_HSIOM_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[163]) /* 0x400130C0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[164]) /* 0x40013100 */ +#define PERI_MS_PPU_FX_HSIOM_AMUX ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[165]) /* 0x40013140 */ +#define PERI_MS_PPU_FX_HSIOM_MON ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[166]) /* 0x40013180 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[167]) /* 0x400131C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[168]) /* 0x40013200 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[169]) /* 0x40013240 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[170]) /* 0x40013280 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[171]) /* 0x400132C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[172]) /* 0x40013300 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[173]) /* 0x40013340 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[174]) /* 0x40013380 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[175]) /* 0x400133C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[176]) /* 0x40013400 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[177]) /* 0x40013440 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[178]) /* 0x40013480 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[179]) /* 0x400134C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[180]) /* 0x40013500 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[181]) /* 0x40013540 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[182]) /* 0x40013580 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[183]) /* 0x400135C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[184]) /* 0x40013600 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[185]) /* 0x40013640 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[186]) /* 0x40013680 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[187]) /* 0x400136C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[188]) /* 0x40013700 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[189]) /* 0x40013740 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[190]) /* 0x40013780 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[191]) /* 0x400137C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[192]) /* 0x40013800 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[193]) /* 0x40013840 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[194]) /* 0x40013880 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[195]) /* 0x400138C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[196]) /* 0x40013900 */ +#define PERI_MS_PPU_FX_GPIO_GPIO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[197]) /* 0x40013940 */ +#define PERI_MS_PPU_FX_GPIO_TEST ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[198]) /* 0x40013980 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[199]) /* 0x400139C0 */ +#define PERI_MS_PPU_FX_LPCOMP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[200]) /* 0x40013A00 */ +#define PERI_MS_PPU_FX_CSD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[201]) /* 0x40013A40 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT0_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[202]) /* 0x40013A80 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT1_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[203]) /* 0x40013AC0 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT2_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[204]) /* 0x40013B00 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT3_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[205]) /* 0x40013B40 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT0_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[206]) /* 0x40013B80 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT1_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[207]) /* 0x40013BC0 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT2_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[208]) /* 0x40013C00 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT3_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[209]) /* 0x40013C40 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT4_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[210]) /* 0x40013C80 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT5_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[211]) /* 0x40013CC0 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT6_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[212]) /* 0x40013D00 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT7_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[213]) /* 0x40013D40 */ +#define PERI_MS_PPU_FX_LCD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[214]) /* 0x40013D80 */ +#define PERI_MS_PPU_FX_USBFS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[215]) /* 0x40013DC0 */ +#define PERI_MS_PPU_FX_SMIF0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[216]) /* 0x40013E00 */ +#define PERI_MS_PPU_FX_CANFD0_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[217]) /* 0x40013E40 */ +#define PERI_MS_PPU_FX_CANFD0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[218]) /* 0x40013E80 */ +#define PERI_MS_PPU_FX_CANFD0_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[219]) /* 0x40013EC0 */ +#define PERI_MS_PPU_FX_SCB0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[220]) /* 0x40013F00 */ +#define PERI_MS_PPU_FX_SCB1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[221]) /* 0x40013F40 */ +#define PERI_MS_PPU_FX_SCB2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[222]) /* 0x40013F80 */ +#define PERI_MS_PPU_FX_SCB4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[223]) /* 0x40013FC0 */ +#define PERI_MS_PPU_FX_SCB5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[224]) /* 0x40014000 */ +#define PERI_MS_PPU_FX_SCB6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[225]) /* 0x40014040 */ + +/******************************************************************************* +* CRYPTO +*******************************************************************************/ + +#define CRYPTO_BASE 0x40100000UL +#define CRYPTO ((CRYPTO_Type*) CRYPTO_BASE) /* 0x40100000 */ + +/******************************************************************************* +* CPUSS +*******************************************************************************/ + +#define CPUSS_BASE 0x40200000UL +#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40200000 */ + +/******************************************************************************* +* FAULT +*******************************************************************************/ + +#define FAULT_BASE 0x40210000UL +#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40210000 */ +#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40210000 */ +#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40210100 */ + +/******************************************************************************* +* IPC +*******************************************************************************/ + +#define IPC_BASE 0x40220000UL +#define IPC ((IPC_Type*) IPC_BASE) /* 0x40220000 */ +#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40220000 */ +#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40220020 */ +#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40220040 */ +#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40220060 */ +#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40220080 */ +#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402200A0 */ +#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402200C0 */ +#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402200E0 */ +#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40220100 */ +#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40220120 */ +#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40220140 */ +#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40220160 */ +#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40220180 */ +#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402201A0 */ +#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402201C0 */ +#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402201E0 */ +#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40221000 */ +#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40221020 */ +#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40221040 */ +#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40221060 */ +#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40221080 */ +#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402210A0 */ +#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402210C0 */ +#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402210E0 */ +#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40221100 */ +#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40221120 */ +#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40221140 */ +#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40221160 */ +#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40221180 */ +#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402211A0 */ +#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402211C0 */ +#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402211E0 */ + +/******************************************************************************* +* PROT +*******************************************************************************/ + +#define PROT_BASE 0x40230000UL +#define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ +#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ +#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ +#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402320C0 */ +#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40232100 */ +#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40232140 */ +#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40232180 */ +#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402321C0 */ +#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40232200 */ +#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40232240 */ +#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40232280 */ +#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402322C0 */ +#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40232300 */ +#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ +#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ +#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ + +/******************************************************************************* +* FLASHC +*******************************************************************************/ + +#define FLASHC_BASE 0x40240000UL +#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40240000 */ +#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4024F000 */ + +/******************************************************************************* +* SRSS +*******************************************************************************/ + +#define SRSS_BASE 0x40260000UL +#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ +#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */ +#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */ + +/******************************************************************************* +* BACKUP +*******************************************************************************/ + +#define BACKUP_BASE 0x40270000UL +#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ + +/******************************************************************************* +* DW +*******************************************************************************/ + +#define DW0_BASE 0x40280000UL +#define DW1_BASE 0x40290000UL +#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ +#define DW1 ((DW_Type*) DW1_BASE) /* 0x40290000 */ +#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40288000 */ +#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40288040 */ +#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40288080 */ +#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x402880C0 */ +#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40288100 */ +#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x40288140 */ +#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x40288180 */ +#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402881C0 */ +#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40288200 */ +#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40288240 */ +#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40288280 */ +#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x402882C0 */ +#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40288300 */ +#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x40288340 */ +#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x40288380 */ +#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402883C0 */ +#define DW0_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[16]) /* 0x40288400 */ +#define DW0_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[17]) /* 0x40288440 */ +#define DW0_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[18]) /* 0x40288480 */ +#define DW0_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[19]) /* 0x402884C0 */ +#define DW0_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[20]) /* 0x40288500 */ +#define DW0_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[21]) /* 0x40288540 */ +#define DW0_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[22]) /* 0x40288580 */ +#define DW0_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[23]) /* 0x402885C0 */ +#define DW0_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[24]) /* 0x40288600 */ +#define DW0_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[25]) /* 0x40288640 */ +#define DW0_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[26]) /* 0x40288680 */ +#define DW0_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[27]) /* 0x402886C0 */ +#define DW0_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[28]) /* 0x40288700 */ +#define DW0_CH_STRUCT29 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[29]) /* 0x40288740 */ +#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40298000 */ +#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40298040 */ +#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40298080 */ +#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x402980C0 */ +#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40298100 */ +#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x40298140 */ +#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x40298180 */ +#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402981C0 */ +#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40298200 */ +#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40298240 */ +#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40298280 */ +#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x402982C0 */ +#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40298300 */ +#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x40298340 */ +#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x40298380 */ +#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402983C0 */ +#define DW1_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[16]) /* 0x40298400 */ +#define DW1_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[17]) /* 0x40298440 */ +#define DW1_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[18]) /* 0x40298480 */ +#define DW1_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[19]) /* 0x402984C0 */ +#define DW1_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[20]) /* 0x40298500 */ +#define DW1_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[21]) /* 0x40298540 */ +#define DW1_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[22]) /* 0x40298580 */ +#define DW1_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[23]) /* 0x402985C0 */ +#define DW1_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[24]) /* 0x40298600 */ +#define DW1_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[25]) /* 0x40298640 */ +#define DW1_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[26]) /* 0x40298680 */ +#define DW1_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[27]) /* 0x402986C0 */ +#define DW1_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[28]) /* 0x40298700 */ +#define DW1_CH_STRUCT29 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[29]) /* 0x40298740 */ +#define DW1_CH_STRUCT30 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[30]) /* 0x40298780 */ +#define DW1_CH_STRUCT31 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[31]) /* 0x402987C0 */ + +/******************************************************************************* +* DMAC +*******************************************************************************/ + +#define DMAC_BASE 0x402A0000UL +#define DMAC ((DMAC_Type*) DMAC_BASE) /* 0x402A0000 */ +#define DMAC_CH0 ((DMAC_CH_Type*) &DMAC->CH[0]) /* 0x402A1000 */ +#define DMAC_CH1 ((DMAC_CH_Type*) &DMAC->CH[1]) /* 0x402A1100 */ + +/******************************************************************************* +* EFUSE +*******************************************************************************/ + +#define EFUSE_BASE 0x402C0000UL +#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ + +/******************************************************************************* +* HSIOM +*******************************************************************************/ + +#define HSIOM_BASE 0x40300000UL +#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40300000 */ +#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40300000 */ +#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40300010 */ +#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40300020 */ +#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40300030 */ +#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40300040 */ +#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40300050 */ +#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40300060 */ +#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40300070 */ +#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40300080 */ +#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40300090 */ +#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403000A0 */ +#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403000B0 */ +#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403000C0 */ +#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403000D0 */ +#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403000E0 */ + +/******************************************************************************* +* GPIO +*******************************************************************************/ + +#define GPIO_BASE 0x40310000UL +#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40310000 */ +#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40310000 */ +#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40310080 */ +#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40310100 */ +#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40310180 */ +#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40310200 */ +#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40310280 */ +#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40310300 */ +#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40310380 */ +#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40310400 */ +#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40310480 */ +#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40310500 */ +#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40310580 */ +#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40310600 */ +#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40310680 */ +#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40310700 */ + +/******************************************************************************* +* SMARTIO +*******************************************************************************/ + +#define SMARTIO_BASE 0x40320000UL +#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40320000 */ +#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40320900 */ + +/******************************************************************************* +* LPCOMP +*******************************************************************************/ + +#define LPCOMP_BASE 0x40350000UL +#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */ + +/******************************************************************************* +* CSD +*******************************************************************************/ + +#define CSD0_BASE 0x40360000UL +#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */ + +/******************************************************************************* +* TCPWM +*******************************************************************************/ + +#define TCPWM0_BASE 0x40380000UL +#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM0_GRP0 ((TCPWM_GRP_Type*) &TCPWM0->GRP[0]) /* 0x40380000 */ +#define TCPWM0_GRP1 ((TCPWM_GRP_Type*) &TCPWM0->GRP[1]) /* 0x40388000 */ +#define TCPWM0_GRP0_CNT0 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[0]) /* 0x40380000 */ +#define TCPWM0_GRP0_CNT1 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[1]) /* 0x40380080 */ +#define TCPWM0_GRP0_CNT2 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[2]) /* 0x40380100 */ +#define TCPWM0_GRP0_CNT3 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[3]) /* 0x40380180 */ +#define TCPWM0_GRP1_CNT0 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[0]) /* 0x40388000 */ +#define TCPWM0_GRP1_CNT1 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[1]) /* 0x40388080 */ +#define TCPWM0_GRP1_CNT2 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[2]) /* 0x40388100 */ +#define TCPWM0_GRP1_CNT3 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[3]) /* 0x40388180 */ +#define TCPWM0_GRP1_CNT4 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[4]) /* 0x40388200 */ +#define TCPWM0_GRP1_CNT5 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[5]) /* 0x40388280 */ +#define TCPWM0_GRP1_CNT6 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[6]) /* 0x40388300 */ +#define TCPWM0_GRP1_CNT7 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[7]) /* 0x40388380 */ + +/******************************************************************************* +* LCD +*******************************************************************************/ + +#define LCD0_BASE 0x403B0000UL +#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ + +/******************************************************************************* +* SMIF +*******************************************************************************/ + +#define SMIF0_BASE 0x40420000UL +#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ +#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ +#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ +#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ + +/******************************************************************************* +* CANFD +*******************************************************************************/ + +#define CANFD0_BASE 0x40520000UL +#define CANFD0 ((CANFD_Type*) CANFD0_BASE) /* 0x40520000 */ +#define CANFD0_CH0 ((CANFD_CH_Type*) &CANFD0->CH[0]) /* 0x40520000 */ +#define CANFD0_CH0_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[0].M_TTCAN) /* 0x40520000 */ + +/******************************************************************************* +* SCB +*******************************************************************************/ + +#define SCB0_BASE 0x40600000UL +#define SCB1_BASE 0x40610000UL +#define SCB2_BASE 0x40620000UL +#define SCB4_BASE 0x40640000UL +#define SCB5_BASE 0x40650000UL +#define SCB6_BASE 0x40660000UL +#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40600000 */ +#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40610000 */ +#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40620000 */ +#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40640000 */ +#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40650000 */ +#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40660000 */ + +/******************************************************************************* +* CTBM +*******************************************************************************/ + +#define CTBM0_BASE 0x40900000UL +#define CTBM0 ((CTBM_Type*) CTBM0_BASE) /* 0x40900000 */ + +/******************************************************************************* +* CTDAC +*******************************************************************************/ + +#define CTDAC0_BASE 0x40940000UL +#define CTDAC0 ((CTDAC_Type*) CTDAC0_BASE) /* 0x40940000 */ + +/******************************************************************************* +* SAR +*******************************************************************************/ + +#define SAR0_BASE 0x409B0000UL +#define SAR1_BASE 0x409C0000UL +#define SAR0 ((SAR_Type*) SAR0_BASE) /* 0x409B0000 */ +#define SAR1 ((SAR_Type*) SAR1_BASE) /* 0x409C0000 */ + +/******************************************************************************* +* PASS +*******************************************************************************/ + +#define PASS_BASE 0x409F0000UL +#define PASS ((PASS_Type*) PASS_BASE) /* 0x409F0000 */ +#define PASS_TIMER ((PASS_TIMER_Type*) &PASS->TIMER) /* 0x409F0100 */ +#define PASS_LPOSC ((PASS_LPOSC_Type*) &PASS->LPOSC) /* 0x409F0200 */ +#define PASS_FIFO0 ((PASS_FIFO_Type*) &PASS->FIFO[0]) /* 0x409F0300 */ +#define PASS_FIFO1 ((PASS_FIFO_Type*) &PASS->FIFO[1]) /* 0x409F0400 */ +#define PASS_AREFV2 ((PASS_AREFV2_Type*) &PASS->AREFV2) /* 0x409F0E00 */ + +/** \} CY8C6144AZI-S4F83 */ + +#endif /* _CY8C6144AZI_S4F83_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6144azi_s4f92.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6144azi_s4f92.h new file mode 100644 index 0000000000..d140945ba0 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6144azi_s4f92.h @@ -0,0 +1,980 @@ +/***************************************************************************//** +* \file cy8c6144azi_s4f92.h +* +* \brief +* CY8C6144AZI-S4F92 device header +* +* \note +* Generator version: 1.6.0.225 +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CY8C6144AZI_S4F92_H_ +#define _CY8C6144AZI_S4F92_H_ + +/** +* \addtogroup group_device CY8C6144AZI-S4F92 +* \{ +*/ + +/** +* \addtogroup Configuration_of_CMSIS +* \{ +*/ + +/******************************************************************************* +* Interrupt Number Definition +*******************************************************************************/ + +typedef enum { + /* ARM Cortex-M4 Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C6144AZI-S4F92 Peripheral Interrupt Numbers */ + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_6_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #6 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + pass_interrupt_sar_0_IRQn = 39, /*!< 39 [DeepSleep] SAR ADC0 interrupt */ + pass_interrupt_sar_1_IRQn = 40, /*!< 40 [DeepSleep] SAR ADC1 interrupt */ + pass_interrupt_ctb_IRQn = 41, /*!< 41 [DeepSleep] individual interrupt per CTB */ + pass_interrupt_fifo_0_IRQn = 43, /*!< 43 [DeepSleep] PASS FIFO0 */ + pass_interrupt_fifo_1_IRQn = 44, /*!< 44 [DeepSleep] PASS FIFO1 */ + scb_0_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #2 */ + scb_4_interrupt_IRQn = 49, /*!< 49 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 50, /*!< 50 [Active] Serial Communication Block #5 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_0_interrupts_256_IRQn = 131, /*!< 131 [Active] TCPWM #0, Counter #256 */ + tcpwm_0_interrupts_257_IRQn = 132, /*!< 132 [Active] TCPWM #0, Counter #257 */ + tcpwm_0_interrupts_258_IRQn = 133, /*!< 133 [Active] TCPWM #0, Counter #258 */ + tcpwm_0_interrupts_259_IRQn = 134, /*!< 134 [Active] TCPWM #0, Counter #259 */ + tcpwm_0_interrupts_260_IRQn = 135, /*!< 135 [Active] TCPWM #0, Counter #260 */ + tcpwm_0_interrupts_261_IRQn = 136, /*!< 136 [Active] TCPWM #0, Counter #261 */ + tcpwm_0_interrupts_262_IRQn = 137, /*!< 137 [Active] TCPWM #0, Counter #262 */ + tcpwm_0_interrupts_263_IRQn = 138, /*!< 138 [Active] TCPWM #0, Counter #263 */ + pass_interrupt_dacs_IRQn = 146, /*!< 146 [Active] Consolidated interrrupt for all DACs */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + canfd_0_interrupt0_IRQn = 168, /*!< 168 [Active] Can #0, Consolidated interrupt #0 */ + canfd_0_interrupts0_0_IRQn = 169, /*!< 169 [Active] CAN #0, Interrupt #0, Channel #0 */ + canfd_0_interrupts1_0_IRQn = 170, /*!< 170 [Active] CAN #0, Interrupt #1, Channel #0 */ + cpuss_interrupts_dw1_29_IRQn = 171, /*!< 171 [Active] CPUSS DataWire #1, Channel #29 */ + cpuss_interrupts_dw1_30_IRQn = 172, /*!< 172 [Active] CPUSS DataWire #1, Channel #30 */ + cpuss_interrupts_dw1_31_IRQn = 173, /*!< 173 [Active] CPUSS DataWire #1, Channel #31 */ + cpuss_interrupts_dw0_29_IRQn = 174, /*!< 174 [Active] CPUSS DataWire #0, Channel #29 */ + unconnected_IRQn = 240 /*!< 240 Unconnected */ +} IRQn_Type; + + +/******************************************************************************* +* Processor and Core Peripheral Section +*******************************************************************************/ + +/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __CM0P_PRESENT 0 /*!< CM0P present or not */ +#define __DTCM_PRESENT 0 /*!< DTCM present or not */ +#define __ICACHE_PRESENT 0 /*!< ICACHE present or not */ +#define __DCACHE_PRESENT 0 /*!< DCACHE present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + + +/* Memory Blocks */ +#define CY_ROM_BASE 0x00000000UL +#define CY_ROM_SIZE 0x00010000UL +#define CY_SRAM_BASE 0x08000000UL +#define CY_SRAM_SIZE 0x00020000UL +#define CY_FLASH_BASE 0x10000000UL +#define CY_FLASH_SIZE 0x00040000UL +#define CY_EM_EEPROM_BASE 0x14000000UL +#define CY_EM_EEPROM_SIZE 0x00000000UL +#define CY_SFLASH_BASE 0x16000000UL +#define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL +#define CY_EFUSE_BASE 0x402C0800UL +#define CY_EFUSE_SIZE 0x00000200UL +#define CY_CAN0MRAM_BASE 0x40530000UL +#define CY_CAN0MRAM_SIZE 0x00010000UL + +#include "system_psoc6.h" /*!< PSoC 6 System */ + +/* IP List */ +#define CY_IP_MXTTCANFD 1u +#define CY_IP_MXTTCANFD_INSTANCES 1u +#define CY_IP_MXTTCANFD_VERSION 1u +#define CY_IP_M4CPUSS 1u +#define CY_IP_M4CPUSS_INSTANCES 1u +#define CY_IP_M4CPUSS_VERSION 2u +#define CY_IP_M4CPUSS_DMAC 1u +#define CY_IP_M4CPUSS_DMAC_INSTANCES 1u +#define CY_IP_M4CPUSS_DMAC_VERSION 2u +#define CY_IP_M4CPUSS_DMA 1u +#define CY_IP_M4CPUSS_DMA_INSTANCES 2u +#define CY_IP_M4CPUSS_DMA_VERSION 2u +#define CY_IP_MXCRYPTO 1u +#define CY_IP_MXCRYPTO_INSTANCES 1u +#define CY_IP_MXCRYPTO_VERSION 2u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 2u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 6u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u + +#include "psoc6_04_config.h" +#include "gpio_psoc6_04_64_tqfp.h" + +#define CY_DEVICE_PSOC6A256K +#define CY_SILICON_ID 0xEACA110EUL +#define CY_HF_CLK_MAX_FREQ 150000000UL + +#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL + +/******************************************************************************* +* SFLASH +*******************************************************************************/ + +#define SFLASH_BASE 0x16000000UL +#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */ + +/******************************************************************************* +* PERI +*******************************************************************************/ + +#define PERI_BASE 0x40000000UL +#define PERI ((PERI_Type*) PERI_BASE) /* 0x40000000 */ +#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40004000 */ +#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40004020 */ +#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40004040 */ +#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x40004060 */ +#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40004080 */ +#define PERI_GR5 ((PERI_GR_Type*) &PERI->GR[5]) /* 0x400040A0 */ +#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x400040C0 */ +#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40004120 */ +#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40008000 */ +#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40008400 */ +#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40008800 */ +#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40008C00 */ +#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40009000 */ +#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40009400 */ +#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40009800 */ +#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40009C00 */ +#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ +#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ +#define PERI_TR_GR10 ((PERI_TR_GR_Type*) &PERI->TR_GR[10]) /* 0x4000A800 */ +#define PERI_TR_GR11 ((PERI_TR_GR_Type*) &PERI->TR_GR[11]) /* 0x4000AC00 */ +#define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ +#define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ +#define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ +#define PERI_TR_1TO1_GR3 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[3]) /* 0x4000CC00 */ +#define PERI_TR_1TO1_GR4 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[4]) /* 0x4000D000 */ +#define PERI_TR_1TO1_GR5 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[5]) /* 0x4000D400 */ +#define PERI_TR_1TO1_GR6 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[6]) /* 0x4000D800 */ +#define PERI_TR_1TO1_GR7 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[7]) /* 0x4000DC00 */ +#define PERI_TR_1TO1_GR8 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[8]) /* 0x4000E000 */ + +/******************************************************************************* +* PERI_MS +*******************************************************************************/ + +#define PERI_MS_BASE 0x40010000UL +#define PERI_MS ((PERI_MS_Type*) PERI_MS_BASE) /* 0x40010000 */ +#define PERI_MS_PPU_PR0 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[0]) /* 0x40010000 */ +#define PERI_MS_PPU_PR1 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[1]) /* 0x40010040 */ +#define PERI_MS_PPU_PR2 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[2]) /* 0x40010080 */ +#define PERI_MS_PPU_PR3 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[3]) /* 0x400100C0 */ +#define PERI_MS_PPU_PR4 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[4]) /* 0x40010100 */ +#define PERI_MS_PPU_PR5 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[5]) /* 0x40010140 */ +#define PERI_MS_PPU_PR6 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[6]) /* 0x40010180 */ +#define PERI_MS_PPU_PR7 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[7]) /* 0x400101C0 */ +#define PERI_MS_PPU_FX_PERI_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[0]) /* 0x40010800 */ +#define PERI_MS_PPU_FX_PERI_GR0_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[1]) /* 0x40010840 */ +#define PERI_MS_PPU_FX_PERI_GR1_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[2]) /* 0x40010880 */ +#define PERI_MS_PPU_FX_PERI_GR2_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[3]) /* 0x400108C0 */ +#define PERI_MS_PPU_FX_PERI_GR3_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[4]) /* 0x40010900 */ +#define PERI_MS_PPU_FX_PERI_GR4_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[5]) /* 0x40010940 */ +#define PERI_MS_PPU_FX_PERI_GR5_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[6]) /* 0x40010980 */ +#define PERI_MS_PPU_FX_PERI_GR6_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[7]) /* 0x400109C0 */ +#define PERI_MS_PPU_FX_PERI_GR9_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[8]) /* 0x40010A00 */ +#define PERI_MS_PPU_FX_PERI_TR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[9]) /* 0x40010A40 */ +#define PERI_MS_PPU_FX_CRYPTO_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[10]) /* 0x40010A80 */ +#define PERI_MS_PPU_FX_CRYPTO_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[11]) /* 0x40010AC0 */ +#define PERI_MS_PPU_FX_CRYPTO_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[12]) /* 0x40010B00 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[13]) /* 0x40010B40 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[14]) /* 0x40010B80 */ +#define PERI_MS_PPU_FX_CRYPTO_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[15]) /* 0x40010BC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[16]) /* 0x40010C00 */ +#define PERI_MS_PPU_FX_CPUSS_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[17]) /* 0x40010C40 */ +#define PERI_MS_PPU_FX_CPUSS_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[18]) /* 0x40010C80 */ +#define PERI_MS_PPU_FX_CPUSS_CM0_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[19]) /* 0x40010CC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[20]) /* 0x40010D00 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[21]) /* 0x40010D40 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT1_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[22]) /* 0x40010D80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT0_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[23]) /* 0x40010DC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT1_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[24]) /* 0x40010E00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT2_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[25]) /* 0x40010E40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT3_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[26]) /* 0x40010E80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT4_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[27]) /* 0x40010EC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT5_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[28]) /* 0x40010F00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT6_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[29]) /* 0x40010F40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT7_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[30]) /* 0x40010F80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT8_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[31]) /* 0x40010FC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT9_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[32]) /* 0x40011000 */ +#define PERI_MS_PPU_FX_IPC_STRUCT10_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[33]) /* 0x40011040 */ +#define PERI_MS_PPU_FX_IPC_STRUCT11_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[34]) /* 0x40011080 */ +#define PERI_MS_PPU_FX_IPC_STRUCT12_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[35]) /* 0x400110C0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT13_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[36]) /* 0x40011100 */ +#define PERI_MS_PPU_FX_IPC_STRUCT14_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[37]) /* 0x40011140 */ +#define PERI_MS_PPU_FX_IPC_STRUCT15_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[38]) /* 0x40011180 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT0_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[39]) /* 0x400111C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT1_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[40]) /* 0x40011200 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT2_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[41]) /* 0x40011240 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT3_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[42]) /* 0x40011280 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT4_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[43]) /* 0x400112C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT5_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[44]) /* 0x40011300 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT6_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[45]) /* 0x40011340 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT7_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[46]) /* 0x40011380 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT8_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[47]) /* 0x400113C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT9_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[48]) /* 0x40011400 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT10_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[49]) /* 0x40011440 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT11_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[50]) /* 0x40011480 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT12_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[51]) /* 0x400114C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT13_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[52]) /* 0x40011500 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT14_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[53]) /* 0x40011540 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT15_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[54]) /* 0x40011580 */ +#define PERI_MS_PPU_FX_PROT_SMPU_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[55]) /* 0x400115C0 */ +#define PERI_MS_PPU_FX_PROT_MPU0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[56]) /* 0x40011600 */ +#define PERI_MS_PPU_FX_PROT_MPU14_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[57]) /* 0x40011640 */ +#define PERI_MS_PPU_FX_PROT_MPU15_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[58]) /* 0x40011680 */ +#define PERI_MS_PPU_FX_FLASHC_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[59]) /* 0x400116C0 */ +#define PERI_MS_PPU_FX_FLASHC_CMD ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[60]) /* 0x40011700 */ +#define PERI_MS_PPU_FX_FLASHC_DFT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[61]) /* 0x40011740 */ +#define PERI_MS_PPU_FX_FLASHC_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[62]) /* 0x40011780 */ +#define PERI_MS_PPU_FX_FLASHC_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[63]) /* 0x400117C0 */ +#define PERI_MS_PPU_FX_FLASHC_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[64]) /* 0x40011800 */ +#define PERI_MS_PPU_FX_FLASHC_DW0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[65]) /* 0x40011840 */ +#define PERI_MS_PPU_FX_FLASHC_DW1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[66]) /* 0x40011880 */ +#define PERI_MS_PPU_FX_FLASHC_DMAC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[67]) /* 0x400118C0 */ +#define PERI_MS_PPU_FX_FLASHC_FM ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[68]) /* 0x40011900 */ +#define PERI_MS_PPU_FX_SRSS_MAIN1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[69]) /* 0x40011940 */ +#define PERI_MS_PPU_FX_SRSS_MAIN2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[70]) /* 0x40011980 */ +#define PERI_MS_PPU_FX_WDT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[71]) /* 0x400119C0 */ +#define PERI_MS_PPU_FX_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[72]) /* 0x40011A00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[73]) /* 0x40011A40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[74]) /* 0x40011A80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[75]) /* 0x40011AC0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[76]) /* 0x40011B00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[77]) /* 0x40011B40 */ +#define PERI_MS_PPU_FX_BACKUP_BACKUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[78]) /* 0x40011B80 */ +#define PERI_MS_PPU_FX_DW0_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[79]) /* 0x40011BC0 */ +#define PERI_MS_PPU_FX_DW1_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[80]) /* 0x40011C00 */ +#define PERI_MS_PPU_FX_DW0_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[81]) /* 0x40011C40 */ +#define PERI_MS_PPU_FX_DW1_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[82]) /* 0x40011C80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[83]) /* 0x40011CC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[84]) /* 0x40011D00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[85]) /* 0x40011D40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[86]) /* 0x40011D80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[87]) /* 0x40011DC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[88]) /* 0x40011E00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[89]) /* 0x40011E40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[90]) /* 0x40011E80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[91]) /* 0x40011EC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[92]) /* 0x40011F00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[93]) /* 0x40011F40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[94]) /* 0x40011F80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[95]) /* 0x40011FC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[96]) /* 0x40012000 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[97]) /* 0x40012040 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[98]) /* 0x40012080 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[99]) /* 0x400120C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[100]) /* 0x40012100 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[101]) /* 0x40012140 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[102]) /* 0x40012180 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[103]) /* 0x400121C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[104]) /* 0x40012200 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[105]) /* 0x40012240 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[106]) /* 0x40012280 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[107]) /* 0x400122C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[108]) /* 0x40012300 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[109]) /* 0x40012340 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[110]) /* 0x40012380 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[111]) /* 0x400123C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT29_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[112]) /* 0x40012400 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[113]) /* 0x40012440 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[114]) /* 0x40012480 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[115]) /* 0x400124C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[116]) /* 0x40012500 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[117]) /* 0x40012540 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[118]) /* 0x40012580 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[119]) /* 0x400125C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[120]) /* 0x40012600 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[121]) /* 0x40012640 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[122]) /* 0x40012680 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[123]) /* 0x400126C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[124]) /* 0x40012700 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[125]) /* 0x40012740 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[126]) /* 0x40012780 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[127]) /* 0x400127C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[128]) /* 0x40012800 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[129]) /* 0x40012840 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[130]) /* 0x40012880 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[131]) /* 0x400128C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[132]) /* 0x40012900 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[133]) /* 0x40012940 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[134]) /* 0x40012980 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[135]) /* 0x400129C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[136]) /* 0x40012A00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[137]) /* 0x40012A40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[138]) /* 0x40012A80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[139]) /* 0x40012AC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[140]) /* 0x40012B00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[141]) /* 0x40012B40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT29_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[142]) /* 0x40012B80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT30_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[143]) /* 0x40012BC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT31_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[144]) /* 0x40012C00 */ +#define PERI_MS_PPU_FX_DMAC_TOP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[145]) /* 0x40012C40 */ +#define PERI_MS_PPU_FX_DMAC_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[146]) /* 0x40012C80 */ +#define PERI_MS_PPU_FX_DMAC_CH1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[147]) /* 0x40012CC0 */ +#define PERI_MS_PPU_FX_EFUSE_CTL ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[148]) /* 0x40012D00 */ +#define PERI_MS_PPU_FX_EFUSE_DATA ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[149]) /* 0x40012D40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[150]) /* 0x40012D80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[151]) /* 0x40012DC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[152]) /* 0x40012E00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[153]) /* 0x40012E40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[154]) /* 0x40012E80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[155]) /* 0x40012EC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[156]) /* 0x40012F00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[157]) /* 0x40012F40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[158]) /* 0x40012F80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[159]) /* 0x40012FC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[160]) /* 0x40013000 */ +#define PERI_MS_PPU_FX_HSIOM_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[161]) /* 0x40013040 */ +#define PERI_MS_PPU_FX_HSIOM_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[162]) /* 0x40013080 */ +#define PERI_MS_PPU_FX_HSIOM_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[163]) /* 0x400130C0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[164]) /* 0x40013100 */ +#define PERI_MS_PPU_FX_HSIOM_AMUX ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[165]) /* 0x40013140 */ +#define PERI_MS_PPU_FX_HSIOM_MON ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[166]) /* 0x40013180 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[167]) /* 0x400131C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[168]) /* 0x40013200 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[169]) /* 0x40013240 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[170]) /* 0x40013280 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[171]) /* 0x400132C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[172]) /* 0x40013300 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[173]) /* 0x40013340 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[174]) /* 0x40013380 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[175]) /* 0x400133C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[176]) /* 0x40013400 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[177]) /* 0x40013440 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[178]) /* 0x40013480 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[179]) /* 0x400134C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[180]) /* 0x40013500 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[181]) /* 0x40013540 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[182]) /* 0x40013580 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[183]) /* 0x400135C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[184]) /* 0x40013600 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[185]) /* 0x40013640 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[186]) /* 0x40013680 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[187]) /* 0x400136C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[188]) /* 0x40013700 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[189]) /* 0x40013740 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[190]) /* 0x40013780 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[191]) /* 0x400137C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[192]) /* 0x40013800 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[193]) /* 0x40013840 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[194]) /* 0x40013880 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[195]) /* 0x400138C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[196]) /* 0x40013900 */ +#define PERI_MS_PPU_FX_GPIO_GPIO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[197]) /* 0x40013940 */ +#define PERI_MS_PPU_FX_GPIO_TEST ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[198]) /* 0x40013980 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[199]) /* 0x400139C0 */ +#define PERI_MS_PPU_FX_LPCOMP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[200]) /* 0x40013A00 */ +#define PERI_MS_PPU_FX_CSD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[201]) /* 0x40013A40 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT0_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[202]) /* 0x40013A80 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT1_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[203]) /* 0x40013AC0 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT2_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[204]) /* 0x40013B00 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT3_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[205]) /* 0x40013B40 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT0_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[206]) /* 0x40013B80 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT1_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[207]) /* 0x40013BC0 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT2_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[208]) /* 0x40013C00 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT3_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[209]) /* 0x40013C40 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT4_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[210]) /* 0x40013C80 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT5_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[211]) /* 0x40013CC0 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT6_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[212]) /* 0x40013D00 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT7_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[213]) /* 0x40013D40 */ +#define PERI_MS_PPU_FX_LCD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[214]) /* 0x40013D80 */ +#define PERI_MS_PPU_FX_USBFS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[215]) /* 0x40013DC0 */ +#define PERI_MS_PPU_FX_SMIF0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[216]) /* 0x40013E00 */ +#define PERI_MS_PPU_FX_CANFD0_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[217]) /* 0x40013E40 */ +#define PERI_MS_PPU_FX_CANFD0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[218]) /* 0x40013E80 */ +#define PERI_MS_PPU_FX_CANFD0_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[219]) /* 0x40013EC0 */ +#define PERI_MS_PPU_FX_SCB0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[220]) /* 0x40013F00 */ +#define PERI_MS_PPU_FX_SCB1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[221]) /* 0x40013F40 */ +#define PERI_MS_PPU_FX_SCB2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[222]) /* 0x40013F80 */ +#define PERI_MS_PPU_FX_SCB4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[223]) /* 0x40013FC0 */ +#define PERI_MS_PPU_FX_SCB5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[224]) /* 0x40014000 */ +#define PERI_MS_PPU_FX_SCB6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[225]) /* 0x40014040 */ + +/******************************************************************************* +* CRYPTO +*******************************************************************************/ + +#define CRYPTO_BASE 0x40100000UL +#define CRYPTO ((CRYPTO_Type*) CRYPTO_BASE) /* 0x40100000 */ + +/******************************************************************************* +* CPUSS +*******************************************************************************/ + +#define CPUSS_BASE 0x40200000UL +#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40200000 */ + +/******************************************************************************* +* FAULT +*******************************************************************************/ + +#define FAULT_BASE 0x40210000UL +#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40210000 */ +#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40210000 */ +#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40210100 */ + +/******************************************************************************* +* IPC +*******************************************************************************/ + +#define IPC_BASE 0x40220000UL +#define IPC ((IPC_Type*) IPC_BASE) /* 0x40220000 */ +#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40220000 */ +#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40220020 */ +#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40220040 */ +#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40220060 */ +#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40220080 */ +#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402200A0 */ +#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402200C0 */ +#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402200E0 */ +#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40220100 */ +#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40220120 */ +#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40220140 */ +#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40220160 */ +#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40220180 */ +#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402201A0 */ +#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402201C0 */ +#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402201E0 */ +#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40221000 */ +#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40221020 */ +#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40221040 */ +#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40221060 */ +#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40221080 */ +#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402210A0 */ +#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402210C0 */ +#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402210E0 */ +#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40221100 */ +#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40221120 */ +#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40221140 */ +#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40221160 */ +#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40221180 */ +#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402211A0 */ +#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402211C0 */ +#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402211E0 */ + +/******************************************************************************* +* PROT +*******************************************************************************/ + +#define PROT_BASE 0x40230000UL +#define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ +#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ +#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ +#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402320C0 */ +#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40232100 */ +#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40232140 */ +#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40232180 */ +#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402321C0 */ +#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40232200 */ +#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40232240 */ +#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40232280 */ +#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402322C0 */ +#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40232300 */ +#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ +#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ +#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ + +/******************************************************************************* +* FLASHC +*******************************************************************************/ + +#define FLASHC_BASE 0x40240000UL +#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40240000 */ +#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4024F000 */ + +/******************************************************************************* +* SRSS +*******************************************************************************/ + +#define SRSS_BASE 0x40260000UL +#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ +#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */ +#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */ + +/******************************************************************************* +* BACKUP +*******************************************************************************/ + +#define BACKUP_BASE 0x40270000UL +#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ + +/******************************************************************************* +* DW +*******************************************************************************/ + +#define DW0_BASE 0x40280000UL +#define DW1_BASE 0x40290000UL +#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ +#define DW1 ((DW_Type*) DW1_BASE) /* 0x40290000 */ +#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40288000 */ +#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40288040 */ +#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40288080 */ +#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x402880C0 */ +#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40288100 */ +#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x40288140 */ +#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x40288180 */ +#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402881C0 */ +#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40288200 */ +#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40288240 */ +#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40288280 */ +#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x402882C0 */ +#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40288300 */ +#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x40288340 */ +#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x40288380 */ +#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402883C0 */ +#define DW0_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[16]) /* 0x40288400 */ +#define DW0_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[17]) /* 0x40288440 */ +#define DW0_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[18]) /* 0x40288480 */ +#define DW0_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[19]) /* 0x402884C0 */ +#define DW0_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[20]) /* 0x40288500 */ +#define DW0_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[21]) /* 0x40288540 */ +#define DW0_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[22]) /* 0x40288580 */ +#define DW0_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[23]) /* 0x402885C0 */ +#define DW0_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[24]) /* 0x40288600 */ +#define DW0_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[25]) /* 0x40288640 */ +#define DW0_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[26]) /* 0x40288680 */ +#define DW0_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[27]) /* 0x402886C0 */ +#define DW0_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[28]) /* 0x40288700 */ +#define DW0_CH_STRUCT29 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[29]) /* 0x40288740 */ +#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40298000 */ +#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40298040 */ +#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40298080 */ +#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x402980C0 */ +#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40298100 */ +#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x40298140 */ +#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x40298180 */ +#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402981C0 */ +#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40298200 */ +#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40298240 */ +#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40298280 */ +#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x402982C0 */ +#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40298300 */ +#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x40298340 */ +#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x40298380 */ +#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402983C0 */ +#define DW1_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[16]) /* 0x40298400 */ +#define DW1_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[17]) /* 0x40298440 */ +#define DW1_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[18]) /* 0x40298480 */ +#define DW1_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[19]) /* 0x402984C0 */ +#define DW1_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[20]) /* 0x40298500 */ +#define DW1_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[21]) /* 0x40298540 */ +#define DW1_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[22]) /* 0x40298580 */ +#define DW1_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[23]) /* 0x402985C0 */ +#define DW1_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[24]) /* 0x40298600 */ +#define DW1_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[25]) /* 0x40298640 */ +#define DW1_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[26]) /* 0x40298680 */ +#define DW1_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[27]) /* 0x402986C0 */ +#define DW1_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[28]) /* 0x40298700 */ +#define DW1_CH_STRUCT29 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[29]) /* 0x40298740 */ +#define DW1_CH_STRUCT30 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[30]) /* 0x40298780 */ +#define DW1_CH_STRUCT31 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[31]) /* 0x402987C0 */ + +/******************************************************************************* +* DMAC +*******************************************************************************/ + +#define DMAC_BASE 0x402A0000UL +#define DMAC ((DMAC_Type*) DMAC_BASE) /* 0x402A0000 */ +#define DMAC_CH0 ((DMAC_CH_Type*) &DMAC->CH[0]) /* 0x402A1000 */ +#define DMAC_CH1 ((DMAC_CH_Type*) &DMAC->CH[1]) /* 0x402A1100 */ + +/******************************************************************************* +* EFUSE +*******************************************************************************/ + +#define EFUSE_BASE 0x402C0000UL +#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ + +/******************************************************************************* +* HSIOM +*******************************************************************************/ + +#define HSIOM_BASE 0x40300000UL +#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40300000 */ +#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40300000 */ +#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40300010 */ +#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40300020 */ +#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40300030 */ +#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40300040 */ +#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40300050 */ +#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40300060 */ +#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40300070 */ +#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40300080 */ +#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40300090 */ +#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403000A0 */ +#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403000B0 */ +#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403000C0 */ +#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403000D0 */ +#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403000E0 */ + +/******************************************************************************* +* GPIO +*******************************************************************************/ + +#define GPIO_BASE 0x40310000UL +#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40310000 */ +#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40310000 */ +#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40310080 */ +#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40310100 */ +#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40310180 */ +#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40310200 */ +#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40310280 */ +#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40310300 */ +#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40310380 */ +#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40310400 */ +#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40310480 */ +#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40310500 */ +#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40310580 */ +#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40310600 */ +#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40310680 */ +#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40310700 */ + +/******************************************************************************* +* SMARTIO +*******************************************************************************/ + +#define SMARTIO_BASE 0x40320000UL +#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40320000 */ +#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40320900 */ + +/******************************************************************************* +* LPCOMP +*******************************************************************************/ + +#define LPCOMP_BASE 0x40350000UL +#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */ + +/******************************************************************************* +* CSD +*******************************************************************************/ + +#define CSD0_BASE 0x40360000UL +#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */ + +/******************************************************************************* +* TCPWM +*******************************************************************************/ + +#define TCPWM0_BASE 0x40380000UL +#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM0_GRP0 ((TCPWM_GRP_Type*) &TCPWM0->GRP[0]) /* 0x40380000 */ +#define TCPWM0_GRP1 ((TCPWM_GRP_Type*) &TCPWM0->GRP[1]) /* 0x40388000 */ +#define TCPWM0_GRP0_CNT0 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[0]) /* 0x40380000 */ +#define TCPWM0_GRP0_CNT1 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[1]) /* 0x40380080 */ +#define TCPWM0_GRP0_CNT2 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[2]) /* 0x40380100 */ +#define TCPWM0_GRP0_CNT3 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[3]) /* 0x40380180 */ +#define TCPWM0_GRP1_CNT0 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[0]) /* 0x40388000 */ +#define TCPWM0_GRP1_CNT1 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[1]) /* 0x40388080 */ +#define TCPWM0_GRP1_CNT2 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[2]) /* 0x40388100 */ +#define TCPWM0_GRP1_CNT3 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[3]) /* 0x40388180 */ +#define TCPWM0_GRP1_CNT4 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[4]) /* 0x40388200 */ +#define TCPWM0_GRP1_CNT5 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[5]) /* 0x40388280 */ +#define TCPWM0_GRP1_CNT6 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[6]) /* 0x40388300 */ +#define TCPWM0_GRP1_CNT7 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[7]) /* 0x40388380 */ + +/******************************************************************************* +* LCD +*******************************************************************************/ + +#define LCD0_BASE 0x403B0000UL +#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ + +/******************************************************************************* +* SMIF +*******************************************************************************/ + +#define SMIF0_BASE 0x40420000UL +#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ +#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ +#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ +#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ + +/******************************************************************************* +* CANFD +*******************************************************************************/ + +#define CANFD0_BASE 0x40520000UL +#define CANFD0 ((CANFD_Type*) CANFD0_BASE) /* 0x40520000 */ +#define CANFD0_CH0 ((CANFD_CH_Type*) &CANFD0->CH[0]) /* 0x40520000 */ +#define CANFD0_CH0_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[0].M_TTCAN) /* 0x40520000 */ + +/******************************************************************************* +* SCB +*******************************************************************************/ + +#define SCB0_BASE 0x40600000UL +#define SCB1_BASE 0x40610000UL +#define SCB2_BASE 0x40620000UL +#define SCB4_BASE 0x40640000UL +#define SCB5_BASE 0x40650000UL +#define SCB6_BASE 0x40660000UL +#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40600000 */ +#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40610000 */ +#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40620000 */ +#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40640000 */ +#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40650000 */ +#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40660000 */ + +/******************************************************************************* +* CTBM +*******************************************************************************/ + +#define CTBM0_BASE 0x40900000UL +#define CTBM0 ((CTBM_Type*) CTBM0_BASE) /* 0x40900000 */ + +/******************************************************************************* +* CTDAC +*******************************************************************************/ + +#define CTDAC0_BASE 0x40940000UL +#define CTDAC0 ((CTDAC_Type*) CTDAC0_BASE) /* 0x40940000 */ + +/******************************************************************************* +* SAR +*******************************************************************************/ + +#define SAR0_BASE 0x409B0000UL +#define SAR1_BASE 0x409C0000UL +#define SAR0 ((SAR_Type*) SAR0_BASE) /* 0x409B0000 */ +#define SAR1 ((SAR_Type*) SAR1_BASE) /* 0x409C0000 */ + +/******************************************************************************* +* PASS +*******************************************************************************/ + +#define PASS_BASE 0x409F0000UL +#define PASS ((PASS_Type*) PASS_BASE) /* 0x409F0000 */ +#define PASS_TIMER ((PASS_TIMER_Type*) &PASS->TIMER) /* 0x409F0100 */ +#define PASS_LPOSC ((PASS_LPOSC_Type*) &PASS->LPOSC) /* 0x409F0200 */ +#define PASS_FIFO0 ((PASS_FIFO_Type*) &PASS->FIFO[0]) /* 0x409F0300 */ +#define PASS_FIFO1 ((PASS_FIFO_Type*) &PASS->FIFO[1]) /* 0x409F0400 */ +#define PASS_AREFV2 ((PASS_AREFV2_Type*) &PASS->AREFV2) /* 0x409F0E00 */ + +/** \} CY8C6144AZI-S4F92 */ + +#endif /* _CY8C6144AZI_S4F92_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6144azi_s4f93.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6144azi_s4f93.h new file mode 100644 index 0000000000..54d3551a8c --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6144azi_s4f93.h @@ -0,0 +1,980 @@ +/***************************************************************************//** +* \file cy8c6144azi_s4f93.h +* +* \brief +* CY8C6144AZI-S4F93 device header +* +* \note +* Generator version: 1.6.0.225 +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CY8C6144AZI_S4F93_H_ +#define _CY8C6144AZI_S4F93_H_ + +/** +* \addtogroup group_device CY8C6144AZI-S4F93 +* \{ +*/ + +/** +* \addtogroup Configuration_of_CMSIS +* \{ +*/ + +/******************************************************************************* +* Interrupt Number Definition +*******************************************************************************/ + +typedef enum { + /* ARM Cortex-M4 Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C6144AZI-S4F93 Peripheral Interrupt Numbers */ + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_6_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #6 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + pass_interrupt_sar_0_IRQn = 39, /*!< 39 [DeepSleep] SAR ADC0 interrupt */ + pass_interrupt_sar_1_IRQn = 40, /*!< 40 [DeepSleep] SAR ADC1 interrupt */ + pass_interrupt_ctb_IRQn = 41, /*!< 41 [DeepSleep] individual interrupt per CTB */ + pass_interrupt_fifo_0_IRQn = 43, /*!< 43 [DeepSleep] PASS FIFO0 */ + pass_interrupt_fifo_1_IRQn = 44, /*!< 44 [DeepSleep] PASS FIFO1 */ + scb_0_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #2 */ + scb_4_interrupt_IRQn = 49, /*!< 49 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 50, /*!< 50 [Active] Serial Communication Block #5 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_0_interrupts_256_IRQn = 131, /*!< 131 [Active] TCPWM #0, Counter #256 */ + tcpwm_0_interrupts_257_IRQn = 132, /*!< 132 [Active] TCPWM #0, Counter #257 */ + tcpwm_0_interrupts_258_IRQn = 133, /*!< 133 [Active] TCPWM #0, Counter #258 */ + tcpwm_0_interrupts_259_IRQn = 134, /*!< 134 [Active] TCPWM #0, Counter #259 */ + tcpwm_0_interrupts_260_IRQn = 135, /*!< 135 [Active] TCPWM #0, Counter #260 */ + tcpwm_0_interrupts_261_IRQn = 136, /*!< 136 [Active] TCPWM #0, Counter #261 */ + tcpwm_0_interrupts_262_IRQn = 137, /*!< 137 [Active] TCPWM #0, Counter #262 */ + tcpwm_0_interrupts_263_IRQn = 138, /*!< 138 [Active] TCPWM #0, Counter #263 */ + pass_interrupt_dacs_IRQn = 146, /*!< 146 [Active] Consolidated interrrupt for all DACs */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + canfd_0_interrupt0_IRQn = 168, /*!< 168 [Active] Can #0, Consolidated interrupt #0 */ + canfd_0_interrupts0_0_IRQn = 169, /*!< 169 [Active] CAN #0, Interrupt #0, Channel #0 */ + canfd_0_interrupts1_0_IRQn = 170, /*!< 170 [Active] CAN #0, Interrupt #1, Channel #0 */ + cpuss_interrupts_dw1_29_IRQn = 171, /*!< 171 [Active] CPUSS DataWire #1, Channel #29 */ + cpuss_interrupts_dw1_30_IRQn = 172, /*!< 172 [Active] CPUSS DataWire #1, Channel #30 */ + cpuss_interrupts_dw1_31_IRQn = 173, /*!< 173 [Active] CPUSS DataWire #1, Channel #31 */ + cpuss_interrupts_dw0_29_IRQn = 174, /*!< 174 [Active] CPUSS DataWire #0, Channel #29 */ + unconnected_IRQn = 240 /*!< 240 Unconnected */ +} IRQn_Type; + + +/******************************************************************************* +* Processor and Core Peripheral Section +*******************************************************************************/ + +/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __CM0P_PRESENT 0 /*!< CM0P present or not */ +#define __DTCM_PRESENT 0 /*!< DTCM present or not */ +#define __ICACHE_PRESENT 0 /*!< ICACHE present or not */ +#define __DCACHE_PRESENT 0 /*!< DCACHE present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + + +/* Memory Blocks */ +#define CY_ROM_BASE 0x00000000UL +#define CY_ROM_SIZE 0x00010000UL +#define CY_SRAM_BASE 0x08000000UL +#define CY_SRAM_SIZE 0x00020000UL +#define CY_FLASH_BASE 0x10000000UL +#define CY_FLASH_SIZE 0x00040000UL +#define CY_EM_EEPROM_BASE 0x14000000UL +#define CY_EM_EEPROM_SIZE 0x00000000UL +#define CY_SFLASH_BASE 0x16000000UL +#define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL +#define CY_EFUSE_BASE 0x402C0800UL +#define CY_EFUSE_SIZE 0x00000200UL +#define CY_CAN0MRAM_BASE 0x40530000UL +#define CY_CAN0MRAM_SIZE 0x00010000UL + +#include "system_psoc6.h" /*!< PSoC 6 System */ + +/* IP List */ +#define CY_IP_MXTTCANFD 1u +#define CY_IP_MXTTCANFD_INSTANCES 1u +#define CY_IP_MXTTCANFD_VERSION 1u +#define CY_IP_M4CPUSS 1u +#define CY_IP_M4CPUSS_INSTANCES 1u +#define CY_IP_M4CPUSS_VERSION 2u +#define CY_IP_M4CPUSS_DMAC 1u +#define CY_IP_M4CPUSS_DMAC_INSTANCES 1u +#define CY_IP_M4CPUSS_DMAC_VERSION 2u +#define CY_IP_M4CPUSS_DMA 1u +#define CY_IP_M4CPUSS_DMA_INSTANCES 2u +#define CY_IP_M4CPUSS_DMA_VERSION 2u +#define CY_IP_MXCRYPTO 1u +#define CY_IP_MXCRYPTO_INSTANCES 1u +#define CY_IP_MXCRYPTO_VERSION 2u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 2u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 6u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u + +#include "psoc6_04_config.h" +#include "gpio_psoc6_04_80_tqfp.h" + +#define CY_DEVICE_PSOC6A256K +#define CY_SILICON_ID 0xEACC110EUL +#define CY_HF_CLK_MAX_FREQ 150000000UL + +#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL + +/******************************************************************************* +* SFLASH +*******************************************************************************/ + +#define SFLASH_BASE 0x16000000UL +#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */ + +/******************************************************************************* +* PERI +*******************************************************************************/ + +#define PERI_BASE 0x40000000UL +#define PERI ((PERI_Type*) PERI_BASE) /* 0x40000000 */ +#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40004000 */ +#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40004020 */ +#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40004040 */ +#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x40004060 */ +#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40004080 */ +#define PERI_GR5 ((PERI_GR_Type*) &PERI->GR[5]) /* 0x400040A0 */ +#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x400040C0 */ +#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40004120 */ +#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40008000 */ +#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40008400 */ +#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40008800 */ +#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40008C00 */ +#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40009000 */ +#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40009400 */ +#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40009800 */ +#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40009C00 */ +#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ +#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ +#define PERI_TR_GR10 ((PERI_TR_GR_Type*) &PERI->TR_GR[10]) /* 0x4000A800 */ +#define PERI_TR_GR11 ((PERI_TR_GR_Type*) &PERI->TR_GR[11]) /* 0x4000AC00 */ +#define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ +#define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ +#define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ +#define PERI_TR_1TO1_GR3 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[3]) /* 0x4000CC00 */ +#define PERI_TR_1TO1_GR4 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[4]) /* 0x4000D000 */ +#define PERI_TR_1TO1_GR5 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[5]) /* 0x4000D400 */ +#define PERI_TR_1TO1_GR6 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[6]) /* 0x4000D800 */ +#define PERI_TR_1TO1_GR7 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[7]) /* 0x4000DC00 */ +#define PERI_TR_1TO1_GR8 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[8]) /* 0x4000E000 */ + +/******************************************************************************* +* PERI_MS +*******************************************************************************/ + +#define PERI_MS_BASE 0x40010000UL +#define PERI_MS ((PERI_MS_Type*) PERI_MS_BASE) /* 0x40010000 */ +#define PERI_MS_PPU_PR0 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[0]) /* 0x40010000 */ +#define PERI_MS_PPU_PR1 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[1]) /* 0x40010040 */ +#define PERI_MS_PPU_PR2 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[2]) /* 0x40010080 */ +#define PERI_MS_PPU_PR3 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[3]) /* 0x400100C0 */ +#define PERI_MS_PPU_PR4 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[4]) /* 0x40010100 */ +#define PERI_MS_PPU_PR5 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[5]) /* 0x40010140 */ +#define PERI_MS_PPU_PR6 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[6]) /* 0x40010180 */ +#define PERI_MS_PPU_PR7 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[7]) /* 0x400101C0 */ +#define PERI_MS_PPU_FX_PERI_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[0]) /* 0x40010800 */ +#define PERI_MS_PPU_FX_PERI_GR0_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[1]) /* 0x40010840 */ +#define PERI_MS_PPU_FX_PERI_GR1_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[2]) /* 0x40010880 */ +#define PERI_MS_PPU_FX_PERI_GR2_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[3]) /* 0x400108C0 */ +#define PERI_MS_PPU_FX_PERI_GR3_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[4]) /* 0x40010900 */ +#define PERI_MS_PPU_FX_PERI_GR4_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[5]) /* 0x40010940 */ +#define PERI_MS_PPU_FX_PERI_GR5_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[6]) /* 0x40010980 */ +#define PERI_MS_PPU_FX_PERI_GR6_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[7]) /* 0x400109C0 */ +#define PERI_MS_PPU_FX_PERI_GR9_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[8]) /* 0x40010A00 */ +#define PERI_MS_PPU_FX_PERI_TR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[9]) /* 0x40010A40 */ +#define PERI_MS_PPU_FX_CRYPTO_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[10]) /* 0x40010A80 */ +#define PERI_MS_PPU_FX_CRYPTO_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[11]) /* 0x40010AC0 */ +#define PERI_MS_PPU_FX_CRYPTO_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[12]) /* 0x40010B00 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[13]) /* 0x40010B40 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[14]) /* 0x40010B80 */ +#define PERI_MS_PPU_FX_CRYPTO_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[15]) /* 0x40010BC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[16]) /* 0x40010C00 */ +#define PERI_MS_PPU_FX_CPUSS_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[17]) /* 0x40010C40 */ +#define PERI_MS_PPU_FX_CPUSS_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[18]) /* 0x40010C80 */ +#define PERI_MS_PPU_FX_CPUSS_CM0_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[19]) /* 0x40010CC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[20]) /* 0x40010D00 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[21]) /* 0x40010D40 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT1_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[22]) /* 0x40010D80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT0_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[23]) /* 0x40010DC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT1_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[24]) /* 0x40010E00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT2_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[25]) /* 0x40010E40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT3_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[26]) /* 0x40010E80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT4_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[27]) /* 0x40010EC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT5_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[28]) /* 0x40010F00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT6_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[29]) /* 0x40010F40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT7_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[30]) /* 0x40010F80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT8_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[31]) /* 0x40010FC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT9_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[32]) /* 0x40011000 */ +#define PERI_MS_PPU_FX_IPC_STRUCT10_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[33]) /* 0x40011040 */ +#define PERI_MS_PPU_FX_IPC_STRUCT11_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[34]) /* 0x40011080 */ +#define PERI_MS_PPU_FX_IPC_STRUCT12_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[35]) /* 0x400110C0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT13_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[36]) /* 0x40011100 */ +#define PERI_MS_PPU_FX_IPC_STRUCT14_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[37]) /* 0x40011140 */ +#define PERI_MS_PPU_FX_IPC_STRUCT15_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[38]) /* 0x40011180 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT0_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[39]) /* 0x400111C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT1_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[40]) /* 0x40011200 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT2_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[41]) /* 0x40011240 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT3_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[42]) /* 0x40011280 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT4_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[43]) /* 0x400112C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT5_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[44]) /* 0x40011300 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT6_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[45]) /* 0x40011340 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT7_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[46]) /* 0x40011380 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT8_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[47]) /* 0x400113C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT9_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[48]) /* 0x40011400 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT10_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[49]) /* 0x40011440 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT11_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[50]) /* 0x40011480 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT12_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[51]) /* 0x400114C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT13_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[52]) /* 0x40011500 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT14_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[53]) /* 0x40011540 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT15_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[54]) /* 0x40011580 */ +#define PERI_MS_PPU_FX_PROT_SMPU_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[55]) /* 0x400115C0 */ +#define PERI_MS_PPU_FX_PROT_MPU0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[56]) /* 0x40011600 */ +#define PERI_MS_PPU_FX_PROT_MPU14_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[57]) /* 0x40011640 */ +#define PERI_MS_PPU_FX_PROT_MPU15_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[58]) /* 0x40011680 */ +#define PERI_MS_PPU_FX_FLASHC_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[59]) /* 0x400116C0 */ +#define PERI_MS_PPU_FX_FLASHC_CMD ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[60]) /* 0x40011700 */ +#define PERI_MS_PPU_FX_FLASHC_DFT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[61]) /* 0x40011740 */ +#define PERI_MS_PPU_FX_FLASHC_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[62]) /* 0x40011780 */ +#define PERI_MS_PPU_FX_FLASHC_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[63]) /* 0x400117C0 */ +#define PERI_MS_PPU_FX_FLASHC_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[64]) /* 0x40011800 */ +#define PERI_MS_PPU_FX_FLASHC_DW0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[65]) /* 0x40011840 */ +#define PERI_MS_PPU_FX_FLASHC_DW1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[66]) /* 0x40011880 */ +#define PERI_MS_PPU_FX_FLASHC_DMAC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[67]) /* 0x400118C0 */ +#define PERI_MS_PPU_FX_FLASHC_FM ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[68]) /* 0x40011900 */ +#define PERI_MS_PPU_FX_SRSS_MAIN1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[69]) /* 0x40011940 */ +#define PERI_MS_PPU_FX_SRSS_MAIN2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[70]) /* 0x40011980 */ +#define PERI_MS_PPU_FX_WDT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[71]) /* 0x400119C0 */ +#define PERI_MS_PPU_FX_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[72]) /* 0x40011A00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[73]) /* 0x40011A40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[74]) /* 0x40011A80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[75]) /* 0x40011AC0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[76]) /* 0x40011B00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[77]) /* 0x40011B40 */ +#define PERI_MS_PPU_FX_BACKUP_BACKUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[78]) /* 0x40011B80 */ +#define PERI_MS_PPU_FX_DW0_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[79]) /* 0x40011BC0 */ +#define PERI_MS_PPU_FX_DW1_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[80]) /* 0x40011C00 */ +#define PERI_MS_PPU_FX_DW0_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[81]) /* 0x40011C40 */ +#define PERI_MS_PPU_FX_DW1_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[82]) /* 0x40011C80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[83]) /* 0x40011CC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[84]) /* 0x40011D00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[85]) /* 0x40011D40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[86]) /* 0x40011D80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[87]) /* 0x40011DC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[88]) /* 0x40011E00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[89]) /* 0x40011E40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[90]) /* 0x40011E80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[91]) /* 0x40011EC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[92]) /* 0x40011F00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[93]) /* 0x40011F40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[94]) /* 0x40011F80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[95]) /* 0x40011FC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[96]) /* 0x40012000 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[97]) /* 0x40012040 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[98]) /* 0x40012080 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[99]) /* 0x400120C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[100]) /* 0x40012100 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[101]) /* 0x40012140 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[102]) /* 0x40012180 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[103]) /* 0x400121C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[104]) /* 0x40012200 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[105]) /* 0x40012240 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[106]) /* 0x40012280 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[107]) /* 0x400122C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[108]) /* 0x40012300 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[109]) /* 0x40012340 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[110]) /* 0x40012380 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[111]) /* 0x400123C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT29_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[112]) /* 0x40012400 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[113]) /* 0x40012440 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[114]) /* 0x40012480 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[115]) /* 0x400124C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[116]) /* 0x40012500 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[117]) /* 0x40012540 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[118]) /* 0x40012580 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[119]) /* 0x400125C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[120]) /* 0x40012600 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[121]) /* 0x40012640 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[122]) /* 0x40012680 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[123]) /* 0x400126C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[124]) /* 0x40012700 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[125]) /* 0x40012740 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[126]) /* 0x40012780 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[127]) /* 0x400127C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[128]) /* 0x40012800 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[129]) /* 0x40012840 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[130]) /* 0x40012880 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[131]) /* 0x400128C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[132]) /* 0x40012900 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[133]) /* 0x40012940 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[134]) /* 0x40012980 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[135]) /* 0x400129C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[136]) /* 0x40012A00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[137]) /* 0x40012A40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[138]) /* 0x40012A80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[139]) /* 0x40012AC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[140]) /* 0x40012B00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[141]) /* 0x40012B40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT29_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[142]) /* 0x40012B80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT30_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[143]) /* 0x40012BC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT31_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[144]) /* 0x40012C00 */ +#define PERI_MS_PPU_FX_DMAC_TOP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[145]) /* 0x40012C40 */ +#define PERI_MS_PPU_FX_DMAC_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[146]) /* 0x40012C80 */ +#define PERI_MS_PPU_FX_DMAC_CH1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[147]) /* 0x40012CC0 */ +#define PERI_MS_PPU_FX_EFUSE_CTL ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[148]) /* 0x40012D00 */ +#define PERI_MS_PPU_FX_EFUSE_DATA ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[149]) /* 0x40012D40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[150]) /* 0x40012D80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[151]) /* 0x40012DC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[152]) /* 0x40012E00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[153]) /* 0x40012E40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[154]) /* 0x40012E80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[155]) /* 0x40012EC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[156]) /* 0x40012F00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[157]) /* 0x40012F40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[158]) /* 0x40012F80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[159]) /* 0x40012FC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[160]) /* 0x40013000 */ +#define PERI_MS_PPU_FX_HSIOM_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[161]) /* 0x40013040 */ +#define PERI_MS_PPU_FX_HSIOM_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[162]) /* 0x40013080 */ +#define PERI_MS_PPU_FX_HSIOM_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[163]) /* 0x400130C0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[164]) /* 0x40013100 */ +#define PERI_MS_PPU_FX_HSIOM_AMUX ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[165]) /* 0x40013140 */ +#define PERI_MS_PPU_FX_HSIOM_MON ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[166]) /* 0x40013180 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[167]) /* 0x400131C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[168]) /* 0x40013200 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[169]) /* 0x40013240 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[170]) /* 0x40013280 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[171]) /* 0x400132C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[172]) /* 0x40013300 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[173]) /* 0x40013340 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[174]) /* 0x40013380 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[175]) /* 0x400133C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[176]) /* 0x40013400 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[177]) /* 0x40013440 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[178]) /* 0x40013480 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[179]) /* 0x400134C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[180]) /* 0x40013500 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[181]) /* 0x40013540 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[182]) /* 0x40013580 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[183]) /* 0x400135C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[184]) /* 0x40013600 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[185]) /* 0x40013640 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[186]) /* 0x40013680 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[187]) /* 0x400136C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[188]) /* 0x40013700 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[189]) /* 0x40013740 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[190]) /* 0x40013780 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[191]) /* 0x400137C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[192]) /* 0x40013800 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[193]) /* 0x40013840 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[194]) /* 0x40013880 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[195]) /* 0x400138C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[196]) /* 0x40013900 */ +#define PERI_MS_PPU_FX_GPIO_GPIO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[197]) /* 0x40013940 */ +#define PERI_MS_PPU_FX_GPIO_TEST ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[198]) /* 0x40013980 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[199]) /* 0x400139C0 */ +#define PERI_MS_PPU_FX_LPCOMP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[200]) /* 0x40013A00 */ +#define PERI_MS_PPU_FX_CSD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[201]) /* 0x40013A40 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT0_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[202]) /* 0x40013A80 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT1_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[203]) /* 0x40013AC0 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT2_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[204]) /* 0x40013B00 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT3_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[205]) /* 0x40013B40 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT0_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[206]) /* 0x40013B80 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT1_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[207]) /* 0x40013BC0 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT2_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[208]) /* 0x40013C00 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT3_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[209]) /* 0x40013C40 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT4_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[210]) /* 0x40013C80 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT5_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[211]) /* 0x40013CC0 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT6_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[212]) /* 0x40013D00 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT7_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[213]) /* 0x40013D40 */ +#define PERI_MS_PPU_FX_LCD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[214]) /* 0x40013D80 */ +#define PERI_MS_PPU_FX_USBFS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[215]) /* 0x40013DC0 */ +#define PERI_MS_PPU_FX_SMIF0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[216]) /* 0x40013E00 */ +#define PERI_MS_PPU_FX_CANFD0_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[217]) /* 0x40013E40 */ +#define PERI_MS_PPU_FX_CANFD0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[218]) /* 0x40013E80 */ +#define PERI_MS_PPU_FX_CANFD0_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[219]) /* 0x40013EC0 */ +#define PERI_MS_PPU_FX_SCB0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[220]) /* 0x40013F00 */ +#define PERI_MS_PPU_FX_SCB1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[221]) /* 0x40013F40 */ +#define PERI_MS_PPU_FX_SCB2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[222]) /* 0x40013F80 */ +#define PERI_MS_PPU_FX_SCB4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[223]) /* 0x40013FC0 */ +#define PERI_MS_PPU_FX_SCB5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[224]) /* 0x40014000 */ +#define PERI_MS_PPU_FX_SCB6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[225]) /* 0x40014040 */ + +/******************************************************************************* +* CRYPTO +*******************************************************************************/ + +#define CRYPTO_BASE 0x40100000UL +#define CRYPTO ((CRYPTO_Type*) CRYPTO_BASE) /* 0x40100000 */ + +/******************************************************************************* +* CPUSS +*******************************************************************************/ + +#define CPUSS_BASE 0x40200000UL +#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40200000 */ + +/******************************************************************************* +* FAULT +*******************************************************************************/ + +#define FAULT_BASE 0x40210000UL +#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40210000 */ +#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40210000 */ +#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40210100 */ + +/******************************************************************************* +* IPC +*******************************************************************************/ + +#define IPC_BASE 0x40220000UL +#define IPC ((IPC_Type*) IPC_BASE) /* 0x40220000 */ +#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40220000 */ +#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40220020 */ +#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40220040 */ +#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40220060 */ +#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40220080 */ +#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402200A0 */ +#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402200C0 */ +#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402200E0 */ +#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40220100 */ +#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40220120 */ +#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40220140 */ +#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40220160 */ +#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40220180 */ +#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402201A0 */ +#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402201C0 */ +#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402201E0 */ +#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40221000 */ +#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40221020 */ +#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40221040 */ +#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40221060 */ +#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40221080 */ +#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402210A0 */ +#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402210C0 */ +#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402210E0 */ +#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40221100 */ +#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40221120 */ +#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40221140 */ +#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40221160 */ +#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40221180 */ +#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402211A0 */ +#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402211C0 */ +#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402211E0 */ + +/******************************************************************************* +* PROT +*******************************************************************************/ + +#define PROT_BASE 0x40230000UL +#define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ +#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ +#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ +#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402320C0 */ +#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40232100 */ +#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40232140 */ +#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40232180 */ +#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402321C0 */ +#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40232200 */ +#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40232240 */ +#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40232280 */ +#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402322C0 */ +#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40232300 */ +#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ +#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ +#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ + +/******************************************************************************* +* FLASHC +*******************************************************************************/ + +#define FLASHC_BASE 0x40240000UL +#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40240000 */ +#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4024F000 */ + +/******************************************************************************* +* SRSS +*******************************************************************************/ + +#define SRSS_BASE 0x40260000UL +#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ +#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */ +#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */ + +/******************************************************************************* +* BACKUP +*******************************************************************************/ + +#define BACKUP_BASE 0x40270000UL +#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ + +/******************************************************************************* +* DW +*******************************************************************************/ + +#define DW0_BASE 0x40280000UL +#define DW1_BASE 0x40290000UL +#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ +#define DW1 ((DW_Type*) DW1_BASE) /* 0x40290000 */ +#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40288000 */ +#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40288040 */ +#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40288080 */ +#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x402880C0 */ +#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40288100 */ +#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x40288140 */ +#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x40288180 */ +#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402881C0 */ +#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40288200 */ +#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40288240 */ +#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40288280 */ +#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x402882C0 */ +#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40288300 */ +#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x40288340 */ +#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x40288380 */ +#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402883C0 */ +#define DW0_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[16]) /* 0x40288400 */ +#define DW0_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[17]) /* 0x40288440 */ +#define DW0_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[18]) /* 0x40288480 */ +#define DW0_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[19]) /* 0x402884C0 */ +#define DW0_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[20]) /* 0x40288500 */ +#define DW0_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[21]) /* 0x40288540 */ +#define DW0_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[22]) /* 0x40288580 */ +#define DW0_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[23]) /* 0x402885C0 */ +#define DW0_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[24]) /* 0x40288600 */ +#define DW0_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[25]) /* 0x40288640 */ +#define DW0_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[26]) /* 0x40288680 */ +#define DW0_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[27]) /* 0x402886C0 */ +#define DW0_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[28]) /* 0x40288700 */ +#define DW0_CH_STRUCT29 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[29]) /* 0x40288740 */ +#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40298000 */ +#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40298040 */ +#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40298080 */ +#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x402980C0 */ +#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40298100 */ +#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x40298140 */ +#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x40298180 */ +#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402981C0 */ +#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40298200 */ +#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40298240 */ +#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40298280 */ +#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x402982C0 */ +#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40298300 */ +#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x40298340 */ +#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x40298380 */ +#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402983C0 */ +#define DW1_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[16]) /* 0x40298400 */ +#define DW1_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[17]) /* 0x40298440 */ +#define DW1_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[18]) /* 0x40298480 */ +#define DW1_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[19]) /* 0x402984C0 */ +#define DW1_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[20]) /* 0x40298500 */ +#define DW1_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[21]) /* 0x40298540 */ +#define DW1_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[22]) /* 0x40298580 */ +#define DW1_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[23]) /* 0x402985C0 */ +#define DW1_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[24]) /* 0x40298600 */ +#define DW1_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[25]) /* 0x40298640 */ +#define DW1_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[26]) /* 0x40298680 */ +#define DW1_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[27]) /* 0x402986C0 */ +#define DW1_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[28]) /* 0x40298700 */ +#define DW1_CH_STRUCT29 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[29]) /* 0x40298740 */ +#define DW1_CH_STRUCT30 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[30]) /* 0x40298780 */ +#define DW1_CH_STRUCT31 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[31]) /* 0x402987C0 */ + +/******************************************************************************* +* DMAC +*******************************************************************************/ + +#define DMAC_BASE 0x402A0000UL +#define DMAC ((DMAC_Type*) DMAC_BASE) /* 0x402A0000 */ +#define DMAC_CH0 ((DMAC_CH_Type*) &DMAC->CH[0]) /* 0x402A1000 */ +#define DMAC_CH1 ((DMAC_CH_Type*) &DMAC->CH[1]) /* 0x402A1100 */ + +/******************************************************************************* +* EFUSE +*******************************************************************************/ + +#define EFUSE_BASE 0x402C0000UL +#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ + +/******************************************************************************* +* HSIOM +*******************************************************************************/ + +#define HSIOM_BASE 0x40300000UL +#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40300000 */ +#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40300000 */ +#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40300010 */ +#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40300020 */ +#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40300030 */ +#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40300040 */ +#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40300050 */ +#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40300060 */ +#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40300070 */ +#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40300080 */ +#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40300090 */ +#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403000A0 */ +#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403000B0 */ +#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403000C0 */ +#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403000D0 */ +#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403000E0 */ + +/******************************************************************************* +* GPIO +*******************************************************************************/ + +#define GPIO_BASE 0x40310000UL +#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40310000 */ +#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40310000 */ +#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40310080 */ +#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40310100 */ +#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40310180 */ +#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40310200 */ +#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40310280 */ +#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40310300 */ +#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40310380 */ +#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40310400 */ +#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40310480 */ +#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40310500 */ +#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40310580 */ +#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40310600 */ +#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40310680 */ +#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40310700 */ + +/******************************************************************************* +* SMARTIO +*******************************************************************************/ + +#define SMARTIO_BASE 0x40320000UL +#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40320000 */ +#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40320900 */ + +/******************************************************************************* +* LPCOMP +*******************************************************************************/ + +#define LPCOMP_BASE 0x40350000UL +#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */ + +/******************************************************************************* +* CSD +*******************************************************************************/ + +#define CSD0_BASE 0x40360000UL +#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */ + +/******************************************************************************* +* TCPWM +*******************************************************************************/ + +#define TCPWM0_BASE 0x40380000UL +#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM0_GRP0 ((TCPWM_GRP_Type*) &TCPWM0->GRP[0]) /* 0x40380000 */ +#define TCPWM0_GRP1 ((TCPWM_GRP_Type*) &TCPWM0->GRP[1]) /* 0x40388000 */ +#define TCPWM0_GRP0_CNT0 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[0]) /* 0x40380000 */ +#define TCPWM0_GRP0_CNT1 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[1]) /* 0x40380080 */ +#define TCPWM0_GRP0_CNT2 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[2]) /* 0x40380100 */ +#define TCPWM0_GRP0_CNT3 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[3]) /* 0x40380180 */ +#define TCPWM0_GRP1_CNT0 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[0]) /* 0x40388000 */ +#define TCPWM0_GRP1_CNT1 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[1]) /* 0x40388080 */ +#define TCPWM0_GRP1_CNT2 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[2]) /* 0x40388100 */ +#define TCPWM0_GRP1_CNT3 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[3]) /* 0x40388180 */ +#define TCPWM0_GRP1_CNT4 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[4]) /* 0x40388200 */ +#define TCPWM0_GRP1_CNT5 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[5]) /* 0x40388280 */ +#define TCPWM0_GRP1_CNT6 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[6]) /* 0x40388300 */ +#define TCPWM0_GRP1_CNT7 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[7]) /* 0x40388380 */ + +/******************************************************************************* +* LCD +*******************************************************************************/ + +#define LCD0_BASE 0x403B0000UL +#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ + +/******************************************************************************* +* SMIF +*******************************************************************************/ + +#define SMIF0_BASE 0x40420000UL +#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ +#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ +#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ +#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ + +/******************************************************************************* +* CANFD +*******************************************************************************/ + +#define CANFD0_BASE 0x40520000UL +#define CANFD0 ((CANFD_Type*) CANFD0_BASE) /* 0x40520000 */ +#define CANFD0_CH0 ((CANFD_CH_Type*) &CANFD0->CH[0]) /* 0x40520000 */ +#define CANFD0_CH0_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[0].M_TTCAN) /* 0x40520000 */ + +/******************************************************************************* +* SCB +*******************************************************************************/ + +#define SCB0_BASE 0x40600000UL +#define SCB1_BASE 0x40610000UL +#define SCB2_BASE 0x40620000UL +#define SCB4_BASE 0x40640000UL +#define SCB5_BASE 0x40650000UL +#define SCB6_BASE 0x40660000UL +#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40600000 */ +#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40610000 */ +#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40620000 */ +#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40640000 */ +#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40650000 */ +#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40660000 */ + +/******************************************************************************* +* CTBM +*******************************************************************************/ + +#define CTBM0_BASE 0x40900000UL +#define CTBM0 ((CTBM_Type*) CTBM0_BASE) /* 0x40900000 */ + +/******************************************************************************* +* CTDAC +*******************************************************************************/ + +#define CTDAC0_BASE 0x40940000UL +#define CTDAC0 ((CTDAC_Type*) CTDAC0_BASE) /* 0x40940000 */ + +/******************************************************************************* +* SAR +*******************************************************************************/ + +#define SAR0_BASE 0x409B0000UL +#define SAR1_BASE 0x409C0000UL +#define SAR0 ((SAR_Type*) SAR0_BASE) /* 0x409B0000 */ +#define SAR1 ((SAR_Type*) SAR1_BASE) /* 0x409C0000 */ + +/******************************************************************************* +* PASS +*******************************************************************************/ + +#define PASS_BASE 0x409F0000UL +#define PASS ((PASS_Type*) PASS_BASE) /* 0x409F0000 */ +#define PASS_TIMER ((PASS_TIMER_Type*) &PASS->TIMER) /* 0x409F0100 */ +#define PASS_LPOSC ((PASS_LPOSC_Type*) &PASS->LPOSC) /* 0x409F0200 */ +#define PASS_FIFO0 ((PASS_FIFO_Type*) &PASS->FIFO[0]) /* 0x409F0300 */ +#define PASS_FIFO1 ((PASS_FIFO_Type*) &PASS->FIFO[1]) /* 0x409F0400 */ +#define PASS_AREFV2 ((PASS_AREFV2_Type*) &PASS->AREFV2) /* 0x409F0E00 */ + +/** \} CY8C6144AZI-S4F93 */ + +#endif /* _CY8C6144AZI_S4F93_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6144lqi_s4f12.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6144lqi_s4f12.h new file mode 100644 index 0000000000..bf9e69cc64 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6144lqi_s4f12.h @@ -0,0 +1,981 @@ +/***************************************************************************//** +* \file cy8c6144lqi_s4f12.h +* +* \brief +* CY8C6144LQI-S4F12 device header +* +* \note +* Generator version: 1.6.0.225 +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CY8C6144LQI_S4F12_H_ +#define _CY8C6144LQI_S4F12_H_ + +/** +* \addtogroup group_device CY8C6144LQI-S4F12 +* \{ +*/ + +/** +* \addtogroup Configuration_of_CMSIS +* \{ +*/ + +/******************************************************************************* +* Interrupt Number Definition +*******************************************************************************/ + +typedef enum { + /* ARM Cortex-M4 Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C6144LQI-S4F12 Peripheral Interrupt Numbers */ + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_6_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #6 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + pass_interrupt_sar_0_IRQn = 39, /*!< 39 [DeepSleep] SAR ADC0 interrupt */ + pass_interrupt_sar_1_IRQn = 40, /*!< 40 [DeepSleep] SAR ADC1 interrupt */ + pass_interrupt_ctb_IRQn = 41, /*!< 41 [DeepSleep] individual interrupt per CTB */ + pass_interrupt_fifo_0_IRQn = 43, /*!< 43 [DeepSleep] PASS FIFO0 */ + pass_interrupt_fifo_1_IRQn = 44, /*!< 44 [DeepSleep] PASS FIFO1 */ + scb_0_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #2 */ + scb_4_interrupt_IRQn = 49, /*!< 49 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 50, /*!< 50 [Active] Serial Communication Block #5 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_0_interrupts_256_IRQn = 131, /*!< 131 [Active] TCPWM #0, Counter #256 */ + tcpwm_0_interrupts_257_IRQn = 132, /*!< 132 [Active] TCPWM #0, Counter #257 */ + tcpwm_0_interrupts_258_IRQn = 133, /*!< 133 [Active] TCPWM #0, Counter #258 */ + tcpwm_0_interrupts_259_IRQn = 134, /*!< 134 [Active] TCPWM #0, Counter #259 */ + tcpwm_0_interrupts_260_IRQn = 135, /*!< 135 [Active] TCPWM #0, Counter #260 */ + tcpwm_0_interrupts_261_IRQn = 136, /*!< 136 [Active] TCPWM #0, Counter #261 */ + tcpwm_0_interrupts_262_IRQn = 137, /*!< 137 [Active] TCPWM #0, Counter #262 */ + tcpwm_0_interrupts_263_IRQn = 138, /*!< 138 [Active] TCPWM #0, Counter #263 */ + pass_interrupt_dacs_IRQn = 146, /*!< 146 [Active] Consolidated interrrupt for all DACs */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + canfd_0_interrupt0_IRQn = 168, /*!< 168 [Active] Can #0, Consolidated interrupt #0 */ + canfd_0_interrupts0_0_IRQn = 169, /*!< 169 [Active] CAN #0, Interrupt #0, Channel #0 */ + canfd_0_interrupts1_0_IRQn = 170, /*!< 170 [Active] CAN #0, Interrupt #1, Channel #0 */ + cpuss_interrupts_dw1_29_IRQn = 171, /*!< 171 [Active] CPUSS DataWire #1, Channel #29 */ + cpuss_interrupts_dw1_30_IRQn = 172, /*!< 172 [Active] CPUSS DataWire #1, Channel #30 */ + cpuss_interrupts_dw1_31_IRQn = 173, /*!< 173 [Active] CPUSS DataWire #1, Channel #31 */ + cpuss_interrupts_dw0_29_IRQn = 174, /*!< 174 [Active] CPUSS DataWire #0, Channel #29 */ + unconnected_IRQn = 240 /*!< 240 Unconnected */ +} IRQn_Type; + + +/******************************************************************************* +* Processor and Core Peripheral Section +*******************************************************************************/ + +/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __CM0P_PRESENT 0 /*!< CM0P present or not */ +#define __DTCM_PRESENT 0 /*!< DTCM present or not */ +#define __ICACHE_PRESENT 0 /*!< ICACHE present or not */ +#define __DCACHE_PRESENT 0 /*!< DCACHE present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + + +/* Memory Blocks */ +#define CY_ROM_BASE 0x00000000UL +#define CY_ROM_SIZE 0x00010000UL +#define CY_SRAM_BASE 0x08000000UL +#define CY_SRAM_SIZE 0x00020000UL +#define CY_FLASH_BASE 0x10000000UL +#define CY_FLASH_SIZE 0x00040000UL +#define CY_EM_EEPROM_BASE 0x14000000UL +#define CY_EM_EEPROM_SIZE 0x00000000UL +#define CY_SFLASH_BASE 0x16000000UL +#define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL +#define CY_EFUSE_BASE 0x402C0800UL +#define CY_EFUSE_SIZE 0x00000200UL +#define CY_CAN0MRAM_BASE 0x40530000UL +#define CY_CAN0MRAM_SIZE 0x00010000UL + +#include "system_psoc6.h" /*!< PSoC 6 System */ + +/* IP List */ +#define CY_IP_MXTTCANFD 1u +#define CY_IP_MXTTCANFD_INSTANCES 1u +#define CY_IP_MXTTCANFD_VERSION 1u +#define CY_IP_M4CPUSS 1u +#define CY_IP_M4CPUSS_INSTANCES 1u +#define CY_IP_M4CPUSS_VERSION 2u +#define CY_IP_M4CPUSS_DMAC 1u +#define CY_IP_M4CPUSS_DMAC_INSTANCES 1u +#define CY_IP_M4CPUSS_DMAC_VERSION 2u +#define CY_IP_M4CPUSS_DMA 1u +#define CY_IP_M4CPUSS_DMA_INSTANCES 2u +#define CY_IP_M4CPUSS_DMA_VERSION 2u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 2u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 6u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u + +#include "psoc6_04_config.h" +#include "gpio_psoc6_04_68_qfn.h" + +#define CY_DEVICE_PSOC6A256K +#define CY_SILICON_ID 0xEAD3110EUL +#define CY_HF_CLK_MAX_FREQ 150000000UL + +#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL + +/******************************************************************************* +* SFLASH +*******************************************************************************/ + +#define SFLASH_BASE 0x16000000UL +#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */ + +/******************************************************************************* +* PERI +*******************************************************************************/ + +#define PERI_BASE 0x40000000UL +#define PERI ((PERI_Type*) PERI_BASE) /* 0x40000000 */ +#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40004000 */ +#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40004020 */ +#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40004040 */ +#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x40004060 */ +#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40004080 */ +#define PERI_GR5 ((PERI_GR_Type*) &PERI->GR[5]) /* 0x400040A0 */ +#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x400040C0 */ +#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40004120 */ +#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40008000 */ +#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40008400 */ +#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40008800 */ +#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40008C00 */ +#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40009000 */ +#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40009400 */ +#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40009800 */ +#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40009C00 */ +#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ +#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ +#define PERI_TR_GR10 ((PERI_TR_GR_Type*) &PERI->TR_GR[10]) /* 0x4000A800 */ +#define PERI_TR_GR11 ((PERI_TR_GR_Type*) &PERI->TR_GR[11]) /* 0x4000AC00 */ +#define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ +#define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ +#define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ +#define PERI_TR_1TO1_GR3 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[3]) /* 0x4000CC00 */ +#define PERI_TR_1TO1_GR4 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[4]) /* 0x4000D000 */ +#define PERI_TR_1TO1_GR5 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[5]) /* 0x4000D400 */ +#define PERI_TR_1TO1_GR6 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[6]) /* 0x4000D800 */ +#define PERI_TR_1TO1_GR7 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[7]) /* 0x4000DC00 */ +#define PERI_TR_1TO1_GR8 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[8]) /* 0x4000E000 */ + +/******************************************************************************* +* PERI_MS +*******************************************************************************/ + +#define PERI_MS_BASE 0x40010000UL +#define PERI_MS ((PERI_MS_Type*) PERI_MS_BASE) /* 0x40010000 */ +#define PERI_MS_PPU_PR0 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[0]) /* 0x40010000 */ +#define PERI_MS_PPU_PR1 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[1]) /* 0x40010040 */ +#define PERI_MS_PPU_PR2 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[2]) /* 0x40010080 */ +#define PERI_MS_PPU_PR3 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[3]) /* 0x400100C0 */ +#define PERI_MS_PPU_PR4 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[4]) /* 0x40010100 */ +#define PERI_MS_PPU_PR5 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[5]) /* 0x40010140 */ +#define PERI_MS_PPU_PR6 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[6]) /* 0x40010180 */ +#define PERI_MS_PPU_PR7 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[7]) /* 0x400101C0 */ +#define PERI_MS_PPU_FX_PERI_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[0]) /* 0x40010800 */ +#define PERI_MS_PPU_FX_PERI_GR0_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[1]) /* 0x40010840 */ +#define PERI_MS_PPU_FX_PERI_GR1_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[2]) /* 0x40010880 */ +#define PERI_MS_PPU_FX_PERI_GR2_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[3]) /* 0x400108C0 */ +#define PERI_MS_PPU_FX_PERI_GR3_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[4]) /* 0x40010900 */ +#define PERI_MS_PPU_FX_PERI_GR4_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[5]) /* 0x40010940 */ +#define PERI_MS_PPU_FX_PERI_GR5_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[6]) /* 0x40010980 */ +#define PERI_MS_PPU_FX_PERI_GR6_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[7]) /* 0x400109C0 */ +#define PERI_MS_PPU_FX_PERI_GR9_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[8]) /* 0x40010A00 */ +#define PERI_MS_PPU_FX_PERI_TR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[9]) /* 0x40010A40 */ +#define PERI_MS_PPU_FX_CRYPTO_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[10]) /* 0x40010A80 */ +#define PERI_MS_PPU_FX_CRYPTO_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[11]) /* 0x40010AC0 */ +#define PERI_MS_PPU_FX_CRYPTO_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[12]) /* 0x40010B00 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[13]) /* 0x40010B40 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[14]) /* 0x40010B80 */ +#define PERI_MS_PPU_FX_CRYPTO_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[15]) /* 0x40010BC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[16]) /* 0x40010C00 */ +#define PERI_MS_PPU_FX_CPUSS_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[17]) /* 0x40010C40 */ +#define PERI_MS_PPU_FX_CPUSS_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[18]) /* 0x40010C80 */ +#define PERI_MS_PPU_FX_CPUSS_CM0_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[19]) /* 0x40010CC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[20]) /* 0x40010D00 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[21]) /* 0x40010D40 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT1_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[22]) /* 0x40010D80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT0_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[23]) /* 0x40010DC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT1_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[24]) /* 0x40010E00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT2_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[25]) /* 0x40010E40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT3_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[26]) /* 0x40010E80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT4_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[27]) /* 0x40010EC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT5_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[28]) /* 0x40010F00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT6_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[29]) /* 0x40010F40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT7_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[30]) /* 0x40010F80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT8_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[31]) /* 0x40010FC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT9_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[32]) /* 0x40011000 */ +#define PERI_MS_PPU_FX_IPC_STRUCT10_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[33]) /* 0x40011040 */ +#define PERI_MS_PPU_FX_IPC_STRUCT11_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[34]) /* 0x40011080 */ +#define PERI_MS_PPU_FX_IPC_STRUCT12_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[35]) /* 0x400110C0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT13_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[36]) /* 0x40011100 */ +#define PERI_MS_PPU_FX_IPC_STRUCT14_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[37]) /* 0x40011140 */ +#define PERI_MS_PPU_FX_IPC_STRUCT15_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[38]) /* 0x40011180 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT0_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[39]) /* 0x400111C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT1_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[40]) /* 0x40011200 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT2_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[41]) /* 0x40011240 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT3_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[42]) /* 0x40011280 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT4_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[43]) /* 0x400112C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT5_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[44]) /* 0x40011300 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT6_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[45]) /* 0x40011340 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT7_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[46]) /* 0x40011380 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT8_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[47]) /* 0x400113C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT9_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[48]) /* 0x40011400 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT10_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[49]) /* 0x40011440 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT11_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[50]) /* 0x40011480 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT12_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[51]) /* 0x400114C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT13_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[52]) /* 0x40011500 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT14_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[53]) /* 0x40011540 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT15_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[54]) /* 0x40011580 */ +#define PERI_MS_PPU_FX_PROT_SMPU_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[55]) /* 0x400115C0 */ +#define PERI_MS_PPU_FX_PROT_MPU0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[56]) /* 0x40011600 */ +#define PERI_MS_PPU_FX_PROT_MPU14_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[57]) /* 0x40011640 */ +#define PERI_MS_PPU_FX_PROT_MPU15_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[58]) /* 0x40011680 */ +#define PERI_MS_PPU_FX_FLASHC_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[59]) /* 0x400116C0 */ +#define PERI_MS_PPU_FX_FLASHC_CMD ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[60]) /* 0x40011700 */ +#define PERI_MS_PPU_FX_FLASHC_DFT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[61]) /* 0x40011740 */ +#define PERI_MS_PPU_FX_FLASHC_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[62]) /* 0x40011780 */ +#define PERI_MS_PPU_FX_FLASHC_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[63]) /* 0x400117C0 */ +#define PERI_MS_PPU_FX_FLASHC_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[64]) /* 0x40011800 */ +#define PERI_MS_PPU_FX_FLASHC_DW0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[65]) /* 0x40011840 */ +#define PERI_MS_PPU_FX_FLASHC_DW1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[66]) /* 0x40011880 */ +#define PERI_MS_PPU_FX_FLASHC_DMAC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[67]) /* 0x400118C0 */ +#define PERI_MS_PPU_FX_FLASHC_FM ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[68]) /* 0x40011900 */ +#define PERI_MS_PPU_FX_SRSS_MAIN1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[69]) /* 0x40011940 */ +#define PERI_MS_PPU_FX_SRSS_MAIN2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[70]) /* 0x40011980 */ +#define PERI_MS_PPU_FX_WDT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[71]) /* 0x400119C0 */ +#define PERI_MS_PPU_FX_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[72]) /* 0x40011A00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[73]) /* 0x40011A40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[74]) /* 0x40011A80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[75]) /* 0x40011AC0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[76]) /* 0x40011B00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[77]) /* 0x40011B40 */ +#define PERI_MS_PPU_FX_BACKUP_BACKUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[78]) /* 0x40011B80 */ +#define PERI_MS_PPU_FX_DW0_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[79]) /* 0x40011BC0 */ +#define PERI_MS_PPU_FX_DW1_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[80]) /* 0x40011C00 */ +#define PERI_MS_PPU_FX_DW0_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[81]) /* 0x40011C40 */ +#define PERI_MS_PPU_FX_DW1_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[82]) /* 0x40011C80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[83]) /* 0x40011CC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[84]) /* 0x40011D00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[85]) /* 0x40011D40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[86]) /* 0x40011D80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[87]) /* 0x40011DC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[88]) /* 0x40011E00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[89]) /* 0x40011E40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[90]) /* 0x40011E80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[91]) /* 0x40011EC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[92]) /* 0x40011F00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[93]) /* 0x40011F40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[94]) /* 0x40011F80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[95]) /* 0x40011FC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[96]) /* 0x40012000 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[97]) /* 0x40012040 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[98]) /* 0x40012080 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[99]) /* 0x400120C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[100]) /* 0x40012100 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[101]) /* 0x40012140 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[102]) /* 0x40012180 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[103]) /* 0x400121C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[104]) /* 0x40012200 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[105]) /* 0x40012240 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[106]) /* 0x40012280 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[107]) /* 0x400122C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[108]) /* 0x40012300 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[109]) /* 0x40012340 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[110]) /* 0x40012380 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[111]) /* 0x400123C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT29_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[112]) /* 0x40012400 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[113]) /* 0x40012440 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[114]) /* 0x40012480 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[115]) /* 0x400124C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[116]) /* 0x40012500 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[117]) /* 0x40012540 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[118]) /* 0x40012580 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[119]) /* 0x400125C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[120]) /* 0x40012600 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[121]) /* 0x40012640 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[122]) /* 0x40012680 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[123]) /* 0x400126C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[124]) /* 0x40012700 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[125]) /* 0x40012740 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[126]) /* 0x40012780 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[127]) /* 0x400127C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[128]) /* 0x40012800 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[129]) /* 0x40012840 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[130]) /* 0x40012880 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[131]) /* 0x400128C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[132]) /* 0x40012900 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[133]) /* 0x40012940 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[134]) /* 0x40012980 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[135]) /* 0x400129C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[136]) /* 0x40012A00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[137]) /* 0x40012A40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[138]) /* 0x40012A80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[139]) /* 0x40012AC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[140]) /* 0x40012B00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[141]) /* 0x40012B40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT29_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[142]) /* 0x40012B80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT30_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[143]) /* 0x40012BC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT31_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[144]) /* 0x40012C00 */ +#define PERI_MS_PPU_FX_DMAC_TOP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[145]) /* 0x40012C40 */ +#define PERI_MS_PPU_FX_DMAC_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[146]) /* 0x40012C80 */ +#define PERI_MS_PPU_FX_DMAC_CH1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[147]) /* 0x40012CC0 */ +#define PERI_MS_PPU_FX_EFUSE_CTL ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[148]) /* 0x40012D00 */ +#define PERI_MS_PPU_FX_EFUSE_DATA ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[149]) /* 0x40012D40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[150]) /* 0x40012D80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[151]) /* 0x40012DC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[152]) /* 0x40012E00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[153]) /* 0x40012E40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[154]) /* 0x40012E80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[155]) /* 0x40012EC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[156]) /* 0x40012F00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[157]) /* 0x40012F40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[158]) /* 0x40012F80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[159]) /* 0x40012FC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[160]) /* 0x40013000 */ +#define PERI_MS_PPU_FX_HSIOM_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[161]) /* 0x40013040 */ +#define PERI_MS_PPU_FX_HSIOM_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[162]) /* 0x40013080 */ +#define PERI_MS_PPU_FX_HSIOM_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[163]) /* 0x400130C0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[164]) /* 0x40013100 */ +#define PERI_MS_PPU_FX_HSIOM_AMUX ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[165]) /* 0x40013140 */ +#define PERI_MS_PPU_FX_HSIOM_MON ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[166]) /* 0x40013180 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[167]) /* 0x400131C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[168]) /* 0x40013200 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[169]) /* 0x40013240 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[170]) /* 0x40013280 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[171]) /* 0x400132C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[172]) /* 0x40013300 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[173]) /* 0x40013340 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[174]) /* 0x40013380 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[175]) /* 0x400133C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[176]) /* 0x40013400 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[177]) /* 0x40013440 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[178]) /* 0x40013480 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[179]) /* 0x400134C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[180]) /* 0x40013500 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[181]) /* 0x40013540 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[182]) /* 0x40013580 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[183]) /* 0x400135C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[184]) /* 0x40013600 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[185]) /* 0x40013640 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[186]) /* 0x40013680 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[187]) /* 0x400136C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[188]) /* 0x40013700 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[189]) /* 0x40013740 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[190]) /* 0x40013780 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[191]) /* 0x400137C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[192]) /* 0x40013800 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[193]) /* 0x40013840 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[194]) /* 0x40013880 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[195]) /* 0x400138C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[196]) /* 0x40013900 */ +#define PERI_MS_PPU_FX_GPIO_GPIO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[197]) /* 0x40013940 */ +#define PERI_MS_PPU_FX_GPIO_TEST ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[198]) /* 0x40013980 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[199]) /* 0x400139C0 */ +#define PERI_MS_PPU_FX_LPCOMP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[200]) /* 0x40013A00 */ +#define PERI_MS_PPU_FX_CSD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[201]) /* 0x40013A40 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT0_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[202]) /* 0x40013A80 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT1_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[203]) /* 0x40013AC0 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT2_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[204]) /* 0x40013B00 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT3_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[205]) /* 0x40013B40 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT0_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[206]) /* 0x40013B80 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT1_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[207]) /* 0x40013BC0 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT2_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[208]) /* 0x40013C00 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT3_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[209]) /* 0x40013C40 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT4_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[210]) /* 0x40013C80 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT5_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[211]) /* 0x40013CC0 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT6_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[212]) /* 0x40013D00 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT7_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[213]) /* 0x40013D40 */ +#define PERI_MS_PPU_FX_LCD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[214]) /* 0x40013D80 */ +#define PERI_MS_PPU_FX_USBFS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[215]) /* 0x40013DC0 */ +#define PERI_MS_PPU_FX_SMIF0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[216]) /* 0x40013E00 */ +#define PERI_MS_PPU_FX_CANFD0_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[217]) /* 0x40013E40 */ +#define PERI_MS_PPU_FX_CANFD0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[218]) /* 0x40013E80 */ +#define PERI_MS_PPU_FX_CANFD0_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[219]) /* 0x40013EC0 */ +#define PERI_MS_PPU_FX_SCB0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[220]) /* 0x40013F00 */ +#define PERI_MS_PPU_FX_SCB1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[221]) /* 0x40013F40 */ +#define PERI_MS_PPU_FX_SCB2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[222]) /* 0x40013F80 */ +#define PERI_MS_PPU_FX_SCB4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[223]) /* 0x40013FC0 */ +#define PERI_MS_PPU_FX_SCB5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[224]) /* 0x40014000 */ +#define PERI_MS_PPU_FX_SCB6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[225]) /* 0x40014040 */ + +/******************************************************************************* +* CPUSS +*******************************************************************************/ + +#define CPUSS_BASE 0x40200000UL +#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40200000 */ + +/******************************************************************************* +* FAULT +*******************************************************************************/ + +#define FAULT_BASE 0x40210000UL +#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40210000 */ +#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40210000 */ +#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40210100 */ + +/******************************************************************************* +* IPC +*******************************************************************************/ + +#define IPC_BASE 0x40220000UL +#define IPC ((IPC_Type*) IPC_BASE) /* 0x40220000 */ +#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40220000 */ +#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40220020 */ +#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40220040 */ +#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40220060 */ +#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40220080 */ +#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402200A0 */ +#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402200C0 */ +#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402200E0 */ +#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40220100 */ +#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40220120 */ +#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40220140 */ +#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40220160 */ +#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40220180 */ +#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402201A0 */ +#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402201C0 */ +#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402201E0 */ +#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40221000 */ +#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40221020 */ +#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40221040 */ +#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40221060 */ +#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40221080 */ +#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402210A0 */ +#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402210C0 */ +#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402210E0 */ +#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40221100 */ +#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40221120 */ +#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40221140 */ +#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40221160 */ +#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40221180 */ +#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402211A0 */ +#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402211C0 */ +#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402211E0 */ + +/******************************************************************************* +* PROT +*******************************************************************************/ + +#define PROT_BASE 0x40230000UL +#define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ +#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ +#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ +#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402320C0 */ +#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40232100 */ +#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40232140 */ +#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40232180 */ +#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402321C0 */ +#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40232200 */ +#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40232240 */ +#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40232280 */ +#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402322C0 */ +#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40232300 */ +#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ +#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ +#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ + +/******************************************************************************* +* FLASHC +*******************************************************************************/ + +#define FLASHC_BASE 0x40240000UL +#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40240000 */ +#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4024F000 */ + +/******************************************************************************* +* SRSS +*******************************************************************************/ + +#define SRSS_BASE 0x40260000UL +#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ +#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */ +#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */ + +/******************************************************************************* +* BACKUP +*******************************************************************************/ + +#define BACKUP_BASE 0x40270000UL +#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ + +/******************************************************************************* +* DW +*******************************************************************************/ + +#define DW0_BASE 0x40280000UL +#define DW1_BASE 0x40290000UL +#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ +#define DW1 ((DW_Type*) DW1_BASE) /* 0x40290000 */ +#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40288000 */ +#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40288040 */ +#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40288080 */ +#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x402880C0 */ +#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40288100 */ +#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x40288140 */ +#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x40288180 */ +#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402881C0 */ +#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40288200 */ +#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40288240 */ +#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40288280 */ +#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x402882C0 */ +#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40288300 */ +#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x40288340 */ +#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x40288380 */ +#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402883C0 */ +#define DW0_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[16]) /* 0x40288400 */ +#define DW0_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[17]) /* 0x40288440 */ +#define DW0_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[18]) /* 0x40288480 */ +#define DW0_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[19]) /* 0x402884C0 */ +#define DW0_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[20]) /* 0x40288500 */ +#define DW0_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[21]) /* 0x40288540 */ +#define DW0_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[22]) /* 0x40288580 */ +#define DW0_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[23]) /* 0x402885C0 */ +#define DW0_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[24]) /* 0x40288600 */ +#define DW0_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[25]) /* 0x40288640 */ +#define DW0_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[26]) /* 0x40288680 */ +#define DW0_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[27]) /* 0x402886C0 */ +#define DW0_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[28]) /* 0x40288700 */ +#define DW0_CH_STRUCT29 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[29]) /* 0x40288740 */ +#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40298000 */ +#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40298040 */ +#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40298080 */ +#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x402980C0 */ +#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40298100 */ +#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x40298140 */ +#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x40298180 */ +#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402981C0 */ +#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40298200 */ +#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40298240 */ +#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40298280 */ +#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x402982C0 */ +#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40298300 */ +#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x40298340 */ +#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x40298380 */ +#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402983C0 */ +#define DW1_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[16]) /* 0x40298400 */ +#define DW1_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[17]) /* 0x40298440 */ +#define DW1_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[18]) /* 0x40298480 */ +#define DW1_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[19]) /* 0x402984C0 */ +#define DW1_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[20]) /* 0x40298500 */ +#define DW1_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[21]) /* 0x40298540 */ +#define DW1_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[22]) /* 0x40298580 */ +#define DW1_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[23]) /* 0x402985C0 */ +#define DW1_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[24]) /* 0x40298600 */ +#define DW1_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[25]) /* 0x40298640 */ +#define DW1_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[26]) /* 0x40298680 */ +#define DW1_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[27]) /* 0x402986C0 */ +#define DW1_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[28]) /* 0x40298700 */ +#define DW1_CH_STRUCT29 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[29]) /* 0x40298740 */ +#define DW1_CH_STRUCT30 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[30]) /* 0x40298780 */ +#define DW1_CH_STRUCT31 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[31]) /* 0x402987C0 */ + +/******************************************************************************* +* DMAC +*******************************************************************************/ + +#define DMAC_BASE 0x402A0000UL +#define DMAC ((DMAC_Type*) DMAC_BASE) /* 0x402A0000 */ +#define DMAC_CH0 ((DMAC_CH_Type*) &DMAC->CH[0]) /* 0x402A1000 */ +#define DMAC_CH1 ((DMAC_CH_Type*) &DMAC->CH[1]) /* 0x402A1100 */ + +/******************************************************************************* +* EFUSE +*******************************************************************************/ + +#define EFUSE_BASE 0x402C0000UL +#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ + +/******************************************************************************* +* HSIOM +*******************************************************************************/ + +#define HSIOM_BASE 0x40300000UL +#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40300000 */ +#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40300000 */ +#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40300010 */ +#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40300020 */ +#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40300030 */ +#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40300040 */ +#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40300050 */ +#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40300060 */ +#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40300070 */ +#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40300080 */ +#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40300090 */ +#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403000A0 */ +#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403000B0 */ +#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403000C0 */ +#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403000D0 */ +#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403000E0 */ + +/******************************************************************************* +* GPIO +*******************************************************************************/ + +#define GPIO_BASE 0x40310000UL +#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40310000 */ +#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40310000 */ +#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40310080 */ +#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40310100 */ +#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40310180 */ +#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40310200 */ +#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40310280 */ +#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40310300 */ +#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40310380 */ +#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40310400 */ +#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40310480 */ +#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40310500 */ +#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40310580 */ +#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40310600 */ +#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40310680 */ +#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40310700 */ + +/******************************************************************************* +* SMARTIO +*******************************************************************************/ + +#define SMARTIO_BASE 0x40320000UL +#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40320000 */ +#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40320900 */ + +/******************************************************************************* +* LPCOMP +*******************************************************************************/ + +#define LPCOMP_BASE 0x40350000UL +#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */ + +/******************************************************************************* +* CSD +*******************************************************************************/ + +#define CSD0_BASE 0x40360000UL +#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */ + +/******************************************************************************* +* TCPWM +*******************************************************************************/ + +#define TCPWM0_BASE 0x40380000UL +#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM0_GRP0 ((TCPWM_GRP_Type*) &TCPWM0->GRP[0]) /* 0x40380000 */ +#define TCPWM0_GRP1 ((TCPWM_GRP_Type*) &TCPWM0->GRP[1]) /* 0x40388000 */ +#define TCPWM0_GRP0_CNT0 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[0]) /* 0x40380000 */ +#define TCPWM0_GRP0_CNT1 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[1]) /* 0x40380080 */ +#define TCPWM0_GRP0_CNT2 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[2]) /* 0x40380100 */ +#define TCPWM0_GRP0_CNT3 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[3]) /* 0x40380180 */ +#define TCPWM0_GRP1_CNT0 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[0]) /* 0x40388000 */ +#define TCPWM0_GRP1_CNT1 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[1]) /* 0x40388080 */ +#define TCPWM0_GRP1_CNT2 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[2]) /* 0x40388100 */ +#define TCPWM0_GRP1_CNT3 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[3]) /* 0x40388180 */ +#define TCPWM0_GRP1_CNT4 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[4]) /* 0x40388200 */ +#define TCPWM0_GRP1_CNT5 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[5]) /* 0x40388280 */ +#define TCPWM0_GRP1_CNT6 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[6]) /* 0x40388300 */ +#define TCPWM0_GRP1_CNT7 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[7]) /* 0x40388380 */ + +/******************************************************************************* +* LCD +*******************************************************************************/ + +#define LCD0_BASE 0x403B0000UL +#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ + +/******************************************************************************* +* USBFS +*******************************************************************************/ + +#define USBFS0_BASE 0x403F0000UL +#define USBFS0 ((USBFS_Type*) USBFS0_BASE) /* 0x403F0000 */ +#define USBFS0_USBDEV ((USBFS_USBDEV_Type*) &USBFS0->USBDEV) /* 0x403F0000 */ +#define USBFS0_USBLPM ((USBFS_USBLPM_Type*) &USBFS0->USBLPM) /* 0x403F2000 */ +#define USBFS0_USBHOST ((USBFS_USBHOST_Type*) &USBFS0->USBHOST) /* 0x403F4000 */ + +/******************************************************************************* +* SMIF +*******************************************************************************/ + +#define SMIF0_BASE 0x40420000UL +#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ +#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ +#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ +#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ + +/******************************************************************************* +* CANFD +*******************************************************************************/ + +#define CANFD0_BASE 0x40520000UL +#define CANFD0 ((CANFD_Type*) CANFD0_BASE) /* 0x40520000 */ +#define CANFD0_CH0 ((CANFD_CH_Type*) &CANFD0->CH[0]) /* 0x40520000 */ +#define CANFD0_CH0_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[0].M_TTCAN) /* 0x40520000 */ + +/******************************************************************************* +* SCB +*******************************************************************************/ + +#define SCB0_BASE 0x40600000UL +#define SCB1_BASE 0x40610000UL +#define SCB2_BASE 0x40620000UL +#define SCB4_BASE 0x40640000UL +#define SCB5_BASE 0x40650000UL +#define SCB6_BASE 0x40660000UL +#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40600000 */ +#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40610000 */ +#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40620000 */ +#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40640000 */ +#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40650000 */ +#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40660000 */ + +/******************************************************************************* +* CTBM +*******************************************************************************/ + +#define CTBM0_BASE 0x40900000UL +#define CTBM0 ((CTBM_Type*) CTBM0_BASE) /* 0x40900000 */ + +/******************************************************************************* +* CTDAC +*******************************************************************************/ + +#define CTDAC0_BASE 0x40940000UL +#define CTDAC0 ((CTDAC_Type*) CTDAC0_BASE) /* 0x40940000 */ + +/******************************************************************************* +* SAR +*******************************************************************************/ + +#define SAR0_BASE 0x409B0000UL +#define SAR0 ((SAR_Type*) SAR0_BASE) /* 0x409B0000 */ + +/******************************************************************************* +* PASS +*******************************************************************************/ + +#define PASS_BASE 0x409F0000UL +#define PASS ((PASS_Type*) PASS_BASE) /* 0x409F0000 */ +#define PASS_TIMER ((PASS_TIMER_Type*) &PASS->TIMER) /* 0x409F0100 */ +#define PASS_LPOSC ((PASS_LPOSC_Type*) &PASS->LPOSC) /* 0x409F0200 */ +#define PASS_FIFO0 ((PASS_FIFO_Type*) &PASS->FIFO[0]) /* 0x409F0300 */ +#define PASS_FIFO1 ((PASS_FIFO_Type*) &PASS->FIFO[1]) /* 0x409F0400 */ +#define PASS_AREFV2 ((PASS_AREFV2_Type*) &PASS->AREFV2) /* 0x409F0E00 */ + +/** \} CY8C6144LQI-S4F12 */ + +#endif /* _CY8C6144LQI_S4F12_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6144lqi_s4f62.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6144lqi_s4f62.h new file mode 100644 index 0000000000..d2a6a3c812 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6144lqi_s4f62.h @@ -0,0 +1,981 @@ +/***************************************************************************//** +* \file cy8c6144lqi_s4f62.h +* +* \brief +* CY8C6144LQI-S4F62 device header +* +* \note +* Generator version: 1.6.0.225 +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CY8C6144LQI_S4F62_H_ +#define _CY8C6144LQI_S4F62_H_ + +/** +* \addtogroup group_device CY8C6144LQI-S4F62 +* \{ +*/ + +/** +* \addtogroup Configuration_of_CMSIS +* \{ +*/ + +/******************************************************************************* +* Interrupt Number Definition +*******************************************************************************/ + +typedef enum { + /* ARM Cortex-M4 Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C6144LQI-S4F62 Peripheral Interrupt Numbers */ + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_6_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #6 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + pass_interrupt_sar_0_IRQn = 39, /*!< 39 [DeepSleep] SAR ADC0 interrupt */ + pass_interrupt_sar_1_IRQn = 40, /*!< 40 [DeepSleep] SAR ADC1 interrupt */ + pass_interrupt_ctb_IRQn = 41, /*!< 41 [DeepSleep] individual interrupt per CTB */ + pass_interrupt_fifo_0_IRQn = 43, /*!< 43 [DeepSleep] PASS FIFO0 */ + pass_interrupt_fifo_1_IRQn = 44, /*!< 44 [DeepSleep] PASS FIFO1 */ + scb_0_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #2 */ + scb_4_interrupt_IRQn = 49, /*!< 49 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 50, /*!< 50 [Active] Serial Communication Block #5 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_0_interrupts_256_IRQn = 131, /*!< 131 [Active] TCPWM #0, Counter #256 */ + tcpwm_0_interrupts_257_IRQn = 132, /*!< 132 [Active] TCPWM #0, Counter #257 */ + tcpwm_0_interrupts_258_IRQn = 133, /*!< 133 [Active] TCPWM #0, Counter #258 */ + tcpwm_0_interrupts_259_IRQn = 134, /*!< 134 [Active] TCPWM #0, Counter #259 */ + tcpwm_0_interrupts_260_IRQn = 135, /*!< 135 [Active] TCPWM #0, Counter #260 */ + tcpwm_0_interrupts_261_IRQn = 136, /*!< 136 [Active] TCPWM #0, Counter #261 */ + tcpwm_0_interrupts_262_IRQn = 137, /*!< 137 [Active] TCPWM #0, Counter #262 */ + tcpwm_0_interrupts_263_IRQn = 138, /*!< 138 [Active] TCPWM #0, Counter #263 */ + pass_interrupt_dacs_IRQn = 146, /*!< 146 [Active] Consolidated interrrupt for all DACs */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + canfd_0_interrupt0_IRQn = 168, /*!< 168 [Active] Can #0, Consolidated interrupt #0 */ + canfd_0_interrupts0_0_IRQn = 169, /*!< 169 [Active] CAN #0, Interrupt #0, Channel #0 */ + canfd_0_interrupts1_0_IRQn = 170, /*!< 170 [Active] CAN #0, Interrupt #1, Channel #0 */ + cpuss_interrupts_dw1_29_IRQn = 171, /*!< 171 [Active] CPUSS DataWire #1, Channel #29 */ + cpuss_interrupts_dw1_30_IRQn = 172, /*!< 172 [Active] CPUSS DataWire #1, Channel #30 */ + cpuss_interrupts_dw1_31_IRQn = 173, /*!< 173 [Active] CPUSS DataWire #1, Channel #31 */ + cpuss_interrupts_dw0_29_IRQn = 174, /*!< 174 [Active] CPUSS DataWire #0, Channel #29 */ + unconnected_IRQn = 240 /*!< 240 Unconnected */ +} IRQn_Type; + + +/******************************************************************************* +* Processor and Core Peripheral Section +*******************************************************************************/ + +/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __CM0P_PRESENT 0 /*!< CM0P present or not */ +#define __DTCM_PRESENT 0 /*!< DTCM present or not */ +#define __ICACHE_PRESENT 0 /*!< ICACHE present or not */ +#define __DCACHE_PRESENT 0 /*!< DCACHE present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + + +/* Memory Blocks */ +#define CY_ROM_BASE 0x00000000UL +#define CY_ROM_SIZE 0x00010000UL +#define CY_SRAM_BASE 0x08000000UL +#define CY_SRAM_SIZE 0x00020000UL +#define CY_FLASH_BASE 0x10000000UL +#define CY_FLASH_SIZE 0x00040000UL +#define CY_EM_EEPROM_BASE 0x14000000UL +#define CY_EM_EEPROM_SIZE 0x00000000UL +#define CY_SFLASH_BASE 0x16000000UL +#define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL +#define CY_EFUSE_BASE 0x402C0800UL +#define CY_EFUSE_SIZE 0x00000200UL +#define CY_CAN0MRAM_BASE 0x40530000UL +#define CY_CAN0MRAM_SIZE 0x00010000UL + +#include "system_psoc6.h" /*!< PSoC 6 System */ + +/* IP List */ +#define CY_IP_MXTTCANFD 1u +#define CY_IP_MXTTCANFD_INSTANCES 1u +#define CY_IP_MXTTCANFD_VERSION 1u +#define CY_IP_M4CPUSS 1u +#define CY_IP_M4CPUSS_INSTANCES 1u +#define CY_IP_M4CPUSS_VERSION 2u +#define CY_IP_M4CPUSS_DMAC 1u +#define CY_IP_M4CPUSS_DMAC_INSTANCES 1u +#define CY_IP_M4CPUSS_DMAC_VERSION 2u +#define CY_IP_M4CPUSS_DMA 1u +#define CY_IP_M4CPUSS_DMA_INSTANCES 2u +#define CY_IP_M4CPUSS_DMA_VERSION 2u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 2u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 6u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u + +#include "psoc6_04_config.h" +#include "gpio_psoc6_04_68_qfn.h" + +#define CY_DEVICE_PSOC6A256K +#define CY_SILICON_ID 0xEAD1110EUL +#define CY_HF_CLK_MAX_FREQ 150000000UL + +#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL + +/******************************************************************************* +* SFLASH +*******************************************************************************/ + +#define SFLASH_BASE 0x16000000UL +#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */ + +/******************************************************************************* +* PERI +*******************************************************************************/ + +#define PERI_BASE 0x40000000UL +#define PERI ((PERI_Type*) PERI_BASE) /* 0x40000000 */ +#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40004000 */ +#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40004020 */ +#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40004040 */ +#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x40004060 */ +#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40004080 */ +#define PERI_GR5 ((PERI_GR_Type*) &PERI->GR[5]) /* 0x400040A0 */ +#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x400040C0 */ +#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40004120 */ +#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40008000 */ +#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40008400 */ +#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40008800 */ +#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40008C00 */ +#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40009000 */ +#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40009400 */ +#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40009800 */ +#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40009C00 */ +#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ +#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ +#define PERI_TR_GR10 ((PERI_TR_GR_Type*) &PERI->TR_GR[10]) /* 0x4000A800 */ +#define PERI_TR_GR11 ((PERI_TR_GR_Type*) &PERI->TR_GR[11]) /* 0x4000AC00 */ +#define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ +#define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ +#define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ +#define PERI_TR_1TO1_GR3 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[3]) /* 0x4000CC00 */ +#define PERI_TR_1TO1_GR4 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[4]) /* 0x4000D000 */ +#define PERI_TR_1TO1_GR5 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[5]) /* 0x4000D400 */ +#define PERI_TR_1TO1_GR6 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[6]) /* 0x4000D800 */ +#define PERI_TR_1TO1_GR7 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[7]) /* 0x4000DC00 */ +#define PERI_TR_1TO1_GR8 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[8]) /* 0x4000E000 */ + +/******************************************************************************* +* PERI_MS +*******************************************************************************/ + +#define PERI_MS_BASE 0x40010000UL +#define PERI_MS ((PERI_MS_Type*) PERI_MS_BASE) /* 0x40010000 */ +#define PERI_MS_PPU_PR0 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[0]) /* 0x40010000 */ +#define PERI_MS_PPU_PR1 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[1]) /* 0x40010040 */ +#define PERI_MS_PPU_PR2 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[2]) /* 0x40010080 */ +#define PERI_MS_PPU_PR3 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[3]) /* 0x400100C0 */ +#define PERI_MS_PPU_PR4 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[4]) /* 0x40010100 */ +#define PERI_MS_PPU_PR5 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[5]) /* 0x40010140 */ +#define PERI_MS_PPU_PR6 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[6]) /* 0x40010180 */ +#define PERI_MS_PPU_PR7 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[7]) /* 0x400101C0 */ +#define PERI_MS_PPU_FX_PERI_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[0]) /* 0x40010800 */ +#define PERI_MS_PPU_FX_PERI_GR0_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[1]) /* 0x40010840 */ +#define PERI_MS_PPU_FX_PERI_GR1_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[2]) /* 0x40010880 */ +#define PERI_MS_PPU_FX_PERI_GR2_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[3]) /* 0x400108C0 */ +#define PERI_MS_PPU_FX_PERI_GR3_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[4]) /* 0x40010900 */ +#define PERI_MS_PPU_FX_PERI_GR4_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[5]) /* 0x40010940 */ +#define PERI_MS_PPU_FX_PERI_GR5_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[6]) /* 0x40010980 */ +#define PERI_MS_PPU_FX_PERI_GR6_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[7]) /* 0x400109C0 */ +#define PERI_MS_PPU_FX_PERI_GR9_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[8]) /* 0x40010A00 */ +#define PERI_MS_PPU_FX_PERI_TR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[9]) /* 0x40010A40 */ +#define PERI_MS_PPU_FX_CRYPTO_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[10]) /* 0x40010A80 */ +#define PERI_MS_PPU_FX_CRYPTO_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[11]) /* 0x40010AC0 */ +#define PERI_MS_PPU_FX_CRYPTO_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[12]) /* 0x40010B00 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[13]) /* 0x40010B40 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[14]) /* 0x40010B80 */ +#define PERI_MS_PPU_FX_CRYPTO_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[15]) /* 0x40010BC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[16]) /* 0x40010C00 */ +#define PERI_MS_PPU_FX_CPUSS_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[17]) /* 0x40010C40 */ +#define PERI_MS_PPU_FX_CPUSS_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[18]) /* 0x40010C80 */ +#define PERI_MS_PPU_FX_CPUSS_CM0_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[19]) /* 0x40010CC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[20]) /* 0x40010D00 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[21]) /* 0x40010D40 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT1_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[22]) /* 0x40010D80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT0_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[23]) /* 0x40010DC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT1_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[24]) /* 0x40010E00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT2_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[25]) /* 0x40010E40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT3_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[26]) /* 0x40010E80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT4_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[27]) /* 0x40010EC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT5_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[28]) /* 0x40010F00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT6_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[29]) /* 0x40010F40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT7_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[30]) /* 0x40010F80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT8_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[31]) /* 0x40010FC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT9_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[32]) /* 0x40011000 */ +#define PERI_MS_PPU_FX_IPC_STRUCT10_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[33]) /* 0x40011040 */ +#define PERI_MS_PPU_FX_IPC_STRUCT11_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[34]) /* 0x40011080 */ +#define PERI_MS_PPU_FX_IPC_STRUCT12_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[35]) /* 0x400110C0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT13_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[36]) /* 0x40011100 */ +#define PERI_MS_PPU_FX_IPC_STRUCT14_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[37]) /* 0x40011140 */ +#define PERI_MS_PPU_FX_IPC_STRUCT15_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[38]) /* 0x40011180 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT0_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[39]) /* 0x400111C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT1_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[40]) /* 0x40011200 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT2_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[41]) /* 0x40011240 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT3_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[42]) /* 0x40011280 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT4_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[43]) /* 0x400112C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT5_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[44]) /* 0x40011300 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT6_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[45]) /* 0x40011340 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT7_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[46]) /* 0x40011380 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT8_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[47]) /* 0x400113C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT9_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[48]) /* 0x40011400 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT10_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[49]) /* 0x40011440 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT11_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[50]) /* 0x40011480 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT12_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[51]) /* 0x400114C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT13_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[52]) /* 0x40011500 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT14_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[53]) /* 0x40011540 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT15_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[54]) /* 0x40011580 */ +#define PERI_MS_PPU_FX_PROT_SMPU_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[55]) /* 0x400115C0 */ +#define PERI_MS_PPU_FX_PROT_MPU0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[56]) /* 0x40011600 */ +#define PERI_MS_PPU_FX_PROT_MPU14_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[57]) /* 0x40011640 */ +#define PERI_MS_PPU_FX_PROT_MPU15_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[58]) /* 0x40011680 */ +#define PERI_MS_PPU_FX_FLASHC_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[59]) /* 0x400116C0 */ +#define PERI_MS_PPU_FX_FLASHC_CMD ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[60]) /* 0x40011700 */ +#define PERI_MS_PPU_FX_FLASHC_DFT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[61]) /* 0x40011740 */ +#define PERI_MS_PPU_FX_FLASHC_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[62]) /* 0x40011780 */ +#define PERI_MS_PPU_FX_FLASHC_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[63]) /* 0x400117C0 */ +#define PERI_MS_PPU_FX_FLASHC_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[64]) /* 0x40011800 */ +#define PERI_MS_PPU_FX_FLASHC_DW0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[65]) /* 0x40011840 */ +#define PERI_MS_PPU_FX_FLASHC_DW1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[66]) /* 0x40011880 */ +#define PERI_MS_PPU_FX_FLASHC_DMAC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[67]) /* 0x400118C0 */ +#define PERI_MS_PPU_FX_FLASHC_FM ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[68]) /* 0x40011900 */ +#define PERI_MS_PPU_FX_SRSS_MAIN1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[69]) /* 0x40011940 */ +#define PERI_MS_PPU_FX_SRSS_MAIN2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[70]) /* 0x40011980 */ +#define PERI_MS_PPU_FX_WDT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[71]) /* 0x400119C0 */ +#define PERI_MS_PPU_FX_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[72]) /* 0x40011A00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[73]) /* 0x40011A40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[74]) /* 0x40011A80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[75]) /* 0x40011AC0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[76]) /* 0x40011B00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[77]) /* 0x40011B40 */ +#define PERI_MS_PPU_FX_BACKUP_BACKUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[78]) /* 0x40011B80 */ +#define PERI_MS_PPU_FX_DW0_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[79]) /* 0x40011BC0 */ +#define PERI_MS_PPU_FX_DW1_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[80]) /* 0x40011C00 */ +#define PERI_MS_PPU_FX_DW0_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[81]) /* 0x40011C40 */ +#define PERI_MS_PPU_FX_DW1_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[82]) /* 0x40011C80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[83]) /* 0x40011CC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[84]) /* 0x40011D00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[85]) /* 0x40011D40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[86]) /* 0x40011D80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[87]) /* 0x40011DC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[88]) /* 0x40011E00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[89]) /* 0x40011E40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[90]) /* 0x40011E80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[91]) /* 0x40011EC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[92]) /* 0x40011F00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[93]) /* 0x40011F40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[94]) /* 0x40011F80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[95]) /* 0x40011FC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[96]) /* 0x40012000 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[97]) /* 0x40012040 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[98]) /* 0x40012080 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[99]) /* 0x400120C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[100]) /* 0x40012100 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[101]) /* 0x40012140 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[102]) /* 0x40012180 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[103]) /* 0x400121C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[104]) /* 0x40012200 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[105]) /* 0x40012240 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[106]) /* 0x40012280 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[107]) /* 0x400122C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[108]) /* 0x40012300 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[109]) /* 0x40012340 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[110]) /* 0x40012380 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[111]) /* 0x400123C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT29_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[112]) /* 0x40012400 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[113]) /* 0x40012440 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[114]) /* 0x40012480 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[115]) /* 0x400124C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[116]) /* 0x40012500 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[117]) /* 0x40012540 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[118]) /* 0x40012580 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[119]) /* 0x400125C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[120]) /* 0x40012600 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[121]) /* 0x40012640 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[122]) /* 0x40012680 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[123]) /* 0x400126C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[124]) /* 0x40012700 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[125]) /* 0x40012740 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[126]) /* 0x40012780 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[127]) /* 0x400127C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[128]) /* 0x40012800 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[129]) /* 0x40012840 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[130]) /* 0x40012880 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[131]) /* 0x400128C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[132]) /* 0x40012900 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[133]) /* 0x40012940 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[134]) /* 0x40012980 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[135]) /* 0x400129C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[136]) /* 0x40012A00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[137]) /* 0x40012A40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[138]) /* 0x40012A80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[139]) /* 0x40012AC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[140]) /* 0x40012B00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[141]) /* 0x40012B40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT29_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[142]) /* 0x40012B80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT30_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[143]) /* 0x40012BC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT31_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[144]) /* 0x40012C00 */ +#define PERI_MS_PPU_FX_DMAC_TOP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[145]) /* 0x40012C40 */ +#define PERI_MS_PPU_FX_DMAC_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[146]) /* 0x40012C80 */ +#define PERI_MS_PPU_FX_DMAC_CH1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[147]) /* 0x40012CC0 */ +#define PERI_MS_PPU_FX_EFUSE_CTL ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[148]) /* 0x40012D00 */ +#define PERI_MS_PPU_FX_EFUSE_DATA ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[149]) /* 0x40012D40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[150]) /* 0x40012D80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[151]) /* 0x40012DC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[152]) /* 0x40012E00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[153]) /* 0x40012E40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[154]) /* 0x40012E80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[155]) /* 0x40012EC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[156]) /* 0x40012F00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[157]) /* 0x40012F40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[158]) /* 0x40012F80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[159]) /* 0x40012FC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[160]) /* 0x40013000 */ +#define PERI_MS_PPU_FX_HSIOM_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[161]) /* 0x40013040 */ +#define PERI_MS_PPU_FX_HSIOM_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[162]) /* 0x40013080 */ +#define PERI_MS_PPU_FX_HSIOM_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[163]) /* 0x400130C0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[164]) /* 0x40013100 */ +#define PERI_MS_PPU_FX_HSIOM_AMUX ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[165]) /* 0x40013140 */ +#define PERI_MS_PPU_FX_HSIOM_MON ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[166]) /* 0x40013180 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[167]) /* 0x400131C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[168]) /* 0x40013200 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[169]) /* 0x40013240 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[170]) /* 0x40013280 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[171]) /* 0x400132C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[172]) /* 0x40013300 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[173]) /* 0x40013340 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[174]) /* 0x40013380 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[175]) /* 0x400133C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[176]) /* 0x40013400 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[177]) /* 0x40013440 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[178]) /* 0x40013480 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[179]) /* 0x400134C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[180]) /* 0x40013500 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[181]) /* 0x40013540 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[182]) /* 0x40013580 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[183]) /* 0x400135C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[184]) /* 0x40013600 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[185]) /* 0x40013640 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[186]) /* 0x40013680 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[187]) /* 0x400136C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[188]) /* 0x40013700 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[189]) /* 0x40013740 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[190]) /* 0x40013780 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[191]) /* 0x400137C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[192]) /* 0x40013800 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[193]) /* 0x40013840 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[194]) /* 0x40013880 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[195]) /* 0x400138C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[196]) /* 0x40013900 */ +#define PERI_MS_PPU_FX_GPIO_GPIO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[197]) /* 0x40013940 */ +#define PERI_MS_PPU_FX_GPIO_TEST ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[198]) /* 0x40013980 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[199]) /* 0x400139C0 */ +#define PERI_MS_PPU_FX_LPCOMP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[200]) /* 0x40013A00 */ +#define PERI_MS_PPU_FX_CSD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[201]) /* 0x40013A40 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT0_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[202]) /* 0x40013A80 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT1_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[203]) /* 0x40013AC0 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT2_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[204]) /* 0x40013B00 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT3_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[205]) /* 0x40013B40 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT0_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[206]) /* 0x40013B80 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT1_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[207]) /* 0x40013BC0 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT2_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[208]) /* 0x40013C00 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT3_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[209]) /* 0x40013C40 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT4_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[210]) /* 0x40013C80 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT5_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[211]) /* 0x40013CC0 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT6_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[212]) /* 0x40013D00 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT7_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[213]) /* 0x40013D40 */ +#define PERI_MS_PPU_FX_LCD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[214]) /* 0x40013D80 */ +#define PERI_MS_PPU_FX_USBFS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[215]) /* 0x40013DC0 */ +#define PERI_MS_PPU_FX_SMIF0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[216]) /* 0x40013E00 */ +#define PERI_MS_PPU_FX_CANFD0_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[217]) /* 0x40013E40 */ +#define PERI_MS_PPU_FX_CANFD0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[218]) /* 0x40013E80 */ +#define PERI_MS_PPU_FX_CANFD0_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[219]) /* 0x40013EC0 */ +#define PERI_MS_PPU_FX_SCB0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[220]) /* 0x40013F00 */ +#define PERI_MS_PPU_FX_SCB1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[221]) /* 0x40013F40 */ +#define PERI_MS_PPU_FX_SCB2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[222]) /* 0x40013F80 */ +#define PERI_MS_PPU_FX_SCB4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[223]) /* 0x40013FC0 */ +#define PERI_MS_PPU_FX_SCB5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[224]) /* 0x40014000 */ +#define PERI_MS_PPU_FX_SCB6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[225]) /* 0x40014040 */ + +/******************************************************************************* +* CPUSS +*******************************************************************************/ + +#define CPUSS_BASE 0x40200000UL +#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40200000 */ + +/******************************************************************************* +* FAULT +*******************************************************************************/ + +#define FAULT_BASE 0x40210000UL +#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40210000 */ +#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40210000 */ +#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40210100 */ + +/******************************************************************************* +* IPC +*******************************************************************************/ + +#define IPC_BASE 0x40220000UL +#define IPC ((IPC_Type*) IPC_BASE) /* 0x40220000 */ +#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40220000 */ +#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40220020 */ +#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40220040 */ +#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40220060 */ +#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40220080 */ +#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402200A0 */ +#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402200C0 */ +#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402200E0 */ +#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40220100 */ +#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40220120 */ +#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40220140 */ +#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40220160 */ +#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40220180 */ +#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402201A0 */ +#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402201C0 */ +#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402201E0 */ +#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40221000 */ +#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40221020 */ +#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40221040 */ +#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40221060 */ +#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40221080 */ +#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402210A0 */ +#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402210C0 */ +#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402210E0 */ +#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40221100 */ +#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40221120 */ +#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40221140 */ +#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40221160 */ +#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40221180 */ +#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402211A0 */ +#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402211C0 */ +#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402211E0 */ + +/******************************************************************************* +* PROT +*******************************************************************************/ + +#define PROT_BASE 0x40230000UL +#define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ +#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ +#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ +#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402320C0 */ +#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40232100 */ +#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40232140 */ +#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40232180 */ +#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402321C0 */ +#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40232200 */ +#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40232240 */ +#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40232280 */ +#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402322C0 */ +#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40232300 */ +#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ +#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ +#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ + +/******************************************************************************* +* FLASHC +*******************************************************************************/ + +#define FLASHC_BASE 0x40240000UL +#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40240000 */ +#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4024F000 */ + +/******************************************************************************* +* SRSS +*******************************************************************************/ + +#define SRSS_BASE 0x40260000UL +#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ +#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */ +#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */ + +/******************************************************************************* +* BACKUP +*******************************************************************************/ + +#define BACKUP_BASE 0x40270000UL +#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ + +/******************************************************************************* +* DW +*******************************************************************************/ + +#define DW0_BASE 0x40280000UL +#define DW1_BASE 0x40290000UL +#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ +#define DW1 ((DW_Type*) DW1_BASE) /* 0x40290000 */ +#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40288000 */ +#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40288040 */ +#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40288080 */ +#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x402880C0 */ +#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40288100 */ +#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x40288140 */ +#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x40288180 */ +#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402881C0 */ +#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40288200 */ +#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40288240 */ +#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40288280 */ +#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x402882C0 */ +#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40288300 */ +#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x40288340 */ +#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x40288380 */ +#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402883C0 */ +#define DW0_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[16]) /* 0x40288400 */ +#define DW0_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[17]) /* 0x40288440 */ +#define DW0_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[18]) /* 0x40288480 */ +#define DW0_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[19]) /* 0x402884C0 */ +#define DW0_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[20]) /* 0x40288500 */ +#define DW0_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[21]) /* 0x40288540 */ +#define DW0_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[22]) /* 0x40288580 */ +#define DW0_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[23]) /* 0x402885C0 */ +#define DW0_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[24]) /* 0x40288600 */ +#define DW0_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[25]) /* 0x40288640 */ +#define DW0_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[26]) /* 0x40288680 */ +#define DW0_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[27]) /* 0x402886C0 */ +#define DW0_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[28]) /* 0x40288700 */ +#define DW0_CH_STRUCT29 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[29]) /* 0x40288740 */ +#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40298000 */ +#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40298040 */ +#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40298080 */ +#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x402980C0 */ +#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40298100 */ +#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x40298140 */ +#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x40298180 */ +#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402981C0 */ +#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40298200 */ +#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40298240 */ +#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40298280 */ +#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x402982C0 */ +#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40298300 */ +#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x40298340 */ +#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x40298380 */ +#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402983C0 */ +#define DW1_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[16]) /* 0x40298400 */ +#define DW1_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[17]) /* 0x40298440 */ +#define DW1_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[18]) /* 0x40298480 */ +#define DW1_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[19]) /* 0x402984C0 */ +#define DW1_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[20]) /* 0x40298500 */ +#define DW1_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[21]) /* 0x40298540 */ +#define DW1_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[22]) /* 0x40298580 */ +#define DW1_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[23]) /* 0x402985C0 */ +#define DW1_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[24]) /* 0x40298600 */ +#define DW1_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[25]) /* 0x40298640 */ +#define DW1_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[26]) /* 0x40298680 */ +#define DW1_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[27]) /* 0x402986C0 */ +#define DW1_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[28]) /* 0x40298700 */ +#define DW1_CH_STRUCT29 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[29]) /* 0x40298740 */ +#define DW1_CH_STRUCT30 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[30]) /* 0x40298780 */ +#define DW1_CH_STRUCT31 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[31]) /* 0x402987C0 */ + +/******************************************************************************* +* DMAC +*******************************************************************************/ + +#define DMAC_BASE 0x402A0000UL +#define DMAC ((DMAC_Type*) DMAC_BASE) /* 0x402A0000 */ +#define DMAC_CH0 ((DMAC_CH_Type*) &DMAC->CH[0]) /* 0x402A1000 */ +#define DMAC_CH1 ((DMAC_CH_Type*) &DMAC->CH[1]) /* 0x402A1100 */ + +/******************************************************************************* +* EFUSE +*******************************************************************************/ + +#define EFUSE_BASE 0x402C0000UL +#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ + +/******************************************************************************* +* HSIOM +*******************************************************************************/ + +#define HSIOM_BASE 0x40300000UL +#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40300000 */ +#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40300000 */ +#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40300010 */ +#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40300020 */ +#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40300030 */ +#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40300040 */ +#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40300050 */ +#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40300060 */ +#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40300070 */ +#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40300080 */ +#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40300090 */ +#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403000A0 */ +#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403000B0 */ +#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403000C0 */ +#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403000D0 */ +#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403000E0 */ + +/******************************************************************************* +* GPIO +*******************************************************************************/ + +#define GPIO_BASE 0x40310000UL +#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40310000 */ +#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40310000 */ +#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40310080 */ +#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40310100 */ +#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40310180 */ +#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40310200 */ +#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40310280 */ +#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40310300 */ +#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40310380 */ +#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40310400 */ +#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40310480 */ +#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40310500 */ +#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40310580 */ +#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40310600 */ +#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40310680 */ +#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40310700 */ + +/******************************************************************************* +* SMARTIO +*******************************************************************************/ + +#define SMARTIO_BASE 0x40320000UL +#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40320000 */ +#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40320900 */ + +/******************************************************************************* +* LPCOMP +*******************************************************************************/ + +#define LPCOMP_BASE 0x40350000UL +#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */ + +/******************************************************************************* +* CSD +*******************************************************************************/ + +#define CSD0_BASE 0x40360000UL +#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */ + +/******************************************************************************* +* TCPWM +*******************************************************************************/ + +#define TCPWM0_BASE 0x40380000UL +#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM0_GRP0 ((TCPWM_GRP_Type*) &TCPWM0->GRP[0]) /* 0x40380000 */ +#define TCPWM0_GRP1 ((TCPWM_GRP_Type*) &TCPWM0->GRP[1]) /* 0x40388000 */ +#define TCPWM0_GRP0_CNT0 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[0]) /* 0x40380000 */ +#define TCPWM0_GRP0_CNT1 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[1]) /* 0x40380080 */ +#define TCPWM0_GRP0_CNT2 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[2]) /* 0x40380100 */ +#define TCPWM0_GRP0_CNT3 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[3]) /* 0x40380180 */ +#define TCPWM0_GRP1_CNT0 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[0]) /* 0x40388000 */ +#define TCPWM0_GRP1_CNT1 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[1]) /* 0x40388080 */ +#define TCPWM0_GRP1_CNT2 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[2]) /* 0x40388100 */ +#define TCPWM0_GRP1_CNT3 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[3]) /* 0x40388180 */ +#define TCPWM0_GRP1_CNT4 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[4]) /* 0x40388200 */ +#define TCPWM0_GRP1_CNT5 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[5]) /* 0x40388280 */ +#define TCPWM0_GRP1_CNT6 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[6]) /* 0x40388300 */ +#define TCPWM0_GRP1_CNT7 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[7]) /* 0x40388380 */ + +/******************************************************************************* +* LCD +*******************************************************************************/ + +#define LCD0_BASE 0x403B0000UL +#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ + +/******************************************************************************* +* USBFS +*******************************************************************************/ + +#define USBFS0_BASE 0x403F0000UL +#define USBFS0 ((USBFS_Type*) USBFS0_BASE) /* 0x403F0000 */ +#define USBFS0_USBDEV ((USBFS_USBDEV_Type*) &USBFS0->USBDEV) /* 0x403F0000 */ +#define USBFS0_USBLPM ((USBFS_USBLPM_Type*) &USBFS0->USBLPM) /* 0x403F2000 */ +#define USBFS0_USBHOST ((USBFS_USBHOST_Type*) &USBFS0->USBHOST) /* 0x403F4000 */ + +/******************************************************************************* +* SMIF +*******************************************************************************/ + +#define SMIF0_BASE 0x40420000UL +#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ +#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ +#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ +#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ + +/******************************************************************************* +* CANFD +*******************************************************************************/ + +#define CANFD0_BASE 0x40520000UL +#define CANFD0 ((CANFD_Type*) CANFD0_BASE) /* 0x40520000 */ +#define CANFD0_CH0 ((CANFD_CH_Type*) &CANFD0->CH[0]) /* 0x40520000 */ +#define CANFD0_CH0_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[0].M_TTCAN) /* 0x40520000 */ + +/******************************************************************************* +* SCB +*******************************************************************************/ + +#define SCB0_BASE 0x40600000UL +#define SCB1_BASE 0x40610000UL +#define SCB2_BASE 0x40620000UL +#define SCB4_BASE 0x40640000UL +#define SCB5_BASE 0x40650000UL +#define SCB6_BASE 0x40660000UL +#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40600000 */ +#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40610000 */ +#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40620000 */ +#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40640000 */ +#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40650000 */ +#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40660000 */ + +/******************************************************************************* +* CTBM +*******************************************************************************/ + +#define CTBM0_BASE 0x40900000UL +#define CTBM0 ((CTBM_Type*) CTBM0_BASE) /* 0x40900000 */ + +/******************************************************************************* +* CTDAC +*******************************************************************************/ + +#define CTDAC0_BASE 0x40940000UL +#define CTDAC0 ((CTDAC_Type*) CTDAC0_BASE) /* 0x40940000 */ + +/******************************************************************************* +* SAR +*******************************************************************************/ + +#define SAR0_BASE 0x409B0000UL +#define SAR0 ((SAR_Type*) SAR0_BASE) /* 0x409B0000 */ + +/******************************************************************************* +* PASS +*******************************************************************************/ + +#define PASS_BASE 0x409F0000UL +#define PASS ((PASS_Type*) PASS_BASE) /* 0x409F0000 */ +#define PASS_TIMER ((PASS_TIMER_Type*) &PASS->TIMER) /* 0x409F0100 */ +#define PASS_LPOSC ((PASS_LPOSC_Type*) &PASS->LPOSC) /* 0x409F0200 */ +#define PASS_FIFO0 ((PASS_FIFO_Type*) &PASS->FIFO[0]) /* 0x409F0300 */ +#define PASS_FIFO1 ((PASS_FIFO_Type*) &PASS->FIFO[1]) /* 0x409F0400 */ +#define PASS_AREFV2 ((PASS_AREFV2_Type*) &PASS->AREFV2) /* 0x409F0E00 */ + +/** \} CY8C6144LQI-S4F62 */ + +#endif /* _CY8C6144LQI_S4F62_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6144lqi_s4f82.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6144lqi_s4f82.h new file mode 100644 index 0000000000..86c856b2b4 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6144lqi_s4f82.h @@ -0,0 +1,993 @@ +/***************************************************************************//** +* \file cy8c6144lqi_s4f82.h +* +* \brief +* CY8C6144LQI-S4F82 device header +* +* \note +* Generator version: 1.6.0.225 +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CY8C6144LQI_S4F82_H_ +#define _CY8C6144LQI_S4F82_H_ + +/** +* \addtogroup group_device CY8C6144LQI-S4F82 +* \{ +*/ + +/** +* \addtogroup Configuration_of_CMSIS +* \{ +*/ + +/******************************************************************************* +* Interrupt Number Definition +*******************************************************************************/ + +typedef enum { + /* ARM Cortex-M4 Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C6144LQI-S4F82 Peripheral Interrupt Numbers */ + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_6_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #6 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + pass_interrupt_sar_0_IRQn = 39, /*!< 39 [DeepSleep] SAR ADC0 interrupt */ + pass_interrupt_sar_1_IRQn = 40, /*!< 40 [DeepSleep] SAR ADC1 interrupt */ + pass_interrupt_ctb_IRQn = 41, /*!< 41 [DeepSleep] individual interrupt per CTB */ + pass_interrupt_fifo_0_IRQn = 43, /*!< 43 [DeepSleep] PASS FIFO0 */ + pass_interrupt_fifo_1_IRQn = 44, /*!< 44 [DeepSleep] PASS FIFO1 */ + scb_0_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #2 */ + scb_4_interrupt_IRQn = 49, /*!< 49 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 50, /*!< 50 [Active] Serial Communication Block #5 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_0_interrupts_256_IRQn = 131, /*!< 131 [Active] TCPWM #0, Counter #256 */ + tcpwm_0_interrupts_257_IRQn = 132, /*!< 132 [Active] TCPWM #0, Counter #257 */ + tcpwm_0_interrupts_258_IRQn = 133, /*!< 133 [Active] TCPWM #0, Counter #258 */ + tcpwm_0_interrupts_259_IRQn = 134, /*!< 134 [Active] TCPWM #0, Counter #259 */ + tcpwm_0_interrupts_260_IRQn = 135, /*!< 135 [Active] TCPWM #0, Counter #260 */ + tcpwm_0_interrupts_261_IRQn = 136, /*!< 136 [Active] TCPWM #0, Counter #261 */ + tcpwm_0_interrupts_262_IRQn = 137, /*!< 137 [Active] TCPWM #0, Counter #262 */ + tcpwm_0_interrupts_263_IRQn = 138, /*!< 138 [Active] TCPWM #0, Counter #263 */ + pass_interrupt_dacs_IRQn = 146, /*!< 146 [Active] Consolidated interrrupt for all DACs */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + canfd_0_interrupt0_IRQn = 168, /*!< 168 [Active] Can #0, Consolidated interrupt #0 */ + canfd_0_interrupts0_0_IRQn = 169, /*!< 169 [Active] CAN #0, Interrupt #0, Channel #0 */ + canfd_0_interrupts1_0_IRQn = 170, /*!< 170 [Active] CAN #0, Interrupt #1, Channel #0 */ + cpuss_interrupts_dw1_29_IRQn = 171, /*!< 171 [Active] CPUSS DataWire #1, Channel #29 */ + cpuss_interrupts_dw1_30_IRQn = 172, /*!< 172 [Active] CPUSS DataWire #1, Channel #30 */ + cpuss_interrupts_dw1_31_IRQn = 173, /*!< 173 [Active] CPUSS DataWire #1, Channel #31 */ + cpuss_interrupts_dw0_29_IRQn = 174, /*!< 174 [Active] CPUSS DataWire #0, Channel #29 */ + unconnected_IRQn = 240 /*!< 240 Unconnected */ +} IRQn_Type; + + +/******************************************************************************* +* Processor and Core Peripheral Section +*******************************************************************************/ + +/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __CM0P_PRESENT 0 /*!< CM0P present or not */ +#define __DTCM_PRESENT 0 /*!< DTCM present or not */ +#define __ICACHE_PRESENT 0 /*!< ICACHE present or not */ +#define __DCACHE_PRESENT 0 /*!< DCACHE present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + + +/* Memory Blocks */ +#define CY_ROM_BASE 0x00000000UL +#define CY_ROM_SIZE 0x00010000UL +#define CY_SRAM_BASE 0x08000000UL +#define CY_SRAM_SIZE 0x00020000UL +#define CY_FLASH_BASE 0x10000000UL +#define CY_FLASH_SIZE 0x00040000UL +#define CY_EM_EEPROM_BASE 0x14000000UL +#define CY_EM_EEPROM_SIZE 0x00000000UL +#define CY_SFLASH_BASE 0x16000000UL +#define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL +#define CY_EFUSE_BASE 0x402C0800UL +#define CY_EFUSE_SIZE 0x00000200UL +#define CY_CAN0MRAM_BASE 0x40530000UL +#define CY_CAN0MRAM_SIZE 0x00010000UL + +#include "system_psoc6.h" /*!< PSoC 6 System */ + +/* IP List */ +#define CY_IP_MXTTCANFD 1u +#define CY_IP_MXTTCANFD_INSTANCES 1u +#define CY_IP_MXTTCANFD_VERSION 1u +#define CY_IP_M4CPUSS 1u +#define CY_IP_M4CPUSS_INSTANCES 1u +#define CY_IP_M4CPUSS_VERSION 2u +#define CY_IP_M4CPUSS_DMAC 1u +#define CY_IP_M4CPUSS_DMAC_INSTANCES 1u +#define CY_IP_M4CPUSS_DMAC_VERSION 2u +#define CY_IP_M4CPUSS_DMA 1u +#define CY_IP_M4CPUSS_DMA_INSTANCES 2u +#define CY_IP_M4CPUSS_DMA_VERSION 2u +#define CY_IP_MXCRYPTO 1u +#define CY_IP_MXCRYPTO_INSTANCES 1u +#define CY_IP_MXCRYPTO_VERSION 2u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 2u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 6u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u + +#include "psoc6_04_config.h" +#include "gpio_psoc6_04_68_qfn.h" + +#define CY_DEVICE_PSOC6A256K +#define CY_SILICON_ID 0xEACE110EUL +#define CY_HF_CLK_MAX_FREQ 150000000UL + +#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL + +/******************************************************************************* +* SFLASH +*******************************************************************************/ + +#define SFLASH_BASE 0x16000000UL +#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */ + +/******************************************************************************* +* PERI +*******************************************************************************/ + +#define PERI_BASE 0x40000000UL +#define PERI ((PERI_Type*) PERI_BASE) /* 0x40000000 */ +#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40004000 */ +#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40004020 */ +#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40004040 */ +#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x40004060 */ +#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40004080 */ +#define PERI_GR5 ((PERI_GR_Type*) &PERI->GR[5]) /* 0x400040A0 */ +#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x400040C0 */ +#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40004120 */ +#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40008000 */ +#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40008400 */ +#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40008800 */ +#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40008C00 */ +#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40009000 */ +#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40009400 */ +#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40009800 */ +#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40009C00 */ +#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ +#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ +#define PERI_TR_GR10 ((PERI_TR_GR_Type*) &PERI->TR_GR[10]) /* 0x4000A800 */ +#define PERI_TR_GR11 ((PERI_TR_GR_Type*) &PERI->TR_GR[11]) /* 0x4000AC00 */ +#define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ +#define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ +#define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ +#define PERI_TR_1TO1_GR3 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[3]) /* 0x4000CC00 */ +#define PERI_TR_1TO1_GR4 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[4]) /* 0x4000D000 */ +#define PERI_TR_1TO1_GR5 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[5]) /* 0x4000D400 */ +#define PERI_TR_1TO1_GR6 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[6]) /* 0x4000D800 */ +#define PERI_TR_1TO1_GR7 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[7]) /* 0x4000DC00 */ +#define PERI_TR_1TO1_GR8 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[8]) /* 0x4000E000 */ + +/******************************************************************************* +* PERI_MS +*******************************************************************************/ + +#define PERI_MS_BASE 0x40010000UL +#define PERI_MS ((PERI_MS_Type*) PERI_MS_BASE) /* 0x40010000 */ +#define PERI_MS_PPU_PR0 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[0]) /* 0x40010000 */ +#define PERI_MS_PPU_PR1 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[1]) /* 0x40010040 */ +#define PERI_MS_PPU_PR2 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[2]) /* 0x40010080 */ +#define PERI_MS_PPU_PR3 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[3]) /* 0x400100C0 */ +#define PERI_MS_PPU_PR4 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[4]) /* 0x40010100 */ +#define PERI_MS_PPU_PR5 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[5]) /* 0x40010140 */ +#define PERI_MS_PPU_PR6 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[6]) /* 0x40010180 */ +#define PERI_MS_PPU_PR7 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[7]) /* 0x400101C0 */ +#define PERI_MS_PPU_FX_PERI_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[0]) /* 0x40010800 */ +#define PERI_MS_PPU_FX_PERI_GR0_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[1]) /* 0x40010840 */ +#define PERI_MS_PPU_FX_PERI_GR1_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[2]) /* 0x40010880 */ +#define PERI_MS_PPU_FX_PERI_GR2_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[3]) /* 0x400108C0 */ +#define PERI_MS_PPU_FX_PERI_GR3_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[4]) /* 0x40010900 */ +#define PERI_MS_PPU_FX_PERI_GR4_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[5]) /* 0x40010940 */ +#define PERI_MS_PPU_FX_PERI_GR5_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[6]) /* 0x40010980 */ +#define PERI_MS_PPU_FX_PERI_GR6_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[7]) /* 0x400109C0 */ +#define PERI_MS_PPU_FX_PERI_GR9_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[8]) /* 0x40010A00 */ +#define PERI_MS_PPU_FX_PERI_TR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[9]) /* 0x40010A40 */ +#define PERI_MS_PPU_FX_CRYPTO_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[10]) /* 0x40010A80 */ +#define PERI_MS_PPU_FX_CRYPTO_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[11]) /* 0x40010AC0 */ +#define PERI_MS_PPU_FX_CRYPTO_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[12]) /* 0x40010B00 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[13]) /* 0x40010B40 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[14]) /* 0x40010B80 */ +#define PERI_MS_PPU_FX_CRYPTO_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[15]) /* 0x40010BC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[16]) /* 0x40010C00 */ +#define PERI_MS_PPU_FX_CPUSS_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[17]) /* 0x40010C40 */ +#define PERI_MS_PPU_FX_CPUSS_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[18]) /* 0x40010C80 */ +#define PERI_MS_PPU_FX_CPUSS_CM0_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[19]) /* 0x40010CC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[20]) /* 0x40010D00 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[21]) /* 0x40010D40 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT1_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[22]) /* 0x40010D80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT0_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[23]) /* 0x40010DC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT1_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[24]) /* 0x40010E00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT2_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[25]) /* 0x40010E40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT3_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[26]) /* 0x40010E80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT4_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[27]) /* 0x40010EC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT5_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[28]) /* 0x40010F00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT6_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[29]) /* 0x40010F40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT7_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[30]) /* 0x40010F80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT8_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[31]) /* 0x40010FC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT9_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[32]) /* 0x40011000 */ +#define PERI_MS_PPU_FX_IPC_STRUCT10_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[33]) /* 0x40011040 */ +#define PERI_MS_PPU_FX_IPC_STRUCT11_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[34]) /* 0x40011080 */ +#define PERI_MS_PPU_FX_IPC_STRUCT12_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[35]) /* 0x400110C0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT13_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[36]) /* 0x40011100 */ +#define PERI_MS_PPU_FX_IPC_STRUCT14_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[37]) /* 0x40011140 */ +#define PERI_MS_PPU_FX_IPC_STRUCT15_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[38]) /* 0x40011180 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT0_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[39]) /* 0x400111C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT1_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[40]) /* 0x40011200 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT2_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[41]) /* 0x40011240 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT3_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[42]) /* 0x40011280 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT4_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[43]) /* 0x400112C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT5_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[44]) /* 0x40011300 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT6_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[45]) /* 0x40011340 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT7_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[46]) /* 0x40011380 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT8_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[47]) /* 0x400113C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT9_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[48]) /* 0x40011400 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT10_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[49]) /* 0x40011440 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT11_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[50]) /* 0x40011480 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT12_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[51]) /* 0x400114C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT13_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[52]) /* 0x40011500 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT14_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[53]) /* 0x40011540 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT15_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[54]) /* 0x40011580 */ +#define PERI_MS_PPU_FX_PROT_SMPU_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[55]) /* 0x400115C0 */ +#define PERI_MS_PPU_FX_PROT_MPU0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[56]) /* 0x40011600 */ +#define PERI_MS_PPU_FX_PROT_MPU14_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[57]) /* 0x40011640 */ +#define PERI_MS_PPU_FX_PROT_MPU15_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[58]) /* 0x40011680 */ +#define PERI_MS_PPU_FX_FLASHC_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[59]) /* 0x400116C0 */ +#define PERI_MS_PPU_FX_FLASHC_CMD ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[60]) /* 0x40011700 */ +#define PERI_MS_PPU_FX_FLASHC_DFT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[61]) /* 0x40011740 */ +#define PERI_MS_PPU_FX_FLASHC_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[62]) /* 0x40011780 */ +#define PERI_MS_PPU_FX_FLASHC_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[63]) /* 0x400117C0 */ +#define PERI_MS_PPU_FX_FLASHC_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[64]) /* 0x40011800 */ +#define PERI_MS_PPU_FX_FLASHC_DW0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[65]) /* 0x40011840 */ +#define PERI_MS_PPU_FX_FLASHC_DW1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[66]) /* 0x40011880 */ +#define PERI_MS_PPU_FX_FLASHC_DMAC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[67]) /* 0x400118C0 */ +#define PERI_MS_PPU_FX_FLASHC_FM ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[68]) /* 0x40011900 */ +#define PERI_MS_PPU_FX_SRSS_MAIN1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[69]) /* 0x40011940 */ +#define PERI_MS_PPU_FX_SRSS_MAIN2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[70]) /* 0x40011980 */ +#define PERI_MS_PPU_FX_WDT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[71]) /* 0x400119C0 */ +#define PERI_MS_PPU_FX_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[72]) /* 0x40011A00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[73]) /* 0x40011A40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[74]) /* 0x40011A80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[75]) /* 0x40011AC0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[76]) /* 0x40011B00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[77]) /* 0x40011B40 */ +#define PERI_MS_PPU_FX_BACKUP_BACKUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[78]) /* 0x40011B80 */ +#define PERI_MS_PPU_FX_DW0_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[79]) /* 0x40011BC0 */ +#define PERI_MS_PPU_FX_DW1_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[80]) /* 0x40011C00 */ +#define PERI_MS_PPU_FX_DW0_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[81]) /* 0x40011C40 */ +#define PERI_MS_PPU_FX_DW1_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[82]) /* 0x40011C80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[83]) /* 0x40011CC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[84]) /* 0x40011D00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[85]) /* 0x40011D40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[86]) /* 0x40011D80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[87]) /* 0x40011DC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[88]) /* 0x40011E00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[89]) /* 0x40011E40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[90]) /* 0x40011E80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[91]) /* 0x40011EC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[92]) /* 0x40011F00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[93]) /* 0x40011F40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[94]) /* 0x40011F80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[95]) /* 0x40011FC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[96]) /* 0x40012000 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[97]) /* 0x40012040 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[98]) /* 0x40012080 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[99]) /* 0x400120C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[100]) /* 0x40012100 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[101]) /* 0x40012140 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[102]) /* 0x40012180 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[103]) /* 0x400121C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[104]) /* 0x40012200 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[105]) /* 0x40012240 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[106]) /* 0x40012280 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[107]) /* 0x400122C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[108]) /* 0x40012300 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[109]) /* 0x40012340 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[110]) /* 0x40012380 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[111]) /* 0x400123C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT29_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[112]) /* 0x40012400 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[113]) /* 0x40012440 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[114]) /* 0x40012480 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[115]) /* 0x400124C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[116]) /* 0x40012500 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[117]) /* 0x40012540 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[118]) /* 0x40012580 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[119]) /* 0x400125C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[120]) /* 0x40012600 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[121]) /* 0x40012640 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[122]) /* 0x40012680 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[123]) /* 0x400126C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[124]) /* 0x40012700 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[125]) /* 0x40012740 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[126]) /* 0x40012780 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[127]) /* 0x400127C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[128]) /* 0x40012800 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[129]) /* 0x40012840 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[130]) /* 0x40012880 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[131]) /* 0x400128C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[132]) /* 0x40012900 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[133]) /* 0x40012940 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[134]) /* 0x40012980 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[135]) /* 0x400129C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[136]) /* 0x40012A00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[137]) /* 0x40012A40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[138]) /* 0x40012A80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[139]) /* 0x40012AC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[140]) /* 0x40012B00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[141]) /* 0x40012B40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT29_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[142]) /* 0x40012B80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT30_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[143]) /* 0x40012BC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT31_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[144]) /* 0x40012C00 */ +#define PERI_MS_PPU_FX_DMAC_TOP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[145]) /* 0x40012C40 */ +#define PERI_MS_PPU_FX_DMAC_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[146]) /* 0x40012C80 */ +#define PERI_MS_PPU_FX_DMAC_CH1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[147]) /* 0x40012CC0 */ +#define PERI_MS_PPU_FX_EFUSE_CTL ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[148]) /* 0x40012D00 */ +#define PERI_MS_PPU_FX_EFUSE_DATA ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[149]) /* 0x40012D40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[150]) /* 0x40012D80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[151]) /* 0x40012DC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[152]) /* 0x40012E00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[153]) /* 0x40012E40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[154]) /* 0x40012E80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[155]) /* 0x40012EC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[156]) /* 0x40012F00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[157]) /* 0x40012F40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[158]) /* 0x40012F80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[159]) /* 0x40012FC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[160]) /* 0x40013000 */ +#define PERI_MS_PPU_FX_HSIOM_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[161]) /* 0x40013040 */ +#define PERI_MS_PPU_FX_HSIOM_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[162]) /* 0x40013080 */ +#define PERI_MS_PPU_FX_HSIOM_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[163]) /* 0x400130C0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[164]) /* 0x40013100 */ +#define PERI_MS_PPU_FX_HSIOM_AMUX ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[165]) /* 0x40013140 */ +#define PERI_MS_PPU_FX_HSIOM_MON ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[166]) /* 0x40013180 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[167]) /* 0x400131C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[168]) /* 0x40013200 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[169]) /* 0x40013240 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[170]) /* 0x40013280 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[171]) /* 0x400132C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[172]) /* 0x40013300 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[173]) /* 0x40013340 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[174]) /* 0x40013380 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[175]) /* 0x400133C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[176]) /* 0x40013400 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[177]) /* 0x40013440 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[178]) /* 0x40013480 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[179]) /* 0x400134C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[180]) /* 0x40013500 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[181]) /* 0x40013540 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[182]) /* 0x40013580 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[183]) /* 0x400135C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[184]) /* 0x40013600 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[185]) /* 0x40013640 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[186]) /* 0x40013680 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[187]) /* 0x400136C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[188]) /* 0x40013700 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[189]) /* 0x40013740 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[190]) /* 0x40013780 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[191]) /* 0x400137C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[192]) /* 0x40013800 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[193]) /* 0x40013840 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[194]) /* 0x40013880 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[195]) /* 0x400138C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[196]) /* 0x40013900 */ +#define PERI_MS_PPU_FX_GPIO_GPIO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[197]) /* 0x40013940 */ +#define PERI_MS_PPU_FX_GPIO_TEST ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[198]) /* 0x40013980 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[199]) /* 0x400139C0 */ +#define PERI_MS_PPU_FX_LPCOMP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[200]) /* 0x40013A00 */ +#define PERI_MS_PPU_FX_CSD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[201]) /* 0x40013A40 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT0_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[202]) /* 0x40013A80 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT1_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[203]) /* 0x40013AC0 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT2_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[204]) /* 0x40013B00 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT3_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[205]) /* 0x40013B40 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT0_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[206]) /* 0x40013B80 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT1_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[207]) /* 0x40013BC0 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT2_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[208]) /* 0x40013C00 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT3_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[209]) /* 0x40013C40 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT4_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[210]) /* 0x40013C80 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT5_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[211]) /* 0x40013CC0 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT6_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[212]) /* 0x40013D00 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT7_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[213]) /* 0x40013D40 */ +#define PERI_MS_PPU_FX_LCD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[214]) /* 0x40013D80 */ +#define PERI_MS_PPU_FX_USBFS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[215]) /* 0x40013DC0 */ +#define PERI_MS_PPU_FX_SMIF0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[216]) /* 0x40013E00 */ +#define PERI_MS_PPU_FX_CANFD0_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[217]) /* 0x40013E40 */ +#define PERI_MS_PPU_FX_CANFD0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[218]) /* 0x40013E80 */ +#define PERI_MS_PPU_FX_CANFD0_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[219]) /* 0x40013EC0 */ +#define PERI_MS_PPU_FX_SCB0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[220]) /* 0x40013F00 */ +#define PERI_MS_PPU_FX_SCB1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[221]) /* 0x40013F40 */ +#define PERI_MS_PPU_FX_SCB2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[222]) /* 0x40013F80 */ +#define PERI_MS_PPU_FX_SCB4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[223]) /* 0x40013FC0 */ +#define PERI_MS_PPU_FX_SCB5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[224]) /* 0x40014000 */ +#define PERI_MS_PPU_FX_SCB6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[225]) /* 0x40014040 */ + +/******************************************************************************* +* CRYPTO +*******************************************************************************/ + +#define CRYPTO_BASE 0x40100000UL +#define CRYPTO ((CRYPTO_Type*) CRYPTO_BASE) /* 0x40100000 */ + +/******************************************************************************* +* CPUSS +*******************************************************************************/ + +#define CPUSS_BASE 0x40200000UL +#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40200000 */ + +/******************************************************************************* +* FAULT +*******************************************************************************/ + +#define FAULT_BASE 0x40210000UL +#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40210000 */ +#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40210000 */ +#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40210100 */ + +/******************************************************************************* +* IPC +*******************************************************************************/ + +#define IPC_BASE 0x40220000UL +#define IPC ((IPC_Type*) IPC_BASE) /* 0x40220000 */ +#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40220000 */ +#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40220020 */ +#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40220040 */ +#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40220060 */ +#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40220080 */ +#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402200A0 */ +#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402200C0 */ +#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402200E0 */ +#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40220100 */ +#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40220120 */ +#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40220140 */ +#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40220160 */ +#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40220180 */ +#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402201A0 */ +#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402201C0 */ +#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402201E0 */ +#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40221000 */ +#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40221020 */ +#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40221040 */ +#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40221060 */ +#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40221080 */ +#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402210A0 */ +#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402210C0 */ +#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402210E0 */ +#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40221100 */ +#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40221120 */ +#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40221140 */ +#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40221160 */ +#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40221180 */ +#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402211A0 */ +#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402211C0 */ +#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402211E0 */ + +/******************************************************************************* +* PROT +*******************************************************************************/ + +#define PROT_BASE 0x40230000UL +#define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ +#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ +#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ +#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402320C0 */ +#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40232100 */ +#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40232140 */ +#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40232180 */ +#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402321C0 */ +#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40232200 */ +#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40232240 */ +#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40232280 */ +#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402322C0 */ +#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40232300 */ +#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ +#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ +#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ + +/******************************************************************************* +* FLASHC +*******************************************************************************/ + +#define FLASHC_BASE 0x40240000UL +#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40240000 */ +#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4024F000 */ + +/******************************************************************************* +* SRSS +*******************************************************************************/ + +#define SRSS_BASE 0x40260000UL +#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ +#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */ +#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */ + +/******************************************************************************* +* BACKUP +*******************************************************************************/ + +#define BACKUP_BASE 0x40270000UL +#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ + +/******************************************************************************* +* DW +*******************************************************************************/ + +#define DW0_BASE 0x40280000UL +#define DW1_BASE 0x40290000UL +#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ +#define DW1 ((DW_Type*) DW1_BASE) /* 0x40290000 */ +#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40288000 */ +#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40288040 */ +#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40288080 */ +#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x402880C0 */ +#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40288100 */ +#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x40288140 */ +#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x40288180 */ +#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402881C0 */ +#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40288200 */ +#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40288240 */ +#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40288280 */ +#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x402882C0 */ +#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40288300 */ +#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x40288340 */ +#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x40288380 */ +#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402883C0 */ +#define DW0_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[16]) /* 0x40288400 */ +#define DW0_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[17]) /* 0x40288440 */ +#define DW0_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[18]) /* 0x40288480 */ +#define DW0_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[19]) /* 0x402884C0 */ +#define DW0_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[20]) /* 0x40288500 */ +#define DW0_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[21]) /* 0x40288540 */ +#define DW0_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[22]) /* 0x40288580 */ +#define DW0_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[23]) /* 0x402885C0 */ +#define DW0_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[24]) /* 0x40288600 */ +#define DW0_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[25]) /* 0x40288640 */ +#define DW0_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[26]) /* 0x40288680 */ +#define DW0_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[27]) /* 0x402886C0 */ +#define DW0_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[28]) /* 0x40288700 */ +#define DW0_CH_STRUCT29 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[29]) /* 0x40288740 */ +#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40298000 */ +#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40298040 */ +#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40298080 */ +#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x402980C0 */ +#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40298100 */ +#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x40298140 */ +#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x40298180 */ +#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402981C0 */ +#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40298200 */ +#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40298240 */ +#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40298280 */ +#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x402982C0 */ +#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40298300 */ +#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x40298340 */ +#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x40298380 */ +#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402983C0 */ +#define DW1_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[16]) /* 0x40298400 */ +#define DW1_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[17]) /* 0x40298440 */ +#define DW1_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[18]) /* 0x40298480 */ +#define DW1_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[19]) /* 0x402984C0 */ +#define DW1_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[20]) /* 0x40298500 */ +#define DW1_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[21]) /* 0x40298540 */ +#define DW1_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[22]) /* 0x40298580 */ +#define DW1_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[23]) /* 0x402985C0 */ +#define DW1_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[24]) /* 0x40298600 */ +#define DW1_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[25]) /* 0x40298640 */ +#define DW1_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[26]) /* 0x40298680 */ +#define DW1_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[27]) /* 0x402986C0 */ +#define DW1_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[28]) /* 0x40298700 */ +#define DW1_CH_STRUCT29 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[29]) /* 0x40298740 */ +#define DW1_CH_STRUCT30 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[30]) /* 0x40298780 */ +#define DW1_CH_STRUCT31 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[31]) /* 0x402987C0 */ + +/******************************************************************************* +* DMAC +*******************************************************************************/ + +#define DMAC_BASE 0x402A0000UL +#define DMAC ((DMAC_Type*) DMAC_BASE) /* 0x402A0000 */ +#define DMAC_CH0 ((DMAC_CH_Type*) &DMAC->CH[0]) /* 0x402A1000 */ +#define DMAC_CH1 ((DMAC_CH_Type*) &DMAC->CH[1]) /* 0x402A1100 */ + +/******************************************************************************* +* EFUSE +*******************************************************************************/ + +#define EFUSE_BASE 0x402C0000UL +#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ + +/******************************************************************************* +* HSIOM +*******************************************************************************/ + +#define HSIOM_BASE 0x40300000UL +#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40300000 */ +#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40300000 */ +#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40300010 */ +#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40300020 */ +#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40300030 */ +#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40300040 */ +#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40300050 */ +#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40300060 */ +#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40300070 */ +#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40300080 */ +#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40300090 */ +#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403000A0 */ +#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403000B0 */ +#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403000C0 */ +#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403000D0 */ +#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403000E0 */ + +/******************************************************************************* +* GPIO +*******************************************************************************/ + +#define GPIO_BASE 0x40310000UL +#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40310000 */ +#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40310000 */ +#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40310080 */ +#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40310100 */ +#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40310180 */ +#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40310200 */ +#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40310280 */ +#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40310300 */ +#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40310380 */ +#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40310400 */ +#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40310480 */ +#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40310500 */ +#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40310580 */ +#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40310600 */ +#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40310680 */ +#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40310700 */ + +/******************************************************************************* +* SMARTIO +*******************************************************************************/ + +#define SMARTIO_BASE 0x40320000UL +#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40320000 */ +#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40320900 */ + +/******************************************************************************* +* LPCOMP +*******************************************************************************/ + +#define LPCOMP_BASE 0x40350000UL +#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */ + +/******************************************************************************* +* CSD +*******************************************************************************/ + +#define CSD0_BASE 0x40360000UL +#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */ + +/******************************************************************************* +* TCPWM +*******************************************************************************/ + +#define TCPWM0_BASE 0x40380000UL +#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM0_GRP0 ((TCPWM_GRP_Type*) &TCPWM0->GRP[0]) /* 0x40380000 */ +#define TCPWM0_GRP1 ((TCPWM_GRP_Type*) &TCPWM0->GRP[1]) /* 0x40388000 */ +#define TCPWM0_GRP0_CNT0 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[0]) /* 0x40380000 */ +#define TCPWM0_GRP0_CNT1 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[1]) /* 0x40380080 */ +#define TCPWM0_GRP0_CNT2 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[2]) /* 0x40380100 */ +#define TCPWM0_GRP0_CNT3 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[3]) /* 0x40380180 */ +#define TCPWM0_GRP1_CNT0 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[0]) /* 0x40388000 */ +#define TCPWM0_GRP1_CNT1 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[1]) /* 0x40388080 */ +#define TCPWM0_GRP1_CNT2 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[2]) /* 0x40388100 */ +#define TCPWM0_GRP1_CNT3 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[3]) /* 0x40388180 */ +#define TCPWM0_GRP1_CNT4 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[4]) /* 0x40388200 */ +#define TCPWM0_GRP1_CNT5 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[5]) /* 0x40388280 */ +#define TCPWM0_GRP1_CNT6 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[6]) /* 0x40388300 */ +#define TCPWM0_GRP1_CNT7 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[7]) /* 0x40388380 */ + +/******************************************************************************* +* LCD +*******************************************************************************/ + +#define LCD0_BASE 0x403B0000UL +#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ + +/******************************************************************************* +* USBFS +*******************************************************************************/ + +#define USBFS0_BASE 0x403F0000UL +#define USBFS0 ((USBFS_Type*) USBFS0_BASE) /* 0x403F0000 */ +#define USBFS0_USBDEV ((USBFS_USBDEV_Type*) &USBFS0->USBDEV) /* 0x403F0000 */ +#define USBFS0_USBLPM ((USBFS_USBLPM_Type*) &USBFS0->USBLPM) /* 0x403F2000 */ +#define USBFS0_USBHOST ((USBFS_USBHOST_Type*) &USBFS0->USBHOST) /* 0x403F4000 */ + +/******************************************************************************* +* SMIF +*******************************************************************************/ + +#define SMIF0_BASE 0x40420000UL +#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ +#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ +#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ +#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ + +/******************************************************************************* +* CANFD +*******************************************************************************/ + +#define CANFD0_BASE 0x40520000UL +#define CANFD0 ((CANFD_Type*) CANFD0_BASE) /* 0x40520000 */ +#define CANFD0_CH0 ((CANFD_CH_Type*) &CANFD0->CH[0]) /* 0x40520000 */ +#define CANFD0_CH0_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[0].M_TTCAN) /* 0x40520000 */ + +/******************************************************************************* +* SCB +*******************************************************************************/ + +#define SCB0_BASE 0x40600000UL +#define SCB1_BASE 0x40610000UL +#define SCB2_BASE 0x40620000UL +#define SCB4_BASE 0x40640000UL +#define SCB5_BASE 0x40650000UL +#define SCB6_BASE 0x40660000UL +#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40600000 */ +#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40610000 */ +#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40620000 */ +#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40640000 */ +#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40650000 */ +#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40660000 */ + +/******************************************************************************* +* CTBM +*******************************************************************************/ + +#define CTBM0_BASE 0x40900000UL +#define CTBM0 ((CTBM_Type*) CTBM0_BASE) /* 0x40900000 */ + +/******************************************************************************* +* CTDAC +*******************************************************************************/ + +#define CTDAC0_BASE 0x40940000UL +#define CTDAC0 ((CTDAC_Type*) CTDAC0_BASE) /* 0x40940000 */ + +/******************************************************************************* +* SAR +*******************************************************************************/ + +#define SAR0_BASE 0x409B0000UL +#define SAR1_BASE 0x409C0000UL +#define SAR0 ((SAR_Type*) SAR0_BASE) /* 0x409B0000 */ +#define SAR1 ((SAR_Type*) SAR1_BASE) /* 0x409C0000 */ + +/******************************************************************************* +* PASS +*******************************************************************************/ + +#define PASS_BASE 0x409F0000UL +#define PASS ((PASS_Type*) PASS_BASE) /* 0x409F0000 */ +#define PASS_TIMER ((PASS_TIMER_Type*) &PASS->TIMER) /* 0x409F0100 */ +#define PASS_LPOSC ((PASS_LPOSC_Type*) &PASS->LPOSC) /* 0x409F0200 */ +#define PASS_FIFO0 ((PASS_FIFO_Type*) &PASS->FIFO[0]) /* 0x409F0300 */ +#define PASS_FIFO1 ((PASS_FIFO_Type*) &PASS->FIFO[1]) /* 0x409F0400 */ +#define PASS_AREFV2 ((PASS_AREFV2_Type*) &PASS->AREFV2) /* 0x409F0E00 */ + +/** \} CY8C6144LQI-S4F82 */ + +#endif /* _CY8C6144LQI_S4F82_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6144lqi_s4f92.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6144lqi_s4f92.h new file mode 100644 index 0000000000..c6f9a35c82 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6144lqi_s4f92.h @@ -0,0 +1,993 @@ +/***************************************************************************//** +* \file cy8c6144lqi_s4f92.h +* +* \brief +* CY8C6144LQI-S4F92 device header +* +* \note +* Generator version: 1.6.0.225 +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CY8C6144LQI_S4F92_H_ +#define _CY8C6144LQI_S4F92_H_ + +/** +* \addtogroup group_device CY8C6144LQI-S4F92 +* \{ +*/ + +/** +* \addtogroup Configuration_of_CMSIS +* \{ +*/ + +/******************************************************************************* +* Interrupt Number Definition +*******************************************************************************/ + +typedef enum { + /* ARM Cortex-M4 Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C6144LQI-S4F92 Peripheral Interrupt Numbers */ + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_6_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #6 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + pass_interrupt_sar_0_IRQn = 39, /*!< 39 [DeepSleep] SAR ADC0 interrupt */ + pass_interrupt_sar_1_IRQn = 40, /*!< 40 [DeepSleep] SAR ADC1 interrupt */ + pass_interrupt_ctb_IRQn = 41, /*!< 41 [DeepSleep] individual interrupt per CTB */ + pass_interrupt_fifo_0_IRQn = 43, /*!< 43 [DeepSleep] PASS FIFO0 */ + pass_interrupt_fifo_1_IRQn = 44, /*!< 44 [DeepSleep] PASS FIFO1 */ + scb_0_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #2 */ + scb_4_interrupt_IRQn = 49, /*!< 49 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 50, /*!< 50 [Active] Serial Communication Block #5 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_0_interrupts_256_IRQn = 131, /*!< 131 [Active] TCPWM #0, Counter #256 */ + tcpwm_0_interrupts_257_IRQn = 132, /*!< 132 [Active] TCPWM #0, Counter #257 */ + tcpwm_0_interrupts_258_IRQn = 133, /*!< 133 [Active] TCPWM #0, Counter #258 */ + tcpwm_0_interrupts_259_IRQn = 134, /*!< 134 [Active] TCPWM #0, Counter #259 */ + tcpwm_0_interrupts_260_IRQn = 135, /*!< 135 [Active] TCPWM #0, Counter #260 */ + tcpwm_0_interrupts_261_IRQn = 136, /*!< 136 [Active] TCPWM #0, Counter #261 */ + tcpwm_0_interrupts_262_IRQn = 137, /*!< 137 [Active] TCPWM #0, Counter #262 */ + tcpwm_0_interrupts_263_IRQn = 138, /*!< 138 [Active] TCPWM #0, Counter #263 */ + pass_interrupt_dacs_IRQn = 146, /*!< 146 [Active] Consolidated interrrupt for all DACs */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + canfd_0_interrupt0_IRQn = 168, /*!< 168 [Active] Can #0, Consolidated interrupt #0 */ + canfd_0_interrupts0_0_IRQn = 169, /*!< 169 [Active] CAN #0, Interrupt #0, Channel #0 */ + canfd_0_interrupts1_0_IRQn = 170, /*!< 170 [Active] CAN #0, Interrupt #1, Channel #0 */ + cpuss_interrupts_dw1_29_IRQn = 171, /*!< 171 [Active] CPUSS DataWire #1, Channel #29 */ + cpuss_interrupts_dw1_30_IRQn = 172, /*!< 172 [Active] CPUSS DataWire #1, Channel #30 */ + cpuss_interrupts_dw1_31_IRQn = 173, /*!< 173 [Active] CPUSS DataWire #1, Channel #31 */ + cpuss_interrupts_dw0_29_IRQn = 174, /*!< 174 [Active] CPUSS DataWire #0, Channel #29 */ + unconnected_IRQn = 240 /*!< 240 Unconnected */ +} IRQn_Type; + + +/******************************************************************************* +* Processor and Core Peripheral Section +*******************************************************************************/ + +/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __CM0P_PRESENT 0 /*!< CM0P present or not */ +#define __DTCM_PRESENT 0 /*!< DTCM present or not */ +#define __ICACHE_PRESENT 0 /*!< ICACHE present or not */ +#define __DCACHE_PRESENT 0 /*!< DCACHE present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + + +/* Memory Blocks */ +#define CY_ROM_BASE 0x00000000UL +#define CY_ROM_SIZE 0x00010000UL +#define CY_SRAM_BASE 0x08000000UL +#define CY_SRAM_SIZE 0x00020000UL +#define CY_FLASH_BASE 0x10000000UL +#define CY_FLASH_SIZE 0x00040000UL +#define CY_EM_EEPROM_BASE 0x14000000UL +#define CY_EM_EEPROM_SIZE 0x00000000UL +#define CY_SFLASH_BASE 0x16000000UL +#define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL +#define CY_EFUSE_BASE 0x402C0800UL +#define CY_EFUSE_SIZE 0x00000200UL +#define CY_CAN0MRAM_BASE 0x40530000UL +#define CY_CAN0MRAM_SIZE 0x00010000UL + +#include "system_psoc6.h" /*!< PSoC 6 System */ + +/* IP List */ +#define CY_IP_MXTTCANFD 1u +#define CY_IP_MXTTCANFD_INSTANCES 1u +#define CY_IP_MXTTCANFD_VERSION 1u +#define CY_IP_M4CPUSS 1u +#define CY_IP_M4CPUSS_INSTANCES 1u +#define CY_IP_M4CPUSS_VERSION 2u +#define CY_IP_M4CPUSS_DMAC 1u +#define CY_IP_M4CPUSS_DMAC_INSTANCES 1u +#define CY_IP_M4CPUSS_DMAC_VERSION 2u +#define CY_IP_M4CPUSS_DMA 1u +#define CY_IP_M4CPUSS_DMA_INSTANCES 2u +#define CY_IP_M4CPUSS_DMA_VERSION 2u +#define CY_IP_MXCRYPTO 1u +#define CY_IP_MXCRYPTO_INSTANCES 1u +#define CY_IP_MXCRYPTO_VERSION 2u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 2u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 6u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u + +#include "psoc6_04_config.h" +#include "gpio_psoc6_04_68_qfn.h" + +#define CY_DEVICE_PSOC6A256K +#define CY_SILICON_ID 0xEACB110EUL +#define CY_HF_CLK_MAX_FREQ 150000000UL + +#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL + +/******************************************************************************* +* SFLASH +*******************************************************************************/ + +#define SFLASH_BASE 0x16000000UL +#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */ + +/******************************************************************************* +* PERI +*******************************************************************************/ + +#define PERI_BASE 0x40000000UL +#define PERI ((PERI_Type*) PERI_BASE) /* 0x40000000 */ +#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40004000 */ +#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40004020 */ +#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40004040 */ +#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x40004060 */ +#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40004080 */ +#define PERI_GR5 ((PERI_GR_Type*) &PERI->GR[5]) /* 0x400040A0 */ +#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x400040C0 */ +#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40004120 */ +#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40008000 */ +#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40008400 */ +#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40008800 */ +#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40008C00 */ +#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40009000 */ +#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40009400 */ +#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40009800 */ +#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40009C00 */ +#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ +#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ +#define PERI_TR_GR10 ((PERI_TR_GR_Type*) &PERI->TR_GR[10]) /* 0x4000A800 */ +#define PERI_TR_GR11 ((PERI_TR_GR_Type*) &PERI->TR_GR[11]) /* 0x4000AC00 */ +#define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ +#define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ +#define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ +#define PERI_TR_1TO1_GR3 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[3]) /* 0x4000CC00 */ +#define PERI_TR_1TO1_GR4 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[4]) /* 0x4000D000 */ +#define PERI_TR_1TO1_GR5 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[5]) /* 0x4000D400 */ +#define PERI_TR_1TO1_GR6 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[6]) /* 0x4000D800 */ +#define PERI_TR_1TO1_GR7 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[7]) /* 0x4000DC00 */ +#define PERI_TR_1TO1_GR8 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[8]) /* 0x4000E000 */ + +/******************************************************************************* +* PERI_MS +*******************************************************************************/ + +#define PERI_MS_BASE 0x40010000UL +#define PERI_MS ((PERI_MS_Type*) PERI_MS_BASE) /* 0x40010000 */ +#define PERI_MS_PPU_PR0 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[0]) /* 0x40010000 */ +#define PERI_MS_PPU_PR1 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[1]) /* 0x40010040 */ +#define PERI_MS_PPU_PR2 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[2]) /* 0x40010080 */ +#define PERI_MS_PPU_PR3 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[3]) /* 0x400100C0 */ +#define PERI_MS_PPU_PR4 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[4]) /* 0x40010100 */ +#define PERI_MS_PPU_PR5 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[5]) /* 0x40010140 */ +#define PERI_MS_PPU_PR6 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[6]) /* 0x40010180 */ +#define PERI_MS_PPU_PR7 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[7]) /* 0x400101C0 */ +#define PERI_MS_PPU_FX_PERI_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[0]) /* 0x40010800 */ +#define PERI_MS_PPU_FX_PERI_GR0_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[1]) /* 0x40010840 */ +#define PERI_MS_PPU_FX_PERI_GR1_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[2]) /* 0x40010880 */ +#define PERI_MS_PPU_FX_PERI_GR2_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[3]) /* 0x400108C0 */ +#define PERI_MS_PPU_FX_PERI_GR3_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[4]) /* 0x40010900 */ +#define PERI_MS_PPU_FX_PERI_GR4_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[5]) /* 0x40010940 */ +#define PERI_MS_PPU_FX_PERI_GR5_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[6]) /* 0x40010980 */ +#define PERI_MS_PPU_FX_PERI_GR6_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[7]) /* 0x400109C0 */ +#define PERI_MS_PPU_FX_PERI_GR9_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[8]) /* 0x40010A00 */ +#define PERI_MS_PPU_FX_PERI_TR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[9]) /* 0x40010A40 */ +#define PERI_MS_PPU_FX_CRYPTO_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[10]) /* 0x40010A80 */ +#define PERI_MS_PPU_FX_CRYPTO_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[11]) /* 0x40010AC0 */ +#define PERI_MS_PPU_FX_CRYPTO_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[12]) /* 0x40010B00 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[13]) /* 0x40010B40 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[14]) /* 0x40010B80 */ +#define PERI_MS_PPU_FX_CRYPTO_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[15]) /* 0x40010BC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[16]) /* 0x40010C00 */ +#define PERI_MS_PPU_FX_CPUSS_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[17]) /* 0x40010C40 */ +#define PERI_MS_PPU_FX_CPUSS_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[18]) /* 0x40010C80 */ +#define PERI_MS_PPU_FX_CPUSS_CM0_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[19]) /* 0x40010CC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[20]) /* 0x40010D00 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[21]) /* 0x40010D40 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT1_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[22]) /* 0x40010D80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT0_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[23]) /* 0x40010DC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT1_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[24]) /* 0x40010E00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT2_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[25]) /* 0x40010E40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT3_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[26]) /* 0x40010E80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT4_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[27]) /* 0x40010EC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT5_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[28]) /* 0x40010F00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT6_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[29]) /* 0x40010F40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT7_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[30]) /* 0x40010F80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT8_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[31]) /* 0x40010FC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT9_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[32]) /* 0x40011000 */ +#define PERI_MS_PPU_FX_IPC_STRUCT10_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[33]) /* 0x40011040 */ +#define PERI_MS_PPU_FX_IPC_STRUCT11_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[34]) /* 0x40011080 */ +#define PERI_MS_PPU_FX_IPC_STRUCT12_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[35]) /* 0x400110C0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT13_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[36]) /* 0x40011100 */ +#define PERI_MS_PPU_FX_IPC_STRUCT14_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[37]) /* 0x40011140 */ +#define PERI_MS_PPU_FX_IPC_STRUCT15_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[38]) /* 0x40011180 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT0_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[39]) /* 0x400111C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT1_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[40]) /* 0x40011200 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT2_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[41]) /* 0x40011240 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT3_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[42]) /* 0x40011280 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT4_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[43]) /* 0x400112C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT5_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[44]) /* 0x40011300 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT6_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[45]) /* 0x40011340 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT7_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[46]) /* 0x40011380 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT8_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[47]) /* 0x400113C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT9_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[48]) /* 0x40011400 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT10_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[49]) /* 0x40011440 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT11_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[50]) /* 0x40011480 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT12_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[51]) /* 0x400114C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT13_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[52]) /* 0x40011500 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT14_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[53]) /* 0x40011540 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT15_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[54]) /* 0x40011580 */ +#define PERI_MS_PPU_FX_PROT_SMPU_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[55]) /* 0x400115C0 */ +#define PERI_MS_PPU_FX_PROT_MPU0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[56]) /* 0x40011600 */ +#define PERI_MS_PPU_FX_PROT_MPU14_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[57]) /* 0x40011640 */ +#define PERI_MS_PPU_FX_PROT_MPU15_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[58]) /* 0x40011680 */ +#define PERI_MS_PPU_FX_FLASHC_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[59]) /* 0x400116C0 */ +#define PERI_MS_PPU_FX_FLASHC_CMD ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[60]) /* 0x40011700 */ +#define PERI_MS_PPU_FX_FLASHC_DFT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[61]) /* 0x40011740 */ +#define PERI_MS_PPU_FX_FLASHC_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[62]) /* 0x40011780 */ +#define PERI_MS_PPU_FX_FLASHC_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[63]) /* 0x400117C0 */ +#define PERI_MS_PPU_FX_FLASHC_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[64]) /* 0x40011800 */ +#define PERI_MS_PPU_FX_FLASHC_DW0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[65]) /* 0x40011840 */ +#define PERI_MS_PPU_FX_FLASHC_DW1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[66]) /* 0x40011880 */ +#define PERI_MS_PPU_FX_FLASHC_DMAC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[67]) /* 0x400118C0 */ +#define PERI_MS_PPU_FX_FLASHC_FM ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[68]) /* 0x40011900 */ +#define PERI_MS_PPU_FX_SRSS_MAIN1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[69]) /* 0x40011940 */ +#define PERI_MS_PPU_FX_SRSS_MAIN2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[70]) /* 0x40011980 */ +#define PERI_MS_PPU_FX_WDT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[71]) /* 0x400119C0 */ +#define PERI_MS_PPU_FX_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[72]) /* 0x40011A00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[73]) /* 0x40011A40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[74]) /* 0x40011A80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[75]) /* 0x40011AC0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[76]) /* 0x40011B00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[77]) /* 0x40011B40 */ +#define PERI_MS_PPU_FX_BACKUP_BACKUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[78]) /* 0x40011B80 */ +#define PERI_MS_PPU_FX_DW0_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[79]) /* 0x40011BC0 */ +#define PERI_MS_PPU_FX_DW1_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[80]) /* 0x40011C00 */ +#define PERI_MS_PPU_FX_DW0_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[81]) /* 0x40011C40 */ +#define PERI_MS_PPU_FX_DW1_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[82]) /* 0x40011C80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[83]) /* 0x40011CC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[84]) /* 0x40011D00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[85]) /* 0x40011D40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[86]) /* 0x40011D80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[87]) /* 0x40011DC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[88]) /* 0x40011E00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[89]) /* 0x40011E40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[90]) /* 0x40011E80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[91]) /* 0x40011EC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[92]) /* 0x40011F00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[93]) /* 0x40011F40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[94]) /* 0x40011F80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[95]) /* 0x40011FC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[96]) /* 0x40012000 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[97]) /* 0x40012040 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[98]) /* 0x40012080 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[99]) /* 0x400120C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[100]) /* 0x40012100 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[101]) /* 0x40012140 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[102]) /* 0x40012180 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[103]) /* 0x400121C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[104]) /* 0x40012200 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[105]) /* 0x40012240 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[106]) /* 0x40012280 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[107]) /* 0x400122C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[108]) /* 0x40012300 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[109]) /* 0x40012340 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[110]) /* 0x40012380 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[111]) /* 0x400123C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT29_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[112]) /* 0x40012400 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[113]) /* 0x40012440 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[114]) /* 0x40012480 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[115]) /* 0x400124C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[116]) /* 0x40012500 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[117]) /* 0x40012540 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[118]) /* 0x40012580 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[119]) /* 0x400125C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[120]) /* 0x40012600 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[121]) /* 0x40012640 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[122]) /* 0x40012680 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[123]) /* 0x400126C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[124]) /* 0x40012700 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[125]) /* 0x40012740 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[126]) /* 0x40012780 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[127]) /* 0x400127C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[128]) /* 0x40012800 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[129]) /* 0x40012840 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[130]) /* 0x40012880 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[131]) /* 0x400128C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[132]) /* 0x40012900 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[133]) /* 0x40012940 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[134]) /* 0x40012980 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[135]) /* 0x400129C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[136]) /* 0x40012A00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[137]) /* 0x40012A40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[138]) /* 0x40012A80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[139]) /* 0x40012AC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[140]) /* 0x40012B00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[141]) /* 0x40012B40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT29_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[142]) /* 0x40012B80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT30_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[143]) /* 0x40012BC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT31_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[144]) /* 0x40012C00 */ +#define PERI_MS_PPU_FX_DMAC_TOP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[145]) /* 0x40012C40 */ +#define PERI_MS_PPU_FX_DMAC_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[146]) /* 0x40012C80 */ +#define PERI_MS_PPU_FX_DMAC_CH1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[147]) /* 0x40012CC0 */ +#define PERI_MS_PPU_FX_EFUSE_CTL ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[148]) /* 0x40012D00 */ +#define PERI_MS_PPU_FX_EFUSE_DATA ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[149]) /* 0x40012D40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[150]) /* 0x40012D80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[151]) /* 0x40012DC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[152]) /* 0x40012E00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[153]) /* 0x40012E40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[154]) /* 0x40012E80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[155]) /* 0x40012EC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[156]) /* 0x40012F00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[157]) /* 0x40012F40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[158]) /* 0x40012F80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[159]) /* 0x40012FC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[160]) /* 0x40013000 */ +#define PERI_MS_PPU_FX_HSIOM_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[161]) /* 0x40013040 */ +#define PERI_MS_PPU_FX_HSIOM_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[162]) /* 0x40013080 */ +#define PERI_MS_PPU_FX_HSIOM_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[163]) /* 0x400130C0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[164]) /* 0x40013100 */ +#define PERI_MS_PPU_FX_HSIOM_AMUX ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[165]) /* 0x40013140 */ +#define PERI_MS_PPU_FX_HSIOM_MON ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[166]) /* 0x40013180 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[167]) /* 0x400131C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[168]) /* 0x40013200 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[169]) /* 0x40013240 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[170]) /* 0x40013280 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[171]) /* 0x400132C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[172]) /* 0x40013300 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[173]) /* 0x40013340 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[174]) /* 0x40013380 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[175]) /* 0x400133C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[176]) /* 0x40013400 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[177]) /* 0x40013440 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[178]) /* 0x40013480 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[179]) /* 0x400134C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[180]) /* 0x40013500 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[181]) /* 0x40013540 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[182]) /* 0x40013580 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[183]) /* 0x400135C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[184]) /* 0x40013600 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[185]) /* 0x40013640 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[186]) /* 0x40013680 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[187]) /* 0x400136C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[188]) /* 0x40013700 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[189]) /* 0x40013740 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[190]) /* 0x40013780 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[191]) /* 0x400137C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[192]) /* 0x40013800 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[193]) /* 0x40013840 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[194]) /* 0x40013880 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[195]) /* 0x400138C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[196]) /* 0x40013900 */ +#define PERI_MS_PPU_FX_GPIO_GPIO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[197]) /* 0x40013940 */ +#define PERI_MS_PPU_FX_GPIO_TEST ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[198]) /* 0x40013980 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[199]) /* 0x400139C0 */ +#define PERI_MS_PPU_FX_LPCOMP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[200]) /* 0x40013A00 */ +#define PERI_MS_PPU_FX_CSD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[201]) /* 0x40013A40 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT0_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[202]) /* 0x40013A80 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT1_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[203]) /* 0x40013AC0 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT2_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[204]) /* 0x40013B00 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT3_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[205]) /* 0x40013B40 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT0_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[206]) /* 0x40013B80 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT1_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[207]) /* 0x40013BC0 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT2_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[208]) /* 0x40013C00 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT3_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[209]) /* 0x40013C40 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT4_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[210]) /* 0x40013C80 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT5_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[211]) /* 0x40013CC0 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT6_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[212]) /* 0x40013D00 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT7_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[213]) /* 0x40013D40 */ +#define PERI_MS_PPU_FX_LCD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[214]) /* 0x40013D80 */ +#define PERI_MS_PPU_FX_USBFS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[215]) /* 0x40013DC0 */ +#define PERI_MS_PPU_FX_SMIF0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[216]) /* 0x40013E00 */ +#define PERI_MS_PPU_FX_CANFD0_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[217]) /* 0x40013E40 */ +#define PERI_MS_PPU_FX_CANFD0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[218]) /* 0x40013E80 */ +#define PERI_MS_PPU_FX_CANFD0_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[219]) /* 0x40013EC0 */ +#define PERI_MS_PPU_FX_SCB0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[220]) /* 0x40013F00 */ +#define PERI_MS_PPU_FX_SCB1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[221]) /* 0x40013F40 */ +#define PERI_MS_PPU_FX_SCB2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[222]) /* 0x40013F80 */ +#define PERI_MS_PPU_FX_SCB4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[223]) /* 0x40013FC0 */ +#define PERI_MS_PPU_FX_SCB5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[224]) /* 0x40014000 */ +#define PERI_MS_PPU_FX_SCB6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[225]) /* 0x40014040 */ + +/******************************************************************************* +* CRYPTO +*******************************************************************************/ + +#define CRYPTO_BASE 0x40100000UL +#define CRYPTO ((CRYPTO_Type*) CRYPTO_BASE) /* 0x40100000 */ + +/******************************************************************************* +* CPUSS +*******************************************************************************/ + +#define CPUSS_BASE 0x40200000UL +#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40200000 */ + +/******************************************************************************* +* FAULT +*******************************************************************************/ + +#define FAULT_BASE 0x40210000UL +#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40210000 */ +#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40210000 */ +#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40210100 */ + +/******************************************************************************* +* IPC +*******************************************************************************/ + +#define IPC_BASE 0x40220000UL +#define IPC ((IPC_Type*) IPC_BASE) /* 0x40220000 */ +#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40220000 */ +#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40220020 */ +#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40220040 */ +#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40220060 */ +#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40220080 */ +#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402200A0 */ +#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402200C0 */ +#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402200E0 */ +#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40220100 */ +#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40220120 */ +#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40220140 */ +#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40220160 */ +#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40220180 */ +#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402201A0 */ +#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402201C0 */ +#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402201E0 */ +#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40221000 */ +#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40221020 */ +#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40221040 */ +#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40221060 */ +#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40221080 */ +#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402210A0 */ +#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402210C0 */ +#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402210E0 */ +#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40221100 */ +#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40221120 */ +#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40221140 */ +#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40221160 */ +#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40221180 */ +#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402211A0 */ +#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402211C0 */ +#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402211E0 */ + +/******************************************************************************* +* PROT +*******************************************************************************/ + +#define PROT_BASE 0x40230000UL +#define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ +#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ +#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ +#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402320C0 */ +#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40232100 */ +#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40232140 */ +#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40232180 */ +#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402321C0 */ +#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40232200 */ +#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40232240 */ +#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40232280 */ +#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402322C0 */ +#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40232300 */ +#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ +#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ +#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ + +/******************************************************************************* +* FLASHC +*******************************************************************************/ + +#define FLASHC_BASE 0x40240000UL +#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40240000 */ +#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4024F000 */ + +/******************************************************************************* +* SRSS +*******************************************************************************/ + +#define SRSS_BASE 0x40260000UL +#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ +#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */ +#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */ + +/******************************************************************************* +* BACKUP +*******************************************************************************/ + +#define BACKUP_BASE 0x40270000UL +#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ + +/******************************************************************************* +* DW +*******************************************************************************/ + +#define DW0_BASE 0x40280000UL +#define DW1_BASE 0x40290000UL +#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ +#define DW1 ((DW_Type*) DW1_BASE) /* 0x40290000 */ +#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40288000 */ +#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40288040 */ +#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40288080 */ +#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x402880C0 */ +#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40288100 */ +#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x40288140 */ +#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x40288180 */ +#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402881C0 */ +#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40288200 */ +#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40288240 */ +#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40288280 */ +#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x402882C0 */ +#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40288300 */ +#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x40288340 */ +#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x40288380 */ +#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402883C0 */ +#define DW0_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[16]) /* 0x40288400 */ +#define DW0_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[17]) /* 0x40288440 */ +#define DW0_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[18]) /* 0x40288480 */ +#define DW0_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[19]) /* 0x402884C0 */ +#define DW0_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[20]) /* 0x40288500 */ +#define DW0_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[21]) /* 0x40288540 */ +#define DW0_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[22]) /* 0x40288580 */ +#define DW0_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[23]) /* 0x402885C0 */ +#define DW0_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[24]) /* 0x40288600 */ +#define DW0_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[25]) /* 0x40288640 */ +#define DW0_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[26]) /* 0x40288680 */ +#define DW0_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[27]) /* 0x402886C0 */ +#define DW0_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[28]) /* 0x40288700 */ +#define DW0_CH_STRUCT29 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[29]) /* 0x40288740 */ +#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40298000 */ +#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40298040 */ +#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40298080 */ +#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x402980C0 */ +#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40298100 */ +#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x40298140 */ +#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x40298180 */ +#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402981C0 */ +#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40298200 */ +#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40298240 */ +#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40298280 */ +#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x402982C0 */ +#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40298300 */ +#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x40298340 */ +#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x40298380 */ +#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402983C0 */ +#define DW1_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[16]) /* 0x40298400 */ +#define DW1_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[17]) /* 0x40298440 */ +#define DW1_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[18]) /* 0x40298480 */ +#define DW1_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[19]) /* 0x402984C0 */ +#define DW1_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[20]) /* 0x40298500 */ +#define DW1_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[21]) /* 0x40298540 */ +#define DW1_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[22]) /* 0x40298580 */ +#define DW1_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[23]) /* 0x402985C0 */ +#define DW1_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[24]) /* 0x40298600 */ +#define DW1_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[25]) /* 0x40298640 */ +#define DW1_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[26]) /* 0x40298680 */ +#define DW1_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[27]) /* 0x402986C0 */ +#define DW1_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[28]) /* 0x40298700 */ +#define DW1_CH_STRUCT29 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[29]) /* 0x40298740 */ +#define DW1_CH_STRUCT30 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[30]) /* 0x40298780 */ +#define DW1_CH_STRUCT31 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[31]) /* 0x402987C0 */ + +/******************************************************************************* +* DMAC +*******************************************************************************/ + +#define DMAC_BASE 0x402A0000UL +#define DMAC ((DMAC_Type*) DMAC_BASE) /* 0x402A0000 */ +#define DMAC_CH0 ((DMAC_CH_Type*) &DMAC->CH[0]) /* 0x402A1000 */ +#define DMAC_CH1 ((DMAC_CH_Type*) &DMAC->CH[1]) /* 0x402A1100 */ + +/******************************************************************************* +* EFUSE +*******************************************************************************/ + +#define EFUSE_BASE 0x402C0000UL +#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ + +/******************************************************************************* +* HSIOM +*******************************************************************************/ + +#define HSIOM_BASE 0x40300000UL +#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40300000 */ +#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40300000 */ +#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40300010 */ +#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40300020 */ +#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40300030 */ +#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40300040 */ +#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40300050 */ +#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40300060 */ +#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40300070 */ +#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40300080 */ +#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40300090 */ +#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403000A0 */ +#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403000B0 */ +#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403000C0 */ +#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403000D0 */ +#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403000E0 */ + +/******************************************************************************* +* GPIO +*******************************************************************************/ + +#define GPIO_BASE 0x40310000UL +#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40310000 */ +#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40310000 */ +#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40310080 */ +#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40310100 */ +#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40310180 */ +#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40310200 */ +#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40310280 */ +#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40310300 */ +#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40310380 */ +#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40310400 */ +#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40310480 */ +#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40310500 */ +#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40310580 */ +#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40310600 */ +#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40310680 */ +#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40310700 */ + +/******************************************************************************* +* SMARTIO +*******************************************************************************/ + +#define SMARTIO_BASE 0x40320000UL +#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40320000 */ +#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40320900 */ + +/******************************************************************************* +* LPCOMP +*******************************************************************************/ + +#define LPCOMP_BASE 0x40350000UL +#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */ + +/******************************************************************************* +* CSD +*******************************************************************************/ + +#define CSD0_BASE 0x40360000UL +#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */ + +/******************************************************************************* +* TCPWM +*******************************************************************************/ + +#define TCPWM0_BASE 0x40380000UL +#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM0_GRP0 ((TCPWM_GRP_Type*) &TCPWM0->GRP[0]) /* 0x40380000 */ +#define TCPWM0_GRP1 ((TCPWM_GRP_Type*) &TCPWM0->GRP[1]) /* 0x40388000 */ +#define TCPWM0_GRP0_CNT0 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[0]) /* 0x40380000 */ +#define TCPWM0_GRP0_CNT1 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[1]) /* 0x40380080 */ +#define TCPWM0_GRP0_CNT2 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[2]) /* 0x40380100 */ +#define TCPWM0_GRP0_CNT3 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[3]) /* 0x40380180 */ +#define TCPWM0_GRP1_CNT0 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[0]) /* 0x40388000 */ +#define TCPWM0_GRP1_CNT1 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[1]) /* 0x40388080 */ +#define TCPWM0_GRP1_CNT2 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[2]) /* 0x40388100 */ +#define TCPWM0_GRP1_CNT3 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[3]) /* 0x40388180 */ +#define TCPWM0_GRP1_CNT4 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[4]) /* 0x40388200 */ +#define TCPWM0_GRP1_CNT5 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[5]) /* 0x40388280 */ +#define TCPWM0_GRP1_CNT6 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[6]) /* 0x40388300 */ +#define TCPWM0_GRP1_CNT7 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[7]) /* 0x40388380 */ + +/******************************************************************************* +* LCD +*******************************************************************************/ + +#define LCD0_BASE 0x403B0000UL +#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ + +/******************************************************************************* +* USBFS +*******************************************************************************/ + +#define USBFS0_BASE 0x403F0000UL +#define USBFS0 ((USBFS_Type*) USBFS0_BASE) /* 0x403F0000 */ +#define USBFS0_USBDEV ((USBFS_USBDEV_Type*) &USBFS0->USBDEV) /* 0x403F0000 */ +#define USBFS0_USBLPM ((USBFS_USBLPM_Type*) &USBFS0->USBLPM) /* 0x403F2000 */ +#define USBFS0_USBHOST ((USBFS_USBHOST_Type*) &USBFS0->USBHOST) /* 0x403F4000 */ + +/******************************************************************************* +* SMIF +*******************************************************************************/ + +#define SMIF0_BASE 0x40420000UL +#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ +#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ +#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ +#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ + +/******************************************************************************* +* CANFD +*******************************************************************************/ + +#define CANFD0_BASE 0x40520000UL +#define CANFD0 ((CANFD_Type*) CANFD0_BASE) /* 0x40520000 */ +#define CANFD0_CH0 ((CANFD_CH_Type*) &CANFD0->CH[0]) /* 0x40520000 */ +#define CANFD0_CH0_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[0].M_TTCAN) /* 0x40520000 */ + +/******************************************************************************* +* SCB +*******************************************************************************/ + +#define SCB0_BASE 0x40600000UL +#define SCB1_BASE 0x40610000UL +#define SCB2_BASE 0x40620000UL +#define SCB4_BASE 0x40640000UL +#define SCB5_BASE 0x40650000UL +#define SCB6_BASE 0x40660000UL +#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40600000 */ +#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40610000 */ +#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40620000 */ +#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40640000 */ +#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40650000 */ +#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40660000 */ + +/******************************************************************************* +* CTBM +*******************************************************************************/ + +#define CTBM0_BASE 0x40900000UL +#define CTBM0 ((CTBM_Type*) CTBM0_BASE) /* 0x40900000 */ + +/******************************************************************************* +* CTDAC +*******************************************************************************/ + +#define CTDAC0_BASE 0x40940000UL +#define CTDAC0 ((CTDAC_Type*) CTDAC0_BASE) /* 0x40940000 */ + +/******************************************************************************* +* SAR +*******************************************************************************/ + +#define SAR0_BASE 0x409B0000UL +#define SAR1_BASE 0x409C0000UL +#define SAR0 ((SAR_Type*) SAR0_BASE) /* 0x409B0000 */ +#define SAR1 ((SAR_Type*) SAR1_BASE) /* 0x409C0000 */ + +/******************************************************************************* +* PASS +*******************************************************************************/ + +#define PASS_BASE 0x409F0000UL +#define PASS ((PASS_Type*) PASS_BASE) /* 0x409F0000 */ +#define PASS_TIMER ((PASS_TIMER_Type*) &PASS->TIMER) /* 0x409F0100 */ +#define PASS_LPOSC ((PASS_LPOSC_Type*) &PASS->LPOSC) /* 0x409F0200 */ +#define PASS_FIFO0 ((PASS_FIFO_Type*) &PASS->FIFO[0]) /* 0x409F0300 */ +#define PASS_FIFO1 ((PASS_FIFO_Type*) &PASS->FIFO[1]) /* 0x409F0400 */ +#define PASS_AREFV2 ((PASS_AREFV2_Type*) &PASS->AREFV2) /* 0x409F0E00 */ + +/** \} CY8C6144LQI-S4F92 */ + +#endif /* _CY8C6144LQI_S4F92_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6145azi_s3f02.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6145azi_s3f02.h new file mode 100644 index 0000000000..7d4466a393 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6145azi_s3f02.h @@ -0,0 +1,983 @@ +/***************************************************************************//** +* \file cy8c6145azi_s3f02.h +* +* \brief +* CY8C6145AZI-S3F02 device header +* +* \note +* Generator version: 1.6.0.225 +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CY8C6145AZI_S3F02_H_ +#define _CY8C6145AZI_S3F02_H_ + +/** +* \addtogroup group_device CY8C6145AZI-S3F02 +* \{ +*/ + +/** +* \addtogroup Configuration_of_CMSIS +* \{ +*/ + +/******************************************************************************* +* Interrupt Number Definition +*******************************************************************************/ + +typedef enum { + /* ARM Cortex-M4 Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C6145AZI-S3F02 Peripheral Interrupt Numbers */ + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_6_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #6 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + canfd_0_interrupt0_IRQn = 168, /*!< 168 [Active] Can #0, Consolidated interrupt #0 */ + canfd_0_interrupts0_0_IRQn = 169, /*!< 169 [Active] CAN #0, Interrupt #0, Channel #0 */ + canfd_0_interrupts1_0_IRQn = 170, /*!< 170 [Active] CAN #0, Interrupt #1, Channel #0 */ + cpuss_interrupts_dw1_29_IRQn = 171, /*!< 171 [Active] CPUSS DataWire #1, Channel #29 */ + cpuss_interrupts_dw1_30_IRQn = 172, /*!< 172 [Active] CPUSS DataWire #1, Channel #30 */ + cpuss_interrupts_dw1_31_IRQn = 173, /*!< 173 [Active] CPUSS DataWire #1, Channel #31 */ + unconnected_IRQn = 240 /*!< 240 Unconnected */ +} IRQn_Type; + + +/******************************************************************************* +* Processor and Core Peripheral Section +*******************************************************************************/ + +/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __CM0P_PRESENT 0 /*!< CM0P present or not */ +#define __DTCM_PRESENT 0 /*!< DTCM present or not */ +#define __ICACHE_PRESENT 0 /*!< ICACHE present or not */ +#define __DCACHE_PRESENT 0 /*!< DCACHE present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + + +/* Memory Blocks */ +#define CY_ROM_BASE 0x00000000UL +#define CY_ROM_SIZE 0x00010000UL +#define CY_SRAM_BASE 0x08000000UL +#define CY_SRAM_SIZE 0x00040000UL +#define CY_FLASH_BASE 0x10000000UL +#define CY_FLASH_SIZE 0x00080000UL +#define CY_EM_EEPROM_BASE 0x14000000UL +#define CY_EM_EEPROM_SIZE 0x00008000UL +#define CY_SFLASH_BASE 0x16000000UL +#define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL +#define CY_EFUSE_BASE 0x402C0800UL +#define CY_EFUSE_SIZE 0x00000200UL +#define CY_CAN0MRAM_BASE 0x40530000UL +#define CY_CAN0MRAM_SIZE 0x00010000UL + +#include "system_psoc6.h" /*!< PSoC 6 System */ + +/* IP List */ +#define CY_IP_MXTTCANFD 1u +#define CY_IP_MXTTCANFD_INSTANCES 1u +#define CY_IP_MXTTCANFD_VERSION 1u +#define CY_IP_M4CPUSS 1u +#define CY_IP_M4CPUSS_INSTANCES 1u +#define CY_IP_M4CPUSS_VERSION 2u +#define CY_IP_M4CPUSS_DMAC 1u +#define CY_IP_M4CPUSS_DMAC_INSTANCES 1u +#define CY_IP_M4CPUSS_DMAC_VERSION 2u +#define CY_IP_M4CPUSS_DMA 1u +#define CY_IP_M4CPUSS_DMA_INSTANCES 2u +#define CY_IP_M4CPUSS_DMA_VERSION 2u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 2u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u +#define CY_IP_MXS40PASS 1u +#define CY_IP_MXS40PASS_INSTANCES 1u +#define CY_IP_MXS40PASS_VERSION 1u +#define CY_IP_MXS40PASS_SAR 1u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u +#define CY_IP_MXS40PASS_SAR_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 7u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 1u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u + +#include "psoc6_03_config.h" +#include "gpio_psoc6_03_100_tqfp.h" + +#define CY_DEVICE_PSOC6A512K +#define CY_SILICON_ID 0xE71A1105UL +#define CY_HF_CLK_MAX_FREQ 150000000UL + +#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL + +/******************************************************************************* +* SFLASH +*******************************************************************************/ + +#define SFLASH_BASE 0x16000000UL +#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */ + +/******************************************************************************* +* PERI +*******************************************************************************/ + +#define PERI_BASE 0x40000000UL +#define PERI ((PERI_Type*) PERI_BASE) /* 0x40000000 */ +#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40004000 */ +#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40004020 */ +#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40004040 */ +#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x40004060 */ +#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40004080 */ +#define PERI_GR5 ((PERI_GR_Type*) &PERI->GR[5]) /* 0x400040A0 */ +#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x400040C0 */ +#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40004120 */ +#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40008000 */ +#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40008400 */ +#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40008800 */ +#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40008C00 */ +#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40009000 */ +#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40009400 */ +#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40009800 */ +#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40009C00 */ +#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ +#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ +#define PERI_TR_GR10 ((PERI_TR_GR_Type*) &PERI->TR_GR[10]) /* 0x4000A800 */ +#define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ +#define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ +#define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ +#define PERI_TR_1TO1_GR3 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[3]) /* 0x4000CC00 */ +#define PERI_TR_1TO1_GR4 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[4]) /* 0x4000D000 */ +#define PERI_TR_1TO1_GR5 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[5]) /* 0x4000D400 */ +#define PERI_TR_1TO1_GR6 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[6]) /* 0x4000D800 */ +#define PERI_TR_1TO1_GR7 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[7]) /* 0x4000DC00 */ + +/******************************************************************************* +* PERI_MS +*******************************************************************************/ + +#define PERI_MS_BASE 0x40010000UL +#define PERI_MS ((PERI_MS_Type*) PERI_MS_BASE) /* 0x40010000 */ +#define PERI_MS_PPU_PR0 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[0]) /* 0x40010000 */ +#define PERI_MS_PPU_PR1 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[1]) /* 0x40010040 */ +#define PERI_MS_PPU_PR2 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[2]) /* 0x40010080 */ +#define PERI_MS_PPU_PR3 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[3]) /* 0x400100C0 */ +#define PERI_MS_PPU_PR4 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[4]) /* 0x40010100 */ +#define PERI_MS_PPU_PR5 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[5]) /* 0x40010140 */ +#define PERI_MS_PPU_PR6 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[6]) /* 0x40010180 */ +#define PERI_MS_PPU_PR7 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[7]) /* 0x400101C0 */ +#define PERI_MS_PPU_FX_PERI_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[0]) /* 0x40010800 */ +#define PERI_MS_PPU_FX_PERI_GR0_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[1]) /* 0x40010840 */ +#define PERI_MS_PPU_FX_PERI_GR1_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[2]) /* 0x40010880 */ +#define PERI_MS_PPU_FX_PERI_GR2_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[3]) /* 0x400108C0 */ +#define PERI_MS_PPU_FX_PERI_GR3_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[4]) /* 0x40010900 */ +#define PERI_MS_PPU_FX_PERI_GR4_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[5]) /* 0x40010940 */ +#define PERI_MS_PPU_FX_PERI_GR5_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[6]) /* 0x40010980 */ +#define PERI_MS_PPU_FX_PERI_GR6_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[7]) /* 0x400109C0 */ +#define PERI_MS_PPU_FX_PERI_GR9_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[8]) /* 0x40010A00 */ +#define PERI_MS_PPU_FX_PERI_TR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[9]) /* 0x40010A40 */ +#define PERI_MS_PPU_FX_CRYPTO_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[10]) /* 0x40010A80 */ +#define PERI_MS_PPU_FX_CRYPTO_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[11]) /* 0x40010AC0 */ +#define PERI_MS_PPU_FX_CRYPTO_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[12]) /* 0x40010B00 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[13]) /* 0x40010B40 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[14]) /* 0x40010B80 */ +#define PERI_MS_PPU_FX_CRYPTO_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[15]) /* 0x40010BC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[16]) /* 0x40010C00 */ +#define PERI_MS_PPU_FX_CPUSS_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[17]) /* 0x40010C40 */ +#define PERI_MS_PPU_FX_CPUSS_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[18]) /* 0x40010C80 */ +#define PERI_MS_PPU_FX_CPUSS_CM0_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[19]) /* 0x40010CC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[20]) /* 0x40010D00 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[21]) /* 0x40010D40 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT1_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[22]) /* 0x40010D80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT0_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[23]) /* 0x40010DC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT1_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[24]) /* 0x40010E00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT2_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[25]) /* 0x40010E40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT3_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[26]) /* 0x40010E80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT4_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[27]) /* 0x40010EC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT5_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[28]) /* 0x40010F00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT6_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[29]) /* 0x40010F40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT7_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[30]) /* 0x40010F80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT8_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[31]) /* 0x40010FC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT9_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[32]) /* 0x40011000 */ +#define PERI_MS_PPU_FX_IPC_STRUCT10_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[33]) /* 0x40011040 */ +#define PERI_MS_PPU_FX_IPC_STRUCT11_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[34]) /* 0x40011080 */ +#define PERI_MS_PPU_FX_IPC_STRUCT12_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[35]) /* 0x400110C0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT13_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[36]) /* 0x40011100 */ +#define PERI_MS_PPU_FX_IPC_STRUCT14_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[37]) /* 0x40011140 */ +#define PERI_MS_PPU_FX_IPC_STRUCT15_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[38]) /* 0x40011180 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT0_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[39]) /* 0x400111C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT1_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[40]) /* 0x40011200 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT2_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[41]) /* 0x40011240 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT3_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[42]) /* 0x40011280 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT4_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[43]) /* 0x400112C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT5_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[44]) /* 0x40011300 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT6_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[45]) /* 0x40011340 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT7_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[46]) /* 0x40011380 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT8_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[47]) /* 0x400113C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT9_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[48]) /* 0x40011400 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT10_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[49]) /* 0x40011440 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT11_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[50]) /* 0x40011480 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT12_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[51]) /* 0x400114C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT13_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[52]) /* 0x40011500 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT14_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[53]) /* 0x40011540 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT15_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[54]) /* 0x40011580 */ +#define PERI_MS_PPU_FX_PROT_SMPU_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[55]) /* 0x400115C0 */ +#define PERI_MS_PPU_FX_PROT_MPU0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[56]) /* 0x40011600 */ +#define PERI_MS_PPU_FX_PROT_MPU5_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[57]) /* 0x40011640 */ +#define PERI_MS_PPU_FX_PROT_MPU14_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[58]) /* 0x40011680 */ +#define PERI_MS_PPU_FX_PROT_MPU15_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[59]) /* 0x400116C0 */ +#define PERI_MS_PPU_FX_FLASHC_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[60]) /* 0x40011700 */ +#define PERI_MS_PPU_FX_FLASHC_CMD ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[61]) /* 0x40011740 */ +#define PERI_MS_PPU_FX_FLASHC_DFT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[62]) /* 0x40011780 */ +#define PERI_MS_PPU_FX_FLASHC_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[63]) /* 0x400117C0 */ +#define PERI_MS_PPU_FX_FLASHC_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[64]) /* 0x40011800 */ +#define PERI_MS_PPU_FX_FLASHC_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[65]) /* 0x40011840 */ +#define PERI_MS_PPU_FX_FLASHC_DW0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[66]) /* 0x40011880 */ +#define PERI_MS_PPU_FX_FLASHC_DW1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[67]) /* 0x400118C0 */ +#define PERI_MS_PPU_FX_FLASHC_DMAC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[68]) /* 0x40011900 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[69]) /* 0x40011940 */ +#define PERI_MS_PPU_FX_FLASHC_FM ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[70]) /* 0x40011980 */ +#define PERI_MS_PPU_FX_SRSS_MAIN1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[71]) /* 0x400119C0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[72]) /* 0x40011A00 */ +#define PERI_MS_PPU_FX_WDT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[73]) /* 0x40011A40 */ +#define PERI_MS_PPU_FX_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[74]) /* 0x40011A80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[75]) /* 0x40011AC0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[76]) /* 0x40011B00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[77]) /* 0x40011B40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[78]) /* 0x40011B80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[79]) /* 0x40011BC0 */ +#define PERI_MS_PPU_FX_BACKUP_BACKUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[80]) /* 0x40011C00 */ +#define PERI_MS_PPU_FX_DW0_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[81]) /* 0x40011C40 */ +#define PERI_MS_PPU_FX_DW1_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[82]) /* 0x40011C80 */ +#define PERI_MS_PPU_FX_DW0_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[83]) /* 0x40011CC0 */ +#define PERI_MS_PPU_FX_DW1_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[84]) /* 0x40011D00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[85]) /* 0x40011D40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[86]) /* 0x40011D80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[87]) /* 0x40011DC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[88]) /* 0x40011E00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[89]) /* 0x40011E40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[90]) /* 0x40011E80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[91]) /* 0x40011EC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[92]) /* 0x40011F00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[93]) /* 0x40011F40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[94]) /* 0x40011F80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[95]) /* 0x40011FC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[96]) /* 0x40012000 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[97]) /* 0x40012040 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[98]) /* 0x40012080 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[99]) /* 0x400120C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[100]) /* 0x40012100 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[101]) /* 0x40012140 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[102]) /* 0x40012180 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[103]) /* 0x400121C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[104]) /* 0x40012200 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[105]) /* 0x40012240 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[106]) /* 0x40012280 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[107]) /* 0x400122C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[108]) /* 0x40012300 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[109]) /* 0x40012340 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[110]) /* 0x40012380 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[111]) /* 0x400123C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[112]) /* 0x40012400 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[113]) /* 0x40012440 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[114]) /* 0x40012480 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[115]) /* 0x400124C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[116]) /* 0x40012500 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[117]) /* 0x40012540 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[118]) /* 0x40012580 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[119]) /* 0x400125C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[120]) /* 0x40012600 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[121]) /* 0x40012640 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[122]) /* 0x40012680 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[123]) /* 0x400126C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[124]) /* 0x40012700 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[125]) /* 0x40012740 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[126]) /* 0x40012780 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[127]) /* 0x400127C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[128]) /* 0x40012800 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[129]) /* 0x40012840 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[130]) /* 0x40012880 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[131]) /* 0x400128C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[132]) /* 0x40012900 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[133]) /* 0x40012940 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[134]) /* 0x40012980 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[135]) /* 0x400129C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[136]) /* 0x40012A00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[137]) /* 0x40012A40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[138]) /* 0x40012A80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[139]) /* 0x40012AC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[140]) /* 0x40012B00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[141]) /* 0x40012B40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[142]) /* 0x40012B80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT29_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[143]) /* 0x40012BC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT30_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[144]) /* 0x40012C00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT31_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[145]) /* 0x40012C40 */ +#define PERI_MS_PPU_FX_DMAC_TOP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[146]) /* 0x40012C80 */ +#define PERI_MS_PPU_FX_DMAC_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[147]) /* 0x40012CC0 */ +#define PERI_MS_PPU_FX_DMAC_CH1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[148]) /* 0x40012D00 */ +#define PERI_MS_PPU_FX_EFUSE_CTL ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[149]) /* 0x40012D40 */ +#define PERI_MS_PPU_FX_EFUSE_DATA ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[150]) /* 0x40012D80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[151]) /* 0x40012DC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[152]) /* 0x40012E00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[153]) /* 0x40012E40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[154]) /* 0x40012E80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[155]) /* 0x40012EC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[156]) /* 0x40012F00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[157]) /* 0x40012F40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[158]) /* 0x40012F80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[159]) /* 0x40012FC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[160]) /* 0x40013000 */ +#define PERI_MS_PPU_FX_HSIOM_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[161]) /* 0x40013040 */ +#define PERI_MS_PPU_FX_HSIOM_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[162]) /* 0x40013080 */ +#define PERI_MS_PPU_FX_HSIOM_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[163]) /* 0x400130C0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[164]) /* 0x40013100 */ +#define PERI_MS_PPU_FX_HSIOM_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[165]) /* 0x40013140 */ +#define PERI_MS_PPU_FX_HSIOM_AMUX ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[166]) /* 0x40013180 */ +#define PERI_MS_PPU_FX_HSIOM_MON ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[167]) /* 0x400131C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[168]) /* 0x40013200 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[169]) /* 0x40013240 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[170]) /* 0x40013280 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[171]) /* 0x400132C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[172]) /* 0x40013300 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[173]) /* 0x40013340 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[174]) /* 0x40013380 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[175]) /* 0x400133C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[176]) /* 0x40013400 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[177]) /* 0x40013440 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[178]) /* 0x40013480 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[179]) /* 0x400134C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[180]) /* 0x40013500 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[181]) /* 0x40013540 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[182]) /* 0x40013580 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[183]) /* 0x400135C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[184]) /* 0x40013600 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[185]) /* 0x40013640 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[186]) /* 0x40013680 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[187]) /* 0x400136C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[188]) /* 0x40013700 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[189]) /* 0x40013740 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[190]) /* 0x40013780 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[191]) /* 0x400137C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[192]) /* 0x40013800 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[193]) /* 0x40013840 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[194]) /* 0x40013880 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[195]) /* 0x400138C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[196]) /* 0x40013900 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[197]) /* 0x40013940 */ +#define PERI_MS_PPU_FX_GPIO_GPIO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[198]) /* 0x40013980 */ +#define PERI_MS_PPU_FX_GPIO_TEST ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[199]) /* 0x400139C0 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[200]) /* 0x40013A00 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[201]) /* 0x40013A40 */ +#define PERI_MS_PPU_FX_LPCOMP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[202]) /* 0x40013A80 */ +#define PERI_MS_PPU_FX_CSD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[203]) /* 0x40013AC0 */ +#define PERI_MS_PPU_FX_TCPWM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[204]) /* 0x40013B00 */ +#define PERI_MS_PPU_FX_TCPWM1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[205]) /* 0x40013B40 */ +#define PERI_MS_PPU_FX_LCD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[206]) /* 0x40013B80 */ +#define PERI_MS_PPU_FX_USBFS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[207]) /* 0x40013BC0 */ +#define PERI_MS_PPU_FX_SMIF0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[208]) /* 0x40013C00 */ +#define PERI_MS_PPU_FX_SDHC0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[209]) /* 0x40013C40 */ +#define PERI_MS_PPU_FX_CANFD0_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[210]) /* 0x40013C80 */ +#define PERI_MS_PPU_FX_CANFD0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[211]) /* 0x40013CC0 */ +#define PERI_MS_PPU_FX_CANFD0_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[212]) /* 0x40013D00 */ +#define PERI_MS_PPU_FX_SCB0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[213]) /* 0x40013D40 */ +#define PERI_MS_PPU_FX_SCB1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[214]) /* 0x40013D80 */ +#define PERI_MS_PPU_FX_SCB2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[215]) /* 0x40013DC0 */ +#define PERI_MS_PPU_FX_SCB3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[216]) /* 0x40013E00 */ +#define PERI_MS_PPU_FX_SCB4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[217]) /* 0x40013E40 */ +#define PERI_MS_PPU_FX_SCB5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[218]) /* 0x40013E80 */ +#define PERI_MS_PPU_FX_SCB6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[219]) /* 0x40013EC0 */ + +/******************************************************************************* +* CPUSS +*******************************************************************************/ + +#define CPUSS_BASE 0x40200000UL +#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40200000 */ + +/******************************************************************************* +* FAULT +*******************************************************************************/ + +#define FAULT_BASE 0x40210000UL +#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40210000 */ +#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40210000 */ +#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40210100 */ + +/******************************************************************************* +* IPC +*******************************************************************************/ + +#define IPC_BASE 0x40220000UL +#define IPC ((IPC_Type*) IPC_BASE) /* 0x40220000 */ +#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40220000 */ +#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40220020 */ +#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40220040 */ +#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40220060 */ +#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40220080 */ +#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402200A0 */ +#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402200C0 */ +#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402200E0 */ +#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40220100 */ +#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40220120 */ +#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40220140 */ +#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40220160 */ +#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40220180 */ +#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402201A0 */ +#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402201C0 */ +#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402201E0 */ +#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40221000 */ +#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40221020 */ +#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40221040 */ +#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40221060 */ +#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40221080 */ +#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402210A0 */ +#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402210C0 */ +#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402210E0 */ +#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40221100 */ +#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40221120 */ +#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40221140 */ +#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40221160 */ +#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40221180 */ +#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402211A0 */ +#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402211C0 */ +#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402211E0 */ + +/******************************************************************************* +* PROT +*******************************************************************************/ + +#define PROT_BASE 0x40230000UL +#define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ +#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ +#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ +#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402320C0 */ +#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40232100 */ +#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40232140 */ +#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40232180 */ +#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402321C0 */ +#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40232200 */ +#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40232240 */ +#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40232280 */ +#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402322C0 */ +#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40232300 */ +#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ +#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ +#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ +#define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ +#define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ +#define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ +#define PROT_MPU5_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[3]) /* 0x40235660 */ +#define PROT_MPU5_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[4]) /* 0x40235680 */ +#define PROT_MPU5_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[5]) /* 0x402356A0 */ +#define PROT_MPU5_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[6]) /* 0x402356C0 */ +#define PROT_MPU5_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[7]) /* 0x402356E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ + +/******************************************************************************* +* FLASHC +*******************************************************************************/ + +#define FLASHC_BASE 0x40240000UL +#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40240000 */ +#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4024F000 */ + +/******************************************************************************* +* SRSS +*******************************************************************************/ + +#define SRSS_BASE 0x40260000UL +#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ +#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */ +#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */ + +/******************************************************************************* +* BACKUP +*******************************************************************************/ + +#define BACKUP_BASE 0x40270000UL +#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ + +/******************************************************************************* +* DW +*******************************************************************************/ + +#define DW0_BASE 0x40280000UL +#define DW1_BASE 0x40290000UL +#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ +#define DW1 ((DW_Type*) DW1_BASE) /* 0x40290000 */ +#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40288000 */ +#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40288040 */ +#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40288080 */ +#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x402880C0 */ +#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40288100 */ +#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x40288140 */ +#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x40288180 */ +#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402881C0 */ +#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40288200 */ +#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40288240 */ +#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40288280 */ +#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x402882C0 */ +#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40288300 */ +#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x40288340 */ +#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x40288380 */ +#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402883C0 */ +#define DW0_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[16]) /* 0x40288400 */ +#define DW0_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[17]) /* 0x40288440 */ +#define DW0_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[18]) /* 0x40288480 */ +#define DW0_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[19]) /* 0x402884C0 */ +#define DW0_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[20]) /* 0x40288500 */ +#define DW0_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[21]) /* 0x40288540 */ +#define DW0_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[22]) /* 0x40288580 */ +#define DW0_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[23]) /* 0x402885C0 */ +#define DW0_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[24]) /* 0x40288600 */ +#define DW0_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[25]) /* 0x40288640 */ +#define DW0_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[26]) /* 0x40288680 */ +#define DW0_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[27]) /* 0x402886C0 */ +#define DW0_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[28]) /* 0x40288700 */ +#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40298000 */ +#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40298040 */ +#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40298080 */ +#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x402980C0 */ +#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40298100 */ +#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x40298140 */ +#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x40298180 */ +#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402981C0 */ +#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40298200 */ +#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40298240 */ +#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40298280 */ +#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x402982C0 */ +#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40298300 */ +#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x40298340 */ +#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x40298380 */ +#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402983C0 */ +#define DW1_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[16]) /* 0x40298400 */ +#define DW1_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[17]) /* 0x40298440 */ +#define DW1_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[18]) /* 0x40298480 */ +#define DW1_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[19]) /* 0x402984C0 */ +#define DW1_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[20]) /* 0x40298500 */ +#define DW1_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[21]) /* 0x40298540 */ +#define DW1_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[22]) /* 0x40298580 */ +#define DW1_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[23]) /* 0x402985C0 */ +#define DW1_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[24]) /* 0x40298600 */ +#define DW1_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[25]) /* 0x40298640 */ +#define DW1_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[26]) /* 0x40298680 */ +#define DW1_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[27]) /* 0x402986C0 */ +#define DW1_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[28]) /* 0x40298700 */ +#define DW1_CH_STRUCT29 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[29]) /* 0x40298740 */ +#define DW1_CH_STRUCT30 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[30]) /* 0x40298780 */ +#define DW1_CH_STRUCT31 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[31]) /* 0x402987C0 */ + +/******************************************************************************* +* DMAC +*******************************************************************************/ + +#define DMAC_BASE 0x402A0000UL +#define DMAC ((DMAC_Type*) DMAC_BASE) /* 0x402A0000 */ +#define DMAC_CH0 ((DMAC_CH_Type*) &DMAC->CH[0]) /* 0x402A1000 */ +#define DMAC_CH1 ((DMAC_CH_Type*) &DMAC->CH[1]) /* 0x402A1100 */ + +/******************************************************************************* +* EFUSE +*******************************************************************************/ + +#define EFUSE_BASE 0x402C0000UL +#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ + +/******************************************************************************* +* HSIOM +*******************************************************************************/ + +#define HSIOM_BASE 0x40300000UL +#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40300000 */ +#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40300000 */ +#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40300010 */ +#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40300020 */ +#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40300030 */ +#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40300040 */ +#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40300050 */ +#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40300060 */ +#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40300070 */ +#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40300080 */ +#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40300090 */ +#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403000A0 */ +#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403000B0 */ +#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403000C0 */ +#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403000D0 */ +#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403000E0 */ + +/******************************************************************************* +* GPIO +*******************************************************************************/ + +#define GPIO_BASE 0x40310000UL +#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40310000 */ +#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40310000 */ +#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40310080 */ +#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40310100 */ +#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40310180 */ +#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40310200 */ +#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40310280 */ +#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40310300 */ +#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40310380 */ +#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40310400 */ +#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40310480 */ +#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40310500 */ +#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40310580 */ +#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40310600 */ +#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40310680 */ +#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40310700 */ + +/******************************************************************************* +* SMARTIO +*******************************************************************************/ + +#define SMARTIO_BASE 0x40320000UL +#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40320000 */ +#define SMARTIO_PRT8 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[8]) /* 0x40320800 */ +#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40320900 */ + +/******************************************************************************* +* LPCOMP +*******************************************************************************/ + +#define LPCOMP_BASE 0x40350000UL +#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */ + +/******************************************************************************* +* CSD +*******************************************************************************/ + +#define CSD0_BASE 0x40360000UL +#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */ + +/******************************************************************************* +* TCPWM +*******************************************************************************/ + +#define TCPWM0_BASE 0x40380000UL +#define TCPWM1_BASE 0x40390000UL +#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM1 ((TCPWM_Type*) TCPWM1_BASE) /* 0x40390000 */ +#define TCPWM0_CNT0 ((TCPWM_CNT_Type*) &TCPWM0->CNT[0]) /* 0x40380100 */ +#define TCPWM0_CNT1 ((TCPWM_CNT_Type*) &TCPWM0->CNT[1]) /* 0x40380140 */ +#define TCPWM0_CNT2 ((TCPWM_CNT_Type*) &TCPWM0->CNT[2]) /* 0x40380180 */ +#define TCPWM0_CNT3 ((TCPWM_CNT_Type*) &TCPWM0->CNT[3]) /* 0x403801C0 */ +#define TCPWM1_CNT0 ((TCPWM_CNT_Type*) &TCPWM1->CNT[0]) /* 0x40390100 */ +#define TCPWM1_CNT1 ((TCPWM_CNT_Type*) &TCPWM1->CNT[1]) /* 0x40390140 */ +#define TCPWM1_CNT2 ((TCPWM_CNT_Type*) &TCPWM1->CNT[2]) /* 0x40390180 */ +#define TCPWM1_CNT3 ((TCPWM_CNT_Type*) &TCPWM1->CNT[3]) /* 0x403901C0 */ +#define TCPWM1_CNT4 ((TCPWM_CNT_Type*) &TCPWM1->CNT[4]) /* 0x40390200 */ +#define TCPWM1_CNT5 ((TCPWM_CNT_Type*) &TCPWM1->CNT[5]) /* 0x40390240 */ +#define TCPWM1_CNT6 ((TCPWM_CNT_Type*) &TCPWM1->CNT[6]) /* 0x40390280 */ +#define TCPWM1_CNT7 ((TCPWM_CNT_Type*) &TCPWM1->CNT[7]) /* 0x403902C0 */ + +/******************************************************************************* +* LCD +*******************************************************************************/ + +#define LCD0_BASE 0x403B0000UL +#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ + +/******************************************************************************* +* USBFS +*******************************************************************************/ + +#define USBFS0_BASE 0x403F0000UL +#define USBFS0 ((USBFS_Type*) USBFS0_BASE) /* 0x403F0000 */ +#define USBFS0_USBDEV ((USBFS_USBDEV_Type*) &USBFS0->USBDEV) /* 0x403F0000 */ +#define USBFS0_USBLPM ((USBFS_USBLPM_Type*) &USBFS0->USBLPM) /* 0x403F2000 */ +#define USBFS0_USBHOST ((USBFS_USBHOST_Type*) &USBFS0->USBHOST) /* 0x403F4000 */ + +/******************************************************************************* +* SMIF +*******************************************************************************/ + +#define SMIF0_BASE 0x40420000UL +#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ +#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ +#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ +#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ + +/******************************************************************************* +* SDHC +*******************************************************************************/ + +#define SDHC0_BASE 0x40460000UL +#define SDHC0 ((SDHC_Type*) SDHC0_BASE) /* 0x40460000 */ +#define SDHC0_WRAP ((SDHC_WRAP_Type*) &SDHC0->WRAP) /* 0x40460000 */ +#define SDHC0_CORE ((SDHC_CORE_Type*) &SDHC0->CORE) /* 0x40461000 */ + +/******************************************************************************* +* CANFD +*******************************************************************************/ + +#define CANFD0_BASE 0x40520000UL +#define CANFD0 ((CANFD_Type*) CANFD0_BASE) /* 0x40520000 */ +#define CANFD0_CH0 ((CANFD_CH_Type*) &CANFD0->CH[0]) /* 0x40520000 */ +#define CANFD0_CH0_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[0].M_TTCAN) /* 0x40520000 */ + +/******************************************************************************* +* SCB +*******************************************************************************/ + +#define SCB0_BASE 0x40600000UL +#define SCB1_BASE 0x40610000UL +#define SCB2_BASE 0x40620000UL +#define SCB3_BASE 0x40630000UL +#define SCB4_BASE 0x40640000UL +#define SCB5_BASE 0x40650000UL +#define SCB6_BASE 0x40660000UL +#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40600000 */ +#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40610000 */ +#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40620000 */ +#define SCB3 ((CySCB_Type*) SCB3_BASE) /* 0x40630000 */ +#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40640000 */ +#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40650000 */ +#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40660000 */ + +/******************************************************************************* +* SAR +*******************************************************************************/ + +#define SAR_BASE 0x409D0000UL +#define SAR ((SAR_Type*) SAR_BASE) /* 0x409D0000 */ + +/******************************************************************************* +* PASS +*******************************************************************************/ + +#define PASS_BASE 0x409F0000UL +#define PASS ((PASS_Type*) PASS_BASE) /* 0x409F0000 */ +#define PASS_AREF ((PASS_AREF_Type*) &PASS->AREF) /* 0x409F0E00 */ + +/** \} CY8C6145AZI-S3F02 */ + +#endif /* _CY8C6145AZI_S3F02_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6145azi_s3f12.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6145azi_s3f12.h new file mode 100644 index 0000000000..91a95c3b1d --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6145azi_s3f12.h @@ -0,0 +1,983 @@ +/***************************************************************************//** +* \file cy8c6145azi_s3f12.h +* +* \brief +* CY8C6145AZI-S3F12 device header +* +* \note +* Generator version: 1.6.0.225 +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CY8C6145AZI_S3F12_H_ +#define _CY8C6145AZI_S3F12_H_ + +/** +* \addtogroup group_device CY8C6145AZI-S3F12 +* \{ +*/ + +/** +* \addtogroup Configuration_of_CMSIS +* \{ +*/ + +/******************************************************************************* +* Interrupt Number Definition +*******************************************************************************/ + +typedef enum { + /* ARM Cortex-M4 Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C6145AZI-S3F12 Peripheral Interrupt Numbers */ + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_6_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #6 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + canfd_0_interrupt0_IRQn = 168, /*!< 168 [Active] Can #0, Consolidated interrupt #0 */ + canfd_0_interrupts0_0_IRQn = 169, /*!< 169 [Active] CAN #0, Interrupt #0, Channel #0 */ + canfd_0_interrupts1_0_IRQn = 170, /*!< 170 [Active] CAN #0, Interrupt #1, Channel #0 */ + cpuss_interrupts_dw1_29_IRQn = 171, /*!< 171 [Active] CPUSS DataWire #1, Channel #29 */ + cpuss_interrupts_dw1_30_IRQn = 172, /*!< 172 [Active] CPUSS DataWire #1, Channel #30 */ + cpuss_interrupts_dw1_31_IRQn = 173, /*!< 173 [Active] CPUSS DataWire #1, Channel #31 */ + unconnected_IRQn = 240 /*!< 240 Unconnected */ +} IRQn_Type; + + +/******************************************************************************* +* Processor and Core Peripheral Section +*******************************************************************************/ + +/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __CM0P_PRESENT 0 /*!< CM0P present or not */ +#define __DTCM_PRESENT 0 /*!< DTCM present or not */ +#define __ICACHE_PRESENT 0 /*!< ICACHE present or not */ +#define __DCACHE_PRESENT 0 /*!< DCACHE present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + + +/* Memory Blocks */ +#define CY_ROM_BASE 0x00000000UL +#define CY_ROM_SIZE 0x00010000UL +#define CY_SRAM_BASE 0x08000000UL +#define CY_SRAM_SIZE 0x00040000UL +#define CY_FLASH_BASE 0x10000000UL +#define CY_FLASH_SIZE 0x00080000UL +#define CY_EM_EEPROM_BASE 0x14000000UL +#define CY_EM_EEPROM_SIZE 0x00008000UL +#define CY_SFLASH_BASE 0x16000000UL +#define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL +#define CY_EFUSE_BASE 0x402C0800UL +#define CY_EFUSE_SIZE 0x00000200UL +#define CY_CAN0MRAM_BASE 0x40530000UL +#define CY_CAN0MRAM_SIZE 0x00010000UL + +#include "system_psoc6.h" /*!< PSoC 6 System */ + +/* IP List */ +#define CY_IP_MXTTCANFD 1u +#define CY_IP_MXTTCANFD_INSTANCES 1u +#define CY_IP_MXTTCANFD_VERSION 1u +#define CY_IP_M4CPUSS 1u +#define CY_IP_M4CPUSS_INSTANCES 1u +#define CY_IP_M4CPUSS_VERSION 2u +#define CY_IP_M4CPUSS_DMAC 1u +#define CY_IP_M4CPUSS_DMAC_INSTANCES 1u +#define CY_IP_M4CPUSS_DMAC_VERSION 2u +#define CY_IP_M4CPUSS_DMA 1u +#define CY_IP_M4CPUSS_DMA_INSTANCES 2u +#define CY_IP_M4CPUSS_DMA_VERSION 2u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 2u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u +#define CY_IP_MXS40PASS 1u +#define CY_IP_MXS40PASS_INSTANCES 1u +#define CY_IP_MXS40PASS_VERSION 1u +#define CY_IP_MXS40PASS_SAR 1u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u +#define CY_IP_MXS40PASS_SAR_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 7u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 1u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u + +#include "psoc6_03_config.h" +#include "gpio_psoc6_03_100_tqfp.h" + +#define CY_DEVICE_PSOC6A512K +#define CY_SILICON_ID 0xE7171105UL +#define CY_HF_CLK_MAX_FREQ 150000000UL + +#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL + +/******************************************************************************* +* SFLASH +*******************************************************************************/ + +#define SFLASH_BASE 0x16000000UL +#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */ + +/******************************************************************************* +* PERI +*******************************************************************************/ + +#define PERI_BASE 0x40000000UL +#define PERI ((PERI_Type*) PERI_BASE) /* 0x40000000 */ +#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40004000 */ +#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40004020 */ +#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40004040 */ +#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x40004060 */ +#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40004080 */ +#define PERI_GR5 ((PERI_GR_Type*) &PERI->GR[5]) /* 0x400040A0 */ +#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x400040C0 */ +#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40004120 */ +#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40008000 */ +#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40008400 */ +#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40008800 */ +#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40008C00 */ +#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40009000 */ +#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40009400 */ +#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40009800 */ +#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40009C00 */ +#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ +#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ +#define PERI_TR_GR10 ((PERI_TR_GR_Type*) &PERI->TR_GR[10]) /* 0x4000A800 */ +#define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ +#define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ +#define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ +#define PERI_TR_1TO1_GR3 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[3]) /* 0x4000CC00 */ +#define PERI_TR_1TO1_GR4 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[4]) /* 0x4000D000 */ +#define PERI_TR_1TO1_GR5 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[5]) /* 0x4000D400 */ +#define PERI_TR_1TO1_GR6 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[6]) /* 0x4000D800 */ +#define PERI_TR_1TO1_GR7 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[7]) /* 0x4000DC00 */ + +/******************************************************************************* +* PERI_MS +*******************************************************************************/ + +#define PERI_MS_BASE 0x40010000UL +#define PERI_MS ((PERI_MS_Type*) PERI_MS_BASE) /* 0x40010000 */ +#define PERI_MS_PPU_PR0 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[0]) /* 0x40010000 */ +#define PERI_MS_PPU_PR1 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[1]) /* 0x40010040 */ +#define PERI_MS_PPU_PR2 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[2]) /* 0x40010080 */ +#define PERI_MS_PPU_PR3 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[3]) /* 0x400100C0 */ +#define PERI_MS_PPU_PR4 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[4]) /* 0x40010100 */ +#define PERI_MS_PPU_PR5 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[5]) /* 0x40010140 */ +#define PERI_MS_PPU_PR6 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[6]) /* 0x40010180 */ +#define PERI_MS_PPU_PR7 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[7]) /* 0x400101C0 */ +#define PERI_MS_PPU_FX_PERI_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[0]) /* 0x40010800 */ +#define PERI_MS_PPU_FX_PERI_GR0_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[1]) /* 0x40010840 */ +#define PERI_MS_PPU_FX_PERI_GR1_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[2]) /* 0x40010880 */ +#define PERI_MS_PPU_FX_PERI_GR2_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[3]) /* 0x400108C0 */ +#define PERI_MS_PPU_FX_PERI_GR3_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[4]) /* 0x40010900 */ +#define PERI_MS_PPU_FX_PERI_GR4_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[5]) /* 0x40010940 */ +#define PERI_MS_PPU_FX_PERI_GR5_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[6]) /* 0x40010980 */ +#define PERI_MS_PPU_FX_PERI_GR6_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[7]) /* 0x400109C0 */ +#define PERI_MS_PPU_FX_PERI_GR9_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[8]) /* 0x40010A00 */ +#define PERI_MS_PPU_FX_PERI_TR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[9]) /* 0x40010A40 */ +#define PERI_MS_PPU_FX_CRYPTO_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[10]) /* 0x40010A80 */ +#define PERI_MS_PPU_FX_CRYPTO_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[11]) /* 0x40010AC0 */ +#define PERI_MS_PPU_FX_CRYPTO_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[12]) /* 0x40010B00 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[13]) /* 0x40010B40 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[14]) /* 0x40010B80 */ +#define PERI_MS_PPU_FX_CRYPTO_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[15]) /* 0x40010BC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[16]) /* 0x40010C00 */ +#define PERI_MS_PPU_FX_CPUSS_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[17]) /* 0x40010C40 */ +#define PERI_MS_PPU_FX_CPUSS_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[18]) /* 0x40010C80 */ +#define PERI_MS_PPU_FX_CPUSS_CM0_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[19]) /* 0x40010CC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[20]) /* 0x40010D00 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[21]) /* 0x40010D40 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT1_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[22]) /* 0x40010D80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT0_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[23]) /* 0x40010DC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT1_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[24]) /* 0x40010E00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT2_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[25]) /* 0x40010E40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT3_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[26]) /* 0x40010E80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT4_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[27]) /* 0x40010EC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT5_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[28]) /* 0x40010F00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT6_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[29]) /* 0x40010F40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT7_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[30]) /* 0x40010F80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT8_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[31]) /* 0x40010FC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT9_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[32]) /* 0x40011000 */ +#define PERI_MS_PPU_FX_IPC_STRUCT10_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[33]) /* 0x40011040 */ +#define PERI_MS_PPU_FX_IPC_STRUCT11_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[34]) /* 0x40011080 */ +#define PERI_MS_PPU_FX_IPC_STRUCT12_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[35]) /* 0x400110C0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT13_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[36]) /* 0x40011100 */ +#define PERI_MS_PPU_FX_IPC_STRUCT14_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[37]) /* 0x40011140 */ +#define PERI_MS_PPU_FX_IPC_STRUCT15_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[38]) /* 0x40011180 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT0_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[39]) /* 0x400111C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT1_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[40]) /* 0x40011200 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT2_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[41]) /* 0x40011240 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT3_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[42]) /* 0x40011280 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT4_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[43]) /* 0x400112C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT5_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[44]) /* 0x40011300 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT6_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[45]) /* 0x40011340 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT7_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[46]) /* 0x40011380 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT8_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[47]) /* 0x400113C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT9_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[48]) /* 0x40011400 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT10_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[49]) /* 0x40011440 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT11_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[50]) /* 0x40011480 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT12_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[51]) /* 0x400114C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT13_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[52]) /* 0x40011500 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT14_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[53]) /* 0x40011540 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT15_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[54]) /* 0x40011580 */ +#define PERI_MS_PPU_FX_PROT_SMPU_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[55]) /* 0x400115C0 */ +#define PERI_MS_PPU_FX_PROT_MPU0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[56]) /* 0x40011600 */ +#define PERI_MS_PPU_FX_PROT_MPU5_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[57]) /* 0x40011640 */ +#define PERI_MS_PPU_FX_PROT_MPU14_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[58]) /* 0x40011680 */ +#define PERI_MS_PPU_FX_PROT_MPU15_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[59]) /* 0x400116C0 */ +#define PERI_MS_PPU_FX_FLASHC_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[60]) /* 0x40011700 */ +#define PERI_MS_PPU_FX_FLASHC_CMD ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[61]) /* 0x40011740 */ +#define PERI_MS_PPU_FX_FLASHC_DFT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[62]) /* 0x40011780 */ +#define PERI_MS_PPU_FX_FLASHC_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[63]) /* 0x400117C0 */ +#define PERI_MS_PPU_FX_FLASHC_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[64]) /* 0x40011800 */ +#define PERI_MS_PPU_FX_FLASHC_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[65]) /* 0x40011840 */ +#define PERI_MS_PPU_FX_FLASHC_DW0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[66]) /* 0x40011880 */ +#define PERI_MS_PPU_FX_FLASHC_DW1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[67]) /* 0x400118C0 */ +#define PERI_MS_PPU_FX_FLASHC_DMAC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[68]) /* 0x40011900 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[69]) /* 0x40011940 */ +#define PERI_MS_PPU_FX_FLASHC_FM ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[70]) /* 0x40011980 */ +#define PERI_MS_PPU_FX_SRSS_MAIN1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[71]) /* 0x400119C0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[72]) /* 0x40011A00 */ +#define PERI_MS_PPU_FX_WDT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[73]) /* 0x40011A40 */ +#define PERI_MS_PPU_FX_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[74]) /* 0x40011A80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[75]) /* 0x40011AC0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[76]) /* 0x40011B00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[77]) /* 0x40011B40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[78]) /* 0x40011B80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[79]) /* 0x40011BC0 */ +#define PERI_MS_PPU_FX_BACKUP_BACKUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[80]) /* 0x40011C00 */ +#define PERI_MS_PPU_FX_DW0_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[81]) /* 0x40011C40 */ +#define PERI_MS_PPU_FX_DW1_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[82]) /* 0x40011C80 */ +#define PERI_MS_PPU_FX_DW0_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[83]) /* 0x40011CC0 */ +#define PERI_MS_PPU_FX_DW1_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[84]) /* 0x40011D00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[85]) /* 0x40011D40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[86]) /* 0x40011D80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[87]) /* 0x40011DC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[88]) /* 0x40011E00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[89]) /* 0x40011E40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[90]) /* 0x40011E80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[91]) /* 0x40011EC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[92]) /* 0x40011F00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[93]) /* 0x40011F40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[94]) /* 0x40011F80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[95]) /* 0x40011FC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[96]) /* 0x40012000 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[97]) /* 0x40012040 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[98]) /* 0x40012080 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[99]) /* 0x400120C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[100]) /* 0x40012100 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[101]) /* 0x40012140 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[102]) /* 0x40012180 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[103]) /* 0x400121C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[104]) /* 0x40012200 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[105]) /* 0x40012240 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[106]) /* 0x40012280 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[107]) /* 0x400122C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[108]) /* 0x40012300 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[109]) /* 0x40012340 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[110]) /* 0x40012380 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[111]) /* 0x400123C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[112]) /* 0x40012400 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[113]) /* 0x40012440 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[114]) /* 0x40012480 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[115]) /* 0x400124C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[116]) /* 0x40012500 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[117]) /* 0x40012540 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[118]) /* 0x40012580 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[119]) /* 0x400125C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[120]) /* 0x40012600 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[121]) /* 0x40012640 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[122]) /* 0x40012680 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[123]) /* 0x400126C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[124]) /* 0x40012700 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[125]) /* 0x40012740 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[126]) /* 0x40012780 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[127]) /* 0x400127C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[128]) /* 0x40012800 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[129]) /* 0x40012840 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[130]) /* 0x40012880 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[131]) /* 0x400128C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[132]) /* 0x40012900 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[133]) /* 0x40012940 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[134]) /* 0x40012980 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[135]) /* 0x400129C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[136]) /* 0x40012A00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[137]) /* 0x40012A40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[138]) /* 0x40012A80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[139]) /* 0x40012AC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[140]) /* 0x40012B00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[141]) /* 0x40012B40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[142]) /* 0x40012B80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT29_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[143]) /* 0x40012BC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT30_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[144]) /* 0x40012C00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT31_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[145]) /* 0x40012C40 */ +#define PERI_MS_PPU_FX_DMAC_TOP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[146]) /* 0x40012C80 */ +#define PERI_MS_PPU_FX_DMAC_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[147]) /* 0x40012CC0 */ +#define PERI_MS_PPU_FX_DMAC_CH1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[148]) /* 0x40012D00 */ +#define PERI_MS_PPU_FX_EFUSE_CTL ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[149]) /* 0x40012D40 */ +#define PERI_MS_PPU_FX_EFUSE_DATA ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[150]) /* 0x40012D80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[151]) /* 0x40012DC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[152]) /* 0x40012E00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[153]) /* 0x40012E40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[154]) /* 0x40012E80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[155]) /* 0x40012EC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[156]) /* 0x40012F00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[157]) /* 0x40012F40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[158]) /* 0x40012F80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[159]) /* 0x40012FC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[160]) /* 0x40013000 */ +#define PERI_MS_PPU_FX_HSIOM_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[161]) /* 0x40013040 */ +#define PERI_MS_PPU_FX_HSIOM_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[162]) /* 0x40013080 */ +#define PERI_MS_PPU_FX_HSIOM_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[163]) /* 0x400130C0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[164]) /* 0x40013100 */ +#define PERI_MS_PPU_FX_HSIOM_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[165]) /* 0x40013140 */ +#define PERI_MS_PPU_FX_HSIOM_AMUX ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[166]) /* 0x40013180 */ +#define PERI_MS_PPU_FX_HSIOM_MON ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[167]) /* 0x400131C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[168]) /* 0x40013200 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[169]) /* 0x40013240 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[170]) /* 0x40013280 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[171]) /* 0x400132C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[172]) /* 0x40013300 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[173]) /* 0x40013340 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[174]) /* 0x40013380 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[175]) /* 0x400133C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[176]) /* 0x40013400 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[177]) /* 0x40013440 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[178]) /* 0x40013480 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[179]) /* 0x400134C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[180]) /* 0x40013500 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[181]) /* 0x40013540 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[182]) /* 0x40013580 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[183]) /* 0x400135C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[184]) /* 0x40013600 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[185]) /* 0x40013640 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[186]) /* 0x40013680 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[187]) /* 0x400136C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[188]) /* 0x40013700 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[189]) /* 0x40013740 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[190]) /* 0x40013780 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[191]) /* 0x400137C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[192]) /* 0x40013800 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[193]) /* 0x40013840 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[194]) /* 0x40013880 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[195]) /* 0x400138C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[196]) /* 0x40013900 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[197]) /* 0x40013940 */ +#define PERI_MS_PPU_FX_GPIO_GPIO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[198]) /* 0x40013980 */ +#define PERI_MS_PPU_FX_GPIO_TEST ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[199]) /* 0x400139C0 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[200]) /* 0x40013A00 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[201]) /* 0x40013A40 */ +#define PERI_MS_PPU_FX_LPCOMP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[202]) /* 0x40013A80 */ +#define PERI_MS_PPU_FX_CSD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[203]) /* 0x40013AC0 */ +#define PERI_MS_PPU_FX_TCPWM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[204]) /* 0x40013B00 */ +#define PERI_MS_PPU_FX_TCPWM1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[205]) /* 0x40013B40 */ +#define PERI_MS_PPU_FX_LCD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[206]) /* 0x40013B80 */ +#define PERI_MS_PPU_FX_USBFS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[207]) /* 0x40013BC0 */ +#define PERI_MS_PPU_FX_SMIF0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[208]) /* 0x40013C00 */ +#define PERI_MS_PPU_FX_SDHC0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[209]) /* 0x40013C40 */ +#define PERI_MS_PPU_FX_CANFD0_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[210]) /* 0x40013C80 */ +#define PERI_MS_PPU_FX_CANFD0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[211]) /* 0x40013CC0 */ +#define PERI_MS_PPU_FX_CANFD0_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[212]) /* 0x40013D00 */ +#define PERI_MS_PPU_FX_SCB0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[213]) /* 0x40013D40 */ +#define PERI_MS_PPU_FX_SCB1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[214]) /* 0x40013D80 */ +#define PERI_MS_PPU_FX_SCB2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[215]) /* 0x40013DC0 */ +#define PERI_MS_PPU_FX_SCB3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[216]) /* 0x40013E00 */ +#define PERI_MS_PPU_FX_SCB4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[217]) /* 0x40013E40 */ +#define PERI_MS_PPU_FX_SCB5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[218]) /* 0x40013E80 */ +#define PERI_MS_PPU_FX_SCB6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[219]) /* 0x40013EC0 */ + +/******************************************************************************* +* CPUSS +*******************************************************************************/ + +#define CPUSS_BASE 0x40200000UL +#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40200000 */ + +/******************************************************************************* +* FAULT +*******************************************************************************/ + +#define FAULT_BASE 0x40210000UL +#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40210000 */ +#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40210000 */ +#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40210100 */ + +/******************************************************************************* +* IPC +*******************************************************************************/ + +#define IPC_BASE 0x40220000UL +#define IPC ((IPC_Type*) IPC_BASE) /* 0x40220000 */ +#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40220000 */ +#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40220020 */ +#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40220040 */ +#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40220060 */ +#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40220080 */ +#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402200A0 */ +#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402200C0 */ +#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402200E0 */ +#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40220100 */ +#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40220120 */ +#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40220140 */ +#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40220160 */ +#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40220180 */ +#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402201A0 */ +#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402201C0 */ +#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402201E0 */ +#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40221000 */ +#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40221020 */ +#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40221040 */ +#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40221060 */ +#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40221080 */ +#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402210A0 */ +#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402210C0 */ +#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402210E0 */ +#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40221100 */ +#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40221120 */ +#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40221140 */ +#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40221160 */ +#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40221180 */ +#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402211A0 */ +#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402211C0 */ +#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402211E0 */ + +/******************************************************************************* +* PROT +*******************************************************************************/ + +#define PROT_BASE 0x40230000UL +#define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ +#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ +#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ +#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402320C0 */ +#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40232100 */ +#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40232140 */ +#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40232180 */ +#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402321C0 */ +#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40232200 */ +#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40232240 */ +#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40232280 */ +#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402322C0 */ +#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40232300 */ +#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ +#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ +#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ +#define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ +#define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ +#define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ +#define PROT_MPU5_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[3]) /* 0x40235660 */ +#define PROT_MPU5_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[4]) /* 0x40235680 */ +#define PROT_MPU5_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[5]) /* 0x402356A0 */ +#define PROT_MPU5_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[6]) /* 0x402356C0 */ +#define PROT_MPU5_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[7]) /* 0x402356E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ + +/******************************************************************************* +* FLASHC +*******************************************************************************/ + +#define FLASHC_BASE 0x40240000UL +#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40240000 */ +#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4024F000 */ + +/******************************************************************************* +* SRSS +*******************************************************************************/ + +#define SRSS_BASE 0x40260000UL +#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ +#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */ +#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */ + +/******************************************************************************* +* BACKUP +*******************************************************************************/ + +#define BACKUP_BASE 0x40270000UL +#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ + +/******************************************************************************* +* DW +*******************************************************************************/ + +#define DW0_BASE 0x40280000UL +#define DW1_BASE 0x40290000UL +#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ +#define DW1 ((DW_Type*) DW1_BASE) /* 0x40290000 */ +#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40288000 */ +#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40288040 */ +#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40288080 */ +#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x402880C0 */ +#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40288100 */ +#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x40288140 */ +#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x40288180 */ +#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402881C0 */ +#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40288200 */ +#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40288240 */ +#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40288280 */ +#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x402882C0 */ +#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40288300 */ +#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x40288340 */ +#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x40288380 */ +#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402883C0 */ +#define DW0_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[16]) /* 0x40288400 */ +#define DW0_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[17]) /* 0x40288440 */ +#define DW0_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[18]) /* 0x40288480 */ +#define DW0_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[19]) /* 0x402884C0 */ +#define DW0_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[20]) /* 0x40288500 */ +#define DW0_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[21]) /* 0x40288540 */ +#define DW0_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[22]) /* 0x40288580 */ +#define DW0_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[23]) /* 0x402885C0 */ +#define DW0_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[24]) /* 0x40288600 */ +#define DW0_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[25]) /* 0x40288640 */ +#define DW0_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[26]) /* 0x40288680 */ +#define DW0_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[27]) /* 0x402886C0 */ +#define DW0_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[28]) /* 0x40288700 */ +#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40298000 */ +#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40298040 */ +#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40298080 */ +#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x402980C0 */ +#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40298100 */ +#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x40298140 */ +#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x40298180 */ +#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402981C0 */ +#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40298200 */ +#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40298240 */ +#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40298280 */ +#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x402982C0 */ +#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40298300 */ +#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x40298340 */ +#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x40298380 */ +#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402983C0 */ +#define DW1_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[16]) /* 0x40298400 */ +#define DW1_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[17]) /* 0x40298440 */ +#define DW1_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[18]) /* 0x40298480 */ +#define DW1_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[19]) /* 0x402984C0 */ +#define DW1_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[20]) /* 0x40298500 */ +#define DW1_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[21]) /* 0x40298540 */ +#define DW1_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[22]) /* 0x40298580 */ +#define DW1_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[23]) /* 0x402985C0 */ +#define DW1_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[24]) /* 0x40298600 */ +#define DW1_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[25]) /* 0x40298640 */ +#define DW1_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[26]) /* 0x40298680 */ +#define DW1_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[27]) /* 0x402986C0 */ +#define DW1_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[28]) /* 0x40298700 */ +#define DW1_CH_STRUCT29 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[29]) /* 0x40298740 */ +#define DW1_CH_STRUCT30 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[30]) /* 0x40298780 */ +#define DW1_CH_STRUCT31 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[31]) /* 0x402987C0 */ + +/******************************************************************************* +* DMAC +*******************************************************************************/ + +#define DMAC_BASE 0x402A0000UL +#define DMAC ((DMAC_Type*) DMAC_BASE) /* 0x402A0000 */ +#define DMAC_CH0 ((DMAC_CH_Type*) &DMAC->CH[0]) /* 0x402A1000 */ +#define DMAC_CH1 ((DMAC_CH_Type*) &DMAC->CH[1]) /* 0x402A1100 */ + +/******************************************************************************* +* EFUSE +*******************************************************************************/ + +#define EFUSE_BASE 0x402C0000UL +#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ + +/******************************************************************************* +* HSIOM +*******************************************************************************/ + +#define HSIOM_BASE 0x40300000UL +#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40300000 */ +#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40300000 */ +#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40300010 */ +#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40300020 */ +#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40300030 */ +#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40300040 */ +#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40300050 */ +#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40300060 */ +#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40300070 */ +#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40300080 */ +#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40300090 */ +#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403000A0 */ +#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403000B0 */ +#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403000C0 */ +#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403000D0 */ +#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403000E0 */ + +/******************************************************************************* +* GPIO +*******************************************************************************/ + +#define GPIO_BASE 0x40310000UL +#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40310000 */ +#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40310000 */ +#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40310080 */ +#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40310100 */ +#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40310180 */ +#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40310200 */ +#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40310280 */ +#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40310300 */ +#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40310380 */ +#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40310400 */ +#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40310480 */ +#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40310500 */ +#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40310580 */ +#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40310600 */ +#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40310680 */ +#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40310700 */ + +/******************************************************************************* +* SMARTIO +*******************************************************************************/ + +#define SMARTIO_BASE 0x40320000UL +#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40320000 */ +#define SMARTIO_PRT8 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[8]) /* 0x40320800 */ +#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40320900 */ + +/******************************************************************************* +* LPCOMP +*******************************************************************************/ + +#define LPCOMP_BASE 0x40350000UL +#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */ + +/******************************************************************************* +* CSD +*******************************************************************************/ + +#define CSD0_BASE 0x40360000UL +#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */ + +/******************************************************************************* +* TCPWM +*******************************************************************************/ + +#define TCPWM0_BASE 0x40380000UL +#define TCPWM1_BASE 0x40390000UL +#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM1 ((TCPWM_Type*) TCPWM1_BASE) /* 0x40390000 */ +#define TCPWM0_CNT0 ((TCPWM_CNT_Type*) &TCPWM0->CNT[0]) /* 0x40380100 */ +#define TCPWM0_CNT1 ((TCPWM_CNT_Type*) &TCPWM0->CNT[1]) /* 0x40380140 */ +#define TCPWM0_CNT2 ((TCPWM_CNT_Type*) &TCPWM0->CNT[2]) /* 0x40380180 */ +#define TCPWM0_CNT3 ((TCPWM_CNT_Type*) &TCPWM0->CNT[3]) /* 0x403801C0 */ +#define TCPWM1_CNT0 ((TCPWM_CNT_Type*) &TCPWM1->CNT[0]) /* 0x40390100 */ +#define TCPWM1_CNT1 ((TCPWM_CNT_Type*) &TCPWM1->CNT[1]) /* 0x40390140 */ +#define TCPWM1_CNT2 ((TCPWM_CNT_Type*) &TCPWM1->CNT[2]) /* 0x40390180 */ +#define TCPWM1_CNT3 ((TCPWM_CNT_Type*) &TCPWM1->CNT[3]) /* 0x403901C0 */ +#define TCPWM1_CNT4 ((TCPWM_CNT_Type*) &TCPWM1->CNT[4]) /* 0x40390200 */ +#define TCPWM1_CNT5 ((TCPWM_CNT_Type*) &TCPWM1->CNT[5]) /* 0x40390240 */ +#define TCPWM1_CNT6 ((TCPWM_CNT_Type*) &TCPWM1->CNT[6]) /* 0x40390280 */ +#define TCPWM1_CNT7 ((TCPWM_CNT_Type*) &TCPWM1->CNT[7]) /* 0x403902C0 */ + +/******************************************************************************* +* LCD +*******************************************************************************/ + +#define LCD0_BASE 0x403B0000UL +#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ + +/******************************************************************************* +* USBFS +*******************************************************************************/ + +#define USBFS0_BASE 0x403F0000UL +#define USBFS0 ((USBFS_Type*) USBFS0_BASE) /* 0x403F0000 */ +#define USBFS0_USBDEV ((USBFS_USBDEV_Type*) &USBFS0->USBDEV) /* 0x403F0000 */ +#define USBFS0_USBLPM ((USBFS_USBLPM_Type*) &USBFS0->USBLPM) /* 0x403F2000 */ +#define USBFS0_USBHOST ((USBFS_USBHOST_Type*) &USBFS0->USBHOST) /* 0x403F4000 */ + +/******************************************************************************* +* SMIF +*******************************************************************************/ + +#define SMIF0_BASE 0x40420000UL +#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ +#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ +#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ +#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ + +/******************************************************************************* +* SDHC +*******************************************************************************/ + +#define SDHC0_BASE 0x40460000UL +#define SDHC0 ((SDHC_Type*) SDHC0_BASE) /* 0x40460000 */ +#define SDHC0_WRAP ((SDHC_WRAP_Type*) &SDHC0->WRAP) /* 0x40460000 */ +#define SDHC0_CORE ((SDHC_CORE_Type*) &SDHC0->CORE) /* 0x40461000 */ + +/******************************************************************************* +* CANFD +*******************************************************************************/ + +#define CANFD0_BASE 0x40520000UL +#define CANFD0 ((CANFD_Type*) CANFD0_BASE) /* 0x40520000 */ +#define CANFD0_CH0 ((CANFD_CH_Type*) &CANFD0->CH[0]) /* 0x40520000 */ +#define CANFD0_CH0_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[0].M_TTCAN) /* 0x40520000 */ + +/******************************************************************************* +* SCB +*******************************************************************************/ + +#define SCB0_BASE 0x40600000UL +#define SCB1_BASE 0x40610000UL +#define SCB2_BASE 0x40620000UL +#define SCB3_BASE 0x40630000UL +#define SCB4_BASE 0x40640000UL +#define SCB5_BASE 0x40650000UL +#define SCB6_BASE 0x40660000UL +#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40600000 */ +#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40610000 */ +#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40620000 */ +#define SCB3 ((CySCB_Type*) SCB3_BASE) /* 0x40630000 */ +#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40640000 */ +#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40650000 */ +#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40660000 */ + +/******************************************************************************* +* SAR +*******************************************************************************/ + +#define SAR_BASE 0x409D0000UL +#define SAR ((SAR_Type*) SAR_BASE) /* 0x409D0000 */ + +/******************************************************************************* +* PASS +*******************************************************************************/ + +#define PASS_BASE 0x409F0000UL +#define PASS ((PASS_Type*) PASS_BASE) /* 0x409F0000 */ +#define PASS_AREF ((PASS_AREF_Type*) &PASS->AREF) /* 0x409F0E00 */ + +/** \} CY8C6145AZI-S3F12 */ + +#endif /* _CY8C6145AZI_S3F12_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6145azi_s3f42.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6145azi_s3f42.h new file mode 100644 index 0000000000..de940011a7 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6145azi_s3f42.h @@ -0,0 +1,993 @@ +/***************************************************************************//** +* \file cy8c6145azi_s3f42.h +* +* \brief +* CY8C6145AZI-S3F42 device header +* +* \note +* Generator version: 1.6.0.225 +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CY8C6145AZI_S3F42_H_ +#define _CY8C6145AZI_S3F42_H_ + +/** +* \addtogroup group_device CY8C6145AZI-S3F42 +* \{ +*/ + +/** +* \addtogroup Configuration_of_CMSIS +* \{ +*/ + +/******************************************************************************* +* Interrupt Number Definition +*******************************************************************************/ + +typedef enum { + /* ARM Cortex-M4 Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C6145AZI-S3F42 Peripheral Interrupt Numbers */ + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_6_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #6 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + canfd_0_interrupt0_IRQn = 168, /*!< 168 [Active] Can #0, Consolidated interrupt #0 */ + canfd_0_interrupts0_0_IRQn = 169, /*!< 169 [Active] CAN #0, Interrupt #0, Channel #0 */ + canfd_0_interrupts1_0_IRQn = 170, /*!< 170 [Active] CAN #0, Interrupt #1, Channel #0 */ + cpuss_interrupts_dw1_29_IRQn = 171, /*!< 171 [Active] CPUSS DataWire #1, Channel #29 */ + cpuss_interrupts_dw1_30_IRQn = 172, /*!< 172 [Active] CPUSS DataWire #1, Channel #30 */ + cpuss_interrupts_dw1_31_IRQn = 173, /*!< 173 [Active] CPUSS DataWire #1, Channel #31 */ + unconnected_IRQn = 240 /*!< 240 Unconnected */ +} IRQn_Type; + + +/******************************************************************************* +* Processor and Core Peripheral Section +*******************************************************************************/ + +/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __CM0P_PRESENT 0 /*!< CM0P present or not */ +#define __DTCM_PRESENT 0 /*!< DTCM present or not */ +#define __ICACHE_PRESENT 0 /*!< ICACHE present or not */ +#define __DCACHE_PRESENT 0 /*!< DCACHE present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + + +/* Memory Blocks */ +#define CY_ROM_BASE 0x00000000UL +#define CY_ROM_SIZE 0x00010000UL +#define CY_SRAM_BASE 0x08000000UL +#define CY_SRAM_SIZE 0x00040000UL +#define CY_FLASH_BASE 0x10000000UL +#define CY_FLASH_SIZE 0x00080000UL +#define CY_EM_EEPROM_BASE 0x14000000UL +#define CY_EM_EEPROM_SIZE 0x00008000UL +#define CY_SFLASH_BASE 0x16000000UL +#define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL +#define CY_EFUSE_BASE 0x402C0800UL +#define CY_EFUSE_SIZE 0x00000200UL +#define CY_CAN0MRAM_BASE 0x40530000UL +#define CY_CAN0MRAM_SIZE 0x00010000UL + +#include "system_psoc6.h" /*!< PSoC 6 System */ + +/* IP List */ +#define CY_IP_MXTTCANFD 1u +#define CY_IP_MXTTCANFD_INSTANCES 1u +#define CY_IP_MXTTCANFD_VERSION 1u +#define CY_IP_M4CPUSS 1u +#define CY_IP_M4CPUSS_INSTANCES 1u +#define CY_IP_M4CPUSS_VERSION 2u +#define CY_IP_M4CPUSS_DMAC 1u +#define CY_IP_M4CPUSS_DMAC_INSTANCES 1u +#define CY_IP_M4CPUSS_DMAC_VERSION 2u +#define CY_IP_M4CPUSS_DMA 1u +#define CY_IP_M4CPUSS_DMA_INSTANCES 2u +#define CY_IP_M4CPUSS_DMA_VERSION 2u +#define CY_IP_MXCRYPTO 1u +#define CY_IP_MXCRYPTO_INSTANCES 1u +#define CY_IP_MXCRYPTO_VERSION 2u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 2u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u +#define CY_IP_MXS40PASS 1u +#define CY_IP_MXS40PASS_INSTANCES 1u +#define CY_IP_MXS40PASS_VERSION 1u +#define CY_IP_MXS40PASS_SAR 1u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u +#define CY_IP_MXS40PASS_SAR_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 7u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 1u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u + +#include "psoc6_03_config.h" +#include "gpio_psoc6_03_100_tqfp.h" + +#define CY_DEVICE_PSOC6A512K +#define CY_SILICON_ID 0xE7141105UL +#define CY_HF_CLK_MAX_FREQ 150000000UL + +#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL + +/******************************************************************************* +* SFLASH +*******************************************************************************/ + +#define SFLASH_BASE 0x16000000UL +#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */ + +/******************************************************************************* +* PERI +*******************************************************************************/ + +#define PERI_BASE 0x40000000UL +#define PERI ((PERI_Type*) PERI_BASE) /* 0x40000000 */ +#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40004000 */ +#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40004020 */ +#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40004040 */ +#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x40004060 */ +#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40004080 */ +#define PERI_GR5 ((PERI_GR_Type*) &PERI->GR[5]) /* 0x400040A0 */ +#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x400040C0 */ +#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40004120 */ +#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40008000 */ +#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40008400 */ +#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40008800 */ +#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40008C00 */ +#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40009000 */ +#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40009400 */ +#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40009800 */ +#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40009C00 */ +#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ +#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ +#define PERI_TR_GR10 ((PERI_TR_GR_Type*) &PERI->TR_GR[10]) /* 0x4000A800 */ +#define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ +#define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ +#define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ +#define PERI_TR_1TO1_GR3 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[3]) /* 0x4000CC00 */ +#define PERI_TR_1TO1_GR4 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[4]) /* 0x4000D000 */ +#define PERI_TR_1TO1_GR5 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[5]) /* 0x4000D400 */ +#define PERI_TR_1TO1_GR6 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[6]) /* 0x4000D800 */ +#define PERI_TR_1TO1_GR7 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[7]) /* 0x4000DC00 */ + +/******************************************************************************* +* PERI_MS +*******************************************************************************/ + +#define PERI_MS_BASE 0x40010000UL +#define PERI_MS ((PERI_MS_Type*) PERI_MS_BASE) /* 0x40010000 */ +#define PERI_MS_PPU_PR0 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[0]) /* 0x40010000 */ +#define PERI_MS_PPU_PR1 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[1]) /* 0x40010040 */ +#define PERI_MS_PPU_PR2 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[2]) /* 0x40010080 */ +#define PERI_MS_PPU_PR3 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[3]) /* 0x400100C0 */ +#define PERI_MS_PPU_PR4 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[4]) /* 0x40010100 */ +#define PERI_MS_PPU_PR5 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[5]) /* 0x40010140 */ +#define PERI_MS_PPU_PR6 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[6]) /* 0x40010180 */ +#define PERI_MS_PPU_PR7 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[7]) /* 0x400101C0 */ +#define PERI_MS_PPU_FX_PERI_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[0]) /* 0x40010800 */ +#define PERI_MS_PPU_FX_PERI_GR0_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[1]) /* 0x40010840 */ +#define PERI_MS_PPU_FX_PERI_GR1_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[2]) /* 0x40010880 */ +#define PERI_MS_PPU_FX_PERI_GR2_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[3]) /* 0x400108C0 */ +#define PERI_MS_PPU_FX_PERI_GR3_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[4]) /* 0x40010900 */ +#define PERI_MS_PPU_FX_PERI_GR4_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[5]) /* 0x40010940 */ +#define PERI_MS_PPU_FX_PERI_GR5_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[6]) /* 0x40010980 */ +#define PERI_MS_PPU_FX_PERI_GR6_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[7]) /* 0x400109C0 */ +#define PERI_MS_PPU_FX_PERI_GR9_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[8]) /* 0x40010A00 */ +#define PERI_MS_PPU_FX_PERI_TR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[9]) /* 0x40010A40 */ +#define PERI_MS_PPU_FX_CRYPTO_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[10]) /* 0x40010A80 */ +#define PERI_MS_PPU_FX_CRYPTO_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[11]) /* 0x40010AC0 */ +#define PERI_MS_PPU_FX_CRYPTO_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[12]) /* 0x40010B00 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[13]) /* 0x40010B40 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[14]) /* 0x40010B80 */ +#define PERI_MS_PPU_FX_CRYPTO_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[15]) /* 0x40010BC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[16]) /* 0x40010C00 */ +#define PERI_MS_PPU_FX_CPUSS_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[17]) /* 0x40010C40 */ +#define PERI_MS_PPU_FX_CPUSS_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[18]) /* 0x40010C80 */ +#define PERI_MS_PPU_FX_CPUSS_CM0_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[19]) /* 0x40010CC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[20]) /* 0x40010D00 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[21]) /* 0x40010D40 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT1_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[22]) /* 0x40010D80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT0_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[23]) /* 0x40010DC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT1_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[24]) /* 0x40010E00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT2_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[25]) /* 0x40010E40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT3_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[26]) /* 0x40010E80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT4_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[27]) /* 0x40010EC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT5_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[28]) /* 0x40010F00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT6_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[29]) /* 0x40010F40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT7_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[30]) /* 0x40010F80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT8_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[31]) /* 0x40010FC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT9_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[32]) /* 0x40011000 */ +#define PERI_MS_PPU_FX_IPC_STRUCT10_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[33]) /* 0x40011040 */ +#define PERI_MS_PPU_FX_IPC_STRUCT11_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[34]) /* 0x40011080 */ +#define PERI_MS_PPU_FX_IPC_STRUCT12_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[35]) /* 0x400110C0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT13_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[36]) /* 0x40011100 */ +#define PERI_MS_PPU_FX_IPC_STRUCT14_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[37]) /* 0x40011140 */ +#define PERI_MS_PPU_FX_IPC_STRUCT15_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[38]) /* 0x40011180 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT0_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[39]) /* 0x400111C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT1_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[40]) /* 0x40011200 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT2_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[41]) /* 0x40011240 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT3_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[42]) /* 0x40011280 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT4_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[43]) /* 0x400112C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT5_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[44]) /* 0x40011300 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT6_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[45]) /* 0x40011340 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT7_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[46]) /* 0x40011380 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT8_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[47]) /* 0x400113C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT9_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[48]) /* 0x40011400 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT10_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[49]) /* 0x40011440 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT11_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[50]) /* 0x40011480 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT12_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[51]) /* 0x400114C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT13_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[52]) /* 0x40011500 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT14_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[53]) /* 0x40011540 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT15_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[54]) /* 0x40011580 */ +#define PERI_MS_PPU_FX_PROT_SMPU_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[55]) /* 0x400115C0 */ +#define PERI_MS_PPU_FX_PROT_MPU0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[56]) /* 0x40011600 */ +#define PERI_MS_PPU_FX_PROT_MPU5_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[57]) /* 0x40011640 */ +#define PERI_MS_PPU_FX_PROT_MPU14_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[58]) /* 0x40011680 */ +#define PERI_MS_PPU_FX_PROT_MPU15_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[59]) /* 0x400116C0 */ +#define PERI_MS_PPU_FX_FLASHC_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[60]) /* 0x40011700 */ +#define PERI_MS_PPU_FX_FLASHC_CMD ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[61]) /* 0x40011740 */ +#define PERI_MS_PPU_FX_FLASHC_DFT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[62]) /* 0x40011780 */ +#define PERI_MS_PPU_FX_FLASHC_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[63]) /* 0x400117C0 */ +#define PERI_MS_PPU_FX_FLASHC_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[64]) /* 0x40011800 */ +#define PERI_MS_PPU_FX_FLASHC_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[65]) /* 0x40011840 */ +#define PERI_MS_PPU_FX_FLASHC_DW0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[66]) /* 0x40011880 */ +#define PERI_MS_PPU_FX_FLASHC_DW1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[67]) /* 0x400118C0 */ +#define PERI_MS_PPU_FX_FLASHC_DMAC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[68]) /* 0x40011900 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[69]) /* 0x40011940 */ +#define PERI_MS_PPU_FX_FLASHC_FM ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[70]) /* 0x40011980 */ +#define PERI_MS_PPU_FX_SRSS_MAIN1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[71]) /* 0x400119C0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[72]) /* 0x40011A00 */ +#define PERI_MS_PPU_FX_WDT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[73]) /* 0x40011A40 */ +#define PERI_MS_PPU_FX_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[74]) /* 0x40011A80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[75]) /* 0x40011AC0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[76]) /* 0x40011B00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[77]) /* 0x40011B40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[78]) /* 0x40011B80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[79]) /* 0x40011BC0 */ +#define PERI_MS_PPU_FX_BACKUP_BACKUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[80]) /* 0x40011C00 */ +#define PERI_MS_PPU_FX_DW0_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[81]) /* 0x40011C40 */ +#define PERI_MS_PPU_FX_DW1_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[82]) /* 0x40011C80 */ +#define PERI_MS_PPU_FX_DW0_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[83]) /* 0x40011CC0 */ +#define PERI_MS_PPU_FX_DW1_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[84]) /* 0x40011D00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[85]) /* 0x40011D40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[86]) /* 0x40011D80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[87]) /* 0x40011DC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[88]) /* 0x40011E00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[89]) /* 0x40011E40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[90]) /* 0x40011E80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[91]) /* 0x40011EC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[92]) /* 0x40011F00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[93]) /* 0x40011F40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[94]) /* 0x40011F80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[95]) /* 0x40011FC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[96]) /* 0x40012000 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[97]) /* 0x40012040 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[98]) /* 0x40012080 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[99]) /* 0x400120C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[100]) /* 0x40012100 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[101]) /* 0x40012140 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[102]) /* 0x40012180 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[103]) /* 0x400121C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[104]) /* 0x40012200 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[105]) /* 0x40012240 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[106]) /* 0x40012280 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[107]) /* 0x400122C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[108]) /* 0x40012300 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[109]) /* 0x40012340 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[110]) /* 0x40012380 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[111]) /* 0x400123C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[112]) /* 0x40012400 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[113]) /* 0x40012440 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[114]) /* 0x40012480 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[115]) /* 0x400124C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[116]) /* 0x40012500 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[117]) /* 0x40012540 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[118]) /* 0x40012580 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[119]) /* 0x400125C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[120]) /* 0x40012600 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[121]) /* 0x40012640 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[122]) /* 0x40012680 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[123]) /* 0x400126C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[124]) /* 0x40012700 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[125]) /* 0x40012740 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[126]) /* 0x40012780 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[127]) /* 0x400127C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[128]) /* 0x40012800 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[129]) /* 0x40012840 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[130]) /* 0x40012880 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[131]) /* 0x400128C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[132]) /* 0x40012900 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[133]) /* 0x40012940 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[134]) /* 0x40012980 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[135]) /* 0x400129C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[136]) /* 0x40012A00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[137]) /* 0x40012A40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[138]) /* 0x40012A80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[139]) /* 0x40012AC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[140]) /* 0x40012B00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[141]) /* 0x40012B40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[142]) /* 0x40012B80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT29_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[143]) /* 0x40012BC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT30_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[144]) /* 0x40012C00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT31_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[145]) /* 0x40012C40 */ +#define PERI_MS_PPU_FX_DMAC_TOP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[146]) /* 0x40012C80 */ +#define PERI_MS_PPU_FX_DMAC_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[147]) /* 0x40012CC0 */ +#define PERI_MS_PPU_FX_DMAC_CH1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[148]) /* 0x40012D00 */ +#define PERI_MS_PPU_FX_EFUSE_CTL ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[149]) /* 0x40012D40 */ +#define PERI_MS_PPU_FX_EFUSE_DATA ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[150]) /* 0x40012D80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[151]) /* 0x40012DC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[152]) /* 0x40012E00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[153]) /* 0x40012E40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[154]) /* 0x40012E80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[155]) /* 0x40012EC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[156]) /* 0x40012F00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[157]) /* 0x40012F40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[158]) /* 0x40012F80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[159]) /* 0x40012FC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[160]) /* 0x40013000 */ +#define PERI_MS_PPU_FX_HSIOM_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[161]) /* 0x40013040 */ +#define PERI_MS_PPU_FX_HSIOM_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[162]) /* 0x40013080 */ +#define PERI_MS_PPU_FX_HSIOM_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[163]) /* 0x400130C0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[164]) /* 0x40013100 */ +#define PERI_MS_PPU_FX_HSIOM_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[165]) /* 0x40013140 */ +#define PERI_MS_PPU_FX_HSIOM_AMUX ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[166]) /* 0x40013180 */ +#define PERI_MS_PPU_FX_HSIOM_MON ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[167]) /* 0x400131C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[168]) /* 0x40013200 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[169]) /* 0x40013240 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[170]) /* 0x40013280 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[171]) /* 0x400132C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[172]) /* 0x40013300 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[173]) /* 0x40013340 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[174]) /* 0x40013380 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[175]) /* 0x400133C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[176]) /* 0x40013400 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[177]) /* 0x40013440 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[178]) /* 0x40013480 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[179]) /* 0x400134C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[180]) /* 0x40013500 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[181]) /* 0x40013540 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[182]) /* 0x40013580 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[183]) /* 0x400135C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[184]) /* 0x40013600 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[185]) /* 0x40013640 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[186]) /* 0x40013680 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[187]) /* 0x400136C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[188]) /* 0x40013700 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[189]) /* 0x40013740 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[190]) /* 0x40013780 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[191]) /* 0x400137C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[192]) /* 0x40013800 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[193]) /* 0x40013840 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[194]) /* 0x40013880 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[195]) /* 0x400138C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[196]) /* 0x40013900 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[197]) /* 0x40013940 */ +#define PERI_MS_PPU_FX_GPIO_GPIO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[198]) /* 0x40013980 */ +#define PERI_MS_PPU_FX_GPIO_TEST ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[199]) /* 0x400139C0 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[200]) /* 0x40013A00 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[201]) /* 0x40013A40 */ +#define PERI_MS_PPU_FX_LPCOMP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[202]) /* 0x40013A80 */ +#define PERI_MS_PPU_FX_CSD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[203]) /* 0x40013AC0 */ +#define PERI_MS_PPU_FX_TCPWM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[204]) /* 0x40013B00 */ +#define PERI_MS_PPU_FX_TCPWM1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[205]) /* 0x40013B40 */ +#define PERI_MS_PPU_FX_LCD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[206]) /* 0x40013B80 */ +#define PERI_MS_PPU_FX_USBFS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[207]) /* 0x40013BC0 */ +#define PERI_MS_PPU_FX_SMIF0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[208]) /* 0x40013C00 */ +#define PERI_MS_PPU_FX_SDHC0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[209]) /* 0x40013C40 */ +#define PERI_MS_PPU_FX_CANFD0_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[210]) /* 0x40013C80 */ +#define PERI_MS_PPU_FX_CANFD0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[211]) /* 0x40013CC0 */ +#define PERI_MS_PPU_FX_CANFD0_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[212]) /* 0x40013D00 */ +#define PERI_MS_PPU_FX_SCB0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[213]) /* 0x40013D40 */ +#define PERI_MS_PPU_FX_SCB1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[214]) /* 0x40013D80 */ +#define PERI_MS_PPU_FX_SCB2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[215]) /* 0x40013DC0 */ +#define PERI_MS_PPU_FX_SCB3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[216]) /* 0x40013E00 */ +#define PERI_MS_PPU_FX_SCB4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[217]) /* 0x40013E40 */ +#define PERI_MS_PPU_FX_SCB5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[218]) /* 0x40013E80 */ +#define PERI_MS_PPU_FX_SCB6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[219]) /* 0x40013EC0 */ + +/******************************************************************************* +* CRYPTO +*******************************************************************************/ + +#define CRYPTO_BASE 0x40100000UL +#define CRYPTO ((CRYPTO_Type*) CRYPTO_BASE) /* 0x40100000 */ + +/******************************************************************************* +* CPUSS +*******************************************************************************/ + +#define CPUSS_BASE 0x40200000UL +#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40200000 */ + +/******************************************************************************* +* FAULT +*******************************************************************************/ + +#define FAULT_BASE 0x40210000UL +#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40210000 */ +#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40210000 */ +#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40210100 */ + +/******************************************************************************* +* IPC +*******************************************************************************/ + +#define IPC_BASE 0x40220000UL +#define IPC ((IPC_Type*) IPC_BASE) /* 0x40220000 */ +#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40220000 */ +#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40220020 */ +#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40220040 */ +#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40220060 */ +#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40220080 */ +#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402200A0 */ +#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402200C0 */ +#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402200E0 */ +#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40220100 */ +#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40220120 */ +#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40220140 */ +#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40220160 */ +#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40220180 */ +#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402201A0 */ +#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402201C0 */ +#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402201E0 */ +#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40221000 */ +#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40221020 */ +#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40221040 */ +#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40221060 */ +#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40221080 */ +#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402210A0 */ +#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402210C0 */ +#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402210E0 */ +#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40221100 */ +#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40221120 */ +#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40221140 */ +#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40221160 */ +#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40221180 */ +#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402211A0 */ +#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402211C0 */ +#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402211E0 */ + +/******************************************************************************* +* PROT +*******************************************************************************/ + +#define PROT_BASE 0x40230000UL +#define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ +#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ +#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ +#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402320C0 */ +#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40232100 */ +#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40232140 */ +#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40232180 */ +#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402321C0 */ +#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40232200 */ +#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40232240 */ +#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40232280 */ +#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402322C0 */ +#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40232300 */ +#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ +#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ +#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ +#define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ +#define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ +#define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ +#define PROT_MPU5_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[3]) /* 0x40235660 */ +#define PROT_MPU5_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[4]) /* 0x40235680 */ +#define PROT_MPU5_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[5]) /* 0x402356A0 */ +#define PROT_MPU5_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[6]) /* 0x402356C0 */ +#define PROT_MPU5_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[7]) /* 0x402356E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ + +/******************************************************************************* +* FLASHC +*******************************************************************************/ + +#define FLASHC_BASE 0x40240000UL +#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40240000 */ +#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4024F000 */ + +/******************************************************************************* +* SRSS +*******************************************************************************/ + +#define SRSS_BASE 0x40260000UL +#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ +#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */ +#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */ + +/******************************************************************************* +* BACKUP +*******************************************************************************/ + +#define BACKUP_BASE 0x40270000UL +#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ + +/******************************************************************************* +* DW +*******************************************************************************/ + +#define DW0_BASE 0x40280000UL +#define DW1_BASE 0x40290000UL +#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ +#define DW1 ((DW_Type*) DW1_BASE) /* 0x40290000 */ +#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40288000 */ +#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40288040 */ +#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40288080 */ +#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x402880C0 */ +#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40288100 */ +#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x40288140 */ +#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x40288180 */ +#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402881C0 */ +#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40288200 */ +#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40288240 */ +#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40288280 */ +#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x402882C0 */ +#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40288300 */ +#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x40288340 */ +#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x40288380 */ +#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402883C0 */ +#define DW0_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[16]) /* 0x40288400 */ +#define DW0_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[17]) /* 0x40288440 */ +#define DW0_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[18]) /* 0x40288480 */ +#define DW0_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[19]) /* 0x402884C0 */ +#define DW0_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[20]) /* 0x40288500 */ +#define DW0_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[21]) /* 0x40288540 */ +#define DW0_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[22]) /* 0x40288580 */ +#define DW0_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[23]) /* 0x402885C0 */ +#define DW0_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[24]) /* 0x40288600 */ +#define DW0_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[25]) /* 0x40288640 */ +#define DW0_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[26]) /* 0x40288680 */ +#define DW0_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[27]) /* 0x402886C0 */ +#define DW0_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[28]) /* 0x40288700 */ +#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40298000 */ +#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40298040 */ +#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40298080 */ +#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x402980C0 */ +#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40298100 */ +#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x40298140 */ +#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x40298180 */ +#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402981C0 */ +#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40298200 */ +#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40298240 */ +#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40298280 */ +#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x402982C0 */ +#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40298300 */ +#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x40298340 */ +#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x40298380 */ +#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402983C0 */ +#define DW1_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[16]) /* 0x40298400 */ +#define DW1_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[17]) /* 0x40298440 */ +#define DW1_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[18]) /* 0x40298480 */ +#define DW1_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[19]) /* 0x402984C0 */ +#define DW1_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[20]) /* 0x40298500 */ +#define DW1_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[21]) /* 0x40298540 */ +#define DW1_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[22]) /* 0x40298580 */ +#define DW1_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[23]) /* 0x402985C0 */ +#define DW1_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[24]) /* 0x40298600 */ +#define DW1_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[25]) /* 0x40298640 */ +#define DW1_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[26]) /* 0x40298680 */ +#define DW1_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[27]) /* 0x402986C0 */ +#define DW1_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[28]) /* 0x40298700 */ +#define DW1_CH_STRUCT29 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[29]) /* 0x40298740 */ +#define DW1_CH_STRUCT30 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[30]) /* 0x40298780 */ +#define DW1_CH_STRUCT31 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[31]) /* 0x402987C0 */ + +/******************************************************************************* +* DMAC +*******************************************************************************/ + +#define DMAC_BASE 0x402A0000UL +#define DMAC ((DMAC_Type*) DMAC_BASE) /* 0x402A0000 */ +#define DMAC_CH0 ((DMAC_CH_Type*) &DMAC->CH[0]) /* 0x402A1000 */ +#define DMAC_CH1 ((DMAC_CH_Type*) &DMAC->CH[1]) /* 0x402A1100 */ + +/******************************************************************************* +* EFUSE +*******************************************************************************/ + +#define EFUSE_BASE 0x402C0000UL +#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ + +/******************************************************************************* +* HSIOM +*******************************************************************************/ + +#define HSIOM_BASE 0x40300000UL +#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40300000 */ +#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40300000 */ +#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40300010 */ +#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40300020 */ +#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40300030 */ +#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40300040 */ +#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40300050 */ +#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40300060 */ +#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40300070 */ +#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40300080 */ +#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40300090 */ +#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403000A0 */ +#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403000B0 */ +#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403000C0 */ +#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403000D0 */ +#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403000E0 */ + +/******************************************************************************* +* GPIO +*******************************************************************************/ + +#define GPIO_BASE 0x40310000UL +#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40310000 */ +#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40310000 */ +#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40310080 */ +#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40310100 */ +#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40310180 */ +#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40310200 */ +#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40310280 */ +#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40310300 */ +#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40310380 */ +#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40310400 */ +#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40310480 */ +#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40310500 */ +#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40310580 */ +#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40310600 */ +#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40310680 */ +#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40310700 */ + +/******************************************************************************* +* SMARTIO +*******************************************************************************/ + +#define SMARTIO_BASE 0x40320000UL +#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40320000 */ +#define SMARTIO_PRT8 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[8]) /* 0x40320800 */ +#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40320900 */ + +/******************************************************************************* +* LPCOMP +*******************************************************************************/ + +#define LPCOMP_BASE 0x40350000UL +#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */ + +/******************************************************************************* +* CSD +*******************************************************************************/ + +#define CSD0_BASE 0x40360000UL +#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */ + +/******************************************************************************* +* TCPWM +*******************************************************************************/ + +#define TCPWM0_BASE 0x40380000UL +#define TCPWM1_BASE 0x40390000UL +#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM1 ((TCPWM_Type*) TCPWM1_BASE) /* 0x40390000 */ +#define TCPWM0_CNT0 ((TCPWM_CNT_Type*) &TCPWM0->CNT[0]) /* 0x40380100 */ +#define TCPWM0_CNT1 ((TCPWM_CNT_Type*) &TCPWM0->CNT[1]) /* 0x40380140 */ +#define TCPWM0_CNT2 ((TCPWM_CNT_Type*) &TCPWM0->CNT[2]) /* 0x40380180 */ +#define TCPWM0_CNT3 ((TCPWM_CNT_Type*) &TCPWM0->CNT[3]) /* 0x403801C0 */ +#define TCPWM1_CNT0 ((TCPWM_CNT_Type*) &TCPWM1->CNT[0]) /* 0x40390100 */ +#define TCPWM1_CNT1 ((TCPWM_CNT_Type*) &TCPWM1->CNT[1]) /* 0x40390140 */ +#define TCPWM1_CNT2 ((TCPWM_CNT_Type*) &TCPWM1->CNT[2]) /* 0x40390180 */ +#define TCPWM1_CNT3 ((TCPWM_CNT_Type*) &TCPWM1->CNT[3]) /* 0x403901C0 */ +#define TCPWM1_CNT4 ((TCPWM_CNT_Type*) &TCPWM1->CNT[4]) /* 0x40390200 */ +#define TCPWM1_CNT5 ((TCPWM_CNT_Type*) &TCPWM1->CNT[5]) /* 0x40390240 */ +#define TCPWM1_CNT6 ((TCPWM_CNT_Type*) &TCPWM1->CNT[6]) /* 0x40390280 */ +#define TCPWM1_CNT7 ((TCPWM_CNT_Type*) &TCPWM1->CNT[7]) /* 0x403902C0 */ + +/******************************************************************************* +* LCD +*******************************************************************************/ + +#define LCD0_BASE 0x403B0000UL +#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ + +/******************************************************************************* +* USBFS +*******************************************************************************/ + +#define USBFS0_BASE 0x403F0000UL +#define USBFS0 ((USBFS_Type*) USBFS0_BASE) /* 0x403F0000 */ +#define USBFS0_USBDEV ((USBFS_USBDEV_Type*) &USBFS0->USBDEV) /* 0x403F0000 */ +#define USBFS0_USBLPM ((USBFS_USBLPM_Type*) &USBFS0->USBLPM) /* 0x403F2000 */ +#define USBFS0_USBHOST ((USBFS_USBHOST_Type*) &USBFS0->USBHOST) /* 0x403F4000 */ + +/******************************************************************************* +* SMIF +*******************************************************************************/ + +#define SMIF0_BASE 0x40420000UL +#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ +#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ +#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ +#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ + +/******************************************************************************* +* SDHC +*******************************************************************************/ + +#define SDHC0_BASE 0x40460000UL +#define SDHC0 ((SDHC_Type*) SDHC0_BASE) /* 0x40460000 */ +#define SDHC0_WRAP ((SDHC_WRAP_Type*) &SDHC0->WRAP) /* 0x40460000 */ +#define SDHC0_CORE ((SDHC_CORE_Type*) &SDHC0->CORE) /* 0x40461000 */ + +/******************************************************************************* +* CANFD +*******************************************************************************/ + +#define CANFD0_BASE 0x40520000UL +#define CANFD0 ((CANFD_Type*) CANFD0_BASE) /* 0x40520000 */ +#define CANFD0_CH0 ((CANFD_CH_Type*) &CANFD0->CH[0]) /* 0x40520000 */ +#define CANFD0_CH0_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[0].M_TTCAN) /* 0x40520000 */ + +/******************************************************************************* +* SCB +*******************************************************************************/ + +#define SCB0_BASE 0x40600000UL +#define SCB1_BASE 0x40610000UL +#define SCB2_BASE 0x40620000UL +#define SCB3_BASE 0x40630000UL +#define SCB4_BASE 0x40640000UL +#define SCB5_BASE 0x40650000UL +#define SCB6_BASE 0x40660000UL +#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40600000 */ +#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40610000 */ +#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40620000 */ +#define SCB3 ((CySCB_Type*) SCB3_BASE) /* 0x40630000 */ +#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40640000 */ +#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40650000 */ +#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40660000 */ + +/******************************************************************************* +* SAR +*******************************************************************************/ + +#define SAR_BASE 0x409D0000UL +#define SAR ((SAR_Type*) SAR_BASE) /* 0x409D0000 */ + +/******************************************************************************* +* PASS +*******************************************************************************/ + +#define PASS_BASE 0x409F0000UL +#define PASS ((PASS_Type*) PASS_BASE) /* 0x409F0000 */ +#define PASS_AREF ((PASS_AREF_Type*) &PASS->AREF) /* 0x409F0E00 */ + +/** \} CY8C6145AZI-S3F42 */ + +#endif /* _CY8C6145AZI_S3F42_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6145azi_s3f62.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6145azi_s3f62.h new file mode 100644 index 0000000000..4fbace6c09 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6145azi_s3f62.h @@ -0,0 +1,983 @@ +/***************************************************************************//** +* \file cy8c6145azi_s3f62.h +* +* \brief +* CY8C6145AZI-S3F62 device header +* +* \note +* Generator version: 1.6.0.225 +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CY8C6145AZI_S3F62_H_ +#define _CY8C6145AZI_S3F62_H_ + +/** +* \addtogroup group_device CY8C6145AZI-S3F62 +* \{ +*/ + +/** +* \addtogroup Configuration_of_CMSIS +* \{ +*/ + +/******************************************************************************* +* Interrupt Number Definition +*******************************************************************************/ + +typedef enum { + /* ARM Cortex-M4 Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C6145AZI-S3F62 Peripheral Interrupt Numbers */ + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_6_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #6 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + canfd_0_interrupt0_IRQn = 168, /*!< 168 [Active] Can #0, Consolidated interrupt #0 */ + canfd_0_interrupts0_0_IRQn = 169, /*!< 169 [Active] CAN #0, Interrupt #0, Channel #0 */ + canfd_0_interrupts1_0_IRQn = 170, /*!< 170 [Active] CAN #0, Interrupt #1, Channel #0 */ + cpuss_interrupts_dw1_29_IRQn = 171, /*!< 171 [Active] CPUSS DataWire #1, Channel #29 */ + cpuss_interrupts_dw1_30_IRQn = 172, /*!< 172 [Active] CPUSS DataWire #1, Channel #30 */ + cpuss_interrupts_dw1_31_IRQn = 173, /*!< 173 [Active] CPUSS DataWire #1, Channel #31 */ + unconnected_IRQn = 240 /*!< 240 Unconnected */ +} IRQn_Type; + + +/******************************************************************************* +* Processor and Core Peripheral Section +*******************************************************************************/ + +/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __CM0P_PRESENT 0 /*!< CM0P present or not */ +#define __DTCM_PRESENT 0 /*!< DTCM present or not */ +#define __ICACHE_PRESENT 0 /*!< ICACHE present or not */ +#define __DCACHE_PRESENT 0 /*!< DCACHE present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + + +/* Memory Blocks */ +#define CY_ROM_BASE 0x00000000UL +#define CY_ROM_SIZE 0x00010000UL +#define CY_SRAM_BASE 0x08000000UL +#define CY_SRAM_SIZE 0x00040000UL +#define CY_FLASH_BASE 0x10000000UL +#define CY_FLASH_SIZE 0x00080000UL +#define CY_EM_EEPROM_BASE 0x14000000UL +#define CY_EM_EEPROM_SIZE 0x00008000UL +#define CY_SFLASH_BASE 0x16000000UL +#define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL +#define CY_EFUSE_BASE 0x402C0800UL +#define CY_EFUSE_SIZE 0x00000200UL +#define CY_CAN0MRAM_BASE 0x40530000UL +#define CY_CAN0MRAM_SIZE 0x00010000UL + +#include "system_psoc6.h" /*!< PSoC 6 System */ + +/* IP List */ +#define CY_IP_MXTTCANFD 1u +#define CY_IP_MXTTCANFD_INSTANCES 1u +#define CY_IP_MXTTCANFD_VERSION 1u +#define CY_IP_M4CPUSS 1u +#define CY_IP_M4CPUSS_INSTANCES 1u +#define CY_IP_M4CPUSS_VERSION 2u +#define CY_IP_M4CPUSS_DMAC 1u +#define CY_IP_M4CPUSS_DMAC_INSTANCES 1u +#define CY_IP_M4CPUSS_DMAC_VERSION 2u +#define CY_IP_M4CPUSS_DMA 1u +#define CY_IP_M4CPUSS_DMA_INSTANCES 2u +#define CY_IP_M4CPUSS_DMA_VERSION 2u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 2u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u +#define CY_IP_MXS40PASS 1u +#define CY_IP_MXS40PASS_INSTANCES 1u +#define CY_IP_MXS40PASS_VERSION 1u +#define CY_IP_MXS40PASS_SAR 1u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u +#define CY_IP_MXS40PASS_SAR_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 7u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 1u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u + +#include "psoc6_03_config.h" +#include "gpio_psoc6_03_100_tqfp.h" + +#define CY_DEVICE_PSOC6A512K +#define CY_SILICON_ID 0xE7121105UL +#define CY_HF_CLK_MAX_FREQ 150000000UL + +#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL + +/******************************************************************************* +* SFLASH +*******************************************************************************/ + +#define SFLASH_BASE 0x16000000UL +#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */ + +/******************************************************************************* +* PERI +*******************************************************************************/ + +#define PERI_BASE 0x40000000UL +#define PERI ((PERI_Type*) PERI_BASE) /* 0x40000000 */ +#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40004000 */ +#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40004020 */ +#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40004040 */ +#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x40004060 */ +#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40004080 */ +#define PERI_GR5 ((PERI_GR_Type*) &PERI->GR[5]) /* 0x400040A0 */ +#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x400040C0 */ +#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40004120 */ +#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40008000 */ +#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40008400 */ +#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40008800 */ +#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40008C00 */ +#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40009000 */ +#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40009400 */ +#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40009800 */ +#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40009C00 */ +#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ +#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ +#define PERI_TR_GR10 ((PERI_TR_GR_Type*) &PERI->TR_GR[10]) /* 0x4000A800 */ +#define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ +#define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ +#define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ +#define PERI_TR_1TO1_GR3 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[3]) /* 0x4000CC00 */ +#define PERI_TR_1TO1_GR4 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[4]) /* 0x4000D000 */ +#define PERI_TR_1TO1_GR5 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[5]) /* 0x4000D400 */ +#define PERI_TR_1TO1_GR6 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[6]) /* 0x4000D800 */ +#define PERI_TR_1TO1_GR7 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[7]) /* 0x4000DC00 */ + +/******************************************************************************* +* PERI_MS +*******************************************************************************/ + +#define PERI_MS_BASE 0x40010000UL +#define PERI_MS ((PERI_MS_Type*) PERI_MS_BASE) /* 0x40010000 */ +#define PERI_MS_PPU_PR0 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[0]) /* 0x40010000 */ +#define PERI_MS_PPU_PR1 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[1]) /* 0x40010040 */ +#define PERI_MS_PPU_PR2 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[2]) /* 0x40010080 */ +#define PERI_MS_PPU_PR3 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[3]) /* 0x400100C0 */ +#define PERI_MS_PPU_PR4 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[4]) /* 0x40010100 */ +#define PERI_MS_PPU_PR5 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[5]) /* 0x40010140 */ +#define PERI_MS_PPU_PR6 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[6]) /* 0x40010180 */ +#define PERI_MS_PPU_PR7 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[7]) /* 0x400101C0 */ +#define PERI_MS_PPU_FX_PERI_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[0]) /* 0x40010800 */ +#define PERI_MS_PPU_FX_PERI_GR0_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[1]) /* 0x40010840 */ +#define PERI_MS_PPU_FX_PERI_GR1_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[2]) /* 0x40010880 */ +#define PERI_MS_PPU_FX_PERI_GR2_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[3]) /* 0x400108C0 */ +#define PERI_MS_PPU_FX_PERI_GR3_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[4]) /* 0x40010900 */ +#define PERI_MS_PPU_FX_PERI_GR4_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[5]) /* 0x40010940 */ +#define PERI_MS_PPU_FX_PERI_GR5_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[6]) /* 0x40010980 */ +#define PERI_MS_PPU_FX_PERI_GR6_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[7]) /* 0x400109C0 */ +#define PERI_MS_PPU_FX_PERI_GR9_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[8]) /* 0x40010A00 */ +#define PERI_MS_PPU_FX_PERI_TR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[9]) /* 0x40010A40 */ +#define PERI_MS_PPU_FX_CRYPTO_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[10]) /* 0x40010A80 */ +#define PERI_MS_PPU_FX_CRYPTO_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[11]) /* 0x40010AC0 */ +#define PERI_MS_PPU_FX_CRYPTO_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[12]) /* 0x40010B00 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[13]) /* 0x40010B40 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[14]) /* 0x40010B80 */ +#define PERI_MS_PPU_FX_CRYPTO_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[15]) /* 0x40010BC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[16]) /* 0x40010C00 */ +#define PERI_MS_PPU_FX_CPUSS_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[17]) /* 0x40010C40 */ +#define PERI_MS_PPU_FX_CPUSS_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[18]) /* 0x40010C80 */ +#define PERI_MS_PPU_FX_CPUSS_CM0_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[19]) /* 0x40010CC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[20]) /* 0x40010D00 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[21]) /* 0x40010D40 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT1_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[22]) /* 0x40010D80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT0_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[23]) /* 0x40010DC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT1_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[24]) /* 0x40010E00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT2_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[25]) /* 0x40010E40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT3_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[26]) /* 0x40010E80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT4_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[27]) /* 0x40010EC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT5_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[28]) /* 0x40010F00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT6_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[29]) /* 0x40010F40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT7_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[30]) /* 0x40010F80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT8_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[31]) /* 0x40010FC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT9_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[32]) /* 0x40011000 */ +#define PERI_MS_PPU_FX_IPC_STRUCT10_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[33]) /* 0x40011040 */ +#define PERI_MS_PPU_FX_IPC_STRUCT11_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[34]) /* 0x40011080 */ +#define PERI_MS_PPU_FX_IPC_STRUCT12_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[35]) /* 0x400110C0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT13_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[36]) /* 0x40011100 */ +#define PERI_MS_PPU_FX_IPC_STRUCT14_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[37]) /* 0x40011140 */ +#define PERI_MS_PPU_FX_IPC_STRUCT15_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[38]) /* 0x40011180 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT0_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[39]) /* 0x400111C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT1_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[40]) /* 0x40011200 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT2_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[41]) /* 0x40011240 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT3_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[42]) /* 0x40011280 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT4_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[43]) /* 0x400112C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT5_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[44]) /* 0x40011300 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT6_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[45]) /* 0x40011340 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT7_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[46]) /* 0x40011380 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT8_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[47]) /* 0x400113C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT9_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[48]) /* 0x40011400 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT10_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[49]) /* 0x40011440 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT11_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[50]) /* 0x40011480 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT12_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[51]) /* 0x400114C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT13_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[52]) /* 0x40011500 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT14_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[53]) /* 0x40011540 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT15_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[54]) /* 0x40011580 */ +#define PERI_MS_PPU_FX_PROT_SMPU_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[55]) /* 0x400115C0 */ +#define PERI_MS_PPU_FX_PROT_MPU0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[56]) /* 0x40011600 */ +#define PERI_MS_PPU_FX_PROT_MPU5_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[57]) /* 0x40011640 */ +#define PERI_MS_PPU_FX_PROT_MPU14_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[58]) /* 0x40011680 */ +#define PERI_MS_PPU_FX_PROT_MPU15_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[59]) /* 0x400116C0 */ +#define PERI_MS_PPU_FX_FLASHC_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[60]) /* 0x40011700 */ +#define PERI_MS_PPU_FX_FLASHC_CMD ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[61]) /* 0x40011740 */ +#define PERI_MS_PPU_FX_FLASHC_DFT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[62]) /* 0x40011780 */ +#define PERI_MS_PPU_FX_FLASHC_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[63]) /* 0x400117C0 */ +#define PERI_MS_PPU_FX_FLASHC_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[64]) /* 0x40011800 */ +#define PERI_MS_PPU_FX_FLASHC_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[65]) /* 0x40011840 */ +#define PERI_MS_PPU_FX_FLASHC_DW0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[66]) /* 0x40011880 */ +#define PERI_MS_PPU_FX_FLASHC_DW1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[67]) /* 0x400118C0 */ +#define PERI_MS_PPU_FX_FLASHC_DMAC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[68]) /* 0x40011900 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[69]) /* 0x40011940 */ +#define PERI_MS_PPU_FX_FLASHC_FM ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[70]) /* 0x40011980 */ +#define PERI_MS_PPU_FX_SRSS_MAIN1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[71]) /* 0x400119C0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[72]) /* 0x40011A00 */ +#define PERI_MS_PPU_FX_WDT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[73]) /* 0x40011A40 */ +#define PERI_MS_PPU_FX_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[74]) /* 0x40011A80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[75]) /* 0x40011AC0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[76]) /* 0x40011B00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[77]) /* 0x40011B40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[78]) /* 0x40011B80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[79]) /* 0x40011BC0 */ +#define PERI_MS_PPU_FX_BACKUP_BACKUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[80]) /* 0x40011C00 */ +#define PERI_MS_PPU_FX_DW0_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[81]) /* 0x40011C40 */ +#define PERI_MS_PPU_FX_DW1_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[82]) /* 0x40011C80 */ +#define PERI_MS_PPU_FX_DW0_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[83]) /* 0x40011CC0 */ +#define PERI_MS_PPU_FX_DW1_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[84]) /* 0x40011D00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[85]) /* 0x40011D40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[86]) /* 0x40011D80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[87]) /* 0x40011DC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[88]) /* 0x40011E00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[89]) /* 0x40011E40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[90]) /* 0x40011E80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[91]) /* 0x40011EC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[92]) /* 0x40011F00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[93]) /* 0x40011F40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[94]) /* 0x40011F80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[95]) /* 0x40011FC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[96]) /* 0x40012000 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[97]) /* 0x40012040 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[98]) /* 0x40012080 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[99]) /* 0x400120C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[100]) /* 0x40012100 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[101]) /* 0x40012140 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[102]) /* 0x40012180 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[103]) /* 0x400121C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[104]) /* 0x40012200 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[105]) /* 0x40012240 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[106]) /* 0x40012280 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[107]) /* 0x400122C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[108]) /* 0x40012300 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[109]) /* 0x40012340 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[110]) /* 0x40012380 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[111]) /* 0x400123C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[112]) /* 0x40012400 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[113]) /* 0x40012440 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[114]) /* 0x40012480 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[115]) /* 0x400124C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[116]) /* 0x40012500 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[117]) /* 0x40012540 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[118]) /* 0x40012580 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[119]) /* 0x400125C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[120]) /* 0x40012600 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[121]) /* 0x40012640 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[122]) /* 0x40012680 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[123]) /* 0x400126C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[124]) /* 0x40012700 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[125]) /* 0x40012740 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[126]) /* 0x40012780 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[127]) /* 0x400127C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[128]) /* 0x40012800 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[129]) /* 0x40012840 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[130]) /* 0x40012880 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[131]) /* 0x400128C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[132]) /* 0x40012900 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[133]) /* 0x40012940 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[134]) /* 0x40012980 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[135]) /* 0x400129C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[136]) /* 0x40012A00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[137]) /* 0x40012A40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[138]) /* 0x40012A80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[139]) /* 0x40012AC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[140]) /* 0x40012B00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[141]) /* 0x40012B40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[142]) /* 0x40012B80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT29_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[143]) /* 0x40012BC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT30_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[144]) /* 0x40012C00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT31_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[145]) /* 0x40012C40 */ +#define PERI_MS_PPU_FX_DMAC_TOP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[146]) /* 0x40012C80 */ +#define PERI_MS_PPU_FX_DMAC_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[147]) /* 0x40012CC0 */ +#define PERI_MS_PPU_FX_DMAC_CH1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[148]) /* 0x40012D00 */ +#define PERI_MS_PPU_FX_EFUSE_CTL ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[149]) /* 0x40012D40 */ +#define PERI_MS_PPU_FX_EFUSE_DATA ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[150]) /* 0x40012D80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[151]) /* 0x40012DC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[152]) /* 0x40012E00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[153]) /* 0x40012E40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[154]) /* 0x40012E80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[155]) /* 0x40012EC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[156]) /* 0x40012F00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[157]) /* 0x40012F40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[158]) /* 0x40012F80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[159]) /* 0x40012FC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[160]) /* 0x40013000 */ +#define PERI_MS_PPU_FX_HSIOM_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[161]) /* 0x40013040 */ +#define PERI_MS_PPU_FX_HSIOM_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[162]) /* 0x40013080 */ +#define PERI_MS_PPU_FX_HSIOM_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[163]) /* 0x400130C0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[164]) /* 0x40013100 */ +#define PERI_MS_PPU_FX_HSIOM_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[165]) /* 0x40013140 */ +#define PERI_MS_PPU_FX_HSIOM_AMUX ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[166]) /* 0x40013180 */ +#define PERI_MS_PPU_FX_HSIOM_MON ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[167]) /* 0x400131C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[168]) /* 0x40013200 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[169]) /* 0x40013240 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[170]) /* 0x40013280 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[171]) /* 0x400132C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[172]) /* 0x40013300 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[173]) /* 0x40013340 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[174]) /* 0x40013380 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[175]) /* 0x400133C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[176]) /* 0x40013400 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[177]) /* 0x40013440 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[178]) /* 0x40013480 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[179]) /* 0x400134C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[180]) /* 0x40013500 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[181]) /* 0x40013540 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[182]) /* 0x40013580 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[183]) /* 0x400135C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[184]) /* 0x40013600 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[185]) /* 0x40013640 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[186]) /* 0x40013680 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[187]) /* 0x400136C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[188]) /* 0x40013700 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[189]) /* 0x40013740 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[190]) /* 0x40013780 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[191]) /* 0x400137C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[192]) /* 0x40013800 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[193]) /* 0x40013840 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[194]) /* 0x40013880 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[195]) /* 0x400138C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[196]) /* 0x40013900 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[197]) /* 0x40013940 */ +#define PERI_MS_PPU_FX_GPIO_GPIO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[198]) /* 0x40013980 */ +#define PERI_MS_PPU_FX_GPIO_TEST ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[199]) /* 0x400139C0 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[200]) /* 0x40013A00 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[201]) /* 0x40013A40 */ +#define PERI_MS_PPU_FX_LPCOMP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[202]) /* 0x40013A80 */ +#define PERI_MS_PPU_FX_CSD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[203]) /* 0x40013AC0 */ +#define PERI_MS_PPU_FX_TCPWM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[204]) /* 0x40013B00 */ +#define PERI_MS_PPU_FX_TCPWM1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[205]) /* 0x40013B40 */ +#define PERI_MS_PPU_FX_LCD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[206]) /* 0x40013B80 */ +#define PERI_MS_PPU_FX_USBFS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[207]) /* 0x40013BC0 */ +#define PERI_MS_PPU_FX_SMIF0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[208]) /* 0x40013C00 */ +#define PERI_MS_PPU_FX_SDHC0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[209]) /* 0x40013C40 */ +#define PERI_MS_PPU_FX_CANFD0_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[210]) /* 0x40013C80 */ +#define PERI_MS_PPU_FX_CANFD0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[211]) /* 0x40013CC0 */ +#define PERI_MS_PPU_FX_CANFD0_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[212]) /* 0x40013D00 */ +#define PERI_MS_PPU_FX_SCB0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[213]) /* 0x40013D40 */ +#define PERI_MS_PPU_FX_SCB1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[214]) /* 0x40013D80 */ +#define PERI_MS_PPU_FX_SCB2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[215]) /* 0x40013DC0 */ +#define PERI_MS_PPU_FX_SCB3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[216]) /* 0x40013E00 */ +#define PERI_MS_PPU_FX_SCB4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[217]) /* 0x40013E40 */ +#define PERI_MS_PPU_FX_SCB5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[218]) /* 0x40013E80 */ +#define PERI_MS_PPU_FX_SCB6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[219]) /* 0x40013EC0 */ + +/******************************************************************************* +* CPUSS +*******************************************************************************/ + +#define CPUSS_BASE 0x40200000UL +#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40200000 */ + +/******************************************************************************* +* FAULT +*******************************************************************************/ + +#define FAULT_BASE 0x40210000UL +#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40210000 */ +#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40210000 */ +#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40210100 */ + +/******************************************************************************* +* IPC +*******************************************************************************/ + +#define IPC_BASE 0x40220000UL +#define IPC ((IPC_Type*) IPC_BASE) /* 0x40220000 */ +#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40220000 */ +#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40220020 */ +#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40220040 */ +#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40220060 */ +#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40220080 */ +#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402200A0 */ +#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402200C0 */ +#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402200E0 */ +#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40220100 */ +#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40220120 */ +#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40220140 */ +#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40220160 */ +#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40220180 */ +#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402201A0 */ +#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402201C0 */ +#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402201E0 */ +#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40221000 */ +#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40221020 */ +#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40221040 */ +#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40221060 */ +#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40221080 */ +#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402210A0 */ +#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402210C0 */ +#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402210E0 */ +#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40221100 */ +#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40221120 */ +#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40221140 */ +#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40221160 */ +#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40221180 */ +#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402211A0 */ +#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402211C0 */ +#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402211E0 */ + +/******************************************************************************* +* PROT +*******************************************************************************/ + +#define PROT_BASE 0x40230000UL +#define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ +#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ +#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ +#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402320C0 */ +#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40232100 */ +#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40232140 */ +#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40232180 */ +#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402321C0 */ +#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40232200 */ +#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40232240 */ +#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40232280 */ +#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402322C0 */ +#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40232300 */ +#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ +#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ +#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ +#define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ +#define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ +#define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ +#define PROT_MPU5_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[3]) /* 0x40235660 */ +#define PROT_MPU5_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[4]) /* 0x40235680 */ +#define PROT_MPU5_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[5]) /* 0x402356A0 */ +#define PROT_MPU5_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[6]) /* 0x402356C0 */ +#define PROT_MPU5_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[7]) /* 0x402356E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ + +/******************************************************************************* +* FLASHC +*******************************************************************************/ + +#define FLASHC_BASE 0x40240000UL +#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40240000 */ +#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4024F000 */ + +/******************************************************************************* +* SRSS +*******************************************************************************/ + +#define SRSS_BASE 0x40260000UL +#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ +#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */ +#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */ + +/******************************************************************************* +* BACKUP +*******************************************************************************/ + +#define BACKUP_BASE 0x40270000UL +#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ + +/******************************************************************************* +* DW +*******************************************************************************/ + +#define DW0_BASE 0x40280000UL +#define DW1_BASE 0x40290000UL +#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ +#define DW1 ((DW_Type*) DW1_BASE) /* 0x40290000 */ +#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40288000 */ +#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40288040 */ +#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40288080 */ +#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x402880C0 */ +#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40288100 */ +#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x40288140 */ +#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x40288180 */ +#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402881C0 */ +#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40288200 */ +#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40288240 */ +#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40288280 */ +#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x402882C0 */ +#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40288300 */ +#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x40288340 */ +#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x40288380 */ +#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402883C0 */ +#define DW0_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[16]) /* 0x40288400 */ +#define DW0_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[17]) /* 0x40288440 */ +#define DW0_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[18]) /* 0x40288480 */ +#define DW0_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[19]) /* 0x402884C0 */ +#define DW0_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[20]) /* 0x40288500 */ +#define DW0_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[21]) /* 0x40288540 */ +#define DW0_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[22]) /* 0x40288580 */ +#define DW0_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[23]) /* 0x402885C0 */ +#define DW0_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[24]) /* 0x40288600 */ +#define DW0_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[25]) /* 0x40288640 */ +#define DW0_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[26]) /* 0x40288680 */ +#define DW0_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[27]) /* 0x402886C0 */ +#define DW0_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[28]) /* 0x40288700 */ +#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40298000 */ +#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40298040 */ +#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40298080 */ +#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x402980C0 */ +#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40298100 */ +#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x40298140 */ +#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x40298180 */ +#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402981C0 */ +#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40298200 */ +#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40298240 */ +#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40298280 */ +#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x402982C0 */ +#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40298300 */ +#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x40298340 */ +#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x40298380 */ +#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402983C0 */ +#define DW1_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[16]) /* 0x40298400 */ +#define DW1_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[17]) /* 0x40298440 */ +#define DW1_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[18]) /* 0x40298480 */ +#define DW1_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[19]) /* 0x402984C0 */ +#define DW1_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[20]) /* 0x40298500 */ +#define DW1_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[21]) /* 0x40298540 */ +#define DW1_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[22]) /* 0x40298580 */ +#define DW1_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[23]) /* 0x402985C0 */ +#define DW1_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[24]) /* 0x40298600 */ +#define DW1_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[25]) /* 0x40298640 */ +#define DW1_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[26]) /* 0x40298680 */ +#define DW1_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[27]) /* 0x402986C0 */ +#define DW1_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[28]) /* 0x40298700 */ +#define DW1_CH_STRUCT29 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[29]) /* 0x40298740 */ +#define DW1_CH_STRUCT30 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[30]) /* 0x40298780 */ +#define DW1_CH_STRUCT31 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[31]) /* 0x402987C0 */ + +/******************************************************************************* +* DMAC +*******************************************************************************/ + +#define DMAC_BASE 0x402A0000UL +#define DMAC ((DMAC_Type*) DMAC_BASE) /* 0x402A0000 */ +#define DMAC_CH0 ((DMAC_CH_Type*) &DMAC->CH[0]) /* 0x402A1000 */ +#define DMAC_CH1 ((DMAC_CH_Type*) &DMAC->CH[1]) /* 0x402A1100 */ + +/******************************************************************************* +* EFUSE +*******************************************************************************/ + +#define EFUSE_BASE 0x402C0000UL +#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ + +/******************************************************************************* +* HSIOM +*******************************************************************************/ + +#define HSIOM_BASE 0x40300000UL +#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40300000 */ +#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40300000 */ +#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40300010 */ +#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40300020 */ +#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40300030 */ +#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40300040 */ +#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40300050 */ +#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40300060 */ +#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40300070 */ +#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40300080 */ +#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40300090 */ +#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403000A0 */ +#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403000B0 */ +#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403000C0 */ +#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403000D0 */ +#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403000E0 */ + +/******************************************************************************* +* GPIO +*******************************************************************************/ + +#define GPIO_BASE 0x40310000UL +#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40310000 */ +#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40310000 */ +#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40310080 */ +#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40310100 */ +#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40310180 */ +#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40310200 */ +#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40310280 */ +#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40310300 */ +#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40310380 */ +#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40310400 */ +#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40310480 */ +#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40310500 */ +#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40310580 */ +#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40310600 */ +#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40310680 */ +#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40310700 */ + +/******************************************************************************* +* SMARTIO +*******************************************************************************/ + +#define SMARTIO_BASE 0x40320000UL +#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40320000 */ +#define SMARTIO_PRT8 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[8]) /* 0x40320800 */ +#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40320900 */ + +/******************************************************************************* +* LPCOMP +*******************************************************************************/ + +#define LPCOMP_BASE 0x40350000UL +#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */ + +/******************************************************************************* +* CSD +*******************************************************************************/ + +#define CSD0_BASE 0x40360000UL +#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */ + +/******************************************************************************* +* TCPWM +*******************************************************************************/ + +#define TCPWM0_BASE 0x40380000UL +#define TCPWM1_BASE 0x40390000UL +#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM1 ((TCPWM_Type*) TCPWM1_BASE) /* 0x40390000 */ +#define TCPWM0_CNT0 ((TCPWM_CNT_Type*) &TCPWM0->CNT[0]) /* 0x40380100 */ +#define TCPWM0_CNT1 ((TCPWM_CNT_Type*) &TCPWM0->CNT[1]) /* 0x40380140 */ +#define TCPWM0_CNT2 ((TCPWM_CNT_Type*) &TCPWM0->CNT[2]) /* 0x40380180 */ +#define TCPWM0_CNT3 ((TCPWM_CNT_Type*) &TCPWM0->CNT[3]) /* 0x403801C0 */ +#define TCPWM1_CNT0 ((TCPWM_CNT_Type*) &TCPWM1->CNT[0]) /* 0x40390100 */ +#define TCPWM1_CNT1 ((TCPWM_CNT_Type*) &TCPWM1->CNT[1]) /* 0x40390140 */ +#define TCPWM1_CNT2 ((TCPWM_CNT_Type*) &TCPWM1->CNT[2]) /* 0x40390180 */ +#define TCPWM1_CNT3 ((TCPWM_CNT_Type*) &TCPWM1->CNT[3]) /* 0x403901C0 */ +#define TCPWM1_CNT4 ((TCPWM_CNT_Type*) &TCPWM1->CNT[4]) /* 0x40390200 */ +#define TCPWM1_CNT5 ((TCPWM_CNT_Type*) &TCPWM1->CNT[5]) /* 0x40390240 */ +#define TCPWM1_CNT6 ((TCPWM_CNT_Type*) &TCPWM1->CNT[6]) /* 0x40390280 */ +#define TCPWM1_CNT7 ((TCPWM_CNT_Type*) &TCPWM1->CNT[7]) /* 0x403902C0 */ + +/******************************************************************************* +* LCD +*******************************************************************************/ + +#define LCD0_BASE 0x403B0000UL +#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ + +/******************************************************************************* +* USBFS +*******************************************************************************/ + +#define USBFS0_BASE 0x403F0000UL +#define USBFS0 ((USBFS_Type*) USBFS0_BASE) /* 0x403F0000 */ +#define USBFS0_USBDEV ((USBFS_USBDEV_Type*) &USBFS0->USBDEV) /* 0x403F0000 */ +#define USBFS0_USBLPM ((USBFS_USBLPM_Type*) &USBFS0->USBLPM) /* 0x403F2000 */ +#define USBFS0_USBHOST ((USBFS_USBHOST_Type*) &USBFS0->USBHOST) /* 0x403F4000 */ + +/******************************************************************************* +* SMIF +*******************************************************************************/ + +#define SMIF0_BASE 0x40420000UL +#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ +#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ +#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ +#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ + +/******************************************************************************* +* SDHC +*******************************************************************************/ + +#define SDHC0_BASE 0x40460000UL +#define SDHC0 ((SDHC_Type*) SDHC0_BASE) /* 0x40460000 */ +#define SDHC0_WRAP ((SDHC_WRAP_Type*) &SDHC0->WRAP) /* 0x40460000 */ +#define SDHC0_CORE ((SDHC_CORE_Type*) &SDHC0->CORE) /* 0x40461000 */ + +/******************************************************************************* +* CANFD +*******************************************************************************/ + +#define CANFD0_BASE 0x40520000UL +#define CANFD0 ((CANFD_Type*) CANFD0_BASE) /* 0x40520000 */ +#define CANFD0_CH0 ((CANFD_CH_Type*) &CANFD0->CH[0]) /* 0x40520000 */ +#define CANFD0_CH0_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[0].M_TTCAN) /* 0x40520000 */ + +/******************************************************************************* +* SCB +*******************************************************************************/ + +#define SCB0_BASE 0x40600000UL +#define SCB1_BASE 0x40610000UL +#define SCB2_BASE 0x40620000UL +#define SCB3_BASE 0x40630000UL +#define SCB4_BASE 0x40640000UL +#define SCB5_BASE 0x40650000UL +#define SCB6_BASE 0x40660000UL +#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40600000 */ +#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40610000 */ +#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40620000 */ +#define SCB3 ((CySCB_Type*) SCB3_BASE) /* 0x40630000 */ +#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40640000 */ +#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40650000 */ +#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40660000 */ + +/******************************************************************************* +* SAR +*******************************************************************************/ + +#define SAR_BASE 0x409D0000UL +#define SAR ((SAR_Type*) SAR_BASE) /* 0x409D0000 */ + +/******************************************************************************* +* PASS +*******************************************************************************/ + +#define PASS_BASE 0x409F0000UL +#define PASS ((PASS_Type*) PASS_BASE) /* 0x409F0000 */ +#define PASS_AREF ((PASS_AREF_Type*) &PASS->AREF) /* 0x409F0E00 */ + +/** \} CY8C6145AZI-S3F62 */ + +#endif /* _CY8C6145AZI_S3F62_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6145azi_s3f72.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6145azi_s3f72.h new file mode 100644 index 0000000000..7a16cf8aad --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6145azi_s3f72.h @@ -0,0 +1,993 @@ +/***************************************************************************//** +* \file cy8c6145azi_s3f72.h +* +* \brief +* CY8C6145AZI-S3F72 device header +* +* \note +* Generator version: 1.6.0.225 +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CY8C6145AZI_S3F72_H_ +#define _CY8C6145AZI_S3F72_H_ + +/** +* \addtogroup group_device CY8C6145AZI-S3F72 +* \{ +*/ + +/** +* \addtogroup Configuration_of_CMSIS +* \{ +*/ + +/******************************************************************************* +* Interrupt Number Definition +*******************************************************************************/ + +typedef enum { + /* ARM Cortex-M4 Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C6145AZI-S3F72 Peripheral Interrupt Numbers */ + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_6_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #6 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + canfd_0_interrupt0_IRQn = 168, /*!< 168 [Active] Can #0, Consolidated interrupt #0 */ + canfd_0_interrupts0_0_IRQn = 169, /*!< 169 [Active] CAN #0, Interrupt #0, Channel #0 */ + canfd_0_interrupts1_0_IRQn = 170, /*!< 170 [Active] CAN #0, Interrupt #1, Channel #0 */ + cpuss_interrupts_dw1_29_IRQn = 171, /*!< 171 [Active] CPUSS DataWire #1, Channel #29 */ + cpuss_interrupts_dw1_30_IRQn = 172, /*!< 172 [Active] CPUSS DataWire #1, Channel #30 */ + cpuss_interrupts_dw1_31_IRQn = 173, /*!< 173 [Active] CPUSS DataWire #1, Channel #31 */ + unconnected_IRQn = 240 /*!< 240 Unconnected */ +} IRQn_Type; + + +/******************************************************************************* +* Processor and Core Peripheral Section +*******************************************************************************/ + +/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __CM0P_PRESENT 0 /*!< CM0P present or not */ +#define __DTCM_PRESENT 0 /*!< DTCM present or not */ +#define __ICACHE_PRESENT 0 /*!< ICACHE present or not */ +#define __DCACHE_PRESENT 0 /*!< DCACHE present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + + +/* Memory Blocks */ +#define CY_ROM_BASE 0x00000000UL +#define CY_ROM_SIZE 0x00010000UL +#define CY_SRAM_BASE 0x08000000UL +#define CY_SRAM_SIZE 0x00040000UL +#define CY_FLASH_BASE 0x10000000UL +#define CY_FLASH_SIZE 0x00080000UL +#define CY_EM_EEPROM_BASE 0x14000000UL +#define CY_EM_EEPROM_SIZE 0x00008000UL +#define CY_SFLASH_BASE 0x16000000UL +#define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL +#define CY_EFUSE_BASE 0x402C0800UL +#define CY_EFUSE_SIZE 0x00000200UL +#define CY_CAN0MRAM_BASE 0x40530000UL +#define CY_CAN0MRAM_SIZE 0x00010000UL + +#include "system_psoc6.h" /*!< PSoC 6 System */ + +/* IP List */ +#define CY_IP_MXTTCANFD 1u +#define CY_IP_MXTTCANFD_INSTANCES 1u +#define CY_IP_MXTTCANFD_VERSION 1u +#define CY_IP_M4CPUSS 1u +#define CY_IP_M4CPUSS_INSTANCES 1u +#define CY_IP_M4CPUSS_VERSION 2u +#define CY_IP_M4CPUSS_DMAC 1u +#define CY_IP_M4CPUSS_DMAC_INSTANCES 1u +#define CY_IP_M4CPUSS_DMAC_VERSION 2u +#define CY_IP_M4CPUSS_DMA 1u +#define CY_IP_M4CPUSS_DMA_INSTANCES 2u +#define CY_IP_M4CPUSS_DMA_VERSION 2u +#define CY_IP_MXCRYPTO 1u +#define CY_IP_MXCRYPTO_INSTANCES 1u +#define CY_IP_MXCRYPTO_VERSION 2u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 2u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u +#define CY_IP_MXS40PASS 1u +#define CY_IP_MXS40PASS_INSTANCES 1u +#define CY_IP_MXS40PASS_VERSION 1u +#define CY_IP_MXS40PASS_SAR 1u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u +#define CY_IP_MXS40PASS_SAR_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 7u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 1u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u + +#include "psoc6_03_config.h" +#include "gpio_psoc6_03_100_tqfp.h" + +#define CY_DEVICE_PSOC6A512K +#define CY_SILICON_ID 0xE70F1105UL +#define CY_HF_CLK_MAX_FREQ 150000000UL + +#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL + +/******************************************************************************* +* SFLASH +*******************************************************************************/ + +#define SFLASH_BASE 0x16000000UL +#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */ + +/******************************************************************************* +* PERI +*******************************************************************************/ + +#define PERI_BASE 0x40000000UL +#define PERI ((PERI_Type*) PERI_BASE) /* 0x40000000 */ +#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40004000 */ +#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40004020 */ +#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40004040 */ +#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x40004060 */ +#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40004080 */ +#define PERI_GR5 ((PERI_GR_Type*) &PERI->GR[5]) /* 0x400040A0 */ +#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x400040C0 */ +#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40004120 */ +#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40008000 */ +#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40008400 */ +#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40008800 */ +#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40008C00 */ +#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40009000 */ +#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40009400 */ +#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40009800 */ +#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40009C00 */ +#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ +#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ +#define PERI_TR_GR10 ((PERI_TR_GR_Type*) &PERI->TR_GR[10]) /* 0x4000A800 */ +#define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ +#define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ +#define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ +#define PERI_TR_1TO1_GR3 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[3]) /* 0x4000CC00 */ +#define PERI_TR_1TO1_GR4 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[4]) /* 0x4000D000 */ +#define PERI_TR_1TO1_GR5 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[5]) /* 0x4000D400 */ +#define PERI_TR_1TO1_GR6 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[6]) /* 0x4000D800 */ +#define PERI_TR_1TO1_GR7 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[7]) /* 0x4000DC00 */ + +/******************************************************************************* +* PERI_MS +*******************************************************************************/ + +#define PERI_MS_BASE 0x40010000UL +#define PERI_MS ((PERI_MS_Type*) PERI_MS_BASE) /* 0x40010000 */ +#define PERI_MS_PPU_PR0 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[0]) /* 0x40010000 */ +#define PERI_MS_PPU_PR1 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[1]) /* 0x40010040 */ +#define PERI_MS_PPU_PR2 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[2]) /* 0x40010080 */ +#define PERI_MS_PPU_PR3 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[3]) /* 0x400100C0 */ +#define PERI_MS_PPU_PR4 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[4]) /* 0x40010100 */ +#define PERI_MS_PPU_PR5 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[5]) /* 0x40010140 */ +#define PERI_MS_PPU_PR6 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[6]) /* 0x40010180 */ +#define PERI_MS_PPU_PR7 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[7]) /* 0x400101C0 */ +#define PERI_MS_PPU_FX_PERI_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[0]) /* 0x40010800 */ +#define PERI_MS_PPU_FX_PERI_GR0_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[1]) /* 0x40010840 */ +#define PERI_MS_PPU_FX_PERI_GR1_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[2]) /* 0x40010880 */ +#define PERI_MS_PPU_FX_PERI_GR2_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[3]) /* 0x400108C0 */ +#define PERI_MS_PPU_FX_PERI_GR3_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[4]) /* 0x40010900 */ +#define PERI_MS_PPU_FX_PERI_GR4_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[5]) /* 0x40010940 */ +#define PERI_MS_PPU_FX_PERI_GR5_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[6]) /* 0x40010980 */ +#define PERI_MS_PPU_FX_PERI_GR6_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[7]) /* 0x400109C0 */ +#define PERI_MS_PPU_FX_PERI_GR9_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[8]) /* 0x40010A00 */ +#define PERI_MS_PPU_FX_PERI_TR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[9]) /* 0x40010A40 */ +#define PERI_MS_PPU_FX_CRYPTO_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[10]) /* 0x40010A80 */ +#define PERI_MS_PPU_FX_CRYPTO_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[11]) /* 0x40010AC0 */ +#define PERI_MS_PPU_FX_CRYPTO_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[12]) /* 0x40010B00 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[13]) /* 0x40010B40 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[14]) /* 0x40010B80 */ +#define PERI_MS_PPU_FX_CRYPTO_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[15]) /* 0x40010BC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[16]) /* 0x40010C00 */ +#define PERI_MS_PPU_FX_CPUSS_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[17]) /* 0x40010C40 */ +#define PERI_MS_PPU_FX_CPUSS_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[18]) /* 0x40010C80 */ +#define PERI_MS_PPU_FX_CPUSS_CM0_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[19]) /* 0x40010CC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[20]) /* 0x40010D00 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[21]) /* 0x40010D40 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT1_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[22]) /* 0x40010D80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT0_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[23]) /* 0x40010DC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT1_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[24]) /* 0x40010E00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT2_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[25]) /* 0x40010E40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT3_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[26]) /* 0x40010E80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT4_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[27]) /* 0x40010EC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT5_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[28]) /* 0x40010F00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT6_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[29]) /* 0x40010F40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT7_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[30]) /* 0x40010F80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT8_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[31]) /* 0x40010FC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT9_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[32]) /* 0x40011000 */ +#define PERI_MS_PPU_FX_IPC_STRUCT10_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[33]) /* 0x40011040 */ +#define PERI_MS_PPU_FX_IPC_STRUCT11_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[34]) /* 0x40011080 */ +#define PERI_MS_PPU_FX_IPC_STRUCT12_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[35]) /* 0x400110C0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT13_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[36]) /* 0x40011100 */ +#define PERI_MS_PPU_FX_IPC_STRUCT14_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[37]) /* 0x40011140 */ +#define PERI_MS_PPU_FX_IPC_STRUCT15_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[38]) /* 0x40011180 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT0_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[39]) /* 0x400111C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT1_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[40]) /* 0x40011200 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT2_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[41]) /* 0x40011240 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT3_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[42]) /* 0x40011280 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT4_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[43]) /* 0x400112C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT5_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[44]) /* 0x40011300 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT6_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[45]) /* 0x40011340 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT7_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[46]) /* 0x40011380 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT8_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[47]) /* 0x400113C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT9_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[48]) /* 0x40011400 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT10_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[49]) /* 0x40011440 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT11_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[50]) /* 0x40011480 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT12_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[51]) /* 0x400114C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT13_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[52]) /* 0x40011500 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT14_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[53]) /* 0x40011540 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT15_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[54]) /* 0x40011580 */ +#define PERI_MS_PPU_FX_PROT_SMPU_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[55]) /* 0x400115C0 */ +#define PERI_MS_PPU_FX_PROT_MPU0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[56]) /* 0x40011600 */ +#define PERI_MS_PPU_FX_PROT_MPU5_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[57]) /* 0x40011640 */ +#define PERI_MS_PPU_FX_PROT_MPU14_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[58]) /* 0x40011680 */ +#define PERI_MS_PPU_FX_PROT_MPU15_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[59]) /* 0x400116C0 */ +#define PERI_MS_PPU_FX_FLASHC_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[60]) /* 0x40011700 */ +#define PERI_MS_PPU_FX_FLASHC_CMD ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[61]) /* 0x40011740 */ +#define PERI_MS_PPU_FX_FLASHC_DFT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[62]) /* 0x40011780 */ +#define PERI_MS_PPU_FX_FLASHC_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[63]) /* 0x400117C0 */ +#define PERI_MS_PPU_FX_FLASHC_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[64]) /* 0x40011800 */ +#define PERI_MS_PPU_FX_FLASHC_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[65]) /* 0x40011840 */ +#define PERI_MS_PPU_FX_FLASHC_DW0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[66]) /* 0x40011880 */ +#define PERI_MS_PPU_FX_FLASHC_DW1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[67]) /* 0x400118C0 */ +#define PERI_MS_PPU_FX_FLASHC_DMAC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[68]) /* 0x40011900 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[69]) /* 0x40011940 */ +#define PERI_MS_PPU_FX_FLASHC_FM ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[70]) /* 0x40011980 */ +#define PERI_MS_PPU_FX_SRSS_MAIN1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[71]) /* 0x400119C0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[72]) /* 0x40011A00 */ +#define PERI_MS_PPU_FX_WDT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[73]) /* 0x40011A40 */ +#define PERI_MS_PPU_FX_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[74]) /* 0x40011A80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[75]) /* 0x40011AC0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[76]) /* 0x40011B00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[77]) /* 0x40011B40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[78]) /* 0x40011B80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[79]) /* 0x40011BC0 */ +#define PERI_MS_PPU_FX_BACKUP_BACKUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[80]) /* 0x40011C00 */ +#define PERI_MS_PPU_FX_DW0_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[81]) /* 0x40011C40 */ +#define PERI_MS_PPU_FX_DW1_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[82]) /* 0x40011C80 */ +#define PERI_MS_PPU_FX_DW0_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[83]) /* 0x40011CC0 */ +#define PERI_MS_PPU_FX_DW1_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[84]) /* 0x40011D00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[85]) /* 0x40011D40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[86]) /* 0x40011D80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[87]) /* 0x40011DC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[88]) /* 0x40011E00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[89]) /* 0x40011E40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[90]) /* 0x40011E80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[91]) /* 0x40011EC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[92]) /* 0x40011F00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[93]) /* 0x40011F40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[94]) /* 0x40011F80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[95]) /* 0x40011FC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[96]) /* 0x40012000 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[97]) /* 0x40012040 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[98]) /* 0x40012080 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[99]) /* 0x400120C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[100]) /* 0x40012100 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[101]) /* 0x40012140 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[102]) /* 0x40012180 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[103]) /* 0x400121C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[104]) /* 0x40012200 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[105]) /* 0x40012240 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[106]) /* 0x40012280 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[107]) /* 0x400122C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[108]) /* 0x40012300 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[109]) /* 0x40012340 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[110]) /* 0x40012380 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[111]) /* 0x400123C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[112]) /* 0x40012400 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[113]) /* 0x40012440 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[114]) /* 0x40012480 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[115]) /* 0x400124C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[116]) /* 0x40012500 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[117]) /* 0x40012540 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[118]) /* 0x40012580 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[119]) /* 0x400125C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[120]) /* 0x40012600 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[121]) /* 0x40012640 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[122]) /* 0x40012680 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[123]) /* 0x400126C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[124]) /* 0x40012700 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[125]) /* 0x40012740 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[126]) /* 0x40012780 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[127]) /* 0x400127C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[128]) /* 0x40012800 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[129]) /* 0x40012840 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[130]) /* 0x40012880 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[131]) /* 0x400128C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[132]) /* 0x40012900 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[133]) /* 0x40012940 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[134]) /* 0x40012980 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[135]) /* 0x400129C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[136]) /* 0x40012A00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[137]) /* 0x40012A40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[138]) /* 0x40012A80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[139]) /* 0x40012AC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[140]) /* 0x40012B00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[141]) /* 0x40012B40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[142]) /* 0x40012B80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT29_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[143]) /* 0x40012BC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT30_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[144]) /* 0x40012C00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT31_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[145]) /* 0x40012C40 */ +#define PERI_MS_PPU_FX_DMAC_TOP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[146]) /* 0x40012C80 */ +#define PERI_MS_PPU_FX_DMAC_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[147]) /* 0x40012CC0 */ +#define PERI_MS_PPU_FX_DMAC_CH1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[148]) /* 0x40012D00 */ +#define PERI_MS_PPU_FX_EFUSE_CTL ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[149]) /* 0x40012D40 */ +#define PERI_MS_PPU_FX_EFUSE_DATA ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[150]) /* 0x40012D80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[151]) /* 0x40012DC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[152]) /* 0x40012E00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[153]) /* 0x40012E40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[154]) /* 0x40012E80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[155]) /* 0x40012EC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[156]) /* 0x40012F00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[157]) /* 0x40012F40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[158]) /* 0x40012F80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[159]) /* 0x40012FC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[160]) /* 0x40013000 */ +#define PERI_MS_PPU_FX_HSIOM_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[161]) /* 0x40013040 */ +#define PERI_MS_PPU_FX_HSIOM_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[162]) /* 0x40013080 */ +#define PERI_MS_PPU_FX_HSIOM_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[163]) /* 0x400130C0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[164]) /* 0x40013100 */ +#define PERI_MS_PPU_FX_HSIOM_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[165]) /* 0x40013140 */ +#define PERI_MS_PPU_FX_HSIOM_AMUX ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[166]) /* 0x40013180 */ +#define PERI_MS_PPU_FX_HSIOM_MON ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[167]) /* 0x400131C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[168]) /* 0x40013200 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[169]) /* 0x40013240 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[170]) /* 0x40013280 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[171]) /* 0x400132C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[172]) /* 0x40013300 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[173]) /* 0x40013340 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[174]) /* 0x40013380 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[175]) /* 0x400133C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[176]) /* 0x40013400 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[177]) /* 0x40013440 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[178]) /* 0x40013480 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[179]) /* 0x400134C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[180]) /* 0x40013500 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[181]) /* 0x40013540 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[182]) /* 0x40013580 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[183]) /* 0x400135C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[184]) /* 0x40013600 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[185]) /* 0x40013640 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[186]) /* 0x40013680 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[187]) /* 0x400136C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[188]) /* 0x40013700 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[189]) /* 0x40013740 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[190]) /* 0x40013780 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[191]) /* 0x400137C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[192]) /* 0x40013800 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[193]) /* 0x40013840 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[194]) /* 0x40013880 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[195]) /* 0x400138C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[196]) /* 0x40013900 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[197]) /* 0x40013940 */ +#define PERI_MS_PPU_FX_GPIO_GPIO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[198]) /* 0x40013980 */ +#define PERI_MS_PPU_FX_GPIO_TEST ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[199]) /* 0x400139C0 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[200]) /* 0x40013A00 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[201]) /* 0x40013A40 */ +#define PERI_MS_PPU_FX_LPCOMP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[202]) /* 0x40013A80 */ +#define PERI_MS_PPU_FX_CSD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[203]) /* 0x40013AC0 */ +#define PERI_MS_PPU_FX_TCPWM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[204]) /* 0x40013B00 */ +#define PERI_MS_PPU_FX_TCPWM1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[205]) /* 0x40013B40 */ +#define PERI_MS_PPU_FX_LCD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[206]) /* 0x40013B80 */ +#define PERI_MS_PPU_FX_USBFS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[207]) /* 0x40013BC0 */ +#define PERI_MS_PPU_FX_SMIF0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[208]) /* 0x40013C00 */ +#define PERI_MS_PPU_FX_SDHC0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[209]) /* 0x40013C40 */ +#define PERI_MS_PPU_FX_CANFD0_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[210]) /* 0x40013C80 */ +#define PERI_MS_PPU_FX_CANFD0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[211]) /* 0x40013CC0 */ +#define PERI_MS_PPU_FX_CANFD0_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[212]) /* 0x40013D00 */ +#define PERI_MS_PPU_FX_SCB0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[213]) /* 0x40013D40 */ +#define PERI_MS_PPU_FX_SCB1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[214]) /* 0x40013D80 */ +#define PERI_MS_PPU_FX_SCB2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[215]) /* 0x40013DC0 */ +#define PERI_MS_PPU_FX_SCB3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[216]) /* 0x40013E00 */ +#define PERI_MS_PPU_FX_SCB4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[217]) /* 0x40013E40 */ +#define PERI_MS_PPU_FX_SCB5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[218]) /* 0x40013E80 */ +#define PERI_MS_PPU_FX_SCB6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[219]) /* 0x40013EC0 */ + +/******************************************************************************* +* CRYPTO +*******************************************************************************/ + +#define CRYPTO_BASE 0x40100000UL +#define CRYPTO ((CRYPTO_Type*) CRYPTO_BASE) /* 0x40100000 */ + +/******************************************************************************* +* CPUSS +*******************************************************************************/ + +#define CPUSS_BASE 0x40200000UL +#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40200000 */ + +/******************************************************************************* +* FAULT +*******************************************************************************/ + +#define FAULT_BASE 0x40210000UL +#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40210000 */ +#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40210000 */ +#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40210100 */ + +/******************************************************************************* +* IPC +*******************************************************************************/ + +#define IPC_BASE 0x40220000UL +#define IPC ((IPC_Type*) IPC_BASE) /* 0x40220000 */ +#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40220000 */ +#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40220020 */ +#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40220040 */ +#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40220060 */ +#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40220080 */ +#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402200A0 */ +#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402200C0 */ +#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402200E0 */ +#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40220100 */ +#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40220120 */ +#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40220140 */ +#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40220160 */ +#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40220180 */ +#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402201A0 */ +#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402201C0 */ +#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402201E0 */ +#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40221000 */ +#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40221020 */ +#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40221040 */ +#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40221060 */ +#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40221080 */ +#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402210A0 */ +#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402210C0 */ +#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402210E0 */ +#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40221100 */ +#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40221120 */ +#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40221140 */ +#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40221160 */ +#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40221180 */ +#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402211A0 */ +#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402211C0 */ +#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402211E0 */ + +/******************************************************************************* +* PROT +*******************************************************************************/ + +#define PROT_BASE 0x40230000UL +#define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ +#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ +#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ +#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402320C0 */ +#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40232100 */ +#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40232140 */ +#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40232180 */ +#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402321C0 */ +#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40232200 */ +#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40232240 */ +#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40232280 */ +#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402322C0 */ +#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40232300 */ +#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ +#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ +#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ +#define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ +#define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ +#define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ +#define PROT_MPU5_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[3]) /* 0x40235660 */ +#define PROT_MPU5_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[4]) /* 0x40235680 */ +#define PROT_MPU5_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[5]) /* 0x402356A0 */ +#define PROT_MPU5_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[6]) /* 0x402356C0 */ +#define PROT_MPU5_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[7]) /* 0x402356E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ + +/******************************************************************************* +* FLASHC +*******************************************************************************/ + +#define FLASHC_BASE 0x40240000UL +#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40240000 */ +#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4024F000 */ + +/******************************************************************************* +* SRSS +*******************************************************************************/ + +#define SRSS_BASE 0x40260000UL +#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ +#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */ +#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */ + +/******************************************************************************* +* BACKUP +*******************************************************************************/ + +#define BACKUP_BASE 0x40270000UL +#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ + +/******************************************************************************* +* DW +*******************************************************************************/ + +#define DW0_BASE 0x40280000UL +#define DW1_BASE 0x40290000UL +#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ +#define DW1 ((DW_Type*) DW1_BASE) /* 0x40290000 */ +#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40288000 */ +#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40288040 */ +#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40288080 */ +#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x402880C0 */ +#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40288100 */ +#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x40288140 */ +#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x40288180 */ +#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402881C0 */ +#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40288200 */ +#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40288240 */ +#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40288280 */ +#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x402882C0 */ +#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40288300 */ +#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x40288340 */ +#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x40288380 */ +#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402883C0 */ +#define DW0_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[16]) /* 0x40288400 */ +#define DW0_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[17]) /* 0x40288440 */ +#define DW0_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[18]) /* 0x40288480 */ +#define DW0_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[19]) /* 0x402884C0 */ +#define DW0_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[20]) /* 0x40288500 */ +#define DW0_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[21]) /* 0x40288540 */ +#define DW0_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[22]) /* 0x40288580 */ +#define DW0_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[23]) /* 0x402885C0 */ +#define DW0_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[24]) /* 0x40288600 */ +#define DW0_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[25]) /* 0x40288640 */ +#define DW0_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[26]) /* 0x40288680 */ +#define DW0_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[27]) /* 0x402886C0 */ +#define DW0_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[28]) /* 0x40288700 */ +#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40298000 */ +#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40298040 */ +#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40298080 */ +#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x402980C0 */ +#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40298100 */ +#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x40298140 */ +#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x40298180 */ +#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402981C0 */ +#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40298200 */ +#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40298240 */ +#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40298280 */ +#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x402982C0 */ +#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40298300 */ +#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x40298340 */ +#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x40298380 */ +#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402983C0 */ +#define DW1_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[16]) /* 0x40298400 */ +#define DW1_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[17]) /* 0x40298440 */ +#define DW1_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[18]) /* 0x40298480 */ +#define DW1_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[19]) /* 0x402984C0 */ +#define DW1_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[20]) /* 0x40298500 */ +#define DW1_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[21]) /* 0x40298540 */ +#define DW1_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[22]) /* 0x40298580 */ +#define DW1_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[23]) /* 0x402985C0 */ +#define DW1_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[24]) /* 0x40298600 */ +#define DW1_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[25]) /* 0x40298640 */ +#define DW1_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[26]) /* 0x40298680 */ +#define DW1_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[27]) /* 0x402986C0 */ +#define DW1_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[28]) /* 0x40298700 */ +#define DW1_CH_STRUCT29 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[29]) /* 0x40298740 */ +#define DW1_CH_STRUCT30 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[30]) /* 0x40298780 */ +#define DW1_CH_STRUCT31 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[31]) /* 0x402987C0 */ + +/******************************************************************************* +* DMAC +*******************************************************************************/ + +#define DMAC_BASE 0x402A0000UL +#define DMAC ((DMAC_Type*) DMAC_BASE) /* 0x402A0000 */ +#define DMAC_CH0 ((DMAC_CH_Type*) &DMAC->CH[0]) /* 0x402A1000 */ +#define DMAC_CH1 ((DMAC_CH_Type*) &DMAC->CH[1]) /* 0x402A1100 */ + +/******************************************************************************* +* EFUSE +*******************************************************************************/ + +#define EFUSE_BASE 0x402C0000UL +#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ + +/******************************************************************************* +* HSIOM +*******************************************************************************/ + +#define HSIOM_BASE 0x40300000UL +#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40300000 */ +#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40300000 */ +#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40300010 */ +#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40300020 */ +#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40300030 */ +#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40300040 */ +#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40300050 */ +#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40300060 */ +#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40300070 */ +#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40300080 */ +#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40300090 */ +#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403000A0 */ +#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403000B0 */ +#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403000C0 */ +#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403000D0 */ +#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403000E0 */ + +/******************************************************************************* +* GPIO +*******************************************************************************/ + +#define GPIO_BASE 0x40310000UL +#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40310000 */ +#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40310000 */ +#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40310080 */ +#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40310100 */ +#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40310180 */ +#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40310200 */ +#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40310280 */ +#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40310300 */ +#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40310380 */ +#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40310400 */ +#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40310480 */ +#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40310500 */ +#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40310580 */ +#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40310600 */ +#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40310680 */ +#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40310700 */ + +/******************************************************************************* +* SMARTIO +*******************************************************************************/ + +#define SMARTIO_BASE 0x40320000UL +#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40320000 */ +#define SMARTIO_PRT8 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[8]) /* 0x40320800 */ +#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40320900 */ + +/******************************************************************************* +* LPCOMP +*******************************************************************************/ + +#define LPCOMP_BASE 0x40350000UL +#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */ + +/******************************************************************************* +* CSD +*******************************************************************************/ + +#define CSD0_BASE 0x40360000UL +#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */ + +/******************************************************************************* +* TCPWM +*******************************************************************************/ + +#define TCPWM0_BASE 0x40380000UL +#define TCPWM1_BASE 0x40390000UL +#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM1 ((TCPWM_Type*) TCPWM1_BASE) /* 0x40390000 */ +#define TCPWM0_CNT0 ((TCPWM_CNT_Type*) &TCPWM0->CNT[0]) /* 0x40380100 */ +#define TCPWM0_CNT1 ((TCPWM_CNT_Type*) &TCPWM0->CNT[1]) /* 0x40380140 */ +#define TCPWM0_CNT2 ((TCPWM_CNT_Type*) &TCPWM0->CNT[2]) /* 0x40380180 */ +#define TCPWM0_CNT3 ((TCPWM_CNT_Type*) &TCPWM0->CNT[3]) /* 0x403801C0 */ +#define TCPWM1_CNT0 ((TCPWM_CNT_Type*) &TCPWM1->CNT[0]) /* 0x40390100 */ +#define TCPWM1_CNT1 ((TCPWM_CNT_Type*) &TCPWM1->CNT[1]) /* 0x40390140 */ +#define TCPWM1_CNT2 ((TCPWM_CNT_Type*) &TCPWM1->CNT[2]) /* 0x40390180 */ +#define TCPWM1_CNT3 ((TCPWM_CNT_Type*) &TCPWM1->CNT[3]) /* 0x403901C0 */ +#define TCPWM1_CNT4 ((TCPWM_CNT_Type*) &TCPWM1->CNT[4]) /* 0x40390200 */ +#define TCPWM1_CNT5 ((TCPWM_CNT_Type*) &TCPWM1->CNT[5]) /* 0x40390240 */ +#define TCPWM1_CNT6 ((TCPWM_CNT_Type*) &TCPWM1->CNT[6]) /* 0x40390280 */ +#define TCPWM1_CNT7 ((TCPWM_CNT_Type*) &TCPWM1->CNT[7]) /* 0x403902C0 */ + +/******************************************************************************* +* LCD +*******************************************************************************/ + +#define LCD0_BASE 0x403B0000UL +#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ + +/******************************************************************************* +* USBFS +*******************************************************************************/ + +#define USBFS0_BASE 0x403F0000UL +#define USBFS0 ((USBFS_Type*) USBFS0_BASE) /* 0x403F0000 */ +#define USBFS0_USBDEV ((USBFS_USBDEV_Type*) &USBFS0->USBDEV) /* 0x403F0000 */ +#define USBFS0_USBLPM ((USBFS_USBLPM_Type*) &USBFS0->USBLPM) /* 0x403F2000 */ +#define USBFS0_USBHOST ((USBFS_USBHOST_Type*) &USBFS0->USBHOST) /* 0x403F4000 */ + +/******************************************************************************* +* SMIF +*******************************************************************************/ + +#define SMIF0_BASE 0x40420000UL +#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ +#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ +#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ +#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ + +/******************************************************************************* +* SDHC +*******************************************************************************/ + +#define SDHC0_BASE 0x40460000UL +#define SDHC0 ((SDHC_Type*) SDHC0_BASE) /* 0x40460000 */ +#define SDHC0_WRAP ((SDHC_WRAP_Type*) &SDHC0->WRAP) /* 0x40460000 */ +#define SDHC0_CORE ((SDHC_CORE_Type*) &SDHC0->CORE) /* 0x40461000 */ + +/******************************************************************************* +* CANFD +*******************************************************************************/ + +#define CANFD0_BASE 0x40520000UL +#define CANFD0 ((CANFD_Type*) CANFD0_BASE) /* 0x40520000 */ +#define CANFD0_CH0 ((CANFD_CH_Type*) &CANFD0->CH[0]) /* 0x40520000 */ +#define CANFD0_CH0_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[0].M_TTCAN) /* 0x40520000 */ + +/******************************************************************************* +* SCB +*******************************************************************************/ + +#define SCB0_BASE 0x40600000UL +#define SCB1_BASE 0x40610000UL +#define SCB2_BASE 0x40620000UL +#define SCB3_BASE 0x40630000UL +#define SCB4_BASE 0x40640000UL +#define SCB5_BASE 0x40650000UL +#define SCB6_BASE 0x40660000UL +#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40600000 */ +#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40610000 */ +#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40620000 */ +#define SCB3 ((CySCB_Type*) SCB3_BASE) /* 0x40630000 */ +#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40640000 */ +#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40650000 */ +#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40660000 */ + +/******************************************************************************* +* SAR +*******************************************************************************/ + +#define SAR_BASE 0x409D0000UL +#define SAR ((SAR_Type*) SAR_BASE) /* 0x409D0000 */ + +/******************************************************************************* +* PASS +*******************************************************************************/ + +#define PASS_BASE 0x409F0000UL +#define PASS ((PASS_Type*) PASS_BASE) /* 0x409F0000 */ +#define PASS_AREF ((PASS_AREF_Type*) &PASS->AREF) /* 0x409F0E00 */ + +/** \} CY8C6145AZI-S3F72 */ + +#endif /* _CY8C6145AZI_S3F72_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6145fni_s3f11.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6145fni_s3f11.h new file mode 100644 index 0000000000..bc3400320e --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6145fni_s3f11.h @@ -0,0 +1,970 @@ +/***************************************************************************//** +* \file cy8c6145fni_s3f11.h +* +* \brief +* CY8C6145FNI-S3F11 device header +* +* \note +* Generator version: 1.6.0.225 +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CY8C6145FNI_S3F11_H_ +#define _CY8C6145FNI_S3F11_H_ + +/** +* \addtogroup group_device CY8C6145FNI-S3F11 +* \{ +*/ + +/** +* \addtogroup Configuration_of_CMSIS +* \{ +*/ + +/******************************************************************************* +* Interrupt Number Definition +*******************************************************************************/ + +typedef enum { + /* ARM Cortex-M4 Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C6145FNI-S3F11 Peripheral Interrupt Numbers */ + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_6_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #6 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + canfd_0_interrupt0_IRQn = 168, /*!< 168 [Active] Can #0, Consolidated interrupt #0 */ + canfd_0_interrupts0_0_IRQn = 169, /*!< 169 [Active] CAN #0, Interrupt #0, Channel #0 */ + canfd_0_interrupts1_0_IRQn = 170, /*!< 170 [Active] CAN #0, Interrupt #1, Channel #0 */ + cpuss_interrupts_dw1_29_IRQn = 171, /*!< 171 [Active] CPUSS DataWire #1, Channel #29 */ + cpuss_interrupts_dw1_30_IRQn = 172, /*!< 172 [Active] CPUSS DataWire #1, Channel #30 */ + cpuss_interrupts_dw1_31_IRQn = 173, /*!< 173 [Active] CPUSS DataWire #1, Channel #31 */ + unconnected_IRQn = 240 /*!< 240 Unconnected */ +} IRQn_Type; + + +/******************************************************************************* +* Processor and Core Peripheral Section +*******************************************************************************/ + +/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __CM0P_PRESENT 0 /*!< CM0P present or not */ +#define __DTCM_PRESENT 0 /*!< DTCM present or not */ +#define __ICACHE_PRESENT 0 /*!< ICACHE present or not */ +#define __DCACHE_PRESENT 0 /*!< DCACHE present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + + +/* Memory Blocks */ +#define CY_ROM_BASE 0x00000000UL +#define CY_ROM_SIZE 0x00010000UL +#define CY_SRAM_BASE 0x08000000UL +#define CY_SRAM_SIZE 0x00040000UL +#define CY_FLASH_BASE 0x10000000UL +#define CY_FLASH_SIZE 0x00080000UL +#define CY_EM_EEPROM_BASE 0x14000000UL +#define CY_EM_EEPROM_SIZE 0x00008000UL +#define CY_SFLASH_BASE 0x16000000UL +#define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL +#define CY_EFUSE_BASE 0x402C0800UL +#define CY_EFUSE_SIZE 0x00000200UL +#define CY_CAN0MRAM_BASE 0x40530000UL +#define CY_CAN0MRAM_SIZE 0x00010000UL + +#include "system_psoc6.h" /*!< PSoC 6 System */ + +/* IP List */ +#define CY_IP_MXTTCANFD 1u +#define CY_IP_MXTTCANFD_INSTANCES 1u +#define CY_IP_MXTTCANFD_VERSION 1u +#define CY_IP_M4CPUSS 1u +#define CY_IP_M4CPUSS_INSTANCES 1u +#define CY_IP_M4CPUSS_VERSION 2u +#define CY_IP_M4CPUSS_DMAC 1u +#define CY_IP_M4CPUSS_DMAC_INSTANCES 1u +#define CY_IP_M4CPUSS_DMAC_VERSION 2u +#define CY_IP_M4CPUSS_DMA 1u +#define CY_IP_M4CPUSS_DMA_INSTANCES 2u +#define CY_IP_M4CPUSS_DMA_VERSION 2u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 2u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u +#define CY_IP_MXS40PASS 1u +#define CY_IP_MXS40PASS_INSTANCES 1u +#define CY_IP_MXS40PASS_VERSION 1u +#define CY_IP_MXS40PASS_SAR 1u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u +#define CY_IP_MXS40PASS_SAR_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 7u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 1u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u + +#include "psoc6_03_config.h" +#include "gpio_psoc6_03_49_wlcsp.h" + +#define CY_DEVICE_PSOC6A512K +#define CY_SILICON_ID 0xE7191105UL +#define CY_HF_CLK_MAX_FREQ 150000000UL + +#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL + +/******************************************************************************* +* SFLASH +*******************************************************************************/ + +#define SFLASH_BASE 0x16000000UL +#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */ + +/******************************************************************************* +* PERI +*******************************************************************************/ + +#define PERI_BASE 0x40000000UL +#define PERI ((PERI_Type*) PERI_BASE) /* 0x40000000 */ +#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40004000 */ +#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40004020 */ +#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40004040 */ +#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x40004060 */ +#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40004080 */ +#define PERI_GR5 ((PERI_GR_Type*) &PERI->GR[5]) /* 0x400040A0 */ +#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x400040C0 */ +#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40004120 */ +#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40008000 */ +#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40008400 */ +#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40008800 */ +#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40008C00 */ +#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40009000 */ +#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40009400 */ +#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40009800 */ +#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40009C00 */ +#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ +#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ +#define PERI_TR_GR10 ((PERI_TR_GR_Type*) &PERI->TR_GR[10]) /* 0x4000A800 */ +#define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ +#define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ +#define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ +#define PERI_TR_1TO1_GR3 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[3]) /* 0x4000CC00 */ +#define PERI_TR_1TO1_GR4 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[4]) /* 0x4000D000 */ +#define PERI_TR_1TO1_GR5 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[5]) /* 0x4000D400 */ +#define PERI_TR_1TO1_GR6 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[6]) /* 0x4000D800 */ +#define PERI_TR_1TO1_GR7 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[7]) /* 0x4000DC00 */ + +/******************************************************************************* +* PERI_MS +*******************************************************************************/ + +#define PERI_MS_BASE 0x40010000UL +#define PERI_MS ((PERI_MS_Type*) PERI_MS_BASE) /* 0x40010000 */ +#define PERI_MS_PPU_PR0 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[0]) /* 0x40010000 */ +#define PERI_MS_PPU_PR1 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[1]) /* 0x40010040 */ +#define PERI_MS_PPU_PR2 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[2]) /* 0x40010080 */ +#define PERI_MS_PPU_PR3 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[3]) /* 0x400100C0 */ +#define PERI_MS_PPU_PR4 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[4]) /* 0x40010100 */ +#define PERI_MS_PPU_PR5 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[5]) /* 0x40010140 */ +#define PERI_MS_PPU_PR6 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[6]) /* 0x40010180 */ +#define PERI_MS_PPU_PR7 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[7]) /* 0x400101C0 */ +#define PERI_MS_PPU_FX_PERI_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[0]) /* 0x40010800 */ +#define PERI_MS_PPU_FX_PERI_GR0_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[1]) /* 0x40010840 */ +#define PERI_MS_PPU_FX_PERI_GR1_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[2]) /* 0x40010880 */ +#define PERI_MS_PPU_FX_PERI_GR2_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[3]) /* 0x400108C0 */ +#define PERI_MS_PPU_FX_PERI_GR3_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[4]) /* 0x40010900 */ +#define PERI_MS_PPU_FX_PERI_GR4_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[5]) /* 0x40010940 */ +#define PERI_MS_PPU_FX_PERI_GR5_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[6]) /* 0x40010980 */ +#define PERI_MS_PPU_FX_PERI_GR6_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[7]) /* 0x400109C0 */ +#define PERI_MS_PPU_FX_PERI_GR9_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[8]) /* 0x40010A00 */ +#define PERI_MS_PPU_FX_PERI_TR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[9]) /* 0x40010A40 */ +#define PERI_MS_PPU_FX_CRYPTO_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[10]) /* 0x40010A80 */ +#define PERI_MS_PPU_FX_CRYPTO_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[11]) /* 0x40010AC0 */ +#define PERI_MS_PPU_FX_CRYPTO_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[12]) /* 0x40010B00 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[13]) /* 0x40010B40 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[14]) /* 0x40010B80 */ +#define PERI_MS_PPU_FX_CRYPTO_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[15]) /* 0x40010BC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[16]) /* 0x40010C00 */ +#define PERI_MS_PPU_FX_CPUSS_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[17]) /* 0x40010C40 */ +#define PERI_MS_PPU_FX_CPUSS_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[18]) /* 0x40010C80 */ +#define PERI_MS_PPU_FX_CPUSS_CM0_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[19]) /* 0x40010CC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[20]) /* 0x40010D00 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[21]) /* 0x40010D40 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT1_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[22]) /* 0x40010D80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT0_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[23]) /* 0x40010DC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT1_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[24]) /* 0x40010E00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT2_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[25]) /* 0x40010E40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT3_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[26]) /* 0x40010E80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT4_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[27]) /* 0x40010EC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT5_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[28]) /* 0x40010F00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT6_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[29]) /* 0x40010F40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT7_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[30]) /* 0x40010F80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT8_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[31]) /* 0x40010FC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT9_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[32]) /* 0x40011000 */ +#define PERI_MS_PPU_FX_IPC_STRUCT10_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[33]) /* 0x40011040 */ +#define PERI_MS_PPU_FX_IPC_STRUCT11_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[34]) /* 0x40011080 */ +#define PERI_MS_PPU_FX_IPC_STRUCT12_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[35]) /* 0x400110C0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT13_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[36]) /* 0x40011100 */ +#define PERI_MS_PPU_FX_IPC_STRUCT14_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[37]) /* 0x40011140 */ +#define PERI_MS_PPU_FX_IPC_STRUCT15_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[38]) /* 0x40011180 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT0_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[39]) /* 0x400111C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT1_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[40]) /* 0x40011200 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT2_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[41]) /* 0x40011240 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT3_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[42]) /* 0x40011280 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT4_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[43]) /* 0x400112C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT5_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[44]) /* 0x40011300 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT6_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[45]) /* 0x40011340 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT7_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[46]) /* 0x40011380 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT8_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[47]) /* 0x400113C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT9_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[48]) /* 0x40011400 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT10_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[49]) /* 0x40011440 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT11_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[50]) /* 0x40011480 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT12_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[51]) /* 0x400114C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT13_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[52]) /* 0x40011500 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT14_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[53]) /* 0x40011540 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT15_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[54]) /* 0x40011580 */ +#define PERI_MS_PPU_FX_PROT_SMPU_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[55]) /* 0x400115C0 */ +#define PERI_MS_PPU_FX_PROT_MPU0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[56]) /* 0x40011600 */ +#define PERI_MS_PPU_FX_PROT_MPU5_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[57]) /* 0x40011640 */ +#define PERI_MS_PPU_FX_PROT_MPU14_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[58]) /* 0x40011680 */ +#define PERI_MS_PPU_FX_PROT_MPU15_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[59]) /* 0x400116C0 */ +#define PERI_MS_PPU_FX_FLASHC_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[60]) /* 0x40011700 */ +#define PERI_MS_PPU_FX_FLASHC_CMD ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[61]) /* 0x40011740 */ +#define PERI_MS_PPU_FX_FLASHC_DFT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[62]) /* 0x40011780 */ +#define PERI_MS_PPU_FX_FLASHC_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[63]) /* 0x400117C0 */ +#define PERI_MS_PPU_FX_FLASHC_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[64]) /* 0x40011800 */ +#define PERI_MS_PPU_FX_FLASHC_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[65]) /* 0x40011840 */ +#define PERI_MS_PPU_FX_FLASHC_DW0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[66]) /* 0x40011880 */ +#define PERI_MS_PPU_FX_FLASHC_DW1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[67]) /* 0x400118C0 */ +#define PERI_MS_PPU_FX_FLASHC_DMAC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[68]) /* 0x40011900 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[69]) /* 0x40011940 */ +#define PERI_MS_PPU_FX_FLASHC_FM ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[70]) /* 0x40011980 */ +#define PERI_MS_PPU_FX_SRSS_MAIN1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[71]) /* 0x400119C0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[72]) /* 0x40011A00 */ +#define PERI_MS_PPU_FX_WDT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[73]) /* 0x40011A40 */ +#define PERI_MS_PPU_FX_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[74]) /* 0x40011A80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[75]) /* 0x40011AC0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[76]) /* 0x40011B00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[77]) /* 0x40011B40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[78]) /* 0x40011B80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[79]) /* 0x40011BC0 */ +#define PERI_MS_PPU_FX_BACKUP_BACKUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[80]) /* 0x40011C00 */ +#define PERI_MS_PPU_FX_DW0_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[81]) /* 0x40011C40 */ +#define PERI_MS_PPU_FX_DW1_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[82]) /* 0x40011C80 */ +#define PERI_MS_PPU_FX_DW0_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[83]) /* 0x40011CC0 */ +#define PERI_MS_PPU_FX_DW1_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[84]) /* 0x40011D00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[85]) /* 0x40011D40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[86]) /* 0x40011D80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[87]) /* 0x40011DC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[88]) /* 0x40011E00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[89]) /* 0x40011E40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[90]) /* 0x40011E80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[91]) /* 0x40011EC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[92]) /* 0x40011F00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[93]) /* 0x40011F40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[94]) /* 0x40011F80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[95]) /* 0x40011FC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[96]) /* 0x40012000 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[97]) /* 0x40012040 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[98]) /* 0x40012080 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[99]) /* 0x400120C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[100]) /* 0x40012100 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[101]) /* 0x40012140 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[102]) /* 0x40012180 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[103]) /* 0x400121C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[104]) /* 0x40012200 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[105]) /* 0x40012240 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[106]) /* 0x40012280 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[107]) /* 0x400122C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[108]) /* 0x40012300 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[109]) /* 0x40012340 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[110]) /* 0x40012380 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[111]) /* 0x400123C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[112]) /* 0x40012400 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[113]) /* 0x40012440 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[114]) /* 0x40012480 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[115]) /* 0x400124C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[116]) /* 0x40012500 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[117]) /* 0x40012540 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[118]) /* 0x40012580 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[119]) /* 0x400125C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[120]) /* 0x40012600 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[121]) /* 0x40012640 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[122]) /* 0x40012680 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[123]) /* 0x400126C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[124]) /* 0x40012700 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[125]) /* 0x40012740 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[126]) /* 0x40012780 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[127]) /* 0x400127C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[128]) /* 0x40012800 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[129]) /* 0x40012840 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[130]) /* 0x40012880 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[131]) /* 0x400128C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[132]) /* 0x40012900 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[133]) /* 0x40012940 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[134]) /* 0x40012980 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[135]) /* 0x400129C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[136]) /* 0x40012A00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[137]) /* 0x40012A40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[138]) /* 0x40012A80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[139]) /* 0x40012AC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[140]) /* 0x40012B00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[141]) /* 0x40012B40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[142]) /* 0x40012B80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT29_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[143]) /* 0x40012BC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT30_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[144]) /* 0x40012C00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT31_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[145]) /* 0x40012C40 */ +#define PERI_MS_PPU_FX_DMAC_TOP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[146]) /* 0x40012C80 */ +#define PERI_MS_PPU_FX_DMAC_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[147]) /* 0x40012CC0 */ +#define PERI_MS_PPU_FX_DMAC_CH1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[148]) /* 0x40012D00 */ +#define PERI_MS_PPU_FX_EFUSE_CTL ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[149]) /* 0x40012D40 */ +#define PERI_MS_PPU_FX_EFUSE_DATA ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[150]) /* 0x40012D80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[151]) /* 0x40012DC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[152]) /* 0x40012E00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[153]) /* 0x40012E40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[154]) /* 0x40012E80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[155]) /* 0x40012EC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[156]) /* 0x40012F00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[157]) /* 0x40012F40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[158]) /* 0x40012F80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[159]) /* 0x40012FC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[160]) /* 0x40013000 */ +#define PERI_MS_PPU_FX_HSIOM_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[161]) /* 0x40013040 */ +#define PERI_MS_PPU_FX_HSIOM_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[162]) /* 0x40013080 */ +#define PERI_MS_PPU_FX_HSIOM_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[163]) /* 0x400130C0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[164]) /* 0x40013100 */ +#define PERI_MS_PPU_FX_HSIOM_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[165]) /* 0x40013140 */ +#define PERI_MS_PPU_FX_HSIOM_AMUX ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[166]) /* 0x40013180 */ +#define PERI_MS_PPU_FX_HSIOM_MON ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[167]) /* 0x400131C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[168]) /* 0x40013200 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[169]) /* 0x40013240 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[170]) /* 0x40013280 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[171]) /* 0x400132C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[172]) /* 0x40013300 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[173]) /* 0x40013340 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[174]) /* 0x40013380 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[175]) /* 0x400133C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[176]) /* 0x40013400 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[177]) /* 0x40013440 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[178]) /* 0x40013480 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[179]) /* 0x400134C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[180]) /* 0x40013500 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[181]) /* 0x40013540 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[182]) /* 0x40013580 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[183]) /* 0x400135C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[184]) /* 0x40013600 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[185]) /* 0x40013640 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[186]) /* 0x40013680 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[187]) /* 0x400136C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[188]) /* 0x40013700 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[189]) /* 0x40013740 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[190]) /* 0x40013780 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[191]) /* 0x400137C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[192]) /* 0x40013800 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[193]) /* 0x40013840 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[194]) /* 0x40013880 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[195]) /* 0x400138C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[196]) /* 0x40013900 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[197]) /* 0x40013940 */ +#define PERI_MS_PPU_FX_GPIO_GPIO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[198]) /* 0x40013980 */ +#define PERI_MS_PPU_FX_GPIO_TEST ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[199]) /* 0x400139C0 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[200]) /* 0x40013A00 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[201]) /* 0x40013A40 */ +#define PERI_MS_PPU_FX_LPCOMP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[202]) /* 0x40013A80 */ +#define PERI_MS_PPU_FX_CSD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[203]) /* 0x40013AC0 */ +#define PERI_MS_PPU_FX_TCPWM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[204]) /* 0x40013B00 */ +#define PERI_MS_PPU_FX_TCPWM1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[205]) /* 0x40013B40 */ +#define PERI_MS_PPU_FX_LCD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[206]) /* 0x40013B80 */ +#define PERI_MS_PPU_FX_USBFS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[207]) /* 0x40013BC0 */ +#define PERI_MS_PPU_FX_SMIF0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[208]) /* 0x40013C00 */ +#define PERI_MS_PPU_FX_SDHC0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[209]) /* 0x40013C40 */ +#define PERI_MS_PPU_FX_CANFD0_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[210]) /* 0x40013C80 */ +#define PERI_MS_PPU_FX_CANFD0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[211]) /* 0x40013CC0 */ +#define PERI_MS_PPU_FX_CANFD0_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[212]) /* 0x40013D00 */ +#define PERI_MS_PPU_FX_SCB0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[213]) /* 0x40013D40 */ +#define PERI_MS_PPU_FX_SCB1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[214]) /* 0x40013D80 */ +#define PERI_MS_PPU_FX_SCB2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[215]) /* 0x40013DC0 */ +#define PERI_MS_PPU_FX_SCB3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[216]) /* 0x40013E00 */ +#define PERI_MS_PPU_FX_SCB4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[217]) /* 0x40013E40 */ +#define PERI_MS_PPU_FX_SCB5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[218]) /* 0x40013E80 */ +#define PERI_MS_PPU_FX_SCB6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[219]) /* 0x40013EC0 */ + +/******************************************************************************* +* CPUSS +*******************************************************************************/ + +#define CPUSS_BASE 0x40200000UL +#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40200000 */ + +/******************************************************************************* +* FAULT +*******************************************************************************/ + +#define FAULT_BASE 0x40210000UL +#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40210000 */ +#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40210000 */ +#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40210100 */ + +/******************************************************************************* +* IPC +*******************************************************************************/ + +#define IPC_BASE 0x40220000UL +#define IPC ((IPC_Type*) IPC_BASE) /* 0x40220000 */ +#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40220000 */ +#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40220020 */ +#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40220040 */ +#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40220060 */ +#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40220080 */ +#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402200A0 */ +#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402200C0 */ +#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402200E0 */ +#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40220100 */ +#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40220120 */ +#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40220140 */ +#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40220160 */ +#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40220180 */ +#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402201A0 */ +#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402201C0 */ +#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402201E0 */ +#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40221000 */ +#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40221020 */ +#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40221040 */ +#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40221060 */ +#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40221080 */ +#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402210A0 */ +#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402210C0 */ +#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402210E0 */ +#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40221100 */ +#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40221120 */ +#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40221140 */ +#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40221160 */ +#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40221180 */ +#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402211A0 */ +#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402211C0 */ +#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402211E0 */ + +/******************************************************************************* +* PROT +*******************************************************************************/ + +#define PROT_BASE 0x40230000UL +#define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ +#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ +#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ +#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402320C0 */ +#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40232100 */ +#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40232140 */ +#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40232180 */ +#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402321C0 */ +#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40232200 */ +#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40232240 */ +#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40232280 */ +#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402322C0 */ +#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40232300 */ +#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ +#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ +#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ +#define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ +#define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ +#define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ +#define PROT_MPU5_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[3]) /* 0x40235660 */ +#define PROT_MPU5_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[4]) /* 0x40235680 */ +#define PROT_MPU5_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[5]) /* 0x402356A0 */ +#define PROT_MPU5_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[6]) /* 0x402356C0 */ +#define PROT_MPU5_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[7]) /* 0x402356E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ + +/******************************************************************************* +* FLASHC +*******************************************************************************/ + +#define FLASHC_BASE 0x40240000UL +#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40240000 */ +#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4024F000 */ + +/******************************************************************************* +* SRSS +*******************************************************************************/ + +#define SRSS_BASE 0x40260000UL +#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ +#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */ +#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */ + +/******************************************************************************* +* BACKUP +*******************************************************************************/ + +#define BACKUP_BASE 0x40270000UL +#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ + +/******************************************************************************* +* DW +*******************************************************************************/ + +#define DW0_BASE 0x40280000UL +#define DW1_BASE 0x40290000UL +#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ +#define DW1 ((DW_Type*) DW1_BASE) /* 0x40290000 */ +#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40288000 */ +#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40288040 */ +#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40288080 */ +#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x402880C0 */ +#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40288100 */ +#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x40288140 */ +#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x40288180 */ +#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402881C0 */ +#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40288200 */ +#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40288240 */ +#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40288280 */ +#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x402882C0 */ +#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40288300 */ +#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x40288340 */ +#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x40288380 */ +#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402883C0 */ +#define DW0_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[16]) /* 0x40288400 */ +#define DW0_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[17]) /* 0x40288440 */ +#define DW0_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[18]) /* 0x40288480 */ +#define DW0_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[19]) /* 0x402884C0 */ +#define DW0_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[20]) /* 0x40288500 */ +#define DW0_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[21]) /* 0x40288540 */ +#define DW0_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[22]) /* 0x40288580 */ +#define DW0_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[23]) /* 0x402885C0 */ +#define DW0_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[24]) /* 0x40288600 */ +#define DW0_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[25]) /* 0x40288640 */ +#define DW0_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[26]) /* 0x40288680 */ +#define DW0_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[27]) /* 0x402886C0 */ +#define DW0_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[28]) /* 0x40288700 */ +#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40298000 */ +#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40298040 */ +#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40298080 */ +#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x402980C0 */ +#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40298100 */ +#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x40298140 */ +#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x40298180 */ +#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402981C0 */ +#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40298200 */ +#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40298240 */ +#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40298280 */ +#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x402982C0 */ +#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40298300 */ +#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x40298340 */ +#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x40298380 */ +#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402983C0 */ +#define DW1_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[16]) /* 0x40298400 */ +#define DW1_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[17]) /* 0x40298440 */ +#define DW1_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[18]) /* 0x40298480 */ +#define DW1_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[19]) /* 0x402984C0 */ +#define DW1_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[20]) /* 0x40298500 */ +#define DW1_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[21]) /* 0x40298540 */ +#define DW1_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[22]) /* 0x40298580 */ +#define DW1_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[23]) /* 0x402985C0 */ +#define DW1_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[24]) /* 0x40298600 */ +#define DW1_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[25]) /* 0x40298640 */ +#define DW1_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[26]) /* 0x40298680 */ +#define DW1_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[27]) /* 0x402986C0 */ +#define DW1_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[28]) /* 0x40298700 */ +#define DW1_CH_STRUCT29 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[29]) /* 0x40298740 */ +#define DW1_CH_STRUCT30 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[30]) /* 0x40298780 */ +#define DW1_CH_STRUCT31 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[31]) /* 0x402987C0 */ + +/******************************************************************************* +* DMAC +*******************************************************************************/ + +#define DMAC_BASE 0x402A0000UL +#define DMAC ((DMAC_Type*) DMAC_BASE) /* 0x402A0000 */ +#define DMAC_CH0 ((DMAC_CH_Type*) &DMAC->CH[0]) /* 0x402A1000 */ +#define DMAC_CH1 ((DMAC_CH_Type*) &DMAC->CH[1]) /* 0x402A1100 */ + +/******************************************************************************* +* EFUSE +*******************************************************************************/ + +#define EFUSE_BASE 0x402C0000UL +#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ + +/******************************************************************************* +* HSIOM +*******************************************************************************/ + +#define HSIOM_BASE 0x40300000UL +#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40300000 */ +#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40300000 */ +#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40300010 */ +#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40300020 */ +#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40300030 */ +#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40300040 */ +#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40300050 */ +#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40300060 */ +#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40300070 */ +#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40300080 */ +#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40300090 */ +#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403000A0 */ +#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403000B0 */ +#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403000C0 */ +#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403000D0 */ +#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403000E0 */ + +/******************************************************************************* +* GPIO +*******************************************************************************/ + +#define GPIO_BASE 0x40310000UL +#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40310000 */ +#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40310000 */ +#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40310080 */ +#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40310100 */ +#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40310180 */ +#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40310200 */ +#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40310280 */ +#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40310300 */ +#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40310380 */ +#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40310400 */ +#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40310480 */ +#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40310500 */ +#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40310580 */ +#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40310600 */ +#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40310680 */ +#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40310700 */ + +/******************************************************************************* +* SMARTIO +*******************************************************************************/ + +#define SMARTIO_BASE 0x40320000UL +#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40320000 */ +#define SMARTIO_PRT8 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[8]) /* 0x40320800 */ +#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40320900 */ + +/******************************************************************************* +* LPCOMP +*******************************************************************************/ + +#define LPCOMP_BASE 0x40350000UL +#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */ + +/******************************************************************************* +* CSD +*******************************************************************************/ + +#define CSD0_BASE 0x40360000UL +#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */ + +/******************************************************************************* +* TCPWM +*******************************************************************************/ + +#define TCPWM0_BASE 0x40380000UL +#define TCPWM1_BASE 0x40390000UL +#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM1 ((TCPWM_Type*) TCPWM1_BASE) /* 0x40390000 */ +#define TCPWM0_CNT0 ((TCPWM_CNT_Type*) &TCPWM0->CNT[0]) /* 0x40380100 */ +#define TCPWM0_CNT1 ((TCPWM_CNT_Type*) &TCPWM0->CNT[1]) /* 0x40380140 */ +#define TCPWM0_CNT2 ((TCPWM_CNT_Type*) &TCPWM0->CNT[2]) /* 0x40380180 */ +#define TCPWM0_CNT3 ((TCPWM_CNT_Type*) &TCPWM0->CNT[3]) /* 0x403801C0 */ +#define TCPWM1_CNT0 ((TCPWM_CNT_Type*) &TCPWM1->CNT[0]) /* 0x40390100 */ +#define TCPWM1_CNT1 ((TCPWM_CNT_Type*) &TCPWM1->CNT[1]) /* 0x40390140 */ +#define TCPWM1_CNT2 ((TCPWM_CNT_Type*) &TCPWM1->CNT[2]) /* 0x40390180 */ +#define TCPWM1_CNT3 ((TCPWM_CNT_Type*) &TCPWM1->CNT[3]) /* 0x403901C0 */ +#define TCPWM1_CNT4 ((TCPWM_CNT_Type*) &TCPWM1->CNT[4]) /* 0x40390200 */ +#define TCPWM1_CNT5 ((TCPWM_CNT_Type*) &TCPWM1->CNT[5]) /* 0x40390240 */ +#define TCPWM1_CNT6 ((TCPWM_CNT_Type*) &TCPWM1->CNT[6]) /* 0x40390280 */ +#define TCPWM1_CNT7 ((TCPWM_CNT_Type*) &TCPWM1->CNT[7]) /* 0x403902C0 */ + +/******************************************************************************* +* LCD +*******************************************************************************/ + +#define LCD0_BASE 0x403B0000UL +#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ + +/******************************************************************************* +* SMIF +*******************************************************************************/ + +#define SMIF0_BASE 0x40420000UL +#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ +#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ +#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ +#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ + +/******************************************************************************* +* SDHC +*******************************************************************************/ + +#define SDHC0_BASE 0x40460000UL +#define SDHC0 ((SDHC_Type*) SDHC0_BASE) /* 0x40460000 */ +#define SDHC0_WRAP ((SDHC_WRAP_Type*) &SDHC0->WRAP) /* 0x40460000 */ +#define SDHC0_CORE ((SDHC_CORE_Type*) &SDHC0->CORE) /* 0x40461000 */ + +/******************************************************************************* +* CANFD +*******************************************************************************/ + +#define CANFD0_BASE 0x40520000UL +#define CANFD0 ((CANFD_Type*) CANFD0_BASE) /* 0x40520000 */ +#define CANFD0_CH0 ((CANFD_CH_Type*) &CANFD0->CH[0]) /* 0x40520000 */ +#define CANFD0_CH0_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[0].M_TTCAN) /* 0x40520000 */ + +/******************************************************************************* +* SCB +*******************************************************************************/ + +#define SCB0_BASE 0x40600000UL +#define SCB1_BASE 0x40610000UL +#define SCB2_BASE 0x40620000UL +#define SCB3_BASE 0x40630000UL +#define SCB4_BASE 0x40640000UL +#define SCB5_BASE 0x40650000UL +#define SCB6_BASE 0x40660000UL +#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40600000 */ +#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40610000 */ +#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40620000 */ +#define SCB3 ((CySCB_Type*) SCB3_BASE) /* 0x40630000 */ +#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40640000 */ +#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40650000 */ +#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40660000 */ + +/******************************************************************************* +* SAR +*******************************************************************************/ + +#define SAR_BASE 0x409D0000UL +#define SAR ((SAR_Type*) SAR_BASE) /* 0x409D0000 */ + +/******************************************************************************* +* PASS +*******************************************************************************/ + +#define PASS_BASE 0x409F0000UL +#define PASS ((PASS_Type*) PASS_BASE) /* 0x409F0000 */ +#define PASS_AREF ((PASS_AREF_Type*) &PASS->AREF) /* 0x409F0E00 */ + +/** \} CY8C6145FNI-S3F11 */ + +#endif /* _CY8C6145FNI_S3F11_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6145fni_s3f41.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6145fni_s3f41.h new file mode 100644 index 0000000000..89284841ce --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6145fni_s3f41.h @@ -0,0 +1,980 @@ +/***************************************************************************//** +* \file cy8c6145fni_s3f41.h +* +* \brief +* CY8C6145FNI-S3F41 device header +* +* \note +* Generator version: 1.6.0.225 +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CY8C6145FNI_S3F41_H_ +#define _CY8C6145FNI_S3F41_H_ + +/** +* \addtogroup group_device CY8C6145FNI-S3F41 +* \{ +*/ + +/** +* \addtogroup Configuration_of_CMSIS +* \{ +*/ + +/******************************************************************************* +* Interrupt Number Definition +*******************************************************************************/ + +typedef enum { + /* ARM Cortex-M4 Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C6145FNI-S3F41 Peripheral Interrupt Numbers */ + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_6_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #6 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + canfd_0_interrupt0_IRQn = 168, /*!< 168 [Active] Can #0, Consolidated interrupt #0 */ + canfd_0_interrupts0_0_IRQn = 169, /*!< 169 [Active] CAN #0, Interrupt #0, Channel #0 */ + canfd_0_interrupts1_0_IRQn = 170, /*!< 170 [Active] CAN #0, Interrupt #1, Channel #0 */ + cpuss_interrupts_dw1_29_IRQn = 171, /*!< 171 [Active] CPUSS DataWire #1, Channel #29 */ + cpuss_interrupts_dw1_30_IRQn = 172, /*!< 172 [Active] CPUSS DataWire #1, Channel #30 */ + cpuss_interrupts_dw1_31_IRQn = 173, /*!< 173 [Active] CPUSS DataWire #1, Channel #31 */ + unconnected_IRQn = 240 /*!< 240 Unconnected */ +} IRQn_Type; + + +/******************************************************************************* +* Processor and Core Peripheral Section +*******************************************************************************/ + +/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __CM0P_PRESENT 0 /*!< CM0P present or not */ +#define __DTCM_PRESENT 0 /*!< DTCM present or not */ +#define __ICACHE_PRESENT 0 /*!< ICACHE present or not */ +#define __DCACHE_PRESENT 0 /*!< DCACHE present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + + +/* Memory Blocks */ +#define CY_ROM_BASE 0x00000000UL +#define CY_ROM_SIZE 0x00010000UL +#define CY_SRAM_BASE 0x08000000UL +#define CY_SRAM_SIZE 0x00040000UL +#define CY_FLASH_BASE 0x10000000UL +#define CY_FLASH_SIZE 0x00080000UL +#define CY_EM_EEPROM_BASE 0x14000000UL +#define CY_EM_EEPROM_SIZE 0x00008000UL +#define CY_SFLASH_BASE 0x16000000UL +#define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL +#define CY_EFUSE_BASE 0x402C0800UL +#define CY_EFUSE_SIZE 0x00000200UL +#define CY_CAN0MRAM_BASE 0x40530000UL +#define CY_CAN0MRAM_SIZE 0x00010000UL + +#include "system_psoc6.h" /*!< PSoC 6 System */ + +/* IP List */ +#define CY_IP_MXTTCANFD 1u +#define CY_IP_MXTTCANFD_INSTANCES 1u +#define CY_IP_MXTTCANFD_VERSION 1u +#define CY_IP_M4CPUSS 1u +#define CY_IP_M4CPUSS_INSTANCES 1u +#define CY_IP_M4CPUSS_VERSION 2u +#define CY_IP_M4CPUSS_DMAC 1u +#define CY_IP_M4CPUSS_DMAC_INSTANCES 1u +#define CY_IP_M4CPUSS_DMAC_VERSION 2u +#define CY_IP_M4CPUSS_DMA 1u +#define CY_IP_M4CPUSS_DMA_INSTANCES 2u +#define CY_IP_M4CPUSS_DMA_VERSION 2u +#define CY_IP_MXCRYPTO 1u +#define CY_IP_MXCRYPTO_INSTANCES 1u +#define CY_IP_MXCRYPTO_VERSION 2u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 2u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u +#define CY_IP_MXS40PASS 1u +#define CY_IP_MXS40PASS_INSTANCES 1u +#define CY_IP_MXS40PASS_VERSION 1u +#define CY_IP_MXS40PASS_SAR 1u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u +#define CY_IP_MXS40PASS_SAR_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 7u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 1u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u + +#include "psoc6_03_config.h" +#include "gpio_psoc6_03_49_wlcsp.h" + +#define CY_DEVICE_PSOC6A512K +#define CY_SILICON_ID 0xE7161105UL +#define CY_HF_CLK_MAX_FREQ 150000000UL + +#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL + +/******************************************************************************* +* SFLASH +*******************************************************************************/ + +#define SFLASH_BASE 0x16000000UL +#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */ + +/******************************************************************************* +* PERI +*******************************************************************************/ + +#define PERI_BASE 0x40000000UL +#define PERI ((PERI_Type*) PERI_BASE) /* 0x40000000 */ +#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40004000 */ +#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40004020 */ +#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40004040 */ +#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x40004060 */ +#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40004080 */ +#define PERI_GR5 ((PERI_GR_Type*) &PERI->GR[5]) /* 0x400040A0 */ +#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x400040C0 */ +#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40004120 */ +#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40008000 */ +#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40008400 */ +#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40008800 */ +#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40008C00 */ +#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40009000 */ +#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40009400 */ +#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40009800 */ +#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40009C00 */ +#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ +#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ +#define PERI_TR_GR10 ((PERI_TR_GR_Type*) &PERI->TR_GR[10]) /* 0x4000A800 */ +#define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ +#define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ +#define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ +#define PERI_TR_1TO1_GR3 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[3]) /* 0x4000CC00 */ +#define PERI_TR_1TO1_GR4 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[4]) /* 0x4000D000 */ +#define PERI_TR_1TO1_GR5 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[5]) /* 0x4000D400 */ +#define PERI_TR_1TO1_GR6 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[6]) /* 0x4000D800 */ +#define PERI_TR_1TO1_GR7 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[7]) /* 0x4000DC00 */ + +/******************************************************************************* +* PERI_MS +*******************************************************************************/ + +#define PERI_MS_BASE 0x40010000UL +#define PERI_MS ((PERI_MS_Type*) PERI_MS_BASE) /* 0x40010000 */ +#define PERI_MS_PPU_PR0 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[0]) /* 0x40010000 */ +#define PERI_MS_PPU_PR1 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[1]) /* 0x40010040 */ +#define PERI_MS_PPU_PR2 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[2]) /* 0x40010080 */ +#define PERI_MS_PPU_PR3 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[3]) /* 0x400100C0 */ +#define PERI_MS_PPU_PR4 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[4]) /* 0x40010100 */ +#define PERI_MS_PPU_PR5 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[5]) /* 0x40010140 */ +#define PERI_MS_PPU_PR6 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[6]) /* 0x40010180 */ +#define PERI_MS_PPU_PR7 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[7]) /* 0x400101C0 */ +#define PERI_MS_PPU_FX_PERI_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[0]) /* 0x40010800 */ +#define PERI_MS_PPU_FX_PERI_GR0_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[1]) /* 0x40010840 */ +#define PERI_MS_PPU_FX_PERI_GR1_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[2]) /* 0x40010880 */ +#define PERI_MS_PPU_FX_PERI_GR2_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[3]) /* 0x400108C0 */ +#define PERI_MS_PPU_FX_PERI_GR3_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[4]) /* 0x40010900 */ +#define PERI_MS_PPU_FX_PERI_GR4_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[5]) /* 0x40010940 */ +#define PERI_MS_PPU_FX_PERI_GR5_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[6]) /* 0x40010980 */ +#define PERI_MS_PPU_FX_PERI_GR6_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[7]) /* 0x400109C0 */ +#define PERI_MS_PPU_FX_PERI_GR9_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[8]) /* 0x40010A00 */ +#define PERI_MS_PPU_FX_PERI_TR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[9]) /* 0x40010A40 */ +#define PERI_MS_PPU_FX_CRYPTO_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[10]) /* 0x40010A80 */ +#define PERI_MS_PPU_FX_CRYPTO_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[11]) /* 0x40010AC0 */ +#define PERI_MS_PPU_FX_CRYPTO_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[12]) /* 0x40010B00 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[13]) /* 0x40010B40 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[14]) /* 0x40010B80 */ +#define PERI_MS_PPU_FX_CRYPTO_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[15]) /* 0x40010BC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[16]) /* 0x40010C00 */ +#define PERI_MS_PPU_FX_CPUSS_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[17]) /* 0x40010C40 */ +#define PERI_MS_PPU_FX_CPUSS_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[18]) /* 0x40010C80 */ +#define PERI_MS_PPU_FX_CPUSS_CM0_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[19]) /* 0x40010CC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[20]) /* 0x40010D00 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[21]) /* 0x40010D40 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT1_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[22]) /* 0x40010D80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT0_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[23]) /* 0x40010DC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT1_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[24]) /* 0x40010E00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT2_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[25]) /* 0x40010E40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT3_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[26]) /* 0x40010E80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT4_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[27]) /* 0x40010EC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT5_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[28]) /* 0x40010F00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT6_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[29]) /* 0x40010F40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT7_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[30]) /* 0x40010F80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT8_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[31]) /* 0x40010FC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT9_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[32]) /* 0x40011000 */ +#define PERI_MS_PPU_FX_IPC_STRUCT10_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[33]) /* 0x40011040 */ +#define PERI_MS_PPU_FX_IPC_STRUCT11_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[34]) /* 0x40011080 */ +#define PERI_MS_PPU_FX_IPC_STRUCT12_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[35]) /* 0x400110C0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT13_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[36]) /* 0x40011100 */ +#define PERI_MS_PPU_FX_IPC_STRUCT14_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[37]) /* 0x40011140 */ +#define PERI_MS_PPU_FX_IPC_STRUCT15_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[38]) /* 0x40011180 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT0_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[39]) /* 0x400111C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT1_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[40]) /* 0x40011200 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT2_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[41]) /* 0x40011240 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT3_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[42]) /* 0x40011280 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT4_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[43]) /* 0x400112C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT5_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[44]) /* 0x40011300 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT6_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[45]) /* 0x40011340 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT7_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[46]) /* 0x40011380 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT8_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[47]) /* 0x400113C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT9_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[48]) /* 0x40011400 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT10_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[49]) /* 0x40011440 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT11_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[50]) /* 0x40011480 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT12_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[51]) /* 0x400114C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT13_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[52]) /* 0x40011500 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT14_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[53]) /* 0x40011540 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT15_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[54]) /* 0x40011580 */ +#define PERI_MS_PPU_FX_PROT_SMPU_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[55]) /* 0x400115C0 */ +#define PERI_MS_PPU_FX_PROT_MPU0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[56]) /* 0x40011600 */ +#define PERI_MS_PPU_FX_PROT_MPU5_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[57]) /* 0x40011640 */ +#define PERI_MS_PPU_FX_PROT_MPU14_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[58]) /* 0x40011680 */ +#define PERI_MS_PPU_FX_PROT_MPU15_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[59]) /* 0x400116C0 */ +#define PERI_MS_PPU_FX_FLASHC_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[60]) /* 0x40011700 */ +#define PERI_MS_PPU_FX_FLASHC_CMD ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[61]) /* 0x40011740 */ +#define PERI_MS_PPU_FX_FLASHC_DFT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[62]) /* 0x40011780 */ +#define PERI_MS_PPU_FX_FLASHC_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[63]) /* 0x400117C0 */ +#define PERI_MS_PPU_FX_FLASHC_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[64]) /* 0x40011800 */ +#define PERI_MS_PPU_FX_FLASHC_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[65]) /* 0x40011840 */ +#define PERI_MS_PPU_FX_FLASHC_DW0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[66]) /* 0x40011880 */ +#define PERI_MS_PPU_FX_FLASHC_DW1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[67]) /* 0x400118C0 */ +#define PERI_MS_PPU_FX_FLASHC_DMAC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[68]) /* 0x40011900 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[69]) /* 0x40011940 */ +#define PERI_MS_PPU_FX_FLASHC_FM ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[70]) /* 0x40011980 */ +#define PERI_MS_PPU_FX_SRSS_MAIN1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[71]) /* 0x400119C0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[72]) /* 0x40011A00 */ +#define PERI_MS_PPU_FX_WDT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[73]) /* 0x40011A40 */ +#define PERI_MS_PPU_FX_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[74]) /* 0x40011A80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[75]) /* 0x40011AC0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[76]) /* 0x40011B00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[77]) /* 0x40011B40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[78]) /* 0x40011B80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[79]) /* 0x40011BC0 */ +#define PERI_MS_PPU_FX_BACKUP_BACKUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[80]) /* 0x40011C00 */ +#define PERI_MS_PPU_FX_DW0_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[81]) /* 0x40011C40 */ +#define PERI_MS_PPU_FX_DW1_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[82]) /* 0x40011C80 */ +#define PERI_MS_PPU_FX_DW0_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[83]) /* 0x40011CC0 */ +#define PERI_MS_PPU_FX_DW1_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[84]) /* 0x40011D00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[85]) /* 0x40011D40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[86]) /* 0x40011D80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[87]) /* 0x40011DC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[88]) /* 0x40011E00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[89]) /* 0x40011E40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[90]) /* 0x40011E80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[91]) /* 0x40011EC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[92]) /* 0x40011F00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[93]) /* 0x40011F40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[94]) /* 0x40011F80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[95]) /* 0x40011FC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[96]) /* 0x40012000 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[97]) /* 0x40012040 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[98]) /* 0x40012080 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[99]) /* 0x400120C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[100]) /* 0x40012100 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[101]) /* 0x40012140 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[102]) /* 0x40012180 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[103]) /* 0x400121C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[104]) /* 0x40012200 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[105]) /* 0x40012240 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[106]) /* 0x40012280 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[107]) /* 0x400122C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[108]) /* 0x40012300 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[109]) /* 0x40012340 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[110]) /* 0x40012380 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[111]) /* 0x400123C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[112]) /* 0x40012400 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[113]) /* 0x40012440 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[114]) /* 0x40012480 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[115]) /* 0x400124C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[116]) /* 0x40012500 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[117]) /* 0x40012540 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[118]) /* 0x40012580 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[119]) /* 0x400125C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[120]) /* 0x40012600 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[121]) /* 0x40012640 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[122]) /* 0x40012680 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[123]) /* 0x400126C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[124]) /* 0x40012700 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[125]) /* 0x40012740 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[126]) /* 0x40012780 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[127]) /* 0x400127C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[128]) /* 0x40012800 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[129]) /* 0x40012840 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[130]) /* 0x40012880 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[131]) /* 0x400128C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[132]) /* 0x40012900 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[133]) /* 0x40012940 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[134]) /* 0x40012980 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[135]) /* 0x400129C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[136]) /* 0x40012A00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[137]) /* 0x40012A40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[138]) /* 0x40012A80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[139]) /* 0x40012AC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[140]) /* 0x40012B00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[141]) /* 0x40012B40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[142]) /* 0x40012B80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT29_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[143]) /* 0x40012BC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT30_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[144]) /* 0x40012C00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT31_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[145]) /* 0x40012C40 */ +#define PERI_MS_PPU_FX_DMAC_TOP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[146]) /* 0x40012C80 */ +#define PERI_MS_PPU_FX_DMAC_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[147]) /* 0x40012CC0 */ +#define PERI_MS_PPU_FX_DMAC_CH1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[148]) /* 0x40012D00 */ +#define PERI_MS_PPU_FX_EFUSE_CTL ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[149]) /* 0x40012D40 */ +#define PERI_MS_PPU_FX_EFUSE_DATA ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[150]) /* 0x40012D80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[151]) /* 0x40012DC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[152]) /* 0x40012E00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[153]) /* 0x40012E40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[154]) /* 0x40012E80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[155]) /* 0x40012EC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[156]) /* 0x40012F00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[157]) /* 0x40012F40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[158]) /* 0x40012F80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[159]) /* 0x40012FC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[160]) /* 0x40013000 */ +#define PERI_MS_PPU_FX_HSIOM_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[161]) /* 0x40013040 */ +#define PERI_MS_PPU_FX_HSIOM_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[162]) /* 0x40013080 */ +#define PERI_MS_PPU_FX_HSIOM_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[163]) /* 0x400130C0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[164]) /* 0x40013100 */ +#define PERI_MS_PPU_FX_HSIOM_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[165]) /* 0x40013140 */ +#define PERI_MS_PPU_FX_HSIOM_AMUX ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[166]) /* 0x40013180 */ +#define PERI_MS_PPU_FX_HSIOM_MON ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[167]) /* 0x400131C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[168]) /* 0x40013200 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[169]) /* 0x40013240 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[170]) /* 0x40013280 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[171]) /* 0x400132C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[172]) /* 0x40013300 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[173]) /* 0x40013340 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[174]) /* 0x40013380 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[175]) /* 0x400133C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[176]) /* 0x40013400 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[177]) /* 0x40013440 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[178]) /* 0x40013480 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[179]) /* 0x400134C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[180]) /* 0x40013500 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[181]) /* 0x40013540 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[182]) /* 0x40013580 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[183]) /* 0x400135C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[184]) /* 0x40013600 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[185]) /* 0x40013640 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[186]) /* 0x40013680 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[187]) /* 0x400136C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[188]) /* 0x40013700 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[189]) /* 0x40013740 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[190]) /* 0x40013780 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[191]) /* 0x400137C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[192]) /* 0x40013800 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[193]) /* 0x40013840 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[194]) /* 0x40013880 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[195]) /* 0x400138C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[196]) /* 0x40013900 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[197]) /* 0x40013940 */ +#define PERI_MS_PPU_FX_GPIO_GPIO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[198]) /* 0x40013980 */ +#define PERI_MS_PPU_FX_GPIO_TEST ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[199]) /* 0x400139C0 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[200]) /* 0x40013A00 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[201]) /* 0x40013A40 */ +#define PERI_MS_PPU_FX_LPCOMP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[202]) /* 0x40013A80 */ +#define PERI_MS_PPU_FX_CSD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[203]) /* 0x40013AC0 */ +#define PERI_MS_PPU_FX_TCPWM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[204]) /* 0x40013B00 */ +#define PERI_MS_PPU_FX_TCPWM1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[205]) /* 0x40013B40 */ +#define PERI_MS_PPU_FX_LCD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[206]) /* 0x40013B80 */ +#define PERI_MS_PPU_FX_USBFS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[207]) /* 0x40013BC0 */ +#define PERI_MS_PPU_FX_SMIF0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[208]) /* 0x40013C00 */ +#define PERI_MS_PPU_FX_SDHC0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[209]) /* 0x40013C40 */ +#define PERI_MS_PPU_FX_CANFD0_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[210]) /* 0x40013C80 */ +#define PERI_MS_PPU_FX_CANFD0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[211]) /* 0x40013CC0 */ +#define PERI_MS_PPU_FX_CANFD0_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[212]) /* 0x40013D00 */ +#define PERI_MS_PPU_FX_SCB0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[213]) /* 0x40013D40 */ +#define PERI_MS_PPU_FX_SCB1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[214]) /* 0x40013D80 */ +#define PERI_MS_PPU_FX_SCB2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[215]) /* 0x40013DC0 */ +#define PERI_MS_PPU_FX_SCB3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[216]) /* 0x40013E00 */ +#define PERI_MS_PPU_FX_SCB4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[217]) /* 0x40013E40 */ +#define PERI_MS_PPU_FX_SCB5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[218]) /* 0x40013E80 */ +#define PERI_MS_PPU_FX_SCB6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[219]) /* 0x40013EC0 */ + +/******************************************************************************* +* CRYPTO +*******************************************************************************/ + +#define CRYPTO_BASE 0x40100000UL +#define CRYPTO ((CRYPTO_Type*) CRYPTO_BASE) /* 0x40100000 */ + +/******************************************************************************* +* CPUSS +*******************************************************************************/ + +#define CPUSS_BASE 0x40200000UL +#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40200000 */ + +/******************************************************************************* +* FAULT +*******************************************************************************/ + +#define FAULT_BASE 0x40210000UL +#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40210000 */ +#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40210000 */ +#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40210100 */ + +/******************************************************************************* +* IPC +*******************************************************************************/ + +#define IPC_BASE 0x40220000UL +#define IPC ((IPC_Type*) IPC_BASE) /* 0x40220000 */ +#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40220000 */ +#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40220020 */ +#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40220040 */ +#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40220060 */ +#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40220080 */ +#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402200A0 */ +#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402200C0 */ +#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402200E0 */ +#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40220100 */ +#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40220120 */ +#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40220140 */ +#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40220160 */ +#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40220180 */ +#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402201A0 */ +#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402201C0 */ +#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402201E0 */ +#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40221000 */ +#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40221020 */ +#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40221040 */ +#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40221060 */ +#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40221080 */ +#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402210A0 */ +#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402210C0 */ +#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402210E0 */ +#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40221100 */ +#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40221120 */ +#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40221140 */ +#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40221160 */ +#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40221180 */ +#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402211A0 */ +#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402211C0 */ +#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402211E0 */ + +/******************************************************************************* +* PROT +*******************************************************************************/ + +#define PROT_BASE 0x40230000UL +#define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ +#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ +#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ +#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402320C0 */ +#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40232100 */ +#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40232140 */ +#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40232180 */ +#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402321C0 */ +#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40232200 */ +#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40232240 */ +#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40232280 */ +#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402322C0 */ +#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40232300 */ +#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ +#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ +#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ +#define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ +#define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ +#define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ +#define PROT_MPU5_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[3]) /* 0x40235660 */ +#define PROT_MPU5_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[4]) /* 0x40235680 */ +#define PROT_MPU5_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[5]) /* 0x402356A0 */ +#define PROT_MPU5_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[6]) /* 0x402356C0 */ +#define PROT_MPU5_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[7]) /* 0x402356E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ + +/******************************************************************************* +* FLASHC +*******************************************************************************/ + +#define FLASHC_BASE 0x40240000UL +#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40240000 */ +#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4024F000 */ + +/******************************************************************************* +* SRSS +*******************************************************************************/ + +#define SRSS_BASE 0x40260000UL +#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ +#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */ +#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */ + +/******************************************************************************* +* BACKUP +*******************************************************************************/ + +#define BACKUP_BASE 0x40270000UL +#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ + +/******************************************************************************* +* DW +*******************************************************************************/ + +#define DW0_BASE 0x40280000UL +#define DW1_BASE 0x40290000UL +#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ +#define DW1 ((DW_Type*) DW1_BASE) /* 0x40290000 */ +#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40288000 */ +#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40288040 */ +#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40288080 */ +#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x402880C0 */ +#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40288100 */ +#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x40288140 */ +#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x40288180 */ +#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402881C0 */ +#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40288200 */ +#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40288240 */ +#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40288280 */ +#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x402882C0 */ +#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40288300 */ +#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x40288340 */ +#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x40288380 */ +#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402883C0 */ +#define DW0_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[16]) /* 0x40288400 */ +#define DW0_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[17]) /* 0x40288440 */ +#define DW0_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[18]) /* 0x40288480 */ +#define DW0_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[19]) /* 0x402884C0 */ +#define DW0_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[20]) /* 0x40288500 */ +#define DW0_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[21]) /* 0x40288540 */ +#define DW0_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[22]) /* 0x40288580 */ +#define DW0_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[23]) /* 0x402885C0 */ +#define DW0_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[24]) /* 0x40288600 */ +#define DW0_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[25]) /* 0x40288640 */ +#define DW0_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[26]) /* 0x40288680 */ +#define DW0_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[27]) /* 0x402886C0 */ +#define DW0_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[28]) /* 0x40288700 */ +#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40298000 */ +#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40298040 */ +#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40298080 */ +#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x402980C0 */ +#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40298100 */ +#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x40298140 */ +#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x40298180 */ +#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402981C0 */ +#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40298200 */ +#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40298240 */ +#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40298280 */ +#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x402982C0 */ +#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40298300 */ +#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x40298340 */ +#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x40298380 */ +#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402983C0 */ +#define DW1_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[16]) /* 0x40298400 */ +#define DW1_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[17]) /* 0x40298440 */ +#define DW1_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[18]) /* 0x40298480 */ +#define DW1_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[19]) /* 0x402984C0 */ +#define DW1_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[20]) /* 0x40298500 */ +#define DW1_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[21]) /* 0x40298540 */ +#define DW1_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[22]) /* 0x40298580 */ +#define DW1_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[23]) /* 0x402985C0 */ +#define DW1_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[24]) /* 0x40298600 */ +#define DW1_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[25]) /* 0x40298640 */ +#define DW1_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[26]) /* 0x40298680 */ +#define DW1_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[27]) /* 0x402986C0 */ +#define DW1_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[28]) /* 0x40298700 */ +#define DW1_CH_STRUCT29 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[29]) /* 0x40298740 */ +#define DW1_CH_STRUCT30 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[30]) /* 0x40298780 */ +#define DW1_CH_STRUCT31 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[31]) /* 0x402987C0 */ + +/******************************************************************************* +* DMAC +*******************************************************************************/ + +#define DMAC_BASE 0x402A0000UL +#define DMAC ((DMAC_Type*) DMAC_BASE) /* 0x402A0000 */ +#define DMAC_CH0 ((DMAC_CH_Type*) &DMAC->CH[0]) /* 0x402A1000 */ +#define DMAC_CH1 ((DMAC_CH_Type*) &DMAC->CH[1]) /* 0x402A1100 */ + +/******************************************************************************* +* EFUSE +*******************************************************************************/ + +#define EFUSE_BASE 0x402C0000UL +#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ + +/******************************************************************************* +* HSIOM +*******************************************************************************/ + +#define HSIOM_BASE 0x40300000UL +#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40300000 */ +#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40300000 */ +#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40300010 */ +#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40300020 */ +#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40300030 */ +#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40300040 */ +#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40300050 */ +#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40300060 */ +#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40300070 */ +#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40300080 */ +#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40300090 */ +#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403000A0 */ +#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403000B0 */ +#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403000C0 */ +#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403000D0 */ +#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403000E0 */ + +/******************************************************************************* +* GPIO +*******************************************************************************/ + +#define GPIO_BASE 0x40310000UL +#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40310000 */ +#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40310000 */ +#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40310080 */ +#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40310100 */ +#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40310180 */ +#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40310200 */ +#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40310280 */ +#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40310300 */ +#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40310380 */ +#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40310400 */ +#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40310480 */ +#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40310500 */ +#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40310580 */ +#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40310600 */ +#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40310680 */ +#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40310700 */ + +/******************************************************************************* +* SMARTIO +*******************************************************************************/ + +#define SMARTIO_BASE 0x40320000UL +#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40320000 */ +#define SMARTIO_PRT8 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[8]) /* 0x40320800 */ +#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40320900 */ + +/******************************************************************************* +* LPCOMP +*******************************************************************************/ + +#define LPCOMP_BASE 0x40350000UL +#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */ + +/******************************************************************************* +* CSD +*******************************************************************************/ + +#define CSD0_BASE 0x40360000UL +#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */ + +/******************************************************************************* +* TCPWM +*******************************************************************************/ + +#define TCPWM0_BASE 0x40380000UL +#define TCPWM1_BASE 0x40390000UL +#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM1 ((TCPWM_Type*) TCPWM1_BASE) /* 0x40390000 */ +#define TCPWM0_CNT0 ((TCPWM_CNT_Type*) &TCPWM0->CNT[0]) /* 0x40380100 */ +#define TCPWM0_CNT1 ((TCPWM_CNT_Type*) &TCPWM0->CNT[1]) /* 0x40380140 */ +#define TCPWM0_CNT2 ((TCPWM_CNT_Type*) &TCPWM0->CNT[2]) /* 0x40380180 */ +#define TCPWM0_CNT3 ((TCPWM_CNT_Type*) &TCPWM0->CNT[3]) /* 0x403801C0 */ +#define TCPWM1_CNT0 ((TCPWM_CNT_Type*) &TCPWM1->CNT[0]) /* 0x40390100 */ +#define TCPWM1_CNT1 ((TCPWM_CNT_Type*) &TCPWM1->CNT[1]) /* 0x40390140 */ +#define TCPWM1_CNT2 ((TCPWM_CNT_Type*) &TCPWM1->CNT[2]) /* 0x40390180 */ +#define TCPWM1_CNT3 ((TCPWM_CNT_Type*) &TCPWM1->CNT[3]) /* 0x403901C0 */ +#define TCPWM1_CNT4 ((TCPWM_CNT_Type*) &TCPWM1->CNT[4]) /* 0x40390200 */ +#define TCPWM1_CNT5 ((TCPWM_CNT_Type*) &TCPWM1->CNT[5]) /* 0x40390240 */ +#define TCPWM1_CNT6 ((TCPWM_CNT_Type*) &TCPWM1->CNT[6]) /* 0x40390280 */ +#define TCPWM1_CNT7 ((TCPWM_CNT_Type*) &TCPWM1->CNT[7]) /* 0x403902C0 */ + +/******************************************************************************* +* LCD +*******************************************************************************/ + +#define LCD0_BASE 0x403B0000UL +#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ + +/******************************************************************************* +* SMIF +*******************************************************************************/ + +#define SMIF0_BASE 0x40420000UL +#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ +#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ +#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ +#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ + +/******************************************************************************* +* SDHC +*******************************************************************************/ + +#define SDHC0_BASE 0x40460000UL +#define SDHC0 ((SDHC_Type*) SDHC0_BASE) /* 0x40460000 */ +#define SDHC0_WRAP ((SDHC_WRAP_Type*) &SDHC0->WRAP) /* 0x40460000 */ +#define SDHC0_CORE ((SDHC_CORE_Type*) &SDHC0->CORE) /* 0x40461000 */ + +/******************************************************************************* +* CANFD +*******************************************************************************/ + +#define CANFD0_BASE 0x40520000UL +#define CANFD0 ((CANFD_Type*) CANFD0_BASE) /* 0x40520000 */ +#define CANFD0_CH0 ((CANFD_CH_Type*) &CANFD0->CH[0]) /* 0x40520000 */ +#define CANFD0_CH0_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[0].M_TTCAN) /* 0x40520000 */ + +/******************************************************************************* +* SCB +*******************************************************************************/ + +#define SCB0_BASE 0x40600000UL +#define SCB1_BASE 0x40610000UL +#define SCB2_BASE 0x40620000UL +#define SCB3_BASE 0x40630000UL +#define SCB4_BASE 0x40640000UL +#define SCB5_BASE 0x40650000UL +#define SCB6_BASE 0x40660000UL +#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40600000 */ +#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40610000 */ +#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40620000 */ +#define SCB3 ((CySCB_Type*) SCB3_BASE) /* 0x40630000 */ +#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40640000 */ +#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40650000 */ +#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40660000 */ + +/******************************************************************************* +* SAR +*******************************************************************************/ + +#define SAR_BASE 0x409D0000UL +#define SAR ((SAR_Type*) SAR_BASE) /* 0x409D0000 */ + +/******************************************************************************* +* PASS +*******************************************************************************/ + +#define PASS_BASE 0x409F0000UL +#define PASS ((PASS_Type*) PASS_BASE) /* 0x409F0000 */ +#define PASS_AREF ((PASS_AREF_Type*) &PASS->AREF) /* 0x409F0E00 */ + +/** \} CY8C6145FNI-S3F41 */ + +#endif /* _CY8C6145FNI_S3F41_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6145fni_s3f71.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6145fni_s3f71.h new file mode 100644 index 0000000000..0193cbc358 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6145fni_s3f71.h @@ -0,0 +1,980 @@ +/***************************************************************************//** +* \file cy8c6145fni_s3f71.h +* +* \brief +* CY8C6145FNI-S3F71 device header +* +* \note +* Generator version: 1.6.0.225 +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CY8C6145FNI_S3F71_H_ +#define _CY8C6145FNI_S3F71_H_ + +/** +* \addtogroup group_device CY8C6145FNI-S3F71 +* \{ +*/ + +/** +* \addtogroup Configuration_of_CMSIS +* \{ +*/ + +/******************************************************************************* +* Interrupt Number Definition +*******************************************************************************/ + +typedef enum { + /* ARM Cortex-M4 Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C6145FNI-S3F71 Peripheral Interrupt Numbers */ + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_6_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #6 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + canfd_0_interrupt0_IRQn = 168, /*!< 168 [Active] Can #0, Consolidated interrupt #0 */ + canfd_0_interrupts0_0_IRQn = 169, /*!< 169 [Active] CAN #0, Interrupt #0, Channel #0 */ + canfd_0_interrupts1_0_IRQn = 170, /*!< 170 [Active] CAN #0, Interrupt #1, Channel #0 */ + cpuss_interrupts_dw1_29_IRQn = 171, /*!< 171 [Active] CPUSS DataWire #1, Channel #29 */ + cpuss_interrupts_dw1_30_IRQn = 172, /*!< 172 [Active] CPUSS DataWire #1, Channel #30 */ + cpuss_interrupts_dw1_31_IRQn = 173, /*!< 173 [Active] CPUSS DataWire #1, Channel #31 */ + unconnected_IRQn = 240 /*!< 240 Unconnected */ +} IRQn_Type; + + +/******************************************************************************* +* Processor and Core Peripheral Section +*******************************************************************************/ + +/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __CM0P_PRESENT 0 /*!< CM0P present or not */ +#define __DTCM_PRESENT 0 /*!< DTCM present or not */ +#define __ICACHE_PRESENT 0 /*!< ICACHE present or not */ +#define __DCACHE_PRESENT 0 /*!< DCACHE present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + + +/* Memory Blocks */ +#define CY_ROM_BASE 0x00000000UL +#define CY_ROM_SIZE 0x00010000UL +#define CY_SRAM_BASE 0x08000000UL +#define CY_SRAM_SIZE 0x00040000UL +#define CY_FLASH_BASE 0x10000000UL +#define CY_FLASH_SIZE 0x00080000UL +#define CY_EM_EEPROM_BASE 0x14000000UL +#define CY_EM_EEPROM_SIZE 0x00008000UL +#define CY_SFLASH_BASE 0x16000000UL +#define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL +#define CY_EFUSE_BASE 0x402C0800UL +#define CY_EFUSE_SIZE 0x00000200UL +#define CY_CAN0MRAM_BASE 0x40530000UL +#define CY_CAN0MRAM_SIZE 0x00010000UL + +#include "system_psoc6.h" /*!< PSoC 6 System */ + +/* IP List */ +#define CY_IP_MXTTCANFD 1u +#define CY_IP_MXTTCANFD_INSTANCES 1u +#define CY_IP_MXTTCANFD_VERSION 1u +#define CY_IP_M4CPUSS 1u +#define CY_IP_M4CPUSS_INSTANCES 1u +#define CY_IP_M4CPUSS_VERSION 2u +#define CY_IP_M4CPUSS_DMAC 1u +#define CY_IP_M4CPUSS_DMAC_INSTANCES 1u +#define CY_IP_M4CPUSS_DMAC_VERSION 2u +#define CY_IP_M4CPUSS_DMA 1u +#define CY_IP_M4CPUSS_DMA_INSTANCES 2u +#define CY_IP_M4CPUSS_DMA_VERSION 2u +#define CY_IP_MXCRYPTO 1u +#define CY_IP_MXCRYPTO_INSTANCES 1u +#define CY_IP_MXCRYPTO_VERSION 2u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 2u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u +#define CY_IP_MXS40PASS 1u +#define CY_IP_MXS40PASS_INSTANCES 1u +#define CY_IP_MXS40PASS_VERSION 1u +#define CY_IP_MXS40PASS_SAR 1u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u +#define CY_IP_MXS40PASS_SAR_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 7u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 1u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u + +#include "psoc6_03_config.h" +#include "gpio_psoc6_03_49_wlcsp.h" + +#define CY_DEVICE_PSOC6A512K +#define CY_SILICON_ID 0xE7111105UL +#define CY_HF_CLK_MAX_FREQ 150000000UL + +#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL + +/******************************************************************************* +* SFLASH +*******************************************************************************/ + +#define SFLASH_BASE 0x16000000UL +#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */ + +/******************************************************************************* +* PERI +*******************************************************************************/ + +#define PERI_BASE 0x40000000UL +#define PERI ((PERI_Type*) PERI_BASE) /* 0x40000000 */ +#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40004000 */ +#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40004020 */ +#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40004040 */ +#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x40004060 */ +#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40004080 */ +#define PERI_GR5 ((PERI_GR_Type*) &PERI->GR[5]) /* 0x400040A0 */ +#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x400040C0 */ +#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40004120 */ +#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40008000 */ +#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40008400 */ +#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40008800 */ +#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40008C00 */ +#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40009000 */ +#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40009400 */ +#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40009800 */ +#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40009C00 */ +#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ +#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ +#define PERI_TR_GR10 ((PERI_TR_GR_Type*) &PERI->TR_GR[10]) /* 0x4000A800 */ +#define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ +#define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ +#define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ +#define PERI_TR_1TO1_GR3 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[3]) /* 0x4000CC00 */ +#define PERI_TR_1TO1_GR4 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[4]) /* 0x4000D000 */ +#define PERI_TR_1TO1_GR5 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[5]) /* 0x4000D400 */ +#define PERI_TR_1TO1_GR6 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[6]) /* 0x4000D800 */ +#define PERI_TR_1TO1_GR7 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[7]) /* 0x4000DC00 */ + +/******************************************************************************* +* PERI_MS +*******************************************************************************/ + +#define PERI_MS_BASE 0x40010000UL +#define PERI_MS ((PERI_MS_Type*) PERI_MS_BASE) /* 0x40010000 */ +#define PERI_MS_PPU_PR0 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[0]) /* 0x40010000 */ +#define PERI_MS_PPU_PR1 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[1]) /* 0x40010040 */ +#define PERI_MS_PPU_PR2 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[2]) /* 0x40010080 */ +#define PERI_MS_PPU_PR3 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[3]) /* 0x400100C0 */ +#define PERI_MS_PPU_PR4 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[4]) /* 0x40010100 */ +#define PERI_MS_PPU_PR5 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[5]) /* 0x40010140 */ +#define PERI_MS_PPU_PR6 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[6]) /* 0x40010180 */ +#define PERI_MS_PPU_PR7 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[7]) /* 0x400101C0 */ +#define PERI_MS_PPU_FX_PERI_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[0]) /* 0x40010800 */ +#define PERI_MS_PPU_FX_PERI_GR0_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[1]) /* 0x40010840 */ +#define PERI_MS_PPU_FX_PERI_GR1_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[2]) /* 0x40010880 */ +#define PERI_MS_PPU_FX_PERI_GR2_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[3]) /* 0x400108C0 */ +#define PERI_MS_PPU_FX_PERI_GR3_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[4]) /* 0x40010900 */ +#define PERI_MS_PPU_FX_PERI_GR4_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[5]) /* 0x40010940 */ +#define PERI_MS_PPU_FX_PERI_GR5_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[6]) /* 0x40010980 */ +#define PERI_MS_PPU_FX_PERI_GR6_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[7]) /* 0x400109C0 */ +#define PERI_MS_PPU_FX_PERI_GR9_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[8]) /* 0x40010A00 */ +#define PERI_MS_PPU_FX_PERI_TR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[9]) /* 0x40010A40 */ +#define PERI_MS_PPU_FX_CRYPTO_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[10]) /* 0x40010A80 */ +#define PERI_MS_PPU_FX_CRYPTO_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[11]) /* 0x40010AC0 */ +#define PERI_MS_PPU_FX_CRYPTO_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[12]) /* 0x40010B00 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[13]) /* 0x40010B40 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[14]) /* 0x40010B80 */ +#define PERI_MS_PPU_FX_CRYPTO_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[15]) /* 0x40010BC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[16]) /* 0x40010C00 */ +#define PERI_MS_PPU_FX_CPUSS_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[17]) /* 0x40010C40 */ +#define PERI_MS_PPU_FX_CPUSS_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[18]) /* 0x40010C80 */ +#define PERI_MS_PPU_FX_CPUSS_CM0_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[19]) /* 0x40010CC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[20]) /* 0x40010D00 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[21]) /* 0x40010D40 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT1_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[22]) /* 0x40010D80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT0_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[23]) /* 0x40010DC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT1_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[24]) /* 0x40010E00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT2_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[25]) /* 0x40010E40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT3_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[26]) /* 0x40010E80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT4_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[27]) /* 0x40010EC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT5_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[28]) /* 0x40010F00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT6_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[29]) /* 0x40010F40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT7_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[30]) /* 0x40010F80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT8_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[31]) /* 0x40010FC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT9_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[32]) /* 0x40011000 */ +#define PERI_MS_PPU_FX_IPC_STRUCT10_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[33]) /* 0x40011040 */ +#define PERI_MS_PPU_FX_IPC_STRUCT11_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[34]) /* 0x40011080 */ +#define PERI_MS_PPU_FX_IPC_STRUCT12_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[35]) /* 0x400110C0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT13_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[36]) /* 0x40011100 */ +#define PERI_MS_PPU_FX_IPC_STRUCT14_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[37]) /* 0x40011140 */ +#define PERI_MS_PPU_FX_IPC_STRUCT15_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[38]) /* 0x40011180 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT0_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[39]) /* 0x400111C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT1_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[40]) /* 0x40011200 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT2_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[41]) /* 0x40011240 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT3_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[42]) /* 0x40011280 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT4_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[43]) /* 0x400112C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT5_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[44]) /* 0x40011300 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT6_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[45]) /* 0x40011340 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT7_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[46]) /* 0x40011380 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT8_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[47]) /* 0x400113C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT9_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[48]) /* 0x40011400 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT10_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[49]) /* 0x40011440 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT11_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[50]) /* 0x40011480 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT12_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[51]) /* 0x400114C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT13_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[52]) /* 0x40011500 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT14_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[53]) /* 0x40011540 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT15_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[54]) /* 0x40011580 */ +#define PERI_MS_PPU_FX_PROT_SMPU_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[55]) /* 0x400115C0 */ +#define PERI_MS_PPU_FX_PROT_MPU0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[56]) /* 0x40011600 */ +#define PERI_MS_PPU_FX_PROT_MPU5_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[57]) /* 0x40011640 */ +#define PERI_MS_PPU_FX_PROT_MPU14_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[58]) /* 0x40011680 */ +#define PERI_MS_PPU_FX_PROT_MPU15_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[59]) /* 0x400116C0 */ +#define PERI_MS_PPU_FX_FLASHC_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[60]) /* 0x40011700 */ +#define PERI_MS_PPU_FX_FLASHC_CMD ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[61]) /* 0x40011740 */ +#define PERI_MS_PPU_FX_FLASHC_DFT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[62]) /* 0x40011780 */ +#define PERI_MS_PPU_FX_FLASHC_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[63]) /* 0x400117C0 */ +#define PERI_MS_PPU_FX_FLASHC_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[64]) /* 0x40011800 */ +#define PERI_MS_PPU_FX_FLASHC_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[65]) /* 0x40011840 */ +#define PERI_MS_PPU_FX_FLASHC_DW0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[66]) /* 0x40011880 */ +#define PERI_MS_PPU_FX_FLASHC_DW1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[67]) /* 0x400118C0 */ +#define PERI_MS_PPU_FX_FLASHC_DMAC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[68]) /* 0x40011900 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[69]) /* 0x40011940 */ +#define PERI_MS_PPU_FX_FLASHC_FM ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[70]) /* 0x40011980 */ +#define PERI_MS_PPU_FX_SRSS_MAIN1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[71]) /* 0x400119C0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[72]) /* 0x40011A00 */ +#define PERI_MS_PPU_FX_WDT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[73]) /* 0x40011A40 */ +#define PERI_MS_PPU_FX_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[74]) /* 0x40011A80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[75]) /* 0x40011AC0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[76]) /* 0x40011B00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[77]) /* 0x40011B40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[78]) /* 0x40011B80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[79]) /* 0x40011BC0 */ +#define PERI_MS_PPU_FX_BACKUP_BACKUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[80]) /* 0x40011C00 */ +#define PERI_MS_PPU_FX_DW0_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[81]) /* 0x40011C40 */ +#define PERI_MS_PPU_FX_DW1_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[82]) /* 0x40011C80 */ +#define PERI_MS_PPU_FX_DW0_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[83]) /* 0x40011CC0 */ +#define PERI_MS_PPU_FX_DW1_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[84]) /* 0x40011D00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[85]) /* 0x40011D40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[86]) /* 0x40011D80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[87]) /* 0x40011DC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[88]) /* 0x40011E00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[89]) /* 0x40011E40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[90]) /* 0x40011E80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[91]) /* 0x40011EC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[92]) /* 0x40011F00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[93]) /* 0x40011F40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[94]) /* 0x40011F80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[95]) /* 0x40011FC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[96]) /* 0x40012000 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[97]) /* 0x40012040 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[98]) /* 0x40012080 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[99]) /* 0x400120C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[100]) /* 0x40012100 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[101]) /* 0x40012140 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[102]) /* 0x40012180 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[103]) /* 0x400121C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[104]) /* 0x40012200 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[105]) /* 0x40012240 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[106]) /* 0x40012280 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[107]) /* 0x400122C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[108]) /* 0x40012300 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[109]) /* 0x40012340 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[110]) /* 0x40012380 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[111]) /* 0x400123C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[112]) /* 0x40012400 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[113]) /* 0x40012440 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[114]) /* 0x40012480 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[115]) /* 0x400124C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[116]) /* 0x40012500 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[117]) /* 0x40012540 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[118]) /* 0x40012580 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[119]) /* 0x400125C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[120]) /* 0x40012600 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[121]) /* 0x40012640 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[122]) /* 0x40012680 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[123]) /* 0x400126C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[124]) /* 0x40012700 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[125]) /* 0x40012740 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[126]) /* 0x40012780 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[127]) /* 0x400127C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[128]) /* 0x40012800 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[129]) /* 0x40012840 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[130]) /* 0x40012880 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[131]) /* 0x400128C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[132]) /* 0x40012900 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[133]) /* 0x40012940 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[134]) /* 0x40012980 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[135]) /* 0x400129C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[136]) /* 0x40012A00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[137]) /* 0x40012A40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[138]) /* 0x40012A80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[139]) /* 0x40012AC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[140]) /* 0x40012B00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[141]) /* 0x40012B40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[142]) /* 0x40012B80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT29_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[143]) /* 0x40012BC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT30_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[144]) /* 0x40012C00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT31_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[145]) /* 0x40012C40 */ +#define PERI_MS_PPU_FX_DMAC_TOP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[146]) /* 0x40012C80 */ +#define PERI_MS_PPU_FX_DMAC_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[147]) /* 0x40012CC0 */ +#define PERI_MS_PPU_FX_DMAC_CH1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[148]) /* 0x40012D00 */ +#define PERI_MS_PPU_FX_EFUSE_CTL ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[149]) /* 0x40012D40 */ +#define PERI_MS_PPU_FX_EFUSE_DATA ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[150]) /* 0x40012D80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[151]) /* 0x40012DC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[152]) /* 0x40012E00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[153]) /* 0x40012E40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[154]) /* 0x40012E80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[155]) /* 0x40012EC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[156]) /* 0x40012F00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[157]) /* 0x40012F40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[158]) /* 0x40012F80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[159]) /* 0x40012FC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[160]) /* 0x40013000 */ +#define PERI_MS_PPU_FX_HSIOM_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[161]) /* 0x40013040 */ +#define PERI_MS_PPU_FX_HSIOM_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[162]) /* 0x40013080 */ +#define PERI_MS_PPU_FX_HSIOM_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[163]) /* 0x400130C0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[164]) /* 0x40013100 */ +#define PERI_MS_PPU_FX_HSIOM_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[165]) /* 0x40013140 */ +#define PERI_MS_PPU_FX_HSIOM_AMUX ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[166]) /* 0x40013180 */ +#define PERI_MS_PPU_FX_HSIOM_MON ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[167]) /* 0x400131C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[168]) /* 0x40013200 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[169]) /* 0x40013240 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[170]) /* 0x40013280 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[171]) /* 0x400132C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[172]) /* 0x40013300 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[173]) /* 0x40013340 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[174]) /* 0x40013380 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[175]) /* 0x400133C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[176]) /* 0x40013400 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[177]) /* 0x40013440 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[178]) /* 0x40013480 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[179]) /* 0x400134C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[180]) /* 0x40013500 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[181]) /* 0x40013540 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[182]) /* 0x40013580 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[183]) /* 0x400135C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[184]) /* 0x40013600 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[185]) /* 0x40013640 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[186]) /* 0x40013680 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[187]) /* 0x400136C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[188]) /* 0x40013700 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[189]) /* 0x40013740 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[190]) /* 0x40013780 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[191]) /* 0x400137C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[192]) /* 0x40013800 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[193]) /* 0x40013840 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[194]) /* 0x40013880 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[195]) /* 0x400138C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[196]) /* 0x40013900 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[197]) /* 0x40013940 */ +#define PERI_MS_PPU_FX_GPIO_GPIO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[198]) /* 0x40013980 */ +#define PERI_MS_PPU_FX_GPIO_TEST ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[199]) /* 0x400139C0 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[200]) /* 0x40013A00 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[201]) /* 0x40013A40 */ +#define PERI_MS_PPU_FX_LPCOMP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[202]) /* 0x40013A80 */ +#define PERI_MS_PPU_FX_CSD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[203]) /* 0x40013AC0 */ +#define PERI_MS_PPU_FX_TCPWM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[204]) /* 0x40013B00 */ +#define PERI_MS_PPU_FX_TCPWM1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[205]) /* 0x40013B40 */ +#define PERI_MS_PPU_FX_LCD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[206]) /* 0x40013B80 */ +#define PERI_MS_PPU_FX_USBFS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[207]) /* 0x40013BC0 */ +#define PERI_MS_PPU_FX_SMIF0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[208]) /* 0x40013C00 */ +#define PERI_MS_PPU_FX_SDHC0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[209]) /* 0x40013C40 */ +#define PERI_MS_PPU_FX_CANFD0_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[210]) /* 0x40013C80 */ +#define PERI_MS_PPU_FX_CANFD0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[211]) /* 0x40013CC0 */ +#define PERI_MS_PPU_FX_CANFD0_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[212]) /* 0x40013D00 */ +#define PERI_MS_PPU_FX_SCB0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[213]) /* 0x40013D40 */ +#define PERI_MS_PPU_FX_SCB1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[214]) /* 0x40013D80 */ +#define PERI_MS_PPU_FX_SCB2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[215]) /* 0x40013DC0 */ +#define PERI_MS_PPU_FX_SCB3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[216]) /* 0x40013E00 */ +#define PERI_MS_PPU_FX_SCB4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[217]) /* 0x40013E40 */ +#define PERI_MS_PPU_FX_SCB5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[218]) /* 0x40013E80 */ +#define PERI_MS_PPU_FX_SCB6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[219]) /* 0x40013EC0 */ + +/******************************************************************************* +* CRYPTO +*******************************************************************************/ + +#define CRYPTO_BASE 0x40100000UL +#define CRYPTO ((CRYPTO_Type*) CRYPTO_BASE) /* 0x40100000 */ + +/******************************************************************************* +* CPUSS +*******************************************************************************/ + +#define CPUSS_BASE 0x40200000UL +#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40200000 */ + +/******************************************************************************* +* FAULT +*******************************************************************************/ + +#define FAULT_BASE 0x40210000UL +#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40210000 */ +#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40210000 */ +#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40210100 */ + +/******************************************************************************* +* IPC +*******************************************************************************/ + +#define IPC_BASE 0x40220000UL +#define IPC ((IPC_Type*) IPC_BASE) /* 0x40220000 */ +#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40220000 */ +#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40220020 */ +#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40220040 */ +#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40220060 */ +#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40220080 */ +#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402200A0 */ +#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402200C0 */ +#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402200E0 */ +#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40220100 */ +#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40220120 */ +#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40220140 */ +#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40220160 */ +#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40220180 */ +#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402201A0 */ +#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402201C0 */ +#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402201E0 */ +#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40221000 */ +#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40221020 */ +#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40221040 */ +#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40221060 */ +#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40221080 */ +#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402210A0 */ +#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402210C0 */ +#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402210E0 */ +#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40221100 */ +#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40221120 */ +#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40221140 */ +#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40221160 */ +#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40221180 */ +#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402211A0 */ +#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402211C0 */ +#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402211E0 */ + +/******************************************************************************* +* PROT +*******************************************************************************/ + +#define PROT_BASE 0x40230000UL +#define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ +#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ +#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ +#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402320C0 */ +#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40232100 */ +#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40232140 */ +#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40232180 */ +#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402321C0 */ +#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40232200 */ +#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40232240 */ +#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40232280 */ +#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402322C0 */ +#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40232300 */ +#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ +#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ +#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ +#define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ +#define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ +#define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ +#define PROT_MPU5_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[3]) /* 0x40235660 */ +#define PROT_MPU5_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[4]) /* 0x40235680 */ +#define PROT_MPU5_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[5]) /* 0x402356A0 */ +#define PROT_MPU5_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[6]) /* 0x402356C0 */ +#define PROT_MPU5_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[7]) /* 0x402356E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ + +/******************************************************************************* +* FLASHC +*******************************************************************************/ + +#define FLASHC_BASE 0x40240000UL +#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40240000 */ +#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4024F000 */ + +/******************************************************************************* +* SRSS +*******************************************************************************/ + +#define SRSS_BASE 0x40260000UL +#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ +#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */ +#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */ + +/******************************************************************************* +* BACKUP +*******************************************************************************/ + +#define BACKUP_BASE 0x40270000UL +#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ + +/******************************************************************************* +* DW +*******************************************************************************/ + +#define DW0_BASE 0x40280000UL +#define DW1_BASE 0x40290000UL +#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ +#define DW1 ((DW_Type*) DW1_BASE) /* 0x40290000 */ +#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40288000 */ +#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40288040 */ +#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40288080 */ +#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x402880C0 */ +#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40288100 */ +#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x40288140 */ +#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x40288180 */ +#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402881C0 */ +#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40288200 */ +#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40288240 */ +#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40288280 */ +#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x402882C0 */ +#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40288300 */ +#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x40288340 */ +#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x40288380 */ +#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402883C0 */ +#define DW0_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[16]) /* 0x40288400 */ +#define DW0_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[17]) /* 0x40288440 */ +#define DW0_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[18]) /* 0x40288480 */ +#define DW0_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[19]) /* 0x402884C0 */ +#define DW0_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[20]) /* 0x40288500 */ +#define DW0_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[21]) /* 0x40288540 */ +#define DW0_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[22]) /* 0x40288580 */ +#define DW0_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[23]) /* 0x402885C0 */ +#define DW0_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[24]) /* 0x40288600 */ +#define DW0_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[25]) /* 0x40288640 */ +#define DW0_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[26]) /* 0x40288680 */ +#define DW0_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[27]) /* 0x402886C0 */ +#define DW0_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[28]) /* 0x40288700 */ +#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40298000 */ +#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40298040 */ +#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40298080 */ +#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x402980C0 */ +#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40298100 */ +#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x40298140 */ +#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x40298180 */ +#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402981C0 */ +#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40298200 */ +#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40298240 */ +#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40298280 */ +#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x402982C0 */ +#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40298300 */ +#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x40298340 */ +#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x40298380 */ +#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402983C0 */ +#define DW1_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[16]) /* 0x40298400 */ +#define DW1_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[17]) /* 0x40298440 */ +#define DW1_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[18]) /* 0x40298480 */ +#define DW1_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[19]) /* 0x402984C0 */ +#define DW1_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[20]) /* 0x40298500 */ +#define DW1_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[21]) /* 0x40298540 */ +#define DW1_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[22]) /* 0x40298580 */ +#define DW1_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[23]) /* 0x402985C0 */ +#define DW1_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[24]) /* 0x40298600 */ +#define DW1_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[25]) /* 0x40298640 */ +#define DW1_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[26]) /* 0x40298680 */ +#define DW1_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[27]) /* 0x402986C0 */ +#define DW1_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[28]) /* 0x40298700 */ +#define DW1_CH_STRUCT29 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[29]) /* 0x40298740 */ +#define DW1_CH_STRUCT30 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[30]) /* 0x40298780 */ +#define DW1_CH_STRUCT31 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[31]) /* 0x402987C0 */ + +/******************************************************************************* +* DMAC +*******************************************************************************/ + +#define DMAC_BASE 0x402A0000UL +#define DMAC ((DMAC_Type*) DMAC_BASE) /* 0x402A0000 */ +#define DMAC_CH0 ((DMAC_CH_Type*) &DMAC->CH[0]) /* 0x402A1000 */ +#define DMAC_CH1 ((DMAC_CH_Type*) &DMAC->CH[1]) /* 0x402A1100 */ + +/******************************************************************************* +* EFUSE +*******************************************************************************/ + +#define EFUSE_BASE 0x402C0000UL +#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ + +/******************************************************************************* +* HSIOM +*******************************************************************************/ + +#define HSIOM_BASE 0x40300000UL +#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40300000 */ +#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40300000 */ +#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40300010 */ +#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40300020 */ +#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40300030 */ +#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40300040 */ +#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40300050 */ +#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40300060 */ +#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40300070 */ +#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40300080 */ +#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40300090 */ +#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403000A0 */ +#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403000B0 */ +#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403000C0 */ +#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403000D0 */ +#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403000E0 */ + +/******************************************************************************* +* GPIO +*******************************************************************************/ + +#define GPIO_BASE 0x40310000UL +#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40310000 */ +#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40310000 */ +#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40310080 */ +#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40310100 */ +#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40310180 */ +#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40310200 */ +#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40310280 */ +#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40310300 */ +#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40310380 */ +#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40310400 */ +#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40310480 */ +#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40310500 */ +#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40310580 */ +#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40310600 */ +#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40310680 */ +#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40310700 */ + +/******************************************************************************* +* SMARTIO +*******************************************************************************/ + +#define SMARTIO_BASE 0x40320000UL +#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40320000 */ +#define SMARTIO_PRT8 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[8]) /* 0x40320800 */ +#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40320900 */ + +/******************************************************************************* +* LPCOMP +*******************************************************************************/ + +#define LPCOMP_BASE 0x40350000UL +#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */ + +/******************************************************************************* +* CSD +*******************************************************************************/ + +#define CSD0_BASE 0x40360000UL +#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */ + +/******************************************************************************* +* TCPWM +*******************************************************************************/ + +#define TCPWM0_BASE 0x40380000UL +#define TCPWM1_BASE 0x40390000UL +#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM1 ((TCPWM_Type*) TCPWM1_BASE) /* 0x40390000 */ +#define TCPWM0_CNT0 ((TCPWM_CNT_Type*) &TCPWM0->CNT[0]) /* 0x40380100 */ +#define TCPWM0_CNT1 ((TCPWM_CNT_Type*) &TCPWM0->CNT[1]) /* 0x40380140 */ +#define TCPWM0_CNT2 ((TCPWM_CNT_Type*) &TCPWM0->CNT[2]) /* 0x40380180 */ +#define TCPWM0_CNT3 ((TCPWM_CNT_Type*) &TCPWM0->CNT[3]) /* 0x403801C0 */ +#define TCPWM1_CNT0 ((TCPWM_CNT_Type*) &TCPWM1->CNT[0]) /* 0x40390100 */ +#define TCPWM1_CNT1 ((TCPWM_CNT_Type*) &TCPWM1->CNT[1]) /* 0x40390140 */ +#define TCPWM1_CNT2 ((TCPWM_CNT_Type*) &TCPWM1->CNT[2]) /* 0x40390180 */ +#define TCPWM1_CNT3 ((TCPWM_CNT_Type*) &TCPWM1->CNT[3]) /* 0x403901C0 */ +#define TCPWM1_CNT4 ((TCPWM_CNT_Type*) &TCPWM1->CNT[4]) /* 0x40390200 */ +#define TCPWM1_CNT5 ((TCPWM_CNT_Type*) &TCPWM1->CNT[5]) /* 0x40390240 */ +#define TCPWM1_CNT6 ((TCPWM_CNT_Type*) &TCPWM1->CNT[6]) /* 0x40390280 */ +#define TCPWM1_CNT7 ((TCPWM_CNT_Type*) &TCPWM1->CNT[7]) /* 0x403902C0 */ + +/******************************************************************************* +* LCD +*******************************************************************************/ + +#define LCD0_BASE 0x403B0000UL +#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ + +/******************************************************************************* +* SMIF +*******************************************************************************/ + +#define SMIF0_BASE 0x40420000UL +#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ +#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ +#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ +#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ + +/******************************************************************************* +* SDHC +*******************************************************************************/ + +#define SDHC0_BASE 0x40460000UL +#define SDHC0 ((SDHC_Type*) SDHC0_BASE) /* 0x40460000 */ +#define SDHC0_WRAP ((SDHC_WRAP_Type*) &SDHC0->WRAP) /* 0x40460000 */ +#define SDHC0_CORE ((SDHC_CORE_Type*) &SDHC0->CORE) /* 0x40461000 */ + +/******************************************************************************* +* CANFD +*******************************************************************************/ + +#define CANFD0_BASE 0x40520000UL +#define CANFD0 ((CANFD_Type*) CANFD0_BASE) /* 0x40520000 */ +#define CANFD0_CH0 ((CANFD_CH_Type*) &CANFD0->CH[0]) /* 0x40520000 */ +#define CANFD0_CH0_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[0].M_TTCAN) /* 0x40520000 */ + +/******************************************************************************* +* SCB +*******************************************************************************/ + +#define SCB0_BASE 0x40600000UL +#define SCB1_BASE 0x40610000UL +#define SCB2_BASE 0x40620000UL +#define SCB3_BASE 0x40630000UL +#define SCB4_BASE 0x40640000UL +#define SCB5_BASE 0x40650000UL +#define SCB6_BASE 0x40660000UL +#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40600000 */ +#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40610000 */ +#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40620000 */ +#define SCB3 ((CySCB_Type*) SCB3_BASE) /* 0x40630000 */ +#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40640000 */ +#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40650000 */ +#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40660000 */ + +/******************************************************************************* +* SAR +*******************************************************************************/ + +#define SAR_BASE 0x409D0000UL +#define SAR ((SAR_Type*) SAR_BASE) /* 0x409D0000 */ + +/******************************************************************************* +* PASS +*******************************************************************************/ + +#define PASS_BASE 0x409F0000UL +#define PASS ((PASS_Type*) PASS_BASE) /* 0x409F0000 */ +#define PASS_AREF ((PASS_AREF_Type*) &PASS->AREF) /* 0x409F0E00 */ + +/** \} CY8C6145FNI-S3F71 */ + +#endif /* _CY8C6145FNI_S3F71_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6145lqi_s3f02.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6145lqi_s3f02.h new file mode 100644 index 0000000000..70e31314d9 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6145lqi_s3f02.h @@ -0,0 +1,983 @@ +/***************************************************************************//** +* \file cy8c6145lqi_s3f02.h +* +* \brief +* CY8C6145LQI-S3F02 device header +* +* \note +* Generator version: 1.6.0.225 +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CY8C6145LQI_S3F02_H_ +#define _CY8C6145LQI_S3F02_H_ + +/** +* \addtogroup group_device CY8C6145LQI-S3F02 +* \{ +*/ + +/** +* \addtogroup Configuration_of_CMSIS +* \{ +*/ + +/******************************************************************************* +* Interrupt Number Definition +*******************************************************************************/ + +typedef enum { + /* ARM Cortex-M4 Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C6145LQI-S3F02 Peripheral Interrupt Numbers */ + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_6_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #6 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + canfd_0_interrupt0_IRQn = 168, /*!< 168 [Active] Can #0, Consolidated interrupt #0 */ + canfd_0_interrupts0_0_IRQn = 169, /*!< 169 [Active] CAN #0, Interrupt #0, Channel #0 */ + canfd_0_interrupts1_0_IRQn = 170, /*!< 170 [Active] CAN #0, Interrupt #1, Channel #0 */ + cpuss_interrupts_dw1_29_IRQn = 171, /*!< 171 [Active] CPUSS DataWire #1, Channel #29 */ + cpuss_interrupts_dw1_30_IRQn = 172, /*!< 172 [Active] CPUSS DataWire #1, Channel #30 */ + cpuss_interrupts_dw1_31_IRQn = 173, /*!< 173 [Active] CPUSS DataWire #1, Channel #31 */ + unconnected_IRQn = 240 /*!< 240 Unconnected */ +} IRQn_Type; + + +/******************************************************************************* +* Processor and Core Peripheral Section +*******************************************************************************/ + +/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __CM0P_PRESENT 0 /*!< CM0P present or not */ +#define __DTCM_PRESENT 0 /*!< DTCM present or not */ +#define __ICACHE_PRESENT 0 /*!< ICACHE present or not */ +#define __DCACHE_PRESENT 0 /*!< DCACHE present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + + +/* Memory Blocks */ +#define CY_ROM_BASE 0x00000000UL +#define CY_ROM_SIZE 0x00010000UL +#define CY_SRAM_BASE 0x08000000UL +#define CY_SRAM_SIZE 0x00040000UL +#define CY_FLASH_BASE 0x10000000UL +#define CY_FLASH_SIZE 0x00080000UL +#define CY_EM_EEPROM_BASE 0x14000000UL +#define CY_EM_EEPROM_SIZE 0x00008000UL +#define CY_SFLASH_BASE 0x16000000UL +#define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL +#define CY_EFUSE_BASE 0x402C0800UL +#define CY_EFUSE_SIZE 0x00000200UL +#define CY_CAN0MRAM_BASE 0x40530000UL +#define CY_CAN0MRAM_SIZE 0x00010000UL + +#include "system_psoc6.h" /*!< PSoC 6 System */ + +/* IP List */ +#define CY_IP_MXTTCANFD 1u +#define CY_IP_MXTTCANFD_INSTANCES 1u +#define CY_IP_MXTTCANFD_VERSION 1u +#define CY_IP_M4CPUSS 1u +#define CY_IP_M4CPUSS_INSTANCES 1u +#define CY_IP_M4CPUSS_VERSION 2u +#define CY_IP_M4CPUSS_DMAC 1u +#define CY_IP_M4CPUSS_DMAC_INSTANCES 1u +#define CY_IP_M4CPUSS_DMAC_VERSION 2u +#define CY_IP_M4CPUSS_DMA 1u +#define CY_IP_M4CPUSS_DMA_INSTANCES 2u +#define CY_IP_M4CPUSS_DMA_VERSION 2u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 2u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u +#define CY_IP_MXS40PASS 1u +#define CY_IP_MXS40PASS_INSTANCES 1u +#define CY_IP_MXS40PASS_VERSION 1u +#define CY_IP_MXS40PASS_SAR 1u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u +#define CY_IP_MXS40PASS_SAR_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 7u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 1u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u + +#include "psoc6_03_config.h" +#include "gpio_psoc6_03_68_qfn.h" + +#define CY_DEVICE_PSOC6A512K +#define CY_SILICON_ID 0xE71B1105UL +#define CY_HF_CLK_MAX_FREQ 150000000UL + +#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL + +/******************************************************************************* +* SFLASH +*******************************************************************************/ + +#define SFLASH_BASE 0x16000000UL +#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */ + +/******************************************************************************* +* PERI +*******************************************************************************/ + +#define PERI_BASE 0x40000000UL +#define PERI ((PERI_Type*) PERI_BASE) /* 0x40000000 */ +#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40004000 */ +#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40004020 */ +#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40004040 */ +#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x40004060 */ +#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40004080 */ +#define PERI_GR5 ((PERI_GR_Type*) &PERI->GR[5]) /* 0x400040A0 */ +#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x400040C0 */ +#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40004120 */ +#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40008000 */ +#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40008400 */ +#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40008800 */ +#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40008C00 */ +#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40009000 */ +#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40009400 */ +#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40009800 */ +#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40009C00 */ +#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ +#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ +#define PERI_TR_GR10 ((PERI_TR_GR_Type*) &PERI->TR_GR[10]) /* 0x4000A800 */ +#define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ +#define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ +#define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ +#define PERI_TR_1TO1_GR3 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[3]) /* 0x4000CC00 */ +#define PERI_TR_1TO1_GR4 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[4]) /* 0x4000D000 */ +#define PERI_TR_1TO1_GR5 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[5]) /* 0x4000D400 */ +#define PERI_TR_1TO1_GR6 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[6]) /* 0x4000D800 */ +#define PERI_TR_1TO1_GR7 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[7]) /* 0x4000DC00 */ + +/******************************************************************************* +* PERI_MS +*******************************************************************************/ + +#define PERI_MS_BASE 0x40010000UL +#define PERI_MS ((PERI_MS_Type*) PERI_MS_BASE) /* 0x40010000 */ +#define PERI_MS_PPU_PR0 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[0]) /* 0x40010000 */ +#define PERI_MS_PPU_PR1 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[1]) /* 0x40010040 */ +#define PERI_MS_PPU_PR2 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[2]) /* 0x40010080 */ +#define PERI_MS_PPU_PR3 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[3]) /* 0x400100C0 */ +#define PERI_MS_PPU_PR4 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[4]) /* 0x40010100 */ +#define PERI_MS_PPU_PR5 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[5]) /* 0x40010140 */ +#define PERI_MS_PPU_PR6 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[6]) /* 0x40010180 */ +#define PERI_MS_PPU_PR7 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[7]) /* 0x400101C0 */ +#define PERI_MS_PPU_FX_PERI_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[0]) /* 0x40010800 */ +#define PERI_MS_PPU_FX_PERI_GR0_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[1]) /* 0x40010840 */ +#define PERI_MS_PPU_FX_PERI_GR1_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[2]) /* 0x40010880 */ +#define PERI_MS_PPU_FX_PERI_GR2_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[3]) /* 0x400108C0 */ +#define PERI_MS_PPU_FX_PERI_GR3_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[4]) /* 0x40010900 */ +#define PERI_MS_PPU_FX_PERI_GR4_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[5]) /* 0x40010940 */ +#define PERI_MS_PPU_FX_PERI_GR5_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[6]) /* 0x40010980 */ +#define PERI_MS_PPU_FX_PERI_GR6_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[7]) /* 0x400109C0 */ +#define PERI_MS_PPU_FX_PERI_GR9_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[8]) /* 0x40010A00 */ +#define PERI_MS_PPU_FX_PERI_TR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[9]) /* 0x40010A40 */ +#define PERI_MS_PPU_FX_CRYPTO_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[10]) /* 0x40010A80 */ +#define PERI_MS_PPU_FX_CRYPTO_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[11]) /* 0x40010AC0 */ +#define PERI_MS_PPU_FX_CRYPTO_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[12]) /* 0x40010B00 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[13]) /* 0x40010B40 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[14]) /* 0x40010B80 */ +#define PERI_MS_PPU_FX_CRYPTO_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[15]) /* 0x40010BC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[16]) /* 0x40010C00 */ +#define PERI_MS_PPU_FX_CPUSS_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[17]) /* 0x40010C40 */ +#define PERI_MS_PPU_FX_CPUSS_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[18]) /* 0x40010C80 */ +#define PERI_MS_PPU_FX_CPUSS_CM0_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[19]) /* 0x40010CC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[20]) /* 0x40010D00 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[21]) /* 0x40010D40 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT1_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[22]) /* 0x40010D80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT0_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[23]) /* 0x40010DC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT1_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[24]) /* 0x40010E00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT2_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[25]) /* 0x40010E40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT3_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[26]) /* 0x40010E80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT4_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[27]) /* 0x40010EC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT5_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[28]) /* 0x40010F00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT6_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[29]) /* 0x40010F40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT7_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[30]) /* 0x40010F80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT8_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[31]) /* 0x40010FC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT9_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[32]) /* 0x40011000 */ +#define PERI_MS_PPU_FX_IPC_STRUCT10_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[33]) /* 0x40011040 */ +#define PERI_MS_PPU_FX_IPC_STRUCT11_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[34]) /* 0x40011080 */ +#define PERI_MS_PPU_FX_IPC_STRUCT12_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[35]) /* 0x400110C0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT13_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[36]) /* 0x40011100 */ +#define PERI_MS_PPU_FX_IPC_STRUCT14_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[37]) /* 0x40011140 */ +#define PERI_MS_PPU_FX_IPC_STRUCT15_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[38]) /* 0x40011180 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT0_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[39]) /* 0x400111C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT1_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[40]) /* 0x40011200 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT2_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[41]) /* 0x40011240 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT3_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[42]) /* 0x40011280 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT4_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[43]) /* 0x400112C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT5_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[44]) /* 0x40011300 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT6_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[45]) /* 0x40011340 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT7_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[46]) /* 0x40011380 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT8_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[47]) /* 0x400113C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT9_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[48]) /* 0x40011400 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT10_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[49]) /* 0x40011440 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT11_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[50]) /* 0x40011480 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT12_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[51]) /* 0x400114C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT13_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[52]) /* 0x40011500 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT14_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[53]) /* 0x40011540 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT15_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[54]) /* 0x40011580 */ +#define PERI_MS_PPU_FX_PROT_SMPU_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[55]) /* 0x400115C0 */ +#define PERI_MS_PPU_FX_PROT_MPU0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[56]) /* 0x40011600 */ +#define PERI_MS_PPU_FX_PROT_MPU5_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[57]) /* 0x40011640 */ +#define PERI_MS_PPU_FX_PROT_MPU14_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[58]) /* 0x40011680 */ +#define PERI_MS_PPU_FX_PROT_MPU15_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[59]) /* 0x400116C0 */ +#define PERI_MS_PPU_FX_FLASHC_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[60]) /* 0x40011700 */ +#define PERI_MS_PPU_FX_FLASHC_CMD ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[61]) /* 0x40011740 */ +#define PERI_MS_PPU_FX_FLASHC_DFT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[62]) /* 0x40011780 */ +#define PERI_MS_PPU_FX_FLASHC_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[63]) /* 0x400117C0 */ +#define PERI_MS_PPU_FX_FLASHC_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[64]) /* 0x40011800 */ +#define PERI_MS_PPU_FX_FLASHC_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[65]) /* 0x40011840 */ +#define PERI_MS_PPU_FX_FLASHC_DW0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[66]) /* 0x40011880 */ +#define PERI_MS_PPU_FX_FLASHC_DW1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[67]) /* 0x400118C0 */ +#define PERI_MS_PPU_FX_FLASHC_DMAC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[68]) /* 0x40011900 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[69]) /* 0x40011940 */ +#define PERI_MS_PPU_FX_FLASHC_FM ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[70]) /* 0x40011980 */ +#define PERI_MS_PPU_FX_SRSS_MAIN1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[71]) /* 0x400119C0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[72]) /* 0x40011A00 */ +#define PERI_MS_PPU_FX_WDT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[73]) /* 0x40011A40 */ +#define PERI_MS_PPU_FX_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[74]) /* 0x40011A80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[75]) /* 0x40011AC0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[76]) /* 0x40011B00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[77]) /* 0x40011B40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[78]) /* 0x40011B80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[79]) /* 0x40011BC0 */ +#define PERI_MS_PPU_FX_BACKUP_BACKUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[80]) /* 0x40011C00 */ +#define PERI_MS_PPU_FX_DW0_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[81]) /* 0x40011C40 */ +#define PERI_MS_PPU_FX_DW1_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[82]) /* 0x40011C80 */ +#define PERI_MS_PPU_FX_DW0_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[83]) /* 0x40011CC0 */ +#define PERI_MS_PPU_FX_DW1_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[84]) /* 0x40011D00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[85]) /* 0x40011D40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[86]) /* 0x40011D80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[87]) /* 0x40011DC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[88]) /* 0x40011E00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[89]) /* 0x40011E40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[90]) /* 0x40011E80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[91]) /* 0x40011EC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[92]) /* 0x40011F00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[93]) /* 0x40011F40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[94]) /* 0x40011F80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[95]) /* 0x40011FC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[96]) /* 0x40012000 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[97]) /* 0x40012040 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[98]) /* 0x40012080 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[99]) /* 0x400120C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[100]) /* 0x40012100 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[101]) /* 0x40012140 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[102]) /* 0x40012180 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[103]) /* 0x400121C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[104]) /* 0x40012200 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[105]) /* 0x40012240 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[106]) /* 0x40012280 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[107]) /* 0x400122C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[108]) /* 0x40012300 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[109]) /* 0x40012340 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[110]) /* 0x40012380 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[111]) /* 0x400123C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[112]) /* 0x40012400 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[113]) /* 0x40012440 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[114]) /* 0x40012480 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[115]) /* 0x400124C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[116]) /* 0x40012500 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[117]) /* 0x40012540 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[118]) /* 0x40012580 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[119]) /* 0x400125C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[120]) /* 0x40012600 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[121]) /* 0x40012640 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[122]) /* 0x40012680 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[123]) /* 0x400126C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[124]) /* 0x40012700 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[125]) /* 0x40012740 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[126]) /* 0x40012780 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[127]) /* 0x400127C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[128]) /* 0x40012800 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[129]) /* 0x40012840 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[130]) /* 0x40012880 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[131]) /* 0x400128C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[132]) /* 0x40012900 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[133]) /* 0x40012940 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[134]) /* 0x40012980 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[135]) /* 0x400129C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[136]) /* 0x40012A00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[137]) /* 0x40012A40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[138]) /* 0x40012A80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[139]) /* 0x40012AC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[140]) /* 0x40012B00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[141]) /* 0x40012B40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[142]) /* 0x40012B80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT29_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[143]) /* 0x40012BC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT30_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[144]) /* 0x40012C00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT31_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[145]) /* 0x40012C40 */ +#define PERI_MS_PPU_FX_DMAC_TOP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[146]) /* 0x40012C80 */ +#define PERI_MS_PPU_FX_DMAC_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[147]) /* 0x40012CC0 */ +#define PERI_MS_PPU_FX_DMAC_CH1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[148]) /* 0x40012D00 */ +#define PERI_MS_PPU_FX_EFUSE_CTL ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[149]) /* 0x40012D40 */ +#define PERI_MS_PPU_FX_EFUSE_DATA ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[150]) /* 0x40012D80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[151]) /* 0x40012DC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[152]) /* 0x40012E00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[153]) /* 0x40012E40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[154]) /* 0x40012E80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[155]) /* 0x40012EC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[156]) /* 0x40012F00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[157]) /* 0x40012F40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[158]) /* 0x40012F80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[159]) /* 0x40012FC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[160]) /* 0x40013000 */ +#define PERI_MS_PPU_FX_HSIOM_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[161]) /* 0x40013040 */ +#define PERI_MS_PPU_FX_HSIOM_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[162]) /* 0x40013080 */ +#define PERI_MS_PPU_FX_HSIOM_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[163]) /* 0x400130C0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[164]) /* 0x40013100 */ +#define PERI_MS_PPU_FX_HSIOM_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[165]) /* 0x40013140 */ +#define PERI_MS_PPU_FX_HSIOM_AMUX ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[166]) /* 0x40013180 */ +#define PERI_MS_PPU_FX_HSIOM_MON ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[167]) /* 0x400131C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[168]) /* 0x40013200 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[169]) /* 0x40013240 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[170]) /* 0x40013280 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[171]) /* 0x400132C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[172]) /* 0x40013300 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[173]) /* 0x40013340 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[174]) /* 0x40013380 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[175]) /* 0x400133C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[176]) /* 0x40013400 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[177]) /* 0x40013440 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[178]) /* 0x40013480 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[179]) /* 0x400134C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[180]) /* 0x40013500 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[181]) /* 0x40013540 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[182]) /* 0x40013580 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[183]) /* 0x400135C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[184]) /* 0x40013600 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[185]) /* 0x40013640 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[186]) /* 0x40013680 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[187]) /* 0x400136C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[188]) /* 0x40013700 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[189]) /* 0x40013740 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[190]) /* 0x40013780 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[191]) /* 0x400137C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[192]) /* 0x40013800 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[193]) /* 0x40013840 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[194]) /* 0x40013880 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[195]) /* 0x400138C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[196]) /* 0x40013900 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[197]) /* 0x40013940 */ +#define PERI_MS_PPU_FX_GPIO_GPIO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[198]) /* 0x40013980 */ +#define PERI_MS_PPU_FX_GPIO_TEST ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[199]) /* 0x400139C0 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[200]) /* 0x40013A00 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[201]) /* 0x40013A40 */ +#define PERI_MS_PPU_FX_LPCOMP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[202]) /* 0x40013A80 */ +#define PERI_MS_PPU_FX_CSD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[203]) /* 0x40013AC0 */ +#define PERI_MS_PPU_FX_TCPWM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[204]) /* 0x40013B00 */ +#define PERI_MS_PPU_FX_TCPWM1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[205]) /* 0x40013B40 */ +#define PERI_MS_PPU_FX_LCD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[206]) /* 0x40013B80 */ +#define PERI_MS_PPU_FX_USBFS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[207]) /* 0x40013BC0 */ +#define PERI_MS_PPU_FX_SMIF0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[208]) /* 0x40013C00 */ +#define PERI_MS_PPU_FX_SDHC0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[209]) /* 0x40013C40 */ +#define PERI_MS_PPU_FX_CANFD0_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[210]) /* 0x40013C80 */ +#define PERI_MS_PPU_FX_CANFD0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[211]) /* 0x40013CC0 */ +#define PERI_MS_PPU_FX_CANFD0_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[212]) /* 0x40013D00 */ +#define PERI_MS_PPU_FX_SCB0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[213]) /* 0x40013D40 */ +#define PERI_MS_PPU_FX_SCB1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[214]) /* 0x40013D80 */ +#define PERI_MS_PPU_FX_SCB2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[215]) /* 0x40013DC0 */ +#define PERI_MS_PPU_FX_SCB3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[216]) /* 0x40013E00 */ +#define PERI_MS_PPU_FX_SCB4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[217]) /* 0x40013E40 */ +#define PERI_MS_PPU_FX_SCB5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[218]) /* 0x40013E80 */ +#define PERI_MS_PPU_FX_SCB6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[219]) /* 0x40013EC0 */ + +/******************************************************************************* +* CPUSS +*******************************************************************************/ + +#define CPUSS_BASE 0x40200000UL +#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40200000 */ + +/******************************************************************************* +* FAULT +*******************************************************************************/ + +#define FAULT_BASE 0x40210000UL +#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40210000 */ +#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40210000 */ +#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40210100 */ + +/******************************************************************************* +* IPC +*******************************************************************************/ + +#define IPC_BASE 0x40220000UL +#define IPC ((IPC_Type*) IPC_BASE) /* 0x40220000 */ +#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40220000 */ +#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40220020 */ +#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40220040 */ +#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40220060 */ +#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40220080 */ +#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402200A0 */ +#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402200C0 */ +#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402200E0 */ +#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40220100 */ +#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40220120 */ +#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40220140 */ +#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40220160 */ +#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40220180 */ +#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402201A0 */ +#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402201C0 */ +#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402201E0 */ +#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40221000 */ +#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40221020 */ +#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40221040 */ +#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40221060 */ +#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40221080 */ +#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402210A0 */ +#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402210C0 */ +#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402210E0 */ +#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40221100 */ +#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40221120 */ +#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40221140 */ +#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40221160 */ +#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40221180 */ +#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402211A0 */ +#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402211C0 */ +#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402211E0 */ + +/******************************************************************************* +* PROT +*******************************************************************************/ + +#define PROT_BASE 0x40230000UL +#define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ +#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ +#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ +#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402320C0 */ +#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40232100 */ +#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40232140 */ +#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40232180 */ +#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402321C0 */ +#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40232200 */ +#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40232240 */ +#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40232280 */ +#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402322C0 */ +#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40232300 */ +#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ +#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ +#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ +#define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ +#define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ +#define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ +#define PROT_MPU5_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[3]) /* 0x40235660 */ +#define PROT_MPU5_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[4]) /* 0x40235680 */ +#define PROT_MPU5_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[5]) /* 0x402356A0 */ +#define PROT_MPU5_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[6]) /* 0x402356C0 */ +#define PROT_MPU5_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[7]) /* 0x402356E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ + +/******************************************************************************* +* FLASHC +*******************************************************************************/ + +#define FLASHC_BASE 0x40240000UL +#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40240000 */ +#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4024F000 */ + +/******************************************************************************* +* SRSS +*******************************************************************************/ + +#define SRSS_BASE 0x40260000UL +#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ +#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */ +#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */ + +/******************************************************************************* +* BACKUP +*******************************************************************************/ + +#define BACKUP_BASE 0x40270000UL +#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ + +/******************************************************************************* +* DW +*******************************************************************************/ + +#define DW0_BASE 0x40280000UL +#define DW1_BASE 0x40290000UL +#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ +#define DW1 ((DW_Type*) DW1_BASE) /* 0x40290000 */ +#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40288000 */ +#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40288040 */ +#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40288080 */ +#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x402880C0 */ +#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40288100 */ +#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x40288140 */ +#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x40288180 */ +#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402881C0 */ +#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40288200 */ +#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40288240 */ +#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40288280 */ +#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x402882C0 */ +#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40288300 */ +#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x40288340 */ +#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x40288380 */ +#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402883C0 */ +#define DW0_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[16]) /* 0x40288400 */ +#define DW0_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[17]) /* 0x40288440 */ +#define DW0_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[18]) /* 0x40288480 */ +#define DW0_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[19]) /* 0x402884C0 */ +#define DW0_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[20]) /* 0x40288500 */ +#define DW0_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[21]) /* 0x40288540 */ +#define DW0_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[22]) /* 0x40288580 */ +#define DW0_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[23]) /* 0x402885C0 */ +#define DW0_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[24]) /* 0x40288600 */ +#define DW0_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[25]) /* 0x40288640 */ +#define DW0_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[26]) /* 0x40288680 */ +#define DW0_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[27]) /* 0x402886C0 */ +#define DW0_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[28]) /* 0x40288700 */ +#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40298000 */ +#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40298040 */ +#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40298080 */ +#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x402980C0 */ +#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40298100 */ +#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x40298140 */ +#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x40298180 */ +#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402981C0 */ +#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40298200 */ +#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40298240 */ +#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40298280 */ +#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x402982C0 */ +#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40298300 */ +#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x40298340 */ +#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x40298380 */ +#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402983C0 */ +#define DW1_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[16]) /* 0x40298400 */ +#define DW1_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[17]) /* 0x40298440 */ +#define DW1_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[18]) /* 0x40298480 */ +#define DW1_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[19]) /* 0x402984C0 */ +#define DW1_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[20]) /* 0x40298500 */ +#define DW1_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[21]) /* 0x40298540 */ +#define DW1_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[22]) /* 0x40298580 */ +#define DW1_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[23]) /* 0x402985C0 */ +#define DW1_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[24]) /* 0x40298600 */ +#define DW1_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[25]) /* 0x40298640 */ +#define DW1_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[26]) /* 0x40298680 */ +#define DW1_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[27]) /* 0x402986C0 */ +#define DW1_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[28]) /* 0x40298700 */ +#define DW1_CH_STRUCT29 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[29]) /* 0x40298740 */ +#define DW1_CH_STRUCT30 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[30]) /* 0x40298780 */ +#define DW1_CH_STRUCT31 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[31]) /* 0x402987C0 */ + +/******************************************************************************* +* DMAC +*******************************************************************************/ + +#define DMAC_BASE 0x402A0000UL +#define DMAC ((DMAC_Type*) DMAC_BASE) /* 0x402A0000 */ +#define DMAC_CH0 ((DMAC_CH_Type*) &DMAC->CH[0]) /* 0x402A1000 */ +#define DMAC_CH1 ((DMAC_CH_Type*) &DMAC->CH[1]) /* 0x402A1100 */ + +/******************************************************************************* +* EFUSE +*******************************************************************************/ + +#define EFUSE_BASE 0x402C0000UL +#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ + +/******************************************************************************* +* HSIOM +*******************************************************************************/ + +#define HSIOM_BASE 0x40300000UL +#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40300000 */ +#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40300000 */ +#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40300010 */ +#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40300020 */ +#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40300030 */ +#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40300040 */ +#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40300050 */ +#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40300060 */ +#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40300070 */ +#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40300080 */ +#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40300090 */ +#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403000A0 */ +#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403000B0 */ +#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403000C0 */ +#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403000D0 */ +#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403000E0 */ + +/******************************************************************************* +* GPIO +*******************************************************************************/ + +#define GPIO_BASE 0x40310000UL +#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40310000 */ +#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40310000 */ +#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40310080 */ +#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40310100 */ +#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40310180 */ +#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40310200 */ +#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40310280 */ +#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40310300 */ +#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40310380 */ +#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40310400 */ +#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40310480 */ +#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40310500 */ +#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40310580 */ +#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40310600 */ +#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40310680 */ +#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40310700 */ + +/******************************************************************************* +* SMARTIO +*******************************************************************************/ + +#define SMARTIO_BASE 0x40320000UL +#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40320000 */ +#define SMARTIO_PRT8 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[8]) /* 0x40320800 */ +#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40320900 */ + +/******************************************************************************* +* LPCOMP +*******************************************************************************/ + +#define LPCOMP_BASE 0x40350000UL +#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */ + +/******************************************************************************* +* CSD +*******************************************************************************/ + +#define CSD0_BASE 0x40360000UL +#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */ + +/******************************************************************************* +* TCPWM +*******************************************************************************/ + +#define TCPWM0_BASE 0x40380000UL +#define TCPWM1_BASE 0x40390000UL +#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM1 ((TCPWM_Type*) TCPWM1_BASE) /* 0x40390000 */ +#define TCPWM0_CNT0 ((TCPWM_CNT_Type*) &TCPWM0->CNT[0]) /* 0x40380100 */ +#define TCPWM0_CNT1 ((TCPWM_CNT_Type*) &TCPWM0->CNT[1]) /* 0x40380140 */ +#define TCPWM0_CNT2 ((TCPWM_CNT_Type*) &TCPWM0->CNT[2]) /* 0x40380180 */ +#define TCPWM0_CNT3 ((TCPWM_CNT_Type*) &TCPWM0->CNT[3]) /* 0x403801C0 */ +#define TCPWM1_CNT0 ((TCPWM_CNT_Type*) &TCPWM1->CNT[0]) /* 0x40390100 */ +#define TCPWM1_CNT1 ((TCPWM_CNT_Type*) &TCPWM1->CNT[1]) /* 0x40390140 */ +#define TCPWM1_CNT2 ((TCPWM_CNT_Type*) &TCPWM1->CNT[2]) /* 0x40390180 */ +#define TCPWM1_CNT3 ((TCPWM_CNT_Type*) &TCPWM1->CNT[3]) /* 0x403901C0 */ +#define TCPWM1_CNT4 ((TCPWM_CNT_Type*) &TCPWM1->CNT[4]) /* 0x40390200 */ +#define TCPWM1_CNT5 ((TCPWM_CNT_Type*) &TCPWM1->CNT[5]) /* 0x40390240 */ +#define TCPWM1_CNT6 ((TCPWM_CNT_Type*) &TCPWM1->CNT[6]) /* 0x40390280 */ +#define TCPWM1_CNT7 ((TCPWM_CNT_Type*) &TCPWM1->CNT[7]) /* 0x403902C0 */ + +/******************************************************************************* +* LCD +*******************************************************************************/ + +#define LCD0_BASE 0x403B0000UL +#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ + +/******************************************************************************* +* USBFS +*******************************************************************************/ + +#define USBFS0_BASE 0x403F0000UL +#define USBFS0 ((USBFS_Type*) USBFS0_BASE) /* 0x403F0000 */ +#define USBFS0_USBDEV ((USBFS_USBDEV_Type*) &USBFS0->USBDEV) /* 0x403F0000 */ +#define USBFS0_USBLPM ((USBFS_USBLPM_Type*) &USBFS0->USBLPM) /* 0x403F2000 */ +#define USBFS0_USBHOST ((USBFS_USBHOST_Type*) &USBFS0->USBHOST) /* 0x403F4000 */ + +/******************************************************************************* +* SMIF +*******************************************************************************/ + +#define SMIF0_BASE 0x40420000UL +#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ +#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ +#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ +#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ + +/******************************************************************************* +* SDHC +*******************************************************************************/ + +#define SDHC0_BASE 0x40460000UL +#define SDHC0 ((SDHC_Type*) SDHC0_BASE) /* 0x40460000 */ +#define SDHC0_WRAP ((SDHC_WRAP_Type*) &SDHC0->WRAP) /* 0x40460000 */ +#define SDHC0_CORE ((SDHC_CORE_Type*) &SDHC0->CORE) /* 0x40461000 */ + +/******************************************************************************* +* CANFD +*******************************************************************************/ + +#define CANFD0_BASE 0x40520000UL +#define CANFD0 ((CANFD_Type*) CANFD0_BASE) /* 0x40520000 */ +#define CANFD0_CH0 ((CANFD_CH_Type*) &CANFD0->CH[0]) /* 0x40520000 */ +#define CANFD0_CH0_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[0].M_TTCAN) /* 0x40520000 */ + +/******************************************************************************* +* SCB +*******************************************************************************/ + +#define SCB0_BASE 0x40600000UL +#define SCB1_BASE 0x40610000UL +#define SCB2_BASE 0x40620000UL +#define SCB3_BASE 0x40630000UL +#define SCB4_BASE 0x40640000UL +#define SCB5_BASE 0x40650000UL +#define SCB6_BASE 0x40660000UL +#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40600000 */ +#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40610000 */ +#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40620000 */ +#define SCB3 ((CySCB_Type*) SCB3_BASE) /* 0x40630000 */ +#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40640000 */ +#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40650000 */ +#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40660000 */ + +/******************************************************************************* +* SAR +*******************************************************************************/ + +#define SAR_BASE 0x409D0000UL +#define SAR ((SAR_Type*) SAR_BASE) /* 0x409D0000 */ + +/******************************************************************************* +* PASS +*******************************************************************************/ + +#define PASS_BASE 0x409F0000UL +#define PASS ((PASS_Type*) PASS_BASE) /* 0x409F0000 */ +#define PASS_AREF ((PASS_AREF_Type*) &PASS->AREF) /* 0x409F0E00 */ + +/** \} CY8C6145LQI-S3F02 */ + +#endif /* _CY8C6145LQI_S3F02_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6145lqi_s3f12.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6145lqi_s3f12.h new file mode 100644 index 0000000000..551b9fbb77 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6145lqi_s3f12.h @@ -0,0 +1,983 @@ +/***************************************************************************//** +* \file cy8c6145lqi_s3f12.h +* +* \brief +* CY8C6145LQI-S3F12 device header +* +* \note +* Generator version: 1.6.0.225 +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CY8C6145LQI_S3F12_H_ +#define _CY8C6145LQI_S3F12_H_ + +/** +* \addtogroup group_device CY8C6145LQI-S3F12 +* \{ +*/ + +/** +* \addtogroup Configuration_of_CMSIS +* \{ +*/ + +/******************************************************************************* +* Interrupt Number Definition +*******************************************************************************/ + +typedef enum { + /* ARM Cortex-M4 Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C6145LQI-S3F12 Peripheral Interrupt Numbers */ + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_6_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #6 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + canfd_0_interrupt0_IRQn = 168, /*!< 168 [Active] Can #0, Consolidated interrupt #0 */ + canfd_0_interrupts0_0_IRQn = 169, /*!< 169 [Active] CAN #0, Interrupt #0, Channel #0 */ + canfd_0_interrupts1_0_IRQn = 170, /*!< 170 [Active] CAN #0, Interrupt #1, Channel #0 */ + cpuss_interrupts_dw1_29_IRQn = 171, /*!< 171 [Active] CPUSS DataWire #1, Channel #29 */ + cpuss_interrupts_dw1_30_IRQn = 172, /*!< 172 [Active] CPUSS DataWire #1, Channel #30 */ + cpuss_interrupts_dw1_31_IRQn = 173, /*!< 173 [Active] CPUSS DataWire #1, Channel #31 */ + unconnected_IRQn = 240 /*!< 240 Unconnected */ +} IRQn_Type; + + +/******************************************************************************* +* Processor and Core Peripheral Section +*******************************************************************************/ + +/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __CM0P_PRESENT 0 /*!< CM0P present or not */ +#define __DTCM_PRESENT 0 /*!< DTCM present or not */ +#define __ICACHE_PRESENT 0 /*!< ICACHE present or not */ +#define __DCACHE_PRESENT 0 /*!< DCACHE present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + + +/* Memory Blocks */ +#define CY_ROM_BASE 0x00000000UL +#define CY_ROM_SIZE 0x00010000UL +#define CY_SRAM_BASE 0x08000000UL +#define CY_SRAM_SIZE 0x00040000UL +#define CY_FLASH_BASE 0x10000000UL +#define CY_FLASH_SIZE 0x00080000UL +#define CY_EM_EEPROM_BASE 0x14000000UL +#define CY_EM_EEPROM_SIZE 0x00008000UL +#define CY_SFLASH_BASE 0x16000000UL +#define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL +#define CY_EFUSE_BASE 0x402C0800UL +#define CY_EFUSE_SIZE 0x00000200UL +#define CY_CAN0MRAM_BASE 0x40530000UL +#define CY_CAN0MRAM_SIZE 0x00010000UL + +#include "system_psoc6.h" /*!< PSoC 6 System */ + +/* IP List */ +#define CY_IP_MXTTCANFD 1u +#define CY_IP_MXTTCANFD_INSTANCES 1u +#define CY_IP_MXTTCANFD_VERSION 1u +#define CY_IP_M4CPUSS 1u +#define CY_IP_M4CPUSS_INSTANCES 1u +#define CY_IP_M4CPUSS_VERSION 2u +#define CY_IP_M4CPUSS_DMAC 1u +#define CY_IP_M4CPUSS_DMAC_INSTANCES 1u +#define CY_IP_M4CPUSS_DMAC_VERSION 2u +#define CY_IP_M4CPUSS_DMA 1u +#define CY_IP_M4CPUSS_DMA_INSTANCES 2u +#define CY_IP_M4CPUSS_DMA_VERSION 2u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 2u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u +#define CY_IP_MXS40PASS 1u +#define CY_IP_MXS40PASS_INSTANCES 1u +#define CY_IP_MXS40PASS_VERSION 1u +#define CY_IP_MXS40PASS_SAR 1u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u +#define CY_IP_MXS40PASS_SAR_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 7u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 1u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u + +#include "psoc6_03_config.h" +#include "gpio_psoc6_03_68_qfn.h" + +#define CY_DEVICE_PSOC6A512K +#define CY_SILICON_ID 0xE7181105UL +#define CY_HF_CLK_MAX_FREQ 150000000UL + +#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL + +/******************************************************************************* +* SFLASH +*******************************************************************************/ + +#define SFLASH_BASE 0x16000000UL +#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */ + +/******************************************************************************* +* PERI +*******************************************************************************/ + +#define PERI_BASE 0x40000000UL +#define PERI ((PERI_Type*) PERI_BASE) /* 0x40000000 */ +#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40004000 */ +#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40004020 */ +#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40004040 */ +#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x40004060 */ +#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40004080 */ +#define PERI_GR5 ((PERI_GR_Type*) &PERI->GR[5]) /* 0x400040A0 */ +#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x400040C0 */ +#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40004120 */ +#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40008000 */ +#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40008400 */ +#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40008800 */ +#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40008C00 */ +#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40009000 */ +#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40009400 */ +#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40009800 */ +#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40009C00 */ +#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ +#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ +#define PERI_TR_GR10 ((PERI_TR_GR_Type*) &PERI->TR_GR[10]) /* 0x4000A800 */ +#define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ +#define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ +#define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ +#define PERI_TR_1TO1_GR3 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[3]) /* 0x4000CC00 */ +#define PERI_TR_1TO1_GR4 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[4]) /* 0x4000D000 */ +#define PERI_TR_1TO1_GR5 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[5]) /* 0x4000D400 */ +#define PERI_TR_1TO1_GR6 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[6]) /* 0x4000D800 */ +#define PERI_TR_1TO1_GR7 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[7]) /* 0x4000DC00 */ + +/******************************************************************************* +* PERI_MS +*******************************************************************************/ + +#define PERI_MS_BASE 0x40010000UL +#define PERI_MS ((PERI_MS_Type*) PERI_MS_BASE) /* 0x40010000 */ +#define PERI_MS_PPU_PR0 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[0]) /* 0x40010000 */ +#define PERI_MS_PPU_PR1 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[1]) /* 0x40010040 */ +#define PERI_MS_PPU_PR2 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[2]) /* 0x40010080 */ +#define PERI_MS_PPU_PR3 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[3]) /* 0x400100C0 */ +#define PERI_MS_PPU_PR4 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[4]) /* 0x40010100 */ +#define PERI_MS_PPU_PR5 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[5]) /* 0x40010140 */ +#define PERI_MS_PPU_PR6 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[6]) /* 0x40010180 */ +#define PERI_MS_PPU_PR7 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[7]) /* 0x400101C0 */ +#define PERI_MS_PPU_FX_PERI_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[0]) /* 0x40010800 */ +#define PERI_MS_PPU_FX_PERI_GR0_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[1]) /* 0x40010840 */ +#define PERI_MS_PPU_FX_PERI_GR1_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[2]) /* 0x40010880 */ +#define PERI_MS_PPU_FX_PERI_GR2_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[3]) /* 0x400108C0 */ +#define PERI_MS_PPU_FX_PERI_GR3_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[4]) /* 0x40010900 */ +#define PERI_MS_PPU_FX_PERI_GR4_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[5]) /* 0x40010940 */ +#define PERI_MS_PPU_FX_PERI_GR5_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[6]) /* 0x40010980 */ +#define PERI_MS_PPU_FX_PERI_GR6_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[7]) /* 0x400109C0 */ +#define PERI_MS_PPU_FX_PERI_GR9_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[8]) /* 0x40010A00 */ +#define PERI_MS_PPU_FX_PERI_TR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[9]) /* 0x40010A40 */ +#define PERI_MS_PPU_FX_CRYPTO_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[10]) /* 0x40010A80 */ +#define PERI_MS_PPU_FX_CRYPTO_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[11]) /* 0x40010AC0 */ +#define PERI_MS_PPU_FX_CRYPTO_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[12]) /* 0x40010B00 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[13]) /* 0x40010B40 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[14]) /* 0x40010B80 */ +#define PERI_MS_PPU_FX_CRYPTO_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[15]) /* 0x40010BC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[16]) /* 0x40010C00 */ +#define PERI_MS_PPU_FX_CPUSS_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[17]) /* 0x40010C40 */ +#define PERI_MS_PPU_FX_CPUSS_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[18]) /* 0x40010C80 */ +#define PERI_MS_PPU_FX_CPUSS_CM0_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[19]) /* 0x40010CC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[20]) /* 0x40010D00 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[21]) /* 0x40010D40 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT1_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[22]) /* 0x40010D80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT0_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[23]) /* 0x40010DC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT1_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[24]) /* 0x40010E00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT2_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[25]) /* 0x40010E40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT3_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[26]) /* 0x40010E80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT4_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[27]) /* 0x40010EC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT5_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[28]) /* 0x40010F00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT6_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[29]) /* 0x40010F40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT7_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[30]) /* 0x40010F80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT8_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[31]) /* 0x40010FC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT9_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[32]) /* 0x40011000 */ +#define PERI_MS_PPU_FX_IPC_STRUCT10_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[33]) /* 0x40011040 */ +#define PERI_MS_PPU_FX_IPC_STRUCT11_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[34]) /* 0x40011080 */ +#define PERI_MS_PPU_FX_IPC_STRUCT12_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[35]) /* 0x400110C0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT13_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[36]) /* 0x40011100 */ +#define PERI_MS_PPU_FX_IPC_STRUCT14_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[37]) /* 0x40011140 */ +#define PERI_MS_PPU_FX_IPC_STRUCT15_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[38]) /* 0x40011180 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT0_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[39]) /* 0x400111C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT1_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[40]) /* 0x40011200 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT2_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[41]) /* 0x40011240 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT3_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[42]) /* 0x40011280 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT4_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[43]) /* 0x400112C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT5_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[44]) /* 0x40011300 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT6_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[45]) /* 0x40011340 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT7_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[46]) /* 0x40011380 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT8_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[47]) /* 0x400113C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT9_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[48]) /* 0x40011400 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT10_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[49]) /* 0x40011440 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT11_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[50]) /* 0x40011480 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT12_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[51]) /* 0x400114C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT13_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[52]) /* 0x40011500 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT14_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[53]) /* 0x40011540 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT15_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[54]) /* 0x40011580 */ +#define PERI_MS_PPU_FX_PROT_SMPU_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[55]) /* 0x400115C0 */ +#define PERI_MS_PPU_FX_PROT_MPU0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[56]) /* 0x40011600 */ +#define PERI_MS_PPU_FX_PROT_MPU5_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[57]) /* 0x40011640 */ +#define PERI_MS_PPU_FX_PROT_MPU14_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[58]) /* 0x40011680 */ +#define PERI_MS_PPU_FX_PROT_MPU15_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[59]) /* 0x400116C0 */ +#define PERI_MS_PPU_FX_FLASHC_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[60]) /* 0x40011700 */ +#define PERI_MS_PPU_FX_FLASHC_CMD ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[61]) /* 0x40011740 */ +#define PERI_MS_PPU_FX_FLASHC_DFT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[62]) /* 0x40011780 */ +#define PERI_MS_PPU_FX_FLASHC_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[63]) /* 0x400117C0 */ +#define PERI_MS_PPU_FX_FLASHC_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[64]) /* 0x40011800 */ +#define PERI_MS_PPU_FX_FLASHC_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[65]) /* 0x40011840 */ +#define PERI_MS_PPU_FX_FLASHC_DW0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[66]) /* 0x40011880 */ +#define PERI_MS_PPU_FX_FLASHC_DW1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[67]) /* 0x400118C0 */ +#define PERI_MS_PPU_FX_FLASHC_DMAC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[68]) /* 0x40011900 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[69]) /* 0x40011940 */ +#define PERI_MS_PPU_FX_FLASHC_FM ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[70]) /* 0x40011980 */ +#define PERI_MS_PPU_FX_SRSS_MAIN1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[71]) /* 0x400119C0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[72]) /* 0x40011A00 */ +#define PERI_MS_PPU_FX_WDT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[73]) /* 0x40011A40 */ +#define PERI_MS_PPU_FX_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[74]) /* 0x40011A80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[75]) /* 0x40011AC0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[76]) /* 0x40011B00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[77]) /* 0x40011B40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[78]) /* 0x40011B80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[79]) /* 0x40011BC0 */ +#define PERI_MS_PPU_FX_BACKUP_BACKUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[80]) /* 0x40011C00 */ +#define PERI_MS_PPU_FX_DW0_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[81]) /* 0x40011C40 */ +#define PERI_MS_PPU_FX_DW1_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[82]) /* 0x40011C80 */ +#define PERI_MS_PPU_FX_DW0_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[83]) /* 0x40011CC0 */ +#define PERI_MS_PPU_FX_DW1_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[84]) /* 0x40011D00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[85]) /* 0x40011D40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[86]) /* 0x40011D80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[87]) /* 0x40011DC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[88]) /* 0x40011E00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[89]) /* 0x40011E40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[90]) /* 0x40011E80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[91]) /* 0x40011EC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[92]) /* 0x40011F00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[93]) /* 0x40011F40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[94]) /* 0x40011F80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[95]) /* 0x40011FC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[96]) /* 0x40012000 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[97]) /* 0x40012040 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[98]) /* 0x40012080 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[99]) /* 0x400120C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[100]) /* 0x40012100 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[101]) /* 0x40012140 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[102]) /* 0x40012180 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[103]) /* 0x400121C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[104]) /* 0x40012200 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[105]) /* 0x40012240 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[106]) /* 0x40012280 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[107]) /* 0x400122C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[108]) /* 0x40012300 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[109]) /* 0x40012340 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[110]) /* 0x40012380 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[111]) /* 0x400123C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[112]) /* 0x40012400 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[113]) /* 0x40012440 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[114]) /* 0x40012480 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[115]) /* 0x400124C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[116]) /* 0x40012500 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[117]) /* 0x40012540 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[118]) /* 0x40012580 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[119]) /* 0x400125C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[120]) /* 0x40012600 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[121]) /* 0x40012640 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[122]) /* 0x40012680 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[123]) /* 0x400126C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[124]) /* 0x40012700 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[125]) /* 0x40012740 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[126]) /* 0x40012780 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[127]) /* 0x400127C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[128]) /* 0x40012800 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[129]) /* 0x40012840 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[130]) /* 0x40012880 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[131]) /* 0x400128C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[132]) /* 0x40012900 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[133]) /* 0x40012940 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[134]) /* 0x40012980 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[135]) /* 0x400129C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[136]) /* 0x40012A00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[137]) /* 0x40012A40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[138]) /* 0x40012A80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[139]) /* 0x40012AC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[140]) /* 0x40012B00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[141]) /* 0x40012B40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[142]) /* 0x40012B80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT29_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[143]) /* 0x40012BC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT30_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[144]) /* 0x40012C00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT31_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[145]) /* 0x40012C40 */ +#define PERI_MS_PPU_FX_DMAC_TOP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[146]) /* 0x40012C80 */ +#define PERI_MS_PPU_FX_DMAC_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[147]) /* 0x40012CC0 */ +#define PERI_MS_PPU_FX_DMAC_CH1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[148]) /* 0x40012D00 */ +#define PERI_MS_PPU_FX_EFUSE_CTL ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[149]) /* 0x40012D40 */ +#define PERI_MS_PPU_FX_EFUSE_DATA ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[150]) /* 0x40012D80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[151]) /* 0x40012DC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[152]) /* 0x40012E00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[153]) /* 0x40012E40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[154]) /* 0x40012E80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[155]) /* 0x40012EC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[156]) /* 0x40012F00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[157]) /* 0x40012F40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[158]) /* 0x40012F80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[159]) /* 0x40012FC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[160]) /* 0x40013000 */ +#define PERI_MS_PPU_FX_HSIOM_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[161]) /* 0x40013040 */ +#define PERI_MS_PPU_FX_HSIOM_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[162]) /* 0x40013080 */ +#define PERI_MS_PPU_FX_HSIOM_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[163]) /* 0x400130C0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[164]) /* 0x40013100 */ +#define PERI_MS_PPU_FX_HSIOM_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[165]) /* 0x40013140 */ +#define PERI_MS_PPU_FX_HSIOM_AMUX ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[166]) /* 0x40013180 */ +#define PERI_MS_PPU_FX_HSIOM_MON ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[167]) /* 0x400131C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[168]) /* 0x40013200 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[169]) /* 0x40013240 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[170]) /* 0x40013280 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[171]) /* 0x400132C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[172]) /* 0x40013300 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[173]) /* 0x40013340 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[174]) /* 0x40013380 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[175]) /* 0x400133C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[176]) /* 0x40013400 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[177]) /* 0x40013440 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[178]) /* 0x40013480 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[179]) /* 0x400134C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[180]) /* 0x40013500 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[181]) /* 0x40013540 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[182]) /* 0x40013580 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[183]) /* 0x400135C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[184]) /* 0x40013600 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[185]) /* 0x40013640 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[186]) /* 0x40013680 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[187]) /* 0x400136C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[188]) /* 0x40013700 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[189]) /* 0x40013740 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[190]) /* 0x40013780 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[191]) /* 0x400137C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[192]) /* 0x40013800 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[193]) /* 0x40013840 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[194]) /* 0x40013880 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[195]) /* 0x400138C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[196]) /* 0x40013900 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[197]) /* 0x40013940 */ +#define PERI_MS_PPU_FX_GPIO_GPIO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[198]) /* 0x40013980 */ +#define PERI_MS_PPU_FX_GPIO_TEST ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[199]) /* 0x400139C0 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[200]) /* 0x40013A00 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[201]) /* 0x40013A40 */ +#define PERI_MS_PPU_FX_LPCOMP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[202]) /* 0x40013A80 */ +#define PERI_MS_PPU_FX_CSD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[203]) /* 0x40013AC0 */ +#define PERI_MS_PPU_FX_TCPWM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[204]) /* 0x40013B00 */ +#define PERI_MS_PPU_FX_TCPWM1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[205]) /* 0x40013B40 */ +#define PERI_MS_PPU_FX_LCD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[206]) /* 0x40013B80 */ +#define PERI_MS_PPU_FX_USBFS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[207]) /* 0x40013BC0 */ +#define PERI_MS_PPU_FX_SMIF0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[208]) /* 0x40013C00 */ +#define PERI_MS_PPU_FX_SDHC0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[209]) /* 0x40013C40 */ +#define PERI_MS_PPU_FX_CANFD0_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[210]) /* 0x40013C80 */ +#define PERI_MS_PPU_FX_CANFD0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[211]) /* 0x40013CC0 */ +#define PERI_MS_PPU_FX_CANFD0_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[212]) /* 0x40013D00 */ +#define PERI_MS_PPU_FX_SCB0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[213]) /* 0x40013D40 */ +#define PERI_MS_PPU_FX_SCB1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[214]) /* 0x40013D80 */ +#define PERI_MS_PPU_FX_SCB2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[215]) /* 0x40013DC0 */ +#define PERI_MS_PPU_FX_SCB3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[216]) /* 0x40013E00 */ +#define PERI_MS_PPU_FX_SCB4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[217]) /* 0x40013E40 */ +#define PERI_MS_PPU_FX_SCB5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[218]) /* 0x40013E80 */ +#define PERI_MS_PPU_FX_SCB6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[219]) /* 0x40013EC0 */ + +/******************************************************************************* +* CPUSS +*******************************************************************************/ + +#define CPUSS_BASE 0x40200000UL +#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40200000 */ + +/******************************************************************************* +* FAULT +*******************************************************************************/ + +#define FAULT_BASE 0x40210000UL +#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40210000 */ +#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40210000 */ +#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40210100 */ + +/******************************************************************************* +* IPC +*******************************************************************************/ + +#define IPC_BASE 0x40220000UL +#define IPC ((IPC_Type*) IPC_BASE) /* 0x40220000 */ +#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40220000 */ +#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40220020 */ +#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40220040 */ +#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40220060 */ +#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40220080 */ +#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402200A0 */ +#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402200C0 */ +#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402200E0 */ +#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40220100 */ +#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40220120 */ +#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40220140 */ +#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40220160 */ +#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40220180 */ +#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402201A0 */ +#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402201C0 */ +#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402201E0 */ +#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40221000 */ +#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40221020 */ +#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40221040 */ +#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40221060 */ +#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40221080 */ +#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402210A0 */ +#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402210C0 */ +#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402210E0 */ +#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40221100 */ +#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40221120 */ +#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40221140 */ +#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40221160 */ +#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40221180 */ +#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402211A0 */ +#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402211C0 */ +#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402211E0 */ + +/******************************************************************************* +* PROT +*******************************************************************************/ + +#define PROT_BASE 0x40230000UL +#define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ +#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ +#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ +#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402320C0 */ +#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40232100 */ +#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40232140 */ +#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40232180 */ +#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402321C0 */ +#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40232200 */ +#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40232240 */ +#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40232280 */ +#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402322C0 */ +#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40232300 */ +#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ +#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ +#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ +#define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ +#define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ +#define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ +#define PROT_MPU5_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[3]) /* 0x40235660 */ +#define PROT_MPU5_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[4]) /* 0x40235680 */ +#define PROT_MPU5_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[5]) /* 0x402356A0 */ +#define PROT_MPU5_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[6]) /* 0x402356C0 */ +#define PROT_MPU5_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[7]) /* 0x402356E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ + +/******************************************************************************* +* FLASHC +*******************************************************************************/ + +#define FLASHC_BASE 0x40240000UL +#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40240000 */ +#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4024F000 */ + +/******************************************************************************* +* SRSS +*******************************************************************************/ + +#define SRSS_BASE 0x40260000UL +#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ +#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */ +#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */ + +/******************************************************************************* +* BACKUP +*******************************************************************************/ + +#define BACKUP_BASE 0x40270000UL +#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ + +/******************************************************************************* +* DW +*******************************************************************************/ + +#define DW0_BASE 0x40280000UL +#define DW1_BASE 0x40290000UL +#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ +#define DW1 ((DW_Type*) DW1_BASE) /* 0x40290000 */ +#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40288000 */ +#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40288040 */ +#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40288080 */ +#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x402880C0 */ +#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40288100 */ +#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x40288140 */ +#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x40288180 */ +#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402881C0 */ +#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40288200 */ +#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40288240 */ +#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40288280 */ +#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x402882C0 */ +#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40288300 */ +#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x40288340 */ +#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x40288380 */ +#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402883C0 */ +#define DW0_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[16]) /* 0x40288400 */ +#define DW0_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[17]) /* 0x40288440 */ +#define DW0_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[18]) /* 0x40288480 */ +#define DW0_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[19]) /* 0x402884C0 */ +#define DW0_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[20]) /* 0x40288500 */ +#define DW0_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[21]) /* 0x40288540 */ +#define DW0_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[22]) /* 0x40288580 */ +#define DW0_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[23]) /* 0x402885C0 */ +#define DW0_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[24]) /* 0x40288600 */ +#define DW0_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[25]) /* 0x40288640 */ +#define DW0_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[26]) /* 0x40288680 */ +#define DW0_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[27]) /* 0x402886C0 */ +#define DW0_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[28]) /* 0x40288700 */ +#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40298000 */ +#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40298040 */ +#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40298080 */ +#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x402980C0 */ +#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40298100 */ +#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x40298140 */ +#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x40298180 */ +#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402981C0 */ +#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40298200 */ +#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40298240 */ +#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40298280 */ +#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x402982C0 */ +#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40298300 */ +#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x40298340 */ +#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x40298380 */ +#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402983C0 */ +#define DW1_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[16]) /* 0x40298400 */ +#define DW1_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[17]) /* 0x40298440 */ +#define DW1_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[18]) /* 0x40298480 */ +#define DW1_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[19]) /* 0x402984C0 */ +#define DW1_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[20]) /* 0x40298500 */ +#define DW1_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[21]) /* 0x40298540 */ +#define DW1_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[22]) /* 0x40298580 */ +#define DW1_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[23]) /* 0x402985C0 */ +#define DW1_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[24]) /* 0x40298600 */ +#define DW1_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[25]) /* 0x40298640 */ +#define DW1_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[26]) /* 0x40298680 */ +#define DW1_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[27]) /* 0x402986C0 */ +#define DW1_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[28]) /* 0x40298700 */ +#define DW1_CH_STRUCT29 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[29]) /* 0x40298740 */ +#define DW1_CH_STRUCT30 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[30]) /* 0x40298780 */ +#define DW1_CH_STRUCT31 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[31]) /* 0x402987C0 */ + +/******************************************************************************* +* DMAC +*******************************************************************************/ + +#define DMAC_BASE 0x402A0000UL +#define DMAC ((DMAC_Type*) DMAC_BASE) /* 0x402A0000 */ +#define DMAC_CH0 ((DMAC_CH_Type*) &DMAC->CH[0]) /* 0x402A1000 */ +#define DMAC_CH1 ((DMAC_CH_Type*) &DMAC->CH[1]) /* 0x402A1100 */ + +/******************************************************************************* +* EFUSE +*******************************************************************************/ + +#define EFUSE_BASE 0x402C0000UL +#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ + +/******************************************************************************* +* HSIOM +*******************************************************************************/ + +#define HSIOM_BASE 0x40300000UL +#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40300000 */ +#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40300000 */ +#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40300010 */ +#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40300020 */ +#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40300030 */ +#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40300040 */ +#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40300050 */ +#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40300060 */ +#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40300070 */ +#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40300080 */ +#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40300090 */ +#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403000A0 */ +#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403000B0 */ +#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403000C0 */ +#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403000D0 */ +#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403000E0 */ + +/******************************************************************************* +* GPIO +*******************************************************************************/ + +#define GPIO_BASE 0x40310000UL +#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40310000 */ +#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40310000 */ +#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40310080 */ +#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40310100 */ +#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40310180 */ +#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40310200 */ +#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40310280 */ +#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40310300 */ +#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40310380 */ +#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40310400 */ +#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40310480 */ +#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40310500 */ +#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40310580 */ +#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40310600 */ +#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40310680 */ +#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40310700 */ + +/******************************************************************************* +* SMARTIO +*******************************************************************************/ + +#define SMARTIO_BASE 0x40320000UL +#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40320000 */ +#define SMARTIO_PRT8 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[8]) /* 0x40320800 */ +#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40320900 */ + +/******************************************************************************* +* LPCOMP +*******************************************************************************/ + +#define LPCOMP_BASE 0x40350000UL +#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */ + +/******************************************************************************* +* CSD +*******************************************************************************/ + +#define CSD0_BASE 0x40360000UL +#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */ + +/******************************************************************************* +* TCPWM +*******************************************************************************/ + +#define TCPWM0_BASE 0x40380000UL +#define TCPWM1_BASE 0x40390000UL +#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM1 ((TCPWM_Type*) TCPWM1_BASE) /* 0x40390000 */ +#define TCPWM0_CNT0 ((TCPWM_CNT_Type*) &TCPWM0->CNT[0]) /* 0x40380100 */ +#define TCPWM0_CNT1 ((TCPWM_CNT_Type*) &TCPWM0->CNT[1]) /* 0x40380140 */ +#define TCPWM0_CNT2 ((TCPWM_CNT_Type*) &TCPWM0->CNT[2]) /* 0x40380180 */ +#define TCPWM0_CNT3 ((TCPWM_CNT_Type*) &TCPWM0->CNT[3]) /* 0x403801C0 */ +#define TCPWM1_CNT0 ((TCPWM_CNT_Type*) &TCPWM1->CNT[0]) /* 0x40390100 */ +#define TCPWM1_CNT1 ((TCPWM_CNT_Type*) &TCPWM1->CNT[1]) /* 0x40390140 */ +#define TCPWM1_CNT2 ((TCPWM_CNT_Type*) &TCPWM1->CNT[2]) /* 0x40390180 */ +#define TCPWM1_CNT3 ((TCPWM_CNT_Type*) &TCPWM1->CNT[3]) /* 0x403901C0 */ +#define TCPWM1_CNT4 ((TCPWM_CNT_Type*) &TCPWM1->CNT[4]) /* 0x40390200 */ +#define TCPWM1_CNT5 ((TCPWM_CNT_Type*) &TCPWM1->CNT[5]) /* 0x40390240 */ +#define TCPWM1_CNT6 ((TCPWM_CNT_Type*) &TCPWM1->CNT[6]) /* 0x40390280 */ +#define TCPWM1_CNT7 ((TCPWM_CNT_Type*) &TCPWM1->CNT[7]) /* 0x403902C0 */ + +/******************************************************************************* +* LCD +*******************************************************************************/ + +#define LCD0_BASE 0x403B0000UL +#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ + +/******************************************************************************* +* USBFS +*******************************************************************************/ + +#define USBFS0_BASE 0x403F0000UL +#define USBFS0 ((USBFS_Type*) USBFS0_BASE) /* 0x403F0000 */ +#define USBFS0_USBDEV ((USBFS_USBDEV_Type*) &USBFS0->USBDEV) /* 0x403F0000 */ +#define USBFS0_USBLPM ((USBFS_USBLPM_Type*) &USBFS0->USBLPM) /* 0x403F2000 */ +#define USBFS0_USBHOST ((USBFS_USBHOST_Type*) &USBFS0->USBHOST) /* 0x403F4000 */ + +/******************************************************************************* +* SMIF +*******************************************************************************/ + +#define SMIF0_BASE 0x40420000UL +#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ +#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ +#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ +#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ + +/******************************************************************************* +* SDHC +*******************************************************************************/ + +#define SDHC0_BASE 0x40460000UL +#define SDHC0 ((SDHC_Type*) SDHC0_BASE) /* 0x40460000 */ +#define SDHC0_WRAP ((SDHC_WRAP_Type*) &SDHC0->WRAP) /* 0x40460000 */ +#define SDHC0_CORE ((SDHC_CORE_Type*) &SDHC0->CORE) /* 0x40461000 */ + +/******************************************************************************* +* CANFD +*******************************************************************************/ + +#define CANFD0_BASE 0x40520000UL +#define CANFD0 ((CANFD_Type*) CANFD0_BASE) /* 0x40520000 */ +#define CANFD0_CH0 ((CANFD_CH_Type*) &CANFD0->CH[0]) /* 0x40520000 */ +#define CANFD0_CH0_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[0].M_TTCAN) /* 0x40520000 */ + +/******************************************************************************* +* SCB +*******************************************************************************/ + +#define SCB0_BASE 0x40600000UL +#define SCB1_BASE 0x40610000UL +#define SCB2_BASE 0x40620000UL +#define SCB3_BASE 0x40630000UL +#define SCB4_BASE 0x40640000UL +#define SCB5_BASE 0x40650000UL +#define SCB6_BASE 0x40660000UL +#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40600000 */ +#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40610000 */ +#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40620000 */ +#define SCB3 ((CySCB_Type*) SCB3_BASE) /* 0x40630000 */ +#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40640000 */ +#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40650000 */ +#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40660000 */ + +/******************************************************************************* +* SAR +*******************************************************************************/ + +#define SAR_BASE 0x409D0000UL +#define SAR ((SAR_Type*) SAR_BASE) /* 0x409D0000 */ + +/******************************************************************************* +* PASS +*******************************************************************************/ + +#define PASS_BASE 0x409F0000UL +#define PASS ((PASS_Type*) PASS_BASE) /* 0x409F0000 */ +#define PASS_AREF ((PASS_AREF_Type*) &PASS->AREF) /* 0x409F0E00 */ + +/** \} CY8C6145LQI-S3F12 */ + +#endif /* _CY8C6145LQI_S3F12_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6145lqi_s3f42.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6145lqi_s3f42.h new file mode 100644 index 0000000000..e43d30cdac --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6145lqi_s3f42.h @@ -0,0 +1,993 @@ +/***************************************************************************//** +* \file cy8c6145lqi_s3f42.h +* +* \brief +* CY8C6145LQI-S3F42 device header +* +* \note +* Generator version: 1.6.0.225 +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CY8C6145LQI_S3F42_H_ +#define _CY8C6145LQI_S3F42_H_ + +/** +* \addtogroup group_device CY8C6145LQI-S3F42 +* \{ +*/ + +/** +* \addtogroup Configuration_of_CMSIS +* \{ +*/ + +/******************************************************************************* +* Interrupt Number Definition +*******************************************************************************/ + +typedef enum { + /* ARM Cortex-M4 Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C6145LQI-S3F42 Peripheral Interrupt Numbers */ + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_6_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #6 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + canfd_0_interrupt0_IRQn = 168, /*!< 168 [Active] Can #0, Consolidated interrupt #0 */ + canfd_0_interrupts0_0_IRQn = 169, /*!< 169 [Active] CAN #0, Interrupt #0, Channel #0 */ + canfd_0_interrupts1_0_IRQn = 170, /*!< 170 [Active] CAN #0, Interrupt #1, Channel #0 */ + cpuss_interrupts_dw1_29_IRQn = 171, /*!< 171 [Active] CPUSS DataWire #1, Channel #29 */ + cpuss_interrupts_dw1_30_IRQn = 172, /*!< 172 [Active] CPUSS DataWire #1, Channel #30 */ + cpuss_interrupts_dw1_31_IRQn = 173, /*!< 173 [Active] CPUSS DataWire #1, Channel #31 */ + unconnected_IRQn = 240 /*!< 240 Unconnected */ +} IRQn_Type; + + +/******************************************************************************* +* Processor and Core Peripheral Section +*******************************************************************************/ + +/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __CM0P_PRESENT 0 /*!< CM0P present or not */ +#define __DTCM_PRESENT 0 /*!< DTCM present or not */ +#define __ICACHE_PRESENT 0 /*!< ICACHE present or not */ +#define __DCACHE_PRESENT 0 /*!< DCACHE present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + + +/* Memory Blocks */ +#define CY_ROM_BASE 0x00000000UL +#define CY_ROM_SIZE 0x00010000UL +#define CY_SRAM_BASE 0x08000000UL +#define CY_SRAM_SIZE 0x00040000UL +#define CY_FLASH_BASE 0x10000000UL +#define CY_FLASH_SIZE 0x00080000UL +#define CY_EM_EEPROM_BASE 0x14000000UL +#define CY_EM_EEPROM_SIZE 0x00008000UL +#define CY_SFLASH_BASE 0x16000000UL +#define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL +#define CY_EFUSE_BASE 0x402C0800UL +#define CY_EFUSE_SIZE 0x00000200UL +#define CY_CAN0MRAM_BASE 0x40530000UL +#define CY_CAN0MRAM_SIZE 0x00010000UL + +#include "system_psoc6.h" /*!< PSoC 6 System */ + +/* IP List */ +#define CY_IP_MXTTCANFD 1u +#define CY_IP_MXTTCANFD_INSTANCES 1u +#define CY_IP_MXTTCANFD_VERSION 1u +#define CY_IP_M4CPUSS 1u +#define CY_IP_M4CPUSS_INSTANCES 1u +#define CY_IP_M4CPUSS_VERSION 2u +#define CY_IP_M4CPUSS_DMAC 1u +#define CY_IP_M4CPUSS_DMAC_INSTANCES 1u +#define CY_IP_M4CPUSS_DMAC_VERSION 2u +#define CY_IP_M4CPUSS_DMA 1u +#define CY_IP_M4CPUSS_DMA_INSTANCES 2u +#define CY_IP_M4CPUSS_DMA_VERSION 2u +#define CY_IP_MXCRYPTO 1u +#define CY_IP_MXCRYPTO_INSTANCES 1u +#define CY_IP_MXCRYPTO_VERSION 2u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 2u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u +#define CY_IP_MXS40PASS 1u +#define CY_IP_MXS40PASS_INSTANCES 1u +#define CY_IP_MXS40PASS_VERSION 1u +#define CY_IP_MXS40PASS_SAR 1u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u +#define CY_IP_MXS40PASS_SAR_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 7u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 1u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u + +#include "psoc6_03_config.h" +#include "gpio_psoc6_03_68_qfn.h" + +#define CY_DEVICE_PSOC6A512K +#define CY_SILICON_ID 0xE7151105UL +#define CY_HF_CLK_MAX_FREQ 150000000UL + +#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL + +/******************************************************************************* +* SFLASH +*******************************************************************************/ + +#define SFLASH_BASE 0x16000000UL +#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */ + +/******************************************************************************* +* PERI +*******************************************************************************/ + +#define PERI_BASE 0x40000000UL +#define PERI ((PERI_Type*) PERI_BASE) /* 0x40000000 */ +#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40004000 */ +#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40004020 */ +#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40004040 */ +#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x40004060 */ +#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40004080 */ +#define PERI_GR5 ((PERI_GR_Type*) &PERI->GR[5]) /* 0x400040A0 */ +#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x400040C0 */ +#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40004120 */ +#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40008000 */ +#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40008400 */ +#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40008800 */ +#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40008C00 */ +#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40009000 */ +#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40009400 */ +#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40009800 */ +#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40009C00 */ +#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ +#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ +#define PERI_TR_GR10 ((PERI_TR_GR_Type*) &PERI->TR_GR[10]) /* 0x4000A800 */ +#define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ +#define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ +#define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ +#define PERI_TR_1TO1_GR3 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[3]) /* 0x4000CC00 */ +#define PERI_TR_1TO1_GR4 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[4]) /* 0x4000D000 */ +#define PERI_TR_1TO1_GR5 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[5]) /* 0x4000D400 */ +#define PERI_TR_1TO1_GR6 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[6]) /* 0x4000D800 */ +#define PERI_TR_1TO1_GR7 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[7]) /* 0x4000DC00 */ + +/******************************************************************************* +* PERI_MS +*******************************************************************************/ + +#define PERI_MS_BASE 0x40010000UL +#define PERI_MS ((PERI_MS_Type*) PERI_MS_BASE) /* 0x40010000 */ +#define PERI_MS_PPU_PR0 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[0]) /* 0x40010000 */ +#define PERI_MS_PPU_PR1 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[1]) /* 0x40010040 */ +#define PERI_MS_PPU_PR2 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[2]) /* 0x40010080 */ +#define PERI_MS_PPU_PR3 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[3]) /* 0x400100C0 */ +#define PERI_MS_PPU_PR4 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[4]) /* 0x40010100 */ +#define PERI_MS_PPU_PR5 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[5]) /* 0x40010140 */ +#define PERI_MS_PPU_PR6 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[6]) /* 0x40010180 */ +#define PERI_MS_PPU_PR7 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[7]) /* 0x400101C0 */ +#define PERI_MS_PPU_FX_PERI_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[0]) /* 0x40010800 */ +#define PERI_MS_PPU_FX_PERI_GR0_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[1]) /* 0x40010840 */ +#define PERI_MS_PPU_FX_PERI_GR1_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[2]) /* 0x40010880 */ +#define PERI_MS_PPU_FX_PERI_GR2_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[3]) /* 0x400108C0 */ +#define PERI_MS_PPU_FX_PERI_GR3_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[4]) /* 0x40010900 */ +#define PERI_MS_PPU_FX_PERI_GR4_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[5]) /* 0x40010940 */ +#define PERI_MS_PPU_FX_PERI_GR5_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[6]) /* 0x40010980 */ +#define PERI_MS_PPU_FX_PERI_GR6_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[7]) /* 0x400109C0 */ +#define PERI_MS_PPU_FX_PERI_GR9_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[8]) /* 0x40010A00 */ +#define PERI_MS_PPU_FX_PERI_TR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[9]) /* 0x40010A40 */ +#define PERI_MS_PPU_FX_CRYPTO_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[10]) /* 0x40010A80 */ +#define PERI_MS_PPU_FX_CRYPTO_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[11]) /* 0x40010AC0 */ +#define PERI_MS_PPU_FX_CRYPTO_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[12]) /* 0x40010B00 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[13]) /* 0x40010B40 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[14]) /* 0x40010B80 */ +#define PERI_MS_PPU_FX_CRYPTO_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[15]) /* 0x40010BC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[16]) /* 0x40010C00 */ +#define PERI_MS_PPU_FX_CPUSS_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[17]) /* 0x40010C40 */ +#define PERI_MS_PPU_FX_CPUSS_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[18]) /* 0x40010C80 */ +#define PERI_MS_PPU_FX_CPUSS_CM0_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[19]) /* 0x40010CC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[20]) /* 0x40010D00 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[21]) /* 0x40010D40 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT1_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[22]) /* 0x40010D80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT0_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[23]) /* 0x40010DC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT1_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[24]) /* 0x40010E00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT2_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[25]) /* 0x40010E40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT3_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[26]) /* 0x40010E80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT4_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[27]) /* 0x40010EC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT5_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[28]) /* 0x40010F00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT6_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[29]) /* 0x40010F40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT7_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[30]) /* 0x40010F80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT8_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[31]) /* 0x40010FC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT9_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[32]) /* 0x40011000 */ +#define PERI_MS_PPU_FX_IPC_STRUCT10_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[33]) /* 0x40011040 */ +#define PERI_MS_PPU_FX_IPC_STRUCT11_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[34]) /* 0x40011080 */ +#define PERI_MS_PPU_FX_IPC_STRUCT12_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[35]) /* 0x400110C0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT13_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[36]) /* 0x40011100 */ +#define PERI_MS_PPU_FX_IPC_STRUCT14_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[37]) /* 0x40011140 */ +#define PERI_MS_PPU_FX_IPC_STRUCT15_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[38]) /* 0x40011180 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT0_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[39]) /* 0x400111C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT1_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[40]) /* 0x40011200 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT2_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[41]) /* 0x40011240 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT3_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[42]) /* 0x40011280 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT4_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[43]) /* 0x400112C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT5_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[44]) /* 0x40011300 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT6_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[45]) /* 0x40011340 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT7_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[46]) /* 0x40011380 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT8_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[47]) /* 0x400113C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT9_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[48]) /* 0x40011400 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT10_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[49]) /* 0x40011440 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT11_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[50]) /* 0x40011480 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT12_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[51]) /* 0x400114C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT13_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[52]) /* 0x40011500 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT14_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[53]) /* 0x40011540 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT15_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[54]) /* 0x40011580 */ +#define PERI_MS_PPU_FX_PROT_SMPU_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[55]) /* 0x400115C0 */ +#define PERI_MS_PPU_FX_PROT_MPU0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[56]) /* 0x40011600 */ +#define PERI_MS_PPU_FX_PROT_MPU5_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[57]) /* 0x40011640 */ +#define PERI_MS_PPU_FX_PROT_MPU14_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[58]) /* 0x40011680 */ +#define PERI_MS_PPU_FX_PROT_MPU15_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[59]) /* 0x400116C0 */ +#define PERI_MS_PPU_FX_FLASHC_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[60]) /* 0x40011700 */ +#define PERI_MS_PPU_FX_FLASHC_CMD ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[61]) /* 0x40011740 */ +#define PERI_MS_PPU_FX_FLASHC_DFT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[62]) /* 0x40011780 */ +#define PERI_MS_PPU_FX_FLASHC_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[63]) /* 0x400117C0 */ +#define PERI_MS_PPU_FX_FLASHC_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[64]) /* 0x40011800 */ +#define PERI_MS_PPU_FX_FLASHC_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[65]) /* 0x40011840 */ +#define PERI_MS_PPU_FX_FLASHC_DW0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[66]) /* 0x40011880 */ +#define PERI_MS_PPU_FX_FLASHC_DW1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[67]) /* 0x400118C0 */ +#define PERI_MS_PPU_FX_FLASHC_DMAC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[68]) /* 0x40011900 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[69]) /* 0x40011940 */ +#define PERI_MS_PPU_FX_FLASHC_FM ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[70]) /* 0x40011980 */ +#define PERI_MS_PPU_FX_SRSS_MAIN1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[71]) /* 0x400119C0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[72]) /* 0x40011A00 */ +#define PERI_MS_PPU_FX_WDT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[73]) /* 0x40011A40 */ +#define PERI_MS_PPU_FX_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[74]) /* 0x40011A80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[75]) /* 0x40011AC0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[76]) /* 0x40011B00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[77]) /* 0x40011B40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[78]) /* 0x40011B80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[79]) /* 0x40011BC0 */ +#define PERI_MS_PPU_FX_BACKUP_BACKUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[80]) /* 0x40011C00 */ +#define PERI_MS_PPU_FX_DW0_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[81]) /* 0x40011C40 */ +#define PERI_MS_PPU_FX_DW1_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[82]) /* 0x40011C80 */ +#define PERI_MS_PPU_FX_DW0_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[83]) /* 0x40011CC0 */ +#define PERI_MS_PPU_FX_DW1_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[84]) /* 0x40011D00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[85]) /* 0x40011D40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[86]) /* 0x40011D80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[87]) /* 0x40011DC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[88]) /* 0x40011E00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[89]) /* 0x40011E40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[90]) /* 0x40011E80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[91]) /* 0x40011EC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[92]) /* 0x40011F00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[93]) /* 0x40011F40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[94]) /* 0x40011F80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[95]) /* 0x40011FC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[96]) /* 0x40012000 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[97]) /* 0x40012040 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[98]) /* 0x40012080 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[99]) /* 0x400120C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[100]) /* 0x40012100 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[101]) /* 0x40012140 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[102]) /* 0x40012180 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[103]) /* 0x400121C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[104]) /* 0x40012200 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[105]) /* 0x40012240 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[106]) /* 0x40012280 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[107]) /* 0x400122C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[108]) /* 0x40012300 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[109]) /* 0x40012340 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[110]) /* 0x40012380 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[111]) /* 0x400123C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[112]) /* 0x40012400 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[113]) /* 0x40012440 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[114]) /* 0x40012480 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[115]) /* 0x400124C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[116]) /* 0x40012500 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[117]) /* 0x40012540 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[118]) /* 0x40012580 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[119]) /* 0x400125C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[120]) /* 0x40012600 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[121]) /* 0x40012640 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[122]) /* 0x40012680 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[123]) /* 0x400126C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[124]) /* 0x40012700 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[125]) /* 0x40012740 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[126]) /* 0x40012780 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[127]) /* 0x400127C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[128]) /* 0x40012800 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[129]) /* 0x40012840 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[130]) /* 0x40012880 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[131]) /* 0x400128C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[132]) /* 0x40012900 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[133]) /* 0x40012940 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[134]) /* 0x40012980 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[135]) /* 0x400129C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[136]) /* 0x40012A00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[137]) /* 0x40012A40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[138]) /* 0x40012A80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[139]) /* 0x40012AC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[140]) /* 0x40012B00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[141]) /* 0x40012B40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[142]) /* 0x40012B80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT29_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[143]) /* 0x40012BC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT30_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[144]) /* 0x40012C00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT31_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[145]) /* 0x40012C40 */ +#define PERI_MS_PPU_FX_DMAC_TOP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[146]) /* 0x40012C80 */ +#define PERI_MS_PPU_FX_DMAC_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[147]) /* 0x40012CC0 */ +#define PERI_MS_PPU_FX_DMAC_CH1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[148]) /* 0x40012D00 */ +#define PERI_MS_PPU_FX_EFUSE_CTL ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[149]) /* 0x40012D40 */ +#define PERI_MS_PPU_FX_EFUSE_DATA ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[150]) /* 0x40012D80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[151]) /* 0x40012DC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[152]) /* 0x40012E00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[153]) /* 0x40012E40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[154]) /* 0x40012E80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[155]) /* 0x40012EC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[156]) /* 0x40012F00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[157]) /* 0x40012F40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[158]) /* 0x40012F80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[159]) /* 0x40012FC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[160]) /* 0x40013000 */ +#define PERI_MS_PPU_FX_HSIOM_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[161]) /* 0x40013040 */ +#define PERI_MS_PPU_FX_HSIOM_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[162]) /* 0x40013080 */ +#define PERI_MS_PPU_FX_HSIOM_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[163]) /* 0x400130C0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[164]) /* 0x40013100 */ +#define PERI_MS_PPU_FX_HSIOM_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[165]) /* 0x40013140 */ +#define PERI_MS_PPU_FX_HSIOM_AMUX ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[166]) /* 0x40013180 */ +#define PERI_MS_PPU_FX_HSIOM_MON ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[167]) /* 0x400131C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[168]) /* 0x40013200 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[169]) /* 0x40013240 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[170]) /* 0x40013280 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[171]) /* 0x400132C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[172]) /* 0x40013300 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[173]) /* 0x40013340 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[174]) /* 0x40013380 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[175]) /* 0x400133C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[176]) /* 0x40013400 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[177]) /* 0x40013440 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[178]) /* 0x40013480 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[179]) /* 0x400134C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[180]) /* 0x40013500 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[181]) /* 0x40013540 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[182]) /* 0x40013580 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[183]) /* 0x400135C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[184]) /* 0x40013600 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[185]) /* 0x40013640 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[186]) /* 0x40013680 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[187]) /* 0x400136C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[188]) /* 0x40013700 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[189]) /* 0x40013740 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[190]) /* 0x40013780 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[191]) /* 0x400137C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[192]) /* 0x40013800 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[193]) /* 0x40013840 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[194]) /* 0x40013880 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[195]) /* 0x400138C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[196]) /* 0x40013900 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[197]) /* 0x40013940 */ +#define PERI_MS_PPU_FX_GPIO_GPIO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[198]) /* 0x40013980 */ +#define PERI_MS_PPU_FX_GPIO_TEST ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[199]) /* 0x400139C0 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[200]) /* 0x40013A00 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[201]) /* 0x40013A40 */ +#define PERI_MS_PPU_FX_LPCOMP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[202]) /* 0x40013A80 */ +#define PERI_MS_PPU_FX_CSD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[203]) /* 0x40013AC0 */ +#define PERI_MS_PPU_FX_TCPWM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[204]) /* 0x40013B00 */ +#define PERI_MS_PPU_FX_TCPWM1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[205]) /* 0x40013B40 */ +#define PERI_MS_PPU_FX_LCD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[206]) /* 0x40013B80 */ +#define PERI_MS_PPU_FX_USBFS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[207]) /* 0x40013BC0 */ +#define PERI_MS_PPU_FX_SMIF0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[208]) /* 0x40013C00 */ +#define PERI_MS_PPU_FX_SDHC0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[209]) /* 0x40013C40 */ +#define PERI_MS_PPU_FX_CANFD0_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[210]) /* 0x40013C80 */ +#define PERI_MS_PPU_FX_CANFD0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[211]) /* 0x40013CC0 */ +#define PERI_MS_PPU_FX_CANFD0_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[212]) /* 0x40013D00 */ +#define PERI_MS_PPU_FX_SCB0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[213]) /* 0x40013D40 */ +#define PERI_MS_PPU_FX_SCB1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[214]) /* 0x40013D80 */ +#define PERI_MS_PPU_FX_SCB2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[215]) /* 0x40013DC0 */ +#define PERI_MS_PPU_FX_SCB3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[216]) /* 0x40013E00 */ +#define PERI_MS_PPU_FX_SCB4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[217]) /* 0x40013E40 */ +#define PERI_MS_PPU_FX_SCB5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[218]) /* 0x40013E80 */ +#define PERI_MS_PPU_FX_SCB6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[219]) /* 0x40013EC0 */ + +/******************************************************************************* +* CRYPTO +*******************************************************************************/ + +#define CRYPTO_BASE 0x40100000UL +#define CRYPTO ((CRYPTO_Type*) CRYPTO_BASE) /* 0x40100000 */ + +/******************************************************************************* +* CPUSS +*******************************************************************************/ + +#define CPUSS_BASE 0x40200000UL +#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40200000 */ + +/******************************************************************************* +* FAULT +*******************************************************************************/ + +#define FAULT_BASE 0x40210000UL +#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40210000 */ +#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40210000 */ +#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40210100 */ + +/******************************************************************************* +* IPC +*******************************************************************************/ + +#define IPC_BASE 0x40220000UL +#define IPC ((IPC_Type*) IPC_BASE) /* 0x40220000 */ +#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40220000 */ +#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40220020 */ +#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40220040 */ +#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40220060 */ +#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40220080 */ +#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402200A0 */ +#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402200C0 */ +#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402200E0 */ +#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40220100 */ +#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40220120 */ +#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40220140 */ +#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40220160 */ +#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40220180 */ +#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402201A0 */ +#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402201C0 */ +#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402201E0 */ +#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40221000 */ +#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40221020 */ +#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40221040 */ +#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40221060 */ +#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40221080 */ +#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402210A0 */ +#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402210C0 */ +#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402210E0 */ +#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40221100 */ +#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40221120 */ +#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40221140 */ +#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40221160 */ +#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40221180 */ +#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402211A0 */ +#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402211C0 */ +#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402211E0 */ + +/******************************************************************************* +* PROT +*******************************************************************************/ + +#define PROT_BASE 0x40230000UL +#define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ +#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ +#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ +#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402320C0 */ +#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40232100 */ +#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40232140 */ +#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40232180 */ +#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402321C0 */ +#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40232200 */ +#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40232240 */ +#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40232280 */ +#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402322C0 */ +#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40232300 */ +#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ +#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ +#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ +#define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ +#define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ +#define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ +#define PROT_MPU5_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[3]) /* 0x40235660 */ +#define PROT_MPU5_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[4]) /* 0x40235680 */ +#define PROT_MPU5_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[5]) /* 0x402356A0 */ +#define PROT_MPU5_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[6]) /* 0x402356C0 */ +#define PROT_MPU5_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[7]) /* 0x402356E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ + +/******************************************************************************* +* FLASHC +*******************************************************************************/ + +#define FLASHC_BASE 0x40240000UL +#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40240000 */ +#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4024F000 */ + +/******************************************************************************* +* SRSS +*******************************************************************************/ + +#define SRSS_BASE 0x40260000UL +#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ +#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */ +#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */ + +/******************************************************************************* +* BACKUP +*******************************************************************************/ + +#define BACKUP_BASE 0x40270000UL +#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ + +/******************************************************************************* +* DW +*******************************************************************************/ + +#define DW0_BASE 0x40280000UL +#define DW1_BASE 0x40290000UL +#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ +#define DW1 ((DW_Type*) DW1_BASE) /* 0x40290000 */ +#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40288000 */ +#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40288040 */ +#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40288080 */ +#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x402880C0 */ +#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40288100 */ +#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x40288140 */ +#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x40288180 */ +#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402881C0 */ +#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40288200 */ +#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40288240 */ +#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40288280 */ +#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x402882C0 */ +#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40288300 */ +#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x40288340 */ +#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x40288380 */ +#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402883C0 */ +#define DW0_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[16]) /* 0x40288400 */ +#define DW0_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[17]) /* 0x40288440 */ +#define DW0_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[18]) /* 0x40288480 */ +#define DW0_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[19]) /* 0x402884C0 */ +#define DW0_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[20]) /* 0x40288500 */ +#define DW0_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[21]) /* 0x40288540 */ +#define DW0_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[22]) /* 0x40288580 */ +#define DW0_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[23]) /* 0x402885C0 */ +#define DW0_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[24]) /* 0x40288600 */ +#define DW0_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[25]) /* 0x40288640 */ +#define DW0_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[26]) /* 0x40288680 */ +#define DW0_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[27]) /* 0x402886C0 */ +#define DW0_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[28]) /* 0x40288700 */ +#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40298000 */ +#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40298040 */ +#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40298080 */ +#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x402980C0 */ +#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40298100 */ +#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x40298140 */ +#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x40298180 */ +#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402981C0 */ +#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40298200 */ +#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40298240 */ +#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40298280 */ +#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x402982C0 */ +#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40298300 */ +#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x40298340 */ +#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x40298380 */ +#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402983C0 */ +#define DW1_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[16]) /* 0x40298400 */ +#define DW1_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[17]) /* 0x40298440 */ +#define DW1_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[18]) /* 0x40298480 */ +#define DW1_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[19]) /* 0x402984C0 */ +#define DW1_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[20]) /* 0x40298500 */ +#define DW1_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[21]) /* 0x40298540 */ +#define DW1_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[22]) /* 0x40298580 */ +#define DW1_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[23]) /* 0x402985C0 */ +#define DW1_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[24]) /* 0x40298600 */ +#define DW1_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[25]) /* 0x40298640 */ +#define DW1_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[26]) /* 0x40298680 */ +#define DW1_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[27]) /* 0x402986C0 */ +#define DW1_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[28]) /* 0x40298700 */ +#define DW1_CH_STRUCT29 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[29]) /* 0x40298740 */ +#define DW1_CH_STRUCT30 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[30]) /* 0x40298780 */ +#define DW1_CH_STRUCT31 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[31]) /* 0x402987C0 */ + +/******************************************************************************* +* DMAC +*******************************************************************************/ + +#define DMAC_BASE 0x402A0000UL +#define DMAC ((DMAC_Type*) DMAC_BASE) /* 0x402A0000 */ +#define DMAC_CH0 ((DMAC_CH_Type*) &DMAC->CH[0]) /* 0x402A1000 */ +#define DMAC_CH1 ((DMAC_CH_Type*) &DMAC->CH[1]) /* 0x402A1100 */ + +/******************************************************************************* +* EFUSE +*******************************************************************************/ + +#define EFUSE_BASE 0x402C0000UL +#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ + +/******************************************************************************* +* HSIOM +*******************************************************************************/ + +#define HSIOM_BASE 0x40300000UL +#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40300000 */ +#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40300000 */ +#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40300010 */ +#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40300020 */ +#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40300030 */ +#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40300040 */ +#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40300050 */ +#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40300060 */ +#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40300070 */ +#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40300080 */ +#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40300090 */ +#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403000A0 */ +#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403000B0 */ +#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403000C0 */ +#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403000D0 */ +#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403000E0 */ + +/******************************************************************************* +* GPIO +*******************************************************************************/ + +#define GPIO_BASE 0x40310000UL +#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40310000 */ +#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40310000 */ +#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40310080 */ +#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40310100 */ +#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40310180 */ +#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40310200 */ +#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40310280 */ +#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40310300 */ +#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40310380 */ +#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40310400 */ +#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40310480 */ +#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40310500 */ +#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40310580 */ +#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40310600 */ +#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40310680 */ +#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40310700 */ + +/******************************************************************************* +* SMARTIO +*******************************************************************************/ + +#define SMARTIO_BASE 0x40320000UL +#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40320000 */ +#define SMARTIO_PRT8 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[8]) /* 0x40320800 */ +#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40320900 */ + +/******************************************************************************* +* LPCOMP +*******************************************************************************/ + +#define LPCOMP_BASE 0x40350000UL +#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */ + +/******************************************************************************* +* CSD +*******************************************************************************/ + +#define CSD0_BASE 0x40360000UL +#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */ + +/******************************************************************************* +* TCPWM +*******************************************************************************/ + +#define TCPWM0_BASE 0x40380000UL +#define TCPWM1_BASE 0x40390000UL +#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM1 ((TCPWM_Type*) TCPWM1_BASE) /* 0x40390000 */ +#define TCPWM0_CNT0 ((TCPWM_CNT_Type*) &TCPWM0->CNT[0]) /* 0x40380100 */ +#define TCPWM0_CNT1 ((TCPWM_CNT_Type*) &TCPWM0->CNT[1]) /* 0x40380140 */ +#define TCPWM0_CNT2 ((TCPWM_CNT_Type*) &TCPWM0->CNT[2]) /* 0x40380180 */ +#define TCPWM0_CNT3 ((TCPWM_CNT_Type*) &TCPWM0->CNT[3]) /* 0x403801C0 */ +#define TCPWM1_CNT0 ((TCPWM_CNT_Type*) &TCPWM1->CNT[0]) /* 0x40390100 */ +#define TCPWM1_CNT1 ((TCPWM_CNT_Type*) &TCPWM1->CNT[1]) /* 0x40390140 */ +#define TCPWM1_CNT2 ((TCPWM_CNT_Type*) &TCPWM1->CNT[2]) /* 0x40390180 */ +#define TCPWM1_CNT3 ((TCPWM_CNT_Type*) &TCPWM1->CNT[3]) /* 0x403901C0 */ +#define TCPWM1_CNT4 ((TCPWM_CNT_Type*) &TCPWM1->CNT[4]) /* 0x40390200 */ +#define TCPWM1_CNT5 ((TCPWM_CNT_Type*) &TCPWM1->CNT[5]) /* 0x40390240 */ +#define TCPWM1_CNT6 ((TCPWM_CNT_Type*) &TCPWM1->CNT[6]) /* 0x40390280 */ +#define TCPWM1_CNT7 ((TCPWM_CNT_Type*) &TCPWM1->CNT[7]) /* 0x403902C0 */ + +/******************************************************************************* +* LCD +*******************************************************************************/ + +#define LCD0_BASE 0x403B0000UL +#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ + +/******************************************************************************* +* USBFS +*******************************************************************************/ + +#define USBFS0_BASE 0x403F0000UL +#define USBFS0 ((USBFS_Type*) USBFS0_BASE) /* 0x403F0000 */ +#define USBFS0_USBDEV ((USBFS_USBDEV_Type*) &USBFS0->USBDEV) /* 0x403F0000 */ +#define USBFS0_USBLPM ((USBFS_USBLPM_Type*) &USBFS0->USBLPM) /* 0x403F2000 */ +#define USBFS0_USBHOST ((USBFS_USBHOST_Type*) &USBFS0->USBHOST) /* 0x403F4000 */ + +/******************************************************************************* +* SMIF +*******************************************************************************/ + +#define SMIF0_BASE 0x40420000UL +#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ +#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ +#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ +#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ + +/******************************************************************************* +* SDHC +*******************************************************************************/ + +#define SDHC0_BASE 0x40460000UL +#define SDHC0 ((SDHC_Type*) SDHC0_BASE) /* 0x40460000 */ +#define SDHC0_WRAP ((SDHC_WRAP_Type*) &SDHC0->WRAP) /* 0x40460000 */ +#define SDHC0_CORE ((SDHC_CORE_Type*) &SDHC0->CORE) /* 0x40461000 */ + +/******************************************************************************* +* CANFD +*******************************************************************************/ + +#define CANFD0_BASE 0x40520000UL +#define CANFD0 ((CANFD_Type*) CANFD0_BASE) /* 0x40520000 */ +#define CANFD0_CH0 ((CANFD_CH_Type*) &CANFD0->CH[0]) /* 0x40520000 */ +#define CANFD0_CH0_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[0].M_TTCAN) /* 0x40520000 */ + +/******************************************************************************* +* SCB +*******************************************************************************/ + +#define SCB0_BASE 0x40600000UL +#define SCB1_BASE 0x40610000UL +#define SCB2_BASE 0x40620000UL +#define SCB3_BASE 0x40630000UL +#define SCB4_BASE 0x40640000UL +#define SCB5_BASE 0x40650000UL +#define SCB6_BASE 0x40660000UL +#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40600000 */ +#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40610000 */ +#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40620000 */ +#define SCB3 ((CySCB_Type*) SCB3_BASE) /* 0x40630000 */ +#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40640000 */ +#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40650000 */ +#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40660000 */ + +/******************************************************************************* +* SAR +*******************************************************************************/ + +#define SAR_BASE 0x409D0000UL +#define SAR ((SAR_Type*) SAR_BASE) /* 0x409D0000 */ + +/******************************************************************************* +* PASS +*******************************************************************************/ + +#define PASS_BASE 0x409F0000UL +#define PASS ((PASS_Type*) PASS_BASE) /* 0x409F0000 */ +#define PASS_AREF ((PASS_AREF_Type*) &PASS->AREF) /* 0x409F0E00 */ + +/** \} CY8C6145LQI-S3F42 */ + +#endif /* _CY8C6145LQI_S3F42_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6145lqi_s3f62.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6145lqi_s3f62.h new file mode 100644 index 0000000000..e34256c12f --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6145lqi_s3f62.h @@ -0,0 +1,983 @@ +/***************************************************************************//** +* \file cy8c6145lqi_s3f62.h +* +* \brief +* CY8C6145LQI-S3F62 device header +* +* \note +* Generator version: 1.6.0.225 +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CY8C6145LQI_S3F62_H_ +#define _CY8C6145LQI_S3F62_H_ + +/** +* \addtogroup group_device CY8C6145LQI-S3F62 +* \{ +*/ + +/** +* \addtogroup Configuration_of_CMSIS +* \{ +*/ + +/******************************************************************************* +* Interrupt Number Definition +*******************************************************************************/ + +typedef enum { + /* ARM Cortex-M4 Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C6145LQI-S3F62 Peripheral Interrupt Numbers */ + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_6_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #6 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + canfd_0_interrupt0_IRQn = 168, /*!< 168 [Active] Can #0, Consolidated interrupt #0 */ + canfd_0_interrupts0_0_IRQn = 169, /*!< 169 [Active] CAN #0, Interrupt #0, Channel #0 */ + canfd_0_interrupts1_0_IRQn = 170, /*!< 170 [Active] CAN #0, Interrupt #1, Channel #0 */ + cpuss_interrupts_dw1_29_IRQn = 171, /*!< 171 [Active] CPUSS DataWire #1, Channel #29 */ + cpuss_interrupts_dw1_30_IRQn = 172, /*!< 172 [Active] CPUSS DataWire #1, Channel #30 */ + cpuss_interrupts_dw1_31_IRQn = 173, /*!< 173 [Active] CPUSS DataWire #1, Channel #31 */ + unconnected_IRQn = 240 /*!< 240 Unconnected */ +} IRQn_Type; + + +/******************************************************************************* +* Processor and Core Peripheral Section +*******************************************************************************/ + +/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __CM0P_PRESENT 0 /*!< CM0P present or not */ +#define __DTCM_PRESENT 0 /*!< DTCM present or not */ +#define __ICACHE_PRESENT 0 /*!< ICACHE present or not */ +#define __DCACHE_PRESENT 0 /*!< DCACHE present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + + +/* Memory Blocks */ +#define CY_ROM_BASE 0x00000000UL +#define CY_ROM_SIZE 0x00010000UL +#define CY_SRAM_BASE 0x08000000UL +#define CY_SRAM_SIZE 0x00040000UL +#define CY_FLASH_BASE 0x10000000UL +#define CY_FLASH_SIZE 0x00080000UL +#define CY_EM_EEPROM_BASE 0x14000000UL +#define CY_EM_EEPROM_SIZE 0x00008000UL +#define CY_SFLASH_BASE 0x16000000UL +#define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL +#define CY_EFUSE_BASE 0x402C0800UL +#define CY_EFUSE_SIZE 0x00000200UL +#define CY_CAN0MRAM_BASE 0x40530000UL +#define CY_CAN0MRAM_SIZE 0x00010000UL + +#include "system_psoc6.h" /*!< PSoC 6 System */ + +/* IP List */ +#define CY_IP_MXTTCANFD 1u +#define CY_IP_MXTTCANFD_INSTANCES 1u +#define CY_IP_MXTTCANFD_VERSION 1u +#define CY_IP_M4CPUSS 1u +#define CY_IP_M4CPUSS_INSTANCES 1u +#define CY_IP_M4CPUSS_VERSION 2u +#define CY_IP_M4CPUSS_DMAC 1u +#define CY_IP_M4CPUSS_DMAC_INSTANCES 1u +#define CY_IP_M4CPUSS_DMAC_VERSION 2u +#define CY_IP_M4CPUSS_DMA 1u +#define CY_IP_M4CPUSS_DMA_INSTANCES 2u +#define CY_IP_M4CPUSS_DMA_VERSION 2u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 2u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u +#define CY_IP_MXS40PASS 1u +#define CY_IP_MXS40PASS_INSTANCES 1u +#define CY_IP_MXS40PASS_VERSION 1u +#define CY_IP_MXS40PASS_SAR 1u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u +#define CY_IP_MXS40PASS_SAR_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 7u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 1u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u + +#include "psoc6_03_config.h" +#include "gpio_psoc6_03_68_qfn.h" + +#define CY_DEVICE_PSOC6A512K +#define CY_SILICON_ID 0xE7131105UL +#define CY_HF_CLK_MAX_FREQ 150000000UL + +#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL + +/******************************************************************************* +* SFLASH +*******************************************************************************/ + +#define SFLASH_BASE 0x16000000UL +#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */ + +/******************************************************************************* +* PERI +*******************************************************************************/ + +#define PERI_BASE 0x40000000UL +#define PERI ((PERI_Type*) PERI_BASE) /* 0x40000000 */ +#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40004000 */ +#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40004020 */ +#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40004040 */ +#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x40004060 */ +#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40004080 */ +#define PERI_GR5 ((PERI_GR_Type*) &PERI->GR[5]) /* 0x400040A0 */ +#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x400040C0 */ +#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40004120 */ +#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40008000 */ +#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40008400 */ +#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40008800 */ +#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40008C00 */ +#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40009000 */ +#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40009400 */ +#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40009800 */ +#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40009C00 */ +#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ +#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ +#define PERI_TR_GR10 ((PERI_TR_GR_Type*) &PERI->TR_GR[10]) /* 0x4000A800 */ +#define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ +#define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ +#define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ +#define PERI_TR_1TO1_GR3 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[3]) /* 0x4000CC00 */ +#define PERI_TR_1TO1_GR4 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[4]) /* 0x4000D000 */ +#define PERI_TR_1TO1_GR5 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[5]) /* 0x4000D400 */ +#define PERI_TR_1TO1_GR6 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[6]) /* 0x4000D800 */ +#define PERI_TR_1TO1_GR7 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[7]) /* 0x4000DC00 */ + +/******************************************************************************* +* PERI_MS +*******************************************************************************/ + +#define PERI_MS_BASE 0x40010000UL +#define PERI_MS ((PERI_MS_Type*) PERI_MS_BASE) /* 0x40010000 */ +#define PERI_MS_PPU_PR0 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[0]) /* 0x40010000 */ +#define PERI_MS_PPU_PR1 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[1]) /* 0x40010040 */ +#define PERI_MS_PPU_PR2 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[2]) /* 0x40010080 */ +#define PERI_MS_PPU_PR3 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[3]) /* 0x400100C0 */ +#define PERI_MS_PPU_PR4 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[4]) /* 0x40010100 */ +#define PERI_MS_PPU_PR5 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[5]) /* 0x40010140 */ +#define PERI_MS_PPU_PR6 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[6]) /* 0x40010180 */ +#define PERI_MS_PPU_PR7 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[7]) /* 0x400101C0 */ +#define PERI_MS_PPU_FX_PERI_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[0]) /* 0x40010800 */ +#define PERI_MS_PPU_FX_PERI_GR0_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[1]) /* 0x40010840 */ +#define PERI_MS_PPU_FX_PERI_GR1_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[2]) /* 0x40010880 */ +#define PERI_MS_PPU_FX_PERI_GR2_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[3]) /* 0x400108C0 */ +#define PERI_MS_PPU_FX_PERI_GR3_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[4]) /* 0x40010900 */ +#define PERI_MS_PPU_FX_PERI_GR4_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[5]) /* 0x40010940 */ +#define PERI_MS_PPU_FX_PERI_GR5_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[6]) /* 0x40010980 */ +#define PERI_MS_PPU_FX_PERI_GR6_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[7]) /* 0x400109C0 */ +#define PERI_MS_PPU_FX_PERI_GR9_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[8]) /* 0x40010A00 */ +#define PERI_MS_PPU_FX_PERI_TR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[9]) /* 0x40010A40 */ +#define PERI_MS_PPU_FX_CRYPTO_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[10]) /* 0x40010A80 */ +#define PERI_MS_PPU_FX_CRYPTO_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[11]) /* 0x40010AC0 */ +#define PERI_MS_PPU_FX_CRYPTO_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[12]) /* 0x40010B00 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[13]) /* 0x40010B40 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[14]) /* 0x40010B80 */ +#define PERI_MS_PPU_FX_CRYPTO_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[15]) /* 0x40010BC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[16]) /* 0x40010C00 */ +#define PERI_MS_PPU_FX_CPUSS_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[17]) /* 0x40010C40 */ +#define PERI_MS_PPU_FX_CPUSS_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[18]) /* 0x40010C80 */ +#define PERI_MS_PPU_FX_CPUSS_CM0_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[19]) /* 0x40010CC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[20]) /* 0x40010D00 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[21]) /* 0x40010D40 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT1_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[22]) /* 0x40010D80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT0_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[23]) /* 0x40010DC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT1_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[24]) /* 0x40010E00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT2_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[25]) /* 0x40010E40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT3_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[26]) /* 0x40010E80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT4_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[27]) /* 0x40010EC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT5_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[28]) /* 0x40010F00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT6_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[29]) /* 0x40010F40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT7_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[30]) /* 0x40010F80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT8_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[31]) /* 0x40010FC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT9_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[32]) /* 0x40011000 */ +#define PERI_MS_PPU_FX_IPC_STRUCT10_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[33]) /* 0x40011040 */ +#define PERI_MS_PPU_FX_IPC_STRUCT11_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[34]) /* 0x40011080 */ +#define PERI_MS_PPU_FX_IPC_STRUCT12_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[35]) /* 0x400110C0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT13_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[36]) /* 0x40011100 */ +#define PERI_MS_PPU_FX_IPC_STRUCT14_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[37]) /* 0x40011140 */ +#define PERI_MS_PPU_FX_IPC_STRUCT15_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[38]) /* 0x40011180 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT0_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[39]) /* 0x400111C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT1_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[40]) /* 0x40011200 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT2_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[41]) /* 0x40011240 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT3_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[42]) /* 0x40011280 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT4_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[43]) /* 0x400112C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT5_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[44]) /* 0x40011300 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT6_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[45]) /* 0x40011340 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT7_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[46]) /* 0x40011380 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT8_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[47]) /* 0x400113C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT9_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[48]) /* 0x40011400 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT10_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[49]) /* 0x40011440 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT11_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[50]) /* 0x40011480 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT12_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[51]) /* 0x400114C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT13_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[52]) /* 0x40011500 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT14_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[53]) /* 0x40011540 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT15_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[54]) /* 0x40011580 */ +#define PERI_MS_PPU_FX_PROT_SMPU_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[55]) /* 0x400115C0 */ +#define PERI_MS_PPU_FX_PROT_MPU0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[56]) /* 0x40011600 */ +#define PERI_MS_PPU_FX_PROT_MPU5_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[57]) /* 0x40011640 */ +#define PERI_MS_PPU_FX_PROT_MPU14_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[58]) /* 0x40011680 */ +#define PERI_MS_PPU_FX_PROT_MPU15_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[59]) /* 0x400116C0 */ +#define PERI_MS_PPU_FX_FLASHC_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[60]) /* 0x40011700 */ +#define PERI_MS_PPU_FX_FLASHC_CMD ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[61]) /* 0x40011740 */ +#define PERI_MS_PPU_FX_FLASHC_DFT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[62]) /* 0x40011780 */ +#define PERI_MS_PPU_FX_FLASHC_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[63]) /* 0x400117C0 */ +#define PERI_MS_PPU_FX_FLASHC_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[64]) /* 0x40011800 */ +#define PERI_MS_PPU_FX_FLASHC_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[65]) /* 0x40011840 */ +#define PERI_MS_PPU_FX_FLASHC_DW0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[66]) /* 0x40011880 */ +#define PERI_MS_PPU_FX_FLASHC_DW1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[67]) /* 0x400118C0 */ +#define PERI_MS_PPU_FX_FLASHC_DMAC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[68]) /* 0x40011900 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[69]) /* 0x40011940 */ +#define PERI_MS_PPU_FX_FLASHC_FM ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[70]) /* 0x40011980 */ +#define PERI_MS_PPU_FX_SRSS_MAIN1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[71]) /* 0x400119C0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[72]) /* 0x40011A00 */ +#define PERI_MS_PPU_FX_WDT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[73]) /* 0x40011A40 */ +#define PERI_MS_PPU_FX_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[74]) /* 0x40011A80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[75]) /* 0x40011AC0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[76]) /* 0x40011B00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[77]) /* 0x40011B40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[78]) /* 0x40011B80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[79]) /* 0x40011BC0 */ +#define PERI_MS_PPU_FX_BACKUP_BACKUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[80]) /* 0x40011C00 */ +#define PERI_MS_PPU_FX_DW0_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[81]) /* 0x40011C40 */ +#define PERI_MS_PPU_FX_DW1_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[82]) /* 0x40011C80 */ +#define PERI_MS_PPU_FX_DW0_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[83]) /* 0x40011CC0 */ +#define PERI_MS_PPU_FX_DW1_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[84]) /* 0x40011D00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[85]) /* 0x40011D40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[86]) /* 0x40011D80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[87]) /* 0x40011DC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[88]) /* 0x40011E00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[89]) /* 0x40011E40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[90]) /* 0x40011E80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[91]) /* 0x40011EC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[92]) /* 0x40011F00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[93]) /* 0x40011F40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[94]) /* 0x40011F80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[95]) /* 0x40011FC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[96]) /* 0x40012000 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[97]) /* 0x40012040 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[98]) /* 0x40012080 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[99]) /* 0x400120C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[100]) /* 0x40012100 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[101]) /* 0x40012140 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[102]) /* 0x40012180 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[103]) /* 0x400121C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[104]) /* 0x40012200 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[105]) /* 0x40012240 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[106]) /* 0x40012280 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[107]) /* 0x400122C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[108]) /* 0x40012300 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[109]) /* 0x40012340 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[110]) /* 0x40012380 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[111]) /* 0x400123C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[112]) /* 0x40012400 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[113]) /* 0x40012440 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[114]) /* 0x40012480 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[115]) /* 0x400124C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[116]) /* 0x40012500 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[117]) /* 0x40012540 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[118]) /* 0x40012580 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[119]) /* 0x400125C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[120]) /* 0x40012600 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[121]) /* 0x40012640 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[122]) /* 0x40012680 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[123]) /* 0x400126C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[124]) /* 0x40012700 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[125]) /* 0x40012740 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[126]) /* 0x40012780 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[127]) /* 0x400127C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[128]) /* 0x40012800 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[129]) /* 0x40012840 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[130]) /* 0x40012880 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[131]) /* 0x400128C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[132]) /* 0x40012900 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[133]) /* 0x40012940 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[134]) /* 0x40012980 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[135]) /* 0x400129C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[136]) /* 0x40012A00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[137]) /* 0x40012A40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[138]) /* 0x40012A80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[139]) /* 0x40012AC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[140]) /* 0x40012B00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[141]) /* 0x40012B40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[142]) /* 0x40012B80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT29_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[143]) /* 0x40012BC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT30_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[144]) /* 0x40012C00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT31_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[145]) /* 0x40012C40 */ +#define PERI_MS_PPU_FX_DMAC_TOP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[146]) /* 0x40012C80 */ +#define PERI_MS_PPU_FX_DMAC_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[147]) /* 0x40012CC0 */ +#define PERI_MS_PPU_FX_DMAC_CH1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[148]) /* 0x40012D00 */ +#define PERI_MS_PPU_FX_EFUSE_CTL ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[149]) /* 0x40012D40 */ +#define PERI_MS_PPU_FX_EFUSE_DATA ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[150]) /* 0x40012D80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[151]) /* 0x40012DC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[152]) /* 0x40012E00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[153]) /* 0x40012E40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[154]) /* 0x40012E80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[155]) /* 0x40012EC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[156]) /* 0x40012F00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[157]) /* 0x40012F40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[158]) /* 0x40012F80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[159]) /* 0x40012FC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[160]) /* 0x40013000 */ +#define PERI_MS_PPU_FX_HSIOM_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[161]) /* 0x40013040 */ +#define PERI_MS_PPU_FX_HSIOM_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[162]) /* 0x40013080 */ +#define PERI_MS_PPU_FX_HSIOM_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[163]) /* 0x400130C0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[164]) /* 0x40013100 */ +#define PERI_MS_PPU_FX_HSIOM_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[165]) /* 0x40013140 */ +#define PERI_MS_PPU_FX_HSIOM_AMUX ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[166]) /* 0x40013180 */ +#define PERI_MS_PPU_FX_HSIOM_MON ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[167]) /* 0x400131C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[168]) /* 0x40013200 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[169]) /* 0x40013240 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[170]) /* 0x40013280 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[171]) /* 0x400132C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[172]) /* 0x40013300 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[173]) /* 0x40013340 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[174]) /* 0x40013380 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[175]) /* 0x400133C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[176]) /* 0x40013400 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[177]) /* 0x40013440 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[178]) /* 0x40013480 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[179]) /* 0x400134C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[180]) /* 0x40013500 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[181]) /* 0x40013540 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[182]) /* 0x40013580 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[183]) /* 0x400135C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[184]) /* 0x40013600 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[185]) /* 0x40013640 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[186]) /* 0x40013680 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[187]) /* 0x400136C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[188]) /* 0x40013700 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[189]) /* 0x40013740 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[190]) /* 0x40013780 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[191]) /* 0x400137C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[192]) /* 0x40013800 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[193]) /* 0x40013840 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[194]) /* 0x40013880 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[195]) /* 0x400138C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[196]) /* 0x40013900 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[197]) /* 0x40013940 */ +#define PERI_MS_PPU_FX_GPIO_GPIO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[198]) /* 0x40013980 */ +#define PERI_MS_PPU_FX_GPIO_TEST ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[199]) /* 0x400139C0 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[200]) /* 0x40013A00 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[201]) /* 0x40013A40 */ +#define PERI_MS_PPU_FX_LPCOMP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[202]) /* 0x40013A80 */ +#define PERI_MS_PPU_FX_CSD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[203]) /* 0x40013AC0 */ +#define PERI_MS_PPU_FX_TCPWM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[204]) /* 0x40013B00 */ +#define PERI_MS_PPU_FX_TCPWM1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[205]) /* 0x40013B40 */ +#define PERI_MS_PPU_FX_LCD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[206]) /* 0x40013B80 */ +#define PERI_MS_PPU_FX_USBFS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[207]) /* 0x40013BC0 */ +#define PERI_MS_PPU_FX_SMIF0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[208]) /* 0x40013C00 */ +#define PERI_MS_PPU_FX_SDHC0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[209]) /* 0x40013C40 */ +#define PERI_MS_PPU_FX_CANFD0_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[210]) /* 0x40013C80 */ +#define PERI_MS_PPU_FX_CANFD0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[211]) /* 0x40013CC0 */ +#define PERI_MS_PPU_FX_CANFD0_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[212]) /* 0x40013D00 */ +#define PERI_MS_PPU_FX_SCB0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[213]) /* 0x40013D40 */ +#define PERI_MS_PPU_FX_SCB1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[214]) /* 0x40013D80 */ +#define PERI_MS_PPU_FX_SCB2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[215]) /* 0x40013DC0 */ +#define PERI_MS_PPU_FX_SCB3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[216]) /* 0x40013E00 */ +#define PERI_MS_PPU_FX_SCB4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[217]) /* 0x40013E40 */ +#define PERI_MS_PPU_FX_SCB5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[218]) /* 0x40013E80 */ +#define PERI_MS_PPU_FX_SCB6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[219]) /* 0x40013EC0 */ + +/******************************************************************************* +* CPUSS +*******************************************************************************/ + +#define CPUSS_BASE 0x40200000UL +#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40200000 */ + +/******************************************************************************* +* FAULT +*******************************************************************************/ + +#define FAULT_BASE 0x40210000UL +#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40210000 */ +#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40210000 */ +#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40210100 */ + +/******************************************************************************* +* IPC +*******************************************************************************/ + +#define IPC_BASE 0x40220000UL +#define IPC ((IPC_Type*) IPC_BASE) /* 0x40220000 */ +#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40220000 */ +#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40220020 */ +#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40220040 */ +#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40220060 */ +#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40220080 */ +#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402200A0 */ +#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402200C0 */ +#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402200E0 */ +#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40220100 */ +#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40220120 */ +#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40220140 */ +#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40220160 */ +#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40220180 */ +#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402201A0 */ +#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402201C0 */ +#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402201E0 */ +#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40221000 */ +#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40221020 */ +#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40221040 */ +#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40221060 */ +#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40221080 */ +#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402210A0 */ +#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402210C0 */ +#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402210E0 */ +#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40221100 */ +#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40221120 */ +#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40221140 */ +#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40221160 */ +#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40221180 */ +#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402211A0 */ +#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402211C0 */ +#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402211E0 */ + +/******************************************************************************* +* PROT +*******************************************************************************/ + +#define PROT_BASE 0x40230000UL +#define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ +#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ +#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ +#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402320C0 */ +#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40232100 */ +#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40232140 */ +#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40232180 */ +#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402321C0 */ +#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40232200 */ +#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40232240 */ +#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40232280 */ +#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402322C0 */ +#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40232300 */ +#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ +#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ +#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ +#define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ +#define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ +#define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ +#define PROT_MPU5_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[3]) /* 0x40235660 */ +#define PROT_MPU5_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[4]) /* 0x40235680 */ +#define PROT_MPU5_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[5]) /* 0x402356A0 */ +#define PROT_MPU5_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[6]) /* 0x402356C0 */ +#define PROT_MPU5_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[7]) /* 0x402356E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ + +/******************************************************************************* +* FLASHC +*******************************************************************************/ + +#define FLASHC_BASE 0x40240000UL +#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40240000 */ +#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4024F000 */ + +/******************************************************************************* +* SRSS +*******************************************************************************/ + +#define SRSS_BASE 0x40260000UL +#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ +#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */ +#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */ + +/******************************************************************************* +* BACKUP +*******************************************************************************/ + +#define BACKUP_BASE 0x40270000UL +#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ + +/******************************************************************************* +* DW +*******************************************************************************/ + +#define DW0_BASE 0x40280000UL +#define DW1_BASE 0x40290000UL +#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ +#define DW1 ((DW_Type*) DW1_BASE) /* 0x40290000 */ +#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40288000 */ +#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40288040 */ +#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40288080 */ +#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x402880C0 */ +#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40288100 */ +#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x40288140 */ +#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x40288180 */ +#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402881C0 */ +#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40288200 */ +#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40288240 */ +#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40288280 */ +#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x402882C0 */ +#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40288300 */ +#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x40288340 */ +#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x40288380 */ +#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402883C0 */ +#define DW0_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[16]) /* 0x40288400 */ +#define DW0_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[17]) /* 0x40288440 */ +#define DW0_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[18]) /* 0x40288480 */ +#define DW0_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[19]) /* 0x402884C0 */ +#define DW0_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[20]) /* 0x40288500 */ +#define DW0_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[21]) /* 0x40288540 */ +#define DW0_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[22]) /* 0x40288580 */ +#define DW0_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[23]) /* 0x402885C0 */ +#define DW0_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[24]) /* 0x40288600 */ +#define DW0_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[25]) /* 0x40288640 */ +#define DW0_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[26]) /* 0x40288680 */ +#define DW0_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[27]) /* 0x402886C0 */ +#define DW0_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[28]) /* 0x40288700 */ +#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40298000 */ +#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40298040 */ +#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40298080 */ +#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x402980C0 */ +#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40298100 */ +#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x40298140 */ +#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x40298180 */ +#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402981C0 */ +#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40298200 */ +#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40298240 */ +#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40298280 */ +#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x402982C0 */ +#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40298300 */ +#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x40298340 */ +#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x40298380 */ +#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402983C0 */ +#define DW1_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[16]) /* 0x40298400 */ +#define DW1_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[17]) /* 0x40298440 */ +#define DW1_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[18]) /* 0x40298480 */ +#define DW1_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[19]) /* 0x402984C0 */ +#define DW1_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[20]) /* 0x40298500 */ +#define DW1_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[21]) /* 0x40298540 */ +#define DW1_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[22]) /* 0x40298580 */ +#define DW1_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[23]) /* 0x402985C0 */ +#define DW1_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[24]) /* 0x40298600 */ +#define DW1_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[25]) /* 0x40298640 */ +#define DW1_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[26]) /* 0x40298680 */ +#define DW1_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[27]) /* 0x402986C0 */ +#define DW1_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[28]) /* 0x40298700 */ +#define DW1_CH_STRUCT29 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[29]) /* 0x40298740 */ +#define DW1_CH_STRUCT30 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[30]) /* 0x40298780 */ +#define DW1_CH_STRUCT31 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[31]) /* 0x402987C0 */ + +/******************************************************************************* +* DMAC +*******************************************************************************/ + +#define DMAC_BASE 0x402A0000UL +#define DMAC ((DMAC_Type*) DMAC_BASE) /* 0x402A0000 */ +#define DMAC_CH0 ((DMAC_CH_Type*) &DMAC->CH[0]) /* 0x402A1000 */ +#define DMAC_CH1 ((DMAC_CH_Type*) &DMAC->CH[1]) /* 0x402A1100 */ + +/******************************************************************************* +* EFUSE +*******************************************************************************/ + +#define EFUSE_BASE 0x402C0000UL +#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ + +/******************************************************************************* +* HSIOM +*******************************************************************************/ + +#define HSIOM_BASE 0x40300000UL +#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40300000 */ +#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40300000 */ +#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40300010 */ +#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40300020 */ +#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40300030 */ +#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40300040 */ +#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40300050 */ +#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40300060 */ +#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40300070 */ +#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40300080 */ +#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40300090 */ +#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403000A0 */ +#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403000B0 */ +#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403000C0 */ +#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403000D0 */ +#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403000E0 */ + +/******************************************************************************* +* GPIO +*******************************************************************************/ + +#define GPIO_BASE 0x40310000UL +#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40310000 */ +#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40310000 */ +#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40310080 */ +#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40310100 */ +#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40310180 */ +#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40310200 */ +#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40310280 */ +#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40310300 */ +#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40310380 */ +#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40310400 */ +#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40310480 */ +#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40310500 */ +#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40310580 */ +#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40310600 */ +#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40310680 */ +#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40310700 */ + +/******************************************************************************* +* SMARTIO +*******************************************************************************/ + +#define SMARTIO_BASE 0x40320000UL +#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40320000 */ +#define SMARTIO_PRT8 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[8]) /* 0x40320800 */ +#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40320900 */ + +/******************************************************************************* +* LPCOMP +*******************************************************************************/ + +#define LPCOMP_BASE 0x40350000UL +#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */ + +/******************************************************************************* +* CSD +*******************************************************************************/ + +#define CSD0_BASE 0x40360000UL +#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */ + +/******************************************************************************* +* TCPWM +*******************************************************************************/ + +#define TCPWM0_BASE 0x40380000UL +#define TCPWM1_BASE 0x40390000UL +#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM1 ((TCPWM_Type*) TCPWM1_BASE) /* 0x40390000 */ +#define TCPWM0_CNT0 ((TCPWM_CNT_Type*) &TCPWM0->CNT[0]) /* 0x40380100 */ +#define TCPWM0_CNT1 ((TCPWM_CNT_Type*) &TCPWM0->CNT[1]) /* 0x40380140 */ +#define TCPWM0_CNT2 ((TCPWM_CNT_Type*) &TCPWM0->CNT[2]) /* 0x40380180 */ +#define TCPWM0_CNT3 ((TCPWM_CNT_Type*) &TCPWM0->CNT[3]) /* 0x403801C0 */ +#define TCPWM1_CNT0 ((TCPWM_CNT_Type*) &TCPWM1->CNT[0]) /* 0x40390100 */ +#define TCPWM1_CNT1 ((TCPWM_CNT_Type*) &TCPWM1->CNT[1]) /* 0x40390140 */ +#define TCPWM1_CNT2 ((TCPWM_CNT_Type*) &TCPWM1->CNT[2]) /* 0x40390180 */ +#define TCPWM1_CNT3 ((TCPWM_CNT_Type*) &TCPWM1->CNT[3]) /* 0x403901C0 */ +#define TCPWM1_CNT4 ((TCPWM_CNT_Type*) &TCPWM1->CNT[4]) /* 0x40390200 */ +#define TCPWM1_CNT5 ((TCPWM_CNT_Type*) &TCPWM1->CNT[5]) /* 0x40390240 */ +#define TCPWM1_CNT6 ((TCPWM_CNT_Type*) &TCPWM1->CNT[6]) /* 0x40390280 */ +#define TCPWM1_CNT7 ((TCPWM_CNT_Type*) &TCPWM1->CNT[7]) /* 0x403902C0 */ + +/******************************************************************************* +* LCD +*******************************************************************************/ + +#define LCD0_BASE 0x403B0000UL +#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ + +/******************************************************************************* +* USBFS +*******************************************************************************/ + +#define USBFS0_BASE 0x403F0000UL +#define USBFS0 ((USBFS_Type*) USBFS0_BASE) /* 0x403F0000 */ +#define USBFS0_USBDEV ((USBFS_USBDEV_Type*) &USBFS0->USBDEV) /* 0x403F0000 */ +#define USBFS0_USBLPM ((USBFS_USBLPM_Type*) &USBFS0->USBLPM) /* 0x403F2000 */ +#define USBFS0_USBHOST ((USBFS_USBHOST_Type*) &USBFS0->USBHOST) /* 0x403F4000 */ + +/******************************************************************************* +* SMIF +*******************************************************************************/ + +#define SMIF0_BASE 0x40420000UL +#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ +#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ +#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ +#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ + +/******************************************************************************* +* SDHC +*******************************************************************************/ + +#define SDHC0_BASE 0x40460000UL +#define SDHC0 ((SDHC_Type*) SDHC0_BASE) /* 0x40460000 */ +#define SDHC0_WRAP ((SDHC_WRAP_Type*) &SDHC0->WRAP) /* 0x40460000 */ +#define SDHC0_CORE ((SDHC_CORE_Type*) &SDHC0->CORE) /* 0x40461000 */ + +/******************************************************************************* +* CANFD +*******************************************************************************/ + +#define CANFD0_BASE 0x40520000UL +#define CANFD0 ((CANFD_Type*) CANFD0_BASE) /* 0x40520000 */ +#define CANFD0_CH0 ((CANFD_CH_Type*) &CANFD0->CH[0]) /* 0x40520000 */ +#define CANFD0_CH0_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[0].M_TTCAN) /* 0x40520000 */ + +/******************************************************************************* +* SCB +*******************************************************************************/ + +#define SCB0_BASE 0x40600000UL +#define SCB1_BASE 0x40610000UL +#define SCB2_BASE 0x40620000UL +#define SCB3_BASE 0x40630000UL +#define SCB4_BASE 0x40640000UL +#define SCB5_BASE 0x40650000UL +#define SCB6_BASE 0x40660000UL +#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40600000 */ +#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40610000 */ +#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40620000 */ +#define SCB3 ((CySCB_Type*) SCB3_BASE) /* 0x40630000 */ +#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40640000 */ +#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40650000 */ +#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40660000 */ + +/******************************************************************************* +* SAR +*******************************************************************************/ + +#define SAR_BASE 0x409D0000UL +#define SAR ((SAR_Type*) SAR_BASE) /* 0x409D0000 */ + +/******************************************************************************* +* PASS +*******************************************************************************/ + +#define PASS_BASE 0x409F0000UL +#define PASS ((PASS_Type*) PASS_BASE) /* 0x409F0000 */ +#define PASS_AREF ((PASS_AREF_Type*) &PASS->AREF) /* 0x409F0E00 */ + +/** \} CY8C6145LQI-S3F62 */ + +#endif /* _CY8C6145LQI_S3F62_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6145lqi_s3f72.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6145lqi_s3f72.h new file mode 100644 index 0000000000..987416dde1 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6145lqi_s3f72.h @@ -0,0 +1,993 @@ +/***************************************************************************//** +* \file cy8c6145lqi_s3f72.h +* +* \brief +* CY8C6145LQI-S3F72 device header +* +* \note +* Generator version: 1.6.0.225 +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CY8C6145LQI_S3F72_H_ +#define _CY8C6145LQI_S3F72_H_ + +/** +* \addtogroup group_device CY8C6145LQI-S3F72 +* \{ +*/ + +/** +* \addtogroup Configuration_of_CMSIS +* \{ +*/ + +/******************************************************************************* +* Interrupt Number Definition +*******************************************************************************/ + +typedef enum { + /* ARM Cortex-M4 Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C6145LQI-S3F72 Peripheral Interrupt Numbers */ + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_6_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #6 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + canfd_0_interrupt0_IRQn = 168, /*!< 168 [Active] Can #0, Consolidated interrupt #0 */ + canfd_0_interrupts0_0_IRQn = 169, /*!< 169 [Active] CAN #0, Interrupt #0, Channel #0 */ + canfd_0_interrupts1_0_IRQn = 170, /*!< 170 [Active] CAN #0, Interrupt #1, Channel #0 */ + cpuss_interrupts_dw1_29_IRQn = 171, /*!< 171 [Active] CPUSS DataWire #1, Channel #29 */ + cpuss_interrupts_dw1_30_IRQn = 172, /*!< 172 [Active] CPUSS DataWire #1, Channel #30 */ + cpuss_interrupts_dw1_31_IRQn = 173, /*!< 173 [Active] CPUSS DataWire #1, Channel #31 */ + unconnected_IRQn = 240 /*!< 240 Unconnected */ +} IRQn_Type; + + +/******************************************************************************* +* Processor and Core Peripheral Section +*******************************************************************************/ + +/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __CM0P_PRESENT 0 /*!< CM0P present or not */ +#define __DTCM_PRESENT 0 /*!< DTCM present or not */ +#define __ICACHE_PRESENT 0 /*!< ICACHE present or not */ +#define __DCACHE_PRESENT 0 /*!< DCACHE present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + + +/* Memory Blocks */ +#define CY_ROM_BASE 0x00000000UL +#define CY_ROM_SIZE 0x00010000UL +#define CY_SRAM_BASE 0x08000000UL +#define CY_SRAM_SIZE 0x00040000UL +#define CY_FLASH_BASE 0x10000000UL +#define CY_FLASH_SIZE 0x00080000UL +#define CY_EM_EEPROM_BASE 0x14000000UL +#define CY_EM_EEPROM_SIZE 0x00008000UL +#define CY_SFLASH_BASE 0x16000000UL +#define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL +#define CY_EFUSE_BASE 0x402C0800UL +#define CY_EFUSE_SIZE 0x00000200UL +#define CY_CAN0MRAM_BASE 0x40530000UL +#define CY_CAN0MRAM_SIZE 0x00010000UL + +#include "system_psoc6.h" /*!< PSoC 6 System */ + +/* IP List */ +#define CY_IP_MXTTCANFD 1u +#define CY_IP_MXTTCANFD_INSTANCES 1u +#define CY_IP_MXTTCANFD_VERSION 1u +#define CY_IP_M4CPUSS 1u +#define CY_IP_M4CPUSS_INSTANCES 1u +#define CY_IP_M4CPUSS_VERSION 2u +#define CY_IP_M4CPUSS_DMAC 1u +#define CY_IP_M4CPUSS_DMAC_INSTANCES 1u +#define CY_IP_M4CPUSS_DMAC_VERSION 2u +#define CY_IP_M4CPUSS_DMA 1u +#define CY_IP_M4CPUSS_DMA_INSTANCES 2u +#define CY_IP_M4CPUSS_DMA_VERSION 2u +#define CY_IP_MXCRYPTO 1u +#define CY_IP_MXCRYPTO_INSTANCES 1u +#define CY_IP_MXCRYPTO_VERSION 2u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 2u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u +#define CY_IP_MXS40PASS 1u +#define CY_IP_MXS40PASS_INSTANCES 1u +#define CY_IP_MXS40PASS_VERSION 1u +#define CY_IP_MXS40PASS_SAR 1u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u +#define CY_IP_MXS40PASS_SAR_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 7u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 1u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u + +#include "psoc6_03_config.h" +#include "gpio_psoc6_03_68_qfn.h" + +#define CY_DEVICE_PSOC6A512K +#define CY_SILICON_ID 0xE7101105UL +#define CY_HF_CLK_MAX_FREQ 150000000UL + +#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL + +/******************************************************************************* +* SFLASH +*******************************************************************************/ + +#define SFLASH_BASE 0x16000000UL +#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */ + +/******************************************************************************* +* PERI +*******************************************************************************/ + +#define PERI_BASE 0x40000000UL +#define PERI ((PERI_Type*) PERI_BASE) /* 0x40000000 */ +#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40004000 */ +#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40004020 */ +#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40004040 */ +#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x40004060 */ +#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40004080 */ +#define PERI_GR5 ((PERI_GR_Type*) &PERI->GR[5]) /* 0x400040A0 */ +#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x400040C0 */ +#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40004120 */ +#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40008000 */ +#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40008400 */ +#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40008800 */ +#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40008C00 */ +#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40009000 */ +#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40009400 */ +#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40009800 */ +#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40009C00 */ +#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ +#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ +#define PERI_TR_GR10 ((PERI_TR_GR_Type*) &PERI->TR_GR[10]) /* 0x4000A800 */ +#define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ +#define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ +#define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ +#define PERI_TR_1TO1_GR3 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[3]) /* 0x4000CC00 */ +#define PERI_TR_1TO1_GR4 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[4]) /* 0x4000D000 */ +#define PERI_TR_1TO1_GR5 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[5]) /* 0x4000D400 */ +#define PERI_TR_1TO1_GR6 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[6]) /* 0x4000D800 */ +#define PERI_TR_1TO1_GR7 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[7]) /* 0x4000DC00 */ + +/******************************************************************************* +* PERI_MS +*******************************************************************************/ + +#define PERI_MS_BASE 0x40010000UL +#define PERI_MS ((PERI_MS_Type*) PERI_MS_BASE) /* 0x40010000 */ +#define PERI_MS_PPU_PR0 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[0]) /* 0x40010000 */ +#define PERI_MS_PPU_PR1 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[1]) /* 0x40010040 */ +#define PERI_MS_PPU_PR2 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[2]) /* 0x40010080 */ +#define PERI_MS_PPU_PR3 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[3]) /* 0x400100C0 */ +#define PERI_MS_PPU_PR4 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[4]) /* 0x40010100 */ +#define PERI_MS_PPU_PR5 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[5]) /* 0x40010140 */ +#define PERI_MS_PPU_PR6 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[6]) /* 0x40010180 */ +#define PERI_MS_PPU_PR7 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[7]) /* 0x400101C0 */ +#define PERI_MS_PPU_FX_PERI_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[0]) /* 0x40010800 */ +#define PERI_MS_PPU_FX_PERI_GR0_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[1]) /* 0x40010840 */ +#define PERI_MS_PPU_FX_PERI_GR1_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[2]) /* 0x40010880 */ +#define PERI_MS_PPU_FX_PERI_GR2_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[3]) /* 0x400108C0 */ +#define PERI_MS_PPU_FX_PERI_GR3_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[4]) /* 0x40010900 */ +#define PERI_MS_PPU_FX_PERI_GR4_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[5]) /* 0x40010940 */ +#define PERI_MS_PPU_FX_PERI_GR5_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[6]) /* 0x40010980 */ +#define PERI_MS_PPU_FX_PERI_GR6_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[7]) /* 0x400109C0 */ +#define PERI_MS_PPU_FX_PERI_GR9_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[8]) /* 0x40010A00 */ +#define PERI_MS_PPU_FX_PERI_TR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[9]) /* 0x40010A40 */ +#define PERI_MS_PPU_FX_CRYPTO_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[10]) /* 0x40010A80 */ +#define PERI_MS_PPU_FX_CRYPTO_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[11]) /* 0x40010AC0 */ +#define PERI_MS_PPU_FX_CRYPTO_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[12]) /* 0x40010B00 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[13]) /* 0x40010B40 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[14]) /* 0x40010B80 */ +#define PERI_MS_PPU_FX_CRYPTO_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[15]) /* 0x40010BC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[16]) /* 0x40010C00 */ +#define PERI_MS_PPU_FX_CPUSS_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[17]) /* 0x40010C40 */ +#define PERI_MS_PPU_FX_CPUSS_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[18]) /* 0x40010C80 */ +#define PERI_MS_PPU_FX_CPUSS_CM0_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[19]) /* 0x40010CC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[20]) /* 0x40010D00 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[21]) /* 0x40010D40 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT1_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[22]) /* 0x40010D80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT0_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[23]) /* 0x40010DC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT1_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[24]) /* 0x40010E00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT2_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[25]) /* 0x40010E40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT3_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[26]) /* 0x40010E80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT4_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[27]) /* 0x40010EC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT5_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[28]) /* 0x40010F00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT6_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[29]) /* 0x40010F40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT7_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[30]) /* 0x40010F80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT8_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[31]) /* 0x40010FC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT9_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[32]) /* 0x40011000 */ +#define PERI_MS_PPU_FX_IPC_STRUCT10_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[33]) /* 0x40011040 */ +#define PERI_MS_PPU_FX_IPC_STRUCT11_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[34]) /* 0x40011080 */ +#define PERI_MS_PPU_FX_IPC_STRUCT12_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[35]) /* 0x400110C0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT13_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[36]) /* 0x40011100 */ +#define PERI_MS_PPU_FX_IPC_STRUCT14_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[37]) /* 0x40011140 */ +#define PERI_MS_PPU_FX_IPC_STRUCT15_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[38]) /* 0x40011180 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT0_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[39]) /* 0x400111C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT1_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[40]) /* 0x40011200 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT2_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[41]) /* 0x40011240 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT3_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[42]) /* 0x40011280 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT4_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[43]) /* 0x400112C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT5_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[44]) /* 0x40011300 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT6_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[45]) /* 0x40011340 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT7_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[46]) /* 0x40011380 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT8_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[47]) /* 0x400113C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT9_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[48]) /* 0x40011400 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT10_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[49]) /* 0x40011440 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT11_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[50]) /* 0x40011480 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT12_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[51]) /* 0x400114C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT13_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[52]) /* 0x40011500 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT14_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[53]) /* 0x40011540 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT15_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[54]) /* 0x40011580 */ +#define PERI_MS_PPU_FX_PROT_SMPU_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[55]) /* 0x400115C0 */ +#define PERI_MS_PPU_FX_PROT_MPU0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[56]) /* 0x40011600 */ +#define PERI_MS_PPU_FX_PROT_MPU5_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[57]) /* 0x40011640 */ +#define PERI_MS_PPU_FX_PROT_MPU14_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[58]) /* 0x40011680 */ +#define PERI_MS_PPU_FX_PROT_MPU15_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[59]) /* 0x400116C0 */ +#define PERI_MS_PPU_FX_FLASHC_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[60]) /* 0x40011700 */ +#define PERI_MS_PPU_FX_FLASHC_CMD ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[61]) /* 0x40011740 */ +#define PERI_MS_PPU_FX_FLASHC_DFT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[62]) /* 0x40011780 */ +#define PERI_MS_PPU_FX_FLASHC_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[63]) /* 0x400117C0 */ +#define PERI_MS_PPU_FX_FLASHC_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[64]) /* 0x40011800 */ +#define PERI_MS_PPU_FX_FLASHC_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[65]) /* 0x40011840 */ +#define PERI_MS_PPU_FX_FLASHC_DW0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[66]) /* 0x40011880 */ +#define PERI_MS_PPU_FX_FLASHC_DW1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[67]) /* 0x400118C0 */ +#define PERI_MS_PPU_FX_FLASHC_DMAC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[68]) /* 0x40011900 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[69]) /* 0x40011940 */ +#define PERI_MS_PPU_FX_FLASHC_FM ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[70]) /* 0x40011980 */ +#define PERI_MS_PPU_FX_SRSS_MAIN1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[71]) /* 0x400119C0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[72]) /* 0x40011A00 */ +#define PERI_MS_PPU_FX_WDT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[73]) /* 0x40011A40 */ +#define PERI_MS_PPU_FX_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[74]) /* 0x40011A80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[75]) /* 0x40011AC0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[76]) /* 0x40011B00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[77]) /* 0x40011B40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[78]) /* 0x40011B80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[79]) /* 0x40011BC0 */ +#define PERI_MS_PPU_FX_BACKUP_BACKUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[80]) /* 0x40011C00 */ +#define PERI_MS_PPU_FX_DW0_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[81]) /* 0x40011C40 */ +#define PERI_MS_PPU_FX_DW1_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[82]) /* 0x40011C80 */ +#define PERI_MS_PPU_FX_DW0_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[83]) /* 0x40011CC0 */ +#define PERI_MS_PPU_FX_DW1_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[84]) /* 0x40011D00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[85]) /* 0x40011D40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[86]) /* 0x40011D80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[87]) /* 0x40011DC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[88]) /* 0x40011E00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[89]) /* 0x40011E40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[90]) /* 0x40011E80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[91]) /* 0x40011EC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[92]) /* 0x40011F00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[93]) /* 0x40011F40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[94]) /* 0x40011F80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[95]) /* 0x40011FC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[96]) /* 0x40012000 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[97]) /* 0x40012040 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[98]) /* 0x40012080 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[99]) /* 0x400120C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[100]) /* 0x40012100 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[101]) /* 0x40012140 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[102]) /* 0x40012180 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[103]) /* 0x400121C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[104]) /* 0x40012200 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[105]) /* 0x40012240 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[106]) /* 0x40012280 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[107]) /* 0x400122C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[108]) /* 0x40012300 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[109]) /* 0x40012340 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[110]) /* 0x40012380 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[111]) /* 0x400123C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[112]) /* 0x40012400 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[113]) /* 0x40012440 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[114]) /* 0x40012480 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[115]) /* 0x400124C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[116]) /* 0x40012500 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[117]) /* 0x40012540 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[118]) /* 0x40012580 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[119]) /* 0x400125C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[120]) /* 0x40012600 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[121]) /* 0x40012640 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[122]) /* 0x40012680 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[123]) /* 0x400126C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[124]) /* 0x40012700 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[125]) /* 0x40012740 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[126]) /* 0x40012780 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[127]) /* 0x400127C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[128]) /* 0x40012800 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[129]) /* 0x40012840 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[130]) /* 0x40012880 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[131]) /* 0x400128C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[132]) /* 0x40012900 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[133]) /* 0x40012940 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[134]) /* 0x40012980 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[135]) /* 0x400129C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[136]) /* 0x40012A00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[137]) /* 0x40012A40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[138]) /* 0x40012A80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[139]) /* 0x40012AC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[140]) /* 0x40012B00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[141]) /* 0x40012B40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[142]) /* 0x40012B80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT29_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[143]) /* 0x40012BC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT30_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[144]) /* 0x40012C00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT31_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[145]) /* 0x40012C40 */ +#define PERI_MS_PPU_FX_DMAC_TOP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[146]) /* 0x40012C80 */ +#define PERI_MS_PPU_FX_DMAC_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[147]) /* 0x40012CC0 */ +#define PERI_MS_PPU_FX_DMAC_CH1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[148]) /* 0x40012D00 */ +#define PERI_MS_PPU_FX_EFUSE_CTL ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[149]) /* 0x40012D40 */ +#define PERI_MS_PPU_FX_EFUSE_DATA ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[150]) /* 0x40012D80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[151]) /* 0x40012DC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[152]) /* 0x40012E00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[153]) /* 0x40012E40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[154]) /* 0x40012E80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[155]) /* 0x40012EC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[156]) /* 0x40012F00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[157]) /* 0x40012F40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[158]) /* 0x40012F80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[159]) /* 0x40012FC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[160]) /* 0x40013000 */ +#define PERI_MS_PPU_FX_HSIOM_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[161]) /* 0x40013040 */ +#define PERI_MS_PPU_FX_HSIOM_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[162]) /* 0x40013080 */ +#define PERI_MS_PPU_FX_HSIOM_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[163]) /* 0x400130C0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[164]) /* 0x40013100 */ +#define PERI_MS_PPU_FX_HSIOM_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[165]) /* 0x40013140 */ +#define PERI_MS_PPU_FX_HSIOM_AMUX ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[166]) /* 0x40013180 */ +#define PERI_MS_PPU_FX_HSIOM_MON ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[167]) /* 0x400131C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[168]) /* 0x40013200 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[169]) /* 0x40013240 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[170]) /* 0x40013280 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[171]) /* 0x400132C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[172]) /* 0x40013300 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[173]) /* 0x40013340 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[174]) /* 0x40013380 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[175]) /* 0x400133C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[176]) /* 0x40013400 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[177]) /* 0x40013440 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[178]) /* 0x40013480 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[179]) /* 0x400134C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[180]) /* 0x40013500 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[181]) /* 0x40013540 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[182]) /* 0x40013580 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[183]) /* 0x400135C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[184]) /* 0x40013600 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[185]) /* 0x40013640 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[186]) /* 0x40013680 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[187]) /* 0x400136C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[188]) /* 0x40013700 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[189]) /* 0x40013740 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[190]) /* 0x40013780 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[191]) /* 0x400137C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[192]) /* 0x40013800 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[193]) /* 0x40013840 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[194]) /* 0x40013880 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[195]) /* 0x400138C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[196]) /* 0x40013900 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[197]) /* 0x40013940 */ +#define PERI_MS_PPU_FX_GPIO_GPIO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[198]) /* 0x40013980 */ +#define PERI_MS_PPU_FX_GPIO_TEST ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[199]) /* 0x400139C0 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[200]) /* 0x40013A00 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[201]) /* 0x40013A40 */ +#define PERI_MS_PPU_FX_LPCOMP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[202]) /* 0x40013A80 */ +#define PERI_MS_PPU_FX_CSD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[203]) /* 0x40013AC0 */ +#define PERI_MS_PPU_FX_TCPWM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[204]) /* 0x40013B00 */ +#define PERI_MS_PPU_FX_TCPWM1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[205]) /* 0x40013B40 */ +#define PERI_MS_PPU_FX_LCD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[206]) /* 0x40013B80 */ +#define PERI_MS_PPU_FX_USBFS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[207]) /* 0x40013BC0 */ +#define PERI_MS_PPU_FX_SMIF0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[208]) /* 0x40013C00 */ +#define PERI_MS_PPU_FX_SDHC0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[209]) /* 0x40013C40 */ +#define PERI_MS_PPU_FX_CANFD0_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[210]) /* 0x40013C80 */ +#define PERI_MS_PPU_FX_CANFD0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[211]) /* 0x40013CC0 */ +#define PERI_MS_PPU_FX_CANFD0_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[212]) /* 0x40013D00 */ +#define PERI_MS_PPU_FX_SCB0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[213]) /* 0x40013D40 */ +#define PERI_MS_PPU_FX_SCB1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[214]) /* 0x40013D80 */ +#define PERI_MS_PPU_FX_SCB2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[215]) /* 0x40013DC0 */ +#define PERI_MS_PPU_FX_SCB3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[216]) /* 0x40013E00 */ +#define PERI_MS_PPU_FX_SCB4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[217]) /* 0x40013E40 */ +#define PERI_MS_PPU_FX_SCB5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[218]) /* 0x40013E80 */ +#define PERI_MS_PPU_FX_SCB6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[219]) /* 0x40013EC0 */ + +/******************************************************************************* +* CRYPTO +*******************************************************************************/ + +#define CRYPTO_BASE 0x40100000UL +#define CRYPTO ((CRYPTO_Type*) CRYPTO_BASE) /* 0x40100000 */ + +/******************************************************************************* +* CPUSS +*******************************************************************************/ + +#define CPUSS_BASE 0x40200000UL +#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40200000 */ + +/******************************************************************************* +* FAULT +*******************************************************************************/ + +#define FAULT_BASE 0x40210000UL +#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40210000 */ +#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40210000 */ +#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40210100 */ + +/******************************************************************************* +* IPC +*******************************************************************************/ + +#define IPC_BASE 0x40220000UL +#define IPC ((IPC_Type*) IPC_BASE) /* 0x40220000 */ +#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40220000 */ +#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40220020 */ +#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40220040 */ +#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40220060 */ +#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40220080 */ +#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402200A0 */ +#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402200C0 */ +#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402200E0 */ +#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40220100 */ +#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40220120 */ +#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40220140 */ +#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40220160 */ +#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40220180 */ +#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402201A0 */ +#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402201C0 */ +#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402201E0 */ +#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40221000 */ +#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40221020 */ +#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40221040 */ +#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40221060 */ +#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40221080 */ +#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402210A0 */ +#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402210C0 */ +#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402210E0 */ +#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40221100 */ +#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40221120 */ +#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40221140 */ +#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40221160 */ +#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40221180 */ +#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402211A0 */ +#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402211C0 */ +#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402211E0 */ + +/******************************************************************************* +* PROT +*******************************************************************************/ + +#define PROT_BASE 0x40230000UL +#define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ +#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ +#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ +#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402320C0 */ +#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40232100 */ +#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40232140 */ +#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40232180 */ +#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402321C0 */ +#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40232200 */ +#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40232240 */ +#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40232280 */ +#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402322C0 */ +#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40232300 */ +#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ +#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ +#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ +#define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ +#define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ +#define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ +#define PROT_MPU5_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[3]) /* 0x40235660 */ +#define PROT_MPU5_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[4]) /* 0x40235680 */ +#define PROT_MPU5_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[5]) /* 0x402356A0 */ +#define PROT_MPU5_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[6]) /* 0x402356C0 */ +#define PROT_MPU5_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[7]) /* 0x402356E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ + +/******************************************************************************* +* FLASHC +*******************************************************************************/ + +#define FLASHC_BASE 0x40240000UL +#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40240000 */ +#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4024F000 */ + +/******************************************************************************* +* SRSS +*******************************************************************************/ + +#define SRSS_BASE 0x40260000UL +#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ +#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */ +#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */ + +/******************************************************************************* +* BACKUP +*******************************************************************************/ + +#define BACKUP_BASE 0x40270000UL +#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ + +/******************************************************************************* +* DW +*******************************************************************************/ + +#define DW0_BASE 0x40280000UL +#define DW1_BASE 0x40290000UL +#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ +#define DW1 ((DW_Type*) DW1_BASE) /* 0x40290000 */ +#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40288000 */ +#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40288040 */ +#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40288080 */ +#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x402880C0 */ +#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40288100 */ +#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x40288140 */ +#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x40288180 */ +#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402881C0 */ +#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40288200 */ +#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40288240 */ +#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40288280 */ +#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x402882C0 */ +#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40288300 */ +#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x40288340 */ +#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x40288380 */ +#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402883C0 */ +#define DW0_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[16]) /* 0x40288400 */ +#define DW0_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[17]) /* 0x40288440 */ +#define DW0_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[18]) /* 0x40288480 */ +#define DW0_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[19]) /* 0x402884C0 */ +#define DW0_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[20]) /* 0x40288500 */ +#define DW0_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[21]) /* 0x40288540 */ +#define DW0_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[22]) /* 0x40288580 */ +#define DW0_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[23]) /* 0x402885C0 */ +#define DW0_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[24]) /* 0x40288600 */ +#define DW0_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[25]) /* 0x40288640 */ +#define DW0_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[26]) /* 0x40288680 */ +#define DW0_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[27]) /* 0x402886C0 */ +#define DW0_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[28]) /* 0x40288700 */ +#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40298000 */ +#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40298040 */ +#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40298080 */ +#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x402980C0 */ +#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40298100 */ +#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x40298140 */ +#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x40298180 */ +#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402981C0 */ +#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40298200 */ +#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40298240 */ +#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40298280 */ +#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x402982C0 */ +#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40298300 */ +#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x40298340 */ +#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x40298380 */ +#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402983C0 */ +#define DW1_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[16]) /* 0x40298400 */ +#define DW1_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[17]) /* 0x40298440 */ +#define DW1_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[18]) /* 0x40298480 */ +#define DW1_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[19]) /* 0x402984C0 */ +#define DW1_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[20]) /* 0x40298500 */ +#define DW1_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[21]) /* 0x40298540 */ +#define DW1_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[22]) /* 0x40298580 */ +#define DW1_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[23]) /* 0x402985C0 */ +#define DW1_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[24]) /* 0x40298600 */ +#define DW1_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[25]) /* 0x40298640 */ +#define DW1_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[26]) /* 0x40298680 */ +#define DW1_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[27]) /* 0x402986C0 */ +#define DW1_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[28]) /* 0x40298700 */ +#define DW1_CH_STRUCT29 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[29]) /* 0x40298740 */ +#define DW1_CH_STRUCT30 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[30]) /* 0x40298780 */ +#define DW1_CH_STRUCT31 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[31]) /* 0x402987C0 */ + +/******************************************************************************* +* DMAC +*******************************************************************************/ + +#define DMAC_BASE 0x402A0000UL +#define DMAC ((DMAC_Type*) DMAC_BASE) /* 0x402A0000 */ +#define DMAC_CH0 ((DMAC_CH_Type*) &DMAC->CH[0]) /* 0x402A1000 */ +#define DMAC_CH1 ((DMAC_CH_Type*) &DMAC->CH[1]) /* 0x402A1100 */ + +/******************************************************************************* +* EFUSE +*******************************************************************************/ + +#define EFUSE_BASE 0x402C0000UL +#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ + +/******************************************************************************* +* HSIOM +*******************************************************************************/ + +#define HSIOM_BASE 0x40300000UL +#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40300000 */ +#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40300000 */ +#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40300010 */ +#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40300020 */ +#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40300030 */ +#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40300040 */ +#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40300050 */ +#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40300060 */ +#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40300070 */ +#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40300080 */ +#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40300090 */ +#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403000A0 */ +#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403000B0 */ +#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403000C0 */ +#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403000D0 */ +#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403000E0 */ + +/******************************************************************************* +* GPIO +*******************************************************************************/ + +#define GPIO_BASE 0x40310000UL +#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40310000 */ +#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40310000 */ +#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40310080 */ +#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40310100 */ +#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40310180 */ +#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40310200 */ +#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40310280 */ +#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40310300 */ +#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40310380 */ +#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40310400 */ +#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40310480 */ +#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40310500 */ +#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40310580 */ +#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40310600 */ +#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40310680 */ +#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40310700 */ + +/******************************************************************************* +* SMARTIO +*******************************************************************************/ + +#define SMARTIO_BASE 0x40320000UL +#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40320000 */ +#define SMARTIO_PRT8 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[8]) /* 0x40320800 */ +#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40320900 */ + +/******************************************************************************* +* LPCOMP +*******************************************************************************/ + +#define LPCOMP_BASE 0x40350000UL +#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */ + +/******************************************************************************* +* CSD +*******************************************************************************/ + +#define CSD0_BASE 0x40360000UL +#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */ + +/******************************************************************************* +* TCPWM +*******************************************************************************/ + +#define TCPWM0_BASE 0x40380000UL +#define TCPWM1_BASE 0x40390000UL +#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM1 ((TCPWM_Type*) TCPWM1_BASE) /* 0x40390000 */ +#define TCPWM0_CNT0 ((TCPWM_CNT_Type*) &TCPWM0->CNT[0]) /* 0x40380100 */ +#define TCPWM0_CNT1 ((TCPWM_CNT_Type*) &TCPWM0->CNT[1]) /* 0x40380140 */ +#define TCPWM0_CNT2 ((TCPWM_CNT_Type*) &TCPWM0->CNT[2]) /* 0x40380180 */ +#define TCPWM0_CNT3 ((TCPWM_CNT_Type*) &TCPWM0->CNT[3]) /* 0x403801C0 */ +#define TCPWM1_CNT0 ((TCPWM_CNT_Type*) &TCPWM1->CNT[0]) /* 0x40390100 */ +#define TCPWM1_CNT1 ((TCPWM_CNT_Type*) &TCPWM1->CNT[1]) /* 0x40390140 */ +#define TCPWM1_CNT2 ((TCPWM_CNT_Type*) &TCPWM1->CNT[2]) /* 0x40390180 */ +#define TCPWM1_CNT3 ((TCPWM_CNT_Type*) &TCPWM1->CNT[3]) /* 0x403901C0 */ +#define TCPWM1_CNT4 ((TCPWM_CNT_Type*) &TCPWM1->CNT[4]) /* 0x40390200 */ +#define TCPWM1_CNT5 ((TCPWM_CNT_Type*) &TCPWM1->CNT[5]) /* 0x40390240 */ +#define TCPWM1_CNT6 ((TCPWM_CNT_Type*) &TCPWM1->CNT[6]) /* 0x40390280 */ +#define TCPWM1_CNT7 ((TCPWM_CNT_Type*) &TCPWM1->CNT[7]) /* 0x403902C0 */ + +/******************************************************************************* +* LCD +*******************************************************************************/ + +#define LCD0_BASE 0x403B0000UL +#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ + +/******************************************************************************* +* USBFS +*******************************************************************************/ + +#define USBFS0_BASE 0x403F0000UL +#define USBFS0 ((USBFS_Type*) USBFS0_BASE) /* 0x403F0000 */ +#define USBFS0_USBDEV ((USBFS_USBDEV_Type*) &USBFS0->USBDEV) /* 0x403F0000 */ +#define USBFS0_USBLPM ((USBFS_USBLPM_Type*) &USBFS0->USBLPM) /* 0x403F2000 */ +#define USBFS0_USBHOST ((USBFS_USBHOST_Type*) &USBFS0->USBHOST) /* 0x403F4000 */ + +/******************************************************************************* +* SMIF +*******************************************************************************/ + +#define SMIF0_BASE 0x40420000UL +#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ +#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ +#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ +#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ + +/******************************************************************************* +* SDHC +*******************************************************************************/ + +#define SDHC0_BASE 0x40460000UL +#define SDHC0 ((SDHC_Type*) SDHC0_BASE) /* 0x40460000 */ +#define SDHC0_WRAP ((SDHC_WRAP_Type*) &SDHC0->WRAP) /* 0x40460000 */ +#define SDHC0_CORE ((SDHC_CORE_Type*) &SDHC0->CORE) /* 0x40461000 */ + +/******************************************************************************* +* CANFD +*******************************************************************************/ + +#define CANFD0_BASE 0x40520000UL +#define CANFD0 ((CANFD_Type*) CANFD0_BASE) /* 0x40520000 */ +#define CANFD0_CH0 ((CANFD_CH_Type*) &CANFD0->CH[0]) /* 0x40520000 */ +#define CANFD0_CH0_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[0].M_TTCAN) /* 0x40520000 */ + +/******************************************************************************* +* SCB +*******************************************************************************/ + +#define SCB0_BASE 0x40600000UL +#define SCB1_BASE 0x40610000UL +#define SCB2_BASE 0x40620000UL +#define SCB3_BASE 0x40630000UL +#define SCB4_BASE 0x40640000UL +#define SCB5_BASE 0x40650000UL +#define SCB6_BASE 0x40660000UL +#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40600000 */ +#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40610000 */ +#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40620000 */ +#define SCB3 ((CySCB_Type*) SCB3_BASE) /* 0x40630000 */ +#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40640000 */ +#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40650000 */ +#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40660000 */ + +/******************************************************************************* +* SAR +*******************************************************************************/ + +#define SAR_BASE 0x409D0000UL +#define SAR ((SAR_Type*) SAR_BASE) /* 0x409D0000 */ + +/******************************************************************************* +* PASS +*******************************************************************************/ + +#define PASS_BASE 0x409F0000UL +#define PASS ((PASS_Type*) PASS_BASE) /* 0x409F0000 */ +#define PASS_AREF ((PASS_AREF_Type*) &PASS->AREF) /* 0x409F0E00 */ + +/** \} CY8C6145LQI-S3F72 */ + +#endif /* _CY8C6145LQI_S3F72_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6148azi_s2f44.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6148azi_s2f44.h new file mode 100644 index 0000000000..5987877e67 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6148azi_s2f44.h @@ -0,0 +1,1098 @@ +/***************************************************************************//** +* \file cy8c6148azi_s2f44.h +* +* \brief +* CY8C6148AZI-S2F44 device header +* +* \note +* Generator version: 1.6.0.225 +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CY8C6148AZI_S2F44_H_ +#define _CY8C6148AZI_S2F44_H_ + +/** +* \addtogroup group_device CY8C6148AZI-S2F44 +* \{ +*/ + +/** +* \addtogroup Configuration_of_CMSIS +* \{ +*/ + +/******************************************************************************* +* Interrupt Number Definition +*******************************************************************************/ + +typedef enum { + /* ARM Cortex-M4 Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C6148AZI-S2F44 Peripheral Interrupt Numbers */ + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_1_IRQn = 1, /*!< 1 [DeepSleep] GPIO Port Interrupt #1 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_4_IRQn = 4, /*!< 4 [DeepSleep] GPIO Port Interrupt #4 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_13_IRQn = 13, /*!< 13 [DeepSleep] GPIO Port Interrupt #13 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_8_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #8 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + scb_6_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #6 */ + scb_7_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #7 */ + scb_9_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #9 */ + scb_10_interrupt_IRQn = 48, /*!< 48 [Active] Serial Communication Block #10 */ + scb_11_interrupt_IRQn = 49, /*!< 49 [Active] Serial Communication Block #11 */ + scb_12_interrupt_IRQn = 50, /*!< 50 [Active] Serial Communication Block #12 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dmac_2_IRQn = 54, /*!< 54 [Active] CPUSS DMAC, Channel #2 */ + cpuss_interrupts_dmac_3_IRQn = 55, /*!< 55 [Active] CPUSS DMAC, Channel #3 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_0_interrupts_4_IRQn = 127, /*!< 127 [Active] TCPWM #0, Counter #4 */ + tcpwm_0_interrupts_5_IRQn = 128, /*!< 128 [Active] TCPWM #0, Counter #5 */ + tcpwm_0_interrupts_6_IRQn = 129, /*!< 129 [Active] TCPWM #0, Counter #6 */ + tcpwm_0_interrupts_7_IRQn = 130, /*!< 130 [Active] TCPWM #0, Counter #7 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + tcpwm_1_interrupts_8_IRQn = 139, /*!< 139 [Active] TCPWM #1, Counter #8 */ + tcpwm_1_interrupts_9_IRQn = 140, /*!< 140 [Active] TCPWM #1, Counter #9 */ + tcpwm_1_interrupts_10_IRQn = 141, /*!< 141 [Active] TCPWM #1, Counter #10 */ + tcpwm_1_interrupts_11_IRQn = 142, /*!< 142 [Active] TCPWM #1, Counter #11 */ + tcpwm_1_interrupts_12_IRQn = 143, /*!< 143 [Active] TCPWM #1, Counter #12 */ + tcpwm_1_interrupts_13_IRQn = 144, /*!< 144 [Active] TCPWM #1, Counter #13 */ + tcpwm_1_interrupts_14_IRQn = 145, /*!< 145 [Active] TCPWM #1, Counter #14 */ + tcpwm_1_interrupts_15_IRQn = 146, /*!< 146 [Active] TCPWM #1, Counter #15 */ + tcpwm_1_interrupts_16_IRQn = 147, /*!< 147 [Active] TCPWM #1, Counter #16 */ + tcpwm_1_interrupts_17_IRQn = 148, /*!< 148 [Active] TCPWM #1, Counter #17 */ + tcpwm_1_interrupts_18_IRQn = 149, /*!< 149 [Active] TCPWM #1, Counter #18 */ + tcpwm_1_interrupts_19_IRQn = 150, /*!< 150 [Active] TCPWM #1, Counter #19 */ + tcpwm_1_interrupts_20_IRQn = 151, /*!< 151 [Active] TCPWM #1, Counter #20 */ + tcpwm_1_interrupts_21_IRQn = 152, /*!< 152 [Active] TCPWM #1, Counter #21 */ + tcpwm_1_interrupts_22_IRQn = 153, /*!< 153 [Active] TCPWM #1, Counter #22 */ + tcpwm_1_interrupts_23_IRQn = 154, /*!< 154 [Active] TCPWM #1, Counter #23 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + audioss_0_interrupt_i2s_IRQn = 156, /*!< 156 [Active] I2S0 Audio interrupt */ + audioss_0_interrupt_pdm_IRQn = 157, /*!< 157 [Active] PDM0/PCM0 Audio interrupt */ + audioss_1_interrupt_i2s_IRQn = 158, /*!< 158 [Active] I2S1 Audio interrupt */ + profile_interrupt_IRQn = 159, /*!< 159 [Active] Energy Profiler interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + sdhc_1_interrupt_wakeup_IRQn = 166, /*!< 166 [Active] EEMC wakeup interrupt for mxsdhc, not used */ + sdhc_1_interrupt_general_IRQn = 167, /*!< 167 [Active] Consolidated interrupt for mxsdhc for everything else */ + unconnected_IRQn = 240 /*!< 240 Unconnected */ +} IRQn_Type; + + +/******************************************************************************* +* Processor and Core Peripheral Section +*******************************************************************************/ + +/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __CM0P_PRESENT 0 /*!< CM0P present or not */ +#define __DTCM_PRESENT 0 /*!< DTCM present or not */ +#define __ICACHE_PRESENT 0 /*!< ICACHE present or not */ +#define __DCACHE_PRESENT 0 /*!< DCACHE present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + + +/* Memory Blocks */ +#define CY_ROM_BASE 0x00000000UL +#define CY_ROM_SIZE 0x00010000UL +#define CY_SRAM_BASE 0x08000000UL +#define CY_SRAM_SIZE 0x00080000UL +#define CY_FLASH_BASE 0x10000000UL +#define CY_FLASH_SIZE 0x00100000UL +#define CY_EM_EEPROM_BASE 0x14000000UL +#define CY_EM_EEPROM_SIZE 0x00008000UL +#define CY_SFLASH_BASE 0x16000000UL +#define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL +#define CY_EFUSE_BASE 0x402C0800UL +#define CY_EFUSE_SIZE 0x00000200UL + +#include "system_psoc6.h" /*!< PSoC 6 System */ + +/* IP List */ +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 2u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_M4CPUSS 1u +#define CY_IP_M4CPUSS_INSTANCES 1u +#define CY_IP_M4CPUSS_VERSION 2u +#define CY_IP_M4CPUSS_DMAC 1u +#define CY_IP_M4CPUSS_DMAC_INSTANCES 1u +#define CY_IP_M4CPUSS_DMAC_VERSION 2u +#define CY_IP_M4CPUSS_DMA 1u +#define CY_IP_M4CPUSS_DMA_INSTANCES 2u +#define CY_IP_M4CPUSS_DMA_VERSION 2u +#define CY_IP_MXCRYPTO 1u +#define CY_IP_MXCRYPTO_INSTANCES 1u +#define CY_IP_MXCRYPTO_VERSION 2u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u +#define CY_IP_MXS40PASS 1u +#define CY_IP_MXS40PASS_INSTANCES 1u +#define CY_IP_MXS40PASS_VERSION 1u +#define CY_IP_MXS40PASS_SAR 1u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u +#define CY_IP_MXS40PASS_SAR_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXPROFILE 1u +#define CY_IP_MXPROFILE_INSTANCES 1u +#define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 13u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 2u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u + +#include "psoc6_02_config.h" +#include "gpio_psoc6_02_128_tqfp.h" + +#define CY_DEVICE_PSOC6A2M +#define CY_SILICON_ID 0xE4621202UL +#define CY_HF_CLK_MAX_FREQ 150000000UL + +#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL + +/******************************************************************************* +* SFLASH +*******************************************************************************/ + +#define SFLASH_BASE 0x16000000UL +#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */ + +/******************************************************************************* +* PERI +*******************************************************************************/ + +#define PERI_BASE 0x40000000UL +#define PERI ((PERI_Type*) PERI_BASE) /* 0x40000000 */ +#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40004000 */ +#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40004020 */ +#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40004040 */ +#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x40004060 */ +#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40004080 */ +#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x400040C0 */ +#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40004120 */ +#define PERI_GR10 ((PERI_GR_Type*) &PERI->GR[10]) /* 0x40004140 */ +#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40008000 */ +#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40008400 */ +#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40008800 */ +#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40008C00 */ +#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40009000 */ +#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40009400 */ +#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40009800 */ +#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40009C00 */ +#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ +#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ +#define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ +#define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ +#define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ +#define PERI_TR_1TO1_GR3 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[3]) /* 0x4000CC00 */ +#define PERI_TR_1TO1_GR4 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[4]) /* 0x4000D000 */ +#define PERI_TR_1TO1_GR5 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[5]) /* 0x4000D400 */ +#define PERI_TR_1TO1_GR6 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[6]) /* 0x4000D800 */ + +/******************************************************************************* +* PERI_MS +*******************************************************************************/ + +#define PERI_MS_BASE 0x40010000UL +#define PERI_MS ((PERI_MS_Type*) PERI_MS_BASE) /* 0x40010000 */ +#define PERI_MS_PPU_PR0 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[0]) /* 0x40010000 */ +#define PERI_MS_PPU_PR1 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[1]) /* 0x40010040 */ +#define PERI_MS_PPU_PR2 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[2]) /* 0x40010080 */ +#define PERI_MS_PPU_PR3 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[3]) /* 0x400100C0 */ +#define PERI_MS_PPU_PR4 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[4]) /* 0x40010100 */ +#define PERI_MS_PPU_PR5 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[5]) /* 0x40010140 */ +#define PERI_MS_PPU_PR6 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[6]) /* 0x40010180 */ +#define PERI_MS_PPU_PR7 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[7]) /* 0x400101C0 */ +#define PERI_MS_PPU_FX_PERI_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[0]) /* 0x40010800 */ +#define PERI_MS_PPU_FX_PERI_GR0_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[1]) /* 0x40010840 */ +#define PERI_MS_PPU_FX_PERI_GR1_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[2]) /* 0x40010880 */ +#define PERI_MS_PPU_FX_PERI_GR2_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[3]) /* 0x400108C0 */ +#define PERI_MS_PPU_FX_PERI_GR3_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[4]) /* 0x40010900 */ +#define PERI_MS_PPU_FX_PERI_GR4_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[5]) /* 0x40010940 */ +#define PERI_MS_PPU_FX_PERI_GR6_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[6]) /* 0x40010980 */ +#define PERI_MS_PPU_FX_PERI_GR9_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[7]) /* 0x400109C0 */ +#define PERI_MS_PPU_FX_PERI_GR10_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[8]) /* 0x40010A00 */ +#define PERI_MS_PPU_FX_PERI_TR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[9]) /* 0x40010A40 */ +#define PERI_MS_PPU_FX_CRYPTO_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[10]) /* 0x40010A80 */ +#define PERI_MS_PPU_FX_CRYPTO_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[11]) /* 0x40010AC0 */ +#define PERI_MS_PPU_FX_CRYPTO_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[12]) /* 0x40010B00 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[13]) /* 0x40010B40 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[14]) /* 0x40010B80 */ +#define PERI_MS_PPU_FX_CRYPTO_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[15]) /* 0x40010BC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[16]) /* 0x40010C00 */ +#define PERI_MS_PPU_FX_CPUSS_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[17]) /* 0x40010C40 */ +#define PERI_MS_PPU_FX_CPUSS_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[18]) /* 0x40010C80 */ +#define PERI_MS_PPU_FX_CPUSS_CM0_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[19]) /* 0x40010CC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[20]) /* 0x40010D00 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[21]) /* 0x40010D40 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT1_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[22]) /* 0x40010D80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT0_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[23]) /* 0x40010DC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT1_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[24]) /* 0x40010E00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT2_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[25]) /* 0x40010E40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT3_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[26]) /* 0x40010E80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT4_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[27]) /* 0x40010EC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT5_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[28]) /* 0x40010F00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT6_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[29]) /* 0x40010F40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT7_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[30]) /* 0x40010F80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT8_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[31]) /* 0x40010FC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT9_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[32]) /* 0x40011000 */ +#define PERI_MS_PPU_FX_IPC_STRUCT10_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[33]) /* 0x40011040 */ +#define PERI_MS_PPU_FX_IPC_STRUCT11_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[34]) /* 0x40011080 */ +#define PERI_MS_PPU_FX_IPC_STRUCT12_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[35]) /* 0x400110C0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT13_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[36]) /* 0x40011100 */ +#define PERI_MS_PPU_FX_IPC_STRUCT14_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[37]) /* 0x40011140 */ +#define PERI_MS_PPU_FX_IPC_STRUCT15_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[38]) /* 0x40011180 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT0_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[39]) /* 0x400111C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT1_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[40]) /* 0x40011200 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT2_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[41]) /* 0x40011240 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT3_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[42]) /* 0x40011280 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT4_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[43]) /* 0x400112C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT5_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[44]) /* 0x40011300 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT6_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[45]) /* 0x40011340 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT7_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[46]) /* 0x40011380 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT8_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[47]) /* 0x400113C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT9_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[48]) /* 0x40011400 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT10_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[49]) /* 0x40011440 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT11_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[50]) /* 0x40011480 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT12_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[51]) /* 0x400114C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT13_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[52]) /* 0x40011500 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT14_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[53]) /* 0x40011540 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT15_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[54]) /* 0x40011580 */ +#define PERI_MS_PPU_FX_PROT_SMPU_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[55]) /* 0x400115C0 */ +#define PERI_MS_PPU_FX_PROT_MPU0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[56]) /* 0x40011600 */ +#define PERI_MS_PPU_FX_PROT_MPU5_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[57]) /* 0x40011640 */ +#define PERI_MS_PPU_FX_PROT_MPU6_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[58]) /* 0x40011680 */ +#define PERI_MS_PPU_FX_PROT_MPU14_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[59]) /* 0x400116C0 */ +#define PERI_MS_PPU_FX_PROT_MPU15_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[60]) /* 0x40011700 */ +#define PERI_MS_PPU_FX_FLASHC_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[61]) /* 0x40011740 */ +#define PERI_MS_PPU_FX_FLASHC_CMD ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[62]) /* 0x40011780 */ +#define PERI_MS_PPU_FX_FLASHC_DFT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[63]) /* 0x400117C0 */ +#define PERI_MS_PPU_FX_FLASHC_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[64]) /* 0x40011800 */ +#define PERI_MS_PPU_FX_FLASHC_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[65]) /* 0x40011840 */ +#define PERI_MS_PPU_FX_FLASHC_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[66]) /* 0x40011880 */ +#define PERI_MS_PPU_FX_FLASHC_DW0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[67]) /* 0x400118C0 */ +#define PERI_MS_PPU_FX_FLASHC_DW1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[68]) /* 0x40011900 */ +#define PERI_MS_PPU_FX_FLASHC_DMAC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[69]) /* 0x40011940 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[70]) /* 0x40011980 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[71]) /* 0x400119C0 */ +#define PERI_MS_PPU_FX_FLASHC_FM ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[72]) /* 0x40011A00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[73]) /* 0x40011A40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[74]) /* 0x40011A80 */ +#define PERI_MS_PPU_FX_WDT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[75]) /* 0x40011AC0 */ +#define PERI_MS_PPU_FX_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[76]) /* 0x40011B00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[77]) /* 0x40011B40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[78]) /* 0x40011B80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[79]) /* 0x40011BC0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[80]) /* 0x40011C00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[81]) /* 0x40011C40 */ +#define PERI_MS_PPU_FX_BACKUP_BACKUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[82]) /* 0x40011C80 */ +#define PERI_MS_PPU_FX_DW0_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[83]) /* 0x40011CC0 */ +#define PERI_MS_PPU_FX_DW1_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[84]) /* 0x40011D00 */ +#define PERI_MS_PPU_FX_DW0_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[85]) /* 0x40011D40 */ +#define PERI_MS_PPU_FX_DW1_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[86]) /* 0x40011D80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[87]) /* 0x40011DC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[88]) /* 0x40011E00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[89]) /* 0x40011E40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[90]) /* 0x40011E80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[91]) /* 0x40011EC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[92]) /* 0x40011F00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[93]) /* 0x40011F40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[94]) /* 0x40011F80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[95]) /* 0x40011FC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[96]) /* 0x40012000 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[97]) /* 0x40012040 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[98]) /* 0x40012080 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[99]) /* 0x400120C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[100]) /* 0x40012100 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[101]) /* 0x40012140 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[102]) /* 0x40012180 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[103]) /* 0x400121C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[104]) /* 0x40012200 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[105]) /* 0x40012240 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[106]) /* 0x40012280 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[107]) /* 0x400122C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[108]) /* 0x40012300 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[109]) /* 0x40012340 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[110]) /* 0x40012380 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[111]) /* 0x400123C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[112]) /* 0x40012400 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[113]) /* 0x40012440 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[114]) /* 0x40012480 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[115]) /* 0x400124C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[116]) /* 0x40012500 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[117]) /* 0x40012540 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[118]) /* 0x40012580 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[119]) /* 0x400125C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[120]) /* 0x40012600 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[121]) /* 0x40012640 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[122]) /* 0x40012680 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[123]) /* 0x400126C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[124]) /* 0x40012700 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[125]) /* 0x40012740 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[126]) /* 0x40012780 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[127]) /* 0x400127C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[128]) /* 0x40012800 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[129]) /* 0x40012840 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[130]) /* 0x40012880 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[131]) /* 0x400128C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[132]) /* 0x40012900 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[133]) /* 0x40012940 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[134]) /* 0x40012980 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[135]) /* 0x400129C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[136]) /* 0x40012A00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[137]) /* 0x40012A40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[138]) /* 0x40012A80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[139]) /* 0x40012AC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[140]) /* 0x40012B00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[141]) /* 0x40012B40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[142]) /* 0x40012B80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[143]) /* 0x40012BC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[144]) /* 0x40012C00 */ +#define PERI_MS_PPU_FX_DMAC_TOP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[145]) /* 0x40012C40 */ +#define PERI_MS_PPU_FX_DMAC_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[146]) /* 0x40012C80 */ +#define PERI_MS_PPU_FX_DMAC_CH1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[147]) /* 0x40012CC0 */ +#define PERI_MS_PPU_FX_DMAC_CH2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[148]) /* 0x40012D00 */ +#define PERI_MS_PPU_FX_DMAC_CH3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[149]) /* 0x40012D40 */ +#define PERI_MS_PPU_FX_EFUSE_CTL ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[150]) /* 0x40012D80 */ +#define PERI_MS_PPU_FX_EFUSE_DATA ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[151]) /* 0x40012DC0 */ +#define PERI_MS_PPU_FX_PROFILE ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[152]) /* 0x40012E00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[153]) /* 0x40012E40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[154]) /* 0x40012E80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[155]) /* 0x40012EC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[156]) /* 0x40012F00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[157]) /* 0x40012F40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[158]) /* 0x40012F80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[159]) /* 0x40012FC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[160]) /* 0x40013000 */ +#define PERI_MS_PPU_FX_HSIOM_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[161]) /* 0x40013040 */ +#define PERI_MS_PPU_FX_HSIOM_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[162]) /* 0x40013080 */ +#define PERI_MS_PPU_FX_HSIOM_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[163]) /* 0x400130C0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[164]) /* 0x40013100 */ +#define PERI_MS_PPU_FX_HSIOM_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[165]) /* 0x40013140 */ +#define PERI_MS_PPU_FX_HSIOM_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[166]) /* 0x40013180 */ +#define PERI_MS_PPU_FX_HSIOM_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[167]) /* 0x400131C0 */ +#define PERI_MS_PPU_FX_HSIOM_AMUX ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[168]) /* 0x40013200 */ +#define PERI_MS_PPU_FX_HSIOM_MON ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[169]) /* 0x40013240 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[170]) /* 0x40013280 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[171]) /* 0x400132C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[172]) /* 0x40013300 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[173]) /* 0x40013340 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[174]) /* 0x40013380 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[175]) /* 0x400133C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[176]) /* 0x40013400 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[177]) /* 0x40013440 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[178]) /* 0x40013480 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[179]) /* 0x400134C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[180]) /* 0x40013500 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[181]) /* 0x40013540 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[182]) /* 0x40013580 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[183]) /* 0x400135C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[184]) /* 0x40013600 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[185]) /* 0x40013640 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[186]) /* 0x40013680 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[187]) /* 0x400136C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[188]) /* 0x40013700 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[189]) /* 0x40013740 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[190]) /* 0x40013780 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[191]) /* 0x400137C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[192]) /* 0x40013800 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[193]) /* 0x40013840 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[194]) /* 0x40013880 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[195]) /* 0x400138C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[196]) /* 0x40013900 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[197]) /* 0x40013940 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[198]) /* 0x40013980 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[199]) /* 0x400139C0 */ +#define PERI_MS_PPU_FX_GPIO_GPIO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[200]) /* 0x40013A00 */ +#define PERI_MS_PPU_FX_GPIO_TEST ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[201]) /* 0x40013A40 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[202]) /* 0x40013A80 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[203]) /* 0x40013AC0 */ +#define PERI_MS_PPU_FX_LPCOMP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[204]) /* 0x40013B00 */ +#define PERI_MS_PPU_FX_CSD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[205]) /* 0x40013B40 */ +#define PERI_MS_PPU_FX_TCPWM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[206]) /* 0x40013B80 */ +#define PERI_MS_PPU_FX_TCPWM1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[207]) /* 0x40013BC0 */ +#define PERI_MS_PPU_FX_LCD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[208]) /* 0x40013C00 */ +#define PERI_MS_PPU_FX_USBFS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[209]) /* 0x40013C40 */ +#define PERI_MS_PPU_FX_SMIF0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[210]) /* 0x40013C80 */ +#define PERI_MS_PPU_FX_SDHC0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[211]) /* 0x40013CC0 */ +#define PERI_MS_PPU_FX_SDHC1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[212]) /* 0x40013D00 */ +#define PERI_MS_PPU_FX_SCB0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[213]) /* 0x40013D40 */ +#define PERI_MS_PPU_FX_SCB1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[214]) /* 0x40013D80 */ +#define PERI_MS_PPU_FX_SCB2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[215]) /* 0x40013DC0 */ +#define PERI_MS_PPU_FX_SCB3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[216]) /* 0x40013E00 */ +#define PERI_MS_PPU_FX_SCB4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[217]) /* 0x40013E40 */ +#define PERI_MS_PPU_FX_SCB5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[218]) /* 0x40013E80 */ +#define PERI_MS_PPU_FX_SCB6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[219]) /* 0x40013EC0 */ +#define PERI_MS_PPU_FX_SCB7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[220]) /* 0x40013F00 */ +#define PERI_MS_PPU_FX_SCB8 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[221]) /* 0x40013F40 */ +#define PERI_MS_PPU_FX_SCB9 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[222]) /* 0x40013F80 */ +#define PERI_MS_PPU_FX_SCB10 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[223]) /* 0x40013FC0 */ +#define PERI_MS_PPU_FX_SCB11 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[224]) /* 0x40014000 */ +#define PERI_MS_PPU_FX_SCB12 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[225]) /* 0x40014040 */ +#define PERI_MS_PPU_FX_PDM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[226]) /* 0x40014080 */ +#define PERI_MS_PPU_FX_I2S0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[227]) /* 0x400140C0 */ +#define PERI_MS_PPU_FX_I2S1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[228]) /* 0x40014100 */ + +/******************************************************************************* +* CRYPTO +*******************************************************************************/ + +#define CRYPTO_BASE 0x40100000UL +#define CRYPTO ((CRYPTO_Type*) CRYPTO_BASE) /* 0x40100000 */ + +/******************************************************************************* +* CPUSS +*******************************************************************************/ + +#define CPUSS_BASE 0x40200000UL +#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40200000 */ + +/******************************************************************************* +* FAULT +*******************************************************************************/ + +#define FAULT_BASE 0x40210000UL +#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40210000 */ +#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40210000 */ +#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40210100 */ + +/******************************************************************************* +* IPC +*******************************************************************************/ + +#define IPC_BASE 0x40220000UL +#define IPC ((IPC_Type*) IPC_BASE) /* 0x40220000 */ +#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40220000 */ +#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40220020 */ +#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40220040 */ +#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40220060 */ +#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40220080 */ +#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402200A0 */ +#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402200C0 */ +#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402200E0 */ +#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40220100 */ +#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40220120 */ +#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40220140 */ +#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40220160 */ +#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40220180 */ +#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402201A0 */ +#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402201C0 */ +#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402201E0 */ +#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40221000 */ +#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40221020 */ +#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40221040 */ +#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40221060 */ +#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40221080 */ +#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402210A0 */ +#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402210C0 */ +#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402210E0 */ +#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40221100 */ +#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40221120 */ +#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40221140 */ +#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40221160 */ +#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40221180 */ +#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402211A0 */ +#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402211C0 */ +#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402211E0 */ + +/******************************************************************************* +* PROT +*******************************************************************************/ + +#define PROT_BASE 0x40230000UL +#define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ +#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ +#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ +#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402320C0 */ +#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40232100 */ +#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40232140 */ +#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40232180 */ +#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402321C0 */ +#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40232200 */ +#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40232240 */ +#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40232280 */ +#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402322C0 */ +#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40232300 */ +#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ +#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ +#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ +#define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ +#define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ +#define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ +#define PROT_MPU5_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[3]) /* 0x40235660 */ +#define PROT_MPU5_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[4]) /* 0x40235680 */ +#define PROT_MPU5_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[5]) /* 0x402356A0 */ +#define PROT_MPU5_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[6]) /* 0x402356C0 */ +#define PROT_MPU5_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[7]) /* 0x402356E0 */ +#define PROT_MPU6_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[0]) /* 0x40235A00 */ +#define PROT_MPU6_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[1]) /* 0x40235A20 */ +#define PROT_MPU6_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[2]) /* 0x40235A40 */ +#define PROT_MPU6_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[3]) /* 0x40235A60 */ +#define PROT_MPU6_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[4]) /* 0x40235A80 */ +#define PROT_MPU6_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[5]) /* 0x40235AA0 */ +#define PROT_MPU6_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[6]) /* 0x40235AC0 */ +#define PROT_MPU6_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[7]) /* 0x40235AE0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ + +/******************************************************************************* +* FLASHC +*******************************************************************************/ + +#define FLASHC_BASE 0x40240000UL +#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40240000 */ +#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4024F000 */ + +/******************************************************************************* +* SRSS +*******************************************************************************/ + +#define SRSS_BASE 0x40260000UL +#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ +#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */ +#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */ + +/******************************************************************************* +* BACKUP +*******************************************************************************/ + +#define BACKUP_BASE 0x40270000UL +#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ + +/******************************************************************************* +* DW +*******************************************************************************/ + +#define DW0_BASE 0x40280000UL +#define DW1_BASE 0x40290000UL +#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ +#define DW1 ((DW_Type*) DW1_BASE) /* 0x40290000 */ +#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40288000 */ +#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40288040 */ +#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40288080 */ +#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x402880C0 */ +#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40288100 */ +#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x40288140 */ +#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x40288180 */ +#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402881C0 */ +#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40288200 */ +#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40288240 */ +#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40288280 */ +#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x402882C0 */ +#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40288300 */ +#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x40288340 */ +#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x40288380 */ +#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402883C0 */ +#define DW0_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[16]) /* 0x40288400 */ +#define DW0_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[17]) /* 0x40288440 */ +#define DW0_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[18]) /* 0x40288480 */ +#define DW0_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[19]) /* 0x402884C0 */ +#define DW0_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[20]) /* 0x40288500 */ +#define DW0_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[21]) /* 0x40288540 */ +#define DW0_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[22]) /* 0x40288580 */ +#define DW0_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[23]) /* 0x402885C0 */ +#define DW0_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[24]) /* 0x40288600 */ +#define DW0_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[25]) /* 0x40288640 */ +#define DW0_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[26]) /* 0x40288680 */ +#define DW0_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[27]) /* 0x402886C0 */ +#define DW0_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[28]) /* 0x40288700 */ +#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40298000 */ +#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40298040 */ +#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40298080 */ +#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x402980C0 */ +#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40298100 */ +#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x40298140 */ +#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x40298180 */ +#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402981C0 */ +#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40298200 */ +#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40298240 */ +#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40298280 */ +#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x402982C0 */ +#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40298300 */ +#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x40298340 */ +#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x40298380 */ +#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402983C0 */ +#define DW1_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[16]) /* 0x40298400 */ +#define DW1_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[17]) /* 0x40298440 */ +#define DW1_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[18]) /* 0x40298480 */ +#define DW1_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[19]) /* 0x402984C0 */ +#define DW1_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[20]) /* 0x40298500 */ +#define DW1_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[21]) /* 0x40298540 */ +#define DW1_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[22]) /* 0x40298580 */ +#define DW1_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[23]) /* 0x402985C0 */ +#define DW1_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[24]) /* 0x40298600 */ +#define DW1_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[25]) /* 0x40298640 */ +#define DW1_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[26]) /* 0x40298680 */ +#define DW1_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[27]) /* 0x402986C0 */ +#define DW1_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[28]) /* 0x40298700 */ + +/******************************************************************************* +* DMAC +*******************************************************************************/ + +#define DMAC_BASE 0x402A0000UL +#define DMAC ((DMAC_Type*) DMAC_BASE) /* 0x402A0000 */ +#define DMAC_CH0 ((DMAC_CH_Type*) &DMAC->CH[0]) /* 0x402A1000 */ +#define DMAC_CH1 ((DMAC_CH_Type*) &DMAC->CH[1]) /* 0x402A1100 */ +#define DMAC_CH2 ((DMAC_CH_Type*) &DMAC->CH[2]) /* 0x402A1200 */ +#define DMAC_CH3 ((DMAC_CH_Type*) &DMAC->CH[3]) /* 0x402A1300 */ + +/******************************************************************************* +* EFUSE +*******************************************************************************/ + +#define EFUSE_BASE 0x402C0000UL +#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ + +/******************************************************************************* +* PROFILE +*******************************************************************************/ + +#define PROFILE_BASE 0x402D0000UL +#define PROFILE ((PROFILE_Type*) PROFILE_BASE) /* 0x402D0000 */ +#define PROFILE_CNT_STRUCT0 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[0]) /* 0x402D0800 */ +#define PROFILE_CNT_STRUCT1 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[1]) /* 0x402D0810 */ +#define PROFILE_CNT_STRUCT2 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[2]) /* 0x402D0820 */ +#define PROFILE_CNT_STRUCT3 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[3]) /* 0x402D0830 */ +#define PROFILE_CNT_STRUCT4 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[4]) /* 0x402D0840 */ +#define PROFILE_CNT_STRUCT5 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[5]) /* 0x402D0850 */ +#define PROFILE_CNT_STRUCT6 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[6]) /* 0x402D0860 */ +#define PROFILE_CNT_STRUCT7 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[7]) /* 0x402D0870 */ + +/******************************************************************************* +* HSIOM +*******************************************************************************/ + +#define HSIOM_BASE 0x40300000UL +#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40300000 */ +#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40300000 */ +#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40300010 */ +#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40300020 */ +#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40300030 */ +#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40300040 */ +#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40300050 */ +#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40300060 */ +#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40300070 */ +#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40300080 */ +#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40300090 */ +#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403000A0 */ +#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403000B0 */ +#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403000C0 */ +#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403000D0 */ +#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403000E0 */ + +/******************************************************************************* +* GPIO +*******************************************************************************/ + +#define GPIO_BASE 0x40310000UL +#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40310000 */ +#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40310000 */ +#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40310080 */ +#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40310100 */ +#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40310180 */ +#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40310200 */ +#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40310280 */ +#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40310300 */ +#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40310380 */ +#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40310400 */ +#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40310480 */ +#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40310500 */ +#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40310580 */ +#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40310600 */ +#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40310680 */ +#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40310700 */ + +/******************************************************************************* +* SMARTIO +*******************************************************************************/ + +#define SMARTIO_BASE 0x40320000UL +#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40320000 */ +#define SMARTIO_PRT8 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[8]) /* 0x40320800 */ +#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40320900 */ + +/******************************************************************************* +* LPCOMP +*******************************************************************************/ + +#define LPCOMP_BASE 0x40350000UL +#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */ + +/******************************************************************************* +* CSD +*******************************************************************************/ + +#define CSD0_BASE 0x40360000UL +#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */ + +/******************************************************************************* +* TCPWM +*******************************************************************************/ + +#define TCPWM0_BASE 0x40380000UL +#define TCPWM1_BASE 0x40390000UL +#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM1 ((TCPWM_Type*) TCPWM1_BASE) /* 0x40390000 */ +#define TCPWM0_CNT0 ((TCPWM_CNT_Type*) &TCPWM0->CNT[0]) /* 0x40380100 */ +#define TCPWM0_CNT1 ((TCPWM_CNT_Type*) &TCPWM0->CNT[1]) /* 0x40380140 */ +#define TCPWM0_CNT2 ((TCPWM_CNT_Type*) &TCPWM0->CNT[2]) /* 0x40380180 */ +#define TCPWM0_CNT3 ((TCPWM_CNT_Type*) &TCPWM0->CNT[3]) /* 0x403801C0 */ +#define TCPWM0_CNT4 ((TCPWM_CNT_Type*) &TCPWM0->CNT[4]) /* 0x40380200 */ +#define TCPWM0_CNT5 ((TCPWM_CNT_Type*) &TCPWM0->CNT[5]) /* 0x40380240 */ +#define TCPWM0_CNT6 ((TCPWM_CNT_Type*) &TCPWM0->CNT[6]) /* 0x40380280 */ +#define TCPWM0_CNT7 ((TCPWM_CNT_Type*) &TCPWM0->CNT[7]) /* 0x403802C0 */ +#define TCPWM1_CNT0 ((TCPWM_CNT_Type*) &TCPWM1->CNT[0]) /* 0x40390100 */ +#define TCPWM1_CNT1 ((TCPWM_CNT_Type*) &TCPWM1->CNT[1]) /* 0x40390140 */ +#define TCPWM1_CNT2 ((TCPWM_CNT_Type*) &TCPWM1->CNT[2]) /* 0x40390180 */ +#define TCPWM1_CNT3 ((TCPWM_CNT_Type*) &TCPWM1->CNT[3]) /* 0x403901C0 */ +#define TCPWM1_CNT4 ((TCPWM_CNT_Type*) &TCPWM1->CNT[4]) /* 0x40390200 */ +#define TCPWM1_CNT5 ((TCPWM_CNT_Type*) &TCPWM1->CNT[5]) /* 0x40390240 */ +#define TCPWM1_CNT6 ((TCPWM_CNT_Type*) &TCPWM1->CNT[6]) /* 0x40390280 */ +#define TCPWM1_CNT7 ((TCPWM_CNT_Type*) &TCPWM1->CNT[7]) /* 0x403902C0 */ +#define TCPWM1_CNT8 ((TCPWM_CNT_Type*) &TCPWM1->CNT[8]) /* 0x40390300 */ +#define TCPWM1_CNT9 ((TCPWM_CNT_Type*) &TCPWM1->CNT[9]) /* 0x40390340 */ +#define TCPWM1_CNT10 ((TCPWM_CNT_Type*) &TCPWM1->CNT[10]) /* 0x40390380 */ +#define TCPWM1_CNT11 ((TCPWM_CNT_Type*) &TCPWM1->CNT[11]) /* 0x403903C0 */ +#define TCPWM1_CNT12 ((TCPWM_CNT_Type*) &TCPWM1->CNT[12]) /* 0x40390400 */ +#define TCPWM1_CNT13 ((TCPWM_CNT_Type*) &TCPWM1->CNT[13]) /* 0x40390440 */ +#define TCPWM1_CNT14 ((TCPWM_CNT_Type*) &TCPWM1->CNT[14]) /* 0x40390480 */ +#define TCPWM1_CNT15 ((TCPWM_CNT_Type*) &TCPWM1->CNT[15]) /* 0x403904C0 */ +#define TCPWM1_CNT16 ((TCPWM_CNT_Type*) &TCPWM1->CNT[16]) /* 0x40390500 */ +#define TCPWM1_CNT17 ((TCPWM_CNT_Type*) &TCPWM1->CNT[17]) /* 0x40390540 */ +#define TCPWM1_CNT18 ((TCPWM_CNT_Type*) &TCPWM1->CNT[18]) /* 0x40390580 */ +#define TCPWM1_CNT19 ((TCPWM_CNT_Type*) &TCPWM1->CNT[19]) /* 0x403905C0 */ +#define TCPWM1_CNT20 ((TCPWM_CNT_Type*) &TCPWM1->CNT[20]) /* 0x40390600 */ +#define TCPWM1_CNT21 ((TCPWM_CNT_Type*) &TCPWM1->CNT[21]) /* 0x40390640 */ +#define TCPWM1_CNT22 ((TCPWM_CNT_Type*) &TCPWM1->CNT[22]) /* 0x40390680 */ +#define TCPWM1_CNT23 ((TCPWM_CNT_Type*) &TCPWM1->CNT[23]) /* 0x403906C0 */ + +/******************************************************************************* +* LCD +*******************************************************************************/ + +#define LCD0_BASE 0x403B0000UL +#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ + +/******************************************************************************* +* USBFS +*******************************************************************************/ + +#define USBFS0_BASE 0x403F0000UL +#define USBFS0 ((USBFS_Type*) USBFS0_BASE) /* 0x403F0000 */ +#define USBFS0_USBDEV ((USBFS_USBDEV_Type*) &USBFS0->USBDEV) /* 0x403F0000 */ +#define USBFS0_USBLPM ((USBFS_USBLPM_Type*) &USBFS0->USBLPM) /* 0x403F2000 */ +#define USBFS0_USBHOST ((USBFS_USBHOST_Type*) &USBFS0->USBHOST) /* 0x403F4000 */ + +/******************************************************************************* +* SMIF +*******************************************************************************/ + +#define SMIF0_BASE 0x40420000UL +#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ +#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ +#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ +#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ +#define SMIF0_DEVICE3 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[3]) /* 0x40420980 */ + +/******************************************************************************* +* SDHC +*******************************************************************************/ + +#define SDHC0_BASE 0x40460000UL +#define SDHC1_BASE 0x40470000UL +#define SDHC0 ((SDHC_Type*) SDHC0_BASE) /* 0x40460000 */ +#define SDHC1 ((SDHC_Type*) SDHC1_BASE) /* 0x40470000 */ +#define SDHC0_WRAP ((SDHC_WRAP_Type*) &SDHC0->WRAP) /* 0x40460000 */ +#define SDHC1_WRAP ((SDHC_WRAP_Type*) &SDHC1->WRAP) /* 0x40470000 */ +#define SDHC0_CORE ((SDHC_CORE_Type*) &SDHC0->CORE) /* 0x40461000 */ +#define SDHC1_CORE ((SDHC_CORE_Type*) &SDHC1->CORE) /* 0x40471000 */ + +/******************************************************************************* +* SCB +*******************************************************************************/ + +#define SCB0_BASE 0x40600000UL +#define SCB1_BASE 0x40610000UL +#define SCB2_BASE 0x40620000UL +#define SCB3_BASE 0x40630000UL +#define SCB4_BASE 0x40640000UL +#define SCB5_BASE 0x40650000UL +#define SCB6_BASE 0x40660000UL +#define SCB7_BASE 0x40670000UL +#define SCB8_BASE 0x40680000UL +#define SCB9_BASE 0x40690000UL +#define SCB10_BASE 0x406A0000UL +#define SCB11_BASE 0x406B0000UL +#define SCB12_BASE 0x406C0000UL +#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40600000 */ +#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40610000 */ +#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40620000 */ +#define SCB3 ((CySCB_Type*) SCB3_BASE) /* 0x40630000 */ +#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40640000 */ +#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40650000 */ +#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40660000 */ +#define SCB7 ((CySCB_Type*) SCB7_BASE) /* 0x40670000 */ +#define SCB8 ((CySCB_Type*) SCB8_BASE) /* 0x40680000 */ +#define SCB9 ((CySCB_Type*) SCB9_BASE) /* 0x40690000 */ +#define SCB10 ((CySCB_Type*) SCB10_BASE) /* 0x406A0000 */ +#define SCB11 ((CySCB_Type*) SCB11_BASE) /* 0x406B0000 */ +#define SCB12 ((CySCB_Type*) SCB12_BASE) /* 0x406C0000 */ + +/******************************************************************************* +* SAR +*******************************************************************************/ + +#define SAR_BASE 0x409D0000UL +#define SAR ((SAR_Type*) SAR_BASE) /* 0x409D0000 */ + +/******************************************************************************* +* PASS +*******************************************************************************/ + +#define PASS_BASE 0x409F0000UL +#define PASS ((PASS_Type*) PASS_BASE) /* 0x409F0000 */ +#define PASS_AREF ((PASS_AREF_Type*) &PASS->AREF) /* 0x409F0E00 */ + +/******************************************************************************* +* PDM +*******************************************************************************/ + +#define PDM0_BASE 0x40A00000UL +#define PDM0 ((PDM_Type*) PDM0_BASE) /* 0x40A00000 */ + +/******************************************************************************* +* I2S +*******************************************************************************/ + +#define I2S0_BASE 0x40A10000UL +#define I2S1_BASE 0x40A11000UL +#define I2S0 ((I2S_Type*) I2S0_BASE) /* 0x40A10000 */ +#define I2S1 ((I2S_Type*) I2S1_BASE) /* 0x40A11000 */ + +/** \} CY8C6148AZI-S2F44 */ + +#endif /* _CY8C6148AZI_S2F44_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6148bzi_s2f44.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6148bzi_s2f44.h new file mode 100644 index 0000000000..1389299a52 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6148bzi_s2f44.h @@ -0,0 +1,1098 @@ +/***************************************************************************//** +* \file cy8c6148bzi_s2f44.h +* +* \brief +* CY8C6148BZI-S2F44 device header +* +* \note +* Generator version: 1.6.0.225 +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CY8C6148BZI_S2F44_H_ +#define _CY8C6148BZI_S2F44_H_ + +/** +* \addtogroup group_device CY8C6148BZI-S2F44 +* \{ +*/ + +/** +* \addtogroup Configuration_of_CMSIS +* \{ +*/ + +/******************************************************************************* +* Interrupt Number Definition +*******************************************************************************/ + +typedef enum { + /* ARM Cortex-M4 Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C6148BZI-S2F44 Peripheral Interrupt Numbers */ + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_1_IRQn = 1, /*!< 1 [DeepSleep] GPIO Port Interrupt #1 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_4_IRQn = 4, /*!< 4 [DeepSleep] GPIO Port Interrupt #4 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_13_IRQn = 13, /*!< 13 [DeepSleep] GPIO Port Interrupt #13 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_8_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #8 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + scb_6_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #6 */ + scb_7_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #7 */ + scb_9_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #9 */ + scb_10_interrupt_IRQn = 48, /*!< 48 [Active] Serial Communication Block #10 */ + scb_11_interrupt_IRQn = 49, /*!< 49 [Active] Serial Communication Block #11 */ + scb_12_interrupt_IRQn = 50, /*!< 50 [Active] Serial Communication Block #12 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dmac_2_IRQn = 54, /*!< 54 [Active] CPUSS DMAC, Channel #2 */ + cpuss_interrupts_dmac_3_IRQn = 55, /*!< 55 [Active] CPUSS DMAC, Channel #3 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_0_interrupts_4_IRQn = 127, /*!< 127 [Active] TCPWM #0, Counter #4 */ + tcpwm_0_interrupts_5_IRQn = 128, /*!< 128 [Active] TCPWM #0, Counter #5 */ + tcpwm_0_interrupts_6_IRQn = 129, /*!< 129 [Active] TCPWM #0, Counter #6 */ + tcpwm_0_interrupts_7_IRQn = 130, /*!< 130 [Active] TCPWM #0, Counter #7 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + tcpwm_1_interrupts_8_IRQn = 139, /*!< 139 [Active] TCPWM #1, Counter #8 */ + tcpwm_1_interrupts_9_IRQn = 140, /*!< 140 [Active] TCPWM #1, Counter #9 */ + tcpwm_1_interrupts_10_IRQn = 141, /*!< 141 [Active] TCPWM #1, Counter #10 */ + tcpwm_1_interrupts_11_IRQn = 142, /*!< 142 [Active] TCPWM #1, Counter #11 */ + tcpwm_1_interrupts_12_IRQn = 143, /*!< 143 [Active] TCPWM #1, Counter #12 */ + tcpwm_1_interrupts_13_IRQn = 144, /*!< 144 [Active] TCPWM #1, Counter #13 */ + tcpwm_1_interrupts_14_IRQn = 145, /*!< 145 [Active] TCPWM #1, Counter #14 */ + tcpwm_1_interrupts_15_IRQn = 146, /*!< 146 [Active] TCPWM #1, Counter #15 */ + tcpwm_1_interrupts_16_IRQn = 147, /*!< 147 [Active] TCPWM #1, Counter #16 */ + tcpwm_1_interrupts_17_IRQn = 148, /*!< 148 [Active] TCPWM #1, Counter #17 */ + tcpwm_1_interrupts_18_IRQn = 149, /*!< 149 [Active] TCPWM #1, Counter #18 */ + tcpwm_1_interrupts_19_IRQn = 150, /*!< 150 [Active] TCPWM #1, Counter #19 */ + tcpwm_1_interrupts_20_IRQn = 151, /*!< 151 [Active] TCPWM #1, Counter #20 */ + tcpwm_1_interrupts_21_IRQn = 152, /*!< 152 [Active] TCPWM #1, Counter #21 */ + tcpwm_1_interrupts_22_IRQn = 153, /*!< 153 [Active] TCPWM #1, Counter #22 */ + tcpwm_1_interrupts_23_IRQn = 154, /*!< 154 [Active] TCPWM #1, Counter #23 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + audioss_0_interrupt_i2s_IRQn = 156, /*!< 156 [Active] I2S0 Audio interrupt */ + audioss_0_interrupt_pdm_IRQn = 157, /*!< 157 [Active] PDM0/PCM0 Audio interrupt */ + audioss_1_interrupt_i2s_IRQn = 158, /*!< 158 [Active] I2S1 Audio interrupt */ + profile_interrupt_IRQn = 159, /*!< 159 [Active] Energy Profiler interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + sdhc_1_interrupt_wakeup_IRQn = 166, /*!< 166 [Active] EEMC wakeup interrupt for mxsdhc, not used */ + sdhc_1_interrupt_general_IRQn = 167, /*!< 167 [Active] Consolidated interrupt for mxsdhc for everything else */ + unconnected_IRQn = 240 /*!< 240 Unconnected */ +} IRQn_Type; + + +/******************************************************************************* +* Processor and Core Peripheral Section +*******************************************************************************/ + +/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __CM0P_PRESENT 0 /*!< CM0P present or not */ +#define __DTCM_PRESENT 0 /*!< DTCM present or not */ +#define __ICACHE_PRESENT 0 /*!< ICACHE present or not */ +#define __DCACHE_PRESENT 0 /*!< DCACHE present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + + +/* Memory Blocks */ +#define CY_ROM_BASE 0x00000000UL +#define CY_ROM_SIZE 0x00010000UL +#define CY_SRAM_BASE 0x08000000UL +#define CY_SRAM_SIZE 0x00080000UL +#define CY_FLASH_BASE 0x10000000UL +#define CY_FLASH_SIZE 0x00100000UL +#define CY_EM_EEPROM_BASE 0x14000000UL +#define CY_EM_EEPROM_SIZE 0x00008000UL +#define CY_SFLASH_BASE 0x16000000UL +#define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL +#define CY_EFUSE_BASE 0x402C0800UL +#define CY_EFUSE_SIZE 0x00000200UL + +#include "system_psoc6.h" /*!< PSoC 6 System */ + +/* IP List */ +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 2u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_M4CPUSS 1u +#define CY_IP_M4CPUSS_INSTANCES 1u +#define CY_IP_M4CPUSS_VERSION 2u +#define CY_IP_M4CPUSS_DMAC 1u +#define CY_IP_M4CPUSS_DMAC_INSTANCES 1u +#define CY_IP_M4CPUSS_DMAC_VERSION 2u +#define CY_IP_M4CPUSS_DMA 1u +#define CY_IP_M4CPUSS_DMA_INSTANCES 2u +#define CY_IP_M4CPUSS_DMA_VERSION 2u +#define CY_IP_MXCRYPTO 1u +#define CY_IP_MXCRYPTO_INSTANCES 1u +#define CY_IP_MXCRYPTO_VERSION 2u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u +#define CY_IP_MXS40PASS 1u +#define CY_IP_MXS40PASS_INSTANCES 1u +#define CY_IP_MXS40PASS_VERSION 1u +#define CY_IP_MXS40PASS_SAR 1u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u +#define CY_IP_MXS40PASS_SAR_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXPROFILE 1u +#define CY_IP_MXPROFILE_INSTANCES 1u +#define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 13u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 2u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u + +#include "psoc6_02_config.h" +#include "gpio_psoc6_02_124_bga.h" + +#define CY_DEVICE_PSOC6A2M +#define CY_SILICON_ID 0xE4611202UL +#define CY_HF_CLK_MAX_FREQ 150000000UL + +#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL + +/******************************************************************************* +* SFLASH +*******************************************************************************/ + +#define SFLASH_BASE 0x16000000UL +#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */ + +/******************************************************************************* +* PERI +*******************************************************************************/ + +#define PERI_BASE 0x40000000UL +#define PERI ((PERI_Type*) PERI_BASE) /* 0x40000000 */ +#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40004000 */ +#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40004020 */ +#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40004040 */ +#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x40004060 */ +#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40004080 */ +#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x400040C0 */ +#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40004120 */ +#define PERI_GR10 ((PERI_GR_Type*) &PERI->GR[10]) /* 0x40004140 */ +#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40008000 */ +#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40008400 */ +#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40008800 */ +#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40008C00 */ +#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40009000 */ +#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40009400 */ +#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40009800 */ +#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40009C00 */ +#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ +#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ +#define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ +#define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ +#define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ +#define PERI_TR_1TO1_GR3 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[3]) /* 0x4000CC00 */ +#define PERI_TR_1TO1_GR4 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[4]) /* 0x4000D000 */ +#define PERI_TR_1TO1_GR5 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[5]) /* 0x4000D400 */ +#define PERI_TR_1TO1_GR6 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[6]) /* 0x4000D800 */ + +/******************************************************************************* +* PERI_MS +*******************************************************************************/ + +#define PERI_MS_BASE 0x40010000UL +#define PERI_MS ((PERI_MS_Type*) PERI_MS_BASE) /* 0x40010000 */ +#define PERI_MS_PPU_PR0 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[0]) /* 0x40010000 */ +#define PERI_MS_PPU_PR1 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[1]) /* 0x40010040 */ +#define PERI_MS_PPU_PR2 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[2]) /* 0x40010080 */ +#define PERI_MS_PPU_PR3 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[3]) /* 0x400100C0 */ +#define PERI_MS_PPU_PR4 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[4]) /* 0x40010100 */ +#define PERI_MS_PPU_PR5 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[5]) /* 0x40010140 */ +#define PERI_MS_PPU_PR6 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[6]) /* 0x40010180 */ +#define PERI_MS_PPU_PR7 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[7]) /* 0x400101C0 */ +#define PERI_MS_PPU_FX_PERI_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[0]) /* 0x40010800 */ +#define PERI_MS_PPU_FX_PERI_GR0_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[1]) /* 0x40010840 */ +#define PERI_MS_PPU_FX_PERI_GR1_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[2]) /* 0x40010880 */ +#define PERI_MS_PPU_FX_PERI_GR2_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[3]) /* 0x400108C0 */ +#define PERI_MS_PPU_FX_PERI_GR3_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[4]) /* 0x40010900 */ +#define PERI_MS_PPU_FX_PERI_GR4_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[5]) /* 0x40010940 */ +#define PERI_MS_PPU_FX_PERI_GR6_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[6]) /* 0x40010980 */ +#define PERI_MS_PPU_FX_PERI_GR9_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[7]) /* 0x400109C0 */ +#define PERI_MS_PPU_FX_PERI_GR10_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[8]) /* 0x40010A00 */ +#define PERI_MS_PPU_FX_PERI_TR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[9]) /* 0x40010A40 */ +#define PERI_MS_PPU_FX_CRYPTO_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[10]) /* 0x40010A80 */ +#define PERI_MS_PPU_FX_CRYPTO_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[11]) /* 0x40010AC0 */ +#define PERI_MS_PPU_FX_CRYPTO_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[12]) /* 0x40010B00 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[13]) /* 0x40010B40 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[14]) /* 0x40010B80 */ +#define PERI_MS_PPU_FX_CRYPTO_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[15]) /* 0x40010BC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[16]) /* 0x40010C00 */ +#define PERI_MS_PPU_FX_CPUSS_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[17]) /* 0x40010C40 */ +#define PERI_MS_PPU_FX_CPUSS_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[18]) /* 0x40010C80 */ +#define PERI_MS_PPU_FX_CPUSS_CM0_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[19]) /* 0x40010CC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[20]) /* 0x40010D00 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[21]) /* 0x40010D40 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT1_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[22]) /* 0x40010D80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT0_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[23]) /* 0x40010DC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT1_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[24]) /* 0x40010E00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT2_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[25]) /* 0x40010E40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT3_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[26]) /* 0x40010E80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT4_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[27]) /* 0x40010EC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT5_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[28]) /* 0x40010F00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT6_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[29]) /* 0x40010F40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT7_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[30]) /* 0x40010F80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT8_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[31]) /* 0x40010FC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT9_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[32]) /* 0x40011000 */ +#define PERI_MS_PPU_FX_IPC_STRUCT10_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[33]) /* 0x40011040 */ +#define PERI_MS_PPU_FX_IPC_STRUCT11_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[34]) /* 0x40011080 */ +#define PERI_MS_PPU_FX_IPC_STRUCT12_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[35]) /* 0x400110C0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT13_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[36]) /* 0x40011100 */ +#define PERI_MS_PPU_FX_IPC_STRUCT14_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[37]) /* 0x40011140 */ +#define PERI_MS_PPU_FX_IPC_STRUCT15_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[38]) /* 0x40011180 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT0_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[39]) /* 0x400111C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT1_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[40]) /* 0x40011200 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT2_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[41]) /* 0x40011240 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT3_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[42]) /* 0x40011280 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT4_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[43]) /* 0x400112C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT5_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[44]) /* 0x40011300 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT6_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[45]) /* 0x40011340 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT7_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[46]) /* 0x40011380 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT8_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[47]) /* 0x400113C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT9_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[48]) /* 0x40011400 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT10_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[49]) /* 0x40011440 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT11_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[50]) /* 0x40011480 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT12_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[51]) /* 0x400114C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT13_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[52]) /* 0x40011500 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT14_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[53]) /* 0x40011540 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT15_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[54]) /* 0x40011580 */ +#define PERI_MS_PPU_FX_PROT_SMPU_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[55]) /* 0x400115C0 */ +#define PERI_MS_PPU_FX_PROT_MPU0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[56]) /* 0x40011600 */ +#define PERI_MS_PPU_FX_PROT_MPU5_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[57]) /* 0x40011640 */ +#define PERI_MS_PPU_FX_PROT_MPU6_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[58]) /* 0x40011680 */ +#define PERI_MS_PPU_FX_PROT_MPU14_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[59]) /* 0x400116C0 */ +#define PERI_MS_PPU_FX_PROT_MPU15_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[60]) /* 0x40011700 */ +#define PERI_MS_PPU_FX_FLASHC_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[61]) /* 0x40011740 */ +#define PERI_MS_PPU_FX_FLASHC_CMD ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[62]) /* 0x40011780 */ +#define PERI_MS_PPU_FX_FLASHC_DFT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[63]) /* 0x400117C0 */ +#define PERI_MS_PPU_FX_FLASHC_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[64]) /* 0x40011800 */ +#define PERI_MS_PPU_FX_FLASHC_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[65]) /* 0x40011840 */ +#define PERI_MS_PPU_FX_FLASHC_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[66]) /* 0x40011880 */ +#define PERI_MS_PPU_FX_FLASHC_DW0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[67]) /* 0x400118C0 */ +#define PERI_MS_PPU_FX_FLASHC_DW1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[68]) /* 0x40011900 */ +#define PERI_MS_PPU_FX_FLASHC_DMAC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[69]) /* 0x40011940 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[70]) /* 0x40011980 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[71]) /* 0x400119C0 */ +#define PERI_MS_PPU_FX_FLASHC_FM ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[72]) /* 0x40011A00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[73]) /* 0x40011A40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[74]) /* 0x40011A80 */ +#define PERI_MS_PPU_FX_WDT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[75]) /* 0x40011AC0 */ +#define PERI_MS_PPU_FX_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[76]) /* 0x40011B00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[77]) /* 0x40011B40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[78]) /* 0x40011B80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[79]) /* 0x40011BC0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[80]) /* 0x40011C00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[81]) /* 0x40011C40 */ +#define PERI_MS_PPU_FX_BACKUP_BACKUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[82]) /* 0x40011C80 */ +#define PERI_MS_PPU_FX_DW0_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[83]) /* 0x40011CC0 */ +#define PERI_MS_PPU_FX_DW1_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[84]) /* 0x40011D00 */ +#define PERI_MS_PPU_FX_DW0_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[85]) /* 0x40011D40 */ +#define PERI_MS_PPU_FX_DW1_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[86]) /* 0x40011D80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[87]) /* 0x40011DC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[88]) /* 0x40011E00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[89]) /* 0x40011E40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[90]) /* 0x40011E80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[91]) /* 0x40011EC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[92]) /* 0x40011F00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[93]) /* 0x40011F40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[94]) /* 0x40011F80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[95]) /* 0x40011FC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[96]) /* 0x40012000 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[97]) /* 0x40012040 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[98]) /* 0x40012080 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[99]) /* 0x400120C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[100]) /* 0x40012100 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[101]) /* 0x40012140 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[102]) /* 0x40012180 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[103]) /* 0x400121C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[104]) /* 0x40012200 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[105]) /* 0x40012240 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[106]) /* 0x40012280 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[107]) /* 0x400122C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[108]) /* 0x40012300 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[109]) /* 0x40012340 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[110]) /* 0x40012380 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[111]) /* 0x400123C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[112]) /* 0x40012400 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[113]) /* 0x40012440 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[114]) /* 0x40012480 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[115]) /* 0x400124C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[116]) /* 0x40012500 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[117]) /* 0x40012540 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[118]) /* 0x40012580 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[119]) /* 0x400125C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[120]) /* 0x40012600 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[121]) /* 0x40012640 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[122]) /* 0x40012680 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[123]) /* 0x400126C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[124]) /* 0x40012700 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[125]) /* 0x40012740 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[126]) /* 0x40012780 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[127]) /* 0x400127C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[128]) /* 0x40012800 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[129]) /* 0x40012840 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[130]) /* 0x40012880 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[131]) /* 0x400128C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[132]) /* 0x40012900 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[133]) /* 0x40012940 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[134]) /* 0x40012980 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[135]) /* 0x400129C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[136]) /* 0x40012A00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[137]) /* 0x40012A40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[138]) /* 0x40012A80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[139]) /* 0x40012AC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[140]) /* 0x40012B00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[141]) /* 0x40012B40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[142]) /* 0x40012B80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[143]) /* 0x40012BC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[144]) /* 0x40012C00 */ +#define PERI_MS_PPU_FX_DMAC_TOP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[145]) /* 0x40012C40 */ +#define PERI_MS_PPU_FX_DMAC_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[146]) /* 0x40012C80 */ +#define PERI_MS_PPU_FX_DMAC_CH1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[147]) /* 0x40012CC0 */ +#define PERI_MS_PPU_FX_DMAC_CH2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[148]) /* 0x40012D00 */ +#define PERI_MS_PPU_FX_DMAC_CH3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[149]) /* 0x40012D40 */ +#define PERI_MS_PPU_FX_EFUSE_CTL ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[150]) /* 0x40012D80 */ +#define PERI_MS_PPU_FX_EFUSE_DATA ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[151]) /* 0x40012DC0 */ +#define PERI_MS_PPU_FX_PROFILE ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[152]) /* 0x40012E00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[153]) /* 0x40012E40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[154]) /* 0x40012E80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[155]) /* 0x40012EC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[156]) /* 0x40012F00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[157]) /* 0x40012F40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[158]) /* 0x40012F80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[159]) /* 0x40012FC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[160]) /* 0x40013000 */ +#define PERI_MS_PPU_FX_HSIOM_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[161]) /* 0x40013040 */ +#define PERI_MS_PPU_FX_HSIOM_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[162]) /* 0x40013080 */ +#define PERI_MS_PPU_FX_HSIOM_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[163]) /* 0x400130C0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[164]) /* 0x40013100 */ +#define PERI_MS_PPU_FX_HSIOM_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[165]) /* 0x40013140 */ +#define PERI_MS_PPU_FX_HSIOM_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[166]) /* 0x40013180 */ +#define PERI_MS_PPU_FX_HSIOM_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[167]) /* 0x400131C0 */ +#define PERI_MS_PPU_FX_HSIOM_AMUX ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[168]) /* 0x40013200 */ +#define PERI_MS_PPU_FX_HSIOM_MON ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[169]) /* 0x40013240 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[170]) /* 0x40013280 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[171]) /* 0x400132C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[172]) /* 0x40013300 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[173]) /* 0x40013340 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[174]) /* 0x40013380 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[175]) /* 0x400133C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[176]) /* 0x40013400 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[177]) /* 0x40013440 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[178]) /* 0x40013480 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[179]) /* 0x400134C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[180]) /* 0x40013500 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[181]) /* 0x40013540 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[182]) /* 0x40013580 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[183]) /* 0x400135C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[184]) /* 0x40013600 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[185]) /* 0x40013640 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[186]) /* 0x40013680 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[187]) /* 0x400136C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[188]) /* 0x40013700 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[189]) /* 0x40013740 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[190]) /* 0x40013780 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[191]) /* 0x400137C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[192]) /* 0x40013800 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[193]) /* 0x40013840 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[194]) /* 0x40013880 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[195]) /* 0x400138C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[196]) /* 0x40013900 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[197]) /* 0x40013940 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[198]) /* 0x40013980 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[199]) /* 0x400139C0 */ +#define PERI_MS_PPU_FX_GPIO_GPIO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[200]) /* 0x40013A00 */ +#define PERI_MS_PPU_FX_GPIO_TEST ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[201]) /* 0x40013A40 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[202]) /* 0x40013A80 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[203]) /* 0x40013AC0 */ +#define PERI_MS_PPU_FX_LPCOMP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[204]) /* 0x40013B00 */ +#define PERI_MS_PPU_FX_CSD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[205]) /* 0x40013B40 */ +#define PERI_MS_PPU_FX_TCPWM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[206]) /* 0x40013B80 */ +#define PERI_MS_PPU_FX_TCPWM1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[207]) /* 0x40013BC0 */ +#define PERI_MS_PPU_FX_LCD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[208]) /* 0x40013C00 */ +#define PERI_MS_PPU_FX_USBFS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[209]) /* 0x40013C40 */ +#define PERI_MS_PPU_FX_SMIF0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[210]) /* 0x40013C80 */ +#define PERI_MS_PPU_FX_SDHC0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[211]) /* 0x40013CC0 */ +#define PERI_MS_PPU_FX_SDHC1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[212]) /* 0x40013D00 */ +#define PERI_MS_PPU_FX_SCB0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[213]) /* 0x40013D40 */ +#define PERI_MS_PPU_FX_SCB1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[214]) /* 0x40013D80 */ +#define PERI_MS_PPU_FX_SCB2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[215]) /* 0x40013DC0 */ +#define PERI_MS_PPU_FX_SCB3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[216]) /* 0x40013E00 */ +#define PERI_MS_PPU_FX_SCB4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[217]) /* 0x40013E40 */ +#define PERI_MS_PPU_FX_SCB5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[218]) /* 0x40013E80 */ +#define PERI_MS_PPU_FX_SCB6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[219]) /* 0x40013EC0 */ +#define PERI_MS_PPU_FX_SCB7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[220]) /* 0x40013F00 */ +#define PERI_MS_PPU_FX_SCB8 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[221]) /* 0x40013F40 */ +#define PERI_MS_PPU_FX_SCB9 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[222]) /* 0x40013F80 */ +#define PERI_MS_PPU_FX_SCB10 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[223]) /* 0x40013FC0 */ +#define PERI_MS_PPU_FX_SCB11 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[224]) /* 0x40014000 */ +#define PERI_MS_PPU_FX_SCB12 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[225]) /* 0x40014040 */ +#define PERI_MS_PPU_FX_PDM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[226]) /* 0x40014080 */ +#define PERI_MS_PPU_FX_I2S0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[227]) /* 0x400140C0 */ +#define PERI_MS_PPU_FX_I2S1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[228]) /* 0x40014100 */ + +/******************************************************************************* +* CRYPTO +*******************************************************************************/ + +#define CRYPTO_BASE 0x40100000UL +#define CRYPTO ((CRYPTO_Type*) CRYPTO_BASE) /* 0x40100000 */ + +/******************************************************************************* +* CPUSS +*******************************************************************************/ + +#define CPUSS_BASE 0x40200000UL +#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40200000 */ + +/******************************************************************************* +* FAULT +*******************************************************************************/ + +#define FAULT_BASE 0x40210000UL +#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40210000 */ +#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40210000 */ +#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40210100 */ + +/******************************************************************************* +* IPC +*******************************************************************************/ + +#define IPC_BASE 0x40220000UL +#define IPC ((IPC_Type*) IPC_BASE) /* 0x40220000 */ +#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40220000 */ +#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40220020 */ +#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40220040 */ +#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40220060 */ +#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40220080 */ +#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402200A0 */ +#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402200C0 */ +#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402200E0 */ +#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40220100 */ +#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40220120 */ +#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40220140 */ +#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40220160 */ +#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40220180 */ +#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402201A0 */ +#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402201C0 */ +#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402201E0 */ +#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40221000 */ +#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40221020 */ +#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40221040 */ +#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40221060 */ +#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40221080 */ +#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402210A0 */ +#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402210C0 */ +#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402210E0 */ +#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40221100 */ +#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40221120 */ +#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40221140 */ +#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40221160 */ +#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40221180 */ +#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402211A0 */ +#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402211C0 */ +#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402211E0 */ + +/******************************************************************************* +* PROT +*******************************************************************************/ + +#define PROT_BASE 0x40230000UL +#define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ +#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ +#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ +#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402320C0 */ +#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40232100 */ +#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40232140 */ +#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40232180 */ +#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402321C0 */ +#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40232200 */ +#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40232240 */ +#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40232280 */ +#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402322C0 */ +#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40232300 */ +#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ +#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ +#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ +#define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ +#define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ +#define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ +#define PROT_MPU5_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[3]) /* 0x40235660 */ +#define PROT_MPU5_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[4]) /* 0x40235680 */ +#define PROT_MPU5_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[5]) /* 0x402356A0 */ +#define PROT_MPU5_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[6]) /* 0x402356C0 */ +#define PROT_MPU5_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[7]) /* 0x402356E0 */ +#define PROT_MPU6_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[0]) /* 0x40235A00 */ +#define PROT_MPU6_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[1]) /* 0x40235A20 */ +#define PROT_MPU6_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[2]) /* 0x40235A40 */ +#define PROT_MPU6_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[3]) /* 0x40235A60 */ +#define PROT_MPU6_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[4]) /* 0x40235A80 */ +#define PROT_MPU6_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[5]) /* 0x40235AA0 */ +#define PROT_MPU6_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[6]) /* 0x40235AC0 */ +#define PROT_MPU6_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[7]) /* 0x40235AE0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ + +/******************************************************************************* +* FLASHC +*******************************************************************************/ + +#define FLASHC_BASE 0x40240000UL +#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40240000 */ +#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4024F000 */ + +/******************************************************************************* +* SRSS +*******************************************************************************/ + +#define SRSS_BASE 0x40260000UL +#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ +#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */ +#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */ + +/******************************************************************************* +* BACKUP +*******************************************************************************/ + +#define BACKUP_BASE 0x40270000UL +#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ + +/******************************************************************************* +* DW +*******************************************************************************/ + +#define DW0_BASE 0x40280000UL +#define DW1_BASE 0x40290000UL +#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ +#define DW1 ((DW_Type*) DW1_BASE) /* 0x40290000 */ +#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40288000 */ +#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40288040 */ +#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40288080 */ +#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x402880C0 */ +#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40288100 */ +#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x40288140 */ +#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x40288180 */ +#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402881C0 */ +#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40288200 */ +#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40288240 */ +#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40288280 */ +#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x402882C0 */ +#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40288300 */ +#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x40288340 */ +#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x40288380 */ +#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402883C0 */ +#define DW0_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[16]) /* 0x40288400 */ +#define DW0_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[17]) /* 0x40288440 */ +#define DW0_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[18]) /* 0x40288480 */ +#define DW0_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[19]) /* 0x402884C0 */ +#define DW0_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[20]) /* 0x40288500 */ +#define DW0_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[21]) /* 0x40288540 */ +#define DW0_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[22]) /* 0x40288580 */ +#define DW0_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[23]) /* 0x402885C0 */ +#define DW0_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[24]) /* 0x40288600 */ +#define DW0_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[25]) /* 0x40288640 */ +#define DW0_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[26]) /* 0x40288680 */ +#define DW0_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[27]) /* 0x402886C0 */ +#define DW0_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[28]) /* 0x40288700 */ +#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40298000 */ +#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40298040 */ +#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40298080 */ +#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x402980C0 */ +#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40298100 */ +#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x40298140 */ +#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x40298180 */ +#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402981C0 */ +#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40298200 */ +#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40298240 */ +#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40298280 */ +#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x402982C0 */ +#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40298300 */ +#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x40298340 */ +#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x40298380 */ +#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402983C0 */ +#define DW1_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[16]) /* 0x40298400 */ +#define DW1_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[17]) /* 0x40298440 */ +#define DW1_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[18]) /* 0x40298480 */ +#define DW1_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[19]) /* 0x402984C0 */ +#define DW1_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[20]) /* 0x40298500 */ +#define DW1_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[21]) /* 0x40298540 */ +#define DW1_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[22]) /* 0x40298580 */ +#define DW1_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[23]) /* 0x402985C0 */ +#define DW1_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[24]) /* 0x40298600 */ +#define DW1_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[25]) /* 0x40298640 */ +#define DW1_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[26]) /* 0x40298680 */ +#define DW1_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[27]) /* 0x402986C0 */ +#define DW1_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[28]) /* 0x40298700 */ + +/******************************************************************************* +* DMAC +*******************************************************************************/ + +#define DMAC_BASE 0x402A0000UL +#define DMAC ((DMAC_Type*) DMAC_BASE) /* 0x402A0000 */ +#define DMAC_CH0 ((DMAC_CH_Type*) &DMAC->CH[0]) /* 0x402A1000 */ +#define DMAC_CH1 ((DMAC_CH_Type*) &DMAC->CH[1]) /* 0x402A1100 */ +#define DMAC_CH2 ((DMAC_CH_Type*) &DMAC->CH[2]) /* 0x402A1200 */ +#define DMAC_CH3 ((DMAC_CH_Type*) &DMAC->CH[3]) /* 0x402A1300 */ + +/******************************************************************************* +* EFUSE +*******************************************************************************/ + +#define EFUSE_BASE 0x402C0000UL +#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ + +/******************************************************************************* +* PROFILE +*******************************************************************************/ + +#define PROFILE_BASE 0x402D0000UL +#define PROFILE ((PROFILE_Type*) PROFILE_BASE) /* 0x402D0000 */ +#define PROFILE_CNT_STRUCT0 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[0]) /* 0x402D0800 */ +#define PROFILE_CNT_STRUCT1 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[1]) /* 0x402D0810 */ +#define PROFILE_CNT_STRUCT2 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[2]) /* 0x402D0820 */ +#define PROFILE_CNT_STRUCT3 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[3]) /* 0x402D0830 */ +#define PROFILE_CNT_STRUCT4 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[4]) /* 0x402D0840 */ +#define PROFILE_CNT_STRUCT5 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[5]) /* 0x402D0850 */ +#define PROFILE_CNT_STRUCT6 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[6]) /* 0x402D0860 */ +#define PROFILE_CNT_STRUCT7 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[7]) /* 0x402D0870 */ + +/******************************************************************************* +* HSIOM +*******************************************************************************/ + +#define HSIOM_BASE 0x40300000UL +#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40300000 */ +#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40300000 */ +#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40300010 */ +#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40300020 */ +#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40300030 */ +#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40300040 */ +#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40300050 */ +#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40300060 */ +#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40300070 */ +#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40300080 */ +#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40300090 */ +#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403000A0 */ +#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403000B0 */ +#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403000C0 */ +#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403000D0 */ +#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403000E0 */ + +/******************************************************************************* +* GPIO +*******************************************************************************/ + +#define GPIO_BASE 0x40310000UL +#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40310000 */ +#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40310000 */ +#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40310080 */ +#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40310100 */ +#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40310180 */ +#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40310200 */ +#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40310280 */ +#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40310300 */ +#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40310380 */ +#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40310400 */ +#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40310480 */ +#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40310500 */ +#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40310580 */ +#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40310600 */ +#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40310680 */ +#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40310700 */ + +/******************************************************************************* +* SMARTIO +*******************************************************************************/ + +#define SMARTIO_BASE 0x40320000UL +#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40320000 */ +#define SMARTIO_PRT8 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[8]) /* 0x40320800 */ +#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40320900 */ + +/******************************************************************************* +* LPCOMP +*******************************************************************************/ + +#define LPCOMP_BASE 0x40350000UL +#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */ + +/******************************************************************************* +* CSD +*******************************************************************************/ + +#define CSD0_BASE 0x40360000UL +#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */ + +/******************************************************************************* +* TCPWM +*******************************************************************************/ + +#define TCPWM0_BASE 0x40380000UL +#define TCPWM1_BASE 0x40390000UL +#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM1 ((TCPWM_Type*) TCPWM1_BASE) /* 0x40390000 */ +#define TCPWM0_CNT0 ((TCPWM_CNT_Type*) &TCPWM0->CNT[0]) /* 0x40380100 */ +#define TCPWM0_CNT1 ((TCPWM_CNT_Type*) &TCPWM0->CNT[1]) /* 0x40380140 */ +#define TCPWM0_CNT2 ((TCPWM_CNT_Type*) &TCPWM0->CNT[2]) /* 0x40380180 */ +#define TCPWM0_CNT3 ((TCPWM_CNT_Type*) &TCPWM0->CNT[3]) /* 0x403801C0 */ +#define TCPWM0_CNT4 ((TCPWM_CNT_Type*) &TCPWM0->CNT[4]) /* 0x40380200 */ +#define TCPWM0_CNT5 ((TCPWM_CNT_Type*) &TCPWM0->CNT[5]) /* 0x40380240 */ +#define TCPWM0_CNT6 ((TCPWM_CNT_Type*) &TCPWM0->CNT[6]) /* 0x40380280 */ +#define TCPWM0_CNT7 ((TCPWM_CNT_Type*) &TCPWM0->CNT[7]) /* 0x403802C0 */ +#define TCPWM1_CNT0 ((TCPWM_CNT_Type*) &TCPWM1->CNT[0]) /* 0x40390100 */ +#define TCPWM1_CNT1 ((TCPWM_CNT_Type*) &TCPWM1->CNT[1]) /* 0x40390140 */ +#define TCPWM1_CNT2 ((TCPWM_CNT_Type*) &TCPWM1->CNT[2]) /* 0x40390180 */ +#define TCPWM1_CNT3 ((TCPWM_CNT_Type*) &TCPWM1->CNT[3]) /* 0x403901C0 */ +#define TCPWM1_CNT4 ((TCPWM_CNT_Type*) &TCPWM1->CNT[4]) /* 0x40390200 */ +#define TCPWM1_CNT5 ((TCPWM_CNT_Type*) &TCPWM1->CNT[5]) /* 0x40390240 */ +#define TCPWM1_CNT6 ((TCPWM_CNT_Type*) &TCPWM1->CNT[6]) /* 0x40390280 */ +#define TCPWM1_CNT7 ((TCPWM_CNT_Type*) &TCPWM1->CNT[7]) /* 0x403902C0 */ +#define TCPWM1_CNT8 ((TCPWM_CNT_Type*) &TCPWM1->CNT[8]) /* 0x40390300 */ +#define TCPWM1_CNT9 ((TCPWM_CNT_Type*) &TCPWM1->CNT[9]) /* 0x40390340 */ +#define TCPWM1_CNT10 ((TCPWM_CNT_Type*) &TCPWM1->CNT[10]) /* 0x40390380 */ +#define TCPWM1_CNT11 ((TCPWM_CNT_Type*) &TCPWM1->CNT[11]) /* 0x403903C0 */ +#define TCPWM1_CNT12 ((TCPWM_CNT_Type*) &TCPWM1->CNT[12]) /* 0x40390400 */ +#define TCPWM1_CNT13 ((TCPWM_CNT_Type*) &TCPWM1->CNT[13]) /* 0x40390440 */ +#define TCPWM1_CNT14 ((TCPWM_CNT_Type*) &TCPWM1->CNT[14]) /* 0x40390480 */ +#define TCPWM1_CNT15 ((TCPWM_CNT_Type*) &TCPWM1->CNT[15]) /* 0x403904C0 */ +#define TCPWM1_CNT16 ((TCPWM_CNT_Type*) &TCPWM1->CNT[16]) /* 0x40390500 */ +#define TCPWM1_CNT17 ((TCPWM_CNT_Type*) &TCPWM1->CNT[17]) /* 0x40390540 */ +#define TCPWM1_CNT18 ((TCPWM_CNT_Type*) &TCPWM1->CNT[18]) /* 0x40390580 */ +#define TCPWM1_CNT19 ((TCPWM_CNT_Type*) &TCPWM1->CNT[19]) /* 0x403905C0 */ +#define TCPWM1_CNT20 ((TCPWM_CNT_Type*) &TCPWM1->CNT[20]) /* 0x40390600 */ +#define TCPWM1_CNT21 ((TCPWM_CNT_Type*) &TCPWM1->CNT[21]) /* 0x40390640 */ +#define TCPWM1_CNT22 ((TCPWM_CNT_Type*) &TCPWM1->CNT[22]) /* 0x40390680 */ +#define TCPWM1_CNT23 ((TCPWM_CNT_Type*) &TCPWM1->CNT[23]) /* 0x403906C0 */ + +/******************************************************************************* +* LCD +*******************************************************************************/ + +#define LCD0_BASE 0x403B0000UL +#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ + +/******************************************************************************* +* USBFS +*******************************************************************************/ + +#define USBFS0_BASE 0x403F0000UL +#define USBFS0 ((USBFS_Type*) USBFS0_BASE) /* 0x403F0000 */ +#define USBFS0_USBDEV ((USBFS_USBDEV_Type*) &USBFS0->USBDEV) /* 0x403F0000 */ +#define USBFS0_USBLPM ((USBFS_USBLPM_Type*) &USBFS0->USBLPM) /* 0x403F2000 */ +#define USBFS0_USBHOST ((USBFS_USBHOST_Type*) &USBFS0->USBHOST) /* 0x403F4000 */ + +/******************************************************************************* +* SMIF +*******************************************************************************/ + +#define SMIF0_BASE 0x40420000UL +#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ +#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ +#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ +#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ +#define SMIF0_DEVICE3 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[3]) /* 0x40420980 */ + +/******************************************************************************* +* SDHC +*******************************************************************************/ + +#define SDHC0_BASE 0x40460000UL +#define SDHC1_BASE 0x40470000UL +#define SDHC0 ((SDHC_Type*) SDHC0_BASE) /* 0x40460000 */ +#define SDHC1 ((SDHC_Type*) SDHC1_BASE) /* 0x40470000 */ +#define SDHC0_WRAP ((SDHC_WRAP_Type*) &SDHC0->WRAP) /* 0x40460000 */ +#define SDHC1_WRAP ((SDHC_WRAP_Type*) &SDHC1->WRAP) /* 0x40470000 */ +#define SDHC0_CORE ((SDHC_CORE_Type*) &SDHC0->CORE) /* 0x40461000 */ +#define SDHC1_CORE ((SDHC_CORE_Type*) &SDHC1->CORE) /* 0x40471000 */ + +/******************************************************************************* +* SCB +*******************************************************************************/ + +#define SCB0_BASE 0x40600000UL +#define SCB1_BASE 0x40610000UL +#define SCB2_BASE 0x40620000UL +#define SCB3_BASE 0x40630000UL +#define SCB4_BASE 0x40640000UL +#define SCB5_BASE 0x40650000UL +#define SCB6_BASE 0x40660000UL +#define SCB7_BASE 0x40670000UL +#define SCB8_BASE 0x40680000UL +#define SCB9_BASE 0x40690000UL +#define SCB10_BASE 0x406A0000UL +#define SCB11_BASE 0x406B0000UL +#define SCB12_BASE 0x406C0000UL +#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40600000 */ +#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40610000 */ +#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40620000 */ +#define SCB3 ((CySCB_Type*) SCB3_BASE) /* 0x40630000 */ +#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40640000 */ +#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40650000 */ +#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40660000 */ +#define SCB7 ((CySCB_Type*) SCB7_BASE) /* 0x40670000 */ +#define SCB8 ((CySCB_Type*) SCB8_BASE) /* 0x40680000 */ +#define SCB9 ((CySCB_Type*) SCB9_BASE) /* 0x40690000 */ +#define SCB10 ((CySCB_Type*) SCB10_BASE) /* 0x406A0000 */ +#define SCB11 ((CySCB_Type*) SCB11_BASE) /* 0x406B0000 */ +#define SCB12 ((CySCB_Type*) SCB12_BASE) /* 0x406C0000 */ + +/******************************************************************************* +* SAR +*******************************************************************************/ + +#define SAR_BASE 0x409D0000UL +#define SAR ((SAR_Type*) SAR_BASE) /* 0x409D0000 */ + +/******************************************************************************* +* PASS +*******************************************************************************/ + +#define PASS_BASE 0x409F0000UL +#define PASS ((PASS_Type*) PASS_BASE) /* 0x409F0000 */ +#define PASS_AREF ((PASS_AREF_Type*) &PASS->AREF) /* 0x409F0E00 */ + +/******************************************************************************* +* PDM +*******************************************************************************/ + +#define PDM0_BASE 0x40A00000UL +#define PDM0 ((PDM_Type*) PDM0_BASE) /* 0x40A00000 */ + +/******************************************************************************* +* I2S +*******************************************************************************/ + +#define I2S0_BASE 0x40A10000UL +#define I2S1_BASE 0x40A11000UL +#define I2S0 ((I2S_Type*) I2S0_BASE) /* 0x40A10000 */ +#define I2S1 ((I2S_Type*) I2S1_BASE) /* 0x40A11000 */ + +/** \} CY8C6148BZI-S2F44 */ + +#endif /* _CY8C6148BZI_S2F44_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6148fni_s2f43.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6148fni_s2f43.h new file mode 100644 index 0000000000..a52da93fc9 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6148fni_s2f43.h @@ -0,0 +1,1098 @@ +/***************************************************************************//** +* \file cy8c6148fni_s2f43.h +* +* \brief +* CY8C6148FNI-S2F43 device header +* +* \note +* Generator version: 1.6.0.225 +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CY8C6148FNI_S2F43_H_ +#define _CY8C6148FNI_S2F43_H_ + +/** +* \addtogroup group_device CY8C6148FNI-S2F43 +* \{ +*/ + +/** +* \addtogroup Configuration_of_CMSIS +* \{ +*/ + +/******************************************************************************* +* Interrupt Number Definition +*******************************************************************************/ + +typedef enum { + /* ARM Cortex-M4 Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C6148FNI-S2F43 Peripheral Interrupt Numbers */ + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_1_IRQn = 1, /*!< 1 [DeepSleep] GPIO Port Interrupt #1 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_4_IRQn = 4, /*!< 4 [DeepSleep] GPIO Port Interrupt #4 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_13_IRQn = 13, /*!< 13 [DeepSleep] GPIO Port Interrupt #13 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_8_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #8 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + scb_6_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #6 */ + scb_7_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #7 */ + scb_9_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #9 */ + scb_10_interrupt_IRQn = 48, /*!< 48 [Active] Serial Communication Block #10 */ + scb_11_interrupt_IRQn = 49, /*!< 49 [Active] Serial Communication Block #11 */ + scb_12_interrupt_IRQn = 50, /*!< 50 [Active] Serial Communication Block #12 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dmac_2_IRQn = 54, /*!< 54 [Active] CPUSS DMAC, Channel #2 */ + cpuss_interrupts_dmac_3_IRQn = 55, /*!< 55 [Active] CPUSS DMAC, Channel #3 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_0_interrupts_4_IRQn = 127, /*!< 127 [Active] TCPWM #0, Counter #4 */ + tcpwm_0_interrupts_5_IRQn = 128, /*!< 128 [Active] TCPWM #0, Counter #5 */ + tcpwm_0_interrupts_6_IRQn = 129, /*!< 129 [Active] TCPWM #0, Counter #6 */ + tcpwm_0_interrupts_7_IRQn = 130, /*!< 130 [Active] TCPWM #0, Counter #7 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + tcpwm_1_interrupts_8_IRQn = 139, /*!< 139 [Active] TCPWM #1, Counter #8 */ + tcpwm_1_interrupts_9_IRQn = 140, /*!< 140 [Active] TCPWM #1, Counter #9 */ + tcpwm_1_interrupts_10_IRQn = 141, /*!< 141 [Active] TCPWM #1, Counter #10 */ + tcpwm_1_interrupts_11_IRQn = 142, /*!< 142 [Active] TCPWM #1, Counter #11 */ + tcpwm_1_interrupts_12_IRQn = 143, /*!< 143 [Active] TCPWM #1, Counter #12 */ + tcpwm_1_interrupts_13_IRQn = 144, /*!< 144 [Active] TCPWM #1, Counter #13 */ + tcpwm_1_interrupts_14_IRQn = 145, /*!< 145 [Active] TCPWM #1, Counter #14 */ + tcpwm_1_interrupts_15_IRQn = 146, /*!< 146 [Active] TCPWM #1, Counter #15 */ + tcpwm_1_interrupts_16_IRQn = 147, /*!< 147 [Active] TCPWM #1, Counter #16 */ + tcpwm_1_interrupts_17_IRQn = 148, /*!< 148 [Active] TCPWM #1, Counter #17 */ + tcpwm_1_interrupts_18_IRQn = 149, /*!< 149 [Active] TCPWM #1, Counter #18 */ + tcpwm_1_interrupts_19_IRQn = 150, /*!< 150 [Active] TCPWM #1, Counter #19 */ + tcpwm_1_interrupts_20_IRQn = 151, /*!< 151 [Active] TCPWM #1, Counter #20 */ + tcpwm_1_interrupts_21_IRQn = 152, /*!< 152 [Active] TCPWM #1, Counter #21 */ + tcpwm_1_interrupts_22_IRQn = 153, /*!< 153 [Active] TCPWM #1, Counter #22 */ + tcpwm_1_interrupts_23_IRQn = 154, /*!< 154 [Active] TCPWM #1, Counter #23 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + audioss_0_interrupt_i2s_IRQn = 156, /*!< 156 [Active] I2S0 Audio interrupt */ + audioss_0_interrupt_pdm_IRQn = 157, /*!< 157 [Active] PDM0/PCM0 Audio interrupt */ + audioss_1_interrupt_i2s_IRQn = 158, /*!< 158 [Active] I2S1 Audio interrupt */ + profile_interrupt_IRQn = 159, /*!< 159 [Active] Energy Profiler interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + sdhc_1_interrupt_wakeup_IRQn = 166, /*!< 166 [Active] EEMC wakeup interrupt for mxsdhc, not used */ + sdhc_1_interrupt_general_IRQn = 167, /*!< 167 [Active] Consolidated interrupt for mxsdhc for everything else */ + unconnected_IRQn = 240 /*!< 240 Unconnected */ +} IRQn_Type; + + +/******************************************************************************* +* Processor and Core Peripheral Section +*******************************************************************************/ + +/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __CM0P_PRESENT 0 /*!< CM0P present or not */ +#define __DTCM_PRESENT 0 /*!< DTCM present or not */ +#define __ICACHE_PRESENT 0 /*!< ICACHE present or not */ +#define __DCACHE_PRESENT 0 /*!< DCACHE present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + + +/* Memory Blocks */ +#define CY_ROM_BASE 0x00000000UL +#define CY_ROM_SIZE 0x00010000UL +#define CY_SRAM_BASE 0x08000000UL +#define CY_SRAM_SIZE 0x00080000UL +#define CY_FLASH_BASE 0x10000000UL +#define CY_FLASH_SIZE 0x00100000UL +#define CY_EM_EEPROM_BASE 0x14000000UL +#define CY_EM_EEPROM_SIZE 0x00008000UL +#define CY_SFLASH_BASE 0x16000000UL +#define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL +#define CY_EFUSE_BASE 0x402C0800UL +#define CY_EFUSE_SIZE 0x00000200UL + +#include "system_psoc6.h" /*!< PSoC 6 System */ + +/* IP List */ +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 2u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_M4CPUSS 1u +#define CY_IP_M4CPUSS_INSTANCES 1u +#define CY_IP_M4CPUSS_VERSION 2u +#define CY_IP_M4CPUSS_DMAC 1u +#define CY_IP_M4CPUSS_DMAC_INSTANCES 1u +#define CY_IP_M4CPUSS_DMAC_VERSION 2u +#define CY_IP_M4CPUSS_DMA 1u +#define CY_IP_M4CPUSS_DMA_INSTANCES 2u +#define CY_IP_M4CPUSS_DMA_VERSION 2u +#define CY_IP_MXCRYPTO 1u +#define CY_IP_MXCRYPTO_INSTANCES 1u +#define CY_IP_MXCRYPTO_VERSION 2u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u +#define CY_IP_MXS40PASS 1u +#define CY_IP_MXS40PASS_INSTANCES 1u +#define CY_IP_MXS40PASS_VERSION 1u +#define CY_IP_MXS40PASS_SAR 1u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u +#define CY_IP_MXS40PASS_SAR_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXPROFILE 1u +#define CY_IP_MXPROFILE_INSTANCES 1u +#define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 13u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 2u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u + +#include "psoc6_02_config.h" +#include "gpio_psoc6_02_100_wlcsp.h" + +#define CY_DEVICE_PSOC6A2M +#define CY_SILICON_ID 0xE4631202UL +#define CY_HF_CLK_MAX_FREQ 150000000UL + +#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL + +/******************************************************************************* +* SFLASH +*******************************************************************************/ + +#define SFLASH_BASE 0x16000000UL +#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */ + +/******************************************************************************* +* PERI +*******************************************************************************/ + +#define PERI_BASE 0x40000000UL +#define PERI ((PERI_Type*) PERI_BASE) /* 0x40000000 */ +#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40004000 */ +#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40004020 */ +#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40004040 */ +#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x40004060 */ +#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40004080 */ +#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x400040C0 */ +#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40004120 */ +#define PERI_GR10 ((PERI_GR_Type*) &PERI->GR[10]) /* 0x40004140 */ +#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40008000 */ +#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40008400 */ +#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40008800 */ +#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40008C00 */ +#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40009000 */ +#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40009400 */ +#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40009800 */ +#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40009C00 */ +#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ +#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ +#define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ +#define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ +#define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ +#define PERI_TR_1TO1_GR3 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[3]) /* 0x4000CC00 */ +#define PERI_TR_1TO1_GR4 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[4]) /* 0x4000D000 */ +#define PERI_TR_1TO1_GR5 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[5]) /* 0x4000D400 */ +#define PERI_TR_1TO1_GR6 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[6]) /* 0x4000D800 */ + +/******************************************************************************* +* PERI_MS +*******************************************************************************/ + +#define PERI_MS_BASE 0x40010000UL +#define PERI_MS ((PERI_MS_Type*) PERI_MS_BASE) /* 0x40010000 */ +#define PERI_MS_PPU_PR0 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[0]) /* 0x40010000 */ +#define PERI_MS_PPU_PR1 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[1]) /* 0x40010040 */ +#define PERI_MS_PPU_PR2 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[2]) /* 0x40010080 */ +#define PERI_MS_PPU_PR3 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[3]) /* 0x400100C0 */ +#define PERI_MS_PPU_PR4 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[4]) /* 0x40010100 */ +#define PERI_MS_PPU_PR5 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[5]) /* 0x40010140 */ +#define PERI_MS_PPU_PR6 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[6]) /* 0x40010180 */ +#define PERI_MS_PPU_PR7 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[7]) /* 0x400101C0 */ +#define PERI_MS_PPU_FX_PERI_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[0]) /* 0x40010800 */ +#define PERI_MS_PPU_FX_PERI_GR0_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[1]) /* 0x40010840 */ +#define PERI_MS_PPU_FX_PERI_GR1_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[2]) /* 0x40010880 */ +#define PERI_MS_PPU_FX_PERI_GR2_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[3]) /* 0x400108C0 */ +#define PERI_MS_PPU_FX_PERI_GR3_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[4]) /* 0x40010900 */ +#define PERI_MS_PPU_FX_PERI_GR4_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[5]) /* 0x40010940 */ +#define PERI_MS_PPU_FX_PERI_GR6_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[6]) /* 0x40010980 */ +#define PERI_MS_PPU_FX_PERI_GR9_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[7]) /* 0x400109C0 */ +#define PERI_MS_PPU_FX_PERI_GR10_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[8]) /* 0x40010A00 */ +#define PERI_MS_PPU_FX_PERI_TR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[9]) /* 0x40010A40 */ +#define PERI_MS_PPU_FX_CRYPTO_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[10]) /* 0x40010A80 */ +#define PERI_MS_PPU_FX_CRYPTO_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[11]) /* 0x40010AC0 */ +#define PERI_MS_PPU_FX_CRYPTO_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[12]) /* 0x40010B00 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[13]) /* 0x40010B40 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[14]) /* 0x40010B80 */ +#define PERI_MS_PPU_FX_CRYPTO_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[15]) /* 0x40010BC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[16]) /* 0x40010C00 */ +#define PERI_MS_PPU_FX_CPUSS_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[17]) /* 0x40010C40 */ +#define PERI_MS_PPU_FX_CPUSS_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[18]) /* 0x40010C80 */ +#define PERI_MS_PPU_FX_CPUSS_CM0_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[19]) /* 0x40010CC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[20]) /* 0x40010D00 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[21]) /* 0x40010D40 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT1_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[22]) /* 0x40010D80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT0_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[23]) /* 0x40010DC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT1_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[24]) /* 0x40010E00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT2_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[25]) /* 0x40010E40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT3_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[26]) /* 0x40010E80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT4_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[27]) /* 0x40010EC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT5_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[28]) /* 0x40010F00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT6_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[29]) /* 0x40010F40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT7_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[30]) /* 0x40010F80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT8_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[31]) /* 0x40010FC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT9_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[32]) /* 0x40011000 */ +#define PERI_MS_PPU_FX_IPC_STRUCT10_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[33]) /* 0x40011040 */ +#define PERI_MS_PPU_FX_IPC_STRUCT11_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[34]) /* 0x40011080 */ +#define PERI_MS_PPU_FX_IPC_STRUCT12_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[35]) /* 0x400110C0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT13_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[36]) /* 0x40011100 */ +#define PERI_MS_PPU_FX_IPC_STRUCT14_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[37]) /* 0x40011140 */ +#define PERI_MS_PPU_FX_IPC_STRUCT15_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[38]) /* 0x40011180 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT0_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[39]) /* 0x400111C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT1_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[40]) /* 0x40011200 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT2_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[41]) /* 0x40011240 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT3_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[42]) /* 0x40011280 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT4_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[43]) /* 0x400112C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT5_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[44]) /* 0x40011300 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT6_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[45]) /* 0x40011340 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT7_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[46]) /* 0x40011380 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT8_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[47]) /* 0x400113C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT9_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[48]) /* 0x40011400 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT10_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[49]) /* 0x40011440 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT11_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[50]) /* 0x40011480 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT12_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[51]) /* 0x400114C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT13_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[52]) /* 0x40011500 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT14_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[53]) /* 0x40011540 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT15_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[54]) /* 0x40011580 */ +#define PERI_MS_PPU_FX_PROT_SMPU_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[55]) /* 0x400115C0 */ +#define PERI_MS_PPU_FX_PROT_MPU0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[56]) /* 0x40011600 */ +#define PERI_MS_PPU_FX_PROT_MPU5_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[57]) /* 0x40011640 */ +#define PERI_MS_PPU_FX_PROT_MPU6_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[58]) /* 0x40011680 */ +#define PERI_MS_PPU_FX_PROT_MPU14_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[59]) /* 0x400116C0 */ +#define PERI_MS_PPU_FX_PROT_MPU15_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[60]) /* 0x40011700 */ +#define PERI_MS_PPU_FX_FLASHC_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[61]) /* 0x40011740 */ +#define PERI_MS_PPU_FX_FLASHC_CMD ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[62]) /* 0x40011780 */ +#define PERI_MS_PPU_FX_FLASHC_DFT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[63]) /* 0x400117C0 */ +#define PERI_MS_PPU_FX_FLASHC_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[64]) /* 0x40011800 */ +#define PERI_MS_PPU_FX_FLASHC_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[65]) /* 0x40011840 */ +#define PERI_MS_PPU_FX_FLASHC_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[66]) /* 0x40011880 */ +#define PERI_MS_PPU_FX_FLASHC_DW0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[67]) /* 0x400118C0 */ +#define PERI_MS_PPU_FX_FLASHC_DW1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[68]) /* 0x40011900 */ +#define PERI_MS_PPU_FX_FLASHC_DMAC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[69]) /* 0x40011940 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[70]) /* 0x40011980 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[71]) /* 0x400119C0 */ +#define PERI_MS_PPU_FX_FLASHC_FM ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[72]) /* 0x40011A00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[73]) /* 0x40011A40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[74]) /* 0x40011A80 */ +#define PERI_MS_PPU_FX_WDT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[75]) /* 0x40011AC0 */ +#define PERI_MS_PPU_FX_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[76]) /* 0x40011B00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[77]) /* 0x40011B40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[78]) /* 0x40011B80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[79]) /* 0x40011BC0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[80]) /* 0x40011C00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[81]) /* 0x40011C40 */ +#define PERI_MS_PPU_FX_BACKUP_BACKUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[82]) /* 0x40011C80 */ +#define PERI_MS_PPU_FX_DW0_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[83]) /* 0x40011CC0 */ +#define PERI_MS_PPU_FX_DW1_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[84]) /* 0x40011D00 */ +#define PERI_MS_PPU_FX_DW0_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[85]) /* 0x40011D40 */ +#define PERI_MS_PPU_FX_DW1_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[86]) /* 0x40011D80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[87]) /* 0x40011DC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[88]) /* 0x40011E00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[89]) /* 0x40011E40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[90]) /* 0x40011E80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[91]) /* 0x40011EC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[92]) /* 0x40011F00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[93]) /* 0x40011F40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[94]) /* 0x40011F80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[95]) /* 0x40011FC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[96]) /* 0x40012000 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[97]) /* 0x40012040 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[98]) /* 0x40012080 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[99]) /* 0x400120C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[100]) /* 0x40012100 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[101]) /* 0x40012140 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[102]) /* 0x40012180 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[103]) /* 0x400121C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[104]) /* 0x40012200 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[105]) /* 0x40012240 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[106]) /* 0x40012280 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[107]) /* 0x400122C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[108]) /* 0x40012300 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[109]) /* 0x40012340 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[110]) /* 0x40012380 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[111]) /* 0x400123C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[112]) /* 0x40012400 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[113]) /* 0x40012440 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[114]) /* 0x40012480 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[115]) /* 0x400124C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[116]) /* 0x40012500 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[117]) /* 0x40012540 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[118]) /* 0x40012580 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[119]) /* 0x400125C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[120]) /* 0x40012600 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[121]) /* 0x40012640 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[122]) /* 0x40012680 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[123]) /* 0x400126C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[124]) /* 0x40012700 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[125]) /* 0x40012740 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[126]) /* 0x40012780 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[127]) /* 0x400127C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[128]) /* 0x40012800 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[129]) /* 0x40012840 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[130]) /* 0x40012880 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[131]) /* 0x400128C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[132]) /* 0x40012900 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[133]) /* 0x40012940 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[134]) /* 0x40012980 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[135]) /* 0x400129C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[136]) /* 0x40012A00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[137]) /* 0x40012A40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[138]) /* 0x40012A80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[139]) /* 0x40012AC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[140]) /* 0x40012B00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[141]) /* 0x40012B40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[142]) /* 0x40012B80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[143]) /* 0x40012BC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[144]) /* 0x40012C00 */ +#define PERI_MS_PPU_FX_DMAC_TOP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[145]) /* 0x40012C40 */ +#define PERI_MS_PPU_FX_DMAC_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[146]) /* 0x40012C80 */ +#define PERI_MS_PPU_FX_DMAC_CH1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[147]) /* 0x40012CC0 */ +#define PERI_MS_PPU_FX_DMAC_CH2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[148]) /* 0x40012D00 */ +#define PERI_MS_PPU_FX_DMAC_CH3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[149]) /* 0x40012D40 */ +#define PERI_MS_PPU_FX_EFUSE_CTL ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[150]) /* 0x40012D80 */ +#define PERI_MS_PPU_FX_EFUSE_DATA ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[151]) /* 0x40012DC0 */ +#define PERI_MS_PPU_FX_PROFILE ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[152]) /* 0x40012E00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[153]) /* 0x40012E40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[154]) /* 0x40012E80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[155]) /* 0x40012EC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[156]) /* 0x40012F00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[157]) /* 0x40012F40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[158]) /* 0x40012F80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[159]) /* 0x40012FC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[160]) /* 0x40013000 */ +#define PERI_MS_PPU_FX_HSIOM_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[161]) /* 0x40013040 */ +#define PERI_MS_PPU_FX_HSIOM_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[162]) /* 0x40013080 */ +#define PERI_MS_PPU_FX_HSIOM_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[163]) /* 0x400130C0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[164]) /* 0x40013100 */ +#define PERI_MS_PPU_FX_HSIOM_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[165]) /* 0x40013140 */ +#define PERI_MS_PPU_FX_HSIOM_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[166]) /* 0x40013180 */ +#define PERI_MS_PPU_FX_HSIOM_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[167]) /* 0x400131C0 */ +#define PERI_MS_PPU_FX_HSIOM_AMUX ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[168]) /* 0x40013200 */ +#define PERI_MS_PPU_FX_HSIOM_MON ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[169]) /* 0x40013240 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[170]) /* 0x40013280 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[171]) /* 0x400132C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[172]) /* 0x40013300 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[173]) /* 0x40013340 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[174]) /* 0x40013380 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[175]) /* 0x400133C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[176]) /* 0x40013400 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[177]) /* 0x40013440 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[178]) /* 0x40013480 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[179]) /* 0x400134C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[180]) /* 0x40013500 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[181]) /* 0x40013540 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[182]) /* 0x40013580 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[183]) /* 0x400135C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[184]) /* 0x40013600 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[185]) /* 0x40013640 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[186]) /* 0x40013680 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[187]) /* 0x400136C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[188]) /* 0x40013700 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[189]) /* 0x40013740 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[190]) /* 0x40013780 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[191]) /* 0x400137C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[192]) /* 0x40013800 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[193]) /* 0x40013840 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[194]) /* 0x40013880 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[195]) /* 0x400138C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[196]) /* 0x40013900 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[197]) /* 0x40013940 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[198]) /* 0x40013980 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[199]) /* 0x400139C0 */ +#define PERI_MS_PPU_FX_GPIO_GPIO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[200]) /* 0x40013A00 */ +#define PERI_MS_PPU_FX_GPIO_TEST ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[201]) /* 0x40013A40 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[202]) /* 0x40013A80 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[203]) /* 0x40013AC0 */ +#define PERI_MS_PPU_FX_LPCOMP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[204]) /* 0x40013B00 */ +#define PERI_MS_PPU_FX_CSD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[205]) /* 0x40013B40 */ +#define PERI_MS_PPU_FX_TCPWM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[206]) /* 0x40013B80 */ +#define PERI_MS_PPU_FX_TCPWM1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[207]) /* 0x40013BC0 */ +#define PERI_MS_PPU_FX_LCD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[208]) /* 0x40013C00 */ +#define PERI_MS_PPU_FX_USBFS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[209]) /* 0x40013C40 */ +#define PERI_MS_PPU_FX_SMIF0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[210]) /* 0x40013C80 */ +#define PERI_MS_PPU_FX_SDHC0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[211]) /* 0x40013CC0 */ +#define PERI_MS_PPU_FX_SDHC1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[212]) /* 0x40013D00 */ +#define PERI_MS_PPU_FX_SCB0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[213]) /* 0x40013D40 */ +#define PERI_MS_PPU_FX_SCB1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[214]) /* 0x40013D80 */ +#define PERI_MS_PPU_FX_SCB2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[215]) /* 0x40013DC0 */ +#define PERI_MS_PPU_FX_SCB3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[216]) /* 0x40013E00 */ +#define PERI_MS_PPU_FX_SCB4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[217]) /* 0x40013E40 */ +#define PERI_MS_PPU_FX_SCB5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[218]) /* 0x40013E80 */ +#define PERI_MS_PPU_FX_SCB6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[219]) /* 0x40013EC0 */ +#define PERI_MS_PPU_FX_SCB7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[220]) /* 0x40013F00 */ +#define PERI_MS_PPU_FX_SCB8 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[221]) /* 0x40013F40 */ +#define PERI_MS_PPU_FX_SCB9 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[222]) /* 0x40013F80 */ +#define PERI_MS_PPU_FX_SCB10 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[223]) /* 0x40013FC0 */ +#define PERI_MS_PPU_FX_SCB11 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[224]) /* 0x40014000 */ +#define PERI_MS_PPU_FX_SCB12 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[225]) /* 0x40014040 */ +#define PERI_MS_PPU_FX_PDM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[226]) /* 0x40014080 */ +#define PERI_MS_PPU_FX_I2S0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[227]) /* 0x400140C0 */ +#define PERI_MS_PPU_FX_I2S1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[228]) /* 0x40014100 */ + +/******************************************************************************* +* CRYPTO +*******************************************************************************/ + +#define CRYPTO_BASE 0x40100000UL +#define CRYPTO ((CRYPTO_Type*) CRYPTO_BASE) /* 0x40100000 */ + +/******************************************************************************* +* CPUSS +*******************************************************************************/ + +#define CPUSS_BASE 0x40200000UL +#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40200000 */ + +/******************************************************************************* +* FAULT +*******************************************************************************/ + +#define FAULT_BASE 0x40210000UL +#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40210000 */ +#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40210000 */ +#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40210100 */ + +/******************************************************************************* +* IPC +*******************************************************************************/ + +#define IPC_BASE 0x40220000UL +#define IPC ((IPC_Type*) IPC_BASE) /* 0x40220000 */ +#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40220000 */ +#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40220020 */ +#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40220040 */ +#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40220060 */ +#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40220080 */ +#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402200A0 */ +#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402200C0 */ +#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402200E0 */ +#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40220100 */ +#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40220120 */ +#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40220140 */ +#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40220160 */ +#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40220180 */ +#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402201A0 */ +#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402201C0 */ +#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402201E0 */ +#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40221000 */ +#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40221020 */ +#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40221040 */ +#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40221060 */ +#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40221080 */ +#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402210A0 */ +#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402210C0 */ +#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402210E0 */ +#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40221100 */ +#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40221120 */ +#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40221140 */ +#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40221160 */ +#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40221180 */ +#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402211A0 */ +#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402211C0 */ +#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402211E0 */ + +/******************************************************************************* +* PROT +*******************************************************************************/ + +#define PROT_BASE 0x40230000UL +#define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ +#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ +#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ +#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402320C0 */ +#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40232100 */ +#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40232140 */ +#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40232180 */ +#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402321C0 */ +#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40232200 */ +#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40232240 */ +#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40232280 */ +#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402322C0 */ +#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40232300 */ +#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ +#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ +#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ +#define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ +#define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ +#define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ +#define PROT_MPU5_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[3]) /* 0x40235660 */ +#define PROT_MPU5_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[4]) /* 0x40235680 */ +#define PROT_MPU5_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[5]) /* 0x402356A0 */ +#define PROT_MPU5_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[6]) /* 0x402356C0 */ +#define PROT_MPU5_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[7]) /* 0x402356E0 */ +#define PROT_MPU6_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[0]) /* 0x40235A00 */ +#define PROT_MPU6_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[1]) /* 0x40235A20 */ +#define PROT_MPU6_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[2]) /* 0x40235A40 */ +#define PROT_MPU6_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[3]) /* 0x40235A60 */ +#define PROT_MPU6_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[4]) /* 0x40235A80 */ +#define PROT_MPU6_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[5]) /* 0x40235AA0 */ +#define PROT_MPU6_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[6]) /* 0x40235AC0 */ +#define PROT_MPU6_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[7]) /* 0x40235AE0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ + +/******************************************************************************* +* FLASHC +*******************************************************************************/ + +#define FLASHC_BASE 0x40240000UL +#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40240000 */ +#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4024F000 */ + +/******************************************************************************* +* SRSS +*******************************************************************************/ + +#define SRSS_BASE 0x40260000UL +#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ +#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */ +#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */ + +/******************************************************************************* +* BACKUP +*******************************************************************************/ + +#define BACKUP_BASE 0x40270000UL +#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ + +/******************************************************************************* +* DW +*******************************************************************************/ + +#define DW0_BASE 0x40280000UL +#define DW1_BASE 0x40290000UL +#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ +#define DW1 ((DW_Type*) DW1_BASE) /* 0x40290000 */ +#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40288000 */ +#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40288040 */ +#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40288080 */ +#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x402880C0 */ +#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40288100 */ +#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x40288140 */ +#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x40288180 */ +#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402881C0 */ +#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40288200 */ +#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40288240 */ +#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40288280 */ +#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x402882C0 */ +#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40288300 */ +#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x40288340 */ +#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x40288380 */ +#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402883C0 */ +#define DW0_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[16]) /* 0x40288400 */ +#define DW0_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[17]) /* 0x40288440 */ +#define DW0_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[18]) /* 0x40288480 */ +#define DW0_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[19]) /* 0x402884C0 */ +#define DW0_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[20]) /* 0x40288500 */ +#define DW0_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[21]) /* 0x40288540 */ +#define DW0_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[22]) /* 0x40288580 */ +#define DW0_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[23]) /* 0x402885C0 */ +#define DW0_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[24]) /* 0x40288600 */ +#define DW0_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[25]) /* 0x40288640 */ +#define DW0_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[26]) /* 0x40288680 */ +#define DW0_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[27]) /* 0x402886C0 */ +#define DW0_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[28]) /* 0x40288700 */ +#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40298000 */ +#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40298040 */ +#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40298080 */ +#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x402980C0 */ +#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40298100 */ +#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x40298140 */ +#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x40298180 */ +#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402981C0 */ +#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40298200 */ +#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40298240 */ +#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40298280 */ +#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x402982C0 */ +#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40298300 */ +#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x40298340 */ +#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x40298380 */ +#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402983C0 */ +#define DW1_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[16]) /* 0x40298400 */ +#define DW1_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[17]) /* 0x40298440 */ +#define DW1_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[18]) /* 0x40298480 */ +#define DW1_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[19]) /* 0x402984C0 */ +#define DW1_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[20]) /* 0x40298500 */ +#define DW1_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[21]) /* 0x40298540 */ +#define DW1_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[22]) /* 0x40298580 */ +#define DW1_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[23]) /* 0x402985C0 */ +#define DW1_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[24]) /* 0x40298600 */ +#define DW1_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[25]) /* 0x40298640 */ +#define DW1_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[26]) /* 0x40298680 */ +#define DW1_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[27]) /* 0x402986C0 */ +#define DW1_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[28]) /* 0x40298700 */ + +/******************************************************************************* +* DMAC +*******************************************************************************/ + +#define DMAC_BASE 0x402A0000UL +#define DMAC ((DMAC_Type*) DMAC_BASE) /* 0x402A0000 */ +#define DMAC_CH0 ((DMAC_CH_Type*) &DMAC->CH[0]) /* 0x402A1000 */ +#define DMAC_CH1 ((DMAC_CH_Type*) &DMAC->CH[1]) /* 0x402A1100 */ +#define DMAC_CH2 ((DMAC_CH_Type*) &DMAC->CH[2]) /* 0x402A1200 */ +#define DMAC_CH3 ((DMAC_CH_Type*) &DMAC->CH[3]) /* 0x402A1300 */ + +/******************************************************************************* +* EFUSE +*******************************************************************************/ + +#define EFUSE_BASE 0x402C0000UL +#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ + +/******************************************************************************* +* PROFILE +*******************************************************************************/ + +#define PROFILE_BASE 0x402D0000UL +#define PROFILE ((PROFILE_Type*) PROFILE_BASE) /* 0x402D0000 */ +#define PROFILE_CNT_STRUCT0 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[0]) /* 0x402D0800 */ +#define PROFILE_CNT_STRUCT1 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[1]) /* 0x402D0810 */ +#define PROFILE_CNT_STRUCT2 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[2]) /* 0x402D0820 */ +#define PROFILE_CNT_STRUCT3 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[3]) /* 0x402D0830 */ +#define PROFILE_CNT_STRUCT4 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[4]) /* 0x402D0840 */ +#define PROFILE_CNT_STRUCT5 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[5]) /* 0x402D0850 */ +#define PROFILE_CNT_STRUCT6 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[6]) /* 0x402D0860 */ +#define PROFILE_CNT_STRUCT7 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[7]) /* 0x402D0870 */ + +/******************************************************************************* +* HSIOM +*******************************************************************************/ + +#define HSIOM_BASE 0x40300000UL +#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40300000 */ +#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40300000 */ +#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40300010 */ +#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40300020 */ +#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40300030 */ +#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40300040 */ +#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40300050 */ +#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40300060 */ +#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40300070 */ +#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40300080 */ +#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40300090 */ +#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403000A0 */ +#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403000B0 */ +#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403000C0 */ +#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403000D0 */ +#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403000E0 */ + +/******************************************************************************* +* GPIO +*******************************************************************************/ + +#define GPIO_BASE 0x40310000UL +#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40310000 */ +#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40310000 */ +#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40310080 */ +#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40310100 */ +#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40310180 */ +#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40310200 */ +#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40310280 */ +#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40310300 */ +#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40310380 */ +#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40310400 */ +#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40310480 */ +#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40310500 */ +#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40310580 */ +#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40310600 */ +#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40310680 */ +#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40310700 */ + +/******************************************************************************* +* SMARTIO +*******************************************************************************/ + +#define SMARTIO_BASE 0x40320000UL +#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40320000 */ +#define SMARTIO_PRT8 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[8]) /* 0x40320800 */ +#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40320900 */ + +/******************************************************************************* +* LPCOMP +*******************************************************************************/ + +#define LPCOMP_BASE 0x40350000UL +#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */ + +/******************************************************************************* +* CSD +*******************************************************************************/ + +#define CSD0_BASE 0x40360000UL +#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */ + +/******************************************************************************* +* TCPWM +*******************************************************************************/ + +#define TCPWM0_BASE 0x40380000UL +#define TCPWM1_BASE 0x40390000UL +#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM1 ((TCPWM_Type*) TCPWM1_BASE) /* 0x40390000 */ +#define TCPWM0_CNT0 ((TCPWM_CNT_Type*) &TCPWM0->CNT[0]) /* 0x40380100 */ +#define TCPWM0_CNT1 ((TCPWM_CNT_Type*) &TCPWM0->CNT[1]) /* 0x40380140 */ +#define TCPWM0_CNT2 ((TCPWM_CNT_Type*) &TCPWM0->CNT[2]) /* 0x40380180 */ +#define TCPWM0_CNT3 ((TCPWM_CNT_Type*) &TCPWM0->CNT[3]) /* 0x403801C0 */ +#define TCPWM0_CNT4 ((TCPWM_CNT_Type*) &TCPWM0->CNT[4]) /* 0x40380200 */ +#define TCPWM0_CNT5 ((TCPWM_CNT_Type*) &TCPWM0->CNT[5]) /* 0x40380240 */ +#define TCPWM0_CNT6 ((TCPWM_CNT_Type*) &TCPWM0->CNT[6]) /* 0x40380280 */ +#define TCPWM0_CNT7 ((TCPWM_CNT_Type*) &TCPWM0->CNT[7]) /* 0x403802C0 */ +#define TCPWM1_CNT0 ((TCPWM_CNT_Type*) &TCPWM1->CNT[0]) /* 0x40390100 */ +#define TCPWM1_CNT1 ((TCPWM_CNT_Type*) &TCPWM1->CNT[1]) /* 0x40390140 */ +#define TCPWM1_CNT2 ((TCPWM_CNT_Type*) &TCPWM1->CNT[2]) /* 0x40390180 */ +#define TCPWM1_CNT3 ((TCPWM_CNT_Type*) &TCPWM1->CNT[3]) /* 0x403901C0 */ +#define TCPWM1_CNT4 ((TCPWM_CNT_Type*) &TCPWM1->CNT[4]) /* 0x40390200 */ +#define TCPWM1_CNT5 ((TCPWM_CNT_Type*) &TCPWM1->CNT[5]) /* 0x40390240 */ +#define TCPWM1_CNT6 ((TCPWM_CNT_Type*) &TCPWM1->CNT[6]) /* 0x40390280 */ +#define TCPWM1_CNT7 ((TCPWM_CNT_Type*) &TCPWM1->CNT[7]) /* 0x403902C0 */ +#define TCPWM1_CNT8 ((TCPWM_CNT_Type*) &TCPWM1->CNT[8]) /* 0x40390300 */ +#define TCPWM1_CNT9 ((TCPWM_CNT_Type*) &TCPWM1->CNT[9]) /* 0x40390340 */ +#define TCPWM1_CNT10 ((TCPWM_CNT_Type*) &TCPWM1->CNT[10]) /* 0x40390380 */ +#define TCPWM1_CNT11 ((TCPWM_CNT_Type*) &TCPWM1->CNT[11]) /* 0x403903C0 */ +#define TCPWM1_CNT12 ((TCPWM_CNT_Type*) &TCPWM1->CNT[12]) /* 0x40390400 */ +#define TCPWM1_CNT13 ((TCPWM_CNT_Type*) &TCPWM1->CNT[13]) /* 0x40390440 */ +#define TCPWM1_CNT14 ((TCPWM_CNT_Type*) &TCPWM1->CNT[14]) /* 0x40390480 */ +#define TCPWM1_CNT15 ((TCPWM_CNT_Type*) &TCPWM1->CNT[15]) /* 0x403904C0 */ +#define TCPWM1_CNT16 ((TCPWM_CNT_Type*) &TCPWM1->CNT[16]) /* 0x40390500 */ +#define TCPWM1_CNT17 ((TCPWM_CNT_Type*) &TCPWM1->CNT[17]) /* 0x40390540 */ +#define TCPWM1_CNT18 ((TCPWM_CNT_Type*) &TCPWM1->CNT[18]) /* 0x40390580 */ +#define TCPWM1_CNT19 ((TCPWM_CNT_Type*) &TCPWM1->CNT[19]) /* 0x403905C0 */ +#define TCPWM1_CNT20 ((TCPWM_CNT_Type*) &TCPWM1->CNT[20]) /* 0x40390600 */ +#define TCPWM1_CNT21 ((TCPWM_CNT_Type*) &TCPWM1->CNT[21]) /* 0x40390640 */ +#define TCPWM1_CNT22 ((TCPWM_CNT_Type*) &TCPWM1->CNT[22]) /* 0x40390680 */ +#define TCPWM1_CNT23 ((TCPWM_CNT_Type*) &TCPWM1->CNT[23]) /* 0x403906C0 */ + +/******************************************************************************* +* LCD +*******************************************************************************/ + +#define LCD0_BASE 0x403B0000UL +#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ + +/******************************************************************************* +* USBFS +*******************************************************************************/ + +#define USBFS0_BASE 0x403F0000UL +#define USBFS0 ((USBFS_Type*) USBFS0_BASE) /* 0x403F0000 */ +#define USBFS0_USBDEV ((USBFS_USBDEV_Type*) &USBFS0->USBDEV) /* 0x403F0000 */ +#define USBFS0_USBLPM ((USBFS_USBLPM_Type*) &USBFS0->USBLPM) /* 0x403F2000 */ +#define USBFS0_USBHOST ((USBFS_USBHOST_Type*) &USBFS0->USBHOST) /* 0x403F4000 */ + +/******************************************************************************* +* SMIF +*******************************************************************************/ + +#define SMIF0_BASE 0x40420000UL +#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ +#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ +#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ +#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ +#define SMIF0_DEVICE3 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[3]) /* 0x40420980 */ + +/******************************************************************************* +* SDHC +*******************************************************************************/ + +#define SDHC0_BASE 0x40460000UL +#define SDHC1_BASE 0x40470000UL +#define SDHC0 ((SDHC_Type*) SDHC0_BASE) /* 0x40460000 */ +#define SDHC1 ((SDHC_Type*) SDHC1_BASE) /* 0x40470000 */ +#define SDHC0_WRAP ((SDHC_WRAP_Type*) &SDHC0->WRAP) /* 0x40460000 */ +#define SDHC1_WRAP ((SDHC_WRAP_Type*) &SDHC1->WRAP) /* 0x40470000 */ +#define SDHC0_CORE ((SDHC_CORE_Type*) &SDHC0->CORE) /* 0x40461000 */ +#define SDHC1_CORE ((SDHC_CORE_Type*) &SDHC1->CORE) /* 0x40471000 */ + +/******************************************************************************* +* SCB +*******************************************************************************/ + +#define SCB0_BASE 0x40600000UL +#define SCB1_BASE 0x40610000UL +#define SCB2_BASE 0x40620000UL +#define SCB3_BASE 0x40630000UL +#define SCB4_BASE 0x40640000UL +#define SCB5_BASE 0x40650000UL +#define SCB6_BASE 0x40660000UL +#define SCB7_BASE 0x40670000UL +#define SCB8_BASE 0x40680000UL +#define SCB9_BASE 0x40690000UL +#define SCB10_BASE 0x406A0000UL +#define SCB11_BASE 0x406B0000UL +#define SCB12_BASE 0x406C0000UL +#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40600000 */ +#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40610000 */ +#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40620000 */ +#define SCB3 ((CySCB_Type*) SCB3_BASE) /* 0x40630000 */ +#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40640000 */ +#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40650000 */ +#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40660000 */ +#define SCB7 ((CySCB_Type*) SCB7_BASE) /* 0x40670000 */ +#define SCB8 ((CySCB_Type*) SCB8_BASE) /* 0x40680000 */ +#define SCB9 ((CySCB_Type*) SCB9_BASE) /* 0x40690000 */ +#define SCB10 ((CySCB_Type*) SCB10_BASE) /* 0x406A0000 */ +#define SCB11 ((CySCB_Type*) SCB11_BASE) /* 0x406B0000 */ +#define SCB12 ((CySCB_Type*) SCB12_BASE) /* 0x406C0000 */ + +/******************************************************************************* +* SAR +*******************************************************************************/ + +#define SAR_BASE 0x409D0000UL +#define SAR ((SAR_Type*) SAR_BASE) /* 0x409D0000 */ + +/******************************************************************************* +* PASS +*******************************************************************************/ + +#define PASS_BASE 0x409F0000UL +#define PASS ((PASS_Type*) PASS_BASE) /* 0x409F0000 */ +#define PASS_AREF ((PASS_AREF_Type*) &PASS->AREF) /* 0x409F0E00 */ + +/******************************************************************************* +* PDM +*******************************************************************************/ + +#define PDM0_BASE 0x40A00000UL +#define PDM0 ((PDM_Type*) PDM0_BASE) /* 0x40A00000 */ + +/******************************************************************************* +* I2S +*******************************************************************************/ + +#define I2S0_BASE 0x40A10000UL +#define I2S1_BASE 0x40A11000UL +#define I2S0 ((I2S_Type*) I2S0_BASE) /* 0x40A10000 */ +#define I2S1 ((I2S_Type*) I2S1_BASE) /* 0x40A11000 */ + +/** \} CY8C6148FNI-S2F43 */ + +#endif /* _CY8C6148FNI_S2F43_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c614aazi_s2f04.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c614aazi_s2f04.h new file mode 100644 index 0000000000..37bdca82bd --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c614aazi_s2f04.h @@ -0,0 +1,1088 @@ +/***************************************************************************//** +* \file cy8c614aazi_s2f04.h +* +* \brief +* CY8C614AAZI-S2F04 device header +* +* \note +* Generator version: 1.6.0.225 +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CY8C614AAZI_S2F04_H_ +#define _CY8C614AAZI_S2F04_H_ + +/** +* \addtogroup group_device CY8C614AAZI-S2F04 +* \{ +*/ + +/** +* \addtogroup Configuration_of_CMSIS +* \{ +*/ + +/******************************************************************************* +* Interrupt Number Definition +*******************************************************************************/ + +typedef enum { + /* ARM Cortex-M4 Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C614AAZI-S2F04 Peripheral Interrupt Numbers */ + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_1_IRQn = 1, /*!< 1 [DeepSleep] GPIO Port Interrupt #1 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_4_IRQn = 4, /*!< 4 [DeepSleep] GPIO Port Interrupt #4 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_13_IRQn = 13, /*!< 13 [DeepSleep] GPIO Port Interrupt #13 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_8_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #8 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + scb_6_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #6 */ + scb_7_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #7 */ + scb_9_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #9 */ + scb_10_interrupt_IRQn = 48, /*!< 48 [Active] Serial Communication Block #10 */ + scb_11_interrupt_IRQn = 49, /*!< 49 [Active] Serial Communication Block #11 */ + scb_12_interrupt_IRQn = 50, /*!< 50 [Active] Serial Communication Block #12 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dmac_2_IRQn = 54, /*!< 54 [Active] CPUSS DMAC, Channel #2 */ + cpuss_interrupts_dmac_3_IRQn = 55, /*!< 55 [Active] CPUSS DMAC, Channel #3 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_0_interrupts_4_IRQn = 127, /*!< 127 [Active] TCPWM #0, Counter #4 */ + tcpwm_0_interrupts_5_IRQn = 128, /*!< 128 [Active] TCPWM #0, Counter #5 */ + tcpwm_0_interrupts_6_IRQn = 129, /*!< 129 [Active] TCPWM #0, Counter #6 */ + tcpwm_0_interrupts_7_IRQn = 130, /*!< 130 [Active] TCPWM #0, Counter #7 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + tcpwm_1_interrupts_8_IRQn = 139, /*!< 139 [Active] TCPWM #1, Counter #8 */ + tcpwm_1_interrupts_9_IRQn = 140, /*!< 140 [Active] TCPWM #1, Counter #9 */ + tcpwm_1_interrupts_10_IRQn = 141, /*!< 141 [Active] TCPWM #1, Counter #10 */ + tcpwm_1_interrupts_11_IRQn = 142, /*!< 142 [Active] TCPWM #1, Counter #11 */ + tcpwm_1_interrupts_12_IRQn = 143, /*!< 143 [Active] TCPWM #1, Counter #12 */ + tcpwm_1_interrupts_13_IRQn = 144, /*!< 144 [Active] TCPWM #1, Counter #13 */ + tcpwm_1_interrupts_14_IRQn = 145, /*!< 145 [Active] TCPWM #1, Counter #14 */ + tcpwm_1_interrupts_15_IRQn = 146, /*!< 146 [Active] TCPWM #1, Counter #15 */ + tcpwm_1_interrupts_16_IRQn = 147, /*!< 147 [Active] TCPWM #1, Counter #16 */ + tcpwm_1_interrupts_17_IRQn = 148, /*!< 148 [Active] TCPWM #1, Counter #17 */ + tcpwm_1_interrupts_18_IRQn = 149, /*!< 149 [Active] TCPWM #1, Counter #18 */ + tcpwm_1_interrupts_19_IRQn = 150, /*!< 150 [Active] TCPWM #1, Counter #19 */ + tcpwm_1_interrupts_20_IRQn = 151, /*!< 151 [Active] TCPWM #1, Counter #20 */ + tcpwm_1_interrupts_21_IRQn = 152, /*!< 152 [Active] TCPWM #1, Counter #21 */ + tcpwm_1_interrupts_22_IRQn = 153, /*!< 153 [Active] TCPWM #1, Counter #22 */ + tcpwm_1_interrupts_23_IRQn = 154, /*!< 154 [Active] TCPWM #1, Counter #23 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + audioss_0_interrupt_i2s_IRQn = 156, /*!< 156 [Active] I2S0 Audio interrupt */ + audioss_0_interrupt_pdm_IRQn = 157, /*!< 157 [Active] PDM0/PCM0 Audio interrupt */ + audioss_1_interrupt_i2s_IRQn = 158, /*!< 158 [Active] I2S1 Audio interrupt */ + profile_interrupt_IRQn = 159, /*!< 159 [Active] Energy Profiler interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + sdhc_1_interrupt_wakeup_IRQn = 166, /*!< 166 [Active] EEMC wakeup interrupt for mxsdhc, not used */ + sdhc_1_interrupt_general_IRQn = 167, /*!< 167 [Active] Consolidated interrupt for mxsdhc for everything else */ + unconnected_IRQn = 240 /*!< 240 Unconnected */ +} IRQn_Type; + + +/******************************************************************************* +* Processor and Core Peripheral Section +*******************************************************************************/ + +/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __CM0P_PRESENT 0 /*!< CM0P present or not */ +#define __DTCM_PRESENT 0 /*!< DTCM present or not */ +#define __ICACHE_PRESENT 0 /*!< ICACHE present or not */ +#define __DCACHE_PRESENT 0 /*!< DCACHE present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + + +/* Memory Blocks */ +#define CY_ROM_BASE 0x00000000UL +#define CY_ROM_SIZE 0x00010000UL +#define CY_SRAM_BASE 0x08000000UL +#define CY_SRAM_SIZE 0x00100000UL +#define CY_FLASH_BASE 0x10000000UL +#define CY_FLASH_SIZE 0x00200000UL +#define CY_EM_EEPROM_BASE 0x14000000UL +#define CY_EM_EEPROM_SIZE 0x00008000UL +#define CY_SFLASH_BASE 0x16000000UL +#define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL +#define CY_EFUSE_BASE 0x402C0800UL +#define CY_EFUSE_SIZE 0x00000200UL + +#include "system_psoc6.h" /*!< PSoC 6 System */ + +/* IP List */ +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 2u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_M4CPUSS 1u +#define CY_IP_M4CPUSS_INSTANCES 1u +#define CY_IP_M4CPUSS_VERSION 2u +#define CY_IP_M4CPUSS_DMAC 1u +#define CY_IP_M4CPUSS_DMAC_INSTANCES 1u +#define CY_IP_M4CPUSS_DMAC_VERSION 2u +#define CY_IP_M4CPUSS_DMA 1u +#define CY_IP_M4CPUSS_DMA_INSTANCES 2u +#define CY_IP_M4CPUSS_DMA_VERSION 2u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u +#define CY_IP_MXS40PASS 1u +#define CY_IP_MXS40PASS_INSTANCES 1u +#define CY_IP_MXS40PASS_VERSION 1u +#define CY_IP_MXS40PASS_SAR 1u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u +#define CY_IP_MXS40PASS_SAR_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXPROFILE 1u +#define CY_IP_MXPROFILE_INSTANCES 1u +#define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 13u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 2u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u + +#include "psoc6_02_config.h" +#include "gpio_psoc6_02_128_tqfp.h" + +#define CY_DEVICE_PSOC6A2M +#define CY_SILICON_ID 0xE45B1202UL +#define CY_HF_CLK_MAX_FREQ 150000000UL + +#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL + +/******************************************************************************* +* SFLASH +*******************************************************************************/ + +#define SFLASH_BASE 0x16000000UL +#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */ + +/******************************************************************************* +* PERI +*******************************************************************************/ + +#define PERI_BASE 0x40000000UL +#define PERI ((PERI_Type*) PERI_BASE) /* 0x40000000 */ +#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40004000 */ +#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40004020 */ +#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40004040 */ +#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x40004060 */ +#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40004080 */ +#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x400040C0 */ +#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40004120 */ +#define PERI_GR10 ((PERI_GR_Type*) &PERI->GR[10]) /* 0x40004140 */ +#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40008000 */ +#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40008400 */ +#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40008800 */ +#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40008C00 */ +#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40009000 */ +#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40009400 */ +#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40009800 */ +#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40009C00 */ +#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ +#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ +#define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ +#define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ +#define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ +#define PERI_TR_1TO1_GR3 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[3]) /* 0x4000CC00 */ +#define PERI_TR_1TO1_GR4 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[4]) /* 0x4000D000 */ +#define PERI_TR_1TO1_GR5 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[5]) /* 0x4000D400 */ +#define PERI_TR_1TO1_GR6 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[6]) /* 0x4000D800 */ + +/******************************************************************************* +* PERI_MS +*******************************************************************************/ + +#define PERI_MS_BASE 0x40010000UL +#define PERI_MS ((PERI_MS_Type*) PERI_MS_BASE) /* 0x40010000 */ +#define PERI_MS_PPU_PR0 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[0]) /* 0x40010000 */ +#define PERI_MS_PPU_PR1 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[1]) /* 0x40010040 */ +#define PERI_MS_PPU_PR2 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[2]) /* 0x40010080 */ +#define PERI_MS_PPU_PR3 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[3]) /* 0x400100C0 */ +#define PERI_MS_PPU_PR4 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[4]) /* 0x40010100 */ +#define PERI_MS_PPU_PR5 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[5]) /* 0x40010140 */ +#define PERI_MS_PPU_PR6 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[6]) /* 0x40010180 */ +#define PERI_MS_PPU_PR7 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[7]) /* 0x400101C0 */ +#define PERI_MS_PPU_FX_PERI_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[0]) /* 0x40010800 */ +#define PERI_MS_PPU_FX_PERI_GR0_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[1]) /* 0x40010840 */ +#define PERI_MS_PPU_FX_PERI_GR1_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[2]) /* 0x40010880 */ +#define PERI_MS_PPU_FX_PERI_GR2_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[3]) /* 0x400108C0 */ +#define PERI_MS_PPU_FX_PERI_GR3_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[4]) /* 0x40010900 */ +#define PERI_MS_PPU_FX_PERI_GR4_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[5]) /* 0x40010940 */ +#define PERI_MS_PPU_FX_PERI_GR6_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[6]) /* 0x40010980 */ +#define PERI_MS_PPU_FX_PERI_GR9_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[7]) /* 0x400109C0 */ +#define PERI_MS_PPU_FX_PERI_GR10_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[8]) /* 0x40010A00 */ +#define PERI_MS_PPU_FX_PERI_TR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[9]) /* 0x40010A40 */ +#define PERI_MS_PPU_FX_CRYPTO_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[10]) /* 0x40010A80 */ +#define PERI_MS_PPU_FX_CRYPTO_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[11]) /* 0x40010AC0 */ +#define PERI_MS_PPU_FX_CRYPTO_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[12]) /* 0x40010B00 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[13]) /* 0x40010B40 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[14]) /* 0x40010B80 */ +#define PERI_MS_PPU_FX_CRYPTO_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[15]) /* 0x40010BC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[16]) /* 0x40010C00 */ +#define PERI_MS_PPU_FX_CPUSS_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[17]) /* 0x40010C40 */ +#define PERI_MS_PPU_FX_CPUSS_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[18]) /* 0x40010C80 */ +#define PERI_MS_PPU_FX_CPUSS_CM0_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[19]) /* 0x40010CC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[20]) /* 0x40010D00 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[21]) /* 0x40010D40 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT1_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[22]) /* 0x40010D80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT0_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[23]) /* 0x40010DC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT1_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[24]) /* 0x40010E00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT2_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[25]) /* 0x40010E40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT3_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[26]) /* 0x40010E80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT4_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[27]) /* 0x40010EC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT5_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[28]) /* 0x40010F00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT6_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[29]) /* 0x40010F40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT7_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[30]) /* 0x40010F80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT8_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[31]) /* 0x40010FC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT9_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[32]) /* 0x40011000 */ +#define PERI_MS_PPU_FX_IPC_STRUCT10_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[33]) /* 0x40011040 */ +#define PERI_MS_PPU_FX_IPC_STRUCT11_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[34]) /* 0x40011080 */ +#define PERI_MS_PPU_FX_IPC_STRUCT12_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[35]) /* 0x400110C0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT13_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[36]) /* 0x40011100 */ +#define PERI_MS_PPU_FX_IPC_STRUCT14_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[37]) /* 0x40011140 */ +#define PERI_MS_PPU_FX_IPC_STRUCT15_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[38]) /* 0x40011180 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT0_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[39]) /* 0x400111C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT1_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[40]) /* 0x40011200 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT2_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[41]) /* 0x40011240 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT3_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[42]) /* 0x40011280 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT4_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[43]) /* 0x400112C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT5_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[44]) /* 0x40011300 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT6_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[45]) /* 0x40011340 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT7_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[46]) /* 0x40011380 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT8_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[47]) /* 0x400113C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT9_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[48]) /* 0x40011400 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT10_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[49]) /* 0x40011440 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT11_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[50]) /* 0x40011480 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT12_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[51]) /* 0x400114C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT13_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[52]) /* 0x40011500 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT14_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[53]) /* 0x40011540 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT15_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[54]) /* 0x40011580 */ +#define PERI_MS_PPU_FX_PROT_SMPU_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[55]) /* 0x400115C0 */ +#define PERI_MS_PPU_FX_PROT_MPU0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[56]) /* 0x40011600 */ +#define PERI_MS_PPU_FX_PROT_MPU5_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[57]) /* 0x40011640 */ +#define PERI_MS_PPU_FX_PROT_MPU6_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[58]) /* 0x40011680 */ +#define PERI_MS_PPU_FX_PROT_MPU14_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[59]) /* 0x400116C0 */ +#define PERI_MS_PPU_FX_PROT_MPU15_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[60]) /* 0x40011700 */ +#define PERI_MS_PPU_FX_FLASHC_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[61]) /* 0x40011740 */ +#define PERI_MS_PPU_FX_FLASHC_CMD ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[62]) /* 0x40011780 */ +#define PERI_MS_PPU_FX_FLASHC_DFT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[63]) /* 0x400117C0 */ +#define PERI_MS_PPU_FX_FLASHC_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[64]) /* 0x40011800 */ +#define PERI_MS_PPU_FX_FLASHC_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[65]) /* 0x40011840 */ +#define PERI_MS_PPU_FX_FLASHC_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[66]) /* 0x40011880 */ +#define PERI_MS_PPU_FX_FLASHC_DW0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[67]) /* 0x400118C0 */ +#define PERI_MS_PPU_FX_FLASHC_DW1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[68]) /* 0x40011900 */ +#define PERI_MS_PPU_FX_FLASHC_DMAC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[69]) /* 0x40011940 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[70]) /* 0x40011980 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[71]) /* 0x400119C0 */ +#define PERI_MS_PPU_FX_FLASHC_FM ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[72]) /* 0x40011A00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[73]) /* 0x40011A40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[74]) /* 0x40011A80 */ +#define PERI_MS_PPU_FX_WDT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[75]) /* 0x40011AC0 */ +#define PERI_MS_PPU_FX_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[76]) /* 0x40011B00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[77]) /* 0x40011B40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[78]) /* 0x40011B80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[79]) /* 0x40011BC0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[80]) /* 0x40011C00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[81]) /* 0x40011C40 */ +#define PERI_MS_PPU_FX_BACKUP_BACKUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[82]) /* 0x40011C80 */ +#define PERI_MS_PPU_FX_DW0_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[83]) /* 0x40011CC0 */ +#define PERI_MS_PPU_FX_DW1_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[84]) /* 0x40011D00 */ +#define PERI_MS_PPU_FX_DW0_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[85]) /* 0x40011D40 */ +#define PERI_MS_PPU_FX_DW1_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[86]) /* 0x40011D80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[87]) /* 0x40011DC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[88]) /* 0x40011E00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[89]) /* 0x40011E40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[90]) /* 0x40011E80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[91]) /* 0x40011EC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[92]) /* 0x40011F00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[93]) /* 0x40011F40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[94]) /* 0x40011F80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[95]) /* 0x40011FC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[96]) /* 0x40012000 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[97]) /* 0x40012040 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[98]) /* 0x40012080 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[99]) /* 0x400120C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[100]) /* 0x40012100 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[101]) /* 0x40012140 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[102]) /* 0x40012180 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[103]) /* 0x400121C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[104]) /* 0x40012200 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[105]) /* 0x40012240 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[106]) /* 0x40012280 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[107]) /* 0x400122C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[108]) /* 0x40012300 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[109]) /* 0x40012340 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[110]) /* 0x40012380 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[111]) /* 0x400123C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[112]) /* 0x40012400 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[113]) /* 0x40012440 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[114]) /* 0x40012480 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[115]) /* 0x400124C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[116]) /* 0x40012500 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[117]) /* 0x40012540 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[118]) /* 0x40012580 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[119]) /* 0x400125C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[120]) /* 0x40012600 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[121]) /* 0x40012640 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[122]) /* 0x40012680 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[123]) /* 0x400126C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[124]) /* 0x40012700 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[125]) /* 0x40012740 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[126]) /* 0x40012780 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[127]) /* 0x400127C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[128]) /* 0x40012800 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[129]) /* 0x40012840 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[130]) /* 0x40012880 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[131]) /* 0x400128C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[132]) /* 0x40012900 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[133]) /* 0x40012940 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[134]) /* 0x40012980 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[135]) /* 0x400129C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[136]) /* 0x40012A00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[137]) /* 0x40012A40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[138]) /* 0x40012A80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[139]) /* 0x40012AC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[140]) /* 0x40012B00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[141]) /* 0x40012B40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[142]) /* 0x40012B80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[143]) /* 0x40012BC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[144]) /* 0x40012C00 */ +#define PERI_MS_PPU_FX_DMAC_TOP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[145]) /* 0x40012C40 */ +#define PERI_MS_PPU_FX_DMAC_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[146]) /* 0x40012C80 */ +#define PERI_MS_PPU_FX_DMAC_CH1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[147]) /* 0x40012CC0 */ +#define PERI_MS_PPU_FX_DMAC_CH2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[148]) /* 0x40012D00 */ +#define PERI_MS_PPU_FX_DMAC_CH3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[149]) /* 0x40012D40 */ +#define PERI_MS_PPU_FX_EFUSE_CTL ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[150]) /* 0x40012D80 */ +#define PERI_MS_PPU_FX_EFUSE_DATA ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[151]) /* 0x40012DC0 */ +#define PERI_MS_PPU_FX_PROFILE ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[152]) /* 0x40012E00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[153]) /* 0x40012E40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[154]) /* 0x40012E80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[155]) /* 0x40012EC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[156]) /* 0x40012F00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[157]) /* 0x40012F40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[158]) /* 0x40012F80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[159]) /* 0x40012FC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[160]) /* 0x40013000 */ +#define PERI_MS_PPU_FX_HSIOM_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[161]) /* 0x40013040 */ +#define PERI_MS_PPU_FX_HSIOM_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[162]) /* 0x40013080 */ +#define PERI_MS_PPU_FX_HSIOM_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[163]) /* 0x400130C0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[164]) /* 0x40013100 */ +#define PERI_MS_PPU_FX_HSIOM_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[165]) /* 0x40013140 */ +#define PERI_MS_PPU_FX_HSIOM_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[166]) /* 0x40013180 */ +#define PERI_MS_PPU_FX_HSIOM_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[167]) /* 0x400131C0 */ +#define PERI_MS_PPU_FX_HSIOM_AMUX ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[168]) /* 0x40013200 */ +#define PERI_MS_PPU_FX_HSIOM_MON ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[169]) /* 0x40013240 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[170]) /* 0x40013280 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[171]) /* 0x400132C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[172]) /* 0x40013300 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[173]) /* 0x40013340 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[174]) /* 0x40013380 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[175]) /* 0x400133C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[176]) /* 0x40013400 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[177]) /* 0x40013440 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[178]) /* 0x40013480 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[179]) /* 0x400134C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[180]) /* 0x40013500 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[181]) /* 0x40013540 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[182]) /* 0x40013580 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[183]) /* 0x400135C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[184]) /* 0x40013600 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[185]) /* 0x40013640 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[186]) /* 0x40013680 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[187]) /* 0x400136C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[188]) /* 0x40013700 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[189]) /* 0x40013740 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[190]) /* 0x40013780 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[191]) /* 0x400137C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[192]) /* 0x40013800 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[193]) /* 0x40013840 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[194]) /* 0x40013880 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[195]) /* 0x400138C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[196]) /* 0x40013900 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[197]) /* 0x40013940 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[198]) /* 0x40013980 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[199]) /* 0x400139C0 */ +#define PERI_MS_PPU_FX_GPIO_GPIO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[200]) /* 0x40013A00 */ +#define PERI_MS_PPU_FX_GPIO_TEST ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[201]) /* 0x40013A40 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[202]) /* 0x40013A80 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[203]) /* 0x40013AC0 */ +#define PERI_MS_PPU_FX_LPCOMP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[204]) /* 0x40013B00 */ +#define PERI_MS_PPU_FX_CSD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[205]) /* 0x40013B40 */ +#define PERI_MS_PPU_FX_TCPWM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[206]) /* 0x40013B80 */ +#define PERI_MS_PPU_FX_TCPWM1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[207]) /* 0x40013BC0 */ +#define PERI_MS_PPU_FX_LCD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[208]) /* 0x40013C00 */ +#define PERI_MS_PPU_FX_USBFS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[209]) /* 0x40013C40 */ +#define PERI_MS_PPU_FX_SMIF0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[210]) /* 0x40013C80 */ +#define PERI_MS_PPU_FX_SDHC0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[211]) /* 0x40013CC0 */ +#define PERI_MS_PPU_FX_SDHC1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[212]) /* 0x40013D00 */ +#define PERI_MS_PPU_FX_SCB0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[213]) /* 0x40013D40 */ +#define PERI_MS_PPU_FX_SCB1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[214]) /* 0x40013D80 */ +#define PERI_MS_PPU_FX_SCB2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[215]) /* 0x40013DC0 */ +#define PERI_MS_PPU_FX_SCB3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[216]) /* 0x40013E00 */ +#define PERI_MS_PPU_FX_SCB4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[217]) /* 0x40013E40 */ +#define PERI_MS_PPU_FX_SCB5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[218]) /* 0x40013E80 */ +#define PERI_MS_PPU_FX_SCB6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[219]) /* 0x40013EC0 */ +#define PERI_MS_PPU_FX_SCB7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[220]) /* 0x40013F00 */ +#define PERI_MS_PPU_FX_SCB8 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[221]) /* 0x40013F40 */ +#define PERI_MS_PPU_FX_SCB9 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[222]) /* 0x40013F80 */ +#define PERI_MS_PPU_FX_SCB10 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[223]) /* 0x40013FC0 */ +#define PERI_MS_PPU_FX_SCB11 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[224]) /* 0x40014000 */ +#define PERI_MS_PPU_FX_SCB12 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[225]) /* 0x40014040 */ +#define PERI_MS_PPU_FX_PDM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[226]) /* 0x40014080 */ +#define PERI_MS_PPU_FX_I2S0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[227]) /* 0x400140C0 */ +#define PERI_MS_PPU_FX_I2S1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[228]) /* 0x40014100 */ + +/******************************************************************************* +* CPUSS +*******************************************************************************/ + +#define CPUSS_BASE 0x40200000UL +#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40200000 */ + +/******************************************************************************* +* FAULT +*******************************************************************************/ + +#define FAULT_BASE 0x40210000UL +#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40210000 */ +#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40210000 */ +#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40210100 */ + +/******************************************************************************* +* IPC +*******************************************************************************/ + +#define IPC_BASE 0x40220000UL +#define IPC ((IPC_Type*) IPC_BASE) /* 0x40220000 */ +#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40220000 */ +#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40220020 */ +#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40220040 */ +#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40220060 */ +#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40220080 */ +#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402200A0 */ +#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402200C0 */ +#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402200E0 */ +#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40220100 */ +#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40220120 */ +#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40220140 */ +#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40220160 */ +#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40220180 */ +#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402201A0 */ +#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402201C0 */ +#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402201E0 */ +#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40221000 */ +#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40221020 */ +#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40221040 */ +#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40221060 */ +#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40221080 */ +#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402210A0 */ +#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402210C0 */ +#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402210E0 */ +#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40221100 */ +#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40221120 */ +#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40221140 */ +#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40221160 */ +#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40221180 */ +#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402211A0 */ +#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402211C0 */ +#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402211E0 */ + +/******************************************************************************* +* PROT +*******************************************************************************/ + +#define PROT_BASE 0x40230000UL +#define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ +#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ +#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ +#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402320C0 */ +#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40232100 */ +#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40232140 */ +#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40232180 */ +#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402321C0 */ +#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40232200 */ +#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40232240 */ +#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40232280 */ +#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402322C0 */ +#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40232300 */ +#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ +#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ +#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ +#define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ +#define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ +#define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ +#define PROT_MPU5_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[3]) /* 0x40235660 */ +#define PROT_MPU5_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[4]) /* 0x40235680 */ +#define PROT_MPU5_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[5]) /* 0x402356A0 */ +#define PROT_MPU5_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[6]) /* 0x402356C0 */ +#define PROT_MPU5_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[7]) /* 0x402356E0 */ +#define PROT_MPU6_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[0]) /* 0x40235A00 */ +#define PROT_MPU6_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[1]) /* 0x40235A20 */ +#define PROT_MPU6_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[2]) /* 0x40235A40 */ +#define PROT_MPU6_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[3]) /* 0x40235A60 */ +#define PROT_MPU6_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[4]) /* 0x40235A80 */ +#define PROT_MPU6_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[5]) /* 0x40235AA0 */ +#define PROT_MPU6_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[6]) /* 0x40235AC0 */ +#define PROT_MPU6_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[7]) /* 0x40235AE0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ + +/******************************************************************************* +* FLASHC +*******************************************************************************/ + +#define FLASHC_BASE 0x40240000UL +#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40240000 */ +#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4024F000 */ + +/******************************************************************************* +* SRSS +*******************************************************************************/ + +#define SRSS_BASE 0x40260000UL +#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ +#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */ +#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */ + +/******************************************************************************* +* BACKUP +*******************************************************************************/ + +#define BACKUP_BASE 0x40270000UL +#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ + +/******************************************************************************* +* DW +*******************************************************************************/ + +#define DW0_BASE 0x40280000UL +#define DW1_BASE 0x40290000UL +#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ +#define DW1 ((DW_Type*) DW1_BASE) /* 0x40290000 */ +#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40288000 */ +#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40288040 */ +#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40288080 */ +#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x402880C0 */ +#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40288100 */ +#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x40288140 */ +#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x40288180 */ +#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402881C0 */ +#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40288200 */ +#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40288240 */ +#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40288280 */ +#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x402882C0 */ +#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40288300 */ +#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x40288340 */ +#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x40288380 */ +#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402883C0 */ +#define DW0_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[16]) /* 0x40288400 */ +#define DW0_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[17]) /* 0x40288440 */ +#define DW0_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[18]) /* 0x40288480 */ +#define DW0_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[19]) /* 0x402884C0 */ +#define DW0_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[20]) /* 0x40288500 */ +#define DW0_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[21]) /* 0x40288540 */ +#define DW0_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[22]) /* 0x40288580 */ +#define DW0_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[23]) /* 0x402885C0 */ +#define DW0_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[24]) /* 0x40288600 */ +#define DW0_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[25]) /* 0x40288640 */ +#define DW0_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[26]) /* 0x40288680 */ +#define DW0_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[27]) /* 0x402886C0 */ +#define DW0_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[28]) /* 0x40288700 */ +#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40298000 */ +#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40298040 */ +#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40298080 */ +#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x402980C0 */ +#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40298100 */ +#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x40298140 */ +#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x40298180 */ +#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402981C0 */ +#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40298200 */ +#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40298240 */ +#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40298280 */ +#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x402982C0 */ +#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40298300 */ +#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x40298340 */ +#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x40298380 */ +#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402983C0 */ +#define DW1_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[16]) /* 0x40298400 */ +#define DW1_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[17]) /* 0x40298440 */ +#define DW1_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[18]) /* 0x40298480 */ +#define DW1_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[19]) /* 0x402984C0 */ +#define DW1_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[20]) /* 0x40298500 */ +#define DW1_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[21]) /* 0x40298540 */ +#define DW1_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[22]) /* 0x40298580 */ +#define DW1_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[23]) /* 0x402985C0 */ +#define DW1_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[24]) /* 0x40298600 */ +#define DW1_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[25]) /* 0x40298640 */ +#define DW1_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[26]) /* 0x40298680 */ +#define DW1_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[27]) /* 0x402986C0 */ +#define DW1_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[28]) /* 0x40298700 */ + +/******************************************************************************* +* DMAC +*******************************************************************************/ + +#define DMAC_BASE 0x402A0000UL +#define DMAC ((DMAC_Type*) DMAC_BASE) /* 0x402A0000 */ +#define DMAC_CH0 ((DMAC_CH_Type*) &DMAC->CH[0]) /* 0x402A1000 */ +#define DMAC_CH1 ((DMAC_CH_Type*) &DMAC->CH[1]) /* 0x402A1100 */ +#define DMAC_CH2 ((DMAC_CH_Type*) &DMAC->CH[2]) /* 0x402A1200 */ +#define DMAC_CH3 ((DMAC_CH_Type*) &DMAC->CH[3]) /* 0x402A1300 */ + +/******************************************************************************* +* EFUSE +*******************************************************************************/ + +#define EFUSE_BASE 0x402C0000UL +#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ + +/******************************************************************************* +* PROFILE +*******************************************************************************/ + +#define PROFILE_BASE 0x402D0000UL +#define PROFILE ((PROFILE_Type*) PROFILE_BASE) /* 0x402D0000 */ +#define PROFILE_CNT_STRUCT0 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[0]) /* 0x402D0800 */ +#define PROFILE_CNT_STRUCT1 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[1]) /* 0x402D0810 */ +#define PROFILE_CNT_STRUCT2 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[2]) /* 0x402D0820 */ +#define PROFILE_CNT_STRUCT3 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[3]) /* 0x402D0830 */ +#define PROFILE_CNT_STRUCT4 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[4]) /* 0x402D0840 */ +#define PROFILE_CNT_STRUCT5 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[5]) /* 0x402D0850 */ +#define PROFILE_CNT_STRUCT6 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[6]) /* 0x402D0860 */ +#define PROFILE_CNT_STRUCT7 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[7]) /* 0x402D0870 */ + +/******************************************************************************* +* HSIOM +*******************************************************************************/ + +#define HSIOM_BASE 0x40300000UL +#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40300000 */ +#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40300000 */ +#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40300010 */ +#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40300020 */ +#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40300030 */ +#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40300040 */ +#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40300050 */ +#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40300060 */ +#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40300070 */ +#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40300080 */ +#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40300090 */ +#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403000A0 */ +#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403000B0 */ +#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403000C0 */ +#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403000D0 */ +#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403000E0 */ + +/******************************************************************************* +* GPIO +*******************************************************************************/ + +#define GPIO_BASE 0x40310000UL +#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40310000 */ +#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40310000 */ +#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40310080 */ +#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40310100 */ +#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40310180 */ +#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40310200 */ +#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40310280 */ +#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40310300 */ +#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40310380 */ +#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40310400 */ +#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40310480 */ +#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40310500 */ +#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40310580 */ +#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40310600 */ +#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40310680 */ +#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40310700 */ + +/******************************************************************************* +* SMARTIO +*******************************************************************************/ + +#define SMARTIO_BASE 0x40320000UL +#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40320000 */ +#define SMARTIO_PRT8 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[8]) /* 0x40320800 */ +#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40320900 */ + +/******************************************************************************* +* LPCOMP +*******************************************************************************/ + +#define LPCOMP_BASE 0x40350000UL +#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */ + +/******************************************************************************* +* CSD +*******************************************************************************/ + +#define CSD0_BASE 0x40360000UL +#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */ + +/******************************************************************************* +* TCPWM +*******************************************************************************/ + +#define TCPWM0_BASE 0x40380000UL +#define TCPWM1_BASE 0x40390000UL +#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM1 ((TCPWM_Type*) TCPWM1_BASE) /* 0x40390000 */ +#define TCPWM0_CNT0 ((TCPWM_CNT_Type*) &TCPWM0->CNT[0]) /* 0x40380100 */ +#define TCPWM0_CNT1 ((TCPWM_CNT_Type*) &TCPWM0->CNT[1]) /* 0x40380140 */ +#define TCPWM0_CNT2 ((TCPWM_CNT_Type*) &TCPWM0->CNT[2]) /* 0x40380180 */ +#define TCPWM0_CNT3 ((TCPWM_CNT_Type*) &TCPWM0->CNT[3]) /* 0x403801C0 */ +#define TCPWM0_CNT4 ((TCPWM_CNT_Type*) &TCPWM0->CNT[4]) /* 0x40380200 */ +#define TCPWM0_CNT5 ((TCPWM_CNT_Type*) &TCPWM0->CNT[5]) /* 0x40380240 */ +#define TCPWM0_CNT6 ((TCPWM_CNT_Type*) &TCPWM0->CNT[6]) /* 0x40380280 */ +#define TCPWM0_CNT7 ((TCPWM_CNT_Type*) &TCPWM0->CNT[7]) /* 0x403802C0 */ +#define TCPWM1_CNT0 ((TCPWM_CNT_Type*) &TCPWM1->CNT[0]) /* 0x40390100 */ +#define TCPWM1_CNT1 ((TCPWM_CNT_Type*) &TCPWM1->CNT[1]) /* 0x40390140 */ +#define TCPWM1_CNT2 ((TCPWM_CNT_Type*) &TCPWM1->CNT[2]) /* 0x40390180 */ +#define TCPWM1_CNT3 ((TCPWM_CNT_Type*) &TCPWM1->CNT[3]) /* 0x403901C0 */ +#define TCPWM1_CNT4 ((TCPWM_CNT_Type*) &TCPWM1->CNT[4]) /* 0x40390200 */ +#define TCPWM1_CNT5 ((TCPWM_CNT_Type*) &TCPWM1->CNT[5]) /* 0x40390240 */ +#define TCPWM1_CNT6 ((TCPWM_CNT_Type*) &TCPWM1->CNT[6]) /* 0x40390280 */ +#define TCPWM1_CNT7 ((TCPWM_CNT_Type*) &TCPWM1->CNT[7]) /* 0x403902C0 */ +#define TCPWM1_CNT8 ((TCPWM_CNT_Type*) &TCPWM1->CNT[8]) /* 0x40390300 */ +#define TCPWM1_CNT9 ((TCPWM_CNT_Type*) &TCPWM1->CNT[9]) /* 0x40390340 */ +#define TCPWM1_CNT10 ((TCPWM_CNT_Type*) &TCPWM1->CNT[10]) /* 0x40390380 */ +#define TCPWM1_CNT11 ((TCPWM_CNT_Type*) &TCPWM1->CNT[11]) /* 0x403903C0 */ +#define TCPWM1_CNT12 ((TCPWM_CNT_Type*) &TCPWM1->CNT[12]) /* 0x40390400 */ +#define TCPWM1_CNT13 ((TCPWM_CNT_Type*) &TCPWM1->CNT[13]) /* 0x40390440 */ +#define TCPWM1_CNT14 ((TCPWM_CNT_Type*) &TCPWM1->CNT[14]) /* 0x40390480 */ +#define TCPWM1_CNT15 ((TCPWM_CNT_Type*) &TCPWM1->CNT[15]) /* 0x403904C0 */ +#define TCPWM1_CNT16 ((TCPWM_CNT_Type*) &TCPWM1->CNT[16]) /* 0x40390500 */ +#define TCPWM1_CNT17 ((TCPWM_CNT_Type*) &TCPWM1->CNT[17]) /* 0x40390540 */ +#define TCPWM1_CNT18 ((TCPWM_CNT_Type*) &TCPWM1->CNT[18]) /* 0x40390580 */ +#define TCPWM1_CNT19 ((TCPWM_CNT_Type*) &TCPWM1->CNT[19]) /* 0x403905C0 */ +#define TCPWM1_CNT20 ((TCPWM_CNT_Type*) &TCPWM1->CNT[20]) /* 0x40390600 */ +#define TCPWM1_CNT21 ((TCPWM_CNT_Type*) &TCPWM1->CNT[21]) /* 0x40390640 */ +#define TCPWM1_CNT22 ((TCPWM_CNT_Type*) &TCPWM1->CNT[22]) /* 0x40390680 */ +#define TCPWM1_CNT23 ((TCPWM_CNT_Type*) &TCPWM1->CNT[23]) /* 0x403906C0 */ + +/******************************************************************************* +* LCD +*******************************************************************************/ + +#define LCD0_BASE 0x403B0000UL +#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ + +/******************************************************************************* +* USBFS +*******************************************************************************/ + +#define USBFS0_BASE 0x403F0000UL +#define USBFS0 ((USBFS_Type*) USBFS0_BASE) /* 0x403F0000 */ +#define USBFS0_USBDEV ((USBFS_USBDEV_Type*) &USBFS0->USBDEV) /* 0x403F0000 */ +#define USBFS0_USBLPM ((USBFS_USBLPM_Type*) &USBFS0->USBLPM) /* 0x403F2000 */ +#define USBFS0_USBHOST ((USBFS_USBHOST_Type*) &USBFS0->USBHOST) /* 0x403F4000 */ + +/******************************************************************************* +* SMIF +*******************************************************************************/ + +#define SMIF0_BASE 0x40420000UL +#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ +#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ +#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ +#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ +#define SMIF0_DEVICE3 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[3]) /* 0x40420980 */ + +/******************************************************************************* +* SDHC +*******************************************************************************/ + +#define SDHC0_BASE 0x40460000UL +#define SDHC1_BASE 0x40470000UL +#define SDHC0 ((SDHC_Type*) SDHC0_BASE) /* 0x40460000 */ +#define SDHC1 ((SDHC_Type*) SDHC1_BASE) /* 0x40470000 */ +#define SDHC0_WRAP ((SDHC_WRAP_Type*) &SDHC0->WRAP) /* 0x40460000 */ +#define SDHC1_WRAP ((SDHC_WRAP_Type*) &SDHC1->WRAP) /* 0x40470000 */ +#define SDHC0_CORE ((SDHC_CORE_Type*) &SDHC0->CORE) /* 0x40461000 */ +#define SDHC1_CORE ((SDHC_CORE_Type*) &SDHC1->CORE) /* 0x40471000 */ + +/******************************************************************************* +* SCB +*******************************************************************************/ + +#define SCB0_BASE 0x40600000UL +#define SCB1_BASE 0x40610000UL +#define SCB2_BASE 0x40620000UL +#define SCB3_BASE 0x40630000UL +#define SCB4_BASE 0x40640000UL +#define SCB5_BASE 0x40650000UL +#define SCB6_BASE 0x40660000UL +#define SCB7_BASE 0x40670000UL +#define SCB8_BASE 0x40680000UL +#define SCB9_BASE 0x40690000UL +#define SCB10_BASE 0x406A0000UL +#define SCB11_BASE 0x406B0000UL +#define SCB12_BASE 0x406C0000UL +#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40600000 */ +#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40610000 */ +#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40620000 */ +#define SCB3 ((CySCB_Type*) SCB3_BASE) /* 0x40630000 */ +#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40640000 */ +#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40650000 */ +#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40660000 */ +#define SCB7 ((CySCB_Type*) SCB7_BASE) /* 0x40670000 */ +#define SCB8 ((CySCB_Type*) SCB8_BASE) /* 0x40680000 */ +#define SCB9 ((CySCB_Type*) SCB9_BASE) /* 0x40690000 */ +#define SCB10 ((CySCB_Type*) SCB10_BASE) /* 0x406A0000 */ +#define SCB11 ((CySCB_Type*) SCB11_BASE) /* 0x406B0000 */ +#define SCB12 ((CySCB_Type*) SCB12_BASE) /* 0x406C0000 */ + +/******************************************************************************* +* SAR +*******************************************************************************/ + +#define SAR_BASE 0x409D0000UL +#define SAR ((SAR_Type*) SAR_BASE) /* 0x409D0000 */ + +/******************************************************************************* +* PASS +*******************************************************************************/ + +#define PASS_BASE 0x409F0000UL +#define PASS ((PASS_Type*) PASS_BASE) /* 0x409F0000 */ +#define PASS_AREF ((PASS_AREF_Type*) &PASS->AREF) /* 0x409F0E00 */ + +/******************************************************************************* +* PDM +*******************************************************************************/ + +#define PDM0_BASE 0x40A00000UL +#define PDM0 ((PDM_Type*) PDM0_BASE) /* 0x40A00000 */ + +/******************************************************************************* +* I2S +*******************************************************************************/ + +#define I2S0_BASE 0x40A10000UL +#define I2S1_BASE 0x40A11000UL +#define I2S0 ((I2S_Type*) I2S0_BASE) /* 0x40A10000 */ +#define I2S1 ((I2S_Type*) I2S1_BASE) /* 0x40A11000 */ + +/** \} CY8C614AAZI-S2F04 */ + +#endif /* _CY8C614AAZI_S2F04_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c614aazi_s2f14.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c614aazi_s2f14.h new file mode 100644 index 0000000000..47ad77bb21 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c614aazi_s2f14.h @@ -0,0 +1,1088 @@ +/***************************************************************************//** +* \file cy8c614aazi_s2f14.h +* +* \brief +* CY8C614AAZI-S2F14 device header +* +* \note +* Generator version: 1.6.0.225 +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CY8C614AAZI_S2F14_H_ +#define _CY8C614AAZI_S2F14_H_ + +/** +* \addtogroup group_device CY8C614AAZI-S2F14 +* \{ +*/ + +/** +* \addtogroup Configuration_of_CMSIS +* \{ +*/ + +/******************************************************************************* +* Interrupt Number Definition +*******************************************************************************/ + +typedef enum { + /* ARM Cortex-M4 Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C614AAZI-S2F14 Peripheral Interrupt Numbers */ + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_1_IRQn = 1, /*!< 1 [DeepSleep] GPIO Port Interrupt #1 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_4_IRQn = 4, /*!< 4 [DeepSleep] GPIO Port Interrupt #4 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_13_IRQn = 13, /*!< 13 [DeepSleep] GPIO Port Interrupt #13 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_8_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #8 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + scb_6_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #6 */ + scb_7_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #7 */ + scb_9_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #9 */ + scb_10_interrupt_IRQn = 48, /*!< 48 [Active] Serial Communication Block #10 */ + scb_11_interrupt_IRQn = 49, /*!< 49 [Active] Serial Communication Block #11 */ + scb_12_interrupt_IRQn = 50, /*!< 50 [Active] Serial Communication Block #12 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dmac_2_IRQn = 54, /*!< 54 [Active] CPUSS DMAC, Channel #2 */ + cpuss_interrupts_dmac_3_IRQn = 55, /*!< 55 [Active] CPUSS DMAC, Channel #3 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_0_interrupts_4_IRQn = 127, /*!< 127 [Active] TCPWM #0, Counter #4 */ + tcpwm_0_interrupts_5_IRQn = 128, /*!< 128 [Active] TCPWM #0, Counter #5 */ + tcpwm_0_interrupts_6_IRQn = 129, /*!< 129 [Active] TCPWM #0, Counter #6 */ + tcpwm_0_interrupts_7_IRQn = 130, /*!< 130 [Active] TCPWM #0, Counter #7 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + tcpwm_1_interrupts_8_IRQn = 139, /*!< 139 [Active] TCPWM #1, Counter #8 */ + tcpwm_1_interrupts_9_IRQn = 140, /*!< 140 [Active] TCPWM #1, Counter #9 */ + tcpwm_1_interrupts_10_IRQn = 141, /*!< 141 [Active] TCPWM #1, Counter #10 */ + tcpwm_1_interrupts_11_IRQn = 142, /*!< 142 [Active] TCPWM #1, Counter #11 */ + tcpwm_1_interrupts_12_IRQn = 143, /*!< 143 [Active] TCPWM #1, Counter #12 */ + tcpwm_1_interrupts_13_IRQn = 144, /*!< 144 [Active] TCPWM #1, Counter #13 */ + tcpwm_1_interrupts_14_IRQn = 145, /*!< 145 [Active] TCPWM #1, Counter #14 */ + tcpwm_1_interrupts_15_IRQn = 146, /*!< 146 [Active] TCPWM #1, Counter #15 */ + tcpwm_1_interrupts_16_IRQn = 147, /*!< 147 [Active] TCPWM #1, Counter #16 */ + tcpwm_1_interrupts_17_IRQn = 148, /*!< 148 [Active] TCPWM #1, Counter #17 */ + tcpwm_1_interrupts_18_IRQn = 149, /*!< 149 [Active] TCPWM #1, Counter #18 */ + tcpwm_1_interrupts_19_IRQn = 150, /*!< 150 [Active] TCPWM #1, Counter #19 */ + tcpwm_1_interrupts_20_IRQn = 151, /*!< 151 [Active] TCPWM #1, Counter #20 */ + tcpwm_1_interrupts_21_IRQn = 152, /*!< 152 [Active] TCPWM #1, Counter #21 */ + tcpwm_1_interrupts_22_IRQn = 153, /*!< 153 [Active] TCPWM #1, Counter #22 */ + tcpwm_1_interrupts_23_IRQn = 154, /*!< 154 [Active] TCPWM #1, Counter #23 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + audioss_0_interrupt_i2s_IRQn = 156, /*!< 156 [Active] I2S0 Audio interrupt */ + audioss_0_interrupt_pdm_IRQn = 157, /*!< 157 [Active] PDM0/PCM0 Audio interrupt */ + audioss_1_interrupt_i2s_IRQn = 158, /*!< 158 [Active] I2S1 Audio interrupt */ + profile_interrupt_IRQn = 159, /*!< 159 [Active] Energy Profiler interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + sdhc_1_interrupt_wakeup_IRQn = 166, /*!< 166 [Active] EEMC wakeup interrupt for mxsdhc, not used */ + sdhc_1_interrupt_general_IRQn = 167, /*!< 167 [Active] Consolidated interrupt for mxsdhc for everything else */ + unconnected_IRQn = 240 /*!< 240 Unconnected */ +} IRQn_Type; + + +/******************************************************************************* +* Processor and Core Peripheral Section +*******************************************************************************/ + +/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __CM0P_PRESENT 0 /*!< CM0P present or not */ +#define __DTCM_PRESENT 0 /*!< DTCM present or not */ +#define __ICACHE_PRESENT 0 /*!< ICACHE present or not */ +#define __DCACHE_PRESENT 0 /*!< DCACHE present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + + +/* Memory Blocks */ +#define CY_ROM_BASE 0x00000000UL +#define CY_ROM_SIZE 0x00010000UL +#define CY_SRAM_BASE 0x08000000UL +#define CY_SRAM_SIZE 0x00100000UL +#define CY_FLASH_BASE 0x10000000UL +#define CY_FLASH_SIZE 0x00200000UL +#define CY_EM_EEPROM_BASE 0x14000000UL +#define CY_EM_EEPROM_SIZE 0x00008000UL +#define CY_SFLASH_BASE 0x16000000UL +#define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL +#define CY_EFUSE_BASE 0x402C0800UL +#define CY_EFUSE_SIZE 0x00000200UL + +#include "system_psoc6.h" /*!< PSoC 6 System */ + +/* IP List */ +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 2u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_M4CPUSS 1u +#define CY_IP_M4CPUSS_INSTANCES 1u +#define CY_IP_M4CPUSS_VERSION 2u +#define CY_IP_M4CPUSS_DMAC 1u +#define CY_IP_M4CPUSS_DMAC_INSTANCES 1u +#define CY_IP_M4CPUSS_DMAC_VERSION 2u +#define CY_IP_M4CPUSS_DMA 1u +#define CY_IP_M4CPUSS_DMA_INSTANCES 2u +#define CY_IP_M4CPUSS_DMA_VERSION 2u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u +#define CY_IP_MXS40PASS 1u +#define CY_IP_MXS40PASS_INSTANCES 1u +#define CY_IP_MXS40PASS_VERSION 1u +#define CY_IP_MXS40PASS_SAR 1u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u +#define CY_IP_MXS40PASS_SAR_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXPROFILE 1u +#define CY_IP_MXPROFILE_INSTANCES 1u +#define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 13u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 2u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u + +#include "psoc6_02_config.h" +#include "gpio_psoc6_02_128_tqfp.h" + +#define CY_DEVICE_PSOC6A2M +#define CY_SILICON_ID 0xE45D1202UL +#define CY_HF_CLK_MAX_FREQ 150000000UL + +#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL + +/******************************************************************************* +* SFLASH +*******************************************************************************/ + +#define SFLASH_BASE 0x16000000UL +#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */ + +/******************************************************************************* +* PERI +*******************************************************************************/ + +#define PERI_BASE 0x40000000UL +#define PERI ((PERI_Type*) PERI_BASE) /* 0x40000000 */ +#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40004000 */ +#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40004020 */ +#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40004040 */ +#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x40004060 */ +#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40004080 */ +#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x400040C0 */ +#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40004120 */ +#define PERI_GR10 ((PERI_GR_Type*) &PERI->GR[10]) /* 0x40004140 */ +#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40008000 */ +#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40008400 */ +#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40008800 */ +#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40008C00 */ +#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40009000 */ +#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40009400 */ +#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40009800 */ +#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40009C00 */ +#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ +#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ +#define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ +#define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ +#define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ +#define PERI_TR_1TO1_GR3 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[3]) /* 0x4000CC00 */ +#define PERI_TR_1TO1_GR4 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[4]) /* 0x4000D000 */ +#define PERI_TR_1TO1_GR5 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[5]) /* 0x4000D400 */ +#define PERI_TR_1TO1_GR6 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[6]) /* 0x4000D800 */ + +/******************************************************************************* +* PERI_MS +*******************************************************************************/ + +#define PERI_MS_BASE 0x40010000UL +#define PERI_MS ((PERI_MS_Type*) PERI_MS_BASE) /* 0x40010000 */ +#define PERI_MS_PPU_PR0 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[0]) /* 0x40010000 */ +#define PERI_MS_PPU_PR1 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[1]) /* 0x40010040 */ +#define PERI_MS_PPU_PR2 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[2]) /* 0x40010080 */ +#define PERI_MS_PPU_PR3 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[3]) /* 0x400100C0 */ +#define PERI_MS_PPU_PR4 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[4]) /* 0x40010100 */ +#define PERI_MS_PPU_PR5 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[5]) /* 0x40010140 */ +#define PERI_MS_PPU_PR6 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[6]) /* 0x40010180 */ +#define PERI_MS_PPU_PR7 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[7]) /* 0x400101C0 */ +#define PERI_MS_PPU_FX_PERI_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[0]) /* 0x40010800 */ +#define PERI_MS_PPU_FX_PERI_GR0_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[1]) /* 0x40010840 */ +#define PERI_MS_PPU_FX_PERI_GR1_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[2]) /* 0x40010880 */ +#define PERI_MS_PPU_FX_PERI_GR2_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[3]) /* 0x400108C0 */ +#define PERI_MS_PPU_FX_PERI_GR3_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[4]) /* 0x40010900 */ +#define PERI_MS_PPU_FX_PERI_GR4_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[5]) /* 0x40010940 */ +#define PERI_MS_PPU_FX_PERI_GR6_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[6]) /* 0x40010980 */ +#define PERI_MS_PPU_FX_PERI_GR9_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[7]) /* 0x400109C0 */ +#define PERI_MS_PPU_FX_PERI_GR10_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[8]) /* 0x40010A00 */ +#define PERI_MS_PPU_FX_PERI_TR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[9]) /* 0x40010A40 */ +#define PERI_MS_PPU_FX_CRYPTO_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[10]) /* 0x40010A80 */ +#define PERI_MS_PPU_FX_CRYPTO_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[11]) /* 0x40010AC0 */ +#define PERI_MS_PPU_FX_CRYPTO_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[12]) /* 0x40010B00 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[13]) /* 0x40010B40 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[14]) /* 0x40010B80 */ +#define PERI_MS_PPU_FX_CRYPTO_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[15]) /* 0x40010BC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[16]) /* 0x40010C00 */ +#define PERI_MS_PPU_FX_CPUSS_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[17]) /* 0x40010C40 */ +#define PERI_MS_PPU_FX_CPUSS_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[18]) /* 0x40010C80 */ +#define PERI_MS_PPU_FX_CPUSS_CM0_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[19]) /* 0x40010CC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[20]) /* 0x40010D00 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[21]) /* 0x40010D40 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT1_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[22]) /* 0x40010D80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT0_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[23]) /* 0x40010DC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT1_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[24]) /* 0x40010E00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT2_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[25]) /* 0x40010E40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT3_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[26]) /* 0x40010E80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT4_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[27]) /* 0x40010EC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT5_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[28]) /* 0x40010F00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT6_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[29]) /* 0x40010F40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT7_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[30]) /* 0x40010F80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT8_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[31]) /* 0x40010FC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT9_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[32]) /* 0x40011000 */ +#define PERI_MS_PPU_FX_IPC_STRUCT10_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[33]) /* 0x40011040 */ +#define PERI_MS_PPU_FX_IPC_STRUCT11_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[34]) /* 0x40011080 */ +#define PERI_MS_PPU_FX_IPC_STRUCT12_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[35]) /* 0x400110C0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT13_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[36]) /* 0x40011100 */ +#define PERI_MS_PPU_FX_IPC_STRUCT14_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[37]) /* 0x40011140 */ +#define PERI_MS_PPU_FX_IPC_STRUCT15_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[38]) /* 0x40011180 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT0_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[39]) /* 0x400111C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT1_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[40]) /* 0x40011200 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT2_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[41]) /* 0x40011240 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT3_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[42]) /* 0x40011280 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT4_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[43]) /* 0x400112C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT5_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[44]) /* 0x40011300 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT6_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[45]) /* 0x40011340 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT7_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[46]) /* 0x40011380 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT8_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[47]) /* 0x400113C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT9_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[48]) /* 0x40011400 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT10_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[49]) /* 0x40011440 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT11_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[50]) /* 0x40011480 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT12_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[51]) /* 0x400114C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT13_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[52]) /* 0x40011500 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT14_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[53]) /* 0x40011540 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT15_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[54]) /* 0x40011580 */ +#define PERI_MS_PPU_FX_PROT_SMPU_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[55]) /* 0x400115C0 */ +#define PERI_MS_PPU_FX_PROT_MPU0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[56]) /* 0x40011600 */ +#define PERI_MS_PPU_FX_PROT_MPU5_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[57]) /* 0x40011640 */ +#define PERI_MS_PPU_FX_PROT_MPU6_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[58]) /* 0x40011680 */ +#define PERI_MS_PPU_FX_PROT_MPU14_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[59]) /* 0x400116C0 */ +#define PERI_MS_PPU_FX_PROT_MPU15_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[60]) /* 0x40011700 */ +#define PERI_MS_PPU_FX_FLASHC_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[61]) /* 0x40011740 */ +#define PERI_MS_PPU_FX_FLASHC_CMD ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[62]) /* 0x40011780 */ +#define PERI_MS_PPU_FX_FLASHC_DFT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[63]) /* 0x400117C0 */ +#define PERI_MS_PPU_FX_FLASHC_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[64]) /* 0x40011800 */ +#define PERI_MS_PPU_FX_FLASHC_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[65]) /* 0x40011840 */ +#define PERI_MS_PPU_FX_FLASHC_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[66]) /* 0x40011880 */ +#define PERI_MS_PPU_FX_FLASHC_DW0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[67]) /* 0x400118C0 */ +#define PERI_MS_PPU_FX_FLASHC_DW1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[68]) /* 0x40011900 */ +#define PERI_MS_PPU_FX_FLASHC_DMAC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[69]) /* 0x40011940 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[70]) /* 0x40011980 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[71]) /* 0x400119C0 */ +#define PERI_MS_PPU_FX_FLASHC_FM ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[72]) /* 0x40011A00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[73]) /* 0x40011A40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[74]) /* 0x40011A80 */ +#define PERI_MS_PPU_FX_WDT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[75]) /* 0x40011AC0 */ +#define PERI_MS_PPU_FX_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[76]) /* 0x40011B00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[77]) /* 0x40011B40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[78]) /* 0x40011B80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[79]) /* 0x40011BC0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[80]) /* 0x40011C00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[81]) /* 0x40011C40 */ +#define PERI_MS_PPU_FX_BACKUP_BACKUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[82]) /* 0x40011C80 */ +#define PERI_MS_PPU_FX_DW0_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[83]) /* 0x40011CC0 */ +#define PERI_MS_PPU_FX_DW1_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[84]) /* 0x40011D00 */ +#define PERI_MS_PPU_FX_DW0_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[85]) /* 0x40011D40 */ +#define PERI_MS_PPU_FX_DW1_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[86]) /* 0x40011D80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[87]) /* 0x40011DC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[88]) /* 0x40011E00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[89]) /* 0x40011E40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[90]) /* 0x40011E80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[91]) /* 0x40011EC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[92]) /* 0x40011F00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[93]) /* 0x40011F40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[94]) /* 0x40011F80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[95]) /* 0x40011FC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[96]) /* 0x40012000 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[97]) /* 0x40012040 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[98]) /* 0x40012080 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[99]) /* 0x400120C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[100]) /* 0x40012100 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[101]) /* 0x40012140 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[102]) /* 0x40012180 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[103]) /* 0x400121C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[104]) /* 0x40012200 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[105]) /* 0x40012240 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[106]) /* 0x40012280 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[107]) /* 0x400122C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[108]) /* 0x40012300 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[109]) /* 0x40012340 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[110]) /* 0x40012380 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[111]) /* 0x400123C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[112]) /* 0x40012400 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[113]) /* 0x40012440 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[114]) /* 0x40012480 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[115]) /* 0x400124C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[116]) /* 0x40012500 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[117]) /* 0x40012540 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[118]) /* 0x40012580 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[119]) /* 0x400125C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[120]) /* 0x40012600 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[121]) /* 0x40012640 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[122]) /* 0x40012680 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[123]) /* 0x400126C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[124]) /* 0x40012700 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[125]) /* 0x40012740 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[126]) /* 0x40012780 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[127]) /* 0x400127C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[128]) /* 0x40012800 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[129]) /* 0x40012840 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[130]) /* 0x40012880 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[131]) /* 0x400128C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[132]) /* 0x40012900 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[133]) /* 0x40012940 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[134]) /* 0x40012980 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[135]) /* 0x400129C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[136]) /* 0x40012A00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[137]) /* 0x40012A40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[138]) /* 0x40012A80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[139]) /* 0x40012AC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[140]) /* 0x40012B00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[141]) /* 0x40012B40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[142]) /* 0x40012B80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[143]) /* 0x40012BC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[144]) /* 0x40012C00 */ +#define PERI_MS_PPU_FX_DMAC_TOP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[145]) /* 0x40012C40 */ +#define PERI_MS_PPU_FX_DMAC_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[146]) /* 0x40012C80 */ +#define PERI_MS_PPU_FX_DMAC_CH1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[147]) /* 0x40012CC0 */ +#define PERI_MS_PPU_FX_DMAC_CH2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[148]) /* 0x40012D00 */ +#define PERI_MS_PPU_FX_DMAC_CH3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[149]) /* 0x40012D40 */ +#define PERI_MS_PPU_FX_EFUSE_CTL ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[150]) /* 0x40012D80 */ +#define PERI_MS_PPU_FX_EFUSE_DATA ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[151]) /* 0x40012DC0 */ +#define PERI_MS_PPU_FX_PROFILE ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[152]) /* 0x40012E00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[153]) /* 0x40012E40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[154]) /* 0x40012E80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[155]) /* 0x40012EC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[156]) /* 0x40012F00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[157]) /* 0x40012F40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[158]) /* 0x40012F80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[159]) /* 0x40012FC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[160]) /* 0x40013000 */ +#define PERI_MS_PPU_FX_HSIOM_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[161]) /* 0x40013040 */ +#define PERI_MS_PPU_FX_HSIOM_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[162]) /* 0x40013080 */ +#define PERI_MS_PPU_FX_HSIOM_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[163]) /* 0x400130C0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[164]) /* 0x40013100 */ +#define PERI_MS_PPU_FX_HSIOM_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[165]) /* 0x40013140 */ +#define PERI_MS_PPU_FX_HSIOM_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[166]) /* 0x40013180 */ +#define PERI_MS_PPU_FX_HSIOM_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[167]) /* 0x400131C0 */ +#define PERI_MS_PPU_FX_HSIOM_AMUX ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[168]) /* 0x40013200 */ +#define PERI_MS_PPU_FX_HSIOM_MON ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[169]) /* 0x40013240 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[170]) /* 0x40013280 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[171]) /* 0x400132C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[172]) /* 0x40013300 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[173]) /* 0x40013340 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[174]) /* 0x40013380 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[175]) /* 0x400133C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[176]) /* 0x40013400 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[177]) /* 0x40013440 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[178]) /* 0x40013480 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[179]) /* 0x400134C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[180]) /* 0x40013500 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[181]) /* 0x40013540 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[182]) /* 0x40013580 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[183]) /* 0x400135C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[184]) /* 0x40013600 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[185]) /* 0x40013640 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[186]) /* 0x40013680 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[187]) /* 0x400136C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[188]) /* 0x40013700 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[189]) /* 0x40013740 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[190]) /* 0x40013780 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[191]) /* 0x400137C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[192]) /* 0x40013800 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[193]) /* 0x40013840 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[194]) /* 0x40013880 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[195]) /* 0x400138C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[196]) /* 0x40013900 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[197]) /* 0x40013940 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[198]) /* 0x40013980 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[199]) /* 0x400139C0 */ +#define PERI_MS_PPU_FX_GPIO_GPIO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[200]) /* 0x40013A00 */ +#define PERI_MS_PPU_FX_GPIO_TEST ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[201]) /* 0x40013A40 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[202]) /* 0x40013A80 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[203]) /* 0x40013AC0 */ +#define PERI_MS_PPU_FX_LPCOMP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[204]) /* 0x40013B00 */ +#define PERI_MS_PPU_FX_CSD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[205]) /* 0x40013B40 */ +#define PERI_MS_PPU_FX_TCPWM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[206]) /* 0x40013B80 */ +#define PERI_MS_PPU_FX_TCPWM1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[207]) /* 0x40013BC0 */ +#define PERI_MS_PPU_FX_LCD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[208]) /* 0x40013C00 */ +#define PERI_MS_PPU_FX_USBFS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[209]) /* 0x40013C40 */ +#define PERI_MS_PPU_FX_SMIF0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[210]) /* 0x40013C80 */ +#define PERI_MS_PPU_FX_SDHC0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[211]) /* 0x40013CC0 */ +#define PERI_MS_PPU_FX_SDHC1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[212]) /* 0x40013D00 */ +#define PERI_MS_PPU_FX_SCB0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[213]) /* 0x40013D40 */ +#define PERI_MS_PPU_FX_SCB1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[214]) /* 0x40013D80 */ +#define PERI_MS_PPU_FX_SCB2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[215]) /* 0x40013DC0 */ +#define PERI_MS_PPU_FX_SCB3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[216]) /* 0x40013E00 */ +#define PERI_MS_PPU_FX_SCB4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[217]) /* 0x40013E40 */ +#define PERI_MS_PPU_FX_SCB5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[218]) /* 0x40013E80 */ +#define PERI_MS_PPU_FX_SCB6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[219]) /* 0x40013EC0 */ +#define PERI_MS_PPU_FX_SCB7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[220]) /* 0x40013F00 */ +#define PERI_MS_PPU_FX_SCB8 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[221]) /* 0x40013F40 */ +#define PERI_MS_PPU_FX_SCB9 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[222]) /* 0x40013F80 */ +#define PERI_MS_PPU_FX_SCB10 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[223]) /* 0x40013FC0 */ +#define PERI_MS_PPU_FX_SCB11 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[224]) /* 0x40014000 */ +#define PERI_MS_PPU_FX_SCB12 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[225]) /* 0x40014040 */ +#define PERI_MS_PPU_FX_PDM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[226]) /* 0x40014080 */ +#define PERI_MS_PPU_FX_I2S0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[227]) /* 0x400140C0 */ +#define PERI_MS_PPU_FX_I2S1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[228]) /* 0x40014100 */ + +/******************************************************************************* +* CPUSS +*******************************************************************************/ + +#define CPUSS_BASE 0x40200000UL +#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40200000 */ + +/******************************************************************************* +* FAULT +*******************************************************************************/ + +#define FAULT_BASE 0x40210000UL +#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40210000 */ +#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40210000 */ +#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40210100 */ + +/******************************************************************************* +* IPC +*******************************************************************************/ + +#define IPC_BASE 0x40220000UL +#define IPC ((IPC_Type*) IPC_BASE) /* 0x40220000 */ +#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40220000 */ +#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40220020 */ +#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40220040 */ +#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40220060 */ +#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40220080 */ +#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402200A0 */ +#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402200C0 */ +#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402200E0 */ +#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40220100 */ +#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40220120 */ +#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40220140 */ +#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40220160 */ +#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40220180 */ +#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402201A0 */ +#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402201C0 */ +#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402201E0 */ +#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40221000 */ +#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40221020 */ +#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40221040 */ +#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40221060 */ +#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40221080 */ +#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402210A0 */ +#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402210C0 */ +#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402210E0 */ +#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40221100 */ +#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40221120 */ +#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40221140 */ +#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40221160 */ +#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40221180 */ +#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402211A0 */ +#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402211C0 */ +#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402211E0 */ + +/******************************************************************************* +* PROT +*******************************************************************************/ + +#define PROT_BASE 0x40230000UL +#define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ +#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ +#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ +#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402320C0 */ +#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40232100 */ +#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40232140 */ +#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40232180 */ +#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402321C0 */ +#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40232200 */ +#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40232240 */ +#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40232280 */ +#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402322C0 */ +#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40232300 */ +#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ +#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ +#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ +#define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ +#define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ +#define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ +#define PROT_MPU5_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[3]) /* 0x40235660 */ +#define PROT_MPU5_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[4]) /* 0x40235680 */ +#define PROT_MPU5_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[5]) /* 0x402356A0 */ +#define PROT_MPU5_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[6]) /* 0x402356C0 */ +#define PROT_MPU5_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[7]) /* 0x402356E0 */ +#define PROT_MPU6_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[0]) /* 0x40235A00 */ +#define PROT_MPU6_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[1]) /* 0x40235A20 */ +#define PROT_MPU6_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[2]) /* 0x40235A40 */ +#define PROT_MPU6_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[3]) /* 0x40235A60 */ +#define PROT_MPU6_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[4]) /* 0x40235A80 */ +#define PROT_MPU6_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[5]) /* 0x40235AA0 */ +#define PROT_MPU6_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[6]) /* 0x40235AC0 */ +#define PROT_MPU6_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[7]) /* 0x40235AE0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ + +/******************************************************************************* +* FLASHC +*******************************************************************************/ + +#define FLASHC_BASE 0x40240000UL +#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40240000 */ +#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4024F000 */ + +/******************************************************************************* +* SRSS +*******************************************************************************/ + +#define SRSS_BASE 0x40260000UL +#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ +#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */ +#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */ + +/******************************************************************************* +* BACKUP +*******************************************************************************/ + +#define BACKUP_BASE 0x40270000UL +#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ + +/******************************************************************************* +* DW +*******************************************************************************/ + +#define DW0_BASE 0x40280000UL +#define DW1_BASE 0x40290000UL +#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ +#define DW1 ((DW_Type*) DW1_BASE) /* 0x40290000 */ +#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40288000 */ +#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40288040 */ +#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40288080 */ +#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x402880C0 */ +#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40288100 */ +#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x40288140 */ +#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x40288180 */ +#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402881C0 */ +#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40288200 */ +#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40288240 */ +#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40288280 */ +#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x402882C0 */ +#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40288300 */ +#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x40288340 */ +#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x40288380 */ +#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402883C0 */ +#define DW0_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[16]) /* 0x40288400 */ +#define DW0_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[17]) /* 0x40288440 */ +#define DW0_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[18]) /* 0x40288480 */ +#define DW0_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[19]) /* 0x402884C0 */ +#define DW0_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[20]) /* 0x40288500 */ +#define DW0_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[21]) /* 0x40288540 */ +#define DW0_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[22]) /* 0x40288580 */ +#define DW0_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[23]) /* 0x402885C0 */ +#define DW0_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[24]) /* 0x40288600 */ +#define DW0_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[25]) /* 0x40288640 */ +#define DW0_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[26]) /* 0x40288680 */ +#define DW0_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[27]) /* 0x402886C0 */ +#define DW0_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[28]) /* 0x40288700 */ +#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40298000 */ +#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40298040 */ +#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40298080 */ +#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x402980C0 */ +#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40298100 */ +#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x40298140 */ +#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x40298180 */ +#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402981C0 */ +#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40298200 */ +#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40298240 */ +#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40298280 */ +#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x402982C0 */ +#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40298300 */ +#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x40298340 */ +#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x40298380 */ +#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402983C0 */ +#define DW1_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[16]) /* 0x40298400 */ +#define DW1_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[17]) /* 0x40298440 */ +#define DW1_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[18]) /* 0x40298480 */ +#define DW1_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[19]) /* 0x402984C0 */ +#define DW1_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[20]) /* 0x40298500 */ +#define DW1_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[21]) /* 0x40298540 */ +#define DW1_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[22]) /* 0x40298580 */ +#define DW1_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[23]) /* 0x402985C0 */ +#define DW1_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[24]) /* 0x40298600 */ +#define DW1_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[25]) /* 0x40298640 */ +#define DW1_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[26]) /* 0x40298680 */ +#define DW1_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[27]) /* 0x402986C0 */ +#define DW1_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[28]) /* 0x40298700 */ + +/******************************************************************************* +* DMAC +*******************************************************************************/ + +#define DMAC_BASE 0x402A0000UL +#define DMAC ((DMAC_Type*) DMAC_BASE) /* 0x402A0000 */ +#define DMAC_CH0 ((DMAC_CH_Type*) &DMAC->CH[0]) /* 0x402A1000 */ +#define DMAC_CH1 ((DMAC_CH_Type*) &DMAC->CH[1]) /* 0x402A1100 */ +#define DMAC_CH2 ((DMAC_CH_Type*) &DMAC->CH[2]) /* 0x402A1200 */ +#define DMAC_CH3 ((DMAC_CH_Type*) &DMAC->CH[3]) /* 0x402A1300 */ + +/******************************************************************************* +* EFUSE +*******************************************************************************/ + +#define EFUSE_BASE 0x402C0000UL +#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ + +/******************************************************************************* +* PROFILE +*******************************************************************************/ + +#define PROFILE_BASE 0x402D0000UL +#define PROFILE ((PROFILE_Type*) PROFILE_BASE) /* 0x402D0000 */ +#define PROFILE_CNT_STRUCT0 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[0]) /* 0x402D0800 */ +#define PROFILE_CNT_STRUCT1 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[1]) /* 0x402D0810 */ +#define PROFILE_CNT_STRUCT2 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[2]) /* 0x402D0820 */ +#define PROFILE_CNT_STRUCT3 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[3]) /* 0x402D0830 */ +#define PROFILE_CNT_STRUCT4 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[4]) /* 0x402D0840 */ +#define PROFILE_CNT_STRUCT5 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[5]) /* 0x402D0850 */ +#define PROFILE_CNT_STRUCT6 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[6]) /* 0x402D0860 */ +#define PROFILE_CNT_STRUCT7 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[7]) /* 0x402D0870 */ + +/******************************************************************************* +* HSIOM +*******************************************************************************/ + +#define HSIOM_BASE 0x40300000UL +#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40300000 */ +#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40300000 */ +#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40300010 */ +#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40300020 */ +#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40300030 */ +#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40300040 */ +#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40300050 */ +#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40300060 */ +#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40300070 */ +#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40300080 */ +#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40300090 */ +#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403000A0 */ +#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403000B0 */ +#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403000C0 */ +#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403000D0 */ +#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403000E0 */ + +/******************************************************************************* +* GPIO +*******************************************************************************/ + +#define GPIO_BASE 0x40310000UL +#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40310000 */ +#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40310000 */ +#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40310080 */ +#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40310100 */ +#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40310180 */ +#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40310200 */ +#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40310280 */ +#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40310300 */ +#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40310380 */ +#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40310400 */ +#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40310480 */ +#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40310500 */ +#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40310580 */ +#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40310600 */ +#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40310680 */ +#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40310700 */ + +/******************************************************************************* +* SMARTIO +*******************************************************************************/ + +#define SMARTIO_BASE 0x40320000UL +#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40320000 */ +#define SMARTIO_PRT8 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[8]) /* 0x40320800 */ +#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40320900 */ + +/******************************************************************************* +* LPCOMP +*******************************************************************************/ + +#define LPCOMP_BASE 0x40350000UL +#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */ + +/******************************************************************************* +* CSD +*******************************************************************************/ + +#define CSD0_BASE 0x40360000UL +#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */ + +/******************************************************************************* +* TCPWM +*******************************************************************************/ + +#define TCPWM0_BASE 0x40380000UL +#define TCPWM1_BASE 0x40390000UL +#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM1 ((TCPWM_Type*) TCPWM1_BASE) /* 0x40390000 */ +#define TCPWM0_CNT0 ((TCPWM_CNT_Type*) &TCPWM0->CNT[0]) /* 0x40380100 */ +#define TCPWM0_CNT1 ((TCPWM_CNT_Type*) &TCPWM0->CNT[1]) /* 0x40380140 */ +#define TCPWM0_CNT2 ((TCPWM_CNT_Type*) &TCPWM0->CNT[2]) /* 0x40380180 */ +#define TCPWM0_CNT3 ((TCPWM_CNT_Type*) &TCPWM0->CNT[3]) /* 0x403801C0 */ +#define TCPWM0_CNT4 ((TCPWM_CNT_Type*) &TCPWM0->CNT[4]) /* 0x40380200 */ +#define TCPWM0_CNT5 ((TCPWM_CNT_Type*) &TCPWM0->CNT[5]) /* 0x40380240 */ +#define TCPWM0_CNT6 ((TCPWM_CNT_Type*) &TCPWM0->CNT[6]) /* 0x40380280 */ +#define TCPWM0_CNT7 ((TCPWM_CNT_Type*) &TCPWM0->CNT[7]) /* 0x403802C0 */ +#define TCPWM1_CNT0 ((TCPWM_CNT_Type*) &TCPWM1->CNT[0]) /* 0x40390100 */ +#define TCPWM1_CNT1 ((TCPWM_CNT_Type*) &TCPWM1->CNT[1]) /* 0x40390140 */ +#define TCPWM1_CNT2 ((TCPWM_CNT_Type*) &TCPWM1->CNT[2]) /* 0x40390180 */ +#define TCPWM1_CNT3 ((TCPWM_CNT_Type*) &TCPWM1->CNT[3]) /* 0x403901C0 */ +#define TCPWM1_CNT4 ((TCPWM_CNT_Type*) &TCPWM1->CNT[4]) /* 0x40390200 */ +#define TCPWM1_CNT5 ((TCPWM_CNT_Type*) &TCPWM1->CNT[5]) /* 0x40390240 */ +#define TCPWM1_CNT6 ((TCPWM_CNT_Type*) &TCPWM1->CNT[6]) /* 0x40390280 */ +#define TCPWM1_CNT7 ((TCPWM_CNT_Type*) &TCPWM1->CNT[7]) /* 0x403902C0 */ +#define TCPWM1_CNT8 ((TCPWM_CNT_Type*) &TCPWM1->CNT[8]) /* 0x40390300 */ +#define TCPWM1_CNT9 ((TCPWM_CNT_Type*) &TCPWM1->CNT[9]) /* 0x40390340 */ +#define TCPWM1_CNT10 ((TCPWM_CNT_Type*) &TCPWM1->CNT[10]) /* 0x40390380 */ +#define TCPWM1_CNT11 ((TCPWM_CNT_Type*) &TCPWM1->CNT[11]) /* 0x403903C0 */ +#define TCPWM1_CNT12 ((TCPWM_CNT_Type*) &TCPWM1->CNT[12]) /* 0x40390400 */ +#define TCPWM1_CNT13 ((TCPWM_CNT_Type*) &TCPWM1->CNT[13]) /* 0x40390440 */ +#define TCPWM1_CNT14 ((TCPWM_CNT_Type*) &TCPWM1->CNT[14]) /* 0x40390480 */ +#define TCPWM1_CNT15 ((TCPWM_CNT_Type*) &TCPWM1->CNT[15]) /* 0x403904C0 */ +#define TCPWM1_CNT16 ((TCPWM_CNT_Type*) &TCPWM1->CNT[16]) /* 0x40390500 */ +#define TCPWM1_CNT17 ((TCPWM_CNT_Type*) &TCPWM1->CNT[17]) /* 0x40390540 */ +#define TCPWM1_CNT18 ((TCPWM_CNT_Type*) &TCPWM1->CNT[18]) /* 0x40390580 */ +#define TCPWM1_CNT19 ((TCPWM_CNT_Type*) &TCPWM1->CNT[19]) /* 0x403905C0 */ +#define TCPWM1_CNT20 ((TCPWM_CNT_Type*) &TCPWM1->CNT[20]) /* 0x40390600 */ +#define TCPWM1_CNT21 ((TCPWM_CNT_Type*) &TCPWM1->CNT[21]) /* 0x40390640 */ +#define TCPWM1_CNT22 ((TCPWM_CNT_Type*) &TCPWM1->CNT[22]) /* 0x40390680 */ +#define TCPWM1_CNT23 ((TCPWM_CNT_Type*) &TCPWM1->CNT[23]) /* 0x403906C0 */ + +/******************************************************************************* +* LCD +*******************************************************************************/ + +#define LCD0_BASE 0x403B0000UL +#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ + +/******************************************************************************* +* USBFS +*******************************************************************************/ + +#define USBFS0_BASE 0x403F0000UL +#define USBFS0 ((USBFS_Type*) USBFS0_BASE) /* 0x403F0000 */ +#define USBFS0_USBDEV ((USBFS_USBDEV_Type*) &USBFS0->USBDEV) /* 0x403F0000 */ +#define USBFS0_USBLPM ((USBFS_USBLPM_Type*) &USBFS0->USBLPM) /* 0x403F2000 */ +#define USBFS0_USBHOST ((USBFS_USBHOST_Type*) &USBFS0->USBHOST) /* 0x403F4000 */ + +/******************************************************************************* +* SMIF +*******************************************************************************/ + +#define SMIF0_BASE 0x40420000UL +#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ +#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ +#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ +#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ +#define SMIF0_DEVICE3 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[3]) /* 0x40420980 */ + +/******************************************************************************* +* SDHC +*******************************************************************************/ + +#define SDHC0_BASE 0x40460000UL +#define SDHC1_BASE 0x40470000UL +#define SDHC0 ((SDHC_Type*) SDHC0_BASE) /* 0x40460000 */ +#define SDHC1 ((SDHC_Type*) SDHC1_BASE) /* 0x40470000 */ +#define SDHC0_WRAP ((SDHC_WRAP_Type*) &SDHC0->WRAP) /* 0x40460000 */ +#define SDHC1_WRAP ((SDHC_WRAP_Type*) &SDHC1->WRAP) /* 0x40470000 */ +#define SDHC0_CORE ((SDHC_CORE_Type*) &SDHC0->CORE) /* 0x40461000 */ +#define SDHC1_CORE ((SDHC_CORE_Type*) &SDHC1->CORE) /* 0x40471000 */ + +/******************************************************************************* +* SCB +*******************************************************************************/ + +#define SCB0_BASE 0x40600000UL +#define SCB1_BASE 0x40610000UL +#define SCB2_BASE 0x40620000UL +#define SCB3_BASE 0x40630000UL +#define SCB4_BASE 0x40640000UL +#define SCB5_BASE 0x40650000UL +#define SCB6_BASE 0x40660000UL +#define SCB7_BASE 0x40670000UL +#define SCB8_BASE 0x40680000UL +#define SCB9_BASE 0x40690000UL +#define SCB10_BASE 0x406A0000UL +#define SCB11_BASE 0x406B0000UL +#define SCB12_BASE 0x406C0000UL +#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40600000 */ +#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40610000 */ +#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40620000 */ +#define SCB3 ((CySCB_Type*) SCB3_BASE) /* 0x40630000 */ +#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40640000 */ +#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40650000 */ +#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40660000 */ +#define SCB7 ((CySCB_Type*) SCB7_BASE) /* 0x40670000 */ +#define SCB8 ((CySCB_Type*) SCB8_BASE) /* 0x40680000 */ +#define SCB9 ((CySCB_Type*) SCB9_BASE) /* 0x40690000 */ +#define SCB10 ((CySCB_Type*) SCB10_BASE) /* 0x406A0000 */ +#define SCB11 ((CySCB_Type*) SCB11_BASE) /* 0x406B0000 */ +#define SCB12 ((CySCB_Type*) SCB12_BASE) /* 0x406C0000 */ + +/******************************************************************************* +* SAR +*******************************************************************************/ + +#define SAR_BASE 0x409D0000UL +#define SAR ((SAR_Type*) SAR_BASE) /* 0x409D0000 */ + +/******************************************************************************* +* PASS +*******************************************************************************/ + +#define PASS_BASE 0x409F0000UL +#define PASS ((PASS_Type*) PASS_BASE) /* 0x409F0000 */ +#define PASS_AREF ((PASS_AREF_Type*) &PASS->AREF) /* 0x409F0E00 */ + +/******************************************************************************* +* PDM +*******************************************************************************/ + +#define PDM0_BASE 0x40A00000UL +#define PDM0 ((PDM_Type*) PDM0_BASE) /* 0x40A00000 */ + +/******************************************************************************* +* I2S +*******************************************************************************/ + +#define I2S0_BASE 0x40A10000UL +#define I2S1_BASE 0x40A11000UL +#define I2S0 ((I2S_Type*) I2S0_BASE) /* 0x40A10000 */ +#define I2S1 ((I2S_Type*) I2S1_BASE) /* 0x40A11000 */ + +/** \} CY8C614AAZI-S2F14 */ + +#endif /* _CY8C614AAZI_S2F14_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c614aazi_s2f44.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c614aazi_s2f44.h new file mode 100644 index 0000000000..bb1464403c --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c614aazi_s2f44.h @@ -0,0 +1,1098 @@ +/***************************************************************************//** +* \file cy8c614aazi_s2f44.h +* +* \brief +* CY8C614AAZI-S2F44 device header +* +* \note +* Generator version: 1.6.0.225 +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CY8C614AAZI_S2F44_H_ +#define _CY8C614AAZI_S2F44_H_ + +/** +* \addtogroup group_device CY8C614AAZI-S2F44 +* \{ +*/ + +/** +* \addtogroup Configuration_of_CMSIS +* \{ +*/ + +/******************************************************************************* +* Interrupt Number Definition +*******************************************************************************/ + +typedef enum { + /* ARM Cortex-M4 Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C614AAZI-S2F44 Peripheral Interrupt Numbers */ + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_1_IRQn = 1, /*!< 1 [DeepSleep] GPIO Port Interrupt #1 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_4_IRQn = 4, /*!< 4 [DeepSleep] GPIO Port Interrupt #4 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_13_IRQn = 13, /*!< 13 [DeepSleep] GPIO Port Interrupt #13 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_8_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #8 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + scb_6_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #6 */ + scb_7_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #7 */ + scb_9_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #9 */ + scb_10_interrupt_IRQn = 48, /*!< 48 [Active] Serial Communication Block #10 */ + scb_11_interrupt_IRQn = 49, /*!< 49 [Active] Serial Communication Block #11 */ + scb_12_interrupt_IRQn = 50, /*!< 50 [Active] Serial Communication Block #12 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dmac_2_IRQn = 54, /*!< 54 [Active] CPUSS DMAC, Channel #2 */ + cpuss_interrupts_dmac_3_IRQn = 55, /*!< 55 [Active] CPUSS DMAC, Channel #3 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_0_interrupts_4_IRQn = 127, /*!< 127 [Active] TCPWM #0, Counter #4 */ + tcpwm_0_interrupts_5_IRQn = 128, /*!< 128 [Active] TCPWM #0, Counter #5 */ + tcpwm_0_interrupts_6_IRQn = 129, /*!< 129 [Active] TCPWM #0, Counter #6 */ + tcpwm_0_interrupts_7_IRQn = 130, /*!< 130 [Active] TCPWM #0, Counter #7 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + tcpwm_1_interrupts_8_IRQn = 139, /*!< 139 [Active] TCPWM #1, Counter #8 */ + tcpwm_1_interrupts_9_IRQn = 140, /*!< 140 [Active] TCPWM #1, Counter #9 */ + tcpwm_1_interrupts_10_IRQn = 141, /*!< 141 [Active] TCPWM #1, Counter #10 */ + tcpwm_1_interrupts_11_IRQn = 142, /*!< 142 [Active] TCPWM #1, Counter #11 */ + tcpwm_1_interrupts_12_IRQn = 143, /*!< 143 [Active] TCPWM #1, Counter #12 */ + tcpwm_1_interrupts_13_IRQn = 144, /*!< 144 [Active] TCPWM #1, Counter #13 */ + tcpwm_1_interrupts_14_IRQn = 145, /*!< 145 [Active] TCPWM #1, Counter #14 */ + tcpwm_1_interrupts_15_IRQn = 146, /*!< 146 [Active] TCPWM #1, Counter #15 */ + tcpwm_1_interrupts_16_IRQn = 147, /*!< 147 [Active] TCPWM #1, Counter #16 */ + tcpwm_1_interrupts_17_IRQn = 148, /*!< 148 [Active] TCPWM #1, Counter #17 */ + tcpwm_1_interrupts_18_IRQn = 149, /*!< 149 [Active] TCPWM #1, Counter #18 */ + tcpwm_1_interrupts_19_IRQn = 150, /*!< 150 [Active] TCPWM #1, Counter #19 */ + tcpwm_1_interrupts_20_IRQn = 151, /*!< 151 [Active] TCPWM #1, Counter #20 */ + tcpwm_1_interrupts_21_IRQn = 152, /*!< 152 [Active] TCPWM #1, Counter #21 */ + tcpwm_1_interrupts_22_IRQn = 153, /*!< 153 [Active] TCPWM #1, Counter #22 */ + tcpwm_1_interrupts_23_IRQn = 154, /*!< 154 [Active] TCPWM #1, Counter #23 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + audioss_0_interrupt_i2s_IRQn = 156, /*!< 156 [Active] I2S0 Audio interrupt */ + audioss_0_interrupt_pdm_IRQn = 157, /*!< 157 [Active] PDM0/PCM0 Audio interrupt */ + audioss_1_interrupt_i2s_IRQn = 158, /*!< 158 [Active] I2S1 Audio interrupt */ + profile_interrupt_IRQn = 159, /*!< 159 [Active] Energy Profiler interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + sdhc_1_interrupt_wakeup_IRQn = 166, /*!< 166 [Active] EEMC wakeup interrupt for mxsdhc, not used */ + sdhc_1_interrupt_general_IRQn = 167, /*!< 167 [Active] Consolidated interrupt for mxsdhc for everything else */ + unconnected_IRQn = 240 /*!< 240 Unconnected */ +} IRQn_Type; + + +/******************************************************************************* +* Processor and Core Peripheral Section +*******************************************************************************/ + +/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __CM0P_PRESENT 0 /*!< CM0P present or not */ +#define __DTCM_PRESENT 0 /*!< DTCM present or not */ +#define __ICACHE_PRESENT 0 /*!< ICACHE present or not */ +#define __DCACHE_PRESENT 0 /*!< DCACHE present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + + +/* Memory Blocks */ +#define CY_ROM_BASE 0x00000000UL +#define CY_ROM_SIZE 0x00010000UL +#define CY_SRAM_BASE 0x08000000UL +#define CY_SRAM_SIZE 0x00100000UL +#define CY_FLASH_BASE 0x10000000UL +#define CY_FLASH_SIZE 0x00200000UL +#define CY_EM_EEPROM_BASE 0x14000000UL +#define CY_EM_EEPROM_SIZE 0x00008000UL +#define CY_SFLASH_BASE 0x16000000UL +#define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL +#define CY_EFUSE_BASE 0x402C0800UL +#define CY_EFUSE_SIZE 0x00000200UL + +#include "system_psoc6.h" /*!< PSoC 6 System */ + +/* IP List */ +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 2u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_M4CPUSS 1u +#define CY_IP_M4CPUSS_INSTANCES 1u +#define CY_IP_M4CPUSS_VERSION 2u +#define CY_IP_M4CPUSS_DMAC 1u +#define CY_IP_M4CPUSS_DMAC_INSTANCES 1u +#define CY_IP_M4CPUSS_DMAC_VERSION 2u +#define CY_IP_M4CPUSS_DMA 1u +#define CY_IP_M4CPUSS_DMA_INSTANCES 2u +#define CY_IP_M4CPUSS_DMA_VERSION 2u +#define CY_IP_MXCRYPTO 1u +#define CY_IP_MXCRYPTO_INSTANCES 1u +#define CY_IP_MXCRYPTO_VERSION 2u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u +#define CY_IP_MXS40PASS 1u +#define CY_IP_MXS40PASS_INSTANCES 1u +#define CY_IP_MXS40PASS_VERSION 1u +#define CY_IP_MXS40PASS_SAR 1u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u +#define CY_IP_MXS40PASS_SAR_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXPROFILE 1u +#define CY_IP_MXPROFILE_INSTANCES 1u +#define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 13u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 2u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u + +#include "psoc6_02_config.h" +#include "gpio_psoc6_02_128_tqfp.h" + +#define CY_DEVICE_PSOC6A2M +#define CY_SILICON_ID 0xE45F1202UL +#define CY_HF_CLK_MAX_FREQ 150000000UL + +#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL + +/******************************************************************************* +* SFLASH +*******************************************************************************/ + +#define SFLASH_BASE 0x16000000UL +#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */ + +/******************************************************************************* +* PERI +*******************************************************************************/ + +#define PERI_BASE 0x40000000UL +#define PERI ((PERI_Type*) PERI_BASE) /* 0x40000000 */ +#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40004000 */ +#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40004020 */ +#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40004040 */ +#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x40004060 */ +#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40004080 */ +#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x400040C0 */ +#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40004120 */ +#define PERI_GR10 ((PERI_GR_Type*) &PERI->GR[10]) /* 0x40004140 */ +#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40008000 */ +#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40008400 */ +#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40008800 */ +#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40008C00 */ +#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40009000 */ +#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40009400 */ +#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40009800 */ +#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40009C00 */ +#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ +#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ +#define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ +#define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ +#define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ +#define PERI_TR_1TO1_GR3 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[3]) /* 0x4000CC00 */ +#define PERI_TR_1TO1_GR4 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[4]) /* 0x4000D000 */ +#define PERI_TR_1TO1_GR5 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[5]) /* 0x4000D400 */ +#define PERI_TR_1TO1_GR6 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[6]) /* 0x4000D800 */ + +/******************************************************************************* +* PERI_MS +*******************************************************************************/ + +#define PERI_MS_BASE 0x40010000UL +#define PERI_MS ((PERI_MS_Type*) PERI_MS_BASE) /* 0x40010000 */ +#define PERI_MS_PPU_PR0 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[0]) /* 0x40010000 */ +#define PERI_MS_PPU_PR1 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[1]) /* 0x40010040 */ +#define PERI_MS_PPU_PR2 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[2]) /* 0x40010080 */ +#define PERI_MS_PPU_PR3 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[3]) /* 0x400100C0 */ +#define PERI_MS_PPU_PR4 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[4]) /* 0x40010100 */ +#define PERI_MS_PPU_PR5 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[5]) /* 0x40010140 */ +#define PERI_MS_PPU_PR6 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[6]) /* 0x40010180 */ +#define PERI_MS_PPU_PR7 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[7]) /* 0x400101C0 */ +#define PERI_MS_PPU_FX_PERI_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[0]) /* 0x40010800 */ +#define PERI_MS_PPU_FX_PERI_GR0_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[1]) /* 0x40010840 */ +#define PERI_MS_PPU_FX_PERI_GR1_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[2]) /* 0x40010880 */ +#define PERI_MS_PPU_FX_PERI_GR2_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[3]) /* 0x400108C0 */ +#define PERI_MS_PPU_FX_PERI_GR3_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[4]) /* 0x40010900 */ +#define PERI_MS_PPU_FX_PERI_GR4_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[5]) /* 0x40010940 */ +#define PERI_MS_PPU_FX_PERI_GR6_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[6]) /* 0x40010980 */ +#define PERI_MS_PPU_FX_PERI_GR9_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[7]) /* 0x400109C0 */ +#define PERI_MS_PPU_FX_PERI_GR10_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[8]) /* 0x40010A00 */ +#define PERI_MS_PPU_FX_PERI_TR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[9]) /* 0x40010A40 */ +#define PERI_MS_PPU_FX_CRYPTO_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[10]) /* 0x40010A80 */ +#define PERI_MS_PPU_FX_CRYPTO_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[11]) /* 0x40010AC0 */ +#define PERI_MS_PPU_FX_CRYPTO_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[12]) /* 0x40010B00 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[13]) /* 0x40010B40 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[14]) /* 0x40010B80 */ +#define PERI_MS_PPU_FX_CRYPTO_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[15]) /* 0x40010BC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[16]) /* 0x40010C00 */ +#define PERI_MS_PPU_FX_CPUSS_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[17]) /* 0x40010C40 */ +#define PERI_MS_PPU_FX_CPUSS_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[18]) /* 0x40010C80 */ +#define PERI_MS_PPU_FX_CPUSS_CM0_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[19]) /* 0x40010CC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[20]) /* 0x40010D00 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[21]) /* 0x40010D40 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT1_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[22]) /* 0x40010D80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT0_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[23]) /* 0x40010DC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT1_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[24]) /* 0x40010E00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT2_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[25]) /* 0x40010E40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT3_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[26]) /* 0x40010E80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT4_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[27]) /* 0x40010EC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT5_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[28]) /* 0x40010F00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT6_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[29]) /* 0x40010F40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT7_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[30]) /* 0x40010F80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT8_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[31]) /* 0x40010FC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT9_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[32]) /* 0x40011000 */ +#define PERI_MS_PPU_FX_IPC_STRUCT10_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[33]) /* 0x40011040 */ +#define PERI_MS_PPU_FX_IPC_STRUCT11_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[34]) /* 0x40011080 */ +#define PERI_MS_PPU_FX_IPC_STRUCT12_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[35]) /* 0x400110C0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT13_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[36]) /* 0x40011100 */ +#define PERI_MS_PPU_FX_IPC_STRUCT14_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[37]) /* 0x40011140 */ +#define PERI_MS_PPU_FX_IPC_STRUCT15_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[38]) /* 0x40011180 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT0_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[39]) /* 0x400111C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT1_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[40]) /* 0x40011200 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT2_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[41]) /* 0x40011240 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT3_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[42]) /* 0x40011280 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT4_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[43]) /* 0x400112C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT5_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[44]) /* 0x40011300 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT6_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[45]) /* 0x40011340 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT7_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[46]) /* 0x40011380 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT8_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[47]) /* 0x400113C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT9_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[48]) /* 0x40011400 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT10_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[49]) /* 0x40011440 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT11_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[50]) /* 0x40011480 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT12_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[51]) /* 0x400114C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT13_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[52]) /* 0x40011500 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT14_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[53]) /* 0x40011540 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT15_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[54]) /* 0x40011580 */ +#define PERI_MS_PPU_FX_PROT_SMPU_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[55]) /* 0x400115C0 */ +#define PERI_MS_PPU_FX_PROT_MPU0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[56]) /* 0x40011600 */ +#define PERI_MS_PPU_FX_PROT_MPU5_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[57]) /* 0x40011640 */ +#define PERI_MS_PPU_FX_PROT_MPU6_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[58]) /* 0x40011680 */ +#define PERI_MS_PPU_FX_PROT_MPU14_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[59]) /* 0x400116C0 */ +#define PERI_MS_PPU_FX_PROT_MPU15_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[60]) /* 0x40011700 */ +#define PERI_MS_PPU_FX_FLASHC_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[61]) /* 0x40011740 */ +#define PERI_MS_PPU_FX_FLASHC_CMD ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[62]) /* 0x40011780 */ +#define PERI_MS_PPU_FX_FLASHC_DFT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[63]) /* 0x400117C0 */ +#define PERI_MS_PPU_FX_FLASHC_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[64]) /* 0x40011800 */ +#define PERI_MS_PPU_FX_FLASHC_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[65]) /* 0x40011840 */ +#define PERI_MS_PPU_FX_FLASHC_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[66]) /* 0x40011880 */ +#define PERI_MS_PPU_FX_FLASHC_DW0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[67]) /* 0x400118C0 */ +#define PERI_MS_PPU_FX_FLASHC_DW1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[68]) /* 0x40011900 */ +#define PERI_MS_PPU_FX_FLASHC_DMAC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[69]) /* 0x40011940 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[70]) /* 0x40011980 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[71]) /* 0x400119C0 */ +#define PERI_MS_PPU_FX_FLASHC_FM ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[72]) /* 0x40011A00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[73]) /* 0x40011A40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[74]) /* 0x40011A80 */ +#define PERI_MS_PPU_FX_WDT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[75]) /* 0x40011AC0 */ +#define PERI_MS_PPU_FX_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[76]) /* 0x40011B00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[77]) /* 0x40011B40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[78]) /* 0x40011B80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[79]) /* 0x40011BC0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[80]) /* 0x40011C00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[81]) /* 0x40011C40 */ +#define PERI_MS_PPU_FX_BACKUP_BACKUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[82]) /* 0x40011C80 */ +#define PERI_MS_PPU_FX_DW0_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[83]) /* 0x40011CC0 */ +#define PERI_MS_PPU_FX_DW1_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[84]) /* 0x40011D00 */ +#define PERI_MS_PPU_FX_DW0_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[85]) /* 0x40011D40 */ +#define PERI_MS_PPU_FX_DW1_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[86]) /* 0x40011D80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[87]) /* 0x40011DC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[88]) /* 0x40011E00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[89]) /* 0x40011E40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[90]) /* 0x40011E80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[91]) /* 0x40011EC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[92]) /* 0x40011F00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[93]) /* 0x40011F40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[94]) /* 0x40011F80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[95]) /* 0x40011FC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[96]) /* 0x40012000 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[97]) /* 0x40012040 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[98]) /* 0x40012080 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[99]) /* 0x400120C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[100]) /* 0x40012100 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[101]) /* 0x40012140 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[102]) /* 0x40012180 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[103]) /* 0x400121C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[104]) /* 0x40012200 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[105]) /* 0x40012240 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[106]) /* 0x40012280 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[107]) /* 0x400122C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[108]) /* 0x40012300 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[109]) /* 0x40012340 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[110]) /* 0x40012380 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[111]) /* 0x400123C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[112]) /* 0x40012400 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[113]) /* 0x40012440 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[114]) /* 0x40012480 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[115]) /* 0x400124C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[116]) /* 0x40012500 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[117]) /* 0x40012540 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[118]) /* 0x40012580 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[119]) /* 0x400125C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[120]) /* 0x40012600 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[121]) /* 0x40012640 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[122]) /* 0x40012680 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[123]) /* 0x400126C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[124]) /* 0x40012700 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[125]) /* 0x40012740 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[126]) /* 0x40012780 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[127]) /* 0x400127C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[128]) /* 0x40012800 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[129]) /* 0x40012840 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[130]) /* 0x40012880 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[131]) /* 0x400128C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[132]) /* 0x40012900 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[133]) /* 0x40012940 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[134]) /* 0x40012980 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[135]) /* 0x400129C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[136]) /* 0x40012A00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[137]) /* 0x40012A40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[138]) /* 0x40012A80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[139]) /* 0x40012AC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[140]) /* 0x40012B00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[141]) /* 0x40012B40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[142]) /* 0x40012B80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[143]) /* 0x40012BC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[144]) /* 0x40012C00 */ +#define PERI_MS_PPU_FX_DMAC_TOP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[145]) /* 0x40012C40 */ +#define PERI_MS_PPU_FX_DMAC_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[146]) /* 0x40012C80 */ +#define PERI_MS_PPU_FX_DMAC_CH1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[147]) /* 0x40012CC0 */ +#define PERI_MS_PPU_FX_DMAC_CH2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[148]) /* 0x40012D00 */ +#define PERI_MS_PPU_FX_DMAC_CH3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[149]) /* 0x40012D40 */ +#define PERI_MS_PPU_FX_EFUSE_CTL ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[150]) /* 0x40012D80 */ +#define PERI_MS_PPU_FX_EFUSE_DATA ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[151]) /* 0x40012DC0 */ +#define PERI_MS_PPU_FX_PROFILE ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[152]) /* 0x40012E00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[153]) /* 0x40012E40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[154]) /* 0x40012E80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[155]) /* 0x40012EC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[156]) /* 0x40012F00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[157]) /* 0x40012F40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[158]) /* 0x40012F80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[159]) /* 0x40012FC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[160]) /* 0x40013000 */ +#define PERI_MS_PPU_FX_HSIOM_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[161]) /* 0x40013040 */ +#define PERI_MS_PPU_FX_HSIOM_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[162]) /* 0x40013080 */ +#define PERI_MS_PPU_FX_HSIOM_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[163]) /* 0x400130C0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[164]) /* 0x40013100 */ +#define PERI_MS_PPU_FX_HSIOM_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[165]) /* 0x40013140 */ +#define PERI_MS_PPU_FX_HSIOM_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[166]) /* 0x40013180 */ +#define PERI_MS_PPU_FX_HSIOM_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[167]) /* 0x400131C0 */ +#define PERI_MS_PPU_FX_HSIOM_AMUX ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[168]) /* 0x40013200 */ +#define PERI_MS_PPU_FX_HSIOM_MON ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[169]) /* 0x40013240 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[170]) /* 0x40013280 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[171]) /* 0x400132C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[172]) /* 0x40013300 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[173]) /* 0x40013340 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[174]) /* 0x40013380 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[175]) /* 0x400133C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[176]) /* 0x40013400 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[177]) /* 0x40013440 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[178]) /* 0x40013480 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[179]) /* 0x400134C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[180]) /* 0x40013500 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[181]) /* 0x40013540 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[182]) /* 0x40013580 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[183]) /* 0x400135C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[184]) /* 0x40013600 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[185]) /* 0x40013640 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[186]) /* 0x40013680 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[187]) /* 0x400136C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[188]) /* 0x40013700 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[189]) /* 0x40013740 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[190]) /* 0x40013780 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[191]) /* 0x400137C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[192]) /* 0x40013800 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[193]) /* 0x40013840 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[194]) /* 0x40013880 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[195]) /* 0x400138C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[196]) /* 0x40013900 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[197]) /* 0x40013940 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[198]) /* 0x40013980 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[199]) /* 0x400139C0 */ +#define PERI_MS_PPU_FX_GPIO_GPIO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[200]) /* 0x40013A00 */ +#define PERI_MS_PPU_FX_GPIO_TEST ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[201]) /* 0x40013A40 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[202]) /* 0x40013A80 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[203]) /* 0x40013AC0 */ +#define PERI_MS_PPU_FX_LPCOMP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[204]) /* 0x40013B00 */ +#define PERI_MS_PPU_FX_CSD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[205]) /* 0x40013B40 */ +#define PERI_MS_PPU_FX_TCPWM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[206]) /* 0x40013B80 */ +#define PERI_MS_PPU_FX_TCPWM1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[207]) /* 0x40013BC0 */ +#define PERI_MS_PPU_FX_LCD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[208]) /* 0x40013C00 */ +#define PERI_MS_PPU_FX_USBFS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[209]) /* 0x40013C40 */ +#define PERI_MS_PPU_FX_SMIF0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[210]) /* 0x40013C80 */ +#define PERI_MS_PPU_FX_SDHC0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[211]) /* 0x40013CC0 */ +#define PERI_MS_PPU_FX_SDHC1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[212]) /* 0x40013D00 */ +#define PERI_MS_PPU_FX_SCB0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[213]) /* 0x40013D40 */ +#define PERI_MS_PPU_FX_SCB1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[214]) /* 0x40013D80 */ +#define PERI_MS_PPU_FX_SCB2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[215]) /* 0x40013DC0 */ +#define PERI_MS_PPU_FX_SCB3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[216]) /* 0x40013E00 */ +#define PERI_MS_PPU_FX_SCB4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[217]) /* 0x40013E40 */ +#define PERI_MS_PPU_FX_SCB5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[218]) /* 0x40013E80 */ +#define PERI_MS_PPU_FX_SCB6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[219]) /* 0x40013EC0 */ +#define PERI_MS_PPU_FX_SCB7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[220]) /* 0x40013F00 */ +#define PERI_MS_PPU_FX_SCB8 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[221]) /* 0x40013F40 */ +#define PERI_MS_PPU_FX_SCB9 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[222]) /* 0x40013F80 */ +#define PERI_MS_PPU_FX_SCB10 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[223]) /* 0x40013FC0 */ +#define PERI_MS_PPU_FX_SCB11 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[224]) /* 0x40014000 */ +#define PERI_MS_PPU_FX_SCB12 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[225]) /* 0x40014040 */ +#define PERI_MS_PPU_FX_PDM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[226]) /* 0x40014080 */ +#define PERI_MS_PPU_FX_I2S0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[227]) /* 0x400140C0 */ +#define PERI_MS_PPU_FX_I2S1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[228]) /* 0x40014100 */ + +/******************************************************************************* +* CRYPTO +*******************************************************************************/ + +#define CRYPTO_BASE 0x40100000UL +#define CRYPTO ((CRYPTO_Type*) CRYPTO_BASE) /* 0x40100000 */ + +/******************************************************************************* +* CPUSS +*******************************************************************************/ + +#define CPUSS_BASE 0x40200000UL +#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40200000 */ + +/******************************************************************************* +* FAULT +*******************************************************************************/ + +#define FAULT_BASE 0x40210000UL +#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40210000 */ +#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40210000 */ +#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40210100 */ + +/******************************************************************************* +* IPC +*******************************************************************************/ + +#define IPC_BASE 0x40220000UL +#define IPC ((IPC_Type*) IPC_BASE) /* 0x40220000 */ +#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40220000 */ +#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40220020 */ +#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40220040 */ +#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40220060 */ +#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40220080 */ +#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402200A0 */ +#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402200C0 */ +#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402200E0 */ +#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40220100 */ +#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40220120 */ +#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40220140 */ +#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40220160 */ +#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40220180 */ +#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402201A0 */ +#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402201C0 */ +#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402201E0 */ +#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40221000 */ +#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40221020 */ +#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40221040 */ +#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40221060 */ +#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40221080 */ +#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402210A0 */ +#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402210C0 */ +#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402210E0 */ +#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40221100 */ +#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40221120 */ +#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40221140 */ +#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40221160 */ +#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40221180 */ +#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402211A0 */ +#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402211C0 */ +#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402211E0 */ + +/******************************************************************************* +* PROT +*******************************************************************************/ + +#define PROT_BASE 0x40230000UL +#define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ +#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ +#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ +#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402320C0 */ +#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40232100 */ +#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40232140 */ +#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40232180 */ +#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402321C0 */ +#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40232200 */ +#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40232240 */ +#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40232280 */ +#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402322C0 */ +#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40232300 */ +#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ +#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ +#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ +#define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ +#define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ +#define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ +#define PROT_MPU5_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[3]) /* 0x40235660 */ +#define PROT_MPU5_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[4]) /* 0x40235680 */ +#define PROT_MPU5_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[5]) /* 0x402356A0 */ +#define PROT_MPU5_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[6]) /* 0x402356C0 */ +#define PROT_MPU5_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[7]) /* 0x402356E0 */ +#define PROT_MPU6_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[0]) /* 0x40235A00 */ +#define PROT_MPU6_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[1]) /* 0x40235A20 */ +#define PROT_MPU6_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[2]) /* 0x40235A40 */ +#define PROT_MPU6_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[3]) /* 0x40235A60 */ +#define PROT_MPU6_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[4]) /* 0x40235A80 */ +#define PROT_MPU6_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[5]) /* 0x40235AA0 */ +#define PROT_MPU6_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[6]) /* 0x40235AC0 */ +#define PROT_MPU6_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[7]) /* 0x40235AE0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ + +/******************************************************************************* +* FLASHC +*******************************************************************************/ + +#define FLASHC_BASE 0x40240000UL +#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40240000 */ +#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4024F000 */ + +/******************************************************************************* +* SRSS +*******************************************************************************/ + +#define SRSS_BASE 0x40260000UL +#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ +#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */ +#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */ + +/******************************************************************************* +* BACKUP +*******************************************************************************/ + +#define BACKUP_BASE 0x40270000UL +#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ + +/******************************************************************************* +* DW +*******************************************************************************/ + +#define DW0_BASE 0x40280000UL +#define DW1_BASE 0x40290000UL +#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ +#define DW1 ((DW_Type*) DW1_BASE) /* 0x40290000 */ +#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40288000 */ +#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40288040 */ +#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40288080 */ +#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x402880C0 */ +#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40288100 */ +#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x40288140 */ +#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x40288180 */ +#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402881C0 */ +#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40288200 */ +#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40288240 */ +#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40288280 */ +#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x402882C0 */ +#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40288300 */ +#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x40288340 */ +#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x40288380 */ +#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402883C0 */ +#define DW0_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[16]) /* 0x40288400 */ +#define DW0_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[17]) /* 0x40288440 */ +#define DW0_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[18]) /* 0x40288480 */ +#define DW0_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[19]) /* 0x402884C0 */ +#define DW0_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[20]) /* 0x40288500 */ +#define DW0_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[21]) /* 0x40288540 */ +#define DW0_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[22]) /* 0x40288580 */ +#define DW0_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[23]) /* 0x402885C0 */ +#define DW0_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[24]) /* 0x40288600 */ +#define DW0_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[25]) /* 0x40288640 */ +#define DW0_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[26]) /* 0x40288680 */ +#define DW0_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[27]) /* 0x402886C0 */ +#define DW0_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[28]) /* 0x40288700 */ +#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40298000 */ +#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40298040 */ +#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40298080 */ +#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x402980C0 */ +#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40298100 */ +#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x40298140 */ +#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x40298180 */ +#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402981C0 */ +#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40298200 */ +#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40298240 */ +#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40298280 */ +#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x402982C0 */ +#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40298300 */ +#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x40298340 */ +#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x40298380 */ +#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402983C0 */ +#define DW1_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[16]) /* 0x40298400 */ +#define DW1_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[17]) /* 0x40298440 */ +#define DW1_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[18]) /* 0x40298480 */ +#define DW1_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[19]) /* 0x402984C0 */ +#define DW1_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[20]) /* 0x40298500 */ +#define DW1_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[21]) /* 0x40298540 */ +#define DW1_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[22]) /* 0x40298580 */ +#define DW1_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[23]) /* 0x402985C0 */ +#define DW1_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[24]) /* 0x40298600 */ +#define DW1_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[25]) /* 0x40298640 */ +#define DW1_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[26]) /* 0x40298680 */ +#define DW1_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[27]) /* 0x402986C0 */ +#define DW1_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[28]) /* 0x40298700 */ + +/******************************************************************************* +* DMAC +*******************************************************************************/ + +#define DMAC_BASE 0x402A0000UL +#define DMAC ((DMAC_Type*) DMAC_BASE) /* 0x402A0000 */ +#define DMAC_CH0 ((DMAC_CH_Type*) &DMAC->CH[0]) /* 0x402A1000 */ +#define DMAC_CH1 ((DMAC_CH_Type*) &DMAC->CH[1]) /* 0x402A1100 */ +#define DMAC_CH2 ((DMAC_CH_Type*) &DMAC->CH[2]) /* 0x402A1200 */ +#define DMAC_CH3 ((DMAC_CH_Type*) &DMAC->CH[3]) /* 0x402A1300 */ + +/******************************************************************************* +* EFUSE +*******************************************************************************/ + +#define EFUSE_BASE 0x402C0000UL +#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ + +/******************************************************************************* +* PROFILE +*******************************************************************************/ + +#define PROFILE_BASE 0x402D0000UL +#define PROFILE ((PROFILE_Type*) PROFILE_BASE) /* 0x402D0000 */ +#define PROFILE_CNT_STRUCT0 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[0]) /* 0x402D0800 */ +#define PROFILE_CNT_STRUCT1 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[1]) /* 0x402D0810 */ +#define PROFILE_CNT_STRUCT2 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[2]) /* 0x402D0820 */ +#define PROFILE_CNT_STRUCT3 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[3]) /* 0x402D0830 */ +#define PROFILE_CNT_STRUCT4 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[4]) /* 0x402D0840 */ +#define PROFILE_CNT_STRUCT5 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[5]) /* 0x402D0850 */ +#define PROFILE_CNT_STRUCT6 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[6]) /* 0x402D0860 */ +#define PROFILE_CNT_STRUCT7 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[7]) /* 0x402D0870 */ + +/******************************************************************************* +* HSIOM +*******************************************************************************/ + +#define HSIOM_BASE 0x40300000UL +#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40300000 */ +#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40300000 */ +#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40300010 */ +#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40300020 */ +#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40300030 */ +#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40300040 */ +#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40300050 */ +#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40300060 */ +#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40300070 */ +#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40300080 */ +#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40300090 */ +#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403000A0 */ +#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403000B0 */ +#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403000C0 */ +#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403000D0 */ +#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403000E0 */ + +/******************************************************************************* +* GPIO +*******************************************************************************/ + +#define GPIO_BASE 0x40310000UL +#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40310000 */ +#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40310000 */ +#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40310080 */ +#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40310100 */ +#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40310180 */ +#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40310200 */ +#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40310280 */ +#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40310300 */ +#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40310380 */ +#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40310400 */ +#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40310480 */ +#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40310500 */ +#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40310580 */ +#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40310600 */ +#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40310680 */ +#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40310700 */ + +/******************************************************************************* +* SMARTIO +*******************************************************************************/ + +#define SMARTIO_BASE 0x40320000UL +#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40320000 */ +#define SMARTIO_PRT8 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[8]) /* 0x40320800 */ +#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40320900 */ + +/******************************************************************************* +* LPCOMP +*******************************************************************************/ + +#define LPCOMP_BASE 0x40350000UL +#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */ + +/******************************************************************************* +* CSD +*******************************************************************************/ + +#define CSD0_BASE 0x40360000UL +#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */ + +/******************************************************************************* +* TCPWM +*******************************************************************************/ + +#define TCPWM0_BASE 0x40380000UL +#define TCPWM1_BASE 0x40390000UL +#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM1 ((TCPWM_Type*) TCPWM1_BASE) /* 0x40390000 */ +#define TCPWM0_CNT0 ((TCPWM_CNT_Type*) &TCPWM0->CNT[0]) /* 0x40380100 */ +#define TCPWM0_CNT1 ((TCPWM_CNT_Type*) &TCPWM0->CNT[1]) /* 0x40380140 */ +#define TCPWM0_CNT2 ((TCPWM_CNT_Type*) &TCPWM0->CNT[2]) /* 0x40380180 */ +#define TCPWM0_CNT3 ((TCPWM_CNT_Type*) &TCPWM0->CNT[3]) /* 0x403801C0 */ +#define TCPWM0_CNT4 ((TCPWM_CNT_Type*) &TCPWM0->CNT[4]) /* 0x40380200 */ +#define TCPWM0_CNT5 ((TCPWM_CNT_Type*) &TCPWM0->CNT[5]) /* 0x40380240 */ +#define TCPWM0_CNT6 ((TCPWM_CNT_Type*) &TCPWM0->CNT[6]) /* 0x40380280 */ +#define TCPWM0_CNT7 ((TCPWM_CNT_Type*) &TCPWM0->CNT[7]) /* 0x403802C0 */ +#define TCPWM1_CNT0 ((TCPWM_CNT_Type*) &TCPWM1->CNT[0]) /* 0x40390100 */ +#define TCPWM1_CNT1 ((TCPWM_CNT_Type*) &TCPWM1->CNT[1]) /* 0x40390140 */ +#define TCPWM1_CNT2 ((TCPWM_CNT_Type*) &TCPWM1->CNT[2]) /* 0x40390180 */ +#define TCPWM1_CNT3 ((TCPWM_CNT_Type*) &TCPWM1->CNT[3]) /* 0x403901C0 */ +#define TCPWM1_CNT4 ((TCPWM_CNT_Type*) &TCPWM1->CNT[4]) /* 0x40390200 */ +#define TCPWM1_CNT5 ((TCPWM_CNT_Type*) &TCPWM1->CNT[5]) /* 0x40390240 */ +#define TCPWM1_CNT6 ((TCPWM_CNT_Type*) &TCPWM1->CNT[6]) /* 0x40390280 */ +#define TCPWM1_CNT7 ((TCPWM_CNT_Type*) &TCPWM1->CNT[7]) /* 0x403902C0 */ +#define TCPWM1_CNT8 ((TCPWM_CNT_Type*) &TCPWM1->CNT[8]) /* 0x40390300 */ +#define TCPWM1_CNT9 ((TCPWM_CNT_Type*) &TCPWM1->CNT[9]) /* 0x40390340 */ +#define TCPWM1_CNT10 ((TCPWM_CNT_Type*) &TCPWM1->CNT[10]) /* 0x40390380 */ +#define TCPWM1_CNT11 ((TCPWM_CNT_Type*) &TCPWM1->CNT[11]) /* 0x403903C0 */ +#define TCPWM1_CNT12 ((TCPWM_CNT_Type*) &TCPWM1->CNT[12]) /* 0x40390400 */ +#define TCPWM1_CNT13 ((TCPWM_CNT_Type*) &TCPWM1->CNT[13]) /* 0x40390440 */ +#define TCPWM1_CNT14 ((TCPWM_CNT_Type*) &TCPWM1->CNT[14]) /* 0x40390480 */ +#define TCPWM1_CNT15 ((TCPWM_CNT_Type*) &TCPWM1->CNT[15]) /* 0x403904C0 */ +#define TCPWM1_CNT16 ((TCPWM_CNT_Type*) &TCPWM1->CNT[16]) /* 0x40390500 */ +#define TCPWM1_CNT17 ((TCPWM_CNT_Type*) &TCPWM1->CNT[17]) /* 0x40390540 */ +#define TCPWM1_CNT18 ((TCPWM_CNT_Type*) &TCPWM1->CNT[18]) /* 0x40390580 */ +#define TCPWM1_CNT19 ((TCPWM_CNT_Type*) &TCPWM1->CNT[19]) /* 0x403905C0 */ +#define TCPWM1_CNT20 ((TCPWM_CNT_Type*) &TCPWM1->CNT[20]) /* 0x40390600 */ +#define TCPWM1_CNT21 ((TCPWM_CNT_Type*) &TCPWM1->CNT[21]) /* 0x40390640 */ +#define TCPWM1_CNT22 ((TCPWM_CNT_Type*) &TCPWM1->CNT[22]) /* 0x40390680 */ +#define TCPWM1_CNT23 ((TCPWM_CNT_Type*) &TCPWM1->CNT[23]) /* 0x403906C0 */ + +/******************************************************************************* +* LCD +*******************************************************************************/ + +#define LCD0_BASE 0x403B0000UL +#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ + +/******************************************************************************* +* USBFS +*******************************************************************************/ + +#define USBFS0_BASE 0x403F0000UL +#define USBFS0 ((USBFS_Type*) USBFS0_BASE) /* 0x403F0000 */ +#define USBFS0_USBDEV ((USBFS_USBDEV_Type*) &USBFS0->USBDEV) /* 0x403F0000 */ +#define USBFS0_USBLPM ((USBFS_USBLPM_Type*) &USBFS0->USBLPM) /* 0x403F2000 */ +#define USBFS0_USBHOST ((USBFS_USBHOST_Type*) &USBFS0->USBHOST) /* 0x403F4000 */ + +/******************************************************************************* +* SMIF +*******************************************************************************/ + +#define SMIF0_BASE 0x40420000UL +#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ +#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ +#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ +#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ +#define SMIF0_DEVICE3 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[3]) /* 0x40420980 */ + +/******************************************************************************* +* SDHC +*******************************************************************************/ + +#define SDHC0_BASE 0x40460000UL +#define SDHC1_BASE 0x40470000UL +#define SDHC0 ((SDHC_Type*) SDHC0_BASE) /* 0x40460000 */ +#define SDHC1 ((SDHC_Type*) SDHC1_BASE) /* 0x40470000 */ +#define SDHC0_WRAP ((SDHC_WRAP_Type*) &SDHC0->WRAP) /* 0x40460000 */ +#define SDHC1_WRAP ((SDHC_WRAP_Type*) &SDHC1->WRAP) /* 0x40470000 */ +#define SDHC0_CORE ((SDHC_CORE_Type*) &SDHC0->CORE) /* 0x40461000 */ +#define SDHC1_CORE ((SDHC_CORE_Type*) &SDHC1->CORE) /* 0x40471000 */ + +/******************************************************************************* +* SCB +*******************************************************************************/ + +#define SCB0_BASE 0x40600000UL +#define SCB1_BASE 0x40610000UL +#define SCB2_BASE 0x40620000UL +#define SCB3_BASE 0x40630000UL +#define SCB4_BASE 0x40640000UL +#define SCB5_BASE 0x40650000UL +#define SCB6_BASE 0x40660000UL +#define SCB7_BASE 0x40670000UL +#define SCB8_BASE 0x40680000UL +#define SCB9_BASE 0x40690000UL +#define SCB10_BASE 0x406A0000UL +#define SCB11_BASE 0x406B0000UL +#define SCB12_BASE 0x406C0000UL +#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40600000 */ +#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40610000 */ +#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40620000 */ +#define SCB3 ((CySCB_Type*) SCB3_BASE) /* 0x40630000 */ +#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40640000 */ +#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40650000 */ +#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40660000 */ +#define SCB7 ((CySCB_Type*) SCB7_BASE) /* 0x40670000 */ +#define SCB8 ((CySCB_Type*) SCB8_BASE) /* 0x40680000 */ +#define SCB9 ((CySCB_Type*) SCB9_BASE) /* 0x40690000 */ +#define SCB10 ((CySCB_Type*) SCB10_BASE) /* 0x406A0000 */ +#define SCB11 ((CySCB_Type*) SCB11_BASE) /* 0x406B0000 */ +#define SCB12 ((CySCB_Type*) SCB12_BASE) /* 0x406C0000 */ + +/******************************************************************************* +* SAR +*******************************************************************************/ + +#define SAR_BASE 0x409D0000UL +#define SAR ((SAR_Type*) SAR_BASE) /* 0x409D0000 */ + +/******************************************************************************* +* PASS +*******************************************************************************/ + +#define PASS_BASE 0x409F0000UL +#define PASS ((PASS_Type*) PASS_BASE) /* 0x409F0000 */ +#define PASS_AREF ((PASS_AREF_Type*) &PASS->AREF) /* 0x409F0E00 */ + +/******************************************************************************* +* PDM +*******************************************************************************/ + +#define PDM0_BASE 0x40A00000UL +#define PDM0 ((PDM_Type*) PDM0_BASE) /* 0x40A00000 */ + +/******************************************************************************* +* I2S +*******************************************************************************/ + +#define I2S0_BASE 0x40A10000UL +#define I2S1_BASE 0x40A11000UL +#define I2S0 ((I2S_Type*) I2S0_BASE) /* 0x40A10000 */ +#define I2S1 ((I2S_Type*) I2S1_BASE) /* 0x40A11000 */ + +/** \} CY8C614AAZI-S2F44 */ + +#endif /* _CY8C614AAZI_S2F44_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c614abzi_s2f04.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c614abzi_s2f04.h new file mode 100644 index 0000000000..7cc7d8c923 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c614abzi_s2f04.h @@ -0,0 +1,1088 @@ +/***************************************************************************//** +* \file cy8c614abzi_s2f04.h +* +* \brief +* CY8C614ABZI-S2F04 device header +* +* \note +* Generator version: 1.6.0.225 +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CY8C614ABZI_S2F04_H_ +#define _CY8C614ABZI_S2F04_H_ + +/** +* \addtogroup group_device CY8C614ABZI-S2F04 +* \{ +*/ + +/** +* \addtogroup Configuration_of_CMSIS +* \{ +*/ + +/******************************************************************************* +* Interrupt Number Definition +*******************************************************************************/ + +typedef enum { + /* ARM Cortex-M4 Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C614ABZI-S2F04 Peripheral Interrupt Numbers */ + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_1_IRQn = 1, /*!< 1 [DeepSleep] GPIO Port Interrupt #1 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_4_IRQn = 4, /*!< 4 [DeepSleep] GPIO Port Interrupt #4 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_13_IRQn = 13, /*!< 13 [DeepSleep] GPIO Port Interrupt #13 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_8_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #8 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + scb_6_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #6 */ + scb_7_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #7 */ + scb_9_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #9 */ + scb_10_interrupt_IRQn = 48, /*!< 48 [Active] Serial Communication Block #10 */ + scb_11_interrupt_IRQn = 49, /*!< 49 [Active] Serial Communication Block #11 */ + scb_12_interrupt_IRQn = 50, /*!< 50 [Active] Serial Communication Block #12 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dmac_2_IRQn = 54, /*!< 54 [Active] CPUSS DMAC, Channel #2 */ + cpuss_interrupts_dmac_3_IRQn = 55, /*!< 55 [Active] CPUSS DMAC, Channel #3 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_0_interrupts_4_IRQn = 127, /*!< 127 [Active] TCPWM #0, Counter #4 */ + tcpwm_0_interrupts_5_IRQn = 128, /*!< 128 [Active] TCPWM #0, Counter #5 */ + tcpwm_0_interrupts_6_IRQn = 129, /*!< 129 [Active] TCPWM #0, Counter #6 */ + tcpwm_0_interrupts_7_IRQn = 130, /*!< 130 [Active] TCPWM #0, Counter #7 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + tcpwm_1_interrupts_8_IRQn = 139, /*!< 139 [Active] TCPWM #1, Counter #8 */ + tcpwm_1_interrupts_9_IRQn = 140, /*!< 140 [Active] TCPWM #1, Counter #9 */ + tcpwm_1_interrupts_10_IRQn = 141, /*!< 141 [Active] TCPWM #1, Counter #10 */ + tcpwm_1_interrupts_11_IRQn = 142, /*!< 142 [Active] TCPWM #1, Counter #11 */ + tcpwm_1_interrupts_12_IRQn = 143, /*!< 143 [Active] TCPWM #1, Counter #12 */ + tcpwm_1_interrupts_13_IRQn = 144, /*!< 144 [Active] TCPWM #1, Counter #13 */ + tcpwm_1_interrupts_14_IRQn = 145, /*!< 145 [Active] TCPWM #1, Counter #14 */ + tcpwm_1_interrupts_15_IRQn = 146, /*!< 146 [Active] TCPWM #1, Counter #15 */ + tcpwm_1_interrupts_16_IRQn = 147, /*!< 147 [Active] TCPWM #1, Counter #16 */ + tcpwm_1_interrupts_17_IRQn = 148, /*!< 148 [Active] TCPWM #1, Counter #17 */ + tcpwm_1_interrupts_18_IRQn = 149, /*!< 149 [Active] TCPWM #1, Counter #18 */ + tcpwm_1_interrupts_19_IRQn = 150, /*!< 150 [Active] TCPWM #1, Counter #19 */ + tcpwm_1_interrupts_20_IRQn = 151, /*!< 151 [Active] TCPWM #1, Counter #20 */ + tcpwm_1_interrupts_21_IRQn = 152, /*!< 152 [Active] TCPWM #1, Counter #21 */ + tcpwm_1_interrupts_22_IRQn = 153, /*!< 153 [Active] TCPWM #1, Counter #22 */ + tcpwm_1_interrupts_23_IRQn = 154, /*!< 154 [Active] TCPWM #1, Counter #23 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + audioss_0_interrupt_i2s_IRQn = 156, /*!< 156 [Active] I2S0 Audio interrupt */ + audioss_0_interrupt_pdm_IRQn = 157, /*!< 157 [Active] PDM0/PCM0 Audio interrupt */ + audioss_1_interrupt_i2s_IRQn = 158, /*!< 158 [Active] I2S1 Audio interrupt */ + profile_interrupt_IRQn = 159, /*!< 159 [Active] Energy Profiler interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + sdhc_1_interrupt_wakeup_IRQn = 166, /*!< 166 [Active] EEMC wakeup interrupt for mxsdhc, not used */ + sdhc_1_interrupt_general_IRQn = 167, /*!< 167 [Active] Consolidated interrupt for mxsdhc for everything else */ + unconnected_IRQn = 240 /*!< 240 Unconnected */ +} IRQn_Type; + + +/******************************************************************************* +* Processor and Core Peripheral Section +*******************************************************************************/ + +/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __CM0P_PRESENT 0 /*!< CM0P present or not */ +#define __DTCM_PRESENT 0 /*!< DTCM present or not */ +#define __ICACHE_PRESENT 0 /*!< ICACHE present or not */ +#define __DCACHE_PRESENT 0 /*!< DCACHE present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + + +/* Memory Blocks */ +#define CY_ROM_BASE 0x00000000UL +#define CY_ROM_SIZE 0x00010000UL +#define CY_SRAM_BASE 0x08000000UL +#define CY_SRAM_SIZE 0x00100000UL +#define CY_FLASH_BASE 0x10000000UL +#define CY_FLASH_SIZE 0x00200000UL +#define CY_EM_EEPROM_BASE 0x14000000UL +#define CY_EM_EEPROM_SIZE 0x00008000UL +#define CY_SFLASH_BASE 0x16000000UL +#define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL +#define CY_EFUSE_BASE 0x402C0800UL +#define CY_EFUSE_SIZE 0x00000200UL + +#include "system_psoc6.h" /*!< PSoC 6 System */ + +/* IP List */ +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 2u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_M4CPUSS 1u +#define CY_IP_M4CPUSS_INSTANCES 1u +#define CY_IP_M4CPUSS_VERSION 2u +#define CY_IP_M4CPUSS_DMAC 1u +#define CY_IP_M4CPUSS_DMAC_INSTANCES 1u +#define CY_IP_M4CPUSS_DMAC_VERSION 2u +#define CY_IP_M4CPUSS_DMA 1u +#define CY_IP_M4CPUSS_DMA_INSTANCES 2u +#define CY_IP_M4CPUSS_DMA_VERSION 2u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u +#define CY_IP_MXS40PASS 1u +#define CY_IP_MXS40PASS_INSTANCES 1u +#define CY_IP_MXS40PASS_VERSION 1u +#define CY_IP_MXS40PASS_SAR 1u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u +#define CY_IP_MXS40PASS_SAR_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXPROFILE 1u +#define CY_IP_MXPROFILE_INSTANCES 1u +#define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 13u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 2u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u + +#include "psoc6_02_config.h" +#include "gpio_psoc6_02_124_bga.h" + +#define CY_DEVICE_PSOC6A2M +#define CY_SILICON_ID 0xE45A1202UL +#define CY_HF_CLK_MAX_FREQ 150000000UL + +#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL + +/******************************************************************************* +* SFLASH +*******************************************************************************/ + +#define SFLASH_BASE 0x16000000UL +#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */ + +/******************************************************************************* +* PERI +*******************************************************************************/ + +#define PERI_BASE 0x40000000UL +#define PERI ((PERI_Type*) PERI_BASE) /* 0x40000000 */ +#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40004000 */ +#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40004020 */ +#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40004040 */ +#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x40004060 */ +#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40004080 */ +#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x400040C0 */ +#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40004120 */ +#define PERI_GR10 ((PERI_GR_Type*) &PERI->GR[10]) /* 0x40004140 */ +#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40008000 */ +#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40008400 */ +#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40008800 */ +#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40008C00 */ +#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40009000 */ +#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40009400 */ +#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40009800 */ +#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40009C00 */ +#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ +#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ +#define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ +#define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ +#define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ +#define PERI_TR_1TO1_GR3 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[3]) /* 0x4000CC00 */ +#define PERI_TR_1TO1_GR4 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[4]) /* 0x4000D000 */ +#define PERI_TR_1TO1_GR5 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[5]) /* 0x4000D400 */ +#define PERI_TR_1TO1_GR6 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[6]) /* 0x4000D800 */ + +/******************************************************************************* +* PERI_MS +*******************************************************************************/ + +#define PERI_MS_BASE 0x40010000UL +#define PERI_MS ((PERI_MS_Type*) PERI_MS_BASE) /* 0x40010000 */ +#define PERI_MS_PPU_PR0 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[0]) /* 0x40010000 */ +#define PERI_MS_PPU_PR1 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[1]) /* 0x40010040 */ +#define PERI_MS_PPU_PR2 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[2]) /* 0x40010080 */ +#define PERI_MS_PPU_PR3 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[3]) /* 0x400100C0 */ +#define PERI_MS_PPU_PR4 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[4]) /* 0x40010100 */ +#define PERI_MS_PPU_PR5 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[5]) /* 0x40010140 */ +#define PERI_MS_PPU_PR6 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[6]) /* 0x40010180 */ +#define PERI_MS_PPU_PR7 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[7]) /* 0x400101C0 */ +#define PERI_MS_PPU_FX_PERI_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[0]) /* 0x40010800 */ +#define PERI_MS_PPU_FX_PERI_GR0_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[1]) /* 0x40010840 */ +#define PERI_MS_PPU_FX_PERI_GR1_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[2]) /* 0x40010880 */ +#define PERI_MS_PPU_FX_PERI_GR2_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[3]) /* 0x400108C0 */ +#define PERI_MS_PPU_FX_PERI_GR3_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[4]) /* 0x40010900 */ +#define PERI_MS_PPU_FX_PERI_GR4_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[5]) /* 0x40010940 */ +#define PERI_MS_PPU_FX_PERI_GR6_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[6]) /* 0x40010980 */ +#define PERI_MS_PPU_FX_PERI_GR9_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[7]) /* 0x400109C0 */ +#define PERI_MS_PPU_FX_PERI_GR10_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[8]) /* 0x40010A00 */ +#define PERI_MS_PPU_FX_PERI_TR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[9]) /* 0x40010A40 */ +#define PERI_MS_PPU_FX_CRYPTO_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[10]) /* 0x40010A80 */ +#define PERI_MS_PPU_FX_CRYPTO_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[11]) /* 0x40010AC0 */ +#define PERI_MS_PPU_FX_CRYPTO_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[12]) /* 0x40010B00 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[13]) /* 0x40010B40 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[14]) /* 0x40010B80 */ +#define PERI_MS_PPU_FX_CRYPTO_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[15]) /* 0x40010BC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[16]) /* 0x40010C00 */ +#define PERI_MS_PPU_FX_CPUSS_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[17]) /* 0x40010C40 */ +#define PERI_MS_PPU_FX_CPUSS_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[18]) /* 0x40010C80 */ +#define PERI_MS_PPU_FX_CPUSS_CM0_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[19]) /* 0x40010CC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[20]) /* 0x40010D00 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[21]) /* 0x40010D40 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT1_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[22]) /* 0x40010D80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT0_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[23]) /* 0x40010DC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT1_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[24]) /* 0x40010E00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT2_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[25]) /* 0x40010E40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT3_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[26]) /* 0x40010E80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT4_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[27]) /* 0x40010EC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT5_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[28]) /* 0x40010F00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT6_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[29]) /* 0x40010F40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT7_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[30]) /* 0x40010F80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT8_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[31]) /* 0x40010FC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT9_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[32]) /* 0x40011000 */ +#define PERI_MS_PPU_FX_IPC_STRUCT10_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[33]) /* 0x40011040 */ +#define PERI_MS_PPU_FX_IPC_STRUCT11_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[34]) /* 0x40011080 */ +#define PERI_MS_PPU_FX_IPC_STRUCT12_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[35]) /* 0x400110C0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT13_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[36]) /* 0x40011100 */ +#define PERI_MS_PPU_FX_IPC_STRUCT14_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[37]) /* 0x40011140 */ +#define PERI_MS_PPU_FX_IPC_STRUCT15_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[38]) /* 0x40011180 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT0_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[39]) /* 0x400111C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT1_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[40]) /* 0x40011200 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT2_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[41]) /* 0x40011240 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT3_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[42]) /* 0x40011280 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT4_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[43]) /* 0x400112C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT5_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[44]) /* 0x40011300 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT6_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[45]) /* 0x40011340 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT7_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[46]) /* 0x40011380 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT8_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[47]) /* 0x400113C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT9_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[48]) /* 0x40011400 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT10_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[49]) /* 0x40011440 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT11_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[50]) /* 0x40011480 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT12_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[51]) /* 0x400114C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT13_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[52]) /* 0x40011500 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT14_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[53]) /* 0x40011540 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT15_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[54]) /* 0x40011580 */ +#define PERI_MS_PPU_FX_PROT_SMPU_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[55]) /* 0x400115C0 */ +#define PERI_MS_PPU_FX_PROT_MPU0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[56]) /* 0x40011600 */ +#define PERI_MS_PPU_FX_PROT_MPU5_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[57]) /* 0x40011640 */ +#define PERI_MS_PPU_FX_PROT_MPU6_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[58]) /* 0x40011680 */ +#define PERI_MS_PPU_FX_PROT_MPU14_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[59]) /* 0x400116C0 */ +#define PERI_MS_PPU_FX_PROT_MPU15_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[60]) /* 0x40011700 */ +#define PERI_MS_PPU_FX_FLASHC_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[61]) /* 0x40011740 */ +#define PERI_MS_PPU_FX_FLASHC_CMD ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[62]) /* 0x40011780 */ +#define PERI_MS_PPU_FX_FLASHC_DFT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[63]) /* 0x400117C0 */ +#define PERI_MS_PPU_FX_FLASHC_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[64]) /* 0x40011800 */ +#define PERI_MS_PPU_FX_FLASHC_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[65]) /* 0x40011840 */ +#define PERI_MS_PPU_FX_FLASHC_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[66]) /* 0x40011880 */ +#define PERI_MS_PPU_FX_FLASHC_DW0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[67]) /* 0x400118C0 */ +#define PERI_MS_PPU_FX_FLASHC_DW1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[68]) /* 0x40011900 */ +#define PERI_MS_PPU_FX_FLASHC_DMAC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[69]) /* 0x40011940 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[70]) /* 0x40011980 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[71]) /* 0x400119C0 */ +#define PERI_MS_PPU_FX_FLASHC_FM ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[72]) /* 0x40011A00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[73]) /* 0x40011A40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[74]) /* 0x40011A80 */ +#define PERI_MS_PPU_FX_WDT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[75]) /* 0x40011AC0 */ +#define PERI_MS_PPU_FX_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[76]) /* 0x40011B00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[77]) /* 0x40011B40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[78]) /* 0x40011B80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[79]) /* 0x40011BC0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[80]) /* 0x40011C00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[81]) /* 0x40011C40 */ +#define PERI_MS_PPU_FX_BACKUP_BACKUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[82]) /* 0x40011C80 */ +#define PERI_MS_PPU_FX_DW0_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[83]) /* 0x40011CC0 */ +#define PERI_MS_PPU_FX_DW1_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[84]) /* 0x40011D00 */ +#define PERI_MS_PPU_FX_DW0_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[85]) /* 0x40011D40 */ +#define PERI_MS_PPU_FX_DW1_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[86]) /* 0x40011D80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[87]) /* 0x40011DC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[88]) /* 0x40011E00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[89]) /* 0x40011E40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[90]) /* 0x40011E80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[91]) /* 0x40011EC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[92]) /* 0x40011F00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[93]) /* 0x40011F40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[94]) /* 0x40011F80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[95]) /* 0x40011FC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[96]) /* 0x40012000 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[97]) /* 0x40012040 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[98]) /* 0x40012080 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[99]) /* 0x400120C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[100]) /* 0x40012100 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[101]) /* 0x40012140 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[102]) /* 0x40012180 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[103]) /* 0x400121C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[104]) /* 0x40012200 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[105]) /* 0x40012240 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[106]) /* 0x40012280 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[107]) /* 0x400122C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[108]) /* 0x40012300 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[109]) /* 0x40012340 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[110]) /* 0x40012380 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[111]) /* 0x400123C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[112]) /* 0x40012400 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[113]) /* 0x40012440 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[114]) /* 0x40012480 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[115]) /* 0x400124C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[116]) /* 0x40012500 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[117]) /* 0x40012540 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[118]) /* 0x40012580 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[119]) /* 0x400125C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[120]) /* 0x40012600 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[121]) /* 0x40012640 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[122]) /* 0x40012680 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[123]) /* 0x400126C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[124]) /* 0x40012700 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[125]) /* 0x40012740 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[126]) /* 0x40012780 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[127]) /* 0x400127C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[128]) /* 0x40012800 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[129]) /* 0x40012840 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[130]) /* 0x40012880 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[131]) /* 0x400128C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[132]) /* 0x40012900 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[133]) /* 0x40012940 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[134]) /* 0x40012980 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[135]) /* 0x400129C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[136]) /* 0x40012A00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[137]) /* 0x40012A40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[138]) /* 0x40012A80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[139]) /* 0x40012AC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[140]) /* 0x40012B00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[141]) /* 0x40012B40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[142]) /* 0x40012B80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[143]) /* 0x40012BC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[144]) /* 0x40012C00 */ +#define PERI_MS_PPU_FX_DMAC_TOP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[145]) /* 0x40012C40 */ +#define PERI_MS_PPU_FX_DMAC_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[146]) /* 0x40012C80 */ +#define PERI_MS_PPU_FX_DMAC_CH1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[147]) /* 0x40012CC0 */ +#define PERI_MS_PPU_FX_DMAC_CH2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[148]) /* 0x40012D00 */ +#define PERI_MS_PPU_FX_DMAC_CH3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[149]) /* 0x40012D40 */ +#define PERI_MS_PPU_FX_EFUSE_CTL ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[150]) /* 0x40012D80 */ +#define PERI_MS_PPU_FX_EFUSE_DATA ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[151]) /* 0x40012DC0 */ +#define PERI_MS_PPU_FX_PROFILE ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[152]) /* 0x40012E00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[153]) /* 0x40012E40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[154]) /* 0x40012E80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[155]) /* 0x40012EC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[156]) /* 0x40012F00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[157]) /* 0x40012F40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[158]) /* 0x40012F80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[159]) /* 0x40012FC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[160]) /* 0x40013000 */ +#define PERI_MS_PPU_FX_HSIOM_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[161]) /* 0x40013040 */ +#define PERI_MS_PPU_FX_HSIOM_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[162]) /* 0x40013080 */ +#define PERI_MS_PPU_FX_HSIOM_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[163]) /* 0x400130C0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[164]) /* 0x40013100 */ +#define PERI_MS_PPU_FX_HSIOM_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[165]) /* 0x40013140 */ +#define PERI_MS_PPU_FX_HSIOM_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[166]) /* 0x40013180 */ +#define PERI_MS_PPU_FX_HSIOM_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[167]) /* 0x400131C0 */ +#define PERI_MS_PPU_FX_HSIOM_AMUX ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[168]) /* 0x40013200 */ +#define PERI_MS_PPU_FX_HSIOM_MON ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[169]) /* 0x40013240 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[170]) /* 0x40013280 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[171]) /* 0x400132C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[172]) /* 0x40013300 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[173]) /* 0x40013340 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[174]) /* 0x40013380 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[175]) /* 0x400133C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[176]) /* 0x40013400 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[177]) /* 0x40013440 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[178]) /* 0x40013480 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[179]) /* 0x400134C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[180]) /* 0x40013500 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[181]) /* 0x40013540 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[182]) /* 0x40013580 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[183]) /* 0x400135C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[184]) /* 0x40013600 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[185]) /* 0x40013640 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[186]) /* 0x40013680 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[187]) /* 0x400136C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[188]) /* 0x40013700 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[189]) /* 0x40013740 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[190]) /* 0x40013780 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[191]) /* 0x400137C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[192]) /* 0x40013800 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[193]) /* 0x40013840 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[194]) /* 0x40013880 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[195]) /* 0x400138C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[196]) /* 0x40013900 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[197]) /* 0x40013940 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[198]) /* 0x40013980 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[199]) /* 0x400139C0 */ +#define PERI_MS_PPU_FX_GPIO_GPIO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[200]) /* 0x40013A00 */ +#define PERI_MS_PPU_FX_GPIO_TEST ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[201]) /* 0x40013A40 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[202]) /* 0x40013A80 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[203]) /* 0x40013AC0 */ +#define PERI_MS_PPU_FX_LPCOMP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[204]) /* 0x40013B00 */ +#define PERI_MS_PPU_FX_CSD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[205]) /* 0x40013B40 */ +#define PERI_MS_PPU_FX_TCPWM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[206]) /* 0x40013B80 */ +#define PERI_MS_PPU_FX_TCPWM1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[207]) /* 0x40013BC0 */ +#define PERI_MS_PPU_FX_LCD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[208]) /* 0x40013C00 */ +#define PERI_MS_PPU_FX_USBFS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[209]) /* 0x40013C40 */ +#define PERI_MS_PPU_FX_SMIF0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[210]) /* 0x40013C80 */ +#define PERI_MS_PPU_FX_SDHC0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[211]) /* 0x40013CC0 */ +#define PERI_MS_PPU_FX_SDHC1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[212]) /* 0x40013D00 */ +#define PERI_MS_PPU_FX_SCB0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[213]) /* 0x40013D40 */ +#define PERI_MS_PPU_FX_SCB1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[214]) /* 0x40013D80 */ +#define PERI_MS_PPU_FX_SCB2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[215]) /* 0x40013DC0 */ +#define PERI_MS_PPU_FX_SCB3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[216]) /* 0x40013E00 */ +#define PERI_MS_PPU_FX_SCB4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[217]) /* 0x40013E40 */ +#define PERI_MS_PPU_FX_SCB5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[218]) /* 0x40013E80 */ +#define PERI_MS_PPU_FX_SCB6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[219]) /* 0x40013EC0 */ +#define PERI_MS_PPU_FX_SCB7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[220]) /* 0x40013F00 */ +#define PERI_MS_PPU_FX_SCB8 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[221]) /* 0x40013F40 */ +#define PERI_MS_PPU_FX_SCB9 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[222]) /* 0x40013F80 */ +#define PERI_MS_PPU_FX_SCB10 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[223]) /* 0x40013FC0 */ +#define PERI_MS_PPU_FX_SCB11 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[224]) /* 0x40014000 */ +#define PERI_MS_PPU_FX_SCB12 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[225]) /* 0x40014040 */ +#define PERI_MS_PPU_FX_PDM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[226]) /* 0x40014080 */ +#define PERI_MS_PPU_FX_I2S0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[227]) /* 0x400140C0 */ +#define PERI_MS_PPU_FX_I2S1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[228]) /* 0x40014100 */ + +/******************************************************************************* +* CPUSS +*******************************************************************************/ + +#define CPUSS_BASE 0x40200000UL +#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40200000 */ + +/******************************************************************************* +* FAULT +*******************************************************************************/ + +#define FAULT_BASE 0x40210000UL +#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40210000 */ +#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40210000 */ +#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40210100 */ + +/******************************************************************************* +* IPC +*******************************************************************************/ + +#define IPC_BASE 0x40220000UL +#define IPC ((IPC_Type*) IPC_BASE) /* 0x40220000 */ +#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40220000 */ +#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40220020 */ +#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40220040 */ +#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40220060 */ +#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40220080 */ +#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402200A0 */ +#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402200C0 */ +#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402200E0 */ +#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40220100 */ +#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40220120 */ +#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40220140 */ +#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40220160 */ +#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40220180 */ +#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402201A0 */ +#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402201C0 */ +#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402201E0 */ +#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40221000 */ +#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40221020 */ +#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40221040 */ +#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40221060 */ +#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40221080 */ +#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402210A0 */ +#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402210C0 */ +#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402210E0 */ +#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40221100 */ +#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40221120 */ +#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40221140 */ +#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40221160 */ +#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40221180 */ +#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402211A0 */ +#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402211C0 */ +#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402211E0 */ + +/******************************************************************************* +* PROT +*******************************************************************************/ + +#define PROT_BASE 0x40230000UL +#define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ +#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ +#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ +#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402320C0 */ +#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40232100 */ +#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40232140 */ +#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40232180 */ +#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402321C0 */ +#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40232200 */ +#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40232240 */ +#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40232280 */ +#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402322C0 */ +#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40232300 */ +#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ +#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ +#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ +#define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ +#define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ +#define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ +#define PROT_MPU5_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[3]) /* 0x40235660 */ +#define PROT_MPU5_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[4]) /* 0x40235680 */ +#define PROT_MPU5_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[5]) /* 0x402356A0 */ +#define PROT_MPU5_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[6]) /* 0x402356C0 */ +#define PROT_MPU5_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[7]) /* 0x402356E0 */ +#define PROT_MPU6_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[0]) /* 0x40235A00 */ +#define PROT_MPU6_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[1]) /* 0x40235A20 */ +#define PROT_MPU6_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[2]) /* 0x40235A40 */ +#define PROT_MPU6_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[3]) /* 0x40235A60 */ +#define PROT_MPU6_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[4]) /* 0x40235A80 */ +#define PROT_MPU6_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[5]) /* 0x40235AA0 */ +#define PROT_MPU6_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[6]) /* 0x40235AC0 */ +#define PROT_MPU6_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[7]) /* 0x40235AE0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ + +/******************************************************************************* +* FLASHC +*******************************************************************************/ + +#define FLASHC_BASE 0x40240000UL +#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40240000 */ +#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4024F000 */ + +/******************************************************************************* +* SRSS +*******************************************************************************/ + +#define SRSS_BASE 0x40260000UL +#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ +#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */ +#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */ + +/******************************************************************************* +* BACKUP +*******************************************************************************/ + +#define BACKUP_BASE 0x40270000UL +#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ + +/******************************************************************************* +* DW +*******************************************************************************/ + +#define DW0_BASE 0x40280000UL +#define DW1_BASE 0x40290000UL +#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ +#define DW1 ((DW_Type*) DW1_BASE) /* 0x40290000 */ +#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40288000 */ +#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40288040 */ +#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40288080 */ +#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x402880C0 */ +#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40288100 */ +#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x40288140 */ +#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x40288180 */ +#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402881C0 */ +#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40288200 */ +#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40288240 */ +#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40288280 */ +#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x402882C0 */ +#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40288300 */ +#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x40288340 */ +#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x40288380 */ +#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402883C0 */ +#define DW0_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[16]) /* 0x40288400 */ +#define DW0_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[17]) /* 0x40288440 */ +#define DW0_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[18]) /* 0x40288480 */ +#define DW0_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[19]) /* 0x402884C0 */ +#define DW0_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[20]) /* 0x40288500 */ +#define DW0_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[21]) /* 0x40288540 */ +#define DW0_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[22]) /* 0x40288580 */ +#define DW0_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[23]) /* 0x402885C0 */ +#define DW0_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[24]) /* 0x40288600 */ +#define DW0_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[25]) /* 0x40288640 */ +#define DW0_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[26]) /* 0x40288680 */ +#define DW0_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[27]) /* 0x402886C0 */ +#define DW0_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[28]) /* 0x40288700 */ +#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40298000 */ +#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40298040 */ +#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40298080 */ +#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x402980C0 */ +#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40298100 */ +#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x40298140 */ +#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x40298180 */ +#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402981C0 */ +#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40298200 */ +#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40298240 */ +#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40298280 */ +#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x402982C0 */ +#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40298300 */ +#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x40298340 */ +#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x40298380 */ +#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402983C0 */ +#define DW1_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[16]) /* 0x40298400 */ +#define DW1_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[17]) /* 0x40298440 */ +#define DW1_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[18]) /* 0x40298480 */ +#define DW1_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[19]) /* 0x402984C0 */ +#define DW1_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[20]) /* 0x40298500 */ +#define DW1_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[21]) /* 0x40298540 */ +#define DW1_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[22]) /* 0x40298580 */ +#define DW1_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[23]) /* 0x402985C0 */ +#define DW1_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[24]) /* 0x40298600 */ +#define DW1_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[25]) /* 0x40298640 */ +#define DW1_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[26]) /* 0x40298680 */ +#define DW1_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[27]) /* 0x402986C0 */ +#define DW1_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[28]) /* 0x40298700 */ + +/******************************************************************************* +* DMAC +*******************************************************************************/ + +#define DMAC_BASE 0x402A0000UL +#define DMAC ((DMAC_Type*) DMAC_BASE) /* 0x402A0000 */ +#define DMAC_CH0 ((DMAC_CH_Type*) &DMAC->CH[0]) /* 0x402A1000 */ +#define DMAC_CH1 ((DMAC_CH_Type*) &DMAC->CH[1]) /* 0x402A1100 */ +#define DMAC_CH2 ((DMAC_CH_Type*) &DMAC->CH[2]) /* 0x402A1200 */ +#define DMAC_CH3 ((DMAC_CH_Type*) &DMAC->CH[3]) /* 0x402A1300 */ + +/******************************************************************************* +* EFUSE +*******************************************************************************/ + +#define EFUSE_BASE 0x402C0000UL +#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ + +/******************************************************************************* +* PROFILE +*******************************************************************************/ + +#define PROFILE_BASE 0x402D0000UL +#define PROFILE ((PROFILE_Type*) PROFILE_BASE) /* 0x402D0000 */ +#define PROFILE_CNT_STRUCT0 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[0]) /* 0x402D0800 */ +#define PROFILE_CNT_STRUCT1 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[1]) /* 0x402D0810 */ +#define PROFILE_CNT_STRUCT2 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[2]) /* 0x402D0820 */ +#define PROFILE_CNT_STRUCT3 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[3]) /* 0x402D0830 */ +#define PROFILE_CNT_STRUCT4 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[4]) /* 0x402D0840 */ +#define PROFILE_CNT_STRUCT5 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[5]) /* 0x402D0850 */ +#define PROFILE_CNT_STRUCT6 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[6]) /* 0x402D0860 */ +#define PROFILE_CNT_STRUCT7 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[7]) /* 0x402D0870 */ + +/******************************************************************************* +* HSIOM +*******************************************************************************/ + +#define HSIOM_BASE 0x40300000UL +#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40300000 */ +#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40300000 */ +#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40300010 */ +#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40300020 */ +#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40300030 */ +#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40300040 */ +#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40300050 */ +#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40300060 */ +#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40300070 */ +#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40300080 */ +#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40300090 */ +#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403000A0 */ +#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403000B0 */ +#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403000C0 */ +#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403000D0 */ +#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403000E0 */ + +/******************************************************************************* +* GPIO +*******************************************************************************/ + +#define GPIO_BASE 0x40310000UL +#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40310000 */ +#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40310000 */ +#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40310080 */ +#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40310100 */ +#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40310180 */ +#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40310200 */ +#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40310280 */ +#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40310300 */ +#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40310380 */ +#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40310400 */ +#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40310480 */ +#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40310500 */ +#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40310580 */ +#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40310600 */ +#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40310680 */ +#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40310700 */ + +/******************************************************************************* +* SMARTIO +*******************************************************************************/ + +#define SMARTIO_BASE 0x40320000UL +#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40320000 */ +#define SMARTIO_PRT8 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[8]) /* 0x40320800 */ +#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40320900 */ + +/******************************************************************************* +* LPCOMP +*******************************************************************************/ + +#define LPCOMP_BASE 0x40350000UL +#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */ + +/******************************************************************************* +* CSD +*******************************************************************************/ + +#define CSD0_BASE 0x40360000UL +#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */ + +/******************************************************************************* +* TCPWM +*******************************************************************************/ + +#define TCPWM0_BASE 0x40380000UL +#define TCPWM1_BASE 0x40390000UL +#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM1 ((TCPWM_Type*) TCPWM1_BASE) /* 0x40390000 */ +#define TCPWM0_CNT0 ((TCPWM_CNT_Type*) &TCPWM0->CNT[0]) /* 0x40380100 */ +#define TCPWM0_CNT1 ((TCPWM_CNT_Type*) &TCPWM0->CNT[1]) /* 0x40380140 */ +#define TCPWM0_CNT2 ((TCPWM_CNT_Type*) &TCPWM0->CNT[2]) /* 0x40380180 */ +#define TCPWM0_CNT3 ((TCPWM_CNT_Type*) &TCPWM0->CNT[3]) /* 0x403801C0 */ +#define TCPWM0_CNT4 ((TCPWM_CNT_Type*) &TCPWM0->CNT[4]) /* 0x40380200 */ +#define TCPWM0_CNT5 ((TCPWM_CNT_Type*) &TCPWM0->CNT[5]) /* 0x40380240 */ +#define TCPWM0_CNT6 ((TCPWM_CNT_Type*) &TCPWM0->CNT[6]) /* 0x40380280 */ +#define TCPWM0_CNT7 ((TCPWM_CNT_Type*) &TCPWM0->CNT[7]) /* 0x403802C0 */ +#define TCPWM1_CNT0 ((TCPWM_CNT_Type*) &TCPWM1->CNT[0]) /* 0x40390100 */ +#define TCPWM1_CNT1 ((TCPWM_CNT_Type*) &TCPWM1->CNT[1]) /* 0x40390140 */ +#define TCPWM1_CNT2 ((TCPWM_CNT_Type*) &TCPWM1->CNT[2]) /* 0x40390180 */ +#define TCPWM1_CNT3 ((TCPWM_CNT_Type*) &TCPWM1->CNT[3]) /* 0x403901C0 */ +#define TCPWM1_CNT4 ((TCPWM_CNT_Type*) &TCPWM1->CNT[4]) /* 0x40390200 */ +#define TCPWM1_CNT5 ((TCPWM_CNT_Type*) &TCPWM1->CNT[5]) /* 0x40390240 */ +#define TCPWM1_CNT6 ((TCPWM_CNT_Type*) &TCPWM1->CNT[6]) /* 0x40390280 */ +#define TCPWM1_CNT7 ((TCPWM_CNT_Type*) &TCPWM1->CNT[7]) /* 0x403902C0 */ +#define TCPWM1_CNT8 ((TCPWM_CNT_Type*) &TCPWM1->CNT[8]) /* 0x40390300 */ +#define TCPWM1_CNT9 ((TCPWM_CNT_Type*) &TCPWM1->CNT[9]) /* 0x40390340 */ +#define TCPWM1_CNT10 ((TCPWM_CNT_Type*) &TCPWM1->CNT[10]) /* 0x40390380 */ +#define TCPWM1_CNT11 ((TCPWM_CNT_Type*) &TCPWM1->CNT[11]) /* 0x403903C0 */ +#define TCPWM1_CNT12 ((TCPWM_CNT_Type*) &TCPWM1->CNT[12]) /* 0x40390400 */ +#define TCPWM1_CNT13 ((TCPWM_CNT_Type*) &TCPWM1->CNT[13]) /* 0x40390440 */ +#define TCPWM1_CNT14 ((TCPWM_CNT_Type*) &TCPWM1->CNT[14]) /* 0x40390480 */ +#define TCPWM1_CNT15 ((TCPWM_CNT_Type*) &TCPWM1->CNT[15]) /* 0x403904C0 */ +#define TCPWM1_CNT16 ((TCPWM_CNT_Type*) &TCPWM1->CNT[16]) /* 0x40390500 */ +#define TCPWM1_CNT17 ((TCPWM_CNT_Type*) &TCPWM1->CNT[17]) /* 0x40390540 */ +#define TCPWM1_CNT18 ((TCPWM_CNT_Type*) &TCPWM1->CNT[18]) /* 0x40390580 */ +#define TCPWM1_CNT19 ((TCPWM_CNT_Type*) &TCPWM1->CNT[19]) /* 0x403905C0 */ +#define TCPWM1_CNT20 ((TCPWM_CNT_Type*) &TCPWM1->CNT[20]) /* 0x40390600 */ +#define TCPWM1_CNT21 ((TCPWM_CNT_Type*) &TCPWM1->CNT[21]) /* 0x40390640 */ +#define TCPWM1_CNT22 ((TCPWM_CNT_Type*) &TCPWM1->CNT[22]) /* 0x40390680 */ +#define TCPWM1_CNT23 ((TCPWM_CNT_Type*) &TCPWM1->CNT[23]) /* 0x403906C0 */ + +/******************************************************************************* +* LCD +*******************************************************************************/ + +#define LCD0_BASE 0x403B0000UL +#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ + +/******************************************************************************* +* USBFS +*******************************************************************************/ + +#define USBFS0_BASE 0x403F0000UL +#define USBFS0 ((USBFS_Type*) USBFS0_BASE) /* 0x403F0000 */ +#define USBFS0_USBDEV ((USBFS_USBDEV_Type*) &USBFS0->USBDEV) /* 0x403F0000 */ +#define USBFS0_USBLPM ((USBFS_USBLPM_Type*) &USBFS0->USBLPM) /* 0x403F2000 */ +#define USBFS0_USBHOST ((USBFS_USBHOST_Type*) &USBFS0->USBHOST) /* 0x403F4000 */ + +/******************************************************************************* +* SMIF +*******************************************************************************/ + +#define SMIF0_BASE 0x40420000UL +#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ +#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ +#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ +#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ +#define SMIF0_DEVICE3 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[3]) /* 0x40420980 */ + +/******************************************************************************* +* SDHC +*******************************************************************************/ + +#define SDHC0_BASE 0x40460000UL +#define SDHC1_BASE 0x40470000UL +#define SDHC0 ((SDHC_Type*) SDHC0_BASE) /* 0x40460000 */ +#define SDHC1 ((SDHC_Type*) SDHC1_BASE) /* 0x40470000 */ +#define SDHC0_WRAP ((SDHC_WRAP_Type*) &SDHC0->WRAP) /* 0x40460000 */ +#define SDHC1_WRAP ((SDHC_WRAP_Type*) &SDHC1->WRAP) /* 0x40470000 */ +#define SDHC0_CORE ((SDHC_CORE_Type*) &SDHC0->CORE) /* 0x40461000 */ +#define SDHC1_CORE ((SDHC_CORE_Type*) &SDHC1->CORE) /* 0x40471000 */ + +/******************************************************************************* +* SCB +*******************************************************************************/ + +#define SCB0_BASE 0x40600000UL +#define SCB1_BASE 0x40610000UL +#define SCB2_BASE 0x40620000UL +#define SCB3_BASE 0x40630000UL +#define SCB4_BASE 0x40640000UL +#define SCB5_BASE 0x40650000UL +#define SCB6_BASE 0x40660000UL +#define SCB7_BASE 0x40670000UL +#define SCB8_BASE 0x40680000UL +#define SCB9_BASE 0x40690000UL +#define SCB10_BASE 0x406A0000UL +#define SCB11_BASE 0x406B0000UL +#define SCB12_BASE 0x406C0000UL +#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40600000 */ +#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40610000 */ +#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40620000 */ +#define SCB3 ((CySCB_Type*) SCB3_BASE) /* 0x40630000 */ +#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40640000 */ +#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40650000 */ +#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40660000 */ +#define SCB7 ((CySCB_Type*) SCB7_BASE) /* 0x40670000 */ +#define SCB8 ((CySCB_Type*) SCB8_BASE) /* 0x40680000 */ +#define SCB9 ((CySCB_Type*) SCB9_BASE) /* 0x40690000 */ +#define SCB10 ((CySCB_Type*) SCB10_BASE) /* 0x406A0000 */ +#define SCB11 ((CySCB_Type*) SCB11_BASE) /* 0x406B0000 */ +#define SCB12 ((CySCB_Type*) SCB12_BASE) /* 0x406C0000 */ + +/******************************************************************************* +* SAR +*******************************************************************************/ + +#define SAR_BASE 0x409D0000UL +#define SAR ((SAR_Type*) SAR_BASE) /* 0x409D0000 */ + +/******************************************************************************* +* PASS +*******************************************************************************/ + +#define PASS_BASE 0x409F0000UL +#define PASS ((PASS_Type*) PASS_BASE) /* 0x409F0000 */ +#define PASS_AREF ((PASS_AREF_Type*) &PASS->AREF) /* 0x409F0E00 */ + +/******************************************************************************* +* PDM +*******************************************************************************/ + +#define PDM0_BASE 0x40A00000UL +#define PDM0 ((PDM_Type*) PDM0_BASE) /* 0x40A00000 */ + +/******************************************************************************* +* I2S +*******************************************************************************/ + +#define I2S0_BASE 0x40A10000UL +#define I2S1_BASE 0x40A11000UL +#define I2S0 ((I2S_Type*) I2S0_BASE) /* 0x40A10000 */ +#define I2S1 ((I2S_Type*) I2S1_BASE) /* 0x40A11000 */ + +/** \} CY8C614ABZI-S2F04 */ + +#endif /* _CY8C614ABZI_S2F04_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c614abzi_s2f44.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c614abzi_s2f44.h new file mode 100644 index 0000000000..bd1d63e991 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c614abzi_s2f44.h @@ -0,0 +1,1098 @@ +/***************************************************************************//** +* \file cy8c614abzi_s2f44.h +* +* \brief +* CY8C614ABZI-S2F44 device header +* +* \note +* Generator version: 1.6.0.225 +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CY8C614ABZI_S2F44_H_ +#define _CY8C614ABZI_S2F44_H_ + +/** +* \addtogroup group_device CY8C614ABZI-S2F44 +* \{ +*/ + +/** +* \addtogroup Configuration_of_CMSIS +* \{ +*/ + +/******************************************************************************* +* Interrupt Number Definition +*******************************************************************************/ + +typedef enum { + /* ARM Cortex-M4 Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C614ABZI-S2F44 Peripheral Interrupt Numbers */ + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_1_IRQn = 1, /*!< 1 [DeepSleep] GPIO Port Interrupt #1 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_4_IRQn = 4, /*!< 4 [DeepSleep] GPIO Port Interrupt #4 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_13_IRQn = 13, /*!< 13 [DeepSleep] GPIO Port Interrupt #13 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_8_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #8 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + scb_6_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #6 */ + scb_7_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #7 */ + scb_9_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #9 */ + scb_10_interrupt_IRQn = 48, /*!< 48 [Active] Serial Communication Block #10 */ + scb_11_interrupt_IRQn = 49, /*!< 49 [Active] Serial Communication Block #11 */ + scb_12_interrupt_IRQn = 50, /*!< 50 [Active] Serial Communication Block #12 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dmac_2_IRQn = 54, /*!< 54 [Active] CPUSS DMAC, Channel #2 */ + cpuss_interrupts_dmac_3_IRQn = 55, /*!< 55 [Active] CPUSS DMAC, Channel #3 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_0_interrupts_4_IRQn = 127, /*!< 127 [Active] TCPWM #0, Counter #4 */ + tcpwm_0_interrupts_5_IRQn = 128, /*!< 128 [Active] TCPWM #0, Counter #5 */ + tcpwm_0_interrupts_6_IRQn = 129, /*!< 129 [Active] TCPWM #0, Counter #6 */ + tcpwm_0_interrupts_7_IRQn = 130, /*!< 130 [Active] TCPWM #0, Counter #7 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + tcpwm_1_interrupts_8_IRQn = 139, /*!< 139 [Active] TCPWM #1, Counter #8 */ + tcpwm_1_interrupts_9_IRQn = 140, /*!< 140 [Active] TCPWM #1, Counter #9 */ + tcpwm_1_interrupts_10_IRQn = 141, /*!< 141 [Active] TCPWM #1, Counter #10 */ + tcpwm_1_interrupts_11_IRQn = 142, /*!< 142 [Active] TCPWM #1, Counter #11 */ + tcpwm_1_interrupts_12_IRQn = 143, /*!< 143 [Active] TCPWM #1, Counter #12 */ + tcpwm_1_interrupts_13_IRQn = 144, /*!< 144 [Active] TCPWM #1, Counter #13 */ + tcpwm_1_interrupts_14_IRQn = 145, /*!< 145 [Active] TCPWM #1, Counter #14 */ + tcpwm_1_interrupts_15_IRQn = 146, /*!< 146 [Active] TCPWM #1, Counter #15 */ + tcpwm_1_interrupts_16_IRQn = 147, /*!< 147 [Active] TCPWM #1, Counter #16 */ + tcpwm_1_interrupts_17_IRQn = 148, /*!< 148 [Active] TCPWM #1, Counter #17 */ + tcpwm_1_interrupts_18_IRQn = 149, /*!< 149 [Active] TCPWM #1, Counter #18 */ + tcpwm_1_interrupts_19_IRQn = 150, /*!< 150 [Active] TCPWM #1, Counter #19 */ + tcpwm_1_interrupts_20_IRQn = 151, /*!< 151 [Active] TCPWM #1, Counter #20 */ + tcpwm_1_interrupts_21_IRQn = 152, /*!< 152 [Active] TCPWM #1, Counter #21 */ + tcpwm_1_interrupts_22_IRQn = 153, /*!< 153 [Active] TCPWM #1, Counter #22 */ + tcpwm_1_interrupts_23_IRQn = 154, /*!< 154 [Active] TCPWM #1, Counter #23 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + audioss_0_interrupt_i2s_IRQn = 156, /*!< 156 [Active] I2S0 Audio interrupt */ + audioss_0_interrupt_pdm_IRQn = 157, /*!< 157 [Active] PDM0/PCM0 Audio interrupt */ + audioss_1_interrupt_i2s_IRQn = 158, /*!< 158 [Active] I2S1 Audio interrupt */ + profile_interrupt_IRQn = 159, /*!< 159 [Active] Energy Profiler interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + sdhc_1_interrupt_wakeup_IRQn = 166, /*!< 166 [Active] EEMC wakeup interrupt for mxsdhc, not used */ + sdhc_1_interrupt_general_IRQn = 167, /*!< 167 [Active] Consolidated interrupt for mxsdhc for everything else */ + unconnected_IRQn = 240 /*!< 240 Unconnected */ +} IRQn_Type; + + +/******************************************************************************* +* Processor and Core Peripheral Section +*******************************************************************************/ + +/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __CM0P_PRESENT 0 /*!< CM0P present or not */ +#define __DTCM_PRESENT 0 /*!< DTCM present or not */ +#define __ICACHE_PRESENT 0 /*!< ICACHE present or not */ +#define __DCACHE_PRESENT 0 /*!< DCACHE present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + + +/* Memory Blocks */ +#define CY_ROM_BASE 0x00000000UL +#define CY_ROM_SIZE 0x00010000UL +#define CY_SRAM_BASE 0x08000000UL +#define CY_SRAM_SIZE 0x00100000UL +#define CY_FLASH_BASE 0x10000000UL +#define CY_FLASH_SIZE 0x00200000UL +#define CY_EM_EEPROM_BASE 0x14000000UL +#define CY_EM_EEPROM_SIZE 0x00008000UL +#define CY_SFLASH_BASE 0x16000000UL +#define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL +#define CY_EFUSE_BASE 0x402C0800UL +#define CY_EFUSE_SIZE 0x00000200UL + +#include "system_psoc6.h" /*!< PSoC 6 System */ + +/* IP List */ +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 2u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_M4CPUSS 1u +#define CY_IP_M4CPUSS_INSTANCES 1u +#define CY_IP_M4CPUSS_VERSION 2u +#define CY_IP_M4CPUSS_DMAC 1u +#define CY_IP_M4CPUSS_DMAC_INSTANCES 1u +#define CY_IP_M4CPUSS_DMAC_VERSION 2u +#define CY_IP_M4CPUSS_DMA 1u +#define CY_IP_M4CPUSS_DMA_INSTANCES 2u +#define CY_IP_M4CPUSS_DMA_VERSION 2u +#define CY_IP_MXCRYPTO 1u +#define CY_IP_MXCRYPTO_INSTANCES 1u +#define CY_IP_MXCRYPTO_VERSION 2u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u +#define CY_IP_MXS40PASS 1u +#define CY_IP_MXS40PASS_INSTANCES 1u +#define CY_IP_MXS40PASS_VERSION 1u +#define CY_IP_MXS40PASS_SAR 1u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u +#define CY_IP_MXS40PASS_SAR_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXPROFILE 1u +#define CY_IP_MXPROFILE_INSTANCES 1u +#define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 13u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 2u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u + +#include "psoc6_02_config.h" +#include "gpio_psoc6_02_124_bga.h" + +#define CY_DEVICE_PSOC6A2M +#define CY_SILICON_ID 0xE45E1202UL +#define CY_HF_CLK_MAX_FREQ 150000000UL + +#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL + +/******************************************************************************* +* SFLASH +*******************************************************************************/ + +#define SFLASH_BASE 0x16000000UL +#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */ + +/******************************************************************************* +* PERI +*******************************************************************************/ + +#define PERI_BASE 0x40000000UL +#define PERI ((PERI_Type*) PERI_BASE) /* 0x40000000 */ +#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40004000 */ +#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40004020 */ +#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40004040 */ +#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x40004060 */ +#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40004080 */ +#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x400040C0 */ +#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40004120 */ +#define PERI_GR10 ((PERI_GR_Type*) &PERI->GR[10]) /* 0x40004140 */ +#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40008000 */ +#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40008400 */ +#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40008800 */ +#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40008C00 */ +#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40009000 */ +#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40009400 */ +#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40009800 */ +#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40009C00 */ +#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ +#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ +#define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ +#define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ +#define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ +#define PERI_TR_1TO1_GR3 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[3]) /* 0x4000CC00 */ +#define PERI_TR_1TO1_GR4 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[4]) /* 0x4000D000 */ +#define PERI_TR_1TO1_GR5 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[5]) /* 0x4000D400 */ +#define PERI_TR_1TO1_GR6 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[6]) /* 0x4000D800 */ + +/******************************************************************************* +* PERI_MS +*******************************************************************************/ + +#define PERI_MS_BASE 0x40010000UL +#define PERI_MS ((PERI_MS_Type*) PERI_MS_BASE) /* 0x40010000 */ +#define PERI_MS_PPU_PR0 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[0]) /* 0x40010000 */ +#define PERI_MS_PPU_PR1 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[1]) /* 0x40010040 */ +#define PERI_MS_PPU_PR2 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[2]) /* 0x40010080 */ +#define PERI_MS_PPU_PR3 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[3]) /* 0x400100C0 */ +#define PERI_MS_PPU_PR4 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[4]) /* 0x40010100 */ +#define PERI_MS_PPU_PR5 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[5]) /* 0x40010140 */ +#define PERI_MS_PPU_PR6 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[6]) /* 0x40010180 */ +#define PERI_MS_PPU_PR7 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[7]) /* 0x400101C0 */ +#define PERI_MS_PPU_FX_PERI_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[0]) /* 0x40010800 */ +#define PERI_MS_PPU_FX_PERI_GR0_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[1]) /* 0x40010840 */ +#define PERI_MS_PPU_FX_PERI_GR1_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[2]) /* 0x40010880 */ +#define PERI_MS_PPU_FX_PERI_GR2_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[3]) /* 0x400108C0 */ +#define PERI_MS_PPU_FX_PERI_GR3_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[4]) /* 0x40010900 */ +#define PERI_MS_PPU_FX_PERI_GR4_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[5]) /* 0x40010940 */ +#define PERI_MS_PPU_FX_PERI_GR6_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[6]) /* 0x40010980 */ +#define PERI_MS_PPU_FX_PERI_GR9_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[7]) /* 0x400109C0 */ +#define PERI_MS_PPU_FX_PERI_GR10_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[8]) /* 0x40010A00 */ +#define PERI_MS_PPU_FX_PERI_TR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[9]) /* 0x40010A40 */ +#define PERI_MS_PPU_FX_CRYPTO_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[10]) /* 0x40010A80 */ +#define PERI_MS_PPU_FX_CRYPTO_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[11]) /* 0x40010AC0 */ +#define PERI_MS_PPU_FX_CRYPTO_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[12]) /* 0x40010B00 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[13]) /* 0x40010B40 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[14]) /* 0x40010B80 */ +#define PERI_MS_PPU_FX_CRYPTO_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[15]) /* 0x40010BC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[16]) /* 0x40010C00 */ +#define PERI_MS_PPU_FX_CPUSS_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[17]) /* 0x40010C40 */ +#define PERI_MS_PPU_FX_CPUSS_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[18]) /* 0x40010C80 */ +#define PERI_MS_PPU_FX_CPUSS_CM0_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[19]) /* 0x40010CC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[20]) /* 0x40010D00 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[21]) /* 0x40010D40 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT1_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[22]) /* 0x40010D80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT0_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[23]) /* 0x40010DC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT1_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[24]) /* 0x40010E00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT2_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[25]) /* 0x40010E40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT3_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[26]) /* 0x40010E80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT4_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[27]) /* 0x40010EC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT5_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[28]) /* 0x40010F00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT6_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[29]) /* 0x40010F40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT7_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[30]) /* 0x40010F80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT8_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[31]) /* 0x40010FC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT9_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[32]) /* 0x40011000 */ +#define PERI_MS_PPU_FX_IPC_STRUCT10_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[33]) /* 0x40011040 */ +#define PERI_MS_PPU_FX_IPC_STRUCT11_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[34]) /* 0x40011080 */ +#define PERI_MS_PPU_FX_IPC_STRUCT12_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[35]) /* 0x400110C0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT13_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[36]) /* 0x40011100 */ +#define PERI_MS_PPU_FX_IPC_STRUCT14_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[37]) /* 0x40011140 */ +#define PERI_MS_PPU_FX_IPC_STRUCT15_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[38]) /* 0x40011180 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT0_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[39]) /* 0x400111C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT1_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[40]) /* 0x40011200 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT2_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[41]) /* 0x40011240 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT3_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[42]) /* 0x40011280 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT4_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[43]) /* 0x400112C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT5_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[44]) /* 0x40011300 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT6_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[45]) /* 0x40011340 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT7_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[46]) /* 0x40011380 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT8_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[47]) /* 0x400113C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT9_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[48]) /* 0x40011400 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT10_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[49]) /* 0x40011440 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT11_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[50]) /* 0x40011480 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT12_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[51]) /* 0x400114C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT13_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[52]) /* 0x40011500 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT14_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[53]) /* 0x40011540 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT15_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[54]) /* 0x40011580 */ +#define PERI_MS_PPU_FX_PROT_SMPU_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[55]) /* 0x400115C0 */ +#define PERI_MS_PPU_FX_PROT_MPU0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[56]) /* 0x40011600 */ +#define PERI_MS_PPU_FX_PROT_MPU5_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[57]) /* 0x40011640 */ +#define PERI_MS_PPU_FX_PROT_MPU6_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[58]) /* 0x40011680 */ +#define PERI_MS_PPU_FX_PROT_MPU14_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[59]) /* 0x400116C0 */ +#define PERI_MS_PPU_FX_PROT_MPU15_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[60]) /* 0x40011700 */ +#define PERI_MS_PPU_FX_FLASHC_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[61]) /* 0x40011740 */ +#define PERI_MS_PPU_FX_FLASHC_CMD ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[62]) /* 0x40011780 */ +#define PERI_MS_PPU_FX_FLASHC_DFT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[63]) /* 0x400117C0 */ +#define PERI_MS_PPU_FX_FLASHC_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[64]) /* 0x40011800 */ +#define PERI_MS_PPU_FX_FLASHC_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[65]) /* 0x40011840 */ +#define PERI_MS_PPU_FX_FLASHC_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[66]) /* 0x40011880 */ +#define PERI_MS_PPU_FX_FLASHC_DW0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[67]) /* 0x400118C0 */ +#define PERI_MS_PPU_FX_FLASHC_DW1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[68]) /* 0x40011900 */ +#define PERI_MS_PPU_FX_FLASHC_DMAC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[69]) /* 0x40011940 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[70]) /* 0x40011980 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[71]) /* 0x400119C0 */ +#define PERI_MS_PPU_FX_FLASHC_FM ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[72]) /* 0x40011A00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[73]) /* 0x40011A40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[74]) /* 0x40011A80 */ +#define PERI_MS_PPU_FX_WDT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[75]) /* 0x40011AC0 */ +#define PERI_MS_PPU_FX_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[76]) /* 0x40011B00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[77]) /* 0x40011B40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[78]) /* 0x40011B80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[79]) /* 0x40011BC0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[80]) /* 0x40011C00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[81]) /* 0x40011C40 */ +#define PERI_MS_PPU_FX_BACKUP_BACKUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[82]) /* 0x40011C80 */ +#define PERI_MS_PPU_FX_DW0_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[83]) /* 0x40011CC0 */ +#define PERI_MS_PPU_FX_DW1_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[84]) /* 0x40011D00 */ +#define PERI_MS_PPU_FX_DW0_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[85]) /* 0x40011D40 */ +#define PERI_MS_PPU_FX_DW1_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[86]) /* 0x40011D80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[87]) /* 0x40011DC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[88]) /* 0x40011E00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[89]) /* 0x40011E40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[90]) /* 0x40011E80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[91]) /* 0x40011EC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[92]) /* 0x40011F00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[93]) /* 0x40011F40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[94]) /* 0x40011F80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[95]) /* 0x40011FC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[96]) /* 0x40012000 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[97]) /* 0x40012040 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[98]) /* 0x40012080 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[99]) /* 0x400120C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[100]) /* 0x40012100 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[101]) /* 0x40012140 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[102]) /* 0x40012180 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[103]) /* 0x400121C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[104]) /* 0x40012200 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[105]) /* 0x40012240 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[106]) /* 0x40012280 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[107]) /* 0x400122C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[108]) /* 0x40012300 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[109]) /* 0x40012340 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[110]) /* 0x40012380 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[111]) /* 0x400123C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[112]) /* 0x40012400 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[113]) /* 0x40012440 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[114]) /* 0x40012480 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[115]) /* 0x400124C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[116]) /* 0x40012500 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[117]) /* 0x40012540 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[118]) /* 0x40012580 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[119]) /* 0x400125C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[120]) /* 0x40012600 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[121]) /* 0x40012640 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[122]) /* 0x40012680 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[123]) /* 0x400126C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[124]) /* 0x40012700 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[125]) /* 0x40012740 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[126]) /* 0x40012780 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[127]) /* 0x400127C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[128]) /* 0x40012800 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[129]) /* 0x40012840 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[130]) /* 0x40012880 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[131]) /* 0x400128C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[132]) /* 0x40012900 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[133]) /* 0x40012940 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[134]) /* 0x40012980 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[135]) /* 0x400129C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[136]) /* 0x40012A00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[137]) /* 0x40012A40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[138]) /* 0x40012A80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[139]) /* 0x40012AC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[140]) /* 0x40012B00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[141]) /* 0x40012B40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[142]) /* 0x40012B80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[143]) /* 0x40012BC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[144]) /* 0x40012C00 */ +#define PERI_MS_PPU_FX_DMAC_TOP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[145]) /* 0x40012C40 */ +#define PERI_MS_PPU_FX_DMAC_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[146]) /* 0x40012C80 */ +#define PERI_MS_PPU_FX_DMAC_CH1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[147]) /* 0x40012CC0 */ +#define PERI_MS_PPU_FX_DMAC_CH2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[148]) /* 0x40012D00 */ +#define PERI_MS_PPU_FX_DMAC_CH3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[149]) /* 0x40012D40 */ +#define PERI_MS_PPU_FX_EFUSE_CTL ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[150]) /* 0x40012D80 */ +#define PERI_MS_PPU_FX_EFUSE_DATA ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[151]) /* 0x40012DC0 */ +#define PERI_MS_PPU_FX_PROFILE ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[152]) /* 0x40012E00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[153]) /* 0x40012E40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[154]) /* 0x40012E80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[155]) /* 0x40012EC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[156]) /* 0x40012F00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[157]) /* 0x40012F40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[158]) /* 0x40012F80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[159]) /* 0x40012FC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[160]) /* 0x40013000 */ +#define PERI_MS_PPU_FX_HSIOM_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[161]) /* 0x40013040 */ +#define PERI_MS_PPU_FX_HSIOM_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[162]) /* 0x40013080 */ +#define PERI_MS_PPU_FX_HSIOM_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[163]) /* 0x400130C0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[164]) /* 0x40013100 */ +#define PERI_MS_PPU_FX_HSIOM_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[165]) /* 0x40013140 */ +#define PERI_MS_PPU_FX_HSIOM_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[166]) /* 0x40013180 */ +#define PERI_MS_PPU_FX_HSIOM_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[167]) /* 0x400131C0 */ +#define PERI_MS_PPU_FX_HSIOM_AMUX ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[168]) /* 0x40013200 */ +#define PERI_MS_PPU_FX_HSIOM_MON ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[169]) /* 0x40013240 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[170]) /* 0x40013280 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[171]) /* 0x400132C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[172]) /* 0x40013300 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[173]) /* 0x40013340 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[174]) /* 0x40013380 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[175]) /* 0x400133C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[176]) /* 0x40013400 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[177]) /* 0x40013440 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[178]) /* 0x40013480 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[179]) /* 0x400134C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[180]) /* 0x40013500 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[181]) /* 0x40013540 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[182]) /* 0x40013580 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[183]) /* 0x400135C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[184]) /* 0x40013600 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[185]) /* 0x40013640 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[186]) /* 0x40013680 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[187]) /* 0x400136C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[188]) /* 0x40013700 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[189]) /* 0x40013740 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[190]) /* 0x40013780 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[191]) /* 0x400137C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[192]) /* 0x40013800 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[193]) /* 0x40013840 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[194]) /* 0x40013880 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[195]) /* 0x400138C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[196]) /* 0x40013900 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[197]) /* 0x40013940 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[198]) /* 0x40013980 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[199]) /* 0x400139C0 */ +#define PERI_MS_PPU_FX_GPIO_GPIO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[200]) /* 0x40013A00 */ +#define PERI_MS_PPU_FX_GPIO_TEST ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[201]) /* 0x40013A40 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[202]) /* 0x40013A80 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[203]) /* 0x40013AC0 */ +#define PERI_MS_PPU_FX_LPCOMP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[204]) /* 0x40013B00 */ +#define PERI_MS_PPU_FX_CSD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[205]) /* 0x40013B40 */ +#define PERI_MS_PPU_FX_TCPWM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[206]) /* 0x40013B80 */ +#define PERI_MS_PPU_FX_TCPWM1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[207]) /* 0x40013BC0 */ +#define PERI_MS_PPU_FX_LCD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[208]) /* 0x40013C00 */ +#define PERI_MS_PPU_FX_USBFS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[209]) /* 0x40013C40 */ +#define PERI_MS_PPU_FX_SMIF0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[210]) /* 0x40013C80 */ +#define PERI_MS_PPU_FX_SDHC0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[211]) /* 0x40013CC0 */ +#define PERI_MS_PPU_FX_SDHC1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[212]) /* 0x40013D00 */ +#define PERI_MS_PPU_FX_SCB0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[213]) /* 0x40013D40 */ +#define PERI_MS_PPU_FX_SCB1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[214]) /* 0x40013D80 */ +#define PERI_MS_PPU_FX_SCB2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[215]) /* 0x40013DC0 */ +#define PERI_MS_PPU_FX_SCB3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[216]) /* 0x40013E00 */ +#define PERI_MS_PPU_FX_SCB4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[217]) /* 0x40013E40 */ +#define PERI_MS_PPU_FX_SCB5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[218]) /* 0x40013E80 */ +#define PERI_MS_PPU_FX_SCB6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[219]) /* 0x40013EC0 */ +#define PERI_MS_PPU_FX_SCB7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[220]) /* 0x40013F00 */ +#define PERI_MS_PPU_FX_SCB8 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[221]) /* 0x40013F40 */ +#define PERI_MS_PPU_FX_SCB9 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[222]) /* 0x40013F80 */ +#define PERI_MS_PPU_FX_SCB10 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[223]) /* 0x40013FC0 */ +#define PERI_MS_PPU_FX_SCB11 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[224]) /* 0x40014000 */ +#define PERI_MS_PPU_FX_SCB12 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[225]) /* 0x40014040 */ +#define PERI_MS_PPU_FX_PDM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[226]) /* 0x40014080 */ +#define PERI_MS_PPU_FX_I2S0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[227]) /* 0x400140C0 */ +#define PERI_MS_PPU_FX_I2S1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[228]) /* 0x40014100 */ + +/******************************************************************************* +* CRYPTO +*******************************************************************************/ + +#define CRYPTO_BASE 0x40100000UL +#define CRYPTO ((CRYPTO_Type*) CRYPTO_BASE) /* 0x40100000 */ + +/******************************************************************************* +* CPUSS +*******************************************************************************/ + +#define CPUSS_BASE 0x40200000UL +#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40200000 */ + +/******************************************************************************* +* FAULT +*******************************************************************************/ + +#define FAULT_BASE 0x40210000UL +#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40210000 */ +#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40210000 */ +#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40210100 */ + +/******************************************************************************* +* IPC +*******************************************************************************/ + +#define IPC_BASE 0x40220000UL +#define IPC ((IPC_Type*) IPC_BASE) /* 0x40220000 */ +#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40220000 */ +#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40220020 */ +#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40220040 */ +#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40220060 */ +#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40220080 */ +#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402200A0 */ +#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402200C0 */ +#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402200E0 */ +#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40220100 */ +#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40220120 */ +#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40220140 */ +#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40220160 */ +#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40220180 */ +#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402201A0 */ +#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402201C0 */ +#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402201E0 */ +#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40221000 */ +#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40221020 */ +#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40221040 */ +#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40221060 */ +#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40221080 */ +#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402210A0 */ +#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402210C0 */ +#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402210E0 */ +#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40221100 */ +#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40221120 */ +#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40221140 */ +#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40221160 */ +#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40221180 */ +#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402211A0 */ +#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402211C0 */ +#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402211E0 */ + +/******************************************************************************* +* PROT +*******************************************************************************/ + +#define PROT_BASE 0x40230000UL +#define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ +#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ +#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ +#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402320C0 */ +#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40232100 */ +#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40232140 */ +#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40232180 */ +#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402321C0 */ +#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40232200 */ +#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40232240 */ +#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40232280 */ +#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402322C0 */ +#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40232300 */ +#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ +#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ +#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ +#define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ +#define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ +#define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ +#define PROT_MPU5_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[3]) /* 0x40235660 */ +#define PROT_MPU5_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[4]) /* 0x40235680 */ +#define PROT_MPU5_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[5]) /* 0x402356A0 */ +#define PROT_MPU5_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[6]) /* 0x402356C0 */ +#define PROT_MPU5_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[7]) /* 0x402356E0 */ +#define PROT_MPU6_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[0]) /* 0x40235A00 */ +#define PROT_MPU6_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[1]) /* 0x40235A20 */ +#define PROT_MPU6_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[2]) /* 0x40235A40 */ +#define PROT_MPU6_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[3]) /* 0x40235A60 */ +#define PROT_MPU6_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[4]) /* 0x40235A80 */ +#define PROT_MPU6_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[5]) /* 0x40235AA0 */ +#define PROT_MPU6_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[6]) /* 0x40235AC0 */ +#define PROT_MPU6_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[7]) /* 0x40235AE0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ + +/******************************************************************************* +* FLASHC +*******************************************************************************/ + +#define FLASHC_BASE 0x40240000UL +#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40240000 */ +#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4024F000 */ + +/******************************************************************************* +* SRSS +*******************************************************************************/ + +#define SRSS_BASE 0x40260000UL +#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ +#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */ +#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */ + +/******************************************************************************* +* BACKUP +*******************************************************************************/ + +#define BACKUP_BASE 0x40270000UL +#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ + +/******************************************************************************* +* DW +*******************************************************************************/ + +#define DW0_BASE 0x40280000UL +#define DW1_BASE 0x40290000UL +#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ +#define DW1 ((DW_Type*) DW1_BASE) /* 0x40290000 */ +#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40288000 */ +#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40288040 */ +#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40288080 */ +#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x402880C0 */ +#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40288100 */ +#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x40288140 */ +#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x40288180 */ +#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402881C0 */ +#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40288200 */ +#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40288240 */ +#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40288280 */ +#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x402882C0 */ +#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40288300 */ +#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x40288340 */ +#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x40288380 */ +#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402883C0 */ +#define DW0_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[16]) /* 0x40288400 */ +#define DW0_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[17]) /* 0x40288440 */ +#define DW0_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[18]) /* 0x40288480 */ +#define DW0_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[19]) /* 0x402884C0 */ +#define DW0_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[20]) /* 0x40288500 */ +#define DW0_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[21]) /* 0x40288540 */ +#define DW0_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[22]) /* 0x40288580 */ +#define DW0_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[23]) /* 0x402885C0 */ +#define DW0_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[24]) /* 0x40288600 */ +#define DW0_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[25]) /* 0x40288640 */ +#define DW0_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[26]) /* 0x40288680 */ +#define DW0_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[27]) /* 0x402886C0 */ +#define DW0_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[28]) /* 0x40288700 */ +#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40298000 */ +#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40298040 */ +#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40298080 */ +#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x402980C0 */ +#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40298100 */ +#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x40298140 */ +#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x40298180 */ +#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402981C0 */ +#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40298200 */ +#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40298240 */ +#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40298280 */ +#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x402982C0 */ +#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40298300 */ +#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x40298340 */ +#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x40298380 */ +#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402983C0 */ +#define DW1_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[16]) /* 0x40298400 */ +#define DW1_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[17]) /* 0x40298440 */ +#define DW1_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[18]) /* 0x40298480 */ +#define DW1_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[19]) /* 0x402984C0 */ +#define DW1_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[20]) /* 0x40298500 */ +#define DW1_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[21]) /* 0x40298540 */ +#define DW1_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[22]) /* 0x40298580 */ +#define DW1_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[23]) /* 0x402985C0 */ +#define DW1_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[24]) /* 0x40298600 */ +#define DW1_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[25]) /* 0x40298640 */ +#define DW1_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[26]) /* 0x40298680 */ +#define DW1_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[27]) /* 0x402986C0 */ +#define DW1_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[28]) /* 0x40298700 */ + +/******************************************************************************* +* DMAC +*******************************************************************************/ + +#define DMAC_BASE 0x402A0000UL +#define DMAC ((DMAC_Type*) DMAC_BASE) /* 0x402A0000 */ +#define DMAC_CH0 ((DMAC_CH_Type*) &DMAC->CH[0]) /* 0x402A1000 */ +#define DMAC_CH1 ((DMAC_CH_Type*) &DMAC->CH[1]) /* 0x402A1100 */ +#define DMAC_CH2 ((DMAC_CH_Type*) &DMAC->CH[2]) /* 0x402A1200 */ +#define DMAC_CH3 ((DMAC_CH_Type*) &DMAC->CH[3]) /* 0x402A1300 */ + +/******************************************************************************* +* EFUSE +*******************************************************************************/ + +#define EFUSE_BASE 0x402C0000UL +#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ + +/******************************************************************************* +* PROFILE +*******************************************************************************/ + +#define PROFILE_BASE 0x402D0000UL +#define PROFILE ((PROFILE_Type*) PROFILE_BASE) /* 0x402D0000 */ +#define PROFILE_CNT_STRUCT0 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[0]) /* 0x402D0800 */ +#define PROFILE_CNT_STRUCT1 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[1]) /* 0x402D0810 */ +#define PROFILE_CNT_STRUCT2 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[2]) /* 0x402D0820 */ +#define PROFILE_CNT_STRUCT3 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[3]) /* 0x402D0830 */ +#define PROFILE_CNT_STRUCT4 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[4]) /* 0x402D0840 */ +#define PROFILE_CNT_STRUCT5 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[5]) /* 0x402D0850 */ +#define PROFILE_CNT_STRUCT6 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[6]) /* 0x402D0860 */ +#define PROFILE_CNT_STRUCT7 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[7]) /* 0x402D0870 */ + +/******************************************************************************* +* HSIOM +*******************************************************************************/ + +#define HSIOM_BASE 0x40300000UL +#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40300000 */ +#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40300000 */ +#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40300010 */ +#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40300020 */ +#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40300030 */ +#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40300040 */ +#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40300050 */ +#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40300060 */ +#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40300070 */ +#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40300080 */ +#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40300090 */ +#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403000A0 */ +#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403000B0 */ +#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403000C0 */ +#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403000D0 */ +#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403000E0 */ + +/******************************************************************************* +* GPIO +*******************************************************************************/ + +#define GPIO_BASE 0x40310000UL +#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40310000 */ +#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40310000 */ +#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40310080 */ +#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40310100 */ +#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40310180 */ +#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40310200 */ +#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40310280 */ +#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40310300 */ +#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40310380 */ +#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40310400 */ +#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40310480 */ +#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40310500 */ +#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40310580 */ +#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40310600 */ +#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40310680 */ +#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40310700 */ + +/******************************************************************************* +* SMARTIO +*******************************************************************************/ + +#define SMARTIO_BASE 0x40320000UL +#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40320000 */ +#define SMARTIO_PRT8 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[8]) /* 0x40320800 */ +#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40320900 */ + +/******************************************************************************* +* LPCOMP +*******************************************************************************/ + +#define LPCOMP_BASE 0x40350000UL +#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */ + +/******************************************************************************* +* CSD +*******************************************************************************/ + +#define CSD0_BASE 0x40360000UL +#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */ + +/******************************************************************************* +* TCPWM +*******************************************************************************/ + +#define TCPWM0_BASE 0x40380000UL +#define TCPWM1_BASE 0x40390000UL +#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM1 ((TCPWM_Type*) TCPWM1_BASE) /* 0x40390000 */ +#define TCPWM0_CNT0 ((TCPWM_CNT_Type*) &TCPWM0->CNT[0]) /* 0x40380100 */ +#define TCPWM0_CNT1 ((TCPWM_CNT_Type*) &TCPWM0->CNT[1]) /* 0x40380140 */ +#define TCPWM0_CNT2 ((TCPWM_CNT_Type*) &TCPWM0->CNT[2]) /* 0x40380180 */ +#define TCPWM0_CNT3 ((TCPWM_CNT_Type*) &TCPWM0->CNT[3]) /* 0x403801C0 */ +#define TCPWM0_CNT4 ((TCPWM_CNT_Type*) &TCPWM0->CNT[4]) /* 0x40380200 */ +#define TCPWM0_CNT5 ((TCPWM_CNT_Type*) &TCPWM0->CNT[5]) /* 0x40380240 */ +#define TCPWM0_CNT6 ((TCPWM_CNT_Type*) &TCPWM0->CNT[6]) /* 0x40380280 */ +#define TCPWM0_CNT7 ((TCPWM_CNT_Type*) &TCPWM0->CNT[7]) /* 0x403802C0 */ +#define TCPWM1_CNT0 ((TCPWM_CNT_Type*) &TCPWM1->CNT[0]) /* 0x40390100 */ +#define TCPWM1_CNT1 ((TCPWM_CNT_Type*) &TCPWM1->CNT[1]) /* 0x40390140 */ +#define TCPWM1_CNT2 ((TCPWM_CNT_Type*) &TCPWM1->CNT[2]) /* 0x40390180 */ +#define TCPWM1_CNT3 ((TCPWM_CNT_Type*) &TCPWM1->CNT[3]) /* 0x403901C0 */ +#define TCPWM1_CNT4 ((TCPWM_CNT_Type*) &TCPWM1->CNT[4]) /* 0x40390200 */ +#define TCPWM1_CNT5 ((TCPWM_CNT_Type*) &TCPWM1->CNT[5]) /* 0x40390240 */ +#define TCPWM1_CNT6 ((TCPWM_CNT_Type*) &TCPWM1->CNT[6]) /* 0x40390280 */ +#define TCPWM1_CNT7 ((TCPWM_CNT_Type*) &TCPWM1->CNT[7]) /* 0x403902C0 */ +#define TCPWM1_CNT8 ((TCPWM_CNT_Type*) &TCPWM1->CNT[8]) /* 0x40390300 */ +#define TCPWM1_CNT9 ((TCPWM_CNT_Type*) &TCPWM1->CNT[9]) /* 0x40390340 */ +#define TCPWM1_CNT10 ((TCPWM_CNT_Type*) &TCPWM1->CNT[10]) /* 0x40390380 */ +#define TCPWM1_CNT11 ((TCPWM_CNT_Type*) &TCPWM1->CNT[11]) /* 0x403903C0 */ +#define TCPWM1_CNT12 ((TCPWM_CNT_Type*) &TCPWM1->CNT[12]) /* 0x40390400 */ +#define TCPWM1_CNT13 ((TCPWM_CNT_Type*) &TCPWM1->CNT[13]) /* 0x40390440 */ +#define TCPWM1_CNT14 ((TCPWM_CNT_Type*) &TCPWM1->CNT[14]) /* 0x40390480 */ +#define TCPWM1_CNT15 ((TCPWM_CNT_Type*) &TCPWM1->CNT[15]) /* 0x403904C0 */ +#define TCPWM1_CNT16 ((TCPWM_CNT_Type*) &TCPWM1->CNT[16]) /* 0x40390500 */ +#define TCPWM1_CNT17 ((TCPWM_CNT_Type*) &TCPWM1->CNT[17]) /* 0x40390540 */ +#define TCPWM1_CNT18 ((TCPWM_CNT_Type*) &TCPWM1->CNT[18]) /* 0x40390580 */ +#define TCPWM1_CNT19 ((TCPWM_CNT_Type*) &TCPWM1->CNT[19]) /* 0x403905C0 */ +#define TCPWM1_CNT20 ((TCPWM_CNT_Type*) &TCPWM1->CNT[20]) /* 0x40390600 */ +#define TCPWM1_CNT21 ((TCPWM_CNT_Type*) &TCPWM1->CNT[21]) /* 0x40390640 */ +#define TCPWM1_CNT22 ((TCPWM_CNT_Type*) &TCPWM1->CNT[22]) /* 0x40390680 */ +#define TCPWM1_CNT23 ((TCPWM_CNT_Type*) &TCPWM1->CNT[23]) /* 0x403906C0 */ + +/******************************************************************************* +* LCD +*******************************************************************************/ + +#define LCD0_BASE 0x403B0000UL +#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ + +/******************************************************************************* +* USBFS +*******************************************************************************/ + +#define USBFS0_BASE 0x403F0000UL +#define USBFS0 ((USBFS_Type*) USBFS0_BASE) /* 0x403F0000 */ +#define USBFS0_USBDEV ((USBFS_USBDEV_Type*) &USBFS0->USBDEV) /* 0x403F0000 */ +#define USBFS0_USBLPM ((USBFS_USBLPM_Type*) &USBFS0->USBLPM) /* 0x403F2000 */ +#define USBFS0_USBHOST ((USBFS_USBHOST_Type*) &USBFS0->USBHOST) /* 0x403F4000 */ + +/******************************************************************************* +* SMIF +*******************************************************************************/ + +#define SMIF0_BASE 0x40420000UL +#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ +#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ +#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ +#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ +#define SMIF0_DEVICE3 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[3]) /* 0x40420980 */ + +/******************************************************************************* +* SDHC +*******************************************************************************/ + +#define SDHC0_BASE 0x40460000UL +#define SDHC1_BASE 0x40470000UL +#define SDHC0 ((SDHC_Type*) SDHC0_BASE) /* 0x40460000 */ +#define SDHC1 ((SDHC_Type*) SDHC1_BASE) /* 0x40470000 */ +#define SDHC0_WRAP ((SDHC_WRAP_Type*) &SDHC0->WRAP) /* 0x40460000 */ +#define SDHC1_WRAP ((SDHC_WRAP_Type*) &SDHC1->WRAP) /* 0x40470000 */ +#define SDHC0_CORE ((SDHC_CORE_Type*) &SDHC0->CORE) /* 0x40461000 */ +#define SDHC1_CORE ((SDHC_CORE_Type*) &SDHC1->CORE) /* 0x40471000 */ + +/******************************************************************************* +* SCB +*******************************************************************************/ + +#define SCB0_BASE 0x40600000UL +#define SCB1_BASE 0x40610000UL +#define SCB2_BASE 0x40620000UL +#define SCB3_BASE 0x40630000UL +#define SCB4_BASE 0x40640000UL +#define SCB5_BASE 0x40650000UL +#define SCB6_BASE 0x40660000UL +#define SCB7_BASE 0x40670000UL +#define SCB8_BASE 0x40680000UL +#define SCB9_BASE 0x40690000UL +#define SCB10_BASE 0x406A0000UL +#define SCB11_BASE 0x406B0000UL +#define SCB12_BASE 0x406C0000UL +#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40600000 */ +#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40610000 */ +#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40620000 */ +#define SCB3 ((CySCB_Type*) SCB3_BASE) /* 0x40630000 */ +#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40640000 */ +#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40650000 */ +#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40660000 */ +#define SCB7 ((CySCB_Type*) SCB7_BASE) /* 0x40670000 */ +#define SCB8 ((CySCB_Type*) SCB8_BASE) /* 0x40680000 */ +#define SCB9 ((CySCB_Type*) SCB9_BASE) /* 0x40690000 */ +#define SCB10 ((CySCB_Type*) SCB10_BASE) /* 0x406A0000 */ +#define SCB11 ((CySCB_Type*) SCB11_BASE) /* 0x406B0000 */ +#define SCB12 ((CySCB_Type*) SCB12_BASE) /* 0x406C0000 */ + +/******************************************************************************* +* SAR +*******************************************************************************/ + +#define SAR_BASE 0x409D0000UL +#define SAR ((SAR_Type*) SAR_BASE) /* 0x409D0000 */ + +/******************************************************************************* +* PASS +*******************************************************************************/ + +#define PASS_BASE 0x409F0000UL +#define PASS ((PASS_Type*) PASS_BASE) /* 0x409F0000 */ +#define PASS_AREF ((PASS_AREF_Type*) &PASS->AREF) /* 0x409F0E00 */ + +/******************************************************************************* +* PDM +*******************************************************************************/ + +#define PDM0_BASE 0x40A00000UL +#define PDM0 ((PDM_Type*) PDM0_BASE) /* 0x40A00000 */ + +/******************************************************************************* +* I2S +*******************************************************************************/ + +#define I2S0_BASE 0x40A10000UL +#define I2S1_BASE 0x40A11000UL +#define I2S0 ((I2S_Type*) I2S0_BASE) /* 0x40A10000 */ +#define I2S1 ((I2S_Type*) I2S1_BASE) /* 0x40A11000 */ + +/** \} CY8C614ABZI-S2F44 */ + +#endif /* _CY8C614ABZI_S2F44_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c614afni_s2f03.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c614afni_s2f03.h new file mode 100644 index 0000000000..5cf7c0a1cf --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c614afni_s2f03.h @@ -0,0 +1,1088 @@ +/***************************************************************************//** +* \file cy8c614afni_s2f03.h +* +* \brief +* CY8C614AFNI-S2F03 device header +* +* \note +* Generator version: 1.6.0.225 +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CY8C614AFNI_S2F03_H_ +#define _CY8C614AFNI_S2F03_H_ + +/** +* \addtogroup group_device CY8C614AFNI-S2F03 +* \{ +*/ + +/** +* \addtogroup Configuration_of_CMSIS +* \{ +*/ + +/******************************************************************************* +* Interrupt Number Definition +*******************************************************************************/ + +typedef enum { + /* ARM Cortex-M4 Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C614AFNI-S2F03 Peripheral Interrupt Numbers */ + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_1_IRQn = 1, /*!< 1 [DeepSleep] GPIO Port Interrupt #1 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_4_IRQn = 4, /*!< 4 [DeepSleep] GPIO Port Interrupt #4 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_13_IRQn = 13, /*!< 13 [DeepSleep] GPIO Port Interrupt #13 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_8_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #8 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + scb_6_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #6 */ + scb_7_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #7 */ + scb_9_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #9 */ + scb_10_interrupt_IRQn = 48, /*!< 48 [Active] Serial Communication Block #10 */ + scb_11_interrupt_IRQn = 49, /*!< 49 [Active] Serial Communication Block #11 */ + scb_12_interrupt_IRQn = 50, /*!< 50 [Active] Serial Communication Block #12 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dmac_2_IRQn = 54, /*!< 54 [Active] CPUSS DMAC, Channel #2 */ + cpuss_interrupts_dmac_3_IRQn = 55, /*!< 55 [Active] CPUSS DMAC, Channel #3 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_0_interrupts_4_IRQn = 127, /*!< 127 [Active] TCPWM #0, Counter #4 */ + tcpwm_0_interrupts_5_IRQn = 128, /*!< 128 [Active] TCPWM #0, Counter #5 */ + tcpwm_0_interrupts_6_IRQn = 129, /*!< 129 [Active] TCPWM #0, Counter #6 */ + tcpwm_0_interrupts_7_IRQn = 130, /*!< 130 [Active] TCPWM #0, Counter #7 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + tcpwm_1_interrupts_8_IRQn = 139, /*!< 139 [Active] TCPWM #1, Counter #8 */ + tcpwm_1_interrupts_9_IRQn = 140, /*!< 140 [Active] TCPWM #1, Counter #9 */ + tcpwm_1_interrupts_10_IRQn = 141, /*!< 141 [Active] TCPWM #1, Counter #10 */ + tcpwm_1_interrupts_11_IRQn = 142, /*!< 142 [Active] TCPWM #1, Counter #11 */ + tcpwm_1_interrupts_12_IRQn = 143, /*!< 143 [Active] TCPWM #1, Counter #12 */ + tcpwm_1_interrupts_13_IRQn = 144, /*!< 144 [Active] TCPWM #1, Counter #13 */ + tcpwm_1_interrupts_14_IRQn = 145, /*!< 145 [Active] TCPWM #1, Counter #14 */ + tcpwm_1_interrupts_15_IRQn = 146, /*!< 146 [Active] TCPWM #1, Counter #15 */ + tcpwm_1_interrupts_16_IRQn = 147, /*!< 147 [Active] TCPWM #1, Counter #16 */ + tcpwm_1_interrupts_17_IRQn = 148, /*!< 148 [Active] TCPWM #1, Counter #17 */ + tcpwm_1_interrupts_18_IRQn = 149, /*!< 149 [Active] TCPWM #1, Counter #18 */ + tcpwm_1_interrupts_19_IRQn = 150, /*!< 150 [Active] TCPWM #1, Counter #19 */ + tcpwm_1_interrupts_20_IRQn = 151, /*!< 151 [Active] TCPWM #1, Counter #20 */ + tcpwm_1_interrupts_21_IRQn = 152, /*!< 152 [Active] TCPWM #1, Counter #21 */ + tcpwm_1_interrupts_22_IRQn = 153, /*!< 153 [Active] TCPWM #1, Counter #22 */ + tcpwm_1_interrupts_23_IRQn = 154, /*!< 154 [Active] TCPWM #1, Counter #23 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + audioss_0_interrupt_i2s_IRQn = 156, /*!< 156 [Active] I2S0 Audio interrupt */ + audioss_0_interrupt_pdm_IRQn = 157, /*!< 157 [Active] PDM0/PCM0 Audio interrupt */ + audioss_1_interrupt_i2s_IRQn = 158, /*!< 158 [Active] I2S1 Audio interrupt */ + profile_interrupt_IRQn = 159, /*!< 159 [Active] Energy Profiler interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + sdhc_1_interrupt_wakeup_IRQn = 166, /*!< 166 [Active] EEMC wakeup interrupt for mxsdhc, not used */ + sdhc_1_interrupt_general_IRQn = 167, /*!< 167 [Active] Consolidated interrupt for mxsdhc for everything else */ + unconnected_IRQn = 240 /*!< 240 Unconnected */ +} IRQn_Type; + + +/******************************************************************************* +* Processor and Core Peripheral Section +*******************************************************************************/ + +/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __CM0P_PRESENT 0 /*!< CM0P present or not */ +#define __DTCM_PRESENT 0 /*!< DTCM present or not */ +#define __ICACHE_PRESENT 0 /*!< ICACHE present or not */ +#define __DCACHE_PRESENT 0 /*!< DCACHE present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + + +/* Memory Blocks */ +#define CY_ROM_BASE 0x00000000UL +#define CY_ROM_SIZE 0x00010000UL +#define CY_SRAM_BASE 0x08000000UL +#define CY_SRAM_SIZE 0x00100000UL +#define CY_FLASH_BASE 0x10000000UL +#define CY_FLASH_SIZE 0x00200000UL +#define CY_EM_EEPROM_BASE 0x14000000UL +#define CY_EM_EEPROM_SIZE 0x00008000UL +#define CY_SFLASH_BASE 0x16000000UL +#define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL +#define CY_EFUSE_BASE 0x402C0800UL +#define CY_EFUSE_SIZE 0x00000200UL + +#include "system_psoc6.h" /*!< PSoC 6 System */ + +/* IP List */ +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 2u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_M4CPUSS 1u +#define CY_IP_M4CPUSS_INSTANCES 1u +#define CY_IP_M4CPUSS_VERSION 2u +#define CY_IP_M4CPUSS_DMAC 1u +#define CY_IP_M4CPUSS_DMAC_INSTANCES 1u +#define CY_IP_M4CPUSS_DMAC_VERSION 2u +#define CY_IP_M4CPUSS_DMA 1u +#define CY_IP_M4CPUSS_DMA_INSTANCES 2u +#define CY_IP_M4CPUSS_DMA_VERSION 2u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u +#define CY_IP_MXS40PASS 1u +#define CY_IP_MXS40PASS_INSTANCES 1u +#define CY_IP_MXS40PASS_VERSION 1u +#define CY_IP_MXS40PASS_SAR 1u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u +#define CY_IP_MXS40PASS_SAR_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXPROFILE 1u +#define CY_IP_MXPROFILE_INSTANCES 1u +#define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 13u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 2u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u + +#include "psoc6_02_config.h" +#include "gpio_psoc6_02_100_wlcsp.h" + +#define CY_DEVICE_PSOC6A2M +#define CY_SILICON_ID 0xE45C1202UL +#define CY_HF_CLK_MAX_FREQ 150000000UL + +#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL + +/******************************************************************************* +* SFLASH +*******************************************************************************/ + +#define SFLASH_BASE 0x16000000UL +#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */ + +/******************************************************************************* +* PERI +*******************************************************************************/ + +#define PERI_BASE 0x40000000UL +#define PERI ((PERI_Type*) PERI_BASE) /* 0x40000000 */ +#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40004000 */ +#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40004020 */ +#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40004040 */ +#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x40004060 */ +#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40004080 */ +#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x400040C0 */ +#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40004120 */ +#define PERI_GR10 ((PERI_GR_Type*) &PERI->GR[10]) /* 0x40004140 */ +#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40008000 */ +#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40008400 */ +#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40008800 */ +#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40008C00 */ +#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40009000 */ +#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40009400 */ +#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40009800 */ +#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40009C00 */ +#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ +#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ +#define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ +#define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ +#define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ +#define PERI_TR_1TO1_GR3 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[3]) /* 0x4000CC00 */ +#define PERI_TR_1TO1_GR4 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[4]) /* 0x4000D000 */ +#define PERI_TR_1TO1_GR5 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[5]) /* 0x4000D400 */ +#define PERI_TR_1TO1_GR6 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[6]) /* 0x4000D800 */ + +/******************************************************************************* +* PERI_MS +*******************************************************************************/ + +#define PERI_MS_BASE 0x40010000UL +#define PERI_MS ((PERI_MS_Type*) PERI_MS_BASE) /* 0x40010000 */ +#define PERI_MS_PPU_PR0 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[0]) /* 0x40010000 */ +#define PERI_MS_PPU_PR1 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[1]) /* 0x40010040 */ +#define PERI_MS_PPU_PR2 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[2]) /* 0x40010080 */ +#define PERI_MS_PPU_PR3 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[3]) /* 0x400100C0 */ +#define PERI_MS_PPU_PR4 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[4]) /* 0x40010100 */ +#define PERI_MS_PPU_PR5 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[5]) /* 0x40010140 */ +#define PERI_MS_PPU_PR6 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[6]) /* 0x40010180 */ +#define PERI_MS_PPU_PR7 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[7]) /* 0x400101C0 */ +#define PERI_MS_PPU_FX_PERI_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[0]) /* 0x40010800 */ +#define PERI_MS_PPU_FX_PERI_GR0_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[1]) /* 0x40010840 */ +#define PERI_MS_PPU_FX_PERI_GR1_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[2]) /* 0x40010880 */ +#define PERI_MS_PPU_FX_PERI_GR2_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[3]) /* 0x400108C0 */ +#define PERI_MS_PPU_FX_PERI_GR3_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[4]) /* 0x40010900 */ +#define PERI_MS_PPU_FX_PERI_GR4_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[5]) /* 0x40010940 */ +#define PERI_MS_PPU_FX_PERI_GR6_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[6]) /* 0x40010980 */ +#define PERI_MS_PPU_FX_PERI_GR9_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[7]) /* 0x400109C0 */ +#define PERI_MS_PPU_FX_PERI_GR10_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[8]) /* 0x40010A00 */ +#define PERI_MS_PPU_FX_PERI_TR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[9]) /* 0x40010A40 */ +#define PERI_MS_PPU_FX_CRYPTO_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[10]) /* 0x40010A80 */ +#define PERI_MS_PPU_FX_CRYPTO_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[11]) /* 0x40010AC0 */ +#define PERI_MS_PPU_FX_CRYPTO_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[12]) /* 0x40010B00 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[13]) /* 0x40010B40 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[14]) /* 0x40010B80 */ +#define PERI_MS_PPU_FX_CRYPTO_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[15]) /* 0x40010BC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[16]) /* 0x40010C00 */ +#define PERI_MS_PPU_FX_CPUSS_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[17]) /* 0x40010C40 */ +#define PERI_MS_PPU_FX_CPUSS_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[18]) /* 0x40010C80 */ +#define PERI_MS_PPU_FX_CPUSS_CM0_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[19]) /* 0x40010CC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[20]) /* 0x40010D00 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[21]) /* 0x40010D40 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT1_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[22]) /* 0x40010D80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT0_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[23]) /* 0x40010DC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT1_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[24]) /* 0x40010E00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT2_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[25]) /* 0x40010E40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT3_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[26]) /* 0x40010E80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT4_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[27]) /* 0x40010EC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT5_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[28]) /* 0x40010F00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT6_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[29]) /* 0x40010F40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT7_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[30]) /* 0x40010F80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT8_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[31]) /* 0x40010FC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT9_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[32]) /* 0x40011000 */ +#define PERI_MS_PPU_FX_IPC_STRUCT10_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[33]) /* 0x40011040 */ +#define PERI_MS_PPU_FX_IPC_STRUCT11_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[34]) /* 0x40011080 */ +#define PERI_MS_PPU_FX_IPC_STRUCT12_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[35]) /* 0x400110C0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT13_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[36]) /* 0x40011100 */ +#define PERI_MS_PPU_FX_IPC_STRUCT14_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[37]) /* 0x40011140 */ +#define PERI_MS_PPU_FX_IPC_STRUCT15_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[38]) /* 0x40011180 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT0_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[39]) /* 0x400111C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT1_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[40]) /* 0x40011200 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT2_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[41]) /* 0x40011240 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT3_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[42]) /* 0x40011280 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT4_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[43]) /* 0x400112C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT5_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[44]) /* 0x40011300 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT6_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[45]) /* 0x40011340 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT7_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[46]) /* 0x40011380 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT8_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[47]) /* 0x400113C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT9_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[48]) /* 0x40011400 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT10_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[49]) /* 0x40011440 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT11_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[50]) /* 0x40011480 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT12_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[51]) /* 0x400114C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT13_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[52]) /* 0x40011500 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT14_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[53]) /* 0x40011540 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT15_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[54]) /* 0x40011580 */ +#define PERI_MS_PPU_FX_PROT_SMPU_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[55]) /* 0x400115C0 */ +#define PERI_MS_PPU_FX_PROT_MPU0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[56]) /* 0x40011600 */ +#define PERI_MS_PPU_FX_PROT_MPU5_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[57]) /* 0x40011640 */ +#define PERI_MS_PPU_FX_PROT_MPU6_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[58]) /* 0x40011680 */ +#define PERI_MS_PPU_FX_PROT_MPU14_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[59]) /* 0x400116C0 */ +#define PERI_MS_PPU_FX_PROT_MPU15_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[60]) /* 0x40011700 */ +#define PERI_MS_PPU_FX_FLASHC_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[61]) /* 0x40011740 */ +#define PERI_MS_PPU_FX_FLASHC_CMD ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[62]) /* 0x40011780 */ +#define PERI_MS_PPU_FX_FLASHC_DFT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[63]) /* 0x400117C0 */ +#define PERI_MS_PPU_FX_FLASHC_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[64]) /* 0x40011800 */ +#define PERI_MS_PPU_FX_FLASHC_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[65]) /* 0x40011840 */ +#define PERI_MS_PPU_FX_FLASHC_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[66]) /* 0x40011880 */ +#define PERI_MS_PPU_FX_FLASHC_DW0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[67]) /* 0x400118C0 */ +#define PERI_MS_PPU_FX_FLASHC_DW1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[68]) /* 0x40011900 */ +#define PERI_MS_PPU_FX_FLASHC_DMAC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[69]) /* 0x40011940 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[70]) /* 0x40011980 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[71]) /* 0x400119C0 */ +#define PERI_MS_PPU_FX_FLASHC_FM ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[72]) /* 0x40011A00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[73]) /* 0x40011A40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[74]) /* 0x40011A80 */ +#define PERI_MS_PPU_FX_WDT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[75]) /* 0x40011AC0 */ +#define PERI_MS_PPU_FX_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[76]) /* 0x40011B00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[77]) /* 0x40011B40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[78]) /* 0x40011B80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[79]) /* 0x40011BC0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[80]) /* 0x40011C00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[81]) /* 0x40011C40 */ +#define PERI_MS_PPU_FX_BACKUP_BACKUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[82]) /* 0x40011C80 */ +#define PERI_MS_PPU_FX_DW0_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[83]) /* 0x40011CC0 */ +#define PERI_MS_PPU_FX_DW1_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[84]) /* 0x40011D00 */ +#define PERI_MS_PPU_FX_DW0_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[85]) /* 0x40011D40 */ +#define PERI_MS_PPU_FX_DW1_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[86]) /* 0x40011D80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[87]) /* 0x40011DC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[88]) /* 0x40011E00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[89]) /* 0x40011E40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[90]) /* 0x40011E80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[91]) /* 0x40011EC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[92]) /* 0x40011F00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[93]) /* 0x40011F40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[94]) /* 0x40011F80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[95]) /* 0x40011FC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[96]) /* 0x40012000 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[97]) /* 0x40012040 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[98]) /* 0x40012080 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[99]) /* 0x400120C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[100]) /* 0x40012100 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[101]) /* 0x40012140 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[102]) /* 0x40012180 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[103]) /* 0x400121C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[104]) /* 0x40012200 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[105]) /* 0x40012240 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[106]) /* 0x40012280 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[107]) /* 0x400122C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[108]) /* 0x40012300 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[109]) /* 0x40012340 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[110]) /* 0x40012380 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[111]) /* 0x400123C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[112]) /* 0x40012400 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[113]) /* 0x40012440 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[114]) /* 0x40012480 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[115]) /* 0x400124C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[116]) /* 0x40012500 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[117]) /* 0x40012540 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[118]) /* 0x40012580 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[119]) /* 0x400125C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[120]) /* 0x40012600 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[121]) /* 0x40012640 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[122]) /* 0x40012680 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[123]) /* 0x400126C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[124]) /* 0x40012700 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[125]) /* 0x40012740 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[126]) /* 0x40012780 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[127]) /* 0x400127C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[128]) /* 0x40012800 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[129]) /* 0x40012840 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[130]) /* 0x40012880 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[131]) /* 0x400128C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[132]) /* 0x40012900 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[133]) /* 0x40012940 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[134]) /* 0x40012980 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[135]) /* 0x400129C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[136]) /* 0x40012A00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[137]) /* 0x40012A40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[138]) /* 0x40012A80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[139]) /* 0x40012AC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[140]) /* 0x40012B00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[141]) /* 0x40012B40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[142]) /* 0x40012B80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[143]) /* 0x40012BC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[144]) /* 0x40012C00 */ +#define PERI_MS_PPU_FX_DMAC_TOP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[145]) /* 0x40012C40 */ +#define PERI_MS_PPU_FX_DMAC_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[146]) /* 0x40012C80 */ +#define PERI_MS_PPU_FX_DMAC_CH1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[147]) /* 0x40012CC0 */ +#define PERI_MS_PPU_FX_DMAC_CH2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[148]) /* 0x40012D00 */ +#define PERI_MS_PPU_FX_DMAC_CH3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[149]) /* 0x40012D40 */ +#define PERI_MS_PPU_FX_EFUSE_CTL ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[150]) /* 0x40012D80 */ +#define PERI_MS_PPU_FX_EFUSE_DATA ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[151]) /* 0x40012DC0 */ +#define PERI_MS_PPU_FX_PROFILE ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[152]) /* 0x40012E00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[153]) /* 0x40012E40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[154]) /* 0x40012E80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[155]) /* 0x40012EC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[156]) /* 0x40012F00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[157]) /* 0x40012F40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[158]) /* 0x40012F80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[159]) /* 0x40012FC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[160]) /* 0x40013000 */ +#define PERI_MS_PPU_FX_HSIOM_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[161]) /* 0x40013040 */ +#define PERI_MS_PPU_FX_HSIOM_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[162]) /* 0x40013080 */ +#define PERI_MS_PPU_FX_HSIOM_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[163]) /* 0x400130C0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[164]) /* 0x40013100 */ +#define PERI_MS_PPU_FX_HSIOM_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[165]) /* 0x40013140 */ +#define PERI_MS_PPU_FX_HSIOM_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[166]) /* 0x40013180 */ +#define PERI_MS_PPU_FX_HSIOM_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[167]) /* 0x400131C0 */ +#define PERI_MS_PPU_FX_HSIOM_AMUX ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[168]) /* 0x40013200 */ +#define PERI_MS_PPU_FX_HSIOM_MON ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[169]) /* 0x40013240 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[170]) /* 0x40013280 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[171]) /* 0x400132C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[172]) /* 0x40013300 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[173]) /* 0x40013340 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[174]) /* 0x40013380 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[175]) /* 0x400133C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[176]) /* 0x40013400 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[177]) /* 0x40013440 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[178]) /* 0x40013480 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[179]) /* 0x400134C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[180]) /* 0x40013500 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[181]) /* 0x40013540 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[182]) /* 0x40013580 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[183]) /* 0x400135C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[184]) /* 0x40013600 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[185]) /* 0x40013640 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[186]) /* 0x40013680 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[187]) /* 0x400136C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[188]) /* 0x40013700 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[189]) /* 0x40013740 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[190]) /* 0x40013780 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[191]) /* 0x400137C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[192]) /* 0x40013800 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[193]) /* 0x40013840 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[194]) /* 0x40013880 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[195]) /* 0x400138C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[196]) /* 0x40013900 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[197]) /* 0x40013940 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[198]) /* 0x40013980 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[199]) /* 0x400139C0 */ +#define PERI_MS_PPU_FX_GPIO_GPIO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[200]) /* 0x40013A00 */ +#define PERI_MS_PPU_FX_GPIO_TEST ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[201]) /* 0x40013A40 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[202]) /* 0x40013A80 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[203]) /* 0x40013AC0 */ +#define PERI_MS_PPU_FX_LPCOMP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[204]) /* 0x40013B00 */ +#define PERI_MS_PPU_FX_CSD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[205]) /* 0x40013B40 */ +#define PERI_MS_PPU_FX_TCPWM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[206]) /* 0x40013B80 */ +#define PERI_MS_PPU_FX_TCPWM1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[207]) /* 0x40013BC0 */ +#define PERI_MS_PPU_FX_LCD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[208]) /* 0x40013C00 */ +#define PERI_MS_PPU_FX_USBFS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[209]) /* 0x40013C40 */ +#define PERI_MS_PPU_FX_SMIF0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[210]) /* 0x40013C80 */ +#define PERI_MS_PPU_FX_SDHC0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[211]) /* 0x40013CC0 */ +#define PERI_MS_PPU_FX_SDHC1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[212]) /* 0x40013D00 */ +#define PERI_MS_PPU_FX_SCB0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[213]) /* 0x40013D40 */ +#define PERI_MS_PPU_FX_SCB1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[214]) /* 0x40013D80 */ +#define PERI_MS_PPU_FX_SCB2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[215]) /* 0x40013DC0 */ +#define PERI_MS_PPU_FX_SCB3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[216]) /* 0x40013E00 */ +#define PERI_MS_PPU_FX_SCB4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[217]) /* 0x40013E40 */ +#define PERI_MS_PPU_FX_SCB5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[218]) /* 0x40013E80 */ +#define PERI_MS_PPU_FX_SCB6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[219]) /* 0x40013EC0 */ +#define PERI_MS_PPU_FX_SCB7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[220]) /* 0x40013F00 */ +#define PERI_MS_PPU_FX_SCB8 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[221]) /* 0x40013F40 */ +#define PERI_MS_PPU_FX_SCB9 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[222]) /* 0x40013F80 */ +#define PERI_MS_PPU_FX_SCB10 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[223]) /* 0x40013FC0 */ +#define PERI_MS_PPU_FX_SCB11 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[224]) /* 0x40014000 */ +#define PERI_MS_PPU_FX_SCB12 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[225]) /* 0x40014040 */ +#define PERI_MS_PPU_FX_PDM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[226]) /* 0x40014080 */ +#define PERI_MS_PPU_FX_I2S0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[227]) /* 0x400140C0 */ +#define PERI_MS_PPU_FX_I2S1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[228]) /* 0x40014100 */ + +/******************************************************************************* +* CPUSS +*******************************************************************************/ + +#define CPUSS_BASE 0x40200000UL +#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40200000 */ + +/******************************************************************************* +* FAULT +*******************************************************************************/ + +#define FAULT_BASE 0x40210000UL +#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40210000 */ +#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40210000 */ +#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40210100 */ + +/******************************************************************************* +* IPC +*******************************************************************************/ + +#define IPC_BASE 0x40220000UL +#define IPC ((IPC_Type*) IPC_BASE) /* 0x40220000 */ +#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40220000 */ +#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40220020 */ +#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40220040 */ +#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40220060 */ +#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40220080 */ +#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402200A0 */ +#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402200C0 */ +#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402200E0 */ +#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40220100 */ +#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40220120 */ +#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40220140 */ +#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40220160 */ +#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40220180 */ +#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402201A0 */ +#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402201C0 */ +#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402201E0 */ +#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40221000 */ +#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40221020 */ +#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40221040 */ +#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40221060 */ +#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40221080 */ +#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402210A0 */ +#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402210C0 */ +#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402210E0 */ +#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40221100 */ +#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40221120 */ +#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40221140 */ +#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40221160 */ +#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40221180 */ +#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402211A0 */ +#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402211C0 */ +#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402211E0 */ + +/******************************************************************************* +* PROT +*******************************************************************************/ + +#define PROT_BASE 0x40230000UL +#define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ +#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ +#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ +#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402320C0 */ +#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40232100 */ +#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40232140 */ +#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40232180 */ +#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402321C0 */ +#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40232200 */ +#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40232240 */ +#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40232280 */ +#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402322C0 */ +#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40232300 */ +#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ +#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ +#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ +#define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ +#define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ +#define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ +#define PROT_MPU5_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[3]) /* 0x40235660 */ +#define PROT_MPU5_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[4]) /* 0x40235680 */ +#define PROT_MPU5_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[5]) /* 0x402356A0 */ +#define PROT_MPU5_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[6]) /* 0x402356C0 */ +#define PROT_MPU5_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[7]) /* 0x402356E0 */ +#define PROT_MPU6_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[0]) /* 0x40235A00 */ +#define PROT_MPU6_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[1]) /* 0x40235A20 */ +#define PROT_MPU6_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[2]) /* 0x40235A40 */ +#define PROT_MPU6_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[3]) /* 0x40235A60 */ +#define PROT_MPU6_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[4]) /* 0x40235A80 */ +#define PROT_MPU6_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[5]) /* 0x40235AA0 */ +#define PROT_MPU6_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[6]) /* 0x40235AC0 */ +#define PROT_MPU6_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[7]) /* 0x40235AE0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ + +/******************************************************************************* +* FLASHC +*******************************************************************************/ + +#define FLASHC_BASE 0x40240000UL +#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40240000 */ +#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4024F000 */ + +/******************************************************************************* +* SRSS +*******************************************************************************/ + +#define SRSS_BASE 0x40260000UL +#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ +#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */ +#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */ + +/******************************************************************************* +* BACKUP +*******************************************************************************/ + +#define BACKUP_BASE 0x40270000UL +#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ + +/******************************************************************************* +* DW +*******************************************************************************/ + +#define DW0_BASE 0x40280000UL +#define DW1_BASE 0x40290000UL +#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ +#define DW1 ((DW_Type*) DW1_BASE) /* 0x40290000 */ +#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40288000 */ +#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40288040 */ +#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40288080 */ +#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x402880C0 */ +#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40288100 */ +#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x40288140 */ +#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x40288180 */ +#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402881C0 */ +#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40288200 */ +#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40288240 */ +#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40288280 */ +#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x402882C0 */ +#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40288300 */ +#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x40288340 */ +#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x40288380 */ +#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402883C0 */ +#define DW0_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[16]) /* 0x40288400 */ +#define DW0_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[17]) /* 0x40288440 */ +#define DW0_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[18]) /* 0x40288480 */ +#define DW0_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[19]) /* 0x402884C0 */ +#define DW0_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[20]) /* 0x40288500 */ +#define DW0_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[21]) /* 0x40288540 */ +#define DW0_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[22]) /* 0x40288580 */ +#define DW0_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[23]) /* 0x402885C0 */ +#define DW0_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[24]) /* 0x40288600 */ +#define DW0_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[25]) /* 0x40288640 */ +#define DW0_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[26]) /* 0x40288680 */ +#define DW0_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[27]) /* 0x402886C0 */ +#define DW0_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[28]) /* 0x40288700 */ +#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40298000 */ +#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40298040 */ +#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40298080 */ +#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x402980C0 */ +#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40298100 */ +#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x40298140 */ +#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x40298180 */ +#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402981C0 */ +#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40298200 */ +#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40298240 */ +#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40298280 */ +#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x402982C0 */ +#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40298300 */ +#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x40298340 */ +#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x40298380 */ +#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402983C0 */ +#define DW1_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[16]) /* 0x40298400 */ +#define DW1_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[17]) /* 0x40298440 */ +#define DW1_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[18]) /* 0x40298480 */ +#define DW1_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[19]) /* 0x402984C0 */ +#define DW1_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[20]) /* 0x40298500 */ +#define DW1_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[21]) /* 0x40298540 */ +#define DW1_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[22]) /* 0x40298580 */ +#define DW1_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[23]) /* 0x402985C0 */ +#define DW1_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[24]) /* 0x40298600 */ +#define DW1_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[25]) /* 0x40298640 */ +#define DW1_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[26]) /* 0x40298680 */ +#define DW1_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[27]) /* 0x402986C0 */ +#define DW1_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[28]) /* 0x40298700 */ + +/******************************************************************************* +* DMAC +*******************************************************************************/ + +#define DMAC_BASE 0x402A0000UL +#define DMAC ((DMAC_Type*) DMAC_BASE) /* 0x402A0000 */ +#define DMAC_CH0 ((DMAC_CH_Type*) &DMAC->CH[0]) /* 0x402A1000 */ +#define DMAC_CH1 ((DMAC_CH_Type*) &DMAC->CH[1]) /* 0x402A1100 */ +#define DMAC_CH2 ((DMAC_CH_Type*) &DMAC->CH[2]) /* 0x402A1200 */ +#define DMAC_CH3 ((DMAC_CH_Type*) &DMAC->CH[3]) /* 0x402A1300 */ + +/******************************************************************************* +* EFUSE +*******************************************************************************/ + +#define EFUSE_BASE 0x402C0000UL +#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ + +/******************************************************************************* +* PROFILE +*******************************************************************************/ + +#define PROFILE_BASE 0x402D0000UL +#define PROFILE ((PROFILE_Type*) PROFILE_BASE) /* 0x402D0000 */ +#define PROFILE_CNT_STRUCT0 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[0]) /* 0x402D0800 */ +#define PROFILE_CNT_STRUCT1 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[1]) /* 0x402D0810 */ +#define PROFILE_CNT_STRUCT2 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[2]) /* 0x402D0820 */ +#define PROFILE_CNT_STRUCT3 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[3]) /* 0x402D0830 */ +#define PROFILE_CNT_STRUCT4 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[4]) /* 0x402D0840 */ +#define PROFILE_CNT_STRUCT5 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[5]) /* 0x402D0850 */ +#define PROFILE_CNT_STRUCT6 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[6]) /* 0x402D0860 */ +#define PROFILE_CNT_STRUCT7 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[7]) /* 0x402D0870 */ + +/******************************************************************************* +* HSIOM +*******************************************************************************/ + +#define HSIOM_BASE 0x40300000UL +#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40300000 */ +#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40300000 */ +#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40300010 */ +#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40300020 */ +#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40300030 */ +#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40300040 */ +#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40300050 */ +#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40300060 */ +#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40300070 */ +#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40300080 */ +#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40300090 */ +#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403000A0 */ +#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403000B0 */ +#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403000C0 */ +#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403000D0 */ +#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403000E0 */ + +/******************************************************************************* +* GPIO +*******************************************************************************/ + +#define GPIO_BASE 0x40310000UL +#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40310000 */ +#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40310000 */ +#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40310080 */ +#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40310100 */ +#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40310180 */ +#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40310200 */ +#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40310280 */ +#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40310300 */ +#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40310380 */ +#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40310400 */ +#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40310480 */ +#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40310500 */ +#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40310580 */ +#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40310600 */ +#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40310680 */ +#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40310700 */ + +/******************************************************************************* +* SMARTIO +*******************************************************************************/ + +#define SMARTIO_BASE 0x40320000UL +#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40320000 */ +#define SMARTIO_PRT8 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[8]) /* 0x40320800 */ +#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40320900 */ + +/******************************************************************************* +* LPCOMP +*******************************************************************************/ + +#define LPCOMP_BASE 0x40350000UL +#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */ + +/******************************************************************************* +* CSD +*******************************************************************************/ + +#define CSD0_BASE 0x40360000UL +#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */ + +/******************************************************************************* +* TCPWM +*******************************************************************************/ + +#define TCPWM0_BASE 0x40380000UL +#define TCPWM1_BASE 0x40390000UL +#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM1 ((TCPWM_Type*) TCPWM1_BASE) /* 0x40390000 */ +#define TCPWM0_CNT0 ((TCPWM_CNT_Type*) &TCPWM0->CNT[0]) /* 0x40380100 */ +#define TCPWM0_CNT1 ((TCPWM_CNT_Type*) &TCPWM0->CNT[1]) /* 0x40380140 */ +#define TCPWM0_CNT2 ((TCPWM_CNT_Type*) &TCPWM0->CNT[2]) /* 0x40380180 */ +#define TCPWM0_CNT3 ((TCPWM_CNT_Type*) &TCPWM0->CNT[3]) /* 0x403801C0 */ +#define TCPWM0_CNT4 ((TCPWM_CNT_Type*) &TCPWM0->CNT[4]) /* 0x40380200 */ +#define TCPWM0_CNT5 ((TCPWM_CNT_Type*) &TCPWM0->CNT[5]) /* 0x40380240 */ +#define TCPWM0_CNT6 ((TCPWM_CNT_Type*) &TCPWM0->CNT[6]) /* 0x40380280 */ +#define TCPWM0_CNT7 ((TCPWM_CNT_Type*) &TCPWM0->CNT[7]) /* 0x403802C0 */ +#define TCPWM1_CNT0 ((TCPWM_CNT_Type*) &TCPWM1->CNT[0]) /* 0x40390100 */ +#define TCPWM1_CNT1 ((TCPWM_CNT_Type*) &TCPWM1->CNT[1]) /* 0x40390140 */ +#define TCPWM1_CNT2 ((TCPWM_CNT_Type*) &TCPWM1->CNT[2]) /* 0x40390180 */ +#define TCPWM1_CNT3 ((TCPWM_CNT_Type*) &TCPWM1->CNT[3]) /* 0x403901C0 */ +#define TCPWM1_CNT4 ((TCPWM_CNT_Type*) &TCPWM1->CNT[4]) /* 0x40390200 */ +#define TCPWM1_CNT5 ((TCPWM_CNT_Type*) &TCPWM1->CNT[5]) /* 0x40390240 */ +#define TCPWM1_CNT6 ((TCPWM_CNT_Type*) &TCPWM1->CNT[6]) /* 0x40390280 */ +#define TCPWM1_CNT7 ((TCPWM_CNT_Type*) &TCPWM1->CNT[7]) /* 0x403902C0 */ +#define TCPWM1_CNT8 ((TCPWM_CNT_Type*) &TCPWM1->CNT[8]) /* 0x40390300 */ +#define TCPWM1_CNT9 ((TCPWM_CNT_Type*) &TCPWM1->CNT[9]) /* 0x40390340 */ +#define TCPWM1_CNT10 ((TCPWM_CNT_Type*) &TCPWM1->CNT[10]) /* 0x40390380 */ +#define TCPWM1_CNT11 ((TCPWM_CNT_Type*) &TCPWM1->CNT[11]) /* 0x403903C0 */ +#define TCPWM1_CNT12 ((TCPWM_CNT_Type*) &TCPWM1->CNT[12]) /* 0x40390400 */ +#define TCPWM1_CNT13 ((TCPWM_CNT_Type*) &TCPWM1->CNT[13]) /* 0x40390440 */ +#define TCPWM1_CNT14 ((TCPWM_CNT_Type*) &TCPWM1->CNT[14]) /* 0x40390480 */ +#define TCPWM1_CNT15 ((TCPWM_CNT_Type*) &TCPWM1->CNT[15]) /* 0x403904C0 */ +#define TCPWM1_CNT16 ((TCPWM_CNT_Type*) &TCPWM1->CNT[16]) /* 0x40390500 */ +#define TCPWM1_CNT17 ((TCPWM_CNT_Type*) &TCPWM1->CNT[17]) /* 0x40390540 */ +#define TCPWM1_CNT18 ((TCPWM_CNT_Type*) &TCPWM1->CNT[18]) /* 0x40390580 */ +#define TCPWM1_CNT19 ((TCPWM_CNT_Type*) &TCPWM1->CNT[19]) /* 0x403905C0 */ +#define TCPWM1_CNT20 ((TCPWM_CNT_Type*) &TCPWM1->CNT[20]) /* 0x40390600 */ +#define TCPWM1_CNT21 ((TCPWM_CNT_Type*) &TCPWM1->CNT[21]) /* 0x40390640 */ +#define TCPWM1_CNT22 ((TCPWM_CNT_Type*) &TCPWM1->CNT[22]) /* 0x40390680 */ +#define TCPWM1_CNT23 ((TCPWM_CNT_Type*) &TCPWM1->CNT[23]) /* 0x403906C0 */ + +/******************************************************************************* +* LCD +*******************************************************************************/ + +#define LCD0_BASE 0x403B0000UL +#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ + +/******************************************************************************* +* USBFS +*******************************************************************************/ + +#define USBFS0_BASE 0x403F0000UL +#define USBFS0 ((USBFS_Type*) USBFS0_BASE) /* 0x403F0000 */ +#define USBFS0_USBDEV ((USBFS_USBDEV_Type*) &USBFS0->USBDEV) /* 0x403F0000 */ +#define USBFS0_USBLPM ((USBFS_USBLPM_Type*) &USBFS0->USBLPM) /* 0x403F2000 */ +#define USBFS0_USBHOST ((USBFS_USBHOST_Type*) &USBFS0->USBHOST) /* 0x403F4000 */ + +/******************************************************************************* +* SMIF +*******************************************************************************/ + +#define SMIF0_BASE 0x40420000UL +#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ +#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ +#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ +#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ +#define SMIF0_DEVICE3 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[3]) /* 0x40420980 */ + +/******************************************************************************* +* SDHC +*******************************************************************************/ + +#define SDHC0_BASE 0x40460000UL +#define SDHC1_BASE 0x40470000UL +#define SDHC0 ((SDHC_Type*) SDHC0_BASE) /* 0x40460000 */ +#define SDHC1 ((SDHC_Type*) SDHC1_BASE) /* 0x40470000 */ +#define SDHC0_WRAP ((SDHC_WRAP_Type*) &SDHC0->WRAP) /* 0x40460000 */ +#define SDHC1_WRAP ((SDHC_WRAP_Type*) &SDHC1->WRAP) /* 0x40470000 */ +#define SDHC0_CORE ((SDHC_CORE_Type*) &SDHC0->CORE) /* 0x40461000 */ +#define SDHC1_CORE ((SDHC_CORE_Type*) &SDHC1->CORE) /* 0x40471000 */ + +/******************************************************************************* +* SCB +*******************************************************************************/ + +#define SCB0_BASE 0x40600000UL +#define SCB1_BASE 0x40610000UL +#define SCB2_BASE 0x40620000UL +#define SCB3_BASE 0x40630000UL +#define SCB4_BASE 0x40640000UL +#define SCB5_BASE 0x40650000UL +#define SCB6_BASE 0x40660000UL +#define SCB7_BASE 0x40670000UL +#define SCB8_BASE 0x40680000UL +#define SCB9_BASE 0x40690000UL +#define SCB10_BASE 0x406A0000UL +#define SCB11_BASE 0x406B0000UL +#define SCB12_BASE 0x406C0000UL +#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40600000 */ +#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40610000 */ +#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40620000 */ +#define SCB3 ((CySCB_Type*) SCB3_BASE) /* 0x40630000 */ +#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40640000 */ +#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40650000 */ +#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40660000 */ +#define SCB7 ((CySCB_Type*) SCB7_BASE) /* 0x40670000 */ +#define SCB8 ((CySCB_Type*) SCB8_BASE) /* 0x40680000 */ +#define SCB9 ((CySCB_Type*) SCB9_BASE) /* 0x40690000 */ +#define SCB10 ((CySCB_Type*) SCB10_BASE) /* 0x406A0000 */ +#define SCB11 ((CySCB_Type*) SCB11_BASE) /* 0x406B0000 */ +#define SCB12 ((CySCB_Type*) SCB12_BASE) /* 0x406C0000 */ + +/******************************************************************************* +* SAR +*******************************************************************************/ + +#define SAR_BASE 0x409D0000UL +#define SAR ((SAR_Type*) SAR_BASE) /* 0x409D0000 */ + +/******************************************************************************* +* PASS +*******************************************************************************/ + +#define PASS_BASE 0x409F0000UL +#define PASS ((PASS_Type*) PASS_BASE) /* 0x409F0000 */ +#define PASS_AREF ((PASS_AREF_Type*) &PASS->AREF) /* 0x409F0E00 */ + +/******************************************************************************* +* PDM +*******************************************************************************/ + +#define PDM0_BASE 0x40A00000UL +#define PDM0 ((PDM_Type*) PDM0_BASE) /* 0x40A00000 */ + +/******************************************************************************* +* I2S +*******************************************************************************/ + +#define I2S0_BASE 0x40A10000UL +#define I2S1_BASE 0x40A11000UL +#define I2S0 ((I2S_Type*) I2S0_BASE) /* 0x40A10000 */ +#define I2S1 ((I2S_Type*) I2S1_BASE) /* 0x40A11000 */ + +/** \} CY8C614AFNI-S2F03 */ + +#endif /* _CY8C614AFNI_S2F03_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c614afni_s2f43.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c614afni_s2f43.h new file mode 100644 index 0000000000..ef4adad9f0 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c614afni_s2f43.h @@ -0,0 +1,1098 @@ +/***************************************************************************//** +* \file cy8c614afni_s2f43.h +* +* \brief +* CY8C614AFNI-S2F43 device header +* +* \note +* Generator version: 1.6.0.225 +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CY8C614AFNI_S2F43_H_ +#define _CY8C614AFNI_S2F43_H_ + +/** +* \addtogroup group_device CY8C614AFNI-S2F43 +* \{ +*/ + +/** +* \addtogroup Configuration_of_CMSIS +* \{ +*/ + +/******************************************************************************* +* Interrupt Number Definition +*******************************************************************************/ + +typedef enum { + /* ARM Cortex-M4 Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C614AFNI-S2F43 Peripheral Interrupt Numbers */ + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_1_IRQn = 1, /*!< 1 [DeepSleep] GPIO Port Interrupt #1 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_4_IRQn = 4, /*!< 4 [DeepSleep] GPIO Port Interrupt #4 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_13_IRQn = 13, /*!< 13 [DeepSleep] GPIO Port Interrupt #13 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_8_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #8 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + scb_6_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #6 */ + scb_7_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #7 */ + scb_9_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #9 */ + scb_10_interrupt_IRQn = 48, /*!< 48 [Active] Serial Communication Block #10 */ + scb_11_interrupt_IRQn = 49, /*!< 49 [Active] Serial Communication Block #11 */ + scb_12_interrupt_IRQn = 50, /*!< 50 [Active] Serial Communication Block #12 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dmac_2_IRQn = 54, /*!< 54 [Active] CPUSS DMAC, Channel #2 */ + cpuss_interrupts_dmac_3_IRQn = 55, /*!< 55 [Active] CPUSS DMAC, Channel #3 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_0_interrupts_4_IRQn = 127, /*!< 127 [Active] TCPWM #0, Counter #4 */ + tcpwm_0_interrupts_5_IRQn = 128, /*!< 128 [Active] TCPWM #0, Counter #5 */ + tcpwm_0_interrupts_6_IRQn = 129, /*!< 129 [Active] TCPWM #0, Counter #6 */ + tcpwm_0_interrupts_7_IRQn = 130, /*!< 130 [Active] TCPWM #0, Counter #7 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + tcpwm_1_interrupts_8_IRQn = 139, /*!< 139 [Active] TCPWM #1, Counter #8 */ + tcpwm_1_interrupts_9_IRQn = 140, /*!< 140 [Active] TCPWM #1, Counter #9 */ + tcpwm_1_interrupts_10_IRQn = 141, /*!< 141 [Active] TCPWM #1, Counter #10 */ + tcpwm_1_interrupts_11_IRQn = 142, /*!< 142 [Active] TCPWM #1, Counter #11 */ + tcpwm_1_interrupts_12_IRQn = 143, /*!< 143 [Active] TCPWM #1, Counter #12 */ + tcpwm_1_interrupts_13_IRQn = 144, /*!< 144 [Active] TCPWM #1, Counter #13 */ + tcpwm_1_interrupts_14_IRQn = 145, /*!< 145 [Active] TCPWM #1, Counter #14 */ + tcpwm_1_interrupts_15_IRQn = 146, /*!< 146 [Active] TCPWM #1, Counter #15 */ + tcpwm_1_interrupts_16_IRQn = 147, /*!< 147 [Active] TCPWM #1, Counter #16 */ + tcpwm_1_interrupts_17_IRQn = 148, /*!< 148 [Active] TCPWM #1, Counter #17 */ + tcpwm_1_interrupts_18_IRQn = 149, /*!< 149 [Active] TCPWM #1, Counter #18 */ + tcpwm_1_interrupts_19_IRQn = 150, /*!< 150 [Active] TCPWM #1, Counter #19 */ + tcpwm_1_interrupts_20_IRQn = 151, /*!< 151 [Active] TCPWM #1, Counter #20 */ + tcpwm_1_interrupts_21_IRQn = 152, /*!< 152 [Active] TCPWM #1, Counter #21 */ + tcpwm_1_interrupts_22_IRQn = 153, /*!< 153 [Active] TCPWM #1, Counter #22 */ + tcpwm_1_interrupts_23_IRQn = 154, /*!< 154 [Active] TCPWM #1, Counter #23 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + audioss_0_interrupt_i2s_IRQn = 156, /*!< 156 [Active] I2S0 Audio interrupt */ + audioss_0_interrupt_pdm_IRQn = 157, /*!< 157 [Active] PDM0/PCM0 Audio interrupt */ + audioss_1_interrupt_i2s_IRQn = 158, /*!< 158 [Active] I2S1 Audio interrupt */ + profile_interrupt_IRQn = 159, /*!< 159 [Active] Energy Profiler interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + sdhc_1_interrupt_wakeup_IRQn = 166, /*!< 166 [Active] EEMC wakeup interrupt for mxsdhc, not used */ + sdhc_1_interrupt_general_IRQn = 167, /*!< 167 [Active] Consolidated interrupt for mxsdhc for everything else */ + unconnected_IRQn = 240 /*!< 240 Unconnected */ +} IRQn_Type; + + +/******************************************************************************* +* Processor and Core Peripheral Section +*******************************************************************************/ + +/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __CM0P_PRESENT 0 /*!< CM0P present or not */ +#define __DTCM_PRESENT 0 /*!< DTCM present or not */ +#define __ICACHE_PRESENT 0 /*!< ICACHE present or not */ +#define __DCACHE_PRESENT 0 /*!< DCACHE present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + + +/* Memory Blocks */ +#define CY_ROM_BASE 0x00000000UL +#define CY_ROM_SIZE 0x00010000UL +#define CY_SRAM_BASE 0x08000000UL +#define CY_SRAM_SIZE 0x00100000UL +#define CY_FLASH_BASE 0x10000000UL +#define CY_FLASH_SIZE 0x00200000UL +#define CY_EM_EEPROM_BASE 0x14000000UL +#define CY_EM_EEPROM_SIZE 0x00008000UL +#define CY_SFLASH_BASE 0x16000000UL +#define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL +#define CY_EFUSE_BASE 0x402C0800UL +#define CY_EFUSE_SIZE 0x00000200UL + +#include "system_psoc6.h" /*!< PSoC 6 System */ + +/* IP List */ +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 2u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_M4CPUSS 1u +#define CY_IP_M4CPUSS_INSTANCES 1u +#define CY_IP_M4CPUSS_VERSION 2u +#define CY_IP_M4CPUSS_DMAC 1u +#define CY_IP_M4CPUSS_DMAC_INSTANCES 1u +#define CY_IP_M4CPUSS_DMAC_VERSION 2u +#define CY_IP_M4CPUSS_DMA 1u +#define CY_IP_M4CPUSS_DMA_INSTANCES 2u +#define CY_IP_M4CPUSS_DMA_VERSION 2u +#define CY_IP_MXCRYPTO 1u +#define CY_IP_MXCRYPTO_INSTANCES 1u +#define CY_IP_MXCRYPTO_VERSION 2u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u +#define CY_IP_MXS40PASS 1u +#define CY_IP_MXS40PASS_INSTANCES 1u +#define CY_IP_MXS40PASS_VERSION 1u +#define CY_IP_MXS40PASS_SAR 1u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u +#define CY_IP_MXS40PASS_SAR_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXPROFILE 1u +#define CY_IP_MXPROFILE_INSTANCES 1u +#define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 13u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 2u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u + +#include "psoc6_02_config.h" +#include "gpio_psoc6_02_100_wlcsp.h" + +#define CY_DEVICE_PSOC6A2M +#define CY_SILICON_ID 0xE4601202UL +#define CY_HF_CLK_MAX_FREQ 150000000UL + +#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL + +/******************************************************************************* +* SFLASH +*******************************************************************************/ + +#define SFLASH_BASE 0x16000000UL +#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */ + +/******************************************************************************* +* PERI +*******************************************************************************/ + +#define PERI_BASE 0x40000000UL +#define PERI ((PERI_Type*) PERI_BASE) /* 0x40000000 */ +#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40004000 */ +#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40004020 */ +#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40004040 */ +#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x40004060 */ +#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40004080 */ +#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x400040C0 */ +#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40004120 */ +#define PERI_GR10 ((PERI_GR_Type*) &PERI->GR[10]) /* 0x40004140 */ +#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40008000 */ +#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40008400 */ +#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40008800 */ +#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40008C00 */ +#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40009000 */ +#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40009400 */ +#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40009800 */ +#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40009C00 */ +#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ +#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ +#define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ +#define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ +#define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ +#define PERI_TR_1TO1_GR3 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[3]) /* 0x4000CC00 */ +#define PERI_TR_1TO1_GR4 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[4]) /* 0x4000D000 */ +#define PERI_TR_1TO1_GR5 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[5]) /* 0x4000D400 */ +#define PERI_TR_1TO1_GR6 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[6]) /* 0x4000D800 */ + +/******************************************************************************* +* PERI_MS +*******************************************************************************/ + +#define PERI_MS_BASE 0x40010000UL +#define PERI_MS ((PERI_MS_Type*) PERI_MS_BASE) /* 0x40010000 */ +#define PERI_MS_PPU_PR0 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[0]) /* 0x40010000 */ +#define PERI_MS_PPU_PR1 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[1]) /* 0x40010040 */ +#define PERI_MS_PPU_PR2 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[2]) /* 0x40010080 */ +#define PERI_MS_PPU_PR3 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[3]) /* 0x400100C0 */ +#define PERI_MS_PPU_PR4 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[4]) /* 0x40010100 */ +#define PERI_MS_PPU_PR5 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[5]) /* 0x40010140 */ +#define PERI_MS_PPU_PR6 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[6]) /* 0x40010180 */ +#define PERI_MS_PPU_PR7 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[7]) /* 0x400101C0 */ +#define PERI_MS_PPU_FX_PERI_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[0]) /* 0x40010800 */ +#define PERI_MS_PPU_FX_PERI_GR0_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[1]) /* 0x40010840 */ +#define PERI_MS_PPU_FX_PERI_GR1_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[2]) /* 0x40010880 */ +#define PERI_MS_PPU_FX_PERI_GR2_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[3]) /* 0x400108C0 */ +#define PERI_MS_PPU_FX_PERI_GR3_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[4]) /* 0x40010900 */ +#define PERI_MS_PPU_FX_PERI_GR4_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[5]) /* 0x40010940 */ +#define PERI_MS_PPU_FX_PERI_GR6_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[6]) /* 0x40010980 */ +#define PERI_MS_PPU_FX_PERI_GR9_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[7]) /* 0x400109C0 */ +#define PERI_MS_PPU_FX_PERI_GR10_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[8]) /* 0x40010A00 */ +#define PERI_MS_PPU_FX_PERI_TR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[9]) /* 0x40010A40 */ +#define PERI_MS_PPU_FX_CRYPTO_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[10]) /* 0x40010A80 */ +#define PERI_MS_PPU_FX_CRYPTO_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[11]) /* 0x40010AC0 */ +#define PERI_MS_PPU_FX_CRYPTO_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[12]) /* 0x40010B00 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[13]) /* 0x40010B40 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[14]) /* 0x40010B80 */ +#define PERI_MS_PPU_FX_CRYPTO_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[15]) /* 0x40010BC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[16]) /* 0x40010C00 */ +#define PERI_MS_PPU_FX_CPUSS_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[17]) /* 0x40010C40 */ +#define PERI_MS_PPU_FX_CPUSS_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[18]) /* 0x40010C80 */ +#define PERI_MS_PPU_FX_CPUSS_CM0_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[19]) /* 0x40010CC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[20]) /* 0x40010D00 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[21]) /* 0x40010D40 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT1_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[22]) /* 0x40010D80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT0_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[23]) /* 0x40010DC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT1_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[24]) /* 0x40010E00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT2_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[25]) /* 0x40010E40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT3_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[26]) /* 0x40010E80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT4_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[27]) /* 0x40010EC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT5_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[28]) /* 0x40010F00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT6_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[29]) /* 0x40010F40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT7_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[30]) /* 0x40010F80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT8_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[31]) /* 0x40010FC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT9_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[32]) /* 0x40011000 */ +#define PERI_MS_PPU_FX_IPC_STRUCT10_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[33]) /* 0x40011040 */ +#define PERI_MS_PPU_FX_IPC_STRUCT11_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[34]) /* 0x40011080 */ +#define PERI_MS_PPU_FX_IPC_STRUCT12_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[35]) /* 0x400110C0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT13_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[36]) /* 0x40011100 */ +#define PERI_MS_PPU_FX_IPC_STRUCT14_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[37]) /* 0x40011140 */ +#define PERI_MS_PPU_FX_IPC_STRUCT15_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[38]) /* 0x40011180 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT0_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[39]) /* 0x400111C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT1_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[40]) /* 0x40011200 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT2_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[41]) /* 0x40011240 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT3_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[42]) /* 0x40011280 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT4_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[43]) /* 0x400112C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT5_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[44]) /* 0x40011300 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT6_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[45]) /* 0x40011340 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT7_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[46]) /* 0x40011380 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT8_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[47]) /* 0x400113C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT9_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[48]) /* 0x40011400 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT10_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[49]) /* 0x40011440 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT11_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[50]) /* 0x40011480 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT12_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[51]) /* 0x400114C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT13_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[52]) /* 0x40011500 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT14_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[53]) /* 0x40011540 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT15_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[54]) /* 0x40011580 */ +#define PERI_MS_PPU_FX_PROT_SMPU_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[55]) /* 0x400115C0 */ +#define PERI_MS_PPU_FX_PROT_MPU0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[56]) /* 0x40011600 */ +#define PERI_MS_PPU_FX_PROT_MPU5_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[57]) /* 0x40011640 */ +#define PERI_MS_PPU_FX_PROT_MPU6_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[58]) /* 0x40011680 */ +#define PERI_MS_PPU_FX_PROT_MPU14_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[59]) /* 0x400116C0 */ +#define PERI_MS_PPU_FX_PROT_MPU15_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[60]) /* 0x40011700 */ +#define PERI_MS_PPU_FX_FLASHC_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[61]) /* 0x40011740 */ +#define PERI_MS_PPU_FX_FLASHC_CMD ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[62]) /* 0x40011780 */ +#define PERI_MS_PPU_FX_FLASHC_DFT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[63]) /* 0x400117C0 */ +#define PERI_MS_PPU_FX_FLASHC_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[64]) /* 0x40011800 */ +#define PERI_MS_PPU_FX_FLASHC_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[65]) /* 0x40011840 */ +#define PERI_MS_PPU_FX_FLASHC_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[66]) /* 0x40011880 */ +#define PERI_MS_PPU_FX_FLASHC_DW0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[67]) /* 0x400118C0 */ +#define PERI_MS_PPU_FX_FLASHC_DW1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[68]) /* 0x40011900 */ +#define PERI_MS_PPU_FX_FLASHC_DMAC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[69]) /* 0x40011940 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[70]) /* 0x40011980 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[71]) /* 0x400119C0 */ +#define PERI_MS_PPU_FX_FLASHC_FM ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[72]) /* 0x40011A00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[73]) /* 0x40011A40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[74]) /* 0x40011A80 */ +#define PERI_MS_PPU_FX_WDT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[75]) /* 0x40011AC0 */ +#define PERI_MS_PPU_FX_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[76]) /* 0x40011B00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[77]) /* 0x40011B40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[78]) /* 0x40011B80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[79]) /* 0x40011BC0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[80]) /* 0x40011C00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[81]) /* 0x40011C40 */ +#define PERI_MS_PPU_FX_BACKUP_BACKUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[82]) /* 0x40011C80 */ +#define PERI_MS_PPU_FX_DW0_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[83]) /* 0x40011CC0 */ +#define PERI_MS_PPU_FX_DW1_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[84]) /* 0x40011D00 */ +#define PERI_MS_PPU_FX_DW0_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[85]) /* 0x40011D40 */ +#define PERI_MS_PPU_FX_DW1_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[86]) /* 0x40011D80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[87]) /* 0x40011DC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[88]) /* 0x40011E00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[89]) /* 0x40011E40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[90]) /* 0x40011E80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[91]) /* 0x40011EC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[92]) /* 0x40011F00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[93]) /* 0x40011F40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[94]) /* 0x40011F80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[95]) /* 0x40011FC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[96]) /* 0x40012000 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[97]) /* 0x40012040 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[98]) /* 0x40012080 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[99]) /* 0x400120C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[100]) /* 0x40012100 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[101]) /* 0x40012140 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[102]) /* 0x40012180 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[103]) /* 0x400121C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[104]) /* 0x40012200 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[105]) /* 0x40012240 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[106]) /* 0x40012280 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[107]) /* 0x400122C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[108]) /* 0x40012300 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[109]) /* 0x40012340 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[110]) /* 0x40012380 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[111]) /* 0x400123C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[112]) /* 0x40012400 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[113]) /* 0x40012440 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[114]) /* 0x40012480 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[115]) /* 0x400124C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[116]) /* 0x40012500 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[117]) /* 0x40012540 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[118]) /* 0x40012580 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[119]) /* 0x400125C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[120]) /* 0x40012600 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[121]) /* 0x40012640 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[122]) /* 0x40012680 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[123]) /* 0x400126C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[124]) /* 0x40012700 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[125]) /* 0x40012740 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[126]) /* 0x40012780 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[127]) /* 0x400127C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[128]) /* 0x40012800 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[129]) /* 0x40012840 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[130]) /* 0x40012880 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[131]) /* 0x400128C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[132]) /* 0x40012900 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[133]) /* 0x40012940 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[134]) /* 0x40012980 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[135]) /* 0x400129C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[136]) /* 0x40012A00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[137]) /* 0x40012A40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[138]) /* 0x40012A80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[139]) /* 0x40012AC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[140]) /* 0x40012B00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[141]) /* 0x40012B40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[142]) /* 0x40012B80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[143]) /* 0x40012BC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[144]) /* 0x40012C00 */ +#define PERI_MS_PPU_FX_DMAC_TOP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[145]) /* 0x40012C40 */ +#define PERI_MS_PPU_FX_DMAC_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[146]) /* 0x40012C80 */ +#define PERI_MS_PPU_FX_DMAC_CH1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[147]) /* 0x40012CC0 */ +#define PERI_MS_PPU_FX_DMAC_CH2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[148]) /* 0x40012D00 */ +#define PERI_MS_PPU_FX_DMAC_CH3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[149]) /* 0x40012D40 */ +#define PERI_MS_PPU_FX_EFUSE_CTL ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[150]) /* 0x40012D80 */ +#define PERI_MS_PPU_FX_EFUSE_DATA ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[151]) /* 0x40012DC0 */ +#define PERI_MS_PPU_FX_PROFILE ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[152]) /* 0x40012E00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[153]) /* 0x40012E40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[154]) /* 0x40012E80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[155]) /* 0x40012EC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[156]) /* 0x40012F00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[157]) /* 0x40012F40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[158]) /* 0x40012F80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[159]) /* 0x40012FC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[160]) /* 0x40013000 */ +#define PERI_MS_PPU_FX_HSIOM_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[161]) /* 0x40013040 */ +#define PERI_MS_PPU_FX_HSIOM_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[162]) /* 0x40013080 */ +#define PERI_MS_PPU_FX_HSIOM_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[163]) /* 0x400130C0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[164]) /* 0x40013100 */ +#define PERI_MS_PPU_FX_HSIOM_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[165]) /* 0x40013140 */ +#define PERI_MS_PPU_FX_HSIOM_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[166]) /* 0x40013180 */ +#define PERI_MS_PPU_FX_HSIOM_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[167]) /* 0x400131C0 */ +#define PERI_MS_PPU_FX_HSIOM_AMUX ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[168]) /* 0x40013200 */ +#define PERI_MS_PPU_FX_HSIOM_MON ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[169]) /* 0x40013240 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[170]) /* 0x40013280 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[171]) /* 0x400132C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[172]) /* 0x40013300 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[173]) /* 0x40013340 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[174]) /* 0x40013380 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[175]) /* 0x400133C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[176]) /* 0x40013400 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[177]) /* 0x40013440 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[178]) /* 0x40013480 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[179]) /* 0x400134C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[180]) /* 0x40013500 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[181]) /* 0x40013540 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[182]) /* 0x40013580 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[183]) /* 0x400135C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[184]) /* 0x40013600 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[185]) /* 0x40013640 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[186]) /* 0x40013680 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[187]) /* 0x400136C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[188]) /* 0x40013700 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[189]) /* 0x40013740 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[190]) /* 0x40013780 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[191]) /* 0x400137C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[192]) /* 0x40013800 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[193]) /* 0x40013840 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[194]) /* 0x40013880 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[195]) /* 0x400138C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[196]) /* 0x40013900 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[197]) /* 0x40013940 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[198]) /* 0x40013980 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[199]) /* 0x400139C0 */ +#define PERI_MS_PPU_FX_GPIO_GPIO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[200]) /* 0x40013A00 */ +#define PERI_MS_PPU_FX_GPIO_TEST ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[201]) /* 0x40013A40 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[202]) /* 0x40013A80 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[203]) /* 0x40013AC0 */ +#define PERI_MS_PPU_FX_LPCOMP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[204]) /* 0x40013B00 */ +#define PERI_MS_PPU_FX_CSD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[205]) /* 0x40013B40 */ +#define PERI_MS_PPU_FX_TCPWM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[206]) /* 0x40013B80 */ +#define PERI_MS_PPU_FX_TCPWM1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[207]) /* 0x40013BC0 */ +#define PERI_MS_PPU_FX_LCD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[208]) /* 0x40013C00 */ +#define PERI_MS_PPU_FX_USBFS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[209]) /* 0x40013C40 */ +#define PERI_MS_PPU_FX_SMIF0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[210]) /* 0x40013C80 */ +#define PERI_MS_PPU_FX_SDHC0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[211]) /* 0x40013CC0 */ +#define PERI_MS_PPU_FX_SDHC1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[212]) /* 0x40013D00 */ +#define PERI_MS_PPU_FX_SCB0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[213]) /* 0x40013D40 */ +#define PERI_MS_PPU_FX_SCB1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[214]) /* 0x40013D80 */ +#define PERI_MS_PPU_FX_SCB2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[215]) /* 0x40013DC0 */ +#define PERI_MS_PPU_FX_SCB3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[216]) /* 0x40013E00 */ +#define PERI_MS_PPU_FX_SCB4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[217]) /* 0x40013E40 */ +#define PERI_MS_PPU_FX_SCB5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[218]) /* 0x40013E80 */ +#define PERI_MS_PPU_FX_SCB6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[219]) /* 0x40013EC0 */ +#define PERI_MS_PPU_FX_SCB7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[220]) /* 0x40013F00 */ +#define PERI_MS_PPU_FX_SCB8 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[221]) /* 0x40013F40 */ +#define PERI_MS_PPU_FX_SCB9 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[222]) /* 0x40013F80 */ +#define PERI_MS_PPU_FX_SCB10 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[223]) /* 0x40013FC0 */ +#define PERI_MS_PPU_FX_SCB11 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[224]) /* 0x40014000 */ +#define PERI_MS_PPU_FX_SCB12 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[225]) /* 0x40014040 */ +#define PERI_MS_PPU_FX_PDM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[226]) /* 0x40014080 */ +#define PERI_MS_PPU_FX_I2S0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[227]) /* 0x400140C0 */ +#define PERI_MS_PPU_FX_I2S1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[228]) /* 0x40014100 */ + +/******************************************************************************* +* CRYPTO +*******************************************************************************/ + +#define CRYPTO_BASE 0x40100000UL +#define CRYPTO ((CRYPTO_Type*) CRYPTO_BASE) /* 0x40100000 */ + +/******************************************************************************* +* CPUSS +*******************************************************************************/ + +#define CPUSS_BASE 0x40200000UL +#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40200000 */ + +/******************************************************************************* +* FAULT +*******************************************************************************/ + +#define FAULT_BASE 0x40210000UL +#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40210000 */ +#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40210000 */ +#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40210100 */ + +/******************************************************************************* +* IPC +*******************************************************************************/ + +#define IPC_BASE 0x40220000UL +#define IPC ((IPC_Type*) IPC_BASE) /* 0x40220000 */ +#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40220000 */ +#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40220020 */ +#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40220040 */ +#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40220060 */ +#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40220080 */ +#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402200A0 */ +#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402200C0 */ +#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402200E0 */ +#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40220100 */ +#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40220120 */ +#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40220140 */ +#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40220160 */ +#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40220180 */ +#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402201A0 */ +#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402201C0 */ +#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402201E0 */ +#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40221000 */ +#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40221020 */ +#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40221040 */ +#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40221060 */ +#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40221080 */ +#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402210A0 */ +#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402210C0 */ +#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402210E0 */ +#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40221100 */ +#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40221120 */ +#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40221140 */ +#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40221160 */ +#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40221180 */ +#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402211A0 */ +#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402211C0 */ +#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402211E0 */ + +/******************************************************************************* +* PROT +*******************************************************************************/ + +#define PROT_BASE 0x40230000UL +#define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ +#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ +#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ +#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402320C0 */ +#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40232100 */ +#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40232140 */ +#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40232180 */ +#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402321C0 */ +#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40232200 */ +#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40232240 */ +#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40232280 */ +#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402322C0 */ +#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40232300 */ +#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ +#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ +#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ +#define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ +#define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ +#define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ +#define PROT_MPU5_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[3]) /* 0x40235660 */ +#define PROT_MPU5_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[4]) /* 0x40235680 */ +#define PROT_MPU5_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[5]) /* 0x402356A0 */ +#define PROT_MPU5_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[6]) /* 0x402356C0 */ +#define PROT_MPU5_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[7]) /* 0x402356E0 */ +#define PROT_MPU6_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[0]) /* 0x40235A00 */ +#define PROT_MPU6_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[1]) /* 0x40235A20 */ +#define PROT_MPU6_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[2]) /* 0x40235A40 */ +#define PROT_MPU6_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[3]) /* 0x40235A60 */ +#define PROT_MPU6_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[4]) /* 0x40235A80 */ +#define PROT_MPU6_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[5]) /* 0x40235AA0 */ +#define PROT_MPU6_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[6]) /* 0x40235AC0 */ +#define PROT_MPU6_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[7]) /* 0x40235AE0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ + +/******************************************************************************* +* FLASHC +*******************************************************************************/ + +#define FLASHC_BASE 0x40240000UL +#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40240000 */ +#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4024F000 */ + +/******************************************************************************* +* SRSS +*******************************************************************************/ + +#define SRSS_BASE 0x40260000UL +#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ +#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */ +#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */ + +/******************************************************************************* +* BACKUP +*******************************************************************************/ + +#define BACKUP_BASE 0x40270000UL +#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ + +/******************************************************************************* +* DW +*******************************************************************************/ + +#define DW0_BASE 0x40280000UL +#define DW1_BASE 0x40290000UL +#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ +#define DW1 ((DW_Type*) DW1_BASE) /* 0x40290000 */ +#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40288000 */ +#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40288040 */ +#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40288080 */ +#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x402880C0 */ +#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40288100 */ +#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x40288140 */ +#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x40288180 */ +#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402881C0 */ +#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40288200 */ +#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40288240 */ +#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40288280 */ +#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x402882C0 */ +#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40288300 */ +#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x40288340 */ +#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x40288380 */ +#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402883C0 */ +#define DW0_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[16]) /* 0x40288400 */ +#define DW0_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[17]) /* 0x40288440 */ +#define DW0_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[18]) /* 0x40288480 */ +#define DW0_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[19]) /* 0x402884C0 */ +#define DW0_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[20]) /* 0x40288500 */ +#define DW0_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[21]) /* 0x40288540 */ +#define DW0_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[22]) /* 0x40288580 */ +#define DW0_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[23]) /* 0x402885C0 */ +#define DW0_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[24]) /* 0x40288600 */ +#define DW0_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[25]) /* 0x40288640 */ +#define DW0_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[26]) /* 0x40288680 */ +#define DW0_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[27]) /* 0x402886C0 */ +#define DW0_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[28]) /* 0x40288700 */ +#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40298000 */ +#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40298040 */ +#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40298080 */ +#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x402980C0 */ +#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40298100 */ +#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x40298140 */ +#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x40298180 */ +#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402981C0 */ +#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40298200 */ +#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40298240 */ +#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40298280 */ +#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x402982C0 */ +#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40298300 */ +#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x40298340 */ +#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x40298380 */ +#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402983C0 */ +#define DW1_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[16]) /* 0x40298400 */ +#define DW1_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[17]) /* 0x40298440 */ +#define DW1_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[18]) /* 0x40298480 */ +#define DW1_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[19]) /* 0x402984C0 */ +#define DW1_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[20]) /* 0x40298500 */ +#define DW1_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[21]) /* 0x40298540 */ +#define DW1_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[22]) /* 0x40298580 */ +#define DW1_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[23]) /* 0x402985C0 */ +#define DW1_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[24]) /* 0x40298600 */ +#define DW1_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[25]) /* 0x40298640 */ +#define DW1_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[26]) /* 0x40298680 */ +#define DW1_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[27]) /* 0x402986C0 */ +#define DW1_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[28]) /* 0x40298700 */ + +/******************************************************************************* +* DMAC +*******************************************************************************/ + +#define DMAC_BASE 0x402A0000UL +#define DMAC ((DMAC_Type*) DMAC_BASE) /* 0x402A0000 */ +#define DMAC_CH0 ((DMAC_CH_Type*) &DMAC->CH[0]) /* 0x402A1000 */ +#define DMAC_CH1 ((DMAC_CH_Type*) &DMAC->CH[1]) /* 0x402A1100 */ +#define DMAC_CH2 ((DMAC_CH_Type*) &DMAC->CH[2]) /* 0x402A1200 */ +#define DMAC_CH3 ((DMAC_CH_Type*) &DMAC->CH[3]) /* 0x402A1300 */ + +/******************************************************************************* +* EFUSE +*******************************************************************************/ + +#define EFUSE_BASE 0x402C0000UL +#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ + +/******************************************************************************* +* PROFILE +*******************************************************************************/ + +#define PROFILE_BASE 0x402D0000UL +#define PROFILE ((PROFILE_Type*) PROFILE_BASE) /* 0x402D0000 */ +#define PROFILE_CNT_STRUCT0 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[0]) /* 0x402D0800 */ +#define PROFILE_CNT_STRUCT1 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[1]) /* 0x402D0810 */ +#define PROFILE_CNT_STRUCT2 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[2]) /* 0x402D0820 */ +#define PROFILE_CNT_STRUCT3 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[3]) /* 0x402D0830 */ +#define PROFILE_CNT_STRUCT4 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[4]) /* 0x402D0840 */ +#define PROFILE_CNT_STRUCT5 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[5]) /* 0x402D0850 */ +#define PROFILE_CNT_STRUCT6 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[6]) /* 0x402D0860 */ +#define PROFILE_CNT_STRUCT7 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[7]) /* 0x402D0870 */ + +/******************************************************************************* +* HSIOM +*******************************************************************************/ + +#define HSIOM_BASE 0x40300000UL +#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40300000 */ +#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40300000 */ +#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40300010 */ +#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40300020 */ +#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40300030 */ +#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40300040 */ +#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40300050 */ +#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40300060 */ +#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40300070 */ +#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40300080 */ +#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40300090 */ +#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403000A0 */ +#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403000B0 */ +#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403000C0 */ +#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403000D0 */ +#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403000E0 */ + +/******************************************************************************* +* GPIO +*******************************************************************************/ + +#define GPIO_BASE 0x40310000UL +#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40310000 */ +#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40310000 */ +#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40310080 */ +#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40310100 */ +#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40310180 */ +#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40310200 */ +#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40310280 */ +#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40310300 */ +#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40310380 */ +#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40310400 */ +#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40310480 */ +#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40310500 */ +#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40310580 */ +#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40310600 */ +#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40310680 */ +#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40310700 */ + +/******************************************************************************* +* SMARTIO +*******************************************************************************/ + +#define SMARTIO_BASE 0x40320000UL +#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40320000 */ +#define SMARTIO_PRT8 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[8]) /* 0x40320800 */ +#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40320900 */ + +/******************************************************************************* +* LPCOMP +*******************************************************************************/ + +#define LPCOMP_BASE 0x40350000UL +#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */ + +/******************************************************************************* +* CSD +*******************************************************************************/ + +#define CSD0_BASE 0x40360000UL +#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */ + +/******************************************************************************* +* TCPWM +*******************************************************************************/ + +#define TCPWM0_BASE 0x40380000UL +#define TCPWM1_BASE 0x40390000UL +#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM1 ((TCPWM_Type*) TCPWM1_BASE) /* 0x40390000 */ +#define TCPWM0_CNT0 ((TCPWM_CNT_Type*) &TCPWM0->CNT[0]) /* 0x40380100 */ +#define TCPWM0_CNT1 ((TCPWM_CNT_Type*) &TCPWM0->CNT[1]) /* 0x40380140 */ +#define TCPWM0_CNT2 ((TCPWM_CNT_Type*) &TCPWM0->CNT[2]) /* 0x40380180 */ +#define TCPWM0_CNT3 ((TCPWM_CNT_Type*) &TCPWM0->CNT[3]) /* 0x403801C0 */ +#define TCPWM0_CNT4 ((TCPWM_CNT_Type*) &TCPWM0->CNT[4]) /* 0x40380200 */ +#define TCPWM0_CNT5 ((TCPWM_CNT_Type*) &TCPWM0->CNT[5]) /* 0x40380240 */ +#define TCPWM0_CNT6 ((TCPWM_CNT_Type*) &TCPWM0->CNT[6]) /* 0x40380280 */ +#define TCPWM0_CNT7 ((TCPWM_CNT_Type*) &TCPWM0->CNT[7]) /* 0x403802C0 */ +#define TCPWM1_CNT0 ((TCPWM_CNT_Type*) &TCPWM1->CNT[0]) /* 0x40390100 */ +#define TCPWM1_CNT1 ((TCPWM_CNT_Type*) &TCPWM1->CNT[1]) /* 0x40390140 */ +#define TCPWM1_CNT2 ((TCPWM_CNT_Type*) &TCPWM1->CNT[2]) /* 0x40390180 */ +#define TCPWM1_CNT3 ((TCPWM_CNT_Type*) &TCPWM1->CNT[3]) /* 0x403901C0 */ +#define TCPWM1_CNT4 ((TCPWM_CNT_Type*) &TCPWM1->CNT[4]) /* 0x40390200 */ +#define TCPWM1_CNT5 ((TCPWM_CNT_Type*) &TCPWM1->CNT[5]) /* 0x40390240 */ +#define TCPWM1_CNT6 ((TCPWM_CNT_Type*) &TCPWM1->CNT[6]) /* 0x40390280 */ +#define TCPWM1_CNT7 ((TCPWM_CNT_Type*) &TCPWM1->CNT[7]) /* 0x403902C0 */ +#define TCPWM1_CNT8 ((TCPWM_CNT_Type*) &TCPWM1->CNT[8]) /* 0x40390300 */ +#define TCPWM1_CNT9 ((TCPWM_CNT_Type*) &TCPWM1->CNT[9]) /* 0x40390340 */ +#define TCPWM1_CNT10 ((TCPWM_CNT_Type*) &TCPWM1->CNT[10]) /* 0x40390380 */ +#define TCPWM1_CNT11 ((TCPWM_CNT_Type*) &TCPWM1->CNT[11]) /* 0x403903C0 */ +#define TCPWM1_CNT12 ((TCPWM_CNT_Type*) &TCPWM1->CNT[12]) /* 0x40390400 */ +#define TCPWM1_CNT13 ((TCPWM_CNT_Type*) &TCPWM1->CNT[13]) /* 0x40390440 */ +#define TCPWM1_CNT14 ((TCPWM_CNT_Type*) &TCPWM1->CNT[14]) /* 0x40390480 */ +#define TCPWM1_CNT15 ((TCPWM_CNT_Type*) &TCPWM1->CNT[15]) /* 0x403904C0 */ +#define TCPWM1_CNT16 ((TCPWM_CNT_Type*) &TCPWM1->CNT[16]) /* 0x40390500 */ +#define TCPWM1_CNT17 ((TCPWM_CNT_Type*) &TCPWM1->CNT[17]) /* 0x40390540 */ +#define TCPWM1_CNT18 ((TCPWM_CNT_Type*) &TCPWM1->CNT[18]) /* 0x40390580 */ +#define TCPWM1_CNT19 ((TCPWM_CNT_Type*) &TCPWM1->CNT[19]) /* 0x403905C0 */ +#define TCPWM1_CNT20 ((TCPWM_CNT_Type*) &TCPWM1->CNT[20]) /* 0x40390600 */ +#define TCPWM1_CNT21 ((TCPWM_CNT_Type*) &TCPWM1->CNT[21]) /* 0x40390640 */ +#define TCPWM1_CNT22 ((TCPWM_CNT_Type*) &TCPWM1->CNT[22]) /* 0x40390680 */ +#define TCPWM1_CNT23 ((TCPWM_CNT_Type*) &TCPWM1->CNT[23]) /* 0x403906C0 */ + +/******************************************************************************* +* LCD +*******************************************************************************/ + +#define LCD0_BASE 0x403B0000UL +#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ + +/******************************************************************************* +* USBFS +*******************************************************************************/ + +#define USBFS0_BASE 0x403F0000UL +#define USBFS0 ((USBFS_Type*) USBFS0_BASE) /* 0x403F0000 */ +#define USBFS0_USBDEV ((USBFS_USBDEV_Type*) &USBFS0->USBDEV) /* 0x403F0000 */ +#define USBFS0_USBLPM ((USBFS_USBLPM_Type*) &USBFS0->USBLPM) /* 0x403F2000 */ +#define USBFS0_USBHOST ((USBFS_USBHOST_Type*) &USBFS0->USBHOST) /* 0x403F4000 */ + +/******************************************************************************* +* SMIF +*******************************************************************************/ + +#define SMIF0_BASE 0x40420000UL +#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ +#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ +#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ +#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ +#define SMIF0_DEVICE3 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[3]) /* 0x40420980 */ + +/******************************************************************************* +* SDHC +*******************************************************************************/ + +#define SDHC0_BASE 0x40460000UL +#define SDHC1_BASE 0x40470000UL +#define SDHC0 ((SDHC_Type*) SDHC0_BASE) /* 0x40460000 */ +#define SDHC1 ((SDHC_Type*) SDHC1_BASE) /* 0x40470000 */ +#define SDHC0_WRAP ((SDHC_WRAP_Type*) &SDHC0->WRAP) /* 0x40460000 */ +#define SDHC1_WRAP ((SDHC_WRAP_Type*) &SDHC1->WRAP) /* 0x40470000 */ +#define SDHC0_CORE ((SDHC_CORE_Type*) &SDHC0->CORE) /* 0x40461000 */ +#define SDHC1_CORE ((SDHC_CORE_Type*) &SDHC1->CORE) /* 0x40471000 */ + +/******************************************************************************* +* SCB +*******************************************************************************/ + +#define SCB0_BASE 0x40600000UL +#define SCB1_BASE 0x40610000UL +#define SCB2_BASE 0x40620000UL +#define SCB3_BASE 0x40630000UL +#define SCB4_BASE 0x40640000UL +#define SCB5_BASE 0x40650000UL +#define SCB6_BASE 0x40660000UL +#define SCB7_BASE 0x40670000UL +#define SCB8_BASE 0x40680000UL +#define SCB9_BASE 0x40690000UL +#define SCB10_BASE 0x406A0000UL +#define SCB11_BASE 0x406B0000UL +#define SCB12_BASE 0x406C0000UL +#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40600000 */ +#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40610000 */ +#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40620000 */ +#define SCB3 ((CySCB_Type*) SCB3_BASE) /* 0x40630000 */ +#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40640000 */ +#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40650000 */ +#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40660000 */ +#define SCB7 ((CySCB_Type*) SCB7_BASE) /* 0x40670000 */ +#define SCB8 ((CySCB_Type*) SCB8_BASE) /* 0x40680000 */ +#define SCB9 ((CySCB_Type*) SCB9_BASE) /* 0x40690000 */ +#define SCB10 ((CySCB_Type*) SCB10_BASE) /* 0x406A0000 */ +#define SCB11 ((CySCB_Type*) SCB11_BASE) /* 0x406B0000 */ +#define SCB12 ((CySCB_Type*) SCB12_BASE) /* 0x406C0000 */ + +/******************************************************************************* +* SAR +*******************************************************************************/ + +#define SAR_BASE 0x409D0000UL +#define SAR ((SAR_Type*) SAR_BASE) /* 0x409D0000 */ + +/******************************************************************************* +* PASS +*******************************************************************************/ + +#define PASS_BASE 0x409F0000UL +#define PASS ((PASS_Type*) PASS_BASE) /* 0x409F0000 */ +#define PASS_AREF ((PASS_AREF_Type*) &PASS->AREF) /* 0x409F0E00 */ + +/******************************************************************************* +* PDM +*******************************************************************************/ + +#define PDM0_BASE 0x40A00000UL +#define PDM0 ((PDM_Type*) PDM0_BASE) /* 0x40A00000 */ + +/******************************************************************************* +* I2S +*******************************************************************************/ + +#define I2S0_BASE 0x40A10000UL +#define I2S1_BASE 0x40A11000UL +#define I2S0 ((I2S_Type*) I2S0_BASE) /* 0x40A10000 */ +#define I2S1 ((I2S_Type*) I2S1_BASE) /* 0x40A11000 */ + +/** \} CY8C614AFNI-S2F43 */ + +#endif /* _CY8C614AFNI_S2F43_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6244azi_s4d12.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6244azi_s4d12.h index 73c2a285df..63a7c2c370 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6244azi_s4d12.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6244azi_s4d12.h @@ -5,7 +5,7 @@ * CY8C6244AZI-S4D12 device header * * \note -* Generator version: 1.6.0.111 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -432,14 +432,14 @@ typedef enum { #define CY_FLASH_SIZE 0x00040000UL #define CY_EM_EEPROM_BASE 0x14000000UL #define CY_EM_EEPROM_SIZE 0x00000000UL -#define CY_XIP_BASE 0x18000000UL -#define CY_XIP_SIZE 0x08000000UL -#define CY_CAN0MRAM_BASE 0x40530000UL -#define CY_CAN0MRAM_SIZE 0x00010000UL #define CY_SFLASH_BASE 0x16000000UL #define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL #define CY_EFUSE_BASE 0x402C0800UL #define CY_EFUSE_SIZE 0x00000200UL +#define CY_CAN0MRAM_BASE 0x40530000UL +#define CY_CAN0MRAM_SIZE 0x00010000UL #include "system_psoc6.h" /*!< PSoC 6 System */ @@ -471,15 +471,6 @@ typedef enum { #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u -//#define CY_IP_MXS40PASS 1u -//#define CY_IP_MXS40PASS_INSTANCES 1u -//#define CY_IP_MXS40PASS_VERSION 2u -//#define CY_IP_MXS40PASS_SAR 1u -//#define CY_IP_MXS40PASS_SAR_INSTANCES 1u -//#define CY_IP_MXS40PASS_SAR_VERSION 2u -//#define CY_IP_MXS40PASS_CTDAC 1u -//#define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u -//#define CY_IP_MXS40PASS_CTDAC_VERSION 2u #define CY_IP_MXPERI 1u #define CY_IP_MXPERI_INSTANCES 1u #define CY_IP_MXPERI_VERSION 2u @@ -501,9 +492,6 @@ typedef enum { #define CY_IP_MXS40SRSS_MCWDT 1u #define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u #define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -//#define CY_IP_MXTCPWM 1u -//#define CY_IP_MXTCPWM_INSTANCES 1u -//#define CY_IP_MXTCPWM_VERSION 2u #include "psoc6_04_config.h" #include "gpio_psoc6_04_64_tqfp.h" @@ -546,6 +534,7 @@ typedef enum { #define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ #define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ #define PERI_TR_GR10 ((PERI_TR_GR_Type*) &PERI->TR_GR[10]) /* 0x4000A800 */ +#define PERI_TR_GR11 ((PERI_TR_GR_Type*) &PERI->TR_GR[11]) /* 0x4000AC00 */ #define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ #define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ #define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ @@ -858,6 +847,7 @@ typedef enum { #define PROT_BASE 0x40230000UL #define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ #define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ #define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ #define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ @@ -874,15 +864,6 @@ typedef enum { #define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ #define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ #define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ -#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ -#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ -#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ -#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ -#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ -#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ -#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ -#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ -#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ #define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ #define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ #define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ @@ -899,6 +880,14 @@ typedef enum { #define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ #define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ #define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ /******************************************************************************* * FLASHC @@ -1083,6 +1072,8 @@ typedef enum { #define TCPWM0_BASE 0x40380000UL #define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM0_GRP0 ((TCPWM_GRP_Type*) &TCPWM0->GRP[0]) /* 0x40380000 */ +#define TCPWM0_GRP1 ((TCPWM_GRP_Type*) &TCPWM0->GRP[1]) /* 0x40388000 */ #define TCPWM0_GRP0_CNT0 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[0]) /* 0x40380000 */ #define TCPWM0_GRP0_CNT1 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[1]) /* 0x40380080 */ #define TCPWM0_GRP0_CNT2 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[2]) /* 0x40380100 */ @@ -1095,8 +1086,6 @@ typedef enum { #define TCPWM0_GRP1_CNT5 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[5]) /* 0x40388280 */ #define TCPWM0_GRP1_CNT6 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[6]) /* 0x40388300 */ #define TCPWM0_GRP1_CNT7 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[7]) /* 0x40388380 */ -#define TCPWM0_GRP0 ((TCPWM_GRP_Type*) &TCPWM0->GRP[0]) /* 0x40380000 */ -#define TCPWM0_GRP1 ((TCPWM_GRP_Type*) &TCPWM0->GRP[1]) /* 0x40388000 */ /******************************************************************************* * LCD @@ -1121,8 +1110,8 @@ typedef enum { #define CANFD0_BASE 0x40520000UL #define CANFD0 ((CANFD_Type*) CANFD0_BASE) /* 0x40520000 */ -#define CANFD0_CH0_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[0].M_TTCAN) /* 0x40520000 */ #define CANFD0_CH0 ((CANFD_CH_Type*) &CANFD0->CH[0]) /* 0x40520000 */ +#define CANFD0_CH0_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[0].M_TTCAN) /* 0x40520000 */ /******************************************************************************* * SCB @@ -1160,9 +1149,7 @@ typedef enum { *******************************************************************************/ #define SAR0_BASE 0x409B0000UL -#define SAR1_BASE 0x409C0000UL #define SAR0 ((SAR_Type*) SAR0_BASE) /* 0x409B0000 */ -#define SAR1 ((SAR_Type*) SAR1_BASE) /* 0x409C0000 */ /******************************************************************************* * PASS diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6244azi_s4d62.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6244azi_s4d62.h index 77ec38f623..149fab3153 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6244azi_s4d62.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6244azi_s4d62.h @@ -5,7 +5,7 @@ * CY8C6244AZI-S4D62 device header * * \note -* Generator version: 1.6.0.111 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -432,14 +432,14 @@ typedef enum { #define CY_FLASH_SIZE 0x00040000UL #define CY_EM_EEPROM_BASE 0x14000000UL #define CY_EM_EEPROM_SIZE 0x00000000UL -#define CY_XIP_BASE 0x18000000UL -#define CY_XIP_SIZE 0x08000000UL -#define CY_CAN0MRAM_BASE 0x40530000UL -#define CY_CAN0MRAM_SIZE 0x00010000UL #define CY_SFLASH_BASE 0x16000000UL #define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL #define CY_EFUSE_BASE 0x402C0800UL #define CY_EFUSE_SIZE 0x00000200UL +#define CY_CAN0MRAM_BASE 0x40530000UL +#define CY_CAN0MRAM_SIZE 0x00010000UL #include "system_psoc6.h" /*!< PSoC 6 System */ @@ -471,15 +471,6 @@ typedef enum { #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u -//#define CY_IP_MXS40PASS 1u -//#define CY_IP_MXS40PASS_INSTANCES 1u -//#define CY_IP_MXS40PASS_VERSION 2u -//#define CY_IP_MXS40PASS_SAR 1u -//#define CY_IP_MXS40PASS_SAR_INSTANCES 1u -//#define CY_IP_MXS40PASS_SAR_VERSION 2u -//#define CY_IP_MXS40PASS_CTDAC 1u -//#define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u -//#define CY_IP_MXS40PASS_CTDAC_VERSION 2u #define CY_IP_MXPERI 1u #define CY_IP_MXPERI_INSTANCES 1u #define CY_IP_MXPERI_VERSION 2u @@ -501,9 +492,6 @@ typedef enum { #define CY_IP_MXS40SRSS_MCWDT 1u #define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u #define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -//#define CY_IP_MXTCPWM 1u -//#define CY_IP_MXTCPWM_INSTANCES 1u -//#define CY_IP_MXTCPWM_VERSION 2u #include "psoc6_04_config.h" #include "gpio_psoc6_04_64_tqfp.h" @@ -546,6 +534,7 @@ typedef enum { #define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ #define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ #define PERI_TR_GR10 ((PERI_TR_GR_Type*) &PERI->TR_GR[10]) /* 0x4000A800 */ +#define PERI_TR_GR11 ((PERI_TR_GR_Type*) &PERI->TR_GR[11]) /* 0x4000AC00 */ #define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ #define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ #define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ @@ -858,6 +847,7 @@ typedef enum { #define PROT_BASE 0x40230000UL #define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ #define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ #define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ #define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ @@ -874,15 +864,6 @@ typedef enum { #define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ #define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ #define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ -#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ -#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ -#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ -#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ -#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ -#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ -#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ -#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ -#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ #define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ #define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ #define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ @@ -899,6 +880,14 @@ typedef enum { #define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ #define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ #define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ /******************************************************************************* * FLASHC @@ -1083,6 +1072,8 @@ typedef enum { #define TCPWM0_BASE 0x40380000UL #define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM0_GRP0 ((TCPWM_GRP_Type*) &TCPWM0->GRP[0]) /* 0x40380000 */ +#define TCPWM0_GRP1 ((TCPWM_GRP_Type*) &TCPWM0->GRP[1]) /* 0x40388000 */ #define TCPWM0_GRP0_CNT0 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[0]) /* 0x40380000 */ #define TCPWM0_GRP0_CNT1 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[1]) /* 0x40380080 */ #define TCPWM0_GRP0_CNT2 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[2]) /* 0x40380100 */ @@ -1095,8 +1086,6 @@ typedef enum { #define TCPWM0_GRP1_CNT5 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[5]) /* 0x40388280 */ #define TCPWM0_GRP1_CNT6 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[6]) /* 0x40388300 */ #define TCPWM0_GRP1_CNT7 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[7]) /* 0x40388380 */ -#define TCPWM0_GRP0 ((TCPWM_GRP_Type*) &TCPWM0->GRP[0]) /* 0x40380000 */ -#define TCPWM0_GRP1 ((TCPWM_GRP_Type*) &TCPWM0->GRP[1]) /* 0x40388000 */ /******************************************************************************* * LCD @@ -1121,8 +1110,8 @@ typedef enum { #define CANFD0_BASE 0x40520000UL #define CANFD0 ((CANFD_Type*) CANFD0_BASE) /* 0x40520000 */ -#define CANFD0_CH0_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[0].M_TTCAN) /* 0x40520000 */ #define CANFD0_CH0 ((CANFD_CH_Type*) &CANFD0->CH[0]) /* 0x40520000 */ +#define CANFD0_CH0_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[0].M_TTCAN) /* 0x40520000 */ /******************************************************************************* * SCB @@ -1160,9 +1149,7 @@ typedef enum { *******************************************************************************/ #define SAR0_BASE 0x409B0000UL -#define SAR1_BASE 0x409C0000UL #define SAR0 ((SAR_Type*) SAR0_BASE) /* 0x409B0000 */ -#define SAR1 ((SAR_Type*) SAR1_BASE) /* 0x409C0000 */ /******************************************************************************* * PASS diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6244azi_s4d82.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6244azi_s4d82.h index 715ec78614..743b96e694 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6244azi_s4d82.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6244azi_s4d82.h @@ -5,7 +5,7 @@ * CY8C6244AZI-S4D82 device header * * \note -* Generator version: 1.6.0.111 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -432,14 +432,14 @@ typedef enum { #define CY_FLASH_SIZE 0x00040000UL #define CY_EM_EEPROM_BASE 0x14000000UL #define CY_EM_EEPROM_SIZE 0x00000000UL -#define CY_XIP_BASE 0x18000000UL -#define CY_XIP_SIZE 0x08000000UL -#define CY_CAN0MRAM_BASE 0x40530000UL -#define CY_CAN0MRAM_SIZE 0x00010000UL #define CY_SFLASH_BASE 0x16000000UL #define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL #define CY_EFUSE_BASE 0x402C0800UL #define CY_EFUSE_SIZE 0x00000200UL +#define CY_CAN0MRAM_BASE 0x40530000UL +#define CY_CAN0MRAM_SIZE 0x00010000UL #include "system_psoc6.h" /*!< PSoC 6 System */ @@ -474,18 +474,6 @@ typedef enum { #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u -//#define CY_IP_MXS40PASS 1u -//#define CY_IP_MXS40PASS_INSTANCES 1u -//#define CY_IP_MXS40PASS_VERSION 2u -//#define CY_IP_MXS40PASS_SAR 1u -//#define CY_IP_MXS40PASS_SAR_INSTANCES 1u -//#define CY_IP_MXS40PASS_SAR_VERSION 2u -//#define CY_IP_MXS40PASS_CTDAC 1u -//#define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u -//#define CY_IP_MXS40PASS_CTDAC_VERSION 2u -//#define CY_IP_MXS40PASS_CTB 1u -//#define CY_IP_MXS40PASS_CTB_INSTANCES 1u -//#define CY_IP_MXS40PASS_CTB_VERSION 2u #define CY_IP_MXPERI 1u #define CY_IP_MXPERI_INSTANCES 1u #define CY_IP_MXPERI_VERSION 2u @@ -507,9 +495,6 @@ typedef enum { #define CY_IP_MXS40SRSS_MCWDT 1u #define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u #define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -//#define CY_IP_MXTCPWM 1u -//#define CY_IP_MXTCPWM_INSTANCES 1u -//#define CY_IP_MXTCPWM_VERSION 2u #include "psoc6_04_config.h" #include "gpio_psoc6_04_64_tqfp.h" @@ -552,6 +537,7 @@ typedef enum { #define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ #define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ #define PERI_TR_GR10 ((PERI_TR_GR_Type*) &PERI->TR_GR[10]) /* 0x4000A800 */ +#define PERI_TR_GR11 ((PERI_TR_GR_Type*) &PERI->TR_GR[11]) /* 0x4000AC00 */ #define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ #define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ #define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ @@ -871,6 +857,7 @@ typedef enum { #define PROT_BASE 0x40230000UL #define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ #define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ #define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ #define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ @@ -887,15 +874,6 @@ typedef enum { #define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ #define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ #define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ -#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ -#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ -#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ -#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ -#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ -#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ -#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ -#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ -#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ #define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ #define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ #define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ @@ -912,6 +890,14 @@ typedef enum { #define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ #define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ #define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ /******************************************************************************* * FLASHC @@ -1096,6 +1082,8 @@ typedef enum { #define TCPWM0_BASE 0x40380000UL #define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM0_GRP0 ((TCPWM_GRP_Type*) &TCPWM0->GRP[0]) /* 0x40380000 */ +#define TCPWM0_GRP1 ((TCPWM_GRP_Type*) &TCPWM0->GRP[1]) /* 0x40388000 */ #define TCPWM0_GRP0_CNT0 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[0]) /* 0x40380000 */ #define TCPWM0_GRP0_CNT1 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[1]) /* 0x40380080 */ #define TCPWM0_GRP0_CNT2 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[2]) /* 0x40380100 */ @@ -1108,8 +1096,6 @@ typedef enum { #define TCPWM0_GRP1_CNT5 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[5]) /* 0x40388280 */ #define TCPWM0_GRP1_CNT6 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[6]) /* 0x40388300 */ #define TCPWM0_GRP1_CNT7 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[7]) /* 0x40388380 */ -#define TCPWM0_GRP0 ((TCPWM_GRP_Type*) &TCPWM0->GRP[0]) /* 0x40380000 */ -#define TCPWM0_GRP1 ((TCPWM_GRP_Type*) &TCPWM0->GRP[1]) /* 0x40388000 */ /******************************************************************************* * LCD @@ -1134,8 +1120,8 @@ typedef enum { #define CANFD0_BASE 0x40520000UL #define CANFD0 ((CANFD_Type*) CANFD0_BASE) /* 0x40520000 */ -#define CANFD0_CH0_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[0].M_TTCAN) /* 0x40520000 */ #define CANFD0_CH0 ((CANFD_CH_Type*) &CANFD0->CH[0]) /* 0x40520000 */ +#define CANFD0_CH0_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[0].M_TTCAN) /* 0x40520000 */ /******************************************************************************* * SCB diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6244azi_s4d83.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6244azi_s4d83.h index 4d33399acb..a372cb5995 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6244azi_s4d83.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6244azi_s4d83.h @@ -5,7 +5,7 @@ * CY8C6244AZI-S4D83 device header * * \note -* Generator version: 1.6.0.111 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -432,14 +432,14 @@ typedef enum { #define CY_FLASH_SIZE 0x00040000UL #define CY_EM_EEPROM_BASE 0x14000000UL #define CY_EM_EEPROM_SIZE 0x00000000UL -#define CY_XIP_BASE 0x18000000UL -#define CY_XIP_SIZE 0x08000000UL -#define CY_CAN0MRAM_BASE 0x40530000UL -#define CY_CAN0MRAM_SIZE 0x00010000UL #define CY_SFLASH_BASE 0x16000000UL #define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL #define CY_EFUSE_BASE 0x402C0800UL #define CY_EFUSE_SIZE 0x00000200UL +#define CY_CAN0MRAM_BASE 0x40530000UL +#define CY_CAN0MRAM_SIZE 0x00010000UL #include "system_psoc6.h" /*!< PSoC 6 System */ @@ -474,18 +474,6 @@ typedef enum { #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u -//#define CY_IP_MXS40PASS 1u -//#define CY_IP_MXS40PASS_INSTANCES 1u -//#define CY_IP_MXS40PASS_VERSION 2u -//#define CY_IP_MXS40PASS_SAR 1u -//#define CY_IP_MXS40PASS_SAR_INSTANCES 1u -//#define CY_IP_MXS40PASS_SAR_VERSION 2u -//#define CY_IP_MXS40PASS_CTDAC 1u -//#define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u -//#define CY_IP_MXS40PASS_CTDAC_VERSION 2u -//#define CY_IP_MXS40PASS_CTB 1u -//#define CY_IP_MXS40PASS_CTB_INSTANCES 1u -//#define CY_IP_MXS40PASS_CTB_VERSION 2u #define CY_IP_MXPERI 1u #define CY_IP_MXPERI_INSTANCES 1u #define CY_IP_MXPERI_VERSION 2u @@ -507,9 +495,6 @@ typedef enum { #define CY_IP_MXS40SRSS_MCWDT 1u #define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u #define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -//#define CY_IP_MXTCPWM 1u -//#define CY_IP_MXTCPWM_INSTANCES 1u -//#define CY_IP_MXTCPWM_VERSION 2u #include "psoc6_04_config.h" #include "gpio_psoc6_04_80_tqfp.h" @@ -552,6 +537,7 @@ typedef enum { #define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ #define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ #define PERI_TR_GR10 ((PERI_TR_GR_Type*) &PERI->TR_GR[10]) /* 0x4000A800 */ +#define PERI_TR_GR11 ((PERI_TR_GR_Type*) &PERI->TR_GR[11]) /* 0x4000AC00 */ #define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ #define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ #define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ @@ -871,6 +857,7 @@ typedef enum { #define PROT_BASE 0x40230000UL #define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ #define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ #define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ #define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ @@ -887,15 +874,6 @@ typedef enum { #define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ #define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ #define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ -#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ -#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ -#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ -#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ -#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ -#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ -#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ -#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ -#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ #define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ #define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ #define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ @@ -912,6 +890,14 @@ typedef enum { #define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ #define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ #define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ /******************************************************************************* * FLASHC @@ -1096,6 +1082,8 @@ typedef enum { #define TCPWM0_BASE 0x40380000UL #define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM0_GRP0 ((TCPWM_GRP_Type*) &TCPWM0->GRP[0]) /* 0x40380000 */ +#define TCPWM0_GRP1 ((TCPWM_GRP_Type*) &TCPWM0->GRP[1]) /* 0x40388000 */ #define TCPWM0_GRP0_CNT0 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[0]) /* 0x40380000 */ #define TCPWM0_GRP0_CNT1 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[1]) /* 0x40380080 */ #define TCPWM0_GRP0_CNT2 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[2]) /* 0x40380100 */ @@ -1108,8 +1096,6 @@ typedef enum { #define TCPWM0_GRP1_CNT5 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[5]) /* 0x40388280 */ #define TCPWM0_GRP1_CNT6 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[6]) /* 0x40388300 */ #define TCPWM0_GRP1_CNT7 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[7]) /* 0x40388380 */ -#define TCPWM0_GRP0 ((TCPWM_GRP_Type*) &TCPWM0->GRP[0]) /* 0x40380000 */ -#define TCPWM0_GRP1 ((TCPWM_GRP_Type*) &TCPWM0->GRP[1]) /* 0x40388000 */ /******************************************************************************* * LCD @@ -1134,8 +1120,8 @@ typedef enum { #define CANFD0_BASE 0x40520000UL #define CANFD0 ((CANFD_Type*) CANFD0_BASE) /* 0x40520000 */ -#define CANFD0_CH0_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[0].M_TTCAN) /* 0x40520000 */ #define CANFD0_CH0 ((CANFD_CH_Type*) &CANFD0->CH[0]) /* 0x40520000 */ +#define CANFD0_CH0_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[0].M_TTCAN) /* 0x40520000 */ /******************************************************************************* * SCB diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6244azi_s4d92.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6244azi_s4d92.h index 071c9cdd0a..5d7a245c0a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6244azi_s4d92.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6244azi_s4d92.h @@ -5,7 +5,7 @@ * CY8C6244AZI-S4D92 device header * * \note -* Generator version: 1.6.0.111 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -432,14 +432,14 @@ typedef enum { #define CY_FLASH_SIZE 0x00040000UL #define CY_EM_EEPROM_BASE 0x14000000UL #define CY_EM_EEPROM_SIZE 0x00000000UL -#define CY_XIP_BASE 0x18000000UL -#define CY_XIP_SIZE 0x08000000UL -#define CY_CAN0MRAM_BASE 0x40530000UL -#define CY_CAN0MRAM_SIZE 0x00010000UL #define CY_SFLASH_BASE 0x16000000UL #define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL #define CY_EFUSE_BASE 0x402C0800UL #define CY_EFUSE_SIZE 0x00000200UL +#define CY_CAN0MRAM_BASE 0x40530000UL +#define CY_CAN0MRAM_SIZE 0x00010000UL #include "system_psoc6.h" /*!< PSoC 6 System */ @@ -474,18 +474,6 @@ typedef enum { #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u -//#define CY_IP_MXS40PASS 1u -//#define CY_IP_MXS40PASS_INSTANCES 1u -//#define CY_IP_MXS40PASS_VERSION 2u -//#define CY_IP_MXS40PASS_SAR 1u -//#define CY_IP_MXS40PASS_SAR_INSTANCES 1u -//#define CY_IP_MXS40PASS_SAR_VERSION 2u -//#define CY_IP_MXS40PASS_CTDAC 1u -//#define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u -//#define CY_IP_MXS40PASS_CTDAC_VERSION 2u -//#define CY_IP_MXS40PASS_CTB 1u -//#define CY_IP_MXS40PASS_CTB_INSTANCES 1u -//#define CY_IP_MXS40PASS_CTB_VERSION 2u #define CY_IP_MXPERI 1u #define CY_IP_MXPERI_INSTANCES 1u #define CY_IP_MXPERI_VERSION 2u @@ -507,9 +495,6 @@ typedef enum { #define CY_IP_MXS40SRSS_MCWDT 1u #define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u #define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -//#define CY_IP_MXTCPWM 1u -//#define CY_IP_MXTCPWM_INSTANCES 1u -//#define CY_IP_MXTCPWM_VERSION 2u #include "psoc6_04_config.h" #include "gpio_psoc6_04_64_tqfp.h" @@ -552,6 +537,7 @@ typedef enum { #define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ #define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ #define PERI_TR_GR10 ((PERI_TR_GR_Type*) &PERI->TR_GR[10]) /* 0x4000A800 */ +#define PERI_TR_GR11 ((PERI_TR_GR_Type*) &PERI->TR_GR[11]) /* 0x4000AC00 */ #define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ #define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ #define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ @@ -871,6 +857,7 @@ typedef enum { #define PROT_BASE 0x40230000UL #define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ #define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ #define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ #define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ @@ -887,15 +874,6 @@ typedef enum { #define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ #define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ #define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ -#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ -#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ -#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ -#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ -#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ -#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ -#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ -#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ -#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ #define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ #define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ #define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ @@ -912,6 +890,14 @@ typedef enum { #define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ #define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ #define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ /******************************************************************************* * FLASHC @@ -1096,6 +1082,8 @@ typedef enum { #define TCPWM0_BASE 0x40380000UL #define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM0_GRP0 ((TCPWM_GRP_Type*) &TCPWM0->GRP[0]) /* 0x40380000 */ +#define TCPWM0_GRP1 ((TCPWM_GRP_Type*) &TCPWM0->GRP[1]) /* 0x40388000 */ #define TCPWM0_GRP0_CNT0 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[0]) /* 0x40380000 */ #define TCPWM0_GRP0_CNT1 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[1]) /* 0x40380080 */ #define TCPWM0_GRP0_CNT2 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[2]) /* 0x40380100 */ @@ -1108,8 +1096,6 @@ typedef enum { #define TCPWM0_GRP1_CNT5 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[5]) /* 0x40388280 */ #define TCPWM0_GRP1_CNT6 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[6]) /* 0x40388300 */ #define TCPWM0_GRP1_CNT7 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[7]) /* 0x40388380 */ -#define TCPWM0_GRP0 ((TCPWM_GRP_Type*) &TCPWM0->GRP[0]) /* 0x40380000 */ -#define TCPWM0_GRP1 ((TCPWM_GRP_Type*) &TCPWM0->GRP[1]) /* 0x40388000 */ /******************************************************************************* * LCD @@ -1134,8 +1120,8 @@ typedef enum { #define CANFD0_BASE 0x40520000UL #define CANFD0 ((CANFD_Type*) CANFD0_BASE) /* 0x40520000 */ -#define CANFD0_CH0_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[0].M_TTCAN) /* 0x40520000 */ #define CANFD0_CH0 ((CANFD_CH_Type*) &CANFD0->CH[0]) /* 0x40520000 */ +#define CANFD0_CH0_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[0].M_TTCAN) /* 0x40520000 */ /******************************************************************************* * SCB diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6244azi_s4d93.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6244azi_s4d93.h index 7316b0652e..2d2b98bf78 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6244azi_s4d93.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6244azi_s4d93.h @@ -5,7 +5,7 @@ * CY8C6244AZI-S4D93 device header * * \note -* Generator version: 1.6.0.111 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -432,14 +432,14 @@ typedef enum { #define CY_FLASH_SIZE 0x00040000UL #define CY_EM_EEPROM_BASE 0x14000000UL #define CY_EM_EEPROM_SIZE 0x00000000UL -#define CY_XIP_BASE 0x18000000UL -#define CY_XIP_SIZE 0x08000000UL -#define CY_CAN0MRAM_BASE 0x40530000UL -#define CY_CAN0MRAM_SIZE 0x00010000UL #define CY_SFLASH_BASE 0x16000000UL #define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL #define CY_EFUSE_BASE 0x402C0800UL #define CY_EFUSE_SIZE 0x00000200UL +#define CY_CAN0MRAM_BASE 0x40530000UL +#define CY_CAN0MRAM_SIZE 0x00010000UL #include "system_psoc6.h" /*!< PSoC 6 System */ @@ -474,18 +474,6 @@ typedef enum { #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u -//#define CY_IP_MXS40PASS 1u -//#define CY_IP_MXS40PASS_INSTANCES 1u -//#define CY_IP_MXS40PASS_VERSION 2u -//#define CY_IP_MXS40PASS_SAR 1u -//#define CY_IP_MXS40PASS_SAR_INSTANCES 1u -//#define CY_IP_MXS40PASS_SAR_VERSION 2u -//#define CY_IP_MXS40PASS_CTDAC 1u -//#define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u -//#define CY_IP_MXS40PASS_CTDAC_VERSION 2u -//#define CY_IP_MXS40PASS_CTB 1u -//#define CY_IP_MXS40PASS_CTB_INSTANCES 1u -//#define CY_IP_MXS40PASS_CTB_VERSION 2u #define CY_IP_MXPERI 1u #define CY_IP_MXPERI_INSTANCES 1u #define CY_IP_MXPERI_VERSION 2u @@ -507,9 +495,6 @@ typedef enum { #define CY_IP_MXS40SRSS_MCWDT 1u #define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u #define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -//#define CY_IP_MXTCPWM 1u -//#define CY_IP_MXTCPWM_INSTANCES 1u -//#define CY_IP_MXTCPWM_VERSION 2u #include "psoc6_04_config.h" #include "gpio_psoc6_04_80_tqfp.h" @@ -552,6 +537,7 @@ typedef enum { #define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ #define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ #define PERI_TR_GR10 ((PERI_TR_GR_Type*) &PERI->TR_GR[10]) /* 0x4000A800 */ +#define PERI_TR_GR11 ((PERI_TR_GR_Type*) &PERI->TR_GR[11]) /* 0x4000AC00 */ #define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ #define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ #define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ @@ -871,6 +857,7 @@ typedef enum { #define PROT_BASE 0x40230000UL #define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ #define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ #define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ #define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ @@ -887,15 +874,6 @@ typedef enum { #define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ #define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ #define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ -#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ -#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ -#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ -#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ -#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ -#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ -#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ -#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ -#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ #define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ #define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ #define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ @@ -912,6 +890,14 @@ typedef enum { #define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ #define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ #define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ /******************************************************************************* * FLASHC @@ -1096,6 +1082,8 @@ typedef enum { #define TCPWM0_BASE 0x40380000UL #define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM0_GRP0 ((TCPWM_GRP_Type*) &TCPWM0->GRP[0]) /* 0x40380000 */ +#define TCPWM0_GRP1 ((TCPWM_GRP_Type*) &TCPWM0->GRP[1]) /* 0x40388000 */ #define TCPWM0_GRP0_CNT0 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[0]) /* 0x40380000 */ #define TCPWM0_GRP0_CNT1 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[1]) /* 0x40380080 */ #define TCPWM0_GRP0_CNT2 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[2]) /* 0x40380100 */ @@ -1108,8 +1096,6 @@ typedef enum { #define TCPWM0_GRP1_CNT5 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[5]) /* 0x40388280 */ #define TCPWM0_GRP1_CNT6 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[6]) /* 0x40388300 */ #define TCPWM0_GRP1_CNT7 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[7]) /* 0x40388380 */ -#define TCPWM0_GRP0 ((TCPWM_GRP_Type*) &TCPWM0->GRP[0]) /* 0x40380000 */ -#define TCPWM0_GRP1 ((TCPWM_GRP_Type*) &TCPWM0->GRP[1]) /* 0x40388000 */ /******************************************************************************* * LCD @@ -1134,8 +1120,8 @@ typedef enum { #define CANFD0_BASE 0x40520000UL #define CANFD0 ((CANFD_Type*) CANFD0_BASE) /* 0x40520000 */ -#define CANFD0_CH0_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[0].M_TTCAN) /* 0x40520000 */ #define CANFD0_CH0 ((CANFD_CH_Type*) &CANFD0->CH[0]) /* 0x40520000 */ +#define CANFD0_CH0_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[0].M_TTCAN) /* 0x40520000 */ /******************************************************************************* * SCB diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6244lqi_s4d12.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6244lqi_s4d12.h index d96979e8a3..81d71e8884 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6244lqi_s4d12.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6244lqi_s4d12.h @@ -5,7 +5,7 @@ * CY8C6244LQI-S4D12 device header * * \note -* Generator version: 1.6.0.111 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -432,14 +432,14 @@ typedef enum { #define CY_FLASH_SIZE 0x00040000UL #define CY_EM_EEPROM_BASE 0x14000000UL #define CY_EM_EEPROM_SIZE 0x00000000UL -#define CY_XIP_BASE 0x18000000UL -#define CY_XIP_SIZE 0x08000000UL -#define CY_CAN0MRAM_BASE 0x40530000UL -#define CY_CAN0MRAM_SIZE 0x00010000UL #define CY_SFLASH_BASE 0x16000000UL #define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL #define CY_EFUSE_BASE 0x402C0800UL #define CY_EFUSE_SIZE 0x00000200UL +#define CY_CAN0MRAM_BASE 0x40530000UL +#define CY_CAN0MRAM_SIZE 0x00010000UL #include "system_psoc6.h" /*!< PSoC 6 System */ @@ -471,15 +471,6 @@ typedef enum { #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u -//#define CY_IP_MXS40PASS 1u -//#define CY_IP_MXS40PASS_INSTANCES 1u -//#define CY_IP_MXS40PASS_VERSION 2u -//#define CY_IP_MXS40PASS_SAR 1u -//#define CY_IP_MXS40PASS_SAR_INSTANCES 1u -//#define CY_IP_MXS40PASS_SAR_VERSION 2u -//#define CY_IP_MXS40PASS_CTDAC 1u -//#define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u -//#define CY_IP_MXS40PASS_CTDAC_VERSION 2u #define CY_IP_MXPERI 1u #define CY_IP_MXPERI_INSTANCES 1u #define CY_IP_MXPERI_VERSION 2u @@ -501,9 +492,6 @@ typedef enum { #define CY_IP_MXS40SRSS_MCWDT 1u #define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u #define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -//#define CY_IP_MXTCPWM 1u -//#define CY_IP_MXTCPWM_INSTANCES 1u -//#define CY_IP_MXTCPWM_VERSION 2u #define CY_IP_MXUSBFS 1u #define CY_IP_MXUSBFS_INSTANCES 1u #define CY_IP_MXUSBFS_VERSION 1u @@ -549,6 +537,7 @@ typedef enum { #define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ #define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ #define PERI_TR_GR10 ((PERI_TR_GR_Type*) &PERI->TR_GR[10]) /* 0x4000A800 */ +#define PERI_TR_GR11 ((PERI_TR_GR_Type*) &PERI->TR_GR[11]) /* 0x4000AC00 */ #define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ #define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ #define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ @@ -861,6 +850,7 @@ typedef enum { #define PROT_BASE 0x40230000UL #define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ #define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ #define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ #define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ @@ -877,15 +867,6 @@ typedef enum { #define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ #define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ #define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ -#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ -#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ -#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ -#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ -#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ -#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ -#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ -#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ -#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ #define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ #define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ #define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ @@ -902,6 +883,14 @@ typedef enum { #define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ #define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ #define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ /******************************************************************************* * FLASHC @@ -1086,6 +1075,8 @@ typedef enum { #define TCPWM0_BASE 0x40380000UL #define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM0_GRP0 ((TCPWM_GRP_Type*) &TCPWM0->GRP[0]) /* 0x40380000 */ +#define TCPWM0_GRP1 ((TCPWM_GRP_Type*) &TCPWM0->GRP[1]) /* 0x40388000 */ #define TCPWM0_GRP0_CNT0 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[0]) /* 0x40380000 */ #define TCPWM0_GRP0_CNT1 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[1]) /* 0x40380080 */ #define TCPWM0_GRP0_CNT2 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[2]) /* 0x40380100 */ @@ -1098,8 +1089,6 @@ typedef enum { #define TCPWM0_GRP1_CNT5 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[5]) /* 0x40388280 */ #define TCPWM0_GRP1_CNT6 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[6]) /* 0x40388300 */ #define TCPWM0_GRP1_CNT7 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[7]) /* 0x40388380 */ -#define TCPWM0_GRP0 ((TCPWM_GRP_Type*) &TCPWM0->GRP[0]) /* 0x40380000 */ -#define TCPWM0_GRP1 ((TCPWM_GRP_Type*) &TCPWM0->GRP[1]) /* 0x40388000 */ /******************************************************************************* * LCD @@ -1134,8 +1123,8 @@ typedef enum { #define CANFD0_BASE 0x40520000UL #define CANFD0 ((CANFD_Type*) CANFD0_BASE) /* 0x40520000 */ -#define CANFD0_CH0_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[0].M_TTCAN) /* 0x40520000 */ #define CANFD0_CH0 ((CANFD_CH_Type*) &CANFD0->CH[0]) /* 0x40520000 */ +#define CANFD0_CH0_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[0].M_TTCAN) /* 0x40520000 */ /******************************************************************************* * SCB @@ -1173,9 +1162,7 @@ typedef enum { *******************************************************************************/ #define SAR0_BASE 0x409B0000UL -#define SAR1_BASE 0x409C0000UL #define SAR0 ((SAR_Type*) SAR0_BASE) /* 0x409B0000 */ -#define SAR1 ((SAR_Type*) SAR1_BASE) /* 0x409C0000 */ /******************************************************************************* * PASS diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6244lqi_s4d62.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6244lqi_s4d62.h index 78ef278243..a1c0208380 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6244lqi_s4d62.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6244lqi_s4d62.h @@ -5,7 +5,7 @@ * CY8C6244LQI-S4D62 device header * * \note -* Generator version: 1.6.0.111 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -432,14 +432,14 @@ typedef enum { #define CY_FLASH_SIZE 0x00040000UL #define CY_EM_EEPROM_BASE 0x14000000UL #define CY_EM_EEPROM_SIZE 0x00000000UL -#define CY_XIP_BASE 0x18000000UL -#define CY_XIP_SIZE 0x08000000UL -#define CY_CAN0MRAM_BASE 0x40530000UL -#define CY_CAN0MRAM_SIZE 0x00010000UL #define CY_SFLASH_BASE 0x16000000UL #define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL #define CY_EFUSE_BASE 0x402C0800UL #define CY_EFUSE_SIZE 0x00000200UL +#define CY_CAN0MRAM_BASE 0x40530000UL +#define CY_CAN0MRAM_SIZE 0x00010000UL #include "system_psoc6.h" /*!< PSoC 6 System */ @@ -471,15 +471,6 @@ typedef enum { #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u -//#define CY_IP_MXS40PASS 1u -//#define CY_IP_MXS40PASS_INSTANCES 1u -//#define CY_IP_MXS40PASS_VERSION 2u -//#define CY_IP_MXS40PASS_SAR 1u -//#define CY_IP_MXS40PASS_SAR_INSTANCES 1u -//#define CY_IP_MXS40PASS_SAR_VERSION 2u -//#define CY_IP_MXS40PASS_CTDAC 1u -//#define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u -//#define CY_IP_MXS40PASS_CTDAC_VERSION 2u #define CY_IP_MXPERI 1u #define CY_IP_MXPERI_INSTANCES 1u #define CY_IP_MXPERI_VERSION 2u @@ -501,9 +492,6 @@ typedef enum { #define CY_IP_MXS40SRSS_MCWDT 1u #define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u #define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -//#define CY_IP_MXTCPWM 1u -//#define CY_IP_MXTCPWM_INSTANCES 1u -//#define CY_IP_MXTCPWM_VERSION 2u #define CY_IP_MXUSBFS 1u #define CY_IP_MXUSBFS_INSTANCES 1u #define CY_IP_MXUSBFS_VERSION 1u @@ -549,6 +537,7 @@ typedef enum { #define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ #define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ #define PERI_TR_GR10 ((PERI_TR_GR_Type*) &PERI->TR_GR[10]) /* 0x4000A800 */ +#define PERI_TR_GR11 ((PERI_TR_GR_Type*) &PERI->TR_GR[11]) /* 0x4000AC00 */ #define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ #define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ #define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ @@ -861,6 +850,7 @@ typedef enum { #define PROT_BASE 0x40230000UL #define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ #define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ #define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ #define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ @@ -877,15 +867,6 @@ typedef enum { #define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ #define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ #define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ -#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ -#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ -#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ -#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ -#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ -#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ -#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ -#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ -#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ #define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ #define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ #define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ @@ -902,6 +883,14 @@ typedef enum { #define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ #define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ #define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ /******************************************************************************* * FLASHC @@ -1086,6 +1075,8 @@ typedef enum { #define TCPWM0_BASE 0x40380000UL #define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM0_GRP0 ((TCPWM_GRP_Type*) &TCPWM0->GRP[0]) /* 0x40380000 */ +#define TCPWM0_GRP1 ((TCPWM_GRP_Type*) &TCPWM0->GRP[1]) /* 0x40388000 */ #define TCPWM0_GRP0_CNT0 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[0]) /* 0x40380000 */ #define TCPWM0_GRP0_CNT1 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[1]) /* 0x40380080 */ #define TCPWM0_GRP0_CNT2 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[2]) /* 0x40380100 */ @@ -1098,8 +1089,6 @@ typedef enum { #define TCPWM0_GRP1_CNT5 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[5]) /* 0x40388280 */ #define TCPWM0_GRP1_CNT6 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[6]) /* 0x40388300 */ #define TCPWM0_GRP1_CNT7 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[7]) /* 0x40388380 */ -#define TCPWM0_GRP0 ((TCPWM_GRP_Type*) &TCPWM0->GRP[0]) /* 0x40380000 */ -#define TCPWM0_GRP1 ((TCPWM_GRP_Type*) &TCPWM0->GRP[1]) /* 0x40388000 */ /******************************************************************************* * LCD @@ -1134,8 +1123,8 @@ typedef enum { #define CANFD0_BASE 0x40520000UL #define CANFD0 ((CANFD_Type*) CANFD0_BASE) /* 0x40520000 */ -#define CANFD0_CH0_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[0].M_TTCAN) /* 0x40520000 */ #define CANFD0_CH0 ((CANFD_CH_Type*) &CANFD0->CH[0]) /* 0x40520000 */ +#define CANFD0_CH0_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[0].M_TTCAN) /* 0x40520000 */ /******************************************************************************* * SCB @@ -1173,9 +1162,7 @@ typedef enum { *******************************************************************************/ #define SAR0_BASE 0x409B0000UL -#define SAR1_BASE 0x409C0000UL #define SAR0 ((SAR_Type*) SAR0_BASE) /* 0x409B0000 */ -#define SAR1 ((SAR_Type*) SAR1_BASE) /* 0x409C0000 */ /******************************************************************************* * PASS diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6244lqi_s4d82.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6244lqi_s4d82.h index 32643452a2..756238ac72 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6244lqi_s4d82.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6244lqi_s4d82.h @@ -5,7 +5,7 @@ * CY8C6244LQI-S4D82 device header * * \note -* Generator version: 1.6.0.111 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -432,14 +432,14 @@ typedef enum { #define CY_FLASH_SIZE 0x00040000UL #define CY_EM_EEPROM_BASE 0x14000000UL #define CY_EM_EEPROM_SIZE 0x00000000UL -#define CY_XIP_BASE 0x18000000UL -#define CY_XIP_SIZE 0x08000000UL -#define CY_CAN0MRAM_BASE 0x40530000UL -#define CY_CAN0MRAM_SIZE 0x00010000UL #define CY_SFLASH_BASE 0x16000000UL #define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL #define CY_EFUSE_BASE 0x402C0800UL #define CY_EFUSE_SIZE 0x00000200UL +#define CY_CAN0MRAM_BASE 0x40530000UL +#define CY_CAN0MRAM_SIZE 0x00010000UL #include "system_psoc6.h" /*!< PSoC 6 System */ @@ -474,18 +474,6 @@ typedef enum { #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u -//#define CY_IP_MXS40PASS 1u -//#define CY_IP_MXS40PASS_INSTANCES 1u -//#define CY_IP_MXS40PASS_VERSION 2u -//#define CY_IP_MXS40PASS_SAR 1u -//#define CY_IP_MXS40PASS_SAR_INSTANCES 1u -//#define CY_IP_MXS40PASS_SAR_VERSION 2u -//#define CY_IP_MXS40PASS_CTDAC 1u -//#define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u -//#define CY_IP_MXS40PASS_CTDAC_VERSION 2u -//#define CY_IP_MXS40PASS_CTB 1u -//#define CY_IP_MXS40PASS_CTB_INSTANCES 1u -//#define CY_IP_MXS40PASS_CTB_VERSION 2u #define CY_IP_MXPERI 1u #define CY_IP_MXPERI_INSTANCES 1u #define CY_IP_MXPERI_VERSION 2u @@ -507,9 +495,6 @@ typedef enum { #define CY_IP_MXS40SRSS_MCWDT 1u #define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u #define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -//#define CY_IP_MXTCPWM 1u -//#define CY_IP_MXTCPWM_INSTANCES 1u -//#define CY_IP_MXTCPWM_VERSION 2u #define CY_IP_MXUSBFS 1u #define CY_IP_MXUSBFS_INSTANCES 1u #define CY_IP_MXUSBFS_VERSION 1u @@ -555,6 +540,7 @@ typedef enum { #define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ #define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ #define PERI_TR_GR10 ((PERI_TR_GR_Type*) &PERI->TR_GR[10]) /* 0x4000A800 */ +#define PERI_TR_GR11 ((PERI_TR_GR_Type*) &PERI->TR_GR[11]) /* 0x4000AC00 */ #define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ #define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ #define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ @@ -874,6 +860,7 @@ typedef enum { #define PROT_BASE 0x40230000UL #define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ #define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ #define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ #define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ @@ -890,15 +877,6 @@ typedef enum { #define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ #define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ #define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ -#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ -#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ -#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ -#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ -#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ -#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ -#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ -#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ -#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ #define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ #define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ #define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ @@ -915,6 +893,14 @@ typedef enum { #define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ #define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ #define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ /******************************************************************************* * FLASHC @@ -1099,6 +1085,8 @@ typedef enum { #define TCPWM0_BASE 0x40380000UL #define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM0_GRP0 ((TCPWM_GRP_Type*) &TCPWM0->GRP[0]) /* 0x40380000 */ +#define TCPWM0_GRP1 ((TCPWM_GRP_Type*) &TCPWM0->GRP[1]) /* 0x40388000 */ #define TCPWM0_GRP0_CNT0 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[0]) /* 0x40380000 */ #define TCPWM0_GRP0_CNT1 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[1]) /* 0x40380080 */ #define TCPWM0_GRP0_CNT2 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[2]) /* 0x40380100 */ @@ -1111,8 +1099,6 @@ typedef enum { #define TCPWM0_GRP1_CNT5 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[5]) /* 0x40388280 */ #define TCPWM0_GRP1_CNT6 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[6]) /* 0x40388300 */ #define TCPWM0_GRP1_CNT7 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[7]) /* 0x40388380 */ -#define TCPWM0_GRP0 ((TCPWM_GRP_Type*) &TCPWM0->GRP[0]) /* 0x40380000 */ -#define TCPWM0_GRP1 ((TCPWM_GRP_Type*) &TCPWM0->GRP[1]) /* 0x40388000 */ /******************************************************************************* * LCD @@ -1147,8 +1133,8 @@ typedef enum { #define CANFD0_BASE 0x40520000UL #define CANFD0 ((CANFD_Type*) CANFD0_BASE) /* 0x40520000 */ -#define CANFD0_CH0_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[0].M_TTCAN) /* 0x40520000 */ #define CANFD0_CH0 ((CANFD_CH_Type*) &CANFD0->CH[0]) /* 0x40520000 */ +#define CANFD0_CH0_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[0].M_TTCAN) /* 0x40520000 */ /******************************************************************************* * SCB diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6244lqi_s4d92.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6244lqi_s4d92.h index 2205a57464..691a827509 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6244lqi_s4d92.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6244lqi_s4d92.h @@ -5,7 +5,7 @@ * CY8C6244LQI-S4D92 device header * * \note -* Generator version: 1.6.0.111 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -432,14 +432,14 @@ typedef enum { #define CY_FLASH_SIZE 0x00040000UL #define CY_EM_EEPROM_BASE 0x14000000UL #define CY_EM_EEPROM_SIZE 0x00000000UL -#define CY_XIP_BASE 0x18000000UL -#define CY_XIP_SIZE 0x08000000UL -#define CY_CAN0MRAM_BASE 0x40530000UL -#define CY_CAN0MRAM_SIZE 0x00010000UL #define CY_SFLASH_BASE 0x16000000UL #define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL #define CY_EFUSE_BASE 0x402C0800UL #define CY_EFUSE_SIZE 0x00000200UL +#define CY_CAN0MRAM_BASE 0x40530000UL +#define CY_CAN0MRAM_SIZE 0x00010000UL #include "system_psoc6.h" /*!< PSoC 6 System */ @@ -474,18 +474,6 @@ typedef enum { #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u -//#define CY_IP_MXS40PASS 1u -//#define CY_IP_MXS40PASS_INSTANCES 1u -//#define CY_IP_MXS40PASS_VERSION 2u -//#define CY_IP_MXS40PASS_SAR 1u -//#define CY_IP_MXS40PASS_SAR_INSTANCES 1u -//#define CY_IP_MXS40PASS_SAR_VERSION 2u -//#define CY_IP_MXS40PASS_CTDAC 1u -//#define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u -//#define CY_IP_MXS40PASS_CTDAC_VERSION 2u -//#define CY_IP_MXS40PASS_CTB 1u -//#define CY_IP_MXS40PASS_CTB_INSTANCES 1u -//#define CY_IP_MXS40PASS_CTB_VERSION 2u #define CY_IP_MXPERI 1u #define CY_IP_MXPERI_INSTANCES 1u #define CY_IP_MXPERI_VERSION 2u @@ -507,9 +495,6 @@ typedef enum { #define CY_IP_MXS40SRSS_MCWDT 1u #define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u #define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -//#define CY_IP_MXTCPWM 1u -//#define CY_IP_MXTCPWM_INSTANCES 1u -//#define CY_IP_MXTCPWM_VERSION 2u #define CY_IP_MXUSBFS 1u #define CY_IP_MXUSBFS_INSTANCES 1u #define CY_IP_MXUSBFS_VERSION 1u @@ -555,6 +540,7 @@ typedef enum { #define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ #define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ #define PERI_TR_GR10 ((PERI_TR_GR_Type*) &PERI->TR_GR[10]) /* 0x4000A800 */ +#define PERI_TR_GR11 ((PERI_TR_GR_Type*) &PERI->TR_GR[11]) /* 0x4000AC00 */ #define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ #define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ #define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ @@ -874,6 +860,7 @@ typedef enum { #define PROT_BASE 0x40230000UL #define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ #define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ #define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ #define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ @@ -890,15 +877,6 @@ typedef enum { #define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ #define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ #define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ -#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ -#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ -#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ -#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ -#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ -#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ -#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ -#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ -#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ #define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ #define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ #define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ @@ -915,6 +893,14 @@ typedef enum { #define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ #define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ #define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ /******************************************************************************* * FLASHC @@ -1099,6 +1085,8 @@ typedef enum { #define TCPWM0_BASE 0x40380000UL #define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM0_GRP0 ((TCPWM_GRP_Type*) &TCPWM0->GRP[0]) /* 0x40380000 */ +#define TCPWM0_GRP1 ((TCPWM_GRP_Type*) &TCPWM0->GRP[1]) /* 0x40388000 */ #define TCPWM0_GRP0_CNT0 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[0]) /* 0x40380000 */ #define TCPWM0_GRP0_CNT1 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[1]) /* 0x40380080 */ #define TCPWM0_GRP0_CNT2 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[2]) /* 0x40380100 */ @@ -1111,8 +1099,6 @@ typedef enum { #define TCPWM0_GRP1_CNT5 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[5]) /* 0x40388280 */ #define TCPWM0_GRP1_CNT6 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[6]) /* 0x40388300 */ #define TCPWM0_GRP1_CNT7 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[7]) /* 0x40388380 */ -#define TCPWM0_GRP0 ((TCPWM_GRP_Type*) &TCPWM0->GRP[0]) /* 0x40380000 */ -#define TCPWM0_GRP1 ((TCPWM_GRP_Type*) &TCPWM0->GRP[1]) /* 0x40388000 */ /******************************************************************************* * LCD @@ -1147,8 +1133,8 @@ typedef enum { #define CANFD0_BASE 0x40520000UL #define CANFD0 ((CANFD_Type*) CANFD0_BASE) /* 0x40520000 */ -#define CANFD0_CH0_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[0].M_TTCAN) /* 0x40520000 */ #define CANFD0_CH0 ((CANFD_CH_Type*) &CANFD0->CH[0]) /* 0x40520000 */ +#define CANFD0_CH0_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[0].M_TTCAN) /* 0x40520000 */ /******************************************************************************* * SCB diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245azi_s3d02.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245azi_s3d02.h index 78ba7ff284..4c6d484df2 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245azi_s3d02.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245azi_s3d02.h @@ -5,11 +5,11 @@ * CY8C6245AZI-S3D02 device header * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -426,45 +426,21 @@ typedef enum { #define CY_FLASH_SIZE 0x00080000UL #define CY_EM_EEPROM_BASE 0x14000000UL #define CY_EM_EEPROM_SIZE 0x00008000UL -#define CY_XIP_BASE 0x18000000UL -#define CY_XIP_SIZE 0x08000000UL -#define CY_CAN0MRAM_BASE 0x40530000UL -#define CY_CAN0MRAM_SIZE 0x00010000UL #define CY_SFLASH_BASE 0x16000000UL #define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL #define CY_EFUSE_BASE 0x402C0800UL #define CY_EFUSE_SIZE 0x00000200UL +#define CY_CAN0MRAM_BASE 0x40530000UL +#define CY_CAN0MRAM_SIZE 0x00010000UL #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 2u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 7u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 2u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXTTCANFD 1u +#define CY_IP_MXTTCANFD_INSTANCES 1u +#define CY_IP_MXTTCANFD_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 2u @@ -474,33 +450,57 @@ typedef enum { #define CY_IP_M4CPUSS_DMA 1u #define CY_IP_M4CPUSS_DMA_INSTANCES 2u #define CY_IP_M4CPUSS_DMA_VERSION 2u -#define CY_IP_MXSDHC 1u -#define CY_IP_MXSDHC_INSTANCES 1u -#define CY_IP_MXSDHC_VERSION 1u -#define CY_IP_MXTTCANFD 1u -#define CY_IP_MXTTCANFD_INSTANCES 1u -#define CY_IP_MXTTCANFD_VERSION 1u -#define CY_IP_MXLPCOMP 1u -#define CY_IP_MXLPCOMP_INSTANCES 1u -#define CY_IP_MXLPCOMP_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u #define CY_IP_MXS40IOSS 1u #define CY_IP_MXS40IOSS_INSTANCES 1u #define CY_IP_MXS40IOSS_VERSION 2u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 2u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u #define CY_IP_MXS40PASS 1u #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u #define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 7u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 1u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_03_config.h" #include "gpio_psoc6_03_100_tqfp.h" @@ -848,6 +848,7 @@ typedef enum { #define PROT_BASE 0x40230000UL #define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ #define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ #define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ #define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ @@ -864,23 +865,6 @@ typedef enum { #define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ #define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ #define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ -#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ -#define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ -#define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ -#define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ -#define PROT_MPU5_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[3]) /* 0x40235660 */ -#define PROT_MPU5_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[4]) /* 0x40235680 */ -#define PROT_MPU5_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[5]) /* 0x402356A0 */ -#define PROT_MPU5_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[6]) /* 0x402356C0 */ -#define PROT_MPU5_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[7]) /* 0x402356E0 */ -#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ -#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ -#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ -#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ -#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ -#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ -#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ -#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ #define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ #define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ #define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ @@ -897,6 +881,22 @@ typedef enum { #define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ #define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ #define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ +#define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ +#define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ +#define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ +#define PROT_MPU5_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[3]) /* 0x40235660 */ +#define PROT_MPU5_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[4]) /* 0x40235680 */ +#define PROT_MPU5_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[5]) /* 0x402356A0 */ +#define PROT_MPU5_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[6]) /* 0x402356C0 */ +#define PROT_MPU5_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[7]) /* 0x402356E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ /******************************************************************************* * FLASHC @@ -1138,8 +1138,8 @@ typedef enum { #define CANFD0_BASE 0x40520000UL #define CANFD0 ((CANFD_Type*) CANFD0_BASE) /* 0x40520000 */ -#define CANFD0_CH0_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[0].M_TTCAN) /* 0x40520000 */ #define CANFD0_CH0 ((CANFD_CH_Type*) &CANFD0->CH[0]) /* 0x40520000 */ +#define CANFD0_CH0_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[0].M_TTCAN) /* 0x40520000 */ /******************************************************************************* * SCB diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245azi_s3d12.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245azi_s3d12.h index f7f24414cf..0efc17db40 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245azi_s3d12.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245azi_s3d12.h @@ -5,11 +5,11 @@ * CY8C6245AZI-S3D12 device header * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -426,45 +426,21 @@ typedef enum { #define CY_FLASH_SIZE 0x00080000UL #define CY_EM_EEPROM_BASE 0x14000000UL #define CY_EM_EEPROM_SIZE 0x00008000UL -#define CY_XIP_BASE 0x18000000UL -#define CY_XIP_SIZE 0x08000000UL -#define CY_CAN0MRAM_BASE 0x40530000UL -#define CY_CAN0MRAM_SIZE 0x00010000UL #define CY_SFLASH_BASE 0x16000000UL #define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL #define CY_EFUSE_BASE 0x402C0800UL #define CY_EFUSE_SIZE 0x00000200UL +#define CY_CAN0MRAM_BASE 0x40530000UL +#define CY_CAN0MRAM_SIZE 0x00010000UL #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 2u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 7u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 2u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXTTCANFD 1u +#define CY_IP_MXTTCANFD_INSTANCES 1u +#define CY_IP_MXTTCANFD_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 2u @@ -474,33 +450,57 @@ typedef enum { #define CY_IP_M4CPUSS_DMA 1u #define CY_IP_M4CPUSS_DMA_INSTANCES 2u #define CY_IP_M4CPUSS_DMA_VERSION 2u -#define CY_IP_MXSDHC 1u -#define CY_IP_MXSDHC_INSTANCES 1u -#define CY_IP_MXSDHC_VERSION 1u -#define CY_IP_MXTTCANFD 1u -#define CY_IP_MXTTCANFD_INSTANCES 1u -#define CY_IP_MXTTCANFD_VERSION 1u -#define CY_IP_MXLPCOMP 1u -#define CY_IP_MXLPCOMP_INSTANCES 1u -#define CY_IP_MXLPCOMP_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u #define CY_IP_MXS40IOSS 1u #define CY_IP_MXS40IOSS_INSTANCES 1u #define CY_IP_MXS40IOSS_VERSION 2u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 2u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u #define CY_IP_MXS40PASS 1u #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u #define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 7u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 1u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_03_config.h" #include "gpio_psoc6_03_100_tqfp.h" @@ -848,6 +848,7 @@ typedef enum { #define PROT_BASE 0x40230000UL #define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ #define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ #define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ #define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ @@ -864,23 +865,6 @@ typedef enum { #define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ #define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ #define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ -#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ -#define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ -#define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ -#define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ -#define PROT_MPU5_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[3]) /* 0x40235660 */ -#define PROT_MPU5_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[4]) /* 0x40235680 */ -#define PROT_MPU5_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[5]) /* 0x402356A0 */ -#define PROT_MPU5_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[6]) /* 0x402356C0 */ -#define PROT_MPU5_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[7]) /* 0x402356E0 */ -#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ -#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ -#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ -#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ -#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ -#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ -#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ -#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ #define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ #define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ #define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ @@ -897,6 +881,22 @@ typedef enum { #define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ #define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ #define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ +#define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ +#define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ +#define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ +#define PROT_MPU5_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[3]) /* 0x40235660 */ +#define PROT_MPU5_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[4]) /* 0x40235680 */ +#define PROT_MPU5_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[5]) /* 0x402356A0 */ +#define PROT_MPU5_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[6]) /* 0x402356C0 */ +#define PROT_MPU5_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[7]) /* 0x402356E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ /******************************************************************************* * FLASHC @@ -1138,8 +1138,8 @@ typedef enum { #define CANFD0_BASE 0x40520000UL #define CANFD0 ((CANFD_Type*) CANFD0_BASE) /* 0x40520000 */ -#define CANFD0_CH0_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[0].M_TTCAN) /* 0x40520000 */ #define CANFD0_CH0 ((CANFD_CH_Type*) &CANFD0->CH[0]) /* 0x40520000 */ +#define CANFD0_CH0_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[0].M_TTCAN) /* 0x40520000 */ /******************************************************************************* * SCB diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245azi_s3d42.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245azi_s3d42.h index 6a6cdb3986..a884107ab7 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245azi_s3d42.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245azi_s3d42.h @@ -5,11 +5,11 @@ * CY8C6245AZI-S3D42 device header * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -426,45 +426,21 @@ typedef enum { #define CY_FLASH_SIZE 0x00080000UL #define CY_EM_EEPROM_BASE 0x14000000UL #define CY_EM_EEPROM_SIZE 0x00008000UL -#define CY_XIP_BASE 0x18000000UL -#define CY_XIP_SIZE 0x08000000UL -#define CY_CAN0MRAM_BASE 0x40530000UL -#define CY_CAN0MRAM_SIZE 0x00010000UL #define CY_SFLASH_BASE 0x16000000UL #define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL #define CY_EFUSE_BASE 0x402C0800UL #define CY_EFUSE_SIZE 0x00000200UL +#define CY_CAN0MRAM_BASE 0x40530000UL +#define CY_CAN0MRAM_SIZE 0x00010000UL #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 2u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 7u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 2u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXTTCANFD 1u +#define CY_IP_MXTTCANFD_INSTANCES 1u +#define CY_IP_MXTTCANFD_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 2u @@ -477,33 +453,57 @@ typedef enum { #define CY_IP_MXCRYPTO 1u #define CY_IP_MXCRYPTO_INSTANCES 1u #define CY_IP_MXCRYPTO_VERSION 2u -#define CY_IP_MXSDHC 1u -#define CY_IP_MXSDHC_INSTANCES 1u -#define CY_IP_MXSDHC_VERSION 1u -#define CY_IP_MXTTCANFD 1u -#define CY_IP_MXTTCANFD_INSTANCES 1u -#define CY_IP_MXTTCANFD_VERSION 1u -#define CY_IP_MXLPCOMP 1u -#define CY_IP_MXLPCOMP_INSTANCES 1u -#define CY_IP_MXLPCOMP_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u #define CY_IP_MXS40IOSS 1u #define CY_IP_MXS40IOSS_INSTANCES 1u #define CY_IP_MXS40IOSS_VERSION 2u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 2u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u #define CY_IP_MXS40PASS 1u #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u #define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 7u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 1u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_03_config.h" #include "gpio_psoc6_03_100_tqfp.h" @@ -858,6 +858,7 @@ typedef enum { #define PROT_BASE 0x40230000UL #define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ #define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ #define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ #define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ @@ -874,23 +875,6 @@ typedef enum { #define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ #define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ #define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ -#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ -#define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ -#define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ -#define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ -#define PROT_MPU5_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[3]) /* 0x40235660 */ -#define PROT_MPU5_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[4]) /* 0x40235680 */ -#define PROT_MPU5_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[5]) /* 0x402356A0 */ -#define PROT_MPU5_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[6]) /* 0x402356C0 */ -#define PROT_MPU5_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[7]) /* 0x402356E0 */ -#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ -#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ -#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ -#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ -#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ -#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ -#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ -#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ #define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ #define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ #define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ @@ -907,6 +891,22 @@ typedef enum { #define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ #define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ #define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ +#define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ +#define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ +#define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ +#define PROT_MPU5_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[3]) /* 0x40235660 */ +#define PROT_MPU5_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[4]) /* 0x40235680 */ +#define PROT_MPU5_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[5]) /* 0x402356A0 */ +#define PROT_MPU5_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[6]) /* 0x402356C0 */ +#define PROT_MPU5_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[7]) /* 0x402356E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ /******************************************************************************* * FLASHC @@ -1148,8 +1148,8 @@ typedef enum { #define CANFD0_BASE 0x40520000UL #define CANFD0 ((CANFD_Type*) CANFD0_BASE) /* 0x40520000 */ -#define CANFD0_CH0_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[0].M_TTCAN) /* 0x40520000 */ #define CANFD0_CH0 ((CANFD_CH_Type*) &CANFD0->CH[0]) /* 0x40520000 */ +#define CANFD0_CH0_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[0].M_TTCAN) /* 0x40520000 */ /******************************************************************************* * SCB diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245azi_s3d62.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245azi_s3d62.h index 1221cb5d63..6888385c89 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245azi_s3d62.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245azi_s3d62.h @@ -5,11 +5,11 @@ * CY8C6245AZI-S3D62 device header * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -426,45 +426,21 @@ typedef enum { #define CY_FLASH_SIZE 0x00080000UL #define CY_EM_EEPROM_BASE 0x14000000UL #define CY_EM_EEPROM_SIZE 0x00008000UL -#define CY_XIP_BASE 0x18000000UL -#define CY_XIP_SIZE 0x08000000UL -#define CY_CAN0MRAM_BASE 0x40530000UL -#define CY_CAN0MRAM_SIZE 0x00010000UL #define CY_SFLASH_BASE 0x16000000UL #define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL #define CY_EFUSE_BASE 0x402C0800UL #define CY_EFUSE_SIZE 0x00000200UL +#define CY_CAN0MRAM_BASE 0x40530000UL +#define CY_CAN0MRAM_SIZE 0x00010000UL #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 2u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 7u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 2u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXTTCANFD 1u +#define CY_IP_MXTTCANFD_INSTANCES 1u +#define CY_IP_MXTTCANFD_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 2u @@ -474,33 +450,57 @@ typedef enum { #define CY_IP_M4CPUSS_DMA 1u #define CY_IP_M4CPUSS_DMA_INSTANCES 2u #define CY_IP_M4CPUSS_DMA_VERSION 2u -#define CY_IP_MXSDHC 1u -#define CY_IP_MXSDHC_INSTANCES 1u -#define CY_IP_MXSDHC_VERSION 1u -#define CY_IP_MXTTCANFD 1u -#define CY_IP_MXTTCANFD_INSTANCES 1u -#define CY_IP_MXTTCANFD_VERSION 1u -#define CY_IP_MXLPCOMP 1u -#define CY_IP_MXLPCOMP_INSTANCES 1u -#define CY_IP_MXLPCOMP_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u #define CY_IP_MXS40IOSS 1u #define CY_IP_MXS40IOSS_INSTANCES 1u #define CY_IP_MXS40IOSS_VERSION 2u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 2u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u #define CY_IP_MXS40PASS 1u #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u #define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 7u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 1u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_03_config.h" #include "gpio_psoc6_03_100_tqfp.h" @@ -848,6 +848,7 @@ typedef enum { #define PROT_BASE 0x40230000UL #define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ #define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ #define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ #define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ @@ -864,23 +865,6 @@ typedef enum { #define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ #define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ #define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ -#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ -#define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ -#define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ -#define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ -#define PROT_MPU5_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[3]) /* 0x40235660 */ -#define PROT_MPU5_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[4]) /* 0x40235680 */ -#define PROT_MPU5_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[5]) /* 0x402356A0 */ -#define PROT_MPU5_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[6]) /* 0x402356C0 */ -#define PROT_MPU5_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[7]) /* 0x402356E0 */ -#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ -#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ -#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ -#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ -#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ -#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ -#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ -#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ #define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ #define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ #define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ @@ -897,6 +881,22 @@ typedef enum { #define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ #define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ #define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ +#define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ +#define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ +#define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ +#define PROT_MPU5_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[3]) /* 0x40235660 */ +#define PROT_MPU5_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[4]) /* 0x40235680 */ +#define PROT_MPU5_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[5]) /* 0x402356A0 */ +#define PROT_MPU5_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[6]) /* 0x402356C0 */ +#define PROT_MPU5_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[7]) /* 0x402356E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ /******************************************************************************* * FLASHC @@ -1138,8 +1138,8 @@ typedef enum { #define CANFD0_BASE 0x40520000UL #define CANFD0 ((CANFD_Type*) CANFD0_BASE) /* 0x40520000 */ -#define CANFD0_CH0_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[0].M_TTCAN) /* 0x40520000 */ #define CANFD0_CH0 ((CANFD_CH_Type*) &CANFD0->CH[0]) /* 0x40520000 */ +#define CANFD0_CH0_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[0].M_TTCAN) /* 0x40520000 */ /******************************************************************************* * SCB diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245azi_s3d72.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245azi_s3d72.h index dac4a79e20..4ec19d2952 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245azi_s3d72.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245azi_s3d72.h @@ -5,11 +5,11 @@ * CY8C6245AZI-S3D72 device header * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -426,45 +426,21 @@ typedef enum { #define CY_FLASH_SIZE 0x00080000UL #define CY_EM_EEPROM_BASE 0x14000000UL #define CY_EM_EEPROM_SIZE 0x00008000UL -#define CY_XIP_BASE 0x18000000UL -#define CY_XIP_SIZE 0x08000000UL -#define CY_CAN0MRAM_BASE 0x40530000UL -#define CY_CAN0MRAM_SIZE 0x00010000UL #define CY_SFLASH_BASE 0x16000000UL #define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL #define CY_EFUSE_BASE 0x402C0800UL #define CY_EFUSE_SIZE 0x00000200UL +#define CY_CAN0MRAM_BASE 0x40530000UL +#define CY_CAN0MRAM_SIZE 0x00010000UL #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 2u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 7u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 2u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXTTCANFD 1u +#define CY_IP_MXTTCANFD_INSTANCES 1u +#define CY_IP_MXTTCANFD_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 2u @@ -477,33 +453,57 @@ typedef enum { #define CY_IP_MXCRYPTO 1u #define CY_IP_MXCRYPTO_INSTANCES 1u #define CY_IP_MXCRYPTO_VERSION 2u -#define CY_IP_MXSDHC 1u -#define CY_IP_MXSDHC_INSTANCES 1u -#define CY_IP_MXSDHC_VERSION 1u -#define CY_IP_MXTTCANFD 1u -#define CY_IP_MXTTCANFD_INSTANCES 1u -#define CY_IP_MXTTCANFD_VERSION 1u -#define CY_IP_MXLPCOMP 1u -#define CY_IP_MXLPCOMP_INSTANCES 1u -#define CY_IP_MXLPCOMP_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u #define CY_IP_MXS40IOSS 1u #define CY_IP_MXS40IOSS_INSTANCES 1u #define CY_IP_MXS40IOSS_VERSION 2u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 2u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u #define CY_IP_MXS40PASS 1u #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u #define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 7u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 1u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_03_config.h" #include "gpio_psoc6_03_100_tqfp.h" @@ -858,6 +858,7 @@ typedef enum { #define PROT_BASE 0x40230000UL #define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ #define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ #define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ #define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ @@ -874,23 +875,6 @@ typedef enum { #define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ #define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ #define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ -#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ -#define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ -#define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ -#define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ -#define PROT_MPU5_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[3]) /* 0x40235660 */ -#define PROT_MPU5_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[4]) /* 0x40235680 */ -#define PROT_MPU5_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[5]) /* 0x402356A0 */ -#define PROT_MPU5_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[6]) /* 0x402356C0 */ -#define PROT_MPU5_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[7]) /* 0x402356E0 */ -#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ -#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ -#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ -#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ -#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ -#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ -#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ -#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ #define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ #define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ #define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ @@ -907,6 +891,22 @@ typedef enum { #define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ #define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ #define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ +#define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ +#define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ +#define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ +#define PROT_MPU5_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[3]) /* 0x40235660 */ +#define PROT_MPU5_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[4]) /* 0x40235680 */ +#define PROT_MPU5_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[5]) /* 0x402356A0 */ +#define PROT_MPU5_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[6]) /* 0x402356C0 */ +#define PROT_MPU5_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[7]) /* 0x402356E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ /******************************************************************************* * FLASHC @@ -1148,8 +1148,8 @@ typedef enum { #define CANFD0_BASE 0x40520000UL #define CANFD0 ((CANFD_Type*) CANFD0_BASE) /* 0x40520000 */ -#define CANFD0_CH0_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[0].M_TTCAN) /* 0x40520000 */ #define CANFD0_CH0 ((CANFD_CH_Type*) &CANFD0->CH[0]) /* 0x40520000 */ +#define CANFD0_CH0_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[0].M_TTCAN) /* 0x40520000 */ /******************************************************************************* * SCB diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245fni_s3d11.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245fni_s3d11.h index e9ec4b4b80..987412a9d2 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245fni_s3d11.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245fni_s3d11.h @@ -5,11 +5,11 @@ * CY8C6245FNI-S3D11 device header * * \note -* Generator version: 1.5.1.36 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -426,45 +426,21 @@ typedef enum { #define CY_FLASH_SIZE 0x00080000UL #define CY_EM_EEPROM_BASE 0x14000000UL #define CY_EM_EEPROM_SIZE 0x00008000UL -#define CY_XIP_BASE 0x18000000UL -#define CY_XIP_SIZE 0x08000000UL -#define CY_CAN0MRAM_BASE 0x40530000UL -#define CY_CAN0MRAM_SIZE 0x00010000UL #define CY_SFLASH_BASE 0x16000000UL #define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL #define CY_EFUSE_BASE 0x402C0800UL #define CY_EFUSE_SIZE 0x00000200UL +#define CY_CAN0MRAM_BASE 0x40530000UL +#define CY_CAN0MRAM_SIZE 0x00010000UL #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 2u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 7u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 2u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXTTCANFD 1u +#define CY_IP_MXTTCANFD_INSTANCES 1u +#define CY_IP_MXTTCANFD_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 2u @@ -474,30 +450,54 @@ typedef enum { #define CY_IP_M4CPUSS_DMA 1u #define CY_IP_M4CPUSS_DMA_INSTANCES 2u #define CY_IP_M4CPUSS_DMA_VERSION 2u -#define CY_IP_MXSDHC 1u -#define CY_IP_MXSDHC_INSTANCES 1u -#define CY_IP_MXSDHC_VERSION 1u -#define CY_IP_MXTTCANFD 1u -#define CY_IP_MXTTCANFD_INSTANCES 1u -#define CY_IP_MXTTCANFD_VERSION 1u -#define CY_IP_MXLPCOMP 1u -#define CY_IP_MXLPCOMP_INSTANCES 1u -#define CY_IP_MXLPCOMP_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u #define CY_IP_MXS40IOSS 1u #define CY_IP_MXS40IOSS_INSTANCES 1u #define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 2u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u #define CY_IP_MXS40PASS 1u #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u #define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 7u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 1u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u #include "psoc6_03_config.h" #include "gpio_psoc6_03_49_wlcsp.h" @@ -845,6 +845,7 @@ typedef enum { #define PROT_BASE 0x40230000UL #define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ #define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ #define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ #define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ @@ -861,23 +862,6 @@ typedef enum { #define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ #define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ #define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ -#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ -#define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ -#define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ -#define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ -#define PROT_MPU5_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[3]) /* 0x40235660 */ -#define PROT_MPU5_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[4]) /* 0x40235680 */ -#define PROT_MPU5_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[5]) /* 0x402356A0 */ -#define PROT_MPU5_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[6]) /* 0x402356C0 */ -#define PROT_MPU5_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[7]) /* 0x402356E0 */ -#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ -#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ -#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ -#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ -#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ -#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ -#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ -#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ #define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ #define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ #define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ @@ -894,6 +878,22 @@ typedef enum { #define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ #define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ #define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ +#define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ +#define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ +#define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ +#define PROT_MPU5_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[3]) /* 0x40235660 */ +#define PROT_MPU5_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[4]) /* 0x40235680 */ +#define PROT_MPU5_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[5]) /* 0x402356A0 */ +#define PROT_MPU5_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[6]) /* 0x402356C0 */ +#define PROT_MPU5_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[7]) /* 0x402356E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ /******************************************************************************* * FLASHC @@ -1125,8 +1125,8 @@ typedef enum { #define CANFD0_BASE 0x40520000UL #define CANFD0 ((CANFD_Type*) CANFD0_BASE) /* 0x40520000 */ -#define CANFD0_CH0_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[0].M_TTCAN) /* 0x40520000 */ #define CANFD0_CH0 ((CANFD_CH_Type*) &CANFD0->CH[0]) /* 0x40520000 */ +#define CANFD0_CH0_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[0].M_TTCAN) /* 0x40520000 */ /******************************************************************************* * SCB diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245fni_s3d41.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245fni_s3d41.h index 5b1fe6c31d..59a912d061 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245fni_s3d41.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245fni_s3d41.h @@ -5,11 +5,11 @@ * CY8C6245FNI-S3D41 device header * * \note -* Generator version: 1.5.1.36 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -426,45 +426,21 @@ typedef enum { #define CY_FLASH_SIZE 0x00080000UL #define CY_EM_EEPROM_BASE 0x14000000UL #define CY_EM_EEPROM_SIZE 0x00008000UL -#define CY_XIP_BASE 0x18000000UL -#define CY_XIP_SIZE 0x08000000UL -#define CY_CAN0MRAM_BASE 0x40530000UL -#define CY_CAN0MRAM_SIZE 0x00010000UL #define CY_SFLASH_BASE 0x16000000UL #define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL #define CY_EFUSE_BASE 0x402C0800UL #define CY_EFUSE_SIZE 0x00000200UL +#define CY_CAN0MRAM_BASE 0x40530000UL +#define CY_CAN0MRAM_SIZE 0x00010000UL #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 2u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 7u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 2u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXTTCANFD 1u +#define CY_IP_MXTTCANFD_INSTANCES 1u +#define CY_IP_MXTTCANFD_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 2u @@ -477,30 +453,54 @@ typedef enum { #define CY_IP_MXCRYPTO 1u #define CY_IP_MXCRYPTO_INSTANCES 1u #define CY_IP_MXCRYPTO_VERSION 2u -#define CY_IP_MXSDHC 1u -#define CY_IP_MXSDHC_INSTANCES 1u -#define CY_IP_MXSDHC_VERSION 1u -#define CY_IP_MXTTCANFD 1u -#define CY_IP_MXTTCANFD_INSTANCES 1u -#define CY_IP_MXTTCANFD_VERSION 1u -#define CY_IP_MXLPCOMP 1u -#define CY_IP_MXLPCOMP_INSTANCES 1u -#define CY_IP_MXLPCOMP_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u #define CY_IP_MXS40IOSS 1u #define CY_IP_MXS40IOSS_INSTANCES 1u #define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 2u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u #define CY_IP_MXS40PASS 1u #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u #define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 7u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 1u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u #include "psoc6_03_config.h" #include "gpio_psoc6_03_49_wlcsp.h" @@ -855,6 +855,7 @@ typedef enum { #define PROT_BASE 0x40230000UL #define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ #define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ #define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ #define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ @@ -871,23 +872,6 @@ typedef enum { #define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ #define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ #define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ -#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ -#define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ -#define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ -#define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ -#define PROT_MPU5_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[3]) /* 0x40235660 */ -#define PROT_MPU5_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[4]) /* 0x40235680 */ -#define PROT_MPU5_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[5]) /* 0x402356A0 */ -#define PROT_MPU5_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[6]) /* 0x402356C0 */ -#define PROT_MPU5_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[7]) /* 0x402356E0 */ -#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ -#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ -#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ -#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ -#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ -#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ -#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ -#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ #define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ #define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ #define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ @@ -904,6 +888,22 @@ typedef enum { #define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ #define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ #define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ +#define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ +#define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ +#define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ +#define PROT_MPU5_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[3]) /* 0x40235660 */ +#define PROT_MPU5_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[4]) /* 0x40235680 */ +#define PROT_MPU5_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[5]) /* 0x402356A0 */ +#define PROT_MPU5_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[6]) /* 0x402356C0 */ +#define PROT_MPU5_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[7]) /* 0x402356E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ /******************************************************************************* * FLASHC @@ -1135,8 +1135,8 @@ typedef enum { #define CANFD0_BASE 0x40520000UL #define CANFD0 ((CANFD_Type*) CANFD0_BASE) /* 0x40520000 */ -#define CANFD0_CH0_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[0].M_TTCAN) /* 0x40520000 */ #define CANFD0_CH0 ((CANFD_CH_Type*) &CANFD0->CH[0]) /* 0x40520000 */ +#define CANFD0_CH0_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[0].M_TTCAN) /* 0x40520000 */ /******************************************************************************* * SCB diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245fni_s3d71.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245fni_s3d71.h index 0c7af9deef..eaab1acdbe 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245fni_s3d71.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245fni_s3d71.h @@ -5,11 +5,11 @@ * CY8C6245FNI-S3D71 device header * * \note -* Generator version: 1.5.1.36 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -426,45 +426,21 @@ typedef enum { #define CY_FLASH_SIZE 0x00080000UL #define CY_EM_EEPROM_BASE 0x14000000UL #define CY_EM_EEPROM_SIZE 0x00008000UL -#define CY_XIP_BASE 0x18000000UL -#define CY_XIP_SIZE 0x08000000UL -#define CY_CAN0MRAM_BASE 0x40530000UL -#define CY_CAN0MRAM_SIZE 0x00010000UL #define CY_SFLASH_BASE 0x16000000UL #define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL #define CY_EFUSE_BASE 0x402C0800UL #define CY_EFUSE_SIZE 0x00000200UL +#define CY_CAN0MRAM_BASE 0x40530000UL +#define CY_CAN0MRAM_SIZE 0x00010000UL #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 2u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 7u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 2u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXTTCANFD 1u +#define CY_IP_MXTTCANFD_INSTANCES 1u +#define CY_IP_MXTTCANFD_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 2u @@ -477,30 +453,54 @@ typedef enum { #define CY_IP_MXCRYPTO 1u #define CY_IP_MXCRYPTO_INSTANCES 1u #define CY_IP_MXCRYPTO_VERSION 2u -#define CY_IP_MXSDHC 1u -#define CY_IP_MXSDHC_INSTANCES 1u -#define CY_IP_MXSDHC_VERSION 1u -#define CY_IP_MXTTCANFD 1u -#define CY_IP_MXTTCANFD_INSTANCES 1u -#define CY_IP_MXTTCANFD_VERSION 1u -#define CY_IP_MXLPCOMP 1u -#define CY_IP_MXLPCOMP_INSTANCES 1u -#define CY_IP_MXLPCOMP_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u #define CY_IP_MXS40IOSS 1u #define CY_IP_MXS40IOSS_INSTANCES 1u #define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 2u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u #define CY_IP_MXS40PASS 1u #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u #define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 7u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 1u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u #include "psoc6_03_config.h" #include "gpio_psoc6_03_49_wlcsp.h" @@ -855,6 +855,7 @@ typedef enum { #define PROT_BASE 0x40230000UL #define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ #define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ #define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ #define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ @@ -871,23 +872,6 @@ typedef enum { #define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ #define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ #define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ -#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ -#define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ -#define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ -#define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ -#define PROT_MPU5_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[3]) /* 0x40235660 */ -#define PROT_MPU5_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[4]) /* 0x40235680 */ -#define PROT_MPU5_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[5]) /* 0x402356A0 */ -#define PROT_MPU5_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[6]) /* 0x402356C0 */ -#define PROT_MPU5_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[7]) /* 0x402356E0 */ -#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ -#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ -#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ -#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ -#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ -#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ -#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ -#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ #define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ #define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ #define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ @@ -904,6 +888,22 @@ typedef enum { #define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ #define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ #define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ +#define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ +#define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ +#define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ +#define PROT_MPU5_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[3]) /* 0x40235660 */ +#define PROT_MPU5_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[4]) /* 0x40235680 */ +#define PROT_MPU5_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[5]) /* 0x402356A0 */ +#define PROT_MPU5_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[6]) /* 0x402356C0 */ +#define PROT_MPU5_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[7]) /* 0x402356E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ /******************************************************************************* * FLASHC @@ -1135,8 +1135,8 @@ typedef enum { #define CANFD0_BASE 0x40520000UL #define CANFD0 ((CANFD_Type*) CANFD0_BASE) /* 0x40520000 */ -#define CANFD0_CH0_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[0].M_TTCAN) /* 0x40520000 */ #define CANFD0_CH0 ((CANFD_CH_Type*) &CANFD0->CH[0]) /* 0x40520000 */ +#define CANFD0_CH0_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[0].M_TTCAN) /* 0x40520000 */ /******************************************************************************* * SCB diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245lqi_s3d02.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245lqi_s3d02.h index c86a8d44d4..8089032e98 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245lqi_s3d02.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245lqi_s3d02.h @@ -5,11 +5,11 @@ * CY8C6245LQI-S3D02 device header * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -426,45 +426,21 @@ typedef enum { #define CY_FLASH_SIZE 0x00080000UL #define CY_EM_EEPROM_BASE 0x14000000UL #define CY_EM_EEPROM_SIZE 0x00008000UL -#define CY_XIP_BASE 0x18000000UL -#define CY_XIP_SIZE 0x08000000UL -#define CY_CAN0MRAM_BASE 0x40530000UL -#define CY_CAN0MRAM_SIZE 0x00010000UL #define CY_SFLASH_BASE 0x16000000UL #define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL #define CY_EFUSE_BASE 0x402C0800UL #define CY_EFUSE_SIZE 0x00000200UL +#define CY_CAN0MRAM_BASE 0x40530000UL +#define CY_CAN0MRAM_SIZE 0x00010000UL #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 2u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 7u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 2u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXTTCANFD 1u +#define CY_IP_MXTTCANFD_INSTANCES 1u +#define CY_IP_MXTTCANFD_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 2u @@ -474,33 +450,57 @@ typedef enum { #define CY_IP_M4CPUSS_DMA 1u #define CY_IP_M4CPUSS_DMA_INSTANCES 2u #define CY_IP_M4CPUSS_DMA_VERSION 2u -#define CY_IP_MXSDHC 1u -#define CY_IP_MXSDHC_INSTANCES 1u -#define CY_IP_MXSDHC_VERSION 1u -#define CY_IP_MXTTCANFD 1u -#define CY_IP_MXTTCANFD_INSTANCES 1u -#define CY_IP_MXTTCANFD_VERSION 1u -#define CY_IP_MXLPCOMP 1u -#define CY_IP_MXLPCOMP_INSTANCES 1u -#define CY_IP_MXLPCOMP_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u #define CY_IP_MXS40IOSS 1u #define CY_IP_MXS40IOSS_INSTANCES 1u #define CY_IP_MXS40IOSS_VERSION 2u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 2u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u #define CY_IP_MXS40PASS 1u #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u #define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 7u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 1u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_03_config.h" #include "gpio_psoc6_03_68_qfn.h" @@ -848,6 +848,7 @@ typedef enum { #define PROT_BASE 0x40230000UL #define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ #define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ #define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ #define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ @@ -864,23 +865,6 @@ typedef enum { #define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ #define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ #define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ -#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ -#define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ -#define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ -#define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ -#define PROT_MPU5_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[3]) /* 0x40235660 */ -#define PROT_MPU5_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[4]) /* 0x40235680 */ -#define PROT_MPU5_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[5]) /* 0x402356A0 */ -#define PROT_MPU5_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[6]) /* 0x402356C0 */ -#define PROT_MPU5_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[7]) /* 0x402356E0 */ -#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ -#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ -#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ -#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ -#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ -#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ -#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ -#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ #define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ #define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ #define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ @@ -897,6 +881,22 @@ typedef enum { #define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ #define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ #define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ +#define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ +#define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ +#define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ +#define PROT_MPU5_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[3]) /* 0x40235660 */ +#define PROT_MPU5_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[4]) /* 0x40235680 */ +#define PROT_MPU5_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[5]) /* 0x402356A0 */ +#define PROT_MPU5_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[6]) /* 0x402356C0 */ +#define PROT_MPU5_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[7]) /* 0x402356E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ /******************************************************************************* * FLASHC @@ -1138,8 +1138,8 @@ typedef enum { #define CANFD0_BASE 0x40520000UL #define CANFD0 ((CANFD_Type*) CANFD0_BASE) /* 0x40520000 */ -#define CANFD0_CH0_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[0].M_TTCAN) /* 0x40520000 */ #define CANFD0_CH0 ((CANFD_CH_Type*) &CANFD0->CH[0]) /* 0x40520000 */ +#define CANFD0_CH0_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[0].M_TTCAN) /* 0x40520000 */ /******************************************************************************* * SCB diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245lqi_s3d12.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245lqi_s3d12.h index 535764765c..2ec7abfdb0 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245lqi_s3d12.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245lqi_s3d12.h @@ -5,11 +5,11 @@ * CY8C6245LQI-S3D12 device header * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -426,45 +426,21 @@ typedef enum { #define CY_FLASH_SIZE 0x00080000UL #define CY_EM_EEPROM_BASE 0x14000000UL #define CY_EM_EEPROM_SIZE 0x00008000UL -#define CY_XIP_BASE 0x18000000UL -#define CY_XIP_SIZE 0x08000000UL -#define CY_CAN0MRAM_BASE 0x40530000UL -#define CY_CAN0MRAM_SIZE 0x00010000UL #define CY_SFLASH_BASE 0x16000000UL #define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL #define CY_EFUSE_BASE 0x402C0800UL #define CY_EFUSE_SIZE 0x00000200UL +#define CY_CAN0MRAM_BASE 0x40530000UL +#define CY_CAN0MRAM_SIZE 0x00010000UL #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 2u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 7u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 2u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXTTCANFD 1u +#define CY_IP_MXTTCANFD_INSTANCES 1u +#define CY_IP_MXTTCANFD_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 2u @@ -474,33 +450,57 @@ typedef enum { #define CY_IP_M4CPUSS_DMA 1u #define CY_IP_M4CPUSS_DMA_INSTANCES 2u #define CY_IP_M4CPUSS_DMA_VERSION 2u -#define CY_IP_MXSDHC 1u -#define CY_IP_MXSDHC_INSTANCES 1u -#define CY_IP_MXSDHC_VERSION 1u -#define CY_IP_MXTTCANFD 1u -#define CY_IP_MXTTCANFD_INSTANCES 1u -#define CY_IP_MXTTCANFD_VERSION 1u -#define CY_IP_MXLPCOMP 1u -#define CY_IP_MXLPCOMP_INSTANCES 1u -#define CY_IP_MXLPCOMP_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u #define CY_IP_MXS40IOSS 1u #define CY_IP_MXS40IOSS_INSTANCES 1u #define CY_IP_MXS40IOSS_VERSION 2u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 2u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u #define CY_IP_MXS40PASS 1u #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u #define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 7u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 1u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_03_config.h" #include "gpio_psoc6_03_68_qfn.h" @@ -848,6 +848,7 @@ typedef enum { #define PROT_BASE 0x40230000UL #define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ #define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ #define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ #define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ @@ -864,23 +865,6 @@ typedef enum { #define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ #define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ #define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ -#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ -#define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ -#define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ -#define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ -#define PROT_MPU5_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[3]) /* 0x40235660 */ -#define PROT_MPU5_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[4]) /* 0x40235680 */ -#define PROT_MPU5_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[5]) /* 0x402356A0 */ -#define PROT_MPU5_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[6]) /* 0x402356C0 */ -#define PROT_MPU5_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[7]) /* 0x402356E0 */ -#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ -#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ -#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ -#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ -#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ -#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ -#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ -#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ #define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ #define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ #define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ @@ -897,6 +881,22 @@ typedef enum { #define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ #define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ #define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ +#define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ +#define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ +#define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ +#define PROT_MPU5_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[3]) /* 0x40235660 */ +#define PROT_MPU5_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[4]) /* 0x40235680 */ +#define PROT_MPU5_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[5]) /* 0x402356A0 */ +#define PROT_MPU5_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[6]) /* 0x402356C0 */ +#define PROT_MPU5_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[7]) /* 0x402356E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ /******************************************************************************* * FLASHC @@ -1138,8 +1138,8 @@ typedef enum { #define CANFD0_BASE 0x40520000UL #define CANFD0 ((CANFD_Type*) CANFD0_BASE) /* 0x40520000 */ -#define CANFD0_CH0_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[0].M_TTCAN) /* 0x40520000 */ #define CANFD0_CH0 ((CANFD_CH_Type*) &CANFD0->CH[0]) /* 0x40520000 */ +#define CANFD0_CH0_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[0].M_TTCAN) /* 0x40520000 */ /******************************************************************************* * SCB diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245lqi_s3d42.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245lqi_s3d42.h index 1285634e7f..0c0b492dc8 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245lqi_s3d42.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245lqi_s3d42.h @@ -5,11 +5,11 @@ * CY8C6245LQI-S3D42 device header * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -426,45 +426,21 @@ typedef enum { #define CY_FLASH_SIZE 0x00080000UL #define CY_EM_EEPROM_BASE 0x14000000UL #define CY_EM_EEPROM_SIZE 0x00008000UL -#define CY_XIP_BASE 0x18000000UL -#define CY_XIP_SIZE 0x08000000UL -#define CY_CAN0MRAM_BASE 0x40530000UL -#define CY_CAN0MRAM_SIZE 0x00010000UL #define CY_SFLASH_BASE 0x16000000UL #define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL #define CY_EFUSE_BASE 0x402C0800UL #define CY_EFUSE_SIZE 0x00000200UL +#define CY_CAN0MRAM_BASE 0x40530000UL +#define CY_CAN0MRAM_SIZE 0x00010000UL #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 2u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 7u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 2u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXTTCANFD 1u +#define CY_IP_MXTTCANFD_INSTANCES 1u +#define CY_IP_MXTTCANFD_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 2u @@ -477,33 +453,57 @@ typedef enum { #define CY_IP_MXCRYPTO 1u #define CY_IP_MXCRYPTO_INSTANCES 1u #define CY_IP_MXCRYPTO_VERSION 2u -#define CY_IP_MXSDHC 1u -#define CY_IP_MXSDHC_INSTANCES 1u -#define CY_IP_MXSDHC_VERSION 1u -#define CY_IP_MXTTCANFD 1u -#define CY_IP_MXTTCANFD_INSTANCES 1u -#define CY_IP_MXTTCANFD_VERSION 1u -#define CY_IP_MXLPCOMP 1u -#define CY_IP_MXLPCOMP_INSTANCES 1u -#define CY_IP_MXLPCOMP_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u #define CY_IP_MXS40IOSS 1u #define CY_IP_MXS40IOSS_INSTANCES 1u #define CY_IP_MXS40IOSS_VERSION 2u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 2u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u #define CY_IP_MXS40PASS 1u #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u #define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 7u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 1u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_03_config.h" #include "gpio_psoc6_03_68_qfn.h" @@ -858,6 +858,7 @@ typedef enum { #define PROT_BASE 0x40230000UL #define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ #define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ #define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ #define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ @@ -874,23 +875,6 @@ typedef enum { #define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ #define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ #define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ -#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ -#define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ -#define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ -#define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ -#define PROT_MPU5_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[3]) /* 0x40235660 */ -#define PROT_MPU5_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[4]) /* 0x40235680 */ -#define PROT_MPU5_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[5]) /* 0x402356A0 */ -#define PROT_MPU5_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[6]) /* 0x402356C0 */ -#define PROT_MPU5_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[7]) /* 0x402356E0 */ -#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ -#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ -#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ -#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ -#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ -#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ -#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ -#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ #define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ #define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ #define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ @@ -907,6 +891,22 @@ typedef enum { #define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ #define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ #define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ +#define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ +#define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ +#define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ +#define PROT_MPU5_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[3]) /* 0x40235660 */ +#define PROT_MPU5_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[4]) /* 0x40235680 */ +#define PROT_MPU5_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[5]) /* 0x402356A0 */ +#define PROT_MPU5_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[6]) /* 0x402356C0 */ +#define PROT_MPU5_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[7]) /* 0x402356E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ /******************************************************************************* * FLASHC @@ -1148,8 +1148,8 @@ typedef enum { #define CANFD0_BASE 0x40520000UL #define CANFD0 ((CANFD_Type*) CANFD0_BASE) /* 0x40520000 */ -#define CANFD0_CH0_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[0].M_TTCAN) /* 0x40520000 */ #define CANFD0_CH0 ((CANFD_CH_Type*) &CANFD0->CH[0]) /* 0x40520000 */ +#define CANFD0_CH0_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[0].M_TTCAN) /* 0x40520000 */ /******************************************************************************* * SCB diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245lqi_s3d62.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245lqi_s3d62.h index c74fcfd2c2..f0343467a5 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245lqi_s3d62.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245lqi_s3d62.h @@ -5,11 +5,11 @@ * CY8C6245LQI-S3D62 device header * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -426,45 +426,21 @@ typedef enum { #define CY_FLASH_SIZE 0x00080000UL #define CY_EM_EEPROM_BASE 0x14000000UL #define CY_EM_EEPROM_SIZE 0x00008000UL -#define CY_XIP_BASE 0x18000000UL -#define CY_XIP_SIZE 0x08000000UL -#define CY_CAN0MRAM_BASE 0x40530000UL -#define CY_CAN0MRAM_SIZE 0x00010000UL #define CY_SFLASH_BASE 0x16000000UL #define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL #define CY_EFUSE_BASE 0x402C0800UL #define CY_EFUSE_SIZE 0x00000200UL +#define CY_CAN0MRAM_BASE 0x40530000UL +#define CY_CAN0MRAM_SIZE 0x00010000UL #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 2u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 7u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 2u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXTTCANFD 1u +#define CY_IP_MXTTCANFD_INSTANCES 1u +#define CY_IP_MXTTCANFD_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 2u @@ -474,33 +450,57 @@ typedef enum { #define CY_IP_M4CPUSS_DMA 1u #define CY_IP_M4CPUSS_DMA_INSTANCES 2u #define CY_IP_M4CPUSS_DMA_VERSION 2u -#define CY_IP_MXSDHC 1u -#define CY_IP_MXSDHC_INSTANCES 1u -#define CY_IP_MXSDHC_VERSION 1u -#define CY_IP_MXTTCANFD 1u -#define CY_IP_MXTTCANFD_INSTANCES 1u -#define CY_IP_MXTTCANFD_VERSION 1u -#define CY_IP_MXLPCOMP 1u -#define CY_IP_MXLPCOMP_INSTANCES 1u -#define CY_IP_MXLPCOMP_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u #define CY_IP_MXS40IOSS 1u #define CY_IP_MXS40IOSS_INSTANCES 1u #define CY_IP_MXS40IOSS_VERSION 2u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 2u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u #define CY_IP_MXS40PASS 1u #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u #define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 7u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 1u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_03_config.h" #include "gpio_psoc6_03_68_qfn.h" @@ -848,6 +848,7 @@ typedef enum { #define PROT_BASE 0x40230000UL #define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ #define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ #define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ #define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ @@ -864,23 +865,6 @@ typedef enum { #define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ #define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ #define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ -#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ -#define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ -#define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ -#define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ -#define PROT_MPU5_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[3]) /* 0x40235660 */ -#define PROT_MPU5_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[4]) /* 0x40235680 */ -#define PROT_MPU5_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[5]) /* 0x402356A0 */ -#define PROT_MPU5_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[6]) /* 0x402356C0 */ -#define PROT_MPU5_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[7]) /* 0x402356E0 */ -#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ -#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ -#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ -#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ -#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ -#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ -#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ -#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ #define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ #define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ #define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ @@ -897,6 +881,22 @@ typedef enum { #define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ #define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ #define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ +#define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ +#define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ +#define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ +#define PROT_MPU5_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[3]) /* 0x40235660 */ +#define PROT_MPU5_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[4]) /* 0x40235680 */ +#define PROT_MPU5_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[5]) /* 0x402356A0 */ +#define PROT_MPU5_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[6]) /* 0x402356C0 */ +#define PROT_MPU5_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[7]) /* 0x402356E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ /******************************************************************************* * FLASHC @@ -1138,8 +1138,8 @@ typedef enum { #define CANFD0_BASE 0x40520000UL #define CANFD0 ((CANFD_Type*) CANFD0_BASE) /* 0x40520000 */ -#define CANFD0_CH0_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[0].M_TTCAN) /* 0x40520000 */ #define CANFD0_CH0 ((CANFD_CH_Type*) &CANFD0->CH[0]) /* 0x40520000 */ +#define CANFD0_CH0_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[0].M_TTCAN) /* 0x40520000 */ /******************************************************************************* * SCB diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245lqi_s3d72.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245lqi_s3d72.h index 4888554381..8fba63cf58 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245lqi_s3d72.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245lqi_s3d72.h @@ -5,11 +5,11 @@ * CY8C6245LQI-S3D72 device header * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -426,45 +426,21 @@ typedef enum { #define CY_FLASH_SIZE 0x00080000UL #define CY_EM_EEPROM_BASE 0x14000000UL #define CY_EM_EEPROM_SIZE 0x00008000UL -#define CY_XIP_BASE 0x18000000UL -#define CY_XIP_SIZE 0x08000000UL -#define CY_CAN0MRAM_BASE 0x40530000UL -#define CY_CAN0MRAM_SIZE 0x00010000UL #define CY_SFLASH_BASE 0x16000000UL #define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL #define CY_EFUSE_BASE 0x402C0800UL #define CY_EFUSE_SIZE 0x00000200UL +#define CY_CAN0MRAM_BASE 0x40530000UL +#define CY_CAN0MRAM_SIZE 0x00010000UL #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 2u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 7u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 2u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXTTCANFD 1u +#define CY_IP_MXTTCANFD_INSTANCES 1u +#define CY_IP_MXTTCANFD_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 2u @@ -477,33 +453,57 @@ typedef enum { #define CY_IP_MXCRYPTO 1u #define CY_IP_MXCRYPTO_INSTANCES 1u #define CY_IP_MXCRYPTO_VERSION 2u -#define CY_IP_MXSDHC 1u -#define CY_IP_MXSDHC_INSTANCES 1u -#define CY_IP_MXSDHC_VERSION 1u -#define CY_IP_MXTTCANFD 1u -#define CY_IP_MXTTCANFD_INSTANCES 1u -#define CY_IP_MXTTCANFD_VERSION 1u -#define CY_IP_MXLPCOMP 1u -#define CY_IP_MXLPCOMP_INSTANCES 1u -#define CY_IP_MXLPCOMP_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u #define CY_IP_MXS40IOSS 1u #define CY_IP_MXS40IOSS_INSTANCES 1u #define CY_IP_MXS40IOSS_VERSION 2u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 2u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u #define CY_IP_MXS40PASS 1u #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u #define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 7u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 1u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_03_config.h" #include "gpio_psoc6_03_68_qfn.h" @@ -858,6 +858,7 @@ typedef enum { #define PROT_BASE 0x40230000UL #define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ #define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ #define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ #define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ @@ -874,23 +875,6 @@ typedef enum { #define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ #define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ #define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ -#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ -#define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ -#define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ -#define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ -#define PROT_MPU5_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[3]) /* 0x40235660 */ -#define PROT_MPU5_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[4]) /* 0x40235680 */ -#define PROT_MPU5_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[5]) /* 0x402356A0 */ -#define PROT_MPU5_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[6]) /* 0x402356C0 */ -#define PROT_MPU5_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[7]) /* 0x402356E0 */ -#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ -#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ -#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ -#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ -#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ -#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ -#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ -#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ #define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ #define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ #define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ @@ -907,6 +891,22 @@ typedef enum { #define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ #define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ #define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ +#define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ +#define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ +#define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ +#define PROT_MPU5_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[3]) /* 0x40235660 */ +#define PROT_MPU5_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[4]) /* 0x40235680 */ +#define PROT_MPU5_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[5]) /* 0x402356A0 */ +#define PROT_MPU5_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[6]) /* 0x402356C0 */ +#define PROT_MPU5_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[7]) /* 0x402356E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ /******************************************************************************* * FLASHC @@ -1148,8 +1148,8 @@ typedef enum { #define CANFD0_BASE 0x40520000UL #define CANFD0 ((CANFD_Type*) CANFD0_BASE) /* 0x40520000 */ -#define CANFD0_CH0_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[0].M_TTCAN) /* 0x40520000 */ #define CANFD0_CH0 ((CANFD_CH_Type*) &CANFD0->CH[0]) /* 0x40520000 */ +#define CANFD0_CH0_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[0].M_TTCAN) /* 0x40520000 */ /******************************************************************************* * SCB diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6246bzi_d04.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6246bzi_d04.h index b7ccc547be..e9a38029e2 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6246bzi_d04.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6246bzi_d04.h @@ -5,11 +5,11 @@ * CY8C6246BZI-D04 device header * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -461,52 +461,37 @@ typedef enum { #define CY_FLASH_SIZE 0x00080000UL #define CY_EM_EEPROM_BASE 0x14000000UL #define CY_EM_EEPROM_SIZE 0x00008000UL -#define CY_XIP_BASE 0x18000000UL -#define CY_XIP_SIZE 0x08000000UL #define CY_SFLASH_BASE 0x16000000UL #define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL #define CY_EFUSE_BASE 0x402C0800UL #define CY_EFUSE_SIZE 0x00000200UL #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u #define CY_IP_M4CPUSS_DMA 1u #define CY_IP_M4CPUSS_DMA_INSTANCES 2u #define CY_IP_M4CPUSS_DMA_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -519,21 +504,36 @@ typedef enum { #define CY_IP_MXS40PASS_CTDAC 1u #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u #define CY_IP_MXS40PASS_CTDAC_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_124_bga.h" @@ -826,6 +826,7 @@ typedef enum { #define PROT_BASE 0x40240000UL #define PROT ((PROT_Type*) PROT_BASE) /* 0x40240000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ #define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40242000 */ #define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40242040 */ #define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40242080 */ @@ -842,23 +843,6 @@ typedef enum { #define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40242340 */ #define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40242380 */ #define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402423C0 */ -#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ -#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ -#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ -#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ -#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ -#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ -#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ -#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ -#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ -#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ -#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ -#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ -#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ -#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ -#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ -#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ -#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ #define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40244000 */ #define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40244400 */ #define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40244800 */ @@ -875,6 +859,22 @@ typedef enum { #define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40247400 */ #define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40247800 */ #define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40247C00 */ +#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ +#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ +#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ +#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ +#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ +#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ +#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ +#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ /******************************************************************************* * FLASHC diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247bfi_d54.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247bfi_d54.h index 673ccde310..92282a683b 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247bfi_d54.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247bfi_d54.h @@ -5,11 +5,11 @@ * CY8C6247BFI-D54 device header * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -461,43 +461,19 @@ typedef enum { #define CY_FLASH_SIZE 0x00100000UL #define CY_EM_EEPROM_BASE 0x14000000UL #define CY_EM_EEPROM_SIZE 0x00008000UL -#define CY_XIP_BASE 0x18000000UL -#define CY_XIP_SIZE 0x08000000UL #define CY_SFLASH_BASE 0x16000000UL #define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL #define CY_EFUSE_BASE 0x402C0800UL #define CY_EFUSE_SIZE 0x00000200UL #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u @@ -507,9 +483,18 @@ typedef enum { #define CY_IP_MXCRYPTO 1u #define CY_IP_MXCRYPTO_INSTANCES 1u #define CY_IP_MXCRYPTO_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -525,24 +510,39 @@ typedef enum { #define CY_IP_MXS40PASS_CTB 1u #define CY_IP_MXS40PASS_CTB_INSTANCES 1u #define CY_IP_MXS40PASS_CTB_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u -#define CY_IP_MXUDB 1u -#define CY_IP_MXUDB_INSTANCES 1u -#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUDB 1u +#define CY_IP_MXUDB_INSTANCES 1u +#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_124_bga.h" @@ -842,6 +842,7 @@ typedef enum { #define PROT_BASE 0x40240000UL #define PROT ((PROT_Type*) PROT_BASE) /* 0x40240000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ #define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40242000 */ #define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40242040 */ #define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40242080 */ @@ -858,23 +859,6 @@ typedef enum { #define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40242340 */ #define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40242380 */ #define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402423C0 */ -#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ -#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ -#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ -#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ -#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ -#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ -#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ -#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ -#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ -#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ -#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ -#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ -#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ -#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ -#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ -#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ -#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ #define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40244000 */ #define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40244400 */ #define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40244800 */ @@ -891,6 +875,22 @@ typedef enum { #define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40247400 */ #define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40247800 */ #define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40247C00 */ +#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ +#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ +#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ +#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ +#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ +#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ +#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ +#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ /******************************************************************************* * FLASHC @@ -1040,6 +1040,12 @@ typedef enum { #define UDB ((UDB_Type*) UDB_BASE) /* 0x40340000 */ #define UDB_WRKONE ((UDB_WRKONE_Type*) &UDB->WRKONE) /* 0x40340000 */ #define UDB_WRKMULT ((UDB_WRKMULT_Type*) &UDB->WRKMULT) /* 0x40341000 */ +#define UDB_UDBPAIR0 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[0]) /* 0x40342000 */ +#define UDB_UDBPAIR1 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[1]) /* 0x40342200 */ +#define UDB_UDBPAIR2 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[2]) /* 0x40342400 */ +#define UDB_UDBPAIR3 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[3]) /* 0x40342600 */ +#define UDB_UDBPAIR4 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[4]) /* 0x40342800 */ +#define UDB_UDBPAIR5 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[5]) /* 0x40342A00 */ #define UDB_UDBPAIR0_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[0].UDBSNG[0]) /* 0x40342000 */ #define UDB_UDBPAIR0_UDBSNG1 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[0].UDBSNG[1]) /* 0x40342080 */ #define UDB_UDBPAIR1_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[1].UDBSNG[0]) /* 0x40342200 */ @@ -1058,12 +1064,6 @@ typedef enum { #define UDB_UDBPAIR3_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[3].ROUTE) /* 0x40342700 */ #define UDB_UDBPAIR4_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[4].ROUTE) /* 0x40342900 */ #define UDB_UDBPAIR5_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[5].ROUTE) /* 0x40342B00 */ -#define UDB_UDBPAIR0 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[0]) /* 0x40342000 */ -#define UDB_UDBPAIR1 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[1]) /* 0x40342200 */ -#define UDB_UDBPAIR2 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[2]) /* 0x40342400 */ -#define UDB_UDBPAIR3 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[3]) /* 0x40342600 */ -#define UDB_UDBPAIR4 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[4]) /* 0x40342800 */ -#define UDB_UDBPAIR5 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[5]) /* 0x40342A00 */ #define UDB_DSI0 ((UDB_DSI_Type*) &UDB->DSI[0]) /* 0x40346000 */ #define UDB_DSI1 ((UDB_DSI_Type*) &UDB->DSI[1]) /* 0x40346080 */ #define UDB_DSI2 ((UDB_DSI_Type*) &UDB->DSI[2]) /* 0x40346100 */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247bzi_aud54.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247bzi_aud54.h index c4c2f1ac6c..42886db724 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247bzi_aud54.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247bzi_aud54.h @@ -5,11 +5,11 @@ * CY8C6247BZI-AUD54 device header * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -461,43 +461,19 @@ typedef enum { #define CY_FLASH_SIZE 0x00100000UL #define CY_EM_EEPROM_BASE 0x14000000UL #define CY_EM_EEPROM_SIZE 0x00008000UL -#define CY_XIP_BASE 0x18000000UL -#define CY_XIP_SIZE 0x08000000UL #define CY_SFLASH_BASE 0x16000000UL #define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL #define CY_EFUSE_BASE 0x402C0800UL #define CY_EFUSE_SIZE 0x00000200UL #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u @@ -507,9 +483,18 @@ typedef enum { #define CY_IP_MXCRYPTO 1u #define CY_IP_MXCRYPTO_INSTANCES 1u #define CY_IP_MXCRYPTO_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -525,24 +510,39 @@ typedef enum { #define CY_IP_MXS40PASS_CTB 1u #define CY_IP_MXS40PASS_CTB_INSTANCES 1u #define CY_IP_MXS40PASS_CTB_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u -#define CY_IP_MXUDB 1u -#define CY_IP_MXUDB_INSTANCES 1u -#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUDB 1u +#define CY_IP_MXUDB_INSTANCES 1u +#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_124_bga.h" @@ -842,6 +842,7 @@ typedef enum { #define PROT_BASE 0x40240000UL #define PROT ((PROT_Type*) PROT_BASE) /* 0x40240000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ #define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40242000 */ #define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40242040 */ #define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40242080 */ @@ -858,23 +859,6 @@ typedef enum { #define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40242340 */ #define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40242380 */ #define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402423C0 */ -#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ -#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ -#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ -#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ -#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ -#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ -#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ -#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ -#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ -#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ -#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ -#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ -#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ -#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ -#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ -#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ -#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ #define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40244000 */ #define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40244400 */ #define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40244800 */ @@ -891,6 +875,22 @@ typedef enum { #define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40247400 */ #define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40247800 */ #define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40247C00 */ +#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ +#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ +#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ +#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ +#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ +#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ +#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ +#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ /******************************************************************************* * FLASHC @@ -1040,6 +1040,12 @@ typedef enum { #define UDB ((UDB_Type*) UDB_BASE) /* 0x40340000 */ #define UDB_WRKONE ((UDB_WRKONE_Type*) &UDB->WRKONE) /* 0x40340000 */ #define UDB_WRKMULT ((UDB_WRKMULT_Type*) &UDB->WRKMULT) /* 0x40341000 */ +#define UDB_UDBPAIR0 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[0]) /* 0x40342000 */ +#define UDB_UDBPAIR1 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[1]) /* 0x40342200 */ +#define UDB_UDBPAIR2 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[2]) /* 0x40342400 */ +#define UDB_UDBPAIR3 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[3]) /* 0x40342600 */ +#define UDB_UDBPAIR4 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[4]) /* 0x40342800 */ +#define UDB_UDBPAIR5 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[5]) /* 0x40342A00 */ #define UDB_UDBPAIR0_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[0].UDBSNG[0]) /* 0x40342000 */ #define UDB_UDBPAIR0_UDBSNG1 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[0].UDBSNG[1]) /* 0x40342080 */ #define UDB_UDBPAIR1_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[1].UDBSNG[0]) /* 0x40342200 */ @@ -1058,12 +1064,6 @@ typedef enum { #define UDB_UDBPAIR3_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[3].ROUTE) /* 0x40342700 */ #define UDB_UDBPAIR4_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[4].ROUTE) /* 0x40342900 */ #define UDB_UDBPAIR5_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[5].ROUTE) /* 0x40342B00 */ -#define UDB_UDBPAIR0 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[0]) /* 0x40342000 */ -#define UDB_UDBPAIR1 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[1]) /* 0x40342200 */ -#define UDB_UDBPAIR2 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[2]) /* 0x40342400 */ -#define UDB_UDBPAIR3 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[3]) /* 0x40342600 */ -#define UDB_UDBPAIR4 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[4]) /* 0x40342800 */ -#define UDB_UDBPAIR5 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[5]) /* 0x40342A00 */ #define UDB_DSI0 ((UDB_DSI_Type*) &UDB->DSI[0]) /* 0x40346000 */ #define UDB_DSI1 ((UDB_DSI_Type*) &UDB->DSI[1]) /* 0x40346080 */ #define UDB_DSI2 ((UDB_DSI_Type*) &UDB->DSI[2]) /* 0x40346100 */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247bzi_d34.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247bzi_d34.h index 586dafb463..3027b63d1e 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247bzi_d34.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247bzi_d34.h @@ -5,11 +5,11 @@ * CY8C6247BZI-D34 device header * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -461,52 +461,37 @@ typedef enum { #define CY_FLASH_SIZE 0x00100000UL #define CY_EM_EEPROM_BASE 0x14000000UL #define CY_EM_EEPROM_SIZE 0x00008000UL -#define CY_XIP_BASE 0x18000000UL -#define CY_XIP_SIZE 0x08000000UL #define CY_SFLASH_BASE 0x16000000UL #define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL #define CY_EFUSE_BASE 0x402C0800UL #define CY_EFUSE_SIZE 0x00000200UL #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u #define CY_IP_M4CPUSS_DMA 1u #define CY_IP_M4CPUSS_DMA_INSTANCES 2u #define CY_IP_M4CPUSS_DMA_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -522,24 +507,39 @@ typedef enum { #define CY_IP_MXS40PASS_CTB 1u #define CY_IP_MXS40PASS_CTB_INSTANCES 1u #define CY_IP_MXS40PASS_CTB_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u -#define CY_IP_MXUDB 1u -#define CY_IP_MXUDB_INSTANCES 1u -#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUDB 1u +#define CY_IP_MXUDB_INSTANCES 1u +#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_124_bga.h" @@ -832,6 +832,7 @@ typedef enum { #define PROT_BASE 0x40240000UL #define PROT ((PROT_Type*) PROT_BASE) /* 0x40240000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ #define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40242000 */ #define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40242040 */ #define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40242080 */ @@ -848,23 +849,6 @@ typedef enum { #define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40242340 */ #define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40242380 */ #define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402423C0 */ -#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ -#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ -#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ -#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ -#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ -#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ -#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ -#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ -#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ -#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ -#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ -#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ -#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ -#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ -#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ -#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ -#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ #define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40244000 */ #define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40244400 */ #define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40244800 */ @@ -881,6 +865,22 @@ typedef enum { #define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40247400 */ #define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40247800 */ #define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40247C00 */ +#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ +#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ +#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ +#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ +#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ +#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ +#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ +#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ /******************************************************************************* * FLASHC @@ -1030,6 +1030,12 @@ typedef enum { #define UDB ((UDB_Type*) UDB_BASE) /* 0x40340000 */ #define UDB_WRKONE ((UDB_WRKONE_Type*) &UDB->WRKONE) /* 0x40340000 */ #define UDB_WRKMULT ((UDB_WRKMULT_Type*) &UDB->WRKMULT) /* 0x40341000 */ +#define UDB_UDBPAIR0 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[0]) /* 0x40342000 */ +#define UDB_UDBPAIR1 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[1]) /* 0x40342200 */ +#define UDB_UDBPAIR2 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[2]) /* 0x40342400 */ +#define UDB_UDBPAIR3 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[3]) /* 0x40342600 */ +#define UDB_UDBPAIR4 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[4]) /* 0x40342800 */ +#define UDB_UDBPAIR5 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[5]) /* 0x40342A00 */ #define UDB_UDBPAIR0_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[0].UDBSNG[0]) /* 0x40342000 */ #define UDB_UDBPAIR0_UDBSNG1 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[0].UDBSNG[1]) /* 0x40342080 */ #define UDB_UDBPAIR1_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[1].UDBSNG[0]) /* 0x40342200 */ @@ -1048,12 +1054,6 @@ typedef enum { #define UDB_UDBPAIR3_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[3].ROUTE) /* 0x40342700 */ #define UDB_UDBPAIR4_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[4].ROUTE) /* 0x40342900 */ #define UDB_UDBPAIR5_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[5].ROUTE) /* 0x40342B00 */ -#define UDB_UDBPAIR0 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[0]) /* 0x40342000 */ -#define UDB_UDBPAIR1 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[1]) /* 0x40342200 */ -#define UDB_UDBPAIR2 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[2]) /* 0x40342400 */ -#define UDB_UDBPAIR3 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[3]) /* 0x40342600 */ -#define UDB_UDBPAIR4 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[4]) /* 0x40342800 */ -#define UDB_UDBPAIR5 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[5]) /* 0x40342A00 */ #define UDB_DSI0 ((UDB_DSI_Type*) &UDB->DSI[0]) /* 0x40346000 */ #define UDB_DSI1 ((UDB_DSI_Type*) &UDB->DSI[1]) /* 0x40346080 */ #define UDB_DSI2 ((UDB_DSI_Type*) &UDB->DSI[2]) /* 0x40346100 */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247bzi_d44.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247bzi_d44.h index cd158225df..93c9a4d432 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247bzi_d44.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247bzi_d44.h @@ -5,11 +5,11 @@ * CY8C6247BZI-D44 device header * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -461,43 +461,19 @@ typedef enum { #define CY_FLASH_SIZE 0x00100000UL #define CY_EM_EEPROM_BASE 0x14000000UL #define CY_EM_EEPROM_SIZE 0x00008000UL -#define CY_XIP_BASE 0x18000000UL -#define CY_XIP_SIZE 0x08000000UL #define CY_SFLASH_BASE 0x16000000UL #define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL #define CY_EFUSE_BASE 0x402C0800UL #define CY_EFUSE_SIZE 0x00000200UL #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u @@ -507,9 +483,18 @@ typedef enum { #define CY_IP_MXCRYPTO 1u #define CY_IP_MXCRYPTO_INSTANCES 1u #define CY_IP_MXCRYPTO_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -522,21 +507,36 @@ typedef enum { #define CY_IP_MXS40PASS_CTDAC 1u #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u #define CY_IP_MXS40PASS_CTDAC_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_124_bga.h" @@ -836,6 +836,7 @@ typedef enum { #define PROT_BASE 0x40240000UL #define PROT ((PROT_Type*) PROT_BASE) /* 0x40240000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ #define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40242000 */ #define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40242040 */ #define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40242080 */ @@ -852,23 +853,6 @@ typedef enum { #define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40242340 */ #define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40242380 */ #define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402423C0 */ -#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ -#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ -#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ -#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ -#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ -#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ -#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ -#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ -#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ -#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ -#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ -#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ -#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ -#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ -#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ -#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ -#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ #define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40244000 */ #define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40244400 */ #define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40244800 */ @@ -885,6 +869,22 @@ typedef enum { #define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40247400 */ #define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40247800 */ #define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40247C00 */ +#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ +#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ +#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ +#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ +#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ +#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ +#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ +#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ /******************************************************************************* * FLASHC diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247bzi_d54.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247bzi_d54.h index 12b1ca9d1e..dfb56179f7 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247bzi_d54.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247bzi_d54.h @@ -5,11 +5,11 @@ * CY8C6247BZI-D54 device header * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -461,43 +461,19 @@ typedef enum { #define CY_FLASH_SIZE 0x00100000UL #define CY_EM_EEPROM_BASE 0x14000000UL #define CY_EM_EEPROM_SIZE 0x00008000UL -#define CY_XIP_BASE 0x18000000UL -#define CY_XIP_SIZE 0x08000000UL #define CY_SFLASH_BASE 0x16000000UL #define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL #define CY_EFUSE_BASE 0x402C0800UL #define CY_EFUSE_SIZE 0x00000200UL #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u @@ -507,9 +483,18 @@ typedef enum { #define CY_IP_MXCRYPTO 1u #define CY_IP_MXCRYPTO_INSTANCES 1u #define CY_IP_MXCRYPTO_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -525,24 +510,39 @@ typedef enum { #define CY_IP_MXS40PASS_CTB 1u #define CY_IP_MXS40PASS_CTB_INSTANCES 1u #define CY_IP_MXS40PASS_CTB_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u -#define CY_IP_MXUDB 1u -#define CY_IP_MXUDB_INSTANCES 1u -#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUDB 1u +#define CY_IP_MXUDB_INSTANCES 1u +#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_124_bga.h" @@ -842,6 +842,7 @@ typedef enum { #define PROT_BASE 0x40240000UL #define PROT ((PROT_Type*) PROT_BASE) /* 0x40240000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ #define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40242000 */ #define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40242040 */ #define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40242080 */ @@ -858,23 +859,6 @@ typedef enum { #define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40242340 */ #define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40242380 */ #define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402423C0 */ -#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ -#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ -#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ -#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ -#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ -#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ -#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ -#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ -#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ -#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ -#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ -#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ -#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ -#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ -#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ -#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ -#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ #define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40244000 */ #define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40244400 */ #define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40244800 */ @@ -891,6 +875,22 @@ typedef enum { #define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40247400 */ #define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40247800 */ #define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40247C00 */ +#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ +#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ +#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ +#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ +#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ +#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ +#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ +#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ /******************************************************************************* * FLASHC @@ -1040,6 +1040,12 @@ typedef enum { #define UDB ((UDB_Type*) UDB_BASE) /* 0x40340000 */ #define UDB_WRKONE ((UDB_WRKONE_Type*) &UDB->WRKONE) /* 0x40340000 */ #define UDB_WRKMULT ((UDB_WRKMULT_Type*) &UDB->WRKMULT) /* 0x40341000 */ +#define UDB_UDBPAIR0 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[0]) /* 0x40342000 */ +#define UDB_UDBPAIR1 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[1]) /* 0x40342200 */ +#define UDB_UDBPAIR2 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[2]) /* 0x40342400 */ +#define UDB_UDBPAIR3 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[3]) /* 0x40342600 */ +#define UDB_UDBPAIR4 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[4]) /* 0x40342800 */ +#define UDB_UDBPAIR5 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[5]) /* 0x40342A00 */ #define UDB_UDBPAIR0_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[0].UDBSNG[0]) /* 0x40342000 */ #define UDB_UDBPAIR0_UDBSNG1 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[0].UDBSNG[1]) /* 0x40342080 */ #define UDB_UDBPAIR1_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[1].UDBSNG[0]) /* 0x40342200 */ @@ -1058,12 +1064,6 @@ typedef enum { #define UDB_UDBPAIR3_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[3].ROUTE) /* 0x40342700 */ #define UDB_UDBPAIR4_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[4].ROUTE) /* 0x40342900 */ #define UDB_UDBPAIR5_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[5].ROUTE) /* 0x40342B00 */ -#define UDB_UDBPAIR0 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[0]) /* 0x40342000 */ -#define UDB_UDBPAIR1 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[1]) /* 0x40342200 */ -#define UDB_UDBPAIR2 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[2]) /* 0x40342400 */ -#define UDB_UDBPAIR3 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[3]) /* 0x40342600 */ -#define UDB_UDBPAIR4 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[4]) /* 0x40342800 */ -#define UDB_UDBPAIR5 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[5]) /* 0x40342A00 */ #define UDB_DSI0 ((UDB_DSI_Type*) &UDB->DSI[0]) /* 0x40346000 */ #define UDB_DSI1 ((UDB_DSI_Type*) &UDB->DSI[1]) /* 0x40346080 */ #define UDB_DSI2 ((UDB_DSI_Type*) &UDB->DSI[2]) /* 0x40346100 */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247fdi_d02.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247fdi_d02.h index 962bb1a15f..1a1b44ec4c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247fdi_d02.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247fdi_d02.h @@ -5,11 +5,11 @@ * CY8C6247FDI-D02 device header * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -461,52 +461,37 @@ typedef enum { #define CY_FLASH_SIZE 0x00100000UL #define CY_EM_EEPROM_BASE 0x14000000UL #define CY_EM_EEPROM_SIZE 0x00008000UL -#define CY_XIP_BASE 0x18000000UL -#define CY_XIP_SIZE 0x08000000UL #define CY_SFLASH_BASE 0x16000000UL #define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL #define CY_EFUSE_BASE 0x402C0800UL #define CY_EFUSE_SIZE 0x00000200UL #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u #define CY_IP_M4CPUSS_DMA 1u #define CY_IP_M4CPUSS_DMA_INSTANCES 2u #define CY_IP_M4CPUSS_DMA_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -519,21 +504,36 @@ typedef enum { #define CY_IP_MXS40PASS_CTDAC 1u #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u #define CY_IP_MXS40PASS_CTDAC_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_80_wlcsp.h" @@ -826,6 +826,7 @@ typedef enum { #define PROT_BASE 0x40240000UL #define PROT ((PROT_Type*) PROT_BASE) /* 0x40240000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ #define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40242000 */ #define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40242040 */ #define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40242080 */ @@ -842,23 +843,6 @@ typedef enum { #define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40242340 */ #define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40242380 */ #define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402423C0 */ -#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ -#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ -#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ -#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ -#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ -#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ -#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ -#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ -#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ -#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ -#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ -#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ -#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ -#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ -#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ -#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ -#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ #define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40244000 */ #define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40244400 */ #define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40244800 */ @@ -875,6 +859,22 @@ typedef enum { #define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40247400 */ #define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40247800 */ #define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40247C00 */ +#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ +#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ +#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ +#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ +#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ +#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ +#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ +#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ /******************************************************************************* * FLASHC diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247fdi_d32.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247fdi_d32.h index fb736efcf5..8f08198b49 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247fdi_d32.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247fdi_d32.h @@ -5,11 +5,11 @@ * CY8C6247FDI-D32 device header * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -461,52 +461,37 @@ typedef enum { #define CY_FLASH_SIZE 0x00100000UL #define CY_EM_EEPROM_BASE 0x14000000UL #define CY_EM_EEPROM_SIZE 0x00008000UL -#define CY_XIP_BASE 0x18000000UL -#define CY_XIP_SIZE 0x08000000UL #define CY_SFLASH_BASE 0x16000000UL #define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL #define CY_EFUSE_BASE 0x402C0800UL #define CY_EFUSE_SIZE 0x00000200UL #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u #define CY_IP_M4CPUSS_DMA 1u #define CY_IP_M4CPUSS_DMA_INSTANCES 2u #define CY_IP_M4CPUSS_DMA_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -522,24 +507,39 @@ typedef enum { #define CY_IP_MXS40PASS_CTB 1u #define CY_IP_MXS40PASS_CTB_INSTANCES 1u #define CY_IP_MXS40PASS_CTB_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u -#define CY_IP_MXUDB 1u -#define CY_IP_MXUDB_INSTANCES 1u -#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUDB 1u +#define CY_IP_MXUDB_INSTANCES 1u +#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_80_wlcsp.h" @@ -832,6 +832,7 @@ typedef enum { #define PROT_BASE 0x40240000UL #define PROT ((PROT_Type*) PROT_BASE) /* 0x40240000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ #define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40242000 */ #define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40242040 */ #define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40242080 */ @@ -848,23 +849,6 @@ typedef enum { #define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40242340 */ #define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40242380 */ #define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402423C0 */ -#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ -#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ -#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ -#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ -#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ -#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ -#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ -#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ -#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ -#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ -#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ -#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ -#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ -#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ -#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ -#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ -#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ #define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40244000 */ #define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40244400 */ #define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40244800 */ @@ -881,6 +865,22 @@ typedef enum { #define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40247400 */ #define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40247800 */ #define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40247C00 */ +#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ +#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ +#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ +#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ +#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ +#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ +#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ +#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ /******************************************************************************* * FLASHC @@ -1030,6 +1030,12 @@ typedef enum { #define UDB ((UDB_Type*) UDB_BASE) /* 0x40340000 */ #define UDB_WRKONE ((UDB_WRKONE_Type*) &UDB->WRKONE) /* 0x40340000 */ #define UDB_WRKMULT ((UDB_WRKMULT_Type*) &UDB->WRKMULT) /* 0x40341000 */ +#define UDB_UDBPAIR0 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[0]) /* 0x40342000 */ +#define UDB_UDBPAIR1 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[1]) /* 0x40342200 */ +#define UDB_UDBPAIR2 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[2]) /* 0x40342400 */ +#define UDB_UDBPAIR3 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[3]) /* 0x40342600 */ +#define UDB_UDBPAIR4 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[4]) /* 0x40342800 */ +#define UDB_UDBPAIR5 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[5]) /* 0x40342A00 */ #define UDB_UDBPAIR0_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[0].UDBSNG[0]) /* 0x40342000 */ #define UDB_UDBPAIR0_UDBSNG1 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[0].UDBSNG[1]) /* 0x40342080 */ #define UDB_UDBPAIR1_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[1].UDBSNG[0]) /* 0x40342200 */ @@ -1048,12 +1054,6 @@ typedef enum { #define UDB_UDBPAIR3_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[3].ROUTE) /* 0x40342700 */ #define UDB_UDBPAIR4_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[4].ROUTE) /* 0x40342900 */ #define UDB_UDBPAIR5_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[5].ROUTE) /* 0x40342B00 */ -#define UDB_UDBPAIR0 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[0]) /* 0x40342000 */ -#define UDB_UDBPAIR1 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[1]) /* 0x40342200 */ -#define UDB_UDBPAIR2 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[2]) /* 0x40342400 */ -#define UDB_UDBPAIR3 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[3]) /* 0x40342600 */ -#define UDB_UDBPAIR4 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[4]) /* 0x40342800 */ -#define UDB_UDBPAIR5 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[5]) /* 0x40342A00 */ #define UDB_DSI0 ((UDB_DSI_Type*) &UDB->DSI[0]) /* 0x40346000 */ #define UDB_DSI1 ((UDB_DSI_Type*) &UDB->DSI[1]) /* 0x40346080 */ #define UDB_DSI2 ((UDB_DSI_Type*) &UDB->DSI[2]) /* 0x40346100 */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247fdi_d52.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247fdi_d52.h index 0fc7f8621f..d308237b4f 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247fdi_d52.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247fdi_d52.h @@ -5,11 +5,11 @@ * CY8C6247FDI-D52 device header * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -461,43 +461,19 @@ typedef enum { #define CY_FLASH_SIZE 0x00100000UL #define CY_EM_EEPROM_BASE 0x14000000UL #define CY_EM_EEPROM_SIZE 0x00008000UL -#define CY_XIP_BASE 0x18000000UL -#define CY_XIP_SIZE 0x08000000UL #define CY_SFLASH_BASE 0x16000000UL #define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL #define CY_EFUSE_BASE 0x402C0800UL #define CY_EFUSE_SIZE 0x00000200UL #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u @@ -507,9 +483,18 @@ typedef enum { #define CY_IP_MXCRYPTO 1u #define CY_IP_MXCRYPTO_INSTANCES 1u #define CY_IP_MXCRYPTO_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -525,24 +510,39 @@ typedef enum { #define CY_IP_MXS40PASS_CTB 1u #define CY_IP_MXS40PASS_CTB_INSTANCES 1u #define CY_IP_MXS40PASS_CTB_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u -#define CY_IP_MXUDB 1u -#define CY_IP_MXUDB_INSTANCES 1u -#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUDB 1u +#define CY_IP_MXUDB_INSTANCES 1u +#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_80_wlcsp.h" @@ -842,6 +842,7 @@ typedef enum { #define PROT_BASE 0x40240000UL #define PROT ((PROT_Type*) PROT_BASE) /* 0x40240000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ #define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40242000 */ #define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40242040 */ #define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40242080 */ @@ -858,23 +859,6 @@ typedef enum { #define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40242340 */ #define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40242380 */ #define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402423C0 */ -#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ -#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ -#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ -#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ -#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ -#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ -#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ -#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ -#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ -#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ -#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ -#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ -#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ -#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ -#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ -#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ -#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ #define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40244000 */ #define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40244400 */ #define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40244800 */ @@ -891,6 +875,22 @@ typedef enum { #define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40247400 */ #define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40247800 */ #define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40247C00 */ +#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ +#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ +#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ +#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ +#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ +#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ +#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ +#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ /******************************************************************************* * FLASHC @@ -1040,6 +1040,12 @@ typedef enum { #define UDB ((UDB_Type*) UDB_BASE) /* 0x40340000 */ #define UDB_WRKONE ((UDB_WRKONE_Type*) &UDB->WRKONE) /* 0x40340000 */ #define UDB_WRKMULT ((UDB_WRKMULT_Type*) &UDB->WRKMULT) /* 0x40341000 */ +#define UDB_UDBPAIR0 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[0]) /* 0x40342000 */ +#define UDB_UDBPAIR1 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[1]) /* 0x40342200 */ +#define UDB_UDBPAIR2 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[2]) /* 0x40342400 */ +#define UDB_UDBPAIR3 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[3]) /* 0x40342600 */ +#define UDB_UDBPAIR4 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[4]) /* 0x40342800 */ +#define UDB_UDBPAIR5 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[5]) /* 0x40342A00 */ #define UDB_UDBPAIR0_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[0].UDBSNG[0]) /* 0x40342000 */ #define UDB_UDBPAIR0_UDBSNG1 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[0].UDBSNG[1]) /* 0x40342080 */ #define UDB_UDBPAIR1_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[1].UDBSNG[0]) /* 0x40342200 */ @@ -1058,12 +1064,6 @@ typedef enum { #define UDB_UDBPAIR3_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[3].ROUTE) /* 0x40342700 */ #define UDB_UDBPAIR4_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[4].ROUTE) /* 0x40342900 */ #define UDB_UDBPAIR5_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[5].ROUTE) /* 0x40342B00 */ -#define UDB_UDBPAIR0 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[0]) /* 0x40342000 */ -#define UDB_UDBPAIR1 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[1]) /* 0x40342200 */ -#define UDB_UDBPAIR2 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[2]) /* 0x40342400 */ -#define UDB_UDBPAIR3 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[3]) /* 0x40342600 */ -#define UDB_UDBPAIR4 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[4]) /* 0x40342800 */ -#define UDB_UDBPAIR5 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[5]) /* 0x40342A00 */ #define UDB_DSI0 ((UDB_DSI_Type*) &UDB->DSI[0]) /* 0x40346000 */ #define UDB_DSI1 ((UDB_DSI_Type*) &UDB->DSI[1]) /* 0x40346080 */ #define UDB_DSI2 ((UDB_DSI_Type*) &UDB->DSI[2]) /* 0x40346100 */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247fti_d52.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247fti_d52.h index ee47840cbc..22929ca019 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247fti_d52.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247fti_d52.h @@ -5,11 +5,11 @@ * CY8C6247FTI-D52 device header * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -461,43 +461,19 @@ typedef enum { #define CY_FLASH_SIZE 0x00100000UL #define CY_EM_EEPROM_BASE 0x14000000UL #define CY_EM_EEPROM_SIZE 0x00008000UL -#define CY_XIP_BASE 0x18000000UL -#define CY_XIP_SIZE 0x08000000UL #define CY_SFLASH_BASE 0x16000000UL #define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL #define CY_EFUSE_BASE 0x402C0800UL #define CY_EFUSE_SIZE 0x00000200UL #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u @@ -507,9 +483,18 @@ typedef enum { #define CY_IP_MXCRYPTO 1u #define CY_IP_MXCRYPTO_INSTANCES 1u #define CY_IP_MXCRYPTO_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -525,24 +510,39 @@ typedef enum { #define CY_IP_MXS40PASS_CTB 1u #define CY_IP_MXS40PASS_CTB_INSTANCES 1u #define CY_IP_MXS40PASS_CTB_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u -#define CY_IP_MXUDB 1u -#define CY_IP_MXUDB_INSTANCES 1u -#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUDB 1u +#define CY_IP_MXUDB_INSTANCES 1u +#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_80_wlcsp.h" @@ -842,6 +842,7 @@ typedef enum { #define PROT_BASE 0x40240000UL #define PROT ((PROT_Type*) PROT_BASE) /* 0x40240000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ #define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40242000 */ #define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40242040 */ #define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40242080 */ @@ -858,23 +859,6 @@ typedef enum { #define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40242340 */ #define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40242380 */ #define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402423C0 */ -#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ -#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ -#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ -#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ -#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ -#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ -#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ -#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ -#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ -#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ -#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ -#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ -#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ -#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ -#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ -#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ -#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ #define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40244000 */ #define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40244400 */ #define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40244800 */ @@ -891,6 +875,22 @@ typedef enum { #define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40247400 */ #define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40247800 */ #define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40247C00 */ +#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ +#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ +#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ +#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ +#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ +#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ +#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ +#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ /******************************************************************************* * FLASHC @@ -1040,6 +1040,12 @@ typedef enum { #define UDB ((UDB_Type*) UDB_BASE) /* 0x40340000 */ #define UDB_WRKONE ((UDB_WRKONE_Type*) &UDB->WRKONE) /* 0x40340000 */ #define UDB_WRKMULT ((UDB_WRKMULT_Type*) &UDB->WRKMULT) /* 0x40341000 */ +#define UDB_UDBPAIR0 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[0]) /* 0x40342000 */ +#define UDB_UDBPAIR1 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[1]) /* 0x40342200 */ +#define UDB_UDBPAIR2 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[2]) /* 0x40342400 */ +#define UDB_UDBPAIR3 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[3]) /* 0x40342600 */ +#define UDB_UDBPAIR4 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[4]) /* 0x40342800 */ +#define UDB_UDBPAIR5 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[5]) /* 0x40342A00 */ #define UDB_UDBPAIR0_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[0].UDBSNG[0]) /* 0x40342000 */ #define UDB_UDBPAIR0_UDBSNG1 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[0].UDBSNG[1]) /* 0x40342080 */ #define UDB_UDBPAIR1_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[1].UDBSNG[0]) /* 0x40342200 */ @@ -1058,12 +1064,6 @@ typedef enum { #define UDB_UDBPAIR3_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[3].ROUTE) /* 0x40342700 */ #define UDB_UDBPAIR4_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[4].ROUTE) /* 0x40342900 */ #define UDB_UDBPAIR5_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[5].ROUTE) /* 0x40342B00 */ -#define UDB_UDBPAIR0 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[0]) /* 0x40342000 */ -#define UDB_UDBPAIR1 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[1]) /* 0x40342200 */ -#define UDB_UDBPAIR2 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[2]) /* 0x40342400 */ -#define UDB_UDBPAIR3 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[3]) /* 0x40342600 */ -#define UDB_UDBPAIR4 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[4]) /* 0x40342800 */ -#define UDB_UDBPAIR5 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[5]) /* 0x40342A00 */ #define UDB_DSI0 ((UDB_DSI_Type*) &UDB->DSI[0]) /* 0x40346000 */ #define UDB_DSI1 ((UDB_DSI_Type*) &UDB->DSI[1]) /* 0x40346080 */ #define UDB_DSI2 ((UDB_DSI_Type*) &UDB->DSI[2]) /* 0x40346100 */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247wi_d54.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247wi_d54.h index a2e311765c..a52d0601f2 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247wi_d54.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6247wi_d54.h @@ -5,11 +5,11 @@ * CY8C6247WI-D54 device header * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -461,43 +461,19 @@ typedef enum { #define CY_FLASH_SIZE 0x00100000UL #define CY_EM_EEPROM_BASE 0x14000000UL #define CY_EM_EEPROM_SIZE 0x00008000UL -#define CY_XIP_BASE 0x18000000UL -#define CY_XIP_SIZE 0x08000000UL #define CY_SFLASH_BASE 0x16000000UL #define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL #define CY_EFUSE_BASE 0x402C0800UL #define CY_EFUSE_SIZE 0x00000200UL #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u @@ -507,9 +483,18 @@ typedef enum { #define CY_IP_MXCRYPTO 1u #define CY_IP_MXCRYPTO_INSTANCES 1u #define CY_IP_MXCRYPTO_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -525,24 +510,39 @@ typedef enum { #define CY_IP_MXS40PASS_CTB 1u #define CY_IP_MXS40PASS_CTB_INSTANCES 1u #define CY_IP_MXS40PASS_CTB_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u -#define CY_IP_MXUDB 1u -#define CY_IP_MXUDB_INSTANCES 1u -#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUDB 1u +#define CY_IP_MXUDB_INSTANCES 1u +#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_124_bga.h" @@ -842,6 +842,7 @@ typedef enum { #define PROT_BASE 0x40240000UL #define PROT ((PROT_Type*) PROT_BASE) /* 0x40240000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ #define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40242000 */ #define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40242040 */ #define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40242080 */ @@ -858,23 +859,6 @@ typedef enum { #define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40242340 */ #define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40242380 */ #define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402423C0 */ -#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ -#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ -#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ -#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ -#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ -#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ -#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ -#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ -#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ -#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ -#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ -#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ -#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ -#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ -#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ -#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ -#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ #define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40244000 */ #define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40244400 */ #define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40244800 */ @@ -891,6 +875,22 @@ typedef enum { #define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40247400 */ #define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40247800 */ #define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40247C00 */ +#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ +#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ +#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ +#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ +#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ +#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ +#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ +#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ /******************************************************************************* * FLASHC @@ -1040,6 +1040,12 @@ typedef enum { #define UDB ((UDB_Type*) UDB_BASE) /* 0x40340000 */ #define UDB_WRKONE ((UDB_WRKONE_Type*) &UDB->WRKONE) /* 0x40340000 */ #define UDB_WRKMULT ((UDB_WRKMULT_Type*) &UDB->WRKMULT) /* 0x40341000 */ +#define UDB_UDBPAIR0 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[0]) /* 0x40342000 */ +#define UDB_UDBPAIR1 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[1]) /* 0x40342200 */ +#define UDB_UDBPAIR2 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[2]) /* 0x40342400 */ +#define UDB_UDBPAIR3 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[3]) /* 0x40342600 */ +#define UDB_UDBPAIR4 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[4]) /* 0x40342800 */ +#define UDB_UDBPAIR5 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[5]) /* 0x40342A00 */ #define UDB_UDBPAIR0_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[0].UDBSNG[0]) /* 0x40342000 */ #define UDB_UDBPAIR0_UDBSNG1 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[0].UDBSNG[1]) /* 0x40342080 */ #define UDB_UDBPAIR1_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[1].UDBSNG[0]) /* 0x40342200 */ @@ -1058,12 +1064,6 @@ typedef enum { #define UDB_UDBPAIR3_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[3].ROUTE) /* 0x40342700 */ #define UDB_UDBPAIR4_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[4].ROUTE) /* 0x40342900 */ #define UDB_UDBPAIR5_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[5].ROUTE) /* 0x40342B00 */ -#define UDB_UDBPAIR0 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[0]) /* 0x40342000 */ -#define UDB_UDBPAIR1 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[1]) /* 0x40342200 */ -#define UDB_UDBPAIR2 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[2]) /* 0x40342400 */ -#define UDB_UDBPAIR3 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[3]) /* 0x40342600 */ -#define UDB_UDBPAIR4 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[4]) /* 0x40342800 */ -#define UDB_UDBPAIR5 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[5]) /* 0x40342A00 */ #define UDB_DSI0 ((UDB_DSI_Type*) &UDB->DSI[0]) /* 0x40346000 */ #define UDB_DSI1 ((UDB_DSI_Type*) &UDB->DSI[1]) /* 0x40346080 */ #define UDB_DSI2 ((UDB_DSI_Type*) &UDB->DSI[2]) /* 0x40346100 */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6248azi_d14.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6248azi_d14.h index 8e9736de39..d6aafca4bf 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6248azi_d14.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6248azi_d14.h @@ -5,11 +5,11 @@ * CY8C6248AZI-D14 device header * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -488,43 +488,19 @@ typedef enum { #define CY_FLASH_SIZE 0x00200000UL #define CY_EM_EEPROM_BASE 0x14000000UL #define CY_EM_EEPROM_SIZE 0x00008000UL -#define CY_XIP_BASE 0x18000000UL -#define CY_XIP_SIZE 0x08000000UL #define CY_SFLASH_BASE 0x16000000UL #define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL #define CY_EFUSE_BASE 0x402C0800UL #define CY_EFUSE_SIZE 0x00000200UL #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 13u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 2u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 2u +#define CY_IP_MXAUDIOSS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 2u @@ -534,36 +510,60 @@ typedef enum { #define CY_IP_M4CPUSS_DMA 1u #define CY_IP_M4CPUSS_DMA_INSTANCES 2u #define CY_IP_M4CPUSS_DMA_VERSION 2u -#define CY_IP_MXSDHC 1u -#define CY_IP_MXSDHC_INSTANCES 2u -#define CY_IP_MXSDHC_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 2u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u #define CY_IP_MXS40PASS 1u #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u #define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 2u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 13u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 2u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_02_config.h" #include "gpio_psoc6_02_128_tqfp.h" @@ -918,6 +918,7 @@ typedef enum { #define PROT_BASE 0x40230000UL #define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ #define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ #define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ #define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ @@ -934,7 +935,22 @@ typedef enum { #define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ #define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ #define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ -#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ #define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ #define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ #define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ @@ -959,22 +975,6 @@ typedef enum { #define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ #define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ #define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ -#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ -#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ -#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ -#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ -#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ -#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ -#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ -#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ -#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ -#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ -#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ -#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ -#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ -#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ -#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ -#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ /******************************************************************************* * FLASHC diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6248azi_d44.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6248azi_d44.h index 10115dc54c..71d6c3cff0 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6248azi_d44.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6248azi_d44.h @@ -5,11 +5,11 @@ * CY8C6248AZI-D44 device header * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -488,43 +488,19 @@ typedef enum { #define CY_FLASH_SIZE 0x00100000UL #define CY_EM_EEPROM_BASE 0x14000000UL #define CY_EM_EEPROM_SIZE 0x00008000UL -#define CY_XIP_BASE 0x18000000UL -#define CY_XIP_SIZE 0x08000000UL #define CY_SFLASH_BASE 0x16000000UL #define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL #define CY_EFUSE_BASE 0x402C0800UL #define CY_EFUSE_SIZE 0x00000200UL #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 13u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 2u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 2u +#define CY_IP_MXAUDIOSS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 2u @@ -537,36 +513,60 @@ typedef enum { #define CY_IP_MXCRYPTO 1u #define CY_IP_MXCRYPTO_INSTANCES 1u #define CY_IP_MXCRYPTO_VERSION 2u -#define CY_IP_MXSDHC 1u -#define CY_IP_MXSDHC_INSTANCES 2u -#define CY_IP_MXSDHC_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 2u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u #define CY_IP_MXS40PASS 1u #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u #define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 2u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 13u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 2u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_02_config.h" #include "gpio_psoc6_02_128_tqfp.h" @@ -928,6 +928,7 @@ typedef enum { #define PROT_BASE 0x40230000UL #define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ #define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ #define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ #define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ @@ -944,7 +945,22 @@ typedef enum { #define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ #define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ #define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ -#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ #define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ #define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ #define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ @@ -969,22 +985,6 @@ typedef enum { #define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ #define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ #define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ -#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ -#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ -#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ -#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ -#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ -#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ -#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ -#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ -#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ -#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ -#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ -#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ -#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ -#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ -#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ -#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ /******************************************************************************* * FLASHC diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6248azi_s2d14.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6248azi_s2d14.h index 94c1be1eb6..b72e5e696c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6248azi_s2d14.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6248azi_s2d14.h @@ -5,11 +5,11 @@ * CY8C6248AZI-S2D14 device header * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -488,43 +488,19 @@ typedef enum { #define CY_FLASH_SIZE 0x00200000UL #define CY_EM_EEPROM_BASE 0x14000000UL #define CY_EM_EEPROM_SIZE 0x00008000UL -#define CY_XIP_BASE 0x18000000UL -#define CY_XIP_SIZE 0x08000000UL #define CY_SFLASH_BASE 0x16000000UL #define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL #define CY_EFUSE_BASE 0x402C0800UL #define CY_EFUSE_SIZE 0x00000200UL #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 13u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 2u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 2u +#define CY_IP_MXAUDIOSS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 2u @@ -534,42 +510,66 @@ typedef enum { #define CY_IP_M4CPUSS_DMA 1u #define CY_IP_M4CPUSS_DMA_INSTANCES 2u #define CY_IP_M4CPUSS_DMA_VERSION 2u -#define CY_IP_MXSDHC 1u -#define CY_IP_MXSDHC_INSTANCES 2u -#define CY_IP_MXSDHC_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 2u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u #define CY_IP_MXS40PASS 1u #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u #define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 2u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 13u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 2u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_02_config.h" #include "gpio_psoc6_02_128_tqfp.h" #define CY_DEVICE_PSOC6A2M -#define CY_SILICON_ID 0xE4561102UL +#define CY_SILICON_ID 0xE4561202UL #define CY_HF_CLK_MAX_FREQ 150000000UL #define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL @@ -918,6 +918,7 @@ typedef enum { #define PROT_BASE 0x40230000UL #define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ #define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ #define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ #define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ @@ -934,7 +935,22 @@ typedef enum { #define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ #define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ #define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ -#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ #define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ #define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ #define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ @@ -959,22 +975,6 @@ typedef enum { #define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ #define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ #define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ -#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ -#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ -#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ -#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ -#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ -#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ -#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ -#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ -#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ -#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ -#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ -#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ -#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ -#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ -#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ -#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ /******************************************************************************* * FLASHC diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6248azi_s2d44.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6248azi_s2d44.h index 4a93e33602..40b3f817d7 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6248azi_s2d44.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6248azi_s2d44.h @@ -5,11 +5,11 @@ * CY8C6248AZI-S2D44 device header * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -488,43 +488,19 @@ typedef enum { #define CY_FLASH_SIZE 0x00100000UL #define CY_EM_EEPROM_BASE 0x14000000UL #define CY_EM_EEPROM_SIZE 0x00008000UL -#define CY_XIP_BASE 0x18000000UL -#define CY_XIP_SIZE 0x08000000UL #define CY_SFLASH_BASE 0x16000000UL #define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL #define CY_EFUSE_BASE 0x402C0800UL #define CY_EFUSE_SIZE 0x00000200UL #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 13u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 2u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 2u +#define CY_IP_MXAUDIOSS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 2u @@ -537,42 +513,66 @@ typedef enum { #define CY_IP_MXCRYPTO 1u #define CY_IP_MXCRYPTO_INSTANCES 1u #define CY_IP_MXCRYPTO_VERSION 2u -#define CY_IP_MXSDHC 1u -#define CY_IP_MXSDHC_INSTANCES 2u -#define CY_IP_MXSDHC_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 2u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u #define CY_IP_MXS40PASS 1u #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u #define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 2u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 13u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 2u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_02_config.h" #include "gpio_psoc6_02_128_tqfp.h" #define CY_DEVICE_PSOC6A2M -#define CY_SILICON_ID 0xE4581102UL +#define CY_SILICON_ID 0xE4581202UL #define CY_HF_CLK_MAX_FREQ 150000000UL #define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL @@ -928,6 +928,7 @@ typedef enum { #define PROT_BASE 0x40230000UL #define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ #define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ #define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ #define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ @@ -944,7 +945,22 @@ typedef enum { #define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ #define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ #define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ -#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ #define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ #define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ #define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ @@ -969,22 +985,6 @@ typedef enum { #define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ #define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ #define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ -#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ -#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ -#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ -#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ -#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ -#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ -#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ -#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ -#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ -#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ -#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ -#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ -#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ -#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ -#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ -#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ /******************************************************************************* * FLASHC diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6248bzi_d44.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6248bzi_d44.h index da54f237e4..bb3c195fb4 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6248bzi_d44.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6248bzi_d44.h @@ -5,11 +5,11 @@ * CY8C6248BZI-D44 device header * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -488,43 +488,19 @@ typedef enum { #define CY_FLASH_SIZE 0x00100000UL #define CY_EM_EEPROM_BASE 0x14000000UL #define CY_EM_EEPROM_SIZE 0x00008000UL -#define CY_XIP_BASE 0x18000000UL -#define CY_XIP_SIZE 0x08000000UL #define CY_SFLASH_BASE 0x16000000UL #define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL #define CY_EFUSE_BASE 0x402C0800UL #define CY_EFUSE_SIZE 0x00000200UL #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 13u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 2u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 2u +#define CY_IP_MXAUDIOSS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 2u @@ -537,36 +513,60 @@ typedef enum { #define CY_IP_MXCRYPTO 1u #define CY_IP_MXCRYPTO_INSTANCES 1u #define CY_IP_MXCRYPTO_VERSION 2u -#define CY_IP_MXSDHC 1u -#define CY_IP_MXSDHC_INSTANCES 2u -#define CY_IP_MXSDHC_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 2u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u #define CY_IP_MXS40PASS 1u #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u #define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 2u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 13u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 2u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_02_config.h" #include "gpio_psoc6_02_124_bga.h" @@ -928,6 +928,7 @@ typedef enum { #define PROT_BASE 0x40230000UL #define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ #define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ #define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ #define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ @@ -944,7 +945,22 @@ typedef enum { #define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ #define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ #define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ -#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ #define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ #define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ #define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ @@ -969,22 +985,6 @@ typedef enum { #define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ #define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ #define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ -#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ -#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ -#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ -#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ -#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ -#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ -#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ -#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ -#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ -#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ -#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ -#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ -#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ -#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ -#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ -#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ /******************************************************************************* * FLASHC diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6248bzi_s2d44.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6248bzi_s2d44.h index 69c0ac33fc..421cd7744d 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6248bzi_s2d44.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6248bzi_s2d44.h @@ -5,11 +5,11 @@ * CY8C6248BZI-S2D44 device header * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -488,43 +488,19 @@ typedef enum { #define CY_FLASH_SIZE 0x00100000UL #define CY_EM_EEPROM_BASE 0x14000000UL #define CY_EM_EEPROM_SIZE 0x00008000UL -#define CY_XIP_BASE 0x18000000UL -#define CY_XIP_SIZE 0x08000000UL #define CY_SFLASH_BASE 0x16000000UL #define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL #define CY_EFUSE_BASE 0x402C0800UL #define CY_EFUSE_SIZE 0x00000200UL #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 13u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 2u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 2u +#define CY_IP_MXAUDIOSS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 2u @@ -537,42 +513,66 @@ typedef enum { #define CY_IP_MXCRYPTO 1u #define CY_IP_MXCRYPTO_INSTANCES 1u #define CY_IP_MXCRYPTO_VERSION 2u -#define CY_IP_MXSDHC 1u -#define CY_IP_MXSDHC_INSTANCES 2u -#define CY_IP_MXSDHC_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 2u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u #define CY_IP_MXS40PASS 1u #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u #define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 2u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 13u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 2u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_02_config.h" #include "gpio_psoc6_02_124_bga.h" #define CY_DEVICE_PSOC6A2M -#define CY_SILICON_ID 0xE4571102UL +#define CY_SILICON_ID 0xE4571202UL #define CY_HF_CLK_MAX_FREQ 150000000UL #define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL @@ -928,6 +928,7 @@ typedef enum { #define PROT_BASE 0x40230000UL #define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ #define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ #define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ #define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ @@ -944,7 +945,22 @@ typedef enum { #define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ #define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ #define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ -#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ #define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ #define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ #define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ @@ -969,22 +985,6 @@ typedef enum { #define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ #define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ #define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ -#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ -#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ -#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ -#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ -#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ -#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ -#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ -#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ -#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ -#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ -#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ -#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ -#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ -#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ -#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ -#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ /******************************************************************************* * FLASHC diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6248fni_d43.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6248fni_d43.h index f0a322ac69..ce704005de 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6248fni_d43.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6248fni_d43.h @@ -5,11 +5,11 @@ * CY8C6248FNI-D43 device header * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -488,43 +488,19 @@ typedef enum { #define CY_FLASH_SIZE 0x00100000UL #define CY_EM_EEPROM_BASE 0x14000000UL #define CY_EM_EEPROM_SIZE 0x00008000UL -#define CY_XIP_BASE 0x18000000UL -#define CY_XIP_SIZE 0x08000000UL #define CY_SFLASH_BASE 0x16000000UL #define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL #define CY_EFUSE_BASE 0x402C0800UL #define CY_EFUSE_SIZE 0x00000200UL #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 13u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 2u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 2u +#define CY_IP_MXAUDIOSS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 2u @@ -537,36 +513,60 @@ typedef enum { #define CY_IP_MXCRYPTO 1u #define CY_IP_MXCRYPTO_INSTANCES 1u #define CY_IP_MXCRYPTO_VERSION 2u -#define CY_IP_MXSDHC 1u -#define CY_IP_MXSDHC_INSTANCES 2u -#define CY_IP_MXSDHC_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 2u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u #define CY_IP_MXS40PASS 1u #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u #define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 2u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 13u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 2u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_02_config.h" #include "gpio_psoc6_02_100_wlcsp.h" @@ -928,6 +928,7 @@ typedef enum { #define PROT_BASE 0x40230000UL #define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ #define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ #define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ #define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ @@ -944,7 +945,22 @@ typedef enum { #define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ #define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ #define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ -#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ #define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ #define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ #define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ @@ -969,22 +985,6 @@ typedef enum { #define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ #define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ #define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ -#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ -#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ -#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ -#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ -#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ -#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ -#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ -#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ -#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ -#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ -#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ -#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ -#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ -#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ -#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ -#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ /******************************************************************************* * FLASHC diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6248fni_s2d43.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6248fni_s2d43.h index 30eea14a25..688f8994e6 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6248fni_s2d43.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6248fni_s2d43.h @@ -5,11 +5,11 @@ * CY8C6248FNI-S2D43 device header * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -488,43 +488,19 @@ typedef enum { #define CY_FLASH_SIZE 0x00100000UL #define CY_EM_EEPROM_BASE 0x14000000UL #define CY_EM_EEPROM_SIZE 0x00008000UL -#define CY_XIP_BASE 0x18000000UL -#define CY_XIP_SIZE 0x08000000UL #define CY_SFLASH_BASE 0x16000000UL #define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL #define CY_EFUSE_BASE 0x402C0800UL #define CY_EFUSE_SIZE 0x00000200UL #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 13u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 2u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 2u +#define CY_IP_MXAUDIOSS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 2u @@ -537,42 +513,66 @@ typedef enum { #define CY_IP_MXCRYPTO 1u #define CY_IP_MXCRYPTO_INSTANCES 1u #define CY_IP_MXCRYPTO_VERSION 2u -#define CY_IP_MXSDHC 1u -#define CY_IP_MXSDHC_INSTANCES 2u -#define CY_IP_MXSDHC_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 2u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u #define CY_IP_MXS40PASS 1u #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u #define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 2u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 13u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 2u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_02_config.h" #include "gpio_psoc6_02_100_wlcsp.h" #define CY_DEVICE_PSOC6A2M -#define CY_SILICON_ID 0xE4591102UL +#define CY_SILICON_ID 0xE4591202UL #define CY_HF_CLK_MAX_FREQ 150000000UL #define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL @@ -928,6 +928,7 @@ typedef enum { #define PROT_BASE 0x40230000UL #define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ #define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ #define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ #define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ @@ -944,7 +945,22 @@ typedef enum { #define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ #define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ #define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ -#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ #define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ #define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ #define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ @@ -969,22 +985,6 @@ typedef enum { #define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ #define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ #define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ -#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ -#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ -#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ -#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ -#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ -#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ -#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ -#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ -#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ -#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ -#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ -#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ -#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ -#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ -#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ -#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ /******************************************************************************* * FLASHC diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624aazi_d14.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624aazi_d14.h index 9db65ee0f6..ee783fc545 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624aazi_d14.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624aazi_d14.h @@ -5,11 +5,11 @@ * CY8C624AAZI-D14 device header * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -488,43 +488,19 @@ typedef enum { #define CY_FLASH_SIZE 0x00200000UL #define CY_EM_EEPROM_BASE 0x14000000UL #define CY_EM_EEPROM_SIZE 0x00008000UL -#define CY_XIP_BASE 0x18000000UL -#define CY_XIP_SIZE 0x08000000UL #define CY_SFLASH_BASE 0x16000000UL #define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL #define CY_EFUSE_BASE 0x402C0800UL #define CY_EFUSE_SIZE 0x00000200UL #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 13u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 2u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 2u +#define CY_IP_MXAUDIOSS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 2u @@ -534,36 +510,60 @@ typedef enum { #define CY_IP_M4CPUSS_DMA 1u #define CY_IP_M4CPUSS_DMA_INSTANCES 2u #define CY_IP_M4CPUSS_DMA_VERSION 2u -#define CY_IP_MXSDHC 1u -#define CY_IP_MXSDHC_INSTANCES 2u -#define CY_IP_MXSDHC_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 2u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u #define CY_IP_MXS40PASS 1u #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u #define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 2u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 13u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 2u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_02_config.h" #include "gpio_psoc6_02_128_tqfp.h" @@ -918,6 +918,7 @@ typedef enum { #define PROT_BASE 0x40230000UL #define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ #define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ #define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ #define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ @@ -934,7 +935,22 @@ typedef enum { #define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ #define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ #define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ -#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ #define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ #define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ #define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ @@ -959,22 +975,6 @@ typedef enum { #define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ #define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ #define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ -#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ -#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ -#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ -#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ -#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ -#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ -#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ -#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ -#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ -#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ -#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ -#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ -#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ -#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ -#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ -#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ /******************************************************************************* * FLASHC diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624aazi_d44.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624aazi_d44.h index 7e46decfc1..926bcf4555 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624aazi_d44.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624aazi_d44.h @@ -5,11 +5,11 @@ * CY8C624AAZI-D44 device header * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -488,43 +488,19 @@ typedef enum { #define CY_FLASH_SIZE 0x00200000UL #define CY_EM_EEPROM_BASE 0x14000000UL #define CY_EM_EEPROM_SIZE 0x00008000UL -#define CY_XIP_BASE 0x18000000UL -#define CY_XIP_SIZE 0x08000000UL #define CY_SFLASH_BASE 0x16000000UL #define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL #define CY_EFUSE_BASE 0x402C0800UL #define CY_EFUSE_SIZE 0x00000200UL #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 13u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 2u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 2u +#define CY_IP_MXAUDIOSS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 2u @@ -537,36 +513,60 @@ typedef enum { #define CY_IP_MXCRYPTO 1u #define CY_IP_MXCRYPTO_INSTANCES 1u #define CY_IP_MXCRYPTO_VERSION 2u -#define CY_IP_MXSDHC 1u -#define CY_IP_MXSDHC_INSTANCES 2u -#define CY_IP_MXSDHC_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 2u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u #define CY_IP_MXS40PASS 1u #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u #define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 2u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 13u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 2u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_02_config.h" #include "gpio_psoc6_02_128_tqfp.h" @@ -928,6 +928,7 @@ typedef enum { #define PROT_BASE 0x40230000UL #define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ #define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ #define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ #define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ @@ -944,7 +945,22 @@ typedef enum { #define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ #define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ #define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ -#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ #define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ #define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ #define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ @@ -969,22 +985,6 @@ typedef enum { #define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ #define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ #define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ -#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ -#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ -#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ -#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ -#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ -#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ -#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ -#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ -#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ -#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ -#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ -#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ -#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ -#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ -#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ -#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ /******************************************************************************* * FLASHC diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624aazi_s2d14.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624aazi_s2d14.h index d1a42737c5..ed24eabf17 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624aazi_s2d14.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624aazi_s2d14.h @@ -5,11 +5,11 @@ * CY8C624AAZI-S2D14 device header * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -488,43 +488,19 @@ typedef enum { #define CY_FLASH_SIZE 0x00200000UL #define CY_EM_EEPROM_BASE 0x14000000UL #define CY_EM_EEPROM_SIZE 0x00008000UL -#define CY_XIP_BASE 0x18000000UL -#define CY_XIP_SIZE 0x08000000UL #define CY_SFLASH_BASE 0x16000000UL #define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL #define CY_EFUSE_BASE 0x402C0800UL #define CY_EFUSE_SIZE 0x00000200UL #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 13u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 2u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 2u +#define CY_IP_MXAUDIOSS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 2u @@ -534,42 +510,66 @@ typedef enum { #define CY_IP_M4CPUSS_DMA 1u #define CY_IP_M4CPUSS_DMA_INSTANCES 2u #define CY_IP_M4CPUSS_DMA_VERSION 2u -#define CY_IP_MXSDHC 1u -#define CY_IP_MXSDHC_INSTANCES 2u -#define CY_IP_MXSDHC_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 2u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u #define CY_IP_MXS40PASS 1u #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u #define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 2u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 13u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 2u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_02_config.h" #include "gpio_psoc6_02_128_tqfp.h" #define CY_DEVICE_PSOC6A2M -#define CY_SILICON_ID 0xE4521102UL +#define CY_SILICON_ID 0xE4521202UL #define CY_HF_CLK_MAX_FREQ 150000000UL #define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL @@ -918,6 +918,7 @@ typedef enum { #define PROT_BASE 0x40230000UL #define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ #define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ #define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ #define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ @@ -934,7 +935,22 @@ typedef enum { #define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ #define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ #define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ -#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ #define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ #define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ #define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ @@ -959,22 +975,6 @@ typedef enum { #define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ #define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ #define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ -#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ -#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ -#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ -#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ -#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ -#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ -#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ -#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ -#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ -#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ -#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ -#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ -#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ -#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ -#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ -#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ /******************************************************************************* * FLASHC diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624aazi_s2d44.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624aazi_s2d44.h index 1e2ab95806..d2684e625e 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624aazi_s2d44.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624aazi_s2d44.h @@ -5,11 +5,11 @@ * CY8C624AAZI-S2D44 device header * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -488,43 +488,19 @@ typedef enum { #define CY_FLASH_SIZE 0x00200000UL #define CY_EM_EEPROM_BASE 0x14000000UL #define CY_EM_EEPROM_SIZE 0x00008000UL -#define CY_XIP_BASE 0x18000000UL -#define CY_XIP_SIZE 0x08000000UL #define CY_SFLASH_BASE 0x16000000UL #define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL #define CY_EFUSE_BASE 0x402C0800UL #define CY_EFUSE_SIZE 0x00000200UL #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 13u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 2u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 2u +#define CY_IP_MXAUDIOSS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 2u @@ -537,42 +513,66 @@ typedef enum { #define CY_IP_MXCRYPTO 1u #define CY_IP_MXCRYPTO_INSTANCES 1u #define CY_IP_MXCRYPTO_VERSION 2u -#define CY_IP_MXSDHC 1u -#define CY_IP_MXSDHC_INSTANCES 2u -#define CY_IP_MXSDHC_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 2u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u #define CY_IP_MXS40PASS 1u #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u #define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 2u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 13u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 2u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_02_config.h" #include "gpio_psoc6_02_128_tqfp.h" #define CY_DEVICE_PSOC6A2M -#define CY_SILICON_ID 0xE4541102UL +#define CY_SILICON_ID 0xE4541202UL #define CY_HF_CLK_MAX_FREQ 150000000UL #define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL @@ -928,6 +928,7 @@ typedef enum { #define PROT_BASE 0x40230000UL #define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ #define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ #define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ #define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ @@ -944,7 +945,22 @@ typedef enum { #define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ #define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ #define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ -#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ #define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ #define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ #define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ @@ -969,22 +985,6 @@ typedef enum { #define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ #define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ #define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ -#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ -#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ -#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ -#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ -#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ -#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ -#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ -#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ -#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ -#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ -#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ -#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ -#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ -#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ -#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ -#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ /******************************************************************************* * FLASHC diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624abzi_d04.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624abzi_d04.h index 129c371a69..1651e60577 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624abzi_d04.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624abzi_d04.h @@ -5,11 +5,11 @@ * CY8C624ABZI-D04 device header * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -488,43 +488,19 @@ typedef enum { #define CY_FLASH_SIZE 0x00200000UL #define CY_EM_EEPROM_BASE 0x14000000UL #define CY_EM_EEPROM_SIZE 0x00008000UL -#define CY_XIP_BASE 0x18000000UL -#define CY_XIP_SIZE 0x08000000UL #define CY_SFLASH_BASE 0x16000000UL #define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL #define CY_EFUSE_BASE 0x402C0800UL #define CY_EFUSE_SIZE 0x00000200UL #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 13u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 2u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 2u +#define CY_IP_MXAUDIOSS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 2u @@ -534,36 +510,60 @@ typedef enum { #define CY_IP_M4CPUSS_DMA 1u #define CY_IP_M4CPUSS_DMA_INSTANCES 2u #define CY_IP_M4CPUSS_DMA_VERSION 2u -#define CY_IP_MXSDHC 1u -#define CY_IP_MXSDHC_INSTANCES 2u -#define CY_IP_MXSDHC_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 2u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u #define CY_IP_MXS40PASS 1u #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u #define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 2u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 13u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 2u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_02_config.h" #include "gpio_psoc6_02_124_bga.h" @@ -918,6 +918,7 @@ typedef enum { #define PROT_BASE 0x40230000UL #define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ #define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ #define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ #define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ @@ -934,7 +935,22 @@ typedef enum { #define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ #define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ #define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ -#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ #define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ #define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ #define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ @@ -959,22 +975,6 @@ typedef enum { #define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ #define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ #define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ -#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ -#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ -#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ -#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ -#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ -#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ -#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ -#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ -#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ -#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ -#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ -#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ -#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ -#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ -#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ -#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ /******************************************************************************* * FLASHC diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624abzi_d14.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624abzi_d14.h index 03c890e42e..e23536f87b 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624abzi_d14.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624abzi_d14.h @@ -5,11 +5,11 @@ * CY8C624ABZI-D14 device header * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -488,43 +488,19 @@ typedef enum { #define CY_FLASH_SIZE 0x00200000UL #define CY_EM_EEPROM_BASE 0x14000000UL #define CY_EM_EEPROM_SIZE 0x00008000UL -#define CY_XIP_BASE 0x18000000UL -#define CY_XIP_SIZE 0x08000000UL #define CY_SFLASH_BASE 0x16000000UL #define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL #define CY_EFUSE_BASE 0x402C0800UL #define CY_EFUSE_SIZE 0x00000200UL #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 13u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 2u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 2u +#define CY_IP_MXAUDIOSS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 2u @@ -534,36 +510,60 @@ typedef enum { #define CY_IP_M4CPUSS_DMA 1u #define CY_IP_M4CPUSS_DMA_INSTANCES 2u #define CY_IP_M4CPUSS_DMA_VERSION 2u -#define CY_IP_MXSDHC 1u -#define CY_IP_MXSDHC_INSTANCES 2u -#define CY_IP_MXSDHC_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 2u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u #define CY_IP_MXS40PASS 1u #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u #define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 2u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 13u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 2u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_02_config.h" #include "gpio_psoc6_02_124_bga.h" @@ -918,6 +918,7 @@ typedef enum { #define PROT_BASE 0x40230000UL #define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ #define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ #define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ #define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ @@ -934,7 +935,22 @@ typedef enum { #define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ #define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ #define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ -#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ #define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ #define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ #define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ @@ -959,22 +975,6 @@ typedef enum { #define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ #define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ #define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ -#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ -#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ -#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ -#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ -#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ -#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ -#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ -#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ -#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ -#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ -#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ -#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ -#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ -#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ -#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ -#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ /******************************************************************************* * FLASHC diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624abzi_d44.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624abzi_d44.h index 0876e2b346..62713cee3e 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624abzi_d44.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624abzi_d44.h @@ -5,11 +5,11 @@ * CY8C624ABZI-D44 device header * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -488,43 +488,19 @@ typedef enum { #define CY_FLASH_SIZE 0x00200000UL #define CY_EM_EEPROM_BASE 0x14000000UL #define CY_EM_EEPROM_SIZE 0x00008000UL -#define CY_XIP_BASE 0x18000000UL -#define CY_XIP_SIZE 0x08000000UL #define CY_SFLASH_BASE 0x16000000UL #define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL #define CY_EFUSE_BASE 0x402C0800UL #define CY_EFUSE_SIZE 0x00000200UL #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 13u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 2u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 2u +#define CY_IP_MXAUDIOSS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 2u @@ -537,36 +513,60 @@ typedef enum { #define CY_IP_MXCRYPTO 1u #define CY_IP_MXCRYPTO_INSTANCES 1u #define CY_IP_MXCRYPTO_VERSION 2u -#define CY_IP_MXSDHC 1u -#define CY_IP_MXSDHC_INSTANCES 2u -#define CY_IP_MXSDHC_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 2u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u #define CY_IP_MXS40PASS 1u #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u #define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 2u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 13u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 2u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_02_config.h" #include "gpio_psoc6_02_124_bga.h" @@ -928,6 +928,7 @@ typedef enum { #define PROT_BASE 0x40230000UL #define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ #define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ #define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ #define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ @@ -944,7 +945,22 @@ typedef enum { #define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ #define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ #define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ -#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ #define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ #define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ #define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ @@ -969,22 +985,6 @@ typedef enum { #define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ #define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ #define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ -#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ -#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ -#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ -#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ -#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ -#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ -#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ -#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ -#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ -#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ -#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ -#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ -#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ -#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ -#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ -#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ /******************************************************************************* * FLASHC diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624abzi_s2d04.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624abzi_s2d04.h index 111352ba95..0a747caccb 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624abzi_s2d04.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624abzi_s2d04.h @@ -5,11 +5,11 @@ * CY8C624ABZI-S2D04 device header * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -488,43 +488,19 @@ typedef enum { #define CY_FLASH_SIZE 0x00200000UL #define CY_EM_EEPROM_BASE 0x14000000UL #define CY_EM_EEPROM_SIZE 0x00008000UL -#define CY_XIP_BASE 0x18000000UL -#define CY_XIP_SIZE 0x08000000UL #define CY_SFLASH_BASE 0x16000000UL #define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL #define CY_EFUSE_BASE 0x402C0800UL #define CY_EFUSE_SIZE 0x00000200UL #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 13u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 2u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 2u +#define CY_IP_MXAUDIOSS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 2u @@ -534,42 +510,66 @@ typedef enum { #define CY_IP_M4CPUSS_DMA 1u #define CY_IP_M4CPUSS_DMA_INSTANCES 2u #define CY_IP_M4CPUSS_DMA_VERSION 2u -#define CY_IP_MXSDHC 1u -#define CY_IP_MXSDHC_INSTANCES 2u -#define CY_IP_MXSDHC_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 2u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u #define CY_IP_MXS40PASS 1u #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u #define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 2u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 13u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 2u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_02_config.h" #include "gpio_psoc6_02_124_bga.h" #define CY_DEVICE_PSOC6A2M -#define CY_SILICON_ID 0xE4501102UL +#define CY_SILICON_ID 0xE4501202UL #define CY_HF_CLK_MAX_FREQ 150000000UL #define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL @@ -918,6 +918,7 @@ typedef enum { #define PROT_BASE 0x40230000UL #define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ #define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ #define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ #define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ @@ -934,7 +935,22 @@ typedef enum { #define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ #define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ #define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ -#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ #define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ #define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ #define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ @@ -959,22 +975,6 @@ typedef enum { #define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ #define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ #define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ -#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ -#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ -#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ -#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ -#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ -#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ -#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ -#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ -#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ -#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ -#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ -#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ -#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ -#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ -#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ -#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ /******************************************************************************* * FLASHC diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624abzi_s2d14.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624abzi_s2d14.h index 192ac5b312..305f7d2391 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624abzi_s2d14.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624abzi_s2d14.h @@ -5,11 +5,11 @@ * CY8C624ABZI-S2D14 device header * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -488,43 +488,19 @@ typedef enum { #define CY_FLASH_SIZE 0x00200000UL #define CY_EM_EEPROM_BASE 0x14000000UL #define CY_EM_EEPROM_SIZE 0x00008000UL -#define CY_XIP_BASE 0x18000000UL -#define CY_XIP_SIZE 0x08000000UL #define CY_SFLASH_BASE 0x16000000UL #define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL #define CY_EFUSE_BASE 0x402C0800UL #define CY_EFUSE_SIZE 0x00000200UL #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 13u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 2u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 2u +#define CY_IP_MXAUDIOSS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 2u @@ -534,42 +510,66 @@ typedef enum { #define CY_IP_M4CPUSS_DMA 1u #define CY_IP_M4CPUSS_DMA_INSTANCES 2u #define CY_IP_M4CPUSS_DMA_VERSION 2u -#define CY_IP_MXSDHC 1u -#define CY_IP_MXSDHC_INSTANCES 2u -#define CY_IP_MXSDHC_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 2u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u #define CY_IP_MXS40PASS 1u #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u #define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 2u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 13u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 2u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_02_config.h" #include "gpio_psoc6_02_124_bga.h" #define CY_DEVICE_PSOC6A2M -#define CY_SILICON_ID 0xE4511102UL +#define CY_SILICON_ID 0xE4511202UL #define CY_HF_CLK_MAX_FREQ 150000000UL #define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL @@ -918,6 +918,7 @@ typedef enum { #define PROT_BASE 0x40230000UL #define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ #define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ #define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ #define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ @@ -934,7 +935,22 @@ typedef enum { #define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ #define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ #define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ -#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ #define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ #define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ #define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ @@ -959,22 +975,6 @@ typedef enum { #define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ #define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ #define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ -#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ -#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ -#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ -#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ -#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ -#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ -#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ -#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ -#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ -#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ -#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ -#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ -#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ -#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ -#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ -#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ /******************************************************************************* * FLASHC diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624abzi_s2d44.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624abzi_s2d44.h index 4bf85a11b2..c30199f639 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624abzi_s2d44.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624abzi_s2d44.h @@ -5,11 +5,11 @@ * CY8C624ABZI-S2D44 device header * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -488,43 +488,19 @@ typedef enum { #define CY_FLASH_SIZE 0x00200000UL #define CY_EM_EEPROM_BASE 0x14000000UL #define CY_EM_EEPROM_SIZE 0x00008000UL -#define CY_XIP_BASE 0x18000000UL -#define CY_XIP_SIZE 0x08000000UL #define CY_SFLASH_BASE 0x16000000UL #define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL #define CY_EFUSE_BASE 0x402C0800UL #define CY_EFUSE_SIZE 0x00000200UL #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 13u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 2u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 2u +#define CY_IP_MXAUDIOSS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 2u @@ -537,42 +513,66 @@ typedef enum { #define CY_IP_MXCRYPTO 1u #define CY_IP_MXCRYPTO_INSTANCES 1u #define CY_IP_MXCRYPTO_VERSION 2u -#define CY_IP_MXSDHC 1u -#define CY_IP_MXSDHC_INSTANCES 2u -#define CY_IP_MXSDHC_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 2u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u #define CY_IP_MXS40PASS 1u #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u #define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 2u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 13u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 2u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_02_config.h" #include "gpio_psoc6_02_124_bga.h" #define CY_DEVICE_PSOC6A2M -#define CY_SILICON_ID 0xE4531102UL +#define CY_SILICON_ID 0xE4531202UL #define CY_HF_CLK_MAX_FREQ 150000000UL #define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL @@ -928,6 +928,7 @@ typedef enum { #define PROT_BASE 0x40230000UL #define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ #define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ #define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ #define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ @@ -944,7 +945,22 @@ typedef enum { #define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ #define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ #define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ -#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ #define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ #define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ #define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ @@ -969,22 +985,6 @@ typedef enum { #define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ #define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ #define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ -#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ -#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ -#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ -#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ -#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ -#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ -#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ -#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ -#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ -#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ -#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ -#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ -#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ -#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ -#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ -#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ /******************************************************************************* * FLASHC diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624abzi_s2d44a0.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624abzi_s2d44a0.h index 135b8e8e10..0eccaef7a4 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624abzi_s2d44a0.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624abzi_s2d44a0.h @@ -5,11 +5,11 @@ * CY8C624ABZI-S2D44A0 device header * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -488,43 +488,19 @@ typedef enum { #define CY_FLASH_SIZE 0x00200000UL #define CY_EM_EEPROM_BASE 0x14000000UL #define CY_EM_EEPROM_SIZE 0x00008000UL -#define CY_XIP_BASE 0x18000000UL -#define CY_XIP_SIZE 0x08000000UL #define CY_SFLASH_BASE 0x16000000UL #define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL #define CY_EFUSE_BASE 0x402C0800UL #define CY_EFUSE_SIZE 0x00000200UL #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 13u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 2u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 2u +#define CY_IP_MXAUDIOSS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 2u @@ -537,36 +513,60 @@ typedef enum { #define CY_IP_MXCRYPTO 1u #define CY_IP_MXCRYPTO_INSTANCES 1u #define CY_IP_MXCRYPTO_VERSION 2u -#define CY_IP_MXSDHC 1u -#define CY_IP_MXSDHC_INSTANCES 2u -#define CY_IP_MXSDHC_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 2u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u #define CY_IP_MXS40PASS 1u #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u #define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 2u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 13u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 2u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_02_config.h" #include "gpio_psoc6_02_124_bga.h" @@ -928,6 +928,7 @@ typedef enum { #define PROT_BASE 0x40230000UL #define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ #define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ #define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ #define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ @@ -944,7 +945,22 @@ typedef enum { #define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ #define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ #define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ -#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ #define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ #define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ #define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ @@ -969,22 +985,6 @@ typedef enum { #define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ #define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ #define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ -#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ -#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ -#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ -#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ -#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ -#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ -#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ -#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ -#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ -#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ -#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ -#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ -#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ -#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ -#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ -#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ /******************************************************************************* * FLASHC diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624afni_d43.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624afni_d43.h index daf2978c99..b43756d559 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624afni_d43.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624afni_d43.h @@ -5,11 +5,11 @@ * CY8C624AFNI-D43 device header * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -488,43 +488,19 @@ typedef enum { #define CY_FLASH_SIZE 0x00200000UL #define CY_EM_EEPROM_BASE 0x14000000UL #define CY_EM_EEPROM_SIZE 0x00008000UL -#define CY_XIP_BASE 0x18000000UL -#define CY_XIP_SIZE 0x08000000UL #define CY_SFLASH_BASE 0x16000000UL #define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL #define CY_EFUSE_BASE 0x402C0800UL #define CY_EFUSE_SIZE 0x00000200UL #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 13u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 2u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 2u +#define CY_IP_MXAUDIOSS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 2u @@ -537,36 +513,60 @@ typedef enum { #define CY_IP_MXCRYPTO 1u #define CY_IP_MXCRYPTO_INSTANCES 1u #define CY_IP_MXCRYPTO_VERSION 2u -#define CY_IP_MXSDHC 1u -#define CY_IP_MXSDHC_INSTANCES 2u -#define CY_IP_MXSDHC_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 2u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u #define CY_IP_MXS40PASS 1u #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u #define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 2u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 13u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 2u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_02_config.h" #include "gpio_psoc6_02_100_wlcsp.h" @@ -928,6 +928,7 @@ typedef enum { #define PROT_BASE 0x40230000UL #define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ #define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ #define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ #define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ @@ -944,7 +945,22 @@ typedef enum { #define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ #define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ #define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ -#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ #define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ #define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ #define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ @@ -969,22 +985,6 @@ typedef enum { #define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ #define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ #define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ -#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ -#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ -#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ -#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ -#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ -#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ -#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ -#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ -#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ -#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ -#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ -#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ -#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ -#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ -#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ -#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ /******************************************************************************* * FLASHC diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624afni_s2d43.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624afni_s2d43.h index 6870f09a78..b957475870 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624afni_s2d43.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624afni_s2d43.h @@ -5,11 +5,11 @@ * CY8C624AFNI-S2D43 device header * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -488,43 +488,19 @@ typedef enum { #define CY_FLASH_SIZE 0x00200000UL #define CY_EM_EEPROM_BASE 0x14000000UL #define CY_EM_EEPROM_SIZE 0x00008000UL -#define CY_XIP_BASE 0x18000000UL -#define CY_XIP_SIZE 0x08000000UL #define CY_SFLASH_BASE 0x16000000UL #define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL #define CY_EFUSE_BASE 0x402C0800UL #define CY_EFUSE_SIZE 0x00000200UL #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 13u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 2u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 2u +#define CY_IP_MXAUDIOSS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 2u @@ -537,42 +513,66 @@ typedef enum { #define CY_IP_MXCRYPTO 1u #define CY_IP_MXCRYPTO_INSTANCES 1u #define CY_IP_MXCRYPTO_VERSION 2u -#define CY_IP_MXSDHC 1u -#define CY_IP_MXSDHC_INSTANCES 2u -#define CY_IP_MXSDHC_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 2u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u #define CY_IP_MXS40PASS 1u #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u #define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 2u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 13u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 2u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_02_config.h" #include "gpio_psoc6_02_100_wlcsp.h" #define CY_DEVICE_PSOC6A2M -#define CY_SILICON_ID 0xE4551102UL +#define CY_SILICON_ID 0xE4551202UL #define CY_HF_CLK_MAX_FREQ 150000000UL #define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL @@ -928,6 +928,7 @@ typedef enum { #define PROT_BASE 0x40230000UL #define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ #define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ #define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ #define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ @@ -944,7 +945,22 @@ typedef enum { #define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ #define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ #define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ -#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ #define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ #define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ #define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ @@ -969,22 +985,6 @@ typedef enum { #define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ #define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ #define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ -#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ -#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ -#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ -#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ -#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ -#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ -#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ -#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ -#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ -#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ -#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ -#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ -#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ -#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ -#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ -#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ /******************************************************************************* * FLASHC diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624alqi_d42.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624alqi_d42.h index cb62aa084d..0c4cfd449a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624alqi_d42.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c624alqi_d42.h @@ -5,11 +5,11 @@ * CY8C624ALQI-D42 device header * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -488,43 +488,19 @@ typedef enum { #define CY_FLASH_SIZE 0x00200000UL #define CY_EM_EEPROM_BASE 0x14000000UL #define CY_EM_EEPROM_SIZE 0x00008000UL -#define CY_XIP_BASE 0x18000000UL -#define CY_XIP_SIZE 0x08000000UL #define CY_SFLASH_BASE 0x16000000UL #define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL #define CY_EFUSE_BASE 0x402C0800UL #define CY_EFUSE_SIZE 0x00000200UL #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 13u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 2u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 2u +#define CY_IP_MXAUDIOSS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 2u @@ -537,36 +513,60 @@ typedef enum { #define CY_IP_MXCRYPTO 1u #define CY_IP_MXCRYPTO_INSTANCES 1u #define CY_IP_MXCRYPTO_VERSION 2u -#define CY_IP_MXSDHC 1u -#define CY_IP_MXSDHC_INSTANCES 2u -#define CY_IP_MXSDHC_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 2u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u #define CY_IP_MXS40PASS 1u #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u #define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 2u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 13u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 2u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_02_config.h" #include "gpio_psoc6_02_68_qfn.h" @@ -928,6 +928,7 @@ typedef enum { #define PROT_BASE 0x40230000UL #define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ #define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ #define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ #define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ @@ -944,7 +945,22 @@ typedef enum { #define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ #define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ #define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ -#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ #define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ #define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ #define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ @@ -969,22 +985,6 @@ typedef enum { #define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ #define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ #define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ -#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ -#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ -#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ -#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ -#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ -#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ -#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ -#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ -#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ -#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ -#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ -#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ -#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ -#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ -#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ -#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ /******************************************************************************* * FLASHC diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6316bzi_blf03.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6316bzi_blf03.h index 6deda71c4c..b90a557d5b 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6316bzi_blf03.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6316bzi_blf03.h @@ -5,11 +5,11 @@ * CY8C6316BZI-BLF03 device header * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -236,55 +236,40 @@ typedef enum { #define CY_FLASH_SIZE 0x00080000UL #define CY_EM_EEPROM_BASE 0x14000000UL #define CY_EM_EEPROM_SIZE 0x00008000UL -#define CY_XIP_BASE 0x18000000UL -#define CY_XIP_SIZE 0x08000000UL #define CY_SFLASH_BASE 0x16000000UL #define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL #define CY_EFUSE_BASE 0x402C0800UL #define CY_EFUSE_SIZE 0x00000200UL #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXBLESS 1u +#define CY_IP_MXBLESS_INSTANCES 1u +#define CY_IP_MXBLESS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u #define CY_IP_M4CPUSS_DMA 1u #define CY_IP_M4CPUSS_DMA_INSTANCES 2u #define CY_IP_M4CPUSS_DMA_VERSION 1u -#define CY_IP_MXBLESS 1u -#define CY_IP_MXBLESS_INSTANCES 1u -#define CY_IP_MXBLESS_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -297,18 +282,33 @@ typedef enum { #define CY_IP_MXS40PASS_CTDAC 1u #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u #define CY_IP_MXS40PASS_CTDAC_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_116_bga_ble.h" @@ -601,6 +601,7 @@ typedef enum { #define PROT_BASE 0x40240000UL #define PROT ((PROT_Type*) PROT_BASE) /* 0x40240000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ #define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40242000 */ #define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40242040 */ #define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40242080 */ @@ -617,23 +618,6 @@ typedef enum { #define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40242340 */ #define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40242380 */ #define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402423C0 */ -#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ -#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ -#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ -#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ -#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ -#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ -#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ -#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ -#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ -#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ -#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ -#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ -#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ -#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ -#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ -#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ -#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ #define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40244000 */ #define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40244400 */ #define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40244800 */ @@ -650,6 +634,22 @@ typedef enum { #define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40247400 */ #define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40247800 */ #define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40247C00 */ +#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ +#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ +#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ +#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ +#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ +#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ +#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ +#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ /******************************************************************************* * FLASHC @@ -859,8 +859,8 @@ typedef enum { #define BLE_BASE 0x403C0000UL #define BLE ((BLE_Type*) BLE_BASE) /* 0x403C0000 */ -#define BLE_RCB_RCBLL ((BLE_RCB_RCBLL_Type*) &BLE->RCB.RCBLL) /* 0x403C0100 */ #define BLE_RCB ((BLE_RCB_Type*) &BLE->RCB) /* 0x403C0000 */ +#define BLE_RCB_RCBLL ((BLE_RCB_RCBLL_Type*) &BLE->RCB.RCBLL) /* 0x403C0100 */ #define BLE_BLELL ((BLE_BLELL_Type*) &BLE->BLELL) /* 0x403C1000 */ #define BLE_BLESS ((BLE_BLESS_Type*) &BLE->BLESS) /* 0x403DF000 */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6316bzi_blf04.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6316bzi_blf04.h index 933810b1e0..fa445dac1d 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6316bzi_blf04.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6316bzi_blf04.h @@ -5,11 +5,11 @@ * CY8C6316BZI-BLF04 device header * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -236,55 +236,40 @@ typedef enum { #define CY_FLASH_SIZE 0x00080000UL #define CY_EM_EEPROM_BASE 0x14000000UL #define CY_EM_EEPROM_SIZE 0x00008000UL -#define CY_XIP_BASE 0x18000000UL -#define CY_XIP_SIZE 0x08000000UL #define CY_SFLASH_BASE 0x16000000UL #define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL #define CY_EFUSE_BASE 0x402C0800UL #define CY_EFUSE_SIZE 0x00000200UL #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXBLESS 1u +#define CY_IP_MXBLESS_INSTANCES 1u +#define CY_IP_MXBLESS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u #define CY_IP_M4CPUSS_DMA 1u #define CY_IP_M4CPUSS_DMA_INSTANCES 2u #define CY_IP_M4CPUSS_DMA_VERSION 1u -#define CY_IP_MXBLESS 1u -#define CY_IP_MXBLESS_INSTANCES 1u -#define CY_IP_MXBLESS_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -297,21 +282,36 @@ typedef enum { #define CY_IP_MXS40PASS_CTDAC 1u #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u #define CY_IP_MXS40PASS_CTDAC_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_124_bga_sip.h" @@ -604,6 +604,7 @@ typedef enum { #define PROT_BASE 0x40240000UL #define PROT ((PROT_Type*) PROT_BASE) /* 0x40240000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ #define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40242000 */ #define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40242040 */ #define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40242080 */ @@ -620,23 +621,6 @@ typedef enum { #define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40242340 */ #define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40242380 */ #define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402423C0 */ -#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ -#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ -#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ -#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ -#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ -#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ -#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ -#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ -#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ -#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ -#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ -#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ -#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ -#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ -#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ -#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ -#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ #define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40244000 */ #define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40244400 */ #define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40244800 */ @@ -653,6 +637,22 @@ typedef enum { #define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40247400 */ #define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40247800 */ #define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40247C00 */ +#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ +#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ +#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ +#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ +#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ +#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ +#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ +#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ /******************************************************************************* * FLASHC @@ -862,8 +862,8 @@ typedef enum { #define BLE_BASE 0x403C0000UL #define BLE ((BLE_Type*) BLE_BASE) /* 0x403C0000 */ -#define BLE_RCB_RCBLL ((BLE_RCB_RCBLL_Type*) &BLE->RCB.RCBLL) /* 0x403C0100 */ #define BLE_RCB ((BLE_RCB_Type*) &BLE->RCB) /* 0x403C0000 */ +#define BLE_RCB_RCBLL ((BLE_RCB_RCBLL_Type*) &BLE->RCB.RCBLL) /* 0x403C0100 */ #define BLE_BLELL ((BLE_BLELL_Type*) &BLE->BLELL) /* 0x403C1000 */ #define BLE_BLESS ((BLE_BLESS_Type*) &BLE->BLESS) /* 0x403DF000 */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6316bzi_blf53.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6316bzi_blf53.h index 5d4a98dcd2..7090b02439 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6316bzi_blf53.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6316bzi_blf53.h @@ -5,11 +5,11 @@ * CY8C6316BZI-BLF53 device header * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -236,43 +236,22 @@ typedef enum { #define CY_FLASH_SIZE 0x00080000UL #define CY_EM_EEPROM_BASE 0x14000000UL #define CY_EM_EEPROM_SIZE 0x00008000UL -#define CY_XIP_BASE 0x18000000UL -#define CY_XIP_SIZE 0x08000000UL #define CY_SFLASH_BASE 0x16000000UL #define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL #define CY_EFUSE_BASE 0x402C0800UL #define CY_EFUSE_SIZE 0x00000200UL #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXBLESS 1u +#define CY_IP_MXBLESS_INSTANCES 1u +#define CY_IP_MXBLESS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u @@ -282,12 +261,18 @@ typedef enum { #define CY_IP_MXCRYPTO 1u #define CY_IP_MXCRYPTO_INSTANCES 1u #define CY_IP_MXCRYPTO_VERSION 1u -#define CY_IP_MXBLESS 1u -#define CY_IP_MXBLESS_INSTANCES 1u -#define CY_IP_MXBLESS_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -303,21 +288,36 @@ typedef enum { #define CY_IP_MXS40PASS_CTB 1u #define CY_IP_MXS40PASS_CTB_INSTANCES 1u #define CY_IP_MXS40PASS_CTB_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u -#define CY_IP_MXUDB 1u -#define CY_IP_MXUDB_INSTANCES 1u -#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUDB 1u +#define CY_IP_MXUDB_INSTANCES 1u +#define CY_IP_MXUDB_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_116_bga_ble.h" @@ -617,6 +617,7 @@ typedef enum { #define PROT_BASE 0x40240000UL #define PROT ((PROT_Type*) PROT_BASE) /* 0x40240000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ #define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40242000 */ #define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40242040 */ #define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40242080 */ @@ -633,23 +634,6 @@ typedef enum { #define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40242340 */ #define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40242380 */ #define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402423C0 */ -#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ -#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ -#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ -#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ -#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ -#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ -#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ -#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ -#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ -#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ -#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ -#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ -#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ -#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ -#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ -#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ -#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ #define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40244000 */ #define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40244400 */ #define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40244800 */ @@ -666,6 +650,22 @@ typedef enum { #define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40247400 */ #define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40247800 */ #define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40247C00 */ +#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ +#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ +#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ +#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ +#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ +#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ +#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ +#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ /******************************************************************************* * FLASHC @@ -815,6 +815,12 @@ typedef enum { #define UDB ((UDB_Type*) UDB_BASE) /* 0x40340000 */ #define UDB_WRKONE ((UDB_WRKONE_Type*) &UDB->WRKONE) /* 0x40340000 */ #define UDB_WRKMULT ((UDB_WRKMULT_Type*) &UDB->WRKMULT) /* 0x40341000 */ +#define UDB_UDBPAIR0 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[0]) /* 0x40342000 */ +#define UDB_UDBPAIR1 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[1]) /* 0x40342200 */ +#define UDB_UDBPAIR2 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[2]) /* 0x40342400 */ +#define UDB_UDBPAIR3 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[3]) /* 0x40342600 */ +#define UDB_UDBPAIR4 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[4]) /* 0x40342800 */ +#define UDB_UDBPAIR5 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[5]) /* 0x40342A00 */ #define UDB_UDBPAIR0_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[0].UDBSNG[0]) /* 0x40342000 */ #define UDB_UDBPAIR0_UDBSNG1 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[0].UDBSNG[1]) /* 0x40342080 */ #define UDB_UDBPAIR1_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[1].UDBSNG[0]) /* 0x40342200 */ @@ -833,12 +839,6 @@ typedef enum { #define UDB_UDBPAIR3_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[3].ROUTE) /* 0x40342700 */ #define UDB_UDBPAIR4_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[4].ROUTE) /* 0x40342900 */ #define UDB_UDBPAIR5_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[5].ROUTE) /* 0x40342B00 */ -#define UDB_UDBPAIR0 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[0]) /* 0x40342000 */ -#define UDB_UDBPAIR1 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[1]) /* 0x40342200 */ -#define UDB_UDBPAIR2 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[2]) /* 0x40342400 */ -#define UDB_UDBPAIR3 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[3]) /* 0x40342600 */ -#define UDB_UDBPAIR4 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[4]) /* 0x40342800 */ -#define UDB_UDBPAIR5 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[5]) /* 0x40342A00 */ #define UDB_DSI0 ((UDB_DSI_Type*) &UDB->DSI[0]) /* 0x40346000 */ #define UDB_DSI1 ((UDB_DSI_Type*) &UDB->DSI[1]) /* 0x40346080 */ #define UDB_DSI2 ((UDB_DSI_Type*) &UDB->DSI[2]) /* 0x40346100 */ @@ -934,8 +934,8 @@ typedef enum { #define BLE_BASE 0x403C0000UL #define BLE ((BLE_Type*) BLE_BASE) /* 0x403C0000 */ -#define BLE_RCB_RCBLL ((BLE_RCB_RCBLL_Type*) &BLE->RCB.RCBLL) /* 0x403C0100 */ #define BLE_RCB ((BLE_RCB_Type*) &BLE->RCB) /* 0x403C0000 */ +#define BLE_RCB_RCBLL ((BLE_RCB_RCBLL_Type*) &BLE->RCB.RCBLL) /* 0x403C0100 */ #define BLE_BLELL ((BLE_BLELL_Type*) &BLE->BLELL) /* 0x403C1000 */ #define BLE_BLESS ((BLE_BLESS_Type*) &BLE->BLESS) /* 0x403DF000 */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6316bzi_blf54.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6316bzi_blf54.h index 54b9952790..66db34cf2e 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6316bzi_blf54.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6316bzi_blf54.h @@ -5,11 +5,11 @@ * CY8C6316BZI-BLF54 device header * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -236,43 +236,22 @@ typedef enum { #define CY_FLASH_SIZE 0x00080000UL #define CY_EM_EEPROM_BASE 0x14000000UL #define CY_EM_EEPROM_SIZE 0x00008000UL -#define CY_XIP_BASE 0x18000000UL -#define CY_XIP_SIZE 0x08000000UL #define CY_SFLASH_BASE 0x16000000UL #define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL #define CY_EFUSE_BASE 0x402C0800UL #define CY_EFUSE_SIZE 0x00000200UL #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXBLESS 1u +#define CY_IP_MXBLESS_INSTANCES 1u +#define CY_IP_MXBLESS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u @@ -282,12 +261,18 @@ typedef enum { #define CY_IP_MXCRYPTO 1u #define CY_IP_MXCRYPTO_INSTANCES 1u #define CY_IP_MXCRYPTO_VERSION 1u -#define CY_IP_MXBLESS 1u -#define CY_IP_MXBLESS_INSTANCES 1u -#define CY_IP_MXBLESS_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -303,24 +288,39 @@ typedef enum { #define CY_IP_MXS40PASS_CTB 1u #define CY_IP_MXS40PASS_CTB_INSTANCES 1u #define CY_IP_MXS40PASS_CTB_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u -#define CY_IP_MXUDB 1u -#define CY_IP_MXUDB_INSTANCES 1u -#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUDB 1u +#define CY_IP_MXUDB_INSTANCES 1u +#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_124_bga_sip.h" @@ -620,6 +620,7 @@ typedef enum { #define PROT_BASE 0x40240000UL #define PROT ((PROT_Type*) PROT_BASE) /* 0x40240000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ #define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40242000 */ #define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40242040 */ #define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40242080 */ @@ -636,23 +637,6 @@ typedef enum { #define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40242340 */ #define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40242380 */ #define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402423C0 */ -#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ -#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ -#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ -#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ -#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ -#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ -#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ -#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ -#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ -#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ -#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ -#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ -#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ -#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ -#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ -#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ -#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ #define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40244000 */ #define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40244400 */ #define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40244800 */ @@ -669,6 +653,22 @@ typedef enum { #define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40247400 */ #define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40247800 */ #define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40247C00 */ +#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ +#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ +#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ +#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ +#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ +#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ +#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ +#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ /******************************************************************************* * FLASHC @@ -818,6 +818,12 @@ typedef enum { #define UDB ((UDB_Type*) UDB_BASE) /* 0x40340000 */ #define UDB_WRKONE ((UDB_WRKONE_Type*) &UDB->WRKONE) /* 0x40340000 */ #define UDB_WRKMULT ((UDB_WRKMULT_Type*) &UDB->WRKMULT) /* 0x40341000 */ +#define UDB_UDBPAIR0 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[0]) /* 0x40342000 */ +#define UDB_UDBPAIR1 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[1]) /* 0x40342200 */ +#define UDB_UDBPAIR2 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[2]) /* 0x40342400 */ +#define UDB_UDBPAIR3 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[3]) /* 0x40342600 */ +#define UDB_UDBPAIR4 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[4]) /* 0x40342800 */ +#define UDB_UDBPAIR5 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[5]) /* 0x40342A00 */ #define UDB_UDBPAIR0_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[0].UDBSNG[0]) /* 0x40342000 */ #define UDB_UDBPAIR0_UDBSNG1 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[0].UDBSNG[1]) /* 0x40342080 */ #define UDB_UDBPAIR1_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[1].UDBSNG[0]) /* 0x40342200 */ @@ -836,12 +842,6 @@ typedef enum { #define UDB_UDBPAIR3_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[3].ROUTE) /* 0x40342700 */ #define UDB_UDBPAIR4_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[4].ROUTE) /* 0x40342900 */ #define UDB_UDBPAIR5_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[5].ROUTE) /* 0x40342B00 */ -#define UDB_UDBPAIR0 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[0]) /* 0x40342000 */ -#define UDB_UDBPAIR1 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[1]) /* 0x40342200 */ -#define UDB_UDBPAIR2 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[2]) /* 0x40342400 */ -#define UDB_UDBPAIR3 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[3]) /* 0x40342600 */ -#define UDB_UDBPAIR4 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[4]) /* 0x40342800 */ -#define UDB_UDBPAIR5 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[5]) /* 0x40342A00 */ #define UDB_DSI0 ((UDB_DSI_Type*) &UDB->DSI[0]) /* 0x40346000 */ #define UDB_DSI1 ((UDB_DSI_Type*) &UDB->DSI[1]) /* 0x40346080 */ #define UDB_DSI2 ((UDB_DSI_Type*) &UDB->DSI[2]) /* 0x40346100 */ @@ -937,8 +937,8 @@ typedef enum { #define BLE_BASE 0x403C0000UL #define BLE ((BLE_Type*) BLE_BASE) /* 0x403C0000 */ -#define BLE_RCB_RCBLL ((BLE_RCB_RCBLL_Type*) &BLE->RCB.RCBLL) /* 0x403C0100 */ #define BLE_RCB ((BLE_RCB_Type*) &BLE->RCB) /* 0x403C0000 */ +#define BLE_RCB_RCBLL ((BLE_RCB_RCBLL_Type*) &BLE->RCB.RCBLL) /* 0x403C0100 */ #define BLE_BLELL ((BLE_BLELL_Type*) &BLE->BLELL) /* 0x403C1000 */ #define BLE_BLESS ((BLE_BLESS_Type*) &BLE->BLESS) /* 0x403DF000 */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6336bzi_bld13.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6336bzi_bld13.h index 69c8635ea4..ffed7d0e0c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6336bzi_bld13.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6336bzi_bld13.h @@ -5,11 +5,11 @@ * CY8C6336BZI-BLD13 device header * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -461,55 +461,40 @@ typedef enum { #define CY_FLASH_SIZE 0x00080000UL #define CY_EM_EEPROM_BASE 0x14000000UL #define CY_EM_EEPROM_SIZE 0x00008000UL -#define CY_XIP_BASE 0x18000000UL -#define CY_XIP_SIZE 0x08000000UL #define CY_SFLASH_BASE 0x16000000UL #define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL #define CY_EFUSE_BASE 0x402C0800UL #define CY_EFUSE_SIZE 0x00000200UL #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXBLESS 1u +#define CY_IP_MXBLESS_INSTANCES 1u +#define CY_IP_MXBLESS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u #define CY_IP_M4CPUSS_DMA 1u #define CY_IP_M4CPUSS_DMA_INSTANCES 2u #define CY_IP_M4CPUSS_DMA_VERSION 1u -#define CY_IP_MXBLESS 1u -#define CY_IP_MXBLESS_INSTANCES 1u -#define CY_IP_MXBLESS_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -522,18 +507,33 @@ typedef enum { #define CY_IP_MXS40PASS_CTDAC 1u #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u #define CY_IP_MXS40PASS_CTDAC_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_116_bga_ble.h" @@ -826,6 +826,7 @@ typedef enum { #define PROT_BASE 0x40240000UL #define PROT ((PROT_Type*) PROT_BASE) /* 0x40240000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ #define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40242000 */ #define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40242040 */ #define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40242080 */ @@ -842,23 +843,6 @@ typedef enum { #define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40242340 */ #define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40242380 */ #define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402423C0 */ -#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ -#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ -#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ -#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ -#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ -#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ -#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ -#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ -#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ -#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ -#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ -#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ -#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ -#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ -#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ -#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ -#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ #define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40244000 */ #define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40244400 */ #define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40244800 */ @@ -875,6 +859,22 @@ typedef enum { #define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40247400 */ #define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40247800 */ #define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40247C00 */ +#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ +#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ +#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ +#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ +#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ +#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ +#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ +#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ /******************************************************************************* * FLASHC @@ -1084,8 +1084,8 @@ typedef enum { #define BLE_BASE 0x403C0000UL #define BLE ((BLE_Type*) BLE_BASE) /* 0x403C0000 */ -#define BLE_RCB_RCBLL ((BLE_RCB_RCBLL_Type*) &BLE->RCB.RCBLL) /* 0x403C0100 */ #define BLE_RCB ((BLE_RCB_Type*) &BLE->RCB) /* 0x403C0000 */ +#define BLE_RCB_RCBLL ((BLE_RCB_RCBLL_Type*) &BLE->RCB.RCBLL) /* 0x403C0100 */ #define BLE_BLELL ((BLE_BLELL_Type*) &BLE->BLELL) /* 0x403C1000 */ #define BLE_BLESS ((BLE_BLESS_Type*) &BLE->BLESS) /* 0x403DF000 */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6336bzi_bld14.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6336bzi_bld14.h index fddafdc00f..bba6cffa40 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6336bzi_bld14.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6336bzi_bld14.h @@ -5,11 +5,11 @@ * CY8C6336BZI-BLD14 device header * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -461,55 +461,40 @@ typedef enum { #define CY_FLASH_SIZE 0x00080000UL #define CY_EM_EEPROM_BASE 0x14000000UL #define CY_EM_EEPROM_SIZE 0x00008000UL -#define CY_XIP_BASE 0x18000000UL -#define CY_XIP_SIZE 0x08000000UL #define CY_SFLASH_BASE 0x16000000UL #define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL #define CY_EFUSE_BASE 0x402C0800UL #define CY_EFUSE_SIZE 0x00000200UL #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXBLESS 1u +#define CY_IP_MXBLESS_INSTANCES 1u +#define CY_IP_MXBLESS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u #define CY_IP_M4CPUSS_DMA 1u #define CY_IP_M4CPUSS_DMA_INSTANCES 2u #define CY_IP_M4CPUSS_DMA_VERSION 1u -#define CY_IP_MXBLESS 1u -#define CY_IP_MXBLESS_INSTANCES 1u -#define CY_IP_MXBLESS_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -522,21 +507,36 @@ typedef enum { #define CY_IP_MXS40PASS_CTDAC 1u #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u #define CY_IP_MXS40PASS_CTDAC_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_124_bga_sip.h" @@ -829,6 +829,7 @@ typedef enum { #define PROT_BASE 0x40240000UL #define PROT ((PROT_Type*) PROT_BASE) /* 0x40240000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ #define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40242000 */ #define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40242040 */ #define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40242080 */ @@ -845,23 +846,6 @@ typedef enum { #define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40242340 */ #define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40242380 */ #define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402423C0 */ -#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ -#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ -#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ -#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ -#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ -#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ -#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ -#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ -#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ -#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ -#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ -#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ -#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ -#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ -#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ -#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ -#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ #define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40244000 */ #define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40244400 */ #define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40244800 */ @@ -878,6 +862,22 @@ typedef enum { #define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40247400 */ #define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40247800 */ #define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40247C00 */ +#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ +#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ +#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ +#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ +#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ +#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ +#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ +#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ /******************************************************************************* * FLASHC @@ -1087,8 +1087,8 @@ typedef enum { #define BLE_BASE 0x403C0000UL #define BLE ((BLE_Type*) BLE_BASE) /* 0x403C0000 */ -#define BLE_RCB_RCBLL ((BLE_RCB_RCBLL_Type*) &BLE->RCB.RCBLL) /* 0x403C0100 */ #define BLE_RCB ((BLE_RCB_Type*) &BLE->RCB) /* 0x403C0000 */ +#define BLE_RCB_RCBLL ((BLE_RCB_RCBLL_Type*) &BLE->RCB.RCBLL) /* 0x403C0100 */ #define BLE_BLELL ((BLE_BLELL_Type*) &BLE->BLELL) /* 0x403C1000 */ #define BLE_BLESS ((BLE_BLESS_Type*) &BLE->BLESS) /* 0x403DF000 */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6336bzi_blf03.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6336bzi_blf03.h index 1338a326da..e17764c398 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6336bzi_blf03.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6336bzi_blf03.h @@ -5,11 +5,11 @@ * CY8C6336BZI-BLF03 device header * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -236,55 +236,40 @@ typedef enum { #define CY_FLASH_SIZE 0x00080000UL #define CY_EM_EEPROM_BASE 0x14000000UL #define CY_EM_EEPROM_SIZE 0x00008000UL -#define CY_XIP_BASE 0x18000000UL -#define CY_XIP_SIZE 0x08000000UL #define CY_SFLASH_BASE 0x16000000UL #define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL #define CY_EFUSE_BASE 0x402C0800UL #define CY_EFUSE_SIZE 0x00000200UL #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXBLESS 1u +#define CY_IP_MXBLESS_INSTANCES 1u +#define CY_IP_MXBLESS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u #define CY_IP_M4CPUSS_DMA 1u #define CY_IP_M4CPUSS_DMA_INSTANCES 2u #define CY_IP_M4CPUSS_DMA_VERSION 1u -#define CY_IP_MXBLESS 1u -#define CY_IP_MXBLESS_INSTANCES 1u -#define CY_IP_MXBLESS_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -297,18 +282,33 @@ typedef enum { #define CY_IP_MXS40PASS_CTDAC 1u #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u #define CY_IP_MXS40PASS_CTDAC_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_116_bga_ble.h" @@ -601,6 +601,7 @@ typedef enum { #define PROT_BASE 0x40240000UL #define PROT ((PROT_Type*) PROT_BASE) /* 0x40240000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ #define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40242000 */ #define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40242040 */ #define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40242080 */ @@ -617,23 +618,6 @@ typedef enum { #define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40242340 */ #define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40242380 */ #define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402423C0 */ -#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ -#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ -#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ -#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ -#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ -#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ -#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ -#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ -#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ -#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ -#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ -#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ -#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ -#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ -#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ -#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ -#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ #define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40244000 */ #define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40244400 */ #define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40244800 */ @@ -650,6 +634,22 @@ typedef enum { #define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40247400 */ #define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40247800 */ #define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40247C00 */ +#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ +#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ +#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ +#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ +#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ +#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ +#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ +#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ /******************************************************************************* * FLASHC @@ -859,8 +859,8 @@ typedef enum { #define BLE_BASE 0x403C0000UL #define BLE ((BLE_Type*) BLE_BASE) /* 0x403C0000 */ -#define BLE_RCB_RCBLL ((BLE_RCB_RCBLL_Type*) &BLE->RCB.RCBLL) /* 0x403C0100 */ #define BLE_RCB ((BLE_RCB_Type*) &BLE->RCB) /* 0x403C0000 */ +#define BLE_RCB_RCBLL ((BLE_RCB_RCBLL_Type*) &BLE->RCB.RCBLL) /* 0x403C0100 */ #define BLE_BLELL ((BLE_BLELL_Type*) &BLE->BLELL) /* 0x403C1000 */ #define BLE_BLESS ((BLE_BLESS_Type*) &BLE->BLESS) /* 0x403DF000 */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6336bzi_blf04.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6336bzi_blf04.h index d7725881af..22b2e3d0ae 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6336bzi_blf04.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6336bzi_blf04.h @@ -5,11 +5,11 @@ * CY8C6336BZI-BLF04 device header * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -236,55 +236,40 @@ typedef enum { #define CY_FLASH_SIZE 0x00080000UL #define CY_EM_EEPROM_BASE 0x14000000UL #define CY_EM_EEPROM_SIZE 0x00008000UL -#define CY_XIP_BASE 0x18000000UL -#define CY_XIP_SIZE 0x08000000UL #define CY_SFLASH_BASE 0x16000000UL #define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL #define CY_EFUSE_BASE 0x402C0800UL #define CY_EFUSE_SIZE 0x00000200UL #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXBLESS 1u +#define CY_IP_MXBLESS_INSTANCES 1u +#define CY_IP_MXBLESS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u #define CY_IP_M4CPUSS_DMA 1u #define CY_IP_M4CPUSS_DMA_INSTANCES 2u #define CY_IP_M4CPUSS_DMA_VERSION 1u -#define CY_IP_MXBLESS 1u -#define CY_IP_MXBLESS_INSTANCES 1u -#define CY_IP_MXBLESS_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -297,21 +282,36 @@ typedef enum { #define CY_IP_MXS40PASS_CTDAC 1u #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u #define CY_IP_MXS40PASS_CTDAC_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_124_bga_sip.h" @@ -604,6 +604,7 @@ typedef enum { #define PROT_BASE 0x40240000UL #define PROT ((PROT_Type*) PROT_BASE) /* 0x40240000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ #define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40242000 */ #define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40242040 */ #define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40242080 */ @@ -620,23 +621,6 @@ typedef enum { #define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40242340 */ #define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40242380 */ #define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402423C0 */ -#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ -#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ -#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ -#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ -#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ -#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ -#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ -#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ -#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ -#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ -#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ -#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ -#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ -#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ -#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ -#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ -#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ #define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40244000 */ #define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40244400 */ #define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40244800 */ @@ -653,6 +637,22 @@ typedef enum { #define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40247400 */ #define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40247800 */ #define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40247C00 */ +#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ +#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ +#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ +#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ +#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ +#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ +#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ +#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ /******************************************************************************* * FLASHC @@ -862,8 +862,8 @@ typedef enum { #define BLE_BASE 0x403C0000UL #define BLE ((BLE_Type*) BLE_BASE) /* 0x403C0000 */ -#define BLE_RCB_RCBLL ((BLE_RCB_RCBLL_Type*) &BLE->RCB.RCBLL) /* 0x403C0100 */ #define BLE_RCB ((BLE_RCB_Type*) &BLE->RCB) /* 0x403C0000 */ +#define BLE_RCB_RCBLL ((BLE_RCB_RCBLL_Type*) &BLE->RCB.RCBLL) /* 0x403C0100 */ #define BLE_BLELL ((BLE_BLELL_Type*) &BLE->BLELL) /* 0x403C1000 */ #define BLE_BLESS ((BLE_BLESS_Type*) &BLE->BLESS) /* 0x403DF000 */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6336bzi_bud13.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6336bzi_bud13.h index 0f4c3198ae..e4f844d46e 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6336bzi_bud13.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6336bzi_bud13.h @@ -5,11 +5,11 @@ * CY8C6336BZI-BUD13 device header * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -461,55 +461,40 @@ typedef enum { #define CY_FLASH_SIZE 0x00080000UL #define CY_EM_EEPROM_BASE 0x14000000UL #define CY_EM_EEPROM_SIZE 0x00008000UL -#define CY_XIP_BASE 0x18000000UL -#define CY_XIP_SIZE 0x08000000UL #define CY_SFLASH_BASE 0x16000000UL #define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL #define CY_EFUSE_BASE 0x402C0800UL #define CY_EFUSE_SIZE 0x00000200UL #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXBLESS 1u +#define CY_IP_MXBLESS_INSTANCES 1u +#define CY_IP_MXBLESS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u #define CY_IP_M4CPUSS_DMA 1u #define CY_IP_M4CPUSS_DMA_INSTANCES 2u #define CY_IP_M4CPUSS_DMA_VERSION 1u -#define CY_IP_MXBLESS 1u -#define CY_IP_MXBLESS_INSTANCES 1u -#define CY_IP_MXBLESS_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -522,21 +507,36 @@ typedef enum { #define CY_IP_MXS40PASS_CTDAC 1u #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u #define CY_IP_MXS40PASS_CTDAC_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_116_bga_usb.h" @@ -829,6 +829,7 @@ typedef enum { #define PROT_BASE 0x40240000UL #define PROT ((PROT_Type*) PROT_BASE) /* 0x40240000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ #define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40242000 */ #define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40242040 */ #define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40242080 */ @@ -845,23 +846,6 @@ typedef enum { #define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40242340 */ #define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40242380 */ #define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402423C0 */ -#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ -#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ -#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ -#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ -#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ -#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ -#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ -#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ -#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ -#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ -#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ -#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ -#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ -#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ -#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ -#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ -#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ #define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40244000 */ #define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40244400 */ #define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40244800 */ @@ -878,6 +862,22 @@ typedef enum { #define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40247400 */ #define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40247800 */ #define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40247C00 */ +#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ +#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ +#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ +#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ +#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ +#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ +#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ +#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ /******************************************************************************* * FLASHC @@ -1087,8 +1087,8 @@ typedef enum { #define BLE_BASE 0x403C0000UL #define BLE ((BLE_Type*) BLE_BASE) /* 0x403C0000 */ -#define BLE_RCB_RCBLL ((BLE_RCB_RCBLL_Type*) &BLE->RCB.RCBLL) /* 0x403C0100 */ #define BLE_RCB ((BLE_RCB_Type*) &BLE->RCB) /* 0x403C0000 */ +#define BLE_RCB_RCBLL ((BLE_RCB_RCBLL_Type*) &BLE->RCB.RCBLL) /* 0x403C0100 */ #define BLE_BLELL ((BLE_BLELL_Type*) &BLE->BLELL) /* 0x403C1000 */ #define BLE_BLESS ((BLE_BLESS_Type*) &BLE->BLESS) /* 0x403DF000 */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6336lqi_blf02.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6336lqi_blf02.h index 5b012458cd..8255d9cc56 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6336lqi_blf02.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6336lqi_blf02.h @@ -5,11 +5,11 @@ * CY8C6336LQI-BLF02 device header * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -236,55 +236,40 @@ typedef enum { #define CY_FLASH_SIZE 0x00080000UL #define CY_EM_EEPROM_BASE 0x14000000UL #define CY_EM_EEPROM_SIZE 0x00008000UL -#define CY_XIP_BASE 0x18000000UL -#define CY_XIP_SIZE 0x08000000UL #define CY_SFLASH_BASE 0x16000000UL #define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL #define CY_EFUSE_BASE 0x402C0800UL #define CY_EFUSE_SIZE 0x00000200UL #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXBLESS 1u +#define CY_IP_MXBLESS_INSTANCES 1u +#define CY_IP_MXBLESS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u #define CY_IP_M4CPUSS_DMA 1u #define CY_IP_M4CPUSS_DMA_INSTANCES 2u #define CY_IP_M4CPUSS_DMA_VERSION 1u -#define CY_IP_MXBLESS 1u -#define CY_IP_MXBLESS_INSTANCES 1u -#define CY_IP_MXBLESS_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -297,18 +282,33 @@ typedef enum { #define CY_IP_MXS40PASS_CTDAC 1u #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u #define CY_IP_MXS40PASS_CTDAC_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_68_qfn_ble.h" @@ -601,6 +601,7 @@ typedef enum { #define PROT_BASE 0x40240000UL #define PROT ((PROT_Type*) PROT_BASE) /* 0x40240000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ #define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40242000 */ #define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40242040 */ #define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40242080 */ @@ -617,23 +618,6 @@ typedef enum { #define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40242340 */ #define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40242380 */ #define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402423C0 */ -#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ -#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ -#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ -#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ -#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ -#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ -#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ -#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ -#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ -#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ -#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ -#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ -#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ -#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ -#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ -#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ -#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ #define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40244000 */ #define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40244400 */ #define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40244800 */ @@ -650,6 +634,22 @@ typedef enum { #define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40247400 */ #define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40247800 */ #define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40247C00 */ +#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ +#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ +#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ +#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ +#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ +#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ +#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ +#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ /******************************************************************************* * FLASHC @@ -859,8 +859,8 @@ typedef enum { #define BLE_BASE 0x403C0000UL #define BLE ((BLE_Type*) BLE_BASE) /* 0x403C0000 */ -#define BLE_RCB_RCBLL ((BLE_RCB_RCBLL_Type*) &BLE->RCB.RCBLL) /* 0x403C0100 */ #define BLE_RCB ((BLE_RCB_Type*) &BLE->RCB) /* 0x403C0000 */ +#define BLE_RCB_RCBLL ((BLE_RCB_RCBLL_Type*) &BLE->RCB.RCBLL) /* 0x403C0100 */ #define BLE_BLELL ((BLE_BLELL_Type*) &BLE->BLELL) /* 0x403C1000 */ #define BLE_BLESS ((BLE_BLESS_Type*) &BLE->BLESS) /* 0x403DF000 */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6336lqi_blf42.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6336lqi_blf42.h index 60f34aa3b6..652a3d8f6b 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6336lqi_blf42.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6336lqi_blf42.h @@ -5,11 +5,11 @@ * CY8C6336LQI-BLF42 device header * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -236,43 +236,22 @@ typedef enum { #define CY_FLASH_SIZE 0x00080000UL #define CY_EM_EEPROM_BASE 0x14000000UL #define CY_EM_EEPROM_SIZE 0x00008000UL -#define CY_XIP_BASE 0x18000000UL -#define CY_XIP_SIZE 0x08000000UL #define CY_SFLASH_BASE 0x16000000UL #define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL #define CY_EFUSE_BASE 0x402C0800UL #define CY_EFUSE_SIZE 0x00000200UL #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXBLESS 1u +#define CY_IP_MXBLESS_INSTANCES 1u +#define CY_IP_MXBLESS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u @@ -282,12 +261,18 @@ typedef enum { #define CY_IP_MXCRYPTO 1u #define CY_IP_MXCRYPTO_INSTANCES 1u #define CY_IP_MXCRYPTO_VERSION 1u -#define CY_IP_MXBLESS 1u -#define CY_IP_MXBLESS_INSTANCES 1u -#define CY_IP_MXBLESS_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -300,18 +285,33 @@ typedef enum { #define CY_IP_MXS40PASS_CTDAC 1u #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u #define CY_IP_MXS40PASS_CTDAC_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_68_qfn_ble.h" @@ -611,6 +611,7 @@ typedef enum { #define PROT_BASE 0x40240000UL #define PROT ((PROT_Type*) PROT_BASE) /* 0x40240000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ #define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40242000 */ #define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40242040 */ #define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40242080 */ @@ -627,23 +628,6 @@ typedef enum { #define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40242340 */ #define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40242380 */ #define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402423C0 */ -#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ -#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ -#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ -#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ -#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ -#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ -#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ -#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ -#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ -#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ -#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ -#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ -#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ -#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ -#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ -#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ -#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ #define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40244000 */ #define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40244400 */ #define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40244800 */ @@ -660,6 +644,22 @@ typedef enum { #define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40247400 */ #define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40247800 */ #define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40247C00 */ +#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ +#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ +#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ +#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ +#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ +#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ +#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ +#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ /******************************************************************************* * FLASHC @@ -869,8 +869,8 @@ typedef enum { #define BLE_BASE 0x403C0000UL #define BLE ((BLE_Type*) BLE_BASE) /* 0x403C0000 */ -#define BLE_RCB_RCBLL ((BLE_RCB_RCBLL_Type*) &BLE->RCB.RCBLL) /* 0x403C0100 */ #define BLE_RCB ((BLE_RCB_Type*) &BLE->RCB) /* 0x403C0000 */ +#define BLE_RCB_RCBLL ((BLE_RCB_RCBLL_Type*) &BLE->RCB.RCBLL) /* 0x403C0100 */ #define BLE_BLELL ((BLE_BLELL_Type*) &BLE->BLELL) /* 0x403C1000 */ #define BLE_BLESS ((BLE_BLESS_Type*) &BLE->BLESS) /* 0x403DF000 */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6337bzi_blf13.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6337bzi_blf13.h index 9b7ab97ad6..1cd70d8fc0 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6337bzi_blf13.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6337bzi_blf13.h @@ -5,11 +5,11 @@ * CY8C6337BZI-BLF13 device header * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -236,55 +236,40 @@ typedef enum { #define CY_FLASH_SIZE 0x00100000UL #define CY_EM_EEPROM_BASE 0x14000000UL #define CY_EM_EEPROM_SIZE 0x00008000UL -#define CY_XIP_BASE 0x18000000UL -#define CY_XIP_SIZE 0x08000000UL #define CY_SFLASH_BASE 0x16000000UL #define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL #define CY_EFUSE_BASE 0x402C0800UL #define CY_EFUSE_SIZE 0x00000200UL #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXBLESS 1u +#define CY_IP_MXBLESS_INSTANCES 1u +#define CY_IP_MXBLESS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u #define CY_IP_M4CPUSS_DMA 1u #define CY_IP_M4CPUSS_DMA_INSTANCES 2u #define CY_IP_M4CPUSS_DMA_VERSION 1u -#define CY_IP_MXBLESS 1u -#define CY_IP_MXBLESS_INSTANCES 1u -#define CY_IP_MXBLESS_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -297,18 +282,33 @@ typedef enum { #define CY_IP_MXS40PASS_CTDAC 1u #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u #define CY_IP_MXS40PASS_CTDAC_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_116_bga_ble.h" @@ -601,6 +601,7 @@ typedef enum { #define PROT_BASE 0x40240000UL #define PROT ((PROT_Type*) PROT_BASE) /* 0x40240000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ #define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40242000 */ #define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40242040 */ #define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40242080 */ @@ -617,23 +618,6 @@ typedef enum { #define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40242340 */ #define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40242380 */ #define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402423C0 */ -#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ -#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ -#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ -#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ -#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ -#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ -#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ -#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ -#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ -#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ -#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ -#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ -#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ -#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ -#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ -#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ -#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ #define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40244000 */ #define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40244400 */ #define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40244800 */ @@ -650,6 +634,22 @@ typedef enum { #define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40247400 */ #define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40247800 */ #define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40247C00 */ +#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ +#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ +#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ +#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ +#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ +#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ +#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ +#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ /******************************************************************************* * FLASHC @@ -859,8 +859,8 @@ typedef enum { #define BLE_BASE 0x403C0000UL #define BLE ((BLE_Type*) BLE_BASE) /* 0x403C0000 */ -#define BLE_RCB_RCBLL ((BLE_RCB_RCBLL_Type*) &BLE->RCB.RCBLL) /* 0x403C0100 */ #define BLE_RCB ((BLE_RCB_Type*) &BLE->RCB) /* 0x403C0000 */ +#define BLE_RCB_RCBLL ((BLE_RCB_RCBLL_Type*) &BLE->RCB.RCBLL) /* 0x403C0100 */ #define BLE_BLELL ((BLE_BLELL_Type*) &BLE->BLELL) /* 0x403C1000 */ #define BLE_BLESS ((BLE_BLESS_Type*) &BLE->BLESS) /* 0x403DF000 */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347bzi_bld33.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347bzi_bld33.h index d5e2436b6d..1989708c6d 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347bzi_bld33.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347bzi_bld33.h @@ -5,11 +5,11 @@ * CY8C6347BZI-BLD33 device header * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -461,55 +461,40 @@ typedef enum { #define CY_FLASH_SIZE 0x00100000UL #define CY_EM_EEPROM_BASE 0x14000000UL #define CY_EM_EEPROM_SIZE 0x00008000UL -#define CY_XIP_BASE 0x18000000UL -#define CY_XIP_SIZE 0x08000000UL #define CY_SFLASH_BASE 0x16000000UL #define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL #define CY_EFUSE_BASE 0x402C0800UL #define CY_EFUSE_SIZE 0x00000200UL #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXBLESS 1u +#define CY_IP_MXBLESS_INSTANCES 1u +#define CY_IP_MXBLESS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u #define CY_IP_M4CPUSS_DMA 1u #define CY_IP_M4CPUSS_DMA_INSTANCES 2u #define CY_IP_M4CPUSS_DMA_VERSION 1u -#define CY_IP_MXBLESS 1u -#define CY_IP_MXBLESS_INSTANCES 1u -#define CY_IP_MXBLESS_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -525,21 +510,36 @@ typedef enum { #define CY_IP_MXS40PASS_CTB 1u #define CY_IP_MXS40PASS_CTB_INSTANCES 1u #define CY_IP_MXS40PASS_CTB_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u -#define CY_IP_MXUDB 1u -#define CY_IP_MXUDB_INSTANCES 1u -#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUDB 1u +#define CY_IP_MXUDB_INSTANCES 1u +#define CY_IP_MXUDB_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_116_bga_ble.h" @@ -832,6 +832,7 @@ typedef enum { #define PROT_BASE 0x40240000UL #define PROT ((PROT_Type*) PROT_BASE) /* 0x40240000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ #define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40242000 */ #define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40242040 */ #define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40242080 */ @@ -848,23 +849,6 @@ typedef enum { #define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40242340 */ #define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40242380 */ #define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402423C0 */ -#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ -#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ -#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ -#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ -#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ -#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ -#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ -#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ -#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ -#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ -#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ -#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ -#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ -#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ -#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ -#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ -#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ #define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40244000 */ #define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40244400 */ #define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40244800 */ @@ -881,6 +865,22 @@ typedef enum { #define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40247400 */ #define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40247800 */ #define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40247C00 */ +#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ +#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ +#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ +#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ +#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ +#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ +#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ +#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ /******************************************************************************* * FLASHC @@ -1030,6 +1030,12 @@ typedef enum { #define UDB ((UDB_Type*) UDB_BASE) /* 0x40340000 */ #define UDB_WRKONE ((UDB_WRKONE_Type*) &UDB->WRKONE) /* 0x40340000 */ #define UDB_WRKMULT ((UDB_WRKMULT_Type*) &UDB->WRKMULT) /* 0x40341000 */ +#define UDB_UDBPAIR0 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[0]) /* 0x40342000 */ +#define UDB_UDBPAIR1 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[1]) /* 0x40342200 */ +#define UDB_UDBPAIR2 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[2]) /* 0x40342400 */ +#define UDB_UDBPAIR3 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[3]) /* 0x40342600 */ +#define UDB_UDBPAIR4 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[4]) /* 0x40342800 */ +#define UDB_UDBPAIR5 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[5]) /* 0x40342A00 */ #define UDB_UDBPAIR0_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[0].UDBSNG[0]) /* 0x40342000 */ #define UDB_UDBPAIR0_UDBSNG1 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[0].UDBSNG[1]) /* 0x40342080 */ #define UDB_UDBPAIR1_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[1].UDBSNG[0]) /* 0x40342200 */ @@ -1048,12 +1054,6 @@ typedef enum { #define UDB_UDBPAIR3_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[3].ROUTE) /* 0x40342700 */ #define UDB_UDBPAIR4_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[4].ROUTE) /* 0x40342900 */ #define UDB_UDBPAIR5_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[5].ROUTE) /* 0x40342B00 */ -#define UDB_UDBPAIR0 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[0]) /* 0x40342000 */ -#define UDB_UDBPAIR1 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[1]) /* 0x40342200 */ -#define UDB_UDBPAIR2 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[2]) /* 0x40342400 */ -#define UDB_UDBPAIR3 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[3]) /* 0x40342600 */ -#define UDB_UDBPAIR4 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[4]) /* 0x40342800 */ -#define UDB_UDBPAIR5 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[5]) /* 0x40342A00 */ #define UDB_DSI0 ((UDB_DSI_Type*) &UDB->DSI[0]) /* 0x40346000 */ #define UDB_DSI1 ((UDB_DSI_Type*) &UDB->DSI[1]) /* 0x40346080 */ #define UDB_DSI2 ((UDB_DSI_Type*) &UDB->DSI[2]) /* 0x40346100 */ @@ -1149,8 +1149,8 @@ typedef enum { #define BLE_BASE 0x403C0000UL #define BLE ((BLE_Type*) BLE_BASE) /* 0x403C0000 */ -#define BLE_RCB_RCBLL ((BLE_RCB_RCBLL_Type*) &BLE->RCB.RCBLL) /* 0x403C0100 */ #define BLE_RCB ((BLE_RCB_Type*) &BLE->RCB) /* 0x403C0000 */ +#define BLE_RCB_RCBLL ((BLE_RCB_RCBLL_Type*) &BLE->RCB.RCBLL) /* 0x403C0100 */ #define BLE_BLELL ((BLE_BLELL_Type*) &BLE->BLELL) /* 0x403C1000 */ #define BLE_BLESS ((BLE_BLESS_Type*) &BLE->BLESS) /* 0x403DF000 */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347bzi_bld34.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347bzi_bld34.h index fd74a4e19c..9499800b92 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347bzi_bld34.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347bzi_bld34.h @@ -5,11 +5,11 @@ * CY8C6347BZI-BLD34 device header * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -461,55 +461,40 @@ typedef enum { #define CY_FLASH_SIZE 0x00100000UL #define CY_EM_EEPROM_BASE 0x14000000UL #define CY_EM_EEPROM_SIZE 0x00008000UL -#define CY_XIP_BASE 0x18000000UL -#define CY_XIP_SIZE 0x08000000UL #define CY_SFLASH_BASE 0x16000000UL #define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL #define CY_EFUSE_BASE 0x402C0800UL #define CY_EFUSE_SIZE 0x00000200UL #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXBLESS 1u +#define CY_IP_MXBLESS_INSTANCES 1u +#define CY_IP_MXBLESS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u #define CY_IP_M4CPUSS_DMA 1u #define CY_IP_M4CPUSS_DMA_INSTANCES 2u #define CY_IP_M4CPUSS_DMA_VERSION 1u -#define CY_IP_MXBLESS 1u -#define CY_IP_MXBLESS_INSTANCES 1u -#define CY_IP_MXBLESS_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -525,24 +510,39 @@ typedef enum { #define CY_IP_MXS40PASS_CTB 1u #define CY_IP_MXS40PASS_CTB_INSTANCES 1u #define CY_IP_MXS40PASS_CTB_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u -#define CY_IP_MXUDB 1u -#define CY_IP_MXUDB_INSTANCES 1u -#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUDB 1u +#define CY_IP_MXUDB_INSTANCES 1u +#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_124_bga_sip.h" @@ -835,6 +835,7 @@ typedef enum { #define PROT_BASE 0x40240000UL #define PROT ((PROT_Type*) PROT_BASE) /* 0x40240000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ #define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40242000 */ #define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40242040 */ #define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40242080 */ @@ -851,23 +852,6 @@ typedef enum { #define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40242340 */ #define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40242380 */ #define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402423C0 */ -#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ -#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ -#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ -#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ -#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ -#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ -#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ -#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ -#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ -#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ -#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ -#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ -#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ -#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ -#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ -#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ -#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ #define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40244000 */ #define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40244400 */ #define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40244800 */ @@ -884,6 +868,22 @@ typedef enum { #define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40247400 */ #define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40247800 */ #define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40247C00 */ +#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ +#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ +#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ +#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ +#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ +#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ +#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ +#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ /******************************************************************************* * FLASHC @@ -1033,6 +1033,12 @@ typedef enum { #define UDB ((UDB_Type*) UDB_BASE) /* 0x40340000 */ #define UDB_WRKONE ((UDB_WRKONE_Type*) &UDB->WRKONE) /* 0x40340000 */ #define UDB_WRKMULT ((UDB_WRKMULT_Type*) &UDB->WRKMULT) /* 0x40341000 */ +#define UDB_UDBPAIR0 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[0]) /* 0x40342000 */ +#define UDB_UDBPAIR1 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[1]) /* 0x40342200 */ +#define UDB_UDBPAIR2 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[2]) /* 0x40342400 */ +#define UDB_UDBPAIR3 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[3]) /* 0x40342600 */ +#define UDB_UDBPAIR4 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[4]) /* 0x40342800 */ +#define UDB_UDBPAIR5 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[5]) /* 0x40342A00 */ #define UDB_UDBPAIR0_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[0].UDBSNG[0]) /* 0x40342000 */ #define UDB_UDBPAIR0_UDBSNG1 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[0].UDBSNG[1]) /* 0x40342080 */ #define UDB_UDBPAIR1_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[1].UDBSNG[0]) /* 0x40342200 */ @@ -1051,12 +1057,6 @@ typedef enum { #define UDB_UDBPAIR3_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[3].ROUTE) /* 0x40342700 */ #define UDB_UDBPAIR4_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[4].ROUTE) /* 0x40342900 */ #define UDB_UDBPAIR5_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[5].ROUTE) /* 0x40342B00 */ -#define UDB_UDBPAIR0 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[0]) /* 0x40342000 */ -#define UDB_UDBPAIR1 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[1]) /* 0x40342200 */ -#define UDB_UDBPAIR2 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[2]) /* 0x40342400 */ -#define UDB_UDBPAIR3 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[3]) /* 0x40342600 */ -#define UDB_UDBPAIR4 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[4]) /* 0x40342800 */ -#define UDB_UDBPAIR5 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[5]) /* 0x40342A00 */ #define UDB_DSI0 ((UDB_DSI_Type*) &UDB->DSI[0]) /* 0x40346000 */ #define UDB_DSI1 ((UDB_DSI_Type*) &UDB->DSI[1]) /* 0x40346080 */ #define UDB_DSI2 ((UDB_DSI_Type*) &UDB->DSI[2]) /* 0x40346100 */ @@ -1152,8 +1152,8 @@ typedef enum { #define BLE_BASE 0x403C0000UL #define BLE ((BLE_Type*) BLE_BASE) /* 0x403C0000 */ -#define BLE_RCB_RCBLL ((BLE_RCB_RCBLL_Type*) &BLE->RCB.RCBLL) /* 0x403C0100 */ #define BLE_RCB ((BLE_RCB_Type*) &BLE->RCB) /* 0x403C0000 */ +#define BLE_RCB_RCBLL ((BLE_RCB_RCBLL_Type*) &BLE->RCB.RCBLL) /* 0x403C0100 */ #define BLE_BLELL ((BLE_BLELL_Type*) &BLE->BLELL) /* 0x403C1000 */ #define BLE_BLESS ((BLE_BLESS_Type*) &BLE->BLESS) /* 0x403DF000 */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347bzi_bld43.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347bzi_bld43.h index 0d6fb79a69..22038ba5cb 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347bzi_bld43.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347bzi_bld43.h @@ -5,11 +5,11 @@ * CY8C6347BZI-BLD43 device header * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -461,43 +461,22 @@ typedef enum { #define CY_FLASH_SIZE 0x00100000UL #define CY_EM_EEPROM_BASE 0x14000000UL #define CY_EM_EEPROM_SIZE 0x00008000UL -#define CY_XIP_BASE 0x18000000UL -#define CY_XIP_SIZE 0x08000000UL #define CY_SFLASH_BASE 0x16000000UL #define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL #define CY_EFUSE_BASE 0x402C0800UL #define CY_EFUSE_SIZE 0x00000200UL #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXBLESS 1u +#define CY_IP_MXBLESS_INSTANCES 1u +#define CY_IP_MXBLESS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u @@ -507,12 +486,18 @@ typedef enum { #define CY_IP_MXCRYPTO 1u #define CY_IP_MXCRYPTO_INSTANCES 1u #define CY_IP_MXCRYPTO_VERSION 1u -#define CY_IP_MXBLESS 1u -#define CY_IP_MXBLESS_INSTANCES 1u -#define CY_IP_MXBLESS_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -525,18 +510,33 @@ typedef enum { #define CY_IP_MXS40PASS_CTDAC 1u #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u #define CY_IP_MXS40PASS_CTDAC_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_116_bga_ble.h" @@ -836,6 +836,7 @@ typedef enum { #define PROT_BASE 0x40240000UL #define PROT ((PROT_Type*) PROT_BASE) /* 0x40240000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ #define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40242000 */ #define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40242040 */ #define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40242080 */ @@ -852,23 +853,6 @@ typedef enum { #define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40242340 */ #define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40242380 */ #define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402423C0 */ -#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ -#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ -#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ -#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ -#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ -#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ -#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ -#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ -#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ -#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ -#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ -#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ -#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ -#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ -#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ -#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ -#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ #define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40244000 */ #define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40244400 */ #define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40244800 */ @@ -885,6 +869,22 @@ typedef enum { #define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40247400 */ #define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40247800 */ #define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40247C00 */ +#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ +#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ +#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ +#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ +#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ +#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ +#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ +#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ /******************************************************************************* * FLASHC @@ -1094,8 +1094,8 @@ typedef enum { #define BLE_BASE 0x403C0000UL #define BLE ((BLE_Type*) BLE_BASE) /* 0x403C0000 */ -#define BLE_RCB_RCBLL ((BLE_RCB_RCBLL_Type*) &BLE->RCB.RCBLL) /* 0x403C0100 */ #define BLE_RCB ((BLE_RCB_Type*) &BLE->RCB) /* 0x403C0000 */ +#define BLE_RCB_RCBLL ((BLE_RCB_RCBLL_Type*) &BLE->RCB.RCBLL) /* 0x403C0100 */ #define BLE_BLELL ((BLE_BLELL_Type*) &BLE->BLELL) /* 0x403C1000 */ #define BLE_BLESS ((BLE_BLESS_Type*) &BLE->BLESS) /* 0x403DF000 */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347bzi_bld44.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347bzi_bld44.h index 93a29fa692..eefa5d26c8 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347bzi_bld44.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347bzi_bld44.h @@ -5,11 +5,11 @@ * CY8C6347BZI-BLD44 device header * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -461,43 +461,22 @@ typedef enum { #define CY_FLASH_SIZE 0x00100000UL #define CY_EM_EEPROM_BASE 0x14000000UL #define CY_EM_EEPROM_SIZE 0x00008000UL -#define CY_XIP_BASE 0x18000000UL -#define CY_XIP_SIZE 0x08000000UL #define CY_SFLASH_BASE 0x16000000UL #define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL #define CY_EFUSE_BASE 0x402C0800UL #define CY_EFUSE_SIZE 0x00000200UL #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXBLESS 1u +#define CY_IP_MXBLESS_INSTANCES 1u +#define CY_IP_MXBLESS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u @@ -507,12 +486,18 @@ typedef enum { #define CY_IP_MXCRYPTO 1u #define CY_IP_MXCRYPTO_INSTANCES 1u #define CY_IP_MXCRYPTO_VERSION 1u -#define CY_IP_MXBLESS 1u -#define CY_IP_MXBLESS_INSTANCES 1u -#define CY_IP_MXBLESS_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -525,21 +510,36 @@ typedef enum { #define CY_IP_MXS40PASS_CTDAC 1u #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u #define CY_IP_MXS40PASS_CTDAC_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_124_bga_sip.h" @@ -839,6 +839,7 @@ typedef enum { #define PROT_BASE 0x40240000UL #define PROT ((PROT_Type*) PROT_BASE) /* 0x40240000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ #define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40242000 */ #define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40242040 */ #define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40242080 */ @@ -855,23 +856,6 @@ typedef enum { #define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40242340 */ #define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40242380 */ #define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402423C0 */ -#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ -#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ -#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ -#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ -#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ -#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ -#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ -#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ -#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ -#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ -#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ -#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ -#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ -#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ -#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ -#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ -#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ #define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40244000 */ #define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40244400 */ #define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40244800 */ @@ -888,6 +872,22 @@ typedef enum { #define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40247400 */ #define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40247800 */ #define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40247C00 */ +#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ +#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ +#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ +#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ +#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ +#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ +#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ +#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ /******************************************************************************* * FLASHC @@ -1097,8 +1097,8 @@ typedef enum { #define BLE_BASE 0x403C0000UL #define BLE ((BLE_Type*) BLE_BASE) /* 0x403C0000 */ -#define BLE_RCB_RCBLL ((BLE_RCB_RCBLL_Type*) &BLE->RCB.RCBLL) /* 0x403C0100 */ #define BLE_RCB ((BLE_RCB_Type*) &BLE->RCB) /* 0x403C0000 */ +#define BLE_RCB_RCBLL ((BLE_RCB_RCBLL_Type*) &BLE->RCB.RCBLL) /* 0x403C0100 */ #define BLE_BLELL ((BLE_BLELL_Type*) &BLE->BLELL) /* 0x403C1000 */ #define BLE_BLESS ((BLE_BLESS_Type*) &BLE->BLESS) /* 0x403DF000 */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347bzi_bld53.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347bzi_bld53.h index 06c39a9846..84e29a1511 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347bzi_bld53.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347bzi_bld53.h @@ -5,11 +5,11 @@ * CY8C6347BZI-BLD53 device header * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -461,43 +461,22 @@ typedef enum { #define CY_FLASH_SIZE 0x00100000UL #define CY_EM_EEPROM_BASE 0x14000000UL #define CY_EM_EEPROM_SIZE 0x00008000UL -#define CY_XIP_BASE 0x18000000UL -#define CY_XIP_SIZE 0x08000000UL #define CY_SFLASH_BASE 0x16000000UL #define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL #define CY_EFUSE_BASE 0x402C0800UL #define CY_EFUSE_SIZE 0x00000200UL #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXBLESS 1u +#define CY_IP_MXBLESS_INSTANCES 1u +#define CY_IP_MXBLESS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u @@ -507,12 +486,18 @@ typedef enum { #define CY_IP_MXCRYPTO 1u #define CY_IP_MXCRYPTO_INSTANCES 1u #define CY_IP_MXCRYPTO_VERSION 1u -#define CY_IP_MXBLESS 1u -#define CY_IP_MXBLESS_INSTANCES 1u -#define CY_IP_MXBLESS_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -528,21 +513,36 @@ typedef enum { #define CY_IP_MXS40PASS_CTB 1u #define CY_IP_MXS40PASS_CTB_INSTANCES 1u #define CY_IP_MXS40PASS_CTB_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u -#define CY_IP_MXUDB 1u -#define CY_IP_MXUDB_INSTANCES 1u -#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUDB 1u +#define CY_IP_MXUDB_INSTANCES 1u +#define CY_IP_MXUDB_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_116_bga_ble.h" @@ -842,6 +842,7 @@ typedef enum { #define PROT_BASE 0x40240000UL #define PROT ((PROT_Type*) PROT_BASE) /* 0x40240000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ #define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40242000 */ #define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40242040 */ #define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40242080 */ @@ -858,23 +859,6 @@ typedef enum { #define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40242340 */ #define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40242380 */ #define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402423C0 */ -#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ -#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ -#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ -#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ -#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ -#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ -#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ -#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ -#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ -#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ -#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ -#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ -#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ -#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ -#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ -#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ -#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ #define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40244000 */ #define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40244400 */ #define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40244800 */ @@ -891,6 +875,22 @@ typedef enum { #define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40247400 */ #define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40247800 */ #define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40247C00 */ +#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ +#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ +#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ +#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ +#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ +#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ +#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ +#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ /******************************************************************************* * FLASHC @@ -1040,6 +1040,12 @@ typedef enum { #define UDB ((UDB_Type*) UDB_BASE) /* 0x40340000 */ #define UDB_WRKONE ((UDB_WRKONE_Type*) &UDB->WRKONE) /* 0x40340000 */ #define UDB_WRKMULT ((UDB_WRKMULT_Type*) &UDB->WRKMULT) /* 0x40341000 */ +#define UDB_UDBPAIR0 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[0]) /* 0x40342000 */ +#define UDB_UDBPAIR1 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[1]) /* 0x40342200 */ +#define UDB_UDBPAIR2 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[2]) /* 0x40342400 */ +#define UDB_UDBPAIR3 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[3]) /* 0x40342600 */ +#define UDB_UDBPAIR4 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[4]) /* 0x40342800 */ +#define UDB_UDBPAIR5 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[5]) /* 0x40342A00 */ #define UDB_UDBPAIR0_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[0].UDBSNG[0]) /* 0x40342000 */ #define UDB_UDBPAIR0_UDBSNG1 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[0].UDBSNG[1]) /* 0x40342080 */ #define UDB_UDBPAIR1_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[1].UDBSNG[0]) /* 0x40342200 */ @@ -1058,12 +1064,6 @@ typedef enum { #define UDB_UDBPAIR3_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[3].ROUTE) /* 0x40342700 */ #define UDB_UDBPAIR4_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[4].ROUTE) /* 0x40342900 */ #define UDB_UDBPAIR5_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[5].ROUTE) /* 0x40342B00 */ -#define UDB_UDBPAIR0 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[0]) /* 0x40342000 */ -#define UDB_UDBPAIR1 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[1]) /* 0x40342200 */ -#define UDB_UDBPAIR2 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[2]) /* 0x40342400 */ -#define UDB_UDBPAIR3 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[3]) /* 0x40342600 */ -#define UDB_UDBPAIR4 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[4]) /* 0x40342800 */ -#define UDB_UDBPAIR5 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[5]) /* 0x40342A00 */ #define UDB_DSI0 ((UDB_DSI_Type*) &UDB->DSI[0]) /* 0x40346000 */ #define UDB_DSI1 ((UDB_DSI_Type*) &UDB->DSI[1]) /* 0x40346080 */ #define UDB_DSI2 ((UDB_DSI_Type*) &UDB->DSI[2]) /* 0x40346100 */ @@ -1159,8 +1159,8 @@ typedef enum { #define BLE_BASE 0x403C0000UL #define BLE ((BLE_Type*) BLE_BASE) /* 0x403C0000 */ -#define BLE_RCB_RCBLL ((BLE_RCB_RCBLL_Type*) &BLE->RCB.RCBLL) /* 0x403C0100 */ #define BLE_RCB ((BLE_RCB_Type*) &BLE->RCB) /* 0x403C0000 */ +#define BLE_RCB_RCBLL ((BLE_RCB_RCBLL_Type*) &BLE->RCB.RCBLL) /* 0x403C0100 */ #define BLE_BLELL ((BLE_BLELL_Type*) &BLE->BLELL) /* 0x403C1000 */ #define BLE_BLESS ((BLE_BLESS_Type*) &BLE->BLESS) /* 0x403DF000 */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347bzi_bld54.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347bzi_bld54.h index cfcf1f97bd..6e70c26a52 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347bzi_bld54.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347bzi_bld54.h @@ -5,11 +5,11 @@ * CY8C6347BZI-BLD54 device header * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -461,43 +461,22 @@ typedef enum { #define CY_FLASH_SIZE 0x00100000UL #define CY_EM_EEPROM_BASE 0x14000000UL #define CY_EM_EEPROM_SIZE 0x00008000UL -#define CY_XIP_BASE 0x18000000UL -#define CY_XIP_SIZE 0x08000000UL #define CY_SFLASH_BASE 0x16000000UL #define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL #define CY_EFUSE_BASE 0x402C0800UL #define CY_EFUSE_SIZE 0x00000200UL #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXBLESS 1u +#define CY_IP_MXBLESS_INSTANCES 1u +#define CY_IP_MXBLESS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u @@ -507,12 +486,18 @@ typedef enum { #define CY_IP_MXCRYPTO 1u #define CY_IP_MXCRYPTO_INSTANCES 1u #define CY_IP_MXCRYPTO_VERSION 1u -#define CY_IP_MXBLESS 1u -#define CY_IP_MXBLESS_INSTANCES 1u -#define CY_IP_MXBLESS_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -528,24 +513,39 @@ typedef enum { #define CY_IP_MXS40PASS_CTB 1u #define CY_IP_MXS40PASS_CTB_INSTANCES 1u #define CY_IP_MXS40PASS_CTB_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u -#define CY_IP_MXUDB 1u -#define CY_IP_MXUDB_INSTANCES 1u -#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUDB 1u +#define CY_IP_MXUDB_INSTANCES 1u +#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_124_bga_sip.h" @@ -845,6 +845,7 @@ typedef enum { #define PROT_BASE 0x40240000UL #define PROT ((PROT_Type*) PROT_BASE) /* 0x40240000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ #define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40242000 */ #define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40242040 */ #define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40242080 */ @@ -861,23 +862,6 @@ typedef enum { #define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40242340 */ #define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40242380 */ #define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402423C0 */ -#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ -#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ -#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ -#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ -#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ -#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ -#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ -#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ -#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ -#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ -#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ -#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ -#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ -#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ -#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ -#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ -#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ #define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40244000 */ #define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40244400 */ #define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40244800 */ @@ -894,6 +878,22 @@ typedef enum { #define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40247400 */ #define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40247800 */ #define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40247C00 */ +#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ +#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ +#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ +#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ +#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ +#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ +#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ +#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ /******************************************************************************* * FLASHC @@ -1043,6 +1043,12 @@ typedef enum { #define UDB ((UDB_Type*) UDB_BASE) /* 0x40340000 */ #define UDB_WRKONE ((UDB_WRKONE_Type*) &UDB->WRKONE) /* 0x40340000 */ #define UDB_WRKMULT ((UDB_WRKMULT_Type*) &UDB->WRKMULT) /* 0x40341000 */ +#define UDB_UDBPAIR0 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[0]) /* 0x40342000 */ +#define UDB_UDBPAIR1 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[1]) /* 0x40342200 */ +#define UDB_UDBPAIR2 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[2]) /* 0x40342400 */ +#define UDB_UDBPAIR3 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[3]) /* 0x40342600 */ +#define UDB_UDBPAIR4 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[4]) /* 0x40342800 */ +#define UDB_UDBPAIR5 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[5]) /* 0x40342A00 */ #define UDB_UDBPAIR0_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[0].UDBSNG[0]) /* 0x40342000 */ #define UDB_UDBPAIR0_UDBSNG1 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[0].UDBSNG[1]) /* 0x40342080 */ #define UDB_UDBPAIR1_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[1].UDBSNG[0]) /* 0x40342200 */ @@ -1061,12 +1067,6 @@ typedef enum { #define UDB_UDBPAIR3_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[3].ROUTE) /* 0x40342700 */ #define UDB_UDBPAIR4_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[4].ROUTE) /* 0x40342900 */ #define UDB_UDBPAIR5_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[5].ROUTE) /* 0x40342B00 */ -#define UDB_UDBPAIR0 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[0]) /* 0x40342000 */ -#define UDB_UDBPAIR1 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[1]) /* 0x40342200 */ -#define UDB_UDBPAIR2 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[2]) /* 0x40342400 */ -#define UDB_UDBPAIR3 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[3]) /* 0x40342600 */ -#define UDB_UDBPAIR4 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[4]) /* 0x40342800 */ -#define UDB_UDBPAIR5 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[5]) /* 0x40342A00 */ #define UDB_DSI0 ((UDB_DSI_Type*) &UDB->DSI[0]) /* 0x40346000 */ #define UDB_DSI1 ((UDB_DSI_Type*) &UDB->DSI[1]) /* 0x40346080 */ #define UDB_DSI2 ((UDB_DSI_Type*) &UDB->DSI[2]) /* 0x40346100 */ @@ -1162,8 +1162,8 @@ typedef enum { #define BLE_BASE 0x403C0000UL #define BLE ((BLE_Type*) BLE_BASE) /* 0x403C0000 */ -#define BLE_RCB_RCBLL ((BLE_RCB_RCBLL_Type*) &BLE->RCB.RCBLL) /* 0x403C0100 */ #define BLE_RCB ((BLE_RCB_Type*) &BLE->RCB) /* 0x403C0000 */ +#define BLE_RCB_RCBLL ((BLE_RCB_RCBLL_Type*) &BLE->RCB.RCBLL) /* 0x403C0100 */ #define BLE_BLELL ((BLE_BLELL_Type*) &BLE->BLELL) /* 0x403C1000 */ #define BLE_BLESS ((BLE_BLESS_Type*) &BLE->BLESS) /* 0x403DF000 */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347bzi_bud33.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347bzi_bud33.h index c2bfc635ac..402957529e 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347bzi_bud33.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347bzi_bud33.h @@ -5,11 +5,11 @@ * CY8C6347BZI-BUD33 device header * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -461,55 +461,40 @@ typedef enum { #define CY_FLASH_SIZE 0x00100000UL #define CY_EM_EEPROM_BASE 0x14000000UL #define CY_EM_EEPROM_SIZE 0x00008000UL -#define CY_XIP_BASE 0x18000000UL -#define CY_XIP_SIZE 0x08000000UL #define CY_SFLASH_BASE 0x16000000UL #define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL #define CY_EFUSE_BASE 0x402C0800UL #define CY_EFUSE_SIZE 0x00000200UL #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXBLESS 1u +#define CY_IP_MXBLESS_INSTANCES 1u +#define CY_IP_MXBLESS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u #define CY_IP_M4CPUSS_DMA 1u #define CY_IP_M4CPUSS_DMA_INSTANCES 2u #define CY_IP_M4CPUSS_DMA_VERSION 1u -#define CY_IP_MXBLESS 1u -#define CY_IP_MXBLESS_INSTANCES 1u -#define CY_IP_MXBLESS_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -525,24 +510,39 @@ typedef enum { #define CY_IP_MXS40PASS_CTB 1u #define CY_IP_MXS40PASS_CTB_INSTANCES 1u #define CY_IP_MXS40PASS_CTB_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u -#define CY_IP_MXUDB 1u -#define CY_IP_MXUDB_INSTANCES 1u -#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUDB 1u +#define CY_IP_MXUDB_INSTANCES 1u +#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_116_bga_usb.h" @@ -835,6 +835,7 @@ typedef enum { #define PROT_BASE 0x40240000UL #define PROT ((PROT_Type*) PROT_BASE) /* 0x40240000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ #define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40242000 */ #define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40242040 */ #define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40242080 */ @@ -851,23 +852,6 @@ typedef enum { #define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40242340 */ #define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40242380 */ #define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402423C0 */ -#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ -#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ -#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ -#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ -#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ -#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ -#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ -#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ -#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ -#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ -#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ -#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ -#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ -#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ -#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ -#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ -#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ #define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40244000 */ #define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40244400 */ #define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40244800 */ @@ -884,6 +868,22 @@ typedef enum { #define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40247400 */ #define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40247800 */ #define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40247C00 */ +#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ +#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ +#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ +#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ +#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ +#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ +#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ +#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ /******************************************************************************* * FLASHC @@ -1033,6 +1033,12 @@ typedef enum { #define UDB ((UDB_Type*) UDB_BASE) /* 0x40340000 */ #define UDB_WRKONE ((UDB_WRKONE_Type*) &UDB->WRKONE) /* 0x40340000 */ #define UDB_WRKMULT ((UDB_WRKMULT_Type*) &UDB->WRKMULT) /* 0x40341000 */ +#define UDB_UDBPAIR0 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[0]) /* 0x40342000 */ +#define UDB_UDBPAIR1 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[1]) /* 0x40342200 */ +#define UDB_UDBPAIR2 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[2]) /* 0x40342400 */ +#define UDB_UDBPAIR3 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[3]) /* 0x40342600 */ +#define UDB_UDBPAIR4 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[4]) /* 0x40342800 */ +#define UDB_UDBPAIR5 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[5]) /* 0x40342A00 */ #define UDB_UDBPAIR0_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[0].UDBSNG[0]) /* 0x40342000 */ #define UDB_UDBPAIR0_UDBSNG1 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[0].UDBSNG[1]) /* 0x40342080 */ #define UDB_UDBPAIR1_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[1].UDBSNG[0]) /* 0x40342200 */ @@ -1051,12 +1057,6 @@ typedef enum { #define UDB_UDBPAIR3_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[3].ROUTE) /* 0x40342700 */ #define UDB_UDBPAIR4_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[4].ROUTE) /* 0x40342900 */ #define UDB_UDBPAIR5_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[5].ROUTE) /* 0x40342B00 */ -#define UDB_UDBPAIR0 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[0]) /* 0x40342000 */ -#define UDB_UDBPAIR1 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[1]) /* 0x40342200 */ -#define UDB_UDBPAIR2 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[2]) /* 0x40342400 */ -#define UDB_UDBPAIR3 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[3]) /* 0x40342600 */ -#define UDB_UDBPAIR4 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[4]) /* 0x40342800 */ -#define UDB_UDBPAIR5 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[5]) /* 0x40342A00 */ #define UDB_DSI0 ((UDB_DSI_Type*) &UDB->DSI[0]) /* 0x40346000 */ #define UDB_DSI1 ((UDB_DSI_Type*) &UDB->DSI[1]) /* 0x40346080 */ #define UDB_DSI2 ((UDB_DSI_Type*) &UDB->DSI[2]) /* 0x40346100 */ @@ -1152,8 +1152,8 @@ typedef enum { #define BLE_BASE 0x403C0000UL #define BLE ((BLE_Type*) BLE_BASE) /* 0x403C0000 */ -#define BLE_RCB_RCBLL ((BLE_RCB_RCBLL_Type*) &BLE->RCB.RCBLL) /* 0x403C0100 */ #define BLE_RCB ((BLE_RCB_Type*) &BLE->RCB) /* 0x403C0000 */ +#define BLE_RCB_RCBLL ((BLE_RCB_RCBLL_Type*) &BLE->RCB.RCBLL) /* 0x403C0100 */ #define BLE_BLELL ((BLE_BLELL_Type*) &BLE->BLELL) /* 0x403C1000 */ #define BLE_BLESS ((BLE_BLESS_Type*) &BLE->BLESS) /* 0x403DF000 */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347bzi_bud43.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347bzi_bud43.h index 1003651c50..8e1bdee8fe 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347bzi_bud43.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347bzi_bud43.h @@ -5,11 +5,11 @@ * CY8C6347BZI-BUD43 device header * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -461,43 +461,22 @@ typedef enum { #define CY_FLASH_SIZE 0x00100000UL #define CY_EM_EEPROM_BASE 0x14000000UL #define CY_EM_EEPROM_SIZE 0x00008000UL -#define CY_XIP_BASE 0x18000000UL -#define CY_XIP_SIZE 0x08000000UL #define CY_SFLASH_BASE 0x16000000UL #define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL #define CY_EFUSE_BASE 0x402C0800UL #define CY_EFUSE_SIZE 0x00000200UL #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXBLESS 1u +#define CY_IP_MXBLESS_INSTANCES 1u +#define CY_IP_MXBLESS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u @@ -507,12 +486,18 @@ typedef enum { #define CY_IP_MXCRYPTO 1u #define CY_IP_MXCRYPTO_INSTANCES 1u #define CY_IP_MXCRYPTO_VERSION 1u -#define CY_IP_MXBLESS 1u -#define CY_IP_MXBLESS_INSTANCES 1u -#define CY_IP_MXBLESS_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -525,21 +510,36 @@ typedef enum { #define CY_IP_MXS40PASS_CTDAC 1u #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u #define CY_IP_MXS40PASS_CTDAC_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_116_bga_usb.h" @@ -839,6 +839,7 @@ typedef enum { #define PROT_BASE 0x40240000UL #define PROT ((PROT_Type*) PROT_BASE) /* 0x40240000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ #define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40242000 */ #define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40242040 */ #define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40242080 */ @@ -855,23 +856,6 @@ typedef enum { #define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40242340 */ #define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40242380 */ #define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402423C0 */ -#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ -#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ -#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ -#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ -#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ -#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ -#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ -#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ -#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ -#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ -#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ -#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ -#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ -#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ -#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ -#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ -#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ #define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40244000 */ #define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40244400 */ #define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40244800 */ @@ -888,6 +872,22 @@ typedef enum { #define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40247400 */ #define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40247800 */ #define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40247C00 */ +#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ +#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ +#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ +#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ +#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ +#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ +#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ +#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ /******************************************************************************* * FLASHC @@ -1097,8 +1097,8 @@ typedef enum { #define BLE_BASE 0x403C0000UL #define BLE ((BLE_Type*) BLE_BASE) /* 0x403C0000 */ -#define BLE_RCB_RCBLL ((BLE_RCB_RCBLL_Type*) &BLE->RCB.RCBLL) /* 0x403C0100 */ #define BLE_RCB ((BLE_RCB_Type*) &BLE->RCB) /* 0x403C0000 */ +#define BLE_RCB_RCBLL ((BLE_RCB_RCBLL_Type*) &BLE->RCB.RCBLL) /* 0x403C0100 */ #define BLE_BLELL ((BLE_BLELL_Type*) &BLE->BLELL) /* 0x403C1000 */ #define BLE_BLESS ((BLE_BLESS_Type*) &BLE->BLESS) /* 0x403DF000 */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347bzi_bud53.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347bzi_bud53.h index 143148652f..08ce89c475 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347bzi_bud53.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347bzi_bud53.h @@ -5,11 +5,11 @@ * CY8C6347BZI-BUD53 device header * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -461,43 +461,22 @@ typedef enum { #define CY_FLASH_SIZE 0x00100000UL #define CY_EM_EEPROM_BASE 0x14000000UL #define CY_EM_EEPROM_SIZE 0x00008000UL -#define CY_XIP_BASE 0x18000000UL -#define CY_XIP_SIZE 0x08000000UL #define CY_SFLASH_BASE 0x16000000UL #define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL #define CY_EFUSE_BASE 0x402C0800UL #define CY_EFUSE_SIZE 0x00000200UL #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXBLESS 1u +#define CY_IP_MXBLESS_INSTANCES 1u +#define CY_IP_MXBLESS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u @@ -507,12 +486,18 @@ typedef enum { #define CY_IP_MXCRYPTO 1u #define CY_IP_MXCRYPTO_INSTANCES 1u #define CY_IP_MXCRYPTO_VERSION 1u -#define CY_IP_MXBLESS 1u -#define CY_IP_MXBLESS_INSTANCES 1u -#define CY_IP_MXBLESS_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -528,24 +513,39 @@ typedef enum { #define CY_IP_MXS40PASS_CTB 1u #define CY_IP_MXS40PASS_CTB_INSTANCES 1u #define CY_IP_MXS40PASS_CTB_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u -#define CY_IP_MXUDB 1u -#define CY_IP_MXUDB_INSTANCES 1u -#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUDB 1u +#define CY_IP_MXUDB_INSTANCES 1u +#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_116_bga_usb.h" @@ -845,6 +845,7 @@ typedef enum { #define PROT_BASE 0x40240000UL #define PROT ((PROT_Type*) PROT_BASE) /* 0x40240000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ #define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40242000 */ #define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40242040 */ #define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40242080 */ @@ -861,23 +862,6 @@ typedef enum { #define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40242340 */ #define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40242380 */ #define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402423C0 */ -#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ -#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ -#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ -#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ -#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ -#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ -#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ -#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ -#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ -#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ -#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ -#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ -#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ -#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ -#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ -#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ -#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ #define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40244000 */ #define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40244400 */ #define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40244800 */ @@ -894,6 +878,22 @@ typedef enum { #define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40247400 */ #define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40247800 */ #define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40247C00 */ +#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ +#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ +#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ +#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ +#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ +#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ +#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ +#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ /******************************************************************************* * FLASHC @@ -1043,6 +1043,12 @@ typedef enum { #define UDB ((UDB_Type*) UDB_BASE) /* 0x40340000 */ #define UDB_WRKONE ((UDB_WRKONE_Type*) &UDB->WRKONE) /* 0x40340000 */ #define UDB_WRKMULT ((UDB_WRKMULT_Type*) &UDB->WRKMULT) /* 0x40341000 */ +#define UDB_UDBPAIR0 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[0]) /* 0x40342000 */ +#define UDB_UDBPAIR1 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[1]) /* 0x40342200 */ +#define UDB_UDBPAIR2 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[2]) /* 0x40342400 */ +#define UDB_UDBPAIR3 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[3]) /* 0x40342600 */ +#define UDB_UDBPAIR4 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[4]) /* 0x40342800 */ +#define UDB_UDBPAIR5 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[5]) /* 0x40342A00 */ #define UDB_UDBPAIR0_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[0].UDBSNG[0]) /* 0x40342000 */ #define UDB_UDBPAIR0_UDBSNG1 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[0].UDBSNG[1]) /* 0x40342080 */ #define UDB_UDBPAIR1_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[1].UDBSNG[0]) /* 0x40342200 */ @@ -1061,12 +1067,6 @@ typedef enum { #define UDB_UDBPAIR3_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[3].ROUTE) /* 0x40342700 */ #define UDB_UDBPAIR4_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[4].ROUTE) /* 0x40342900 */ #define UDB_UDBPAIR5_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[5].ROUTE) /* 0x40342B00 */ -#define UDB_UDBPAIR0 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[0]) /* 0x40342000 */ -#define UDB_UDBPAIR1 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[1]) /* 0x40342200 */ -#define UDB_UDBPAIR2 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[2]) /* 0x40342400 */ -#define UDB_UDBPAIR3 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[3]) /* 0x40342600 */ -#define UDB_UDBPAIR4 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[4]) /* 0x40342800 */ -#define UDB_UDBPAIR5 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[5]) /* 0x40342A00 */ #define UDB_DSI0 ((UDB_DSI_Type*) &UDB->DSI[0]) /* 0x40346000 */ #define UDB_DSI1 ((UDB_DSI_Type*) &UDB->DSI[1]) /* 0x40346080 */ #define UDB_DSI2 ((UDB_DSI_Type*) &UDB->DSI[2]) /* 0x40346100 */ @@ -1162,8 +1162,8 @@ typedef enum { #define BLE_BASE 0x403C0000UL #define BLE ((BLE_Type*) BLE_BASE) /* 0x403C0000 */ -#define BLE_RCB_RCBLL ((BLE_RCB_RCBLL_Type*) &BLE->RCB.RCBLL) /* 0x403C0100 */ #define BLE_RCB ((BLE_RCB_Type*) &BLE->RCB) /* 0x403C0000 */ +#define BLE_RCB_RCBLL ((BLE_RCB_RCBLL_Type*) &BLE->RCB.RCBLL) /* 0x403C0100 */ #define BLE_BLELL ((BLE_BLELL_Type*) &BLE->BLELL) /* 0x403C1000 */ #define BLE_BLESS ((BLE_BLESS_Type*) &BLE->BLESS) /* 0x403DF000 */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347fmi_bld13.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347fmi_bld13.h index ed06b84da9..d647245770 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347fmi_bld13.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347fmi_bld13.h @@ -5,11 +5,11 @@ * CY8C6347FMI-BLD13 device header * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -461,55 +461,40 @@ typedef enum { #define CY_FLASH_SIZE 0x00100000UL #define CY_EM_EEPROM_BASE 0x14000000UL #define CY_EM_EEPROM_SIZE 0x00008000UL -#define CY_XIP_BASE 0x18000000UL -#define CY_XIP_SIZE 0x08000000UL #define CY_SFLASH_BASE 0x16000000UL #define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL #define CY_EFUSE_BASE 0x402C0800UL #define CY_EFUSE_SIZE 0x00000200UL #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXBLESS 1u +#define CY_IP_MXBLESS_INSTANCES 1u +#define CY_IP_MXBLESS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u #define CY_IP_M4CPUSS_DMA 1u #define CY_IP_M4CPUSS_DMA_INSTANCES 2u #define CY_IP_M4CPUSS_DMA_VERSION 1u -#define CY_IP_MXBLESS 1u -#define CY_IP_MXBLESS_INSTANCES 1u -#define CY_IP_MXBLESS_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -522,18 +507,33 @@ typedef enum { #define CY_IP_MXS40PASS_CTDAC 1u #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u #define CY_IP_MXS40PASS_CTDAC_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_104_m_csp_ble.h" @@ -826,6 +826,7 @@ typedef enum { #define PROT_BASE 0x40240000UL #define PROT ((PROT_Type*) PROT_BASE) /* 0x40240000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ #define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40242000 */ #define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40242040 */ #define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40242080 */ @@ -842,23 +843,6 @@ typedef enum { #define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40242340 */ #define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40242380 */ #define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402423C0 */ -#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ -#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ -#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ -#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ -#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ -#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ -#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ -#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ -#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ -#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ -#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ -#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ -#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ -#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ -#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ -#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ -#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ #define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40244000 */ #define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40244400 */ #define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40244800 */ @@ -875,6 +859,22 @@ typedef enum { #define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40247400 */ #define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40247800 */ #define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40247C00 */ +#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ +#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ +#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ +#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ +#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ +#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ +#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ +#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ /******************************************************************************* * FLASHC @@ -1084,8 +1084,8 @@ typedef enum { #define BLE_BASE 0x403C0000UL #define BLE ((BLE_Type*) BLE_BASE) /* 0x403C0000 */ -#define BLE_RCB_RCBLL ((BLE_RCB_RCBLL_Type*) &BLE->RCB.RCBLL) /* 0x403C0100 */ #define BLE_RCB ((BLE_RCB_Type*) &BLE->RCB) /* 0x403C0000 */ +#define BLE_RCB_RCBLL ((BLE_RCB_RCBLL_Type*) &BLE->RCB.RCBLL) /* 0x403C0100 */ #define BLE_BLELL ((BLE_BLELL_Type*) &BLE->BLELL) /* 0x403C1000 */ #define BLE_BLESS ((BLE_BLESS_Type*) &BLE->BLESS) /* 0x403DF000 */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347fmi_bld33.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347fmi_bld33.h index bbaf7a4932..80c44d62b8 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347fmi_bld33.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347fmi_bld33.h @@ -5,11 +5,11 @@ * CY8C6347FMI-BLD33 device header * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -461,55 +461,40 @@ typedef enum { #define CY_FLASH_SIZE 0x00100000UL #define CY_EM_EEPROM_BASE 0x14000000UL #define CY_EM_EEPROM_SIZE 0x00008000UL -#define CY_XIP_BASE 0x18000000UL -#define CY_XIP_SIZE 0x08000000UL #define CY_SFLASH_BASE 0x16000000UL #define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL #define CY_EFUSE_BASE 0x402C0800UL #define CY_EFUSE_SIZE 0x00000200UL #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXBLESS 1u +#define CY_IP_MXBLESS_INSTANCES 1u +#define CY_IP_MXBLESS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u #define CY_IP_M4CPUSS_DMA 1u #define CY_IP_M4CPUSS_DMA_INSTANCES 2u #define CY_IP_M4CPUSS_DMA_VERSION 1u -#define CY_IP_MXBLESS 1u -#define CY_IP_MXBLESS_INSTANCES 1u -#define CY_IP_MXBLESS_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -525,21 +510,36 @@ typedef enum { #define CY_IP_MXS40PASS_CTB 1u #define CY_IP_MXS40PASS_CTB_INSTANCES 1u #define CY_IP_MXS40PASS_CTB_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u -#define CY_IP_MXUDB 1u -#define CY_IP_MXUDB_INSTANCES 1u -#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUDB 1u +#define CY_IP_MXUDB_INSTANCES 1u +#define CY_IP_MXUDB_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_104_m_csp_ble.h" @@ -832,6 +832,7 @@ typedef enum { #define PROT_BASE 0x40240000UL #define PROT ((PROT_Type*) PROT_BASE) /* 0x40240000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ #define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40242000 */ #define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40242040 */ #define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40242080 */ @@ -848,23 +849,6 @@ typedef enum { #define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40242340 */ #define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40242380 */ #define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402423C0 */ -#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ -#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ -#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ -#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ -#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ -#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ -#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ -#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ -#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ -#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ -#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ -#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ -#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ -#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ -#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ -#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ -#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ #define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40244000 */ #define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40244400 */ #define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40244800 */ @@ -881,6 +865,22 @@ typedef enum { #define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40247400 */ #define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40247800 */ #define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40247C00 */ +#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ +#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ +#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ +#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ +#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ +#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ +#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ +#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ /******************************************************************************* * FLASHC @@ -1030,6 +1030,12 @@ typedef enum { #define UDB ((UDB_Type*) UDB_BASE) /* 0x40340000 */ #define UDB_WRKONE ((UDB_WRKONE_Type*) &UDB->WRKONE) /* 0x40340000 */ #define UDB_WRKMULT ((UDB_WRKMULT_Type*) &UDB->WRKMULT) /* 0x40341000 */ +#define UDB_UDBPAIR0 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[0]) /* 0x40342000 */ +#define UDB_UDBPAIR1 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[1]) /* 0x40342200 */ +#define UDB_UDBPAIR2 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[2]) /* 0x40342400 */ +#define UDB_UDBPAIR3 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[3]) /* 0x40342600 */ +#define UDB_UDBPAIR4 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[4]) /* 0x40342800 */ +#define UDB_UDBPAIR5 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[5]) /* 0x40342A00 */ #define UDB_UDBPAIR0_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[0].UDBSNG[0]) /* 0x40342000 */ #define UDB_UDBPAIR0_UDBSNG1 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[0].UDBSNG[1]) /* 0x40342080 */ #define UDB_UDBPAIR1_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[1].UDBSNG[0]) /* 0x40342200 */ @@ -1048,12 +1054,6 @@ typedef enum { #define UDB_UDBPAIR3_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[3].ROUTE) /* 0x40342700 */ #define UDB_UDBPAIR4_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[4].ROUTE) /* 0x40342900 */ #define UDB_UDBPAIR5_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[5].ROUTE) /* 0x40342B00 */ -#define UDB_UDBPAIR0 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[0]) /* 0x40342000 */ -#define UDB_UDBPAIR1 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[1]) /* 0x40342200 */ -#define UDB_UDBPAIR2 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[2]) /* 0x40342400 */ -#define UDB_UDBPAIR3 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[3]) /* 0x40342600 */ -#define UDB_UDBPAIR4 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[4]) /* 0x40342800 */ -#define UDB_UDBPAIR5 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[5]) /* 0x40342A00 */ #define UDB_DSI0 ((UDB_DSI_Type*) &UDB->DSI[0]) /* 0x40346000 */ #define UDB_DSI1 ((UDB_DSI_Type*) &UDB->DSI[1]) /* 0x40346080 */ #define UDB_DSI2 ((UDB_DSI_Type*) &UDB->DSI[2]) /* 0x40346100 */ @@ -1149,8 +1149,8 @@ typedef enum { #define BLE_BASE 0x403C0000UL #define BLE ((BLE_Type*) BLE_BASE) /* 0x403C0000 */ -#define BLE_RCB_RCBLL ((BLE_RCB_RCBLL_Type*) &BLE->RCB.RCBLL) /* 0x403C0100 */ #define BLE_RCB ((BLE_RCB_Type*) &BLE->RCB) /* 0x403C0000 */ +#define BLE_RCB_RCBLL ((BLE_RCB_RCBLL_Type*) &BLE->RCB.RCBLL) /* 0x403C0100 */ #define BLE_BLELL ((BLE_BLELL_Type*) &BLE->BLELL) /* 0x403C1000 */ #define BLE_BLESS ((BLE_BLESS_Type*) &BLE->BLESS) /* 0x403DF000 */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347fmi_bld43.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347fmi_bld43.h index 509766848f..ac8e465794 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347fmi_bld43.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347fmi_bld43.h @@ -5,11 +5,11 @@ * CY8C6347FMI-BLD43 device header * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -461,43 +461,22 @@ typedef enum { #define CY_FLASH_SIZE 0x00100000UL #define CY_EM_EEPROM_BASE 0x14000000UL #define CY_EM_EEPROM_SIZE 0x00008000UL -#define CY_XIP_BASE 0x18000000UL -#define CY_XIP_SIZE 0x08000000UL #define CY_SFLASH_BASE 0x16000000UL #define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL #define CY_EFUSE_BASE 0x402C0800UL #define CY_EFUSE_SIZE 0x00000200UL #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXBLESS 1u +#define CY_IP_MXBLESS_INSTANCES 1u +#define CY_IP_MXBLESS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u @@ -507,12 +486,18 @@ typedef enum { #define CY_IP_MXCRYPTO 1u #define CY_IP_MXCRYPTO_INSTANCES 1u #define CY_IP_MXCRYPTO_VERSION 1u -#define CY_IP_MXBLESS 1u -#define CY_IP_MXBLESS_INSTANCES 1u -#define CY_IP_MXBLESS_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -525,18 +510,33 @@ typedef enum { #define CY_IP_MXS40PASS_CTDAC 1u #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u #define CY_IP_MXS40PASS_CTDAC_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_104_m_csp_ble.h" @@ -836,6 +836,7 @@ typedef enum { #define PROT_BASE 0x40240000UL #define PROT ((PROT_Type*) PROT_BASE) /* 0x40240000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ #define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40242000 */ #define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40242040 */ #define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40242080 */ @@ -852,23 +853,6 @@ typedef enum { #define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40242340 */ #define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40242380 */ #define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402423C0 */ -#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ -#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ -#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ -#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ -#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ -#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ -#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ -#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ -#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ -#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ -#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ -#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ -#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ -#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ -#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ -#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ -#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ #define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40244000 */ #define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40244400 */ #define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40244800 */ @@ -885,6 +869,22 @@ typedef enum { #define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40247400 */ #define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40247800 */ #define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40247C00 */ +#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ +#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ +#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ +#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ +#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ +#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ +#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ +#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ /******************************************************************************* * FLASHC @@ -1094,8 +1094,8 @@ typedef enum { #define BLE_BASE 0x403C0000UL #define BLE ((BLE_Type*) BLE_BASE) /* 0x403C0000 */ -#define BLE_RCB_RCBLL ((BLE_RCB_RCBLL_Type*) &BLE->RCB.RCBLL) /* 0x403C0100 */ #define BLE_RCB ((BLE_RCB_Type*) &BLE->RCB) /* 0x403C0000 */ +#define BLE_RCB_RCBLL ((BLE_RCB_RCBLL_Type*) &BLE->RCB.RCBLL) /* 0x403C0100 */ #define BLE_BLELL ((BLE_BLELL_Type*) &BLE->BLELL) /* 0x403C1000 */ #define BLE_BLESS ((BLE_BLESS_Type*) &BLE->BLESS) /* 0x403DF000 */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347fmi_bld53.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347fmi_bld53.h index f4f1b46e37..1051f9ed75 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347fmi_bld53.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347fmi_bld53.h @@ -5,11 +5,11 @@ * CY8C6347FMI-BLD53 device header * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -461,43 +461,22 @@ typedef enum { #define CY_FLASH_SIZE 0x00100000UL #define CY_EM_EEPROM_BASE 0x14000000UL #define CY_EM_EEPROM_SIZE 0x00008000UL -#define CY_XIP_BASE 0x18000000UL -#define CY_XIP_SIZE 0x08000000UL #define CY_SFLASH_BASE 0x16000000UL #define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL #define CY_EFUSE_BASE 0x402C0800UL #define CY_EFUSE_SIZE 0x00000200UL #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXBLESS 1u +#define CY_IP_MXBLESS_INSTANCES 1u +#define CY_IP_MXBLESS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u @@ -507,12 +486,18 @@ typedef enum { #define CY_IP_MXCRYPTO 1u #define CY_IP_MXCRYPTO_INSTANCES 1u #define CY_IP_MXCRYPTO_VERSION 1u -#define CY_IP_MXBLESS 1u -#define CY_IP_MXBLESS_INSTANCES 1u -#define CY_IP_MXBLESS_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -528,21 +513,36 @@ typedef enum { #define CY_IP_MXS40PASS_CTB 1u #define CY_IP_MXS40PASS_CTB_INSTANCES 1u #define CY_IP_MXS40PASS_CTB_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u -#define CY_IP_MXUDB 1u -#define CY_IP_MXUDB_INSTANCES 1u -#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUDB 1u +#define CY_IP_MXUDB_INSTANCES 1u +#define CY_IP_MXUDB_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_104_m_csp_ble.h" @@ -842,6 +842,7 @@ typedef enum { #define PROT_BASE 0x40240000UL #define PROT ((PROT_Type*) PROT_BASE) /* 0x40240000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ #define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40242000 */ #define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40242040 */ #define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40242080 */ @@ -858,23 +859,6 @@ typedef enum { #define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40242340 */ #define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40242380 */ #define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402423C0 */ -#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ -#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ -#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ -#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ -#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ -#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ -#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ -#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ -#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ -#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ -#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ -#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ -#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ -#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ -#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ -#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ -#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ #define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40244000 */ #define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40244400 */ #define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40244800 */ @@ -891,6 +875,22 @@ typedef enum { #define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40247400 */ #define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40247800 */ #define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40247C00 */ +#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ +#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ +#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ +#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ +#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ +#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ +#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ +#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ /******************************************************************************* * FLASHC @@ -1040,6 +1040,12 @@ typedef enum { #define UDB ((UDB_Type*) UDB_BASE) /* 0x40340000 */ #define UDB_WRKONE ((UDB_WRKONE_Type*) &UDB->WRKONE) /* 0x40340000 */ #define UDB_WRKMULT ((UDB_WRKMULT_Type*) &UDB->WRKMULT) /* 0x40341000 */ +#define UDB_UDBPAIR0 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[0]) /* 0x40342000 */ +#define UDB_UDBPAIR1 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[1]) /* 0x40342200 */ +#define UDB_UDBPAIR2 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[2]) /* 0x40342400 */ +#define UDB_UDBPAIR3 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[3]) /* 0x40342600 */ +#define UDB_UDBPAIR4 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[4]) /* 0x40342800 */ +#define UDB_UDBPAIR5 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[5]) /* 0x40342A00 */ #define UDB_UDBPAIR0_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[0].UDBSNG[0]) /* 0x40342000 */ #define UDB_UDBPAIR0_UDBSNG1 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[0].UDBSNG[1]) /* 0x40342080 */ #define UDB_UDBPAIR1_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[1].UDBSNG[0]) /* 0x40342200 */ @@ -1058,12 +1064,6 @@ typedef enum { #define UDB_UDBPAIR3_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[3].ROUTE) /* 0x40342700 */ #define UDB_UDBPAIR4_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[4].ROUTE) /* 0x40342900 */ #define UDB_UDBPAIR5_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[5].ROUTE) /* 0x40342B00 */ -#define UDB_UDBPAIR0 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[0]) /* 0x40342000 */ -#define UDB_UDBPAIR1 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[1]) /* 0x40342200 */ -#define UDB_UDBPAIR2 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[2]) /* 0x40342400 */ -#define UDB_UDBPAIR3 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[3]) /* 0x40342600 */ -#define UDB_UDBPAIR4 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[4]) /* 0x40342800 */ -#define UDB_UDBPAIR5 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[5]) /* 0x40342A00 */ #define UDB_DSI0 ((UDB_DSI_Type*) &UDB->DSI[0]) /* 0x40346000 */ #define UDB_DSI1 ((UDB_DSI_Type*) &UDB->DSI[1]) /* 0x40346080 */ #define UDB_DSI2 ((UDB_DSI_Type*) &UDB->DSI[2]) /* 0x40346100 */ @@ -1159,8 +1159,8 @@ typedef enum { #define BLE_BASE 0x403C0000UL #define BLE ((BLE_Type*) BLE_BASE) /* 0x403C0000 */ -#define BLE_RCB_RCBLL ((BLE_RCB_RCBLL_Type*) &BLE->RCB.RCBLL) /* 0x403C0100 */ #define BLE_RCB ((BLE_RCB_Type*) &BLE->RCB) /* 0x403C0000 */ +#define BLE_RCB_RCBLL ((BLE_RCB_RCBLL_Type*) &BLE->RCB.RCBLL) /* 0x403C0100 */ #define BLE_BLELL ((BLE_BLELL_Type*) &BLE->BLELL) /* 0x403C1000 */ #define BLE_BLESS ((BLE_BLESS_Type*) &BLE->BLESS) /* 0x403DF000 */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347fmi_bud13.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347fmi_bud13.h index 8174405abb..9c574a3ff0 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347fmi_bud13.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347fmi_bud13.h @@ -5,11 +5,11 @@ * CY8C6347FMI-BUD13 device header * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -461,55 +461,40 @@ typedef enum { #define CY_FLASH_SIZE 0x00100000UL #define CY_EM_EEPROM_BASE 0x14000000UL #define CY_EM_EEPROM_SIZE 0x00008000UL -#define CY_XIP_BASE 0x18000000UL -#define CY_XIP_SIZE 0x08000000UL #define CY_SFLASH_BASE 0x16000000UL #define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL #define CY_EFUSE_BASE 0x402C0800UL #define CY_EFUSE_SIZE 0x00000200UL #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXBLESS 1u +#define CY_IP_MXBLESS_INSTANCES 1u +#define CY_IP_MXBLESS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u #define CY_IP_M4CPUSS_DMA 1u #define CY_IP_M4CPUSS_DMA_INSTANCES 2u #define CY_IP_M4CPUSS_DMA_VERSION 1u -#define CY_IP_MXBLESS 1u -#define CY_IP_MXBLESS_INSTANCES 1u -#define CY_IP_MXBLESS_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -522,21 +507,36 @@ typedef enum { #define CY_IP_MXS40PASS_CTDAC 1u #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u #define CY_IP_MXS40PASS_CTDAC_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_104_m_csp_ble_usb.h" @@ -829,6 +829,7 @@ typedef enum { #define PROT_BASE 0x40240000UL #define PROT ((PROT_Type*) PROT_BASE) /* 0x40240000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ #define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40242000 */ #define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40242040 */ #define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40242080 */ @@ -845,23 +846,6 @@ typedef enum { #define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40242340 */ #define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40242380 */ #define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402423C0 */ -#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ -#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ -#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ -#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ -#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ -#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ -#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ -#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ -#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ -#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ -#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ -#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ -#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ -#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ -#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ -#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ -#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ #define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40244000 */ #define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40244400 */ #define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40244800 */ @@ -878,6 +862,22 @@ typedef enum { #define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40247400 */ #define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40247800 */ #define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40247C00 */ +#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ +#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ +#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ +#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ +#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ +#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ +#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ +#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ /******************************************************************************* * FLASHC @@ -1087,8 +1087,8 @@ typedef enum { #define BLE_BASE 0x403C0000UL #define BLE ((BLE_Type*) BLE_BASE) /* 0x403C0000 */ -#define BLE_RCB_RCBLL ((BLE_RCB_RCBLL_Type*) &BLE->RCB.RCBLL) /* 0x403C0100 */ #define BLE_RCB ((BLE_RCB_Type*) &BLE->RCB) /* 0x403C0000 */ +#define BLE_RCB_RCBLL ((BLE_RCB_RCBLL_Type*) &BLE->RCB.RCBLL) /* 0x403C0100 */ #define BLE_BLELL ((BLE_BLELL_Type*) &BLE->BLELL) /* 0x403C1000 */ #define BLE_BLESS ((BLE_BLESS_Type*) &BLE->BLESS) /* 0x403DF000 */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347fmi_bud33.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347fmi_bud33.h index 4ff212251e..537c5fbfcf 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347fmi_bud33.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347fmi_bud33.h @@ -5,11 +5,11 @@ * CY8C6347FMI-BUD33 device header * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -461,55 +461,40 @@ typedef enum { #define CY_FLASH_SIZE 0x00100000UL #define CY_EM_EEPROM_BASE 0x14000000UL #define CY_EM_EEPROM_SIZE 0x00008000UL -#define CY_XIP_BASE 0x18000000UL -#define CY_XIP_SIZE 0x08000000UL #define CY_SFLASH_BASE 0x16000000UL #define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL #define CY_EFUSE_BASE 0x402C0800UL #define CY_EFUSE_SIZE 0x00000200UL #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXBLESS 1u +#define CY_IP_MXBLESS_INSTANCES 1u +#define CY_IP_MXBLESS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u #define CY_IP_M4CPUSS_DMA 1u #define CY_IP_M4CPUSS_DMA_INSTANCES 2u #define CY_IP_M4CPUSS_DMA_VERSION 1u -#define CY_IP_MXBLESS 1u -#define CY_IP_MXBLESS_INSTANCES 1u -#define CY_IP_MXBLESS_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -525,24 +510,39 @@ typedef enum { #define CY_IP_MXS40PASS_CTB 1u #define CY_IP_MXS40PASS_CTB_INSTANCES 1u #define CY_IP_MXS40PASS_CTB_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u -#define CY_IP_MXUDB 1u -#define CY_IP_MXUDB_INSTANCES 1u -#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUDB 1u +#define CY_IP_MXUDB_INSTANCES 1u +#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_104_m_csp_ble_usb.h" @@ -835,6 +835,7 @@ typedef enum { #define PROT_BASE 0x40240000UL #define PROT ((PROT_Type*) PROT_BASE) /* 0x40240000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ #define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40242000 */ #define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40242040 */ #define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40242080 */ @@ -851,23 +852,6 @@ typedef enum { #define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40242340 */ #define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40242380 */ #define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402423C0 */ -#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ -#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ -#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ -#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ -#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ -#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ -#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ -#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ -#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ -#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ -#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ -#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ -#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ -#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ -#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ -#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ -#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ #define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40244000 */ #define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40244400 */ #define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40244800 */ @@ -884,6 +868,22 @@ typedef enum { #define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40247400 */ #define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40247800 */ #define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40247C00 */ +#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ +#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ +#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ +#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ +#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ +#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ +#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ +#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ /******************************************************************************* * FLASHC @@ -1033,6 +1033,12 @@ typedef enum { #define UDB ((UDB_Type*) UDB_BASE) /* 0x40340000 */ #define UDB_WRKONE ((UDB_WRKONE_Type*) &UDB->WRKONE) /* 0x40340000 */ #define UDB_WRKMULT ((UDB_WRKMULT_Type*) &UDB->WRKMULT) /* 0x40341000 */ +#define UDB_UDBPAIR0 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[0]) /* 0x40342000 */ +#define UDB_UDBPAIR1 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[1]) /* 0x40342200 */ +#define UDB_UDBPAIR2 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[2]) /* 0x40342400 */ +#define UDB_UDBPAIR3 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[3]) /* 0x40342600 */ +#define UDB_UDBPAIR4 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[4]) /* 0x40342800 */ +#define UDB_UDBPAIR5 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[5]) /* 0x40342A00 */ #define UDB_UDBPAIR0_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[0].UDBSNG[0]) /* 0x40342000 */ #define UDB_UDBPAIR0_UDBSNG1 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[0].UDBSNG[1]) /* 0x40342080 */ #define UDB_UDBPAIR1_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[1].UDBSNG[0]) /* 0x40342200 */ @@ -1051,12 +1057,6 @@ typedef enum { #define UDB_UDBPAIR3_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[3].ROUTE) /* 0x40342700 */ #define UDB_UDBPAIR4_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[4].ROUTE) /* 0x40342900 */ #define UDB_UDBPAIR5_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[5].ROUTE) /* 0x40342B00 */ -#define UDB_UDBPAIR0 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[0]) /* 0x40342000 */ -#define UDB_UDBPAIR1 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[1]) /* 0x40342200 */ -#define UDB_UDBPAIR2 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[2]) /* 0x40342400 */ -#define UDB_UDBPAIR3 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[3]) /* 0x40342600 */ -#define UDB_UDBPAIR4 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[4]) /* 0x40342800 */ -#define UDB_UDBPAIR5 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[5]) /* 0x40342A00 */ #define UDB_DSI0 ((UDB_DSI_Type*) &UDB->DSI[0]) /* 0x40346000 */ #define UDB_DSI1 ((UDB_DSI_Type*) &UDB->DSI[1]) /* 0x40346080 */ #define UDB_DSI2 ((UDB_DSI_Type*) &UDB->DSI[2]) /* 0x40346100 */ @@ -1152,8 +1152,8 @@ typedef enum { #define BLE_BASE 0x403C0000UL #define BLE ((BLE_Type*) BLE_BASE) /* 0x403C0000 */ -#define BLE_RCB_RCBLL ((BLE_RCB_RCBLL_Type*) &BLE->RCB.RCBLL) /* 0x403C0100 */ #define BLE_RCB ((BLE_RCB_Type*) &BLE->RCB) /* 0x403C0000 */ +#define BLE_RCB_RCBLL ((BLE_RCB_RCBLL_Type*) &BLE->RCB.RCBLL) /* 0x403C0100 */ #define BLE_BLELL ((BLE_BLELL_Type*) &BLE->BLELL) /* 0x403C1000 */ #define BLE_BLESS ((BLE_BLESS_Type*) &BLE->BLESS) /* 0x403DF000 */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347fmi_bud43.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347fmi_bud43.h index 0de797b435..6037d7c552 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347fmi_bud43.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347fmi_bud43.h @@ -5,11 +5,11 @@ * CY8C6347FMI-BUD43 device header * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -461,43 +461,22 @@ typedef enum { #define CY_FLASH_SIZE 0x00100000UL #define CY_EM_EEPROM_BASE 0x14000000UL #define CY_EM_EEPROM_SIZE 0x00008000UL -#define CY_XIP_BASE 0x18000000UL -#define CY_XIP_SIZE 0x08000000UL #define CY_SFLASH_BASE 0x16000000UL #define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL #define CY_EFUSE_BASE 0x402C0800UL #define CY_EFUSE_SIZE 0x00000200UL #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXBLESS 1u +#define CY_IP_MXBLESS_INSTANCES 1u +#define CY_IP_MXBLESS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u @@ -507,12 +486,18 @@ typedef enum { #define CY_IP_MXCRYPTO 1u #define CY_IP_MXCRYPTO_INSTANCES 1u #define CY_IP_MXCRYPTO_VERSION 1u -#define CY_IP_MXBLESS 1u -#define CY_IP_MXBLESS_INSTANCES 1u -#define CY_IP_MXBLESS_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -525,21 +510,36 @@ typedef enum { #define CY_IP_MXS40PASS_CTDAC 1u #define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u #define CY_IP_MXS40PASS_CTDAC_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_104_m_csp_ble_usb.h" @@ -839,6 +839,7 @@ typedef enum { #define PROT_BASE 0x40240000UL #define PROT ((PROT_Type*) PROT_BASE) /* 0x40240000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ #define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40242000 */ #define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40242040 */ #define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40242080 */ @@ -855,23 +856,6 @@ typedef enum { #define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40242340 */ #define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40242380 */ #define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402423C0 */ -#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ -#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ -#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ -#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ -#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ -#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ -#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ -#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ -#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ -#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ -#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ -#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ -#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ -#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ -#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ -#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ -#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ #define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40244000 */ #define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40244400 */ #define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40244800 */ @@ -888,6 +872,22 @@ typedef enum { #define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40247400 */ #define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40247800 */ #define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40247C00 */ +#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ +#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ +#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ +#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ +#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ +#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ +#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ +#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ /******************************************************************************* * FLASHC @@ -1097,8 +1097,8 @@ typedef enum { #define BLE_BASE 0x403C0000UL #define BLE ((BLE_Type*) BLE_BASE) /* 0x403C0000 */ -#define BLE_RCB_RCBLL ((BLE_RCB_RCBLL_Type*) &BLE->RCB.RCBLL) /* 0x403C0100 */ #define BLE_RCB ((BLE_RCB_Type*) &BLE->RCB) /* 0x403C0000 */ +#define BLE_RCB_RCBLL ((BLE_RCB_RCBLL_Type*) &BLE->RCB.RCBLL) /* 0x403C0100 */ #define BLE_BLELL ((BLE_BLELL_Type*) &BLE->BLELL) /* 0x403C1000 */ #define BLE_BLESS ((BLE_BLESS_Type*) &BLE->BLESS) /* 0x403DF000 */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347fmi_bud53.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347fmi_bud53.h index dec4321154..10de9278ae 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347fmi_bud53.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347fmi_bud53.h @@ -5,11 +5,11 @@ * CY8C6347FMI-BUD53 device header * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -461,43 +461,22 @@ typedef enum { #define CY_FLASH_SIZE 0x00100000UL #define CY_EM_EEPROM_BASE 0x14000000UL #define CY_EM_EEPROM_SIZE 0x00008000UL -#define CY_XIP_BASE 0x18000000UL -#define CY_XIP_SIZE 0x08000000UL #define CY_SFLASH_BASE 0x16000000UL #define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL #define CY_EFUSE_BASE 0x402C0800UL #define CY_EFUSE_SIZE 0x00000200UL #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXBLESS 1u +#define CY_IP_MXBLESS_INSTANCES 1u +#define CY_IP_MXBLESS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u @@ -507,12 +486,18 @@ typedef enum { #define CY_IP_MXCRYPTO 1u #define CY_IP_MXCRYPTO_INSTANCES 1u #define CY_IP_MXCRYPTO_VERSION 1u -#define CY_IP_MXBLESS 1u -#define CY_IP_MXBLESS_INSTANCES 1u -#define CY_IP_MXBLESS_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -528,24 +513,39 @@ typedef enum { #define CY_IP_MXS40PASS_CTB 1u #define CY_IP_MXS40PASS_CTB_INSTANCES 1u #define CY_IP_MXS40PASS_CTB_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u -#define CY_IP_MXUDB 1u -#define CY_IP_MXUDB_INSTANCES 1u -#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUDB 1u +#define CY_IP_MXUDB_INSTANCES 1u +#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_104_m_csp_ble_usb.h" @@ -845,6 +845,7 @@ typedef enum { #define PROT_BASE 0x40240000UL #define PROT ((PROT_Type*) PROT_BASE) /* 0x40240000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ #define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40242000 */ #define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40242040 */ #define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40242080 */ @@ -861,23 +862,6 @@ typedef enum { #define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40242340 */ #define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40242380 */ #define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402423C0 */ -#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ -#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ -#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ -#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ -#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ -#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ -#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ -#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ -#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ -#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ -#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ -#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ -#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ -#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ -#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ -#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ -#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ #define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40244000 */ #define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40244400 */ #define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40244800 */ @@ -894,6 +878,22 @@ typedef enum { #define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40247400 */ #define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40247800 */ #define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40247C00 */ +#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ +#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ +#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ +#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ +#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ +#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ +#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ +#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ /******************************************************************************* * FLASHC @@ -1043,6 +1043,12 @@ typedef enum { #define UDB ((UDB_Type*) UDB_BASE) /* 0x40340000 */ #define UDB_WRKONE ((UDB_WRKONE_Type*) &UDB->WRKONE) /* 0x40340000 */ #define UDB_WRKMULT ((UDB_WRKMULT_Type*) &UDB->WRKMULT) /* 0x40341000 */ +#define UDB_UDBPAIR0 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[0]) /* 0x40342000 */ +#define UDB_UDBPAIR1 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[1]) /* 0x40342200 */ +#define UDB_UDBPAIR2 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[2]) /* 0x40342400 */ +#define UDB_UDBPAIR3 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[3]) /* 0x40342600 */ +#define UDB_UDBPAIR4 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[4]) /* 0x40342800 */ +#define UDB_UDBPAIR5 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[5]) /* 0x40342A00 */ #define UDB_UDBPAIR0_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[0].UDBSNG[0]) /* 0x40342000 */ #define UDB_UDBPAIR0_UDBSNG1 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[0].UDBSNG[1]) /* 0x40342080 */ #define UDB_UDBPAIR1_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[1].UDBSNG[0]) /* 0x40342200 */ @@ -1061,12 +1067,6 @@ typedef enum { #define UDB_UDBPAIR3_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[3].ROUTE) /* 0x40342700 */ #define UDB_UDBPAIR4_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[4].ROUTE) /* 0x40342900 */ #define UDB_UDBPAIR5_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[5].ROUTE) /* 0x40342B00 */ -#define UDB_UDBPAIR0 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[0]) /* 0x40342000 */ -#define UDB_UDBPAIR1 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[1]) /* 0x40342200 */ -#define UDB_UDBPAIR2 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[2]) /* 0x40342400 */ -#define UDB_UDBPAIR3 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[3]) /* 0x40342600 */ -#define UDB_UDBPAIR4 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[4]) /* 0x40342800 */ -#define UDB_UDBPAIR5 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[5]) /* 0x40342A00 */ #define UDB_DSI0 ((UDB_DSI_Type*) &UDB->DSI[0]) /* 0x40346000 */ #define UDB_DSI1 ((UDB_DSI_Type*) &UDB->DSI[1]) /* 0x40346080 */ #define UDB_DSI2 ((UDB_DSI_Type*) &UDB->DSI[2]) /* 0x40346100 */ @@ -1162,8 +1162,8 @@ typedef enum { #define BLE_BASE 0x403C0000UL #define BLE ((BLE_Type*) BLE_BASE) /* 0x403C0000 */ -#define BLE_RCB_RCBLL ((BLE_RCB_RCBLL_Type*) &BLE->RCB.RCBLL) /* 0x403C0100 */ #define BLE_RCB ((BLE_RCB_Type*) &BLE->RCB) /* 0x403C0000 */ +#define BLE_RCB_RCBLL ((BLE_RCB_RCBLL_Type*) &BLE->RCB.RCBLL) /* 0x403C0100 */ #define BLE_BLELL ((BLE_BLELL_Type*) &BLE->BLELL) /* 0x403C1000 */ #define BLE_BLESS ((BLE_BLESS_Type*) &BLE->BLESS) /* 0x403DF000 */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347lqi_bld52.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347lqi_bld52.h index bf83846a49..0d4296de53 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347lqi_bld52.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6347lqi_bld52.h @@ -5,11 +5,11 @@ * CY8C6347LQI-BLD52 device header * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -461,43 +461,22 @@ typedef enum { #define CY_FLASH_SIZE 0x00100000UL #define CY_EM_EEPROM_BASE 0x14000000UL #define CY_EM_EEPROM_SIZE 0x00008000UL -#define CY_XIP_BASE 0x18000000UL -#define CY_XIP_SIZE 0x08000000UL #define CY_SFLASH_BASE 0x16000000UL #define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL #define CY_EFUSE_BASE 0x402C0800UL #define CY_EFUSE_SIZE 0x00000200UL #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXBLESS 1u +#define CY_IP_MXBLESS_INSTANCES 1u +#define CY_IP_MXBLESS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u @@ -507,12 +486,18 @@ typedef enum { #define CY_IP_MXCRYPTO 1u #define CY_IP_MXCRYPTO_INSTANCES 1u #define CY_IP_MXCRYPTO_VERSION 1u -#define CY_IP_MXBLESS 1u -#define CY_IP_MXBLESS_INSTANCES 1u -#define CY_IP_MXBLESS_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -528,21 +513,36 @@ typedef enum { #define CY_IP_MXS40PASS_CTB 1u #define CY_IP_MXS40PASS_CTB_INSTANCES 1u #define CY_IP_MXS40PASS_CTB_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u -#define CY_IP_MXUDB 1u -#define CY_IP_MXUDB_INSTANCES 1u -#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUDB 1u +#define CY_IP_MXUDB_INSTANCES 1u +#define CY_IP_MXUDB_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_68_qfn_ble.h" @@ -842,6 +842,7 @@ typedef enum { #define PROT_BASE 0x40240000UL #define PROT ((PROT_Type*) PROT_BASE) /* 0x40240000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ #define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40242000 */ #define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40242040 */ #define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40242080 */ @@ -858,23 +859,6 @@ typedef enum { #define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40242340 */ #define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40242380 */ #define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402423C0 */ -#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ -#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ -#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ -#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ -#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ -#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ -#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ -#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ -#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ -#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ -#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ -#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ -#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ -#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ -#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ -#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ -#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ #define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40244000 */ #define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40244400 */ #define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40244800 */ @@ -891,6 +875,22 @@ typedef enum { #define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40247400 */ #define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40247800 */ #define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40247C00 */ +#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ +#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ +#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ +#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ +#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ +#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ +#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ +#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ /******************************************************************************* * FLASHC @@ -1040,6 +1040,12 @@ typedef enum { #define UDB ((UDB_Type*) UDB_BASE) /* 0x40340000 */ #define UDB_WRKONE ((UDB_WRKONE_Type*) &UDB->WRKONE) /* 0x40340000 */ #define UDB_WRKMULT ((UDB_WRKMULT_Type*) &UDB->WRKMULT) /* 0x40341000 */ +#define UDB_UDBPAIR0 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[0]) /* 0x40342000 */ +#define UDB_UDBPAIR1 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[1]) /* 0x40342200 */ +#define UDB_UDBPAIR2 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[2]) /* 0x40342400 */ +#define UDB_UDBPAIR3 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[3]) /* 0x40342600 */ +#define UDB_UDBPAIR4 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[4]) /* 0x40342800 */ +#define UDB_UDBPAIR5 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[5]) /* 0x40342A00 */ #define UDB_UDBPAIR0_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[0].UDBSNG[0]) /* 0x40342000 */ #define UDB_UDBPAIR0_UDBSNG1 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[0].UDBSNG[1]) /* 0x40342080 */ #define UDB_UDBPAIR1_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[1].UDBSNG[0]) /* 0x40342200 */ @@ -1058,12 +1064,6 @@ typedef enum { #define UDB_UDBPAIR3_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[3].ROUTE) /* 0x40342700 */ #define UDB_UDBPAIR4_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[4].ROUTE) /* 0x40342900 */ #define UDB_UDBPAIR5_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[5].ROUTE) /* 0x40342B00 */ -#define UDB_UDBPAIR0 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[0]) /* 0x40342000 */ -#define UDB_UDBPAIR1 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[1]) /* 0x40342200 */ -#define UDB_UDBPAIR2 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[2]) /* 0x40342400 */ -#define UDB_UDBPAIR3 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[3]) /* 0x40342600 */ -#define UDB_UDBPAIR4 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[4]) /* 0x40342800 */ -#define UDB_UDBPAIR5 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[5]) /* 0x40342A00 */ #define UDB_DSI0 ((UDB_DSI_Type*) &UDB->DSI[0]) /* 0x40346000 */ #define UDB_DSI1 ((UDB_DSI_Type*) &UDB->DSI[1]) /* 0x40346080 */ #define UDB_DSI2 ((UDB_DSI_Type*) &UDB->DSI[2]) /* 0x40346100 */ @@ -1159,8 +1159,8 @@ typedef enum { #define BLE_BASE 0x403C0000UL #define BLE ((BLE_Type*) BLE_BASE) /* 0x403C0000 */ -#define BLE_RCB_RCBLL ((BLE_RCB_RCBLL_Type*) &BLE->RCB.RCBLL) /* 0x403C0100 */ #define BLE_RCB ((BLE_RCB_Type*) &BLE->RCB) /* 0x403C0000 */ +#define BLE_RCB_RCBLL ((BLE_RCB_RCBLL_Type*) &BLE->RCB.RCBLL) /* 0x403C0100 */ #define BLE_BLELL ((BLE_BLELL_Type*) &BLE->BLELL) /* 0x403C1000 */ #define BLE_BLESS ((BLE_BLESS_Type*) &BLE->BLESS) /* 0x403DF000 */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c637bzi_bld74.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c637bzi_bld74.h index 80ffd0d193..dc97f7bb37 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c637bzi_bld74.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c637bzi_bld74.h @@ -5,11 +5,11 @@ * CY8C637BZI-BLD74 device header * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -461,43 +461,22 @@ typedef enum { #define CY_FLASH_SIZE 0x00100000UL #define CY_EM_EEPROM_BASE 0x14000000UL #define CY_EM_EEPROM_SIZE 0x00008000UL -#define CY_XIP_BASE 0x18000000UL -#define CY_XIP_SIZE 0x08000000UL #define CY_SFLASH_BASE 0x16000000UL #define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL #define CY_EFUSE_BASE 0x402C0800UL #define CY_EFUSE_SIZE 0x00000200UL #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXBLESS 1u +#define CY_IP_MXBLESS_INSTANCES 1u +#define CY_IP_MXBLESS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u @@ -507,12 +486,18 @@ typedef enum { #define CY_IP_MXCRYPTO 1u #define CY_IP_MXCRYPTO_INSTANCES 1u #define CY_IP_MXCRYPTO_VERSION 1u -#define CY_IP_MXBLESS 1u -#define CY_IP_MXBLESS_INSTANCES 1u -#define CY_IP_MXBLESS_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -528,21 +513,36 @@ typedef enum { #define CY_IP_MXS40PASS_CTB 1u #define CY_IP_MXS40PASS_CTB_INSTANCES 1u #define CY_IP_MXS40PASS_CTB_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u -#define CY_IP_MXUDB 1u -#define CY_IP_MXUDB_INSTANCES 1u -#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUDB 1u +#define CY_IP_MXUDB_INSTANCES 1u +#define CY_IP_MXUDB_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_116_bga_ble.h" @@ -842,6 +842,7 @@ typedef enum { #define PROT_BASE 0x40240000UL #define PROT ((PROT_Type*) PROT_BASE) /* 0x40240000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ #define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40242000 */ #define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40242040 */ #define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40242080 */ @@ -858,23 +859,6 @@ typedef enum { #define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40242340 */ #define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40242380 */ #define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402423C0 */ -#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ -#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ -#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ -#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ -#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ -#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ -#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ -#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ -#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ -#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ -#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ -#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ -#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ -#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ -#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ -#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ -#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ #define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40244000 */ #define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40244400 */ #define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40244800 */ @@ -891,6 +875,22 @@ typedef enum { #define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40247400 */ #define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40247800 */ #define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40247C00 */ +#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ +#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ +#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ +#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ +#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ +#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ +#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ +#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ /******************************************************************************* * FLASHC @@ -1040,6 +1040,12 @@ typedef enum { #define UDB ((UDB_Type*) UDB_BASE) /* 0x40340000 */ #define UDB_WRKONE ((UDB_WRKONE_Type*) &UDB->WRKONE) /* 0x40340000 */ #define UDB_WRKMULT ((UDB_WRKMULT_Type*) &UDB->WRKMULT) /* 0x40341000 */ +#define UDB_UDBPAIR0 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[0]) /* 0x40342000 */ +#define UDB_UDBPAIR1 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[1]) /* 0x40342200 */ +#define UDB_UDBPAIR2 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[2]) /* 0x40342400 */ +#define UDB_UDBPAIR3 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[3]) /* 0x40342600 */ +#define UDB_UDBPAIR4 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[4]) /* 0x40342800 */ +#define UDB_UDBPAIR5 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[5]) /* 0x40342A00 */ #define UDB_UDBPAIR0_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[0].UDBSNG[0]) /* 0x40342000 */ #define UDB_UDBPAIR0_UDBSNG1 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[0].UDBSNG[1]) /* 0x40342080 */ #define UDB_UDBPAIR1_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[1].UDBSNG[0]) /* 0x40342200 */ @@ -1058,12 +1064,6 @@ typedef enum { #define UDB_UDBPAIR3_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[3].ROUTE) /* 0x40342700 */ #define UDB_UDBPAIR4_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[4].ROUTE) /* 0x40342900 */ #define UDB_UDBPAIR5_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[5].ROUTE) /* 0x40342B00 */ -#define UDB_UDBPAIR0 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[0]) /* 0x40342000 */ -#define UDB_UDBPAIR1 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[1]) /* 0x40342200 */ -#define UDB_UDBPAIR2 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[2]) /* 0x40342400 */ -#define UDB_UDBPAIR3 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[3]) /* 0x40342600 */ -#define UDB_UDBPAIR4 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[4]) /* 0x40342800 */ -#define UDB_UDBPAIR5 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[5]) /* 0x40342A00 */ #define UDB_DSI0 ((UDB_DSI_Type*) &UDB->DSI[0]) /* 0x40346000 */ #define UDB_DSI1 ((UDB_DSI_Type*) &UDB->DSI[1]) /* 0x40346080 */ #define UDB_DSI2 ((UDB_DSI_Type*) &UDB->DSI[2]) /* 0x40346100 */ @@ -1159,8 +1159,8 @@ typedef enum { #define BLE_BASE 0x403C0000UL #define BLE ((BLE_Type*) BLE_BASE) /* 0x403C0000 */ -#define BLE_RCB_RCBLL ((BLE_RCB_RCBLL_Type*) &BLE->RCB.RCBLL) /* 0x403C0100 */ #define BLE_RCB ((BLE_RCB_Type*) &BLE->RCB) /* 0x403C0000 */ +#define BLE_RCB_RCBLL ((BLE_RCB_RCBLL_Type*) &BLE->RCB.RCBLL) /* 0x403C0100 */ #define BLE_BLELL ((BLE_BLELL_Type*) &BLE->BLELL) /* 0x403C1000 */ #define BLE_BLESS ((BLE_BLESS_Type*) &BLE->BLESS) /* 0x403DF000 */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c637bzi_md76.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c637bzi_md76.h index c8e67da31c..62106365ad 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c637bzi_md76.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c637bzi_md76.h @@ -5,11 +5,11 @@ * CY8C637BZI-MD76 device header * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -461,43 +461,19 @@ typedef enum { #define CY_FLASH_SIZE 0x00100000UL #define CY_EM_EEPROM_BASE 0x14000000UL #define CY_EM_EEPROM_SIZE 0x00008000UL -#define CY_XIP_BASE 0x18000000UL -#define CY_XIP_SIZE 0x08000000UL #define CY_SFLASH_BASE 0x16000000UL #define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL #define CY_EFUSE_BASE 0x402C0800UL #define CY_EFUSE_SIZE 0x00000200UL #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u @@ -507,9 +483,18 @@ typedef enum { #define CY_IP_MXCRYPTO 1u #define CY_IP_MXCRYPTO_INSTANCES 1u #define CY_IP_MXCRYPTO_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -525,24 +510,39 @@ typedef enum { #define CY_IP_MXS40PASS_CTB 1u #define CY_IP_MXS40PASS_CTB_INSTANCES 1u #define CY_IP_MXS40PASS_CTB_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u -#define CY_IP_MXUDB 1u -#define CY_IP_MXUDB_INSTANCES 1u -#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUDB 1u +#define CY_IP_MXUDB_INSTANCES 1u +#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_124_bga.h" @@ -842,6 +842,7 @@ typedef enum { #define PROT_BASE 0x40240000UL #define PROT ((PROT_Type*) PROT_BASE) /* 0x40240000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ #define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40242000 */ #define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40242040 */ #define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40242080 */ @@ -858,23 +859,6 @@ typedef enum { #define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40242340 */ #define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40242380 */ #define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402423C0 */ -#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ -#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ -#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ -#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ -#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ -#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ -#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ -#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ -#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ -#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ -#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ -#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ -#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ -#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ -#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ -#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ -#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ #define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40244000 */ #define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40244400 */ #define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40244800 */ @@ -891,6 +875,22 @@ typedef enum { #define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40247400 */ #define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40247800 */ #define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40247C00 */ +#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ +#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ +#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ +#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ +#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ +#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ +#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ +#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ /******************************************************************************* * FLASHC @@ -1040,6 +1040,12 @@ typedef enum { #define UDB ((UDB_Type*) UDB_BASE) /* 0x40340000 */ #define UDB_WRKONE ((UDB_WRKONE_Type*) &UDB->WRKONE) /* 0x40340000 */ #define UDB_WRKMULT ((UDB_WRKMULT_Type*) &UDB->WRKMULT) /* 0x40341000 */ +#define UDB_UDBPAIR0 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[0]) /* 0x40342000 */ +#define UDB_UDBPAIR1 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[1]) /* 0x40342200 */ +#define UDB_UDBPAIR2 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[2]) /* 0x40342400 */ +#define UDB_UDBPAIR3 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[3]) /* 0x40342600 */ +#define UDB_UDBPAIR4 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[4]) /* 0x40342800 */ +#define UDB_UDBPAIR5 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[5]) /* 0x40342A00 */ #define UDB_UDBPAIR0_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[0].UDBSNG[0]) /* 0x40342000 */ #define UDB_UDBPAIR0_UDBSNG1 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[0].UDBSNG[1]) /* 0x40342080 */ #define UDB_UDBPAIR1_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[1].UDBSNG[0]) /* 0x40342200 */ @@ -1058,12 +1064,6 @@ typedef enum { #define UDB_UDBPAIR3_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[3].ROUTE) /* 0x40342700 */ #define UDB_UDBPAIR4_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[4].ROUTE) /* 0x40342900 */ #define UDB_UDBPAIR5_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[5].ROUTE) /* 0x40342B00 */ -#define UDB_UDBPAIR0 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[0]) /* 0x40342000 */ -#define UDB_UDBPAIR1 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[1]) /* 0x40342200 */ -#define UDB_UDBPAIR2 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[2]) /* 0x40342400 */ -#define UDB_UDBPAIR3 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[3]) /* 0x40342600 */ -#define UDB_UDBPAIR4 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[4]) /* 0x40342800 */ -#define UDB_UDBPAIR5 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[5]) /* 0x40342A00 */ #define UDB_DSI0 ((UDB_DSI_Type*) &UDB->DSI[0]) /* 0x40346000 */ #define UDB_DSI1 ((UDB_DSI_Type*) &UDB->DSI[1]) /* 0x40346080 */ #define UDB_DSI2 ((UDB_DSI_Type*) &UDB->DSI[2]) /* 0x40346100 */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c637fmi_bld73.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c637fmi_bld73.h index e71e311015..3603203c1f 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c637fmi_bld73.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c637fmi_bld73.h @@ -5,11 +5,11 @@ * CY8C637FMI-BLD73 device header * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -461,43 +461,22 @@ typedef enum { #define CY_FLASH_SIZE 0x00100000UL #define CY_EM_EEPROM_BASE 0x14000000UL #define CY_EM_EEPROM_SIZE 0x00008000UL -#define CY_XIP_BASE 0x18000000UL -#define CY_XIP_SIZE 0x08000000UL #define CY_SFLASH_BASE 0x16000000UL #define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL #define CY_EFUSE_BASE 0x402C0800UL #define CY_EFUSE_SIZE 0x00000200UL #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXBLESS 1u +#define CY_IP_MXBLESS_INSTANCES 1u +#define CY_IP_MXBLESS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u @@ -507,12 +486,18 @@ typedef enum { #define CY_IP_MXCRYPTO 1u #define CY_IP_MXCRYPTO_INSTANCES 1u #define CY_IP_MXCRYPTO_VERSION 1u -#define CY_IP_MXBLESS 1u -#define CY_IP_MXBLESS_INSTANCES 1u -#define CY_IP_MXBLESS_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -528,21 +513,36 @@ typedef enum { #define CY_IP_MXS40PASS_CTB 1u #define CY_IP_MXS40PASS_CTB_INSTANCES 1u #define CY_IP_MXS40PASS_CTB_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u -#define CY_IP_MXUDB 1u -#define CY_IP_MXUDB_INSTANCES 1u -#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUDB 1u +#define CY_IP_MXUDB_INSTANCES 1u +#define CY_IP_MXUDB_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_104_m_csp_ble.h" @@ -842,6 +842,7 @@ typedef enum { #define PROT_BASE 0x40240000UL #define PROT ((PROT_Type*) PROT_BASE) /* 0x40240000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ #define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40242000 */ #define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40242040 */ #define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40242080 */ @@ -858,23 +859,6 @@ typedef enum { #define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40242340 */ #define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40242380 */ #define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402423C0 */ -#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ -#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ -#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ -#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ -#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ -#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ -#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ -#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ -#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ -#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ -#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ -#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ -#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ -#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ -#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ -#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ -#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ #define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40244000 */ #define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40244400 */ #define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40244800 */ @@ -891,6 +875,22 @@ typedef enum { #define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40247400 */ #define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40247800 */ #define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40247C00 */ +#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ +#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ +#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ +#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ +#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ +#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ +#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ +#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ /******************************************************************************* * FLASHC @@ -1040,6 +1040,12 @@ typedef enum { #define UDB ((UDB_Type*) UDB_BASE) /* 0x40340000 */ #define UDB_WRKONE ((UDB_WRKONE_Type*) &UDB->WRKONE) /* 0x40340000 */ #define UDB_WRKMULT ((UDB_WRKMULT_Type*) &UDB->WRKMULT) /* 0x40341000 */ +#define UDB_UDBPAIR0 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[0]) /* 0x40342000 */ +#define UDB_UDBPAIR1 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[1]) /* 0x40342200 */ +#define UDB_UDBPAIR2 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[2]) /* 0x40342400 */ +#define UDB_UDBPAIR3 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[3]) /* 0x40342600 */ +#define UDB_UDBPAIR4 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[4]) /* 0x40342800 */ +#define UDB_UDBPAIR5 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[5]) /* 0x40342A00 */ #define UDB_UDBPAIR0_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[0].UDBSNG[0]) /* 0x40342000 */ #define UDB_UDBPAIR0_UDBSNG1 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[0].UDBSNG[1]) /* 0x40342080 */ #define UDB_UDBPAIR1_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[1].UDBSNG[0]) /* 0x40342200 */ @@ -1058,12 +1064,6 @@ typedef enum { #define UDB_UDBPAIR3_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[3].ROUTE) /* 0x40342700 */ #define UDB_UDBPAIR4_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[4].ROUTE) /* 0x40342900 */ #define UDB_UDBPAIR5_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[5].ROUTE) /* 0x40342B00 */ -#define UDB_UDBPAIR0 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[0]) /* 0x40342000 */ -#define UDB_UDBPAIR1 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[1]) /* 0x40342200 */ -#define UDB_UDBPAIR2 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[2]) /* 0x40342400 */ -#define UDB_UDBPAIR3 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[3]) /* 0x40342600 */ -#define UDB_UDBPAIR4 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[4]) /* 0x40342800 */ -#define UDB_UDBPAIR5 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[5]) /* 0x40342A00 */ #define UDB_DSI0 ((UDB_DSI_Type*) &UDB->DSI[0]) /* 0x40346000 */ #define UDB_DSI1 ((UDB_DSI_Type*) &UDB->DSI[1]) /* 0x40346080 */ #define UDB_DSI2 ((UDB_DSI_Type*) &UDB->DSI[2]) /* 0x40346100 */ @@ -1159,8 +1159,8 @@ typedef enum { #define BLE_BASE 0x403C0000UL #define BLE ((BLE_Type*) BLE_BASE) /* 0x403C0000 */ -#define BLE_RCB_RCBLL ((BLE_RCB_RCBLL_Type*) &BLE->RCB.RCBLL) /* 0x403C0100 */ #define BLE_RCB ((BLE_RCB_Type*) &BLE->RCB) /* 0x403C0000 */ +#define BLE_RCB_RCBLL ((BLE_RCB_RCBLL_Type*) &BLE->RCB.RCBLL) /* 0x403C0100 */ #define BLE_BLELL ((BLE_BLELL_Type*) &BLE->BLELL) /* 0x403C1000 */ #define BLE_BLESS ((BLE_BLESS_Type*) &BLE->BLESS) /* 0x403DF000 */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c68237bz_ble.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c68237bz_ble.h index 8a7127e37c..31a7a74b45 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c68237bz_ble.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c68237bz_ble.h @@ -5,11 +5,11 @@ * CY8C68237BZ-BLE device header * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -461,43 +461,22 @@ typedef enum { #define CY_FLASH_SIZE 0x00100000UL #define CY_EM_EEPROM_BASE 0x14000000UL #define CY_EM_EEPROM_SIZE 0x00008000UL -#define CY_XIP_BASE 0x18000000UL -#define CY_XIP_SIZE 0x08000000UL #define CY_SFLASH_BASE 0x16000000UL #define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL #define CY_EFUSE_BASE 0x402C0800UL #define CY_EFUSE_SIZE 0x00000200UL #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXBLESS 1u +#define CY_IP_MXBLESS_INSTANCES 1u +#define CY_IP_MXBLESS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u @@ -507,30 +486,51 @@ typedef enum { #define CY_IP_MXCRYPTO 1u #define CY_IP_MXCRYPTO_INSTANCES 1u #define CY_IP_MXCRYPTO_VERSION 1u -#define CY_IP_MXBLESS 1u -#define CY_IP_MXBLESS_INSTANCES 1u -#define CY_IP_MXBLESS_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u #define CY_IP_MXS40PASS 1u #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_116_bga_ble.h" @@ -830,6 +830,7 @@ typedef enum { #define PROT_BASE 0x40240000UL #define PROT ((PROT_Type*) PROT_BASE) /* 0x40240000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ #define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40242000 */ #define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40242040 */ #define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40242080 */ @@ -846,23 +847,6 @@ typedef enum { #define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40242340 */ #define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40242380 */ #define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402423C0 */ -#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ -#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ -#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ -#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ -#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ -#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ -#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ -#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ -#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ -#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ -#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ -#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ -#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ -#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ -#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ -#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ -#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ #define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40244000 */ #define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40244400 */ #define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40244800 */ @@ -879,6 +863,22 @@ typedef enum { #define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40247400 */ #define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40247800 */ #define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40247C00 */ +#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ +#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ +#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ +#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ +#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ +#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ +#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ +#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ /******************************************************************************* * FLASHC @@ -1088,8 +1088,8 @@ typedef enum { #define BLE_BASE 0x403C0000UL #define BLE ((BLE_Type*) BLE_BASE) /* 0x403C0000 */ -#define BLE_RCB_RCBLL ((BLE_RCB_RCBLL_Type*) &BLE->RCB.RCBLL) /* 0x403C0100 */ #define BLE_RCB ((BLE_RCB_Type*) &BLE->RCB) /* 0x403C0000 */ +#define BLE_RCB_RCBLL ((BLE_RCB_RCBLL_Type*) &BLE->RCB.RCBLL) /* 0x403C0100 */ #define BLE_BLELL ((BLE_BLELL_Type*) &BLE->BLELL) /* 0x403C1000 */ #define BLE_BLESS ((BLE_BLESS_Type*) &BLE->BLESS) /* 0x403DF000 */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c68237fm_ble.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c68237fm_ble.h index f8d1c52193..8ea27b85b3 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c68237fm_ble.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c68237fm_ble.h @@ -5,11 +5,11 @@ * CY8C68237FM-BLE device header * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -461,43 +461,22 @@ typedef enum { #define CY_FLASH_SIZE 0x00100000UL #define CY_EM_EEPROM_BASE 0x14000000UL #define CY_EM_EEPROM_SIZE 0x00008000UL -#define CY_XIP_BASE 0x18000000UL -#define CY_XIP_SIZE 0x08000000UL #define CY_SFLASH_BASE 0x16000000UL #define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL #define CY_EFUSE_BASE 0x402C0800UL #define CY_EFUSE_SIZE 0x00000200UL #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXBLESS 1u +#define CY_IP_MXBLESS_INSTANCES 1u +#define CY_IP_MXBLESS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u @@ -507,30 +486,51 @@ typedef enum { #define CY_IP_MXCRYPTO 1u #define CY_IP_MXCRYPTO_INSTANCES 1u #define CY_IP_MXCRYPTO_VERSION 1u -#define CY_IP_MXBLESS 1u -#define CY_IP_MXBLESS_INSTANCES 1u -#define CY_IP_MXBLESS_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u #define CY_IP_MXS40PASS 1u #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_104_m_csp_ble.h" @@ -830,6 +830,7 @@ typedef enum { #define PROT_BASE 0x40240000UL #define PROT ((PROT_Type*) PROT_BASE) /* 0x40240000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ #define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40242000 */ #define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40242040 */ #define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40242080 */ @@ -846,23 +847,6 @@ typedef enum { #define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40242340 */ #define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40242380 */ #define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402423C0 */ -#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ -#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ -#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ -#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ -#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ -#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ -#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ -#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ -#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ -#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ -#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ -#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ -#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ -#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ -#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ -#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ -#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ #define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40244000 */ #define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40244400 */ #define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40244800 */ @@ -879,6 +863,22 @@ typedef enum { #define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40247400 */ #define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40247800 */ #define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40247C00 */ +#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ +#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ +#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ +#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ +#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ +#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ +#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ +#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ /******************************************************************************* * FLASHC @@ -1088,8 +1088,8 @@ typedef enum { #define BLE_BASE 0x403C0000UL #define BLE ((BLE_Type*) BLE_BASE) /* 0x403C0000 */ -#define BLE_RCB_RCBLL ((BLE_RCB_RCBLL_Type*) &BLE->RCB.RCBLL) /* 0x403C0100 */ #define BLE_RCB ((BLE_RCB_Type*) &BLE->RCB) /* 0x403C0000 */ +#define BLE_RCB_RCBLL ((BLE_RCB_RCBLL_Type*) &BLE->RCB.RCBLL) /* 0x403C0100 */ #define BLE_BLELL ((BLE_BLELL_Type*) &BLE->BLELL) /* 0x403C1000 */ #define BLE_BLESS ((BLE_BLESS_Type*) &BLE->BLESS) /* 0x403DF000 */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy_device_common.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy_device_common.h index a815706a5d..c985731bff 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy_device_common.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy_device_common.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_device_common.h -* \version 2.40 +* \version 2.80 * * \brief * This file provides types and IP block definitions common for all PSoC 6 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy_device_headers.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy_device_headers.h index f446b3287e..f172d53492 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy_device_headers.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy_device_headers.h @@ -5,7 +5,7 @@ * Common header file to be included by the drivers. * * \note -* Generator version: 1.6.0.111 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -148,40 +148,18 @@ #include "cy8c6117wi_f34.h" #elif defined (CY8C6247WI_D54) #include "cy8c6247wi_d54.h" -#elif defined (CYB06447BZI_BLD54) - #include "cyb06447bzi_bld54.h" -#elif defined (CYB06447BZI_BLD53) - #include "cyb06447bzi_bld53.h" -#elif defined (CYB06447BZI_D54) - #include "cyb06447bzi_d54.h" #elif defined (CY8C6336LQI_BLF02) #include "cy8c6336lqi_blf02.h" #elif defined (CY8C6336LQI_BLF42) #include "cy8c6336lqi_blf42.h" #elif defined (CY8C6347LQI_BLD52) #include "cy8c6347lqi_bld52.h" -#elif defined (CY8C624ABZI_D44) - #include "cy8c624abzi_d44.h" -#elif defined (CY8C624AAZI_D44) - #include "cy8c624aazi_d44.h" -#elif defined (CY8C624AFNI_D43) - #include "cy8c624afni_d43.h" -#elif defined (CY8C624ABZI_D04) - #include "cy8c624abzi_d04.h" -#elif defined (CY8C624ABZI_D14) - #include "cy8c624abzi_d14.h" -#elif defined (CY8C624AAZI_D14) - #include "cy8c624aazi_d14.h" -#elif defined (CY8C6248AZI_D14) - #include "cy8c6248azi_d14.h" -#elif defined (CY8C6248BZI_D44) - #include "cy8c6248bzi_d44.h" -#elif defined (CY8C6248AZI_D44) - #include "cy8c6248azi_d44.h" -#elif defined (CY8C6248FNI_D43) - #include "cy8c6248fni_d43.h" -#elif defined (CY8C624ALQI_D42) - #include "cy8c624alqi_d42.h" +#elif defined (CYB06447BZI_BLD54) + #include "cyb06447bzi_bld54.h" +#elif defined (CYB06447BZI_BLD53) + #include "cyb06447bzi_bld53.h" +#elif defined (CYB06447BZI_D54) + #include "cyb06447bzi_d54.h" #elif defined (CYB0644ABZI_S2D44) #include "cyb0644abzi_s2d44.h" #elif defined (CYS0644ABZI_S2D44) @@ -208,6 +186,48 @@ #include "cy8c6248azi_s2d44.h" #elif defined (CY8C6248FNI_S2D43) #include "cy8c6248fni_s2d43.h" +#elif defined (CY8C614ABZI_S2F04) + #include "cy8c614abzi_s2f04.h" +#elif defined (CY8C614AAZI_S2F04) + #include "cy8c614aazi_s2f04.h" +#elif defined (CY8C614AFNI_S2F03) + #include "cy8c614afni_s2f03.h" +#elif defined (CY8C614AAZI_S2F14) + #include "cy8c614aazi_s2f14.h" +#elif defined (CY8C614ABZI_S2F44) + #include "cy8c614abzi_s2f44.h" +#elif defined (CY8C614AAZI_S2F44) + #include "cy8c614aazi_s2f44.h" +#elif defined (CY8C614AFNI_S2F43) + #include "cy8c614afni_s2f43.h" +#elif defined (CY8C6148BZI_S2F44) + #include "cy8c6148bzi_s2f44.h" +#elif defined (CY8C6148AZI_S2F44) + #include "cy8c6148azi_s2f44.h" +#elif defined (CY8C6148FNI_S2F43) + #include "cy8c6148fni_s2f43.h" +#elif defined (CY8C624ABZI_D44) + #include "cy8c624abzi_d44.h" +#elif defined (CY8C624AAZI_D44) + #include "cy8c624aazi_d44.h" +#elif defined (CY8C624AFNI_D43) + #include "cy8c624afni_d43.h" +#elif defined (CY8C624ABZI_D04) + #include "cy8c624abzi_d04.h" +#elif defined (CY8C624ABZI_D14) + #include "cy8c624abzi_d14.h" +#elif defined (CY8C624AAZI_D14) + #include "cy8c624aazi_d14.h" +#elif defined (CY8C6248AZI_D14) + #include "cy8c6248azi_d14.h" +#elif defined (CY8C6248BZI_D44) + #include "cy8c6248bzi_d44.h" +#elif defined (CY8C6248AZI_D44) + #include "cy8c6248azi_d44.h" +#elif defined (CY8C6248FNI_D43) + #include "cy8c6248fni_d43.h" +#elif defined (CY8C624ALQI_D42) + #include "cy8c624alqi_d42.h" #elif defined (CY8C6245AZI_S3D72) #include "cy8c6245azi_s3d72.h" #elif defined (CY8C6245LQI_S3D72) @@ -236,8 +256,32 @@ #include "cy8c6245azi_s3d02.h" #elif defined (CY8C6245LQI_S3D02) #include "cy8c6245lqi_s3d02.h" -#elif defined (CY8C6245W_S3D72) - #include "cy8c6245w_s3d72.h" +#elif defined (CY8C6145AZI_S3F72) + #include "cy8c6145azi_s3f72.h" +#elif defined (CY8C6145LQI_S3F72) + #include "cy8c6145lqi_s3f72.h" +#elif defined (CY8C6145FNI_S3F71) + #include "cy8c6145fni_s3f71.h" +#elif defined (CY8C6145AZI_S3F62) + #include "cy8c6145azi_s3f62.h" +#elif defined (CY8C6145LQI_S3F62) + #include "cy8c6145lqi_s3f62.h" +#elif defined (CY8C6145AZI_S3F42) + #include "cy8c6145azi_s3f42.h" +#elif defined (CY8C6145LQI_S3F42) + #include "cy8c6145lqi_s3f42.h" +#elif defined (CY8C6145FNI_S3F41) + #include "cy8c6145fni_s3f41.h" +#elif defined (CY8C6145AZI_S3F12) + #include "cy8c6145azi_s3f12.h" +#elif defined (CY8C6145LQI_S3F12) + #include "cy8c6145lqi_s3f12.h" +#elif defined (CY8C6145FNI_S3F11) + #include "cy8c6145fni_s3f11.h" +#elif defined (CY8C6145AZI_S3F02) + #include "cy8c6145azi_s3f02.h" +#elif defined (CY8C6145LQI_S3F02) + #include "cy8c6145lqi_s3f02.h" #elif defined (CY8C6244AZI_S4D92) #include "cy8c6244azi_s4d92.h" #elif defined (CY8C6244LQI_S4D92) @@ -258,6 +302,34 @@ #include "cy8c6244azi_s4d12.h" #elif defined (CY8C6244LQI_S4D12) #include "cy8c6244lqi_s4d12.h" +#elif defined (CY8C4588AZI_H685) + #include "cy8c4588azi_h685.h" +#elif defined (CY8C4588AZI_H686) + #include "cy8c4588azi_h686.h" +#elif defined (CY8C4588AZI_H675) + #include "cy8c4588azi_h675.h" +#elif defined (CY8C4588AZI_H676) + #include "cy8c4588azi_h676.h" +#elif defined (CY8C6144AZI_S4F92) + #include "cy8c6144azi_s4f92.h" +#elif defined (CY8C6144LQI_S4F92) + #include "cy8c6144lqi_s4f92.h" +#elif defined (CY8C6144AZI_S4F93) + #include "cy8c6144azi_s4f93.h" +#elif defined (CY8C6144AZI_S4F82) + #include "cy8c6144azi_s4f82.h" +#elif defined (CY8C6144LQI_S4F82) + #include "cy8c6144lqi_s4f82.h" +#elif defined (CY8C6144AZI_S4F83) + #include "cy8c6144azi_s4f83.h" +#elif defined (CY8C6144AZI_S4F62) + #include "cy8c6144azi_s4f62.h" +#elif defined (CY8C6144LQI_S4F62) + #include "cy8c6144lqi_s4f62.h" +#elif defined (CY8C6144AZI_S4F12) + #include "cy8c6144azi_s4f12.h" +#elif defined (CY8C6144LQI_S4F12) + #include "cy8c6144lqi_s4f12.h" #else #include "cy_device_common.h" #endif diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cyb06445lqi_s3d42.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cyb06445lqi_s3d42.h index fac6b9fe3d..daee6ad7ff 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cyb06445lqi_s3d42.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cyb06445lqi_s3d42.h @@ -5,11 +5,11 @@ * CYB06445LQI-S3D42 device header * * \note -* Generator version: 1.5.0.1314 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -423,48 +423,24 @@ typedef enum { #define CY_SRAM_BASE 0x08000000UL #define CY_SRAM_SIZE 0x00040000UL #define CY_FLASH_BASE 0x10000000UL -#define CY_FLASH_SIZE 0x00070000UL +#define CY_FLASH_SIZE 0x00060000UL #define CY_EM_EEPROM_BASE 0x14000000UL #define CY_EM_EEPROM_SIZE 0x00008000UL -#define CY_XIP_BASE 0x18000000UL -#define CY_XIP_SIZE 0x08000000UL -#define CY_CAN0MRAM_BASE 0x40530000UL -#define CY_CAN0MRAM_SIZE 0x00010000UL #define CY_SFLASH_BASE 0x16000000UL #define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL #define CY_EFUSE_BASE 0x402C0800UL #define CY_EFUSE_SIZE 0x00000200UL +#define CY_CAN0MRAM_BASE 0x40530000UL +#define CY_CAN0MRAM_SIZE 0x00010000UL #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 2u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 7u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 2u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXTTCANFD 1u +#define CY_IP_MXTTCANFD_INSTANCES 1u +#define CY_IP_MXTTCANFD_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 2u @@ -477,38 +453,63 @@ typedef enum { #define CY_IP_MXCRYPTO 1u #define CY_IP_MXCRYPTO_INSTANCES 1u #define CY_IP_MXCRYPTO_VERSION 2u -#define CY_IP_MXSDHC 1u -#define CY_IP_MXSDHC_INSTANCES 1u -#define CY_IP_MXSDHC_VERSION 1u -#define CY_IP_MXTTCANFD 1u -#define CY_IP_MXTTCANFD_INSTANCES 1u -#define CY_IP_MXTTCANFD_VERSION 1u -#define CY_IP_MXLPCOMP 1u -#define CY_IP_MXLPCOMP_INSTANCES 1u -#define CY_IP_MXLPCOMP_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u #define CY_IP_MXS40IOSS 1u #define CY_IP_MXS40IOSS_INSTANCES 1u #define CY_IP_MXS40IOSS_VERSION 2u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 2u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u #define CY_IP_MXS40PASS 1u #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u #define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 7u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 1u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_03_config.h" #include "gpio_psoc6_03_68_qfn.h" #define CY_DEVICE_PSOC6A512K +#define CY_DEVICE_SECURE #define CY_SILICON_ID 0xE70D1105UL #define CY_HF_CLK_MAX_FREQ 150000000UL @@ -858,6 +859,7 @@ typedef enum { #define PROT_BASE 0x40230000UL #define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ #define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ #define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ #define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ @@ -874,23 +876,6 @@ typedef enum { #define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ #define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ #define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ -#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ -#define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ -#define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ -#define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ -#define PROT_MPU5_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[3]) /* 0x40235660 */ -#define PROT_MPU5_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[4]) /* 0x40235680 */ -#define PROT_MPU5_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[5]) /* 0x402356A0 */ -#define PROT_MPU5_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[6]) /* 0x402356C0 */ -#define PROT_MPU5_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[7]) /* 0x402356E0 */ -#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ -#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ -#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ -#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ -#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ -#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ -#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ -#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ #define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ #define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ #define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ @@ -907,6 +892,22 @@ typedef enum { #define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ #define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ #define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ +#define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ +#define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ +#define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ +#define PROT_MPU5_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[3]) /* 0x40235660 */ +#define PROT_MPU5_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[4]) /* 0x40235680 */ +#define PROT_MPU5_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[5]) /* 0x402356A0 */ +#define PROT_MPU5_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[6]) /* 0x402356C0 */ +#define PROT_MPU5_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[7]) /* 0x402356E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ /******************************************************************************* * FLASHC @@ -1148,8 +1149,8 @@ typedef enum { #define CANFD0_BASE 0x40520000UL #define CANFD0 ((CANFD_Type*) CANFD0_BASE) /* 0x40520000 */ -#define CANFD0_CH0_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[0].M_TTCAN) /* 0x40520000 */ #define CANFD0_CH0 ((CANFD_CH_Type*) &CANFD0->CH[0]) /* 0x40520000 */ +#define CANFD0_CH0_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[0].M_TTCAN) /* 0x40520000 */ /******************************************************************************* * SCB diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cyb06447bzi_bld53.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cyb06447bzi_bld53.h index acd153aae2..6d2a478bfc 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cyb06447bzi_bld53.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cyb06447bzi_bld53.h @@ -5,11 +5,11 @@ * CYB06447BZI-BLD53 device header * * \note -* Generator version: 1.5.0.1292 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -461,43 +461,22 @@ typedef enum { #define CY_FLASH_SIZE 0x000D0000UL #define CY_EM_EEPROM_BASE 0x14000000UL #define CY_EM_EEPROM_SIZE 0x00008000UL -#define CY_XIP_BASE 0x18000000UL -#define CY_XIP_SIZE 0x08000000UL #define CY_SFLASH_BASE 0x16000000UL #define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL #define CY_EFUSE_BASE 0x402C0800UL #define CY_EFUSE_SIZE 0x00000200UL #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXBLESS 1u +#define CY_IP_MXBLESS_INSTANCES 1u +#define CY_IP_MXBLESS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u @@ -507,12 +486,18 @@ typedef enum { #define CY_IP_MXCRYPTO 1u #define CY_IP_MXCRYPTO_INSTANCES 1u #define CY_IP_MXCRYPTO_VERSION 1u -#define CY_IP_MXBLESS 1u -#define CY_IP_MXBLESS_INSTANCES 1u -#define CY_IP_MXBLESS_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -528,26 +513,42 @@ typedef enum { #define CY_IP_MXS40PASS_CTB 1u #define CY_IP_MXS40PASS_CTB_INSTANCES 1u #define CY_IP_MXS40PASS_CTB_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u -#define CY_IP_MXUDB 1u -#define CY_IP_MXUDB_INSTANCES 1u -#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUDB 1u +#define CY_IP_MXUDB_INSTANCES 1u +#define CY_IP_MXUDB_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_116_bga_ble.h" #define CY_DEVICE_PSOC6ABLE2 +#define CY_DEVICE_SECURE #define CY_SILICON_ID 0xE2612100UL #define CY_HF_CLK_MAX_FREQ 150000000UL @@ -842,6 +843,7 @@ typedef enum { #define PROT_BASE 0x40240000UL #define PROT ((PROT_Type*) PROT_BASE) /* 0x40240000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ #define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40242000 */ #define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40242040 */ #define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40242080 */ @@ -858,23 +860,6 @@ typedef enum { #define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40242340 */ #define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40242380 */ #define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402423C0 */ -#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ -#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ -#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ -#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ -#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ -#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ -#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ -#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ -#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ -#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ -#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ -#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ -#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ -#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ -#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ -#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ -#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ #define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40244000 */ #define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40244400 */ #define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40244800 */ @@ -891,6 +876,22 @@ typedef enum { #define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40247400 */ #define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40247800 */ #define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40247C00 */ +#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ +#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ +#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ +#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ +#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ +#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ +#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ +#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ /******************************************************************************* * FLASHC @@ -1040,6 +1041,12 @@ typedef enum { #define UDB ((UDB_Type*) UDB_BASE) /* 0x40340000 */ #define UDB_WRKONE ((UDB_WRKONE_Type*) &UDB->WRKONE) /* 0x40340000 */ #define UDB_WRKMULT ((UDB_WRKMULT_Type*) &UDB->WRKMULT) /* 0x40341000 */ +#define UDB_UDBPAIR0 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[0]) /* 0x40342000 */ +#define UDB_UDBPAIR1 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[1]) /* 0x40342200 */ +#define UDB_UDBPAIR2 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[2]) /* 0x40342400 */ +#define UDB_UDBPAIR3 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[3]) /* 0x40342600 */ +#define UDB_UDBPAIR4 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[4]) /* 0x40342800 */ +#define UDB_UDBPAIR5 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[5]) /* 0x40342A00 */ #define UDB_UDBPAIR0_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[0].UDBSNG[0]) /* 0x40342000 */ #define UDB_UDBPAIR0_UDBSNG1 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[0].UDBSNG[1]) /* 0x40342080 */ #define UDB_UDBPAIR1_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[1].UDBSNG[0]) /* 0x40342200 */ @@ -1058,12 +1065,6 @@ typedef enum { #define UDB_UDBPAIR3_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[3].ROUTE) /* 0x40342700 */ #define UDB_UDBPAIR4_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[4].ROUTE) /* 0x40342900 */ #define UDB_UDBPAIR5_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[5].ROUTE) /* 0x40342B00 */ -#define UDB_UDBPAIR0 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[0]) /* 0x40342000 */ -#define UDB_UDBPAIR1 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[1]) /* 0x40342200 */ -#define UDB_UDBPAIR2 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[2]) /* 0x40342400 */ -#define UDB_UDBPAIR3 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[3]) /* 0x40342600 */ -#define UDB_UDBPAIR4 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[4]) /* 0x40342800 */ -#define UDB_UDBPAIR5 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[5]) /* 0x40342A00 */ #define UDB_DSI0 ((UDB_DSI_Type*) &UDB->DSI[0]) /* 0x40346000 */ #define UDB_DSI1 ((UDB_DSI_Type*) &UDB->DSI[1]) /* 0x40346080 */ #define UDB_DSI2 ((UDB_DSI_Type*) &UDB->DSI[2]) /* 0x40346100 */ @@ -1159,8 +1160,8 @@ typedef enum { #define BLE_BASE 0x403C0000UL #define BLE ((BLE_Type*) BLE_BASE) /* 0x403C0000 */ -#define BLE_RCB_RCBLL ((BLE_RCB_RCBLL_Type*) &BLE->RCB.RCBLL) /* 0x403C0100 */ #define BLE_RCB ((BLE_RCB_Type*) &BLE->RCB) /* 0x403C0000 */ +#define BLE_RCB_RCBLL ((BLE_RCB_RCBLL_Type*) &BLE->RCB.RCBLL) /* 0x403C0100 */ #define BLE_BLELL ((BLE_BLELL_Type*) &BLE->BLELL) /* 0x403C1000 */ #define BLE_BLESS ((BLE_BLESS_Type*) &BLE->BLESS) /* 0x403DF000 */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cyb06447bzi_bld54.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cyb06447bzi_bld54.h index 96163e55f6..db5b772f49 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cyb06447bzi_bld54.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cyb06447bzi_bld54.h @@ -5,11 +5,11 @@ * CYB06447BZI-BLD54 device header * * \note -* Generator version: 1.5.0.1292 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -461,43 +461,22 @@ typedef enum { #define CY_FLASH_SIZE 0x000D0000UL #define CY_EM_EEPROM_BASE 0x14000000UL #define CY_EM_EEPROM_SIZE 0x00008000UL -#define CY_XIP_BASE 0x18000000UL -#define CY_XIP_SIZE 0x08000000UL #define CY_SFLASH_BASE 0x16000000UL #define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL #define CY_EFUSE_BASE 0x402C0800UL #define CY_EFUSE_SIZE 0x00000200UL #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXBLESS 1u +#define CY_IP_MXBLESS_INSTANCES 1u +#define CY_IP_MXBLESS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u @@ -507,12 +486,18 @@ typedef enum { #define CY_IP_MXCRYPTO 1u #define CY_IP_MXCRYPTO_INSTANCES 1u #define CY_IP_MXCRYPTO_VERSION 1u -#define CY_IP_MXBLESS 1u -#define CY_IP_MXBLESS_INSTANCES 1u -#define CY_IP_MXBLESS_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -528,29 +513,45 @@ typedef enum { #define CY_IP_MXS40PASS_CTB 1u #define CY_IP_MXS40PASS_CTB_INSTANCES 1u #define CY_IP_MXS40PASS_CTB_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u -#define CY_IP_MXUDB 1u -#define CY_IP_MXUDB_INSTANCES 1u -#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUDB 1u +#define CY_IP_MXUDB_INSTANCES 1u +#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_124_bga_sip.h" #define CY_DEVICE_PSOC6ABLE2 +#define CY_DEVICE_SECURE #define CY_SILICON_ID 0xE2602100UL #define CY_HF_CLK_MAX_FREQ 150000000UL @@ -845,6 +846,7 @@ typedef enum { #define PROT_BASE 0x40240000UL #define PROT ((PROT_Type*) PROT_BASE) /* 0x40240000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ #define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40242000 */ #define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40242040 */ #define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40242080 */ @@ -861,23 +863,6 @@ typedef enum { #define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40242340 */ #define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40242380 */ #define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402423C0 */ -#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ -#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ -#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ -#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ -#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ -#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ -#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ -#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ -#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ -#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ -#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ -#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ -#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ -#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ -#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ -#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ -#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ #define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40244000 */ #define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40244400 */ #define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40244800 */ @@ -894,6 +879,22 @@ typedef enum { #define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40247400 */ #define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40247800 */ #define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40247C00 */ +#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ +#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ +#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ +#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ +#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ +#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ +#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ +#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ /******************************************************************************* * FLASHC @@ -1043,6 +1044,12 @@ typedef enum { #define UDB ((UDB_Type*) UDB_BASE) /* 0x40340000 */ #define UDB_WRKONE ((UDB_WRKONE_Type*) &UDB->WRKONE) /* 0x40340000 */ #define UDB_WRKMULT ((UDB_WRKMULT_Type*) &UDB->WRKMULT) /* 0x40341000 */ +#define UDB_UDBPAIR0 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[0]) /* 0x40342000 */ +#define UDB_UDBPAIR1 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[1]) /* 0x40342200 */ +#define UDB_UDBPAIR2 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[2]) /* 0x40342400 */ +#define UDB_UDBPAIR3 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[3]) /* 0x40342600 */ +#define UDB_UDBPAIR4 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[4]) /* 0x40342800 */ +#define UDB_UDBPAIR5 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[5]) /* 0x40342A00 */ #define UDB_UDBPAIR0_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[0].UDBSNG[0]) /* 0x40342000 */ #define UDB_UDBPAIR0_UDBSNG1 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[0].UDBSNG[1]) /* 0x40342080 */ #define UDB_UDBPAIR1_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[1].UDBSNG[0]) /* 0x40342200 */ @@ -1061,12 +1068,6 @@ typedef enum { #define UDB_UDBPAIR3_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[3].ROUTE) /* 0x40342700 */ #define UDB_UDBPAIR4_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[4].ROUTE) /* 0x40342900 */ #define UDB_UDBPAIR5_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[5].ROUTE) /* 0x40342B00 */ -#define UDB_UDBPAIR0 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[0]) /* 0x40342000 */ -#define UDB_UDBPAIR1 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[1]) /* 0x40342200 */ -#define UDB_UDBPAIR2 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[2]) /* 0x40342400 */ -#define UDB_UDBPAIR3 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[3]) /* 0x40342600 */ -#define UDB_UDBPAIR4 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[4]) /* 0x40342800 */ -#define UDB_UDBPAIR5 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[5]) /* 0x40342A00 */ #define UDB_DSI0 ((UDB_DSI_Type*) &UDB->DSI[0]) /* 0x40346000 */ #define UDB_DSI1 ((UDB_DSI_Type*) &UDB->DSI[1]) /* 0x40346080 */ #define UDB_DSI2 ((UDB_DSI_Type*) &UDB->DSI[2]) /* 0x40346100 */ @@ -1162,8 +1163,8 @@ typedef enum { #define BLE_BASE 0x403C0000UL #define BLE ((BLE_Type*) BLE_BASE) /* 0x403C0000 */ -#define BLE_RCB_RCBLL ((BLE_RCB_RCBLL_Type*) &BLE->RCB.RCBLL) /* 0x403C0100 */ #define BLE_RCB ((BLE_RCB_Type*) &BLE->RCB) /* 0x403C0000 */ +#define BLE_RCB_RCBLL ((BLE_RCB_RCBLL_Type*) &BLE->RCB.RCBLL) /* 0x403C0100 */ #define BLE_BLELL ((BLE_BLELL_Type*) &BLE->BLELL) /* 0x403C1000 */ #define BLE_BLESS ((BLE_BLESS_Type*) &BLE->BLESS) /* 0x403DF000 */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cyb06447bzi_d54.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cyb06447bzi_d54.h index ecc81689f5..35a18b84f0 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cyb06447bzi_d54.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cyb06447bzi_d54.h @@ -5,11 +5,11 @@ * CYB06447BZI-D54 device header * * \note -* Generator version: 1.5.0.1292 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -461,43 +461,19 @@ typedef enum { #define CY_FLASH_SIZE 0x000D0000UL #define CY_EM_EEPROM_BASE 0x14000000UL #define CY_EM_EEPROM_SIZE 0x00008000UL -#define CY_XIP_BASE 0x18000000UL -#define CY_XIP_SIZE 0x08000000UL #define CY_SFLASH_BASE 0x16000000UL #define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL #define CY_EFUSE_BASE 0x402C0800UL #define CY_EFUSE_SIZE 0x00000200UL #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u @@ -507,9 +483,18 @@ typedef enum { #define CY_IP_MXCRYPTO 1u #define CY_IP_MXCRYPTO_INSTANCES 1u #define CY_IP_MXCRYPTO_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -525,29 +510,45 @@ typedef enum { #define CY_IP_MXS40PASS_CTB 1u #define CY_IP_MXS40PASS_CTB_INSTANCES 1u #define CY_IP_MXS40PASS_CTB_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u -#define CY_IP_MXUDB 1u -#define CY_IP_MXUDB_INSTANCES 1u -#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUDB 1u +#define CY_IP_MXUDB_INSTANCES 1u +#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_124_bga.h" #define CY_DEVICE_PSOC6ABLE2 +#define CY_DEVICE_SECURE #define CY_SILICON_ID 0xE2622100UL #define CY_HF_CLK_MAX_FREQ 150000000UL @@ -842,6 +843,7 @@ typedef enum { #define PROT_BASE 0x40240000UL #define PROT ((PROT_Type*) PROT_BASE) /* 0x40240000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ #define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40242000 */ #define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40242040 */ #define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40242080 */ @@ -858,23 +860,6 @@ typedef enum { #define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40242340 */ #define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40242380 */ #define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402423C0 */ -#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ -#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ -#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ -#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ -#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ -#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ -#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ -#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ -#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ -#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ -#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ -#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ -#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ -#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ -#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ -#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ -#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ #define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40244000 */ #define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40244400 */ #define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40244800 */ @@ -891,6 +876,22 @@ typedef enum { #define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40247400 */ #define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40247800 */ #define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40247C00 */ +#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ +#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ +#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ +#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ +#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ +#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ +#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ +#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ /******************************************************************************* * FLASHC @@ -1040,6 +1041,12 @@ typedef enum { #define UDB ((UDB_Type*) UDB_BASE) /* 0x40340000 */ #define UDB_WRKONE ((UDB_WRKONE_Type*) &UDB->WRKONE) /* 0x40340000 */ #define UDB_WRKMULT ((UDB_WRKMULT_Type*) &UDB->WRKMULT) /* 0x40341000 */ +#define UDB_UDBPAIR0 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[0]) /* 0x40342000 */ +#define UDB_UDBPAIR1 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[1]) /* 0x40342200 */ +#define UDB_UDBPAIR2 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[2]) /* 0x40342400 */ +#define UDB_UDBPAIR3 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[3]) /* 0x40342600 */ +#define UDB_UDBPAIR4 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[4]) /* 0x40342800 */ +#define UDB_UDBPAIR5 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[5]) /* 0x40342A00 */ #define UDB_UDBPAIR0_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[0].UDBSNG[0]) /* 0x40342000 */ #define UDB_UDBPAIR0_UDBSNG1 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[0].UDBSNG[1]) /* 0x40342080 */ #define UDB_UDBPAIR1_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[1].UDBSNG[0]) /* 0x40342200 */ @@ -1058,12 +1065,6 @@ typedef enum { #define UDB_UDBPAIR3_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[3].ROUTE) /* 0x40342700 */ #define UDB_UDBPAIR4_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[4].ROUTE) /* 0x40342900 */ #define UDB_UDBPAIR5_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[5].ROUTE) /* 0x40342B00 */ -#define UDB_UDBPAIR0 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[0]) /* 0x40342000 */ -#define UDB_UDBPAIR1 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[1]) /* 0x40342200 */ -#define UDB_UDBPAIR2 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[2]) /* 0x40342400 */ -#define UDB_UDBPAIR3 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[3]) /* 0x40342600 */ -#define UDB_UDBPAIR4 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[4]) /* 0x40342800 */ -#define UDB_UDBPAIR5 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[5]) /* 0x40342A00 */ #define UDB_DSI0 ((UDB_DSI_Type*) &UDB->DSI[0]) /* 0x40346000 */ #define UDB_DSI1 ((UDB_DSI_Type*) &UDB->DSI[1]) /* 0x40346080 */ #define UDB_DSI2 ((UDB_DSI_Type*) &UDB->DSI[2]) /* 0x40346100 */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cyb0644abzi_s2d44.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cyb0644abzi_s2d44.h index fae778ff48..2cd05d31af 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cyb0644abzi_s2d44.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cyb0644abzi_s2d44.h @@ -5,7 +5,7 @@ * CYB0644ABZI-S2D44 device header * * \note -* Generator version: 1.6.0.81 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -488,43 +488,19 @@ typedef enum { #define CY_FLASH_SIZE 0x001D0000UL #define CY_EM_EEPROM_BASE 0x14000000UL #define CY_EM_EEPROM_SIZE 0x00008000UL -#define CY_XIP_BASE 0x18000000UL -#define CY_XIP_SIZE 0x08000000UL #define CY_SFLASH_BASE 0x16000000UL #define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL #define CY_EFUSE_BASE 0x402C0800UL #define CY_EFUSE_SIZE 0x00000200UL #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 13u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 2u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 2u +#define CY_IP_MXAUDIOSS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 2u @@ -537,41 +513,66 @@ typedef enum { #define CY_IP_MXCRYPTO 1u #define CY_IP_MXCRYPTO_INSTANCES 1u #define CY_IP_MXCRYPTO_VERSION 2u -#define CY_IP_MXSDHC 1u -#define CY_IP_MXSDHC_INSTANCES 2u -#define CY_IP_MXSDHC_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 2u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u #define CY_IP_MXS40PASS 1u #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u #define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 2u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 13u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 2u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_02_config.h" #include "gpio_psoc6_02_124_bga.h" #define CY_DEVICE_PSOC6A2M +#define CY_DEVICE_SECURE #define CY_SILICON_ID 0xE4701202UL #define CY_HF_CLK_MAX_FREQ 150000000UL @@ -928,6 +929,7 @@ typedef enum { #define PROT_BASE 0x40230000UL #define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ #define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ #define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ #define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ @@ -944,7 +946,22 @@ typedef enum { #define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ #define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ #define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ -#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ #define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ #define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ #define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ @@ -969,22 +986,6 @@ typedef enum { #define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ #define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ #define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ -#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ -#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ -#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ -#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ -#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ -#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ -#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ -#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ -#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ -#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ -#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ -#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ -#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ -#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ -#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ -#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ /******************************************************************************* * FLASHC diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cyble_416045_02.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cyble_416045_02.h index e55865918e..b96cf11de6 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cyble_416045_02.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cyble_416045_02.h @@ -5,11 +5,11 @@ * CYBLE-416045-02 device header * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -461,43 +461,22 @@ typedef enum { #define CY_FLASH_SIZE 0x00100000UL #define CY_EM_EEPROM_BASE 0x14000000UL #define CY_EM_EEPROM_SIZE 0x00008000UL -#define CY_XIP_BASE 0x18000000UL -#define CY_XIP_SIZE 0x08000000UL #define CY_SFLASH_BASE 0x16000000UL #define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL #define CY_EFUSE_BASE 0x402C0800UL #define CY_EFUSE_SIZE 0x00000200UL #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 9u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 1u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXBLESS 1u +#define CY_IP_MXBLESS_INSTANCES 1u +#define CY_IP_MXBLESS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 1u @@ -507,12 +486,18 @@ typedef enum { #define CY_IP_MXCRYPTO 1u #define CY_IP_MXCRYPTO_INSTANCES 1u #define CY_IP_MXCRYPTO_VERSION 1u -#define CY_IP_MXBLESS 1u -#define CY_IP_MXBLESS_INSTANCES 1u -#define CY_IP_MXBLESS_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 1u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u @@ -528,18 +513,33 @@ typedef enum { #define CY_IP_MXS40PASS_CTB 1u #define CY_IP_MXS40PASS_CTB_INSTANCES 1u #define CY_IP_MXS40PASS_CTB_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 1u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u -#define CY_IP_MXUDB 1u -#define CY_IP_MXUDB_INSTANCES 1u -#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUDB 1u +#define CY_IP_MXUDB_INSTANCES 1u +#define CY_IP_MXUDB_VERSION 1u #include "psoc6_01_config.h" #include "gpio_psoc6_01_43_smt.h" @@ -839,6 +839,7 @@ typedef enum { #define PROT_BASE 0x40240000UL #define PROT ((PROT_Type*) PROT_BASE) /* 0x40240000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ #define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40242000 */ #define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40242040 */ #define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40242080 */ @@ -855,23 +856,6 @@ typedef enum { #define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40242340 */ #define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40242380 */ #define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402423C0 */ -#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ -#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ -#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ -#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ -#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ -#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ -#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ -#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ -#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ -#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ -#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ -#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ -#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ -#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ -#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ -#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ -#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ #define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40244000 */ #define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40244400 */ #define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40244800 */ @@ -888,6 +872,22 @@ typedef enum { #define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40247400 */ #define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40247800 */ #define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40247C00 */ +#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ +#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ +#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ +#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ +#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ +#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ +#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ +#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ /******************************************************************************* * FLASHC @@ -1037,6 +1037,12 @@ typedef enum { #define UDB ((UDB_Type*) UDB_BASE) /* 0x40340000 */ #define UDB_WRKONE ((UDB_WRKONE_Type*) &UDB->WRKONE) /* 0x40340000 */ #define UDB_WRKMULT ((UDB_WRKMULT_Type*) &UDB->WRKMULT) /* 0x40341000 */ +#define UDB_UDBPAIR0 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[0]) /* 0x40342000 */ +#define UDB_UDBPAIR1 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[1]) /* 0x40342200 */ +#define UDB_UDBPAIR2 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[2]) /* 0x40342400 */ +#define UDB_UDBPAIR3 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[3]) /* 0x40342600 */ +#define UDB_UDBPAIR4 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[4]) /* 0x40342800 */ +#define UDB_UDBPAIR5 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[5]) /* 0x40342A00 */ #define UDB_UDBPAIR0_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[0].UDBSNG[0]) /* 0x40342000 */ #define UDB_UDBPAIR0_UDBSNG1 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[0].UDBSNG[1]) /* 0x40342080 */ #define UDB_UDBPAIR1_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[1].UDBSNG[0]) /* 0x40342200 */ @@ -1055,12 +1061,6 @@ typedef enum { #define UDB_UDBPAIR3_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[3].ROUTE) /* 0x40342700 */ #define UDB_UDBPAIR4_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[4].ROUTE) /* 0x40342900 */ #define UDB_UDBPAIR5_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[5].ROUTE) /* 0x40342B00 */ -#define UDB_UDBPAIR0 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[0]) /* 0x40342000 */ -#define UDB_UDBPAIR1 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[1]) /* 0x40342200 */ -#define UDB_UDBPAIR2 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[2]) /* 0x40342400 */ -#define UDB_UDBPAIR3 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[3]) /* 0x40342600 */ -#define UDB_UDBPAIR4 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[4]) /* 0x40342800 */ -#define UDB_UDBPAIR5 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[5]) /* 0x40342A00 */ #define UDB_DSI0 ((UDB_DSI_Type*) &UDB->DSI[0]) /* 0x40346000 */ #define UDB_DSI1 ((UDB_DSI_Type*) &UDB->DSI[1]) /* 0x40346080 */ #define UDB_DSI2 ((UDB_DSI_Type*) &UDB->DSI[2]) /* 0x40346100 */ @@ -1156,8 +1156,8 @@ typedef enum { #define BLE_BASE 0x403C0000UL #define BLE ((BLE_Type*) BLE_BASE) /* 0x403C0000 */ -#define BLE_RCB_RCBLL ((BLE_RCB_RCBLL_Type*) &BLE->RCB.RCBLL) /* 0x403C0100 */ #define BLE_RCB ((BLE_RCB_Type*) &BLE->RCB) /* 0x403C0000 */ +#define BLE_RCB_RCBLL ((BLE_RCB_RCBLL_Type*) &BLE->RCB.RCBLL) /* 0x403C0100 */ #define BLE_BLELL ((BLE_BLELL_Type*) &BLE->BLELL) /* 0x403C1000 */ #define BLE_BLESS ((BLE_BLESS_Type*) &BLE->BLESS) /* 0x403DF000 */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cys0644abzi_s2d44.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cys0644abzi_s2d44.h index 1894820ddf..34d04241df 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cys0644abzi_s2d44.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cys0644abzi_s2d44.h @@ -5,7 +5,7 @@ * CYS0644ABZI-S2D44 device header * * \note -* Generator version: 1.6.0.81 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -488,43 +488,19 @@ typedef enum { #define CY_FLASH_SIZE 0x001D0000UL #define CY_EM_EEPROM_BASE 0x14000000UL #define CY_EM_EEPROM_SIZE 0x00008000UL -#define CY_XIP_BASE 0x18000000UL -#define CY_XIP_SIZE 0x08000000UL #define CY_SFLASH_BASE 0x16000000UL #define CY_SFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL #define CY_EFUSE_BASE 0x402C0800UL #define CY_EFUSE_SIZE 0x00000200UL #include "system_psoc6.h" /*!< PSoC 6 System */ /* IP List */ -#define CY_IP_MXTCPWM 1u -#define CY_IP_MXTCPWM_INSTANCES 2u -#define CY_IP_MXTCPWM_VERSION 1u -#define CY_IP_MXCSDV2 1u -#define CY_IP_MXCSDV2_INSTANCES 1u -#define CY_IP_MXCSDV2_VERSION 1u -#define CY_IP_MXLCD 1u -#define CY_IP_MXLCD_INSTANCES 1u -#define CY_IP_MXLCD_VERSION 1u -#define CY_IP_MXS40SRSS 1u -#define CY_IP_MXS40SRSS_INSTANCES 1u -#define CY_IP_MXS40SRSS_VERSION 1u -#define CY_IP_MXS40SRSS_RTC 1u -#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u -#define CY_IP_MXS40SRSS_RTC_VERSION 1u -#define CY_IP_MXS40SRSS_MCWDT 1u -#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u -#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u -#define CY_IP_MXSCB 1u -#define CY_IP_MXSCB_INSTANCES 13u -#define CY_IP_MXSCB_VERSION 1u -#define CY_IP_MXPERI 1u -#define CY_IP_MXPERI_INSTANCES 1u -#define CY_IP_MXPERI_VERSION 2u -#define CY_IP_MXPERI_TR 1u -#define CY_IP_MXPERI_TR_INSTANCES 1u -#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 2u +#define CY_IP_MXAUDIOSS_VERSION 1u #define CY_IP_M4CPUSS 1u #define CY_IP_M4CPUSS_INSTANCES 1u #define CY_IP_M4CPUSS_VERSION 2u @@ -537,41 +513,66 @@ typedef enum { #define CY_IP_MXCRYPTO 1u #define CY_IP_MXCRYPTO_INSTANCES 1u #define CY_IP_MXCRYPTO_VERSION 2u -#define CY_IP_MXSDHC 1u -#define CY_IP_MXSDHC_INSTANCES 2u -#define CY_IP_MXSDHC_VERSION 1u -#define CY_IP_MXAUDIOSS 1u -#define CY_IP_MXAUDIOSS_INSTANCES 2u -#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u #define CY_IP_MXLPCOMP 1u #define CY_IP_MXLPCOMP_INSTANCES 1u #define CY_IP_MXLPCOMP_VERSION 1u -#define CY_IP_MXSMIF 1u -#define CY_IP_MXSMIF_INSTANCES 1u -#define CY_IP_MXSMIF_VERSION 1u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u #define CY_IP_MXS40PASS 1u #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u #define CY_IP_MXS40PASS_SAR 1u #define CY_IP_MXS40PASS_SAR_INSTANCES 1u #define CY_IP_MXS40PASS_SAR_VERSION 1u -#define CY_IP_MXS40IOSS 1u -#define CY_IP_MXS40IOSS_INSTANCES 1u -#define CY_IP_MXS40IOSS_VERSION 2u -#define CY_IP_MXEFUSE 1u -#define CY_IP_MXEFUSE_INSTANCES 1u -#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u #define CY_IP_MXPROFILE 1u #define CY_IP_MXPROFILE_INSTANCES 1u #define CY_IP_MXPROFILE_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 13u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 2u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u #include "psoc6_02_config.h" #include "gpio_psoc6_02_124_bga.h" #define CY_DEVICE_PSOC6A2M +#define CY_DEVICE_SECURE #define CY_SILICON_ID 0xE4A01202UL #define CY_HF_CLK_MAX_FREQ 150000000UL @@ -928,6 +929,7 @@ typedef enum { #define PROT_BASE 0x40230000UL #define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ #define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ #define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ #define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ @@ -944,7 +946,22 @@ typedef enum { #define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ #define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ #define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ -#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ #define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ #define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ #define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ @@ -969,22 +986,6 @@ typedef enum { #define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ #define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ #define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ -#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ -#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ -#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ -#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ -#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ -#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ -#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ -#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ -#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ -#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ -#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ -#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ -#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ -#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ -#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ -#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ /******************************************************************************* * FLASHC diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_104_m_csp_ble.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_104_m_csp_ble.h index ab43a2f532..7fb0f99d57 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_104_m_csp_ble.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_104_m_csp_ble.h @@ -5,11 +5,11 @@ * PSoC6_01 device GPIO header for 104-M-CSP-BLE package * * \note -* Generator version: 1.5.0.1304 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -46,16 +46,16 @@ enum /* AMUXBUS Segments */ enum { - AMUXBUS_MAIN, AMUXBUS_ADFT0_VDDD, - AMUXBUS_NOISY, AMUXBUS_ADFT1_VDDD, - AMUXBUS_CSD0, - AMUXBUS_VDDIO_1, - AMUXBUS_CSD1, - AMUXBUS_SAR, - AMUXBUS_ANALOG_VDDD, AMUXBUS_ANALOG_VDDA, + AMUXBUS_ANALOG_VDDD, + AMUXBUS_CSD0, + AMUXBUS_CSD1, + AMUXBUS_MAIN, + AMUXBUS_NOISY, + AMUXBUS_SAR, + AMUXBUS_VDDIO_1, }; /* AMUX Splitter Controls */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_104_m_csp_ble_usb.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_104_m_csp_ble_usb.h index cc8661211b..728c8bcd12 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_104_m_csp_ble_usb.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_104_m_csp_ble_usb.h @@ -5,11 +5,11 @@ * PSoC6_01 device GPIO header for 104-M-CSP-BLE-USB package * * \note -* Generator version: 1.5.0.1304 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -46,16 +46,16 @@ enum /* AMUXBUS Segments */ enum { - AMUXBUS_MAIN, AMUXBUS_ADFT0_VDDD, - AMUXBUS_NOISY, AMUXBUS_ADFT1_VDDD, - AMUXBUS_CSD0, - AMUXBUS_VDDIO_1, - AMUXBUS_CSD1, - AMUXBUS_SAR, - AMUXBUS_ANALOG_VDDD, AMUXBUS_ANALOG_VDDA, + AMUXBUS_ANALOG_VDDD, + AMUXBUS_CSD0, + AMUXBUS_CSD1, + AMUXBUS_MAIN, + AMUXBUS_NOISY, + AMUXBUS_SAR, + AMUXBUS_VDDIO_1, }; /* AMUX Splitter Controls */ @@ -669,12 +669,6 @@ typedef enum P1_5_LCD_SEG11 = 13, /* Digital Deep Sleep - lcd.seg[11]:0 */ P1_5_SCB7_SPI_SELECT2 = 20, /* Digital Active - scb[7].spi_select2:0 */ - /* USBDM */ - USBDM_GPIO = 0, /* GPIO controls 'out' */ - - /* USBDP */ - USBDP_GPIO = 0, /* GPIO controls 'out' */ - /* P5.0 */ P5_0_GPIO = 0, /* GPIO controls 'out' */ P5_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ @@ -1822,7 +1816,13 @@ typedef enum P13_1_SCB6_UART_TX = 18, /* Digital Active - scb[6].uart_tx:1 */ P13_1_SCB6_I2C_SDA = 19, /* Digital Active - scb[6].i2c_sda:1 */ P13_1_SCB6_SPI_MISO = 20, /* Digital Active - scb[6].spi_miso:1 */ - P13_1_PERI_TR_IO_INPUT27 = 24 /* Digital Active - peri.tr_io_input[27]:0 */ + P13_1_PERI_TR_IO_INPUT27 = 24, /* Digital Active - peri.tr_io_input[27]:0 */ + + /* USBDP */ + USBDP_GPIO = 0, /* GPIO controls 'out' */ + + /* USBDM */ + USBDM_GPIO = 0 /* GPIO controls 'out' */ } en_hsiom_sel_t; #endif /* _GPIO_PSOC6_01_104_M_CSP_BLE_USB_H_ */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_116_bga_ble.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_116_bga_ble.h index 2c9b4f4532..9e7a36c19d 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_116_bga_ble.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_116_bga_ble.h @@ -5,11 +5,11 @@ * PSoC6_01 device GPIO header for 116-BGA-BLE package * * \note -* Generator version: 1.5.0.1304 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -46,16 +46,16 @@ enum /* AMUXBUS Segments */ enum { - AMUXBUS_MAIN, AMUXBUS_ADFT0_VDDD, - AMUXBUS_NOISY, AMUXBUS_ADFT1_VDDD, - AMUXBUS_CSD0, - AMUXBUS_VDDIO_1, - AMUXBUS_CSD1, - AMUXBUS_SAR, - AMUXBUS_ANALOG_VDDD, AMUXBUS_ANALOG_VDDA, + AMUXBUS_ANALOG_VDDD, + AMUXBUS_CSD0, + AMUXBUS_CSD1, + AMUXBUS_MAIN, + AMUXBUS_NOISY, + AMUXBUS_SAR, + AMUXBUS_VDDIO_1, }; /* AMUX Splitter Controls */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_116_bga_usb.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_116_bga_usb.h index 08e39964d2..5ca4427fe7 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_116_bga_usb.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_116_bga_usb.h @@ -5,11 +5,11 @@ * PSoC6_01 device GPIO header for 116-BGA-USB package * * \note -* Generator version: 1.5.0.1304 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -46,16 +46,16 @@ enum /* AMUXBUS Segments */ enum { - AMUXBUS_MAIN, AMUXBUS_ADFT0_VDDD, - AMUXBUS_NOISY, AMUXBUS_ADFT1_VDDD, - AMUXBUS_CSD0, - AMUXBUS_VDDIO_1, - AMUXBUS_CSD1, - AMUXBUS_SAR, - AMUXBUS_ANALOG_VDDD, AMUXBUS_ANALOG_VDDA, + AMUXBUS_ANALOG_VDDD, + AMUXBUS_CSD0, + AMUXBUS_CSD1, + AMUXBUS_MAIN, + AMUXBUS_NOISY, + AMUXBUS_SAR, + AMUXBUS_VDDIO_1, }; /* AMUX Splitter Controls */ @@ -687,12 +687,6 @@ typedef enum P1_2_SCB7_UART_RTS = 18, /* Digital Active - scb[7].uart_rts:0 */ P1_2_SCB7_SPI_CLK = 20, /* Digital Active - scb[7].spi_clk:0 */ - /* USBDM */ - USBDM_GPIO = 0, /* GPIO controls 'out' */ - - /* USBDP */ - USBDP_GPIO = 0, /* GPIO controls 'out' */ - /* P5.0 */ P5_0_GPIO = 0, /* GPIO controls 'out' */ P5_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ @@ -1959,7 +1953,13 @@ typedef enum P13_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:100 */ P13_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:100 */ P13_7_LCD_COM38 = 12, /* Digital Deep Sleep - lcd.com[38]:1 */ - P13_7_LCD_SEG38 = 13 /* Digital Deep Sleep - lcd.seg[38]:1 */ + P13_7_LCD_SEG38 = 13, /* Digital Deep Sleep - lcd.seg[38]:1 */ + + /* USBDP */ + USBDP_GPIO = 0, /* GPIO controls 'out' */ + + /* USBDM */ + USBDM_GPIO = 0 /* GPIO controls 'out' */ } en_hsiom_sel_t; #endif /* _GPIO_PSOC6_01_116_BGA_USB_H_ */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_124_bga.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_124_bga.h index f1f07c9a78..37af035c25 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_124_bga.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_124_bga.h @@ -5,11 +5,11 @@ * PSoC6_01 device GPIO header for 124-BGA package * * \note -* Generator version: 1.5.0.1304 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -46,16 +46,16 @@ enum /* AMUXBUS Segments */ enum { - AMUXBUS_MAIN, AMUXBUS_ADFT0_VDDD, - AMUXBUS_NOISY, AMUXBUS_ADFT1_VDDD, - AMUXBUS_CSD0, - AMUXBUS_VDDIO_1, - AMUXBUS_CSD1, - AMUXBUS_SAR, - AMUXBUS_ANALOG_VDDD, AMUXBUS_ANALOG_VDDA, + AMUXBUS_ANALOG_VDDD, + AMUXBUS_CSD0, + AMUXBUS_CSD1, + AMUXBUS_MAIN, + AMUXBUS_NOISY, + AMUXBUS_SAR, + AMUXBUS_VDDIO_1, }; /* AMUX Splitter Controls */ @@ -849,12 +849,6 @@ typedef enum P1_5_LCD_SEG11 = 13, /* Digital Deep Sleep - lcd.seg[11]:0 */ P1_5_SCB7_SPI_SELECT2 = 20, /* Digital Active - scb[7].spi_select2:0 */ - /* USBDM */ - USBDM_GPIO = 0, /* GPIO controls 'out' */ - - /* USBDP */ - USBDP_GPIO = 0, /* GPIO controls 'out' */ - /* P2.0 */ P2_0_GPIO = 0, /* GPIO controls 'out' */ P2_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ @@ -2533,7 +2527,13 @@ typedef enum P13_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:100 */ P13_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:100 */ P13_7_LCD_COM38 = 12, /* Digital Deep Sleep - lcd.com[38]:1 */ - P13_7_LCD_SEG38 = 13 /* Digital Deep Sleep - lcd.seg[38]:1 */ + P13_7_LCD_SEG38 = 13, /* Digital Deep Sleep - lcd.seg[38]:1 */ + + /* USBDP */ + USBDP_GPIO = 0, /* GPIO controls 'out' */ + + /* USBDM */ + USBDM_GPIO = 0 /* GPIO controls 'out' */ } en_hsiom_sel_t; #endif /* _GPIO_PSOC6_01_124_BGA_H_ */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_124_bga_sip.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_124_bga_sip.h index 15c7230c50..303f0706ce 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_124_bga_sip.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_124_bga_sip.h @@ -5,11 +5,11 @@ * PSoC6_01 device GPIO header for 124-BGA-SIP package * * \note -* Generator version: 1.5.0.1304 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -46,16 +46,16 @@ enum /* AMUXBUS Segments */ enum { - AMUXBUS_MAIN, AMUXBUS_ADFT0_VDDD, - AMUXBUS_NOISY, AMUXBUS_ADFT1_VDDD, - AMUXBUS_CSD0, - AMUXBUS_VDDIO_1, - AMUXBUS_CSD1, - AMUXBUS_SAR, - AMUXBUS_ANALOG_VDDD, AMUXBUS_ANALOG_VDDA, + AMUXBUS_ANALOG_VDDD, + AMUXBUS_CSD0, + AMUXBUS_CSD1, + AMUXBUS_MAIN, + AMUXBUS_NOISY, + AMUXBUS_SAR, + AMUXBUS_VDDIO_1, }; /* AMUX Splitter Controls */ @@ -779,12 +779,6 @@ typedef enum P1_5_LCD_SEG11 = 13, /* Digital Deep Sleep - lcd.seg[11]:0 */ P1_5_SCB7_SPI_SELECT2 = 20, /* Digital Active - scb[7].spi_select2:0 */ - /* USBDM */ - USBDM_GPIO = 0, /* GPIO controls 'out' */ - - /* USBDP */ - USBDP_GPIO = 0, /* GPIO controls 'out' */ - /* P5.0 */ P5_0_GPIO = 0, /* GPIO controls 'out' */ P5_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ @@ -2154,7 +2148,13 @@ typedef enum P13_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:100 */ P13_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:100 */ P13_7_LCD_COM38 = 12, /* Digital Deep Sleep - lcd.com[38]:1 */ - P13_7_LCD_SEG38 = 13 /* Digital Deep Sleep - lcd.seg[38]:1 */ + P13_7_LCD_SEG38 = 13, /* Digital Deep Sleep - lcd.seg[38]:1 */ + + /* USBDP */ + USBDP_GPIO = 0, /* GPIO controls 'out' */ + + /* USBDM */ + USBDM_GPIO = 0 /* GPIO controls 'out' */ } en_hsiom_sel_t; #endif /* _GPIO_PSOC6_01_124_BGA_SIP_H_ */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_43_smt.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_43_smt.h index fca88f2943..dae2d3d3b4 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_43_smt.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_43_smt.h @@ -5,11 +5,11 @@ * PSoC6_01 device GPIO header for 43-SMT package * * \note -* Generator version: 1.5.0.1304 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -46,16 +46,16 @@ enum /* AMUXBUS Segments */ enum { - AMUXBUS_MAIN, AMUXBUS_ADFT0_VDDD, - AMUXBUS_NOISY, AMUXBUS_ADFT1_VDDD, - AMUXBUS_CSD0, - AMUXBUS_VDDIO_1, - AMUXBUS_CSD1, - AMUXBUS_SAR, - AMUXBUS_ANALOG_VDDD, AMUXBUS_ANALOG_VDDA, + AMUXBUS_ANALOG_VDDD, + AMUXBUS_CSD0, + AMUXBUS_CSD1, + AMUXBUS_MAIN, + AMUXBUS_NOISY, + AMUXBUS_SAR, + AMUXBUS_VDDIO_1, }; /* AMUX Splitter Controls */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_68_qfn_ble.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_68_qfn_ble.h index 2719e9bda0..a0861f58ca 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_68_qfn_ble.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_68_qfn_ble.h @@ -5,11 +5,11 @@ * PSoC6_01 device GPIO header for 68-QFN-BLE package * * \note -* Generator version: 1.5.0.1304 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -46,16 +46,16 @@ enum /* AMUXBUS Segments */ enum { - AMUXBUS_MAIN, AMUXBUS_ADFT0_VDDD, - AMUXBUS_NOISY, AMUXBUS_ADFT1_VDDD, - AMUXBUS_CSD0, - AMUXBUS_VDDIO_1, - AMUXBUS_CSD1, - AMUXBUS_SAR, - AMUXBUS_ANALOG_VDDD, AMUXBUS_ANALOG_VDDA, + AMUXBUS_ANALOG_VDDD, + AMUXBUS_CSD0, + AMUXBUS_CSD1, + AMUXBUS_MAIN, + AMUXBUS_NOISY, + AMUXBUS_SAR, + AMUXBUS_VDDIO_1, }; /* AMUX Splitter Controls */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_80_wlcsp.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_80_wlcsp.h index 09f3677beb..983e926b14 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_80_wlcsp.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_01_80_wlcsp.h @@ -5,11 +5,11 @@ * PSoC6_01 device GPIO header for 80-WLCSP package * * \note -* Generator version: 1.5.0.1304 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -46,16 +46,16 @@ enum /* AMUXBUS Segments */ enum { - AMUXBUS_MAIN, AMUXBUS_ADFT0_VDDD, - AMUXBUS_NOISY, AMUXBUS_ADFT1_VDDD, - AMUXBUS_CSD0, - AMUXBUS_VDDIO_1, - AMUXBUS_CSD1, - AMUXBUS_SAR, - AMUXBUS_ANALOG_VDDD, AMUXBUS_ANALOG_VDDA, + AMUXBUS_ANALOG_VDDD, + AMUXBUS_CSD0, + AMUXBUS_CSD1, + AMUXBUS_MAIN, + AMUXBUS_NOISY, + AMUXBUS_SAR, + AMUXBUS_VDDIO_1, }; /* AMUX Splitter Controls */ @@ -641,12 +641,6 @@ typedef enum P1_5_LCD_SEG11 = 13, /* Digital Deep Sleep - lcd.seg[11]:0 */ P1_5_SCB7_SPI_SELECT2 = 20, /* Digital Active - scb[7].spi_select2:0 */ - /* USBDM */ - USBDM_GPIO = 0, /* GPIO controls 'out' */ - - /* USBDP */ - USBDP_GPIO = 0, /* GPIO controls 'out' */ - /* P5.0 */ P5_0_GPIO = 0, /* GPIO controls 'out' */ P5_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ @@ -1660,7 +1654,13 @@ typedef enum P12_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:92 */ P12_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:92 */ P12_7_LCD_COM30 = 12, /* Digital Deep Sleep - lcd.com[30]:1 */ - P12_7_LCD_SEG30 = 13 /* Digital Deep Sleep - lcd.seg[30]:1 */ + P12_7_LCD_SEG30 = 13, /* Digital Deep Sleep - lcd.seg[30]:1 */ + + /* USBDP */ + USBDP_GPIO = 0, /* GPIO controls 'out' */ + + /* USBDM */ + USBDM_GPIO = 0 /* GPIO controls 'out' */ } en_hsiom_sel_t; #endif /* _GPIO_PSOC6_01_80_WLCSP_H_ */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_02_100_wlcsp.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_02_100_wlcsp.h index e675fde8c5..0011261e4c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_02_100_wlcsp.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_02_100_wlcsp.h @@ -5,11 +5,11 @@ * PSoC6_02 device GPIO header for 100-WLCSP package * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -46,15 +46,15 @@ enum /* AMUXBUS Segments */ enum { - AMUXBUS_MAIN, AMUXBUS_ADFT0_VDDD, - AMUXBUS_NOISY, - AMUXBUS_CSD0, - AMUXBUS_VDDIO_1, - AMUXBUS_CSD1, - AMUXBUS_SAR, - AMUXBUS_ANALOG_VDDD, AMUXBUS_ANALOG_VDDA, + AMUXBUS_ANALOG_VDDD, + AMUXBUS_CSD0, + AMUXBUS_CSD1, + AMUXBUS_MAIN, + AMUXBUS_NOISY, + AMUXBUS_SAR, + AMUXBUS_VDDIO_1, }; /* AMUX Splitter Controls */ @@ -685,12 +685,6 @@ typedef enum P1_5_LCD_SEG11 = 13, /* Digital Deep Sleep - lcd.seg[11]:0 */ P1_5_SCB7_SPI_SELECT2 = 20, /* Digital Active - scb[7].spi_select2:0 */ - /* USBDM */ - USBDM_GPIO = 0, /* GPIO controls 'out' */ - - /* USBDP */ - USBDP_GPIO = 0, /* GPIO controls 'out' */ - /* P2.0 */ P2_0_GPIO = 0, /* GPIO controls 'out' */ P2_0_AMUXA = 4, /* Analog mux bus A */ @@ -1895,7 +1889,13 @@ typedef enum P13_7_LCD_COM38 = 12, /* Digital Deep Sleep - lcd.com[38]:1 */ P13_7_LCD_SEG38 = 13, /* Digital Deep Sleep - lcd.seg[38]:1 */ P13_7_SCB12_UART_CTS = 18, /* Digital Active - scb[12].uart_cts:0 */ - P13_7_SDHC1_CARD_DAT_7TO43 = 26 /* Digital Active - sdhc[1].card_dat_7to4[3] */ + P13_7_SDHC1_CARD_DAT_7TO43 = 26, /* Digital Active - sdhc[1].card_dat_7to4[3] */ + + /* USBDP */ + USBDP_GPIO = 0, /* GPIO controls 'out' */ + + /* USBDM */ + USBDM_GPIO = 0 /* GPIO controls 'out' */ } en_hsiom_sel_t; #endif /* _GPIO_PSOC6_02_100_WLCSP_H_ */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_02_124_bga.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_02_124_bga.h index a130bc75b2..2c31a3c7f6 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_02_124_bga.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_02_124_bga.h @@ -5,11 +5,11 @@ * PSoC6_02 device GPIO header for 124-BGA package * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -46,15 +46,15 @@ enum /* AMUXBUS Segments */ enum { - AMUXBUS_MAIN, AMUXBUS_ADFT0_VDDD, - AMUXBUS_NOISY, - AMUXBUS_CSD0, - AMUXBUS_VDDIO_1, - AMUXBUS_CSD1, - AMUXBUS_SAR, - AMUXBUS_ANALOG_VDDD, AMUXBUS_ANALOG_VDDA, + AMUXBUS_ANALOG_VDDD, + AMUXBUS_CSD0, + AMUXBUS_CSD1, + AMUXBUS_MAIN, + AMUXBUS_NOISY, + AMUXBUS_SAR, + AMUXBUS_VDDIO_1, }; /* AMUX Splitter Controls */ @@ -791,12 +791,6 @@ typedef enum P1_5_LCD_SEG11 = 13, /* Digital Deep Sleep - lcd.seg[11]:0 */ P1_5_SCB7_SPI_SELECT2 = 20, /* Digital Active - scb[7].spi_select2:0 */ - /* USBDM */ - USBDM_GPIO = 0, /* GPIO controls 'out' */ - - /* USBDP */ - USBDP_GPIO = 0, /* GPIO controls 'out' */ - /* P2.0 */ P2_0_GPIO = 0, /* GPIO controls 'out' */ P2_0_AMUXA = 4, /* Analog mux bus A */ @@ -2250,7 +2244,13 @@ typedef enum P13_7_LCD_COM38 = 12, /* Digital Deep Sleep - lcd.com[38]:1 */ P13_7_LCD_SEG38 = 13, /* Digital Deep Sleep - lcd.seg[38]:1 */ P13_7_SCB12_UART_CTS = 18, /* Digital Active - scb[12].uart_cts:0 */ - P13_7_SDHC1_CARD_DAT_7TO43 = 26 /* Digital Active - sdhc[1].card_dat_7to4[3] */ + P13_7_SDHC1_CARD_DAT_7TO43 = 26, /* Digital Active - sdhc[1].card_dat_7to4[3] */ + + /* USBDP */ + USBDP_GPIO = 0, /* GPIO controls 'out' */ + + /* USBDM */ + USBDM_GPIO = 0 /* GPIO controls 'out' */ } en_hsiom_sel_t; #endif /* _GPIO_PSOC6_02_124_BGA_H_ */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_02_128_tqfp.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_02_128_tqfp.h index a3e99fca78..7368823ad4 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_02_128_tqfp.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_02_128_tqfp.h @@ -5,11 +5,11 @@ * PSoC6_02 device GPIO header for 128-TQFP package * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -46,15 +46,15 @@ enum /* AMUXBUS Segments */ enum { - AMUXBUS_MAIN, AMUXBUS_ADFT0_VDDD, - AMUXBUS_NOISY, - AMUXBUS_CSD0, - AMUXBUS_VDDIO_1, - AMUXBUS_CSD1, - AMUXBUS_SAR, - AMUXBUS_ANALOG_VDDD, AMUXBUS_ANALOG_VDDA, + AMUXBUS_ANALOG_VDDD, + AMUXBUS_CSD0, + AMUXBUS_CSD1, + AMUXBUS_MAIN, + AMUXBUS_NOISY, + AMUXBUS_SAR, + AMUXBUS_VDDIO_1, }; /* AMUX Splitter Controls */ @@ -799,12 +799,6 @@ typedef enum P1_5_LCD_SEG11 = 13, /* Digital Deep Sleep - lcd.seg[11]:0 */ P1_5_SCB7_SPI_SELECT2 = 20, /* Digital Active - scb[7].spi_select2:0 */ - /* USBDM */ - USBDM_GPIO = 0, /* GPIO controls 'out' */ - - /* USBDP */ - USBDP_GPIO = 0, /* GPIO controls 'out' */ - /* P2.0 */ P2_0_GPIO = 0, /* GPIO controls 'out' */ P2_0_AMUXA = 4, /* Analog mux bus A */ @@ -2288,7 +2282,13 @@ typedef enum P13_7_LCD_COM38 = 12, /* Digital Deep Sleep - lcd.com[38]:1 */ P13_7_LCD_SEG38 = 13, /* Digital Deep Sleep - lcd.seg[38]:1 */ P13_7_SCB12_UART_CTS = 18, /* Digital Active - scb[12].uart_cts:0 */ - P13_7_SDHC1_CARD_DAT_7TO43 = 26 /* Digital Active - sdhc[1].card_dat_7to4[3] */ + P13_7_SDHC1_CARD_DAT_7TO43 = 26, /* Digital Active - sdhc[1].card_dat_7to4[3] */ + + /* USBDP */ + USBDP_GPIO = 0, /* GPIO controls 'out' */ + + /* USBDM */ + USBDM_GPIO = 0 /* GPIO controls 'out' */ } en_hsiom_sel_t; #endif /* _GPIO_PSOC6_02_128_TQFP_H_ */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_02_68_qfn.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_02_68_qfn.h index 6993974551..4b9259642d 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_02_68_qfn.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_02_68_qfn.h @@ -5,11 +5,11 @@ * PSoC6_02 device GPIO header for 68-QFN package * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -46,15 +46,15 @@ enum /* AMUXBUS Segments */ enum { - AMUXBUS_MAIN, AMUXBUS_ADFT0_VDDD, - AMUXBUS_NOISY, - AMUXBUS_CSD0, - AMUXBUS_VDDIO_1, - AMUXBUS_CSD1, - AMUXBUS_SAR, - AMUXBUS_ANALOG_VDDD, AMUXBUS_ANALOG_VDDA, + AMUXBUS_ANALOG_VDDD, + AMUXBUS_CSD0, + AMUXBUS_CSD1, + AMUXBUS_MAIN, + AMUXBUS_NOISY, + AMUXBUS_SAR, + AMUXBUS_VDDIO_1, }; /* AMUX Splitter Controls */ @@ -499,12 +499,6 @@ typedef enum P0_5_SCB0_SPI_SELECT0 = 20, /* Digital Active - scb[0].spi_select0:0 */ P0_5_PERI_TR_IO_OUTPUT1 = 25, /* Digital Active - peri.tr_io_output[1]:2 */ - /* USBDM */ - USBDM_GPIO = 0, /* GPIO controls 'out' */ - - /* USBDP */ - USBDP_GPIO = 0, /* GPIO controls 'out' */ - /* P2.0 */ P2_0_GPIO = 0, /* GPIO controls 'out' */ P2_0_AMUXA = 4, /* Analog mux bus A */ @@ -1293,7 +1287,13 @@ typedef enum P12_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:92 */ P12_7_LCD_COM30 = 12, /* Digital Deep Sleep - lcd.com[30]:1 */ P12_7_LCD_SEG30 = 13, /* Digital Deep Sleep - lcd.seg[30]:1 */ - P12_7_SDHC1_IO_VOLT_SEL = 26 /* Digital Active - sdhc[1].io_volt_sel */ + P12_7_SDHC1_IO_VOLT_SEL = 26, /* Digital Active - sdhc[1].io_volt_sel */ + + /* USBDP */ + USBDP_GPIO = 0, /* GPIO controls 'out' */ + + /* USBDM */ + USBDM_GPIO = 0 /* GPIO controls 'out' */ } en_hsiom_sel_t; #endif /* _GPIO_PSOC6_02_68_QFN_H_ */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_03_100_tqfp.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_03_100_tqfp.h index 6d543c0aec..d34f9e186e 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_03_100_tqfp.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_03_100_tqfp.h @@ -5,11 +5,11 @@ * PSoC6_03 device GPIO header for 100-TQFP package * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -46,14 +46,14 @@ enum /* AMUXBUS Segments */ enum { - AMUXBUS_SRSS_AMUXBUSA_ADFT_VDDD, - AMUXBUS_SRSS_AMUXBUSB_ADFT_VDDD, - AMUXBUS_VSSA, - AMUXBUS_VDDIO_1, + AMUXBUS_ANALOG_VDDD, AMUXBUS_CSD0, AMUXBUS_CSD1, AMUXBUS_SAR, - AMUXBUS_ANALOG_VDDD, + AMUXBUS_VDDIO_1, + AMUXBUS_VSSA, + AMUXBUS_SRSS_AMUXBUSA_ADFT_VDDD, + AMUXBUS_SRSS_AMUXBUSB_ADFT_VDDD, }; /* AMUX Splitter Controls */ @@ -496,12 +496,6 @@ typedef enum P0_5_PERI_TR_IO_INPUT3 = 24, /* Digital Active - peri.tr_io_input[3]:0 */ P0_5_PERI_TR_IO_OUTPUT1 = 25, /* Digital Active - peri.tr_io_output[1]:2 */ - /* USBDM */ - USBDM_GPIO = 0, /* GPIO controls 'out' */ - - /* USBDP */ - USBDP_GPIO = 0, /* GPIO controls 'out' */ - /* P2.0 */ P2_0_GPIO = 0, /* GPIO controls 'out' */ P2_0_AMUXA = 4, /* Analog mux bus A */ @@ -1428,7 +1422,13 @@ typedef enum P12_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:63 */ P12_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:63 */ P12_7_LCD_COM3 = 12, /* Digital Deep Sleep - lcd.com[3]:1 */ - P12_7_LCD_SEG3 = 13 /* Digital Deep Sleep - lcd.seg[3]:1 */ + P12_7_LCD_SEG3 = 13, /* Digital Deep Sleep - lcd.seg[3]:1 */ + + /* USBDP */ + USBDP_GPIO = 0, /* GPIO controls 'out' */ + + /* USBDM */ + USBDM_GPIO = 0 /* GPIO controls 'out' */ } en_hsiom_sel_t; #endif /* _GPIO_PSOC6_03_100_TQFP_H_ */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_03_49_wlcsp.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_03_49_wlcsp.h index e47a5345da..4eff9daf1b 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_03_49_wlcsp.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_03_49_wlcsp.h @@ -5,11 +5,11 @@ * PSoC6_03 device GPIO header for 49-WLCSP package * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -46,14 +46,14 @@ enum /* AMUXBUS Segments */ enum { - AMUXBUS_SRSS_AMUXBUSA_ADFT_VDDD, - AMUXBUS_SRSS_AMUXBUSB_ADFT_VDDD, - AMUXBUS_VSSA, - AMUXBUS_VDDIO_1, + AMUXBUS_ANALOG_VDDD, AMUXBUS_CSD0, AMUXBUS_CSD1, AMUXBUS_SAR, - AMUXBUS_ANALOG_VDDD, + AMUXBUS_VDDIO_1, + AMUXBUS_VSSA, + AMUXBUS_SRSS_AMUXBUSA_ADFT_VDDD, + AMUXBUS_SRSS_AMUXBUSB_ADFT_VDDD, }; /* AMUX Splitter Controls */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_03_68_qfn.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_03_68_qfn.h index 3842d65925..2fecaeb37c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_03_68_qfn.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_03_68_qfn.h @@ -5,11 +5,11 @@ * PSoC6_03 device GPIO header for 68-QFN package * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -46,14 +46,14 @@ enum /* AMUXBUS Segments */ enum { - AMUXBUS_SRSS_AMUXBUSA_ADFT_VDDD, - AMUXBUS_SRSS_AMUXBUSB_ADFT_VDDD, - AMUXBUS_VSSA, - AMUXBUS_VDDIO_1, + AMUXBUS_ANALOG_VDDD, AMUXBUS_CSD0, AMUXBUS_CSD1, AMUXBUS_SAR, - AMUXBUS_ANALOG_VDDD, + AMUXBUS_VDDIO_1, + AMUXBUS_VSSA, + AMUXBUS_SRSS_AMUXBUSA_ADFT_VDDD, + AMUXBUS_SRSS_AMUXBUSB_ADFT_VDDD, }; /* AMUX Splitter Controls */ @@ -454,12 +454,6 @@ typedef enum P0_5_PERI_TR_IO_INPUT3 = 24, /* Digital Active - peri.tr_io_input[3]:0 */ P0_5_PERI_TR_IO_OUTPUT1 = 25, /* Digital Active - peri.tr_io_output[1]:2 */ - /* USBDM */ - USBDM_GPIO = 0, /* GPIO controls 'out' */ - - /* USBDP */ - USBDP_GPIO = 0, /* GPIO controls 'out' */ - /* P2.0 */ P2_0_GPIO = 0, /* GPIO controls 'out' */ P2_0_AMUXA = 4, /* Analog mux bus A */ @@ -1218,7 +1212,13 @@ typedef enum P12_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:63 */ P12_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:63 */ P12_7_LCD_COM3 = 12, /* Digital Deep Sleep - lcd.com[3]:1 */ - P12_7_LCD_SEG3 = 13 /* Digital Deep Sleep - lcd.seg[3]:1 */ + P12_7_LCD_SEG3 = 13, /* Digital Deep Sleep - lcd.seg[3]:1 */ + + /* USBDP */ + USBDP_GPIO = 0, /* GPIO controls 'out' */ + + /* USBDM */ + USBDM_GPIO = 0 /* GPIO controls 'out' */ } en_hsiom_sel_t; #endif /* _GPIO_PSOC6_03_68_QFN_H_ */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_04_64_tqfp.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_04_64_tqfp.h index 4611628c57..4c4dfd5311 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_04_64_tqfp.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_04_64_tqfp.h @@ -5,7 +5,7 @@ * PSoC6_04 device GPIO header for 64-TQFP package * * \note -* Generator version: 1.6.0.111 +* Generator version: 1.6.0.150 * ******************************************************************************** * \copyright @@ -363,41 +363,41 @@ typedef enum typedef enum { /* Generic HSIOM connections */ - HSIOM_SEL_GPIO = 0, /* N/A */ - HSIOM_SEL_GPIO_DSI = 1, /* N/A */ - HSIOM_SEL_DSI_DSI = 2, /* N/A */ - HSIOM_SEL_DSI_GPIO = 3, /* N/A */ - HSIOM_SEL_AMUXA = 4, /* AMUXBUS A */ - HSIOM_SEL_AMUXB = 5, /* AMUXBUS B */ - HSIOM_SEL_AMUXA_DSI = 6, /* N/A */ - HSIOM_SEL_AMUXB_DSI = 7, /* N/A */ - HSIOM_SEL_ACT_0 = 8, /* Active peripherals 0 */ - HSIOM_SEL_ACT_1 = 9, /* Active peripherals 1 */ - HSIOM_SEL_ACT_2 = 10, /* Active peripherals 2 */ - HSIOM_SEL_ACT_3 = 11, /* Active peripherals 4 */ - HSIOM_SEL_DS_0 = 12, /* Deep Sleep peripherals 0 */ - HSIOM_SEL_DS_1 = 13, /* Deep Sleep peripherals 1 */ - HSIOM_SEL_DS_2 = 14, /* Deep Sleep peripherals 2 */ - HSIOM_SEL_DS_3 = 15, /* Deep Sleep peripherals 3 */ - HSIOM_SEL_ACT_4 = 16, /* Active peripherals 4 */ - HSIOM_SEL_ACT_5 = 17, /* Active peripherals 5 */ - HSIOM_SEL_ACT_6 = 18, /* Active peripherals 6 */ - HSIOM_SEL_ACT_7 = 19, /* Active peripherals 7 */ - HSIOM_SEL_ACT_8 = 20, /* Active peripherals 8 */ - HSIOM_SEL_ACT_9 = 21, /* Active peripherals 9 */ - HSIOM_SEL_ACT_10 = 22, /* Active peripherals 10 */ - HSIOM_SEL_ACT_11 = 23, /* Active peripherals 11 */ - HSIOM_SEL_ACT_12 = 24, /* Active peripherals 12 */ - HSIOM_SEL_ACT_13 = 25, /* Active peripherals 13 */ - HSIOM_SEL_ACT_14 = 26, /* Active peripherals 14 */ - HSIOM_SEL_ACT_15 = 27, /* Active peripherals 15 */ - HSIOM_SEL_DS_4 = 28, /* N/A */ - HSIOM_SEL_DS_5 = 29, /* N/A */ - HSIOM_SEL_DS_6 = 30, /* N/A */ - HSIOM_SEL_DS_7 = 31, /* N/A */ + HSIOM_SEL_GPIO = 0, /* GPIO controls 'out' */ + HSIOM_SEL_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + HSIOM_SEL_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + HSIOM_SEL_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + HSIOM_SEL_AMUXA = 4, /* Analog mux bus A */ + HSIOM_SEL_AMUXB = 5, /* Analog mux bus B */ + HSIOM_SEL_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + HSIOM_SEL_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + HSIOM_SEL_ACT_0 = 8, /* Active functionality 0 */ + HSIOM_SEL_ACT_1 = 9, /* Active functionality 1 */ + HSIOM_SEL_ACT_2 = 10, /* Active functionality 2 */ + HSIOM_SEL_ACT_3 = 11, /* Active functionality 3 */ + HSIOM_SEL_DS_0 = 12, /* DeepSleep functionality 0 */ + HSIOM_SEL_DS_1 = 13, /* DeepSleep functionality 1 */ + HSIOM_SEL_DS_2 = 14, /* DeepSleep functionality 2 */ + HSIOM_SEL_DS_3 = 15, /* DeepSleep functionality 3 */ + HSIOM_SEL_ACT_4 = 16, /* Active functionality 4 */ + HSIOM_SEL_ACT_5 = 17, /* Active functionality 5 */ + HSIOM_SEL_ACT_6 = 18, /* Active functionality 6 */ + HSIOM_SEL_ACT_7 = 19, /* Active functionality 7 */ + HSIOM_SEL_ACT_8 = 20, /* Active functionality 8 */ + HSIOM_SEL_ACT_9 = 21, /* Active functionality 9 */ + HSIOM_SEL_ACT_10 = 22, /* Active functionality 10 */ + HSIOM_SEL_ACT_11 = 23, /* Active functionality 11 */ + HSIOM_SEL_ACT_12 = 24, /* Active functionality 12 */ + HSIOM_SEL_ACT_13 = 25, /* Active functionality 13 */ + HSIOM_SEL_ACT_14 = 26, /* Active functionality 14 */ + HSIOM_SEL_ACT_15 = 27, /* Active functionality 15 */ + HSIOM_SEL_DS_4 = 28, /* DeepSleep functionality 4 */ + HSIOM_SEL_DS_5 = 29, /* DeepSleep functionality 5 */ + HSIOM_SEL_DS_6 = 30, /* DeepSleep functionality 6 */ + HSIOM_SEL_DS_7 = 31, /* DeepSleep functionality 7 */ /* P0.0 */ - P0_0_GPIO = 0, /* N/A */ + P0_0_GPIO = 0, /* GPIO controls 'out' */ P0_0_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:0 */ P0_0_TCPWM0_LINE256 = 9, /* Digital Active - tcpwm[0].line[256]:0 */ P0_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:0 */ @@ -410,7 +410,7 @@ typedef enum P0_0_PERI_TR_IO_INPUT0 = 24, /* Digital Active - peri.tr_io_input[0]:0 */ /* P0.1 */ - P0_1_GPIO = 0, /* N/A */ + P0_1_GPIO = 0, /* GPIO controls 'out' */ P0_1_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:0 */ P0_1_TCPWM0_LINE_COMPL256 = 9, /* Digital Active - tcpwm[0].line_compl[256]:0 */ P0_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:1 */ @@ -423,7 +423,7 @@ typedef enum P0_1_CPUSS_SWJ_TRSTN = 29, /* Digital Deep Sleep - cpuss.swj_trstn */ /* P0.2 */ - P0_2_GPIO = 0, /* N/A */ + P0_2_GPIO = 0, /* GPIO controls 'out' */ P0_2_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:0 */ P0_2_TCPWM0_LINE257 = 9, /* Digital Active - tcpwm[0].line[257]:0 */ P0_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:2 */ @@ -436,7 +436,7 @@ typedef enum P0_2_TCPWM0_TR_ONE_CNT_IN2 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[2]:0 */ /* P0.3 */ - P0_3_GPIO = 0, /* N/A */ + P0_3_GPIO = 0, /* GPIO controls 'out' */ P0_3_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:0 */ P0_3_TCPWM0_LINE_COMPL257 = 9, /* Digital Active - tcpwm[0].line_compl[257]:0 */ P0_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:3 */ @@ -449,7 +449,7 @@ typedef enum P0_3_TCPWM0_TR_ONE_CNT_IN3 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[3]:0 */ /* P0.4 */ - P0_4_GPIO = 0, /* N/A */ + P0_4_GPIO = 0, /* GPIO controls 'out' */ P0_4_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:0 */ P0_4_TCPWM0_LINE258 = 9, /* Digital Active - tcpwm[0].line[258]:0 */ P0_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:4 */ @@ -463,7 +463,7 @@ typedef enum P0_4_PERI_TR_IO_OUTPUT0 = 25, /* Digital Active - peri.tr_io_output[0]:2 */ /* P0.5 */ - P0_5_GPIO = 0, /* N/A */ + P0_5_GPIO = 0, /* GPIO controls 'out' */ P0_5_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:0 */ P0_5_TCPWM0_LINE_COMPL258 = 9, /* Digital Active - tcpwm[0].line_compl[258]:0 */ P0_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:5 */ @@ -478,7 +478,7 @@ typedef enum P0_5_PERI_TR_IO_OUTPUT1 = 25, /* Digital Active - peri.tr_io_output[1]:2 */ /* P2.0 */ - P2_0_GPIO = 0, /* N/A */ + P2_0_GPIO = 0, /* GPIO controls 'out' */ P2_0_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:0 */ P2_0_TCPWM0_LINE259 = 9, /* Digital Active - tcpwm[0].line[259]:0 */ P2_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:9 */ @@ -492,7 +492,7 @@ typedef enum P2_0_PERI_TR_IO_INPUT4 = 24, /* Digital Active - peri.tr_io_input[4]:0 */ /* P2.1 */ - P2_1_GPIO = 0, /* N/A */ + P2_1_GPIO = 0, /* GPIO controls 'out' */ P2_1_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:0 */ P2_1_TCPWM0_LINE_COMPL259 = 9, /* Digital Active - tcpwm[0].line_compl[259]:0 */ P2_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:10 */ @@ -506,7 +506,7 @@ typedef enum P2_1_PERI_TR_IO_INPUT5 = 24, /* Digital Active - peri.tr_io_input[5]:0 */ /* P2.2 */ - P2_2_GPIO = 0, /* N/A */ + P2_2_GPIO = 0, /* GPIO controls 'out' */ P2_2_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:1 */ P2_2_TCPWM0_LINE260 = 9, /* Digital Active - tcpwm[0].line[260]:0 */ P2_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:11 */ @@ -518,7 +518,7 @@ typedef enum P2_2_TCPWM0_TR_ONE_CNT_IN263 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[263]:0 */ /* P2.3 */ - P2_3_GPIO = 0, /* N/A */ + P2_3_GPIO = 0, /* GPIO controls 'out' */ P2_3_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:1 */ P2_3_TCPWM0_LINE_COMPL260 = 9, /* Digital Active - tcpwm[0].line_compl[260]:0 */ P2_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:12 */ @@ -530,7 +530,7 @@ typedef enum P2_3_TCPWM0_TR_ONE_CNT_IN0 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[0]:1 */ /* P2.4 */ - P2_4_GPIO = 0, /* N/A */ + P2_4_GPIO = 0, /* GPIO controls 'out' */ P2_4_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:1 */ P2_4_TCPWM0_LINE261 = 9, /* Digital Active - tcpwm[0].line[261]:0 */ P2_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:13 */ @@ -541,7 +541,7 @@ typedef enum P2_4_TCPWM0_TR_ONE_CNT_IN1 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[1]:1 */ /* P2.5 */ - P2_5_GPIO = 0, /* N/A */ + P2_5_GPIO = 0, /* GPIO controls 'out' */ P2_5_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:1 */ P2_5_TCPWM0_LINE_COMPL261 = 9, /* Digital Active - tcpwm[0].line_compl[261]:0 */ P2_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:14 */ @@ -552,7 +552,7 @@ typedef enum P2_5_TCPWM0_TR_ONE_CNT_IN2 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[2]:1 */ /* P2.6 */ - P2_6_GPIO = 0, /* N/A */ + P2_6_GPIO = 0, /* GPIO controls 'out' */ P2_6_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:1 */ P2_6_TCPWM0_LINE262 = 9, /* Digital Active - tcpwm[0].line[262]:0 */ P2_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:15 */ @@ -565,7 +565,7 @@ typedef enum P2_6_PERI_TR_IO_INPUT8 = 24, /* Digital Active - peri.tr_io_input[8]:0 */ /* P2.7 */ - P2_7_GPIO = 0, /* N/A */ + P2_7_GPIO = 0, /* GPIO controls 'out' */ P2_7_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:1 */ P2_7_TCPWM0_LINE_COMPL262 = 9, /* Digital Active - tcpwm[0].line_compl[262]:0 */ P2_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:16 */ @@ -577,7 +577,7 @@ typedef enum P2_7_PERI_TR_IO_INPUT9 = 24, /* Digital Active - peri.tr_io_input[9]:0 */ /* P3.0 */ - P3_0_GPIO = 0, /* N/A */ + P3_0_GPIO = 0, /* GPIO controls 'out' */ P3_0_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:1 */ P3_0_TCPWM0_LINE263 = 9, /* Digital Active - tcpwm[0].line[263]:0 */ P3_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:17 */ @@ -590,7 +590,7 @@ typedef enum P3_0_PERI_TR_IO_INPUT6 = 24, /* Digital Active - peri.tr_io_input[6]:0 */ /* P3.1 */ - P3_1_GPIO = 0, /* N/A */ + P3_1_GPIO = 0, /* GPIO controls 'out' */ P3_1_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:1 */ P3_1_TCPWM0_LINE_COMPL263 = 9, /* Digital Active - tcpwm[0].line_compl[263]:0 */ P3_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:18 */ @@ -603,7 +603,7 @@ typedef enum P3_1_PERI_TR_IO_INPUT7 = 24, /* Digital Active - peri.tr_io_input[7]:0 */ /* P5.0 */ - P5_0_GPIO = 0, /* N/A */ + P5_0_GPIO = 0, /* GPIO controls 'out' */ P5_0_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:2 */ P5_0_TCPWM0_LINE256 = 9, /* Digital Active - tcpwm[0].line[256]:1 */ P5_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:19 */ @@ -618,7 +618,7 @@ typedef enum P5_0_PERI_TR_IO_INPUT10 = 24, /* Digital Active - peri.tr_io_input[10]:0 */ /* P5.1 */ - P5_1_GPIO = 0, /* N/A */ + P5_1_GPIO = 0, /* GPIO controls 'out' */ P5_1_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:2 */ P5_1_TCPWM0_LINE_COMPL256 = 9, /* Digital Active - tcpwm[0].line_compl[256]:1 */ P5_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:20 */ @@ -633,7 +633,7 @@ typedef enum P5_1_PERI_TR_IO_INPUT11 = 24, /* Digital Active - peri.tr_io_input[11]:0 */ /* P5.6 */ - P5_6_GPIO = 0, /* N/A */ + P5_6_GPIO = 0, /* GPIO controls 'out' */ P5_6_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:2 */ P5_6_TCPWM0_LINE257 = 9, /* Digital Active - tcpwm[0].line[257]:1 */ P5_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:22 */ @@ -643,7 +643,7 @@ typedef enum P5_6_TCPWM0_TR_ONE_CNT_IN262 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[262]:1 */ /* P5.7 */ - P5_7_GPIO = 0, /* N/A */ + P5_7_GPIO = 0, /* GPIO controls 'out' */ P5_7_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:2 */ P5_7_TCPWM0_LINE_COMPL257 = 9, /* Digital Active - tcpwm[0].line_compl[257]:1 */ P5_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:23 */ @@ -653,7 +653,7 @@ typedef enum P5_7_TCPWM0_TR_ONE_CNT_IN263 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[263]:1 */ /* P6.2 */ - P6_2_GPIO = 0, /* N/A */ + P6_2_GPIO = 0, /* GPIO controls 'out' */ P6_2_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:2 */ P6_2_TCPWM0_LINE259 = 9, /* Digital Active - tcpwm[0].line[259]:1 */ P6_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:24 */ @@ -664,7 +664,7 @@ typedef enum P6_2_CPUSS_FAULT_OUT0 = 25, /* Digital Active - cpuss.fault_out[0] */ /* P6.3 */ - P6_3_GPIO = 0, /* N/A */ + P6_3_GPIO = 0, /* GPIO controls 'out' */ P6_3_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:2 */ P6_3_TCPWM0_LINE_COMPL259 = 9, /* Digital Active - tcpwm[0].line_compl[259]:1 */ P6_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:25 */ @@ -675,7 +675,7 @@ typedef enum P6_3_CPUSS_FAULT_OUT1 = 25, /* Digital Active - cpuss.fault_out[1] */ /* P6.4 */ - P6_4_GPIO = 0, /* N/A */ + P6_4_GPIO = 0, /* GPIO controls 'out' */ P6_4_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:3 */ P6_4_TCPWM0_LINE260 = 9, /* Digital Active - tcpwm[0].line[260]:1 */ P6_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:26 */ @@ -691,7 +691,7 @@ typedef enum P6_4_SRSS_DDFT_PIN_IN0 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[0]:0 */ /* P6.5 */ - P6_5_GPIO = 0, /* N/A */ + P6_5_GPIO = 0, /* GPIO controls 'out' */ P6_5_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:3 */ P6_5_TCPWM0_LINE_COMPL260 = 9, /* Digital Active - tcpwm[0].line_compl[260]:1 */ P6_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:27 */ @@ -707,7 +707,7 @@ typedef enum P6_5_SRSS_DDFT_PIN_IN1 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[1]:0 */ /* P6.6 */ - P6_6_GPIO = 0, /* N/A */ + P6_6_GPIO = 0, /* GPIO controls 'out' */ P6_6_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:3 */ P6_6_TCPWM0_LINE261 = 9, /* Digital Active - tcpwm[0].line[261]:1 */ P6_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:28 */ @@ -719,7 +719,7 @@ typedef enum P6_6_SCB6_SPI_CLK = 30, /* Digital Deep Sleep - scb[6].spi_clk:0 */ /* P6.7 */ - P6_7_GPIO = 0, /* N/A */ + P6_7_GPIO = 0, /* GPIO controls 'out' */ P6_7_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:3 */ P6_7_TCPWM0_LINE_COMPL261 = 9, /* Digital Active - tcpwm[0].line_compl[261]:1 */ P6_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:29 */ @@ -731,11 +731,11 @@ typedef enum P6_7_SCB6_SPI_SELECT0 = 30, /* Digital Deep Sleep - scb[6].spi_select0:0 */ /* P7.0 */ - P7_0_GPIO = 0, /* N/A */ - P7_0_AMUXA = 4, /* AMUXBUS A */ - P7_0_AMUXB = 5, /* AMUXBUS B */ - P7_0_AMUXA_DSI = 6, /* N/A */ - P7_0_AMUXB_DSI = 7, /* N/A */ + P7_0_GPIO = 0, /* GPIO controls 'out' */ + P7_0_AMUXA = 4, /* Analog mux bus A */ + P7_0_AMUXB = 5, /* Analog mux bus B */ + P7_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P7_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P7_0_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:2 */ P7_0_TCPWM0_LINE262 = 9, /* Digital Active - tcpwm[0].line[262]:1 */ P7_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:30 */ @@ -750,11 +750,11 @@ typedef enum P7_0_CPUSS_TRACE_CLOCK = 26, /* Digital Active - cpuss.trace_clock */ /* P7.1 */ - P7_1_GPIO = 0, /* N/A */ - P7_1_AMUXA = 4, /* AMUXBUS A */ - P7_1_AMUXB = 5, /* AMUXBUS B */ - P7_1_AMUXA_DSI = 6, /* N/A */ - P7_1_AMUXB_DSI = 7, /* N/A */ + P7_1_GPIO = 0, /* GPIO controls 'out' */ + P7_1_AMUXA = 4, /* Analog mux bus A */ + P7_1_AMUXB = 5, /* Analog mux bus B */ + P7_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P7_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P7_1_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:2 */ P7_1_TCPWM0_LINE_COMPL262 = 9, /* Digital Active - tcpwm[0].line_compl[262]:1 */ P7_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:31 */ @@ -768,11 +768,11 @@ typedef enum P7_1_PERI_TR_IO_INPUT15 = 24, /* Digital Active - peri.tr_io_input[15]:0 */ /* P7.2 */ - P7_2_GPIO = 0, /* N/A */ - P7_2_AMUXA = 4, /* AMUXBUS A */ - P7_2_AMUXB = 5, /* AMUXBUS B */ - P7_2_AMUXA_DSI = 6, /* N/A */ - P7_2_AMUXB_DSI = 7, /* N/A */ + P7_2_GPIO = 0, /* GPIO controls 'out' */ + P7_2_AMUXA = 4, /* Analog mux bus A */ + P7_2_AMUXB = 5, /* Analog mux bus B */ + P7_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P7_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P7_2_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:3 */ P7_2_TCPWM0_LINE263 = 9, /* Digital Active - tcpwm[0].line[263]:1 */ P7_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:32 */ @@ -784,11 +784,11 @@ typedef enum P7_2_TCPWM0_TR_ONE_CNT_IN260 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[260]:2 */ /* P7.3 */ - P7_3_GPIO = 0, /* N/A */ - P7_3_AMUXA = 4, /* AMUXBUS A */ - P7_3_AMUXB = 5, /* AMUXBUS B */ - P7_3_AMUXA_DSI = 6, /* N/A */ - P7_3_AMUXB_DSI = 7, /* N/A */ + P7_3_GPIO = 0, /* GPIO controls 'out' */ + P7_3_AMUXA = 4, /* Analog mux bus A */ + P7_3_AMUXB = 5, /* Analog mux bus B */ + P7_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P7_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P7_3_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:3 */ P7_3_TCPWM0_LINE_COMPL263 = 9, /* Digital Active - tcpwm[0].line_compl[263]:1 */ P7_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:33 */ @@ -800,11 +800,11 @@ typedef enum P7_3_TCPWM0_TR_ONE_CNT_IN261 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[261]:2 */ /* P8.0 */ - P8_0_GPIO = 0, /* N/A */ - P8_0_AMUXA = 4, /* AMUXBUS A */ - P8_0_AMUXB = 5, /* AMUXBUS B */ - P8_0_AMUXA_DSI = 6, /* N/A */ - P8_0_AMUXB_DSI = 7, /* N/A */ + P8_0_GPIO = 0, /* GPIO controls 'out' */ + P8_0_AMUXA = 4, /* Analog mux bus A */ + P8_0_AMUXB = 5, /* Analog mux bus B */ + P8_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P8_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P8_0_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:3 */ P8_0_TCPWM0_LINE258 = 9, /* Digital Active - tcpwm[0].line[258]:1 */ P8_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:37 */ @@ -818,11 +818,11 @@ typedef enum P8_0_PERI_TR_IO_INPUT16 = 24, /* Digital Active - peri.tr_io_input[16]:0 */ /* P8.1 */ - P8_1_GPIO = 0, /* N/A */ - P8_1_AMUXA = 4, /* AMUXBUS A */ - P8_1_AMUXB = 5, /* AMUXBUS B */ - P8_1_AMUXA_DSI = 6, /* N/A */ - P8_1_AMUXB_DSI = 7, /* N/A */ + P8_1_GPIO = 0, /* GPIO controls 'out' */ + P8_1_AMUXA = 4, /* Analog mux bus A */ + P8_1_AMUXB = 5, /* Analog mux bus B */ + P8_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P8_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P8_1_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:3 */ P8_1_TCPWM0_LINE_COMPL258 = 9, /* Digital Active - tcpwm[0].line_compl[258]:1 */ P8_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:38 */ @@ -836,11 +836,11 @@ typedef enum P8_1_PERI_TR_IO_INPUT17 = 24, /* Digital Active - peri.tr_io_input[17]:0 */ /* P9.0 */ - P9_0_GPIO = 0, /* N/A */ - P9_0_AMUXA = 4, /* AMUXBUS A */ - P9_0_AMUXB = 5, /* AMUXBUS B */ - P9_0_AMUXA_DSI = 6, /* N/A */ - P9_0_AMUXB_DSI = 7, /* N/A */ + P9_0_GPIO = 0, /* GPIO controls 'out' */ + P9_0_AMUXA = 4, /* Analog mux bus A */ + P9_0_AMUXB = 5, /* Analog mux bus B */ + P9_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P9_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P9_0_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:4 */ P9_0_TCPWM0_LINE260 = 9, /* Digital Active - tcpwm[0].line[260]:2 */ P9_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:39 */ @@ -855,11 +855,11 @@ typedef enum P9_0_CPUSS_TRACE_DATA3 = 27, /* Digital Active - cpuss.trace_data[3]:1 */ /* P9.1 */ - P9_1_GPIO = 0, /* N/A */ - P9_1_AMUXA = 4, /* AMUXBUS A */ - P9_1_AMUXB = 5, /* AMUXBUS B */ - P9_1_AMUXA_DSI = 6, /* N/A */ - P9_1_AMUXB_DSI = 7, /* N/A */ + P9_1_GPIO = 0, /* GPIO controls 'out' */ + P9_1_AMUXA = 4, /* Analog mux bus A */ + P9_1_AMUXB = 5, /* Analog mux bus B */ + P9_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P9_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P9_1_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:4 */ P9_1_TCPWM0_LINE_COMPL260 = 9, /* Digital Active - tcpwm[0].line_compl[260]:2 */ P9_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:40 */ @@ -875,11 +875,11 @@ typedef enum P9_1_SRSS_DDFT_PIN_IN0 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[0]:1 */ /* P9.2 */ - P9_2_GPIO = 0, /* N/A */ - P9_2_AMUXA = 4, /* AMUXBUS A */ - P9_2_AMUXB = 5, /* AMUXBUS B */ - P9_2_AMUXA_DSI = 6, /* N/A */ - P9_2_AMUXB_DSI = 7, /* N/A */ + P9_2_GPIO = 0, /* GPIO controls 'out' */ + P9_2_AMUXA = 4, /* Analog mux bus A */ + P9_2_AMUXB = 5, /* Analog mux bus B */ + P9_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P9_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P9_2_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:4 */ P9_2_TCPWM0_LINE261 = 9, /* Digital Active - tcpwm[0].line[261]:2 */ P9_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:41 */ @@ -893,11 +893,11 @@ typedef enum P9_2_CPUSS_TRACE_DATA1 = 27, /* Digital Active - cpuss.trace_data[1]:1 */ /* P9.3 */ - P9_3_GPIO = 0, /* N/A */ - P9_3_AMUXA = 4, /* AMUXBUS A */ - P9_3_AMUXB = 5, /* AMUXBUS B */ - P9_3_AMUXA_DSI = 6, /* N/A */ - P9_3_AMUXB_DSI = 7, /* N/A */ + P9_3_GPIO = 0, /* GPIO controls 'out' */ + P9_3_AMUXA = 4, /* Analog mux bus A */ + P9_3_AMUXB = 5, /* Analog mux bus B */ + P9_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P9_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P9_3_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:4 */ P9_3_TCPWM0_LINE_COMPL261 = 9, /* Digital Active - tcpwm[0].line_compl[261]:3 */ P9_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:42 */ @@ -912,11 +912,11 @@ typedef enum P9_3_SRSS_DDFT_PIN_IN1 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[1]:1 */ /* P9.4 */ - P9_4_GPIO = 0, /* N/A */ - P9_4_AMUXA = 4, /* AMUXBUS A */ - P9_4_AMUXB = 5, /* AMUXBUS B */ - P9_4_AMUXA_DSI = 6, /* N/A */ - P9_4_AMUXB_DSI = 7, /* N/A */ + P9_4_GPIO = 0, /* GPIO controls 'out' */ + P9_4_AMUXA = 4, /* Analog mux bus A */ + P9_4_AMUXB = 5, /* Analog mux bus B */ + P9_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P9_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P9_4_TCPWM0_LINE256 = 9, /* Digital Active - tcpwm[0].line[256]:3 */ P9_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:43 */ P9_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:43 */ @@ -924,11 +924,11 @@ typedef enum P9_4_TCPWM0_TR_ONE_CNT_IN259 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[259]:3 */ /* P9.5 */ - P9_5_GPIO = 0, /* N/A */ - P9_5_AMUXA = 4, /* AMUXBUS A */ - P9_5_AMUXB = 5, /* AMUXBUS B */ - P9_5_AMUXA_DSI = 6, /* N/A */ - P9_5_AMUXB_DSI = 7, /* N/A */ + P9_5_GPIO = 0, /* GPIO controls 'out' */ + P9_5_AMUXA = 4, /* Analog mux bus A */ + P9_5_AMUXB = 5, /* Analog mux bus B */ + P9_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P9_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P9_5_TCPWM0_LINE_COMPL256 = 9, /* Digital Active - tcpwm[0].line_compl[256]:3 */ P9_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:44 */ P9_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:44 */ @@ -936,11 +936,11 @@ typedef enum P9_5_TCPWM0_TR_ONE_CNT_IN260 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[260]:3 */ /* P10.0 */ - P10_0_GPIO = 0, /* N/A */ - P10_0_AMUXA = 4, /* AMUXBUS A */ - P10_0_AMUXB = 5, /* AMUXBUS B */ - P10_0_AMUXA_DSI = 6, /* N/A */ - P10_0_AMUXB_DSI = 7, /* N/A */ + P10_0_GPIO = 0, /* GPIO controls 'out' */ + P10_0_AMUXA = 4, /* Analog mux bus A */ + P10_0_AMUXB = 5, /* Analog mux bus B */ + P10_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P10_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P10_0_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:4 */ P10_0_TCPWM0_LINE262 = 9, /* Digital Active - tcpwm[0].line[262]:2 */ P10_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:45 */ @@ -955,11 +955,11 @@ typedef enum P10_0_CPUSS_TRACE_DATA3 = 27, /* Digital Active - cpuss.trace_data[3]:0 */ /* P10.1 */ - P10_1_GPIO = 0, /* N/A */ - P10_1_AMUXA = 4, /* AMUXBUS A */ - P10_1_AMUXB = 5, /* AMUXBUS B */ - P10_1_AMUXA_DSI = 6, /* N/A */ - P10_1_AMUXB_DSI = 7, /* N/A */ + P10_1_GPIO = 0, /* GPIO controls 'out' */ + P10_1_AMUXA = 4, /* Analog mux bus A */ + P10_1_AMUXB = 5, /* Analog mux bus B */ + P10_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P10_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P10_1_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:4 */ P10_1_TCPWM0_LINE_COMPL262 = 9, /* Digital Active - tcpwm[0].line_compl[262]:2 */ P10_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:46 */ @@ -974,11 +974,11 @@ typedef enum P10_1_CPUSS_TRACE_DATA2 = 27, /* Digital Active - cpuss.trace_data[2]:0 */ /* P10.2 */ - P10_2_GPIO = 0, /* N/A */ - P10_2_AMUXA = 4, /* AMUXBUS A */ - P10_2_AMUXB = 5, /* AMUXBUS B */ - P10_2_AMUXA_DSI = 6, /* N/A */ - P10_2_AMUXB_DSI = 7, /* N/A */ + P10_2_GPIO = 0, /* GPIO controls 'out' */ + P10_2_AMUXA = 4, /* Analog mux bus A */ + P10_2_AMUXB = 5, /* Analog mux bus B */ + P10_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P10_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P10_2_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:4 */ P10_2_TCPWM0_LINE263 = 9, /* Digital Active - tcpwm[0].line[263]:2 */ P10_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:47 */ @@ -991,11 +991,11 @@ typedef enum P10_2_CPUSS_TRACE_DATA1 = 27, /* Digital Active - cpuss.trace_data[1]:0 */ /* P10.3 */ - P10_3_GPIO = 0, /* N/A */ - P10_3_AMUXA = 4, /* AMUXBUS A */ - P10_3_AMUXB = 5, /* AMUXBUS B */ - P10_3_AMUXA_DSI = 6, /* N/A */ - P10_3_AMUXB_DSI = 7, /* N/A */ + P10_3_GPIO = 0, /* GPIO controls 'out' */ + P10_3_AMUXA = 4, /* Analog mux bus A */ + P10_3_AMUXB = 5, /* Analog mux bus B */ + P10_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P10_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P10_3_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:4 */ P10_3_TCPWM0_LINE_COMPL263 = 9, /* Digital Active - tcpwm[0].line_compl[263]:2 */ P10_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:48 */ @@ -1008,11 +1008,11 @@ typedef enum P10_3_CPUSS_TRACE_DATA0 = 27, /* Digital Active - cpuss.trace_data[0]:0 */ /* P10.4 */ - P10_4_GPIO = 0, /* N/A */ - P10_4_AMUXA = 4, /* AMUXBUS A */ - P10_4_AMUXB = 5, /* AMUXBUS B */ - P10_4_AMUXA_DSI = 6, /* N/A */ - P10_4_AMUXB_DSI = 7, /* N/A */ + P10_4_GPIO = 0, /* GPIO controls 'out' */ + P10_4_AMUXA = 4, /* Analog mux bus A */ + P10_4_AMUXB = 5, /* Analog mux bus B */ + P10_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P10_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P10_4_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:5 */ P10_4_TCPWM0_LINE256 = 9, /* Digital Active - tcpwm[0].line[256]:2 */ P10_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:49 */ @@ -1023,11 +1023,11 @@ typedef enum P10_4_TCPWM0_TR_ONE_CNT_IN1 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[1]:4 */ /* P10.5 */ - P10_5_GPIO = 0, /* N/A */ - P10_5_AMUXA = 4, /* AMUXBUS A */ - P10_5_AMUXB = 5, /* AMUXBUS B */ - P10_5_AMUXA_DSI = 6, /* N/A */ - P10_5_AMUXB_DSI = 7, /* N/A */ + P10_5_GPIO = 0, /* GPIO controls 'out' */ + P10_5_AMUXA = 4, /* Analog mux bus A */ + P10_5_AMUXB = 5, /* Analog mux bus B */ + P10_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P10_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P10_5_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:5 */ P10_5_TCPWM0_LINE_COMPL256 = 9, /* Digital Active - tcpwm[0].line_compl[256]:2 */ P10_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:50 */ @@ -1038,11 +1038,11 @@ typedef enum P10_5_TCPWM0_TR_ONE_CNT_IN2 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[2]:4 */ /* P10.6 */ - P10_6_GPIO = 0, /* N/A */ - P10_6_AMUXA = 4, /* AMUXBUS A */ - P10_6_AMUXB = 5, /* AMUXBUS B */ - P10_6_AMUXA_DSI = 6, /* N/A */ - P10_6_AMUXB_DSI = 7, /* N/A */ + P10_6_GPIO = 0, /* GPIO controls 'out' */ + P10_6_AMUXA = 4, /* Analog mux bus A */ + P10_6_AMUXB = 5, /* Analog mux bus B */ + P10_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P10_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P10_6_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:5 */ P10_6_TCPWM0_LINE257 = 9, /* Digital Active - tcpwm[0].line[257]:2 */ P10_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:51 */ @@ -1054,11 +1054,11 @@ typedef enum P10_6_PERI_TR_IO_INPUT22 = 24, /* Digital Active - peri.tr_io_input[22]:0 */ /* P10.7 */ - P10_7_GPIO = 0, /* N/A */ - P10_7_AMUXA = 4, /* AMUXBUS A */ - P10_7_AMUXB = 5, /* AMUXBUS B */ - P10_7_AMUXA_DSI = 6, /* N/A */ - P10_7_AMUXB_DSI = 7, /* N/A */ + P10_7_GPIO = 0, /* GPIO controls 'out' */ + P10_7_AMUXA = 4, /* Analog mux bus A */ + P10_7_AMUXB = 5, /* Analog mux bus B */ + P10_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P10_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P10_7_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:5 */ P10_7_TCPWM0_LINE_COMPL257 = 9, /* Digital Active - tcpwm[0].line_compl[257]:2 */ P10_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:52 */ @@ -1070,7 +1070,7 @@ typedef enum P10_7_PERI_TR_IO_INPUT23 = 24, /* Digital Active - peri.tr_io_input[23]:0 */ /* P11.2 */ - P11_2_GPIO = 0, /* N/A */ + P11_2_GPIO = 0, /* GPIO controls 'out' */ P11_2_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:5 */ P11_2_TCPWM0_LINE259 = 9, /* Digital Active - tcpwm[0].line[259]:2 */ P11_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:54 */ @@ -1083,7 +1083,7 @@ typedef enum P11_2_TCPWM0_TR_ONE_CNT_IN258 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[258]:4 */ /* P11.3 */ - P11_3_GPIO = 0, /* N/A */ + P11_3_GPIO = 0, /* GPIO controls 'out' */ P11_3_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:5 */ P11_3_TCPWM0_LINE_COMPL259 = 9, /* Digital Active - tcpwm[0].line_compl[259]:2 */ P11_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:55 */ @@ -1097,7 +1097,7 @@ typedef enum P11_3_PERI_TR_IO_OUTPUT0 = 25, /* Digital Active - peri.tr_io_output[0]:0 */ /* P11.4 */ - P11_4_GPIO = 0, /* N/A */ + P11_4_GPIO = 0, /* GPIO controls 'out' */ P11_4_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:6 */ P11_4_TCPWM0_LINE260 = 9, /* Digital Active - tcpwm[0].line[260]:3 */ P11_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:56 */ @@ -1110,7 +1110,7 @@ typedef enum P11_4_PERI_TR_IO_OUTPUT1 = 25, /* Digital Active - peri.tr_io_output[1]:0 */ /* P11.5 */ - P11_5_GPIO = 0, /* N/A */ + P11_5_GPIO = 0, /* GPIO controls 'out' */ P11_5_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:6 */ P11_5_TCPWM0_LINE_COMPL260 = 9, /* Digital Active - tcpwm[0].line_compl[260]:3 */ P11_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:57 */ @@ -1122,7 +1122,7 @@ typedef enum P11_5_TCPWM0_TR_ONE_CNT_IN261 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[261]:4 */ /* P11.6 */ - P11_6_GPIO = 0, /* N/A */ + P11_6_GPIO = 0, /* GPIO controls 'out' */ P11_6_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:6 */ P11_6_TCPWM0_LINE261 = 9, /* Digital Active - tcpwm[0].line[261]:3 */ P11_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:58 */ @@ -1134,7 +1134,7 @@ typedef enum P11_6_TCPWM0_TR_ONE_CNT_IN262 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[262]:4 */ /* P11.7 */ - P11_7_GPIO = 0, /* N/A */ + P11_7_GPIO = 0, /* GPIO controls 'out' */ P11_7_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:6 */ P11_7_TCPWM0_LINE_COMPL261 = 9, /* Digital Active - tcpwm[0].line_compl[261]:2 */ P11_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:59 */ @@ -1145,7 +1145,7 @@ typedef enum P11_7_TCPWM0_TR_ONE_CNT_IN263 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[263]:4 */ /* P12.6 */ - P12_6_GPIO = 0, /* N/A */ + P12_6_GPIO = 0, /* GPIO controls 'out' */ P12_6_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:6 */ P12_6_TCPWM0_LINE263 = 9, /* Digital Active - tcpwm[0].line[263]:3 */ P12_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:60 */ @@ -1155,7 +1155,7 @@ typedef enum P12_6_TCPWM0_TR_ONE_CNT_IN0 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[0]:5 */ /* P12.7 */ - P12_7_GPIO = 0, /* N/A */ + P12_7_GPIO = 0, /* GPIO controls 'out' */ P12_7_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:6 */ P12_7_TCPWM0_LINE_COMPL263 = 9, /* Digital Active - tcpwm[0].line_compl[263]:3 */ P12_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:61 */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_04_68_qfn.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_04_68_qfn.h index 75b8468b96..9509862d1c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_04_68_qfn.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_04_68_qfn.h @@ -5,7 +5,7 @@ * PSoC6_04 device GPIO header for 68-QFN package * * \note -* Generator version: 1.6.0.111 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -363,41 +363,41 @@ typedef enum typedef enum { /* Generic HSIOM connections */ - HSIOM_SEL_GPIO = 0, /* N/A */ - HSIOM_SEL_GPIO_DSI = 1, /* N/A */ - HSIOM_SEL_DSI_DSI = 2, /* N/A */ - HSIOM_SEL_DSI_GPIO = 3, /* N/A */ - HSIOM_SEL_AMUXA = 4, /* AMUXBUS A */ - HSIOM_SEL_AMUXB = 5, /* AMUXBUS B */ - HSIOM_SEL_AMUXA_DSI = 6, /* N/A */ - HSIOM_SEL_AMUXB_DSI = 7, /* N/A */ - HSIOM_SEL_ACT_0 = 8, /* Active peripherals 0 */ - HSIOM_SEL_ACT_1 = 9, /* Active peripherals 1 */ - HSIOM_SEL_ACT_2 = 10, /* Active peripherals 2 */ - HSIOM_SEL_ACT_3 = 11, /* Active peripherals 4 */ - HSIOM_SEL_DS_0 = 12, /* Deep Sleep peripherals 0 */ - HSIOM_SEL_DS_1 = 13, /* Deep Sleep peripherals 1 */ - HSIOM_SEL_DS_2 = 14, /* Deep Sleep peripherals 2 */ - HSIOM_SEL_DS_3 = 15, /* Deep Sleep peripherals 3 */ - HSIOM_SEL_ACT_4 = 16, /* Active peripherals 4 */ - HSIOM_SEL_ACT_5 = 17, /* Active peripherals 5 */ - HSIOM_SEL_ACT_6 = 18, /* Active peripherals 6 */ - HSIOM_SEL_ACT_7 = 19, /* Active peripherals 7 */ - HSIOM_SEL_ACT_8 = 20, /* Active peripherals 8 */ - HSIOM_SEL_ACT_9 = 21, /* Active peripherals 9 */ - HSIOM_SEL_ACT_10 = 22, /* Active peripherals 10 */ - HSIOM_SEL_ACT_11 = 23, /* Active peripherals 11 */ - HSIOM_SEL_ACT_12 = 24, /* Active peripherals 12 */ - HSIOM_SEL_ACT_13 = 25, /* Active peripherals 13 */ - HSIOM_SEL_ACT_14 = 26, /* Active peripherals 14 */ - HSIOM_SEL_ACT_15 = 27, /* Active peripherals 15 */ - HSIOM_SEL_DS_4 = 28, /* N/A */ - HSIOM_SEL_DS_5 = 29, /* N/A */ - HSIOM_SEL_DS_6 = 30, /* N/A */ - HSIOM_SEL_DS_7 = 31, /* N/A */ + HSIOM_SEL_GPIO = 0, /* GPIO controls 'out' */ + HSIOM_SEL_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + HSIOM_SEL_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + HSIOM_SEL_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + HSIOM_SEL_AMUXA = 4, /* Analog mux bus A */ + HSIOM_SEL_AMUXB = 5, /* Analog mux bus B */ + HSIOM_SEL_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + HSIOM_SEL_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + HSIOM_SEL_ACT_0 = 8, /* Active functionality 0 */ + HSIOM_SEL_ACT_1 = 9, /* Active functionality 1 */ + HSIOM_SEL_ACT_2 = 10, /* Active functionality 2 */ + HSIOM_SEL_ACT_3 = 11, /* Active functionality 3 */ + HSIOM_SEL_DS_0 = 12, /* DeepSleep functionality 0 */ + HSIOM_SEL_DS_1 = 13, /* DeepSleep functionality 1 */ + HSIOM_SEL_DS_2 = 14, /* DeepSleep functionality 2 */ + HSIOM_SEL_DS_3 = 15, /* DeepSleep functionality 3 */ + HSIOM_SEL_ACT_4 = 16, /* Active functionality 4 */ + HSIOM_SEL_ACT_5 = 17, /* Active functionality 5 */ + HSIOM_SEL_ACT_6 = 18, /* Active functionality 6 */ + HSIOM_SEL_ACT_7 = 19, /* Active functionality 7 */ + HSIOM_SEL_ACT_8 = 20, /* Active functionality 8 */ + HSIOM_SEL_ACT_9 = 21, /* Active functionality 9 */ + HSIOM_SEL_ACT_10 = 22, /* Active functionality 10 */ + HSIOM_SEL_ACT_11 = 23, /* Active functionality 11 */ + HSIOM_SEL_ACT_12 = 24, /* Active functionality 12 */ + HSIOM_SEL_ACT_13 = 25, /* Active functionality 13 */ + HSIOM_SEL_ACT_14 = 26, /* Active functionality 14 */ + HSIOM_SEL_ACT_15 = 27, /* Active functionality 15 */ + HSIOM_SEL_DS_4 = 28, /* DeepSleep functionality 4 */ + HSIOM_SEL_DS_5 = 29, /* DeepSleep functionality 5 */ + HSIOM_SEL_DS_6 = 30, /* DeepSleep functionality 6 */ + HSIOM_SEL_DS_7 = 31, /* DeepSleep functionality 7 */ /* P0.0 */ - P0_0_GPIO = 0, /* N/A */ + P0_0_GPIO = 0, /* GPIO controls 'out' */ P0_0_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:0 */ P0_0_TCPWM0_LINE256 = 9, /* Digital Active - tcpwm[0].line[256]:0 */ P0_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:0 */ @@ -410,7 +410,7 @@ typedef enum P0_0_PERI_TR_IO_INPUT0 = 24, /* Digital Active - peri.tr_io_input[0]:0 */ /* P0.1 */ - P0_1_GPIO = 0, /* N/A */ + P0_1_GPIO = 0, /* GPIO controls 'out' */ P0_1_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:0 */ P0_1_TCPWM0_LINE_COMPL256 = 9, /* Digital Active - tcpwm[0].line_compl[256]:0 */ P0_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:1 */ @@ -423,7 +423,7 @@ typedef enum P0_1_CPUSS_SWJ_TRSTN = 29, /* Digital Deep Sleep - cpuss.swj_trstn */ /* P0.2 */ - P0_2_GPIO = 0, /* N/A */ + P0_2_GPIO = 0, /* GPIO controls 'out' */ P0_2_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:0 */ P0_2_TCPWM0_LINE257 = 9, /* Digital Active - tcpwm[0].line[257]:0 */ P0_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:2 */ @@ -436,7 +436,7 @@ typedef enum P0_2_TCPWM0_TR_ONE_CNT_IN2 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[2]:0 */ /* P0.3 */ - P0_3_GPIO = 0, /* N/A */ + P0_3_GPIO = 0, /* GPIO controls 'out' */ P0_3_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:0 */ P0_3_TCPWM0_LINE_COMPL257 = 9, /* Digital Active - tcpwm[0].line_compl[257]:0 */ P0_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:3 */ @@ -449,7 +449,7 @@ typedef enum P0_3_TCPWM0_TR_ONE_CNT_IN3 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[3]:0 */ /* P0.4 */ - P0_4_GPIO = 0, /* N/A */ + P0_4_GPIO = 0, /* GPIO controls 'out' */ P0_4_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:0 */ P0_4_TCPWM0_LINE258 = 9, /* Digital Active - tcpwm[0].line[258]:0 */ P0_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:4 */ @@ -463,7 +463,7 @@ typedef enum P0_4_PERI_TR_IO_OUTPUT0 = 25, /* Digital Active - peri.tr_io_output[0]:2 */ /* P0.5 */ - P0_5_GPIO = 0, /* N/A */ + P0_5_GPIO = 0, /* GPIO controls 'out' */ P0_5_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:0 */ P0_5_TCPWM0_LINE_COMPL258 = 9, /* Digital Active - tcpwm[0].line_compl[258]:0 */ P0_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:5 */ @@ -477,14 +477,8 @@ typedef enum P0_5_PERI_TR_IO_INPUT3 = 24, /* Digital Active - peri.tr_io_input[3]:0 */ P0_5_PERI_TR_IO_OUTPUT1 = 25, /* Digital Active - peri.tr_io_output[1]:2 */ - /* USBDM */ - USBDM_GPIO = 0, /* N/A */ - - /* USBDP */ - USBDP_GPIO = 0, /* N/A */ - /* P2.0 */ - P2_0_GPIO = 0, /* N/A */ + P2_0_GPIO = 0, /* GPIO controls 'out' */ P2_0_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:0 */ P2_0_TCPWM0_LINE259 = 9, /* Digital Active - tcpwm[0].line[259]:0 */ P2_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:9 */ @@ -498,7 +492,7 @@ typedef enum P2_0_PERI_TR_IO_INPUT4 = 24, /* Digital Active - peri.tr_io_input[4]:0 */ /* P2.1 */ - P2_1_GPIO = 0, /* N/A */ + P2_1_GPIO = 0, /* GPIO controls 'out' */ P2_1_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:0 */ P2_1_TCPWM0_LINE_COMPL259 = 9, /* Digital Active - tcpwm[0].line_compl[259]:0 */ P2_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:10 */ @@ -512,7 +506,7 @@ typedef enum P2_1_PERI_TR_IO_INPUT5 = 24, /* Digital Active - peri.tr_io_input[5]:0 */ /* P2.2 */ - P2_2_GPIO = 0, /* N/A */ + P2_2_GPIO = 0, /* GPIO controls 'out' */ P2_2_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:1 */ P2_2_TCPWM0_LINE260 = 9, /* Digital Active - tcpwm[0].line[260]:0 */ P2_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:11 */ @@ -524,7 +518,7 @@ typedef enum P2_2_TCPWM0_TR_ONE_CNT_IN263 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[263]:0 */ /* P2.3 */ - P2_3_GPIO = 0, /* N/A */ + P2_3_GPIO = 0, /* GPIO controls 'out' */ P2_3_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:1 */ P2_3_TCPWM0_LINE_COMPL260 = 9, /* Digital Active - tcpwm[0].line_compl[260]:0 */ P2_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:12 */ @@ -536,7 +530,7 @@ typedef enum P2_3_TCPWM0_TR_ONE_CNT_IN0 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[0]:1 */ /* P2.4 */ - P2_4_GPIO = 0, /* N/A */ + P2_4_GPIO = 0, /* GPIO controls 'out' */ P2_4_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:1 */ P2_4_TCPWM0_LINE261 = 9, /* Digital Active - tcpwm[0].line[261]:0 */ P2_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:13 */ @@ -547,7 +541,7 @@ typedef enum P2_4_TCPWM0_TR_ONE_CNT_IN1 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[1]:1 */ /* P2.5 */ - P2_5_GPIO = 0, /* N/A */ + P2_5_GPIO = 0, /* GPIO controls 'out' */ P2_5_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:1 */ P2_5_TCPWM0_LINE_COMPL261 = 9, /* Digital Active - tcpwm[0].line_compl[261]:0 */ P2_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:14 */ @@ -558,7 +552,7 @@ typedef enum P2_5_TCPWM0_TR_ONE_CNT_IN2 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[2]:1 */ /* P2.6 */ - P2_6_GPIO = 0, /* N/A */ + P2_6_GPIO = 0, /* GPIO controls 'out' */ P2_6_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:1 */ P2_6_TCPWM0_LINE262 = 9, /* Digital Active - tcpwm[0].line[262]:0 */ P2_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:15 */ @@ -571,7 +565,7 @@ typedef enum P2_6_PERI_TR_IO_INPUT8 = 24, /* Digital Active - peri.tr_io_input[8]:0 */ /* P2.7 */ - P2_7_GPIO = 0, /* N/A */ + P2_7_GPIO = 0, /* GPIO controls 'out' */ P2_7_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:1 */ P2_7_TCPWM0_LINE_COMPL262 = 9, /* Digital Active - tcpwm[0].line_compl[262]:0 */ P2_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:16 */ @@ -583,7 +577,7 @@ typedef enum P2_7_PERI_TR_IO_INPUT9 = 24, /* Digital Active - peri.tr_io_input[9]:0 */ /* P3.0 */ - P3_0_GPIO = 0, /* N/A */ + P3_0_GPIO = 0, /* GPIO controls 'out' */ P3_0_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:1 */ P3_0_TCPWM0_LINE263 = 9, /* Digital Active - tcpwm[0].line[263]:0 */ P3_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:17 */ @@ -596,7 +590,7 @@ typedef enum P3_0_PERI_TR_IO_INPUT6 = 24, /* Digital Active - peri.tr_io_input[6]:0 */ /* P3.1 */ - P3_1_GPIO = 0, /* N/A */ + P3_1_GPIO = 0, /* GPIO controls 'out' */ P3_1_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:1 */ P3_1_TCPWM0_LINE_COMPL263 = 9, /* Digital Active - tcpwm[0].line_compl[263]:0 */ P3_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:18 */ @@ -609,7 +603,7 @@ typedef enum P3_1_PERI_TR_IO_INPUT7 = 24, /* Digital Active - peri.tr_io_input[7]:0 */ /* P5.0 */ - P5_0_GPIO = 0, /* N/A */ + P5_0_GPIO = 0, /* GPIO controls 'out' */ P5_0_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:2 */ P5_0_TCPWM0_LINE256 = 9, /* Digital Active - tcpwm[0].line[256]:1 */ P5_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:19 */ @@ -624,7 +618,7 @@ typedef enum P5_0_PERI_TR_IO_INPUT10 = 24, /* Digital Active - peri.tr_io_input[10]:0 */ /* P5.1 */ - P5_1_GPIO = 0, /* N/A */ + P5_1_GPIO = 0, /* GPIO controls 'out' */ P5_1_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:2 */ P5_1_TCPWM0_LINE_COMPL256 = 9, /* Digital Active - tcpwm[0].line_compl[256]:1 */ P5_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:20 */ @@ -639,7 +633,7 @@ typedef enum P5_1_PERI_TR_IO_INPUT11 = 24, /* Digital Active - peri.tr_io_input[11]:0 */ /* P5.6 */ - P5_6_GPIO = 0, /* N/A */ + P5_6_GPIO = 0, /* GPIO controls 'out' */ P5_6_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:2 */ P5_6_TCPWM0_LINE257 = 9, /* Digital Active - tcpwm[0].line[257]:1 */ P5_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:22 */ @@ -649,7 +643,7 @@ typedef enum P5_6_TCPWM0_TR_ONE_CNT_IN262 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[262]:1 */ /* P5.7 */ - P5_7_GPIO = 0, /* N/A */ + P5_7_GPIO = 0, /* GPIO controls 'out' */ P5_7_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:2 */ P5_7_TCPWM0_LINE_COMPL257 = 9, /* Digital Active - tcpwm[0].line_compl[257]:1 */ P5_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:23 */ @@ -659,7 +653,7 @@ typedef enum P5_7_TCPWM0_TR_ONE_CNT_IN263 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[263]:1 */ /* P6.2 */ - P6_2_GPIO = 0, /* N/A */ + P6_2_GPIO = 0, /* GPIO controls 'out' */ P6_2_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:2 */ P6_2_TCPWM0_LINE259 = 9, /* Digital Active - tcpwm[0].line[259]:1 */ P6_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:24 */ @@ -670,7 +664,7 @@ typedef enum P6_2_CPUSS_FAULT_OUT0 = 25, /* Digital Active - cpuss.fault_out[0] */ /* P6.3 */ - P6_3_GPIO = 0, /* N/A */ + P6_3_GPIO = 0, /* GPIO controls 'out' */ P6_3_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:2 */ P6_3_TCPWM0_LINE_COMPL259 = 9, /* Digital Active - tcpwm[0].line_compl[259]:1 */ P6_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:25 */ @@ -681,7 +675,7 @@ typedef enum P6_3_CPUSS_FAULT_OUT1 = 25, /* Digital Active - cpuss.fault_out[1] */ /* P6.4 */ - P6_4_GPIO = 0, /* N/A */ + P6_4_GPIO = 0, /* GPIO controls 'out' */ P6_4_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:3 */ P6_4_TCPWM0_LINE260 = 9, /* Digital Active - tcpwm[0].line[260]:1 */ P6_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:26 */ @@ -697,7 +691,7 @@ typedef enum P6_4_SRSS_DDFT_PIN_IN0 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[0]:0 */ /* P6.5 */ - P6_5_GPIO = 0, /* N/A */ + P6_5_GPIO = 0, /* GPIO controls 'out' */ P6_5_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:3 */ P6_5_TCPWM0_LINE_COMPL260 = 9, /* Digital Active - tcpwm[0].line_compl[260]:1 */ P6_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:27 */ @@ -713,7 +707,7 @@ typedef enum P6_5_SRSS_DDFT_PIN_IN1 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[1]:0 */ /* P6.6 */ - P6_6_GPIO = 0, /* N/A */ + P6_6_GPIO = 0, /* GPIO controls 'out' */ P6_6_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:3 */ P6_6_TCPWM0_LINE261 = 9, /* Digital Active - tcpwm[0].line[261]:1 */ P6_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:28 */ @@ -725,7 +719,7 @@ typedef enum P6_6_SCB6_SPI_CLK = 30, /* Digital Deep Sleep - scb[6].spi_clk:0 */ /* P6.7 */ - P6_7_GPIO = 0, /* N/A */ + P6_7_GPIO = 0, /* GPIO controls 'out' */ P6_7_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:3 */ P6_7_TCPWM0_LINE_COMPL261 = 9, /* Digital Active - tcpwm[0].line_compl[261]:1 */ P6_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:29 */ @@ -737,11 +731,11 @@ typedef enum P6_7_SCB6_SPI_SELECT0 = 30, /* Digital Deep Sleep - scb[6].spi_select0:0 */ /* P7.0 */ - P7_0_GPIO = 0, /* N/A */ - P7_0_AMUXA = 4, /* AMUXBUS A */ - P7_0_AMUXB = 5, /* AMUXBUS B */ - P7_0_AMUXA_DSI = 6, /* N/A */ - P7_0_AMUXB_DSI = 7, /* N/A */ + P7_0_GPIO = 0, /* GPIO controls 'out' */ + P7_0_AMUXA = 4, /* Analog mux bus A */ + P7_0_AMUXB = 5, /* Analog mux bus B */ + P7_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P7_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P7_0_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:2 */ P7_0_TCPWM0_LINE262 = 9, /* Digital Active - tcpwm[0].line[262]:1 */ P7_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:30 */ @@ -756,11 +750,11 @@ typedef enum P7_0_CPUSS_TRACE_CLOCK = 26, /* Digital Active - cpuss.trace_clock */ /* P7.1 */ - P7_1_GPIO = 0, /* N/A */ - P7_1_AMUXA = 4, /* AMUXBUS A */ - P7_1_AMUXB = 5, /* AMUXBUS B */ - P7_1_AMUXA_DSI = 6, /* N/A */ - P7_1_AMUXB_DSI = 7, /* N/A */ + P7_1_GPIO = 0, /* GPIO controls 'out' */ + P7_1_AMUXA = 4, /* Analog mux bus A */ + P7_1_AMUXB = 5, /* Analog mux bus B */ + P7_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P7_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P7_1_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:2 */ P7_1_TCPWM0_LINE_COMPL262 = 9, /* Digital Active - tcpwm[0].line_compl[262]:1 */ P7_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:31 */ @@ -774,11 +768,11 @@ typedef enum P7_1_PERI_TR_IO_INPUT15 = 24, /* Digital Active - peri.tr_io_input[15]:0 */ /* P7.2 */ - P7_2_GPIO = 0, /* N/A */ - P7_2_AMUXA = 4, /* AMUXBUS A */ - P7_2_AMUXB = 5, /* AMUXBUS B */ - P7_2_AMUXA_DSI = 6, /* N/A */ - P7_2_AMUXB_DSI = 7, /* N/A */ + P7_2_GPIO = 0, /* GPIO controls 'out' */ + P7_2_AMUXA = 4, /* Analog mux bus A */ + P7_2_AMUXB = 5, /* Analog mux bus B */ + P7_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P7_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P7_2_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:3 */ P7_2_TCPWM0_LINE263 = 9, /* Digital Active - tcpwm[0].line[263]:1 */ P7_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:32 */ @@ -790,11 +784,11 @@ typedef enum P7_2_TCPWM0_TR_ONE_CNT_IN260 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[260]:2 */ /* P7.3 */ - P7_3_GPIO = 0, /* N/A */ - P7_3_AMUXA = 4, /* AMUXBUS A */ - P7_3_AMUXB = 5, /* AMUXBUS B */ - P7_3_AMUXA_DSI = 6, /* N/A */ - P7_3_AMUXB_DSI = 7, /* N/A */ + P7_3_GPIO = 0, /* GPIO controls 'out' */ + P7_3_AMUXA = 4, /* Analog mux bus A */ + P7_3_AMUXB = 5, /* Analog mux bus B */ + P7_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P7_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P7_3_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:3 */ P7_3_TCPWM0_LINE_COMPL263 = 9, /* Digital Active - tcpwm[0].line_compl[263]:1 */ P7_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:33 */ @@ -806,11 +800,11 @@ typedef enum P7_3_TCPWM0_TR_ONE_CNT_IN261 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[261]:2 */ /* P7.7 */ - P7_7_GPIO = 0, /* N/A */ - P7_7_AMUXA = 4, /* AMUXBUS A */ - P7_7_AMUXB = 5, /* AMUXBUS B */ - P7_7_AMUXA_DSI = 6, /* N/A */ - P7_7_AMUXB_DSI = 7, /* N/A */ + P7_7_GPIO = 0, /* GPIO controls 'out' */ + P7_7_AMUXA = 4, /* Analog mux bus A */ + P7_7_AMUXB = 5, /* Analog mux bus B */ + P7_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P7_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P7_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:36 */ P7_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:36 */ P7_7_LCD_COM35 = 12, /* Digital Deep Sleep - lcd.com[35]:0 */ @@ -819,11 +813,11 @@ typedef enum P7_7_TCPWM0_TR_ONE_CNT_IN0 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[0]:3 */ /* P8.0 */ - P8_0_GPIO = 0, /* N/A */ - P8_0_AMUXA = 4, /* AMUXBUS A */ - P8_0_AMUXB = 5, /* AMUXBUS B */ - P8_0_AMUXA_DSI = 6, /* N/A */ - P8_0_AMUXB_DSI = 7, /* N/A */ + P8_0_GPIO = 0, /* GPIO controls 'out' */ + P8_0_AMUXA = 4, /* Analog mux bus A */ + P8_0_AMUXB = 5, /* Analog mux bus B */ + P8_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P8_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P8_0_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:3 */ P8_0_TCPWM0_LINE258 = 9, /* Digital Active - tcpwm[0].line[258]:1 */ P8_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:37 */ @@ -837,11 +831,11 @@ typedef enum P8_0_PERI_TR_IO_INPUT16 = 24, /* Digital Active - peri.tr_io_input[16]:0 */ /* P8.1 */ - P8_1_GPIO = 0, /* N/A */ - P8_1_AMUXA = 4, /* AMUXBUS A */ - P8_1_AMUXB = 5, /* AMUXBUS B */ - P8_1_AMUXA_DSI = 6, /* N/A */ - P8_1_AMUXB_DSI = 7, /* N/A */ + P8_1_GPIO = 0, /* GPIO controls 'out' */ + P8_1_AMUXA = 4, /* Analog mux bus A */ + P8_1_AMUXB = 5, /* Analog mux bus B */ + P8_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P8_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P8_1_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:3 */ P8_1_TCPWM0_LINE_COMPL258 = 9, /* Digital Active - tcpwm[0].line_compl[258]:1 */ P8_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:38 */ @@ -855,11 +849,11 @@ typedef enum P8_1_PERI_TR_IO_INPUT17 = 24, /* Digital Active - peri.tr_io_input[17]:0 */ /* P9.0 */ - P9_0_GPIO = 0, /* N/A */ - P9_0_AMUXA = 4, /* AMUXBUS A */ - P9_0_AMUXB = 5, /* AMUXBUS B */ - P9_0_AMUXA_DSI = 6, /* N/A */ - P9_0_AMUXB_DSI = 7, /* N/A */ + P9_0_GPIO = 0, /* GPIO controls 'out' */ + P9_0_AMUXA = 4, /* Analog mux bus A */ + P9_0_AMUXB = 5, /* Analog mux bus B */ + P9_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P9_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P9_0_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:4 */ P9_0_TCPWM0_LINE260 = 9, /* Digital Active - tcpwm[0].line[260]:2 */ P9_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:39 */ @@ -874,11 +868,11 @@ typedef enum P9_0_CPUSS_TRACE_DATA3 = 27, /* Digital Active - cpuss.trace_data[3]:1 */ /* P9.1 */ - P9_1_GPIO = 0, /* N/A */ - P9_1_AMUXA = 4, /* AMUXBUS A */ - P9_1_AMUXB = 5, /* AMUXBUS B */ - P9_1_AMUXA_DSI = 6, /* N/A */ - P9_1_AMUXB_DSI = 7, /* N/A */ + P9_1_GPIO = 0, /* GPIO controls 'out' */ + P9_1_AMUXA = 4, /* Analog mux bus A */ + P9_1_AMUXB = 5, /* Analog mux bus B */ + P9_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P9_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P9_1_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:4 */ P9_1_TCPWM0_LINE_COMPL260 = 9, /* Digital Active - tcpwm[0].line_compl[260]:2 */ P9_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:40 */ @@ -894,11 +888,11 @@ typedef enum P9_1_SRSS_DDFT_PIN_IN0 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[0]:1 */ /* P9.2 */ - P9_2_GPIO = 0, /* N/A */ - P9_2_AMUXA = 4, /* AMUXBUS A */ - P9_2_AMUXB = 5, /* AMUXBUS B */ - P9_2_AMUXA_DSI = 6, /* N/A */ - P9_2_AMUXB_DSI = 7, /* N/A */ + P9_2_GPIO = 0, /* GPIO controls 'out' */ + P9_2_AMUXA = 4, /* Analog mux bus A */ + P9_2_AMUXB = 5, /* Analog mux bus B */ + P9_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P9_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P9_2_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:4 */ P9_2_TCPWM0_LINE261 = 9, /* Digital Active - tcpwm[0].line[261]:2 */ P9_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:41 */ @@ -912,11 +906,11 @@ typedef enum P9_2_CPUSS_TRACE_DATA1 = 27, /* Digital Active - cpuss.trace_data[1]:1 */ /* P9.3 */ - P9_3_GPIO = 0, /* N/A */ - P9_3_AMUXA = 4, /* AMUXBUS A */ - P9_3_AMUXB = 5, /* AMUXBUS B */ - P9_3_AMUXA_DSI = 6, /* N/A */ - P9_3_AMUXB_DSI = 7, /* N/A */ + P9_3_GPIO = 0, /* GPIO controls 'out' */ + P9_3_AMUXA = 4, /* Analog mux bus A */ + P9_3_AMUXB = 5, /* Analog mux bus B */ + P9_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P9_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P9_3_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:4 */ P9_3_TCPWM0_LINE_COMPL261 = 9, /* Digital Active - tcpwm[0].line_compl[261]:3 */ P9_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:42 */ @@ -931,11 +925,11 @@ typedef enum P9_3_SRSS_DDFT_PIN_IN1 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[1]:1 */ /* P10.0 */ - P10_0_GPIO = 0, /* N/A */ - P10_0_AMUXA = 4, /* AMUXBUS A */ - P10_0_AMUXB = 5, /* AMUXBUS B */ - P10_0_AMUXA_DSI = 6, /* N/A */ - P10_0_AMUXB_DSI = 7, /* N/A */ + P10_0_GPIO = 0, /* GPIO controls 'out' */ + P10_0_AMUXA = 4, /* Analog mux bus A */ + P10_0_AMUXB = 5, /* Analog mux bus B */ + P10_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P10_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P10_0_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:4 */ P10_0_TCPWM0_LINE262 = 9, /* Digital Active - tcpwm[0].line[262]:2 */ P10_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:45 */ @@ -950,11 +944,11 @@ typedef enum P10_0_CPUSS_TRACE_DATA3 = 27, /* Digital Active - cpuss.trace_data[3]:0 */ /* P10.1 */ - P10_1_GPIO = 0, /* N/A */ - P10_1_AMUXA = 4, /* AMUXBUS A */ - P10_1_AMUXB = 5, /* AMUXBUS B */ - P10_1_AMUXA_DSI = 6, /* N/A */ - P10_1_AMUXB_DSI = 7, /* N/A */ + P10_1_GPIO = 0, /* GPIO controls 'out' */ + P10_1_AMUXA = 4, /* Analog mux bus A */ + P10_1_AMUXB = 5, /* Analog mux bus B */ + P10_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P10_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P10_1_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:4 */ P10_1_TCPWM0_LINE_COMPL262 = 9, /* Digital Active - tcpwm[0].line_compl[262]:2 */ P10_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:46 */ @@ -969,11 +963,11 @@ typedef enum P10_1_CPUSS_TRACE_DATA2 = 27, /* Digital Active - cpuss.trace_data[2]:0 */ /* P10.2 */ - P10_2_GPIO = 0, /* N/A */ - P10_2_AMUXA = 4, /* AMUXBUS A */ - P10_2_AMUXB = 5, /* AMUXBUS B */ - P10_2_AMUXA_DSI = 6, /* N/A */ - P10_2_AMUXB_DSI = 7, /* N/A */ + P10_2_GPIO = 0, /* GPIO controls 'out' */ + P10_2_AMUXA = 4, /* Analog mux bus A */ + P10_2_AMUXB = 5, /* Analog mux bus B */ + P10_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P10_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P10_2_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:4 */ P10_2_TCPWM0_LINE263 = 9, /* Digital Active - tcpwm[0].line[263]:2 */ P10_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:47 */ @@ -986,11 +980,11 @@ typedef enum P10_2_CPUSS_TRACE_DATA1 = 27, /* Digital Active - cpuss.trace_data[1]:0 */ /* P10.3 */ - P10_3_GPIO = 0, /* N/A */ - P10_3_AMUXA = 4, /* AMUXBUS A */ - P10_3_AMUXB = 5, /* AMUXBUS B */ - P10_3_AMUXA_DSI = 6, /* N/A */ - P10_3_AMUXB_DSI = 7, /* N/A */ + P10_3_GPIO = 0, /* GPIO controls 'out' */ + P10_3_AMUXA = 4, /* Analog mux bus A */ + P10_3_AMUXB = 5, /* Analog mux bus B */ + P10_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P10_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P10_3_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:4 */ P10_3_TCPWM0_LINE_COMPL263 = 9, /* Digital Active - tcpwm[0].line_compl[263]:2 */ P10_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:48 */ @@ -1003,11 +997,11 @@ typedef enum P10_3_CPUSS_TRACE_DATA0 = 27, /* Digital Active - cpuss.trace_data[0]:0 */ /* P10.4 */ - P10_4_GPIO = 0, /* N/A */ - P10_4_AMUXA = 4, /* AMUXBUS A */ - P10_4_AMUXB = 5, /* AMUXBUS B */ - P10_4_AMUXA_DSI = 6, /* N/A */ - P10_4_AMUXB_DSI = 7, /* N/A */ + P10_4_GPIO = 0, /* GPIO controls 'out' */ + P10_4_AMUXA = 4, /* Analog mux bus A */ + P10_4_AMUXB = 5, /* Analog mux bus B */ + P10_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P10_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P10_4_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:5 */ P10_4_TCPWM0_LINE256 = 9, /* Digital Active - tcpwm[0].line[256]:2 */ P10_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:49 */ @@ -1018,11 +1012,11 @@ typedef enum P10_4_TCPWM0_TR_ONE_CNT_IN1 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[1]:4 */ /* P10.5 */ - P10_5_GPIO = 0, /* N/A */ - P10_5_AMUXA = 4, /* AMUXBUS A */ - P10_5_AMUXB = 5, /* AMUXBUS B */ - P10_5_AMUXA_DSI = 6, /* N/A */ - P10_5_AMUXB_DSI = 7, /* N/A */ + P10_5_GPIO = 0, /* GPIO controls 'out' */ + P10_5_AMUXA = 4, /* Analog mux bus A */ + P10_5_AMUXB = 5, /* Analog mux bus B */ + P10_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P10_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P10_5_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:5 */ P10_5_TCPWM0_LINE_COMPL256 = 9, /* Digital Active - tcpwm[0].line_compl[256]:2 */ P10_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:50 */ @@ -1033,11 +1027,11 @@ typedef enum P10_5_TCPWM0_TR_ONE_CNT_IN2 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[2]:4 */ /* P10.6 */ - P10_6_GPIO = 0, /* N/A */ - P10_6_AMUXA = 4, /* AMUXBUS A */ - P10_6_AMUXB = 5, /* AMUXBUS B */ - P10_6_AMUXA_DSI = 6, /* N/A */ - P10_6_AMUXB_DSI = 7, /* N/A */ + P10_6_GPIO = 0, /* GPIO controls 'out' */ + P10_6_AMUXA = 4, /* Analog mux bus A */ + P10_6_AMUXB = 5, /* Analog mux bus B */ + P10_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P10_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P10_6_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:5 */ P10_6_TCPWM0_LINE257 = 9, /* Digital Active - tcpwm[0].line[257]:2 */ P10_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:51 */ @@ -1049,11 +1043,11 @@ typedef enum P10_6_PERI_TR_IO_INPUT22 = 24, /* Digital Active - peri.tr_io_input[22]:0 */ /* P10.7 */ - P10_7_GPIO = 0, /* N/A */ - P10_7_AMUXA = 4, /* AMUXBUS A */ - P10_7_AMUXB = 5, /* AMUXBUS B */ - P10_7_AMUXA_DSI = 6, /* N/A */ - P10_7_AMUXB_DSI = 7, /* N/A */ + P10_7_GPIO = 0, /* GPIO controls 'out' */ + P10_7_AMUXA = 4, /* Analog mux bus A */ + P10_7_AMUXB = 5, /* Analog mux bus B */ + P10_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P10_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P10_7_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:5 */ P10_7_TCPWM0_LINE_COMPL257 = 9, /* Digital Active - tcpwm[0].line_compl[257]:2 */ P10_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:52 */ @@ -1065,7 +1059,7 @@ typedef enum P10_7_PERI_TR_IO_INPUT23 = 24, /* Digital Active - peri.tr_io_input[23]:0 */ /* P11.2 */ - P11_2_GPIO = 0, /* N/A */ + P11_2_GPIO = 0, /* GPIO controls 'out' */ P11_2_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:5 */ P11_2_TCPWM0_LINE259 = 9, /* Digital Active - tcpwm[0].line[259]:2 */ P11_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:54 */ @@ -1078,7 +1072,7 @@ typedef enum P11_2_TCPWM0_TR_ONE_CNT_IN258 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[258]:4 */ /* P11.3 */ - P11_3_GPIO = 0, /* N/A */ + P11_3_GPIO = 0, /* GPIO controls 'out' */ P11_3_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:5 */ P11_3_TCPWM0_LINE_COMPL259 = 9, /* Digital Active - tcpwm[0].line_compl[259]:2 */ P11_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:55 */ @@ -1092,7 +1086,7 @@ typedef enum P11_3_PERI_TR_IO_OUTPUT0 = 25, /* Digital Active - peri.tr_io_output[0]:0 */ /* P11.4 */ - P11_4_GPIO = 0, /* N/A */ + P11_4_GPIO = 0, /* GPIO controls 'out' */ P11_4_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:6 */ P11_4_TCPWM0_LINE260 = 9, /* Digital Active - tcpwm[0].line[260]:3 */ P11_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:56 */ @@ -1105,7 +1099,7 @@ typedef enum P11_4_PERI_TR_IO_OUTPUT1 = 25, /* Digital Active - peri.tr_io_output[1]:0 */ /* P11.5 */ - P11_5_GPIO = 0, /* N/A */ + P11_5_GPIO = 0, /* GPIO controls 'out' */ P11_5_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:6 */ P11_5_TCPWM0_LINE_COMPL260 = 9, /* Digital Active - tcpwm[0].line_compl[260]:3 */ P11_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:57 */ @@ -1117,7 +1111,7 @@ typedef enum P11_5_TCPWM0_TR_ONE_CNT_IN261 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[261]:4 */ /* P11.6 */ - P11_6_GPIO = 0, /* N/A */ + P11_6_GPIO = 0, /* GPIO controls 'out' */ P11_6_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:6 */ P11_6_TCPWM0_LINE261 = 9, /* Digital Active - tcpwm[0].line[261]:3 */ P11_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:58 */ @@ -1129,7 +1123,7 @@ typedef enum P11_6_TCPWM0_TR_ONE_CNT_IN262 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[262]:4 */ /* P11.7 */ - P11_7_GPIO = 0, /* N/A */ + P11_7_GPIO = 0, /* GPIO controls 'out' */ P11_7_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:6 */ P11_7_TCPWM0_LINE_COMPL261 = 9, /* Digital Active - tcpwm[0].line_compl[261]:2 */ P11_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:59 */ @@ -1140,7 +1134,7 @@ typedef enum P11_7_TCPWM0_TR_ONE_CNT_IN263 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[263]:4 */ /* P12.6 */ - P12_6_GPIO = 0, /* N/A */ + P12_6_GPIO = 0, /* GPIO controls 'out' */ P12_6_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:6 */ P12_6_TCPWM0_LINE263 = 9, /* Digital Active - tcpwm[0].line[263]:3 */ P12_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:60 */ @@ -1150,14 +1144,20 @@ typedef enum P12_6_TCPWM0_TR_ONE_CNT_IN0 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[0]:5 */ /* P12.7 */ - P12_7_GPIO = 0, /* N/A */ + P12_7_GPIO = 0, /* GPIO controls 'out' */ P12_7_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:6 */ P12_7_TCPWM0_LINE_COMPL263 = 9, /* Digital Active - tcpwm[0].line_compl[263]:3 */ P12_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:61 */ P12_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:61 */ P12_7_LCD_COM3 = 12, /* Digital Deep Sleep - lcd.com[3]:1 */ P12_7_LCD_SEG3 = 13, /* Digital Deep Sleep - lcd.seg[3]:1 */ - P12_7_TCPWM0_TR_ONE_CNT_IN1 = 23 /* Digital Active - tcpwm[0].tr_one_cnt_in[1]:5 */ + P12_7_TCPWM0_TR_ONE_CNT_IN1 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[1]:5 */ + + /* USBDP */ + USBDP_GPIO = 0, /* GPIO controls 'out' */ + + /* USBDM */ + USBDM_GPIO = 0 /* GPIO controls 'out' */ } en_hsiom_sel_t; #endif /* _GPIO_PSOC6_04_68_QFN_H_ */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_04_80_tqfp.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_04_80_tqfp.h index 53bb9c57e5..fedd647afd 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_04_80_tqfp.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_04_80_tqfp.h @@ -5,7 +5,7 @@ * PSoC6_04 device GPIO header for 80-TQFP package * * \note -* Generator version: 1.6.0.111 +* Generator version: 1.6.0.150 * ******************************************************************************** * \copyright @@ -394,41 +394,41 @@ typedef enum typedef enum { /* Generic HSIOM connections */ - HSIOM_SEL_GPIO = 0, /* N/A */ - HSIOM_SEL_GPIO_DSI = 1, /* N/A */ - HSIOM_SEL_DSI_DSI = 2, /* N/A */ - HSIOM_SEL_DSI_GPIO = 3, /* N/A */ - HSIOM_SEL_AMUXA = 4, /* AMUXBUS A */ - HSIOM_SEL_AMUXB = 5, /* AMUXBUS B */ - HSIOM_SEL_AMUXA_DSI = 6, /* N/A */ - HSIOM_SEL_AMUXB_DSI = 7, /* N/A */ - HSIOM_SEL_ACT_0 = 8, /* Active peripherals 0 */ - HSIOM_SEL_ACT_1 = 9, /* Active peripherals 1 */ - HSIOM_SEL_ACT_2 = 10, /* Active peripherals 2 */ - HSIOM_SEL_ACT_3 = 11, /* Active peripherals 4 */ - HSIOM_SEL_DS_0 = 12, /* Deep Sleep peripherals 0 */ - HSIOM_SEL_DS_1 = 13, /* Deep Sleep peripherals 1 */ - HSIOM_SEL_DS_2 = 14, /* Deep Sleep peripherals 2 */ - HSIOM_SEL_DS_3 = 15, /* Deep Sleep peripherals 3 */ - HSIOM_SEL_ACT_4 = 16, /* Active peripherals 4 */ - HSIOM_SEL_ACT_5 = 17, /* Active peripherals 5 */ - HSIOM_SEL_ACT_6 = 18, /* Active peripherals 6 */ - HSIOM_SEL_ACT_7 = 19, /* Active peripherals 7 */ - HSIOM_SEL_ACT_8 = 20, /* Active peripherals 8 */ - HSIOM_SEL_ACT_9 = 21, /* Active peripherals 9 */ - HSIOM_SEL_ACT_10 = 22, /* Active peripherals 10 */ - HSIOM_SEL_ACT_11 = 23, /* Active peripherals 11 */ - HSIOM_SEL_ACT_12 = 24, /* Active peripherals 12 */ - HSIOM_SEL_ACT_13 = 25, /* Active peripherals 13 */ - HSIOM_SEL_ACT_14 = 26, /* Active peripherals 14 */ - HSIOM_SEL_ACT_15 = 27, /* Active peripherals 15 */ - HSIOM_SEL_DS_4 = 28, /* N/A */ - HSIOM_SEL_DS_5 = 29, /* N/A */ - HSIOM_SEL_DS_6 = 30, /* N/A */ - HSIOM_SEL_DS_7 = 31, /* N/A */ + HSIOM_SEL_GPIO = 0, /* GPIO controls 'out' */ + HSIOM_SEL_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + HSIOM_SEL_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + HSIOM_SEL_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + HSIOM_SEL_AMUXA = 4, /* Analog mux bus A */ + HSIOM_SEL_AMUXB = 5, /* Analog mux bus B */ + HSIOM_SEL_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + HSIOM_SEL_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + HSIOM_SEL_ACT_0 = 8, /* Active functionality 0 */ + HSIOM_SEL_ACT_1 = 9, /* Active functionality 1 */ + HSIOM_SEL_ACT_2 = 10, /* Active functionality 2 */ + HSIOM_SEL_ACT_3 = 11, /* Active functionality 3 */ + HSIOM_SEL_DS_0 = 12, /* DeepSleep functionality 0 */ + HSIOM_SEL_DS_1 = 13, /* DeepSleep functionality 1 */ + HSIOM_SEL_DS_2 = 14, /* DeepSleep functionality 2 */ + HSIOM_SEL_DS_3 = 15, /* DeepSleep functionality 3 */ + HSIOM_SEL_ACT_4 = 16, /* Active functionality 4 */ + HSIOM_SEL_ACT_5 = 17, /* Active functionality 5 */ + HSIOM_SEL_ACT_6 = 18, /* Active functionality 6 */ + HSIOM_SEL_ACT_7 = 19, /* Active functionality 7 */ + HSIOM_SEL_ACT_8 = 20, /* Active functionality 8 */ + HSIOM_SEL_ACT_9 = 21, /* Active functionality 9 */ + HSIOM_SEL_ACT_10 = 22, /* Active functionality 10 */ + HSIOM_SEL_ACT_11 = 23, /* Active functionality 11 */ + HSIOM_SEL_ACT_12 = 24, /* Active functionality 12 */ + HSIOM_SEL_ACT_13 = 25, /* Active functionality 13 */ + HSIOM_SEL_ACT_14 = 26, /* Active functionality 14 */ + HSIOM_SEL_ACT_15 = 27, /* Active functionality 15 */ + HSIOM_SEL_DS_4 = 28, /* DeepSleep functionality 4 */ + HSIOM_SEL_DS_5 = 29, /* DeepSleep functionality 5 */ + HSIOM_SEL_DS_6 = 30, /* DeepSleep functionality 6 */ + HSIOM_SEL_DS_7 = 31, /* DeepSleep functionality 7 */ /* P0.0 */ - P0_0_GPIO = 0, /* N/A */ + P0_0_GPIO = 0, /* GPIO controls 'out' */ P0_0_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:0 */ P0_0_TCPWM0_LINE256 = 9, /* Digital Active - tcpwm[0].line[256]:0 */ P0_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:0 */ @@ -441,7 +441,7 @@ typedef enum P0_0_PERI_TR_IO_INPUT0 = 24, /* Digital Active - peri.tr_io_input[0]:0 */ /* P0.1 */ - P0_1_GPIO = 0, /* N/A */ + P0_1_GPIO = 0, /* GPIO controls 'out' */ P0_1_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:0 */ P0_1_TCPWM0_LINE_COMPL256 = 9, /* Digital Active - tcpwm[0].line_compl[256]:0 */ P0_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:1 */ @@ -454,7 +454,7 @@ typedef enum P0_1_CPUSS_SWJ_TRSTN = 29, /* Digital Deep Sleep - cpuss.swj_trstn */ /* P0.2 */ - P0_2_GPIO = 0, /* N/A */ + P0_2_GPIO = 0, /* GPIO controls 'out' */ P0_2_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:0 */ P0_2_TCPWM0_LINE257 = 9, /* Digital Active - tcpwm[0].line[257]:0 */ P0_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:2 */ @@ -467,7 +467,7 @@ typedef enum P0_2_TCPWM0_TR_ONE_CNT_IN2 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[2]:0 */ /* P0.3 */ - P0_3_GPIO = 0, /* N/A */ + P0_3_GPIO = 0, /* GPIO controls 'out' */ P0_3_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:0 */ P0_3_TCPWM0_LINE_COMPL257 = 9, /* Digital Active - tcpwm[0].line_compl[257]:0 */ P0_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:3 */ @@ -480,7 +480,7 @@ typedef enum P0_3_TCPWM0_TR_ONE_CNT_IN3 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[3]:0 */ /* P0.4 */ - P0_4_GPIO = 0, /* N/A */ + P0_4_GPIO = 0, /* GPIO controls 'out' */ P0_4_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:0 */ P0_4_TCPWM0_LINE258 = 9, /* Digital Active - tcpwm[0].line[258]:0 */ P0_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:4 */ @@ -494,7 +494,7 @@ typedef enum P0_4_PERI_TR_IO_OUTPUT0 = 25, /* Digital Active - peri.tr_io_output[0]:2 */ /* P0.5 */ - P0_5_GPIO = 0, /* N/A */ + P0_5_GPIO = 0, /* GPIO controls 'out' */ P0_5_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:0 */ P0_5_TCPWM0_LINE_COMPL258 = 9, /* Digital Active - tcpwm[0].line_compl[258]:0 */ P0_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:5 */ @@ -509,25 +509,25 @@ typedef enum P0_5_PERI_TR_IO_OUTPUT1 = 25, /* Digital Active - peri.tr_io_output[1]:2 */ /* P1.0 */ - P1_0_GPIO = 0, /* N/A */ + P1_0_GPIO = 0, /* GPIO controls 'out' */ P1_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:6 */ P1_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:6 */ P1_0_TCPWM0_TR_ONE_CNT_IN258 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[258]:0 */ /* P1.1 */ - P1_1_GPIO = 0, /* N/A */ + P1_1_GPIO = 0, /* GPIO controls 'out' */ P1_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:7 */ P1_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:7 */ P1_1_TCPWM0_TR_ONE_CNT_IN259 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[259]:0 */ /* P1.2 */ - P1_2_GPIO = 0, /* N/A */ + P1_2_GPIO = 0, /* GPIO controls 'out' */ P1_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:8 */ P1_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:8 */ P1_2_TCPWM0_TR_ONE_CNT_IN260 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[260]:0 */ /* P2.0 */ - P2_0_GPIO = 0, /* N/A */ + P2_0_GPIO = 0, /* GPIO controls 'out' */ P2_0_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:0 */ P2_0_TCPWM0_LINE259 = 9, /* Digital Active - tcpwm[0].line[259]:0 */ P2_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:9 */ @@ -541,7 +541,7 @@ typedef enum P2_0_PERI_TR_IO_INPUT4 = 24, /* Digital Active - peri.tr_io_input[4]:0 */ /* P2.1 */ - P2_1_GPIO = 0, /* N/A */ + P2_1_GPIO = 0, /* GPIO controls 'out' */ P2_1_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:0 */ P2_1_TCPWM0_LINE_COMPL259 = 9, /* Digital Active - tcpwm[0].line_compl[259]:0 */ P2_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:10 */ @@ -555,7 +555,7 @@ typedef enum P2_1_PERI_TR_IO_INPUT5 = 24, /* Digital Active - peri.tr_io_input[5]:0 */ /* P2.2 */ - P2_2_GPIO = 0, /* N/A */ + P2_2_GPIO = 0, /* GPIO controls 'out' */ P2_2_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:1 */ P2_2_TCPWM0_LINE260 = 9, /* Digital Active - tcpwm[0].line[260]:0 */ P2_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:11 */ @@ -567,7 +567,7 @@ typedef enum P2_2_TCPWM0_TR_ONE_CNT_IN263 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[263]:0 */ /* P2.3 */ - P2_3_GPIO = 0, /* N/A */ + P2_3_GPIO = 0, /* GPIO controls 'out' */ P2_3_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:1 */ P2_3_TCPWM0_LINE_COMPL260 = 9, /* Digital Active - tcpwm[0].line_compl[260]:0 */ P2_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:12 */ @@ -579,7 +579,7 @@ typedef enum P2_3_TCPWM0_TR_ONE_CNT_IN0 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[0]:1 */ /* P2.4 */ - P2_4_GPIO = 0, /* N/A */ + P2_4_GPIO = 0, /* GPIO controls 'out' */ P2_4_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:1 */ P2_4_TCPWM0_LINE261 = 9, /* Digital Active - tcpwm[0].line[261]:0 */ P2_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:13 */ @@ -590,7 +590,7 @@ typedef enum P2_4_TCPWM0_TR_ONE_CNT_IN1 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[1]:1 */ /* P2.5 */ - P2_5_GPIO = 0, /* N/A */ + P2_5_GPIO = 0, /* GPIO controls 'out' */ P2_5_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:1 */ P2_5_TCPWM0_LINE_COMPL261 = 9, /* Digital Active - tcpwm[0].line_compl[261]:0 */ P2_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:14 */ @@ -601,7 +601,7 @@ typedef enum P2_5_TCPWM0_TR_ONE_CNT_IN2 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[2]:1 */ /* P2.6 */ - P2_6_GPIO = 0, /* N/A */ + P2_6_GPIO = 0, /* GPIO controls 'out' */ P2_6_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:1 */ P2_6_TCPWM0_LINE262 = 9, /* Digital Active - tcpwm[0].line[262]:0 */ P2_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:15 */ @@ -614,7 +614,7 @@ typedef enum P2_6_PERI_TR_IO_INPUT8 = 24, /* Digital Active - peri.tr_io_input[8]:0 */ /* P2.7 */ - P2_7_GPIO = 0, /* N/A */ + P2_7_GPIO = 0, /* GPIO controls 'out' */ P2_7_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:1 */ P2_7_TCPWM0_LINE_COMPL262 = 9, /* Digital Active - tcpwm[0].line_compl[262]:0 */ P2_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:16 */ @@ -626,7 +626,7 @@ typedef enum P2_7_PERI_TR_IO_INPUT9 = 24, /* Digital Active - peri.tr_io_input[9]:0 */ /* P3.0 */ - P3_0_GPIO = 0, /* N/A */ + P3_0_GPIO = 0, /* GPIO controls 'out' */ P3_0_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:1 */ P3_0_TCPWM0_LINE263 = 9, /* Digital Active - tcpwm[0].line[263]:0 */ P3_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:17 */ @@ -639,7 +639,7 @@ typedef enum P3_0_PERI_TR_IO_INPUT6 = 24, /* Digital Active - peri.tr_io_input[6]:0 */ /* P3.1 */ - P3_1_GPIO = 0, /* N/A */ + P3_1_GPIO = 0, /* GPIO controls 'out' */ P3_1_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:1 */ P3_1_TCPWM0_LINE_COMPL263 = 9, /* Digital Active - tcpwm[0].line_compl[263]:0 */ P3_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:18 */ @@ -652,7 +652,7 @@ typedef enum P3_1_PERI_TR_IO_INPUT7 = 24, /* Digital Active - peri.tr_io_input[7]:0 */ /* P5.0 */ - P5_0_GPIO = 0, /* N/A */ + P5_0_GPIO = 0, /* GPIO controls 'out' */ P5_0_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:2 */ P5_0_TCPWM0_LINE256 = 9, /* Digital Active - tcpwm[0].line[256]:1 */ P5_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:19 */ @@ -667,7 +667,7 @@ typedef enum P5_0_PERI_TR_IO_INPUT10 = 24, /* Digital Active - peri.tr_io_input[10]:0 */ /* P5.1 */ - P5_1_GPIO = 0, /* N/A */ + P5_1_GPIO = 0, /* GPIO controls 'out' */ P5_1_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:2 */ P5_1_TCPWM0_LINE_COMPL256 = 9, /* Digital Active - tcpwm[0].line_compl[256]:1 */ P5_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:20 */ @@ -682,13 +682,13 @@ typedef enum P5_1_PERI_TR_IO_INPUT11 = 24, /* Digital Active - peri.tr_io_input[11]:0 */ /* P5.2 */ - P5_2_GPIO = 0, /* N/A */ + P5_2_GPIO = 0, /* GPIO controls 'out' */ P5_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:21 */ P5_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:21 */ P5_2_TCPWM0_TR_ONE_CNT_IN261 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[261]:1 */ /* P5.6 */ - P5_6_GPIO = 0, /* N/A */ + P5_6_GPIO = 0, /* GPIO controls 'out' */ P5_6_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:2 */ P5_6_TCPWM0_LINE257 = 9, /* Digital Active - tcpwm[0].line[257]:1 */ P5_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:22 */ @@ -698,7 +698,7 @@ typedef enum P5_6_TCPWM0_TR_ONE_CNT_IN262 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[262]:1 */ /* P5.7 */ - P5_7_GPIO = 0, /* N/A */ + P5_7_GPIO = 0, /* GPIO controls 'out' */ P5_7_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:2 */ P5_7_TCPWM0_LINE_COMPL257 = 9, /* Digital Active - tcpwm[0].line_compl[257]:1 */ P5_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:23 */ @@ -708,7 +708,7 @@ typedef enum P5_7_TCPWM0_TR_ONE_CNT_IN263 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[263]:1 */ /* P6.2 */ - P6_2_GPIO = 0, /* N/A */ + P6_2_GPIO = 0, /* GPIO controls 'out' */ P6_2_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:2 */ P6_2_TCPWM0_LINE259 = 9, /* Digital Active - tcpwm[0].line[259]:1 */ P6_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:24 */ @@ -719,7 +719,7 @@ typedef enum P6_2_CPUSS_FAULT_OUT0 = 25, /* Digital Active - cpuss.fault_out[0] */ /* P6.3 */ - P6_3_GPIO = 0, /* N/A */ + P6_3_GPIO = 0, /* GPIO controls 'out' */ P6_3_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:2 */ P6_3_TCPWM0_LINE_COMPL259 = 9, /* Digital Active - tcpwm[0].line_compl[259]:1 */ P6_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:25 */ @@ -730,7 +730,7 @@ typedef enum P6_3_CPUSS_FAULT_OUT1 = 25, /* Digital Active - cpuss.fault_out[1] */ /* P6.4 */ - P6_4_GPIO = 0, /* N/A */ + P6_4_GPIO = 0, /* GPIO controls 'out' */ P6_4_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:3 */ P6_4_TCPWM0_LINE260 = 9, /* Digital Active - tcpwm[0].line[260]:1 */ P6_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:26 */ @@ -746,7 +746,7 @@ typedef enum P6_4_SRSS_DDFT_PIN_IN0 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[0]:0 */ /* P6.5 */ - P6_5_GPIO = 0, /* N/A */ + P6_5_GPIO = 0, /* GPIO controls 'out' */ P6_5_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:3 */ P6_5_TCPWM0_LINE_COMPL260 = 9, /* Digital Active - tcpwm[0].line_compl[260]:1 */ P6_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:27 */ @@ -762,7 +762,7 @@ typedef enum P6_5_SRSS_DDFT_PIN_IN1 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[1]:0 */ /* P6.6 */ - P6_6_GPIO = 0, /* N/A */ + P6_6_GPIO = 0, /* GPIO controls 'out' */ P6_6_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:3 */ P6_6_TCPWM0_LINE261 = 9, /* Digital Active - tcpwm[0].line[261]:1 */ P6_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:28 */ @@ -774,7 +774,7 @@ typedef enum P6_6_SCB6_SPI_CLK = 30, /* Digital Deep Sleep - scb[6].spi_clk:0 */ /* P6.7 */ - P6_7_GPIO = 0, /* N/A */ + P6_7_GPIO = 0, /* GPIO controls 'out' */ P6_7_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:3 */ P6_7_TCPWM0_LINE_COMPL261 = 9, /* Digital Active - tcpwm[0].line_compl[261]:1 */ P6_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:29 */ @@ -786,11 +786,11 @@ typedef enum P6_7_SCB6_SPI_SELECT0 = 30, /* Digital Deep Sleep - scb[6].spi_select0:0 */ /* P7.0 */ - P7_0_GPIO = 0, /* N/A */ - P7_0_AMUXA = 4, /* AMUXBUS A */ - P7_0_AMUXB = 5, /* AMUXBUS B */ - P7_0_AMUXA_DSI = 6, /* N/A */ - P7_0_AMUXB_DSI = 7, /* N/A */ + P7_0_GPIO = 0, /* GPIO controls 'out' */ + P7_0_AMUXA = 4, /* Analog mux bus A */ + P7_0_AMUXB = 5, /* Analog mux bus B */ + P7_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P7_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P7_0_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:2 */ P7_0_TCPWM0_LINE262 = 9, /* Digital Active - tcpwm[0].line[262]:1 */ P7_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:30 */ @@ -805,11 +805,11 @@ typedef enum P7_0_CPUSS_TRACE_CLOCK = 26, /* Digital Active - cpuss.trace_clock */ /* P7.1 */ - P7_1_GPIO = 0, /* N/A */ - P7_1_AMUXA = 4, /* AMUXBUS A */ - P7_1_AMUXB = 5, /* AMUXBUS B */ - P7_1_AMUXA_DSI = 6, /* N/A */ - P7_1_AMUXB_DSI = 7, /* N/A */ + P7_1_GPIO = 0, /* GPIO controls 'out' */ + P7_1_AMUXA = 4, /* Analog mux bus A */ + P7_1_AMUXB = 5, /* Analog mux bus B */ + P7_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P7_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P7_1_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:2 */ P7_1_TCPWM0_LINE_COMPL262 = 9, /* Digital Active - tcpwm[0].line_compl[262]:1 */ P7_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:31 */ @@ -823,11 +823,11 @@ typedef enum P7_1_PERI_TR_IO_INPUT15 = 24, /* Digital Active - peri.tr_io_input[15]:0 */ /* P7.2 */ - P7_2_GPIO = 0, /* N/A */ - P7_2_AMUXA = 4, /* AMUXBUS A */ - P7_2_AMUXB = 5, /* AMUXBUS B */ - P7_2_AMUXA_DSI = 6, /* N/A */ - P7_2_AMUXB_DSI = 7, /* N/A */ + P7_2_GPIO = 0, /* GPIO controls 'out' */ + P7_2_AMUXA = 4, /* Analog mux bus A */ + P7_2_AMUXB = 5, /* Analog mux bus B */ + P7_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P7_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P7_2_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:3 */ P7_2_TCPWM0_LINE263 = 9, /* Digital Active - tcpwm[0].line[263]:1 */ P7_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:32 */ @@ -839,11 +839,11 @@ typedef enum P7_2_TCPWM0_TR_ONE_CNT_IN260 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[260]:2 */ /* P7.3 */ - P7_3_GPIO = 0, /* N/A */ - P7_3_AMUXA = 4, /* AMUXBUS A */ - P7_3_AMUXB = 5, /* AMUXBUS B */ - P7_3_AMUXA_DSI = 6, /* N/A */ - P7_3_AMUXB_DSI = 7, /* N/A */ + P7_3_GPIO = 0, /* GPIO controls 'out' */ + P7_3_AMUXA = 4, /* Analog mux bus A */ + P7_3_AMUXB = 5, /* Analog mux bus B */ + P7_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P7_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P7_3_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:3 */ P7_3_TCPWM0_LINE_COMPL263 = 9, /* Digital Active - tcpwm[0].line_compl[263]:1 */ P7_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:33 */ @@ -855,11 +855,11 @@ typedef enum P7_3_TCPWM0_TR_ONE_CNT_IN261 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[261]:2 */ /* P7.4 */ - P7_4_GPIO = 0, /* N/A */ - P7_4_AMUXA = 4, /* AMUXBUS A */ - P7_4_AMUXB = 5, /* AMUXBUS B */ - P7_4_AMUXA_DSI = 6, /* N/A */ - P7_4_AMUXB_DSI = 7, /* N/A */ + P7_4_GPIO = 0, /* GPIO controls 'out' */ + P7_4_AMUXA = 4, /* Analog mux bus A */ + P7_4_AMUXB = 5, /* Analog mux bus B */ + P7_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P7_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P7_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:34 */ P7_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:34 */ P7_4_LCD_COM32 = 12, /* Digital Deep Sleep - lcd.com[32]:0 */ @@ -868,11 +868,11 @@ typedef enum P7_4_TCPWM0_TR_ONE_CNT_IN262 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[262]:2 */ /* P7.5 */ - P7_5_GPIO = 0, /* N/A */ - P7_5_AMUXA = 4, /* AMUXBUS A */ - P7_5_AMUXB = 5, /* AMUXBUS B */ - P7_5_AMUXA_DSI = 6, /* N/A */ - P7_5_AMUXB_DSI = 7, /* N/A */ + P7_5_GPIO = 0, /* GPIO controls 'out' */ + P7_5_AMUXA = 4, /* Analog mux bus A */ + P7_5_AMUXB = 5, /* Analog mux bus B */ + P7_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P7_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P7_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:35 */ P7_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:35 */ P7_5_LCD_COM33 = 12, /* Digital Deep Sleep - lcd.com[33]:0 */ @@ -881,11 +881,11 @@ typedef enum P7_5_TCPWM0_TR_ONE_CNT_IN263 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[263]:2 */ /* P7.7 */ - P7_7_GPIO = 0, /* N/A */ - P7_7_AMUXA = 4, /* AMUXBUS A */ - P7_7_AMUXB = 5, /* AMUXBUS B */ - P7_7_AMUXA_DSI = 6, /* N/A */ - P7_7_AMUXB_DSI = 7, /* N/A */ + P7_7_GPIO = 0, /* GPIO controls 'out' */ + P7_7_AMUXA = 4, /* Analog mux bus A */ + P7_7_AMUXB = 5, /* Analog mux bus B */ + P7_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P7_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P7_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:36 */ P7_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:36 */ P7_7_LCD_COM35 = 12, /* Digital Deep Sleep - lcd.com[35]:0 */ @@ -894,11 +894,11 @@ typedef enum P7_7_TCPWM0_TR_ONE_CNT_IN0 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[0]:3 */ /* P8.0 */ - P8_0_GPIO = 0, /* N/A */ - P8_0_AMUXA = 4, /* AMUXBUS A */ - P8_0_AMUXB = 5, /* AMUXBUS B */ - P8_0_AMUXA_DSI = 6, /* N/A */ - P8_0_AMUXB_DSI = 7, /* N/A */ + P8_0_GPIO = 0, /* GPIO controls 'out' */ + P8_0_AMUXA = 4, /* Analog mux bus A */ + P8_0_AMUXB = 5, /* Analog mux bus B */ + P8_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P8_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P8_0_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:3 */ P8_0_TCPWM0_LINE258 = 9, /* Digital Active - tcpwm[0].line[258]:1 */ P8_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:37 */ @@ -912,11 +912,11 @@ typedef enum P8_0_PERI_TR_IO_INPUT16 = 24, /* Digital Active - peri.tr_io_input[16]:0 */ /* P8.1 */ - P8_1_GPIO = 0, /* N/A */ - P8_1_AMUXA = 4, /* AMUXBUS A */ - P8_1_AMUXB = 5, /* AMUXBUS B */ - P8_1_AMUXA_DSI = 6, /* N/A */ - P8_1_AMUXB_DSI = 7, /* N/A */ + P8_1_GPIO = 0, /* GPIO controls 'out' */ + P8_1_AMUXA = 4, /* Analog mux bus A */ + P8_1_AMUXB = 5, /* Analog mux bus B */ + P8_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P8_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P8_1_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:3 */ P8_1_TCPWM0_LINE_COMPL258 = 9, /* Digital Active - tcpwm[0].line_compl[258]:1 */ P8_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:38 */ @@ -930,11 +930,11 @@ typedef enum P8_1_PERI_TR_IO_INPUT17 = 24, /* Digital Active - peri.tr_io_input[17]:0 */ /* P9.0 */ - P9_0_GPIO = 0, /* N/A */ - P9_0_AMUXA = 4, /* AMUXBUS A */ - P9_0_AMUXB = 5, /* AMUXBUS B */ - P9_0_AMUXA_DSI = 6, /* N/A */ - P9_0_AMUXB_DSI = 7, /* N/A */ + P9_0_GPIO = 0, /* GPIO controls 'out' */ + P9_0_AMUXA = 4, /* Analog mux bus A */ + P9_0_AMUXB = 5, /* Analog mux bus B */ + P9_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P9_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P9_0_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:4 */ P9_0_TCPWM0_LINE260 = 9, /* Digital Active - tcpwm[0].line[260]:2 */ P9_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:39 */ @@ -949,11 +949,11 @@ typedef enum P9_0_CPUSS_TRACE_DATA3 = 27, /* Digital Active - cpuss.trace_data[3]:1 */ /* P9.1 */ - P9_1_GPIO = 0, /* N/A */ - P9_1_AMUXA = 4, /* AMUXBUS A */ - P9_1_AMUXB = 5, /* AMUXBUS B */ - P9_1_AMUXA_DSI = 6, /* N/A */ - P9_1_AMUXB_DSI = 7, /* N/A */ + P9_1_GPIO = 0, /* GPIO controls 'out' */ + P9_1_AMUXA = 4, /* Analog mux bus A */ + P9_1_AMUXB = 5, /* Analog mux bus B */ + P9_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P9_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P9_1_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:4 */ P9_1_TCPWM0_LINE_COMPL260 = 9, /* Digital Active - tcpwm[0].line_compl[260]:2 */ P9_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:40 */ @@ -969,11 +969,11 @@ typedef enum P9_1_SRSS_DDFT_PIN_IN0 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[0]:1 */ /* P9.2 */ - P9_2_GPIO = 0, /* N/A */ - P9_2_AMUXA = 4, /* AMUXBUS A */ - P9_2_AMUXB = 5, /* AMUXBUS B */ - P9_2_AMUXA_DSI = 6, /* N/A */ - P9_2_AMUXB_DSI = 7, /* N/A */ + P9_2_GPIO = 0, /* GPIO controls 'out' */ + P9_2_AMUXA = 4, /* Analog mux bus A */ + P9_2_AMUXB = 5, /* Analog mux bus B */ + P9_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P9_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P9_2_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:4 */ P9_2_TCPWM0_LINE261 = 9, /* Digital Active - tcpwm[0].line[261]:2 */ P9_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:41 */ @@ -987,11 +987,11 @@ typedef enum P9_2_CPUSS_TRACE_DATA1 = 27, /* Digital Active - cpuss.trace_data[1]:1 */ /* P9.3 */ - P9_3_GPIO = 0, /* N/A */ - P9_3_AMUXA = 4, /* AMUXBUS A */ - P9_3_AMUXB = 5, /* AMUXBUS B */ - P9_3_AMUXA_DSI = 6, /* N/A */ - P9_3_AMUXB_DSI = 7, /* N/A */ + P9_3_GPIO = 0, /* GPIO controls 'out' */ + P9_3_AMUXA = 4, /* Analog mux bus A */ + P9_3_AMUXB = 5, /* Analog mux bus B */ + P9_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P9_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P9_3_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:4 */ P9_3_TCPWM0_LINE_COMPL261 = 9, /* Digital Active - tcpwm[0].line_compl[261]:3 */ P9_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:42 */ @@ -1006,11 +1006,11 @@ typedef enum P9_3_SRSS_DDFT_PIN_IN1 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[1]:1 */ /* P9.4 */ - P9_4_GPIO = 0, /* N/A */ - P9_4_AMUXA = 4, /* AMUXBUS A */ - P9_4_AMUXB = 5, /* AMUXBUS B */ - P9_4_AMUXA_DSI = 6, /* N/A */ - P9_4_AMUXB_DSI = 7, /* N/A */ + P9_4_GPIO = 0, /* GPIO controls 'out' */ + P9_4_AMUXA = 4, /* Analog mux bus A */ + P9_4_AMUXB = 5, /* Analog mux bus B */ + P9_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P9_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P9_4_TCPWM0_LINE256 = 9, /* Digital Active - tcpwm[0].line[256]:3 */ P9_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:43 */ P9_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:43 */ @@ -1018,11 +1018,11 @@ typedef enum P9_4_TCPWM0_TR_ONE_CNT_IN259 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[259]:3 */ /* P9.5 */ - P9_5_GPIO = 0, /* N/A */ - P9_5_AMUXA = 4, /* AMUXBUS A */ - P9_5_AMUXB = 5, /* AMUXBUS B */ - P9_5_AMUXA_DSI = 6, /* N/A */ - P9_5_AMUXB_DSI = 7, /* N/A */ + P9_5_GPIO = 0, /* GPIO controls 'out' */ + P9_5_AMUXA = 4, /* Analog mux bus A */ + P9_5_AMUXB = 5, /* Analog mux bus B */ + P9_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P9_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P9_5_TCPWM0_LINE_COMPL256 = 9, /* Digital Active - tcpwm[0].line_compl[256]:3 */ P9_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:44 */ P9_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:44 */ @@ -1030,11 +1030,11 @@ typedef enum P9_5_TCPWM0_TR_ONE_CNT_IN260 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[260]:3 */ /* P10.0 */ - P10_0_GPIO = 0, /* N/A */ - P10_0_AMUXA = 4, /* AMUXBUS A */ - P10_0_AMUXB = 5, /* AMUXBUS B */ - P10_0_AMUXA_DSI = 6, /* N/A */ - P10_0_AMUXB_DSI = 7, /* N/A */ + P10_0_GPIO = 0, /* GPIO controls 'out' */ + P10_0_AMUXA = 4, /* Analog mux bus A */ + P10_0_AMUXB = 5, /* Analog mux bus B */ + P10_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P10_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P10_0_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:4 */ P10_0_TCPWM0_LINE262 = 9, /* Digital Active - tcpwm[0].line[262]:2 */ P10_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:45 */ @@ -1049,11 +1049,11 @@ typedef enum P10_0_CPUSS_TRACE_DATA3 = 27, /* Digital Active - cpuss.trace_data[3]:0 */ /* P10.1 */ - P10_1_GPIO = 0, /* N/A */ - P10_1_AMUXA = 4, /* AMUXBUS A */ - P10_1_AMUXB = 5, /* AMUXBUS B */ - P10_1_AMUXA_DSI = 6, /* N/A */ - P10_1_AMUXB_DSI = 7, /* N/A */ + P10_1_GPIO = 0, /* GPIO controls 'out' */ + P10_1_AMUXA = 4, /* Analog mux bus A */ + P10_1_AMUXB = 5, /* Analog mux bus B */ + P10_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P10_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P10_1_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:4 */ P10_1_TCPWM0_LINE_COMPL262 = 9, /* Digital Active - tcpwm[0].line_compl[262]:2 */ P10_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:46 */ @@ -1068,11 +1068,11 @@ typedef enum P10_1_CPUSS_TRACE_DATA2 = 27, /* Digital Active - cpuss.trace_data[2]:0 */ /* P10.2 */ - P10_2_GPIO = 0, /* N/A */ - P10_2_AMUXA = 4, /* AMUXBUS A */ - P10_2_AMUXB = 5, /* AMUXBUS B */ - P10_2_AMUXA_DSI = 6, /* N/A */ - P10_2_AMUXB_DSI = 7, /* N/A */ + P10_2_GPIO = 0, /* GPIO controls 'out' */ + P10_2_AMUXA = 4, /* Analog mux bus A */ + P10_2_AMUXB = 5, /* Analog mux bus B */ + P10_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P10_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P10_2_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:4 */ P10_2_TCPWM0_LINE263 = 9, /* Digital Active - tcpwm[0].line[263]:2 */ P10_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:47 */ @@ -1085,11 +1085,11 @@ typedef enum P10_2_CPUSS_TRACE_DATA1 = 27, /* Digital Active - cpuss.trace_data[1]:0 */ /* P10.3 */ - P10_3_GPIO = 0, /* N/A */ - P10_3_AMUXA = 4, /* AMUXBUS A */ - P10_3_AMUXB = 5, /* AMUXBUS B */ - P10_3_AMUXA_DSI = 6, /* N/A */ - P10_3_AMUXB_DSI = 7, /* N/A */ + P10_3_GPIO = 0, /* GPIO controls 'out' */ + P10_3_AMUXA = 4, /* Analog mux bus A */ + P10_3_AMUXB = 5, /* Analog mux bus B */ + P10_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P10_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P10_3_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:4 */ P10_3_TCPWM0_LINE_COMPL263 = 9, /* Digital Active - tcpwm[0].line_compl[263]:2 */ P10_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:48 */ @@ -1102,11 +1102,11 @@ typedef enum P10_3_CPUSS_TRACE_DATA0 = 27, /* Digital Active - cpuss.trace_data[0]:0 */ /* P10.4 */ - P10_4_GPIO = 0, /* N/A */ - P10_4_AMUXA = 4, /* AMUXBUS A */ - P10_4_AMUXB = 5, /* AMUXBUS B */ - P10_4_AMUXA_DSI = 6, /* N/A */ - P10_4_AMUXB_DSI = 7, /* N/A */ + P10_4_GPIO = 0, /* GPIO controls 'out' */ + P10_4_AMUXA = 4, /* Analog mux bus A */ + P10_4_AMUXB = 5, /* Analog mux bus B */ + P10_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P10_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P10_4_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:5 */ P10_4_TCPWM0_LINE256 = 9, /* Digital Active - tcpwm[0].line[256]:2 */ P10_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:49 */ @@ -1117,11 +1117,11 @@ typedef enum P10_4_TCPWM0_TR_ONE_CNT_IN1 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[1]:4 */ /* P10.5 */ - P10_5_GPIO = 0, /* N/A */ - P10_5_AMUXA = 4, /* AMUXBUS A */ - P10_5_AMUXB = 5, /* AMUXBUS B */ - P10_5_AMUXA_DSI = 6, /* N/A */ - P10_5_AMUXB_DSI = 7, /* N/A */ + P10_5_GPIO = 0, /* GPIO controls 'out' */ + P10_5_AMUXA = 4, /* Analog mux bus A */ + P10_5_AMUXB = 5, /* Analog mux bus B */ + P10_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P10_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P10_5_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:5 */ P10_5_TCPWM0_LINE_COMPL256 = 9, /* Digital Active - tcpwm[0].line_compl[256]:2 */ P10_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:50 */ @@ -1132,11 +1132,11 @@ typedef enum P10_5_TCPWM0_TR_ONE_CNT_IN2 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[2]:4 */ /* P10.6 */ - P10_6_GPIO = 0, /* N/A */ - P10_6_AMUXA = 4, /* AMUXBUS A */ - P10_6_AMUXB = 5, /* AMUXBUS B */ - P10_6_AMUXA_DSI = 6, /* N/A */ - P10_6_AMUXB_DSI = 7, /* N/A */ + P10_6_GPIO = 0, /* GPIO controls 'out' */ + P10_6_AMUXA = 4, /* Analog mux bus A */ + P10_6_AMUXB = 5, /* Analog mux bus B */ + P10_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P10_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P10_6_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:5 */ P10_6_TCPWM0_LINE257 = 9, /* Digital Active - tcpwm[0].line[257]:2 */ P10_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:51 */ @@ -1148,11 +1148,11 @@ typedef enum P10_6_PERI_TR_IO_INPUT22 = 24, /* Digital Active - peri.tr_io_input[22]:0 */ /* P10.7 */ - P10_7_GPIO = 0, /* N/A */ - P10_7_AMUXA = 4, /* AMUXBUS A */ - P10_7_AMUXB = 5, /* AMUXBUS B */ - P10_7_AMUXA_DSI = 6, /* N/A */ - P10_7_AMUXB_DSI = 7, /* N/A */ + P10_7_GPIO = 0, /* GPIO controls 'out' */ + P10_7_AMUXA = 4, /* Analog mux bus A */ + P10_7_AMUXB = 5, /* Analog mux bus B */ + P10_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P10_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P10_7_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:5 */ P10_7_TCPWM0_LINE_COMPL257 = 9, /* Digital Active - tcpwm[0].line_compl[257]:2 */ P10_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:52 */ @@ -1164,7 +1164,7 @@ typedef enum P10_7_PERI_TR_IO_INPUT23 = 24, /* Digital Active - peri.tr_io_input[23]:0 */ /* P11.1 */ - P11_1_GPIO = 0, /* N/A */ + P11_1_GPIO = 0, /* GPIO controls 'out' */ P11_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:53 */ P11_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:53 */ P11_1_LCD_COM53 = 12, /* Digital Deep Sleep - lcd.com[53]:0 */ @@ -1173,7 +1173,7 @@ typedef enum P11_1_TCPWM0_TR_ONE_CNT_IN257 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[257]:4 */ /* P11.2 */ - P11_2_GPIO = 0, /* N/A */ + P11_2_GPIO = 0, /* GPIO controls 'out' */ P11_2_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:5 */ P11_2_TCPWM0_LINE259 = 9, /* Digital Active - tcpwm[0].line[259]:2 */ P11_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:54 */ @@ -1186,7 +1186,7 @@ typedef enum P11_2_TCPWM0_TR_ONE_CNT_IN258 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[258]:4 */ /* P11.3 */ - P11_3_GPIO = 0, /* N/A */ + P11_3_GPIO = 0, /* GPIO controls 'out' */ P11_3_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:5 */ P11_3_TCPWM0_LINE_COMPL259 = 9, /* Digital Active - tcpwm[0].line_compl[259]:2 */ P11_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:55 */ @@ -1200,7 +1200,7 @@ typedef enum P11_3_PERI_TR_IO_OUTPUT0 = 25, /* Digital Active - peri.tr_io_output[0]:0 */ /* P11.4 */ - P11_4_GPIO = 0, /* N/A */ + P11_4_GPIO = 0, /* GPIO controls 'out' */ P11_4_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:6 */ P11_4_TCPWM0_LINE260 = 9, /* Digital Active - tcpwm[0].line[260]:3 */ P11_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:56 */ @@ -1213,7 +1213,7 @@ typedef enum P11_4_PERI_TR_IO_OUTPUT1 = 25, /* Digital Active - peri.tr_io_output[1]:0 */ /* P11.5 */ - P11_5_GPIO = 0, /* N/A */ + P11_5_GPIO = 0, /* GPIO controls 'out' */ P11_5_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:6 */ P11_5_TCPWM0_LINE_COMPL260 = 9, /* Digital Active - tcpwm[0].line_compl[260]:3 */ P11_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:57 */ @@ -1225,7 +1225,7 @@ typedef enum P11_5_TCPWM0_TR_ONE_CNT_IN261 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[261]:4 */ /* P11.6 */ - P11_6_GPIO = 0, /* N/A */ + P11_6_GPIO = 0, /* GPIO controls 'out' */ P11_6_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:6 */ P11_6_TCPWM0_LINE261 = 9, /* Digital Active - tcpwm[0].line[261]:3 */ P11_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:58 */ @@ -1237,7 +1237,7 @@ typedef enum P11_6_TCPWM0_TR_ONE_CNT_IN262 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[262]:4 */ /* P11.7 */ - P11_7_GPIO = 0, /* N/A */ + P11_7_GPIO = 0, /* GPIO controls 'out' */ P11_7_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:6 */ P11_7_TCPWM0_LINE_COMPL261 = 9, /* Digital Active - tcpwm[0].line_compl[261]:2 */ P11_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:59 */ @@ -1248,7 +1248,7 @@ typedef enum P11_7_TCPWM0_TR_ONE_CNT_IN263 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[263]:4 */ /* P12.6 */ - P12_6_GPIO = 0, /* N/A */ + P12_6_GPIO = 0, /* GPIO controls 'out' */ P12_6_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:6 */ P12_6_TCPWM0_LINE263 = 9, /* Digital Active - tcpwm[0].line[263]:3 */ P12_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:60 */ @@ -1258,7 +1258,7 @@ typedef enum P12_6_TCPWM0_TR_ONE_CNT_IN0 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[0]:5 */ /* P12.7 */ - P12_7_GPIO = 0, /* N/A */ + P12_7_GPIO = 0, /* GPIO controls 'out' */ P12_7_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:6 */ P12_7_TCPWM0_LINE_COMPL263 = 9, /* Digital Active - tcpwm[0].line_compl[263]:3 */ P12_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:61 */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_ctbm_v2.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_ctbm_v2.h index 54b84f2af6..a8e1082aef 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_ctbm_v2.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_ctbm_v2.h @@ -5,11 +5,11 @@ * CTBM IP definitions * * \note -* Generator version: 1.5.1.36 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -61,7 +61,14 @@ typedef struct { __IOM uint32_t CTB_SW_DS_CTRL; /*!< 0x000000C0 CTB bus switch control */ __IOM uint32_t CTB_SW_SQ_CTRL; /*!< 0x000000C4 CTB bus switch Sar Sequencer control */ __IM uint32_t CTB_SW_STATUS; /*!< 0x000000C8 CTB bus switch control status */ -} CTBM_V2_Type; /*!< Size = 204 (0xCC) */ + __IM uint32_t RESERVED4[909]; + __IOM uint32_t OA0_OFFSET_TRIM; /*!< 0x00000F00 Opamp0 trim control */ + __IOM uint32_t OA0_SLOPE_OFFSET_TRIM; /*!< 0x00000F04 Opamp0 trim control */ + __IOM uint32_t OA0_COMP_TRIM; /*!< 0x00000F08 Opamp0 trim control */ + __IOM uint32_t OA1_OFFSET_TRIM; /*!< 0x00000F0C Opamp1 trim control */ + __IOM uint32_t OA1_SLOPE_OFFSET_TRIM; /*!< 0x00000F10 Opamp1 trim control */ + __IOM uint32_t OA1_COMP_TRIM; /*!< 0x00000F14 Opamp1 trim control */ +} CTBM_V2_Type; /*!< Size = 3864 (0xF18) */ /* CTBM.CTB_CTRL */ @@ -263,6 +270,24 @@ typedef struct { #define CTBM_V2_CTB_SW_STATUS_OA1O_D62_STAT_Msk 0x40000000UL #define CTBM_V2_CTB_SW_STATUS_CTD_COS_STAT_Pos 31UL #define CTBM_V2_CTB_SW_STATUS_CTD_COS_STAT_Msk 0x80000000UL +/* CTBM.OA0_OFFSET_TRIM */ +#define CTBM_V2_OA0_OFFSET_TRIM_OA0_OFFSET_TRIM_Pos 0UL +#define CTBM_V2_OA0_OFFSET_TRIM_OA0_OFFSET_TRIM_Msk 0x3FUL +/* CTBM.OA0_SLOPE_OFFSET_TRIM */ +#define CTBM_V2_OA0_SLOPE_OFFSET_TRIM_OA0_SLOPE_OFFSET_TRIM_Pos 0UL +#define CTBM_V2_OA0_SLOPE_OFFSET_TRIM_OA0_SLOPE_OFFSET_TRIM_Msk 0x3FUL +/* CTBM.OA0_COMP_TRIM */ +#define CTBM_V2_OA0_COMP_TRIM_OA0_COMP_TRIM_Pos 0UL +#define CTBM_V2_OA0_COMP_TRIM_OA0_COMP_TRIM_Msk 0x3UL +/* CTBM.OA1_OFFSET_TRIM */ +#define CTBM_V2_OA1_OFFSET_TRIM_OA1_OFFSET_TRIM_Pos 0UL +#define CTBM_V2_OA1_OFFSET_TRIM_OA1_OFFSET_TRIM_Msk 0x3FUL +/* CTBM.OA1_SLOPE_OFFSET_TRIM */ +#define CTBM_V2_OA1_SLOPE_OFFSET_TRIM_OA1_SLOPE_OFFSET_TRIM_Pos 0UL +#define CTBM_V2_OA1_SLOPE_OFFSET_TRIM_OA1_SLOPE_OFFSET_TRIM_Msk 0x3FUL +/* CTBM.OA1_COMP_TRIM */ +#define CTBM_V2_OA1_COMP_TRIM_OA1_COMP_TRIM_Pos 0UL +#define CTBM_V2_OA1_COMP_TRIM_OA1_COMP_TRIM_Msk 0x3UL #endif /* _CYIP_CTBM_V2_H_ */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_efuse.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_efuse.h index 5ca86eec26..9cf8bf4bc5 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_efuse.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_efuse.h @@ -5,11 +5,11 @@ * EFUSE IP definitions * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_pass_v2.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_pass_v2.h index 6acc9cab3e..4dae9ca13b 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_pass_v2.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_pass_v2.h @@ -5,7 +5,7 @@ * PASS IP definitions * * \note -* Generator version: 1.6.0.111 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -44,9 +44,9 @@ * \brief Programmable Analog Subsystem (PASS_TIMER) */ typedef struct { - __IOM uint32_t CTRL; /*!< 0x00000000 Timer control register */ - __IOM uint32_t CONFIG; /*!< 0x00000004 Timer configuration register */ - __IOM uint32_t TIMER_PERIOD; /*!< 0x00000008 Timer period register */ + __IOM uint32_t CTRL; /*!< 0x00000000 Timer trigger control register */ + __IOM uint32_t CONFIG; /*!< 0x00000004 Timer trigger configuration register */ + __IOM uint32_t PERIOD; /*!< 0x00000008 Timer trigger period register */ __IM uint32_t RESERVED[61]; } PASS_TIMER_V2_Type; /*!< Size = 256 (0x100) */ @@ -56,7 +56,7 @@ typedef struct { typedef struct { __IOM uint32_t CTRL; /*!< 0x00000000 Low Power Oscillator control */ __IOM uint32_t CONFIG; /*!< 0x00000004 Low Power Oscillator configuration register */ - __IOM uint32_t ADFT; /*!< 0x00000008 Retention */ + __IOM uint32_t ADFT; /*!< 0x00000008 Retention, Hidden */ __IM uint32_t RESERVED[61]; } PASS_LPOSC_V2_Type; /*!< Size = 256 (0x100) */ @@ -94,7 +94,7 @@ typedef struct { __IM uint32_t INTR_CAUSE; /*!< 0x00000000 Interrupt cause register */ __IM uint32_t RESERVED[3]; __IOM uint32_t DPSLP_CLOCK_SEL; /*!< 0x00000010 Deepsleep clock select */ - __IOM uint32_t PWR_WAKE_CTRL; /*!< 0x00000014 Deepsleep wakeup control */ + __IOM uint32_t ANA_PWR_CFG; /*!< 0x00000014 Analog power configuration */ __IM uint32_t RESERVED1[2]; __IOM uint32_t CTBM_CLOCK_SEL; /*!< 0x00000020 Clock select for CTBm */ __IM uint32_t RESERVED2[3]; @@ -132,9 +132,9 @@ typedef struct { /* PASS_TIMER.CONFIG */ #define PASS_TIMER_V2_CONFIG_CLOCK_SEL_Pos 0UL #define PASS_TIMER_V2_CONFIG_CLOCK_SEL_Msk 0x3UL -/* PASS_TIMER.TIMER_PERIOD */ -#define PASS_TIMER_V2_TIMER_PERIOD_PER_VAL_Pos 0UL -#define PASS_TIMER_V2_TIMER_PERIOD_PER_VAL_Msk 0xFFFFUL +/* PASS_TIMER.PERIOD */ +#define PASS_TIMER_V2_PERIOD_PER_VAL_Pos 0UL +#define PASS_TIMER_V2_PERIOD_PER_VAL_Msk 0xFFFFUL /* PASS_LPOSC.CTRL */ @@ -156,8 +156,8 @@ typedef struct { #define PASS_FIFO_V2_CONFIG_CHAN_ID_EN_Msk 0x1UL #define PASS_FIFO_V2_CONFIG_CHAIN_TO_NXT_Pos 1UL #define PASS_FIFO_V2_CONFIG_CHAIN_TO_NXT_Msk 0x2UL -#define PASS_FIFO_V2_CONFIG_TR_CLR_RD_EN_Pos 2UL -#define PASS_FIFO_V2_CONFIG_TR_CLR_RD_EN_Msk 0x4UL +#define PASS_FIFO_V2_CONFIG_TR_INTR_CLR_RD_EN_Pos 2UL +#define PASS_FIFO_V2_CONFIG_TR_INTR_CLR_RD_EN_Msk 0x4UL /* PASS_FIFO.CLEAR */ #define PASS_FIFO_V2_CLEAR_CLEAR_Pos 0UL #define PASS_FIFO_V2_CLEAR_CLEAR_Msk 0x1UL @@ -270,9 +270,11 @@ typedef struct { #define PASS_V2_DPSLP_CLOCK_SEL_DPSLP_CLOCK_SEL_Msk 0x1UL #define PASS_V2_DPSLP_CLOCK_SEL_DPSLP_CLOCK_DIV_Pos 4UL #define PASS_V2_DPSLP_CLOCK_SEL_DPSLP_CLOCK_DIV_Msk 0x70UL -/* PASS.PWR_WAKE_CTRL */ -#define PASS_V2_PWR_WAKE_CTRL_WAKE_DELAY_Pos 0UL -#define PASS_V2_PWR_WAKE_CTRL_WAKE_DELAY_Msk 0x3FUL +/* PASS.ANA_PWR_CFG */ +#define PASS_V2_ANA_PWR_CFG_PWR_UP_DELAY_Pos 0UL +#define PASS_V2_ANA_PWR_CFG_PWR_UP_DELAY_Msk 0xFFUL +#define PASS_V2_ANA_PWR_CFG_DUTY_CYCLE_SAR_ACT_EN_Pos 8UL +#define PASS_V2_ANA_PWR_CFG_DUTY_CYCLE_SAR_ACT_EN_Msk 0xF00UL /* PASS.CTBM_CLOCK_SEL */ #define PASS_V2_CTBM_CLOCK_SEL_PUMP_CLOCK_SEL_Pos 0UL #define PASS_V2_CTBM_CLOCK_SEL_PUMP_CLOCK_SEL_Msk 0x1UL diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_sar_v2.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_sar_v2.h index 40d096bbeb..8296082ec1 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_sar_v2.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_sar_v2.h @@ -5,11 +5,11 @@ * SAR IP definitions * * \note -* Generator version: 1.5.1.36 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -73,13 +73,17 @@ typedef struct { __IOM uint32_t RANGE_INTR_MASK; /*!< 0x00000238 Range detect interrupt mask register. */ __IM uint32_t RANGE_INTR_MASKED; /*!< 0x0000023C Range interrupt masked request register */ __IM uint32_t INTR_CAUSE; /*!< 0x00000240 Interrupt cause register */ - __IM uint32_t RESERVED5[23]; + __IM uint32_t RESERVED5[15]; + __IOM uint32_t INJ_CHAN_CONFIG; /*!< 0x00000280 Injection channel configuration register. */ + __IM uint32_t RESERVED6[3]; + __IM uint32_t INJ_RESULT; /*!< 0x00000290 Injection channel result register */ + __IM uint32_t RESERVED7[3]; __IM uint32_t STATUS; /*!< 0x000002A0 Current status of internal SAR registers (mostly for debug) */ __IM uint32_t AVG_STAT; /*!< 0x000002A4 Current averaging status (for debug) */ - __IM uint32_t RESERVED6[22]; + __IM uint32_t RESERVED8[22]; __IOM uint32_t MUX_SWITCH0; /*!< 0x00000300 SARMUX Firmware switch controls */ __IOM uint32_t MUX_SWITCH_CLEAR0; /*!< 0x00000304 SARMUX Firmware switch control clear */ - __IM uint32_t RESERVED7[15]; + __IM uint32_t RESERVED9[15]; __IOM uint32_t MUX_SWITCH_SQ_CTRL; /*!< 0x00000344 SARMUX switch Sar Sequencer control */ __IM uint32_t MUX_SWITCH_STATUS; /*!< 0x00000348 SARMUX switch status */ } SAR_V2_Type; /*!< Size = 844 (0x34C) */ @@ -337,6 +341,34 @@ typedef struct { #define SAR_V2_INTR_CAUSE_SATURATE_MASKED_RED_Msk 0x40000000UL #define SAR_V2_INTR_CAUSE_RANGE_MASKED_RED_Pos 31UL #define SAR_V2_INTR_CAUSE_RANGE_MASKED_RED_Msk 0x80000000UL +/* SAR.INJ_CHAN_CONFIG */ +#define SAR_V2_INJ_CHAN_CONFIG_INJ_PIN_ADDR_Pos 0UL +#define SAR_V2_INJ_CHAN_CONFIG_INJ_PIN_ADDR_Msk 0x7UL +#define SAR_V2_INJ_CHAN_CONFIG_INJ_PORT_ADDR_Pos 4UL +#define SAR_V2_INJ_CHAN_CONFIG_INJ_PORT_ADDR_Msk 0x70UL +#define SAR_V2_INJ_CHAN_CONFIG_INJ_DIFFERENTIAL_EN_Pos 8UL +#define SAR_V2_INJ_CHAN_CONFIG_INJ_DIFFERENTIAL_EN_Msk 0x100UL +#define SAR_V2_INJ_CHAN_CONFIG_INJ_AVG_EN_Pos 10UL +#define SAR_V2_INJ_CHAN_CONFIG_INJ_AVG_EN_Msk 0x400UL +#define SAR_V2_INJ_CHAN_CONFIG_INJ_SAMPLE_TIME_SEL_Pos 12UL +#define SAR_V2_INJ_CHAN_CONFIG_INJ_SAMPLE_TIME_SEL_Msk 0x3000UL +#define SAR_V2_INJ_CHAN_CONFIG_INJ_TAILGATING_Pos 30UL +#define SAR_V2_INJ_CHAN_CONFIG_INJ_TAILGATING_Msk 0x40000000UL +#define SAR_V2_INJ_CHAN_CONFIG_INJ_START_EN_Pos 31UL +#define SAR_V2_INJ_CHAN_CONFIG_INJ_START_EN_Msk 0x80000000UL +/* SAR.INJ_RESULT */ +#define SAR_V2_INJ_RESULT_INJ_RESULT_Pos 0UL +#define SAR_V2_INJ_RESULT_INJ_RESULT_Msk 0xFFFFUL +#define SAR_V2_INJ_RESULT_INJ_NEWVALUE_Pos 27UL +#define SAR_V2_INJ_RESULT_INJ_NEWVALUE_Msk 0x8000000UL +#define SAR_V2_INJ_RESULT_INJ_COLLISION_INTR_MIR_Pos 28UL +#define SAR_V2_INJ_RESULT_INJ_COLLISION_INTR_MIR_Msk 0x10000000UL +#define SAR_V2_INJ_RESULT_INJ_SATURATE_INTR_MIR_Pos 29UL +#define SAR_V2_INJ_RESULT_INJ_SATURATE_INTR_MIR_Msk 0x20000000UL +#define SAR_V2_INJ_RESULT_INJ_RANGE_INTR_MIR_Pos 30UL +#define SAR_V2_INJ_RESULT_INJ_RANGE_INTR_MIR_Msk 0x40000000UL +#define SAR_V2_INJ_RESULT_INJ_EOC_INTR_MIR_Pos 31UL +#define SAR_V2_INJ_RESULT_INJ_EOC_INTR_MIR_Msk 0x80000000UL /* SAR.STATUS */ #define SAR_V2_STATUS_CUR_CHAN_Pos 0UL #define SAR_V2_STATUS_CUR_CHAN_Msk 0x1FUL diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_sflash.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_sflash.h index cb25d51364..212ce16816 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_sflash.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_sflash.h @@ -5,7 +5,7 @@ * SFLASH IP definitions * * \note -* Generator version: 1.6.0.111 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -47,18 +47,11 @@ typedef struct { __IOM uint16_t FAMILY_ID; /*!< 0x0000000C Indicates Family ID of the device */ __IM uint16_t RESERVED2[3]; __IOM uint32_t CPUSS_WOUNDING; /*!< 0x00000014 CPUSS Wounding */ - __IM uint32_t RESERVED3[2]; - __IOM uint8_t S1_TESTPGM_REV; /*!< 0x00000020 S1_testpgm_rev */ - __IOM uint8_t S2_TESTPGM_REV; /*!< 0x00000021 S2_testpgm_rev */ - __IOM uint8_t S3_TESTPGM_REV; /*!< 0x00000022 S3_testpgm_rev */ - __IOM uint8_t CRI_TESTPGM_REV; /*!< 0x00000023 CRI_testpgm_rev */ - __IOM uint8_t CRI_AB_REV; /*!< 0x00000024 CRI AB Revision */ - __IOM uint8_t CHI_TESTPGM_REV; /*!< 0x00000025 CHI_testpgm_rev */ - __IM uint16_t RESERVED4; + __IM uint32_t RESERVED3[4]; __IOM uint32_t SFLASH_SVN; /*!< 0x00000028 SFLASH Subversion */ - __IM uint32_t RESERVED5[20]; + __IM uint32_t RESERVED4[20]; __IOM uint32_t FB_FLAGS; /*!< 0x0000007C Flash boot flags */ - __IM uint32_t RESERVED6[352]; + __IM uint32_t RESERVED5[352]; __IOM uint8_t DIE_LOT[3]; /*!< 0x00000600 Lot Number (3 bytes) */ __IOM uint8_t DIE_WAFER; /*!< 0x00000603 Wafer Number */ __IOM uint8_t DIE_X; /*!< 0x00000604 X Position on Wafer, CRI Pass/Fail Bin */ @@ -68,20 +61,20 @@ typedef struct { __IOM uint8_t DIE_DAY; /*!< 0x00000608 Day number */ __IOM uint8_t DIE_MONTH; /*!< 0x00000609 Month number */ __IOM uint8_t DIE_YEAR; /*!< 0x0000060A Year number */ - __IM uint8_t RESERVED7[61]; + __IM uint8_t RESERVED6[61]; __IOM uint16_t SAR_TEMP_MULTIPLIER; /*!< 0x00000648 SAR Temperature Sensor Multiplication Factor */ __IOM uint16_t SAR_TEMP_OFFSET; /*!< 0x0000064A SAR Temperature Sensor Offset */ - __IM uint32_t RESERVED8[8]; + __IM uint32_t RESERVED7[8]; __IOM uint32_t CSP_PANEL_ID; /*!< 0x0000066C CSP Panel Id to record panel ID of CSP die */ - __IM uint32_t RESERVED9[52]; + __IM uint32_t RESERVED8[52]; __IOM uint8_t LDO_0P9V_TRIM; /*!< 0x00000740 LDO_0P9V_TRIM */ __IOM uint8_t LDO_1P1V_TRIM; /*!< 0x00000741 LDO_1P1V_TRIM */ - __IM uint16_t RESERVED10[95]; + __IM uint16_t RESERVED9[95]; __IOM uint32_t BLE_DEVICE_ADDRESS[128]; /*!< 0x00000800 BLE_DEVICE_ADDRESS */ __IOM uint32_t USER_FREE_ROW1[128]; /*!< 0x00000A00 USER_FREE_ROW1 */ __IOM uint32_t USER_FREE_ROW2[128]; /*!< 0x00000C00 USER_FREE_ROW2 */ __IOM uint32_t USER_FREE_ROW3[128]; /*!< 0x00000E00 USER_FREE_ROW3 */ - __IM uint32_t RESERVED11[302]; + __IM uint32_t RESERVED10[302]; __IOM uint8_t DEVICE_UID[16]; /*!< 0x000014B8 Unique Identifier Number for each device */ __IOM uint8_t MASTER_KEY[16]; /*!< 0x000014C8 Master key to change other keys */ __IOM uint32_t STANDARD_SMPU_STRUCT_SLAVE_ADDR[16]; /*!< 0x000014D8 Standard SMPU STRUCT Slave Address value */ @@ -89,36 +82,36 @@ typedef struct { __IOM uint32_t STANDARD_SMPU_STRUCT_MASTER_ATTR[16]; /*!< 0x00001558 Standard SMPU STRUCT Master Attribute value */ __IOM uint32_t STANDARD_MPU_STRUCT[16]; /*!< 0x00001598 Standard MPU STRUCT */ __IOM uint32_t STANDARD_PPU_STRUCT[16]; /*!< 0x000015D8 Standard PPU STRUCT */ - __IM uint32_t RESERVED12[122]; + __IM uint32_t RESERVED11[122]; __IOM uint16_t PILO_FREQ_STEP; /*!< 0x00001800 Resolution step for PILO at class in BCD format */ - __IM uint16_t RESERVED13; + __IM uint16_t RESERVED12; __IOM uint32_t CSDV2_CSD0_ADC_VREF0; /*!< 0x00001804 CSD 1p2 & 1p6 voltage levels for accuracy */ __IOM uint32_t CSDV2_CSD0_ADC_VREF1; /*!< 0x00001808 CSD 2p1 & 0p8 voltage levels for accuracy */ __IOM uint32_t CSDV2_CSD0_ADC_VREF2; /*!< 0x0000180C CSD calibration spare voltage level for accuracy */ __IOM uint32_t PWR_TRIM_WAKE_CTL; /*!< 0x00001810 Wakeup delay */ - __IM uint16_t RESERVED14; + __IM uint16_t RESERVED13; __IOM uint16_t RADIO_LDO_TRIMS; /*!< 0x00001816 Radio LDO Trims */ __IOM uint32_t CPUSS_TRIM_ROM_CTL_ULP; /*!< 0x00001818 CPUSS TRIM ROM CTL ULP value */ __IOM uint32_t CPUSS_TRIM_RAM_CTL_ULP; /*!< 0x0000181C CPUSS TRIM RAM CTL ULP value */ __IOM uint32_t CPUSS_TRIM_ROM_CTL_LP; /*!< 0x00001820 CPUSS TRIM ROM CTL LP value */ __IOM uint32_t CPUSS_TRIM_RAM_CTL_LP; /*!< 0x00001824 CPUSS TRIM RAM CTL LP value */ - __IM uint32_t RESERVED15[7]; + __IM uint32_t RESERVED14[7]; __IOM uint32_t CPUSS_TRIM_ROM_CTL_HALF_ULP; /*!< 0x00001844 CPUSS TRIM ROM CTL HALF ULP value */ __IOM uint32_t CPUSS_TRIM_RAM_CTL_HALF_ULP; /*!< 0x00001848 CPUSS TRIM RAM CTL HALF ULP value */ __IOM uint32_t CPUSS_TRIM_ROM_CTL_HALF_LP; /*!< 0x0000184C CPUSS TRIM ROM CTL HALF LP value */ __IOM uint32_t CPUSS_TRIM_RAM_CTL_HALF_LP; /*!< 0x00001850 CPUSS TRIM RAM CTL HALF LP value */ - __IM uint32_t RESERVED16[491]; + __IM uint32_t RESERVED15[491]; __IOM uint32_t FLASH_BOOT_OBJECT_SIZE; /*!< 0x00002000 Flash Boot - Object Size */ __IOM uint32_t FLASH_BOOT_APP_ID; /*!< 0x00002004 Flash Boot - Application ID/Version */ __IOM uint32_t FLASH_BOOT_ATTRIBUTE; /*!< 0x00002008 N/A */ __IOM uint32_t FLASH_BOOT_N_CORES; /*!< 0x0000200C Flash Boot - Number of Cores(N) */ __IOM uint32_t FLASH_BOOT_VT_OFFSET; /*!< 0x00002010 Flash Boot - Core Vector Table offset */ __IOM uint32_t FLASH_BOOT_CORE_CPUID; /*!< 0x00002014 Flash Boot - Core CPU ID/Core Index */ - __IM uint32_t RESERVED17[48]; + __IM uint32_t RESERVED16[48]; __IOM uint8_t FLASH_BOOT_CODE[14632]; /*!< 0x000020D8 Flash Boot - Code and Data */ __IOM uint8_t PUBLIC_KEY[3072]; /*!< 0x00005A00 Public key for signature verification (max RSA key size 4096) */ __IOM uint32_t BOOT_PROT_SETTINGS[384]; /*!< 0x00006600 Boot protection settings (not present in PSOC6ABLE2) */ - __IM uint32_t RESERVED18[768]; + __IM uint32_t RESERVED17[768]; __IOM uint32_t TOC1_OBJECT_SIZE; /*!< 0x00007800 Object size in bytes for CRC calculation starting from offset 0x00 */ __IOM uint32_t TOC1_MAGIC_NUMBER; /*!< 0x00007804 Magic number(0x01211219) */ @@ -129,7 +122,7 @@ typedef struct { __IOM uint32_t TOC1_FB_OBJECT_ADDR; /*!< 0x00007814 Addresss of FLASH Boot(FB) object that include FLASH patch also */ __IOM uint32_t TOC1_SYSCALL_TABLE_ADDR_UNUSED; /*!< 0x00007818 Unused (Address is Hardcoded in ROM) */ __IOM uint32_t TOC1_OBJECT_ADDR_UNUSED; /*!< 0x0000781C Unused (Address is Hardcoded in ROM) */ - __IM uint32_t RESERVED19[119]; + __IM uint32_t RESERVED18[119]; __IOM uint32_t TOC1_CRC_ADDR; /*!< 0x000079FC Upper 2 bytes contain CRC16-CCITT and lower 2 bytes are 0 */ __IOM uint32_t RTOC1_OBJECT_SIZE; /*!< 0x00007A00 Redundant Object size in bytes for CRC calculation starting from offset 0x00 */ @@ -142,7 +135,7 @@ typedef struct { patch also */ __IOM uint32_t RTOC1_SYSCALL_TABLE_ADDR_UNUSED; /*!< 0x00007A18 Redundant Unused (Address is Hardcoded in ROM) */ __IOM uint32_t RTOC1_OBJECT_ADDR_UNUSED; /*!< 0x00007A1C Redundant Unused (Address is Hardcoded in ROM) */ - __IM uint32_t RESERVED20[119]; + __IM uint32_t RESERVED19[119]; __IOM uint32_t RTOC1_CRC_ADDR; /*!< 0x00007BFC Redundant CRC,Upper 2 bytes contain CRC16-CCITT and lower 2 bytes are 0 */ __IOM uint32_t TOC2_OBJECT_SIZE; /*!< 0x00007C00 Object size in bytes for CRC calculation starting from offset @@ -162,7 +155,7 @@ typedef struct { SECURE_HASH(SHASH) */ __IOM uint32_t TOC2_SIGNATURE_VERIF_KEY; /*!< 0x00007C24 Address of signature verification key (0 if none).The object is signature specific key. It is the public key in case of RSA */ - __IM uint32_t RESERVED21[115]; + __IM uint32_t RESERVED20[115]; __IOM uint32_t TOC2_REVISION; /*!< 0x00007DF4 Indicates TOC2 Revision. It is not used now. */ __IOM uint32_t TOC2_FLAGS; /*!< 0x00007DF8 TOC2_FLAGS */ __IOM uint32_t TOC2_CRC_ADDR; /*!< 0x00007DFC CRC,Upper 2 bytes contain CRC16-CCITT and lower 2 bytes are 0 */ @@ -184,7 +177,7 @@ typedef struct { __IOM uint32_t RTOC2_SIGNATURE_VERIF_KEY; /*!< 0x00007E24 Redundant Address of signature verification key (0 if none).The object is signature specific key. It is the public key in case of RSA */ - __IM uint32_t RESERVED22[115]; + __IM uint32_t RESERVED21[115]; __IOM uint32_t RTOC2_REVISION; /*!< 0x00007FF4 Indicates RTOC2 Revision. It is not used now. */ __IOM uint32_t RTOC2_FLAGS; /*!< 0x00007FF8 RTOC2_FLAGS */ __IOM uint32_t RTOC2_CRC_ADDR; /*!< 0x00007FFC Redundant CRC,Upper 2 bytes contain CRC16-CCITT and lower 2 @@ -204,24 +197,6 @@ typedef struct { /* SFLASH.CPUSS_WOUNDING */ #define SFLASH_CPUSS_WOUNDING_CPUSS_WOUNDING_Pos 0UL #define SFLASH_CPUSS_WOUNDING_CPUSS_WOUNDING_Msk 0xFFFFFFFFUL -/* SFLASH.S1_TESTPGM_REV */ -#define SFLASH_S1_TESTPGM_REV_DATA_Pos 0UL -#define SFLASH_S1_TESTPGM_REV_DATA_Msk 0xFFUL -/* SFLASH.S2_TESTPGM_REV */ -#define SFLASH_S2_TESTPGM_REV_DATA_Pos 0UL -#define SFLASH_S2_TESTPGM_REV_DATA_Msk 0xFFUL -/* SFLASH.S3_TESTPGM_REV */ -#define SFLASH_S3_TESTPGM_REV_DATA_Pos 0UL -#define SFLASH_S3_TESTPGM_REV_DATA_Msk 0xFFUL -/* SFLASH.CRI_TESTPGM_REV */ -#define SFLASH_CRI_TESTPGM_REV_DATA_Pos 0UL -#define SFLASH_CRI_TESTPGM_REV_DATA_Msk 0xFFUL -/* SFLASH.CRI_AB_REV */ -#define SFLASH_CRI_AB_REV_DATA_Pos 0UL -#define SFLASH_CRI_AB_REV_DATA_Msk 0xFFUL -/* SFLASH.CHI_TESTPGM_REV */ -#define SFLASH_CHI_TESTPGM_REV_DATA_Pos 0UL -#define SFLASH_CHI_TESTPGM_REV_DATA_Msk 0xFFUL /* SFLASH.SFLASH_SVN */ #define SFLASH_SFLASH_SVN_DATA32_Pos 0UL #define SFLASH_SFLASH_SVN_DATA32_Msk 0xFFFFFFFFUL diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/psoc6_01_config.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/psoc6_01_config.h index 321f0398b4..2a3783af52 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/psoc6_01_config.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/psoc6_01_config.h @@ -5,11 +5,11 @@ * PSoC6_01 device configuration header * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -1405,39 +1405,22 @@ typedef enum } en_trig_type_t; /* Trigger Type Defines */ -/* TCPWM Trigger Types */ -#define TRIGGER_TYPE_TCPWM_LINE TRIGGER_TYPE_LEVEL -#define TRIGGER_TYPE_TCPWM_LINE_COMPL TRIGGER_TYPE_LEVEL -#define TRIGGER_TYPE_TCPWM_TR_IN__LEVEL TRIGGER_TYPE_LEVEL -#define TRIGGER_TYPE_TCPWM_TR_IN__EDGE TRIGGER_TYPE_EDGE -#define TRIGGER_TYPE_TCPWM_TR_OVERFLOW TRIGGER_TYPE_EDGE -#define TRIGGER_TYPE_TCPWM_TR_COMPARE_MATCH TRIGGER_TYPE_EDGE -#define TRIGGER_TYPE_TCPWM_TR_UNDERFLOW TRIGGER_TYPE_EDGE -/* CSD Trigger Types */ -#define TRIGGER_TYPE_CSD_DSI_SAMPLE_OUT TRIGGER_TYPE_EDGE -/* SCB Trigger Types */ -#define TRIGGER_TYPE_SCB_TR_TX_REQ TRIGGER_TYPE_LEVEL -#define TRIGGER_TYPE_SCB_TR_RX_REQ TRIGGER_TYPE_LEVEL -#define TRIGGER_TYPE_SCB_TR_I2C_SCL_FILTERED TRIGGER_TYPE_LEVEL -/* PERI Trigger Types */ -#define TRIGGER_TYPE_PERI_TR_IO_INPUT__LEVEL TRIGGER_TYPE_LEVEL -#define TRIGGER_TYPE_PERI_TR_IO_INPUT__EDGE TRIGGER_TYPE_EDGE -#define TRIGGER_TYPE_PERI_TR_IO_OUTPUT__LEVEL TRIGGER_TYPE_LEVEL -#define TRIGGER_TYPE_PERI_TR_IO_OUTPUT__EDGE TRIGGER_TYPE_EDGE +/* AUDIOSS Trigger Types */ +#define TRIGGER_TYPE_AUDIOSS_TR_I2S_RX_REQ TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_AUDIOSS_TR_I2S_TX_REQ TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_AUDIOSS_TR_PDM_RX_REQ TRIGGER_TYPE_LEVEL /* CPUSS Trigger Types */ +#define TRIGGER_TYPE_CPUSS_CTI_TR_IN TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_CPUSS_CTI_TR_OUT TRIGGER_TYPE_EDGE #define TRIGGER_TYPE_CPUSS_DW0_TR_IN__LEVEL TRIGGER_TYPE_LEVEL #define TRIGGER_TYPE_CPUSS_DW0_TR_IN__EDGE TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_CPUSS_DW0_TR_OUT TRIGGER_TYPE_EDGE #define TRIGGER_TYPE_CPUSS_DW1_TR_IN__LEVEL TRIGGER_TYPE_LEVEL #define TRIGGER_TYPE_CPUSS_DW1_TR_IN__EDGE TRIGGER_TYPE_EDGE -#define TRIGGER_TYPE_CPUSS_CTI_TR_IN TRIGGER_TYPE_EDGE -#define TRIGGER_TYPE_CPUSS_DW0_TR_OUT TRIGGER_TYPE_EDGE #define TRIGGER_TYPE_CPUSS_DW1_TR_OUT TRIGGER_TYPE_EDGE -#define TRIGGER_TYPE_CPUSS_CTI_TR_OUT TRIGGER_TYPE_EDGE #define TRIGGER_TYPE_CPUSS_TR_FAULT TRIGGER_TYPE_EDGE -/* AUDIOSS Trigger Types */ -#define TRIGGER_TYPE_AUDIOSS_TR_PDM_RX_REQ TRIGGER_TYPE_LEVEL -#define TRIGGER_TYPE_AUDIOSS_TR_I2S_TX_REQ TRIGGER_TYPE_LEVEL -#define TRIGGER_TYPE_AUDIOSS_TR_I2S_RX_REQ TRIGGER_TYPE_LEVEL +/* CSD Trigger Types */ +#define TRIGGER_TYPE_CSD_DSI_SAMPLE_OUT TRIGGER_TYPE_EDGE /* LPCOMP Trigger Types */ #define TRIGGER_TYPE_LPCOMP_DSI_COMP0 TRIGGER_TYPE_LEVEL #define TRIGGER_TYPE_LPCOMP_DSI_COMP1 TRIGGER_TYPE_LEVEL @@ -1446,33 +1429,50 @@ typedef enum #define TRIGGER_TYPE_PASS_DSI_CTB_CMP0__EDGE TRIGGER_TYPE_EDGE #define TRIGGER_TYPE_PASS_DSI_CTB_CMP1__LEVEL TRIGGER_TYPE_LEVEL #define TRIGGER_TYPE_PASS_DSI_CTB_CMP1__EDGE TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_PASS_TR_CTDAC_EMPTY TRIGGER_TYPE_EDGE #define TRIGGER_TYPE_PASS_TR_SAR_IN__LEVEL TRIGGER_TYPE_LEVEL #define TRIGGER_TYPE_PASS_TR_SAR_IN__EDGE TRIGGER_TYPE_EDGE #define TRIGGER_TYPE_PASS_TR_SAR_OUT TRIGGER_TYPE_EDGE -#define TRIGGER_TYPE_PASS_TR_CTDAC_EMPTY TRIGGER_TYPE_EDGE -/* SMIF Trigger Types */ -#define TRIGGER_TYPE_SMIF_TR_TX_REQ TRIGGER_TYPE_LEVEL -#define TRIGGER_TYPE_SMIF_TR_RX_REQ TRIGGER_TYPE_LEVEL -/* USB Trigger Types */ -#define TRIGGER_TYPE_USB_DMA_BURSTEND TRIGGER_TYPE_EDGE -#define TRIGGER_TYPE_USB_DMA_REQ TRIGGER_TYPE_EDGE -/* UDB Trigger Types */ -#define TRIGGER_TYPE_UDB_TR_IN__LEVEL TRIGGER_TYPE_LEVEL -#define TRIGGER_TYPE_UDB_TR_IN__EDGE TRIGGER_TYPE_EDGE -#define TRIGGER_TYPE_UDB_TR_DW_ACK__LEVEL TRIGGER_TYPE_LEVEL -#define TRIGGER_TYPE_UDB_TR_DW_ACK__EDGE TRIGGER_TYPE_EDGE -#define TRIGGER_TYPE_UDB_TR_UDB__LEVEL TRIGGER_TYPE_LEVEL -#define TRIGGER_TYPE_UDB_TR_UDB__EDGE TRIGGER_TYPE_EDGE -#define TRIGGER_TYPE_UDB_DSI_OUT_TR__LEVEL TRIGGER_TYPE_LEVEL -#define TRIGGER_TYPE_UDB_DSI_OUT_TR__EDGE TRIGGER_TYPE_EDGE +/* PERI Trigger Types */ +#define TRIGGER_TYPE_PERI_TR_IO_INPUT__LEVEL TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_PERI_TR_IO_INPUT__EDGE TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_PERI_TR_IO_OUTPUT__LEVEL TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_PERI_TR_IO_OUTPUT__EDGE TRIGGER_TYPE_EDGE /* PROFILE Trigger Types */ #define TRIGGER_TYPE_PROFILE_TR_START TRIGGER_TYPE_EDGE #define TRIGGER_TYPE_PROFILE_TR_STOP TRIGGER_TYPE_EDGE +/* SCB Trigger Types */ +#define TRIGGER_TYPE_SCB_TR_I2C_SCL_FILTERED TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_SCB_TR_RX_REQ TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_SCB_TR_TX_REQ TRIGGER_TYPE_LEVEL +/* SMIF Trigger Types */ +#define TRIGGER_TYPE_SMIF_TR_RX_REQ TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_SMIF_TR_TX_REQ TRIGGER_TYPE_LEVEL +/* TCPWM Trigger Types */ +#define TRIGGER_TYPE_TCPWM_LINE TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_TCPWM_LINE_COMPL TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_TCPWM_TR_COMPARE_MATCH TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_TCPWM_TR_IN__LEVEL TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_TCPWM_TR_IN__EDGE TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_TCPWM_TR_OVERFLOW TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_TCPWM_TR_UNDERFLOW TRIGGER_TYPE_EDGE /* TR_GROUP Trigger Types */ -#define TRIGGER_TYPE_TR_GROUP_OUTPUT__LEVEL TRIGGER_TYPE_LEVEL -#define TRIGGER_TYPE_TR_GROUP_OUTPUT__EDGE TRIGGER_TYPE_EDGE #define TRIGGER_TYPE_TR_GROUP_INPUT__LEVEL TRIGGER_TYPE_LEVEL #define TRIGGER_TYPE_TR_GROUP_INPUT__EDGE TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_TR_GROUP_OUTPUT__LEVEL TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_TR_GROUP_OUTPUT__EDGE TRIGGER_TYPE_EDGE +/* UDB Trigger Types */ +#define TRIGGER_TYPE_UDB_DSI_OUT_TR__LEVEL TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_UDB_DSI_OUT_TR__EDGE TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_UDB_TR_DW_ACK__LEVEL TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_UDB_TR_DW_ACK__EDGE TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_UDB_TR_IN__LEVEL TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_UDB_TR_IN__EDGE TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_UDB_TR_UDB__LEVEL TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_UDB_TR_UDB__EDGE TRIGGER_TYPE_EDGE +/* USB Trigger Types */ +#define TRIGGER_TYPE_USB_DMA_BURSTEND TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_USB_DMA_REQ TRIGGER_TYPE_EDGE /* Monitor Signal Defines */ typedef enum @@ -1631,75 +1631,186 @@ typedef I2S_V1_Type I2S_Type; typedef PDM_V1_Type PDM_Type; /* Parameter Defines */ -/* Number of regulator modules instantiated within SRSS */ -#define SRSS_NUM_ACTREG_PWRMOD 2u -/* Number of shorting switches between vccd and vccact */ -#define SRSS_NUM_ACTIVE_SWITCH 3u -/* ULP linear regulator system is present */ -#define SRSS_ULPLINREG_PRESENT 1u -/* HT linear regulator system is present */ -#define SRSS_HTLINREG_PRESENT 0u -/* SIMO buck core regulator is present. Only compatible with ULP linear regulator - system (ULPLINREG_PRESENT==1). */ -#define SRSS_SIMOBUCK_PRESENT 1u -/* Precision ILO (PILO) is present */ -#define SRSS_PILO_PRESENT 1u -/* External Crystal Oscillator is present (high frequency) */ -#define SRSS_ECO_PRESENT 1u -/* System Buck-Boost is present */ -#define SRSS_SYSBB_PRESENT 0u -/* Number of clock paths. Must be > 0 */ -#define SRSS_NUM_CLKPATH 5u -/* Number of PLLs present. Must be <= NUM_CLKPATH */ -#define SRSS_NUM_PLL 1u -/* Number of HFCLK roots present. Must be > 0 */ -#define SRSS_NUM_HFROOT 5u -/* Number of PWR_HIB_DATA registers */ -#define SRSS_NUM_HIBDATA 1u -/* Backup domain is present */ -#define SRSS_BACKUP_PRESENT 1u -/* Mask of HFCLK root clock supervisors (CSV). For each clock root i, bit[i] of - mask indicates presence of a CSV. */ -#define SRSS_MASK_HFCSV 0u -/* Clock supervisor is present on WCO. Must be 0 if BACKUP_PRESENT==0. */ -#define SRSS_WCOCSV_PRESENT 0u -/* Number of software watchdog timers. */ -#define SRSS_NUM_MCWDT 2u -/* Number of DSI inputs into clock muxes. This is used for logic optimization. */ -#define SRSS_NUM_DSI 2u -/* Alternate high-frequency clock is present. This is used for logic optimization. */ -#define SRSS_ALTHF_PRESENT 1u -/* Alternate low-frequency clock is present. This is used for logic optimization. */ -#define SRSS_ALTLF_PRESENT 0u -/* Use the hardened clkactfllmux block */ -#define SRSS_USE_HARD_CLKACTFLLMUX 1u -/* Number of clock paths, including direct paths in hardened clkactfllmux block - (Must be >= NUM_CLKPATH) */ -#define SRSS_HARD_CLKPATH 6u -/* Number of clock paths with muxes in hardened clkactfllmux block (Must be >= - NUM_PLL+1) */ -#define SRSS_HARD_CLKPATHMUX 6u -/* Number of HFCLKS present in hardened clkactfllmux block (Must be >= NUM_HFROOT) */ -#define SRSS_HARD_HFROOT 6u -/* ECO mux is present in hardened clkactfllmux block (Must be >= ECO_PRESENT) */ -#define SRSS_HARD_ECOMUX_PRESENT 1u -/* ALTHF mux is present in hardened clkactfllmux block (Must be >= ALTHF_PRESENT) */ -#define SRSS_HARD_ALTHFMUX_PRESENT 1u -/* Low-current buck regulator present. Can be derived from S40S_SISOBUCKLC_PRESENT - or SIMOBUCK_PRESENT. */ -#define SRSS_BUCKCTL_PRESENT 1u -/* Low-current SISO buck core regulator is present. Only compatible with ULP - linear regulator system (ULPLINREG_PRESENT==1). */ -#define SRSS_S40S_SISOBUCKLC_PRESENT 0u -/* Backup memory is present (only used when BACKUP_PRESENT==1) */ -#define SRSS_BACKUP_BMEM_PRESENT 0u -/* Number of Backup registers to include (each is 32b). Only used when - BACKUP_PRESENT==1. */ -#define SRSS_BACKUP_NUM_BREG 16u -/* Number of AMUX splitter cells */ -#define IOSS_HSIOM_AMUX_SPLIT_NR 9u -/* Number of HSIOM ports in device (same as GPIO.GPIO_PRT_NR) */ -#define IOSS_HSIOM_HSIOM_PORT_NR 15u +/* I2S capable? (0=No,1=Yes) */ +#define AUDIOSS_I2S 1u +/* PDM capable? (0=No,1=Yes) */ +#define AUDIOSS_PDM 1u +/* UDB present or not ('0': no, '1': yes) */ +#define CPUSS_UDB_PRESENT 1u +/* System RAM 0 size in kilobytes */ +#define CPUSS_SRAM0_SIZE 288u +/* Number of macros used to implement System RAM 0. Example: 8 if 256 KB System + SRAM0 is implemented with 8 32KB macros. */ +#define CPUSS_RAMC0_MACRO_NR 9u +/* System RAM 1 present or not (0=No, 1=Yes) */ +#define CPUSS_RAMC1_PRESENT 0u +/* System RAM 1 size in kilobytes */ +#define CPUSS_SRAM1_SIZE 32u +/* Number of macros used to implement System RAM 1. Example: 8 if 256 KB System + RAM 1 is implemented with 8 32KB macros. */ +#define CPUSS_RAMC1_MACRO_NR 1u +/* System RAM 2 present or not (0=No, 1=Yes) */ +#define CPUSS_RAMC2_PRESENT 0u +/* System RAM 2 size in kilobytes */ +#define CPUSS_SRAM2_SIZE 256u +/* Number of macros used to implement System RAM 2. Example: 8 if 256 KB System + RAM 2 is implemented with 8 32KB macros. */ +#define CPUSS_RAMC2_MACRO_NR 16u +/* System ROM size in KB */ +#define CPUSS_ROM_SIZE 128u +/* Flash main region size in KB */ +#define CPUSS_FLASH_SIZE 1024u +/* Flash work region size in KB (EEPROM emulation, data) */ +#define CPUSS_WFLASH_SIZE 32u +/* Flash supervisory region size in KB */ +#define CPUSS_SFLASH_SIZE 32u +/* Flash data output size (in Bytes) */ +#define CPUSS_FLASHC_WORD_SIZE 16u +/* Flash row address width */ +#define CPUSS_FLASHC_ROW_ADDR_WIDTH 12u +/* Flash column address width */ +#define CPUSS_FLASHC_COL_ADDR_WIDTH 5u +/* Number of external slaves directly connected to slow AHB-Lite infrastructure. + Maximum nubmer of slave supported is 4. Width of this parameter is 4-bits. + 1-bit mask for each slave indicating present or not. Example: 4'b0011 - slave + 0 and slave 1 are present. Note: The SLOW_SLx_ADDR and SLOW_SLx_MASK + parameters (for the slaves present) should be derived from the Memory Map. */ +#define CPUSS_SLOW_SL_PRESENT 1u +/* Number of external slaves directly connected to fast AHB-Lite infrastructure. + Maximum nubmer of slave supported is 4. Width of this parameter is 4-bits. + 1-bit mask for each slave indicating present or not. Example: 4'b0011 - slave + 0 and slave 1 are present. Note: The FAST_SLx_ADDR and FAST_SLx_MASK + parameters (for the slaves present) should be derived from the Memory Map. */ +#define CPUSS_FAST_SL_PRESENT 1u +/* Number of external masters driving the slow AHB-Lite infrastructure. Maximum + number of masters supported is 2. Width of this parameter is 2-bits. 1-bit + mask for each master indicating present or not. Example: 2'b01 - master 0 is + present. */ +#define CPUSS_SLOW_MS_PRESENT 0u +/* Number of total interrupt request inputs to CPUSS */ +#define CPUSS_IRQ_NR 147u +/* Number of DeepSleep wakeup interrupt inputs to CPUSS */ +#define CPUSS_DPSLP_IRQ_NR 41u +/* Number of DeepSleep wakeup interrupt inputs to CM0+ (product configuration) */ +#define CPUSS_CM0_DPSLP_IRQ_NR 8u +/* Width of the CM4 interrupt priority bits. Legal range [3,8] Example: 3 = 8 + levels of priority 8 = 256 levels of priority */ +#define CPUSS_CM4_LVL_WIDTH 3u +/* CM4 Floating point unit present or not (0=No, 1=Yes) */ +#define CPUSS_CM4_FPU_PRESENT 1u +/* Debug level. Legal range [0,3] */ +#define CPUSS_DEBUG_LVL 3u +/* Trace level. Legal range [0,2] Note: CM4 HTM is not supported. Hence vaule 3 + for trace level is not supported in CPUSS. */ +#define CPUSS_TRACE_LVL 2u +/* Embedded Trace Buffer present or not (0=No, 1=Yes) */ +#define CPUSS_ETB_PRESENT 0u +/* CM0+ MTB SRAM buffer size in kilobytes. Legal vaules 4, 8 or 16 */ +#define CPUSS_MTB_SRAM_SIZE 4u +/* CM4 ETB SRAM buffer size in kilobytes. Legal vaules 4, 8 or 16 */ +#define CPUSS_ETB_SRAM_SIZE 16u +/* PTM interface present (0=No, 1=Yes) */ +#define CPUSS_PTM_PRESENT 1u +/* Width of the PTM interface in bits ([2,32]) */ +#define CPUSS_PTM_WIDTH 8u +/* Width of the TPIU interface in bits ([1,32]) */ +#define CPUSS_TPIU_WIDTH 4u +/* CoreSight Part Identification Number */ +#define CPUSS_JEPID 52u +/* CoreSight Part Identification Number */ +#define CPUSS_JEPCONTINUATION 0u +/* CoreSight Part Identification Number */ +#define CPUSS_FAMILYID 256u +/* Cryptography IP present or not (0=No, 1=Yes) */ +#define CPUSS_CRYPTO_PRESENT 1u +/* DataWire 0 present or not (0=No, 1=Yes) */ +#define CPUSS_DW0_PRESENT 1u +/* Number of DataWire 0 channels (8, 16 or 32) */ +#define CPUSS_DW0_CH_NR 16u +/* DataWire 1 present or not (0=No, 1=Yes) */ +#define CPUSS_DW1_PRESENT 1u +/* Number of DataWire 1 channels (8, 16 or 32) */ +#define CPUSS_DW1_CH_NR 16u +/* AES cipher support (0 = no support, 1 = support */ +#define CPUSS_CRYPTO_AES 1u +/* (Tripple) DES cipher support (0 = no support, 1 = support */ +#define CPUSS_CRYPTO_DES 1u +/* Pseudo random number generation support (0 = no support, 1 = support) */ +#define CPUSS_CRYPTO_PR 1u +/* SHA support included */ +#define CPUSS_CRYPTO_SHA 1u +/* SHA1 hash support (0 = no support, 1 = support) */ +#define CPUSS_CRYPTO_SHA1 1u +/* SHA256 hash support (0 = no support, 1 = support) */ +#define CPUSS_CRYPTO_SHA256 1u +/* SHA512 hash support (0 = no support, 1 = support) */ +#define CPUSS_CRYPTO_SHA512 1u +/* Cyclic Redundancy Check support (0 = no support, 1 = support) */ +#define CPUSS_CRYPTO_CRC 1u +/* Vector unit support (0 = no support, 1 = support) */ +#define CPUSS_CRYPTO_VU 1u +/* True random number generation support (0 = no support, 1 = support) */ +#define CPUSS_CRYPTO_TR 1u +/* String support (0 = no support, 1 = support) */ +#define CPUSS_CRYPTO_STR 1u +/* AHB-Lite master interface support (0 = no support, 1 = support) */ +#define CPUSS_CRYPTO_MASTER_IF 1u +/* Number of 32-bit words in the IP internal memory buffer (from the set [64, 128, + 256, 512, 1024, 2048, 4096], to allow for a 256 B, 512 B, 1 kB, 2 kB, 4 kB, 8 + kB and 16 kB memory buffer) */ +#define CPUSS_CRYPTO_BUFF_SIZE 1024u +/* Number of DataWire controllers present (max 2) */ +#define CPUSS_DW_NR 2u +/* Number of channels in each DataWire controller (must be the same for now) */ +#define CPUSS_DW_CH_NR 16u +/* Number of fault structures. Legal range [1, 4] */ +#define CPUSS_FAULT_FAULT_NR 2u +/* Number of Flash BIST_DATA registers */ +#define CPUSS_FLASHC_FLASHC_BIST_DATA_NR 4u +/* Page size in # of 32-bit words (1: 4 bytes, 2: 8 bytes, ... */ +#define CPUSS_FLASHC_PA_SIZE 128u +/* Number of IPC structures. Legal range [1, 16] */ +#define CPUSS_IPC_IPC_NR 16u +/* Number of IPC interrupt structures. Legal range [1, 16] */ +#define CPUSS_IPC_IPC_IRQ_NR 16u +/* Master 0 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS0_PC_NR_MINUS1 7u +/* Master 1 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS1_PC_NR_MINUS1 7u +/* Master 2 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS2_PC_NR_MINUS1 0u +/* Master 3 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS3_PC_NR_MINUS1 0u +/* Master 4 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS4_PC_NR_MINUS1 0u +/* Master 5 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS5_PC_NR_MINUS1 0u +/* Master 6 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS6_PC_NR_MINUS1 0u +/* Master 7 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS7_PC_NR_MINUS1 0u +/* Master 8 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS8_PC_NR_MINUS1 0u +/* Master 9 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS9_PC_NR_MINUS1 0u +/* Master 10 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS10_PC_NR_MINUS1 0u +/* Master 11 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS11_PC_NR_MINUS1 0u +/* Master 12 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS12_PC_NR_MINUS1 0u +/* Master 13 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS13_PC_NR_MINUS1 0u +/* Master 14 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS14_PC_NR_MINUS1 7u +/* Master 15 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS15_PC_NR_MINUS1 7u +/* Number of SMPU protection structures */ +#define CPUSS_PROT_SMPU_STRUCT_NR 16u +/* Number of protection contexts supported minus 1. Legal range [1,16] */ +#define CPUSS_SMPU_STRUCT_PC_NR_MINUS1 7u +/* Number of instantiated eFUSE macros (256 bit macros). Legal range [1, 16] */ +#define EFUSE_EFUSE_NR 4u /* Number of GPIO ports in range 0..31 */ #define IOSS_GPIO_GPIO_PORT_NR_0_31 15u /* Number of GPIO ports in range 32..63 */ @@ -1710,8 +1821,53 @@ typedef PDM_V1_Type PDM_Type; #define IOSS_GPIO_GPIO_PORT_NR_96_127 0u /* Number of ports in device */ #define IOSS_GPIO_GPIO_PORT_NR 15u +/* Number of AMUX splitter cells */ +#define IOSS_HSIOM_AMUX_SPLIT_NR 9u +/* Number of HSIOM ports in device (same as GPIO.GPIO_PRT_NR) */ +#define IOSS_HSIOM_HSIOM_PORT_NR 15u /* Mask of SMARTIO instances presence */ #define IOSS_SMARTIO_SMARTIO_MASK 768u +/* Number of ports supoprting up to 4 COMs */ +#define LCD_NUMPORTS 8u +/* Number of ports supporting up to 8 COMs */ +#define LCD_NUMPORTS8 8u +/* Number of ports supporting up to 16 COMs */ +#define LCD_NUMPORTS16 0u +/* Max number of LCD commons supported */ +#define LCD_CHIP_TOP_COM_NR 8u +/* Max number of LCD pins (total) supported */ +#define LCD_CHIP_TOP_PIN_NR 62u +/* Number of IREF outputs from AREF */ +#define PASS_NR_IREFS 4u +/* Number of CTBs in the Subsystem */ +#define PASS_NR_CTBS 1u +/* Number of CTDACs in the Subsystem */ +#define PASS_NR_CTDACS 1u +/* CTB0 Exists */ +#define PASS_CTB0_EXISTS 1u +/* CTB1 Exists */ +#define PASS_CTB1_EXISTS 0u +/* CTB2 Exists */ +#define PASS_CTB2_EXISTS 0u +/* CTB3 Exists */ +#define PASS_CTB3_EXISTS 0u +/* CTDAC0 Exists */ +#define PASS_CTDAC0_EXISTS 1u +/* CTDAC1 Exists */ +#define PASS_CTDAC1_EXISTS 0u +/* CTDAC2 Exists */ +#define PASS_CTDAC2_EXISTS 0u +/* CTDAC3 Exists */ +#define PASS_CTDAC3_EXISTS 0u +#define PASS_CTBM_CTDAC_PRESENT 1u +/* Number of SAR channels */ +#define PASS_SAR_SAR_CHANNELS 16u +/* Averaging logic present in SAR */ +#define PASS_SAR_SAR_AVERAGE 1u +/* Range detect logic present in SAR */ +#define PASS_SAR_SAR_RANGEDET 1u +/* Support for UAB sampling */ +#define PASS_SAR_SAR_UAB 0u /* The number of protection contexts ([2, 16]). */ #define PERI_PC_NR 8u /* Master interface presence mask (4 bits) */ @@ -2284,208 +2440,10 @@ typedef PDM_V1_Type PDM_Type; #define PERI_PPU_FIXED_STRUCT_PC_NR_MINUS1 7u /* The number of protection contexts minus 1 ([1, 15]). */ #define PERI_PPU_PROG_STRUCT_PC_NR_MINUS1 7u -/* UDB present or not ('0': no, '1': yes) */ -#define CPUSS_UDB_PRESENT 1u -/* System RAM 0 size in kilobytes */ -#define CPUSS_SRAM0_SIZE 288u -/* Number of macros used to implement System RAM 0. Example: 8 if 256 KB System - SRAM0 is implemented with 8 32KB macros. */ -#define CPUSS_RAMC0_MACRO_NR 9u -/* System RAM 1 present or not (0=No, 1=Yes) */ -#define CPUSS_RAMC1_PRESENT 0u -/* System RAM 1 size in kilobytes */ -#define CPUSS_SRAM1_SIZE 32u -/* Number of macros used to implement System RAM 1. Example: 8 if 256 KB System - RAM 1 is implemented with 8 32KB macros. */ -#define CPUSS_RAMC1_MACRO_NR 1u -/* System RAM 2 present or not (0=No, 1=Yes) */ -#define CPUSS_RAMC2_PRESENT 0u -/* System RAM 2 size in kilobytes */ -#define CPUSS_SRAM2_SIZE 256u -/* Number of macros used to implement System RAM 2. Example: 8 if 256 KB System - RAM 2 is implemented with 8 32KB macros. */ -#define CPUSS_RAMC2_MACRO_NR 16u -/* System ROM size in KB */ -#define CPUSS_ROM_SIZE 128u -/* Flash main region size in KB */ -#define CPUSS_FLASH_SIZE 1024u -/* Flash work region size in KB (EEPROM emulation, data) */ -#define CPUSS_WFLASH_SIZE 32u -/* Flash supervisory region size in KB */ -#define CPUSS_SFLASH_SIZE 32u -/* Flash data output size (in Bytes) */ -#define CPUSS_FLASHC_WORD_SIZE 16u -/* Flash row address width */ -#define CPUSS_FLASHC_ROW_ADDR_WIDTH 12u -/* Flash column address width */ -#define CPUSS_FLASHC_COL_ADDR_WIDTH 5u -/* Number of external slaves directly connected to slow AHB-Lite infrastructure. - Maximum nubmer of slave supported is 4. Width of this parameter is 4-bits. - 1-bit mask for each slave indicating present or not. Example: 4'b0011 - slave - 0 and slave 1 are present. Note: The SLOW_SLx_ADDR and SLOW_SLx_MASK - parameters (for the slaves present) should be derived from the Memory Map. */ -#define CPUSS_SLOW_SL_PRESENT 1u -/* Number of external slaves directly connected to fast AHB-Lite infrastructure. - Maximum nubmer of slave supported is 4. Width of this parameter is 4-bits. - 1-bit mask for each slave indicating present or not. Example: 4'b0011 - slave - 0 and slave 1 are present. Note: The FAST_SLx_ADDR and FAST_SLx_MASK - parameters (for the slaves present) should be derived from the Memory Map. */ -#define CPUSS_FAST_SL_PRESENT 1u -/* Number of external masters driving the slow AHB-Lite infrastructure. Maximum - number of masters supported is 2. Width of this parameter is 2-bits. 1-bit - mask for each master indicating present or not. Example: 2'b01 - master 0 is - present. */ -#define CPUSS_SLOW_MS_PRESENT 0u -/* Number of total interrupt request inputs to CPUSS */ -#define CPUSS_IRQ_NR 147u -/* Number of DeepSleep wakeup interrupt inputs to CPUSS */ -#define CPUSS_DPSLP_IRQ_NR 41u -/* Number of DeepSleep wakeup interrupt inputs to CM0+ (product configuration) */ -#define CPUSS_CM0_DPSLP_IRQ_NR 8u -/* Width of the CM4 interrupt priority bits. Legal range [3,8] Example: 3 = 8 - levels of priority 8 = 256 levels of priority */ -#define CPUSS_CM4_LVL_WIDTH 3u -/* CM4 Floating point unit present or not (0=No, 1=Yes) */ -#define CPUSS_CM4_FPU_PRESENT 1u -/* Debug level. Legal range [0,3] */ -#define CPUSS_DEBUG_LVL 3u -/* Trace level. Legal range [0,2] Note: CM4 HTM is not supported. Hence vaule 3 - for trace level is not supported in CPUSS. */ -#define CPUSS_TRACE_LVL 2u -/* Embedded Trace Buffer present or not (0=No, 1=Yes) */ -#define CPUSS_ETB_PRESENT 0u -/* CM0+ MTB SRAM buffer size in kilobytes. Legal vaules 4, 8 or 16 */ -#define CPUSS_MTB_SRAM_SIZE 4u -/* CM4 ETB SRAM buffer size in kilobytes. Legal vaules 4, 8 or 16 */ -#define CPUSS_ETB_SRAM_SIZE 16u -/* PTM interface present (0=No, 1=Yes) */ -#define CPUSS_PTM_PRESENT 1u -/* Width of the PTM interface in bits ([2,32]) */ -#define CPUSS_PTM_WIDTH 8u -/* Width of the TPIU interface in bits ([1,32]) */ -#define CPUSS_TPIU_WIDTH 4u -/* CoreSight Part Identification Number */ -#define CPUSS_JEPID 52u -/* CoreSight Part Identification Number */ -#define CPUSS_JEPCONTINUATION 0u -/* CoreSight Part Identification Number */ -#define CPUSS_FAMILYID 256u -/* Cryptography IP present or not (0=No, 1=Yes) */ -#define CPUSS_CRYPTO_PRESENT 1u -/* DataWire 0 present or not (0=No, 1=Yes) */ -#define CPUSS_DW0_PRESENT 1u -/* Number of DataWire 0 channels (8, 16 or 32) */ -#define CPUSS_DW0_CH_NR 16u -/* DataWire 1 present or not (0=No, 1=Yes) */ -#define CPUSS_DW1_PRESENT 1u -/* Number of DataWire 1 channels (8, 16 or 32) */ -#define CPUSS_DW1_CH_NR 16u -/* Number of Flash BIST_DATA registers */ -#define CPUSS_FLASHC_FLASHC_BIST_DATA_NR 4u -/* Page size in # of 32-bit words (1: 4 bytes, 2: 8 bytes, ... */ -#define CPUSS_FLASHC_PA_SIZE 128u -/* AES cipher support (0 = no support, 1 = support */ -#define CPUSS_CRYPTO_AES 1u -/* (Tripple) DES cipher support (0 = no support, 1 = support */ -#define CPUSS_CRYPTO_DES 1u -/* Pseudo random number generation support (0 = no support, 1 = support) */ -#define CPUSS_CRYPTO_PR 1u -/* SHA support included */ -#define CPUSS_CRYPTO_SHA 1u -/* SHA1 hash support (0 = no support, 1 = support) */ -#define CPUSS_CRYPTO_SHA1 1u -/* SHA256 hash support (0 = no support, 1 = support) */ -#define CPUSS_CRYPTO_SHA256 1u -/* SHA512 hash support (0 = no support, 1 = support) */ -#define CPUSS_CRYPTO_SHA512 1u -/* Cyclic Redundancy Check support (0 = no support, 1 = support) */ -#define CPUSS_CRYPTO_CRC 1u -/* Vector unit support (0 = no support, 1 = support) */ -#define CPUSS_CRYPTO_VU 1u -/* True random number generation support (0 = no support, 1 = support) */ -#define CPUSS_CRYPTO_TR 1u -/* String support (0 = no support, 1 = support) */ -#define CPUSS_CRYPTO_STR 1u -/* AHB-Lite master interface support (0 = no support, 1 = support) */ -#define CPUSS_CRYPTO_MASTER_IF 1u -/* Number of 32-bit words in the IP internal memory buffer (from the set [64, 128, - 256, 512, 1024, 2048, 4096], to allow for a 256 B, 512 B, 1 kB, 2 kB, 4 kB, 8 - kB and 16 kB memory buffer) */ -#define CPUSS_CRYPTO_BUFF_SIZE 1024u -/* Number of fault structures. Legal range [1, 4] */ -#define CPUSS_FAULT_FAULT_NR 2u -/* Number of IPC structures. Legal range [1, 16] */ -#define CPUSS_IPC_IPC_NR 16u -/* Number of IPC interrupt structures. Legal range [1, 16] */ -#define CPUSS_IPC_IPC_IRQ_NR 16u -/* Master 0 protect contexts minus one */ -#define CPUSS_PROT_SMPU_MS0_PC_NR_MINUS1 7u -/* Master 1 protect contexts minus one */ -#define CPUSS_PROT_SMPU_MS1_PC_NR_MINUS1 7u -/* Master 2 protect contexts minus one */ -#define CPUSS_PROT_SMPU_MS2_PC_NR_MINUS1 0u -/* Master 3 protect contexts minus one */ -#define CPUSS_PROT_SMPU_MS3_PC_NR_MINUS1 0u -/* Master 4 protect contexts minus one */ -#define CPUSS_PROT_SMPU_MS4_PC_NR_MINUS1 0u -/* Master 5 protect contexts minus one */ -#define CPUSS_PROT_SMPU_MS5_PC_NR_MINUS1 0u -/* Master 6 protect contexts minus one */ -#define CPUSS_PROT_SMPU_MS6_PC_NR_MINUS1 0u -/* Master 7 protect contexts minus one */ -#define CPUSS_PROT_SMPU_MS7_PC_NR_MINUS1 0u -/* Master 8 protect contexts minus one */ -#define CPUSS_PROT_SMPU_MS8_PC_NR_MINUS1 0u -/* Master 9 protect contexts minus one */ -#define CPUSS_PROT_SMPU_MS9_PC_NR_MINUS1 0u -/* Master 10 protect contexts minus one */ -#define CPUSS_PROT_SMPU_MS10_PC_NR_MINUS1 0u -/* Master 11 protect contexts minus one */ -#define CPUSS_PROT_SMPU_MS11_PC_NR_MINUS1 0u -/* Master 12 protect contexts minus one */ -#define CPUSS_PROT_SMPU_MS12_PC_NR_MINUS1 0u -/* Master 13 protect contexts minus one */ -#define CPUSS_PROT_SMPU_MS13_PC_NR_MINUS1 0u -/* Master 14 protect contexts minus one */ -#define CPUSS_PROT_SMPU_MS14_PC_NR_MINUS1 7u -/* Master 15 protect contexts minus one */ -#define CPUSS_PROT_SMPU_MS15_PC_NR_MINUS1 7u -/* Number of SMPU protection structures */ -#define CPUSS_PROT_SMPU_STRUCT_NR 16u -/* Number of protection contexts supported minus 1. Legal range [1,16] */ -#define CPUSS_SMPU_STRUCT_PC_NR_MINUS1 7u -/* Number of DataWire controllers present (max 2) */ -#define CPUSS_DW_NR 2u -/* Number of channels in each DataWire controller (must be the same for now) */ -#define CPUSS_DW_CH_NR 16u /* Number of profiling counters. Legal range [1, 32] */ #define PROFILE_PRFL_CNT_NR 8u /* Number of monitor event signals. Legal range [1, 128] */ #define PROFILE_PRFL_MONITOR_NR 128u -/* Number of instantiated eFUSE macros (256 bit macros). Legal range [1, 16] */ -#define EFUSE_EFUSE_NR 4u -/* SONOS Flash is used or not ('0': no, '1': yes) */ -#define SFLASH_FLASHC_IS_SONOS 1u -/* CPUSS_WOUNDING_PRESENT or not ('0': no, '1': yes) */ -#define SFLASH_CPUSS_WOUNDING_PRESENT 1u -/* Number of UDB Interrupts */ -#define UDB_NUMINT 16u -/* Number of triggers */ -#define UDB_NUMTR 16u -/* Number of UDB array rows (must be multiple of 2) */ -#define UDB_NUMROW 2u -/* Number of UDB array columns */ -#define UDB_NUMCOL 6u -/* DSI on bottom (1) or on bottom and top (2) of UDB array */ -#define UDB_DSISIDES 2u -/* Number of UDBs = NUMROW * NUMCOL */ -#define UDB_NUMUDB 12u -/* Number of UDB pairs = NUMUDB / 2 */ -#define UDB_NUMUDBPAIR 6u -/* Number of DSIs = NUMCOL * DSISIDES */ -#define UDB_NUMDSI 12u -/* Number of quad clocks */ -#define UDB_NUMQCLK 3u /* DeepSleep support ('0':no, '1': yes) */ #define SCB0_DEEPSLEEP 0u /* Externally clocked support? ('0': no, '1': yes) */ @@ -2936,55 +2894,10 @@ typedef PDM_V1_Type PDM_Type; #define SCB8_I2C_FAST_PLUS 1u /* Number of used spi_select signals (max 4) */ #define SCB8_CHIP_TOP_SPI_SEL_NR 1u -/* Number of counters per IP (1..8) */ -#define TCPWM0_CNT_NR 8u -/* Counter width (in number of bits) */ -#define TCPWM0_CNT_CNT_WIDTH 32u -/* Number of counters per IP (1..8) */ -#define TCPWM1_CNT_NR 24u -/* Counter width (in number of bits) */ -#define TCPWM1_CNT_CNT_WIDTH 16u -/* Number of ports supoprting up to 4 COMs */ -#define LCD_NUMPORTS 8u -/* Number of ports supporting up to 8 COMs */ -#define LCD_NUMPORTS8 8u -/* Number of ports supporting up to 16 COMs */ -#define LCD_NUMPORTS16 0u -/* Max number of LCD commons supported */ -#define LCD_CHIP_TOP_COM_NR 8u -/* Max number of LCD pins (total) supported */ -#define LCD_CHIP_TOP_PIN_NR 62u -/* Number of IREF outputs from AREF */ -#define PASS_NR_IREFS 4u -/* Number of CTBs in the Subsystem */ -#define PASS_NR_CTBS 1u -/* Number of CTDACs in the Subsystem */ -#define PASS_NR_CTDACS 1u -/* CTB0 Exists */ -#define PASS_CTB0_EXISTS 1u -/* CTB1 Exists */ -#define PASS_CTB1_EXISTS 0u -/* CTB2 Exists */ -#define PASS_CTB2_EXISTS 0u -/* CTB3 Exists */ -#define PASS_CTB3_EXISTS 0u -/* CTDAC0 Exists */ -#define PASS_CTDAC0_EXISTS 1u -/* CTDAC1 Exists */ -#define PASS_CTDAC1_EXISTS 0u -/* CTDAC2 Exists */ -#define PASS_CTDAC2_EXISTS 0u -/* CTDAC3 Exists */ -#define PASS_CTDAC3_EXISTS 0u -/* Number of SAR channels */ -#define PASS_SAR_SAR_CHANNELS 16u -/* Averaging logic present in SAR */ -#define PASS_SAR_SAR_AVERAGE 1u -/* Range detect logic present in SAR */ -#define PASS_SAR_SAR_RANGEDET 1u -/* Support for UAB sampling */ -#define PASS_SAR_SAR_UAB 0u -#define PASS_CTBM_CTDAC_PRESENT 1u +/* SONOS Flash is used or not ('0': no, '1': yes) */ +#define SFLASH_FLASHC_IS_SONOS 1u +/* CPUSS_WOUNDING_PRESENT or not ('0': no, '1': yes) */ +#define SFLASH_CPUSS_WOUNDING_PRESENT 1u /* Number of AHB-Lite "hmaster[]" bits ([1, 8]) */ #define SMIF_MASTER_WIDTH 8u /* Base address of the SMIF XIP memory region. This address must be a multiple of @@ -3010,10 +2923,97 @@ typedef PDM_V1_Type PDM_Type; #define SMIF_CHIP_TOP_DATA8_PRESENT 1u /* Number of used spi_select signals (max 4) */ #define SMIF_CHIP_TOP_SPI_SEL_NR 4u -/* I2S capable? (0=No,1=Yes) */ -#define AUDIOSS_I2S 1u -/* PDM capable? (0=No,1=Yes) */ -#define AUDIOSS_PDM 1u +/* Number of regulator modules instantiated within SRSS */ +#define SRSS_NUM_ACTREG_PWRMOD 2u +/* Number of shorting switches between vccd and vccact */ +#define SRSS_NUM_ACTIVE_SWITCH 3u +/* ULP linear regulator system is present */ +#define SRSS_ULPLINREG_PRESENT 1u +/* HT linear regulator system is present */ +#define SRSS_HTLINREG_PRESENT 0u +/* SIMO buck core regulator is present. Only compatible with ULP linear regulator + system (ULPLINREG_PRESENT==1). */ +#define SRSS_SIMOBUCK_PRESENT 1u +/* Precision ILO (PILO) is present */ +#define SRSS_PILO_PRESENT 1u +/* External Crystal Oscillator is present (high frequency) */ +#define SRSS_ECO_PRESENT 1u +/* System Buck-Boost is present */ +#define SRSS_SYSBB_PRESENT 0u +/* Number of clock paths. Must be > 0 */ +#define SRSS_NUM_CLKPATH 5u +/* Number of PLLs present. Must be <= NUM_CLKPATH */ +#define SRSS_NUM_PLL 1u +/* Number of HFCLK roots present. Must be > 0 */ +#define SRSS_NUM_HFROOT 5u +/* Number of PWR_HIB_DATA registers */ +#define SRSS_NUM_HIBDATA 1u +/* Backup domain is present */ +#define SRSS_BACKUP_PRESENT 1u +/* Mask of HFCLK root clock supervisors (CSV). For each clock root i, bit[i] of + mask indicates presence of a CSV. */ +#define SRSS_MASK_HFCSV 0u +/* Clock supervisor is present on WCO. Must be 0 if BACKUP_PRESENT==0. */ +#define SRSS_WCOCSV_PRESENT 0u +/* Number of software watchdog timers. */ +#define SRSS_NUM_MCWDT 2u +/* Number of DSI inputs into clock muxes. This is used for logic optimization. */ +#define SRSS_NUM_DSI 2u +/* Alternate high-frequency clock is present. This is used for logic optimization. */ +#define SRSS_ALTHF_PRESENT 1u +/* Alternate low-frequency clock is present. This is used for logic optimization. */ +#define SRSS_ALTLF_PRESENT 0u +/* Use the hardened clkactfllmux block */ +#define SRSS_USE_HARD_CLKACTFLLMUX 1u +/* Number of clock paths, including direct paths in hardened clkactfllmux block + (Must be >= NUM_CLKPATH) */ +#define SRSS_HARD_CLKPATH 6u +/* Number of clock paths with muxes in hardened clkactfllmux block (Must be >= + NUM_PLL+1) */ +#define SRSS_HARD_CLKPATHMUX 6u +/* Number of HFCLKS present in hardened clkactfllmux block (Must be >= NUM_HFROOT) */ +#define SRSS_HARD_HFROOT 6u +/* ECO mux is present in hardened clkactfllmux block (Must be >= ECO_PRESENT) */ +#define SRSS_HARD_ECOMUX_PRESENT 1u +/* ALTHF mux is present in hardened clkactfllmux block (Must be >= ALTHF_PRESENT) */ +#define SRSS_HARD_ALTHFMUX_PRESENT 1u +/* Low-current buck regulator present. Can be derived from S40S_SISOBUCKLC_PRESENT + or SIMOBUCK_PRESENT. */ +#define SRSS_BUCKCTL_PRESENT 1u +/* Low-current SISO buck core regulator is present. Only compatible with ULP + linear regulator system (ULPLINREG_PRESENT==1). */ +#define SRSS_S40S_SISOBUCKLC_PRESENT 0u +/* Backup memory is present (only used when BACKUP_PRESENT==1) */ +#define SRSS_BACKUP_BMEM_PRESENT 0u +/* Number of Backup registers to include (each is 32b). Only used when + BACKUP_PRESENT==1. */ +#define SRSS_BACKUP_NUM_BREG 16u +/* Number of counters per IP (1..8) */ +#define TCPWM0_CNT_NR 8u +/* Counter width (in number of bits) */ +#define TCPWM0_CNT_CNT_WIDTH 32u +/* Number of counters per IP (1..8) */ +#define TCPWM1_CNT_NR 24u +/* Counter width (in number of bits) */ +#define TCPWM1_CNT_CNT_WIDTH 16u +/* Number of UDB Interrupts */ +#define UDB_NUMINT 16u +/* Number of triggers */ +#define UDB_NUMTR 16u +/* Number of UDB array rows (must be multiple of 2) */ +#define UDB_NUMROW 2u +/* Number of UDB array columns */ +#define UDB_NUMCOL 6u +/* DSI on bottom (1) or on bottom and top (2) of UDB array */ +#define UDB_DSISIDES 2u +/* Number of UDBs = NUMROW * NUMCOL */ +#define UDB_NUMUDB 12u +/* Number of UDB pairs = NUMUDB / 2 */ +#define UDB_NUMUDBPAIR 6u +/* Number of DSIs = NUMCOL * DSISIDES */ +#define UDB_NUMDSI 12u +/* Number of quad clocks */ +#define UDB_NUMQCLK 3u /* MMIO Targets Defines */ #define CY_MMIO_CRYPTO_GROUP_NR 1u diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/psoc6_02_config.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/psoc6_02_config.h index e131351a4a..974842e1b4 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/psoc6_02_config.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/psoc6_02_config.h @@ -5,7 +5,7 @@ * PSoC6_02 device configuration header * * \note -* Generator version: 1.6.0.111 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -1537,59 +1537,59 @@ typedef enum } en_trig_type_t; /* Trigger Type Defines */ -/* TCPWM Trigger Types */ -#define TRIGGER_TYPE_TCPWM_LINE TRIGGER_TYPE_LEVEL -#define TRIGGER_TYPE_TCPWM_LINE_COMPL TRIGGER_TYPE_LEVEL -#define TRIGGER_TYPE_TCPWM_TR_OVERFLOW TRIGGER_TYPE_EDGE -#define TRIGGER_TYPE_TCPWM_TR_COMPARE_MATCH TRIGGER_TYPE_EDGE -#define TRIGGER_TYPE_TCPWM_TR_UNDERFLOW TRIGGER_TYPE_EDGE -#define TRIGGER_TYPE_TCPWM_TR_IN__LEVEL TRIGGER_TYPE_LEVEL -#define TRIGGER_TYPE_TCPWM_TR_IN__EDGE TRIGGER_TYPE_EDGE +/* AUDIOSS Trigger Types */ +#define TRIGGER_TYPE_AUDIOSS_TR_I2S_RX_REQ TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_AUDIOSS_TR_I2S_TX_REQ TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_AUDIOSS_TR_PDM_RX_REQ TRIGGER_TYPE_LEVEL +/* CPUSS Trigger Types */ +#define TRIGGER_TYPE_CPUSS_CTI_TR_IN TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_CPUSS_CTI_TR_OUT TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_CPUSS_DMAC_TR_IN__LEVEL TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_CPUSS_DMAC_TR_IN__EDGE TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_CPUSS_DMAC_TR_OUT TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_CPUSS_DW0_TR_IN__LEVEL TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_CPUSS_DW0_TR_IN__EDGE TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_CPUSS_DW0_TR_OUT TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_CPUSS_DW1_TR_IN__LEVEL TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_CPUSS_DW1_TR_IN__EDGE TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_CPUSS_DW1_TR_OUT TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_CPUSS_TR_FAULT TRIGGER_TYPE_EDGE /* CSD Trigger Types */ #define TRIGGER_TYPE_CSD_DSI_SAMPLE_OUT TRIGGER_TYPE_EDGE -/* SCB Trigger Types */ -#define TRIGGER_TYPE_SCB_TR_I2C_SCL_FILTERED TRIGGER_TYPE_LEVEL -#define TRIGGER_TYPE_SCB_TR_TX_REQ TRIGGER_TYPE_LEVEL -#define TRIGGER_TYPE_SCB_TR_RX_REQ TRIGGER_TYPE_LEVEL +/* LPCOMP Trigger Types */ +#define TRIGGER_TYPE_LPCOMP_DSI_COMP0 TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_LPCOMP_DSI_COMP1 TRIGGER_TYPE_LEVEL +/* PASS Trigger Types */ +#define TRIGGER_TYPE_PASS_TR_SAR_IN__LEVEL TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_PASS_TR_SAR_IN__EDGE TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_PASS_TR_SAR_OUT TRIGGER_TYPE_EDGE /* PERI Trigger Types */ +#define TRIGGER_TYPE_PERI_TR_DBG_FREEZE TRIGGER_TYPE_LEVEL #define TRIGGER_TYPE_PERI_TR_IO_INPUT__LEVEL TRIGGER_TYPE_LEVEL #define TRIGGER_TYPE_PERI_TR_IO_INPUT__EDGE TRIGGER_TYPE_EDGE #define TRIGGER_TYPE_PERI_TR_IO_OUTPUT__LEVEL TRIGGER_TYPE_LEVEL #define TRIGGER_TYPE_PERI_TR_IO_OUTPUT__EDGE TRIGGER_TYPE_EDGE -#define TRIGGER_TYPE_PERI_TR_DBG_FREEZE TRIGGER_TYPE_LEVEL -/* CPUSS Trigger Types */ -#define TRIGGER_TYPE_CPUSS_DW0_TR_IN__LEVEL TRIGGER_TYPE_LEVEL -#define TRIGGER_TYPE_CPUSS_DW0_TR_IN__EDGE TRIGGER_TYPE_EDGE -#define TRIGGER_TYPE_CPUSS_DW1_TR_IN__LEVEL TRIGGER_TYPE_LEVEL -#define TRIGGER_TYPE_CPUSS_DW1_TR_IN__EDGE TRIGGER_TYPE_EDGE -#define TRIGGER_TYPE_CPUSS_DMAC_TR_IN__LEVEL TRIGGER_TYPE_LEVEL -#define TRIGGER_TYPE_CPUSS_DMAC_TR_IN__EDGE TRIGGER_TYPE_EDGE -#define TRIGGER_TYPE_CPUSS_DW0_TR_OUT TRIGGER_TYPE_EDGE -#define TRIGGER_TYPE_CPUSS_DW1_TR_OUT TRIGGER_TYPE_EDGE -#define TRIGGER_TYPE_CPUSS_DMAC_TR_OUT TRIGGER_TYPE_EDGE -#define TRIGGER_TYPE_CPUSS_CTI_TR_OUT TRIGGER_TYPE_EDGE -#define TRIGGER_TYPE_CPUSS_TR_FAULT TRIGGER_TYPE_EDGE -#define TRIGGER_TYPE_CPUSS_CTI_TR_IN TRIGGER_TYPE_EDGE -/* AUDIOSS Trigger Types */ -#define TRIGGER_TYPE_AUDIOSS_TR_I2S_TX_REQ TRIGGER_TYPE_LEVEL -#define TRIGGER_TYPE_AUDIOSS_TR_I2S_RX_REQ TRIGGER_TYPE_LEVEL -#define TRIGGER_TYPE_AUDIOSS_TR_PDM_RX_REQ TRIGGER_TYPE_LEVEL -/* LPCOMP Trigger Types */ -#define TRIGGER_TYPE_LPCOMP_DSI_COMP0 TRIGGER_TYPE_LEVEL -#define TRIGGER_TYPE_LPCOMP_DSI_COMP1 TRIGGER_TYPE_LEVEL -/* SMIF Trigger Types */ -#define TRIGGER_TYPE_SMIF_TR_TX_REQ TRIGGER_TYPE_LEVEL -#define TRIGGER_TYPE_SMIF_TR_RX_REQ TRIGGER_TYPE_LEVEL -/* USB Trigger Types */ -#define TRIGGER_TYPE_USB_DMA_REQ TRIGGER_TYPE_EDGE -#define TRIGGER_TYPE_USB_DMA_BURSTEND TRIGGER_TYPE_EDGE -/* PASS Trigger Types */ -#define TRIGGER_TYPE_PASS_TR_SAR_OUT TRIGGER_TYPE_EDGE -#define TRIGGER_TYPE_PASS_TR_SAR_IN__LEVEL TRIGGER_TYPE_LEVEL -#define TRIGGER_TYPE_PASS_TR_SAR_IN__EDGE TRIGGER_TYPE_EDGE /* PROFILE Trigger Types */ #define TRIGGER_TYPE_PROFILE_TR_START TRIGGER_TYPE_EDGE #define TRIGGER_TYPE_PROFILE_TR_STOP TRIGGER_TYPE_EDGE +/* SCB Trigger Types */ +#define TRIGGER_TYPE_SCB_TR_I2C_SCL_FILTERED TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_SCB_TR_RX_REQ TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_SCB_TR_TX_REQ TRIGGER_TYPE_LEVEL +/* SMIF Trigger Types */ +#define TRIGGER_TYPE_SMIF_TR_RX_REQ TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_SMIF_TR_TX_REQ TRIGGER_TYPE_LEVEL +/* TCPWM Trigger Types */ +#define TRIGGER_TYPE_TCPWM_LINE TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_TCPWM_LINE_COMPL TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_TCPWM_TR_COMPARE_MATCH TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_TCPWM_TR_IN__LEVEL TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_TCPWM_TR_IN__EDGE TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_TCPWM_TR_OVERFLOW TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_TCPWM_TR_UNDERFLOW TRIGGER_TYPE_EDGE +/* USB Trigger Types */ +#define TRIGGER_TYPE_USB_DMA_BURSTEND TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_USB_DMA_REQ TRIGGER_TYPE_EDGE /* Monitor Signal Defines */ typedef enum @@ -1746,89 +1746,268 @@ typedef PDM_V1_Type PDM_Type; typedef I2S_V1_Type I2S_Type; /* Parameter Defines */ -/* Number of regulator modules instantiated within SRSS, start with estimate, - update after CMR feedback */ -#define SRSS_NUM_ACTREG_PWRMOD 2u -/* Number of shorting switches between vccd and vccact (target dynamic voltage - drop < 10mV) */ -#define SRSS_NUM_ACTIVE_SWITCH 3u -/* ULP linear regulator system is present */ -#define SRSS_ULPLINREG_PRESENT 1u -/* HT linear regulator system is present */ -#define SRSS_HTLINREG_PRESENT 0u -/* Low-current buck regulator present. Can be derived from S40S_SISOBUCKLC_PRESENT - or SIMOBUCK_PRESENT. */ -#define SRSS_BUCKCTL_PRESENT 1u -/* Low-current SISO buck core regulator is present. Only compatible with ULP - linear regulator system (ULPLINREG_PRESENT==1). */ -#define SRSS_S40S_SISOBUCKLC_PRESENT 1u -/* SIMO buck core regulator is present. Only compatible with ULP linear regulator - system (ULPLINREG_PRESENT==1). */ -#define SRSS_SIMOBUCK_PRESENT 0u -/* Precision ILO (PILO) is present */ -#define SRSS_PILO_PRESENT 0u -/* External Crystal Oscillator is present (high frequency) */ -#define SRSS_ECO_PRESENT 1u -/* System Buck-Boost is present */ -#define SRSS_SYSBB_PRESENT 0u -/* Number of clock paths. Must be > 0 */ -#define SRSS_NUM_CLKPATH 6u -/* Number of PLLs present. Must be <= NUM_CLKPATH */ -#define SRSS_NUM_PLL 2u -/* Number of HFCLK roots present. Must be > 0 */ -#define SRSS_NUM_HFROOT 6u -/* Number of PWR_HIB_DATA registers, should not be needed if BACKUP_PRESENT */ -#define SRSS_NUM_HIBDATA 1u -/* Backup domain is present (includes RTC and WCO) */ -#define SRSS_BACKUP_PRESENT 1u -/* Mask of HFCLK root clock supervisors (CSV). For each clock root i, bit[i] of - mask indicates presence of a CSV. */ -#define SRSS_MASK_HFCSV 0u -/* Clock supervisor is present on WCO. Must be 0 if BACKUP_PRESENT==0. */ -#define SRSS_WCOCSV_PRESENT 0u -/* Number of software watchdog timers. */ -#define SRSS_NUM_MCWDT 2u -/* Number of DSI inputs into clock muxes. This is used for logic optimization. */ -#define SRSS_NUM_DSI 0u -/* Alternate high-frequency clock is present. This is used for logic optimization. */ -#define SRSS_ALTHF_PRESENT 0u -/* Alternate low-frequency clock is present. This is used for logic optimization. */ -#define SRSS_ALTLF_PRESENT 0u -/* Use the hardened clkactfllmux block */ -#define SRSS_USE_HARD_CLKACTFLLMUX 1u -/* Number of clock paths, including direct paths in hardened clkactfllmux block - (Must be >= NUM_CLKPATH) */ -#define SRSS_HARD_CLKPATH 6u -/* Number of clock paths with muxes in hardened clkactfllmux block (Must be >= - NUM_PLL+1) */ -#define SRSS_HARD_CLKPATHMUX 6u -/* Number of HFCLKS present in hardened clkactfllmux block (Must be >= NUM_HFROOT) */ -#define SRSS_HARD_HFROOT 6u -/* ECO mux is present in hardened clkactfllmux block (Must be >= ECO_PRESENT) */ -#define SRSS_HARD_ECOMUX_PRESENT 1u -/* ALTHF mux is present in hardened clkactfllmux block (Must be >= ALTHF_PRESENT) */ -#define SRSS_HARD_ALTHFMUX_PRESENT 1u -/* Backup memory is present (only used when BACKUP_PRESENT==1) */ -#define SRSS_BACKUP_BMEM_PRESENT 0u -/* Number of Backup registers to include (each is 32b). Only used when - BACKUP_PRESENT==1. */ -#define SRSS_BACKUP_NUM_BREG 16u -/* Number of AMUX splitter cells */ -#define IOSS_HSIOM_AMUX_SPLIT_NR 8u -/* Number of HSIOM ports in device (same as GPIO.GPIO_PRT_NR) */ -#define IOSS_HSIOM_HSIOM_PORT_NR 15u -/* Number of PWR/GND MONITOR CELLs in the device */ -#define IOSS_HSIOM_MONITOR_NR 0u -/* Number of PWR/GND MONITOR CELLs in range 0..31 */ -#define IOSS_HSIOM_MONITOR_NR_0_31 0u -/* Number of PWR/GND MONITOR CELLs in range 32..63 */ -#define IOSS_HSIOM_MONITOR_NR_32_63 0u -/* Number of PWR/GND MONITOR CELLs in range 64..95 */ -#define IOSS_HSIOM_MONITOR_NR_64_95 0u -/* Number of PWR/GND MONITOR CELLs in range 96..127 */ -#define IOSS_HSIOM_MONITOR_NR_96_127 0u -/* Indicates the presence of alternate JTAG interface */ -#define IOSS_HSIOM_ALTJTAG_PRESENT 0u +/* I2S capable? (0=No,1=Yes) */ +#define AUDIOSS0_I2S 1u +/* PDM capable? (0=No,1=Yes) */ +#define AUDIOSS0_PDM 1u +/* I2S capable? (0=No,1=Yes) */ +#define AUDIOSS1_I2S 1u +/* PDM capable? (0=No,1=Yes) */ +#define AUDIOSS1_PDM 0u +/* UDB present or not ('0': no, '1': yes) */ +#define CPUSS_UDB_PRESENT 0u +/* MBIST MMIO for Synopsys MBIST ('0': no, '1': yes). Set this to '1' only for the + chips which doesn't use mxdft. */ +#define CPUSS_MBIST_MMIO_PRESENT 1u +/* System RAM 0 size in kilobytes */ +#define CPUSS_SRAM0_SIZE 512u +/* Number of macros used to implement System RAM 0. Example: 8 if 256 KB System + SRAM0 is implemented with 8 32KB macros. */ +#define CPUSS_RAMC0_MACRO_NR 16u +/* System RAM 1 present or not (0=No, 1=Yes) */ +#define CPUSS_RAMC1_PRESENT 1u +/* System RAM 1 size in kilobytes */ +#define CPUSS_SRAM1_SIZE 256u +/* Number of macros used to implement System RAM 1. Example: 8 if 256 KB System + RAM 1 is implemented with 8 32KB macros. */ +#define CPUSS_RAMC1_MACRO_NR 8u +/* System RAM 2 present or not (0=No, 1=Yes) */ +#define CPUSS_RAMC2_PRESENT 1u +/* System RAM 2 size in kilobytes */ +#define CPUSS_SRAM2_SIZE 256u +/* Number of macros used to implement System RAM 2. Example: 8 if 256 KB System + RAM 2 is implemented with 8 32KB macros. */ +#define CPUSS_RAMC2_MACRO_NR 8u +/* System SRAM(s) ECC present or not ('0': no, '1': yes) */ +#define CPUSS_RAMC_ECC_PRESENT 0u +/* System SRAM(s) address ECC present or not ('0': no, '1': yes) */ +#define CPUSS_RAMC_ECC_ADDR_PRESENT 0u +/* ECC present in either system RAM or interrupt handler (RAMC_ECC_PRESENT) */ +#define CPUSS_ECC_PRESENT 0u +/* DataWire SRAMs ECC present or not ('0': no, '1': yes) */ +#define CPUSS_DW_ECC_PRESENT 0u +/* DataWire SRAMs address ECC present or not ('0': no, '1': yes) */ +#define CPUSS_DW_ECC_ADDR_PRESENT 0u +/* System ROM size in KB */ +#define CPUSS_ROM_SIZE 64u +/* Number of macros used to implement system ROM. Example: 4 if 512 KB system ROM + is implemented with 4 128KB macros. */ +#define CPUSS_ROMC_MACRO_NR 1u +/* Flash memory type ('0' : SONOS, '1': ECT) */ +#define CPUSS_FLASHC_ECT 0u +/* Flash main region size in KB */ +#define CPUSS_FLASH_SIZE 2048u +/* Flash work region size in KB (EEPROM emulation, data) */ +#define CPUSS_WFLASH_SIZE 32u +/* Flash supervisory region size in KB */ +#define CPUSS_SFLASH_SIZE 32u +/* Flash data output word size (in Bytes) */ +#define CPUSS_FLASHC_MAIN_DATA_WIDTH 16u +/* SONOS Flash RWW present or not ('0': no, '1': yes) When RWW is '0', No special + sectors present in Flash. Part of main sector 0 is allowcated for Supervisory + Flash, and no Work Flash present. */ +#define CPUSS_FLASHC_SONOS_RWW 1u +/* SONOS Flash, number of main sectors. */ +#define CPUSS_FLASHC_SONOS_MAIN_SECTORS 8u +/* SONOS Flash, number of rows per main sector. */ +#define CPUSS_FLASHC_SONOS_MAIN_ROWS 512u +/* SONOS Flash, number of words per row of main sector. */ +#define CPUSS_FLASHC_SONOS_MAIN_WORDS 128u +/* SONOS Flash, number of special sectors. */ +#define CPUSS_FLASHC_SONOS_SPL_SECTORS 2u +/* SONOS Flash, number of rows per special sector. */ +#define CPUSS_FLASHC_SONOS_SPL_ROWS 64u +/* Flash memory ECC present or not ('0': no, '1': yes) */ +#define CPUSS_FLASHC_FLASH_ECC_PRESENT 0u +/* Flash cache SRAM(s) ECC present or not ('0': no, '1': yes) */ +#define CPUSS_FLASHC_RAM_ECC_PRESENT 0u +/* Number of external slaves directly connected to slow AHB-Lite infrastructure. + Maximum nubmer of slave supported is 4. Width of this parameter is 4-bits. + 1-bit mask for each slave indicating present or not. Example: 4'b0011 - slave + 0 and slave 1 are present. Note: The SLOW_SLx_ADDR and SLOW_SLx_MASK + parameters (for the slaves present) should be derived from the Memory Map. */ +#define CPUSS_SLOW_SL_PRESENT 1u +/* Number of external slaves directly connected to fast AHB-Lite infrastructure. + Maximum nubmer of slave supported is 4. Width of this parameter is 4-bits. + 1-bit mask for each slave indicating present or not. Example: 4'b0011 - slave + 0 and slave 1 are present. Note: The FAST_SLx_ADDR and FAST_SLx_MASK + parameters (for the slaves present) should be derived from the Memory Map. */ +#define CPUSS_FAST_SL_PRESENT 1u +/* Number of external masters driving the slow AHB-Lite infrastructure. Maximum + number of masters supported is 2. Width of this parameter is 2-bits. 1-bit + mask for each master indicating present or not. Example: 2'b01 - master 0 is + present. */ +#define CPUSS_SLOW_MS_PRESENT 3u +/* System interrupt functionality present or not ('0': no; '1': yes). Not used for + CM0+ PCU, which always uses system interrupt functionality. */ +#define CPUSS_SYSTEM_IRQ_PRESENT 0u +/* Number of total interrupt request inputs to CPUSS */ +#define CPUSS_SYSTEM_INT_NR 168u +/* Number of DeepSleep wakeup interrupt inputs to CPUSS */ +#define CPUSS_SYSTEM_DPSLP_INT_NR 39u +/* Width of the CM4 interrupt priority bits. Legal range [3,8] Example: 3 = 8 + levels of priority 8 = 256 levels of priority */ +#define CPUSS_CM4_LVL_WIDTH 3u +/* CM4 Floating point unit present or not (0=No, 1=Yes) */ +#define CPUSS_CM4_FPU_PRESENT 1u +/* Debug level. Legal range [0,3] (0= No support, 1= Minimum: CM0/4 both 2 + breakpoints +1 watchpoint, 2= Full debug: CM0/4 have 4/6 breakpoints, 2/4 + watchpoints and 0/2 literal compare, 3= Full debug + data matching) */ +#define CPUSS_DEBUG_LVL 3u +/* Trace level. Legal range [0,2] (0= No tracing, 1= ITM + TPIU + SWO, 2= ITM + + ETM + TPIU + SWO) Note: CM4 HTM is not supported. Hence vaule 3 for trace + level is not supported in CPUSS. */ +#define CPUSS_TRACE_LVL 2u +/* Embedded Trace Buffer present or not (0=No, 1=Yes) */ +#define CPUSS_ETB_PRESENT 0u +/* CM0+ MTB SRAM buffer size in kilobytes. Legal vaules 4, 8 or 16 */ +#define CPUSS_MTB_SRAM_SIZE 4u +/* CM4 ETB SRAM buffer size in kilobytes. Legal vaules 4, 8 or 16 */ +#define CPUSS_ETB_SRAM_SIZE 8u +/* PTM interface present (0=No, 1=Yes) */ +#define CPUSS_PTM_PRESENT 0u +/* Width of the PTM interface in bits ([2,32]) */ +#define CPUSS_PTM_WIDTH 1u +/* Width of the TPIU interface in bits ([1,4]) */ +#define CPUSS_TPIU_WIDTH 4u +/* CoreSight Part Identification Number */ +#define CPUSS_JEPID 52u +/* CoreSight Part Identification Number */ +#define CPUSS_JEPCONTINUATION 0u +/* CoreSight Part Identification Number */ +#define CPUSS_FAMILYID 258u +/* ROM trim register width (for ARM 3, for Synopsys 5) */ +#define CPUSS_ROM_TRIM_WIDTH 5u +/* ROM trim register default (for both ARM and Synopsys 0x0000_0012) */ +#define CPUSS_ROM_TRIM_DEFAULT 18u +/* RAM trim register width (for ARM 8, for Synopsys 15) */ +#define CPUSS_RAM_TRIM_WIDTH 15u +/* RAM trim register default (for ARM 0x0000_0062 and for Synopsys 0x0000_6012) */ +#define CPUSS_RAM_TRIM_DEFAULT 24594u +/* Cryptography IP present or not (0=No, 1=Yes) */ +#define CPUSS_CRYPTO_PRESENT 1u +/* DataWire and DMAC SW trigger per channel present or not ('0': no, '1': yes) */ +#define CPUSS_SW_TR_PRESENT 0u +/* DataWire 0 present or not (0=No, 1=Yes) */ +#define CPUSS_DW0_PRESENT 1u +/* Number of DataWire 0 channels (8, 16 or 32) */ +#define CPUSS_DW0_CH_NR 29u +/* DataWire 1 present or not (0=No, 1=Yes) */ +#define CPUSS_DW1_PRESENT 1u +/* Number of DataWire 1 channels (8, 16 or 32) */ +#define CPUSS_DW1_CH_NR 29u +/* DMA controller present or not ('0': no, '1': yes) */ +#define CPUSS_DMAC_PRESENT 1u +/* Number of DMA controller channels ([1, 8]) */ +#define CPUSS_DMAC_CH_NR 4u +/* DMAC SW trigger per channel present or not ('0': no, '1': yes) */ +#define CPUSS_CH_SW_TR_PRESENT 0u +/* See MMIO2 instantiation or not */ +#define CPUSS_CHIP_TOP_PROFILER_PRESENT 1u +/* ETAS Calibration support pin out present (automotive only) */ +#define CPUSS_CHIP_TOP_CAL_SUP_NZ_PRESENT 0u +/* TRACE_LVL>0 */ +#define CPUSS_CHIP_TOP_TRACE_PRESENT 1u +/* DataWire SW trigger per channel present or not ('0': no, '1': yes) */ +#define CPUSS_CH_STRUCT_SW_TR_PRESENT 0u +/* Number of DataWire controllers present (max 2) (same as DW.NR above) */ +#define CPUSS_CPUSS_DW_DW_NR 2u +/* Number of channels in each DataWire controller */ +#define CPUSS_CPUSS_DW_DW_NR0_DW_CH_NR 29u +/* Width of a channel number in bits */ +#define CPUSS_CPUSS_DW_DW_NR0_DW_CH_NR_WIDTH 5u +/* Number of channels in each DataWire controller */ +#define CPUSS_CPUSS_DW_DW_NR1_DW_CH_NR 29u +/* Width of a channel number in bits */ +#define CPUSS_CPUSS_DW_DW_NR1_DW_CH_NR_WIDTH 5u +/* Cryptography SRAMs ECC present or not ('0': no, '1': yes) */ +#define CPUSS_CRYPTO_ECC_PRESENT 0u +/* Cryptography SRAMs address ECC present or not ('0': no, '1': yes) */ +#define CPUSS_CRYPTO_ECC_ADDR_PRESENT 0u +/* AES cipher support ('0': no, '1': yes) */ +#define CPUSS_CRYPTO_AES 1u +/* (Tripple) DES cipher support ('0': no, '1': yes) */ +#define CPUSS_CRYPTO_DES 1u +/* Chacha support ('0': no, '1': yes) */ +#define CPUSS_CRYPTO_CHACHA 1u +/* Pseudo random number generation support ('0': no, '1': yes) */ +#define CPUSS_CRYPTO_PR 1u +/* SHA1 hash support ('0': no, '1': yes) */ +#define CPUSS_CRYPTO_SHA1 1u +/* SHA2 hash support ('0': no, '1': yes) */ +#define CPUSS_CRYPTO_SHA2 1u +/* SHA3 hash support ('0': no, '1': yes) */ +#define CPUSS_CRYPTO_SHA3 1u +/* Cyclic Redundancy Check support ('0': no, '1': yes) */ +#define CPUSS_CRYPTO_CRC 1u +/* True random number generation support ('0': no, '1': yes) */ +#define CPUSS_CRYPTO_TR 1u +/* Vector unit support ('0': no, '1': yes) */ +#define CPUSS_CRYPTO_VU 1u +/* Galios/Counter Mode (GCM) support ('0': no, '1': yes) */ +#define CPUSS_CRYPTO_GCM 1u +/* Number of 32-bit words in the IP internal memory buffer (from the set [64, 128, + 256, 512, 1024, 2048, 4096], to allow for a 256 B, 512 B, 1 kB, 2 kB, 4 kB, 8 + kB and 16 kB memory buffer) */ +#define CPUSS_CRYPTO_BUFF_SIZE 1024u +/* Number of DMA controller channels ([1, 8]) */ +#define CPUSS_DMAC_CH_NR 4u +/* Number of DataWire controllers present (max 2) */ +#define CPUSS_DW_NR 2u +/* DataWire SRAMs ECC present or not ('0': no, '1': yes) */ +#define CPUSS_DW_ECC_PRESENT 0u +/* Number of fault structures. Legal range [1, 4] */ +#define CPUSS_FAULT_FAULT_NR 2u +/* Number of Flash BIST_DATA registers */ +#define CPUSS_FLASHC_FLASHC_BIST_DATA_NR 4u +/* Page size in # of 32-bit words (1: 4 bytes, 2: 8 bytes, ... */ +#define CPUSS_FLASHC_PA_SIZE 128u +/* SONOS Flash is used or not ('0': no, '1': yes) */ +#define CPUSS_FLASHC_FLASHC_IS_SONOS 1u +/* eCT Flash is used or not ('0': no, '1': yes) */ +#define CPUSS_FLASHC_FLASHC_IS_ECT 0u +/* Number of IPC structures. Legal range [1, 16] */ +#define CPUSS_IPC_IPC_NR 16u +/* Number of IPC interrupt structures. Legal range [1, 16] */ +#define CPUSS_IPC_IPC_IRQ_NR 16u +/* Master 0 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS0_PC_NR_MINUS1 7u +/* Master 1 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS1_PC_NR_MINUS1 0u +/* Master 2 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS2_PC_NR_MINUS1 0u +/* Master 3 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS3_PC_NR_MINUS1 0u +/* Master 4 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS4_PC_NR_MINUS1 0u +/* Master 5 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS5_PC_NR_MINUS1 7u +/* Master 6 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS6_PC_NR_MINUS1 7u +/* Master 7 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS7_PC_NR_MINUS1 0u +/* Master 8 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS8_PC_NR_MINUS1 0u +/* Master 9 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS9_PC_NR_MINUS1 0u +/* Master 10 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS10_PC_NR_MINUS1 0u +/* Master 11 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS11_PC_NR_MINUS1 0u +/* Master 12 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS12_PC_NR_MINUS1 0u +/* Master 13 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS13_PC_NR_MINUS1 0u +/* Master 14 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS14_PC_NR_MINUS1 7u +/* Master 15 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS15_PC_NR_MINUS1 7u +/* Number of SMPU protection structures */ +#define CPUSS_PROT_SMPU_STRUCT_NR 16u +/* Number of protection contexts supported minus 1. Legal range [1,16] */ +#define CPUSS_SMPU_STRUCT_PC_NR_MINUS1 7u +/* Number of instantiated eFUSE macros (256 bit macros). Legal range [1, 16] */ +#define EFUSE_EFUSE_NR 4u /* Number of GPIO ports in range 0..31 */ #define IOSS_GPIO_GPIO_PORT_NR_0_31 15u /* Number of GPIO ports in range 32..63 */ @@ -2169,8 +2348,65 @@ typedef I2S_V1_Type I2S_Type; #define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_SLOW_IO6 0u /* Indicates that pin #7 exists for this port with slew control feature */ #define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_SLOW_IO7 0u +/* Number of AMUX splitter cells */ +#define IOSS_HSIOM_AMUX_SPLIT_NR 8u +/* Number of HSIOM ports in device (same as GPIO.GPIO_PRT_NR) */ +#define IOSS_HSIOM_HSIOM_PORT_NR 15u +/* Number of PWR/GND MONITOR CELLs in the device */ +#define IOSS_HSIOM_MONITOR_NR 0u +/* Number of PWR/GND MONITOR CELLs in range 0..31 */ +#define IOSS_HSIOM_MONITOR_NR_0_31 0u +/* Number of PWR/GND MONITOR CELLs in range 32..63 */ +#define IOSS_HSIOM_MONITOR_NR_32_63 0u +/* Number of PWR/GND MONITOR CELLs in range 64..95 */ +#define IOSS_HSIOM_MONITOR_NR_64_95 0u +/* Number of PWR/GND MONITOR CELLs in range 96..127 */ +#define IOSS_HSIOM_MONITOR_NR_96_127 0u +/* Indicates the presence of alternate JTAG interface */ +#define IOSS_HSIOM_ALTJTAG_PRESENT 0u /* Mask of SMARTIO instances presence */ #define IOSS_SMARTIO_SMARTIO_MASK 768u +/* Number of ports supoprting up to 4 COMs */ +#define LCD_NUMPORTS 8u +/* Number of ports supporting up to 8 COMs */ +#define LCD_NUMPORTS8 8u +/* Number of ports supporting up to 16 COMs */ +#define LCD_NUMPORTS16 0u +/* Max number of LCD commons supported */ +#define LCD_CHIP_TOP_COM_NR 8u +/* Max number of LCD pins (total) supported */ +#define LCD_CHIP_TOP_PIN_NR 62u +/* Number of IREF outputs from AREF */ +#define PASS_NR_IREFS 4u +/* Number of CTBs in the Subsystem */ +#define PASS_NR_CTBS 0u +/* Number of CTDACs in the Subsystem */ +#define PASS_NR_CTDACS 0u +/* CTB0 Exists */ +#define PASS_CTB0_EXISTS 0u +/* CTB1 Exists */ +#define PASS_CTB1_EXISTS 0u +/* CTB2 Exists */ +#define PASS_CTB2_EXISTS 0u +/* CTB3 Exists */ +#define PASS_CTB3_EXISTS 0u +/* CTDAC0 Exists */ +#define PASS_CTDAC0_EXISTS 0u +/* CTDAC1 Exists */ +#define PASS_CTDAC1_EXISTS 0u +/* CTDAC2 Exists */ +#define PASS_CTDAC2_EXISTS 0u +/* CTDAC3 Exists */ +#define PASS_CTDAC3_EXISTS 0u +#define PASS_CTBM_CTDAC_PRESENT 0u +/* Number of SAR channels */ +#define PASS_SAR_SAR_CHANNELS 16u +/* Averaging logic present in SAR */ +#define PASS_SAR_SAR_AVERAGE 1u +/* Range detect logic present in SAR */ +#define PASS_SAR_SAR_RANGEDET 1u +/* Support for UAB sampling */ +#define PASS_SAR_SAR_UAB 0u /* The number of protection contexts ([2, 16]). */ #define PERI_PC_NR 8u /* Master interface presence mask (4 bits) */ @@ -2777,268 +3013,10 @@ typedef I2S_V1_Type I2S_Type; #define PERI_TR_1TO1_GROUP_NR6_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u /* Number of AHB-Lite "hmaster[]" bits ([1, 8]). */ #define PERI_MASTER_WIDTH 8u -/* UDB present or not ('0': no, '1': yes) */ -#define CPUSS_UDB_PRESENT 0u -/* MBIST MMIO for Synopsys MBIST ('0': no, '1': yes). Set this to '1' only for the - chips which doesn't use mxdft. */ -#define CPUSS_MBIST_MMIO_PRESENT 1u -/* System RAM 0 size in kilobytes */ -#define CPUSS_SRAM0_SIZE 512u -/* Number of macros used to implement System RAM 0. Example: 8 if 256 KB System - SRAM0 is implemented with 8 32KB macros. */ -#define CPUSS_RAMC0_MACRO_NR 16u -/* System RAM 1 present or not (0=No, 1=Yes) */ -#define CPUSS_RAMC1_PRESENT 1u -/* System RAM 1 size in kilobytes */ -#define CPUSS_SRAM1_SIZE 256u -/* Number of macros used to implement System RAM 1. Example: 8 if 256 KB System - RAM 1 is implemented with 8 32KB macros. */ -#define CPUSS_RAMC1_MACRO_NR 8u -/* System RAM 2 present or not (0=No, 1=Yes) */ -#define CPUSS_RAMC2_PRESENT 1u -/* System RAM 2 size in kilobytes */ -#define CPUSS_SRAM2_SIZE 256u -/* Number of macros used to implement System RAM 2. Example: 8 if 256 KB System - RAM 2 is implemented with 8 32KB macros. */ -#define CPUSS_RAMC2_MACRO_NR 8u -/* System SRAM(s) ECC present or not ('0': no, '1': yes) */ -#define CPUSS_RAMC_ECC_PRESENT 0u -/* System SRAM(s) address ECC present or not ('0': no, '1': yes) */ -#define CPUSS_RAMC_ECC_ADDR_PRESENT 0u -/* ECC present in either system RAM or interrupt handler (RAMC_ECC_PRESENT) */ -#define CPUSS_ECC_PRESENT 0u -/* DataWire SRAMs ECC present or not ('0': no, '1': yes) */ -#define CPUSS_DW_ECC_PRESENT 0u -/* DataWire SRAMs address ECC present or not ('0': no, '1': yes) */ -#define CPUSS_DW_ECC_ADDR_PRESENT 0u -/* System ROM size in KB */ -#define CPUSS_ROM_SIZE 64u -/* Number of macros used to implement system ROM. Example: 4 if 512 KB system ROM - is implemented with 4 128KB macros. */ -#define CPUSS_ROMC_MACRO_NR 1u -/* Flash memory type ('0' : SONOS, '1': ECT) */ -#define CPUSS_FLASHC_ECT 0u -/* Flash main region size in KB */ -#define CPUSS_FLASH_SIZE 2048u -/* Flash work region size in KB (EEPROM emulation, data) */ -#define CPUSS_WFLASH_SIZE 32u -/* Flash supervisory region size in KB */ -#define CPUSS_SFLASH_SIZE 32u -/* Flash data output word size (in Bytes) */ -#define CPUSS_FLASHC_MAIN_DATA_WIDTH 16u -/* SONOS Flash RWW present or not ('0': no, '1': yes) When RWW is '0', No special - sectors present in Flash. Part of main sector 0 is allowcated for Supervisory - Flash, and no Work Flash present. */ -#define CPUSS_FLASHC_SONOS_RWW 1u -/* SONOS Flash, number of main sectors. */ -#define CPUSS_FLASHC_SONOS_MAIN_SECTORS 8u -/* SONOS Flash, number of rows per main sector. */ -#define CPUSS_FLASHC_SONOS_MAIN_ROWS 512u -/* SONOS Flash, number of words per row of main sector. */ -#define CPUSS_FLASHC_SONOS_MAIN_WORDS 128u -/* SONOS Flash, number of special sectors. */ -#define CPUSS_FLASHC_SONOS_SPL_SECTORS 2u -/* SONOS Flash, number of rows per special sector. */ -#define CPUSS_FLASHC_SONOS_SPL_ROWS 64u -/* Flash memory ECC present or not ('0': no, '1': yes) */ -#define CPUSS_FLASHC_FLASH_ECC_PRESENT 0u -/* Flash cache SRAM(s) ECC present or not ('0': no, '1': yes) */ -#define CPUSS_FLASHC_RAM_ECC_PRESENT 0u -/* Number of external slaves directly connected to slow AHB-Lite infrastructure. - Maximum nubmer of slave supported is 4. Width of this parameter is 4-bits. - 1-bit mask for each slave indicating present or not. Example: 4'b0011 - slave - 0 and slave 1 are present. Note: The SLOW_SLx_ADDR and SLOW_SLx_MASK - parameters (for the slaves present) should be derived from the Memory Map. */ -#define CPUSS_SLOW_SL_PRESENT 1u -/* Number of external slaves directly connected to fast AHB-Lite infrastructure. - Maximum nubmer of slave supported is 4. Width of this parameter is 4-bits. - 1-bit mask for each slave indicating present or not. Example: 4'b0011 - slave - 0 and slave 1 are present. Note: The FAST_SLx_ADDR and FAST_SLx_MASK - parameters (for the slaves present) should be derived from the Memory Map. */ -#define CPUSS_FAST_SL_PRESENT 1u -/* Number of external masters driving the slow AHB-Lite infrastructure. Maximum - number of masters supported is 2. Width of this parameter is 2-bits. 1-bit - mask for each master indicating present or not. Example: 2'b01 - master 0 is - present. */ -#define CPUSS_SLOW_MS_PRESENT 3u -/* System interrupt functionality present or not ('0': no; '1': yes). Not used for - CM0+ PCU, which always uses system interrupt functionality. */ -#define CPUSS_SYSTEM_IRQ_PRESENT 0u -/* Number of total interrupt request inputs to CPUSS */ -#define CPUSS_SYSTEM_INT_NR 168u -/* Number of DeepSleep wakeup interrupt inputs to CPUSS */ -#define CPUSS_SYSTEM_DPSLP_INT_NR 39u -/* Width of the CM4 interrupt priority bits. Legal range [3,8] Example: 3 = 8 - levels of priority 8 = 256 levels of priority */ -#define CPUSS_CM4_LVL_WIDTH 3u -/* CM4 Floating point unit present or not (0=No, 1=Yes) */ -#define CPUSS_CM4_FPU_PRESENT 1u -/* Debug level. Legal range [0,3] (0= No support, 1= Minimum: CM0/4 both 2 - breakpoints +1 watchpoint, 2= Full debug: CM0/4 have 4/6 breakpoints, 2/4 - watchpoints and 0/2 literal compare, 3= Full debug + data matching) */ -#define CPUSS_DEBUG_LVL 3u -/* Trace level. Legal range [0,2] (0= No tracing, 1= ITM + TPIU + SWO, 2= ITM + - ETM + TPIU + SWO) Note: CM4 HTM is not supported. Hence vaule 3 for trace - level is not supported in CPUSS. */ -#define CPUSS_TRACE_LVL 2u -/* Embedded Trace Buffer present or not (0=No, 1=Yes) */ -#define CPUSS_ETB_PRESENT 0u -/* CM0+ MTB SRAM buffer size in kilobytes. Legal vaules 4, 8 or 16 */ -#define CPUSS_MTB_SRAM_SIZE 4u -/* CM4 ETB SRAM buffer size in kilobytes. Legal vaules 4, 8 or 16 */ -#define CPUSS_ETB_SRAM_SIZE 8u -/* PTM interface present (0=No, 1=Yes) */ -#define CPUSS_PTM_PRESENT 0u -/* Width of the PTM interface in bits ([2,32]) */ -#define CPUSS_PTM_WIDTH 1u -/* Width of the TPIU interface in bits ([1,4]) */ -#define CPUSS_TPIU_WIDTH 4u -/* CoreSight Part Identification Number */ -#define CPUSS_JEPID 52u -/* CoreSight Part Identification Number */ -#define CPUSS_JEPCONTINUATION 0u -/* CoreSight Part Identification Number */ -#define CPUSS_FAMILYID 258u -/* ROM trim register width (for ARM 3, for Synopsys 5) */ -#define CPUSS_ROM_TRIM_WIDTH 5u -/* ROM trim register default (for both ARM and Synopsys 0x0000_0012) */ -#define CPUSS_ROM_TRIM_DEFAULT 18u -/* RAM trim register width (for ARM 8, for Synopsys 15) */ -#define CPUSS_RAM_TRIM_WIDTH 15u -/* RAM trim register default (for ARM 0x0000_0062 and for Synopsys 0x0000_6012) */ -#define CPUSS_RAM_TRIM_DEFAULT 24594u -/* Cryptography IP present or not (0=No, 1=Yes) */ -#define CPUSS_CRYPTO_PRESENT 1u -/* DataWire and DMAC SW trigger per channel present or not ('0': no, '1': yes) */ -#define CPUSS_SW_TR_PRESENT 0u -/* DataWire 0 present or not (0=No, 1=Yes) */ -#define CPUSS_DW0_PRESENT 1u -/* Number of DataWire 0 channels (8, 16 or 32) */ -#define CPUSS_DW0_CH_NR 29u -/* DataWire 1 present or not (0=No, 1=Yes) */ -#define CPUSS_DW1_PRESENT 1u -/* Number of DataWire 1 channels (8, 16 or 32) */ -#define CPUSS_DW1_CH_NR 29u -/* DMA controller present or not ('0': no, '1': yes) */ -#define CPUSS_DMAC_PRESENT 1u -/* Number of DMA controller channels ([1, 8]) */ -#define CPUSS_DMAC_CH_NR 4u -/* Number of Flash BIST_DATA registers */ -#define CPUSS_FLASHC_FLASHC_BIST_DATA_NR 4u -/* Page size in # of 32-bit words (1: 4 bytes, 2: 8 bytes, ... */ -#define CPUSS_FLASHC_PA_SIZE 128u -/* SONOS Flash is used or not ('0': no, '1': yes) */ -#define CPUSS_FLASHC_FLASHC_IS_SONOS 1u -/* eCT Flash is used or not ('0': no, '1': yes) */ -#define CPUSS_FLASHC_FLASHC_IS_ECT 0u -/* Cryptography SRAMs ECC present or not ('0': no, '1': yes) */ -#define CPUSS_CRYPTO_ECC_PRESENT 0u -/* Cryptography SRAMs address ECC present or not ('0': no, '1': yes) */ -#define CPUSS_CRYPTO_ECC_ADDR_PRESENT 0u -/* AES cipher support ('0': no, '1': yes) */ -#define CPUSS_CRYPTO_AES 1u -/* (Tripple) DES cipher support ('0': no, '1': yes) */ -#define CPUSS_CRYPTO_DES 1u -/* Chacha support ('0': no, '1': yes) */ -#define CPUSS_CRYPTO_CHACHA 1u -/* Pseudo random number generation support ('0': no, '1': yes) */ -#define CPUSS_CRYPTO_PR 1u -/* SHA1 hash support ('0': no, '1': yes) */ -#define CPUSS_CRYPTO_SHA1 1u -/* SHA2 hash support ('0': no, '1': yes) */ -#define CPUSS_CRYPTO_SHA2 1u -/* SHA3 hash support ('0': no, '1': yes) */ -#define CPUSS_CRYPTO_SHA3 1u -/* Cyclic Redundancy Check support ('0': no, '1': yes) */ -#define CPUSS_CRYPTO_CRC 1u -/* True random number generation support ('0': no, '1': yes) */ -#define CPUSS_CRYPTO_TR 1u -/* Vector unit support ('0': no, '1': yes) */ -#define CPUSS_CRYPTO_VU 1u -/* Galios/Counter Mode (GCM) support ('0': no, '1': yes) */ -#define CPUSS_CRYPTO_GCM 1u -/* Number of 32-bit words in the IP internal memory buffer (from the set [64, 128, - 256, 512, 1024, 2048, 4096], to allow for a 256 B, 512 B, 1 kB, 2 kB, 4 kB, 8 - kB and 16 kB memory buffer) */ -#define CPUSS_CRYPTO_BUFF_SIZE 1024u -/* Number of fault structures. Legal range [1, 4] */ -#define CPUSS_FAULT_FAULT_NR 2u -/* Number of IPC structures. Legal range [1, 16] */ -#define CPUSS_IPC_IPC_NR 16u -/* Number of IPC interrupt structures. Legal range [1, 16] */ -#define CPUSS_IPC_IPC_IRQ_NR 16u -/* Master 0 protect contexts minus one */ -#define CPUSS_PROT_SMPU_MS0_PC_NR_MINUS1 7u -/* Master 1 protect contexts minus one */ -#define CPUSS_PROT_SMPU_MS1_PC_NR_MINUS1 0u -/* Master 2 protect contexts minus one */ -#define CPUSS_PROT_SMPU_MS2_PC_NR_MINUS1 0u -/* Master 3 protect contexts minus one */ -#define CPUSS_PROT_SMPU_MS3_PC_NR_MINUS1 0u -/* Master 4 protect contexts minus one */ -#define CPUSS_PROT_SMPU_MS4_PC_NR_MINUS1 0u -/* Master 5 protect contexts minus one */ -#define CPUSS_PROT_SMPU_MS5_PC_NR_MINUS1 7u -/* Master 6 protect contexts minus one */ -#define CPUSS_PROT_SMPU_MS6_PC_NR_MINUS1 7u -/* Master 7 protect contexts minus one */ -#define CPUSS_PROT_SMPU_MS7_PC_NR_MINUS1 0u -/* Master 8 protect contexts minus one */ -#define CPUSS_PROT_SMPU_MS8_PC_NR_MINUS1 0u -/* Master 9 protect contexts minus one */ -#define CPUSS_PROT_SMPU_MS9_PC_NR_MINUS1 0u -/* Master 10 protect contexts minus one */ -#define CPUSS_PROT_SMPU_MS10_PC_NR_MINUS1 0u -/* Master 11 protect contexts minus one */ -#define CPUSS_PROT_SMPU_MS11_PC_NR_MINUS1 0u -/* Master 12 protect contexts minus one */ -#define CPUSS_PROT_SMPU_MS12_PC_NR_MINUS1 0u -/* Master 13 protect contexts minus one */ -#define CPUSS_PROT_SMPU_MS13_PC_NR_MINUS1 0u -/* Master 14 protect contexts minus one */ -#define CPUSS_PROT_SMPU_MS14_PC_NR_MINUS1 7u -/* Master 15 protect contexts minus one */ -#define CPUSS_PROT_SMPU_MS15_PC_NR_MINUS1 7u -/* Number of SMPU protection structures */ -#define CPUSS_PROT_SMPU_STRUCT_NR 16u -/* Number of protection contexts supported minus 1. Legal range [1,16] */ -#define CPUSS_SMPU_STRUCT_PC_NR_MINUS1 7u -/* Number of DataWire controllers present (max 2) */ -#define CPUSS_DW_NR 2u -/* DataWire SRAMs ECC present or not ('0': no, '1': yes) */ -#define CPUSS_DW_ECC_PRESENT 0u -/* DataWire SW trigger per channel present or not ('0': no, '1': yes) */ -#define CPUSS_CH_STRUCT_SW_TR_PRESENT 0u -/* Number of DataWire controllers present (max 2) (same as DW.NR above) */ -#define CPUSS_CPUSS_DW_DW_NR 2u -/* Number of channels in each DataWire controller */ -#define CPUSS_CPUSS_DW_DW_NR0_DW_CH_NR 29u -/* Width of a channel number in bits */ -#define CPUSS_CPUSS_DW_DW_NR0_DW_CH_NR_WIDTH 5u -/* Number of channels in each DataWire controller */ -#define CPUSS_CPUSS_DW_DW_NR1_DW_CH_NR 29u -/* Width of a channel number in bits */ -#define CPUSS_CPUSS_DW_DW_NR1_DW_CH_NR_WIDTH 5u -/* Number of DMA controller channels ([1, 8]) */ -#define CPUSS_DMAC_CH_NR 4u -/* DMAC SW trigger per channel present or not ('0': no, '1': yes) */ -#define CPUSS_CH_SW_TR_PRESENT 0u -/* See MMIO2 instantiation or not */ -#define CPUSS_CHIP_TOP_PROFILER_PRESENT 1u -/* ETAS Calibration support pin out present (automotive only) */ -#define CPUSS_CHIP_TOP_CAL_SUP_NZ_PRESENT 0u -/* TRACE_LVL>0 */ -#define CPUSS_CHIP_TOP_TRACE_PRESENT 1u /* Number of profiling counters. Legal range [1, 32] */ #define PROFILE_PRFL_CNT_NR 8u /* Number of monitor event signals. Legal range [1, 128] */ #define PROFILE_PRFL_MONITOR_NR 128u -/* Number of instantiated eFUSE macros (256 bit macros). Legal range [1, 16] */ -#define EFUSE_EFUSE_NR 4u -/* SONOS Flash is used or not ('0': no, '1': yes) */ -#define SFLASH_FLASHC_IS_SONOS 1u -/* CPUSS_WOUNDING_PRESENT or not ('0': no, '1': yes) */ -#define SFLASH_CPUSS_WOUNDING_PRESENT 0u /* DeepSleep support ('0':no, '1': yes) */ #define SCB0_DEEPSLEEP 0u /* Externally clocked support? ('0': no, '1': yes) */ @@ -3138,7 +3116,7 @@ typedef I2S_V1_Type I2S_Type; /* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ #define SCB1_I2C_FAST_PLUS 1u /* Number of used spi_select signals (max 4) */ -#define SCB1_CHIP_TOP_SPI_SEL_NR 3u +#define SCB1_CHIP_TOP_SPI_SEL_NR 4u /* DeepSleep support ('0':no, '1': yes) */ #define SCB2_DEEPSLEEP 0u /* Externally clocked support? ('0': no, '1': yes) */ @@ -3188,7 +3166,7 @@ typedef I2S_V1_Type I2S_Type; /* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ #define SCB2_I2C_FAST_PLUS 1u /* Number of used spi_select signals (max 4) */ -#define SCB2_CHIP_TOP_SPI_SEL_NR 3u +#define SCB2_CHIP_TOP_SPI_SEL_NR 4u /* DeepSleep support ('0':no, '1': yes) */ #define SCB3_DEEPSLEEP 0u /* Externally clocked support? ('0': no, '1': yes) */ @@ -3238,7 +3216,7 @@ typedef I2S_V1_Type I2S_Type; /* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ #define SCB3_I2C_FAST_PLUS 1u /* Number of used spi_select signals (max 4) */ -#define SCB3_CHIP_TOP_SPI_SEL_NR 3u +#define SCB3_CHIP_TOP_SPI_SEL_NR 4u /* DeepSleep support ('0':no, '1': yes) */ #define SCB4_DEEPSLEEP 0u /* Externally clocked support? ('0': no, '1': yes) */ @@ -3288,7 +3266,7 @@ typedef I2S_V1_Type I2S_Type; /* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ #define SCB4_I2C_FAST_PLUS 1u /* Number of used spi_select signals (max 4) */ -#define SCB4_CHIP_TOP_SPI_SEL_NR 3u +#define SCB4_CHIP_TOP_SPI_SEL_NR 4u /* DeepSleep support ('0':no, '1': yes) */ #define SCB5_DEEPSLEEP 0u /* Externally clocked support? ('0': no, '1': yes) */ @@ -3338,7 +3316,7 @@ typedef I2S_V1_Type I2S_Type; /* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ #define SCB5_I2C_FAST_PLUS 1u /* Number of used spi_select signals (max 4) */ -#define SCB5_CHIP_TOP_SPI_SEL_NR 3u +#define SCB5_CHIP_TOP_SPI_SEL_NR 4u /* DeepSleep support ('0':no, '1': yes) */ #define SCB6_DEEPSLEEP 0u /* Externally clocked support? ('0': no, '1': yes) */ @@ -3388,7 +3366,7 @@ typedef I2S_V1_Type I2S_Type; /* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ #define SCB6_I2C_FAST_PLUS 1u /* Number of used spi_select signals (max 4) */ -#define SCB6_CHIP_TOP_SPI_SEL_NR 3u +#define SCB6_CHIP_TOP_SPI_SEL_NR 4u /* DeepSleep support ('0':no, '1': yes) */ #define SCB7_DEEPSLEEP 0u /* Externally clocked support? ('0': no, '1': yes) */ @@ -3689,55 +3667,92 @@ typedef I2S_V1_Type I2S_Type; #define SCB12_I2C_FAST_PLUS 1u /* Number of used spi_select signals (max 4) */ #define SCB12_CHIP_TOP_SPI_SEL_NR 0u -/* Number of counters per IP (1..32) */ -#define TCPWM0_CNT_NR 8u -/* Counter width (in number of bits) */ -#define TCPWM0_CNT_CNT_WIDTH 32u -/* Number of counters per IP (1..32) */ -#define TCPWM1_CNT_NR 24u -/* Counter width (in number of bits) */ -#define TCPWM1_CNT_CNT_WIDTH 16u -/* Number of ports supoprting up to 4 COMs */ -#define LCD_NUMPORTS 8u -/* Number of ports supporting up to 8 COMs */ -#define LCD_NUMPORTS8 8u -/* Number of ports supporting up to 16 COMs */ -#define LCD_NUMPORTS16 0u -/* Max number of LCD commons supported */ -#define LCD_CHIP_TOP_COM_NR 8u -/* Max number of LCD pins (total) supported */ -#define LCD_CHIP_TOP_PIN_NR 62u -/* Number of IREF outputs from AREF */ -#define PASS_NR_IREFS 4u -/* Number of CTBs in the Subsystem */ -#define PASS_NR_CTBS 0u -/* Number of CTDACs in the Subsystem */ -#define PASS_NR_CTDACS 0u -/* CTB0 Exists */ -#define PASS_CTB0_EXISTS 0u -/* CTB1 Exists */ -#define PASS_CTB1_EXISTS 0u -/* CTB2 Exists */ -#define PASS_CTB2_EXISTS 0u -/* CTB3 Exists */ -#define PASS_CTB3_EXISTS 0u -/* CTDAC0 Exists */ -#define PASS_CTDAC0_EXISTS 0u -/* CTDAC1 Exists */ -#define PASS_CTDAC1_EXISTS 0u -/* CTDAC2 Exists */ -#define PASS_CTDAC2_EXISTS 0u -/* CTDAC3 Exists */ -#define PASS_CTDAC3_EXISTS 0u -/* Number of SAR channels */ -#define PASS_SAR_SAR_CHANNELS 16u -/* Averaging logic present in SAR */ -#define PASS_SAR_SAR_AVERAGE 1u -/* Range detect logic present in SAR */ -#define PASS_SAR_SAR_RANGEDET 1u -/* Support for UAB sampling */ -#define PASS_SAR_SAR_UAB 0u -#define PASS_CTBM_CTDAC_PRESENT 0u +/* Basically the max packet size, which gets double buffered in RAM 0: 512B + (implies 1KB of RAM space for data) 1: 1KB (implies 2KB of RAM space for + data) */ +#define SDHC0_MAX_BLK_SIZE 0u +/* 0: No Command Queuing Engine present 1: Command Queuing Engine present; this + adds 288 bytes of space to the RAM for this purpose. */ +#define SDHC0_CQE_PRESENT 0u +/* 0: no retention of any SDHC_CORE regs 1: retention of SDHC_CORE regs that have + the Retention flag (Note, CTL.ENABLE is always retained irrespective of this + parameter) */ +#define SDHC0_RETENTION_PRESENT 1u +/* Chip top connect all 8 data pins (0= connect 4 data pins, 1= connect 8 data + pins) */ +#define SDHC0_CHIP_TOP_DATA8_PRESENT 0u +/* Chip top connect card_detect */ +#define SDHC0_CHIP_TOP_CARD_DETECT_PRESENT 1u +/* Chip top connect card_mech_write_prot_in */ +#define SDHC0_CHIP_TOP_CARD_WRITE_PROT_PRESENT 1u +/* Chip top connect led_ctrl_out and led_ctrl_out_en */ +#define SDHC0_CHIP_TOP_LED_CTRL_PRESENT 0u +/* Chip top connect io_volt_sel_out and io_volt_sel_out_en */ +#define SDHC0_CHIP_TOP_IO_VOLT_SEL_PRESENT 1u +/* Chip top connect io_drive_strength_out and io_drive_strength_out_en */ +#define SDHC0_CHIP_TOP_IO_DRIVE_STRENGTH_PRESENT 0u +/* Chip top connect card_if_pwr_en_out and card_if_pwr_en_out_en */ +#define SDHC0_CHIP_TOP_CARD_IF_PWR_EN_PRESENT 1u +/* Chip top connect card_emmc_reset_n_out and card_emmc_reset_n_out_en */ +#define SDHC0_CHIP_TOP_CARD_EMMC_RESET_PRESENT 0u +/* Chip top connect interrupt_wakeup (not used for eMMC) */ +#define SDHC0_CHIP_TOP_INTERRUPT_WAKEUP_PRESENT 1u +/* Basically the max packet size, which gets double buffered in RAM 0: 512B + (implies 1KB of RAM space for data) 1: 1KB (implies 2KB of RAM space for + data) */ +#define SDHC0_CORE_MAX_BLK_SIZE 0u +/* 0: No Command Queuing Engine present 1: Command Queuing Engine present; this + adds 288 bytes of space to the RAM for this purpose. */ +#define SDHC0_CORE_CQE_PRESENT 0u +/* 0: no retention of any SDHC_CORE regs 1: retention of SDHC_CORE regs that have + the Retention flag (Note, CTL.ENABLE is always retained irrespective of this + parameter) */ +#define SDHC0_CORE_RETENTION_PRESENT 1u +/* Basically the max packet size, which gets double buffered in RAM 0: 512B + (implies 1KB of RAM space for data) 1: 1KB (implies 2KB of RAM space for + data) */ +#define SDHC1_MAX_BLK_SIZE 0u +/* 0: No Command Queuing Engine present 1: Command Queuing Engine present; this + adds 288 bytes of space to the RAM for this purpose. */ +#define SDHC1_CQE_PRESENT 0u +/* 0: no retention of any SDHC_CORE regs 1: retention of SDHC_CORE regs that have + the Retention flag (Note, CTL.ENABLE is always retained irrespective of this + parameter) */ +#define SDHC1_RETENTION_PRESENT 1u +/* Chip top connect all 8 data pins (0= connect 4 data pins, 1= connect 8 data + pins) */ +#define SDHC1_CHIP_TOP_DATA8_PRESENT 1u +/* Chip top connect card_detect */ +#define SDHC1_CHIP_TOP_CARD_DETECT_PRESENT 1u +/* Chip top connect card_mech_write_prot_in */ +#define SDHC1_CHIP_TOP_CARD_WRITE_PROT_PRESENT 1u +/* Chip top connect led_ctrl_out and led_ctrl_out_en */ +#define SDHC1_CHIP_TOP_LED_CTRL_PRESENT 1u +/* Chip top connect io_volt_sel_out and io_volt_sel_out_en */ +#define SDHC1_CHIP_TOP_IO_VOLT_SEL_PRESENT 1u +/* Chip top connect io_drive_strength_out and io_drive_strength_out_en */ +#define SDHC1_CHIP_TOP_IO_DRIVE_STRENGTH_PRESENT 0u +/* Chip top connect card_if_pwr_en_out and card_if_pwr_en_out_en */ +#define SDHC1_CHIP_TOP_CARD_IF_PWR_EN_PRESENT 1u +/* Chip top connect card_emmc_reset_n_out and card_emmc_reset_n_out_en */ +#define SDHC1_CHIP_TOP_CARD_EMMC_RESET_PRESENT 1u +/* Chip top connect interrupt_wakeup (not used for eMMC) */ +#define SDHC1_CHIP_TOP_INTERRUPT_WAKEUP_PRESENT 1u +/* Basically the max packet size, which gets double buffered in RAM 0: 512B + (implies 1KB of RAM space for data) 1: 1KB (implies 2KB of RAM space for + data) */ +#define SDHC1_CORE_MAX_BLK_SIZE 0u +/* 0: No Command Queuing Engine present 1: Command Queuing Engine present; this + adds 288 bytes of space to the RAM for this purpose. */ +#define SDHC1_CORE_CQE_PRESENT 0u +/* 0: no retention of any SDHC_CORE regs 1: retention of SDHC_CORE regs that have + the Retention flag (Note, CTL.ENABLE is always retained irrespective of this + parameter) */ +#define SDHC1_CORE_RETENTION_PRESENT 1u +/* SONOS Flash is used or not ('0': no, '1': yes) */ +#define SFLASH_FLASHC_IS_SONOS 1u +/* CPUSS_WOUNDING_PRESENT or not ('0': no, '1': yes) */ +#define SFLASH_CPUSS_WOUNDING_PRESENT 0u /* Base address of the SMIF XIP memory region. This address must be a multiple of the SMIF XIP memory capacity. This address must be a multiple of 64 KB. This address must be in the [0x0000:0000, 0x1fff:ffff] memory region. The XIP @@ -3763,96 +3778,81 @@ typedef I2S_V1_Type I2S_Type; #define SMIF_CHIP_TOP_DATA8_PRESENT 1u /* Number of used spi_select signals (max 4) */ #define SMIF_CHIP_TOP_SPI_SEL_NR 4u -/* I2S capable? (0=No,1=Yes) */ -#define AUDIOSS0_I2S 1u -/* PDM capable? (0=No,1=Yes) */ -#define AUDIOSS0_PDM 1u -/* I2S capable? (0=No,1=Yes) */ -#define AUDIOSS1_I2S 1u -/* PDM capable? (0=No,1=Yes) */ -#define AUDIOSS1_PDM 0u -/* Basically the max packet size, which gets double buffered in RAM 0: 512B - (implies 1KB of RAM space for data) 1: 1KB (implies 2KB of RAM space for - data) */ -#define SDHC0_MAX_BLK_SIZE 0u -/* 0: No Command Queuing Engine present 1: Command Queuing Engine present; this - adds 288 bytes of space to the RAM for this purpose. */ -#define SDHC0_CQE_PRESENT 0u -/* 0: no retention of any SDHC_CORE regs 1: retention of SDHC_CORE regs that have - the Retention flag (Note, CTL.ENABLE is always retained irrespective of this - parameter) */ -#define SDHC0_RETENTION_PRESENT 1u -/* Basically the max packet size, which gets double buffered in RAM 0: 512B - (implies 1KB of RAM space for data) 1: 1KB (implies 2KB of RAM space for - data) */ -#define SDHC0_CORE_MAX_BLK_SIZE 0u -/* 0: No Command Queuing Engine present 1: Command Queuing Engine present; this - adds 288 bytes of space to the RAM for this purpose. */ -#define SDHC0_CORE_CQE_PRESENT 0u -/* 0: no retention of any SDHC_CORE regs 1: retention of SDHC_CORE regs that have - the Retention flag (Note, CTL.ENABLE is always retained irrespective of this - parameter) */ -#define SDHC0_CORE_RETENTION_PRESENT 1u -/* Chip top connect all 8 data pins (0= connect 4 data pins, 1= connect 8 data - pins) */ -#define SDHC0_CHIP_TOP_DATA8_PRESENT 0u -/* Chip top connect card_detect */ -#define SDHC0_CHIP_TOP_CARD_DETECT_PRESENT 1u -/* Chip top connect card_mech_write_prot_in */ -#define SDHC0_CHIP_TOP_CARD_WRITE_PROT_PRESENT 1u -/* Chip top connect led_ctrl_out and led_ctrl_out_en */ -#define SDHC0_CHIP_TOP_LED_CTRL_PRESENT 0u -/* Chip top connect io_volt_sel_out and io_volt_sel_out_en */ -#define SDHC0_CHIP_TOP_IO_VOLT_SEL_PRESENT 1u -/* Chip top connect io_drive_strength_out and io_drive_strength_out_en */ -#define SDHC0_CHIP_TOP_IO_DRIVE_STRENGTH_PRESENT 0u -/* Chip top connect card_if_pwr_en_out and card_if_pwr_en_out_en */ -#define SDHC0_CHIP_TOP_CARD_IF_PWR_EN_PRESENT 1u -/* Chip top connect card_emmc_reset_n_out and card_emmc_reset_n_out_en */ -#define SDHC0_CHIP_TOP_CARD_EMMC_RESET_PRESENT 0u -/* Chip top connect interrupt_wakeup (not used for eMMC) */ -#define SDHC0_CHIP_TOP_INTERRUPT_WAKEUP_PRESENT 1u -/* Basically the max packet size, which gets double buffered in RAM 0: 512B - (implies 1KB of RAM space for data) 1: 1KB (implies 2KB of RAM space for - data) */ -#define SDHC1_MAX_BLK_SIZE 0u -/* 0: No Command Queuing Engine present 1: Command Queuing Engine present; this - adds 288 bytes of space to the RAM for this purpose. */ -#define SDHC1_CQE_PRESENT 0u -/* 0: no retention of any SDHC_CORE regs 1: retention of SDHC_CORE regs that have - the Retention flag (Note, CTL.ENABLE is always retained irrespective of this - parameter) */ -#define SDHC1_RETENTION_PRESENT 1u -/* Basically the max packet size, which gets double buffered in RAM 0: 512B - (implies 1KB of RAM space for data) 1: 1KB (implies 2KB of RAM space for - data) */ -#define SDHC1_CORE_MAX_BLK_SIZE 0u -/* 0: No Command Queuing Engine present 1: Command Queuing Engine present; this - adds 288 bytes of space to the RAM for this purpose. */ -#define SDHC1_CORE_CQE_PRESENT 0u -/* 0: no retention of any SDHC_CORE regs 1: retention of SDHC_CORE regs that have - the Retention flag (Note, CTL.ENABLE is always retained irrespective of this - parameter) */ -#define SDHC1_CORE_RETENTION_PRESENT 1u -/* Chip top connect all 8 data pins (0= connect 4 data pins, 1= connect 8 data - pins) */ -#define SDHC1_CHIP_TOP_DATA8_PRESENT 1u -/* Chip top connect card_detect */ -#define SDHC1_CHIP_TOP_CARD_DETECT_PRESENT 1u -/* Chip top connect card_mech_write_prot_in */ -#define SDHC1_CHIP_TOP_CARD_WRITE_PROT_PRESENT 1u -/* Chip top connect led_ctrl_out and led_ctrl_out_en */ -#define SDHC1_CHIP_TOP_LED_CTRL_PRESENT 1u -/* Chip top connect io_volt_sel_out and io_volt_sel_out_en */ -#define SDHC1_CHIP_TOP_IO_VOLT_SEL_PRESENT 1u -/* Chip top connect io_drive_strength_out and io_drive_strength_out_en */ -#define SDHC1_CHIP_TOP_IO_DRIVE_STRENGTH_PRESENT 0u -/* Chip top connect card_if_pwr_en_out and card_if_pwr_en_out_en */ -#define SDHC1_CHIP_TOP_CARD_IF_PWR_EN_PRESENT 1u -/* Chip top connect card_emmc_reset_n_out and card_emmc_reset_n_out_en */ -#define SDHC1_CHIP_TOP_CARD_EMMC_RESET_PRESENT 1u -/* Chip top connect interrupt_wakeup (not used for eMMC) */ -#define SDHC1_CHIP_TOP_INTERRUPT_WAKEUP_PRESENT 1u +/* Number of regulator modules instantiated within SRSS, start with estimate, + update after CMR feedback */ +#define SRSS_NUM_ACTREG_PWRMOD 2u +/* Number of shorting switches between vccd and vccact (target dynamic voltage + drop < 10mV) */ +#define SRSS_NUM_ACTIVE_SWITCH 3u +/* ULP linear regulator system is present */ +#define SRSS_ULPLINREG_PRESENT 1u +/* HT linear regulator system is present */ +#define SRSS_HTLINREG_PRESENT 0u +/* Low-current buck regulator present. Can be derived from S40S_SISOBUCKLC_PRESENT + or SIMOBUCK_PRESENT. */ +#define SRSS_BUCKCTL_PRESENT 1u +/* Low-current SISO buck core regulator is present. Only compatible with ULP + linear regulator system (ULPLINREG_PRESENT==1). */ +#define SRSS_S40S_SISOBUCKLC_PRESENT 1u +/* SIMO buck core regulator is present. Only compatible with ULP linear regulator + system (ULPLINREG_PRESENT==1). */ +#define SRSS_SIMOBUCK_PRESENT 0u +/* Precision ILO (PILO) is present */ +#define SRSS_PILO_PRESENT 0u +/* External Crystal Oscillator is present (high frequency) */ +#define SRSS_ECO_PRESENT 1u +/* System Buck-Boost is present */ +#define SRSS_SYSBB_PRESENT 0u +/* Number of clock paths. Must be > 0 */ +#define SRSS_NUM_CLKPATH 6u +/* Number of PLLs present. Must be <= NUM_CLKPATH */ +#define SRSS_NUM_PLL 2u +/* Number of HFCLK roots present. Must be > 0 */ +#define SRSS_NUM_HFROOT 6u +/* Number of PWR_HIB_DATA registers, should not be needed if BACKUP_PRESENT */ +#define SRSS_NUM_HIBDATA 1u +/* Backup domain is present (includes RTC and WCO) */ +#define SRSS_BACKUP_PRESENT 1u +/* Mask of HFCLK root clock supervisors (CSV). For each clock root i, bit[i] of + mask indicates presence of a CSV. */ +#define SRSS_MASK_HFCSV 0u +/* Clock supervisor is present on WCO. Must be 0 if BACKUP_PRESENT==0. */ +#define SRSS_WCOCSV_PRESENT 0u +/* Number of software watchdog timers. */ +#define SRSS_NUM_MCWDT 2u +/* Number of DSI inputs into clock muxes. This is used for logic optimization. */ +#define SRSS_NUM_DSI 0u +/* Alternate high-frequency clock is present. This is used for logic optimization. */ +#define SRSS_ALTHF_PRESENT 0u +/* Alternate low-frequency clock is present. This is used for logic optimization. */ +#define SRSS_ALTLF_PRESENT 0u +/* Use the hardened clkactfllmux block */ +#define SRSS_USE_HARD_CLKACTFLLMUX 1u +/* Number of clock paths, including direct paths in hardened clkactfllmux block + (Must be >= NUM_CLKPATH) */ +#define SRSS_HARD_CLKPATH 6u +/* Number of clock paths with muxes in hardened clkactfllmux block (Must be >= + NUM_PLL+1) */ +#define SRSS_HARD_CLKPATHMUX 6u +/* Number of HFCLKS present in hardened clkactfllmux block (Must be >= NUM_HFROOT) */ +#define SRSS_HARD_HFROOT 6u +/* ECO mux is present in hardened clkactfllmux block (Must be >= ECO_PRESENT) */ +#define SRSS_HARD_ECOMUX_PRESENT 1u +/* ALTHF mux is present in hardened clkactfllmux block (Must be >= ALTHF_PRESENT) */ +#define SRSS_HARD_ALTHFMUX_PRESENT 1u +/* Backup memory is present (only used when BACKUP_PRESENT==1) */ +#define SRSS_BACKUP_BMEM_PRESENT 0u +/* Number of Backup registers to include (each is 32b). Only used when + BACKUP_PRESENT==1. */ +#define SRSS_BACKUP_NUM_BREG 16u +/* Number of counters per IP (1..32) */ +#define TCPWM0_CNT_NR 8u +/* Counter width (in number of bits) */ +#define TCPWM0_CNT_CNT_WIDTH 32u +/* Number of counters per IP (1..32) */ +#define TCPWM1_CNT_NR 24u +/* Counter width (in number of bits) */ +#define TCPWM1_CNT_CNT_WIDTH 16u /* MMIO Targets Defines */ #define CY_MMIO_CRYPTO_GROUP_NR 1u diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/psoc6_03_config.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/psoc6_03_config.h index 2d00cd97ce..31cc4ea980 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/psoc6_03_config.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/psoc6_03_config.h @@ -5,7 +5,7 @@ * PSoC6_03 device configuration header * * \note -* Generator version: 1.6.0.111 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -1058,12 +1058,6 @@ typedef enum TRIG_OUT_1TO1_4_CAN_FIFO1_TO_PDMA1_TR_IN31 = 0x40001402u /* From canfd[0].tr_fifo1[0] to cpuss.dw1_tr_in[31] */ } en_trig_output_1to1_can_dw_tr_t; -/* Trigger Output Group 7 - Acknowledge dma request triggers from DW0 to CAN (OneToOne) */ -typedef enum -{ - TRIG_OUT_1TO1_7_PDMA1_TR_OUT29_ACK_TO_CAN_0 = 0x40001700u /* From cpuss.dw1_tr_out[29] to canfd[0].tr_dbg_dma_ack[0] */ -} en_trig_output_1to1_can0_dw_ack_t; - /* Trigger Output Group 5 - USB PDMA0 Triggers (OneToOne) */ typedef enum { @@ -1090,6 +1084,12 @@ typedef enum TRIG_OUT_1TO1_6_PDMA0_TR_OUT15_TO_USB_ACK7 = 0x40001607u /* From cpuss.dw0_tr_out[15] to usb.dma_burstend[7] */ } en_trig_output_1to1_usb_pdma0_ack_tr_t; +/* Trigger Output Group 7 - Acknowledge dma request triggers from DW0 to CAN (OneToOne) */ +typedef enum +{ + TRIG_OUT_1TO1_7_PDMA1_TR_OUT29_ACK_TO_CAN_0 = 0x40001700u /* From cpuss.dw1_tr_out[29] to canfd[0].tr_dbg_dma_ack[0] */ +} en_trig_output_1to1_can0_dw_ack_t; + /* Level or edge detection setting for a trigger mux */ typedef enum { @@ -1101,59 +1101,59 @@ typedef enum } en_trig_type_t; /* Trigger Type Defines */ -/* TCPWM Trigger Types */ -#define TRIGGER_TYPE_TCPWM_LINE TRIGGER_TYPE_LEVEL -#define TRIGGER_TYPE_TCPWM_LINE_COMPL TRIGGER_TYPE_LEVEL -#define TRIGGER_TYPE_TCPWM_TR_OVERFLOW TRIGGER_TYPE_EDGE -#define TRIGGER_TYPE_TCPWM_TR_COMPARE_MATCH TRIGGER_TYPE_EDGE -#define TRIGGER_TYPE_TCPWM_TR_UNDERFLOW TRIGGER_TYPE_EDGE -#define TRIGGER_TYPE_TCPWM_TR_IN__LEVEL TRIGGER_TYPE_LEVEL -#define TRIGGER_TYPE_TCPWM_TR_IN__EDGE TRIGGER_TYPE_EDGE +/* CANFD Trigger Types */ +#define TRIGGER_TYPE_CANFD_TR_DBG_DMA_ACK TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_CANFD_TR_DBG_DMA_REQ TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_CANFD_TR_EVT_SWT_IN TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_CANFD_TR_FIFO0 TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_CANFD_TR_FIFO1 TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_CANFD_TR_TMP_RTP_OUT TRIGGER_TYPE_EDGE +/* CPUSS Trigger Types */ +#define TRIGGER_TYPE_CPUSS_CTI_TR_IN TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_CPUSS_CTI_TR_OUT TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_CPUSS_DMAC_TR_IN__LEVEL TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_CPUSS_DMAC_TR_IN__EDGE TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_CPUSS_DMAC_TR_OUT TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_CPUSS_DW0_TR_IN__LEVEL TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_CPUSS_DW0_TR_IN__EDGE TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_CPUSS_DW0_TR_OUT TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_CPUSS_DW1_TR_IN__LEVEL TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_CPUSS_DW1_TR_IN__EDGE TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_CPUSS_DW1_TR_OUT TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_CPUSS_TR_FAULT TRIGGER_TYPE_EDGE /* CSD Trigger Types */ #define TRIGGER_TYPE_CSD_DSI_SAMPLE_OUT TRIGGER_TYPE_EDGE -/* SCB Trigger Types */ -#define TRIGGER_TYPE_SCB_TR_I2C_SCL_FILTERED TRIGGER_TYPE_LEVEL -#define TRIGGER_TYPE_SCB_TR_TX_REQ TRIGGER_TYPE_LEVEL -#define TRIGGER_TYPE_SCB_TR_RX_REQ TRIGGER_TYPE_LEVEL +/* LPCOMP Trigger Types */ +#define TRIGGER_TYPE_LPCOMP_DSI_COMP0 TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_LPCOMP_DSI_COMP1 TRIGGER_TYPE_LEVEL +/* PASS Trigger Types */ +#define TRIGGER_TYPE_PASS_TR_SAR_IN__LEVEL TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_PASS_TR_SAR_IN__EDGE TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_PASS_TR_SAR_OUT TRIGGER_TYPE_EDGE /* PERI Trigger Types */ +#define TRIGGER_TYPE_PERI_TR_DBG_FREEZE TRIGGER_TYPE_LEVEL #define TRIGGER_TYPE_PERI_TR_IO_INPUT__LEVEL TRIGGER_TYPE_LEVEL #define TRIGGER_TYPE_PERI_TR_IO_INPUT__EDGE TRIGGER_TYPE_EDGE #define TRIGGER_TYPE_PERI_TR_IO_OUTPUT__LEVEL TRIGGER_TYPE_LEVEL #define TRIGGER_TYPE_PERI_TR_IO_OUTPUT__EDGE TRIGGER_TYPE_EDGE -#define TRIGGER_TYPE_PERI_TR_DBG_FREEZE TRIGGER_TYPE_LEVEL -/* CPUSS Trigger Types */ -#define TRIGGER_TYPE_CPUSS_DW0_TR_IN__LEVEL TRIGGER_TYPE_LEVEL -#define TRIGGER_TYPE_CPUSS_DW0_TR_IN__EDGE TRIGGER_TYPE_EDGE -#define TRIGGER_TYPE_CPUSS_DW1_TR_IN__LEVEL TRIGGER_TYPE_LEVEL -#define TRIGGER_TYPE_CPUSS_DW1_TR_IN__EDGE TRIGGER_TYPE_EDGE -#define TRIGGER_TYPE_CPUSS_DMAC_TR_IN__LEVEL TRIGGER_TYPE_LEVEL -#define TRIGGER_TYPE_CPUSS_DMAC_TR_IN__EDGE TRIGGER_TYPE_EDGE -#define TRIGGER_TYPE_CPUSS_DW0_TR_OUT TRIGGER_TYPE_EDGE -#define TRIGGER_TYPE_CPUSS_DW1_TR_OUT TRIGGER_TYPE_EDGE -#define TRIGGER_TYPE_CPUSS_DMAC_TR_OUT TRIGGER_TYPE_EDGE -#define TRIGGER_TYPE_CPUSS_CTI_TR_OUT TRIGGER_TYPE_EDGE -#define TRIGGER_TYPE_CPUSS_TR_FAULT TRIGGER_TYPE_EDGE -#define TRIGGER_TYPE_CPUSS_CTI_TR_IN TRIGGER_TYPE_EDGE -/* CANFD Trigger Types */ -#define TRIGGER_TYPE_CANFD_TR_TMP_RTP_OUT TRIGGER_TYPE_EDGE -#define TRIGGER_TYPE_CANFD_TR_EVT_SWT_IN TRIGGER_TYPE_EDGE -#define TRIGGER_TYPE_CANFD_TR_DBG_DMA_REQ TRIGGER_TYPE_LEVEL -#define TRIGGER_TYPE_CANFD_TR_FIFO0 TRIGGER_TYPE_LEVEL -#define TRIGGER_TYPE_CANFD_TR_FIFO1 TRIGGER_TYPE_LEVEL -#define TRIGGER_TYPE_CANFD_TR_DBG_DMA_ACK TRIGGER_TYPE_EDGE -/* LPCOMP Trigger Types */ -#define TRIGGER_TYPE_LPCOMP_DSI_COMP0 TRIGGER_TYPE_LEVEL -#define TRIGGER_TYPE_LPCOMP_DSI_COMP1 TRIGGER_TYPE_LEVEL +/* SCB Trigger Types */ +#define TRIGGER_TYPE_SCB_TR_I2C_SCL_FILTERED TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_SCB_TR_RX_REQ TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_SCB_TR_TX_REQ TRIGGER_TYPE_LEVEL /* SMIF Trigger Types */ -#define TRIGGER_TYPE_SMIF_TR_TX_REQ TRIGGER_TYPE_LEVEL #define TRIGGER_TYPE_SMIF_TR_RX_REQ TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_SMIF_TR_TX_REQ TRIGGER_TYPE_LEVEL +/* TCPWM Trigger Types */ +#define TRIGGER_TYPE_TCPWM_LINE TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_TCPWM_LINE_COMPL TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_TCPWM_TR_COMPARE_MATCH TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_TCPWM_TR_IN__LEVEL TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_TCPWM_TR_IN__EDGE TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_TCPWM_TR_OVERFLOW TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_TCPWM_TR_UNDERFLOW TRIGGER_TYPE_EDGE /* USB Trigger Types */ -#define TRIGGER_TYPE_USB_DMA_REQ TRIGGER_TYPE_EDGE #define TRIGGER_TYPE_USB_DMA_BURSTEND TRIGGER_TYPE_EDGE -/* PASS Trigger Types */ -#define TRIGGER_TYPE_PASS_TR_SAR_OUT TRIGGER_TYPE_EDGE -#define TRIGGER_TYPE_PASS_TR_SAR_IN__LEVEL TRIGGER_TYPE_LEVEL -#define TRIGGER_TYPE_PASS_TR_SAR_IN__EDGE TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_USB_DMA_REQ TRIGGER_TYPE_EDGE /* Bus masters */ typedef enum @@ -1267,92 +1267,273 @@ typedef PASS_AREF_V1_Type PASS_AREF_Type; typedef PASS_V1_Type PASS_Type; /* Parameter Defines */ -/* Number of regulator modules instantiated within SRSS, start with estimate, - update after CMR feedback */ -#define SRSS_NUM_ACTREG_PWRMOD 2u -/* Number of shorting switches between vccd and vccact (target dynamic voltage - drop < 10mV) */ -#define SRSS_NUM_ACTIVE_SWITCH 3u -/* ULP linear regulator system is present */ -#define SRSS_ULPLINREG_PRESENT 1u -/* HT linear regulator system is present */ -#define SRSS_HTLINREG_PRESENT 0u -/* Low-current buck regulator present. Can be derived from S40S_SISOBUCKLC_PRESENT - or SIMOBUCK_PRESENT. */ -#define SRSS_BUCKCTL_PRESENT 1u -/* Low-current SISO buck core regulator is present. Only compatible with ULP - linear regulator system (ULPLINREG_PRESENT==1). */ -#define SRSS_S40S_SISOBUCKLC_PRESENT 1u -/* SIMO buck core regulator is present. Only compatible with ULP linear regulator - system (ULPLINREG_PRESENT==1). */ -#define SRSS_SIMOBUCK_PRESENT 0u -/* Precision ILO (PILO) is present */ -#define SRSS_PILO_PRESENT 0u -/* External Crystal Oscillator is present (high frequency) */ -#define SRSS_ECO_PRESENT 1u -/* System Buck-Boost is present */ -#define SRSS_SYSBB_PRESENT 0u -/* Number of clock paths. Must be > 0 */ -#define SRSS_NUM_CLKPATH 5u -/* Number of PLLs present. Must be <= NUM_CLKPATH */ -#define SRSS_NUM_PLL 1u -/* Number of HFCLK roots present. Must be > 0 */ -#define SRSS_NUM_HFROOT 5u -/* Number of PWR_HIB_DATA registers, should not be needed if BACKUP_PRESENT */ -#define SRSS_NUM_HIBDATA 1u -/* Backup domain is present (includes RTC and WCO) */ -#define SRSS_BACKUP_PRESENT 1u -/* Mask of HFCLK root clock supervisors (CSV). For each clock root i, bit[i] of - mask indicates presence of a CSV. */ -#define SRSS_MASK_HFCSV 0u -/* Clock supervisor is present on WCO. Must be 0 if BACKUP_PRESENT==0. */ -#define SRSS_WCOCSV_PRESENT 0u -/* Number of software watchdog timers. */ -#define SRSS_NUM_MCWDT 2u -/* Number of DSI inputs into clock muxes. This is used for logic optimization. */ -#define SRSS_NUM_DSI 0u -/* Alternate high-frequency clock is present. This is used for logic optimization. */ -#define SRSS_ALTHF_PRESENT 0u -/* Alternate low-frequency clock is present. This is used for logic optimization. */ -#define SRSS_ALTLF_PRESENT 0u -/* Use the hardened clkactfllmux block */ -#define SRSS_USE_HARD_CLKACTFLLMUX 1u -/* Number of clock paths, including direct paths in hardened clkactfllmux block - (Must be >= NUM_CLKPATH) */ -#define SRSS_HARD_CLKPATH 6u -/* Number of clock paths with muxes in hardened clkactfllmux block (Must be >= - NUM_PLL+1) */ -#define SRSS_HARD_CLKPATHMUX 6u -/* Number of HFCLKS present in hardened clkactfllmux block (Must be >= NUM_HFROOT) */ -#define SRSS_HARD_HFROOT 6u -/* ECO mux is present in hardened clkactfllmux block (Must be >= ECO_PRESENT) */ -#define SRSS_HARD_ECOMUX_PRESENT 1u -/* ALTHF mux is present in hardened clkactfllmux block (Must be >= ALTHF_PRESENT) */ -#define SRSS_HARD_ALTHFMUX_PRESENT 1u -/* SRSS version is at least SRSS_VER1P3. Set to 1 for new products. Set to 0 for - PSoC6ABLE2, PSoC6A2M. */ -#define SRSS_SRSS_VER1P3 1u -/* Backup memory is present (only used when BACKUP_PRESENT==1) */ -#define SRSS_BACKUP_BMEM_PRESENT 0u -/* Number of Backup registers to include (each is 32b). Only used when - BACKUP_PRESENT==1. */ -#define SRSS_BACKUP_NUM_BREG 16u -/* Number of AMUX splitter cells */ -#define IOSS_HSIOM_AMUX_SPLIT_NR 6u -/* Number of HSIOM ports in device (same as GPIO.GPIO_PRT_NR) */ -#define IOSS_HSIOM_HSIOM_PORT_NR 15u -/* Number of PWR/GND MONITOR CELLs in the device */ -#define IOSS_HSIOM_MONITOR_NR 0u -/* Number of PWR/GND MONITOR CELLs in range 0..31 */ -#define IOSS_HSIOM_MONITOR_NR_0_31 0u -/* Number of PWR/GND MONITOR CELLs in range 32..63 */ -#define IOSS_HSIOM_MONITOR_NR_32_63 0u -/* Number of PWR/GND MONITOR CELLs in range 64..95 */ -#define IOSS_HSIOM_MONITOR_NR_64_95 0u -/* Number of PWR/GND MONITOR CELLs in range 96..127 */ -#define IOSS_HSIOM_MONITOR_NR_96_127 0u -/* Indicates the presence of alternate JTAG interface */ -#define IOSS_HSIOM_ALTJTAG_PRESENT 0u +/* Number of TTCAN instances */ +#define CANFD_CAN_NR 1u +/* ECC logic present or not */ +#define CANFD_ECC_PRESENT 0u +/* address included in ECC logic or not */ +#define CANFD_ECC_ADDR_PRESENT 0u +/* Time Stamp counter present or not (required for instance 0, otherwise not + allowed) */ +#define CANFD_TS_PRESENT 1u +/* Message RAM size in KB */ +#define CANFD_MRAM_SIZE 4u +/* Message RAM address width */ +#define CANFD_MRAM_ADDR_WIDTH 10u +/* UDB present or not ('0': no, '1': yes) */ +#define CPUSS_UDB_PRESENT 0u +/* MBIST MMIO for Synopsys MBIST ('0': no, '1': yes). Set this to '1' only for the + chips which doesn't use mxdft. */ +#define CPUSS_MBIST_MMIO_PRESENT 1u +/* System RAM 0 size in kilobytes */ +#define CPUSS_SRAM0_SIZE 256u +/* Number of macros used to implement System RAM 0. Example: 8 if 256 KB System + SRAM0 is implemented with 8 32KB macros. */ +#define CPUSS_RAMC0_MACRO_NR 8u +/* System RAM 1 present or not (0=No, 1=Yes) */ +#define CPUSS_RAMC1_PRESENT 0u +/* System RAM 1 size in kilobytes */ +#define CPUSS_SRAM1_SIZE 1u +/* Number of macros used to implement System RAM 1. Example: 8 if 256 KB System + RAM 1 is implemented with 8 32KB macros. */ +#define CPUSS_RAMC1_MACRO_NR 1u +/* System RAM 2 present or not (0=No, 1=Yes) */ +#define CPUSS_RAMC2_PRESENT 0u +/* System RAM 2 size in kilobytes */ +#define CPUSS_SRAM2_SIZE 1u +/* Number of macros used to implement System RAM 2. Example: 8 if 256 KB System + RAM 2 is implemented with 8 32KB macros. */ +#define CPUSS_RAMC2_MACRO_NR 1u +/* System SRAM(s) ECC present or not ('0': no, '1': yes) */ +#define CPUSS_RAMC_ECC_PRESENT 0u +/* System SRAM(s) address ECC present or not ('0': no, '1': yes) */ +#define CPUSS_RAMC_ECC_ADDR_PRESENT 0u +/* ECC present in either system RAM or interrupt handler (RAMC_ECC_PRESENT) */ +#define CPUSS_ECC_PRESENT 0u +/* DataWire SRAMs ECC present or not ('0': no, '1': yes) */ +#define CPUSS_DW_ECC_PRESENT 0u +/* DataWire SRAMs address ECC present or not ('0': no, '1': yes) */ +#define CPUSS_DW_ECC_ADDR_PRESENT 0u +/* System ROM size in KB */ +#define CPUSS_ROM_SIZE 64u +/* Number of macros used to implement system ROM. Example: 4 if 512 KB system ROM + is implemented with 4 128KB macros. */ +#define CPUSS_ROMC_MACRO_NR 1u +/* Flash memory type ('0' : SONOS, '1': ECT) */ +#define CPUSS_FLASHC_ECT 0u +/* Flash main region size in KB */ +#define CPUSS_FLASH_SIZE 512u +/* Flash work region size in KB (EEPROM emulation, data) */ +#define CPUSS_WFLASH_SIZE 32u +/* Flash supervisory region size in KB */ +#define CPUSS_SFLASH_SIZE 32u +/* Flash data output word size (in Bytes) */ +#define CPUSS_FLASHC_MAIN_DATA_WIDTH 16u +/* SONOS Flash RWW present or not ('0': no, '1': yes) When RWW is '0', No special + sectors present in Flash. Part of main sector 0 is allowcated for Supervisory + Flash, and no Work Flash present. */ +#define CPUSS_FLASHC_SONOS_RWW 1u +/* SONOS Flash, number of main sectors. */ +#define CPUSS_FLASHC_SONOS_MAIN_SECTORS 2u +/* SONOS Flash, number of rows per main sector. */ +#define CPUSS_FLASHC_SONOS_MAIN_ROWS 512u +/* SONOS Flash, number of words per row of main sector. */ +#define CPUSS_FLASHC_SONOS_MAIN_WORDS 128u +/* SONOS Flash, number of special sectors. */ +#define CPUSS_FLASHC_SONOS_SPL_SECTORS 2u +/* SONOS Flash, number of rows per special sector. */ +#define CPUSS_FLASHC_SONOS_SPL_ROWS 64u +/* Flash memory ECC present or not ('0': no, '1': yes) */ +#define CPUSS_FLASHC_FLASH_ECC_PRESENT 0u +/* Flash cache SRAM(s) ECC present or not ('0': no, '1': yes) */ +#define CPUSS_FLASHC_RAM_ECC_PRESENT 0u +/* Number of external slaves directly connected to slow AHB-Lite infrastructure. + Maximum nubmer of slave supported is 4. Width of this parameter is 4-bits. + 1-bit mask for each slave indicating present or not. Example: 4'b0011 - slave + 0 and slave 1 are present. Note: The SLOW_SLx_ADDR and SLOW_SLx_MASK + parameters (for the slaves present) should be derived from the Memory Map. */ +#define CPUSS_SLOW_SL_PRESENT 1u +/* Number of external slaves directly connected to fast AHB-Lite infrastructure. + Maximum nubmer of slave supported is 4. Width of this parameter is 4-bits. + 1-bit mask for each slave indicating present or not. Example: 4'b0011 - slave + 0 and slave 1 are present. Note: The FAST_SLx_ADDR and FAST_SLx_MASK + parameters (for the slaves present) should be derived from the Memory Map. */ +#define CPUSS_FAST_SL_PRESENT 1u +/* Number of external masters driving the slow AHB-Lite infrastructure. Maximum + number of masters supported is 2. Width of this parameter is 2-bits. 1-bit + mask for each master indicating present or not. Example: 2'b01 - master 0 is + present. */ +#define CPUSS_SLOW_MS_PRESENT 1u +/* System interrupt functionality present or not ('0': no; '1': yes). Not used for + CM0+ PCU, which always uses system interrupt functionality. */ +#define CPUSS_SYSTEM_IRQ_PRESENT 0u +/* Number of total interrupt request inputs to CPUSS */ +#define CPUSS_SYSTEM_INT_NR 174u +/* Number of DeepSleep wakeup interrupt inputs to CPUSS */ +#define CPUSS_SYSTEM_DPSLP_INT_NR 39u +/* Width of the CM4 interrupt priority bits. Legal range [3,8] Example: 3 = 8 + levels of priority 8 = 256 levels of priority */ +#define CPUSS_CM4_LVL_WIDTH 3u +/* CM4 Floating point unit present or not (0=No, 1=Yes) */ +#define CPUSS_CM4_FPU_PRESENT 1u +/* Debug level. Legal range [0,3] (0= No support, 1= Minimum: CM0/4 both 2 + breakpoints +1 watchpoint, 2= Full debug: CM0/4 have 4/6 breakpoints, 2/4 + watchpoints and 0/2 literal compare, 3= Full debug + data matching) */ +#define CPUSS_DEBUG_LVL 3u +/* Trace level. Legal range [0,2] (0= No tracing, 1= ITM + TPIU + SWO, 2= ITM + + ETM + TPIU + SWO) Note: CM4 HTM is not supported. Hence vaule 3 for trace + level is not supported in CPUSS. */ +#define CPUSS_TRACE_LVL 2u +/* Embedded Trace Buffer present or not (0=No, 1=Yes) */ +#define CPUSS_ETB_PRESENT 0u +/* CM0+ MTB SRAM buffer size in kilobytes. Legal vaules 4, 8 or 16 */ +#define CPUSS_MTB_SRAM_SIZE 4u +/* CM4 ETB SRAM buffer size in kilobytes. Legal vaules 4, 8 or 16 */ +#define CPUSS_ETB_SRAM_SIZE 8u +/* PTM interface present (0=No, 1=Yes) */ +#define CPUSS_PTM_PRESENT 0u +/* Width of the PTM interface in bits ([2,32]) */ +#define CPUSS_PTM_WIDTH 1u +/* Width of the TPIU interface in bits ([1,4]) */ +#define CPUSS_TPIU_WIDTH 4u +/* CoreSight Part Identification Number */ +#define CPUSS_JEPID 52u +/* CoreSight Part Identification Number */ +#define CPUSS_JEPCONTINUATION 0u +/* CoreSight Part Identification Number */ +#define CPUSS_FAMILYID 261u +/* ROM trim register width (for ARM 3, for Synopsys 5) */ +#define CPUSS_ROM_TRIM_WIDTH 5u +/* ROM trim register default (for both ARM and Synopsys 0x0000_0012) */ +#define CPUSS_ROM_TRIM_DEFAULT 18u +/* RAM trim register width (for ARM 8, for Synopsys 15) */ +#define CPUSS_RAM_TRIM_WIDTH 15u +/* RAM trim register default (for ARM 0x0000_0062 and for Synopsys 0x0000_6012) */ +#define CPUSS_RAM_TRIM_DEFAULT 24594u +/* Cryptography IP present or not (0=No, 1=Yes) */ +#define CPUSS_CRYPTO_PRESENT 1u +/* DataWire and DMAC SW trigger per channel present or not ('0': no, '1': yes) */ +#define CPUSS_SW_TR_PRESENT 0u +/* DataWire 0 present or not (0=No, 1=Yes) */ +#define CPUSS_DW0_PRESENT 1u +/* Number of DataWire 0 channels (8, 16 or 32) */ +#define CPUSS_DW0_CH_NR 29u +/* DataWire 1 present or not (0=No, 1=Yes) */ +#define CPUSS_DW1_PRESENT 1u +/* Number of DataWire 1 channels (8, 16 or 32) */ +#define CPUSS_DW1_CH_NR 32u +/* DMA controller present or not ('0': no, '1': yes) */ +#define CPUSS_DMAC_PRESENT 1u +/* Number of DMA controller channels ([1, 8]) */ +#define CPUSS_DMAC_CH_NR 2u +/* DMAC SW trigger per channel present or not ('0': no, '1': yes) */ +#define CPUSS_CH_SW_TR_PRESENT 0u +/* Copy value from Globals */ +#define CPUSS_CHIP_TOP_PROFILER_PRESENT 0u +/* ETAS Calibration support pin out present (automotive only) */ +#define CPUSS_CHIP_TOP_CAL_SUP_NZ_PRESENT 0u +/* TRACE_LVL>0 */ +#define CPUSS_CHIP_TOP_TRACE_PRESENT 1u +/* DataWire SW trigger per channel present or not ('0': no, '1': yes) */ +#define CPUSS_CH_STRUCT_SW_TR_PRESENT 0u +/* Number of DataWire controllers present (max 2) (same as DW.NR above) */ +#define CPUSS_CPUSS_DW_DW_NR 2u +/* Number of channels in each DataWire controller */ +#define CPUSS_CPUSS_DW_DW_NR0_DW_CH_NR 29u +/* Width of a channel number in bits */ +#define CPUSS_CPUSS_DW_DW_NR0_DW_CH_NR_WIDTH 5u +/* Number of channels in each DataWire controller */ +#define CPUSS_CPUSS_DW_DW_NR1_DW_CH_NR 32u +/* Width of a channel number in bits */ +#define CPUSS_CPUSS_DW_DW_NR1_DW_CH_NR_WIDTH 5u +/* Cryptography SRAMs ECC present or not ('0': no, '1': yes) */ +#define CPUSS_CRYPTO_ECC_PRESENT 0u +/* Cryptography SRAMs address ECC present or not ('0': no, '1': yes) */ +#define CPUSS_CRYPTO_ECC_ADDR_PRESENT 0u +/* AES cipher support ('0': no, '1': yes) */ +#define CPUSS_CRYPTO_AES 1u +/* (Tripple) DES cipher support ('0': no, '1': yes) */ +#define CPUSS_CRYPTO_DES 1u +/* Chacha support ('0': no, '1': yes) */ +#define CPUSS_CRYPTO_CHACHA 1u +/* Pseudo random number generation support ('0': no, '1': yes) */ +#define CPUSS_CRYPTO_PR 1u +/* SHA1 hash support ('0': no, '1': yes) */ +#define CPUSS_CRYPTO_SHA1 1u +/* SHA2 hash support ('0': no, '1': yes) */ +#define CPUSS_CRYPTO_SHA2 1u +/* SHA3 hash support ('0': no, '1': yes) */ +#define CPUSS_CRYPTO_SHA3 1u +/* Cyclic Redundancy Check support ('0': no, '1': yes) */ +#define CPUSS_CRYPTO_CRC 1u +/* True random number generation support ('0': no, '1': yes) */ +#define CPUSS_CRYPTO_TR 1u +/* Vector unit support ('0': no, '1': yes) */ +#define CPUSS_CRYPTO_VU 1u +/* Galios/Counter Mode (GCM) support ('0': no, '1': yes) */ +#define CPUSS_CRYPTO_GCM 1u +/* Number of 32-bit words in the IP internal memory buffer (from the set [64, 128, + 256, 512, 1024, 2048, 4096], to allow for a 256 B, 512 B, 1 kB, 2 kB, 4 kB, 8 + kB and 16 kB memory buffer) */ +#define CPUSS_CRYPTO_BUFF_SIZE 1024u +/* Number of DMA controller channels ([1, 8]) */ +#define CPUSS_DMAC_CH_NR 2u +/* Number of DataWire controllers present (max 2) */ +#define CPUSS_DW_NR 2u +/* DataWire SRAMs ECC present or not ('0': no, '1': yes) */ +#define CPUSS_DW_ECC_PRESENT 0u +/* Number of fault structures. Legal range [1, 4] */ +#define CPUSS_FAULT_FAULT_NR 2u +/* Number of Flash BIST_DATA registers */ +#define CPUSS_FLASHC_FLASHC_BIST_DATA_NR 4u +/* Page size in # of 32-bit words (1: 4 bytes, 2: 8 bytes, ... */ +#define CPUSS_FLASHC_PA_SIZE 128u +/* SONOS Flash is used or not ('0': no, '1': yes) */ +#define CPUSS_FLASHC_FLASHC_IS_SONOS 1u +/* eCT Flash is used or not ('0': no, '1': yes) */ +#define CPUSS_FLASHC_FLASHC_IS_ECT 0u +/* Number of IPC structures. Legal range [1, 16] */ +#define CPUSS_IPC_IPC_NR 16u +/* Number of IPC interrupt structures. Legal range [1, 16] */ +#define CPUSS_IPC_IPC_IRQ_NR 16u +/* Master 0 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS0_PC_NR_MINUS1 7u +/* Master 1 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS1_PC_NR_MINUS1 0u +/* Master 2 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS2_PC_NR_MINUS1 0u +/* Master 3 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS3_PC_NR_MINUS1 0u +/* Master 4 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS4_PC_NR_MINUS1 0u +/* Master 5 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS5_PC_NR_MINUS1 7u +/* Master 6 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS6_PC_NR_MINUS1 0u +/* Master 7 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS7_PC_NR_MINUS1 0u +/* Master 8 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS8_PC_NR_MINUS1 0u +/* Master 9 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS9_PC_NR_MINUS1 0u +/* Master 10 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS10_PC_NR_MINUS1 0u +/* Master 11 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS11_PC_NR_MINUS1 0u +/* Master 12 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS12_PC_NR_MINUS1 0u +/* Master 13 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS13_PC_NR_MINUS1 0u +/* Master 14 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS14_PC_NR_MINUS1 7u +/* Master 15 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS15_PC_NR_MINUS1 7u +/* Number of SMPU protection structures */ +#define CPUSS_PROT_SMPU_STRUCT_NR 16u +/* Number of protection contexts supported minus 1. Legal range [1,16] */ +#define CPUSS_SMPU_STRUCT_PC_NR_MINUS1 7u +/* Number of instantiated eFUSE macros (256 bit macros). Legal range [1, 16] */ +#define EFUSE_EFUSE_NR 4u /* Number of GPIO ports in range 0..31 */ #define IOSS_GPIO_GPIO_PORT_NR_0_31 15u /* Number of GPIO ports in range 32..63 */ @@ -1693,8 +1874,65 @@ typedef PASS_V1_Type PASS_Type; #define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_SLOW_IO6 0u /* Indicates that pin #7 exists for this port with slew control feature */ #define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_SLOW_IO7 0u +/* Number of AMUX splitter cells */ +#define IOSS_HSIOM_AMUX_SPLIT_NR 6u +/* Number of HSIOM ports in device (same as GPIO.GPIO_PRT_NR) */ +#define IOSS_HSIOM_HSIOM_PORT_NR 15u +/* Number of PWR/GND MONITOR CELLs in the device */ +#define IOSS_HSIOM_MONITOR_NR 0u +/* Number of PWR/GND MONITOR CELLs in range 0..31 */ +#define IOSS_HSIOM_MONITOR_NR_0_31 0u +/* Number of PWR/GND MONITOR CELLs in range 32..63 */ +#define IOSS_HSIOM_MONITOR_NR_32_63 0u +/* Number of PWR/GND MONITOR CELLs in range 64..95 */ +#define IOSS_HSIOM_MONITOR_NR_64_95 0u +/* Number of PWR/GND MONITOR CELLs in range 96..127 */ +#define IOSS_HSIOM_MONITOR_NR_96_127 0u +/* Indicates the presence of alternate JTAG interface */ +#define IOSS_HSIOM_ALTJTAG_PRESENT 0u /* Mask of SMARTIO instances presence */ #define IOSS_SMARTIO_SMARTIO_MASK 768u +/* Number of ports supoprting up to 4 COMs */ +#define LCD_NUMPORTS 8u +/* Number of ports supporting up to 8 COMs */ +#define LCD_NUMPORTS8 8u +/* Number of ports supporting up to 16 COMs */ +#define LCD_NUMPORTS16 0u +/* Max number of LCD commons supported */ +#define LCD_CHIP_TOP_COM_NR 8u +/* Max number of LCD pins (total) supported */ +#define LCD_CHIP_TOP_PIN_NR 60u +/* Number of IREF outputs from AREF */ +#define PASS_NR_IREFS 4u +/* Number of CTBs in the Subsystem */ +#define PASS_NR_CTBS 0u +/* Number of CTDACs in the Subsystem */ +#define PASS_NR_CTDACS 0u +/* CTB0 Exists */ +#define PASS_CTB0_EXISTS 0u +/* CTB1 Exists */ +#define PASS_CTB1_EXISTS 0u +/* CTB2 Exists */ +#define PASS_CTB2_EXISTS 0u +/* CTB3 Exists */ +#define PASS_CTB3_EXISTS 0u +/* CTDAC0 Exists */ +#define PASS_CTDAC0_EXISTS 0u +/* CTDAC1 Exists */ +#define PASS_CTDAC1_EXISTS 0u +/* CTDAC2 Exists */ +#define PASS_CTDAC2_EXISTS 0u +/* CTDAC3 Exists */ +#define PASS_CTDAC3_EXISTS 0u +#define PASS_CTBM_CTDAC_PRESENT 0u +/* Number of SAR channels */ +#define PASS_SAR_SAR_CHANNELS 16u +/* Averaging logic present in SAR */ +#define PASS_SAR_SAR_AVERAGE 1u +/* Range detect logic present in SAR */ +#define PASS_SAR_SAR_RANGEDET 1u +/* Support for UAB sampling */ +#define PASS_SAR_SAR_UAB 0u /* The number of protection contexts ([2, 16]). */ #define PERI_PC_NR 8u /* Master interface presence mask (4 bits) */ @@ -2305,264 +2543,6 @@ typedef PASS_V1_Type PASS_Type; #define PERI_TR_1TO1_GROUP_NR7_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u /* Number of AHB-Lite "hmaster[]" bits ([1, 8]). */ #define PERI_MASTER_WIDTH 8u -/* UDB present or not ('0': no, '1': yes) */ -#define CPUSS_UDB_PRESENT 0u -/* MBIST MMIO for Synopsys MBIST ('0': no, '1': yes). Set this to '1' only for the - chips which doesn't use mxdft. */ -#define CPUSS_MBIST_MMIO_PRESENT 1u -/* System RAM 0 size in kilobytes */ -#define CPUSS_SRAM0_SIZE 256u -/* Number of macros used to implement System RAM 0. Example: 8 if 256 KB System - SRAM0 is implemented with 8 32KB macros. */ -#define CPUSS_RAMC0_MACRO_NR 8u -/* System RAM 1 present or not (0=No, 1=Yes) */ -#define CPUSS_RAMC1_PRESENT 0u -/* System RAM 1 size in kilobytes */ -#define CPUSS_SRAM1_SIZE 1u -/* Number of macros used to implement System RAM 1. Example: 8 if 256 KB System - RAM 1 is implemented with 8 32KB macros. */ -#define CPUSS_RAMC1_MACRO_NR 1u -/* System RAM 2 present or not (0=No, 1=Yes) */ -#define CPUSS_RAMC2_PRESENT 0u -/* System RAM 2 size in kilobytes */ -#define CPUSS_SRAM2_SIZE 1u -/* Number of macros used to implement System RAM 2. Example: 8 if 256 KB System - RAM 2 is implemented with 8 32KB macros. */ -#define CPUSS_RAMC2_MACRO_NR 1u -/* System SRAM(s) ECC present or not ('0': no, '1': yes) */ -#define CPUSS_RAMC_ECC_PRESENT 0u -/* System SRAM(s) address ECC present or not ('0': no, '1': yes) */ -#define CPUSS_RAMC_ECC_ADDR_PRESENT 0u -/* ECC present in either system RAM or interrupt handler (RAMC_ECC_PRESENT) */ -#define CPUSS_ECC_PRESENT 0u -/* DataWire SRAMs ECC present or not ('0': no, '1': yes) */ -#define CPUSS_DW_ECC_PRESENT 0u -/* DataWire SRAMs address ECC present or not ('0': no, '1': yes) */ -#define CPUSS_DW_ECC_ADDR_PRESENT 0u -/* System ROM size in KB */ -#define CPUSS_ROM_SIZE 64u -/* Number of macros used to implement system ROM. Example: 4 if 512 KB system ROM - is implemented with 4 128KB macros. */ -#define CPUSS_ROMC_MACRO_NR 1u -/* Flash memory type ('0' : SONOS, '1': ECT) */ -#define CPUSS_FLASHC_ECT 0u -/* Flash main region size in KB */ -#define CPUSS_FLASH_SIZE 512u -/* Flash work region size in KB (EEPROM emulation, data) */ -#define CPUSS_WFLASH_SIZE 32u -/* Flash supervisory region size in KB */ -#define CPUSS_SFLASH_SIZE 32u -/* Flash data output word size (in Bytes) */ -#define CPUSS_FLASHC_MAIN_DATA_WIDTH 16u -/* SONOS Flash RWW present or not ('0': no, '1': yes) When RWW is '0', No special - sectors present in Flash. Part of main sector 0 is allowcated for Supervisory - Flash, and no Work Flash present. */ -#define CPUSS_FLASHC_SONOS_RWW 1u -/* SONOS Flash, number of main sectors. */ -#define CPUSS_FLASHC_SONOS_MAIN_SECTORS 2u -/* SONOS Flash, number of rows per main sector. */ -#define CPUSS_FLASHC_SONOS_MAIN_ROWS 512u -/* SONOS Flash, number of words per row of main sector. */ -#define CPUSS_FLASHC_SONOS_MAIN_WORDS 128u -/* SONOS Flash, number of special sectors. */ -#define CPUSS_FLASHC_SONOS_SPL_SECTORS 2u -/* SONOS Flash, number of rows per special sector. */ -#define CPUSS_FLASHC_SONOS_SPL_ROWS 64u -/* Flash memory ECC present or not ('0': no, '1': yes) */ -#define CPUSS_FLASHC_FLASH_ECC_PRESENT 0u -/* Flash cache SRAM(s) ECC present or not ('0': no, '1': yes) */ -#define CPUSS_FLASHC_RAM_ECC_PRESENT 0u -/* Number of external slaves directly connected to slow AHB-Lite infrastructure. - Maximum nubmer of slave supported is 4. Width of this parameter is 4-bits. - 1-bit mask for each slave indicating present or not. Example: 4'b0011 - slave - 0 and slave 1 are present. Note: The SLOW_SLx_ADDR and SLOW_SLx_MASK - parameters (for the slaves present) should be derived from the Memory Map. */ -#define CPUSS_SLOW_SL_PRESENT 1u -/* Number of external slaves directly connected to fast AHB-Lite infrastructure. - Maximum nubmer of slave supported is 4. Width of this parameter is 4-bits. - 1-bit mask for each slave indicating present or not. Example: 4'b0011 - slave - 0 and slave 1 are present. Note: The FAST_SLx_ADDR and FAST_SLx_MASK - parameters (for the slaves present) should be derived from the Memory Map. */ -#define CPUSS_FAST_SL_PRESENT 1u -/* Number of external masters driving the slow AHB-Lite infrastructure. Maximum - number of masters supported is 2. Width of this parameter is 2-bits. 1-bit - mask for each master indicating present or not. Example: 2'b01 - master 0 is - present. */ -#define CPUSS_SLOW_MS_PRESENT 1u -/* System interrupt functionality present or not ('0': no; '1': yes). Not used for - CM0+ PCU, which always uses system interrupt functionality. */ -#define CPUSS_SYSTEM_IRQ_PRESENT 0u -/* Number of total interrupt request inputs to CPUSS */ -#define CPUSS_SYSTEM_INT_NR 174u -/* Number of DeepSleep wakeup interrupt inputs to CPUSS */ -#define CPUSS_SYSTEM_DPSLP_INT_NR 39u -/* Width of the CM4 interrupt priority bits. Legal range [3,8] Example: 3 = 8 - levels of priority 8 = 256 levels of priority */ -#define CPUSS_CM4_LVL_WIDTH 3u -/* CM4 Floating point unit present or not (0=No, 1=Yes) */ -#define CPUSS_CM4_FPU_PRESENT 1u -/* Debug level. Legal range [0,3] (0= No support, 1= Minimum: CM0/4 both 2 - breakpoints +1 watchpoint, 2= Full debug: CM0/4 have 4/6 breakpoints, 2/4 - watchpoints and 0/2 literal compare, 3= Full debug + data matching) */ -#define CPUSS_DEBUG_LVL 3u -/* Trace level. Legal range [0,2] (0= No tracing, 1= ITM + TPIU + SWO, 2= ITM + - ETM + TPIU + SWO) Note: CM4 HTM is not supported. Hence vaule 3 for trace - level is not supported in CPUSS. */ -#define CPUSS_TRACE_LVL 2u -/* Embedded Trace Buffer present or not (0=No, 1=Yes) */ -#define CPUSS_ETB_PRESENT 0u -/* CM0+ MTB SRAM buffer size in kilobytes. Legal vaules 4, 8 or 16 */ -#define CPUSS_MTB_SRAM_SIZE 4u -/* CM4 ETB SRAM buffer size in kilobytes. Legal vaules 4, 8 or 16 */ -#define CPUSS_ETB_SRAM_SIZE 8u -/* PTM interface present (0=No, 1=Yes) */ -#define CPUSS_PTM_PRESENT 0u -/* Width of the PTM interface in bits ([2,32]) */ -#define CPUSS_PTM_WIDTH 1u -/* Width of the TPIU interface in bits ([1,4]) */ -#define CPUSS_TPIU_WIDTH 4u -/* CoreSight Part Identification Number */ -#define CPUSS_JEPID 52u -/* CoreSight Part Identification Number */ -#define CPUSS_JEPCONTINUATION 0u -/* CoreSight Part Identification Number */ -#define CPUSS_FAMILYID 261u -/* ROM trim register width (for ARM 3, for Synopsys 5) */ -#define CPUSS_ROM_TRIM_WIDTH 5u -/* ROM trim register default (for both ARM and Synopsys 0x0000_0012) */ -#define CPUSS_ROM_TRIM_DEFAULT 18u -/* RAM trim register width (for ARM 8, for Synopsys 15) */ -#define CPUSS_RAM_TRIM_WIDTH 15u -/* RAM trim register default (for ARM 0x0000_0062 and for Synopsys 0x0000_6012) */ -#define CPUSS_RAM_TRIM_DEFAULT 24594u -/* Cryptography IP present or not (0=No, 1=Yes) */ -#define CPUSS_CRYPTO_PRESENT 1u -/* DataWire and DMAC SW trigger per channel present or not ('0': no, '1': yes) */ -#define CPUSS_SW_TR_PRESENT 0u -/* DataWire 0 present or not (0=No, 1=Yes) */ -#define CPUSS_DW0_PRESENT 1u -/* Number of DataWire 0 channels (8, 16 or 32) */ -#define CPUSS_DW0_CH_NR 29u -/* DataWire 1 present or not (0=No, 1=Yes) */ -#define CPUSS_DW1_PRESENT 1u -/* Number of DataWire 1 channels (8, 16 or 32) */ -#define CPUSS_DW1_CH_NR 32u -/* DMA controller present or not ('0': no, '1': yes) */ -#define CPUSS_DMAC_PRESENT 1u -/* Number of DMA controller channels ([1, 8]) */ -#define CPUSS_DMAC_CH_NR 2u -/* Number of Flash BIST_DATA registers */ -#define CPUSS_FLASHC_FLASHC_BIST_DATA_NR 4u -/* Page size in # of 32-bit words (1: 4 bytes, 2: 8 bytes, ... */ -#define CPUSS_FLASHC_PA_SIZE 128u -/* SONOS Flash is used or not ('0': no, '1': yes) */ -#define CPUSS_FLASHC_FLASHC_IS_SONOS 1u -/* eCT Flash is used or not ('0': no, '1': yes) */ -#define CPUSS_FLASHC_FLASHC_IS_ECT 0u -/* Cryptography SRAMs ECC present or not ('0': no, '1': yes) */ -#define CPUSS_CRYPTO_ECC_PRESENT 0u -/* Cryptography SRAMs address ECC present or not ('0': no, '1': yes) */ -#define CPUSS_CRYPTO_ECC_ADDR_PRESENT 0u -/* AES cipher support ('0': no, '1': yes) */ -#define CPUSS_CRYPTO_AES 1u -/* (Tripple) DES cipher support ('0': no, '1': yes) */ -#define CPUSS_CRYPTO_DES 1u -/* Chacha support ('0': no, '1': yes) */ -#define CPUSS_CRYPTO_CHACHA 1u -/* Pseudo random number generation support ('0': no, '1': yes) */ -#define CPUSS_CRYPTO_PR 1u -/* SHA1 hash support ('0': no, '1': yes) */ -#define CPUSS_CRYPTO_SHA1 1u -/* SHA2 hash support ('0': no, '1': yes) */ -#define CPUSS_CRYPTO_SHA2 1u -/* SHA3 hash support ('0': no, '1': yes) */ -#define CPUSS_CRYPTO_SHA3 1u -/* Cyclic Redundancy Check support ('0': no, '1': yes) */ -#define CPUSS_CRYPTO_CRC 1u -/* True random number generation support ('0': no, '1': yes) */ -#define CPUSS_CRYPTO_TR 1u -/* Vector unit support ('0': no, '1': yes) */ -#define CPUSS_CRYPTO_VU 1u -/* Galios/Counter Mode (GCM) support ('0': no, '1': yes) */ -#define CPUSS_CRYPTO_GCM 1u -/* Number of 32-bit words in the IP internal memory buffer (from the set [64, 128, - 256, 512, 1024, 2048, 4096], to allow for a 256 B, 512 B, 1 kB, 2 kB, 4 kB, 8 - kB and 16 kB memory buffer) */ -#define CPUSS_CRYPTO_BUFF_SIZE 1024u -/* Number of fault structures. Legal range [1, 4] */ -#define CPUSS_FAULT_FAULT_NR 2u -/* Number of IPC structures. Legal range [1, 16] */ -#define CPUSS_IPC_IPC_NR 16u -/* Number of IPC interrupt structures. Legal range [1, 16] */ -#define CPUSS_IPC_IPC_IRQ_NR 16u -/* Master 0 protect contexts minus one */ -#define CPUSS_PROT_SMPU_MS0_PC_NR_MINUS1 7u -/* Master 1 protect contexts minus one */ -#define CPUSS_PROT_SMPU_MS1_PC_NR_MINUS1 0u -/* Master 2 protect contexts minus one */ -#define CPUSS_PROT_SMPU_MS2_PC_NR_MINUS1 0u -/* Master 3 protect contexts minus one */ -#define CPUSS_PROT_SMPU_MS3_PC_NR_MINUS1 0u -/* Master 4 protect contexts minus one */ -#define CPUSS_PROT_SMPU_MS4_PC_NR_MINUS1 0u -/* Master 5 protect contexts minus one */ -#define CPUSS_PROT_SMPU_MS5_PC_NR_MINUS1 7u -/* Master 6 protect contexts minus one */ -#define CPUSS_PROT_SMPU_MS6_PC_NR_MINUS1 0u -/* Master 7 protect contexts minus one */ -#define CPUSS_PROT_SMPU_MS7_PC_NR_MINUS1 0u -/* Master 8 protect contexts minus one */ -#define CPUSS_PROT_SMPU_MS8_PC_NR_MINUS1 0u -/* Master 9 protect contexts minus one */ -#define CPUSS_PROT_SMPU_MS9_PC_NR_MINUS1 0u -/* Master 10 protect contexts minus one */ -#define CPUSS_PROT_SMPU_MS10_PC_NR_MINUS1 0u -/* Master 11 protect contexts minus one */ -#define CPUSS_PROT_SMPU_MS11_PC_NR_MINUS1 0u -/* Master 12 protect contexts minus one */ -#define CPUSS_PROT_SMPU_MS12_PC_NR_MINUS1 0u -/* Master 13 protect contexts minus one */ -#define CPUSS_PROT_SMPU_MS13_PC_NR_MINUS1 0u -/* Master 14 protect contexts minus one */ -#define CPUSS_PROT_SMPU_MS14_PC_NR_MINUS1 7u -/* Master 15 protect contexts minus one */ -#define CPUSS_PROT_SMPU_MS15_PC_NR_MINUS1 7u -/* Number of SMPU protection structures */ -#define CPUSS_PROT_SMPU_STRUCT_NR 16u -/* Number of protection contexts supported minus 1. Legal range [1,16] */ -#define CPUSS_SMPU_STRUCT_PC_NR_MINUS1 7u -/* Number of DataWire controllers present (max 2) */ -#define CPUSS_DW_NR 2u -/* DataWire SRAMs ECC present or not ('0': no, '1': yes) */ -#define CPUSS_DW_ECC_PRESENT 0u -/* DataWire SW trigger per channel present or not ('0': no, '1': yes) */ -#define CPUSS_CH_STRUCT_SW_TR_PRESENT 0u -/* Number of DataWire controllers present (max 2) (same as DW.NR above) */ -#define CPUSS_CPUSS_DW_DW_NR 2u -/* Number of channels in each DataWire controller */ -#define CPUSS_CPUSS_DW_DW_NR0_DW_CH_NR 29u -/* Width of a channel number in bits */ -#define CPUSS_CPUSS_DW_DW_NR0_DW_CH_NR_WIDTH 5u -/* Number of channels in each DataWire controller */ -#define CPUSS_CPUSS_DW_DW_NR1_DW_CH_NR 32u -/* Width of a channel number in bits */ -#define CPUSS_CPUSS_DW_DW_NR1_DW_CH_NR_WIDTH 5u -/* Number of DMA controller channels ([1, 8]) */ -#define CPUSS_DMAC_CH_NR 2u -/* DMAC SW trigger per channel present or not ('0': no, '1': yes) */ -#define CPUSS_CH_SW_TR_PRESENT 0u -/* Copy value from Globals */ -#define CPUSS_CHIP_TOP_PROFILER_PRESENT 0u -/* ETAS Calibration support pin out present (automotive only) */ -#define CPUSS_CHIP_TOP_CAL_SUP_NZ_PRESENT 0u -/* TRACE_LVL>0 */ -#define CPUSS_CHIP_TOP_TRACE_PRESENT 1u -/* Number of instantiated eFUSE macros (256 bit macros). Legal range [1, 16] */ -#define EFUSE_EFUSE_NR 4u -/* SONOS Flash is used or not ('0': no, '1': yes) */ -#define SFLASH_FLASHC_IS_SONOS 1u -/* CPUSS_WOUNDING_PRESENT or not ('0': no, '1': yes) */ -#define SFLASH_CPUSS_WOUNDING_PRESENT 0u /* DeepSleep support ('0':no, '1': yes) */ #define SCB0_DEEPSLEEP 0u /* Externally clocked support? ('0': no, '1': yes) */ @@ -2913,55 +2893,51 @@ typedef PASS_V1_Type PASS_Type; #define SCB6_I2C_FAST_PLUS 1u /* Number of used spi_select signals (max 4) */ #define SCB6_CHIP_TOP_SPI_SEL_NR 1u -/* Number of counters per IP (1..32) */ -#define TCPWM0_CNT_NR 4u -/* Counter width (in number of bits) */ -#define TCPWM0_CNT_CNT_WIDTH 32u -/* Number of counters per IP (1..32) */ -#define TCPWM1_CNT_NR 8u -/* Counter width (in number of bits) */ -#define TCPWM1_CNT_CNT_WIDTH 16u -/* Number of ports supoprting up to 4 COMs */ -#define LCD_NUMPORTS 8u -/* Number of ports supporting up to 8 COMs */ -#define LCD_NUMPORTS8 8u -/* Number of ports supporting up to 16 COMs */ -#define LCD_NUMPORTS16 0u -/* Max number of LCD commons supported */ -#define LCD_CHIP_TOP_COM_NR 8u -/* Max number of LCD pins (total) supported */ -#define LCD_CHIP_TOP_PIN_NR 60u -/* Number of IREF outputs from AREF */ -#define PASS_NR_IREFS 4u -/* Number of CTBs in the Subsystem */ -#define PASS_NR_CTBS 0u -/* Number of CTDACs in the Subsystem */ -#define PASS_NR_CTDACS 0u -/* CTB0 Exists */ -#define PASS_CTB0_EXISTS 0u -/* CTB1 Exists */ -#define PASS_CTB1_EXISTS 0u -/* CTB2 Exists */ -#define PASS_CTB2_EXISTS 0u -/* CTB3 Exists */ -#define PASS_CTB3_EXISTS 0u -/* CTDAC0 Exists */ -#define PASS_CTDAC0_EXISTS 0u -/* CTDAC1 Exists */ -#define PASS_CTDAC1_EXISTS 0u -/* CTDAC2 Exists */ -#define PASS_CTDAC2_EXISTS 0u -/* CTDAC3 Exists */ -#define PASS_CTDAC3_EXISTS 0u -/* Number of SAR channels */ -#define PASS_SAR_SAR_CHANNELS 16u -/* Averaging logic present in SAR */ -#define PASS_SAR_SAR_AVERAGE 1u -/* Range detect logic present in SAR */ -#define PASS_SAR_SAR_RANGEDET 1u -/* Support for UAB sampling */ -#define PASS_SAR_SAR_UAB 0u -#define PASS_CTBM_CTDAC_PRESENT 0u +/* Basically the max packet size, which gets double buffered in RAM 0: 512B + (implies 1KB of RAM space for data) 1: 1KB (implies 2KB of RAM space for + data) */ +#define SDHC_MAX_BLK_SIZE 0u +/* 0: No Command Queuing Engine present 1: Command Queuing Engine present; this + adds 288 bytes of space to the RAM for this purpose. */ +#define SDHC_CQE_PRESENT 0u +/* 0: no retention of any SDHC_CORE regs 1: retention of SDHC_CORE regs that have + the Retention flag (Note, CTL.ENABLE is always retained irrespective of this + parameter) */ +#define SDHC_RETENTION_PRESENT 1u +/* Chip top connect all 8 data pins (0= connect 4 data pins, 1= connect 8 data + pins) */ +#define SDHC_CHIP_TOP_DATA8_PRESENT 0u +/* Chip top connect card_detect */ +#define SDHC_CHIP_TOP_CARD_DETECT_PRESENT 1u +/* Chip top connect card_mech_write_prot_in */ +#define SDHC_CHIP_TOP_CARD_WRITE_PROT_PRESENT 1u +/* Chip top connect led_ctrl_out and led_ctrl_out_en */ +#define SDHC_CHIP_TOP_LED_CTRL_PRESENT 0u +/* Chip top connect io_volt_sel_out and io_volt_sel_out_en */ +#define SDHC_CHIP_TOP_IO_VOLT_SEL_PRESENT 1u +/* Chip top connect io_drive_strength_out and io_drive_strength_out_en */ +#define SDHC_CHIP_TOP_IO_DRIVE_STRENGTH_PRESENT 0u +/* Chip top connect card_if_pwr_en_out and card_if_pwr_en_out_en */ +#define SDHC_CHIP_TOP_CARD_IF_PWR_EN_PRESENT 1u +/* Chip top connect card_emmc_reset_n_out and card_emmc_reset_n_out_en */ +#define SDHC_CHIP_TOP_CARD_EMMC_RESET_PRESENT 0u +/* Chip top connect interrupt_wakeup (not used for eMMC) */ +#define SDHC_CHIP_TOP_INTERRUPT_WAKEUP_PRESENT 1u +/* Basically the max packet size, which gets double buffered in RAM 0: 512B + (implies 1KB of RAM space for data) 1: 1KB (implies 2KB of RAM space for + data) */ +#define SDHC_CORE_MAX_BLK_SIZE 0u +/* 0: No Command Queuing Engine present 1: Command Queuing Engine present; this + adds 288 bytes of space to the RAM for this purpose. */ +#define SDHC_CORE_CQE_PRESENT 0u +/* 0: no retention of any SDHC_CORE regs 1: retention of SDHC_CORE regs that have + the Retention flag (Note, CTL.ENABLE is always retained irrespective of this + parameter) */ +#define SDHC_CORE_RETENTION_PRESENT 1u +/* SONOS Flash is used or not ('0': no, '1': yes) */ +#define SFLASH_FLASHC_IS_SONOS 1u +/* CPUSS_WOUNDING_PRESENT or not ('0': no, '1': yes) */ +#define SFLASH_CPUSS_WOUNDING_PRESENT 0u /* Base address of the SMIF XIP memory region. This address must be a multiple of the SMIF XIP memory capacity. This address must be a multiple of 64 KB. This address must be in the [0x0000:0000, 0x1fff:ffff] memory region. The XIP @@ -2987,60 +2963,84 @@ typedef PASS_V1_Type PASS_Type; #define SMIF_CHIP_TOP_DATA8_PRESENT 0u /* Number of used spi_select signals (max 4) */ #define SMIF_CHIP_TOP_SPI_SEL_NR 3u -/* Basically the max packet size, which gets double buffered in RAM 0: 512B - (implies 1KB of RAM space for data) 1: 1KB (implies 2KB of RAM space for - data) */ -#define SDHC_MAX_BLK_SIZE 0u -/* 0: No Command Queuing Engine present 1: Command Queuing Engine present; this - adds 288 bytes of space to the RAM for this purpose. */ -#define SDHC_CQE_PRESENT 0u -/* 0: no retention of any SDHC_CORE regs 1: retention of SDHC_CORE regs that have - the Retention flag (Note, CTL.ENABLE is always retained irrespective of this - parameter) */ -#define SDHC_RETENTION_PRESENT 1u -/* Basically the max packet size, which gets double buffered in RAM 0: 512B - (implies 1KB of RAM space for data) 1: 1KB (implies 2KB of RAM space for - data) */ -#define SDHC_CORE_MAX_BLK_SIZE 0u -/* 0: No Command Queuing Engine present 1: Command Queuing Engine present; this - adds 288 bytes of space to the RAM for this purpose. */ -#define SDHC_CORE_CQE_PRESENT 0u -/* 0: no retention of any SDHC_CORE regs 1: retention of SDHC_CORE regs that have - the Retention flag (Note, CTL.ENABLE is always retained irrespective of this - parameter) */ -#define SDHC_CORE_RETENTION_PRESENT 1u -/* Chip top connect all 8 data pins (0= connect 4 data pins, 1= connect 8 data - pins) */ -#define SDHC_CHIP_TOP_DATA8_PRESENT 0u -/* Chip top connect card_detect */ -#define SDHC_CHIP_TOP_CARD_DETECT_PRESENT 1u -/* Chip top connect card_mech_write_prot_in */ -#define SDHC_CHIP_TOP_CARD_WRITE_PROT_PRESENT 1u -/* Chip top connect led_ctrl_out and led_ctrl_out_en */ -#define SDHC_CHIP_TOP_LED_CTRL_PRESENT 0u -/* Chip top connect io_volt_sel_out and io_volt_sel_out_en */ -#define SDHC_CHIP_TOP_IO_VOLT_SEL_PRESENT 1u -/* Chip top connect io_drive_strength_out and io_drive_strength_out_en */ -#define SDHC_CHIP_TOP_IO_DRIVE_STRENGTH_PRESENT 0u -/* Chip top connect card_if_pwr_en_out and card_if_pwr_en_out_en */ -#define SDHC_CHIP_TOP_CARD_IF_PWR_EN_PRESENT 1u -/* Chip top connect card_emmc_reset_n_out and card_emmc_reset_n_out_en */ -#define SDHC_CHIP_TOP_CARD_EMMC_RESET_PRESENT 0u -/* Chip top connect interrupt_wakeup (not used for eMMC) */ -#define SDHC_CHIP_TOP_INTERRUPT_WAKEUP_PRESENT 1u -/* Number of TTCAN instances */ -#define CANFD_CAN_NR 1u -/* ECC logic present or not */ -#define CANFD_ECC_PRESENT 0u -/* address included in ECC logic or not */ -#define CANFD_ECC_ADDR_PRESENT 0u -/* Time Stamp counter present or not (required for instance 0, otherwise not - allowed) */ -#define CANFD_TS_PRESENT 1u -/* Message RAM size in KB */ -#define CANFD_MRAM_SIZE 4u -/* Message RAM address width */ -#define CANFD_MRAM_ADDR_WIDTH 10u +/* Number of regulator modules instantiated within SRSS, start with estimate, + update after CMR feedback */ +#define SRSS_NUM_ACTREG_PWRMOD 2u +/* Number of shorting switches between vccd and vccact (target dynamic voltage + drop < 10mV) */ +#define SRSS_NUM_ACTIVE_SWITCH 3u +/* ULP linear regulator system is present */ +#define SRSS_ULPLINREG_PRESENT 1u +/* HT linear regulator system is present */ +#define SRSS_HTLINREG_PRESENT 0u +/* Low-current buck regulator present. Can be derived from S40S_SISOBUCKLC_PRESENT + or SIMOBUCK_PRESENT. */ +#define SRSS_BUCKCTL_PRESENT 1u +/* Low-current SISO buck core regulator is present. Only compatible with ULP + linear regulator system (ULPLINREG_PRESENT==1). */ +#define SRSS_S40S_SISOBUCKLC_PRESENT 1u +/* SIMO buck core regulator is present. Only compatible with ULP linear regulator + system (ULPLINREG_PRESENT==1). */ +#define SRSS_SIMOBUCK_PRESENT 0u +/* Precision ILO (PILO) is present */ +#define SRSS_PILO_PRESENT 0u +/* External Crystal Oscillator is present (high frequency) */ +#define SRSS_ECO_PRESENT 1u +/* System Buck-Boost is present */ +#define SRSS_SYSBB_PRESENT 0u +/* Number of clock paths. Must be > 0 */ +#define SRSS_NUM_CLKPATH 5u +/* Number of PLLs present. Must be <= NUM_CLKPATH */ +#define SRSS_NUM_PLL 1u +/* Number of HFCLK roots present. Must be > 0 */ +#define SRSS_NUM_HFROOT 5u +/* Number of PWR_HIB_DATA registers, should not be needed if BACKUP_PRESENT */ +#define SRSS_NUM_HIBDATA 1u +/* Backup domain is present (includes RTC and WCO) */ +#define SRSS_BACKUP_PRESENT 1u +/* Mask of HFCLK root clock supervisors (CSV). For each clock root i, bit[i] of + mask indicates presence of a CSV. */ +#define SRSS_MASK_HFCSV 0u +/* Clock supervisor is present on WCO. Must be 0 if BACKUP_PRESENT==0. */ +#define SRSS_WCOCSV_PRESENT 0u +/* Number of software watchdog timers. */ +#define SRSS_NUM_MCWDT 2u +/* Number of DSI inputs into clock muxes. This is used for logic optimization. */ +#define SRSS_NUM_DSI 0u +/* Alternate high-frequency clock is present. This is used for logic optimization. */ +#define SRSS_ALTHF_PRESENT 0u +/* Alternate low-frequency clock is present. This is used for logic optimization. */ +#define SRSS_ALTLF_PRESENT 0u +/* Use the hardened clkactfllmux block */ +#define SRSS_USE_HARD_CLKACTFLLMUX 1u +/* Number of clock paths, including direct paths in hardened clkactfllmux block + (Must be >= NUM_CLKPATH) */ +#define SRSS_HARD_CLKPATH 6u +/* Number of clock paths with muxes in hardened clkactfllmux block (Must be >= + NUM_PLL+1) */ +#define SRSS_HARD_CLKPATHMUX 6u +/* Number of HFCLKS present in hardened clkactfllmux block (Must be >= NUM_HFROOT) */ +#define SRSS_HARD_HFROOT 6u +/* ECO mux is present in hardened clkactfllmux block (Must be >= ECO_PRESENT) */ +#define SRSS_HARD_ECOMUX_PRESENT 1u +/* ALTHF mux is present in hardened clkactfllmux block (Must be >= ALTHF_PRESENT) */ +#define SRSS_HARD_ALTHFMUX_PRESENT 1u +/* SRSS version is at least SRSS_VER1P3. Set to 1 for new products. Set to 0 for + PSoC6ABLE2, PSoC6A2M. */ +#define SRSS_SRSS_VER1P3 1u +/* Backup memory is present (only used when BACKUP_PRESENT==1) */ +#define SRSS_BACKUP_BMEM_PRESENT 0u +/* Number of Backup registers to include (each is 32b). Only used when + BACKUP_PRESENT==1. */ +#define SRSS_BACKUP_NUM_BREG 16u +/* Number of counters per IP (1..32) */ +#define TCPWM0_CNT_NR 4u +/* Counter width (in number of bits) */ +#define TCPWM0_CNT_CNT_WIDTH 32u +/* Number of counters per IP (1..32) */ +#define TCPWM1_CNT_NR 8u +/* Counter width (in number of bits) */ +#define TCPWM1_CNT_CNT_WIDTH 16u /* MMIO Targets Defines */ #define CY_MMIO_CRYPTO_GROUP_NR 1u diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/psoc6_04_config.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/psoc6_04_config.h index 832bf1cbbd..0a6f3cd8ab 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/psoc6_04_config.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/psoc6_04_config.h @@ -5,7 +5,7 @@ * PSoC6_04 device configuration header * * \note -* Generator version: 1.6.0.111 +* Generator version: 1.6.0.225 * ******************************************************************************** * \copyright @@ -781,6 +781,61 @@ typedef enum TRIG_IN_MUX_10_CAN_TT_TR_OUT0 = 0x00000A01u /* canfd[0].tr_tmp_rtp_out[0] */ } en_trig_input_cantt_t; +/* Trigger Input Group 11 - CTDAC trigger multiplexer */ +typedef enum +{ + TRIG_IN_MUX_11_TCPWM0_TR_OUT00 = 0x00000B01u, /* tcpwm[0].tr_out0[0] */ + TRIG_IN_MUX_11_TCPWM0_TR_OUT10 = 0x00000B02u, /* tcpwm[0].tr_out1[0] */ + TRIG_IN_MUX_11_TCPWM0_TR_OUT01 = 0x00000B03u, /* tcpwm[0].tr_out0[1] */ + TRIG_IN_MUX_11_TCPWM0_TR_OUT11 = 0x00000B04u, /* tcpwm[0].tr_out1[1] */ + TRIG_IN_MUX_11_TCPWM0_TR_OUT02 = 0x00000B05u, /* tcpwm[0].tr_out0[2] */ + TRIG_IN_MUX_11_TCPWM0_TR_OUT12 = 0x00000B06u, /* tcpwm[0].tr_out1[2] */ + TRIG_IN_MUX_11_TCPWM0_TR_OUT03 = 0x00000B07u, /* tcpwm[0].tr_out0[3] */ + TRIG_IN_MUX_11_TCPWM0_TR_OUT13 = 0x00000B08u, /* tcpwm[0].tr_out1[3] */ + TRIG_IN_MUX_11_TCPWM0_TR_OUT0256 = 0x00000B09u, /* tcpwm[0].tr_out0[256] */ + TRIG_IN_MUX_11_TCPWM0_TR_OUT1256 = 0x00000B0Au, /* tcpwm[0].tr_out1[256] */ + TRIG_IN_MUX_11_TCPWM0_TR_OUT0257 = 0x00000B0Bu, /* tcpwm[0].tr_out0[257] */ + TRIG_IN_MUX_11_TCPWM0_TR_OUT1257 = 0x00000B0Cu, /* tcpwm[0].tr_out1[257] */ + TRIG_IN_MUX_11_TCPWM0_TR_OUT0258 = 0x00000B0Du, /* tcpwm[0].tr_out0[258] */ + TRIG_IN_MUX_11_TCPWM0_TR_OUT1258 = 0x00000B0Eu, /* tcpwm[0].tr_out1[258] */ + TRIG_IN_MUX_11_TCPWM0_TR_OUT0259 = 0x00000B0Fu, /* tcpwm[0].tr_out0[259] */ + TRIG_IN_MUX_11_TCPWM0_TR_OUT1259 = 0x00000B10u, /* tcpwm[0].tr_out1[259] */ + TRIG_IN_MUX_11_TCPWM0_TR_OUT0260 = 0x00000B11u, /* tcpwm[0].tr_out0[260] */ + TRIG_IN_MUX_11_TCPWM0_TR_OUT1260 = 0x00000B12u, /* tcpwm[0].tr_out1[260] */ + TRIG_IN_MUX_11_TCPWM0_TR_OUT0261 = 0x00000B13u, /* tcpwm[0].tr_out0[261] */ + TRIG_IN_MUX_11_TCPWM0_TR_OUT1261 = 0x00000B14u, /* tcpwm[0].tr_out1[261] */ + TRIG_IN_MUX_11_TCPWM0_TR_OUT0262 = 0x00000B15u, /* tcpwm[0].tr_out0[262] */ + TRIG_IN_MUX_11_TCPWM0_TR_OUT1262 = 0x00000B16u, /* tcpwm[0].tr_out1[262] */ + TRIG_IN_MUX_11_TCPWM0_TR_OUT0263 = 0x00000B17u, /* tcpwm[0].tr_out0[263] */ + TRIG_IN_MUX_11_TCPWM0_TR_OUT1263 = 0x00000B18u, /* tcpwm[0].tr_out1[263] */ + TRIG_IN_MUX_11_HSIOM_TR_OUT0 = 0x00000B19u, /* peri.tr_io_input[0] */ + TRIG_IN_MUX_11_HSIOM_TR_OUT1 = 0x00000B1Au, /* peri.tr_io_input[1] */ + TRIG_IN_MUX_11_HSIOM_TR_OUT2 = 0x00000B1Bu, /* peri.tr_io_input[2] */ + TRIG_IN_MUX_11_HSIOM_TR_OUT3 = 0x00000B1Cu, /* peri.tr_io_input[3] */ + TRIG_IN_MUX_11_HSIOM_TR_OUT4 = 0x00000B1Du, /* peri.tr_io_input[4] */ + TRIG_IN_MUX_11_HSIOM_TR_OUT5 = 0x00000B1Eu, /* peri.tr_io_input[5] */ + TRIG_IN_MUX_11_HSIOM_TR_OUT6 = 0x00000B1Fu, /* peri.tr_io_input[6] */ + TRIG_IN_MUX_11_HSIOM_TR_OUT7 = 0x00000B20u, /* peri.tr_io_input[7] */ + TRIG_IN_MUX_11_HSIOM_TR_OUT8 = 0x00000B21u, /* peri.tr_io_input[8] */ + TRIG_IN_MUX_11_HSIOM_TR_OUT9 = 0x00000B22u, /* peri.tr_io_input[9] */ + TRIG_IN_MUX_11_HSIOM_TR_OUT10 = 0x00000B23u, /* peri.tr_io_input[10] */ + TRIG_IN_MUX_11_HSIOM_TR_OUT11 = 0x00000B24u, /* peri.tr_io_input[11] */ + TRIG_IN_MUX_11_HSIOM_TR_OUT12 = 0x00000B25u, /* peri.tr_io_input[12] */ + TRIG_IN_MUX_11_HSIOM_TR_OUT13 = 0x00000B26u, /* peri.tr_io_input[13] */ + TRIG_IN_MUX_11_HSIOM_TR_OUT14 = 0x00000B27u, /* peri.tr_io_input[14] */ + TRIG_IN_MUX_11_HSIOM_TR_OUT15 = 0x00000B28u, /* peri.tr_io_input[15] */ + TRIG_IN_MUX_11_HSIOM_TR_OUT16 = 0x00000B29u, /* peri.tr_io_input[16] */ + TRIG_IN_MUX_11_HSIOM_TR_OUT17 = 0x00000B2Au, /* peri.tr_io_input[17] */ + TRIG_IN_MUX_11_HSIOM_TR_OUT18 = 0x00000B2Bu, /* peri.tr_io_input[18] */ + TRIG_IN_MUX_11_HSIOM_TR_OUT19 = 0x00000B2Cu, /* peri.tr_io_input[19] */ + TRIG_IN_MUX_11_HSIOM_TR_OUT20 = 0x00000B2Du, /* peri.tr_io_input[20] */ + TRIG_IN_MUX_11_HSIOM_TR_OUT21 = 0x00000B2Eu, /* peri.tr_io_input[21] */ + TRIG_IN_MUX_11_HSIOM_TR_OUT22 = 0x00000B2Fu, /* peri.tr_io_input[22] */ + TRIG_IN_MUX_11_HSIOM_TR_OUT23 = 0x00000B30u, /* peri.tr_io_input[23] */ + TRIG_IN_MUX_11_LPCOMP_DSI_COMP0 = 0x00000B31u, /* lpcomp.dsi_comp0 */ + TRIG_IN_MUX_11_LPCOMP_DSI_COMP1 = 0x00000B32u /* lpcomp.dsi_comp1 */ +} en_trig_input_ctadc_strobe_t; + /* Trigger Group Outputs */ /* Trigger Output Group 0 - PDMA0 Request Assignments */ typedef enum @@ -893,6 +948,12 @@ typedef enum TRIG_OUT_MUX_10_CAN_TT_TR_IN0 = 0x40000A00u /* canfd[0].tr_evt_swt_in[0] */ } en_trig_output_cantt_t; +/* Trigger Output Group 11 - CTDAC trigger multiplexer */ +typedef enum +{ + TRIG_OUT_MUX_11_PASS_CTDAC_STROBE = 0x40000B00u /* pass.dsi_ctdac_strobe */ +} en_trig_output_ctadc_strobe_t; + /* Trigger Output Group 0 - SCB PDMA0 Triggers (OneToOne) */ typedef enum { @@ -1101,7 +1162,6 @@ typedef enum #include "ip/cyip_smif.h" #include "ip/cyip_canfd.h" #include "ip/cyip_scb.h" -#include "ip/cyip_scb.h" #include "ip/cyip_ctbm_v2.h" #include "ip/cyip_ctdac_v2.h" #include "ip/cyip_sar_v2.h" @@ -2558,7 +2618,7 @@ typedef PASS_V2_Type PASS_Type; /* Trigger module present (0=No, 1=Yes) */ #define PERI_TR 1u /* Number of trigger groups */ -#define PERI_TR_GROUP_NR 11u +#define PERI_TR_GROUP_NR 12u /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ #define PERI_TR_GROUP_NR0_TR_GROUP_TR_MANIPULATION_PRESENT 1u /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ @@ -2581,6 +2641,8 @@ typedef PASS_V2_Type PASS_Type; #define PERI_TR_GROUP_NR9_TR_GROUP_TR_MANIPULATION_PRESENT 1u /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ #define PERI_TR_GROUP_NR10_TR_GROUP_TR_MANIPULATION_PRESENT 1u +/* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ +#define PERI_TR_GROUP_NR11_TR_GROUP_TR_MANIPULATION_PRESENT 1u /* Trigger 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ #define PERI_TR_1TO1_GROUP_NR0_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u /* Trigger 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ @@ -2752,56 +2814,6 @@ typedef PASS_V2_Type PASS_Type; /* Number of used spi_select signals (max 4) */ #define SCB2_CHIP_TOP_SPI_SEL_NR 3u /* DeepSleep support ('0':no, '1': yes) */ -#define SCB3_DEEPSLEEP 0u -/* Externally clocked support? ('0': no, '1': yes) */ -#define SCB3_EC 0u -/* I2C master support? ('0': no, '1': yes) */ -#define SCB3_I2C_M 1u -/* I2C slave support? ('0': no, '1': yes) */ -#define SCB3_I2C_S 1u -/* I2C support? (I2C_M | I2C_S) */ -#define SCB3_I2C 1u -/* I2C glitch filters present? ('0': no, '1': yes) */ -#define SCB3_I2C_GLITCH 1u -/* I2C externally clocked support? ('0': no, '1': yes) */ -#define SCB3_I2C_EC 0u -/* I2C master and slave support? (I2C_M & I2C_S) */ -#define SCB3_I2C_M_S 1u -/* I2C slave with EC? (I2C_S & I2C_EC) */ -#define SCB3_I2C_S_EC 0u -/* SPI master support? ('0': no, '1': yes) */ -#define SCB3_SPI_M 1u -/* SPI slave support? ('0': no, '1': yes) */ -#define SCB3_SPI_S 1u -/* SPI support? (SPI_M | SPI_S) */ -#define SCB3_SPI 1u -/* SPI externally clocked support? ('0': no, '1': yes) */ -#define SCB3_SPI_EC 0u -/* SPI slave with EC? (SPI_S & SPI_EC) */ -#define SCB3_SPI_S_EC 0u -/* UART support? ('0': no, '1': yes) */ -#define SCB3_UART 1u -/* SPI or UART (SPI | UART) */ -#define SCB3_SPI_UART 1u -/* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, - CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only - 256 B are used. This is because the EZ mode uses 8-bit addresses. */ -#define SCB3_EZ_DATA_NR 256u -/* Command/response mode support? ('0': no, '1': yes) */ -#define SCB3_CMD_RESP 0u -/* EZ mode support? ('0': no, '1': yes) */ -#define SCB3_EZ 0u -/* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ -#define SCB3_EZ_CMD_RESP 0u -/* I2C slave with EZ mode (I2C_S & EZ) */ -#define SCB3_I2C_S_EZ 0u -/* SPI slave with EZ mode (SPI_S & EZ) */ -#define SCB3_SPI_S_EZ 0u -/* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ -#define SCB3_I2C_FAST_PLUS 1u -/* Number of used spi_select signals (max 4) */ -#define SCB3_CHIP_TOP_SPI_SEL_NR 3u -/* DeepSleep support ('0':no, '1': yes) */ #define SCB4_DEEPSLEEP 0u /* Externally clocked support? ('0': no, '1': yes) */ #define SCB4_EC 0u @@ -2901,6 +2913,56 @@ typedef PASS_V2_Type PASS_Type; #define SCB5_I2C_FAST_PLUS 1u /* Number of used spi_select signals (max 4) */ #define SCB5_CHIP_TOP_SPI_SEL_NR 4u +/* DeepSleep support ('0':no, '1': yes) */ +#define SCB6_DEEPSLEEP 1u +/* Externally clocked support? ('0': no, '1': yes) */ +#define SCB6_EC 1u +/* I2C master support? ('0': no, '1': yes) */ +#define SCB6_I2C_M 1u +/* I2C slave support? ('0': no, '1': yes) */ +#define SCB6_I2C_S 1u +/* I2C support? (I2C_M | I2C_S) */ +#define SCB6_I2C 1u +/* I2C glitch filters present? ('0': no, '1': yes) */ +#define SCB6_I2C_GLITCH 1u +/* I2C externally clocked support? ('0': no, '1': yes) */ +#define SCB6_I2C_EC 1u +/* I2C master and slave support? (I2C_M & I2C_S) */ +#define SCB6_I2C_M_S 1u +/* I2C slave with EC? (I2C_S & I2C_EC) */ +#define SCB6_I2C_S_EC 1u +/* SPI master support? ('0': no, '1': yes) */ +#define SCB6_SPI_M 1u +/* SPI slave support? ('0': no, '1': yes) */ +#define SCB6_SPI_S 1u +/* SPI support? (SPI_M | SPI_S) */ +#define SCB6_SPI 1u +/* SPI externally clocked support? ('0': no, '1': yes) */ +#define SCB6_SPI_EC 1u +/* SPI slave with EC? (SPI_S & SPI_EC) */ +#define SCB6_SPI_S_EC 1u +/* UART support? ('0': no, '1': yes) */ +#define SCB6_UART 0u +/* SPI or UART (SPI | UART) */ +#define SCB6_SPI_UART 1u +/* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, + CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only + 256 B are used. This is because the EZ mode uses 8-bit addresses. */ +#define SCB6_EZ_DATA_NR 256u +/* Command/response mode support? ('0': no, '1': yes) */ +#define SCB6_CMD_RESP 1u +/* EZ mode support? ('0': no, '1': yes) */ +#define SCB6_EZ 1u +/* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ +#define SCB6_EZ_CMD_RESP 1u +/* I2C slave with EZ mode (I2C_S & EZ) */ +#define SCB6_I2C_S_EZ 1u +/* SPI slave with EZ mode (SPI_S & EZ) */ +#define SCB6_SPI_S_EZ 1u +/* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ +#define SCB6_I2C_FAST_PLUS 1u +/* Number of used spi_select signals (max 4) */ +#define SCB6_CHIP_TOP_SPI_SEL_NR 1u /* SONOS Flash is used or not ('0': no, '1': yes) */ #define SFLASH_FLASHC_IS_SONOS 1u /* CPUSS_WOUNDING_PRESENT or not ('0': no, '1': yes) */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_ble_clk.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_ble_clk.h index c23e6316f9..140470c15e 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_ble_clk.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_ble_clk.h @@ -1,7 +1,7 @@ /***************************************************************************//** * \file cy_ble_clk.h -* \version 3.40 -* +* \version 3.40.1 +* * The header file of the BLE ECO clock driver. * ******************************************************************************** @@ -27,18 +27,18 @@ * \{ * This driver provides an API to manage the BLE ECO clock block. * -* The functions and other declarations used in this driver are in cy_ble_clk.h. -* You can include cy_pdl.h (ModusToolbox only) to get access to all functions -* and declarations in the PDL. +* The functions and other declarations used in this driver are in cy_ble_clk.h. +* You can include cy_pdl.h to get access to all functions +* and declarations in the PDL. * * The BLE ECO clock is a high-accuracy high-frequency clock that feeds the -* link-layer controller and the radio Phy. +* link-layer controller and the radio Phy. * * This clock is also an input to the system resources subsystem as an * alternative high-frequency clock source (ALTHF). * * \section group_ble_configuration_considerations Configuration Considerations -* To configure the BLE ECO clock, call Cy_BLE_EcoConfigure(). +* To configure the BLE ECO clock, call Cy_BLE_EcoConfigure(). * * The following code shows how to configure the BLE ECO clock: * \snippet bleclk/snippet/main.c BLE ECO clock API: Cy_BLE_EcoConfigure() @@ -70,6 +70,11 @@ * * * +* +* +* +* +* * * * @@ -202,7 +207,7 @@ typedef enum /** Invalid Link Layer clock divider */ CY_BLE_SYS_ECO_CLK_DIV_INVALID - + } cy_en_ble_eco_sys_clk_div_t; /** BLE ECO Clock return value */ @@ -219,10 +224,10 @@ typedef enum /** ECO already started */ CY_BLE_ECO_ALREADY_STARTED = CY_PDL_STATUS_ERROR | CY_BLE_CLK_ID | 0x0003UL, - + /** Hardware error */ CY_BLE_ECO_HARDWARE_ERROR = CY_PDL_STATUS_ERROR | CY_BLE_CLK_ID | 0x0004UL, - + } cy_en_ble_eco_status_t; /** BLE Voltage regulator */ @@ -230,10 +235,10 @@ typedef enum { /** Use SIMO Buck or BLE LDO regulator depend on system usage */ CY_BLE_ECO_VOLTAGE_REG_AUTO, - + /** Use BLE LDO */ CY_BLE_ECO_VOLTAGE_REG_BLESSLDO - + } cy_en_ble_eco_voltage_reg_t; /** \} */ @@ -246,15 +251,15 @@ typedef enum /** BLE ECO configuration structures */ typedef struct { - /** + /** * ECO crystal startup time in multiple of 31.25us (startup_time_from_user min - 31.25us) - * ecoXtalStartUpTime = startup_time_from_user/31.25 + * ecoXtalStartUpTime = startup_time_from_user/31.25 */ uint8_t ecoXtalStartUpTime; - /** + /** * ECO crystal load capacitance - In multiple of 0.075pF (pF_from_user min - 7.5pF, pF_from_user max - 26.625pF) - * loadcap = ((pF_from_user - 7.5)/0.075) + * loadcap = ((pF_from_user - 7.5)/0.075) */ uint8_t loadCap; @@ -263,7 +268,7 @@ typedef struct /** System divider for ECO clock. */ cy_en_ble_eco_sys_clk_div_t ecoSysDiv; - + } cy_stc_ble_eco_config_t; /** \endcond */ @@ -334,4 +339,3 @@ void Cy_BLE_HAL_Init(void); /** \} group_ble_clk */ /* [] END OF FILE */ - diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto.h index f5247c9226..b81191d701 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto.h -* \version 2.30.2 +* \version 2.30.3 * * \brief * This file provides the public interface for the Crypto driver. @@ -32,7 +32,7 @@ * * The functions and other declarations used in this driver are in cy_crypto.h, * cy_crypto_core.h, and cy_crypto_server.h. You can also include cy_pdl.h -* (ModusToolbox only) to get access to all functions and declarations in the PDL. +* to get access to all functions and declarations in the PDL. * * The driver implements two usage models: * * \ref group_crypto_cli_srv @@ -291,6 +291,11 @@ *
VersionChangesReason of Change
3.40.1Minor documentation updates.Documentation enhancement.
3.40A new API function \ref Cy_BLE_EcoIsEnabled() is added.API enhancement.
* * +* +* +* +* +* * *
VersionChangesReason for Change
2.30.3Minor documentation updates.Documentation enhancement.
2.30.1 * Added a C++ namespace guards. @@ -440,7 +445,7 @@ * * The functions and other declarations used in this part of the driver are in * cy_crypto.h and cy_crypto_server.h. You can also include cy_pdl.h -* (ModusToolbox only) to get access to all functions and declarations in the +* to get access to all functions and declarations in the * PDL. * * The firmware initializes and starts the Crypto server. The server can run on any diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_common.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_common.h index a98ad25eda..2af55fb8bc 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_common.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_common.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_common.h -* \version 2.30.2 +* \version 2.30.3 * * \brief * This file provides common constants and parameters diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core.h index 157307e3ba..e0119b529b 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core.h -* \version 2.30.2 +* \version 2.30.3 * * \brief * This file provides common constants and parameters @@ -29,7 +29,7 @@ * Use the low-level API for direct access to the Crypto hardware. * * The functions and other declarations used in this part of the driver are in -* cy_crypto_core.h. You can also include cy_pdl.h (ModusToolbox only) to get +* cy_crypto_core.h. You can also include cy_pdl.h to get * access to all functions and declarations in the PDL. * * Firmware initializes and starts the Crypto operations. The firmware then diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_aes.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_aes.h index 9d18584e22..dd0dbcd133 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_aes.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_aes.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_aes.h -* \version 2.30.2 +* \version 2.30.3 * * \brief * This file provides constant and parameters for the API for the AES method @@ -439,4 +439,3 @@ __STATIC_INLINE cy_en_crypto_status_t Cy_Crypto_Core_Aes_Ctr(CRYPTO_Type *base, /* [] END OF FILE */ - diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_aes_v1.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_aes_v1.h index ab8ba088f7..c9077ef4b7 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_aes_v1.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_aes_v1.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_aes_v1.h -* \version 2.30.2 +* \version 2.30.3 * * \brief * This file provides constant and parameters for the API for the AES method diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_aes_v2.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_aes_v2.h index de29e5f17f..8774bfce3a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_aes_v2.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_aes_v2.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_aes_v2.h -* \version 2.30.2 +* \version 2.30.3 * * \brief * This file provides constant and parameters for the API for the AES method @@ -94,4 +94,3 @@ cy_en_crypto_status_t Cy_Crypto_Core_V2_Aes_Ctr(CRYPTO_Type *base, /* [] END OF FILE */ - diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_cmac.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_cmac.h index accf85d2cf..2824bf1414 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_cmac.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_cmac.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_cmac.h -* \version 2.30.2 +* \version 2.30.3 * * \brief * This file provides constants and function prototypes diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_cmac_v1.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_cmac_v1.h index 3179fdfbf6..7b91a82eba 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_cmac_v1.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_cmac_v1.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_cmac_v1.h -* \version 2.30.2 +* \version 2.30.3 * * \brief * This file provides constants and function prototypes diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_cmac_v2.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_cmac_v2.h index d22928288b..6e0a86c03d 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_cmac_v2.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_cmac_v2.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_cmac_v2.h -* \version 2.30.2 +* \version 2.30.3 * * \brief * This file provides constants and function prototypes diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_crc.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_crc.h index 1731956f43..22903c91f9 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_crc.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_crc.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_crc.h -* \version 2.30.2 +* \version 2.30.3 * * \brief * This file provides the headers for CRC API diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_crc_v1.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_crc_v1.h index bdaa99162b..e3fd62f360 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_crc_v1.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_crc_v1.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_crc_v1.h -* \version 2.30.2 +* \version 2.30.3 * * \brief * This file provides the headers for CRC API diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_crc_v2.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_crc_v2.h index fe1af68be3..83485ca221 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_crc_v2.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_crc_v2.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_crc_v2.h -* \version 2.30.2 +* \version 2.30.3 * * \brief * This file provides the headers for CRC API diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_des.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_des.h index 2743bd025a..fac5548242 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_des.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_des.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_des.h -* \version 2.30.2 +* \version 2.30.3 * * \brief * This file provides constant and parameters for the API for the DES method diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_des_v1.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_des_v1.h index 5cec116209..7034b7a7d0 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_des_v1.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_des_v1.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_des.h -* \version 2.30.2 +* \version 2.30.3 * * \brief * This file provides constant and parameters for the API for the DES method @@ -62,4 +62,3 @@ cy_en_crypto_status_t Cy_Crypto_Core_V1_Tdes(CRYPTO_Type *base, /* [] END OF FILE */ - diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_des_v2.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_des_v2.h index e61b2e31fa..5d766a6e81 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_des_v2.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_des_v2.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_des_v2.h -* \version 2.30.2 +* \version 2.30.3 * * \brief * This file provides constant and parameters for the API for the DES method @@ -62,4 +62,3 @@ cy_en_crypto_status_t Cy_Crypto_Core_V2_Tdes(CRYPTO_Type *base, /* [] END OF FILE */ - diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_ecc.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_ecc.h index 99eda60a9e..bf6c1201b6 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_ecc.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_ecc.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_ecc.h -* \version 2.30.2 +* \version 2.30.3 * * \brief * This file provides constant and parameters for the API for the ECC diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_ecc_nist_p.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_ecc_nist_p.h index c3171340f6..87848c3e77 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_ecc_nist_p.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_ecc_nist_p.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_ecc_nist_p.h -* \version 2.30.2 +* \version 2.30.3 * * \brief * This file provides constant and parameters for the API for the ECC diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_hmac.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_hmac.h index 8bc71f0ed8..f433bc5429 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_hmac.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_hmac.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_hmac.h -* \version 2.30.2 +* \version 2.30.3 * * \brief * This file provides constants and function prototypes diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_hmac_v1.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_hmac_v1.h index b922365f01..2dab57cf8c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_hmac_v1.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_hmac_v1.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_hmac_v1.h -* \version 2.30.2 +* \version 2.30.3 * * \brief * This file provides constants and function prototypes diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_hmac_v2.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_hmac_v2.h index 08a58487fc..6895bf087a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_hmac_v2.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_hmac_v2.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_hmac_v2.h -* \version 2.30.2 +* \version 2.30.3 * * \brief * This file provides constants and function prototypes diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_hw.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_hw.h index cc070380bf..5e955e8f0e 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_hw.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_hw.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_hw.h -* \version 2.30.2 +* \version 2.30.3 * * \brief * This file provides the headers to the API for the utils @@ -531,4 +531,3 @@ __STATIC_INLINE uint32_t * Cy_Crypto_Core_GetVuMemoryAddress(CRYPTO_Type *base) /* [] END OF FILE */ - diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_hw_v1.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_hw_v1.h index e43de21c81..15ab6453d9 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_hw_v1.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_hw_v1.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_hw_v1.h -* \version 2.30.2 +* \version 2.30.3 * * \brief * This file provides constants and function prototypes diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_hw_v2.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_hw_v2.h index 1c9f5ffd5c..048860614e 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_hw_v2.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_hw_v2.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_hw_v2.h -* \version 2.30.2 +* \version 2.30.3 * * \brief * This file provides constants and function prototypes diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_hw_vu.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_hw_vu.h index dd6bd968e5..8e1ae42185 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_hw_vu.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_hw_vu.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_hw_vu.h -* \version 2.30.2 +* \version 2.30.3 * * \brief * This file provides constants and function prototypes diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_mem.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_mem.h index 859b57525a..0446a5c65e 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_mem.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_mem.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_mem.h -* \version 2.30.2 +* \version 2.30.3 * * \brief * This file provides the headers for the memory management API diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_mem_v1.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_mem_v1.h index 9f841df387..91c6bcbff4 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_mem_v1.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_mem_v1.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_mem_v1.h -* \version 2.30.2 +* \version 2.30.3 * * \brief * This file provides the headers for the string management API diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_mem_v2.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_mem_v2.h index 7e2b1d6675..fa4d464cba 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_mem_v2.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_mem_v2.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_mem_v2.h -* \version 2.30.2 +* \version 2.30.3 * * \brief * This file provides the headers for the string management API diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_prng.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_prng.h index 598a4fb118..8cbfb364a9 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_prng.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_prng.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_prng.h -* \version 2.30.2 +* \version 2.30.3 * * \brief * This file provides provides constant and parameters for the API of the PRNG diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_prng_v1.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_prng_v1.h index eb7c0cdb3d..482aa26ae2 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_prng_v1.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_prng_v1.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_prng.h -* \version 2.30.2 +* \version 2.30.3 * * \brief * This file provides provides constant and parameters for the API of the PRNG diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_prng_v2.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_prng_v2.h index 91698d6451..1021128a34 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_prng_v2.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_prng_v2.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_prng_v2.h -* \version 2.30.2 +* \version 2.30.3 * * \brief * This file provides provides constant and parameters for the API of the PRNG diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_rsa.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_rsa.h index b8c207cbe2..5affedf488 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_rsa.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_rsa.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_rsa.h -* \version 2.30.2 +* \version 2.30.3 * * \brief * This file provides provides constant and parameters diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_sha.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_sha.h index 763233b4d2..070c9e8820 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_sha.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_sha.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_sha.h -* \version 2.30.2 +* \version 2.30.3 * * \brief * This file provides constants and function prototypes diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_sha_v1.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_sha_v1.h index cba68a7186..8527f18183 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_sha_v1.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_sha_v1.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_sha.h -* \version 2.30.2 +* \version 2.30.3 * * \brief * This file provides constants and function prototypes diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_sha_v2.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_sha_v2.h index 29ea2561c2..2d1e7b44d9 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_sha_v2.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_sha_v2.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_sha_v2.h -* \version 2.30.2 +* \version 2.30.3 * * \brief * This file provides constants and function prototypes diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_trng.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_trng.h index 01358034da..b850445835 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_trng.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_trng.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_trng.h -* \version 2.30.2 +* \version 2.30.3 * * \brief * This file provides provides constant and parameters diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_trng_config_v1.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_trng_config_v1.h index 2af31b04c9..ee80546c94 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_trng_config_v1.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_trng_config_v1.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_trng_config_v1.h -* \version 2.30.2 +* \version 2.30.3 * * \brief * This file provides internal (not public) constants and parameters diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_trng_config_v2.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_trng_config_v2.h index 170ba3c6d2..688ceed865 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_trng_config_v2.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_trng_config_v2.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_trng_config_v2.h -* \version 2.30.2 +* \version 2.30.3 * * \brief * This file provides internal (not public) constants and parameters diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_trng_v1.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_trng_v1.h index 66e36e5e51..0f2eafb625 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_trng_v1.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_trng_v1.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_trng_v1.h -* \version 2.30.2 +* \version 2.30.3 * * \brief * This file provides provides constant and parameters diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_trng_v2.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_trng_v2.h index fdcddb4bac..c00e49ad0d 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_trng_v2.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_trng_v2.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_trng_v2.h -* \version 2.30.2 +* \version 2.30.3 * * \brief * This file provides provides constant and parameters diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_vu.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_vu.h index 038f9e98c5..51acad6001 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_vu.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_core_vu.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_hw.h -* \version 2.30.2 +* \version 2.30.3 * * \brief * This file provides the headers to the API for the utils @@ -341,4 +341,3 @@ void Cy_Crypto_Core_VU_RegInvertEndianness(CRYPTO_Type *base, uint32_t srcReg); #endif /* #if !defined(CY_CRYPTO_CORE_VU_H) */ /* [] END OF FILE */ - diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_server.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_server.h index fd0645d2ed..1f256198ae 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_server.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_crypto_server.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_server.h -* \version 2.30.2 +* \version 2.30.3 * * \brief * This file provides the prototypes for common API diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_csd.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_csd.h index f88605b284..9ae0fc1d2d 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_csd.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_csd.h @@ -1,12 +1,12 @@ /***************************************************************************//** * \file cy_csd.h -* \version 1.10 +* \version 1.10.1 * * The header file of the CSD driver. * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -254,22 +254,22 @@ * * Technical Reference Manual (TRM) * * * -* Cypress CapSense Middleware Library +* CapSense Middleware Library * * * -* Cypress CapSense Middleware API Reference Guide +* CapSense Middleware API Reference Guide * * * -* Cypress CSDADC Middleware Library +* CSDADC Middleware Library * * * -* Cypress CSDADC Middleware API Reference Guide +* CSDADC Middleware API Reference Guide * * * -* Cypress CSDIDAC Middleware Library +* CSDIDAC Middleware Library * * * -* Cypress CSDIDAC Middleware API Reference Guide +* CSDIDAC Middleware API Reference Guide * * * \ref page_getting_started "Getting Started with the PDL" * @@ -312,6 +312,11 @@ * * * +* +* +* +* +* * *
VersionChangesReason for Change
1.10.1Documentation updatesUpdate middleware references
1.10The CSD driver sources are enclosed with the conditional compilation * to ensure a successful compilation for non-CapSense-capable devices diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_ctb.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_ctb.h index fba32dcf7e..2084866195 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_ctb.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_ctb.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_ctb.h -* \version 1.10.2 +* \version 1.20 * * Header file for the CTB driver * @@ -27,8 +27,8 @@ * \{ * This driver provides API functions to configure and use the analog CTB. * -* The functions and other declarations used in this driver are in cy_ctb.h. -* You can include cy_pdl.h (ModusToolbox only) to get access to all functions +* The functions and other declarations used in this driver are in cy_ctb.h. +* You can include cy_pdl.h to get access to all functions * and declarations in the PDL. * * The CTB comprises two identical opamps, a switch routing matrix, @@ -287,6 +287,16 @@ * * * +* +* +* +* +* +* +* +* +* +* * * @@ -299,7 +309,7 @@ * * * -* * @@ -308,7 +318,7 @@ * * -* * * @@ -1550,4 +1560,3 @@ __STATIC_INLINE void Cy_CTB_DisableRedirect(void) /** \} group_ctb */ /* [] END OF FILE */ - diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_ctdac.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_ctdac.h index 18f2e0078c..bd4a0403f7 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_ctdac.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_ctdac.h @@ -1,12 +1,12 @@ /***************************************************************************//** * \file cy_ctdac.h -* \version 2.0 +* \version 2.0.1 * * Header file for the CTDAC driver * ******************************************************************************** * \copyright -* Copyright 2017-2019 Cypress Semiconductor Corporation +* Copyright 2017-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -27,8 +27,8 @@ * \{ * The CTDAC driver provides APIs to configure the 12-bit Continuous-Time DAC. * -* The functions and other declarations used in this driver are in cy_ctdac.h. -* You can include cy_pdl.h (ModusToolbox only) to get access to all functions +* The functions and other declarations used in this driver are in cy_ctdac.h. +* You can include cy_pdl.h to get access to all functions * and declarations in the PDL. * * - 12-bit continuous time output @@ -322,8 +322,13 @@ *
VersionChangesReason for Change
1.20Fixed the \ref Cy_CTB_OpampInit function to do not affect another OpAmp instance.Bug fixing.
1.10.3Minor documentation updates.Documentation enhancement.
1.10.2The \ref Cy_CTB_Init function description is expanded with a * clarification note.
1.10Flattened the organization of the driver source code into the single +* Flattened the organization of the driver source code into the single * source directory and the single include directory. * Driver library directory-structure simplification.
Added register access layer. Use register access macros instead * of direct register access using dereferenced pointers.Makes register access device-independent, so that the PDL does +* Makes register access device-independent, so that the PDL does * not need to be recompiled for each supported part number.
* * +* +* +* +* +* * -* * @@ -331,7 +336,7 @@ * * -* * * @@ -1084,4 +1089,3 @@ __STATIC_INLINE uint32_t Cy_CTDAC_GetInterruptStatusMasked(const CTDAC_Type *bas /** \} group_ctdac */ /* [] END OF FILE */ - diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_device.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_device.h index d438e510a1..44dca6df2b 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_device.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_device.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_device.h -* \version 2.10 +* \version 2.20 * * This file specifies the structure for core and peripheral block HW base * addresses, versions, and parameters. @@ -120,6 +120,7 @@ typedef struct uint8_t srssNumClkpath; uint8_t srssNumPll; uint8_t srssNumHfroot; + uint8_t srssIsPiloPresent; uint8_t periClockNr; uint8_t smifDeviceNr; uint8_t passSarChannels; @@ -220,6 +221,8 @@ void Cy_PDL_Init(const cy_stc_device_t * device); #define CY_SRSS_V1_3 (0x13U == cy_device->srssVersion) #define CY_SRSS_MFO_PRESENT (CY_SRSS_V1_3) +#define CY_SRSS_PILO_PRESENT (1U == cy_device->srssIsPiloPresent) + #define CY_SRSS_NUM_CLKPATH ((uint32_t)(cy_device->srssNumClkpath)) #define CY_SRSS_NUM_PLL ((uint32_t)(cy_device->srssNumPll)) #define CY_SRSS_NUM_HFROOT ((uint32_t)(cy_device->srssNumHfroot)) @@ -950,6 +953,7 @@ void Cy_PDL_Init(const cy_stc_device_t * device); #define CY_IPC_CHAN_SYSCALL_CM4 (1U) /* System calls for the 1st non-CM0 processor */ #define CY_IPC_CHAN_SYSCALL_DAP (2UL) /* System calls for the DAP */ #define CY_IPC_CHAN_SEMA (3UL) /* IPC data channel for the Semaphores */ +#define CY_IPC_CHAN_PRA (4UL) /* IPC data channel for PRA */ #define CY_IPC_CHAN_CYPIPE_EP0 (5UL) /* IPC data channel for CYPIPE EP0 */ #define CY_IPC_CHAN_CYPIPE_EP1 (6UL) /* IPC data channel for CYPIPE EP1 */ #define CY_IPC_CHAN_DDFT (7UL) /* IPC data channel for DDFT */ @@ -958,6 +962,7 @@ void Cy_PDL_Init(const cy_stc_device_t * device); #define CY_IPC_INTR_SYSCALL1 (0UL) #define CY_IPC_INTR_CYPIPE_EP0 (3UL) #define CY_IPC_INTR_CYPIPE_EP1 (4UL) +#define CY_IPC_INTR_PRA (5UL) #define CY_IPC_INTR_SPARE (7UL) /* Endpoint indexes in the pipe array */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_dma.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_dma.h index 514ba7b8ee..eecb3bc801 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_dma.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_dma.h @@ -1,13 +1,13 @@ /***************************************************************************//** * \file cy_dma.h -* \version 2.20 +* \version 2.20.1 * * \brief * The header file of the DMA driver. * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -28,18 +28,18 @@ * \{ * Configures a DMA channel and its descriptor(s). * -* The functions and other declarations used in this driver are in cy_dma.h. -* You can include cy_pdl.h (ModusToolbox only) to get access to all functions +* The functions and other declarations used in this driver are in cy_dma.h. +* You can include cy_pdl.h to get access to all functions * and declarations in the PDL. * * The DMA channel can be used in any project to transfer data * without CPU intervention basing on a hardware trigger signal from another component. * -* A device may support more than one DMA hardware block. Each block has a set of -* registers, a base hardware address, and supports multiple channels. -* Many API functions for the DMA driver require a base hardware address and +* A device may support more than one DMA hardware block. Each block has a set of +* registers, a base hardware address, and supports multiple channels. +* Many API functions for the DMA driver require a base hardware address and * channel number. Ensure that you use the correct hardware address for the DMA block in use. -* +* * Features: * * Multiple DW blocks (device specific) * * Multiple channels per each DW block (device specific) @@ -52,14 +52,14 @@ * * To set up a DMA driver, initialize a descriptor, * initialize and enable a channel, and enable the DMA block. -* -* To set up a descriptor, provide the configuration parameters for the -* descriptor in the \ref cy_stc_dma_descriptor_config_t structure. Then call the -* \ref Cy_DMA_Descriptor_Init function to initialize the descriptor in SRAM. You can -* modify the source and destination addresses dynamically by calling +* +* To set up a descriptor, provide the configuration parameters for the +* descriptor in the \ref cy_stc_dma_descriptor_config_t structure. Then call the +* \ref Cy_DMA_Descriptor_Init function to initialize the descriptor in SRAM. You can +* modify the source and destination addresses dynamically by calling * \ref Cy_DMA_Descriptor_SetSrcAddress and \ref Cy_DMA_Descriptor_SetDstAddress. -* -* To set up a DMA channel, provide a filled \ref cy_stc_dma_channel_config_t +* +* To set up a DMA channel, provide a filled \ref cy_stc_dma_channel_config_t * structure. Call the \ref Cy_DMA_Channel_Init function, specifying the channel * number. Use \ref Cy_DMA_Channel_Enable to enable the configured DMA channel. * @@ -74,15 +74,15 @@ * in a typical user application: * \image html dma.png * -* NOTE: Even if a DMA channel is enabled, it is not operational until +* NOTE: Even if a DMA channel is enabled, it is not operational until * the DMA block is enabled using function \ref Cy_DMA_Enable.\n -* NOTE: If the DMA descriptor is configured to generate an interrupt, -* the interrupt must be enabled using the \ref Cy_DMA_Channel_SetInterruptMask +* NOTE: If the DMA descriptor is configured to generate an interrupt, +* the interrupt must be enabled using the \ref Cy_DMA_Channel_SetInterruptMask * function for each DMA channel. * * For example: * \snippet dma/snippet/main.c snippet_Cy_DMA_Enable -* +* * \section group_dma_more_information More Information. * See: the DMA chapter of the device technical reference manual (TRM); * the DMA Component datasheet; @@ -121,6 +121,11 @@ *
VersionChangesReason for Change
2.0.1Minor documentation updates.Documentation enhancement.
2.0Flattened the organization of the driver source code into the single +* Flattened the organization of the driver source code into the single * source directory and the single include directory. * Driver library directory-structure simplification.
Added register access layer. Use register access macros instead * of direct register access using dereferenced pointers.Makes register access device-independent, so that the PDL does +* Makes register access device-independent, so that the PDL does * not need to be recompiled for each supported part number.
* * +* +* +* +* +* * * * @@ -137,7 +142,7 @@ * * -* * * @@ -153,10 +158,10 @@ * The \ref Cy_DMA_Descriptor_Init function sets a full bunch of descriptor * settings, and the rest of the descriptor API is a get/set interface * to each of the descriptor settings. -* * There is a group of macros to support the backward compatibility with most +* * There is a group of macros to support the backward compatibility with most * of the driver version 1.0 API. But, you should use * the new v2.0 interface in new designs (do not just copy-paste from old -* projects). To enable the backward compatibility support, the CY_DMA_BWC +* projects). To enable the backward compatibility support, the CY_DMA_BWC * definition should be changed to "1". * * @@ -212,7 +217,7 @@ extern "C" { /** The DMA driver identifier */ #define CY_DMA_ID (CY_PDL_DRV_ID(0x13U)) - + /** The DMA channel interrupt mask */ #define CY_DMA_INTR_MASK (0x01UL) @@ -226,7 +231,7 @@ extern "C" { /** The maximum X/Y Increment API parameters */ #define CY_DMA_LOOP_INCREMENT_MAX (2047L) -/** The backward compatibility flag. Enables a group of macros which provide +/** The backward compatibility flag. Enables a group of macros which provide * the backward compatibility with most of the DMA driver version 1.0 interface. */ #ifndef CY_DMA_BWC #define CY_DMA_BWC (0U) /* Disabled by default */ @@ -304,7 +309,7 @@ typedef enum } cy_en_dma_channel_state_t; /** Contains the return values of the DMA driver */ -typedef enum +typedef enum { CY_DMA_SUCCESS = 0x00UL, /**< Success. */ CY_DMA_BAD_PARAM = CY_DMA_ID | CY_PDL_STATUS_ERROR | 0x01UL /**< The input parameters passed to the DMA API are not valid. */ @@ -384,14 +389,14 @@ typedef enum * \{ */ -/** -* DMA descriptor structure type. It is a user/component-declared structure +/** +* DMA descriptor structure type. It is a user/component-declared structure * allocated in RAM. The DMA HW requires a pointer to this structure to work with it. * * For advanced users: the descriptor can be allocated even in flash, then the user -* manually predefines all the structure items with constants. This is +* manually predefines all the structure items with constants. This is * because most of the driver's API (especially functions modifying -* descriptors, including \ref Cy_DMA_Descriptor_Init()) can't work with +* descriptors, including \ref Cy_DMA_Descriptor_Init()) can't work with * read-only descriptors. */ typedef struct @@ -466,7 +471,7 @@ typedef struct * The XORed value remains in the CRC_REM_RESULT register. */ uint32_t polynomial; /**< CRC polynomial. The polynomial is represented WITHOUT the high order bit (this bit is always assumed '1'). - * The polynomial should be aligned/shifted such that the more significant bits (bit 31 and down) contain the polynomial + * The polynomial should be aligned/shifted such that the more significant bits (bit 31 and down) contain the polynomial * and the less significant bits (bit 0 and up) contain padding '0's. Some frequently used polynomials: * - CRC32: POLYNOMIAL is 0x04c11db7 (x^32 + x^26 + x^23 + x^22 + x^16 + x^12 + x^11 + x^10 + x^8 + x^7 + x^5 + x^4 + x^2 + x + 1). * - CRC16: POLYNOMIAL is 0x80050000 (x^16 + x^15 + x^2 + 1, shifted by 16 bit positions). @@ -533,7 +538,7 @@ __STATIC_INLINE uint32_t Cy_DMA_Channel_GetInterruptStatusMasked(DW_Type const * cy_en_dma_status_t Cy_DMA_Descriptor_Init (cy_stc_dma_descriptor_t * descriptor, cy_stc_dma_descriptor_config_t const * config); void Cy_DMA_Descriptor_DeInit(cy_stc_dma_descriptor_t * descriptor); - + void Cy_DMA_Descriptor_SetNextDescriptor (cy_stc_dma_descriptor_t * descriptor, cy_stc_dma_descriptor_t const * nextDescriptor); void Cy_DMA_Descriptor_SetDescriptorType (cy_stc_dma_descriptor_t * descriptor, cy_en_dma_descriptor_type_t descriptorType); __STATIC_INLINE void Cy_DMA_Descriptor_SetSrcAddress (cy_stc_dma_descriptor_t * descriptor, void const * srcAddress); @@ -596,7 +601,7 @@ __STATIC_INLINE cy_en_dma_channel_state_t Cy_DMA_Descriptor_GetChannelState * \param base * The pointer to the hardware DMA block. * -* \funcusage +* \funcusage * \snippet dma/snippet/main.c snippet_Cy_DMA_Enable * *******************************************************************************/ @@ -615,7 +620,7 @@ __STATIC_INLINE void Cy_DMA_Enable(DW_Type * base) * \param base * The pointer to the hardware DMA block. * -* \funcusage +* \funcusage * \snippet dma/snippet/main.c snippet_Cy_DMA_Disable * *******************************************************************************/ @@ -639,7 +644,7 @@ __STATIC_INLINE void Cy_DMA_Disable(DW_Type * base) * Returns a bit-field with all of the currently active/pending channels in the * DMA block. * -* \funcusage +* \funcusage * \snippet dma/snippet/main.c snippet_Cy_DMA_Disable * *******************************************************************************/ @@ -661,7 +666,7 @@ __STATIC_INLINE uint32_t Cy_DMA_GetActiveChannel(DW_Type const * base) * \return * Returns the pointer to the source of transfer. * -* \funcusage +* \funcusage * \snippet dma/snippet/main.c snippet_Cy_DMA_GetActiveSrcAddress * *******************************************************************************/ @@ -683,7 +688,7 @@ __STATIC_INLINE void * Cy_DMA_GetActiveSrcAddress(DW_Type * base) * \return * Returns the pointer to the destination of transfer. * -* \funcusage +* \funcusage * \snippet dma/snippet/main.c snippet_Cy_DMA_GetActiveSrcAddress * *******************************************************************************/ @@ -712,7 +717,7 @@ __STATIC_INLINE void * Cy_DMA_GetActiveDstAddress(DW_Type * base) * \param srcAddress * The source address value for the descriptor. * -* \funcusage +* \funcusage * \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_SetterFunctions * *******************************************************************************/ @@ -727,14 +732,14 @@ __STATIC_INLINE void Cy_DMA_Descriptor_SetSrcAddress(cy_stc_dma_descriptor_t * d ****************************************************************************//** * * Returns the source address parameter of the specified descriptor. -* +* * \param descriptor * The descriptor structure instance declared by the user/component. * * \return * The source address value of the descriptor. * -* \funcusage +* \funcusage * \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_GetterFunctions * *******************************************************************************/ @@ -756,7 +761,7 @@ __STATIC_INLINE void * Cy_DMA_Descriptor_GetSrcAddress(cy_stc_dma_descriptor_t c * \param dstAddress * The destination address value for the descriptor. * -* \funcusage +* \funcusage * \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_SetterFunctions * *******************************************************************************/ @@ -771,14 +776,14 @@ __STATIC_INLINE void Cy_DMA_Descriptor_SetDstAddress(cy_stc_dma_descriptor_t * d ****************************************************************************//** * * Returns the destination address parameter of the specified descriptor. -* +* * \param descriptor * The descriptor structure instance declared by the user/component. * * \return * The destination address value of the descriptor. * -* \funcusage +* \funcusage * \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_GetterFunctions * *******************************************************************************/ @@ -800,14 +805,14 @@ __STATIC_INLINE void * Cy_DMA_Descriptor_GetDstAddress(cy_stc_dma_descriptor_t c * \param interruptType * The interrupt type set for the descriptor. \ref cy_en_dma_trigger_type_t * -* \funcusage +* \funcusage * \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_SetterFunctions * *******************************************************************************/ __STATIC_INLINE void Cy_DMA_Descriptor_SetInterruptType(cy_stc_dma_descriptor_t * descriptor, cy_en_dma_trigger_type_t interruptType) { CY_ASSERT_L3(CY_DMA_IS_TRIG_TYPE_VALID(interruptType)); - + CY_REG32_CLR_SET(descriptor->ctl, CY_DMA_CTL_INTR_TYPE, interruptType); } @@ -824,9 +829,9 @@ __STATIC_INLINE void Cy_DMA_Descriptor_SetInterruptType(cy_stc_dma_descriptor_t * \return * The Interrupt-Type \ref cy_en_dma_trigger_type_t. * -* \funcusage +* \funcusage * \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_GetterFunctions -* +* *******************************************************************************/ __STATIC_INLINE cy_en_dma_trigger_type_t Cy_DMA_Descriptor_GetInterruptType(cy_stc_dma_descriptor_t const * descriptor) { @@ -846,14 +851,14 @@ __STATIC_INLINE cy_en_dma_trigger_type_t Cy_DMA_Descriptor_GetInterruptType(cy_s * \param triggerInType * The Trigger In Type parameter \ref cy_en_dma_trigger_type_t * -* \funcusage +* \funcusage * \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_SetterFunctions * *******************************************************************************/ __STATIC_INLINE void Cy_DMA_Descriptor_SetTriggerInType(cy_stc_dma_descriptor_t * descriptor, cy_en_dma_trigger_type_t triggerInType) { CY_ASSERT_L3(CY_DMA_IS_TRIG_TYPE_VALID(triggerInType)); - + CY_REG32_CLR_SET(descriptor->ctl, CY_DMA_CTL_TR_IN_TYPE, triggerInType); } @@ -870,9 +875,9 @@ __STATIC_INLINE void Cy_DMA_Descriptor_SetTriggerInType(cy_stc_dma_descriptor_t * \return * The Trigger-In-Type \ref cy_en_dma_trigger_type_t * -* \funcusage +* \funcusage * \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_GetterFunctions -* +* *******************************************************************************/ __STATIC_INLINE cy_en_dma_trigger_type_t Cy_DMA_Descriptor_GetTriggerInType(cy_stc_dma_descriptor_t const * descriptor) { @@ -892,14 +897,14 @@ __STATIC_INLINE cy_en_dma_trigger_type_t Cy_DMA_Descriptor_GetTriggerInType(cy_s * \param triggerOutType * The Trigger-Out-Type set for the descriptor. \ref cy_en_dma_trigger_type_t * -* \funcusage +* \funcusage * \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_SetterFunctions * *******************************************************************************/ __STATIC_INLINE void Cy_DMA_Descriptor_SetTriggerOutType(cy_stc_dma_descriptor_t * descriptor, cy_en_dma_trigger_type_t triggerOutType) { CY_ASSERT_L3(CY_DMA_IS_TRIG_TYPE_VALID(triggerOutType)); - + CY_REG32_CLR_SET(descriptor->ctl, CY_DMA_CTL_TR_OUT_TYPE, triggerOutType); } @@ -916,9 +921,9 @@ __STATIC_INLINE void Cy_DMA_Descriptor_SetTriggerOutType(cy_stc_dma_descriptor_t * \return * The Trigger-Out-Type parameter \ref cy_en_dma_trigger_type_t. * -* \funcusage +* \funcusage * \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_GetterFunctions -* +* *******************************************************************************/ __STATIC_INLINE cy_en_dma_trigger_type_t Cy_DMA_Descriptor_GetTriggerOutType(cy_stc_dma_descriptor_t const * descriptor) { @@ -938,14 +943,14 @@ __STATIC_INLINE cy_en_dma_trigger_type_t Cy_DMA_Descriptor_GetTriggerOutType(cy_ * \param dataSize * The Data Element Size \ref cy_en_dma_data_size_t * -* \funcusage +* \funcusage * \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_SetterFunctions -* +* *******************************************************************************/ __STATIC_INLINE void Cy_DMA_Descriptor_SetDataSize(cy_stc_dma_descriptor_t * descriptor, cy_en_dma_data_size_t dataSize) { CY_ASSERT_L3(CY_DMA_IS_DATA_SIZE_VALID(dataSize)); - + CY_REG32_CLR_SET(descriptor->ctl, CY_DMA_CTL_DATA_SIZE, dataSize); } @@ -962,9 +967,9 @@ __STATIC_INLINE void Cy_DMA_Descriptor_SetDataSize(cy_stc_dma_descriptor_t * des * \return * The Data Element Size \ref cy_en_dma_data_size_t. * -* \funcusage +* \funcusage * \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_GetterFunctions -* +* *******************************************************************************/ __STATIC_INLINE cy_en_dma_data_size_t Cy_DMA_Descriptor_GetDataSize(cy_stc_dma_descriptor_t const * descriptor) { @@ -984,7 +989,7 @@ __STATIC_INLINE cy_en_dma_data_size_t Cy_DMA_Descriptor_GetDataSize(cy_stc_dma_d * \param srcTransferSize * The Source Transfer Size \ref cy_en_dma_transfer_size_t. * -* \funcusage +* \funcusage * \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_SetterFunctions * *******************************************************************************/ @@ -1008,9 +1013,9 @@ __STATIC_INLINE void Cy_DMA_Descriptor_SetSrcTransferSize(cy_stc_dma_descriptor_ * \return * The Source Transfer Size \ref cy_en_dma_transfer_size_t. * -* \funcusage +* \funcusage * \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_GetterFunctions -* +* *******************************************************************************/ __STATIC_INLINE cy_en_dma_transfer_size_t Cy_DMA_Descriptor_GetSrcTransferSize(cy_stc_dma_descriptor_t const * descriptor) { @@ -1030,14 +1035,14 @@ __STATIC_INLINE cy_en_dma_transfer_size_t Cy_DMA_Descriptor_GetSrcTransferSize(c * \param dstTransferSize * The Destination Transfer Size \ref cy_en_dma_transfer_size_t. * -* \funcusage +* \funcusage * \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_SetterFunctions * *******************************************************************************/ __STATIC_INLINE void Cy_DMA_Descriptor_SetDstTransferSize(cy_stc_dma_descriptor_t * descriptor, cy_en_dma_transfer_size_t dstTransferSize) { CY_ASSERT_L3(CY_DMA_IS_XFER_SIZE_VALID(dstTransferSize)); - + CY_REG32_CLR_SET(descriptor->ctl, CY_DMA_CTL_DST_SIZE, dstTransferSize); } @@ -1054,9 +1059,9 @@ __STATIC_INLINE void Cy_DMA_Descriptor_SetDstTransferSize(cy_stc_dma_descriptor_ * \return * The Destination Transfer Size \ref cy_en_dma_transfer_size_t. * -* \funcusage +* \funcusage * \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_GetterFunctions -* +* *******************************************************************************/ __STATIC_INLINE cy_en_dma_transfer_size_t Cy_DMA_Descriptor_GetDstTransferSize(cy_stc_dma_descriptor_t const * descriptor) { @@ -1068,24 +1073,24 @@ __STATIC_INLINE cy_en_dma_transfer_size_t Cy_DMA_Descriptor_GetDstTransferSize(c * Function Name: Cy_DMA_Descriptor_SetRetrigger ****************************************************************************//** * -* Sets the retrigger value that specifies whether the controller should +* Sets the retrigger value that specifies whether the controller should * wait for the input trigger to be deactivated. * * \param descriptor * The descriptor structure instance declared by the user/component. * -* \param retrigger +* \param retrigger * The \ref cy_en_dma_retrigger_t parameter specifies whether the controller * should wait for the input trigger to be deactivated. * -* \funcusage +* \funcusage * \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_SetterFunctions * *******************************************************************************/ __STATIC_INLINE void Cy_DMA_Descriptor_SetRetrigger(cy_stc_dma_descriptor_t * descriptor, cy_en_dma_retrigger_t retrigger) { CY_ASSERT_L3(CY_DMA_IS_RETRIG_VALID(retrigger)); - + CY_REG32_CLR_SET(descriptor->ctl, CY_DMA_CTL_RETRIG, retrigger); } @@ -1094,7 +1099,7 @@ __STATIC_INLINE void Cy_DMA_Descriptor_SetRetrigger(cy_stc_dma_descriptor_t * de * Function Name: Cy_DMA_Descriptor_GetRetrigger ****************************************************************************//** * -* Returns a value that specifies whether the controller should +* Returns a value that specifies whether the controller should * wait for the input trigger to be deactivated. * * \param descriptor @@ -1103,9 +1108,9 @@ __STATIC_INLINE void Cy_DMA_Descriptor_SetRetrigger(cy_stc_dma_descriptor_t * de * \return * The Retrigger setting \ref cy_en_dma_retrigger_t. * -* \funcusage +* \funcusage * \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_GetterFunctions -* +* *******************************************************************************/ __STATIC_INLINE cy_en_dma_retrigger_t Cy_DMA_Descriptor_GetRetrigger(cy_stc_dma_descriptor_t const * descriptor) { @@ -1125,9 +1130,9 @@ __STATIC_INLINE cy_en_dma_retrigger_t Cy_DMA_Descriptor_GetRetrigger(cy_stc_dma_ * \return * The descriptor type \ref cy_en_dma_descriptor_type_t. * -* \funcusage +* \funcusage * \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_GetterFunctions -* +* *******************************************************************************/ __STATIC_INLINE cy_en_dma_descriptor_type_t Cy_DMA_Descriptor_GetDescriptorType(cy_stc_dma_descriptor_t const * descriptor) { @@ -1144,17 +1149,17 @@ __STATIC_INLINE cy_en_dma_descriptor_type_t Cy_DMA_Descriptor_GetDescriptorType( * \param descriptor * The descriptor structure instance declared by the user/component. * -* \param channelState +* \param channelState * The channel state \ref cy_en_dma_channel_state_t. * -* \funcusage +* \funcusage * \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_SetterFunctions * *******************************************************************************/ __STATIC_INLINE void Cy_DMA_Descriptor_SetChannelState(cy_stc_dma_descriptor_t * descriptor, cy_en_dma_channel_state_t channelState) { CY_ASSERT_L3(CY_DMA_IS_CHANNEL_STATE_VALID(channelState)); - + CY_REG32_CLR_SET(descriptor->ctl, CY_DMA_CTL_CH_DISABLE, channelState); } @@ -1171,9 +1176,9 @@ __STATIC_INLINE void Cy_DMA_Descriptor_SetChannelState(cy_stc_dma_descriptor_t * * \return * The Channel State setting \ref cy_en_dma_channel_state_t. * -* \funcusage +* \funcusage * \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_GetterFunctions -* +* *******************************************************************************/ __STATIC_INLINE cy_en_dma_channel_state_t Cy_DMA_Descriptor_GetChannelState(cy_stc_dma_descriptor_t const * descriptor) { @@ -1194,9 +1199,9 @@ __STATIC_INLINE cy_en_dma_channel_state_t Cy_DMA_Descriptor_GetChannelState(cy_s * \param xCount * The number of data elements to transfer in the X loop. Valid range is 1 ... 256. * -* \funcusage +* \funcusage * \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_SetterFunctions -* +* *******************************************************************************/ __STATIC_INLINE void Cy_DMA_Descriptor_SetXloopDataCount(cy_stc_dma_descriptor_t * descriptor, uint32_t xCount) { @@ -1220,9 +1225,9 @@ __STATIC_INLINE void Cy_DMA_Descriptor_SetXloopDataCount(cy_stc_dma_descriptor_t * \return * The number of data elements to transfer in the X loop. The range is 1 ... 256. * -* \funcusage +* \funcusage * \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_GetterFunctions -* +* *******************************************************************************/ __STATIC_INLINE uint32_t Cy_DMA_Descriptor_GetXloopDataCount(cy_stc_dma_descriptor_t const * descriptor) { @@ -1245,7 +1250,7 @@ __STATIC_INLINE uint32_t Cy_DMA_Descriptor_GetXloopDataCount(cy_stc_dma_descript * \param srcXincrement * The value of the source increment. The valid range is -2048 ... 2047. * -* \funcusage +* \funcusage * \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_SetterFunctions * *******************************************************************************/ @@ -1253,7 +1258,7 @@ __STATIC_INLINE void Cy_DMA_Descriptor_SetXloopSrcIncrement(cy_stc_dma_descripto { CY_ASSERT_L1(CY_DMA_SINGLE_TRANSFER != Cy_DMA_Descriptor_GetDescriptorType(descriptor)); CY_ASSERT_L2(CY_DMA_IS_LOOP_INCR_VALID(srcXincrement)); - + CY_REG32_CLR_SET(descriptor->xCtl, CY_DMA_CTL_SRC_INCR, srcXincrement); } @@ -1271,14 +1276,14 @@ __STATIC_INLINE void Cy_DMA_Descriptor_SetXloopSrcIncrement(cy_stc_dma_descripto * \return * The value of the source increment. The range is -2048 ... 2047. * -* \funcusage +* \funcusage * \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_GetterFunctions -* +* *******************************************************************************/ __STATIC_INLINE int32_t Cy_DMA_Descriptor_GetXloopSrcIncrement(cy_stc_dma_descriptor_t const * descriptor) { CY_ASSERT_L1(CY_DMA_SINGLE_TRANSFER != Cy_DMA_Descriptor_GetDescriptorType(descriptor)); - + return ((int32_t) _FLD2VAL(CY_DMA_CTL_SRC_INCR, descriptor->xCtl)); } @@ -1296,15 +1301,15 @@ __STATIC_INLINE int32_t Cy_DMA_Descriptor_GetXloopSrcIncrement(cy_stc_dma_descri * \param dstXincrement * The value of the destination increment. The valid range is -2048 ... 2047. * -* \funcusage +* \funcusage * \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_SetterFunctions -* +* *******************************************************************************/ __STATIC_INLINE void Cy_DMA_Descriptor_SetXloopDstIncrement(cy_stc_dma_descriptor_t * descriptor, int32_t dstXincrement) { CY_ASSERT_L1(CY_DMA_SINGLE_TRANSFER != Cy_DMA_Descriptor_GetDescriptorType(descriptor)); CY_ASSERT_L2(CY_DMA_IS_LOOP_INCR_VALID(dstXincrement)); - + CY_REG32_CLR_SET(descriptor->xCtl, CY_DMA_CTL_DST_INCR, dstXincrement); } @@ -1322,14 +1327,14 @@ __STATIC_INLINE void Cy_DMA_Descriptor_SetXloopDstIncrement(cy_stc_dma_descripto * \return * The value of the destination increment. The range is -2048 ... 2047. * -* \funcusage +* \funcusage * \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_GetterFunctions -* +* *******************************************************************************/ __STATIC_INLINE int32_t Cy_DMA_Descriptor_GetXloopDstIncrement(cy_stc_dma_descriptor_t const * descriptor) { CY_ASSERT_L1(CY_DMA_SINGLE_TRANSFER != Cy_DMA_Descriptor_GetDescriptorType(descriptor)); - + return ((int32_t) _FLD2VAL(CY_DMA_CTL_DST_INCR, descriptor->xCtl)); } @@ -1347,9 +1352,9 @@ __STATIC_INLINE int32_t Cy_DMA_Descriptor_GetXloopDstIncrement(cy_stc_dma_descri * \param yCount * The number of X loops to execute in the Y loop. The valid range is 1 ... 256. * -* \funcusage +* \funcusage * \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_SetterFunctions -* +* *******************************************************************************/ __STATIC_INLINE void Cy_DMA_Descriptor_SetYloopDataCount(cy_stc_dma_descriptor_t * descriptor, uint32_t yCount) { @@ -1373,9 +1378,9 @@ __STATIC_INLINE void Cy_DMA_Descriptor_SetYloopDataCount(cy_stc_dma_descriptor_t * \return * The number of X loops to execute in the Y loop. The range is 1 ... 256. * -* \funcusage +* \funcusage * \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_GetterFunctions -* +* *******************************************************************************/ __STATIC_INLINE uint32_t Cy_DMA_Descriptor_GetYloopDataCount(cy_stc_dma_descriptor_t const * descriptor) { @@ -1398,15 +1403,15 @@ __STATIC_INLINE uint32_t Cy_DMA_Descriptor_GetYloopDataCount(cy_stc_dma_descript * \param srcYincrement * The value of the source increment. The valid range is -2048 ... 2047. * -* \funcusage +* \funcusage * \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_SetterFunctions -* +* *******************************************************************************/ __STATIC_INLINE void Cy_DMA_Descriptor_SetYloopSrcIncrement(cy_stc_dma_descriptor_t * descriptor, int32_t srcYincrement) { CY_ASSERT_L1(CY_DMA_2D_TRANSFER == Cy_DMA_Descriptor_GetDescriptorType(descriptor)); CY_ASSERT_L2(CY_DMA_IS_LOOP_INCR_VALID(srcYincrement)); - + CY_REG32_CLR_SET(descriptor->yCtl, CY_DMA_CTL_SRC_INCR, srcYincrement); } @@ -1424,14 +1429,14 @@ __STATIC_INLINE void Cy_DMA_Descriptor_SetYloopSrcIncrement(cy_stc_dma_descripto * \return * The value of the source increment. The range is -2048 ... 2047. * -* \funcusage +* \funcusage * \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_GetterFunctions -* +* *******************************************************************************/ __STATIC_INLINE int32_t Cy_DMA_Descriptor_GetYloopSrcIncrement(cy_stc_dma_descriptor_t const * descriptor) { CY_ASSERT_L1(CY_DMA_2D_TRANSFER == Cy_DMA_Descriptor_GetDescriptorType(descriptor)); - + return ((int32_t) _FLD2VAL(CY_DMA_CTL_SRC_INCR, descriptor->yCtl)); } @@ -1449,7 +1454,7 @@ __STATIC_INLINE int32_t Cy_DMA_Descriptor_GetYloopSrcIncrement(cy_stc_dma_descri * \param dstYincrement * The value of the destination increment. The valid range is -2048 ... 2047. * -* \funcusage +* \funcusage * \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_SetterFunctions * *******************************************************************************/ @@ -1457,7 +1462,7 @@ __STATIC_INLINE void Cy_DMA_Descriptor_SetYloopDstIncrement(cy_stc_dma_descripto { CY_ASSERT_L1(CY_DMA_2D_TRANSFER == Cy_DMA_Descriptor_GetDescriptorType(descriptor)); CY_ASSERT_L2(CY_DMA_IS_LOOP_INCR_VALID(dstYincrement)); - + CY_REG32_CLR_SET(descriptor->yCtl, CY_DMA_CTL_DST_INCR, dstYincrement); } @@ -1467,7 +1472,7 @@ __STATIC_INLINE void Cy_DMA_Descriptor_SetYloopDstIncrement(cy_stc_dma_descripto ****************************************************************************//** * * Returns the destination increment parameter for the Y loop of the specified -* descriptor (for 2D descriptors only). +* descriptor (for 2D descriptors only). * * \param descriptor * The descriptor structure instance declared by the user/component. @@ -1475,14 +1480,14 @@ __STATIC_INLINE void Cy_DMA_Descriptor_SetYloopDstIncrement(cy_stc_dma_descripto * \return * The value of the destination increment. The range is -2048 ... 2047. * -* \funcusage +* \funcusage * \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_GetterFunctions -* +* *******************************************************************************/ __STATIC_INLINE int32_t Cy_DMA_Descriptor_GetYloopDstIncrement(cy_stc_dma_descriptor_t const * descriptor) { CY_ASSERT_L1(CY_DMA_2D_TRANSFER == Cy_DMA_Descriptor_GetDescriptorType(descriptor)); - + return ((int32_t) _FLD2VAL(CY_DMA_CTL_DST_INCR, descriptor->yCtl)); } @@ -1511,14 +1516,14 @@ __STATIC_INLINE int32_t Cy_DMA_Descriptor_GetYloopDstIncrement(cy_stc_dma_descri * \param descriptor * This is the descriptor to be associated with the channel. * -* \funcusage +* \funcusage * \snippet dma/snippet/main.c snippet_Cy_DMA_Enable * *******************************************************************************/ __STATIC_INLINE void Cy_DMA_Channel_SetDescriptor(DW_Type * base, uint32_t channel, cy_stc_dma_descriptor_t const * descriptor) { CY_ASSERT_L1(CY_DMA_IS_CH_NR_VALID(base, channel)); - + DW_CH_CURR_PTR(base, channel) = (uint32_t)descriptor; DW_CH_IDX(base, channel) &= (uint32_t) ~(DW_CH_STRUCT_CH_IDX_X_IDX_Msk | DW_CH_STRUCT_CH_IDX_Y_IDX_Msk); } @@ -1536,14 +1541,14 @@ __STATIC_INLINE void Cy_DMA_Channel_SetDescriptor(DW_Type * base, uint32_t chann * \param channel * The channel number. * -* \funcusage +* \funcusage * \snippet dma/snippet/main.c snippet_Cy_DMA_Enable * *******************************************************************************/ __STATIC_INLINE void Cy_DMA_Channel_Enable(DW_Type * base, uint32_t channel) { CY_ASSERT_L1(CY_DMA_IS_CH_NR_VALID(base, channel)); - + DW_CH_CTL(base, channel) |= DW_CH_STRUCT_CH_CTL_ENABLED_Msk; } @@ -1560,14 +1565,14 @@ __STATIC_INLINE void Cy_DMA_Channel_Enable(DW_Type * base, uint32_t channel) * \param channel * The channel number. * -* \funcusage +* \funcusage * \snippet dma/snippet/main.c snippet_Cy_DMA_Disable * *******************************************************************************/ __STATIC_INLINE void Cy_DMA_Channel_Disable(DW_Type * base, uint32_t channel) { CY_ASSERT_L1(CY_DMA_IS_CH_NR_VALID(base, channel)); - + DW_CH_CTL(base, channel) &= (uint32_t) ~DW_CH_STRUCT_CH_CTL_ENABLED_Msk; } @@ -1587,7 +1592,7 @@ __STATIC_INLINE void Cy_DMA_Channel_Disable(DW_Type * base, uint32_t channel) * \param priority * The priority to be set for the DMA channel. The allowed values are 0,1,2,3. * -* \funcusage +* \funcusage * \snippet dma/snippet/main.c snippet_Cy_DMA_Enable * *******************************************************************************/ @@ -1595,7 +1600,7 @@ __STATIC_INLINE void Cy_DMA_Channel_SetPriority(DW_Type * base, uint32_t channel { CY_ASSERT_L1(CY_DMA_IS_CH_NR_VALID(base, channel)); CY_ASSERT_L2(CY_DMA_IS_PRIORITY_VALID(priority)); - + CY_REG32_CLR_SET(DW_CH_CTL(base, channel), CY_DW_CH_CTL_PRIO, priority); } @@ -1615,14 +1620,14 @@ __STATIC_INLINE void Cy_DMA_Channel_SetPriority(DW_Type * base, uint32_t channel * \return * The priority of the channel. * -* \funcusage +* \funcusage * \snippet dma/snippet/main.c snippet_Cy_DMA_Disable * *******************************************************************************/ __STATIC_INLINE uint32_t Cy_DMA_Channel_GetPriority(DW_Type const * base, uint32_t channel) { CY_ASSERT_L1(CY_DMA_IS_CH_NR_VALID(base, channel)); - + return ((uint32_t) _FLD2VAL(CY_DW_CH_CTL_PRIO, DW_CH_CTL(base, channel))); } @@ -1642,14 +1647,14 @@ __STATIC_INLINE uint32_t Cy_DMA_Channel_GetPriority(DW_Type const * base, uint32 * \return * The pointer to the descriptor associated with the channel. * -* \funcusage +* \funcusage * \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_Deinit * *******************************************************************************/ __STATIC_INLINE cy_stc_dma_descriptor_t * Cy_DMA_Channel_GetCurrentDescriptor(DW_Type const * base, uint32_t channel) { CY_ASSERT_L1(CY_DMA_IS_CH_NR_VALID(base, channel)); - + return ((cy_stc_dma_descriptor_t*)(DW_CH_CURR_PTR(base, channel))); } @@ -1670,14 +1675,14 @@ __STATIC_INLINE cy_stc_dma_descriptor_t * Cy_DMA_Channel_GetCurrentDescriptor(DW * \return * The status of an interrupt for the specified channel. * -* \funcusage +* \funcusage * \snippet dma/snippet/main.c snippet_Cy_DMA_GetInterruptStatus * *******************************************************************************/ __STATIC_INLINE uint32_t Cy_DMA_Channel_GetInterruptStatus(DW_Type const * base, uint32_t channel) { CY_ASSERT_L1(CY_DMA_IS_CH_NR_VALID(base, channel)); - + return (DW_CH_INTR(base, channel)); } @@ -1697,14 +1702,14 @@ __STATIC_INLINE uint32_t Cy_DMA_Channel_GetInterruptStatus(DW_Type const * base, * \return * The cause \ref cy_en_dma_intr_cause_t of the interrupt. * -* \funcusage +* \funcusage * \snippet dma/snippet/main.c snippet_Cy_DMA_ClearInterrupt * *******************************************************************************/ __STATIC_INLINE cy_en_dma_intr_cause_t Cy_DMA_Channel_GetStatus(DW_Type const * base, uint32_t channel) { CY_ASSERT_L1(CY_DMA_IS_CH_NR_VALID(base, channel)); - + return ((cy_en_dma_intr_cause_t) _FLD2VAL(DW_CH_STRUCT_CH_STATUS_INTR_CAUSE, DW_CH_STATUS(base, channel))); } @@ -1721,14 +1726,14 @@ __STATIC_INLINE cy_en_dma_intr_cause_t Cy_DMA_Channel_GetStatus(DW_Type const * * \param channel * The channel number. * -* \funcusage +* \funcusage * \snippet dma/snippet/main.c snippet_Cy_DMA_ClearInterrupt * *******************************************************************************/ __STATIC_INLINE void Cy_DMA_Channel_ClearInterrupt(DW_Type * base, uint32_t channel) { CY_ASSERT_L1(CY_DMA_IS_CH_NR_VALID(base, channel)); - + DW_CH_INTR(base, channel) = CY_DMA_INTR_MASK; (void) DW_CH_INTR(base, channel); } @@ -1746,14 +1751,14 @@ __STATIC_INLINE void Cy_DMA_Channel_ClearInterrupt(DW_Type * base, uint32_t chan * \param channel * The channel number. * -* \funcusage +* \funcusage * \snippet dma/snippet/main.c snippet_Cy_DMA_SetInterruptMask * *******************************************************************************/ __STATIC_INLINE void Cy_DMA_Channel_SetInterrupt(DW_Type * base, uint32_t channel) { CY_ASSERT_L1(CY_DMA_IS_CH_NR_VALID(base, channel)); - + DW_CH_INTR_SET(base, channel) = CY_DMA_INTR_MASK; } @@ -1773,14 +1778,14 @@ __STATIC_INLINE void Cy_DMA_Channel_SetInterrupt(DW_Type * base, uint32_t channe * \return * The interrupt mask value. * -* \funcusage +* \funcusage * \snippet dma/snippet/main.c snippet_Cy_DMA_SetInterruptMask * *******************************************************************************/ __STATIC_INLINE uint32_t Cy_DMA_Channel_GetInterruptMask(DW_Type const * base, uint32_t channel) { CY_ASSERT_L1(CY_DMA_IS_CH_NR_VALID(base, channel)); - + return (DW_CH_INTR_MASK(base, channel)); } @@ -1801,7 +1806,7 @@ __STATIC_INLINE uint32_t Cy_DMA_Channel_GetInterruptMask(DW_Type const * base, u * The interrupt mask: * CY_DMA_INTR_MASK to enable the interrupt or 0UL to disable the interrupt. * -* \funcusage +* \funcusage * \snippet dma/snippet/main.c snippet_Cy_DMA_SetInterruptMask * *******************************************************************************/ @@ -1826,14 +1831,14 @@ __STATIC_INLINE void Cy_DMA_Channel_SetInterruptMask(DW_Type * base, uint32_t ch * \param channel * The channel number. * -* \funcusage +* \funcusage * \snippet dma/snippet/main.c snippet_Cy_DMA_ClearInterrupt * *******************************************************************************/ __STATIC_INLINE uint32_t Cy_DMA_Channel_GetInterruptStatusMasked(DW_Type const * base, uint32_t channel) { CY_ASSERT_L1(CY_DMA_IS_CH_NR_VALID(base, channel)); - + return (DW_CH_INTR_MASKED(base, channel)); } @@ -1887,14 +1892,14 @@ __STATIC_INLINE uint32_t Cy_DMA_Channel_GetInterruptStatusMasked(DW_Type const * #define CY_DMA_TRIGOUT_X_LOOP_CMPLT (CY_DMA_X_LOOP) #define CY_DMA_TRIGOUT_DESCR_CMPLT (CY_DMA_DESCR) #define CY_DMA_TRIGOUT_DESCRCHAIN_CMPLT (CY_DMA_DESCR_CHAIN) - + #define CY_DMA_TRIGIN_1ELEMENT (CY_DMA_1ELEMENT) #define CY_DMA_TRIGIN_XLOOP (CY_DMA_X_LOOP) #define CY_DMA_TRIGIN_DESCR (CY_DMA_DESCR) #define CY_DMA_TRIGIN_DESCRCHAIN (CY_DMA_DESCR_CHAIN) #define CY_DMA_INVALID_INPUT_PARAMETERS (CY_DMA_BAD_PARAM) - + #define CY_DMA_RETDIG_IM (CY_DMA_RETRIG_IM) #define CY_DMA_RETDIG_4CYC (CY_DMA_RETRIG_4CYC) #define CY_DMA_RETDIG_16CYC (CY_DMA_RETRIG_16CYC) @@ -1906,7 +1911,7 @@ __STATIC_INLINE uint32_t Cy_DMA_Channel_GetInterruptStatusMasked(DW_Type const * #define DESCR_X_CTL xCtl #define DESCR_Y_CTL yCtl #define DESCR_NEXT_PTR nextPtr - + /* Descriptor structure bitfields */ #define DW_DESCR_STRUCT_DESCR_CTL_WAIT_FOR_DEACT_Pos 0UL #define DW_DESCR_STRUCT_DESCR_CTL_WAIT_FOR_DEACT_Msk 0x3UL diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_dmac.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_dmac.h index a3aacf8100..0695841977 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_dmac.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_dmac.h @@ -1,13 +1,13 @@ /***************************************************************************//** * \file cy_dmac.h -* \version 1.10 +* \version 1.10.1 * * \brief * The header file of the DMAC driver. * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -28,8 +28,8 @@ * \{ * Configures the DMA Controller block, channels and descriptors. * -* The functions and other declarations used in this driver are in cy_dmac.h. -* You can include cy_pdl.h (ModusToolbox only) to get access to all functions +* The functions and other declarations used in this driver are in cy_dmac.h. +* You can include cy_pdl.h to get access to all functions * and declarations in the PDL. * * The DMA Controller channel can be used in any project to transfer data @@ -39,7 +39,7 @@ * and supports multiple channels. Many API functions for the DMAC driver require * a base hardware address and channel number. * Ensure that you use the correct hardware address for the DMA Controller block in use. -* +* * Features: * * Multiple channels (device specific). * * Four priority levels for each channel. @@ -53,13 +53,13 @@ * * To set up a DMAC driver, initialize a descriptor, * initialize and enable a channel, and enable the DMAC block. -* -* To set up a descriptor, provide the configuration parameters for the -* descriptor in the \ref cy_stc_dmac_descriptor_config_t structure. Then call the -* \ref Cy_DMAC_Descriptor_Init function to initialize the descriptor in SRAM. You can -* modify the source and destination addresses dynamically by calling +* +* To set up a descriptor, provide the configuration parameters for the +* descriptor in the \ref cy_stc_dmac_descriptor_config_t structure. Then call the +* \ref Cy_DMAC_Descriptor_Init function to initialize the descriptor in SRAM. You can +* modify the source and destination addresses dynamically by calling * \ref Cy_DMAC_Descriptor_SetSrcAddress and \ref Cy_DMAC_Descriptor_SetDstAddress. -* +* * To set up a DMAC channel, provide a filled \ref cy_stc_dmac_channel_config_t * structure. Call the \ref Cy_DMAC_Channel_Init function, specifying the channel * number. Use \ref Cy_DMAC_Channel_Enable to enable the configured DMAC channel. @@ -78,12 +78,12 @@ * NOTE: Even if a DMAC channel is enabled, it is not operational until * the DMAC block is enabled using function \ref Cy_DMAC_Enable.\n * NOTE: If the DMAC descriptor is configured to generate an interrupt, -* the interrupt must be enabled using the \ref Cy_DMAC_Channel_SetInterruptMask +* the interrupt must be enabled using the \ref Cy_DMAC_Channel_SetInterruptMask * function for each DMAC channel. * * For example: * \snippet dmac/snippet/main.c snippet_Cy_DMAC_Enable -* +* * \section group_dmac_more_information More Information. * See the DMAC chapter of the device technical reference manual (TRM). * @@ -119,6 +119,11 @@ *
VersionChangesReason for Change
2.20.1Minor documentation updates.Documentation enhancement.
2.20The channel number validation method is updated.New devices support.
Added register access layer. Use register access macros instead * of direct register access using dereferenced pointers.Makes register access device-independent, so that the PDL does +* Makes register access device-independent, so that the PDL does * not need to be recompiled for each supported part number.
* * +* +* +* +* +* * * * @@ -175,7 +180,7 @@ extern "C" { /** The DMAC driver identifier */ #define CY_DMAC_ID (CY_PDL_DRV_ID(0x3FU)) - + /** The minimum X/Y Count API parameters */ #define CY_DMAC_LOOP_COUNT_MIN (1UL) /** The maximum X/Y Count API parameters */ @@ -271,7 +276,7 @@ typedef enum } cy_en_dmac_channel_state_t; /** Contains the return values of the DMAC driver */ -typedef enum +typedef enum { CY_DMAC_SUCCESS = 0x0UL, /**< Success. */ CY_DMAC_BAD_PARAM = CY_DMAC_ID | CY_PDL_STATUS_ERROR | 0x1UL /**< The input parameters passed to the DMAC API are not valid. */ @@ -334,7 +339,7 @@ typedef enum */ -/** +/** * DMAC descriptor structure type. It is a user-declared structure * allocated in RAM. The DMAC HW requires a pointer to this structure to work with it. * @@ -413,7 +418,7 @@ typedef struct cy_en_dmac_channel_state_t channelState; /**< Specifies whether the channel is enabled or disabled on completion of descriptor see \ref cy_en_dmac_channel_state_t. */ cy_en_dmac_trigger_type_t triggerInType; /**< Sets what type of transfer is triggered. See \ref cy_en_dmac_trigger_type_t. */ bool dataPrefetch; /**< Source data transfers are initiated as soon as the channel is enabled, the current descriptor pointer is NOT "0" - * and there is space available in the channel's data FIFO. + * and there is space available in the channel's data FIFO. */ cy_en_dmac_data_size_t dataSize; /**< The size of the data bus for transfer. See \ref cy_en_dmac_data_size_t. * For memory copy and scatter descriptors this setting will be ignored. @@ -478,7 +483,7 @@ __STATIC_INLINE void * Cy_DMAC_Channel_GetCurrentSrcAddress (DMAC_Type __STATIC_INLINE void * Cy_DMAC_Channel_GetCurrentDstAddress (DMAC_Type * base, uint32_t channel); __STATIC_INLINE uint32_t Cy_DMAC_Channel_GetCurrentXloopIndex (DMAC_Type const * base, uint32_t channel); __STATIC_INLINE uint32_t Cy_DMAC_Channel_GetCurrentYloopIndex (DMAC_Type const * base, uint32_t channel); -__STATIC_INLINE cy_stc_dmac_descriptor_t * +__STATIC_INLINE cy_stc_dmac_descriptor_t * Cy_DMAC_Channel_GetCurrentDescriptor (DMAC_Type const * base, uint32_t channel); __STATIC_INLINE uint32_t Cy_DMAC_Channel_GetInterruptStatus (DMAC_Type const * base, uint32_t channel); __STATIC_INLINE void Cy_DMAC_Channel_ClearInterrupt (DMAC_Type * base, uint32_t channel, uint32_t interrupt); @@ -497,7 +502,7 @@ __STATIC_INLINE uint32_t Cy_DMAC_Channel_GetInterruptStatusMasked(DMAC_Type cons cy_en_dmac_status_t Cy_DMAC_Descriptor_Init (cy_stc_dmac_descriptor_t * descriptor, cy_stc_dmac_descriptor_config_t const * config); void Cy_DMAC_Descriptor_DeInit(cy_stc_dmac_descriptor_t * descriptor); - + void Cy_DMAC_Descriptor_SetNextDescriptor (cy_stc_dmac_descriptor_t * descriptor, cy_stc_dmac_descriptor_t const * nextDescriptor); void Cy_DMAC_Descriptor_SetDescriptorType (cy_stc_dmac_descriptor_t * descriptor, cy_en_dmac_descriptor_type_t descriptorType); __STATIC_INLINE void Cy_DMAC_Descriptor_SetSrcAddress (cy_stc_dmac_descriptor_t * descriptor, void const * srcAddress); @@ -578,7 +583,7 @@ __STATIC_INLINE void Cy_DMAC_Enable(DMAC_Type * base) * \param base * The pointer to the hardware DMAC block. * -* \funcusage +* \funcusage * \snippet dmac/snippet/main.c snippet_Cy_DMAC_Disable * *******************************************************************************/ @@ -601,7 +606,7 @@ __STATIC_INLINE void Cy_DMAC_Disable(DMAC_Type * base) * Returns a bit-field with all of the currently active/pending channels in the * DMAC block. * -* \funcusage +* \funcusage * \snippet dmac/snippet/main.c snippet_Cy_DMAC_Disable * *******************************************************************************/ @@ -631,7 +636,7 @@ __STATIC_INLINE uint32_t Cy_DMAC_GetActiveChannel(DMAC_Type const * base) * \param srcAddress * The source address value for the descriptor. * -* \funcusage +* \funcusage * \snippet dmac/snippet/main.c snippet_Cy_DMAC_Descriptor_SetterFunctions * *******************************************************************************/ @@ -646,14 +651,14 @@ __STATIC_INLINE void Cy_DMAC_Descriptor_SetSrcAddress(cy_stc_dmac_descriptor_t * ****************************************************************************//** * * Returns the source address of the specified descriptor. -* +* * \param descriptor * The descriptor structure instance. * * \return * The source address value of the descriptor. * -* \funcusage +* \funcusage * \snippet dmac/snippet/main.c snippet_Cy_DMAC_Descriptor_GetterFunctions * *******************************************************************************/ @@ -675,7 +680,7 @@ __STATIC_INLINE void * Cy_DMAC_Descriptor_GetSrcAddress(cy_stc_dmac_descriptor_t * \param dstAddress * The destination address value for the descriptor. * -* \funcusage +* \funcusage * \snippet dmac/snippet/main.c snippet_Cy_DMAC_Descriptor_SetterFunctions * *******************************************************************************/ @@ -692,14 +697,14 @@ __STATIC_INLINE void Cy_DMAC_Descriptor_SetDstAddress(cy_stc_dmac_descriptor_t * ****************************************************************************//** * * Returns the destination address of the specified descriptor. -* +* * \param descriptor * The descriptor structure instance. * * \return * The destination address value of the descriptor. * -* \funcusage +* \funcusage * \snippet dmac/snippet/main.c snippet_Cy_DMAC_Descriptor_GetterFunctions * *******************************************************************************/ @@ -723,14 +728,14 @@ __STATIC_INLINE void * Cy_DMAC_Descriptor_GetDstAddress(cy_stc_dmac_descriptor_t * \param interruptType * The interrupt type set for the descriptor. \ref cy_en_dmac_trigger_type_t * -* \funcusage +* \funcusage * \snippet dmac/snippet/main.c snippet_Cy_DMAC_Descriptor_SetterFunctions * *******************************************************************************/ __STATIC_INLINE void Cy_DMAC_Descriptor_SetInterruptType(cy_stc_dmac_descriptor_t * descriptor, cy_en_dmac_trigger_type_t interruptType) { CY_ASSERT_L3(CY_DMAC_IS_TRIG_TYPE_VALID(interruptType)); - + CY_REG32_CLR_SET(descriptor->ctl, DMAC_CH_V2_DESCR_CTL_INTR_TYPE, interruptType); } @@ -747,9 +752,9 @@ __STATIC_INLINE void Cy_DMAC_Descriptor_SetInterruptType(cy_stc_dmac_descriptor_ * \return * The Interrupt-Type \ref cy_en_dmac_trigger_type_t. * -* \funcusage +* \funcusage * \snippet dmac/snippet/main.c snippet_Cy_DMAC_Descriptor_GetterFunctions -* +* *******************************************************************************/ __STATIC_INLINE cy_en_dmac_trigger_type_t Cy_DMAC_Descriptor_GetInterruptType(cy_stc_dmac_descriptor_t const * descriptor) { @@ -769,14 +774,14 @@ __STATIC_INLINE cy_en_dmac_trigger_type_t Cy_DMAC_Descriptor_GetInterruptType(cy * \param triggerInType * The Trigger In Type parameter \ref cy_en_dmac_trigger_type_t * -* \funcusage +* \funcusage * \snippet dmac/snippet/main.c snippet_Cy_DMAC_Descriptor_SetterFunctions * *******************************************************************************/ __STATIC_INLINE void Cy_DMAC_Descriptor_SetTriggerInType(cy_stc_dmac_descriptor_t * descriptor, cy_en_dmac_trigger_type_t triggerInType) { CY_ASSERT_L3(CY_DMAC_IS_TRIG_TYPE_VALID(triggerInType)); - + CY_REG32_CLR_SET(descriptor->ctl, DMAC_CH_V2_DESCR_CTL_TR_IN_TYPE, triggerInType); } @@ -793,9 +798,9 @@ __STATIC_INLINE void Cy_DMAC_Descriptor_SetTriggerInType(cy_stc_dmac_descriptor_ * \return * The Trigger In Type \ref cy_en_dmac_trigger_type_t * -* \funcusage +* \funcusage * \snippet dmac/snippet/main.c snippet_Cy_DMAC_Descriptor_GetterFunctions -* +* *******************************************************************************/ __STATIC_INLINE cy_en_dmac_trigger_type_t Cy_DMAC_Descriptor_GetTriggerInType(cy_stc_dmac_descriptor_t const * descriptor) { @@ -815,14 +820,14 @@ __STATIC_INLINE cy_en_dmac_trigger_type_t Cy_DMAC_Descriptor_GetTriggerInType(cy * \param triggerOutType * The Trigger Out Type set for the descriptor. \ref cy_en_dmac_trigger_type_t * -* \funcusage +* \funcusage * \snippet dmac/snippet/main.c snippet_Cy_DMAC_Descriptor_SetterFunctions * *******************************************************************************/ __STATIC_INLINE void Cy_DMAC_Descriptor_SetTriggerOutType(cy_stc_dmac_descriptor_t * descriptor, cy_en_dmac_trigger_type_t triggerOutType) { CY_ASSERT_L3(CY_DMAC_IS_TRIG_TYPE_VALID(triggerOutType)); - + CY_REG32_CLR_SET(descriptor->ctl, DMAC_CH_V2_DESCR_CTL_TR_OUT_TYPE, triggerOutType); } @@ -839,9 +844,9 @@ __STATIC_INLINE void Cy_DMAC_Descriptor_SetTriggerOutType(cy_stc_dmac_descriptor * \return * The Trigger Out Type parameter \ref cy_en_dmac_trigger_type_t. * -* \funcusage +* \funcusage * \snippet dmac/snippet/main.c snippet_Cy_DMAC_Descriptor_GetterFunctions -* +* *******************************************************************************/ __STATIC_INLINE cy_en_dmac_trigger_type_t Cy_DMAC_Descriptor_GetTriggerOutType(cy_stc_dmac_descriptor_t const * descriptor) { @@ -861,14 +866,14 @@ __STATIC_INLINE cy_en_dmac_trigger_type_t Cy_DMAC_Descriptor_GetTriggerOutType(c * \param dataSize * The Data Element Size \ref cy_en_dmac_data_size_t * -* \funcusage +* \funcusage * \snippet dmac/snippet/main.c snippet_Cy_DMAC_Descriptor_SetterFunctions -* +* *******************************************************************************/ __STATIC_INLINE void Cy_DMAC_Descriptor_SetDataSize(cy_stc_dmac_descriptor_t * descriptor, cy_en_dmac_data_size_t dataSize) { CY_ASSERT_L3(CY_DMAC_IS_DATA_SIZE_VALID(dataSize)); - + CY_REG32_CLR_SET(descriptor->ctl, DMAC_CH_V2_DESCR_CTL_DATA_SIZE, dataSize); } @@ -885,9 +890,9 @@ __STATIC_INLINE void Cy_DMAC_Descriptor_SetDataSize(cy_stc_dmac_descriptor_t * d * \return * The Data Element Size \ref cy_en_dmac_data_size_t. * -* \funcusage +* \funcusage * \snippet dmac/snippet/main.c snippet_Cy_DMAC_Descriptor_GetterFunctions -* +* *******************************************************************************/ __STATIC_INLINE cy_en_dmac_data_size_t Cy_DMAC_Descriptor_GetDataSize(cy_stc_dmac_descriptor_t const * descriptor) { @@ -907,7 +912,7 @@ __STATIC_INLINE cy_en_dmac_data_size_t Cy_DMAC_Descriptor_GetDataSize(cy_stc_dma * \param srcTransferSize * The Source Transfer Size \ref cy_en_dmac_transfer_size_t. * -* \funcusage +* \funcusage * \snippet dmac/snippet/main.c snippet_Cy_DMAC_Descriptor_SetterFunctions *******************************************************************************/ __STATIC_INLINE void Cy_DMAC_Descriptor_SetSrcTransferSize(cy_stc_dmac_descriptor_t * descriptor, cy_en_dmac_transfer_size_t srcTransferSize) @@ -930,9 +935,9 @@ __STATIC_INLINE void Cy_DMAC_Descriptor_SetSrcTransferSize(cy_stc_dmac_descripto * \return * The Source Transfer Size \ref cy_en_dmac_transfer_size_t. * -* \funcusage +* \funcusage * \snippet dmac/snippet/main.c snippet_Cy_DMAC_Descriptor_GetterFunctions -* +* *******************************************************************************/ __STATIC_INLINE cy_en_dmac_transfer_size_t Cy_DMAC_Descriptor_GetSrcTransferSize(cy_stc_dmac_descriptor_t const * descriptor) { @@ -952,14 +957,14 @@ __STATIC_INLINE cy_en_dmac_transfer_size_t Cy_DMAC_Descriptor_GetSrcTransferSize * \param dstTransferSize * The Destination Transfer Size \ref cy_en_dmac_transfer_size_t. * -* \funcusage +* \funcusage * \snippet dmac/snippet/main.c snippet_Cy_DMAC_Descriptor_SetterFunctions * *******************************************************************************/ __STATIC_INLINE void Cy_DMAC_Descriptor_SetDstTransferSize(cy_stc_dmac_descriptor_t * descriptor, cy_en_dmac_transfer_size_t dstTransferSize) { CY_ASSERT_L3(CY_DMAC_IS_XFER_SIZE_VALID(dstTransferSize)); - + CY_REG32_CLR_SET(descriptor->ctl, DMAC_CH_V2_DESCR_CTL_DST_TRANSFER_SIZE, dstTransferSize); } @@ -976,9 +981,9 @@ __STATIC_INLINE void Cy_DMAC_Descriptor_SetDstTransferSize(cy_stc_dmac_descripto * \return * The Destination Transfer Size \ref cy_en_dmac_transfer_size_t * -* \funcusage +* \funcusage * \snippet dmac/snippet/main.c snippet_Cy_DMAC_Descriptor_GetterFunctions -* +* *******************************************************************************/ __STATIC_INLINE cy_en_dmac_transfer_size_t Cy_DMAC_Descriptor_GetDstTransferSize(cy_stc_dmac_descriptor_t const * descriptor) { @@ -990,24 +995,24 @@ __STATIC_INLINE cy_en_dmac_transfer_size_t Cy_DMAC_Descriptor_GetDstTransferSize * Function Name: Cy_DMAC_Descriptor_SetRetrigger ****************************************************************************//** * -* Sets the retrigger value which specifies whether the controller should +* Sets the retrigger value which specifies whether the controller should * wait for the input trigger to be deactivated. * * \param descriptor * The descriptor structure instance. * -* \param retrigger +* \param retrigger * The \ref cy_en_dmac_retrigger_t parameter specifies whether the controller * should wait for the input trigger to be deactivated. * -* \funcusage +* \funcusage * \snippet dmac/snippet/main.c snippet_Cy_DMAC_Descriptor_SetterFunctions * *******************************************************************************/ __STATIC_INLINE void Cy_DMAC_Descriptor_SetRetrigger(cy_stc_dmac_descriptor_t * descriptor, cy_en_dmac_retrigger_t retrigger) { CY_ASSERT_L3(CY_DMAC_IS_RETRIGGER_VALID(retrigger)); - + CY_REG32_CLR_SET(descriptor->ctl, DMAC_CH_V2_DESCR_CTL_WAIT_FOR_DEACT, retrigger); } @@ -1016,7 +1021,7 @@ __STATIC_INLINE void Cy_DMAC_Descriptor_SetRetrigger(cy_stc_dmac_descriptor_t * * Function Name: Cy_DMAC_Descriptor_GetRetrigger ****************************************************************************//** * -* Returns a value which specifies whether the controller should +* Returns a value which specifies whether the controller should * wait for the input trigger to be deactivated. * * \param descriptor @@ -1025,9 +1030,9 @@ __STATIC_INLINE void Cy_DMAC_Descriptor_SetRetrigger(cy_stc_dmac_descriptor_t * * \return * The Retrigger setting \ref cy_en_dmac_retrigger_t. * -* \funcusage +* \funcusage * \snippet dmac/snippet/main.c snippet_Cy_DMAC_Descriptor_GetterFunctions -* +* *******************************************************************************/ __STATIC_INLINE cy_en_dmac_retrigger_t Cy_DMAC_Descriptor_GetRetrigger(cy_stc_dmac_descriptor_t const * descriptor) { @@ -1047,9 +1052,9 @@ __STATIC_INLINE cy_en_dmac_retrigger_t Cy_DMAC_Descriptor_GetRetrigger(cy_stc_dm * \return * The descriptor type \ref cy_en_dmac_descriptor_type_t * -* \funcusage +* \funcusage * \snippet dmac/snippet/main.c snippet_Cy_DMAC_Descriptor_GetterFunctions -* +* *******************************************************************************/ __STATIC_INLINE cy_en_dmac_descriptor_type_t Cy_DMAC_Descriptor_GetDescriptorType(cy_stc_dmac_descriptor_t const * descriptor) { @@ -1066,17 +1071,17 @@ __STATIC_INLINE cy_en_dmac_descriptor_type_t Cy_DMAC_Descriptor_GetDescriptorTyp * \param descriptor * The descriptor structure instance. * -* \param channelState +* \param channelState * The channel state \ref cy_en_dmac_channel_state_t. * -* \funcusage +* \funcusage * \snippet dmac/snippet/main.c snippet_Cy_DMAC_Descriptor_SetterFunctions * *******************************************************************************/ __STATIC_INLINE void Cy_DMAC_Descriptor_SetChannelState(cy_stc_dmac_descriptor_t * descriptor, cy_en_dmac_channel_state_t channelState) { CY_ASSERT_L3(CY_DMAC_IS_CHANNEL_STATE_VALID(channelState)); - + CY_REG32_CLR_SET(descriptor->ctl, DMAC_CH_V2_DESCR_CTL_CH_DISABLE, channelState); } @@ -1093,9 +1098,9 @@ __STATIC_INLINE void Cy_DMAC_Descriptor_SetChannelState(cy_stc_dmac_descriptor_t * \return * The Channel State setting \ref cy_en_dmac_channel_state_t * -* \funcusage +* \funcusage * \snippet dmac/snippet/main.c snippet_Cy_DMAC_Descriptor_GetterFunctions -* +* *******************************************************************************/ __STATIC_INLINE cy_en_dmac_channel_state_t Cy_DMAC_Descriptor_GetChannelState(cy_stc_dmac_descriptor_t const * descriptor) { @@ -1116,7 +1121,7 @@ __STATIC_INLINE cy_en_dmac_channel_state_t Cy_DMAC_Descriptor_GetChannelState(cy * \param srcXincrement * The value of the source increment. The valid range is -32768 ... 32767. * -* \funcusage +* \funcusage * \snippet dmac/snippet/main.c snippet_Cy_DMAC_Descriptor_SetterFunctions * *******************************************************************************/ @@ -1124,7 +1129,7 @@ __STATIC_INLINE void Cy_DMAC_Descriptor_SetXloopSrcIncrement(cy_stc_dmac_descrip { CY_ASSERT_L1(CY_DMAC_SINGLE_TRANSFER != Cy_DMAC_Descriptor_GetDescriptorType(descriptor)); CY_ASSERT_L2(CY_DMAC_IS_LOOP_INCR_VALID(srcXincrement)); - + CY_REG32_CLR_SET(descriptor->xIncr, DMAC_CH_V2_DESCR_X_INCR_SRC_X, srcXincrement); } @@ -1142,14 +1147,14 @@ __STATIC_INLINE void Cy_DMAC_Descriptor_SetXloopSrcIncrement(cy_stc_dmac_descrip * \return * The value of the source increment. The range is -32768 ... 32767. * -* \funcusage +* \funcusage * \snippet dmac/snippet/main.c snippet_Cy_DMAC_Descriptor_GetterFunctions -* +* *******************************************************************************/ __STATIC_INLINE int32_t Cy_DMAC_Descriptor_GetXloopSrcIncrement(cy_stc_dmac_descriptor_t const * descriptor) { CY_ASSERT_L1(CY_DMAC_SINGLE_TRANSFER != Cy_DMAC_Descriptor_GetDescriptorType(descriptor)); - + return ((int32_t) _FLD2VAL(DMAC_CH_V2_DESCR_X_INCR_SRC_X, descriptor->xIncr)); } @@ -1167,15 +1172,15 @@ __STATIC_INLINE int32_t Cy_DMAC_Descriptor_GetXloopSrcIncrement(cy_stc_dmac_desc * \param dstXincrement * The value of the destination increment. The valid range is -32768 ... 32767. * -* \funcusage +* \funcusage * \snippet dmac/snippet/main.c snippet_Cy_DMAC_Descriptor_SetterFunctions -* +* *******************************************************************************/ __STATIC_INLINE void Cy_DMAC_Descriptor_SetXloopDstIncrement(cy_stc_dmac_descriptor_t * descriptor, int32_t dstXincrement) { CY_ASSERT_L1(CY_DMAC_SINGLE_TRANSFER != Cy_DMAC_Descriptor_GetDescriptorType(descriptor)); CY_ASSERT_L2(CY_DMAC_IS_LOOP_INCR_VALID(dstXincrement)); - + CY_REG32_CLR_SET(descriptor->xIncr, DMAC_CH_V2_DESCR_X_INCR_DST_X, dstXincrement); } @@ -1193,14 +1198,14 @@ __STATIC_INLINE void Cy_DMAC_Descriptor_SetXloopDstIncrement(cy_stc_dmac_descrip * \return * The value of the destination increment. The range is -32768 ... 32767. * -* \funcusage +* \funcusage * \snippet dmac/snippet/main.c snippet_Cy_DMAC_Descriptor_GetterFunctions -* +* *******************************************************************************/ __STATIC_INLINE int32_t Cy_DMAC_Descriptor_GetXloopDstIncrement(cy_stc_dmac_descriptor_t const * descriptor) { CY_ASSERT_L1(CY_DMAC_SINGLE_TRANSFER != Cy_DMAC_Descriptor_GetDescriptorType(descriptor)); - + return ((int32_t) _FLD2VAL(DMAC_CH_V2_DESCR_X_INCR_DST_X, descriptor->xIncr)); } @@ -1218,9 +1223,9 @@ __STATIC_INLINE int32_t Cy_DMAC_Descriptor_GetXloopDstIncrement(cy_stc_dmac_desc * \param yCount * The number of X loops to execute in the Y loop. The valid range is 1 ... 65536. * -* \funcusage +* \funcusage * \snippet dmac/snippet/main.c snippet_Cy_DMAC_Descriptor_SetterFunctions -* +* *******************************************************************************/ __STATIC_INLINE void Cy_DMAC_Descriptor_SetYloopDataCount(cy_stc_dmac_descriptor_t * descriptor, uint32_t yCount) { @@ -1244,9 +1249,9 @@ __STATIC_INLINE void Cy_DMAC_Descriptor_SetYloopDataCount(cy_stc_dmac_descriptor * \return * The number of X loops to execute in the Y loop. The range is 1 ... 65536. * -* \funcusage +* \funcusage * \snippet dmac/snippet/main.c snippet_Cy_DMAC_Descriptor_GetterFunctions -* +* *******************************************************************************/ __STATIC_INLINE uint32_t Cy_DMAC_Descriptor_GetYloopDataCount(cy_stc_dmac_descriptor_t const * descriptor) { @@ -1269,15 +1274,15 @@ __STATIC_INLINE uint32_t Cy_DMAC_Descriptor_GetYloopDataCount(cy_stc_dmac_descri * \param srcYincrement * The value of the source increment. The valid range is -32768 ... 32767. * -* \funcusage +* \funcusage * \snippet dmac/snippet/main.c snippet_Cy_DMAC_Descriptor_SetterFunctions -* +* *******************************************************************************/ __STATIC_INLINE void Cy_DMAC_Descriptor_SetYloopSrcIncrement(cy_stc_dmac_descriptor_t * descriptor, int32_t srcYincrement) { CY_ASSERT_L1(CY_DMAC_2D_TRANSFER == Cy_DMAC_Descriptor_GetDescriptorType(descriptor)); CY_ASSERT_L2(CY_DMAC_IS_LOOP_INCR_VALID(srcYincrement)); - + CY_REG32_CLR_SET(descriptor->yIncr, DMAC_CH_V2_DESCR_Y_INCR_SRC_Y, srcYincrement); } @@ -1295,14 +1300,14 @@ __STATIC_INLINE void Cy_DMAC_Descriptor_SetYloopSrcIncrement(cy_stc_dmac_descrip * \return * The value of source increment. The range is -32768 ... 32767. * -* \funcusage +* \funcusage * \snippet dmac/snippet/main.c snippet_Cy_DMAC_Descriptor_GetterFunctions -* +* *******************************************************************************/ __STATIC_INLINE int32_t Cy_DMAC_Descriptor_GetYloopSrcIncrement(cy_stc_dmac_descriptor_t const * descriptor) { CY_ASSERT_L1(CY_DMAC_2D_TRANSFER == Cy_DMAC_Descriptor_GetDescriptorType(descriptor)); - + return ((int32_t) _FLD2VAL(DMAC_CH_V2_DESCR_Y_INCR_SRC_Y, descriptor->yIncr)); } @@ -1320,7 +1325,7 @@ __STATIC_INLINE int32_t Cy_DMAC_Descriptor_GetYloopSrcIncrement(cy_stc_dmac_desc * \param dstYincrement * The value of the destination increment. The valid range is -32768 ... 32767. * -* \funcusage +* \funcusage * \snippet dmac/snippet/main.c snippet_Cy_DMAC_Descriptor_SetterFunctions * *******************************************************************************/ @@ -1328,7 +1333,7 @@ __STATIC_INLINE void Cy_DMAC_Descriptor_SetYloopDstIncrement(cy_stc_dmac_descrip { CY_ASSERT_L1(CY_DMAC_2D_TRANSFER == Cy_DMAC_Descriptor_GetDescriptorType(descriptor)); CY_ASSERT_L2(CY_DMAC_IS_LOOP_INCR_VALID(dstYincrement)); - + CY_REG32_CLR_SET(descriptor->yIncr, DMAC_CH_V2_DESCR_Y_INCR_DST_Y, dstYincrement); } @@ -1338,7 +1343,7 @@ __STATIC_INLINE void Cy_DMAC_Descriptor_SetYloopDstIncrement(cy_stc_dmac_descrip ****************************************************************************//** * * Returns the destination increment parameter for the Y loop of the specified -* descriptor (for 2D descriptors only). +* descriptor (for 2D descriptors only). * * \param descriptor * The descriptor structure instance. @@ -1346,14 +1351,14 @@ __STATIC_INLINE void Cy_DMAC_Descriptor_SetYloopDstIncrement(cy_stc_dmac_descrip * \return * The value of the destination increment. The range is -32768 ... 32767. * -* \funcusage +* \funcusage * \snippet dmac/snippet/main.c snippet_Cy_DMAC_Descriptor_GetterFunctions -* +* *******************************************************************************/ __STATIC_INLINE int32_t Cy_DMAC_Descriptor_GetYloopDstIncrement(cy_stc_dmac_descriptor_t const * descriptor) { CY_ASSERT_L1(CY_DMAC_2D_TRANSFER == Cy_DMAC_Descriptor_GetDescriptorType(descriptor)); - + return ((int32_t) _FLD2VAL(DMAC_CH_V2_DESCR_Y_INCR_DST_Y, descriptor->yIncr)); } @@ -1381,14 +1386,14 @@ __STATIC_INLINE int32_t Cy_DMAC_Descriptor_GetYloopDstIncrement(cy_stc_dmac_desc * \param descriptor * This is the descriptor to be associated with the channel. * -* \funcusage +* \funcusage * \snippet dmac/snippet/main.c snippet_Cy_DMAC_Enable * *******************************************************************************/ __STATIC_INLINE void Cy_DMAC_Channel_SetDescriptor(DMAC_Type * base, uint32_t channel, cy_stc_dmac_descriptor_t const * descriptor) { CY_ASSERT_L1(CY_DMAC_IS_CH_NR_VALID(channel)); - + DMAC_CH_CURR(base, channel) = (uint32_t)descriptor; } @@ -1405,14 +1410,14 @@ __STATIC_INLINE void Cy_DMAC_Channel_SetDescriptor(DMAC_Type * base, uint32_t ch * \param channel * The channel number. * -* \funcusage +* \funcusage * \snippet dmac/snippet/main.c snippet_Cy_DMAC_Enable * *******************************************************************************/ __STATIC_INLINE void Cy_DMAC_Channel_Enable(DMAC_Type * base, uint32_t channel) { CY_ASSERT_L1(CY_DMAC_IS_CH_NR_VALID(channel)); - + DMAC_CH_CTL(base, channel) |= DMAC_CH_V2_CTL_ENABLED_Msk; } @@ -1429,14 +1434,14 @@ __STATIC_INLINE void Cy_DMAC_Channel_Enable(DMAC_Type * base, uint32_t channel) * \param channel * The channel number. * -* \funcusage +* \funcusage * \snippet dmac/snippet/main.c snippet_Cy_DMAC_Disable * *******************************************************************************/ __STATIC_INLINE void Cy_DMAC_Channel_Disable(DMAC_Type * base, uint32_t channel) { CY_ASSERT_L1(CY_DMAC_IS_CH_NR_VALID(channel)); - + DMAC_CH_CTL(base, channel) &= (uint32_t) ~DMAC_CH_V2_CTL_ENABLED_Msk; } @@ -1456,7 +1461,7 @@ __STATIC_INLINE void Cy_DMAC_Channel_Disable(DMAC_Type * base, uint32_t channel) * \param priority * The priority to be set for the DMAC channel. The allowed values are 0,1,2,3. * -* \funcusage +* \funcusage * \snippet dmac/snippet/main.c snippet_Cy_DMAC_Enable * *******************************************************************************/ @@ -1464,7 +1469,7 @@ __STATIC_INLINE void Cy_DMAC_Channel_SetPriority(DMAC_Type * base, uint32_t chan { CY_ASSERT_L1(CY_DMAC_IS_CH_NR_VALID(channel)); CY_ASSERT_L2(CY_DMAC_IS_PRIORITY_VALID(priority)); - + CY_REG32_CLR_SET(DMAC_CH_CTL(base, channel), DMAC_CH_V2_CTL_PRIO, priority); } @@ -1484,14 +1489,14 @@ __STATIC_INLINE void Cy_DMAC_Channel_SetPriority(DMAC_Type * base, uint32_t chan * \return * The priority of the channel. * -* \funcusage +* \funcusage * \snippet dmac/snippet/main.c snippet_Cy_DMAC_Disable * *******************************************************************************/ __STATIC_INLINE uint32_t Cy_DMAC_Channel_GetPriority(DMAC_Type const * base, uint32_t channel) { CY_ASSERT_L1(CY_DMAC_IS_CH_NR_VALID(channel)); - + return ((uint32_t) _FLD2VAL(DMAC_CH_V2_CTL_PRIO, DMAC_CH_CTL(base, channel))); } @@ -1518,7 +1523,7 @@ __STATIC_INLINE uint32_t Cy_DMAC_Channel_GetPriority(DMAC_Type const * base, uin __STATIC_INLINE void * Cy_DMAC_Channel_GetCurrentSrcAddress(DMAC_Type * base, uint32_t channel) { CY_ASSERT_L1(CY_DMAC_IS_CH_NR_VALID(channel)); - + return ((void *)(DMAC_CH_DESCR_SRC(base, channel))); } @@ -1545,7 +1550,7 @@ __STATIC_INLINE void * Cy_DMAC_Channel_GetCurrentSrcAddress(DMAC_Type * base, ui __STATIC_INLINE void * Cy_DMAC_Channel_GetCurrentDstAddress(DMAC_Type * base, uint32_t channel) { CY_ASSERT_L1(CY_DMAC_IS_CH_NR_VALID(channel)); - + return ((void *)(DMAC_CH_DESCR_DST(base, channel))); } @@ -1572,7 +1577,7 @@ __STATIC_INLINE void * Cy_DMAC_Channel_GetCurrentDstAddress(DMAC_Type * base, ui __STATIC_INLINE uint32_t Cy_DMAC_Channel_GetCurrentXloopIndex(DMAC_Type const * base, uint32_t channel) { CY_ASSERT_L1(CY_DMAC_IS_CH_NR_VALID(channel)); - + return (_FLD2VAL(DMAC_CH_V2_IDX_X, DMAC_CH_IDX(base, channel))); } @@ -1599,7 +1604,7 @@ __STATIC_INLINE uint32_t Cy_DMAC_Channel_GetCurrentXloopIndex(DMAC_Type const * __STATIC_INLINE uint32_t Cy_DMAC_Channel_GetCurrentYloopIndex(DMAC_Type const * base, uint32_t channel) { CY_ASSERT_L1(CY_DMAC_IS_CH_NR_VALID(channel)); - + return (_FLD2VAL(DMAC_CH_V2_IDX_Y, DMAC_CH_IDX(base, channel))); } @@ -1619,14 +1624,14 @@ __STATIC_INLINE uint32_t Cy_DMAC_Channel_GetCurrentYloopIndex(DMAC_Type const * * \return * The pointer to the descriptor associated with the channel. * -* \funcusage +* \funcusage * \snippet dmac/snippet/main.c snippet_Cy_DMAC_Descriptor_Deinit * *******************************************************************************/ __STATIC_INLINE cy_stc_dmac_descriptor_t * Cy_DMAC_Channel_GetCurrentDescriptor(DMAC_Type const * base, uint32_t channel) { CY_ASSERT_L1(CY_DMAC_IS_CH_NR_VALID(channel)); - + return ((cy_stc_dmac_descriptor_t*)(DMAC_CH_CURR(base, channel))); } @@ -1646,14 +1651,14 @@ __STATIC_INLINE cy_stc_dmac_descriptor_t * Cy_DMAC_Channel_GetCurrentDescriptor( * \return * The interrupt status, see \ref group_dmac_macros_interrupt_masks. * -* \funcusage +* \funcusage * \snippet dmac/snippet/main.c snippet_Cy_DMAC_GetInterruptStatus * *******************************************************************************/ __STATIC_INLINE uint32_t Cy_DMAC_Channel_GetInterruptStatus(DMAC_Type const * base, uint32_t channel) { CY_ASSERT_L1(CY_DMAC_IS_CH_NR_VALID(channel)); - + return (DMAC_CH_INTR(base, channel)); } @@ -1673,7 +1678,7 @@ __STATIC_INLINE uint32_t Cy_DMAC_Channel_GetInterruptStatus(DMAC_Type const * ba * \param interrupt * The interrupt mask, see \ref group_dmac_macros_interrupt_masks. * -* \funcusage +* \funcusage * \snippet dmac/snippet/main.c snippet_Cy_DMAC_ClearInterrupt * *******************************************************************************/ @@ -1702,7 +1707,7 @@ __STATIC_INLINE void Cy_DMAC_Channel_ClearInterrupt(DMAC_Type * base, uint32_t c * \param interrupt * The interrupt mask. See \ref group_dmac_macros_interrupt_masks. * -* \funcusage +* \funcusage * \snippet dmac/snippet/main.c snippet_Cy_DMAC_SetInterruptMask * *******************************************************************************/ @@ -1710,7 +1715,7 @@ __STATIC_INLINE void Cy_DMAC_Channel_SetInterrupt(DMAC_Type * base, uint32_t cha { CY_ASSERT_L1(CY_DMAC_IS_CH_NR_VALID(channel)); CY_ASSERT_L2(CY_DMAC_IS_INTR_MASK_VALID(interrupt)); - + DMAC_CH_INTR_SET(base, channel) = interrupt; } @@ -1730,14 +1735,14 @@ __STATIC_INLINE void Cy_DMAC_Channel_SetInterrupt(DMAC_Type * base, uint32_t cha * \return * The interrupt mask value. See \ref group_dmac_macros_interrupt_masks. * -* \funcusage +* \funcusage * \snippet dmac/snippet/main.c snippet_Cy_DMAC_SetInterruptMask * *******************************************************************************/ __STATIC_INLINE uint32_t Cy_DMAC_Channel_GetInterruptMask(DMAC_Type const * base, uint32_t channel) { CY_ASSERT_L1(CY_DMAC_IS_CH_NR_VALID(channel)); - + return (DMAC_CH_INTR_MASK(base, channel)); } @@ -1756,8 +1761,8 @@ __STATIC_INLINE uint32_t Cy_DMAC_Channel_GetInterruptMask(DMAC_Type const * base * * \param interrupt * The interrupt mask, see \ref group_dmac_macros_interrupt_masks. -* -* \funcusage +* +* \funcusage * \snippet dmac/snippet/main.c snippet_Cy_DMAC_SetInterruptMask * *******************************************************************************/ @@ -1785,14 +1790,14 @@ __STATIC_INLINE void Cy_DMAC_Channel_SetInterruptMask(DMAC_Type * base, uint32_t * \return * The masked interrupt status. See \ref group_dmac_macros_interrupt_masks. * -* \funcusage +* \funcusage * \snippet dmac/snippet/main.c snippet_Cy_DMAC_ClearInterrupt * *******************************************************************************/ __STATIC_INLINE uint32_t Cy_DMAC_Channel_GetInterruptStatusMasked(DMAC_Type const * base, uint32_t channel) { CY_ASSERT_L1(CY_DMAC_IS_CH_NR_VALID(channel)); - + return (DMAC_CH_INTR_MASKED(base, channel)); } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_efuse.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_efuse.h index caa6a62517..40b7b4ffcf 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_efuse.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_efuse.h @@ -1,12 +1,12 @@ /***************************************************************************//** * \file cy_efuse.h -* \version 1.10.2 +* \version 1.10.3 * * Provides the API declarations of the eFuse driver. * ******************************************************************************** * \copyright -* Copyright 2017-2019 Cypress Semiconductor Corporation +* Copyright 2017-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -33,7 +33,7 @@ * programmable (OTP). * * The functions and other declarations used in this driver are in cy_efuse.h. -* You can include cy_pdl.h (ModusToolbox only) to get access to all functions +* You can include cy_pdl.h to get access to all functions * and declarations in the PDL. * * The eFuse driver enables reading the state of any bit. The eFuse driver does @@ -85,6 +85,11 @@ *
VersionChangesReason for Change
1.10.1Minor documentation updates.Documentation enhancement.
1.10The \ref Cy_DMAC_Channel_ClearInterrupt is changed.Minor defect fixing.
* * +* +* +* +* +* * * * diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_flash.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_flash.h index 00057e3ed3..453cdd617f 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_flash.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_flash.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_flash.h -* \version 3.30.5 +* \version 3.40 * * Provides the API declarations of the Flash driver. * @@ -30,8 +30,8 @@ * \{ * Internal flash memory programming * -* The functions and other declarations used in this driver are in cy_flash.h. -* You can include cy_pdl.h (ModusToolbox only) to get access to all functions +* The functions and other declarations used in this driver are in cy_flash.h. +* You can include cy_pdl.h to get access to all functions * and declarations in the PDL. * * Flash memory in PSoC devices provides non-volatile storage for user firmware, @@ -42,7 +42,7 @@ * or modify the SROM code. The driver API requests the system call by acquiring * the Inter-processor communication (IPC) and writing the SROM function opcode * and parameters to its input registers. As a result, an NMI interrupt is invoked -* and the requested SROM function is executed. The operation status is returned +* and the requested SROM function is executed. The operation status is returned * to the driver context and a release interrupt is triggered. * * Writing to flash can take up to 20 milliseconds. During this time, @@ -52,8 +52,8 @@ * interrupt instead of a reset. * * A Read while Write violation occurs when a flash Read operation is initiated -* in the same or neighboring (neighboring restriction is applicable just for the -* CY8C6xx6, CY8C6xx7 devices) flash sector where the flash Write, Erase, or +* in the same or neighboring (neighboring restriction is applicable just for the +* CY8C6xx6, CY8C6xx7 devices) flash sector where the flash Write, Erase, or * Program operation is working. This violation may cause a HardFault exception. * To avoid the Read while Write violation, carefully split the * Read and Write operation on flash sectors which are not neighboring, @@ -69,14 +69,14 @@ * - Application flash memory (from 2 to 8 sectors) - 128KB/256KB each. * - EE emulation flash memory - 32KB. * -* Write operation may be done as Blocking or Partially Blocking, +* Write operation may be done as Blocking or Partially Blocking, * defined as follows: * * \subsection group_flash_config_blocking Blocking: * In this case, the entire Flash block is not available for the duration of the * Write (∼16ms). Therefore, no Flash accesses (from any Bus Master) can * occur during that time. CPU execution can be performed from SRAM. All -* pre-fetching must be disabled. Code execution from Flash is blocked for the +* pre-fetching must be disabled. Code execution from Flash is blocked for the * Flash Write duration for both cores. * * \subsection group_flash_config_block_const Constraints for Blocking Flash operations: @@ -97,14 +97,14 @@ * -# Flash Write cannot be performed in Ultra Low Power (core voltage 0.9V) mode. * -# Interrupts must be enabled on both active cores. Do not enter a critical * section during flash operation. -* -# For the CY8C6xx6, CY8C6xx7 devices user must guarantee that system pipe -* interrupts (IPC interrupts 3 and 4) have the highest priority, or -* at least that pipe interrupts are not interrupted or in a pending state +* -# For the CY8C6xx6, CY8C6xx7 devices user must guarantee that system pipe +* interrupts (IPC interrupts 3 and 4) have the highest priority, or +* at least that pipe interrupts are not interrupted or in a pending state * for more than 700 µs. * -# User must guarantee that during flash write operation no flash read * operations are performed by bus masters other than CM0+ and CM4 (DMA and * Crypto). -* -# If you do not use the default startup, perform the following steps +* -# If you do not use the default startup, perform the following steps * before any flash write/erase operations: * \snippet flash/snippet/main.c Flash Initialization * @@ -119,7 +119,7 @@ * *
*
VersionChangesReason for Change
1.10.3Minor documentation updates.Documentation enhancement.
1.10.2Fix driver header path.Folder structure changed.
-* * * @@ -167,7 +167,7 @@ * scenario - see Figure 1. * * This allows the core that initiates Cy_Flash_StartWrite() to execute for about -* 20% of Flash Write operation. The other core executes for about 80% of Flash +* 20% of Flash Write operation. The other core executes for about 80% of Flash * Write operation. * * Some constraints must be planned for in the Partially Blocking mode which are @@ -197,7 +197,7 @@ * read of any bus master: CM0+, CM4, DMA, Crypto, etc.) * -# Do not write to and read/execute from the same flash sector at the same * time. This is true for all sectors. -* -# Writing rules in application flash (this restriction is applicable just +* -# Writing rules in application flash (this restriction is applicable just * for CY8C6xx6, CY8C6xx7 devices): * -# Any bus master can read/execute from UFLASH S0 and/or S1, during * flash write to UFLASH S2 or S3. @@ -211,11 +211,11 @@ * -# Flash Write cannot be performed in Ultra Low Power mode (core voltage 0.9V). * -# Interrupts must be enabled on both active cores. Do not enter a critical * section during flash operation. -* -# For the CY8C6xx6, CY8C6xx7 devices user must guarantee that system pipe -* interrupts (IPC interrupts 3 and 4) have the highest priority, or at -* least that pipe interrupts are not interrupted or in a pending state +* -# For the CY8C6xx6, CY8C6xx7 devices user must guarantee that system pipe +* interrupts (IPC interrupts 3 and 4) have the highest priority, or at +* least that pipe interrupts are not interrupted or in a pending state * for more than 700 µs. -* -# If you do not use the default startup, perform the following steps +* -# If you do not use the default startup, perform the following steps * before any flash write/erase operations: * \snippet flash/snippet/main.c Flash Initialization * @@ -248,7 +248,7 @@ * is used to get transmitted data via the \ref group_ipc channel. * We cast only one pointer, so there is no way to avoid this cast. * -* +* *
Table 1 - Block-out periods (timing values are valid just for the +* Table 1 - Block-out periods (timing values are valid just for the * CY8C6xx6, CY8C6xx7 devices)
Block-out
* * \section group_flash_changelog Changelog @@ -256,6 +256,11 @@ * * * +* +* +* +* +* * * * @@ -285,8 +290,8 @@ * * * -* * * @@ -302,14 +307,14 @@ * * -* * * * -* -* * * @@ -395,7 +400,7 @@ extern "C" { #define CY_FLASH_DRV_VERSION_MAJOR 3 /** Driver minor version */ -#define CY_FLASH_DRV_VERSION_MINOR 30 +#define CY_FLASH_DRV_VERSION_MINOR 40 #define CY_FLASH_ID (CY_PDL_DRV_ID(0x14UL)) /**< FLASH PDL ID */ @@ -451,7 +456,7 @@ typedef enum cy_en_flashdrv_status uint16_t intrRelMask; /**< Mask */ } cy_stc_flash_notify_t; #endif /* !defined(CY_FLASH_RWW_DRV_SUPPORT_DISABLED) */ - + /** \} group_flash_enumerated_types */ /*************************************** diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_gpio.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_gpio.h index c74bdc9102..305125ac5e 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_gpio.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_gpio.h @@ -1,12 +1,12 @@ /***************************************************************************//** * \file cy_gpio.h -* \version 1.20 +* \version 1.20.1 * * Provides an API declaration of the GPIO driver * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -27,8 +27,8 @@ * \{ * The GPIO driver provides an API to configure and access device Input/Output pins. * -* The functions and other declarations used in this driver are in cy_gpio.h. -* You can include cy_pdl.h (ModusToolbox only) to get access to all functions +* The functions and other declarations used in this driver are in cy_gpio.h. +* You can include cy_pdl.h to get access to all functions * and declarations in the PDL. * * IO pins include all general purpose types such as GPIO, SIO, HSIO, AUXIO, and @@ -36,21 +36,21 @@ * * Initialization can be performed either at the port level or by configuring the * individual pins. For efficient use of code space, port -* configuration should be used in the field. Refer to the product device header files +* configuration should be used in the field. Refer to the product device header files * for the list of supported ports and pins. -* -* - Single pin configuration is performed by using \ref Cy_GPIO_Pin_FastInit +* +* - Single pin configuration is performed by using \ref Cy_GPIO_Pin_FastInit * (provide specific values) or \ref Cy_GPIO_Pin_Init (provide a filled * cy_stc_gpio_pin_config_t structure). -* - An entire port can be configured using \ref Cy_GPIO_Port_Init. Provide a filled -* cy_stc_gpio_prt_config_t structure. The values in the structure are +* - An entire port can be configured using \ref Cy_GPIO_Port_Init. Provide a filled +* cy_stc_gpio_prt_config_t structure. The values in the structure are * bitfields representing the desired value for each pin in the port. * - Pin configuration and management is based on the port address and pin number. * \ref Cy_GPIO_PortToAddr function can optionally be used to calculate the port * address from the port number at run-time. * -* Once the pin/port initialization is complete, each pin can be accessed by -* specifying the port (GPIO_PRT_Type) and the pin (0-7) in the provided API +* Once the pin/port initialization is complete, each pin can be accessed by +* specifying the port (GPIO_PRT_Type) and the pin (0-7) in the provided API * functions. * * \section group_gpio_configuration Configuration Considerations @@ -63,18 +63,18 @@ * 3. Some API functions perform read-modify-write operations on shared port * registers. These functions are not thread safe and care must be taken when * called by the application. -* 4. Digital input buffer provides a high-impedance buffer for the external -* digital input. The input buffer is connected to the HSIOM for routing to -* the CPU port registers and selected peripheral. Enabling the input +* 4. Digital input buffer provides a high-impedance buffer for the external +* digital input. The input buffer is connected to the HSIOM for routing to +* the CPU port registers and selected peripheral. Enabling the input * buffer provides possibility to read the pin state via the CPU. -* If pin is connected to an analog signal, the input buffer should be -* disabled to avoid crowbar currents. For more information refer to device +* If pin is connected to an analog signal, the input buffer should be +* disabled to avoid crowbar currents. For more information refer to device * TRM and the device datasheet. * * Multiple pins on a port can be updated using direct port register writes with an -* appropriate port mask. An example is shown below, highlighting the different ways of +* appropriate port mask. An example is shown below, highlighting the different ways of * configuring Port 1 pins using: -* +* * - Port output data register * - Port output data set register * - Port output data clear register @@ -100,13 +100,13 @@ * * -* * * * * -* *
VersionChangesReason for Change
3.40Updated Cy_Flash_OperationStatus() to access protected registers.Added PSoC 64 device support.
3.30.4Improved documentation.User experience enhancement.The driver improvements based on the usability feedback.
Added new API functions \ref Cy_Flash_EraseSector, -* \ref Cy_Flash_StartEraseSector, \ref Cy_Flash_EraseSubsector, +* Added new API functions \ref Cy_Flash_EraseSector, +* \ref Cy_Flash_StartEraseSector, \ref Cy_Flash_EraseSubsector, * \ref Cy_Flash_StartEraseSubsector The driver improvements based on the usability feedback.
Added register access layer. Use register access macros instead * of direct register access using dereferenced pointers.Makes register access device-independent, so that the PDL does +* Makes register access device-independent, so that the PDL does * not need to be recompiled for each supported part number.
3.11Updated driver functionality to correctly use the SysClk measurement +* Updated driver functionality to correctly use the SysClk measurement * counters while partially blocking flash operationsAdded arbiter mechanism for correct usage of the SysClk measurement +* Added arbiter mechanism for correct usage of the SysClk measurement * counters
AA cast should not be performed between a pointer to object type and * a different pointer to object type. This code is safe because the elements of both GPIO_PRT_V1_Type and GPIO_PRT_V2_Type +* This code is safe because the elements of both GPIO_PRT_V1_Type and GPIO_PRT_V2_Type * types have identical alignment.
16.7AA pointer parameter in a function prototype should be declared as pointer +* A pointer parameter in a function prototype should be declared as pointer * to const if the pointer is not used to modify the addressed object.The objects pointed to by the base addresses of the GPIO port are not always modified. * While a const qualifier can be used in select scenarios, it brings little benefit @@ -118,6 +118,11 @@ * * * +* +* +* +* +* * * * @@ -132,12 +137,12 @@ * * -* * * * -*
VersionChangesReason for Change
1.20.1Minor documentation updates.Documentation enhancement.
1.20Flattened the organization of the driver source code into the single source directory and the single include directory.Driver library directory-structure simplification.
Added register access layer. Use register access macros instead * of direct register access using dereferenced pointers.Makes register access device-independent, so that the PDL does +* Makes register access device-independent, so that the PDL does * not need to be recompiled for each supported part number.
1.10.1Updated description for the functions: \ref Cy_GPIO_GetInterruptStatus, +* Updated description for the functions: \ref Cy_GPIO_GetInterruptStatus, * \ref Cy_GPIO_GetInterruptMask, \ref Cy_GPIO_GetInterruptStatusMasked. * * Minor documentation edits. @@ -205,7 +210,7 @@ extern "C" { */ /** GPIO Driver error codes */ -typedef enum +typedef enum { CY_GPIO_SUCCESS = 0x00U, /**< Returned successful */ CY_GPIO_BAD_PARAM = CY_GPIO_ID | CY_PDL_STATUS_ERROR | 0x01U, /**< Bad parameter was passed */ @@ -246,7 +251,7 @@ typedef enum */ /** This structure is used to initialize a port of GPIO pins */ -typedef struct +typedef struct { uint32_t out; /**< Initial output data for the IO pins in the port */ uint32_t intrMask; /**< Interrupt enable mask for the port interrupt */ @@ -378,7 +383,7 @@ typedef struct (CY_SIO_VOH_2_50 == (vrefSel)) || \ (CY_SIO_VOH_2_78 == (vrefSel)) || \ (CY_SIO_VOH_4_16 == (vrefSel))) - + #define CY_GPIO_IS_PIN_BIT_VALID(pinBit) (0U == ((pinBit) & (uint32_t)~CY_GPIO_PRT_PINS_MASK)) #define CY_GPIO_IS_INTR_CFG_VALID(intrCfg) (0U == ((intrCfg) & (uint32_t)~CY_GPIO_PRT_INTR_CFG_RANGE_MASK)) #define CY_GPIO_IS_INTR_MASK_VALID(intrMask) (0U == ((intrMask) & (uint32_t)~CY_GPIO_PRT_INT_MASK_MASK)) @@ -641,7 +646,7 @@ __STATIC_INLINE uint32_t Cy_GPIO_GetInterruptCause3(void); * \param value * HSIOM input selection * -* \note +* \note * This function modifies a port register in a read-modify-write operation. It is * not thread safe as the resource is shared among multiple pins on a port. * @@ -699,7 +704,7 @@ __STATIC_INLINE en_hsiom_sel_t Cy_GPIO_GetHSIOM(GPIO_PRT_Type* base, uint32_t pi uint32_t returnValue; uint32_t portNum; HSIOM_PRT_V1_Type* portAddrHSIOM; - + CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum)); portNum = ((uint32_t)(base) - CY_GPIO_BASE) / GPIO_PRT_SECTION_SIZE; @@ -741,7 +746,7 @@ __STATIC_INLINE en_hsiom_sel_t Cy_GPIO_GetHSIOM(GPIO_PRT_Type* base, uint32_t pi __STATIC_INLINE GPIO_PRT_Type* Cy_GPIO_PortToAddr(uint32_t portNum) { GPIO_PRT_Type* portBase; - + if(portNum < (uint32_t)IOSS_GPIO_GPIO_PORT_NR) { portBase = (GPIO_PRT_Type *)(CY_GPIO_BASE + (GPIO_PRT_SECTION_SIZE * portNum)); @@ -785,7 +790,7 @@ __STATIC_INLINE GPIO_PRT_Type* Cy_GPIO_PortToAddr(uint32_t portNum) __STATIC_INLINE uint32_t Cy_GPIO_Read(GPIO_PRT_Type* base, uint32_t pinNum) { CY_ASSERT_L2(CY_GPIO_IS_FILTER_PIN_VALID(pinNum)); - + return (GPIO_PRT_IN(base) >> (pinNum)) & CY_GPIO_IN_MASK; } @@ -878,7 +883,7 @@ __STATIC_INLINE uint32_t Cy_GPIO_ReadOut(GPIO_PRT_Type* base, uint32_t pinNum) __STATIC_INLINE void Cy_GPIO_Set(GPIO_PRT_Type* base, uint32_t pinNum) { CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum)); - + GPIO_PRT_OUT_SET(base) = CY_GPIO_OUT_MASK << pinNum; } @@ -905,7 +910,7 @@ __STATIC_INLINE void Cy_GPIO_Set(GPIO_PRT_Type* base, uint32_t pinNum) __STATIC_INLINE void Cy_GPIO_Clr(GPIO_PRT_Type* base, uint32_t pinNum) { CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum)); - + GPIO_PRT_OUT_CLR(base) = CY_GPIO_OUT_MASK << pinNum; } @@ -933,7 +938,7 @@ __STATIC_INLINE void Cy_GPIO_Clr(GPIO_PRT_Type* base, uint32_t pinNum) __STATIC_INLINE void Cy_GPIO_Inv(GPIO_PRT_Type* base, uint32_t pinNum) { CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum)); - + GPIO_PRT_OUT_INV(base) = CY_GPIO_OUT_MASK << pinNum; } @@ -958,7 +963,7 @@ __STATIC_INLINE void Cy_GPIO_Inv(GPIO_PRT_Type* base, uint32_t pinNum) * \param value * Pin drive mode. Options are detailed in \ref group_gpio_driveModes macros * -* \note +* \note * This function modifies a port register in a read-modify-write operation. It is * not thread safe as the resource is shared among multiple pins on a port. * @@ -1002,7 +1007,7 @@ __STATIC_INLINE void Cy_GPIO_SetDrivemode(GPIO_PRT_Type* base, uint32_t pinNum, __STATIC_INLINE uint32_t Cy_GPIO_GetDrivemode(GPIO_PRT_Type* base, uint32_t pinNum) { CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum)); - + return (GPIO_PRT_CFG(base) >> (pinNum << CY_GPIO_DRIVE_MODE_OFFSET)) & CY_GPIO_CFG_DM_MASK; } @@ -1022,7 +1027,7 @@ __STATIC_INLINE uint32_t Cy_GPIO_GetDrivemode(GPIO_PRT_Type* base, uint32_t pinN * \param value * Pin voltage threshold mode. Options are detailed in \ref group_gpio_vtrip macros * -* \note +* \note * This function modifies a port register in a read-modify-write operation. It is * not thread safe as the resource is shared among multiple pins on a port. * @@ -1064,7 +1069,7 @@ __STATIC_INLINE void Cy_GPIO_SetVtrip(GPIO_PRT_Type* base, uint32_t pinNum, uint __STATIC_INLINE uint32_t Cy_GPIO_GetVtrip(GPIO_PRT_Type* base, uint32_t pinNum) { CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum)); - + return (GPIO_PRT_CFG_IN(base) >> pinNum) & CY_GPIO_CFG_IN_VTRIP_SEL_MASK; } @@ -1075,7 +1080,7 @@ __STATIC_INLINE uint32_t Cy_GPIO_GetVtrip(GPIO_PRT_Type* base, uint32_t pinNum) * * Configures the pin output buffer slew rate. * -* \note +* \note * This function has no effect for the GPIO ports, where the slew rate * configuration is not available. Refer to device datasheet for details. * @@ -1088,7 +1093,7 @@ __STATIC_INLINE uint32_t Cy_GPIO_GetVtrip(GPIO_PRT_Type* base, uint32_t pinNum) * \param value * Pin slew rate. Options are detailed in \ref group_gpio_slewRate macros * -* \note +* \note * This function modifies a port register in a read-modify-write operation. It is * not thread safe as the resource is shared among multiple pins on a port. * @@ -1150,7 +1155,7 @@ __STATIC_INLINE uint32_t Cy_GPIO_GetSlewRate(GPIO_PRT_Type* base, uint32_t pinNu * \param value * Pin drive strength. Options are detailed in \ref group_gpio_driveStrength macros * -* \note +* \note * This function modifies a port register in a read-modify-write operation. It is * not thread safe as the resource is shared among multiple pins on a port. * @@ -1165,7 +1170,7 @@ __STATIC_INLINE void Cy_GPIO_SetDriveSel(GPIO_PRT_Type* base, uint32_t pinNum, u CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum)); CY_ASSERT_L2(CY_GPIO_IS_DRIVE_SEL_VALID(value)); - + pinLoc = (uint32_t)(pinNum << 1u) + CY_GPIO_CFG_OUT_DRIVE_OFFSET; tempReg = GPIO_PRT_CFG_OUT(base) & ~(CY_GPIO_CFG_OUT_DRIVE_SEL_MASK << pinLoc); GPIO_PRT_CFG_OUT(base) = tempReg | ((value & CY_GPIO_CFG_OUT_DRIVE_SEL_MASK) << pinLoc); @@ -1195,7 +1200,7 @@ __STATIC_INLINE uint32_t Cy_GPIO_GetDriveSel(GPIO_PRT_Type* base, uint32_t pinNu { CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum)); - return ((GPIO_PRT_CFG_OUT(base) >> ((uint32_t)(pinNum << 1u) + CY_GPIO_CFG_OUT_DRIVE_OFFSET)) + return ((GPIO_PRT_CFG_OUT(base) >> ((uint32_t)(pinNum << 1u) + CY_GPIO_CFG_OUT_DRIVE_OFFSET)) & CY_GPIO_CFG_OUT_DRIVE_SEL_MASK); } @@ -1223,7 +1228,7 @@ __STATIC_INLINE uint32_t Cy_GPIO_GetDriveSel(GPIO_PRT_Type* base, uint32_t pinNu * \param value * SIO pair output buffer regulator mode. Options are detailed in \ref group_gpio_sioVreg macros * -* \note +* \note * This function modifies a port register in a read-modify-write operation. It is * not thread safe as the resource is shared among multiple pins on a port. * @@ -1269,7 +1274,7 @@ __STATIC_INLINE void Cy_GPIO_SetVregEn(GPIO_PRT_Type* base, uint32_t pinNum, uin __STATIC_INLINE uint32_t Cy_GPIO_GetVregEn(GPIO_PRT_Type* base, uint32_t pinNum) { CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum)); - + return (GPIO_PRT_CFG_SIO(base) >> ((pinNum & CY_GPIO_SIO_ODD_PIN_MASK) << CY_GPIO_CFG_SIO_OFFSET)) & CY_GPIO_VREG_EN_MASK; } @@ -1291,7 +1296,7 @@ __STATIC_INLINE uint32_t Cy_GPIO_GetVregEn(GPIO_PRT_Type* base, uint32_t pinNum) * \param value * SIO pair input buffer mode. Options are detailed in \ref group_gpio_sioIbuf macros * -* \note +* \note * This function modifies a port register in a read-modify-write operation. It is * not thread safe as the resource is shared among multiple pins on a port. * @@ -1337,7 +1342,7 @@ __STATIC_INLINE void Cy_GPIO_SetIbufMode(GPIO_PRT_Type* base, uint32_t pinNum, u __STATIC_INLINE uint32_t Cy_GPIO_GetIbufMode(GPIO_PRT_Type* base, uint32_t pinNum) { CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum)); - + return (GPIO_PRT_CFG_SIO(base) >> (((pinNum & CY_GPIO_SIO_ODD_PIN_MASK) << CY_GPIO_CFG_SIO_OFFSET) + CY_GPIO_IBUF_SHIFT)) & CY_GPIO_IBUF_MASK; } @@ -1359,7 +1364,7 @@ __STATIC_INLINE uint32_t Cy_GPIO_GetIbufMode(GPIO_PRT_Type* base, uint32_t pinNu * \param value * SIO pair input buffer trip point. Options are detailed in \ref group_gpio_sioVtrip macros * -* \note +* \note * This function modifies a port register in a read-modify-write operation. It is * not thread safe as the resource is shared among multiple pins on a port. * @@ -1427,7 +1432,7 @@ __STATIC_INLINE uint32_t Cy_GPIO_GetVtripSel(GPIO_PRT_Type* base, uint32_t pinNu * \param value * SIO pair reference voltage. Options are detailed in \ref group_gpio_sioVref macros * -* \note +* \note * This function modifies a port register in a read-modify-write operation. It is * not thread safe as the resource is shared among multiple pins on a port. * @@ -1442,7 +1447,7 @@ __STATIC_INLINE void Cy_GPIO_SetVrefSel(GPIO_PRT_Type* base, uint32_t pinNum, ui CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum)); CY_ASSERT_L2(CY_GPIO_IS_VREF_SEL_VALID(value)); - + pinLoc = ((pinNum & CY_GPIO_SIO_ODD_PIN_MASK) << CY_GPIO_CFG_SIO_OFFSET) + CY_GPIO_VREF_SEL_SHIFT; tempReg = (GPIO_PRT_CFG_SIO(base) & ~(CY_GPIO_VREF_SEL_MASK << pinLoc)); GPIO_PRT_CFG_SIO(base) = tempReg | ((value & CY_GPIO_VREF_SEL_MASK) << pinLoc); @@ -1473,7 +1478,7 @@ __STATIC_INLINE void Cy_GPIO_SetVrefSel(GPIO_PRT_Type* base, uint32_t pinNum, ui __STATIC_INLINE uint32_t Cy_GPIO_GetVrefSel(GPIO_PRT_Type* base, uint32_t pinNum) { CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum)); - + return (GPIO_PRT_CFG_SIO(base) >> (((pinNum & CY_GPIO_SIO_ODD_PIN_MASK) << CY_GPIO_CFG_SIO_OFFSET) + CY_GPIO_VREF_SEL_SHIFT)) & CY_GPIO_VREF_SEL_MASK; } @@ -1498,7 +1503,7 @@ __STATIC_INLINE uint32_t Cy_GPIO_GetVrefSel(GPIO_PRT_Type* base, uint32_t pinNum * \param value * SIO pair reference voltage. Options are detailed in \ref group_gpio_sioVoh macros * -* \note +* \note * This function modifies a port register in a read-modify-write operation. It is * not thread safe as the resource is shared among multiple pins on a port. * @@ -1544,7 +1549,7 @@ __STATIC_INLINE void Cy_GPIO_SetVohSel(GPIO_PRT_Type* base, uint32_t pinNum, uin __STATIC_INLINE uint32_t Cy_GPIO_GetVohSel(GPIO_PRT_Type* base, uint32_t pinNum) { CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum)); - + return (GPIO_PRT_CFG_SIO(base) >> (((pinNum & CY_GPIO_SIO_ODD_PIN_MASK) << CY_GPIO_CFG_SIO_OFFSET) + CY_GPIO_VOH_SEL_SHIFT)) & CY_GPIO_VOH_SEL_MASK; } @@ -1561,7 +1566,7 @@ __STATIC_INLINE uint32_t Cy_GPIO_GetVohSel(GPIO_PRT_Type* base, uint32_t pinNum) * * Returns the current unmasked interrupt state of the pin. * -* The core processor's NVIC is triggered by the masked interrupt bits. This +* The core processor's NVIC is triggered by the masked interrupt bits. This * function allows reading the unmasked interrupt state. Whether the bit * positions actually trigger the interrupt are defined by the interrupt mask bits. * @@ -1583,7 +1588,7 @@ __STATIC_INLINE uint32_t Cy_GPIO_GetVohSel(GPIO_PRT_Type* base, uint32_t pinNum) __STATIC_INLINE uint32_t Cy_GPIO_GetInterruptStatus(GPIO_PRT_Type* base, uint32_t pinNum) { CY_ASSERT_L2(CY_GPIO_IS_FILTER_PIN_VALID(pinNum)); - + return (GPIO_PRT_INTR(base) >> pinNum) & CY_GPIO_INTR_STATUS_MASK; } @@ -1608,7 +1613,7 @@ __STATIC_INLINE uint32_t Cy_GPIO_GetInterruptStatus(GPIO_PRT_Type* base, uint32_ __STATIC_INLINE void Cy_GPIO_ClearInterrupt(GPIO_PRT_Type* base, uint32_t pinNum) { CY_ASSERT_L2(CY_GPIO_IS_FILTER_PIN_VALID(pinNum)); - + /* Any INTR MMIO registers AHB clearing must be preceded with an AHB read access */ (void)GPIO_PRT_INTR(base); @@ -1636,7 +1641,7 @@ __STATIC_INLINE void Cy_GPIO_ClearInterrupt(GPIO_PRT_Type* base, uint32_t pinNum * 0 = Pin interrupt not forwarded to CPU interrupt controller * 1 = Pin interrupt masked and forwarded to CPU interrupt controller * -* \note +* \note * This function modifies a port register in a read-modify-write operation. It is * not thread safe as the resource is shared among multiple pins on a port. * @@ -1683,7 +1688,7 @@ __STATIC_INLINE void Cy_GPIO_SetInterruptMask(GPIO_PRT_Type* base, uint32_t pinN __STATIC_INLINE uint32_t Cy_GPIO_GetInterruptMask(GPIO_PRT_Type* base, uint32_t pinNum) { CY_ASSERT_L2(CY_GPIO_IS_FILTER_PIN_VALID(pinNum)); - + return (GPIO_PRT_INTR_MASK(base) >> pinNum) & CY_GPIO_INTR_EN_MASK; } @@ -1694,7 +1699,7 @@ __STATIC_INLINE uint32_t Cy_GPIO_GetInterruptMask(GPIO_PRT_Type* base, uint32_t * * Return the pin's current interrupt state after being masked. * -* The core processor's NVIC is triggered by the masked interrupt bits. This +* The core processor's NVIC is triggered by the masked interrupt bits. This * function allows reading this masked interrupt state. Note that the bits that * are not masked will not be forwarded to the NVIC. * @@ -1716,7 +1721,7 @@ __STATIC_INLINE uint32_t Cy_GPIO_GetInterruptMask(GPIO_PRT_Type* base, uint32_t __STATIC_INLINE uint32_t Cy_GPIO_GetInterruptStatusMasked(GPIO_PRT_Type* base, uint32_t pinNum) { CY_ASSERT_L2(CY_GPIO_IS_FILTER_PIN_VALID(pinNum)); - + return (GPIO_PRT_INTR_MASKED(base) >> pinNum) & CY_GPIO_INTR_MASKED_MASK; } @@ -1741,7 +1746,7 @@ __STATIC_INLINE uint32_t Cy_GPIO_GetInterruptStatusMasked(GPIO_PRT_Type* base, u __STATIC_INLINE void Cy_GPIO_SetSwInterrupt(GPIO_PRT_Type* base, uint32_t pinNum) { CY_ASSERT_L2(CY_GPIO_IS_FILTER_PIN_VALID(pinNum)); - + GPIO_PRT_INTR_SET(base) = CY_GPIO_INTR_SET_MASK << pinNum; } @@ -1762,7 +1767,7 @@ __STATIC_INLINE void Cy_GPIO_SetSwInterrupt(GPIO_PRT_Type* base, uint32_t pinNum * \param value * Pin interrupt mode. Options are detailed in \ref group_gpio_interruptTrigger macros * -* \note +* \note * This function modifies a port register in a read-modify-write operation. It is * not thread safe as the resource is shared among multiple pins on a port. * @@ -1829,7 +1834,7 @@ __STATIC_INLINE uint32_t Cy_GPIO_GetInterruptEdge(GPIO_PRT_Type* base, uint32_t * \param value * The number of the port pin to route to the port filter (0...7) * -* \note +* \note * This function modifies a port register in a read-modify-write operation. It is * not thread safe as the resource is shared among multiple pins on a port. * @@ -1846,7 +1851,7 @@ __STATIC_INLINE void Cy_GPIO_SetFilter(GPIO_PRT_Type* base, uint32_t value) uint32_t tempReg; CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(value)); - + tempReg = GPIO_PRT_INTR_CFG(base) & ~(CY_GPIO_INTR_FLT_EDGE_MASK << CY_GPIO_INTR_FILT_OFFSET); GPIO_PRT_INTR_CFG(base) = tempReg | ((value & CY_GPIO_INTR_FLT_EDGE_MASK) << CY_GPIO_INTR_FILT_OFFSET); } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_i2s.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_i2s.h index f488fcb4bd..346e07f722 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_i2s.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_i2s.h @@ -1,12 +1,12 @@ /***************************************************************************//** * \file cy_i2s.h -* \version 2.10 -* +* \version 2.10.1 +* * The header file of the I2S driver. * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -25,13 +25,13 @@ /** * \addtogroup group_i2s * \{ -* The I2S driver provides a function API to manage Inter-IC Sound. +* The I2S driver provides a function API to manage Inter-IC Sound. * -* The functions and other declarations used in this driver are in cy_i2s.h. -* You can include cy_pdl.h (ModusToolbox only) to get access to all functions +* The functions and other declarations used in this driver are in cy_i2s.h. +* You can include cy_pdl.h to get access to all functions * and declarations in the PDL. * -* I2S is used to send digital audio streaming data to external I2S devices, +* I2S is used to send digital audio streaming data to external I2S devices, * such as audio codecs or simple DACs. It can also receive digital audio streaming data. * * Features: @@ -40,14 +40,14 @@ * * Programmable Channel/Word Lengths. * * Supports External Clock operation. * -* The I2S bus is an industry standard. The hardware interface was -* developed by Philips Semiconductors (now NXP Semiconductors). +* The I2S bus is an industry standard. The hardware interface was +* developed by Philips Semiconductors (now NXP Semiconductors). * * \section group_i2s_configuration_considerations Configuration Considerations * * To set up an I2S, provide the configuration parameters in the -* \ref cy_stc_i2s_config_t structure. -* +* \ref cy_stc_i2s_config_t structure. +* * For example, for Tx configuration, set txEnabled to true, configure * txDmaTrigger (depending on whether DMA is going to be used or not), set * extClk (if an external clock is used), provide clkDiv, txMasterMode, @@ -71,13 +71,13 @@ * * For example: * \snippet i2s/snippet/main.c snippet_Cy_I2S_Init -* -* If you use a DMA, the DMA channel should be previously configured. The I2S interrupts +* +* If you use a DMA, the DMA channel should be previously configured. The I2S interrupts * (if applicable) can be enabled by calling \ref Cy_I2S_SetInterruptMask. * * For example, if the trigger interrupt is used during operation, the ISR -* should call the \ref Cy_I2S_WriteTxData as many times as required for your -* FIFO payload, but not more than the FIFO size. Then call \ref Cy_I2S_ClearInterrupt +* should call the \ref Cy_I2S_WriteTxData as many times as required for your +* FIFO payload, but not more than the FIFO size. Then call \ref Cy_I2S_ClearInterrupt * with appropriate parameters. * * The I2S/Left Justified data formats always contains two data channels. @@ -87,7 +87,7 @@ * or combined with zeroes: sample1-zero-sample2-zero (in this case only the * left channel will finally sound, for a right-only case, zero should go first). * The TDM frame word order in FIFOs is similar, one-by-one. -* +* * If a DMA is used and the DMA channel is properly configured - no CPU activity * (or any application code) is needed for I2S operation. * @@ -128,8 +128,13 @@ * * * +* +* +* +* +* * -* * @@ -137,7 +142,7 @@ * * -* * * @@ -234,7 +239,7 @@ extern "C" { * \{ */ -/** Transmission is active */ +/** Transmission is active */ #define CY_I2S_TX_START (I2S_CMD_TX_START_Msk) /** Transmission is paused */ #define CY_I2S_TX_PAUSE (I2S_CMD_TX_PAUSE_Msk) @@ -254,7 +259,7 @@ extern "C" { * I2S status definitions. */ -typedef enum +typedef enum { CY_I2S_SUCCESS = 0x00UL, /**< Successful. */ CY_I2S_BAD_PARAM = CY_I2S_ID | CY_PDL_STATUS_ERROR | 0x01UL /**< One or more invalid parameters. */ @@ -333,7 +338,7 @@ typedef struct 'true': SDO bit starts at rising edge which goes before the above mentioned falling edge, i.e. the SDO signal is advanced by 0.5 SCK period (if txSckoInversion is false). - If txSckoInversion is true - the rising/falling edges just swaps + If txSckoInversion is true - the rising/falling edges just swaps in above explanations. Effective only in slave mode, must be false in master mode.*/ bool txSckoInversion; /**< TX SCKO polarity: @@ -373,7 +378,7 @@ typedef struct 'true': SDI bit starts at rising edge that goes after the above mentioned falling edge, i.e. the SDI signal is delayed by 0.5 SCK period (if rxSckoInversion is false). - If rxSckoInversion is true - the rising/falling edges just swaps + If rxSckoInversion is true - the rising/falling edges just swaps in above explanations. Effective only in master mode, must be false in slave mode. */ bool rxSckoInversion; /**< RX SCKO polarity: @@ -399,7 +404,7 @@ typedef struct cy_en_i2s_len_t rxWordLength; /**< RX word length, see #cy_en_i2s_len_t, must be less or equal to rxChannelLength. */ bool rxSignExtension; /**< RX value sign extension (when the word length is less than 32 bits), - 'false': all MSB are filled by zeroes, + 'false': all MSB are filled by zeroes, 'true': all MSB are filled by the original sign bit value. */ uint8_t rxFifoTriggerLevel; /**< RX FIFO interrupt trigger level (0, 1, ..., (255 - (number of channels))). */ @@ -503,7 +508,7 @@ typedef struct cy_en_i2s_status_t Cy_I2S_Init(I2S_Type * base, cy_stc_i2s_config_t const * config); void Cy_I2S_DeInit(I2S_Type * base); - + /** \addtogroup group_i2s_functions_syspm_callback * The driver supports SysPm callback for Deep Sleep transition. * \{ @@ -547,7 +552,7 @@ __STATIC_INLINE uint32_t Cy_I2S_GetInterruptStatusMasked(I2S_Type const * base); * Function Name: Cy_I2S_EnableTx ****************************************************************************//** * -* Starts an I2S transmission. Interrupt enabling (by the +* Starts an I2S transmission. Interrupt enabling (by the * \ref Cy_I2S_SetInterruptMask) is required after this function call, in case * if any I2S interrupts are used in the application. * @@ -605,7 +610,7 @@ __STATIC_INLINE void Cy_I2S_ResumeTx(I2S_Type * base) * Function Name: Cy_I2S_DisableTx ****************************************************************************//** * -* Stops an I2S transmission. +* Stops an I2S transmission. * * \pre TX interrupt disabling (by the \ref Cy_I2S_SetInterruptMask) is required * prior to this function call, in case any TX I2S interrupts are used. @@ -626,7 +631,7 @@ __STATIC_INLINE void Cy_I2S_DisableTx(I2S_Type * base) * Function Name: Cy_I2S_EnableRx ****************************************************************************//** * -* Starts an I2S reception. Interrupt enabling (by the +* Starts an I2S reception. Interrupt enabling (by the * \ref Cy_I2S_SetInterruptMask) is required after this function call, in case * any I2S interrupts are used in the application. * @@ -720,7 +725,7 @@ __STATIC_INLINE void Cy_I2S_ClearTxFifo(I2S_Type * base) * *******************************************************************************/ __STATIC_INLINE uint32_t Cy_I2S_GetNumInTxFifo(I2S_Type const * base) -{ +{ return (_FLD2VAL(I2S_TX_FIFO_STATUS_USED, REG_I2S_TX_FIFO_STATUS(base))); } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_ipc_drv.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_ipc_drv.h index 95d3dc8087..a65ae4427a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_ipc_drv.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_ipc_drv.h @@ -1,12 +1,12 @@ /***************************************************************************//** * \file cy_ipc_drv.h -* \version 1.40 +* \version 1.40.1 * * Provides an API declaration of the IPC driver. * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -34,8 +34,8 @@ * device can acquire and transfer data at a time so no data is lost or * overwritten by asynchronous processes or CPUs. * -* Include either cy_ipc_pipe.h or cy_ipc_sema.h. Alternatively include cy_pdl.h -* (ModusToolbox only) to get access to all functions and declarations in the PDL. +* Include either cy_ipc_pipe.h or cy_ipc_sema.h. Alternatively include cy_pdl.h +* to get access to all functions and declarations in the PDL. * * There are three parts to the API: * - Driver-level (DRV) API - used internally by Semaphore and Pipe levels @@ -81,7 +81,7 @@ * conduit to transfer messages or data to and from multiple processes or CPUs. * * A pipe has two endpoints, one on each core. Each endpoint contains a dedicated -* IPC channel and an interrupt. IPC channels 0-7(8 for the CYB064XX devices) +* IPC channel and an interrupt. IPC channels 0-7(8 for the CYB064XX devices) * and IPC interrupts 0-7 are reserved for system use. * * The pipe also contains the number of clients it supports, and for each client @@ -106,9 +106,9 @@ * required by the application's logic. * * The PDL provides specific files that set up default IPC functionality. -* They are system_psoc6.h, system_psoc6_cm0plus.c and system_psoc6_cm4.c. You -* can modify these files based on the requirements of your design. -* If you use PSoC Creator as a development environment, it will not overwrite +* They are system_psoc6.h, system_psoc6_cm0plus.c and system_psoc6_cm4.c. You +* can modify these files based on the requirements of your design. +* If you use PSoC Creator as a development environment, it will not overwrite * your changes when you generate the application or build your code. * * \section group_ipc_pipe_layer PIPE layer @@ -188,9 +188,9 @@ * * \section group_ipc_configuration_sema Configuration Considerations - SEMA * -* Startup code calls Cy_IPC_Sema_Init() with default values to set up semaphore -* functionality. By default the semaphore system uses IPC channel 4, and -* creates 128 semaphores. Do not change the IPC channel. +* Startup code calls Cy_IPC_Sema_Init() with default values to set up semaphore +* functionality. By default the semaphore system uses IPC channel 4, and +* creates 128 semaphores. Do not change the IPC channel. * You can change the number of semaphores. * * To change the number of semaphores, modify this line of code in system_psoc6.h. @@ -206,8 +206,8 @@ * * \section group_ipc_more_information More Information * -* If the default startup file is not used, or SystemInit() is not called in your -* project, call the following three functions prior to executing any flash or +* If the default startup file is not used, or SystemInit() is not called in your +* project, call the following three functions prior to executing any flash or * EmEEPROM write or erase operation: * -# Cy_IPC_Sema_Init() * -# Cy_IPC_Pipe_Config() @@ -251,6 +251,11 @@ *
VersionChangesReason for Change
2.10.1Minor documentation updates.Documentation enhancement.
2.10Flattened the organization of the driver source code into the single +* Flattened the organization of the driver source code into the single * source directory and the single include directory. * Driver library directory-structure simplification.
Added register access layer. Use register access macros instead * of direct register access using dereferenced pointers.Makes register access device-independent, so that the PDL does +* Makes register access device-independent, so that the PDL does * not need to be recompiled for each supported part number.
* * +* +* +* +* +* * * * @@ -267,7 +272,7 @@ * * -* * * @@ -301,8 +306,8 @@ * \{ * The functions of this layer are used in the higher IPC levels * (Semaphores and Pipes). -* Users are not expected to call any of these IPC functions directly (cy_ipc_drv.h). -* Instead include either of cy_ipc_sema.h or cy_ipc_pipe.h. +* Users are not expected to call any of these IPC functions directly (cy_ipc_drv.h). +* Instead include either of cy_ipc_sema.h or cy_ipc_pipe.h. * Alternatively include cy_pdl.h to get access to all functions and declarations in the PDL. * * \defgroup group_ipc_macros Macros diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_ipc_pipe.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_ipc_pipe.h index a8c9e78680..0d068675af 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_ipc_pipe.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_ipc_pipe.h @@ -1,13 +1,13 @@ /***************************************************************************//** * \file cy_ipc_pipe.h -* \version 1.40 +* \version 1.40.1 * * Description: * IPC Pipe Driver - This header file contains all the function prototypes, * structure definitions, pipe constants, and pipe endpoint address definitions. * ******************************************************************************** -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -38,9 +38,9 @@ * The Pipe functions provide a method to transfer one or more words of data * between CPUs or tasks. * -* Include cy_ipc_pipe.h. Alternatively include cy_pdl.h (ModusToolbox only) +* Include cy_ipc_pipe.h. Alternatively include cy_pdl.h * to get access to all functions and declarations in the PDL. -* +* * The data can be defined as a single 32-bit unsigned * word, an array of data, or a user-defined structure. The only limitation is * that the first word in the array or structure must be a 32-bit unsigned word diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_ipc_sema.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_ipc_sema.h index a221e49977..3bd9c41d29 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_ipc_sema.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_ipc_sema.h @@ -1,13 +1,13 @@ /***************************************************************************//** * \file cy_ipc_sema.h -* \version 1.40 +* \version 1.40.1 * * \brief * Header file for IPC SEM functions * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -38,7 +38,7 @@ * The semaphores layer functions made use of a single IPC channel to allow * multiple semaphores that can be used by system or user function calls. * -* Include cy_ipc_sema.h. Alternatively include cy_pdl.h (ModusToolbox only) +* Include cy_ipc_sema.h. Alternatively include cy_pdl.h * to get access to all functions and declarations in the PDL. * * By default there are 128 semaphores provided, although the user may modify @@ -106,9 +106,9 @@ typedef enum typedef struct { /** Maximum semaphores in system */ - uint32_t maxSema; + uint32_t maxSema; /** Pointer to semaphores array */ - uint32_t *arrayPtr; + uint32_t *arrayPtr; } cy_stc_ipc_sema_t; /** \} group_ipc_sema_enums */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_lpcomp.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_lpcomp.h index ca6805ad68..218c39e441 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_lpcomp.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_lpcomp.h @@ -1,12 +1,12 @@ /***************************************************************************//** * \file cy_lpcomp.h -* \version 1.20 +* \version 1.20.1 * * This file provides constants and parameter values for the Low Power Comparator driver. * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -28,84 +28,84 @@ * Provides access to the low-power comparators implemented using the fixed-function * LP comparator block that is present in PSoC 6. * -* The functions and other declarations used in this driver are in cy_lpcomp.h. -* You can include cy_pdl.h (ModusToolbox only) to get access to all functions -* and declarations in the PDL. +* The functions and other declarations used in this driver are in cy_lpcomp.h. +* You can include cy_pdl.h to get access to all functions +* and declarations in the PDL. * -* These comparators can perform fast analog signal comparison of internal -* and external analog signals in all system power modes. Low-power comparator -* output can be inspected by the CPU, used as an interrupt/wakeup source to the -* CPU when in low-power mode (Sleep, Low-Power Sleep, or Deep-Sleep), used as -* a wakeup source to system resources when in Hibernate mode, or fed to DSI as +* These comparators can perform fast analog signal comparison of internal +* and external analog signals in all system power modes. Low-power comparator +* output can be inspected by the CPU, used as an interrupt/wakeup source to the +* CPU when in low-power mode (Sleep, Low-Power Sleep, or Deep-Sleep), used as +* a wakeup source to system resources when in Hibernate mode, or fed to DSI as * an asynchronous or synchronous signal (level or pulse). * * \section group_lpcomp_section_Configuration_Considerations Configuration Considerations -* To set up an LPComp, the inputs, the output, the mode, the interrupts and +* To set up an LPComp, the inputs, the output, the mode, the interrupts and * other configuration parameters should be configured. Power the LPComp to operate. * * The sequence recommended for the LPComp operation: * -* 1) To initialize the driver, call the Cy_LPComp_Init() function providing -* the filled cy_stc_lpcomp_config_t structure, the LPComp channel number, +* 1) To initialize the driver, call the Cy_LPComp_Init() function providing +* the filled cy_stc_lpcomp_config_t structure, the LPComp channel number, * and the LPCOMP registers structure pointer. * -* 2) Optionally, configure the interrupt requests if the interrupt event -* triggering is needed. Use the Cy_LPComp_SetInterruptMask() function with -* the parameter for the mask available in the configuration file. -* Additionally, enable the Global interrupts and initialize the referenced -* interrupt by setting the priority and the interrupt vector using +* 2) Optionally, configure the interrupt requests if the interrupt event +* triggering is needed. Use the Cy_LPComp_SetInterruptMask() function with +* the parameter for the mask available in the configuration file. +* Additionally, enable the Global interrupts and initialize the referenced +* interrupt by setting the priority and the interrupt vector using * the \ref Cy_SysInt_Init() function of the sysint driver. * -* 3) Configure the inputs and the output using the \ref Cy_GPIO_Pin_Init() -* functions of the GPIO driver. -* The High Impedance Analog drive mode is for the inputs and -* the Strong drive mode is for the output. -* Use the Cy_LPComp_SetInputs() function to connect the comparator inputs +* 3) Configure the inputs and the output using the \ref Cy_GPIO_Pin_Init() +* functions of the GPIO driver. +* The High Impedance Analog drive mode is for the inputs and +* the Strong drive mode is for the output. +* Use the Cy_LPComp_SetInputs() function to connect the comparator inputs * to the dedicated IO pins, AMUXBUSA/AMUXBUSB or Vref: * \image html lpcomp_inputs.png * * 4) Power on the comparator using the Cy_LPComp_Enable() function. * -* 5) The comparator output can be monitored using -* the Cy_LPComp_GetCompare() function or using the LPComp interrupt +* 5) The comparator output can be monitored using +* the Cy_LPComp_GetCompare() function or using the LPComp interrupt * (if the interrupt is enabled). * -* \note The interrupt is not cleared automatically. -* It is the user's responsibility to do that. -* The interrupt is cleared by writing a 1 in the corresponding interrupt -* register bit position. The preferred way to clear interrupt sources +* \note The interrupt is not cleared automatically. +* It is the user's responsibility to do that. +* The interrupt is cleared by writing a 1 in the corresponding interrupt +* register bit position. The preferred way to clear interrupt sources * is using the Cy_LPComp_ClearInterrupt() function. * -* \note Individual comparator interrupt outputs are ORed together -* as a single asynchronous interrupt source before it is sent out and -* used to wake up the system in the low-power mode. -* For PSoC 6 devices, the individual comparator interrupt is masked +* \note Individual comparator interrupt outputs are ORed together +* as a single asynchronous interrupt source before it is sent out and +* used to wake up the system in the low-power mode. +* For PSoC 6 devices, the individual comparator interrupt is masked * by the INTR_MASK register. The masked result is captured in * the INTR_MASKED register. -* Writing a 1 to the INTR register bit will clear the interrupt. +* Writing a 1 to the INTR register bit will clear the interrupt. * * \section group_lpcomp_lp Low Power Support -* The LPComp provides the callback functions to facilitate -* the low-power mode transition. The callback -* \ref Cy_LPComp_DeepSleepCallback must be called during execution -* of \ref Cy_SysPm_CpuEnterDeepSleep; \ref Cy_LPComp_HibernateCallback must be -* called during execution of \ref Cy_SysPm_SystemEnterHibernate. -* To trigger the callback execution, the callback must be registered -* before calling the mode transition function. -* Refer to \ref group_syspm driver for more +* The LPComp provides the callback functions to facilitate +* the low-power mode transition. The callback +* \ref Cy_LPComp_DeepSleepCallback must be called during execution +* of \ref Cy_SysPm_CpuEnterDeepSleep; \ref Cy_LPComp_HibernateCallback must be +* called during execution of \ref Cy_SysPm_SystemEnterHibernate. +* To trigger the callback execution, the callback must be registered +* before calling the mode transition function. +* Refer to \ref group_syspm driver for more * information about low-power mode transitions. * * The example below shows the entering into Hibernate mode. -* The positive LPComp input connects to dedicated GPIO pin and the +* The positive LPComp input connects to dedicated GPIO pin and the * negative LPComp input connects to the local reference. * The LED blinks twice after device reset and goes into Hibernate mode. -* When the voltage on the positive input great than the local reference +* When the voltage on the positive input great than the local reference * voltage (0.45V - 0.75V) the device wakes up and LED begins blinking. * \snippet lpcomp/snippet/main.c LP_COMP_CFG_HIBERNATE * * \section group_lpcomp_more_information More Information * -* Refer to the appropriate device technical reference manual (TRM) for +* Refer to the appropriate device technical reference manual (TRM) for * a detailed description of the registers. * * \section group_lpcomp_MISRA MISRA-C Compliance @@ -123,12 +123,12 @@ * a different pointer to object type. * * *
VersionChangesReason for Change
1.40.1Minor documentation updates.Documentation enhancement.
1.40Moved cy_semaData structure to the RAM section called ".cy_sharedmem".Support Secure Boot devices.
Added register access layer. Use register access macros instead * of direct register access using dereferenced pointers.Makes register access device-independent, so that the PDL does +* Makes register access device-independent, so that the PDL does * not need to be recompiled for each supported part number.
* The pointer to the buffer memory is void to allow handling different -* different data types: uint8_t (4-8 bits) or uint16_t (9-16 bits). -* The cast operation is safe because the configuration is verified +* different data types: uint8_t (4-8 bits) or uint16_t (9-16 bits). +* The cast operation is safe because the configuration is verified * before operation is performed. -* The function \ref Cy_LPComp_DeepSleepCallback is a callback of +* The function \ref Cy_LPComp_DeepSleepCallback is a callback of * the \ref cy_en_syspm_status_t type. The cast operation safety in this -* function becomes the user's responsibility because the pointers are +* function becomes the user's responsibility because the pointers are * initialized when a callback is registered in the SysPm driver.
@@ -137,8 +137,13 @@ * * * +* +* +* +* +* * -* * @@ -146,7 +151,7 @@ * * -* * * @@ -156,7 +161,7 @@ * * * -* * @@ -214,7 +219,7 @@ extern "C" ******************************************************************************/ /**< LPCOMP PDL ID */ -#define CY_LPCOMP_ID CY_PDL_DRV_ID(0x23u) +#define CY_LPCOMP_ID CY_PDL_DRV_ID(0x23u) /** The LPCOMP's number of channels. */ #define CY_LPCOMP_MAX_CHANNEL_NUM (2u) @@ -254,20 +259,20 @@ extern "C" #define CY_LPCOMP_CMP0_OUTPUT_CONFIG_Pos LPCOMP_CMP0_CTRL_DSI_BYPASS0_Pos #define CY_LPCOMP_CMP1_OUTPUT_CONFIG_Pos LPCOMP_CMP1_CTRL_DSI_BYPASS1_Pos - + #define CY_LPCOMP_CMP0_OUTPUT_CONFIG_Msk (LPCOMP_CMP0_CTRL_DSI_BYPASS0_Msk | \ LPCOMP_CMP0_CTRL_DSI_LEVEL0_Msk) - + #define CY_LPCOMP_CMP1_OUTPUT_CONFIG_Msk (LPCOMP_CMP1_CTRL_DSI_BYPASS1_Msk | \ LPCOMP_CMP1_CTRL_DSI_LEVEL1_Msk) #define CY_HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SL_SR_Pos HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SL_Pos - + #define CY_HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SL_SR_Msk (HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SL_Msk | \ - HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SR_Msk) - + HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SR_Msk) + #define CY_HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SL_SR_Pos HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SL_Pos - + #define CY_HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SL_SR_Msk (HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SL_Msk | \ HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SR_Msk) @@ -297,7 +302,7 @@ typedef enum { CY_LPCOMP_OUT_PULSE = 0u, /**< The LPCOMP DSI output with the pulse option, no bypass. */ CY_LPCOMP_OUT_DIRECT = 1u, /**< The LPCOMP bypass mode, the direct output of a comparator. */ - CY_LPCOMP_OUT_SYNC = 2u /**< The LPCOMP DSI output with the level option, it is similar + CY_LPCOMP_OUT_SYNC = 2u /**< The LPCOMP DSI output with the level option, it is similar to the bypass mode but it is 1 cycle slow than the bypass. */ } cy_en_lpcomp_out_t; @@ -343,7 +348,7 @@ typedef enum } cy_en_lpcomp_inputs_t; /** The LPCOMP error codes. */ -typedef enum +typedef enum { CY_LPCOMP_SUCCESS = 0x00u, /**< Successful */ CY_LPCOMP_BAD_PARAM = CY_LPCOMP_ID | CY_PDL_STATUS_ERROR | 0x01u, /**< One or more invalid parameters */ @@ -365,7 +370,7 @@ typedef enum /** The LPCOMP configuration structure. */ typedef struct { - cy_en_lpcomp_out_t outputMode; /**< The LPCOMP's outputMode: Direct output, + cy_en_lpcomp_out_t outputMode; /**< The LPCOMP's outputMode: Direct output, Synchronized output or Pulse output */ cy_en_lpcomp_hyst_t hysteresis; /**< Enables or disables the LPCOMP's hysteresis */ cy_en_lpcomp_pwr_t power; /**< Sets the LPCOMP power mode */ @@ -413,7 +418,7 @@ typedef struct { ((input) == CY_LPCOMP_SW_AMUXBUSA) || \ ((input) == CY_LPCOMP_SW_AMUXBUSB) || \ ((input) == CY_LPCOMP_SW_LOCAL_VREF)) - + /** \endcond */ /** @@ -458,16 +463,16 @@ cy_en_syspm_status_t Cy_LPComp_HibernateCallback(cy_stc_syspm_callback_params_t * Function Name: Cy_LPComp_GlobalEnable ****************************************************************************//** * -* Activates the IP of the LPCOMP hardware block. This API should be enabled +* Activates the IP of the LPCOMP hardware block. This API should be enabled * before operating any channel of comparators. -* Note: Interrupts can be enabled after the block is enabled and the appropriate +* Note: Interrupts can be enabled after the block is enabled and the appropriate * start-up time has elapsed: * 3 us for the normal power mode; * 6 us for the LP mode; * 50 us for the ULP mode. * * \param *base -* The structure of the channel pointer. +* The structure of the channel pointer. * * \return None * @@ -482,7 +487,7 @@ __STATIC_INLINE void Cy_LPComp_GlobalEnable(LPCOMP_Type* base) * Function Name: Cy_LPComp_GlobalDisable ****************************************************************************//** * -* Deactivates the IP of the LPCOMP hardware block. +* Deactivates the IP of the LPCOMP hardware block. * (Analog in power down, open all switches, all clocks off). * * \param *base @@ -501,7 +506,7 @@ __STATIC_INLINE void Cy_LPComp_GlobalDisable(LPCOMP_Type *base) * Function Name: Cy_LPComp_UlpReferenceEnable ****************************************************************************//** * -* Enables the local reference-generator circuit. +* Enables the local reference-generator circuit. * * \param *base * The structure of the channel pointer. @@ -519,7 +524,7 @@ __STATIC_INLINE void Cy_LPComp_UlpReferenceEnable(LPCOMP_Type *base) * Function Name: Cy_LPComp_UlpReferenceDisable ****************************************************************************//** * -* Disables the local reference-generator circuit. +* Disables the local reference-generator circuit. * * \param *base * The structure of the channel pointer. @@ -537,8 +542,8 @@ __STATIC_INLINE void Cy_LPComp_UlpReferenceDisable(LPCOMP_Type *base) * Function Name: Cy_LPComp_GetCompare ****************************************************************************//** * -* This function returns a nonzero value when the voltage connected to the -* positive input is greater than the negative input voltage. +* This function returns a nonzero value when the voltage connected to the +* positive input is greater than the negative input voltage. * * \param *base * The LPComp register structure pointer. @@ -554,7 +559,7 @@ __STATIC_INLINE void Cy_LPComp_UlpReferenceDisable(LPCOMP_Type *base) __STATIC_INLINE uint32_t Cy_LPComp_GetCompare(LPCOMP_Type const * base, cy_en_lpcomp_channel_t channel) { uint32_t result; - + CY_ASSERT_L3(CY_LPCOMP_IS_CHANNEL_VALID(channel)); if (CY_LPCOMP_CHANNEL_0 == channel) @@ -565,7 +570,7 @@ __STATIC_INLINE uint32_t Cy_LPComp_GetCompare(LPCOMP_Type const * base, cy_en_lp { result = _FLD2VAL(LPCOMP_STATUS_OUT1, LPCOMP_STATUS(base)); } - + return (result); } @@ -574,15 +579,15 @@ __STATIC_INLINE uint32_t Cy_LPComp_GetCompare(LPCOMP_Type const * base, cy_en_lp * Function Name: Cy_LPComp_SetInterruptMask ****************************************************************************//** * -* Configures which bits of the interrupt request register will trigger an +* Configures which bits of the interrupt request register will trigger an * interrupt event. * * \param *base * The LPCOMP register structure pointer. * * \param interrupt -* uint32_t interruptMask: Bit Mask of interrupts to set. -* Bit 0: COMP0 Interrupt Mask +* uint32_t interruptMask: Bit Mask of interrupts to set. +* Bit 0: COMP0 Interrupt Mask * Bit 1: COMP1 Interrupt Mask * * \return None @@ -620,8 +625,8 @@ __STATIC_INLINE uint32_t Cy_LPComp_GetInterruptMask(LPCOMP_Type const * base) * Function Name: Cy_LPComp_GetInterruptStatusMasked ****************************************************************************//** * -* Returns an interrupt request register masked by an interrupt mask. -* Returns the result of the bitwise AND operation between the corresponding +* Returns an interrupt request register masked by an interrupt mask. +* Returns the result of the bitwise AND operation between the corresponding * interrupt request and mask bits. * * \param *base @@ -647,8 +652,8 @@ __STATIC_INLINE uint32_t Cy_LPComp_GetInterruptStatusMasked(LPCOMP_Type const * * \param *base * The LPCOMP register structure pointer. * -* \return bit mapping information -* Bit 0: COMP0 Interrupt status +* \return bit mapping information +* Bit 0: COMP0 Interrupt status * Bit 1: COMP1 Interrupt status * *******************************************************************************/ @@ -662,13 +667,13 @@ __STATIC_INLINE uint32_t Cy_LPComp_GetInterruptStatus(LPCOMP_Type const * base) * Function Name: Cy_LPComp_ClearInterrupt ****************************************************************************//** * -* Clears LPCOMP interrupts by setting each bit. +* Clears LPCOMP interrupts by setting each bit. * * \param *base * The LPCOMP register structure pointer. * * \param interrupt -* Bit 0: COMP0 Interrupt status +* Bit 0: COMP0 Interrupt status * Bit 1: COMP1 Interrupt status * * \return None @@ -686,16 +691,16 @@ __STATIC_INLINE void Cy_LPComp_ClearInterrupt(LPCOMP_Type* base, uint32_t interr * Function Name: Cy_LPComp_SetInterrupt ****************************************************************************//** * -* Sets a software interrupt request. +* Sets a software interrupt request. * This function is used in the case of combined interrupt signal from the global -* signal reference. This function from either component instance can be used +* signal reference. This function from either component instance can be used * to trigger either or both software interrupts. It sets the INTR_SET interrupt mask. * * \param *base * The LPCOMP register structure pointer. * * \param interrupt -* Bit 0: COMP0 Interrupt status +* Bit 0: COMP0 Interrupt status * Bit 1: COMP1 Interrupt status * * \return None @@ -726,7 +731,7 @@ __STATIC_INLINE void Cy_LPComp_SetInterrupt(LPCOMP_Type* base, uint32_t interrup __STATIC_INLINE void Cy_LPComp_ConnectULPReference(LPCOMP_Type *base, cy_en_lpcomp_channel_t channel) { CY_ASSERT_L3(CY_LPCOMP_IS_CHANNEL_VALID(channel)); - + if (CY_LPCOMP_CHANNEL_0 == channel) { LPCOMP_CMP0_SW_CLEAR(base) = CY_LPCOMP_CMP0_SW_NEG_Msk; diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_lvd.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_lvd.h index 6d5fdacfa4..222faf49e5 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_lvd.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_lvd.h @@ -1,12 +1,12 @@ /***************************************************************************//** * \file cy_lvd.h -* \version 1.10 -* +* \version 1.20 +* * The header file of the LVD driver. * ******************************************************************************** * \copyright -* Copyright 2017-2019 Cypress Semiconductor Corporation +* Copyright 2017-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -27,22 +27,22 @@ * \{ * The LVD driver provides an API to manage the Low Voltage Detection block. * -* The functions and other declarations used in this driver are in cy_lvd.h. -* You can include cy_pdl.h (ModusToolbox only) to get access to all functions -* and declarations in the PDL. -* -* The LVD block provides a status of currently observed VDDD voltage +* The functions and other declarations used in this driver are in cy_lvd.h. +* You can include cy_pdl.h to get access to all functions +* and declarations in the PDL. +* +* The LVD block provides a status of currently observed VDDD voltage * and triggers an interrupt when the observed voltage crosses an adjusted * threshold. * * \section group_lvd_configuration_considerations Configuration Considerations -* To set up an LVD, configure the voltage threshold by the -* \ref Cy_LVD_SetThreshold function, ensure that the LVD block itself and LVD -* interrupt are disabled (by the \ref Cy_LVD_Disable and +* To set up an LVD, configure the voltage threshold by the +* \ref Cy_LVD_SetThreshold function, ensure that the LVD block itself and LVD +* interrupt are disabled (by the \ref Cy_LVD_Disable and * \ref Cy_LVD_ClearInterruptMask functions correspondingly) before changing the -* threshold to prevent propagating a false interrupt. +* threshold to prevent propagating a false interrupt. * Then configure interrupts by the \ref Cy_LVD_SetInterruptConfig function, do -* not forget to initialize an interrupt handler (the interrupt source number +* not forget to initialize an interrupt handler (the interrupt source number * is srss_interrupt_IRQn). * Then enable LVD by the \ref Cy_LVD_Enable function, then wait for at least 20us * to get the circuit stabilized and clear the possible false interrupts by the @@ -52,7 +52,7 @@ * For example: * \snippet lvd/snippet/main.c Cy_LVD_Snippet * -* Note that the LVD circuit is available only in Low Power and Ultra Low Power +* Note that the LVD circuit is available only in Low Power and Ultra Low Power * modes. If an LVD is required in Deep Sleep mode, then the device * should be configured to periodically wake up from Deep Sleep using a * Deep Sleep wakeup source. This makes sure a LVD check is performed during @@ -83,14 +83,14 @@ * * -* * *
VersionChangesReason for Change
1.20.1Minor documentation updates.Documentation enhancement.
1.20Flattened the organization of the driver source code into the single +* Flattened the organization of the driver source code into the single * source directory and the single include directory. * Driver library directory-structure simplification.
Added register access layer. Use register access macros instead * of direct register access using dereferenced pointers.Makes register access device-independent, so that the PDL does +* Makes register access device-independent, so that the PDL does * not need to be recompiled for each supported part number.
1.10The CY_WEAK keyword is removed from Cy_LPComp_DeepSleepCallback() +* The CY_WEAK keyword is removed from Cy_LPComp_DeepSleepCallback() * and Cy_LPComp_HibernateCallback() functions
* Added input parameter validation to the API functions.		AThe object addressed by the pointer parameter '%s' is not modified and * so the pointer could be of type 'pointer to const'.The pointer parameter is not used or modified, as there is no need -* to do any actions with it. However, such parameter is -* required to be presented in the function, because the -* \ref Cy_LVD_DeepSleepCallback is a callback +* The pointer parameter is not used or modified, as there is no need +* to do any actions with it. However, such parameter is +* required to be presented in the function, because the +* \ref Cy_LVD_DeepSleepCallback is a callback * of \ref cy_en_syspm_status_t type. -* The SysPM driver callback function type requires implementing the +* The SysPM driver callback function type requires implementing the * function with the next parameters and return value:
-* cy_en_syspm_status_t (*Cy_SysPmCallback) +* cy_en_syspm_status_t (*Cy_SysPmCallback) * (cy_stc_syspm_callback_params_t *callbackParams);
@@ -99,8 +99,19 @@ * * * +* +* +* +* +* * -* * @@ -108,7 +119,7 @@ * * -* * * @@ -134,7 +145,8 @@ #if !defined CY_LVD_H #define CY_LVD_H - + +#include "cy_pra.h" #include "cy_syspm.h" #include "cy_device.h" @@ -150,13 +162,13 @@ extern "C" { #define CY_LVD_DRV_VERSION_MAJOR 1 /** The driver minor version */ -#define CY_LVD_DRV_VERSION_MINOR 10 +#define CY_LVD_DRV_VERSION_MINOR 20 /** The LVD driver identifier */ #define CY_LVD_ID (CY_PDL_DRV_ID(0x39U)) /** Interrupt mask for \ref Cy_LVD_GetInterruptStatus(), - \ref Cy_LVD_GetInterruptMask() and + \ref Cy_LVD_GetInterruptMask() and \ref Cy_LVD_GetInterruptStatusMasked() */ #define CY_LVD_INTR (SRSS_SRSS_INTR_HVLVD1_Msk) @@ -231,7 +243,7 @@ typedef enum ((threshold) == CY_LVD_THRESHOLD_2_9_V) || \ ((threshold) == CY_LVD_THRESHOLD_3_0_V) || \ ((threshold) == CY_LVD_THRESHOLD_3_1_V)) - + #define CY_LVD_CHECK_INTR_CFG(intrCfg) (((intrCfg) == CY_LVD_INTR_DISABLE) || \ ((intrCfg) == CY_LVD_INTR_RISING) || \ ((intrCfg) == CY_LVD_INTR_FALLING) || \ @@ -266,14 +278,18 @@ cy_en_syspm_status_t Cy_LVD_DeepSleepCallback(cy_stc_syspm_callback_params_t * c * Function Name: Cy_LVD_Enable ****************************************************************************//** * -* Enables the output of the LVD block when the VDDD voltage is +* Enables the output of the LVD block when the VDDD voltage is * at or below the threshold. * See the Configuration Considerations section for details. * *******************************************************************************/ __STATIC_INLINE void Cy_LVD_Enable(void) { - SRSS_PWR_LVD_CTL |= SRSS_PWR_LVD_CTL_HVLVD1_EN_Msk; + #if CY_CPU_CORTEX_M4 && defined(CY_DEVICE_SECURE) + CY_PRA_REG32_CLR_SET(CY_PRA_INDX_SRSS_PWR_LVD_CTL, SRSS_PWR_LVD_CTL_HVLVD1_EN, 1U); + #else + SRSS_PWR_LVD_CTL |= SRSS_PWR_LVD_CTL_HVLVD1_EN_Msk; + #endif } @@ -286,7 +302,11 @@ __STATIC_INLINE void Cy_LVD_Enable(void) *******************************************************************************/ __STATIC_INLINE void Cy_LVD_Disable(void) { - SRSS_PWR_LVD_CTL &= (uint32_t) ~SRSS_PWR_LVD_CTL_HVLVD1_EN_Msk; + #if CY_CPU_CORTEX_M4 && defined(CY_DEVICE_SECURE) + CY_PRA_REG32_CLR_SET(CY_PRA_INDX_SRSS_PWR_LVD_CTL, SRSS_PWR_LVD_CTL_HVLVD1_EN, 0U); + #else + SRSS_PWR_LVD_CTL &= (uint32_t) ~SRSS_PWR_LVD_CTL_HVLVD1_EN_Msk; + #endif } @@ -295,19 +315,24 @@ __STATIC_INLINE void Cy_LVD_Disable(void) ****************************************************************************//** * * Sets a threshold for monitoring the VDDD voltage. -* To prevent propagating a false interrupt, before changing the threshold -* ensure that the LVD block itself and LVD interrupt are disabled by the -* \ref Cy_LVD_Disable and \ref Cy_LVD_ClearInterruptMask functions +* To prevent propagating a false interrupt, before changing the threshold +* ensure that the LVD block itself and LVD interrupt are disabled by the +* \ref Cy_LVD_Disable and \ref Cy_LVD_ClearInterruptMask functions * correspondingly. * -* \param threshold +* \param threshold * Threshold selection for Low Voltage Detect circuit, \ref cy_en_lvd_tripsel_t. * *******************************************************************************/ __STATIC_INLINE void Cy_LVD_SetThreshold(cy_en_lvd_tripsel_t threshold) { CY_ASSERT_L3(CY_LVD_CHECK_TRIPSEL(threshold)); - SRSS_PWR_LVD_CTL = _CLR_SET_FLD32U(SRSS_PWR_LVD_CTL, SRSS_PWR_LVD_CTL_HVLVD1_TRIPSEL, threshold); + + #if CY_CPU_CORTEX_M4 && defined(CY_DEVICE_SECURE) + CY_PRA_REG32_CLR_SET(CY_PRA_INDX_SRSS_PWR_LVD_CTL, SRSS_PWR_LVD_CTL_HVLVD1_TRIPSEL, threshold); + #else + SRSS_PWR_LVD_CTL = _CLR_SET_FLD32U(SRSS_PWR_LVD_CTL, SRSS_PWR_LVD_CTL_HVLVD1_TRIPSEL, threshold); + #endif } @@ -317,9 +342,9 @@ __STATIC_INLINE void Cy_LVD_SetThreshold(cy_en_lvd_tripsel_t threshold) * * Returns the status of LVD. * SRSS LVD Status Register (PWR_LVD_STATUS). -* +* * \return LVD status, \ref cy_en_lvd_status_t. -* +* *******************************************************************************/ __STATIC_INLINE cy_en_lvd_status_t Cy_LVD_GetStatus(void) { @@ -331,11 +356,11 @@ __STATIC_INLINE cy_en_lvd_status_t Cy_LVD_GetStatus(void) * Function Name: Cy_LVD_GetInterruptStatus ****************************************************************************//** * -* Returns the status of LVD interrupt. +* Returns the status of LVD interrupt. * SRSS Interrupt Register (SRSS_INTR). -* +* * \return SRSS Interrupt status, \ref CY_LVD_INTR. -* +* *******************************************************************************/ __STATIC_INLINE uint32_t Cy_LVD_GetInterruptStatus(void) { @@ -347,13 +372,18 @@ __STATIC_INLINE uint32_t Cy_LVD_GetInterruptStatus(void) * Function Name: Cy_LVD_ClearInterrupt ****************************************************************************//** * -* Clears LVD interrupt. +* Clears LVD interrupt. * SRSS Interrupt Register (SRSS_INTR). * *******************************************************************************/ __STATIC_INLINE void Cy_LVD_ClearInterrupt(void) { - SRSS_SRSS_INTR = SRSS_SRSS_INTR_HVLVD1_Msk; + #if CY_CPU_CORTEX_M4 && defined(CY_DEVICE_SECURE) + CY_PRA_REG32_SET(CY_PRA_INDX_SRSS_SRSS_INTR, SRSS_SRSS_INTR_HVLVD1_Msk); + #else + SRSS_SRSS_INTR = SRSS_SRSS_INTR_HVLVD1_Msk; + #endif + (void) SRSS_SRSS_INTR; } @@ -364,11 +394,15 @@ __STATIC_INLINE void Cy_LVD_ClearInterrupt(void) * * Triggers the device to generate interrupt for LVD. * SRSS Interrupt Set Register (SRSS_INTR_SET). -* +* *******************************************************************************/ __STATIC_INLINE void Cy_LVD_SetInterrupt(void) { - SRSS_SRSS_INTR_SET = SRSS_SRSS_INTR_SET_HVLVD1_Msk; + #if CY_CPU_CORTEX_M4 && defined(CY_DEVICE_SECURE) + CY_PRA_REG32_SET(CY_PRA_INDX_SRSS_SRSS_INTR_SET, SRSS_SRSS_INTR_SET_HVLVD1_Msk); + #else + SRSS_SRSS_INTR_SET = SRSS_SRSS_INTR_SET_HVLVD1_Msk; + #endif } @@ -383,7 +417,7 @@ __STATIC_INLINE void Cy_LVD_SetInterrupt(void) * *******************************************************************************/ __STATIC_INLINE uint32_t Cy_LVD_GetInterruptMask(void) -{ +{ return (SRSS_SRSS_INTR_MASK & SRSS_SRSS_INTR_MASK_HVLVD1_Msk); } @@ -392,13 +426,17 @@ __STATIC_INLINE uint32_t Cy_LVD_GetInterruptMask(void) * Function Name: Cy_LVD_SetInterruptMask ****************************************************************************//** * -* Enables LVD interrupts. +* Enables LVD interrupts. * Sets the LVD interrupt mask in the SRSS_INTR_MASK register. * *******************************************************************************/ __STATIC_INLINE void Cy_LVD_SetInterruptMask(void) { - SRSS_SRSS_INTR_MASK |= SRSS_SRSS_INTR_MASK_HVLVD1_Msk; + #if CY_CPU_CORTEX_M4 && defined(CY_DEVICE_SECURE) + CY_PRA_REG32_CLR_SET(CY_PRA_INDX_SRSS_SRSS_INTR_MASK, SRSS_SRSS_INTR_SET_HVLVD1, 1U); + #else + SRSS_SRSS_INTR_MASK |= SRSS_SRSS_INTR_MASK_HVLVD1_Msk; + #endif } @@ -406,13 +444,17 @@ __STATIC_INLINE void Cy_LVD_SetInterruptMask(void) * Function Name: Cy_LVD_ClearInterruptMask ****************************************************************************//** * -* Disables LVD interrupts. +* Disables LVD interrupts. * Clears the LVD interrupt mask in the SRSS_INTR_MASK register. * *******************************************************************************/ __STATIC_INLINE void Cy_LVD_ClearInterruptMask(void) { - SRSS_SRSS_INTR_MASK &= (uint32_t) ~SRSS_SRSS_INTR_MASK_HVLVD1_Msk; + #if CY_CPU_CORTEX_M4 && defined(CY_DEVICE_SECURE) + CY_PRA_REG32_CLR_SET(CY_PRA_INDX_SRSS_SRSS_INTR_MASK, SRSS_SRSS_INTR_MASK_HVLVD1, 0U); + #else + SRSS_SRSS_INTR_MASK &= (uint32_t) ~SRSS_SRSS_INTR_MASK_HVLVD1_Msk; + #endif } @@ -420,12 +462,12 @@ __STATIC_INLINE void Cy_LVD_ClearInterruptMask(void) * Function Name: Cy_LVD_GetInterruptStatusMasked ****************************************************************************//** * -* Returns the masked interrupt status which is a bitwise AND between the +* Returns the masked interrupt status which is a bitwise AND between the * interrupt status and interrupt mask registers. * SRSS Interrupt Masked Register (SRSS_INTR_MASKED). -* +* * \return SRSS Interrupt Masked value, \ref CY_LVD_INTR. -* +* *******************************************************************************/ __STATIC_INLINE uint32_t Cy_LVD_GetInterruptStatusMasked(void) { @@ -437,16 +479,21 @@ __STATIC_INLINE uint32_t Cy_LVD_GetInterruptStatusMasked(void) * Function Name: Cy_LVD_SetInterruptConfig ****************************************************************************//** * -* Sets a configuration for LVD interrupt. +* Sets a configuration for LVD interrupt. * SRSS Interrupt Configuration Register (SRSS_INTR_CFG). -* +* * \param lvdInterruptConfig \ref cy_en_lvd_intr_config_t. * *******************************************************************************/ __STATIC_INLINE void Cy_LVD_SetInterruptConfig(cy_en_lvd_intr_config_t lvdInterruptConfig) { CY_ASSERT_L3(CY_LVD_CHECK_INTR_CFG(lvdInterruptConfig)); - SRSS_SRSS_INTR_CFG = _CLR_SET_FLD32U(SRSS_SRSS_INTR_CFG, SRSS_SRSS_INTR_CFG_HVLVD1_EDGE_SEL, lvdInterruptConfig); + + #if CY_CPU_CORTEX_M4 && defined(CY_DEVICE_SECURE) + CY_PRA_REG32_CLR_SET(CY_PRA_INDX_SRSS_SRSS_INTR_CFG, SRSS_SRSS_INTR_CFG_HVLVD1_EDGE_SEL, lvdInterruptConfig); + #else + SRSS_SRSS_INTR_CFG = _CLR_SET_FLD32U(SRSS_SRSS_INTR_CFG, SRSS_SRSS_INTR_CFG_HVLVD1_EDGE_SEL, lvdInterruptConfig); + #endif } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_mcwdt.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_mcwdt.h index e6023c613e..c8f1a690e8 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_mcwdt.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_mcwdt.h @@ -1,12 +1,12 @@ /***************************************************************************//** * \file cy_mcwdt.h -* \version 1.30 +* \version 1.30.1 * * Provides an API declaration of the Cypress PDL 3.0 MCWDT driver * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -27,10 +27,10 @@ * \{ * A MCWDT has two 16-bit counters and one 32-bit counter. * -* The functions and other declarations used in this driver are in cy_mcwdt.h. -* You can include cy_pdl.h (ModusToolbox only) to get access to all functions -* and declarations in the PDL. -* +* The functions and other declarations used in this driver are in cy_mcwdt.h. +* You can include cy_pdl.h to get access to all functions +* and declarations in the PDL. +* * You can use this driver to create a free-running * timer or generate periodic interrupts. The driver also * includes support for the watchdog function to recover from CPU or @@ -47,45 +47,45 @@ * * An additional use case is to implement a watchdog used for recovering from a CPU or * firmware failure. -* +* * \section group_mcwdt_configuration Configuration Considerations * -* Each MCWDT may be configured for a particular product. -* One MCWDT block can be associated with only one CPU during runtime. -* A single MCWDT is not intended to be used by multiple CPUs simultaneously. -* Each block contains three sub-counters, each of which can be configured for -* various system utility functions - free running counter, periodic interrupts, +* Each MCWDT may be configured for a particular product. +* One MCWDT block can be associated with only one CPU during runtime. +* A single MCWDT is not intended to be used by multiple CPUs simultaneously. +* Each block contains three sub-counters, each of which can be configured for +* various system utility functions - free running counter, periodic interrupts, * watchdog reset, or three interrupts followed by a watchdog reset. -* All counters are clocked by either LFCLK (nominal 32 kHz) or by a cascaded +* All counters are clocked by either LFCLK (nominal 32 kHz) or by a cascaded * counter. * A simplified diagram of the MCWDT hardware is shown below: * \image html mcwdt.png -* The frequency of the periodic interrupts can be configured using the Match -* value with combining Clear on match option, which can be set individually -* for each counter using Cy_MCWDT_SetClearOnMatch(). When the Clear on match option -* is not set, the periodic interrupts of the C0 and C1 16-bit sub-counters occur -* after 65535 counts and the match value defines the shift between interrupts -* (see the figure below). The enabled Clear on match option +* The frequency of the periodic interrupts can be configured using the Match +* value with combining Clear on match option, which can be set individually +* for each counter using Cy_MCWDT_SetClearOnMatch(). When the Clear on match option +* is not set, the periodic interrupts of the C0 and C1 16-bit sub-counters occur +* after 65535 counts and the match value defines the shift between interrupts +* (see the figure below). The enabled Clear on match option * resets the counter when the interrupt occurs. * \image html mcwdt_counters.png -* 32-bit sub-counter C2 does not have Clear on match option. -* The interrupt of counter C2 occurs when the counts equal +* 32-bit sub-counter C2 does not have Clear on match option. +* The interrupt of counter C2 occurs when the counts equal * 2Toggle bit value. * \image html mcwdt_subcounters.png -* To set up an MCWDT, provide the configuration parameters in the -* cy_stc_mcwdt_config_t structure. Then call -* Cy_MCWDT_Init() to initialize the driver. +* To set up an MCWDT, provide the configuration parameters in the +* cy_stc_mcwdt_config_t structure. Then call +* Cy_MCWDT_Init() to initialize the driver. * Call Cy_MCWDT_Enable() to enable all specified counters. * * You can also set the mode of operation for any counter. If you choose -* interrupt mode, use Cy_MCWDT_SetInterruptMask() with the -* parameter for the masks described in Macro Section. All counter interrupts +* interrupt mode, use Cy_MCWDT_SetInterruptMask() with the +* parameter for the masks described in Macro Section. All counter interrupts * are OR'd together to from a single combined MCWDT interrupt. -* Additionally, enable the Global interrupts and initialize the referenced -* interrupt by setting the priority and the interrupt vector using +* Additionally, enable the Global interrupts and initialize the referenced +* interrupt by setting the priority and the interrupt vector using * \ref Cy_SysInt_Init() of the sysint driver. -* -* The values of the MCWDT counters can be monitored using +* +* The values of the MCWDT counters can be monitored using * Cy_MCWDT_GetCount(). * * \note In addition to the MCWDTs, each device has a separate watchdog timer @@ -95,7 +95,7 @@ * * \section group_mcwdt_more_information More Information * -* For more information on the MCWDT peripheral, refer to +* For more information on the MCWDT peripheral, refer to * the technical reference manual (TRM). * * \section group_mcwdt_MISRA MISRA-C Compliance @@ -105,8 +105,13 @@ *
VersionChangesReason of Change
1.20 + Updated the following functions for the PSoC 64 devices: + \ref Cy_LVD_Enable, \ref Cy_LVD_Disable, \ref Cy_LVD_SetThreshold, + \ref Cy_LVD_ClearInterrupt, \ref Cy_LVD_SetInterrupt, + \ref Cy_LVD_SetInterruptMask, \ref Cy_LVD_ClearInterruptMask, and + \ref Cy_LVD_SetInterruptConfig. + Added PSoC 64 device support.
1.10Flattened the organization of the driver source code into the single +* Flattened the organization of the driver source code into the single * source directory and the single include directory. * Driver library directory-structure simplification.
Added register access layer. Use register access macros instead * of direct register access using dereferenced pointers.Makes register access device-independent, so that the PDL does +* Makes register access device-independent, so that the PDL does * not need to be recompiled for each supported part number.
* * +* +* +* +* +* * -* @@ -115,7 +120,7 @@ * * * -* * @@ -123,7 +128,7 @@ * * -* * * @@ -173,19 +178,19 @@ extern "C" { /** The MCWDT component configuration structure. */ typedef struct { - uint16_t c0Match; /**< The sub-counter#0 match comparison value, for interrupt or watchdog timeout. - Range: 0 - 65535 for c0ClearOnMatch = 0 and 1 - 65535 for + uint16_t c0Match; /**< The sub-counter#0 match comparison value, for interrupt or watchdog timeout. + Range: 0 - 65535 for c0ClearOnMatch = 0 and 1 - 65535 for c0ClearOnMatch = 1. */ uint16_t c1Match; /**< The sub-counter#1 match comparison value, for interrupt or watchdog timeout. - Range: 0 - 65535 for c1ClearOnMatch = 0 and 1 - 65535 for + Range: 0 - 65535 for c1ClearOnMatch = 0 and 1 - 65535 for c1ClearOnMatch = 1. */ - uint8_t c0Mode; /**< The sub-counter#0 mode. It can have the following values: \ref CY_MCWDT_MODE_NONE, + uint8_t c0Mode; /**< The sub-counter#0 mode. It can have the following values: \ref CY_MCWDT_MODE_NONE, \ref CY_MCWDT_MODE_INT, \ref CY_MCWDT_MODE_RESET and \ref CY_MCWDT_MODE_INT_RESET. */ - uint8_t c1Mode; /**< The sub-counter#1 mode. It can have the following values: \ref CY_MCWDT_MODE_NONE, + uint8_t c1Mode; /**< The sub-counter#1 mode. It can have the following values: \ref CY_MCWDT_MODE_NONE, \ref CY_MCWDT_MODE_INT, \ref CY_MCWDT_MODE_RESET and \ref CY_MCWDT_MODE_INT_RESET. */ - uint8_t c2ToggleBit; /**< The sub-counter#2 Period / Toggle Bit value. + uint8_t c2ToggleBit; /**< The sub-counter#2 Period / Toggle Bit value. Range: 0 - 31. */ - uint8_t c2Mode; /**< The sub-counter#2 mode. It can have the following values: \ref CY_MCWDT_MODE_NONE + uint8_t c2Mode; /**< The sub-counter#2 mode. It can have the following values: \ref CY_MCWDT_MODE_NONE and \ref CY_MCWDT_MODE_INT. */ bool c0ClearOnMatch; /**< The sub-counter#0 Clear On Match parameter enabled/disabled. */ bool c1ClearOnMatch; /**< The sub-counter#1 Clear On Match parameter enabled/disabled. */ @@ -227,7 +232,7 @@ typedef struct #define CY_MCWDT_ALL_WDT_ENABLE_Msk (MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLE0_Msk | MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLE1_Msk | \ MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLE2_Msk) - + #define CY_MCWDT_CTR0_Pos (0u) #define CY_MCWDT_CTR1_Pos (1u) #define CY_MCWDT_CTR2_Pos (2u) @@ -237,16 +242,16 @@ typedef struct #define CY_MCWDT_ID CY_PDL_DRV_ID(0x35u) /**< MCWDT PDL ID */ -#define CY_MCWDT_CTR0 (1UL << CY_MCWDT_CTR0_Pos) /**< The sub-counter#0 mask. This macro is used with functions +#define CY_MCWDT_CTR0 (1UL << CY_MCWDT_CTR0_Pos) /**< The sub-counter#0 mask. This macro is used with functions that handle multiple counters, including Cy_MCWDT_Enable(), Cy_MCWDT_Disable(), Cy_MCWDT_ClearInterrupt() and Cy_MCWDT_ResetCounters(). */ -#define CY_MCWDT_CTR1 (1UL << CY_MCWDT_CTR1_Pos) /**< The sub-counter#1 mask. This macro is used with functions +#define CY_MCWDT_CTR1 (1UL << CY_MCWDT_CTR1_Pos) /**< The sub-counter#1 mask. This macro is used with functions that handle multiple counters, including Cy_MCWDT_Enable(), Cy_MCWDT_Disable(), Cy_MCWDT_ClearInterrupt() and Cy_MCWDT_ResetCounters(). */ -#define CY_MCWDT_CTR2 (1UL << CY_MCWDT_CTR2_Pos) /**< The sub-counter#2 mask. This macro is used with functions +#define CY_MCWDT_CTR2 (1UL << CY_MCWDT_CTR2_Pos) /**< The sub-counter#2 mask. This macro is used with functions that handle multiple counters, including Cy_MCWDT_Enable(), Cy_MCWDT_Disable(), Cy_MCWDT_ClearInterrupt() and Cy_MCWDT_ResetCounters(). */ -#define CY_MCWDT_CTR_Msk (CY_MCWDT_CTR0 | CY_MCWDT_CTR1 | CY_MCWDT_CTR2) /**< The mask for all sub-counters. This macro is used with functions +#define CY_MCWDT_CTR_Msk (CY_MCWDT_CTR0 | CY_MCWDT_CTR1 | CY_MCWDT_CTR2) /**< The mask for all sub-counters. This macro is used with functions that handle multiple counters, including Cy_MCWDT_Enable(), Cy_MCWDT_Disable(), Cy_MCWDT_ClearInterrupt() and Cy_MCWDT_ResetCounters(). */ @@ -272,7 +277,7 @@ typedef enum CY_MCWDT_MODE_NONE, /**< The No action mode. It is used for Set/GetMode functions. */ CY_MCWDT_MODE_INT, /**< The Interrupt mode. It is used for Set/GetMode functions. */ CY_MCWDT_MODE_RESET, /**< The Reset mode. It is used for Set/GetMode functions. */ - CY_MCWDT_MODE_INT_RESET /**< The Three interrupts then watchdog reset mode. It is used for + CY_MCWDT_MODE_INT_RESET /**< The Three interrupts then watchdog reset mode. It is used for Set/GetMode functions. */ } cy_en_mcwdtmode_t; @@ -280,17 +285,17 @@ typedef enum typedef enum { CY_MCWDT_CASCADE_NONE, /**< The cascading is disabled. It is used for Set/GetCascade functions. */ - CY_MCWDT_CASCADE_C0C1, /**< The sub-counter#1 is clocked by LFCLK or from sub-counter#0 cascade. + CY_MCWDT_CASCADE_C0C1, /**< The sub-counter#1 is clocked by LFCLK or from sub-counter#0 cascade. It is used for Set/GetCascade functions. */ CY_MCWDT_CASCADE_C1C2, /**< The sub-counter#2 is clocked by LFCLK or from sub-counter#1 cascade. It is used for Set/GetCascade functions. */ - CY_MCWDT_CASCADE_BOTH /**< The sub-counter#1 is clocked by LFCLK or from sub-counter#0 cascade - and the sub-counter#2 is clocked by LFCLK or from sub-counter#1 cascade. + CY_MCWDT_CASCADE_BOTH /**< The sub-counter#1 is clocked by LFCLK or from sub-counter#0 cascade + and the sub-counter#2 is clocked by LFCLK or from sub-counter#1 cascade. It is used for Set/GetCascade functions. */ } cy_en_mcwdtcascade_t; /** The MCWDT error codes. */ -typedef enum +typedef enum { CY_MCWDT_SUCCESS = 0x00u, /**< Successful */ CY_MCWDT_BAD_PARAM = CY_MCWDT_ID | CY_PDL_STATUS_ERROR | 0x01u, /**< One or more invalid parameters */ @@ -301,9 +306,9 @@ typedef enum /** \cond PARAM_CHECK_MACROS */ -/** Parameter check macros */ -#define CY_MCWDT_IS_CNTS_MASK_VALID(counters) (0U == ((counters) & (uint32_t)~CY_MCWDT_CTR_Msk)) - +/** Parameter check macros */ +#define CY_MCWDT_IS_CNTS_MASK_VALID(counters) (0U == ((counters) & (uint32_t)~CY_MCWDT_CTR_Msk)) + #define CY_MCWDT_IS_CNT_NUM_VALID(counter) ((CY_MCWDT_COUNTER0 == (counter)) || \ (CY_MCWDT_COUNTER1 == (counter)) || \ (CY_MCWDT_COUNTER2 == (counter))) @@ -320,12 +325,12 @@ typedef enum (CY_MCWDT_CASCADE_C0C1 == (cascade)) || \ (CY_MCWDT_CASCADE_C1C2 == (cascade)) || \ (CY_MCWDT_CASCADE_BOTH == (cascade))) - + #define CY_MCWDT_IS_MATCH_VALID(clearOnMatch, match) ((clearOnMatch) ? (1UL <= (match)) : true) -#define CY_MCWDT_IS_BIT_VALID(bit) (31UL >= (bit)) +#define CY_MCWDT_IS_BIT_VALID(bit) (31UL >= (bit)) + - /** \endcond */ @@ -380,13 +385,13 @@ uint32_t Cy_MCWDT_GetCountCascaded(MCWDT_STRUCT_Type const *base); * CY_MCWDT_CTR2 macros. * * \param waitUs -* The function waits for some delay in microseconds before returning, -* because the counter begins counting after two lf_clk cycles pass. +* The function waits for some delay in microseconds before returning, +* because the counter begins counting after two lf_clk cycles pass. * The recommended value is 93 us. * \note * Setting this parameter to a zero means No wait. In this case, it is -* the user's responsibility to check whether the selected counters were enabled -* immediately after the function call. This can be done by the +* the user's responsibility to check whether the selected counters were enabled +* immediately after the function call. This can be done by the * Cy_MCWDT_GetEnabledStatus() API. * *******************************************************************************/ @@ -395,7 +400,7 @@ __STATIC_INLINE void Cy_MCWDT_Enable(MCWDT_STRUCT_Type *base, uint32_t counters, uint32_t enableCounters; CY_ASSERT_L2(CY_MCWDT_IS_CNTS_MASK_VALID(counters)); - + /* Extract particular counters for enable */ enableCounters = ((0UL != (counters & CY_MCWDT_CTR0)) ? MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLE0_Msk : 0UL) | ((0UL != (counters & CY_MCWDT_CTR1)) ? MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLE1_Msk : 0UL) | @@ -421,13 +426,13 @@ __STATIC_INLINE void Cy_MCWDT_Enable(MCWDT_STRUCT_Type *base, uint32_t counters, * CY_MCWDT_CTR2 macros. * * \param waitUs -* The function waits for some delay in microseconds before returning, -* because the counter stops counting after two lf_clk cycles pass. +* The function waits for some delay in microseconds before returning, +* because the counter stops counting after two lf_clk cycles pass. * The recommended value is 93 us. * \note -* Setting this parameter to a zero means No wait. In this case, it is -* the user's responsibility to check whether the selected counters were disabled -* immediately after the function call. This can be done by the +* Setting this parameter to a zero means No wait. In this case, it is +* the user's responsibility to check whether the selected counters were disabled +* immediately after the function call. This can be done by the * Cy_MCWDT_GetEnabledStatus() API. * *******************************************************************************/ @@ -436,7 +441,7 @@ __STATIC_INLINE void Cy_MCWDT_Disable(MCWDT_STRUCT_Type *base, uint32_t counters uint32_t disableCounters; CY_ASSERT_L2(CY_MCWDT_IS_CNTS_MASK_VALID(counters)); - + /* Extract particular counters for disable */ disableCounters = ((0UL != (counters & CY_MCWDT_CTR0)) ? MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLE0_Msk : 0UL) | ((0UL != (counters & CY_MCWDT_CTR1)) ? MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLE1_Msk : 0UL) | @@ -469,7 +474,7 @@ __STATIC_INLINE uint32_t Cy_MCWDT_GetEnabledStatus(MCWDT_STRUCT_Type const *base uint32_t status = 0u; CY_ASSERT_L3(CY_MCWDT_IS_CNT_NUM_VALID(counter)); - + switch (counter) { case CY_MCWDT_COUNTER0: @@ -574,7 +579,7 @@ __STATIC_INLINE uint32_t Cy_MCWDT_GetLockedStatus(MCWDT_STRUCT_Type const *base) * The mode for Counter 2 can be set only to CY_MCWDT_MODE_NONE or CY_MCWDT_MODE_INT. * * \note -* This API must not be called while the counters are running. +* This API must not be called while the counters are running. * Prior to calling this API, the counter must be disabled. * *******************************************************************************/ @@ -641,7 +646,7 @@ __STATIC_INLINE cy_en_mcwdtmode_t Cy_MCWDT_GetMode(MCWDT_STRUCT_Type const *base * Set 0 to disable; 1 to enable. * * \note -* This API must not be called while the counters are running. +* This API must not be called while the counters are running. * Prior to calling this API, the counter must be disabled. * *******************************************************************************/ @@ -712,17 +717,17 @@ __STATIC_INLINE uint32_t Cy_MCWDT_GetClearOnMatch(MCWDT_STRUCT_Type const *base, * Sets or clears each of the cascade options. * * \note -* This API must not be called when the counters are running. +* This API must not be called when the counters are running. * Prior to calling this API, the counter must be disabled. * *******************************************************************************/ __STATIC_INLINE void Cy_MCWDT_SetCascade(MCWDT_STRUCT_Type *base, cy_en_mcwdtcascade_t cascade) { CY_ASSERT_L3(CY_MCWDT_IS_CASCADE_VALID(cascade)); - + MCWDT_STRUCT_MCWDT_CONFIG(base) = _CLR_SET_FLD32U(MCWDT_STRUCT_MCWDT_CONFIG(base), MCWDT_STRUCT_MCWDT_CONFIG_WDT_CASCADE0_1, (uint32_t) cascade); - MCWDT_STRUCT_MCWDT_CONFIG(base) = _CLR_SET_FLD32U(MCWDT_STRUCT_MCWDT_CONFIG(base), MCWDT_STRUCT_MCWDT_CONFIG_WDT_CASCADE1_2, + MCWDT_STRUCT_MCWDT_CONFIG(base) = _CLR_SET_FLD32U(MCWDT_STRUCT_MCWDT_CONFIG(base), MCWDT_STRUCT_MCWDT_CONFIG_WDT_CASCADE1_2, ((uint32_t) cascade >> 1u)); } @@ -764,20 +769,20 @@ __STATIC_INLINE cy_en_mcwdtcascade_t Cy_MCWDT_GetCascade(MCWDT_STRUCT_Type const * The number of the WDT counter. The valid range is [0-1]. * * \param match -* The value to match against the counter. -* The valid range is [0-65535] for c0ClearOnMatch (or c1ClearOnMatch) = 0 +* The value to match against the counter. +* The valid range is [0-65535] for c0ClearOnMatch (or c1ClearOnMatch) = 0 * and [1-65535] for c0ClearOnMatch (or c1ClearOnMatch) = 1. * * \note * The match value is not supported by Counter 2. * * \note -* Action on match is taken on the next increment after the counter value +* Action on match is taken on the next increment after the counter value * equal to match value. * * \param waitUs -* The function waits for some delay in microseconds before returning, -* because the match affects after two lf_clk cycles pass. The recommended +* The function waits for some delay in microseconds before returning, +* because the match affects after two lf_clk cycles pass. The recommended * value is 93 us. * \note * Setting this parameter to a zero means No wait. This must be taken @@ -787,8 +792,8 @@ __STATIC_INLINE cy_en_mcwdtcascade_t Cy_MCWDT_GetCascade(MCWDT_STRUCT_Type const __STATIC_INLINE void Cy_MCWDT_SetMatch(MCWDT_STRUCT_Type *base, cy_en_mcwdtctr_t counter, uint32_t match, uint16_t waitUs) { CY_ASSERT_L3(CY_MCWDT_IS_CNT_NUM_VALID(counter)); - CY_ASSERT_L2(CY_MCWDT_IS_MATCH_VALID((CY_MCWDT_COUNTER0 == counter) ? - ((MCWDT_STRUCT_MCWDT_CONFIG(base) & MCWDT_STRUCT_MCWDT_CONFIG_WDT_CLEAR0_Msk) > 0U) : + CY_ASSERT_L2(CY_MCWDT_IS_MATCH_VALID((CY_MCWDT_COUNTER0 == counter) ? + ((MCWDT_STRUCT_MCWDT_CONFIG(base) & MCWDT_STRUCT_MCWDT_CONFIG_WDT_CLEAR0_Msk) > 0U) : ((MCWDT_STRUCT_MCWDT_CONFIG(base) & MCWDT_STRUCT_MCWDT_CONFIG_WDT_CLEAR1_Msk) > 0U), match)); @@ -854,7 +859,7 @@ __STATIC_INLINE uint32_t Cy_MCWDT_GetMatch(MCWDT_STRUCT_Type const *base, cy_en_ __STATIC_INLINE void Cy_MCWDT_SetToggleBit(MCWDT_STRUCT_Type *base, uint32_t bit) { CY_ASSERT_L2(CY_MCWDT_IS_BIT_VALID(bit)); - + MCWDT_STRUCT_MCWDT_CONFIG(base) = _CLR_SET_FLD32U(MCWDT_STRUCT_MCWDT_CONFIG(base), MCWDT_STRUCT_MCWDT_CONFIG_WDT_BITS2, bit); } @@ -900,7 +905,7 @@ __STATIC_INLINE uint32_t Cy_MCWDT_GetCount(MCWDT_STRUCT_Type const *base, cy_en_ uint32_t countVal = 0u; CY_ASSERT_L3(CY_MCWDT_IS_CNT_NUM_VALID(counter)); - + switch (counter) { case CY_MCWDT_COUNTER0: @@ -936,17 +941,17 @@ __STATIC_INLINE uint32_t Cy_MCWDT_GetCount(MCWDT_STRUCT_Type const *base, cy_en_ * CY_MCWDT_CTR2 macros. * * \param waitUs -* The function waits for some delay in microseconds before returning, because +* The function waits for some delay in microseconds before returning, because * a reset occurs after one lf_clk cycle passes. The recommended value is 62 us. -* \note This function resets the counters two times to prevent the case when +* \note This function resets the counters two times to prevent the case when * the Counter 1 is not reset when the counters are cascaded. The delay waitUs -* must be greater than 100 us when the counters are cascaded. -* The total delay is greater than 2*waitUs because the function has +* must be greater than 100 us when the counters are cascaded. +* The total delay is greater than 2*waitUs because the function has * the delay after the first reset. * \note -* Setting this parameter to a zero means No wait. In this case, it is the -* user's responsibility to check whether the selected counters were reset -* immediately after the function call. This can be done by the +* Setting this parameter to a zero means No wait. In this case, it is the +* user's responsibility to check whether the selected counters were reset +* immediately after the function call. This can be done by the * Cy_MCWDT_GetCount() API. * *******************************************************************************/ @@ -955,18 +960,18 @@ __STATIC_INLINE void Cy_MCWDT_ResetCounters(MCWDT_STRUCT_Type *base, uint32_t co uint32_t resetCounters; CY_ASSERT_L2(CY_MCWDT_IS_CNTS_MASK_VALID(counters)); - + /* Extract particular counters for reset */ resetCounters = ((0UL != (counters & CY_MCWDT_CTR0)) ? MCWDT_STRUCT_MCWDT_CTL_WDT_RESET0_Msk : 0UL) | ((0UL != (counters & CY_MCWDT_CTR1)) ? MCWDT_STRUCT_MCWDT_CTL_WDT_RESET1_Msk : 0UL) | ((0UL != (counters & CY_MCWDT_CTR2)) ? MCWDT_STRUCT_MCWDT_CTL_WDT_RESET2_Msk : 0UL); MCWDT_STRUCT_MCWDT_CTL(base) |= resetCounters; - + Cy_SysLib_DelayUs(waitUs); - + MCWDT_STRUCT_MCWDT_CTL(base) |= resetCounters; - + Cy_SysLib_DelayUs(waitUs); } @@ -1011,7 +1016,7 @@ __STATIC_INLINE uint32_t Cy_MCWDT_GetInterruptStatus(MCWDT_STRUCT_Type const *ba __STATIC_INLINE void Cy_MCWDT_ClearInterrupt(MCWDT_STRUCT_Type *base, uint32_t counters) { CY_ASSERT_L2(CY_MCWDT_IS_CNTS_MASK_VALID(counters)); - + MCWDT_STRUCT_MCWDT_INTR(base) = counters; (void) MCWDT_STRUCT_MCWDT_INTR(base); } @@ -1078,7 +1083,7 @@ __STATIC_INLINE uint32_t Cy_MCWDT_GetInterruptMask(MCWDT_STRUCT_Type const *base __STATIC_INLINE void Cy_MCWDT_SetInterruptMask(MCWDT_STRUCT_Type *base, uint32_t counters) { CY_ASSERT_L2(CY_MCWDT_IS_CNTS_MASK_VALID(counters)); - + MCWDT_STRUCT_MCWDT_INTR_MASK(base) = counters; } @@ -1088,9 +1093,9 @@ __STATIC_INLINE void Cy_MCWDT_SetInterruptMask(MCWDT_STRUCT_Type *base, uint32_t ****************************************************************************//** * * Returns the MCWDT interrupt masked request register. This register contains -* the logical AND of corresponding bits from the MCWDT interrupt request and +* the logical AND of corresponding bits from the MCWDT interrupt request and * mask registers. -* In the interrupt service routine, this function identifies which of the +* In the interrupt service routine, this function identifies which of the * enabled MCWDT interrupt sources caused an interrupt event. * * \param base diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_pdl.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_pdl.h index d844c6451a..18b5067adc 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_pdl.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_pdl.h @@ -49,6 +49,8 @@ #include "cy_lvd.h" #include "cy_mcwdt.h" #include "cy_pdm_pcm.h" +#include "cy_pra.h" +#include "cy_pra_cfg.h" #include "cy_profile.h" #include "cy_prot.h" #include "cy_rtc.h" @@ -80,9 +82,9 @@ #define CY_PDL_VERSION_MAJOR 1 /** Driver Library minor version */ -#define CY_PDL_VERSION_MINOR 5 +#define CY_PDL_VERSION_MINOR 6 /** Driver Library version */ -#define CY_PDL_VERSION 105 +#define CY_PDL_VERSION 106 #endif /* CY_PDL_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_pdm_pcm.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_pdm_pcm.h index 34d1f45f86..046f7c3c29 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_pdm_pcm.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_pdm_pcm.h @@ -1,12 +1,12 @@ /***************************************************************************//** * \file cy_pdm_pcm.h -* \version 2.20.1 +* \version 2.20.2 * * The header file of the PDM_PCM driver. * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -30,9 +30,9 @@ * API to manage PDM-PCM conversion. A PDM-PCM converter is used * to convert 1-bit digital audio streaming data to PCM data. * -* The functions and other declarations used in this driver are in cy_pdm_pcm.h. -* You can include cy_pdl.h (ModusToolbox only) to get access to all functions -* and declarations in the PDL. +* The functions and other declarations used in this driver are in cy_pdm_pcm.h. +* You can include cy_pdl.h to get access to all functions +* and declarations in the PDL. * * Features: * * Supports FIFO buffer for Incoming Data @@ -115,13 +115,18 @@ *
VersionChangesReason for Change
1.30.1Minor documentation updates.Documentation enhancement.
1.30In version 1.20 the Cy_MCWDT_GetCountCascaded() function +* In version 1.20 the Cy_MCWDT_GetCountCascaded() function * returned the wrong value when counter#1 overflowed. * This bug is corrected in version 1.30. *
1.20Flattened the organization of the driver source code into the single +* Flattened the organization of the driver source code into the single * source directory and the single include directory. * Driver library directory-structure simplification.
Added register access layer. Use register access macros instead * of direct register access using dereferenced pointers.Makes register access device-independent, so that the PDL does +* Makes register access device-independent, so that the PDL does * not need to be recompiled for each supported part number.
* * +* +* +* +* +* * * * * * * -* * @@ -129,12 +134,12 @@ * * -* * * * -* * @@ -142,7 +147,7 @@ * * *
VersionChangesReason for Change
2.20.2Minor documentation updates.Documentation enhancement.
2.20.1Snippet updated.Old snippet outdated.
2.20Flattened the organization of the driver source code into the single +* Flattened the organization of the driver source code into the single * source directory and the single include directory. * Driver library directory-structure simplification.
Added register access layer. Use register access macros instead * of direct register access using dereferenced pointers.Makes register access device-independent, so that the PDL does +* Makes register access device-independent, so that the PDL does * not need to be recompiled for each supported part number.
2.10The gain values in range +4.5...+10.5dB (5 items) of /ref cy_en_pdm_pcm_gain_t are corrected. +* The gain values in range +4.5...+10.5dB (5 items) of /ref cy_en_pdm_pcm_gain_t are corrected. * Added Low Power Callback section.Incorrect setting of gain values in limited range. * Documentation update and clarification.
2.0Enumeration types for gain and soft mute cycles are added.
-* Function parameter checks are added.
+* Function parameter checks are added.
* The next functions are removed: * * Cy_PDM_PCM_EnterLowPowerCallback * * Cy_PDM_PCM_ExitLowPowerCallback @@ -375,7 +380,7 @@ typedef struct - 1: extension by sign bits */ cy_en_pdm_pcm_gain_t gainLeft; /**< Gain for left channel, see #cy_en_pdm_pcm_gain_t */ cy_en_pdm_pcm_gain_t gainRight; /**< Gain for right channel, see #cy_en_pdm_pcm_gain_t */ - uint8_t rxFifoTriggerLevel; /**< Fifo interrupt trigger level (in words), + uint8_t rxFifoTriggerLevel; /**< Fifo interrupt trigger level (in words), range: 0 - 253 for stereo and 0 - 254 for mono mode */ bool dmaTriggerEnable; /**< DMA trigger enable */ uint32_t interruptMask; /**< Interrupts enable mask */ @@ -455,7 +460,7 @@ typedef struct #define CY_PDM_PCM_IS_CHAN_VALID(chan) (((chan) == CY_PDM_PCM_CHAN_LEFT) || \ ((chan) == CY_PDM_PCM_CHAN_RIGHT)) - + #define CY_PDM_PCM_IS_S_CYCLES_VALID(sCycles) (((sCycles) == CY_PDM_PCM_SOFT_MUTE_CYCLES_64) || \ ((sCycles) == CY_PDM_PCM_SOFT_MUTE_CYCLES_96) || \ ((sCycles) == CY_PDM_PCM_SOFT_MUTE_CYCLES_128) || \ @@ -464,7 +469,7 @@ typedef struct ((sCycles) == CY_PDM_PCM_SOFT_MUTE_CYCLES_256) || \ ((sCycles) == CY_PDM_PCM_SOFT_MUTE_CYCLES_384) || \ ((sCycles) == CY_PDM_PCM_SOFT_MUTE_CYCLES_512)) - + #define CY_PDM_PCM_IS_INTR_MASK_VALID(interrupt) (0UL == ((interrupt) & ((uint32_t) ~CY_PDM_PCM_INTR_MASK))) #define CY_PDM_PCM_IS_SINC_RATE_VALID(sincRate) ((sincRate) <= 127U) #define CY_PDM_PCM_IS_STEP_SEL_VALID(stepSel) ((stepSel) <= 1UL) @@ -634,7 +639,7 @@ __STATIC_INLINE uint32_t Cy_PDM_PCM_GetInterruptStatus(PDM_Type const * base) * Clears one or more PDM-PCM interrupt statuses (sets an INTR register's bits). * * \param base The pointer to the PDM-PCM instance address -* \param interrupt +* \param interrupt * The interrupt bit mask \ref group_pdm_pcm_macros_interrupt_masks. * ******************************************************************************/ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_pra.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_pra.h new file mode 100644 index 0000000000..3f19c7a60f --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_pra.h @@ -0,0 +1,625 @@ +/***************************************************************************//** +* \file cy_pra.h +* \version 1.0 +* +* \brief The header file of the PRA driver. The API is not intended to +* be used directly by the user application. +* +******************************************************************************** +* \copyright +* Copyright 2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + + +/** +* \addtogroup group_pra +* \{ +* \note The Protection Register Access (PRA) driver is intended for the PSoC 64 +* devices only and provides other PDL drivers access to the registers that have +* secure access restrictions. It is not intended to be used directly by user +* application. +* +* The PRA driver is used to protect the system from invalid configurations that +* could potentially cause the system to be unstable or indirectly allow access +* to registers and memory that are protected. This is done using several +* methods: +* * Allow only valid register settings. +* * Force a specified sequence of operations when writing to a register. +* * Totally block access to registers that are deemed critical to security. +* * Allow only known, well defined system configurations. +* * Allow access to non-critical registers that are protected by a fixed PPU. +* +* On PSoC 64 devices, secure firmware protects entire regions of registers +* with the fixed PPUs, however there are some registers within that regions +* that should not be protected but, are protected due to fixed PPU +* granularity. +* +* The list of the registers that can be accessed by PRA driver directly is +* defined in the cy_pra.h file with the CY_PRA_INDX_ prefix. +* +* Most PDL drivers are not affected or use the PRA driver. Only the following +* PDL drivers are affected by this driver: +* * \ref group_lvd +* * \ref group_syslib +* * \ref group_sysclk +* * \ref group_syspm +* * \ref group_arm_system_timer +* * \ref group_wdt +* * \ref group_flash +* +* The execution time of the functions that access the protected registers is +* increased on the PSoC 64 devices because the access is performed on Cortex-M0+ +* via the IPC command: +* * The access to the protected register may take around by 20 times longer compared +* to unprotected one. +* * The initial device configuration based on the device configuration depends on +* actual configuration, but may take up to 40 times longer. +* * The transition Active to DeepSleep to Active may take 2 times longer. +* +* \section group_pra_basic_operation Basic Operation +* The PRA driver uses an IPC channel to transfer register data between the user +* application running on the Cortex-CM4 and the secure Cortex-CM0+ CPU. The +* secure processor performs the data validation and correct register write +* sequence to ensure proper stable operation of the system. Function status and +* requested data is also returned via the IPC channel. +* +* The PDL driver that accesses protected registers, generates request to the +* PRA driver and it passes request over the IPC to secure Cortex-M0+, where +* request is validated and executed, and, then, reports result back to the +* driver on Cortex-M4 side. +* +* \image html pra_high_level_diagram.png +* +* \section group_pra_device_config Device Configuration +* For PSoC 64 device, device configuration (like system clock settings and +* power modes) is applied on the secure Cortex-M0+. The device configuration +* structure \ref cy_stc_pra_system_config_t is initialized with Device +* Configurator and passed to the secure Cortex-M0+ for validation and +* register the update in the cybsp_init() function. +* +* \warning The external clocks (ECO, ALTHF, WCO, and EXTCLK) are not +* allowed to source CLK_HF0 (clocks both Cortex-M0+ and Cortex-M4 CPUs) +* in order to prevent clock tampering. The external clock support for +* CLK_HF0 feature is planned to be added and validated via secure policy +* statements in the future releases. +* +* \note The internal low-frequency clocks (ILO and PILO) are not allowed to +* source the CLK_HF0 directly and through PLL or FLL. +* +* \note The clock source for Cortex-M4 SysTick cannot be configured with +* the Device Configurator. Enabling CLK_ALT_SYS_TICK will result in a +* compilation error. SysTick still can be configured in run-time with +* some limitations. For more details, refer to \ref Cy_SysTick_GetClockSource() +* in \ref group_arm_system_timer. +* +* \section group_pra_standalone Using without BSPs +* If PDL is used in Standalone mode without Board Support Package (BSP), +* do the following: +* * 1) Call the \ref Cy_PRA_Init function prior to executing +* API of any of the drivers listed above. By default, this function is +* called from \ref SystemInit on both CPU cores. +* * 2) Call the \ref Cy_PRA_SystemConfig function with the initial +* device configuration passed as a parameter. Refer to Section "Function Usage" +* of the \ref Cy_PRA_SystemConfig function for more details. +* +* \section group_pra_more_information More Information +* See the device technical reference manual (TRM) reference manual (TRM) for +* the list of the protected registers. +* +* \section group_pra_MISRA MISRA-C Compliance +* The LVD driver specific deviations: +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +*
MISRA RuleRule Class (Required/Advisory)Rule DescriptionDescription of Deviation(s)
13.7RBoolean operations with invariant results are not permitted.False positive. Cy_PRA_SendCmd() compiled for Cortex-M4 has a shared +* variable, which is modified by the Cortex-M0+ application, but the analysis tool +* is not aware of this fact.
14.1RNo unreachable code.False positive. Cy_PRA_SendCmd() compiled for Cortex-M4 has a shared +* variable, which is modified by the Cortex-M0+ application and used in a condition +* statement, but the analysis tool is not aware of this fact.
14.7RA function has a single exit point at the end of the function.There are a few functions with multiple exit points implemented to +* simplify functions design.
19.13ADo not use the # and ## operators.The ## preprocessor operator is used in macros to form the field mask.
20.3RCheck the validity of values passed to library functions.The additional check to eliminate the possibility of accessing the beyond array in Cy_PRA_ProcessCmd().
+* +* \section group_pra_changelog Changelog +* +* +* +* +* +* +* +*
VersionChangesReason for Change
1.0Initial version
+* +* \defgroup group_pra_macros Macros +* \defgroup group_pra_functions Functions +* \defgroup group_pra_enums Enumerated Types +*/ + +#if !defined(CY_PRA_H) +#define CY_PRA_H + +#include +#include +#include "cy_systick.h" +#include "cy_ble_clk.h" +#include "cy_device_headers.h" + +#if defined (CY_DEVICE_SECURE) || defined (CY_DOXYGEN) + +#ifdef __cplusplus +extern "C" { +#endif + +/*************************************** +* Constants +***************************************/ + +/** \cond INTERNAL */ + +#define CY_PRA_REG_INDEX_COUNT (16U) + +#define CY_PRA_MSG_TYPE_REG32_GET (1U) +#define CY_PRA_MSG_TYPE_REG32_CLR_SET (2U) +#define CY_PRA_MSG_TYPE_REG32_SET (3U) +#define CY_PRA_MSG_TYPE_CM0_WAKEUP (4U) +#define CY_PRA_MSG_TYPE_SYS_CFG_FUNC (5U) +#define CY_PRA_MSG_TYPE_SECURE_ONLY (6U) +#define CY_PRA_MSG_TYPE_FUNC_POLICY (7U) + +/* IPC */ +#define CY_PRA_IPC_NOTIFY_INTR (0x1UL << CY_IPC_INTR_PRA) +#define CY_PRA_IPC_CHAN_INTR (0x1UL << CY_IPC_CHAN_PRA) +#define CY_PRA_IPC_NONE_INTR (0UL) + +/* Registers Index */ +#define CY_PRA_INDX_SRSS_PWR_LVD_CTL (0U) +#define CY_PRA_INDX_SRSS_SRSS_INTR (1U) +#define CY_PRA_INDX_SRSS_SRSS_INTR_SET (2U) +#define CY_PRA_INDX_SRSS_SRSS_INTR_MASK (3U) +#define CY_PRA_INDX_SRSS_SRSS_INTR_CFG (4U) +#define CY_PRA_INDX_SRSS_CLK_ROOT_SELECT_1 (5U) +/* Do not change the index below abecause it is used in flash loaders */ +#define CY_PRA_INDX_SRSS_CLK_ROOT_SELECT_2 (6U) +#define CY_PRA_INDX_SRSS_CLK_ROOT_SELECT_3 (7U) +#define CY_PRA_INDX_SRSS_CLK_ROOT_SELECT_4 (8U) +#define CY_PRA_INDX_SRSS_CLK_ROOT_SELECT_5 (9U) +#define CY_PRA_INDX_SRSS_CLK_ROOT_SELECT_6 (10U) +#define CY_PRA_INDX_FLASHC_FLASH_CMD (11U) +#define CY_PRA_INDX_SRSS_PWR_HIBERNATE (12U) +#define CY_PRA_INDX_SRSS_CLK_MFO_CONFIG (13U) +#define CY_PRA_INDX_SRSS_CLK_MF_SELECT (14U) +#define CY_PRA_INDX_FLASHC_FM_CTL_BOOKMARK (15U) + + +/* Functions Index */ +#define CY_PRA_FUNC_INIT_CYCFG_DEVICE (0U) + +#define CY_PRA_CLK_FUNC_ECO_DISABLE (8U) +#define CY_PRA_CLK_FUNC_FLL_DISABLE (9U) +#define CY_PRA_CLK_FUNC_PLL_DISABLE (10U) +#define CY_PRA_CLK_FUNC_ILO_ENABLE (11U) +#define CY_PRA_CLK_FUNC_ILO_DISABLE (12U) +#define CY_PRA_CLK_FUNC_ILO_HIBERNATE_ON (13U) +#define CY_PRA_CLK_FUNC_PILO_ENABLE (14U) +#define CY_PRA_CLK_FUNC_PILO_DISABLE (15U) +#define CY_PRA_CLK_FUNC_PILO_SET_TRIM (16U) +#define CY_PRA_CLK_FUNC_WCO_ENABLE (17U) +#define CY_PRA_CLK_FUNC_WCO_DISABLE (18U) +#define CY_PRA_CLK_FUNC_WCO_BYPASS (19U) +#define CY_PRA_CLK_FUNC_HF_ENABLE (20U) +#define CY_PRA_CLK_FUNC_HF_DISABLE (21U) +#define CY_PRA_CLK_FUNC_HF_SET_SOURCE (22U) +#define CY_PRA_CLK_FUNC_HF_SET_DIVIDER (23U) +#define CY_PRA_CLK_FUNC_FAST_SET_DIVIDER (24U) +#define CY_PRA_CLK_FUNC_PERI_SET_DIVIDER (25U) +#define CY_PRA_CLK_FUNC_LF_SET_SOURCE (26U) +#define CY_PRA_CLK_FUNC_TIMER_SET_SOURCE (27U) +#define CY_PRA_CLK_FUNC_TIMER_SET_DIVIDER (28U) +#define CY_PRA_CLK_FUNC_TIMER_ENABLE (29U) +#define CY_PRA_CLK_FUNC_TIMER_DISABLE (30U) +#define CY_PRA_CLK_FUNC_PUMP_SET_SOURCE (31U) +#define CY_PRA_CLK_FUNC_PUMP_SET_DIVIDER (32U) +#define CY_PRA_CLK_FUNC_PUMP_ENABLE (33U) +#define CY_PRA_CLK_FUNC_PUMP_DISABLE (34U) +#define CY_PRA_CLK_FUNC_BAK_SET_SOURCE (35U) +#define CY_PRA_CLK_FUNC_ECO_CONFIGURE (36U) +#define CY_PRA_CLK_FUNC_ECO_ENABLE (37U) +#define CY_PRA_CLK_FUNC_PATH_SET_SOURCE (38U) +#define CY_PRA_CLK_FUNC_FLL_MANCONFIG (39U) +#define CY_PRA_CLK_FUNC_FLL_ENABLE (40U) +#define CY_PRA_CLK_FUNC_PLL_MANCONFIG (41U) +#define CY_PRA_CLK_FUNC_PLL_ENABLE (42U) +#define CY_PRA_CLK_FUNC_SLOW_SET_DIVIDER (43U) +#define CY_PRA_CLK_FUNC_DS_BEFORE_TRANSITION (44U) +#define CY_PRA_CLK_FUNC_DS_AFTER_TRANSITION (45U) +#define CY_PRA_CLK_FUNC_EXT_CLK_SET_FREQUENCY (46U) + +#define CY_PRA_PM_FUNC_HIBERNATE (102U) +#define CY_PRA_PM_FUNC_CM4_DP_FLAG_SET (103U) +#define CY_PRA_PM_FUNC_LDO_SET_VOLTAGE (104U) +#define CY_PRA_PM_FUNC_BUCK_ENABLE (105U) +#define CY_PRA_PM_FUNC_SET_MIN_CURRENT (106U) +#define CY_PRA_PM_FUNC_SET_NORMAL_CURRENT (107U) +#define CY_PRA_PM_FUNC_BUCK_ENABLE_VOLTAGE2 (108U) +#define CY_PRA_PM_FUNC_BUCK_DISABLE_VOLTAGE2 (109U) +#define CY_PRA_PM_FUNC_BUCK_VOLTAGE2_HW_CTRL (110U) +#define CY_PRA_PM_FUNC_BUCK_SET_VOLTAGE2 (111U) + +/** Driver major version */ +#define CY_PRA_DRV_VERSION_MAJOR 1 + +/** Driver minor version */ +#define CY_PRA_DRV_VERSION_MINOR 0 + +/** Protected Register Access driver ID */ +#define CY_PRA_ID (CY_PDL_DRV_ID(0x46U)) + +/** \endcond */ + +/** +* \addtogroup group_pra_enums +* \{ +*/ +/** Status definitions of the PRA function return values. */ +typedef enum +{ + CY_PRA_STATUS_SUCCESS = 0x0U, /**< Returns success */ + CY_PRA_STATUS_ACCESS_DENIED = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xFFFU, /**< Access denied - PRA does not allow a call from Non-Secure */ + CY_PRA_STATUS_INVALID_PARAM = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xFFEU, /**< Invalid parameter */ + CY_PRA_STATUS_ERROR_PROCESSING = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xFFDU, /**< An error while applying the device configuration */ + CY_PRA_STATUS_REQUEST_SENT = CY_PRA_ID | CY_PDL_STATUS_INFO | 0xFFCU, /**< The IPC message status when sent from Non-Secure to Secure */ + CY_PRA_STATUS_ERROR_SYSPM_FAIL = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xFFBU, /**< SysPM failure */ + CY_PRA_STATUS_ERROR_SYSPM_TIMEOUT = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xFFAU, /**< SysPM operation timeout */ + /* Reserve 0xFF9 - 0xFF0 */ + + CY_PRA_STATUS_INVALID_PARAM_ECO = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xFEFU, /**< Returns Error while validating the ECO parameters */ + CY_PRA_STATUS_INVALID_PARAM_EXTCLK = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xFEEU, /**< Returns Error while validating the CLK_EXT parameters */ + CY_PRA_STATUS_INVALID_PARAM_ALTHF = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xFEDU, /**< Returns Error while validating the CLK_ALTHF parameters */ + CY_PRA_STATUS_INVALID_PARAM_ILO = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xFECU, /**< Returns Error while validating the CLK_ILO parameters */ + CY_PRA_STATUS_INVALID_PARAM_PILO = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xFEBU, /**< Returns Error while validating the CLK_PILO parameters */ + CY_PRA_STATUS_INVALID_PARAM_WCO = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xFEAU, /**< Returns Error while validating the CLK_WCO parameters */ + /* Reserve for other source clocks 0xFE9 - 0xFE0 */ + + CY_PRA_STATUS_INVALID_PARAM_PATHMUX0 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xFDFU, /**< Returns Error while validating PATH_MUX0 */ + CY_PRA_STATUS_INVALID_PARAM_PATHMUX1 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xFDEU, /**< Returns Error while validating PATH_MUX1 */ + CY_PRA_STATUS_INVALID_PARAM_PATHMUX2 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xFDDU, /**< Returns Error while validating PATH_MUX2 */ + CY_PRA_STATUS_INVALID_PARAM_PATHMUX3 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xFDCU, /**< Returns Error while validating PATH_MUX3 */ + CY_PRA_STATUS_INVALID_PARAM_PATHMUX4 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xFDBU, /**< Returns Error while validating PATH_MUX4 */ + CY_PRA_STATUS_INVALID_PARAM_PATHMUX5 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xFDAU, /**< Returns Error while validating PATH_MUX5 */ + /* Reserve for other path-mux 0xFD9 - 0xFD0 */ + + CY_PRA_STATUS_INVALID_PARAM_FLL0 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xFCFU, /**< Returns Error while validating FLL */ + /* Reserve for other FLLs 0xFCE - 0xFC0 */ + + CY_PRA_STATUS_INVALID_PARAM_PLL0 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xFBFU, /**< Returns Error while validating PLL0 */ + CY_PRA_STATUS_INVALID_PARAM_PLL1 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xFBEU, /**< Returns Error while validating PLL1 */ + CY_PRA_STATUS_INVALID_PARAM_PLL_NUM = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xFBDU, /**< Returns Error for the invalid PLL number */ + /* Reserve for other PLLs 0xFBC - 0xFB0 */ + + CY_PRA_STATUS_INVALID_PARAM_CLKLF = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xFAFU, /**< Returns Error while validating CLK_LF */ + /* Reserve for other clocks 0xFAE - 0xFA0 */ + + CY_PRA_STATUS_INVALID_PARAM_CLKHF0 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF9FU, /**< Returns Error while validating CLK_HF0 */ + CY_PRA_STATUS_INVALID_PARAM_CLKHF1 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF9EU, /**< Returns Error while validating CLK_HF1 */ + CY_PRA_STATUS_INVALID_PARAM_CLKHF2 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF9DU, /**< Returns Error while validating CLK_HF2 */ + CY_PRA_STATUS_INVALID_PARAM_CLKHF3 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF9CU, /**< Returns Error while validating CLK_HF3 */ + CY_PRA_STATUS_INVALID_PARAM_CLKHF4 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF9BU, /**< Returns Error while validating CLK_HF4 */ + CY_PRA_STATUS_INVALID_PARAM_CLKHF5 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF9AU, /**< Returns Error while validating CLK_HF5 */ + /* Reserve for other HF clocks 0xF99 - 0xF90 */ + + CY_PRA_STATUS_INVALID_PARAM_CLKPUMP = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF8FU, /**< Returns Error while validating CLK_PUMP */ + CY_PRA_STATUS_INVALID_PARAM_CLKBAK = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF8EU, /**< Returns Error while validating CLK_BAK */ + CY_PRA_STATUS_INVALID_PARAM_CLKFAST = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF8DU, /**< Returns Error while validating CLK_FAST */ + CY_PRA_STATUS_INVALID_PARAM_CLKPERI = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF8CU, /**< Returns Error while validating CLK_PERI */ + CY_PRA_STATUS_INVALID_PARAM_CLKSLOW = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF8BU, /**< Returns Error while validating CLK_SLOW */ + CY_PRA_STATUS_INVALID_PARAM_SYSTICK = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF8AU, /**< Returns Error while validating CLK_ALT_SYS_TICK */ + CY_PRA_STATUS_INVALID_PARAM_CLKTIMER = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF89U, /**< Returns Error while validating CLK_TIMER */ + /* Reserve for other HF clocks 0xF88 - 0xF70 */ + + CY_PRA_STATUS_ERROR_PROCESSING_PWR = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF6FU, /**< Returns Error while initializing power */ + /* Reserve 0xF6E - 0xF60*/ + + CY_PRA_STATUS_ERROR_PROCESSING_ECO = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF5FU, /**< Returns Error while initializing ECO */ + CY_PRA_STATUS_ERROR_PROCESSING_EXTCLK = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF5EU, /**< Returns Error while enabling CLK_EXT */ + CY_PRA_STATUS_ERROR_PROCESSING_ALTHF = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF5DU, /**< Returns Error while enabling CLK_ALTHF */ + CY_PRA_STATUS_ERROR_PROCESSING_ILO = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF5CU, /**< Returns Error while enabling/disabling CLK_ILO */ + CY_PRA_STATUS_ERROR_PROCESSING_PILO = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF5BU, /**< Returns Error while enabling/disabling CLK_ALTHF */ + CY_PRA_STATUS_ERROR_PROCESSING_WCO = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF5AU, /**< Returns Error while enabling/disabling CLK_WCO */ + CY_PRA_STATUS_ERROR_PROCESSING_ECO_ENABLED = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF59U, /**< Returns Error while enabling CLK_ECO */ + /* Reserve for other source clocks 0xF58 - 0xF50 */ + + CY_PRA_STATUS_ERROR_PROCESSING_PATHMUX0 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF4FU, /**< Returns Error while setting PATH_MUX0 */ + CY_PRA_STATUS_ERROR_PROCESSING_PATHMUX1 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF4EU, /**< Returns Error while setting PATH_MUX1 */ + CY_PRA_STATUS_ERROR_PROCESSING_PATHMUX2 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF4DU, /**< Returns Error while setting PATH_MUX2 */ + CY_PRA_STATUS_ERROR_PROCESSING_PATHMUX3 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF4CU, /**< Returns Error while setting PATH_MUX3 */ + CY_PRA_STATUS_ERROR_PROCESSING_PATHMUX4 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF4BU, /**< Returns Error while setting PATH_MUX4 */ + CY_PRA_STATUS_ERROR_PROCESSING_PATHMUX5 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF4AU, /**< Returns Error while setting PATH_MUX5 */ + /* Reserve for other path-mux 0xF49 - 0xF40 */ + + CY_PRA_STATUS_ERROR_PROCESSING_FLL0 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF3FU, /**< Returns Error while enabling/disabling FLL */ + CY_PRA_STATUS_ERROR_PROCESSING_FLL0_ENABLED = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF3EU, /**< Returns Error while trying to enable an already enabled FLL */ + /* Reserve for other FLLs 0xF3D - 0xF30 */ + + CY_PRA_STATUS_ERROR_PROCESSING_PLL0 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF2FU, /**< Returns Error while enabling/disabling PLL0 */ + CY_PRA_STATUS_ERROR_PROCESSING_PLL1 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF2EU, /**< Returns Error while enabling/disabling PLL1 */ + CY_PRA_STATUS_ERROR_PROCESSING_PLL_ENABLED = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF2DU, /**< Returns Error while trying to enable an already enabled PLL */ + /* Reserve for other PLLs 0xF2C - 0xF20 */ + + CY_PRA_STATUS_ERROR_PROCESSING_CLKLF = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF1FU, /**< Returns Error while enabling/disabling CLK_LF */ + /* Reserve for other clocks 0xF1E - 0xF10 */ + + CY_PRA_STATUS_ERROR_PROCESSING_CLKHF0 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF0FU, /**< Returns Error while enabling/disabling CLK_HF0 */ + CY_PRA_STATUS_ERROR_PROCESSING_CLKHF1 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF0EU, /**< Returns Error while enabling/disabling CLK_HF1 */ + CY_PRA_STATUS_ERROR_PROCESSING_CLKHF2 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF0DU, /**< Returns Error while enabling/disabling CLK_HF2 */ + CY_PRA_STATUS_ERROR_PROCESSING_CLKHF3 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF0CU, /**< Returns Error while enabling/disabling CLK_HF3 */ + CY_PRA_STATUS_ERROR_PROCESSING_CLKHF4 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF0BU, /**< Returns Error while enabling/disabling CLK_HF4 */ + CY_PRA_STATUS_ERROR_PROCESSING_CLKHF5 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF0AU, /**< Returns Error while enabling/disabling CLK_HF5 */ + + /* Reserve for other HF clocks 0xF09 - 0xF00 */ + CY_PRA_STATUS_ERROR_PROCESSING_CLKPUMP = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xEFFU, /**< Returns Error while enabling/disabling CLK_PUMP */ + CY_PRA_STATUS_ERROR_PROCESSING_CLKBAK = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xEFEU, /**< Returns Error while enabling/disabling CLK_BAK */ + CY_PRA_STATUS_ERROR_PROCESSING_CLKFAST = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xEFDU, /**< Returns Error while enabling/disabling CLK_FAST */ + CY_PRA_STATUS_ERROR_PROCESSING_CLKPERI = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xEFCU, /**< Returns Error while enabling/disabling CLK_PERI */ + CY_PRA_STATUS_ERROR_PROCESSING_CLKSLOW = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xEFBU, /**< Returns Error while enabling/disabling CLK_SLOW */ + CY_PRA_STATUS_ERROR_PROCESSING_SYSTICK = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xEFAU, /**< Returns Error while enabling/disabling CLK_ALT_SYS_TICK */ + CY_PRA_STATUS_ERROR_PROCESSING_CLKTIMER = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xEF9U, /**< Returns Error while enabling/disabling CLK_TIMER */ +} cy_en_pra_status_t; +/** \} group_pra_enums */ + + +/******************************************************************************* + * Data Structures + ******************************************************************************/ + +/** \cond INTERNAL */ +/** PRA register access */ +typedef struct +{ + volatile uint32_t * addr; /**< A protected register address */ + uint32_t writeMask; /**< The write mask. Zero grants access, one - no access. */ +} cy_stc_pra_reg_policy_t; + +/** Message used for communication */ +typedef struct +{ + uint16_t praCommand; /**< The message type. Refer to \ref group_pra_macros. */ + uint16_t praIndex; /**< The register or function index. */ + cy_en_pra_status_t praStatus; /**< The status */ + uint32_t praData1; /**< The first data word. The usage depends on \ref group_pra_macros. */ + uint32_t praData2; /**< The second data word. The usage depends on \ref group_pra_macros. */ +} cy_stc_pra_msg_t; +/** \endcond */ + +/** \cond INTERNAL */ +/* Public for testing purposes */ +extern cy_stc_pra_reg_policy_t regIndexToAddr[CY_PRA_REG_INDEX_COUNT]; +/** \endcond */ + + +/******************************************************************************* +* Function Prototypes +*******************************************************************************/ + +/** +* \addtogroup group_pra_functions +* \{ +*/ +void Cy_PRA_Init(void); + +/** \cond INTERNAL */ +#if (CY_CPU_CORTEX_M0P) || defined (CY_DOXYGEN) + void Cy_PRA_CloseSrssMain2(void); + void Cy_PRA_OpenSrssMain2(void); +#endif /* (CY_CPU_CORTEX_M0P) */ +/** \endcond */ + +#if (CY_CPU_CORTEX_M4) || defined (CY_DOXYGEN) + cy_en_pra_status_t Cy_PRA_SendCmd(uint16_t cmd, uint16_t regIndex, uint32_t clearMask, uint32_t setMask); + + /** \} group_pra_functions */ + + /** + * \addtogroup group_pra_macros + * \{ + */ + +/******************************************************************************* +* Macro Name: CY_PRA_REG32_CLR_SET +****************************************************************************//** +* +* Provides get-clear-modify-write operations with a name field and value and +* writes a resulting value to the 32-bit register. +* +* \note An attempt to access not-supported registers (not secure and +* not listed in the TRM) results in an error. The list of the registers that +* can be accessed by the PRA driver directly is defined in the cy_pra.h file +* with the CY_PRA_INDX_ prefix. +* +*******************************************************************************/ + #define CY_PRA_REG32_CLR_SET(regIndex, field, value) \ + (void)Cy_PRA_SendCmd(CY_PRA_MSG_TYPE_REG32_CLR_SET, \ + (regIndex), \ + ((uint32_t)(~(field ## _Msk))), \ + (_VAL2FLD(field, \ + (value)))) + + +/******************************************************************************* +* Macro Name: CY_PRA_REG32_SET(regIndex, value) +****************************************************************************//** +* +* Writes the 32-bit value to the specified register. +* +* \note An attempt to access not-supported registers (not secure and +* not listed in the TRM) results in an error. The list of the registers that +* can be accessed by the PRA driver directly is defined in the cy_pra.h file +* with the CY_PRA_INDX_ prefix. +* +* \param regIndex The register address index. +* +* \param value The value to write. +* +*******************************************************************************/ + #define CY_PRA_REG32_SET(regIndex, value) \ + (void)Cy_PRA_SendCmd(CY_PRA_MSG_TYPE_REG32_SET, (regIndex), (value), 0UL) + + +/******************************************************************************* +* Macro Name: CY_PRA_REG32_GET(regIndex) +****************************************************************************//** +* +* Reads the 32-bit value from the specified register. +* +* \note An attempt to access not-supported registers (not secure and +* not listed in the TRM) results in an error. The list of the registers that +* can be accessed by the PRA driver directly is defined in the cy_pra.h file +* with the CY_PRA_INDX_ prefix. +* +* \param regIndex The register address index. +* +* \return The read value. +* +*******************************************************************************/ + #define CY_PRA_REG32_GET(regIndex) \ + (uint32_t) Cy_PRA_SendCmd(CY_PRA_MSG_TYPE_REG32_GET, (regIndex), 0UL, 0UL) + + +/******************************************************************************* +* Macro Name: CY_PRA_CM0_WAKEUP() +****************************************************************************//** +* +* The request to wake up the Cortex-M0+ core. +* +*******************************************************************************/ + #define CY_PRA_CM0_WAKEUP() \ + (void)Cy_PRA_SendCmd(CY_PRA_MSG_TYPE_CM0_WAKEUP, (uint16_t) 0U, 0UL, 0UL) + + +/******************************************************************************* +* Macro Name: CY_PRA_FUNCTION_CALL_RETURN_PARAM(msgType, funcIndex, param) +****************************************************************************//** +* +* Calls the specified function with the provided parameter and returns the +* execution status. +* +* \param msgType The function type. +* +* \param funcIndex The function reference. +* +* \param param The pointer to the function parameter. +* +* \return The function execution status. +* +*******************************************************************************/ + #define CY_PRA_FUNCTION_CALL_RETURN_PARAM(msgType, funcIndex, param) \ + Cy_PRA_SendCmd((msgType), (funcIndex), (uint32_t)(param), 0UL) + + +/******************************************************************************* +* Macro Name: CY_PRA_FUNCTION_CALL_RETURN_VOID(msgType, funcIndex) +****************************************************************************//** +* +* Calls the specified function without a parameter and returns void. +* +* \param msgType The function type. +* +* \param funcIndex The function reference. +* +* \return The function execution status. +* +*******************************************************************************/ + #define CY_PRA_FUNCTION_CALL_RETURN_VOID(msgType, funcIndex) \ + Cy_PRA_SendCmd((msgType), (funcIndex), 0UL, 0UL) + + +/******************************************************************************* +* Macro Name: CY_PRA_FUNCTION_CALL_VOID_PARAM(msgType, funcIndex, param) +****************************************************************************//** +* +* Calls the specified function with the provided parameter and returns void. +* +* \param msgType The function type. +* +* \param funcIndex The function reference. +* +* \param param The pointer to the function parameter. +* +*******************************************************************************/ + #define CY_PRA_FUNCTION_CALL_VOID_PARAM(msgType, funcIndex, param) \ + (void)Cy_PRA_SendCmd((msgType), (funcIndex), (uint32_t)(param), 0UL) + + +/******************************************************************************* +* Macro Name: CY_PRA_FUNCTION_CALL_VOID_VOID(msgType, funcIndex) +****************************************************************************//** +* +* Calls the specified function without a parameter and returns void. +* +* \param msgType The function type. +* +* \param funcIndex The function reference. +* +*******************************************************************************/ + #define CY_PRA_FUNCTION_CALL_VOID_VOID(msgType, funcIndex) \ + (void)Cy_PRA_SendCmd((msgType), (funcIndex), 0UL, 0UL) + +/** \} group_pra_macros */ + +#endif /* (CY_CPU_CORTEX_M4) */ + +#ifdef __cplusplus +} +#endif + +#endif /* (CY_DEVICE_SECURE) */ + +#endif /* #if !defined(CY_PRA_H) */ + +/** \} group_pra */ + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_pra_cfg.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_pra_cfg.h new file mode 100644 index 0000000000..dc3e5e6828 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_pra_cfg.h @@ -0,0 +1,315 @@ +/***************************************************************************//** +* \file cy_pra_cfg.h +* \version 1.0 +* +* \brief The header file of the PRA driver. The API is not intended to +* be used directly by the user application. +* +******************************************************************************** +* \copyright +* Copyright 2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#if !defined(CY_PRA_CFG_H) +#define CY_PRA_CFG_H + +#include +#include +#include "cy_pra.h" +#include "cy_sysclk.h" +#include "cy_systick.h" +#include "cy_ble_clk.h" +#include "cy_device_headers.h" + +#if defined (CY_DEVICE_SECURE) || defined (CY_DOXYGEN) + +#ifdef __cplusplus +extern "C" { +#endif + + +/******************************************************************************* +* Type Definitions +*******************************************************************************/ + +/** \cond INTERNAL */ + +#define CY_PRA_FREQUENCY_HZ_CONVERSION 1000000UL +#define CY_PRA_150MHZ_FREQUENCY 150UL +#define CY_PRA_FLL_ENABLE_TIMEOUT 200000UL +#define CY_PRA_ECO_ENABLE_TIMEOUT 3000UL +#define CY_PRA_WCO_ENABLE_TIMEOUT 1000000UL +#define CY_PRA_IMO_SRC_FREQUENCY 8000000UL +#define CY_PRA_ILO_SRC_FREQUENCY 32000UL +#define CY_PRA_WCO_SRC_FREQUENCY 32768UL +#define CY_PRA_PILO_SRC_FREQUENCY 32768UL +#define CY_PRA_DEFAULT_SRC_FREQUENCY 0xFFFFFFFEUL +#define CY_PRA_ULP_MODE_MAX_FREQUENCY 50000000UL +#define CY_PRA_LP_MODE_MAX_FREQUENCY 100000000UL +#define CY_PRA_ALTHF_MIN_FREQUENCY 2000000UL +#define CY_PRA_ALTHF_MAX_FREQUENCY 32000000UL +#define CY_PRA_ALTHF_MIN_STARTUP_TIME 400UL +#define CY_PRA_ALTHF_MAX_STARTUP_TIME 4704UL +#define CY_PRA_ALTHF_MIN_LOAD 7.5 +#define CY_PRA_ALTHF_MAX_LOAD 26.325 + +#define CY_PRA_FLL_SRC_MIN_FREQUENCY (1000UL) /* 1 KHz */ +#define CY_PRA_FLL_SRC_MAX_FREQUENCY (100000000UL) /* 100 MHz */ +#define CY_PRA_FLL_OUT_MIN_FREQUENCY (24000000UL) /* 24 MHz */ +#define CY_PRA_FLL_ULP_OUT_MAX_FREQUENCY (50000000UL) /* 50 MHz */ +#define CY_PRA_FLL_OUT_MAX_FREQUENCY ((CY_HF_CLK_MAX_FREQ > 100000000UL) ? (100000000UL) : (CY_HF_CLK_MAX_FREQ)) +#define CY_PRA_FLL_MIN_MULTIPLIER 1UL +#define CY_PRA_FLL_MAX_MULTIPLIER 262143UL +#define CY_PRA_FLL_MIN_REFDIV 1UL +#define CY_PRA_FLL_MAX_REFDIV 8191UL +#define CY_PRA_FLL_MAX_LOCK_TOLERENCE 511UL + +#define CY_PRA_PLL_SRC_MIN_FREQUENCY (4000000UL) /* 4 MHz */ +#define CY_PRA_PLL_SRC_MAX_FREQUENCY (64000000UL) /* 64 MHz */ +#define CY_PRA_PLL_LOW_OUT_MIN_FREQUENCY (10625000UL) /* 10.625 MHz */ +#define CY_PRA_PLL_OUT_MIN_FREQUENCY (12500000UL) /* 12.5 MHz */ +#define CY_PRA_PLL_ULP_OUT_MAX_FREQUENCY (50000000UL) /* 50 MHz */ +#define CY_PRA_PLL_OUT_MAX_FREQUENCY (CY_HF_CLK_MAX_FREQ) + +#define CY_PRA_HF0_MIN_FREQUENCY 200000UL +#define CY_PRA_PUMP_OUT_MAX_FREQUENCY 400000000UL +#define CY_PRA_BAK_OUT_MAX_FREQUENCY 100000UL +#define CY_PRA_FAST_OUT_MAX_FREQUENCY 400000000UL +#define CY_PRA_TIMER_OUT_MAX_FREQUENCY 400000000UL +#define CY_PRA_SLOW_OUT_MAX_FREQUENCY 100000000UL +#define CY_PRA_SYSTICK_OUT_MAX_FREQUENCY 400000000UL +#define CY_PRA_ULP_MODE_HF0_MAX_FREQUENCY 25000000UL + +#define CY_PRA_DEFAULT_ZERO 0U +#define CY_PRA_STRUCT_INITIALIZED 1UL +#define CY_PRA_STRUCT_NOT_INITIALIZED 0UL +#define CY_PRA_DATA_ENABLE 1UL +#define CY_PRA_DATA_DISABLE 0UL +#define CY_PRA_CLKHF_0 0UL +#define CY_PRA_CLKHF_1 1UL +#define CY_PRA_CLKHF_2 2UL +#define CY_PRA_CLKHF_3 3UL +#define CY_PRA_CLKHF_4 4UL +#define CY_PRA_CLKHF_5 5UL +#define CY_PRA_CLKPATH_0 0U +#define CY_PRA_CLKPATH_1 1U +#define CY_PRA_CLKPATH_2 2U +#define CY_PRA_CLKPATH_3 3U +#define CY_PRA_CLKPATH_4 4U +#define CY_PRA_CLKPATH_5 5U +#define CY_PRA_CLKPLL_1 1U +#define CY_PRA_CLKPLL_2 2U +#define CY_PRA_DIVIDER_0 0U +#define CY_PRA_DIVIDER_1 1U +#define CY_PRA_DIVIDER_2 2U +#define CY_PRA_DIVIDER_4 4U +#define CY_PRA_DIVIDER_8 8U + +/** \endcond */ + + +/** +* \addtogroup group_pra_data_structures_cfg +* \{ +*/ + +/** System configuration structure */ +typedef struct +{ + bool powerEnable; /**< Power is enabled or disabled */ + bool ldoEnable; /**< Core Regulator */ + bool pmicEnable; /**< Power using external PMIC output */ + bool vBackupVDDDEnable; /**< vBackup source using VDD or Direct supply */ + bool ulpEnable; /**< System Active Power mode is ULP */ + bool ecoEnable; /**< ECO Enable */ + bool extClkEnable; /**< EXTCLK Enable */ + bool iloEnable; /**< ILO Enable */ + bool wcoEnable; /**< WCO Enable */ + bool fllEnable; /**< FLL Enable */ + bool pll0Enable; /**< PLL0 Enable */ + bool pll1Enable; /**< PLL1 Enable */ + bool path0Enable; /**< PATH_MUX0 Enable */ + bool path1Enable; /**< PATH_MUX1 Enable */ + bool path2Enable; /**< PATH_MUX2 Enable */ + bool path3Enable; /**< PATH_MUX3 Enable */ + bool path4Enable; /**< PATH_MUX4 Enable */ + bool path5Enable; /**< PATH_MUX5 Enable */ + bool clkFastEnable; /**< CLKFAST Enable */ + bool clkPeriEnable; /**< CLKPERI Enable */ + bool clkSlowEnable; /**< CLKSLOW Enable */ + bool clkHF0Enable; /**< CLKHF0 Enable */ + bool clkHF1Enable; /**< CLKHF1 Enable */ + bool clkHF2Enable; /**< CLKHF2 Enable */ + bool clkHF3Enable; /**< CLKHF3 Enable */ + bool clkHF4Enable; /**< CLKHF4 Enable */ + bool clkHF5Enable; /**< CLKHF5 Enable */ + bool clkPumpEnable; /**< CLKPUMP Enable */ + bool clkLFEnable; /**< CLKLF Enable */ + bool clkBakEnable; /**< CLKBAK Enable */ + bool clkTimerEnable; /**< CLKTIMER Enable */ + bool clkAltSysTickEnable; /**< CLKALTSYSTICK Enable */ + bool piloEnable; /**< PILO Enable */ + bool clkAltHfEnable; /**< BLE ECO Clock Enable */ + + /* Power */ + cy_en_syspm_ldo_voltage_t ldoVoltage; /**< LDO Voltage (LP or ULP) */ + cy_en_syspm_buck_voltage1_t buckVoltage; /**< Buck Voltage */ + bool pwrCurrentModeMin; /**< Minimum core regulator current mode */ + + /* System clocks */ + /* IMO is always enabled */ + /* ECO Configuration */ + uint32_t ecoFreqHz; /**< ECO Frequency in Hz */ + uint32_t ecoLoad; /**< Parallel Load Capacitance (pF) */ + uint32_t ecoEsr; /**< Equivalent series resistance (ohm) */ + uint32_t ecoDriveLevel; /**< Drive Level (uW) */ + GPIO_PRT_Type *ecoInPort; /**< ECO input port */ + GPIO_PRT_Type *ecoOutPort; /**< ECO output port */ + uint32_t ecoInPinNum; /**< ECO input pin number */ + uint32_t ecoOutPinNum; /**< ECO output pin number */ + + /* EXTCLK Configuration */ + uint32_t extClkFreqHz; /**< External clock frequency in Hz */ + GPIO_PRT_Type *extClkPort; /**< External connection port */ + uint32_t extClkPinNum; /**< External connection pin */ + en_hsiom_sel_t extClkHsiom; /**< IO mux value */ + + /* ILO Configuration */ + bool iloHibernateON; /**< Run in Hibernate Mode */ + + /* WCO Configuration */ + bool bypassEnable; /**< Clock port bypass to External sine wave or to normal crystal */ + GPIO_PRT_Type *wcoInPort; /**< WCO Input port */ + GPIO_PRT_Type *wcoOutPort; /**< WCO Output port */ + uint32_t wcoInPinNum; /**< WCO Input pin */ + uint32_t wcoOutPinNum; /**< WCO Output pin */ + + /* FLL Configuration */ + uint32_t fllOutFreqHz; /**< FLL Output Frequency in Hz */ + uint32_t fllMult; /**< CLK_FLL_CONFIG register, FLL_MULT bits */ + uint16_t fllRefDiv; /**< CLK_FLL_CONFIG2 register, FLL_REF_DIV bits */ + cy_en_fll_cco_ranges_t fllCcoRange; /**< CLK_FLL_CONFIG4 register, CCO_RANGE bits */ + bool enableOutputDiv; /**< CLK_FLL_CONFIG register, FLL_OUTPUT_DIV bit */ + uint16_t lockTolerance; /**< CLK_FLL_CONFIG2 register, LOCK_TOL bits */ + uint8_t igain; /**< CLK_FLL_CONFIG3 register, FLL_LF_IGAIN bits */ + uint8_t pgain; /**< CLK_FLL_CONFIG3 register, FLL_LF_PGAIN bits */ + uint16_t settlingCount; /**< CLK_FLL_CONFIG3 register, SETTLING_COUNT bits */ + cy_en_fll_pll_output_mode_t outputMode; /**< CLK_FLL_CONFIG3 register, BYPASS_SEL bits */ + uint16_t ccoFreq; /**< CLK_FLL_CONFIG4 register, CCO_FREQ bits */ + + /* Number of PLL available for the device is defined in CY_SRSS_NUM_PLL + * Max 2 instances of PLLs are defined */ + + /* PLL0 Configuration */ + uint32_t pll0OutFreqHz; /**< PLL0 output frequency in Hz */ + uint8_t pll0FeedbackDiv; /**< PLL0 CLK_PLL_CONFIG register, FEEDBACK_DIV (P) bits */ + uint8_t pll0ReferenceDiv; /**< PLL0 CLK_PLL_CONFIG register, REFERENCE_DIV (Q) bits */ + uint8_t pll0OutputDiv; /**< PLL0 CLK_PLL_CONFIG register, OUTPUT_DIV bits */ + bool pll0LfMode; /**< PLL0 CLK_PLL_CONFIG register, PLL_LF_MODE bit */ + cy_en_fll_pll_output_mode_t pll0OutputMode; /**< PLL0 CLK_PLL_CONFIG register, BYPASS_SEL bits */ + + /* PLL1 Configuration */ + uint32_t pll1OutFreqHz; /**< PLL1 output frequency in Hz */ + uint8_t pll1FeedbackDiv; /**< PLL1 CLK_PLL_CONFIG register, FEEDBACK_DIV (P) bits */ + uint8_t pll1ReferenceDiv; /**< PLL1 CLK_PLL_CONFIG register, REFERENCE_DIV (Q) bits */ + uint8_t pll1OutputDiv; /**< PLL1 CLK_PLL_CONFIG register, OUTPUT_DIV bits */ + bool pll1LfMode; /**< PLL1 CLK_PLL_CONFIG register, PLL_LF_MODE bit */ + cy_en_fll_pll_output_mode_t pll1OutputMode; /**< PLL1 CLK_PLL_CONFIG register, BYPASS_SEL bits */ + + /* The number of clock paths available for the device is defined in CY_SRSS_NUM_CLKPATH. + * Max 6 clock paths are defined */ + + /* Clock Paths Configuration */ + cy_en_clkpath_in_sources_t path0Src; /**< Input multiplexer0 clock source */ + cy_en_clkpath_in_sources_t path1Src; /**< Input multiplexer1 clock source */ + cy_en_clkpath_in_sources_t path2Src; /**< Input multiplexer2 clock source */ + cy_en_clkpath_in_sources_t path3Src; /**< Input multiplexer3 clock source */ + cy_en_clkpath_in_sources_t path4Src; /**< Input multiplexer4 clock source */ + cy_en_clkpath_in_sources_t path5Src; /**< Input multiplexer5 clock source */ + + /* Clock Dividers */ + uint8_t clkFastDiv; /**< Fast clock divider. User has to pass actual divider-1 */ + uint8_t clkPeriDiv; /**< Peri clock divider. User has to pass actual divider-1 */ + uint8_t clkSlowDiv; /**< Slow clock divider. User has to pass actual divider-1 */ + + /* The number of HF clocks is defined in the device specific header CY_SRSS_NUM_HFROOT + * Max 6 HFs are defined */ + /* HF Configurations */ + cy_en_clkhf_in_sources_t hf0Source; /**< HF0 Source Clock Path */ + cy_en_clkhf_dividers_t hf0Divider; /**< HF0 Divider */ + uint32_t hf0OutFreqMHz; /**< HF0 Output Frequency in MHz */ + cy_en_clkhf_in_sources_t hf1Source; /**< HF1 Source Clock Path */ + cy_en_clkhf_dividers_t hf1Divider; /**< HF1 Divider */ + uint32_t hf1OutFreqMHz; /**< HF1 Output Frequency in MHz */ + cy_en_clkhf_in_sources_t hf2Source; /**< HF2 Source Clock Path */ + cy_en_clkhf_dividers_t hf2Divider; /**< HF2 Divider */ + uint32_t hf2OutFreqMHz; /**< HF2 Output Frequency in MHz */ + cy_en_clkhf_in_sources_t hf3Source; /**< HF3 Source Clock Path */ + cy_en_clkhf_dividers_t hf3Divider; /**< HF3 Divider */ + uint32_t hf3OutFreqMHz; /**< HF3 Output Frequency in MHz */ + cy_en_clkhf_in_sources_t hf4Source; /**< HF4 Source Clock Path */ + cy_en_clkhf_dividers_t hf4Divider; /**< HF4 Divider */ + uint32_t hf4OutFreqMHz; /**< HF4 Output Frequency in MHz */ + cy_en_clkhf_in_sources_t hf5Source; /**< HF5 Source Clock Path */ + cy_en_clkhf_dividers_t hf5Divider; /**< HF5 Divider */ + uint32_t hf5OutFreqMHz; /**< HF5 Output Frequency in MHz */ + cy_en_clkpump_in_sources_t pumpSource; /**< PUMP Source Clock Path */ + cy_en_clkpump_divide_t pumpDivider; /**< PUMP Divider */ + + /* Misc clock configurations */ + cy_en_clklf_in_sources_t clkLfSource; /**< Clock LF Source */ + cy_en_clkbak_in_sources_t clkBakSource; /**< Clock Backup domain Source */ + cy_en_clktimer_in_sources_t clkTimerSource; /**< Clock Timer Source */ + uint8_t clkTimerDivider; /**< Clock Timer Divider */ + cy_en_systick_clock_source_t clkSrcAltSysTick; /**< SysTick Source */ + + /* BLE ECO */ + uint32_t altHFcLoad; /**< Load Cap (pF) */ + uint32_t altHFxtalStartUpTime; /**< Startup Time (us) */ + uint32_t altHFfreq; /**< Output Frequency */ + uint32_t altHFsysClkDiv; /**< Clock Divider */ + uint32_t altHFvoltageReg; /**< BLE Voltage Regulator */ +} cy_stc_pra_system_config_t; +/** \} group_pra_data_structures_cfg */ + + +/******************************************************************************* +* Function Prototypes +*******************************************************************************/ + +/** +* \addtogroup group_pra_functions +* \{ +*/ + +cy_en_pra_status_t Cy_PRA_SystemConfig(const cy_stc_pra_system_config_t *devConfig); + +/** \} group_pra_functions */ + +#if (CY_CPU_CORTEX_M0P) || defined (CY_DOXYGEN) +uint32_t Cy_PRA_CalculateFLLOutFreq(const cy_stc_pra_system_config_t *devConfig); +uint32_t Cy_PRA_CalculatePLLOutFreq(uint8_t pll, const cy_stc_pra_system_config_t *devConfig); +#endif /* (CY_CPU_CORTEX_M0P) || defined (CY_DOXYGEN) */ + +#ifdef __cplusplus +} +#endif + +#endif /* (CY_DEVICE_SECURE) */ + +#endif /* #if !defined(CY_PRA_CFG_H) */ + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_profile.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_profile.h index efc305eb6c..7a8f990118 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_profile.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_profile.h @@ -1,12 +1,12 @@ /***************************************************************************//** * \file cy_profile.h -* \version 1.20 +* \version 1.20.1 * * Provides an API declaration of the energy profiler driver. * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -25,13 +25,13 @@ /** * \addtogroup group_energy_profiler * \{ -* -* The energy profiler driver is an API for configuring and using the profile -* hardware block. * -* The functions and other declarations used in this driver are in cy_profile.h. -* You can include cy_pdl.h (ModusToolbox only) to get access to all functions -* and declarations in the PDL. +* The energy profiler driver is an API for configuring and using the profile +* hardware block. +* +* The functions and other declarations used in this driver are in cy_profile.h. +* You can include cy_pdl.h to get access to all functions +* and declarations in the PDL. * * The profile block enables measurement of the signal activity * of select peripherals and monitor sources during a measurement window. Using @@ -46,17 +46,17 @@ * \subsection group_profile_hardware Profile Hardware * * The profile hardware consists of a number of profile counters that accept specific -* triggers for incrementing the count value. This allows the events of the source +* triggers for incrementing the count value. This allows the events of the source * (such as the number of SCB0 bus accesses or the duration of time the BLE RX radio -* is active) to be counted during the measurement window. The available monitor -* sources in the device can be found in the en_ep_mon_sel_t enum in the device +* is active) to be counted during the measurement window. The available monitor +* sources in the device can be found in the en_ep_mon_sel_t enum in the device * configuration file (e.g. psoc62_config.h). These can be sourced to any of the * profile counters as triggers. There are two methods of using the monitor sources * in a profile counter. * * - Event: The count value is incremented when a pulse event signal is seen by the -* counter. This type of monitoring is suitable when the monitoring source of -* interest needs to count the discrete events (such as the number of flash read +* counter. This type of monitoring is suitable when the monitoring source of +* interest needs to count the discrete events (such as the number of flash read * accesses) happening in the measurement window. * * - Duration: The count value is incremented at every clock edge while the monitor @@ -65,7 +65,7 @@ * duration must be expressed as number of clock cycles in the measurement window. * * Many of the available monitor sources are suitable for event type monitoring. -* Using a duration type on these signals may not give valuable information. Review +* Using a duration type on these signals may not give valuable information. Review * the device TRM for more information on the monitor sources and detail on how they * should be used. * @@ -82,20 +82,20 @@ * toggled. When the measurement window ends, the energy contribution caused by the * GPIO toggle can be incorporated into the final calculation. * -* - Event measurement: Monitored events happening in a measurement window can be +* - Event measurement: Monitored events happening in a measurement window can be * used to increment a profile counter. This gives the activity numbers, which can * then be multiplied by the instantaneous power numbers associated with the source -* to give the average energy consumption (Energy = Power x time). For example, the +* to give the average energy consumption (Energy = Power x time). For example, the * energy consumed by an Operating System (OS) task can be estimated by monitoring * the processor's active cycle count (E.g. CPUSS_MONITOR_CM4) and the flash read -* accesses (CPUSS_MONITOR_FLASH). Note that these activity numbers can also be +* accesses (CPUSS_MONITOR_FLASH). Note that these activity numbers can also be * timestamped using the continuous measurement method to differentiate between the * different task switches. The activity numbers are then multiplied by the associated * processor and flash access power numbers to give the average energy consumed by * that task. * -* - Duration measurement: A peripheral event such as the SMIF select signal can be -* used by a profile counter to measure the time spent on XIP communication through the +* - Duration measurement: A peripheral event such as the SMIF select signal can be +* used by a profile counter to measure the time spent on XIP communication through the * SPI interface. This activity number can then be multiplied by the power associated * with that activity to give the average energy consumed by that block during the * measurement window. This type of monitoring should be performed only for signals @@ -104,16 +104,16 @@ * monitoring model. However tracking the activity of signals such the BLE radio * should be done using the duration measurement method. * -* - Low power measurement: The profile counters do not support measurement during chip +* - Low power measurement: The profile counters do not support measurement during chip * Deep Sleep, Hibernate, and off states. I.e. the profile counters are meant for active * run-time measurements only. To measure the time spent in low power modes (LPM), -* a real-time clock (RTC) should be used. Take a timestamp before LPM entry and a +* a real-time clock (RTC) should be used. Take a timestamp before LPM entry and a * timestamp upon LPM exit in a continuous measurement model. Then multiply the difference * by the appropriate LPM power numbers. * * \subsection group_profile_usage Driver Usage * -* At the highest level, the energy profiler must perform the following steps to +* At the highest level, the energy profiler must perform the following steps to * obtain a measurement: * * 1. Initialize the profile hardware block. @@ -133,15 +133,15 @@ * Configuration Considerations for more information. * * \section group_profile_configuration Configuration Considerations -* -* Each counter is a 32-bit register that counts either a number of clock cycles, +* +* Each counter is a 32-bit register that counts either a number of clock cycles, * or a number of events. Overflowing the 32-bit register is possible. To address * this issue, the driver implements a 32-bit overflow counter. Combined with the 32-bit -* register, this gives a 64-bit counter for each monitored source. +* register, this gives a 64-bit counter for each monitored source. * -* When an overflow occurs, the profile hardware generates an interrupt. The interrupt is +* When an overflow occurs, the profile hardware generates an interrupt. The interrupt is * configured using the SysInt driver, where the sample interrupt handler Cy_Profile_ISR() -* can be used as the ISR. The ISR increments the overflow counter for each profiling counter +* can be used as the ISR. The ISR increments the overflow counter for each profiling counter * and clears the interrupt. * * \section group_profile_more_information More Information @@ -174,6 +174,11 @@ * * * +* +* +* +* +* * * * @@ -186,7 +191,7 @@ * * -* * * @@ -240,10 +245,10 @@ extern "C" { #define CY_PROFILE_ID CY_PDL_DRV_ID(0x1EU) /** Start profiling command for the CMD register */ -#define CY_PROFILE_START_TR 1UL +#define CY_PROFILE_START_TR 1UL /** Stop profiling command for the CMD register */ -#define CY_PROFILE_STOP_TR 2UL +#define CY_PROFILE_STOP_TR 2UL /** Command to clear all counter registers to 0 */ #define CY_PROFILE_CLR_ALL_CNT 0x100UL @@ -282,7 +287,7 @@ extern "C" { /** * Profile counter reference clock source. Used when duration monitoring. */ -typedef enum +typedef enum { CY_PROFILE_CLK_TIMER = 0, /**< Timer clock (TimerClk) */ CY_PROFILE_CLK_IMO = 1, /**< Internal main oscillator (IMO) */ @@ -295,14 +300,14 @@ typedef enum /** * Monitor method type. */ -typedef enum +typedef enum { CY_PROFILE_EVENT = 0, /**< Count (edge-detected) module events */ CY_PROFILE_DURATION = 1, /**< Count (level) duration in clock cycles */ } cy_en_profile_duration_t; /** Profiler status codes */ -typedef enum +typedef enum { CY_PROFILE_SUCCESS = 0x00U, /**< Operation completed successfully */ CY_PROFILE_BAD_PARAM = CY_PROFILE_ID | CY_PDL_STATUS_ERROR | 1UL /**< Invalid input parameters */ @@ -328,14 +333,14 @@ typedef struct cy_en_profile_duration_t cntDuration; /**< 0 = event; 1 = duration */ cy_en_profile_ref_clk_t refClkSel; /**< The reference clock used by the counter */ en_ep_mon_sel_t monSel; /**< The monitor signal to be observed by the counter */ -} cy_stc_profile_ctr_ctl_t; +} cy_stc_profile_ctr_ctl_t; /** * Software structure for holding a profile counter status and configuration information. */ typedef struct { - uint8_t ctrNum; /**< Profile counter number */ + uint8_t ctrNum; /**< Profile counter number */ uint8_t used; /**< 0 = available; 1 = used */ cy_stc_profile_ctr_ctl_t ctlRegVals; /**< Initial counter CTL register settings */ PROFILE_CNT_STRUCT_Type * cntAddr; /**< Base address of the counter instance registers */ @@ -384,12 +389,12 @@ __STATIC_INLINE uint32_t Cy_Profile_IsProfiling(void); * Function Name: Cy_Profile_Init ****************************************************************************//** * -* Initializes and enables the profile hardware. +* Initializes and enables the profile hardware. * -* This function must be called once when energy profiling is desired. The +* This function must be called once when energy profiling is desired. The * operation does not start a profiling session. * -* \note The profile interrupt must also be configured. \ref Cy_Profile_ISR() +* \note The profile interrupt must also be configured. \ref Cy_Profile_ISR() * can be used as its handler. * * \funcusage @@ -398,7 +403,7 @@ __STATIC_INLINE uint32_t Cy_Profile_IsProfiling(void); *******************************************************************************/ __STATIC_INLINE void Cy_Profile_Init(void) { - PROFILE_CTL = _VAL2FLD(PROFILE_CTL_ENABLED, 1UL/*enabled */) | + PROFILE_CTL = _VAL2FLD(PROFILE_CTL_ENABLED, 1UL/*enabled */) | _VAL2FLD(PROFILE_CTL_WIN_MODE, 0UL/*start/stop mode*/); PROFILE_INTR_MASK = 0UL; /* clear all counter interrupt mask bits */ } @@ -408,7 +413,7 @@ __STATIC_INLINE void Cy_Profile_Init(void) * Function Name: Cy_Profile_DeInit ****************************************************************************//** * -* Clears the interrupt mask and disables the profile hardware. +* Clears the interrupt mask and disables the profile hardware. * * This function should be called when energy profiling is no longer desired. * diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_prot.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_prot.h index b4ba383adf..e477ea4fba 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_prot.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_prot.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_prot.h -* \version 1.30.2 +* \version 1.30.3 * * \brief * Provides an API declaration of the Protection Unit driver @@ -30,7 +30,7 @@ * The Protection Unit driver provides an API to configure the Memory Protection * Units (MPU), Shared Memory Protection Units (SMPU), and Peripheral Protection * Units (PPU). These are separate from the ARM Core MPUs and provide additional -* mechanisms for securing resource accesses. The Protection units address the +* mechanisms for securing resource accesses. The Protection units address the * following concerns in an embedded design: * - Security requirements: This includes the prevention of malicious attacks * to access secure memory or peripherals. @@ -38,14 +38,14 @@ * SW errors and random HW errors. It is important to enable failure analysis * to investigate the root cause of a safety violation. * -* The functions and other declarations used in this driver are in cy_prot.h. -* You can include cy_pdl.h (ModusToolbox only) to get access to all functions -* and declarations in the PDL. -* +* The functions and other declarations used in this driver are in cy_prot.h. +* You can include cy_pdl.h to get access to all functions +* and declarations in the PDL. +* * \section group_prot_protection_type Protection Types * -* Protection units are hardware configuration structures that control bus accesses -* to the resources that they protect. By combining these individual configuration +* Protection units are hardware configuration structures that control bus accesses +* to the resources that they protect. By combining these individual configuration * structures, a system is built to allow strict restrictions on the capabilities * of individual bus masters (e.g. CM0+, CM4, Crypt) and their operating modes. * This architecture can then be integrated into the overall security system @@ -54,16 +54,16 @@ * it must pass the evaluation performed for each category. These access evaluations * are prioritized, where MPU has the highest priority, followed by SMPU, followed * by PPU. i.e. if an SMPU and a PPU protect the same resource and if access is -* denied by the SMPU, then the PPU access evaluation is skipped. This can lead to a +* denied by the SMPU, then the PPU access evaluation is skipped. This can lead to a * denial-of-service scenario and the application should pay special attention in * taking ownership of the protection unit configurations. * * \subsection group_prot_memory_protection Memory Protection * * Memory access control for a bus master is controlled using an MPU. These are -* most often used to distinguish user and privileged accesses from a single bus -* master such as task switching in an OS/kernel. For ARM cores (CM0+, CM4), the -* core MPUs are used to perform this task. For other non-ARM bus masters such +* most often used to distinguish user and privileged accesses from a single bus +* master such as task switching in an OS/kernel. For ARM cores (CM0+, CM4), the +* core MPUs are used to perform this task. For other non-ARM bus masters such * as Crypto, MPU structs are available, which can be used in a similar manner * as the ARM core MPUs. These MPUs however must be configured by the ARM cores. * Other bus masters that do not have an MPU, such as DMA (DW), inherit the access @@ -81,10 +81,10 @@ * This protection effectively allows only those with correct bus master access * settings to read/write/execute the memory region. This type of protection * is used in general memory such as Flash and SRAM. Peripheral registers are -* best configured using the peripheral protection units instead. SMPU structs -* have a descending priority, where larger index struct has higher priority +* best configured using the peripheral protection units instead. SMPU structs +* have a descending priority, where larger index struct has higher priority * access evaluation over lower index structs. E.g. SMPU_STRUCT15 has higher priority -* than SMPU_STRUCT14 and its access will be evaluated before SMPU_STRUCT14. +* than SMPU_STRUCT14 and its access will be evaluated before SMPU_STRUCT14. * If both target the same memory, then the higher index (MPU_STRUCT15) will be * used, and the lower index (SMPU_STRUCT14) will be ignored. * @@ -94,7 +94,7 @@ * register accesses by bus masters. Four types of PPUs are available. * - Fixed Group (GR) PPUs are used to protect an entire peripheral MMIO group * from invalid bus master accesses. The MMIO grouping information and which -* resource belongs to which group is device specific and can be obtained +* resource belongs to which group is device specific and can be obtained * from the device technical reference manual (TRM). Group PPUs have the highest * priority in the PPU category. Therefore their access evaluations take precedence * over the other types of PPUs. @@ -103,17 +103,17 @@ * type of peripheral protection unit. Programmable PPUs have the second highest * priority and take precedence over Region PPUs and Slave PPUs. Similar to SMPUs, * higher index PROG PPUs have higher priority than lower indexes PROG PPUs. -* - Fixed Region (RG) PPUs are used to protect an entire peripheral slave -* instance from invalid bus master accesses. For example, TCPWM0, TCPWM1, +* - Fixed Region (RG) PPUs are used to protect an entire peripheral slave +* instance from invalid bus master accesses. For example, TCPWM0, TCPWM1, * SCB0, and SCB1, etc. Region PPUs have the third highest priority and take precedence * over Slave PPUs. * - Fixed Slave (SL) PPUs are used to protect specified regions of peripheral -* instances. For example, individual DW channel structs, SMPU structs, and +* instances. For example, individual DW channel structs, SMPU structs, and * IPC structs, etc. Slave PPUs have the lowest priority in the PPU category and * therefore are evaluated last. * * \section group_prot_protection_context Protection Context -* +* * Protection context (PC) attribute is present in all bus masters and is evaluated * when accessing memory protected by an SMPU or a PPU. There are no limitations * to how the PC values are allocated to the bus masters and this makes it @@ -140,11 +140,11 @@ * At that point, the only way to re-transition to PC=0 is through the defined * exception/interrupt handler. * -* \note Devices with CPUSS ver_2 have a hardware-controlled protection context -* update mechanism that allows only a single-entry point for transitioning -* into PC=0, 1, 2, and 3. The interrupt vector or the exception handler -* address can be assigned to the CPUSS.CM0_PC0_HANDLER, CPUSS.CM0_PC1_HANDLER, -* CPUSS.CM0_PC2_HANDLER or CPUSS.CM0_PC2_HANDLER register. Also, the control +* \note Devices with CPUSS ver_2 have a hardware-controlled protection context +* update mechanism that allows only a single-entry point for transitioning +* into PC=0, 1, 2, and 3. The interrupt vector or the exception handler +* address can be assigned to the CPUSS.CM0_PC0_HANDLER, CPUSS.CM0_PC1_HANDLER, +* CPUSS.CM0_PC2_HANDLER or CPUSS.CM0_PC2_HANDLER register. Also, the control * register CPUSS.CM0_PC_CTL of the CM0+ protection context must be set: * bit 0 - the valid field for CM0_PC0_HANDLER, * bit 1 - the valid field for CM0_PC1_HANDLER, @@ -166,12 +166,12 @@ * user and privileged modes is handled by updating its Control register or * by exception entries. Other bus masters such as Crypto have their own * user/privileged settings bit in the bus master control register. This is -* then controlled by the ARM cores. Bus masters that do not have +* then controlled by the ARM cores. Bus masters that do not have * user/privileged access controls, such as DMA, inherit their attributes * from the bus master that configured it. The user/privileged distinction * is used mainly in the MPUs for single bus master accesses but they can * also be used in all other protection units. -* - Secure/Non-secure access: The secure/non-secure attribute is another +* - Secure/Non-secure access: The secure/non-secure attribute is another * identifier to distinguish between two separate modes of operations. Much * like the user/privileged access, the secure/non-secure mode flag is present * in the bus master control register. The ARM core does not have this @@ -183,10 +183,10 @@ * both secure and non-secure regions, whereas a bus master with non-secure * attribute can only access non-secure regions. * - Protection Context access: Protection Context is an attribute -* that serves two purposes; To enter the hardware controlled secure PC=0 +* that serves two purposes; To enter the hardware controlled secure PC=0 * mode of operation from non-secure modes and to provide finer granularity * to the bus master access definitions. It is used in SMPU and PPU configuration -* to control which bus master protection context can access the resources +* to control which bus master protection context can access the resources * that they protect. * * \section group_prot_protection_structure Protection Structure @@ -195,7 +195,7 @@ * The exception to this rule is MPU structs, which only have the slave struct * equivalent. The protection units apply their access evaluations in a decreasing * index order. For example, if SMPU1 and SMPU2 both protect a specific memory region, -* the the higher index (SMPU2) will be evaluated first. In a secure system, the +* the the higher index (SMPU2) will be evaluated first. In a secure system, the * higher index protection structs would then provide the high level of security * and the lower indexes would provide the lower level of security. Refer to the * \ref group_prot_protection_type section for more information. @@ -210,41 +210,41 @@ * \subsubsection group_prot_slave_addr Slave Struct Address Definition * * - Address: For MPU, SMPU and PROG PPU, the address field is used to define -* the base memory region to apply the protection. This field has a dependency +* the base memory region to apply the protection. This field has a dependency * on the region size, which dictates the alignment of the protection unit. E.g. * if the region size is 64KB, the address field is aligned to 64KB. Hence -* the lowest bits [15:0] are ignored. For instance, if the address is defined +* the lowest bits [15:0] are ignored. For instance, if the address is defined * at 0x0800FFFF, the protection unit would apply its protection settings from -* 0x08000000. Thus alignment must be checked before defining the protection -* address. The address field for other PPUs are not used, as they are bound -* to their respective peripheral memory locations. +* 0x08000000. Thus alignment must be checked before defining the protection +* address. The address field for other PPUs are not used, as they are bound +* to their respective peripheral memory locations. * - Region Size: For MPU, SMPU and PROG PPU, the region size is used to define * the memory block size to apply the protection settings, starting from the * defined base address. It is also used to define the 8 sub-regions for the * chosen memory block. E.g. If the region size is 64KB, each subregion would * be 8KB. This information can then be used to disable the protection -* settings for select subregions, which gives finer granularity to the -* memory regions. PPUs do not have region size definitions as they are bound -* to their respective peripheral memory locations. +* settings for select subregions, which gives finer granularity to the +* memory regions. PPUs do not have region size definitions as they are bound +* to their respective peripheral memory locations. * - Subregions: The memory block defined by the address and region size fields * is divided into 8 (0 to 7) equally spaced subregions. The protection settings -* of the protection unit can be disabled for these subregions. E.g. for a -* given 64KB of memory block starting from address 0x08000000, disabling +* of the protection unit can be disabled for these subregions. E.g. for a +* given 64KB of memory block starting from address 0x08000000, disabling * subregion 0 would result in the protection settings not affecting the memory -* located between 0x08000000 to 0x08001FFF. PPUs do not have subregion -* definitions as they are bound to their respective peripheral memory locations. +* located between 0x08000000 to 0x08001FFF. PPUs do not have subregion +* definitions as they are bound to their respective peripheral memory locations. * * \subsubsection group_prot_slave_attr Slave Struct Attribute Definition * * - User Permission: Protection units can control the access restrictions -* of the read (R), write (W) and execute (X) (subject to their availability -* depending on the type of protection unit) operations on the memory block +* of the read (R), write (W) and execute (X) (subject to their availability +* depending on the type of protection unit) operations on the memory block * when the bus master is operating in user mode. PPU structs do not provide * execute attributes. * - Privileged Permission: Similar to the user permission, protection units can -* control the access restrictions of the read (R), write (W) and execute (X) -* (subject to their availability depending on the type of protection unit) -* operations on the memory block when the bus master is operating in +* control the access restrictions of the read (R), write (W) and execute (X) +* (subject to their availability depending on the type of protection unit) +* operations on the memory block when the bus master is operating in * privileged mode. PPU structs do not provide execute attributes. * - Secure/Non-secure: Applies the secure/non-secure protection settings to * the defined memory region. Secure protection allows only bus masters that @@ -268,7 +268,7 @@ * protection context values allowed by the protection unit. E.g. If SMPU1 is * configured to allow only PC=1 and PC=5, a bus master (such as CM4) must * be operating at PC=1 or PC=5 when accessing the protected memory region. -* +* * \subsection group_prot_master_struct Master Struct * * The master struct protects its slave struct in the protection unit. This @@ -286,10 +286,10 @@ * * \subsubsection group_prot_master_attr Master Struct Attribute Definition * -* - User Permission: Only the write (W) access attribute is allowed for +* - User Permission: Only the write (W) access attribute is allowed for * master structs, which controls whether a bus master operating in user * mode has the write access. -* - Privileged Permission: Only the write (W) access attribute is allowed for +* - Privileged Permission: Only the write (W) access attribute is allowed for * master structs, which controls whether a bus master operating in privileged * mode has the write access. * - Secure/Non-Secure: Same behavior as slave struct. @@ -314,15 +314,15 @@ * the protected memory. * * For example, by configuring the CM0+ bus master configuration to allow -* only protection contexts 2 and 3, the bus master will be able to -* set its protection context only to 2 or 3. During runtime, the CM0+ core -* can set its protection context to 2 by calling Cy_Prot_SetActivePC() +* only protection contexts 2 and 3, the bus master will be able to +* set its protection context only to 2 or 3. During runtime, the CM0+ core +* can set its protection context to 2 by calling Cy_Prot_SetActivePC() * and access all regions of protected memory that allow PC=2. A fault will * be triggered if a resource is protected with different protection settings. * -* Note that each protection unit is distinguished by its type (e.g. +* Note that each protection unit is distinguished by its type (e.g. * PROT_MPU_MPU_STRUCT_Type). The list of supported protection units can be -* obtained from the device definition header file. Choose a protection unit +* obtained from the device definition header file. Choose a protection unit * of interest, and call its corresponding Cy_Prot_ConfigStruct() function * with its software protection unit configuration structure populated. Then * enable the protection unit by calling the Cy_Prot_EnableStruct() function. @@ -335,17 +335,17 @@ * When a resource (memory/register) is accessed, it must pass evaluation of * all three protection unit categories in the following order: MPU->SMPU->PPU. * The application should ensure that a denial-of-service attack cannot be -* made on the PPU by the SMPU. For this reason, it is recommended that the +* made on the PPU by the SMPU. For this reason, it is recommended that the * application's security policy limit the ability for the non-secure client * from configuring the SMPUs. -* +* * Within each category, the priority hierarchy must be carefully considered * to ensure that a higher priority protection unit cannot be configured to * override the security configuration of a lower index protection unit. * Therefore if a lower index protection unit is configured, relevant higher -* priority indexes should be configured (or protected from unwanted +* priority indexes should be configured (or protected from unwanted * reconfiguration). E.g. If a PPU_SL is configured, PPU_RG and PPU_GR that -* overlaps with the protected registers should also be configured. SImilar +* overlaps with the protected registers should also be configured. SImilar * to SMPUs, it is recommended that the configuration of PPU_PROG be limited. * Otherwise they can be used to override the protection settings of PPU_RG * and PPU_SL structs. @@ -357,8 +357,8 @@ * exception entry in the CPUSS.CM0_PC0_HANDLER register. * * - SMPU 15 and 14 are configured and enabled to only allow PC=0 accesses at -* device boot. -* - PROG PPU 15, 14, 13 and 12 are configured to only allow PC=0 accesses at +* device boot. +* - PROG PPU 15, 14, 13 and 12 are configured to only allow PC=0 accesses at * device boot. * - GR PPU 0 and 2 are configured to only allow PC=0 accesses at device boot. * @@ -384,12 +384,23 @@ * * +* +* +* +* +* +* *
VersionChangesReason for Change
1.20.1Minor documentation updates.Documentation enhancement.
1.20Updated API function \ref Cy_Profile_GetSumWeightedCounts().Minor defect fixing: now the function supports the correct number of counters.
Added register access layer. Use register access macros instead * of direct register access using dereferenced pointers.Makes register access device-independent, so that the PDL does +* Makes register access device-independent, so that the PDL does * not need to be recompiled for each supported part number.
This piece of code is written for DW_V2_Type only and it will be never * executed for DW_V1_Type (which is a default build option for DW_Type).
19.13AThe # and ## operators should not be used.The ## preprocessor operator is used in macros to form the field mask.
* * \section group_prot_changelog Changelog * * * +* +* +* +* +* * * @@ -407,7 +418,7 @@ * * * -* * * @@ -426,13 +437,13 @@ * * -* * * * * * * @@ -500,7 +511,7 @@ extern "C" { /** * Prot Driver error codes */ -typedef enum +typedef enum { CY_PROT_SUCCESS = 0x00U, /**< Returned successful */ CY_PROT_BAD_PARAM = CY_PROT_ID | CY_PDL_STATUS_ERROR | 0x01U, /**< Bad parameter was passed */ @@ -512,7 +523,7 @@ typedef enum /** * User/Privileged permission */ -typedef enum +typedef enum { CY_PROT_PERM_DISABLED = 0x00U, /**< Read, Write and Execute disabled */ CY_PROT_PERM_R = 0x01U, /**< Read enabled */ @@ -527,7 +538,7 @@ typedef enum /** * Memory region size */ -typedef enum +typedef enum { CY_PROT_SIZE_4B = 1U, /**< 4 bytes */ CY_PROT_SIZE_8B = 2U, /**< 8 bytes */ @@ -601,7 +612,7 @@ enum cy_en_prot_subreg_t }; /** -* Protection context mask (PC_MASK) +* Protection context mask (PC_MASK) */ enum cy_en_prot_pcmask_t { @@ -625,7 +636,7 @@ enum cy_en_prot_pcmask_t /** * Request mode to get the SMPU or programmed PU structure */ -typedef enum +typedef enum { CY_PROT_REQMODE_HIGHPRIOR = 0U, /**< Request mode to return PU structure with highest priority */ CY_PROT_REQMODE_LOWPRIOR = 1U, /**< Request mode to return PU structure with lowest priority */ @@ -693,7 +704,7 @@ typedef enum #define CY_PROT_SMPU_PC_LIMIT_MASK ((uint32_t) 0xFFFFFFFFUL << (CY_PROT_PC_MAX - 1UL)) #define CY_PROT_PPU_PROG_PC_LIMIT_MASK ((uint32_t) 0xFFFFFFFFUL << (CY_PROT_PC_MAX - 1UL)) #define CY_PROT_PPU_FIXED_PC_LIMIT_MASK ((uint32_t) 0xFFFFFFFFUL << (CY_PROT_PC_MAX - 1UL)) - + #define CY_PROT_SMPU_ATT0_MASK ((uint32_t)~(PROT_SMPU_SMPU_STRUCT_ATT0_PC_MASK_0_Msk)) #define CY_PROT_SMPU_ATT1_MASK ((uint32_t)~(PROT_SMPU_SMPU_STRUCT_ATT1_UX_Msk \ | PROT_SMPU_SMPU_STRUCT_ATT1_PX_Msk \ @@ -777,10 +788,10 @@ typedef enum ((permission) == CY_PROT_PERM_R) || \ ((permission) == CY_PROT_PERM_W) || \ ((permission) == CY_PROT_PERM_RW)) - + #define CY_PROT_IS_FIXED_MS_MS_PERM_VALID(permission) (((permission) == CY_PROT_PERM_R) || \ - ((permission) == CY_PROT_PERM_RW)) - + ((permission) == CY_PROT_PERM_RW)) + #define CY_PROT_IS_FIXED_SL_PERM_VALID(permission) (((permission) == CY_PROT_PERM_DISABLED) || \ ((permission) == CY_PROT_PERM_R) || \ @@ -848,7 +859,7 @@ typedef enum #define CY_PROT_IS_SMPU_REQ_MODE_VALID(reqMode) (((reqMode) == CY_PROT_REQMODE_HIGHPRIOR) || \ ((reqMode) == CY_PROT_REQMODE_LOWPRIOR) || \ ((reqMode) == CY_PROT_REQMODE_INDEX)) - + #define CY_PROT_IS_PPU_PROG_REQ_MODE_VALID(reqMode) (((reqMode) == CY_PROT_REQMODE_HIGHPRIOR) || \ ((reqMode) == CY_PROT_REQMODE_LOWPRIOR) || \ ((reqMode) == CY_PROT_REQMODE_INDEX)) @@ -873,7 +884,7 @@ typedef enum */ /** Configuration structure for MPU Struct initialization */ -typedef struct +typedef struct { uint32_t* address; /**< Base address of the memory region */ cy_en_prot_size_t regionSize; /**< Size of the memory region */ @@ -884,7 +895,7 @@ typedef struct } cy_stc_mpu_cfg_t; /** Configuration structure for SMPU struct initialization */ -typedef struct +typedef struct { uint32_t* address; /**< Base address of the memory region (Only applicable to slave) */ cy_en_prot_size_t regionSize; /**< Size of the memory region (Only applicable to slave) */ @@ -897,7 +908,7 @@ typedef struct } cy_stc_smpu_cfg_t; /** Configuration structure for Programmable (PROG) PPU (PPU_PR) struct initialization */ -typedef struct +typedef struct { uint32_t* address; /**< Base address of the memory region (Only applicable to slave) */ cy_en_prot_size_t regionSize; /**< Size of the memory region (Only applicable to slave) */ @@ -910,7 +921,7 @@ typedef struct } cy_stc_ppu_prog_cfg_t; /** Configuration structure for Fixed Group (GR) PPU (PPU_GR) struct initialization */ -typedef struct +typedef struct { cy_en_prot_perm_t userPermission; /**< User permissions for the region */ cy_en_prot_perm_t privPermission; /**< Privileged permissions for the region */ @@ -920,7 +931,7 @@ typedef struct } cy_stc_ppu_gr_cfg_t; /** Configuration structure for Fixed Slave (SL) PPU (PPU_SL) struct initialization */ -typedef struct +typedef struct { cy_en_prot_perm_t userPermission; /**< User permissions for the region */ cy_en_prot_perm_t privPermission; /**< Privileged permissions for the region */ @@ -930,7 +941,7 @@ typedef struct } cy_stc_ppu_sl_cfg_t; /** Configuration structure for Fixed Region (RG) PPU (PPU_RG) struct initialization */ -typedef struct +typedef struct { cy_en_prot_perm_t userPermission; /**< User permissions for the region */ cy_en_prot_perm_t privPermission; /**< Privileged permissions for the region */ @@ -1082,7 +1093,7 @@ cy_en_prot_status_t Cy_Prot_DisablePpuFixedRgSlaveStruct(PERI_GR_PPU_RG_Type* ba * This function disables both the master and slave parts of a protection unit. * * \param base -* The base address for the SMPU structure to be disabled. +* The base address for the SMPU structure to be disabled. * * \return * Status of the function call. @@ -1122,11 +1133,11 @@ __STATIC_INLINE cy_en_prot_status_t Cy_Prot_DisableSmpuStruct(PROT_SMPU_SMPU_STR * This function disables both the master and slave parts of a protection unit. * * \note -* This functions has an effect only on devices with PERI IP version 1. Refer +* This functions has an effect only on devices with PERI IP version 1. Refer * to the device datasheet for information about PERI HW IP version. * * \param base -* The base address for the Programmable PU structure to be disabled. +* The base address for the Programmable PU structure to be disabled. * * \return * Status of the function call. diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_rtc.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_rtc.h index f8b90ae8a7..6b78e92c5d 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_rtc.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_rtc.h @@ -1,8 +1,8 @@ /***************************************************************************//** * \file cy_rtc.h -* \version 2.30 +* \version 2.30.1 * -* This file provides constants and parameter values for the APIs for the +* This file provides constants and parameter values for the APIs for the * Real-Time Clock (RTC). * ******************************************************************************** @@ -28,17 +28,17 @@ * \addtogroup group_rtc * \{ * -* The Real-Time Clock (RTC) driver provides an application interface +* The Real-Time Clock (RTC) driver provides an application interface * for keeping track of time and date. * -* The functions and other declarations used in this driver are in cy_rtc.h. -* You can include cy_pdl.h (ModusToolbox only) to get access to all functions -* and declarations in the PDL. +* The functions and other declarations used in this driver are in cy_rtc.h. +* You can include cy_pdl.h to get access to all functions +* and declarations in the PDL. * -* Use the RTC driver when the system requires the current time or date. You -* can also use the RTC when you do not need the current time and date but you +* Use the RTC driver when the system requires the current time or date. You +* can also use the RTC when you do not need the current time and date but you * do need accurate timing of events with one-second resolution. -* +* * The RTC driver provides these features: * * Different hour format support. * * Multiple alarm function (two-alarms). @@ -46,125 +46,125 @@ * * Automatic leap year compensation. * * Option to drive the RTC by an external 50 Hz or 60 Hz clock source * -* The RTC driver provides access to the HW real-time clock. The HW RTC is -* located in the Backup domain. You need to choose the clock source for the -* Backup domain using the Cy_SysClk_ClkBakSetSource() function. If the clock -* for the Backup domain is set and enabled, the RTC automatically +* The RTC driver provides access to the HW real-time clock. The HW RTC is +* located in the Backup domain. You need to choose the clock source for the +* Backup domain using the Cy_SysClk_ClkBakSetSource() function. If the clock +* for the Backup domain is set and enabled, the RTC automatically * starts counting. * -* The RTC driver keeps track of second, minute, hour, day of the week, day of +* The RTC driver keeps track of second, minute, hour, day of the week, day of * the month, month, and year. * -* DST may be enabled and supports any start and end date. The start and end -* dates can be a fixed date (like 24 March) or a relative date (like the +* DST may be enabled and supports any start and end date. The start and end +* dates can be a fixed date (like 24 March) or a relative date (like the * second Sunday in March). * -* The RTC has two alarms that you can configure to generate an interrupt. +* The RTC has two alarms that you can configure to generate an interrupt. * You specify the match value for the time when you want the alarm to occur. -* Your interrupt handler then handles the response. The alarm flexibility -* supports periodic alarms (such as every minute), or a single alarm +* Your interrupt handler then handles the response. The alarm flexibility +* supports periodic alarms (such as every minute), or a single alarm * (13:45 on 28 September, 2043). * * Clock Source * * The Backup domain can be driven by: * * Watch-crystal oscillator (WCO). This is a high-accuracy oscillator that is -* suitable for RTC applications and requires a 32.768 kHz external crystal -* populated on the application board. The WCO can be supplied by Backup domain +* suitable for RTC applications and requires a 32.768 kHz external crystal +* populated on the application board. The WCO can be supplied by Backup domain * and therefore can run without Vddd/Vccd present. This can be used to wake the * chip from Hibernate mode. * -* * The Internal Low-speed Oscillator (ILO) routed from Clk_LF or directly -* (as alternate backup domain clock source). Depending on the device power -* mode the alternate backup domain clock source is set. For example, for +* * The Internal Low-speed Oscillator (ILO) routed from Clk_LF or directly +* (as alternate backup domain clock source). Depending on the device power +* mode the alternate backup domain clock source is set. For example, for * Deep Sleep mode the ILO is routed through Clk_LF. But for Hibernate * power mode the ILO is set directly. Note that, the ILO should be configured to * work in the Hibernate mode. For more info refer to the \ref group_sysclk * driver. The ILO is a low-accuracy RC-oscillator that does not require -* any external elements on the board. Its poor accuracy (+/- 30%) means it is +* any external elements on the board. Its poor accuracy (+/- 30%) means it is * less useful for the RTC. However, current can be supplied by an internal * power supply (Vback) and therefore it can run without Vddd/Vccd present. -* This also can be used to wake the chip from Hibernate mode using RTC alarm +* This also can be used to wake the chip from Hibernate mode using RTC alarm * interrupt. For more details refer to \ref group_syspm driver description. * -* * The Precision Internal Low-speed Oscillator (PILO), routed from Clk_LF +* * The Precision Internal Low-speed Oscillator (PILO), routed from Clk_LF * (alternate backup domain clock source). This is an RC-oscillator (ILO) that -* can achieve accuracy of +/- 2% with periodic calibration. It is not expected -* to be accurate enough for good RTC capability. The PILO requires -* Vddd/Vccd present. It can be used in modes down to Deep Sleep, but ceases to +* can achieve accuracy of +/- 2% with periodic calibration. It is not expected +* to be accurate enough for good RTC capability. The PILO requires +* Vddd/Vccd present. It can be used in modes down to Deep Sleep, but ceases to * function in Hibernate mode. * -* * External 50 Hz or 60 Hz sine-wave clock source or 32.768 kHz square clock +* * External 50 Hz or 60 Hz sine-wave clock source or 32.768 kHz square clock * source. -* For example, the wall AC frequency can be the clock source. Such a clock +* For example, the wall AC frequency can be the clock source. Such a clock * source can be used if the external 32.768 kHz WCO is absent from the board. -* For more details, refer to the Cy_RTC_SelectFrequencyPrescaler() function +* For more details, refer to the Cy_RTC_SelectFrequencyPrescaler() function * description. * -* The WCO is the recommended clock source for the RTC, if it is present -* in design. For setting the Backup domain clock source, refer to the +* The WCO is the recommended clock source for the RTC, if it is present +* in design. For setting the Backup domain clock source, refer to the * \ref group_sysclk driver. * -* \note If the WCO is enabled, it should source the Backup domain directly. -* Do not route the WCO through the Clk_LF. This is because Clk_LF is not +* \note If the WCO is enabled, it should source the Backup domain directly. +* Do not route the WCO through the Clk_LF. This is because Clk_LF is not * available in all low-power modes. * * \section group_rtc_section_configuration Configuration Considerations * -* Before RTC set up, ensure that the Backup domain is clocked with the desired +* Before RTC set up, ensure that the Backup domain is clocked with the desired * clock source. * -* To set up an RTC, provide the configuration parameters in the -* cy_stc_rtc_config_t structure. Then call Cy_RTC_Init(). You can also set the -* date and time at runtime. Call Cy_RTC_SetDateAndTime() using the filled -* cy_stc_rtc_config_t structure, or call Cy_RTC_SetDateAndTimeDirect() with -* valid time and date values. +* To set up an RTC, provide the configuration parameters in the +* cy_stc_rtc_config_t structure. Then call Cy_RTC_Init(). You can also set the +* date and time at runtime. Call Cy_RTC_SetDateAndTime() using the filled +* cy_stc_rtc_config_t structure, or call Cy_RTC_SetDateAndTimeDirect() with +* valid time and date values. * * RTC Interrupt Handling * -* The RTC driver provides three interrupt handler functions: -* Cy_RTC_Alarm1Interrupt(), Cy_RTC_Alarm2Interrupt(), and -* Cy_RTC_CenturyInterrupt(). All three functions are blank functions with +* The RTC driver provides three interrupt handler functions: +* Cy_RTC_Alarm1Interrupt(), Cy_RTC_Alarm2Interrupt(), and +* Cy_RTC_CenturyInterrupt(). All three functions are blank functions with * the WEAK attribute. For any interrupt you use, redefine the interrupt handler * in your source code. * -* When an interrupt occurs, call the Cy_RTC_Interrupt() function. The RTC -* hardware provides a single interrupt line to the NVIC for the three RTC -* interrupts. This function checks the interrupt register to determine which -* interrupt (out of the three) was generated. It then calls the +* When an interrupt occurs, call the Cy_RTC_Interrupt() function. The RTC +* hardware provides a single interrupt line to the NVIC for the three RTC +* interrupts. This function checks the interrupt register to determine which +* interrupt (out of the three) was generated. It then calls the * appropriate handler. * -* \warning The Cy_RTC_Alarm2Interrupt() is not called if the DST feature is -* enabled. If DST is enabled, the Cy_RTC_Interrupt() function redirects that +* \warning The Cy_RTC_Alarm2Interrupt() is not called if the DST feature is +* enabled. If DST is enabled, the Cy_RTC_Interrupt() function redirects that * interrupt to manage daylight savings time using Cy_RTC_DstInterrupt(). -* In general, the RTC interrupt handler function the Cy_RTC_DstInterrupt() +* In general, the RTC interrupt handler function the Cy_RTC_DstInterrupt() * function is called instead of Cy_RTC_Alarm2Interrupt(). * * For RTC interrupt handling, the user should: -* -# Implement strong interrupt handling function(s) for the required events -* (see above). If DST is enabled, then Alarm2 is not available. The DST handler +* -# Implement strong interrupt handling function(s) for the required events +* (see above). If DST is enabled, then Alarm2 is not available. The DST handler * is built into the PDL. -* -# Implement an RTC interrupt handler and call Cy_RTC_Interrupt() +* -# Implement an RTC interrupt handler and call Cy_RTC_Interrupt() * from there. * -# Configure the RTC interrupt: -* - Set the mask for RTC required interrupt using +* - Set the mask for RTC required interrupt using * Cy_RTC_SetInterruptMask(). -* - Initialize the RTC interrupt by setting priority and the RTC interrupt +* - Initialize the RTC interrupt by setting priority and the RTC interrupt * vector using the Cy_SysInt_Init() function. * - Enable the RTC interrupt using the CMSIS core function NVIC_EnableIRQ(). * * Alarm functionality * -* To set up an alarm, enable the required RTC interrupt. Then provide the -* configuration parameters in the cy_stc_rtc_alarm_t structure. You enable -* any item you want matched, and provide a match value. You disable any other. -* You do not need to set match values for disabled elements, as they are -* ignored. -* \note The alarm itself must be enabled in this structure. When a match +* To set up an alarm, enable the required RTC interrupt. Then provide the +* configuration parameters in the cy_stc_rtc_alarm_t structure. You enable +* any item you want matched, and provide a match value. You disable any other. +* You do not need to set match values for disabled elements, as they are +* ignored. +* \note The alarm itself must be enabled in this structure. When a match * occurs, the alarm is triggered and your interrupt handler is called. * -* An example is the best way to explain how this works. If you want an alarm -* on every hour, then in the cy_stc_rtc_alarm_t structure, you provide +* An example is the best way to explain how this works. If you want an alarm +* on every hour, then in the cy_stc_rtc_alarm_t structure, you provide * these values: * * Alarm_1.sec = 0u \n @@ -176,44 +176,44 @@ * Alarm_1.dateEn = CY_RTC_ALARM_DISABLE \n * Alarm_1.monthEn = CY_RTC_ALARM_DISABLE \n * Alarm_1.almEn = CY_RTC_ALARM_ENABLE \n -* -* With this setup, every time both the second and minute are zero, Alarm1 is -* asserted. That happens once per hour. Note that, counterintuitively, to have -* an alarm every hour, Alarm_1.hourEn is disabled. This is disabled because +* +* With this setup, every time both the second and minute are zero, Alarm1 is +* asserted. That happens once per hour. Note that, counterintuitively, to have +* an alarm every hour, Alarm_1.hourEn is disabled. This is disabled because * for an hourly alarm you do not match the value of the hour. * -* After cy_stc_rtc_alarm_t structure is filled, call the -* Cy_RTC_SetAlarmDateAndTime(). The alarm can also be set without using the -* cy_stc_rtc_alarm_t structure. Call Cy_RTC_SetAlarmDateAndTimeDirect() with +* After cy_stc_rtc_alarm_t structure is filled, call the +* Cy_RTC_SetAlarmDateAndTime(). The alarm can also be set without using the +* cy_stc_rtc_alarm_t structure. Call Cy_RTC_SetAlarmDateAndTimeDirect() with * valid values. * * The DST Feature * -* The DST feature is managed by the PDL using the RTC Alarm2 interrupt. -* Therefore, you cannot have both DST enabled and use the Alarm2 interrupt. +* The DST feature is managed by the PDL using the RTC Alarm2 interrupt. +* Therefore, you cannot have both DST enabled and use the Alarm2 interrupt. * * To set up the DST, route the RTC interrupt to NVIC: * -* -# Initialize the RTC interrupt by setting priority and the RTC interrupt +* -# Initialize the RTC interrupt by setting priority and the RTC interrupt * vector using Cy_SysInt_Init(). * -# Enable the RTC interrupt using the CMSIS core function NVIC_EnableIRQ(). -* -* After this, provide the configuration parameters in the -* cy_stc_rtc_dst_t structure. This structure consists of two -* cy_stc_rtc_dst_format_t structures, one for DST Start time and one for +* +* After this, provide the configuration parameters in the +* cy_stc_rtc_dst_t structure. This structure consists of two +* cy_stc_rtc_dst_format_t structures, one for DST Start time and one for * DST Stop time. You also specify whether these times are absolute or relative. -* -* After the cy_stc_rtc_dst_t structure is filled, call Cy_RTC_EnableDstTime() +* +* After the cy_stc_rtc_dst_t structure is filled, call Cy_RTC_EnableDstTime() * * \section group_rtc_lp Low Power Support -* The RTC provides the callback functions to facilitate -* the low-power mode transition. The callback -* \ref Cy_RTC_DeepSleepCallback must be called during execution -* of \ref Cy_SysPm_CpuEnterDeepSleep, \ref Cy_RTC_HibernateCallback must be -* called during execution of \ref Cy_SysPm_SystemEnterHibernate. -* To trigger the callback execution, the callback must be registered -* before calling the mode transition function. -* Refer to \ref group_syspm driver for more +* The RTC provides the callback functions to facilitate +* the low-power mode transition. The callback +* \ref Cy_RTC_DeepSleepCallback must be called during execution +* of \ref Cy_SysPm_CpuEnterDeepSleep, \ref Cy_RTC_HibernateCallback must be +* called during execution of \ref Cy_SysPm_SystemEnterHibernate. +* To trigger the callback execution, the callback must be registered +* before calling the mode transition function. +* Refer to \ref group_syspm driver for more * information about low-power mode transitions. * * \section group_rtc_section_more_information More Information @@ -228,13 +228,18 @@ *
VersionChangesReason for Change
1.30.3Minor documentation updates.Documentation enhancement.
1.30.2Clarified the description of the next API functions: \ref Cy_Prot_ConfigPpuProgMasterAtt,\n * \ref Cy_Prot_ConfigPpuProgSlaveAtt, \ref Cy_Prot_ConfigPpuFixedMasterAtt, \ref Cy_Prot_ConfigPpuFixedSlaveAtt.
1.20Flattened the organization of the driver source code into the single +* Flattened the organization of the driver source code into the single * source directory and the single include directory.Driver library directory-structure simplification.
Added register access layer. Use register access macros instead * of direct register access using dereferenced pointers.Makes register access device-independent, so that the PDL does +* Makes register access device-independent, so that the PDL does * not need to be recompiled for each supported part number.
1.10Added input parameter validation to the API functions.
-* cy_en_prot_pcmask_t, cy_en_prot_subreg_t and cy_en_prot_pc_t +* cy_en_prot_pcmask_t, cy_en_prot_subreg_t and cy_en_prot_pc_t * types are set to typedef enum		Improved debugging capability
* * +* +* +* +* +* * -* -* @@ -246,7 +251,7 @@ * * * -* * @@ -254,7 +259,7 @@ * * -* * * @@ -263,27 +268,27 @@ * * * -* -* * * * * * @@ -376,28 +381,28 @@ typedef enum cy_en_rtc_alarm } cy_en_rtc_alarm_t; /** This enumeration is used to set/get hours format */ -typedef enum +typedef enum { CY_RTC_24_HOURS, /**< The 24 hour format */ CY_RTC_12_HOURS /**< The 12 hour (AM/PM) format */ } cy_en_rtc_hours_format_t; /** Enumeration to configure the RTC Write register */ -typedef enum +typedef enum { CY_RTC_WRITE_DISABLED, /**< Writing the RTC is disabled */ CY_RTC_WRITE_ENABLED /**< Writing the RTC is enabled */ } cy_en_rtc_write_status_t; /** Enumeration used to set/get DST format */ -typedef enum +typedef enum { CY_RTC_DST_RELATIVE, /**< Relative DST format */ CY_RTC_DST_FIXED /**< Fixed DST format */ } cy_en_rtc_dst_format_t; /** Enumeration to indicate the AM/PM period of day */ -typedef enum +typedef enum { CY_RTC_AM, /**< AM period of day */ CY_RTC_PM /**< PM period of day */ @@ -422,7 +427,7 @@ typedef enum */ /** -* This is the data structure that is used to configure the rtc time +* This is the data structure that is used to configure the rtc time * and date values. */ typedef struct cy_stc_rtc_config @@ -431,14 +436,14 @@ typedef struct cy_stc_rtc_config uint32_t sec; /**< Seconds value, range [0-59] */ uint32_t min; /**< Minutes value, range [0-59] */ uint32_t hour; /**< Hour, range depends on hrFormat, if hrFormat = CY_RTC_24_HOURS, range [0-23]; - If hrFormat = CY_RTC_12_HOURS, range [1-12] and appropriate AM/PM day + If hrFormat = CY_RTC_12_HOURS, range [1-12] and appropriate AM/PM day period should be set (amPm) */ cy_en_rtc_am_pm_t amPm; /**< AM/PM hour period, see \ref cy_en_rtc_am_pm_t. - This element is actual when hrFormat = CY_RTC_12_HOURS. The firmware + This element is actual when hrFormat = CY_RTC_12_HOURS. The firmware ignores this element if hrFormat = CY_RTC_24_HOURS */ cy_en_rtc_hours_format_t hrFormat; /**< Hours format, see \ref cy_en_rtc_hours_format_t */ uint32_t dayOfWeek; /**< Day of the week, range [1-7], see \ref group_rtc_day_of_the_week */ - + /* Date information */ uint32_t date; /**< Date of month, range [1-31] */ uint32_t month; /**< Month, range [1-12]. See \ref group_rtc_month */ @@ -449,34 +454,34 @@ typedef struct cy_stc_rtc_config typedef struct cy_stc_rtc_alarm { /* Alarm time information */ - uint32_t sec; /**< Alarm seconds, range [0-59]. - The appropriate ALARMX interrupt is be asserted on matching with this + uint32_t sec; /**< Alarm seconds, range [0-59]. + The appropriate ALARMX interrupt is be asserted on matching with this value if secEn is previous enabled (secEn = 1) */ cy_en_rtc_alarm_enable_t secEn; /**< Enable alarm on seconds matching, see \ref cy_en_rtc_alarm_enable_t. */ - uint32_t min; /**< Alarm minutes, range [0-59]. + uint32_t min; /**< Alarm minutes, range [0-59]. The appropriate ALARMX interrupt is be asserted on matching with this value if minEn is previous enabled (minEn = 1) */ cy_en_rtc_alarm_enable_t minEn; /**< Enable alarm on minutes matching, see \ref cy_en_rtc_alarm_enable_t. */ uint32_t hour; /**< Alarm hours, range [0-23] - The appropriate ALARMX interrupt is be asserted on matching with this + The appropriate ALARMX interrupt is be asserted on matching with this value if hourEn is previous enabled (hourEn = 1) */ cy_en_rtc_alarm_enable_t hourEn; /**< Enable alarm on hours matching, see \ref cy_en_rtc_alarm_enable_t. */ uint32_t dayOfWeek; /**< Alarm day of the week, range [1-7] The appropriate ALARMX interrupt is be asserted on matching with this value if dayOfWeek is previous enabled (dayOfWeekEn = 1) */ - cy_en_rtc_alarm_enable_t dayOfWeekEn; /**< Enable alarm on day of the week matching, + cy_en_rtc_alarm_enable_t dayOfWeekEn; /**< Enable alarm on day of the week matching, see \ref cy_en_rtc_alarm_enable_t */ /* Alarm date information */ - uint32_t date; /**< Alarm date, range [1-31]. - The appropriate ALARMX interrupt is be asserted on matching with this + uint32_t date; /**< Alarm date, range [1-31]. + The appropriate ALARMX interrupt is be asserted on matching with this value if dateEn is previous enabled (dateEn = 1) */ cy_en_rtc_alarm_enable_t dateEn; /**< Enable alarm on date matching, see \ref cy_en_rtc_alarm_enable_t. */ - uint32_t month; /**< Alarm Month, range [1-12]. + uint32_t month; /**< Alarm Month, range [1-12]. The appropriate ALARMX interrupt is be asserted on matching with this value if dateEn is previous enabled (dateEn = 1) */ cy_en_rtc_alarm_enable_t monthEn; /**< Enable alarm on month matching, see \ref cy_en_rtc_alarm_enable_t. */ @@ -493,21 +498,21 @@ typedef struct cy_stc_rtc_alarm */ typedef struct { - cy_en_rtc_dst_format_t format; /**< DST format. See /ref cy_en_rtc_dst_format_t. + cy_en_rtc_dst_format_t format; /**< DST format. See /ref cy_en_rtc_dst_format_t. Based on this value other structure elements should be filled or could be ignored */ uint32_t hour; /**< Should be filled for both format types. Hour is always presented in 24hour format, range[0-23] */ - uint32_t dayOfMonth; /**< Day of Month, range[1-31]. This element should be filled if + uint32_t dayOfMonth; /**< Day of Month, range[1-31]. This element should be filled if format = CY_RTC_DST_FIXED. Firmware calculates this value in condition that format = CY_RTC_DST_RELATIVE is selected */ - uint32_t weekOfMonth; /**< Week of month, range[1-6]. This element should be filled if + uint32_t weekOfMonth; /**< Week of month, range[1-6]. This element should be filled if format = CY_RTC_DST_RELATIVE. - Firmware calculates dayOfMonth value based on weekOfMonth + Firmware calculates dayOfMonth value based on weekOfMonth and dayOfWeek values */ - uint32_t dayOfWeek; /**< Day of the week, this element should be filled in condition that - format = CY_RTC_DST_RELATIVE. Range[1- 7], - see \ref group_rtc_day_of_the_week. Firmware calculates dayOfMonth value + uint32_t dayOfWeek; /**< Day of the week, this element should be filled in condition that + format = CY_RTC_DST_RELATIVE. Range[1- 7], + see \ref group_rtc_day_of_the_week. Firmware calculates dayOfMonth value based on dayOfWeek and weekOfMonth values */ uint32_t month; /**< Month value, range[1-12], see \ref group_rtc_month. This value should be filled for both format types */ @@ -539,7 +544,7 @@ typedef struct cy_en_rtc_status_t Cy_RTC_Init(cy_stc_rtc_config_t const *config); cy_en_rtc_status_t Cy_RTC_SetDateAndTime(cy_stc_rtc_config_t const *dateTime); void Cy_RTC_GetDateAndTime(cy_stc_rtc_config_t *dateTime); -cy_en_rtc_status_t Cy_RTC_SetDateAndTimeDirect(uint32_t sec, uint32_t min, uint32_t hour, +cy_en_rtc_status_t Cy_RTC_SetDateAndTimeDirect(uint32_t sec, uint32_t min, uint32_t hour, uint32_t date, uint32_t month, uint32_t year); cy_en_rtc_status_t Cy_RTC_SetHoursFormat(cy_en_rtc_hours_format_t hoursFormat); void Cy_RTC_SelectFrequencyPrescaler(cy_en_rtc_clock_freq_t clkSel); @@ -551,7 +556,7 @@ void Cy_RTC_SelectFrequencyPrescaler(cy_en_rtc_clock_freq_t clkSel); */ cy_en_rtc_status_t Cy_RTC_SetAlarmDateAndTime(cy_stc_rtc_alarm_t const *alarmDateTime, cy_en_rtc_alarm_t alarmIndex); void Cy_RTC_GetAlarmDateAndTime(cy_stc_rtc_alarm_t *alarmDateTime, cy_en_rtc_alarm_t alarmIndex); -cy_en_rtc_status_t Cy_RTC_SetAlarmDateAndTimeDirect(uint32_t sec, uint32_t min, uint32_t hour, +cy_en_rtc_status_t Cy_RTC_SetAlarmDateAndTimeDirect(uint32_t sec, uint32_t min, uint32_t hour, uint32_t date, uint32_t month, cy_en_rtc_alarm_t alarmIndex); /** \} group_rtc_alarm_functions */ @@ -706,7 +711,7 @@ bool Cy_RTC_GetDstStatus(cy_stc_rtc_dst_t const *dstTime, cy_stc_rtc_config_t co /** * \defgroup group_rtc_busy_status RTC Status definitions * \{ -* Definitions for indicating the RTC BUSY bit +* Definitions for indicating the RTC BUSY bit */ #define CY_RTC_BUSY (1UL) /**< RTC Busy bit is set, RTC is pending */ #define CY_RTC_AVAILABLE (0UL) /**< RTC Busy bit is cleared, RTC is available */ @@ -826,7 +831,7 @@ extern uint8_t const cy_RTC_daysInMonthTbl[CY_RTC_MONTHS_PER_YEAR]; /* Internal macro to validate RTC day of the week parameter */ #define CY_RTC_IS_DOW_VALID(dayOfWeek) (((dayOfWeek) > 0U) && ((dayOfWeek) <= CY_RTC_DAYS_PER_WEEK)) - + /* Internal macro to validate RTC day parameter */ #define CY_RTC_IS_DAY_VALID(day) (((day) > 0U) && ((day) <= CY_RTC_MAX_DAYS_IN_MONTH)) @@ -863,9 +868,9 @@ extern uint8_t const cy_RTC_daysInMonthTbl[CY_RTC_MONTHS_PER_YEAR]; * * Returns a day of the week for a year, month, and day of month that are passed * through parameters. Zeller's congruence is used to calculate the day of -* the week. -* RTC HW block does not provide the converting function for day of week. This -* function should be called before Cy_RTC_SetDateAndTime() to get the day of +* the week. +* RTC HW block does not provide the converting function for day of week. This +* function should be called before Cy_RTC_SetDateAndTime() to get the day of * week. * * For the Georgian calendar, Zeller's congruence is: @@ -903,7 +908,7 @@ __STATIC_INLINE uint32_t Cy_RTC_ConvertDayOfWeek(uint32_t day, uint32_t month, u CY_ASSERT_L2(CY_RTC_IS_DAY_VALID(day)); CY_ASSERT_L2(CY_RTC_IS_MONTH_VALID(month)); CY_ASSERT_L2(CY_RTC_IS_YEAR_LONG_VALID(year)); - + /* Converts month number from regular convention * (1=January,..., 12=December) to convention required for this * algorithm (January and February are counted as months 13 and 14 of @@ -916,7 +921,7 @@ __STATIC_INLINE uint32_t Cy_RTC_ConvertDayOfWeek(uint32_t day, uint32_t month, u } /* Calculates Day of Week using Zeller's congruence algorithms */ - retVal = + retVal = (day + (((month + 1UL) * 26UL) / 10UL) + year + (year / 4UL) + (6UL * (year / 100UL)) + (year / 400UL)) % 7UL; /* Makes correction for Saturday. Saturday number should be 7 instead of 0*/ @@ -936,9 +941,9 @@ __STATIC_INLINE uint32_t Cy_RTC_ConvertDayOfWeek(uint32_t day, uint32_t month, u * Checks whether the year passed through the parameter is leap or not. * * This API is for checking an invalid value input for leap year. -* RTC HW block does not provide a validation checker against time/date values, +* RTC HW block does not provide a validation checker against time/date values, * the valid range of days in Month should be checked before SetDateAndTime() -* function call. Leap year is identified as a year that is a multiple of 4 +* function call. Leap year is identified as a year that is a multiple of 4 * or 400 but not 100. * * \param year @@ -963,7 +968,7 @@ __STATIC_INLINE bool Cy_RTC_IsLeapYear(uint32_t year) * * Returns a number of days in a month passed through the parameters. This API * is for checking an invalid value input for days. -* RTC HW block does not provide a validation checker against time/date values, +* RTC HW block does not provide a validation checker against time/date values, * the valid range of days in Month should be checked before SetDateAndTime() * function call. * @@ -1001,23 +1006,23 @@ __STATIC_INLINE uint32_t Cy_RTC_DaysInMonth(uint32_t month, uint32_t year) * Function Name: Cy_RTC_SyncFromRtc ****************************************************************************//** * -* The Synchronizer updates RTC values into AHB RTC user registers from the -* actual RTC. By calling this function, the actual RTC register values is +* The Synchronizer updates RTC values into AHB RTC user registers from the +* actual RTC. By calling this function, the actual RTC register values is * copied to AHB user registers. * -* \note Only after calling Cy_RTC_SyncFromRtc(), the RTC time values can be -* read. After Cy_RTC_SyncFromRtc() calling the snapshot of the actual RTC -* registers are copied to the user registers. Meanwhile the RTC continues to +* \note Only after calling Cy_RTC_SyncFromRtc(), the RTC time values can be +* read. After Cy_RTC_SyncFromRtc() calling the snapshot of the actual RTC +* registers are copied to the user registers. Meanwhile the RTC continues to * clock. * *******************************************************************************/ __STATIC_INLINE void Cy_RTC_SyncFromRtc(void) { uint32_t interruptState; - - interruptState = Cy_SysLib_EnterCriticalSection(); - - /* RTC Write is possible only in the condition that CY_RTC_BUSY bit = 0 + + interruptState = Cy_SysLib_EnterCriticalSection(); + + /* RTC Write is possible only in the condition that CY_RTC_BUSY bit = 0 * or RTC Write bit is not set. */ if ((CY_RTC_BUSY != Cy_RTC_GetSyncStatus()) && (!_FLD2BOOL(BACKUP_RTC_RW_WRITE, BACKUP_RTC_RW))) @@ -1039,12 +1044,12 @@ __STATIC_INLINE void Cy_RTC_SyncFromRtc(void) * Function Name: Cy_RTC_WriteEnable ****************************************************************************//** * -* Set/Clear writeable option for RTC user registers. When the Write bit is set, -* data can be written into the RTC user registers. After all the RTC writes are +* Set/Clear writeable option for RTC user registers. When the Write bit is set, +* data can be written into the RTC user registers. After all the RTC writes are * done, the firmware must clear (call Cy_RTC_WriteEnable(RTC_WRITE_DISABLED)) -* the Write bit for the RTC update to take effect. +* the Write bit for the RTC update to take effect. * -* Set/Clear cannot be done if the RTC is still busy with a previous update +* Set/Clear cannot be done if the RTC is still busy with a previous update * (CY_RTC_BUSY = 1) or RTC Reading is executing. * * \param writeEnable @@ -1064,7 +1069,7 @@ __STATIC_INLINE cy_en_rtc_status_t Cy_RTC_WriteEnable(cy_en_rtc_write_status_t w if (writeEnable == CY_RTC_WRITE_ENABLED) { - /* RTC Write bit set is possible only in condition that CY_RTC_BUSY bit = 0 + /* RTC Write bit set is possible only in condition that CY_RTC_BUSY bit = 0 * or RTC Read bit is not set */ if ((CY_RTC_BUSY != Cy_RTC_GetSyncStatus()) && (!_FLD2BOOL(BACKUP_RTC_RW_READ, BACKUP_RTC_RW))) @@ -1092,8 +1097,8 @@ __STATIC_INLINE cy_en_rtc_status_t Cy_RTC_WriteEnable(cy_en_rtc_write_status_t w ****************************************************************************//** * * Return current status of CY_RTC_BUSY. The status indicates -* synchronization between the RTC user register and the actual RTC register. -* CY_RTC_BUSY bit is set if it is synchronizing. It is not possible to set +* synchronization between the RTC user register and the actual RTC register. +* CY_RTC_BUSY bit is set if it is synchronizing. It is not possible to set * the Read or Write bit until CY_RTC_BUSY clears. * * \return @@ -1102,7 +1107,7 @@ __STATIC_INLINE cy_en_rtc_status_t Cy_RTC_WriteEnable(cy_en_rtc_write_status_t w * *******************************************************************************/ __STATIC_INLINE uint32_t Cy_RTC_GetSyncStatus(void) -{ +{ return((_FLD2BOOL(BACKUP_STATUS_RTC_BUSY, BACKUP_STATUS)) ? CY_RTC_BUSY : CY_RTC_AVAILABLE); } @@ -1121,7 +1126,7 @@ __STATIC_INLINE uint32_t Cy_RTC_GetSyncStatus(void) * \return * decNum An 8-bit hexadecimal equivalent number of the BCD number. * -* For example, for 0x11223344 BCD number, the function returns +* For example, for 0x11223344 BCD number, the function returns * 0x2C in hexadecimal format. * *******************************************************************************/ @@ -1129,8 +1134,8 @@ __STATIC_INLINE uint32_t Cy_RTC_ConvertBcdToDec(uint32_t bcdNum) { uint32_t retVal; - retVal = - ((bcdNum & (CY_RTC_BCD_ONE_DIGIT_MASK << CY_RTC_BCD_NUMBER_SIZE)) + retVal = + ((bcdNum & (CY_RTC_BCD_ONE_DIGIT_MASK << CY_RTC_BCD_NUMBER_SIZE)) >> CY_RTC_BCD_NUMBER_SIZE ) * CY_RTC_BCD_DOZED_DEGREE; retVal += bcdNum & CY_RTC_BCD_ONE_DIGIT_MASK; @@ -1147,14 +1152,14 @@ __STATIC_INLINE uint32_t Cy_RTC_ConvertBcdToDec(uint32_t bcdNum) * is converted individually and returned as an individual byte in the 32-bit * variable. * -* \param +* \param * decNum An 8-bit hexadecimal number. Each byte is represented in hex. * 0x11223344 -> 0x20 hex format. * * \return * An 8-bit BCD equivalent of the passed hexadecimal number. * -* For example, for 0x11223344 hexadecimal number, the function returns +* For example, for 0x11223344 hexadecimal number, the function returns * 0x20 BCD number. * *******************************************************************************/ @@ -1201,8 +1206,8 @@ __STATIC_INLINE cy_en_rtc_hours_format_t Cy_RTC_GetHoursFormat(void) * True if the reset reason is the power cycle and the XRES (external reset). * False if the reset reason is other than power cycle and the XRES. * -* \note Based on a return value the RTC time and date can be updated or skipped -* after the device reset. For example, you should skip the +* \note Based on a return value the RTC time and date can be updated or skipped +* after the device reset. For example, you should skip the * Cy_RTC_SetAlarmDateAndTime() call function if internal WDT reset occurs. * *******************************************************************************/ @@ -1216,11 +1221,11 @@ __STATIC_INLINE bool Cy_RTC_IsExternalResetOccurred(void) * Function Name: Cy_RTC_SyncToRtcAhbDateAndTime ****************************************************************************//** * -* This function updates new time and date into the time and date RTC AHB +* This function updates new time and date into the time and date RTC AHB * registers. * * \param timeBcd -* The BCD-formatted time variable which has the same bit masks as the +* The BCD-formatted time variable which has the same bit masks as the * RTC_TIME register: * * [0:6] - Calendar seconds in BCD, the range 0-59. \n @@ -1232,7 +1237,7 @@ __STATIC_INLINE bool Cy_RTC_IsExternalResetOccurred(void) * [26:24] - A calendar day of the week, the range 1 - 7, where 1 - Sunday. \n * * \param dateBcd -* The BCD-formatted time variable which has the same bit masks as the +* The BCD-formatted time variable which has the same bit masks as the * RTC_DATE register: * * [5:0] - A calendar day of a month in BCD, the range 1-31. \n @@ -1241,15 +1246,15 @@ __STATIC_INLINE bool Cy_RTC_IsExternalResetOccurred(void) * * \note Ensure that the parameters are presented in the BCD format. Use the * ConstructTimeDate() function to construct BCD time and date values. -* Refer to ConstructTimeDate() function description for more details -* about the RTC_TIME and RTC_DATE bit fields format. +* Refer to ConstructTimeDate() function description for more details +* about the RTC_TIME and RTC_DATE bit fields format. * * The RTC AHB registers can be updated only under condition that the -* Write bit is set and the RTC busy bit is cleared (RTC_BUSY = 0). Call the +* Write bit is set and the RTC busy bit is cleared (RTC_BUSY = 0). Call the * Cy_RTC_WriteEnable(CY_RTC_WRITE_ENABLED) and ensure that Cy_RTC_WriteEnable() * returned CY_RTC_SUCCESS. Then you can call Cy_RTC_SyncToRtcAhbDateAndTime(). -* Do not forget to clear the RTC Write bit to finish an RTC register update by -* calling Cy_RTC_WriteEnable(CY_RTC_WRITE_DISABLED) after you executed +* Do not forget to clear the RTC Write bit to finish an RTC register update by +* calling Cy_RTC_WriteEnable(CY_RTC_WRITE_DISABLED) after you executed * Cy_RTC_SyncToRtcAhbDateAndTime(). Ensure that Cy_RTC_WriteEnable() * returned CY_RTC_SUCCESS. * @@ -1265,18 +1270,18 @@ __STATIC_INLINE void Cy_RTC_SyncToRtcAhbDateAndTime(uint32_t timeBcd, uint32_t d * Function Name: Cy_RTC_SyncToRtcAhbAlarm ****************************************************************************//** * -* This function updates new alarm time and date into the alarm tire and date +* This function updates new alarm time and date into the alarm tire and date * RTC AHB registers. * * \param alarmTimeBcd -* The BCD-formatted time variable which has the same bit masks as the +* The BCD-formatted time variable which has the same bit masks as the * ALMx_TIME register time fields: * * [0:6] - Alarm seconds in BCD, the range 0-59. \n * [7] - Alarm seconds Enable: 0 - ignore, 1 - match. \n * [14:8] - Alarm minutes in BCD, the range 0-59. \n * [15] - Alarm minutes Enable: 0 - ignore, 1 - match. \n -* [21:16] - Alarm hours in BCD, value depending on the 12/24-hour mode +* [21:16] - Alarm hours in BCD, value depending on the 12/24-hour mode * (RTC_CTRL_12HR)\n * 12HR: [21]:0 = AM, 1 = PM, [20:16] = 1 - 12; \n * 24HR: [21:16] = the range 0-23. \n @@ -1285,7 +1290,7 @@ __STATIC_INLINE void Cy_RTC_SyncToRtcAhbDateAndTime(uint32_t timeBcd, uint32_t d * [31] - An alarm day of the week Enable: 0 - ignore, 1 - match. \n * * \param alarmDateBcd -* The BCD-formatted date variable which has the same bit masks as the +* The BCD-formatted date variable which has the same bit masks as the * ALMx_DATE register date fields: \n * [5:0] - An alarm day of a month in BCD, the range 1-31. \n * [7] - An alarm day of a month Enable: 0 - ignore, 1 - match. \n @@ -1296,17 +1301,17 @@ __STATIC_INLINE void Cy_RTC_SyncToRtcAhbDateAndTime(uint32_t timeBcd, uint32_t d * \param alarmIndex * The alarm index to be configured, see \ref cy_en_rtc_alarm_t. * -* \note Ensure that the parameters are presented in the BCD format. Use the +* \note Ensure that the parameters are presented in the BCD format. Use the * ConstructTimeDate() function to construct BCD time and date values. -* Refer to ConstructTimeDate() function description for more details -* about the RTC ALMx_TIME and ALMx_DATE bit-fields format. +* Refer to ConstructTimeDate() function description for more details +* about the RTC ALMx_TIME and ALMx_DATE bit-fields format. * * The RTC AHB registers can be updated only under condition that the -* Write bit is set and the RTC busy bit is cleared (RTC_BUSY = 0). Call the +* Write bit is set and the RTC busy bit is cleared (RTC_BUSY = 0). Call the * Cy_RTC_WriteEnable(CY_RTC_WRITE_ENABLED) and ensure that Cy_RTC_WriteEnable() * returned CY_RTC_SUCCESS. Then you can call Cy_RTC_SyncToRtcAhbDateAndTime(). -* Do not forget to clear the RTC Write bit to finish an RTC register update by -* calling the Cy_RTC_WriteEnable(CY_RTC_WRITE_DISABLED) after you executed +* Do not forget to clear the RTC Write bit to finish an RTC register update by +* calling the Cy_RTC_WriteEnable(CY_RTC_WRITE_DISABLED) after you executed * Cy_RTC_SyncToRtcAhbDateAndTime(). Ensure that Cy_RTC_WriteEnable() * returned CY_RTC_SUCCESS. * @@ -1314,7 +1319,7 @@ __STATIC_INLINE void Cy_RTC_SyncToRtcAhbDateAndTime(uint32_t timeBcd, uint32_t d __STATIC_INLINE void Cy_RTC_SyncToRtcAhbAlarm(uint32_t alarmTimeBcd, uint32_t alarmDateBcd, cy_en_rtc_alarm_t alarmIndex) { CY_ASSERT_L3(CY_RTC_IS_ALARM_IDX_VALID(alarmIndex)); - + if (alarmIndex != CY_RTC_ALARM_2) { BACKUP_ALM1_TIME = alarmTimeBcd; diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_sar.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_sar.h index f0c5bacdc4..77a17c36b3 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_sar.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_sar.h @@ -1,12 +1,12 @@ /***************************************************************************//** * \file cy_sar.h -* \version 1.20.2 +* \version 1.20.3 * * Header file for the SAR driver. * ******************************************************************************** * \copyright -* Copyright 2017-2019 Cypress Semiconductor Corporation +* Copyright 2017-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -27,9 +27,9 @@ * \{ * This driver configures and controls the SAR ADC subsystem block. * -* The functions and other declarations used in this driver are in cy_sar.h. -* You can include cy_pdl.h (ModusToolbox only) to get access to all functions -* and declarations in the PDL. +* The functions and other declarations used in this driver are in cy_sar.h. +* You can include cy_pdl.h to get access to all functions +* and declarations in the PDL. * * This SAR ADC subsystem is comprised of: * - a 12-bit SAR converter (SARADC) @@ -503,7 +503,7 @@ * \snippet sar/snippet/main.c SNIPPET_SAR_SARMUX_AMUXBUS * * -* To connect SARMUX to any other non-dedicated port, you may need to close additional HSIOM switches to route signals +* To connect SARMUX to any other non-dedicated port, you may need to close additional HSIOM switches to route signals * through AMUXBUS. * For more detail, see the device TRM, AMUX splitting. * @@ -511,8 +511,8 @@ * right switches of AMUX_SPLIT_CTL[1] and AMUX_SPLIT_CTL[6]. * * \warning -* This snippet shows how to configure pins for CY8C6347BZI-BLD53. -* +* This snippet shows how to configure pins for CY8C6347BZI-BLD53. +* * \snippet sar/snippet/main.c SNIPPET_SAR_SARMUX_CUSTOM_PORT * * \section group_sar_low_power Low Power Support @@ -558,6 +558,11 @@ *
VersionChangesReason for Change
2.30.1Minor documentation updates.Documentation enhancement.
2.30 +* * * Corrected the Cy_RTC_GetDstStatus() and Cy_RTC_SetNextDstTime() * documentation. * * Fixed the Cy_RTC_GetDstStatus() behaviour in the 'an hour before/after the DST stop event' period. * +* * * Collateral Review: user experience enhancement. * * Bug fix. *
2.20Flattened the organization of the driver source code into the single +* Flattened the organization of the driver source code into the single * source directory and the single include directory. * Driver library directory-structure simplification.
Added register access layer. Use register access macros instead * of direct register access using dereferenced pointers.Makes register access device-independent, so that the PDL does +* Makes register access device-independent, so that the PDL does * not need to be recompiled for each supported part number.
2.10 +* * * Corrected Cy_RTC_SetDateAndTimeDirect(), Cy_RTC_SetNextDstTime() * function. * * Corrected internal macro. * * Documentation updates. * -* * Incorrect behavior of \ref Cy_RTC_SetDateAndTimeDirect() and -* \ref Cy_RTC_SetNextDstTime() work in debug mode. -* * Debug assert correction in \ref Cy_RTC_ConvertDayOfWeek, +* +* * Incorrect behavior of \ref Cy_RTC_SetDateAndTimeDirect() and +* \ref Cy_RTC_SetNextDstTime() work in debug mode. +* * Debug assert correction in \ref Cy_RTC_ConvertDayOfWeek, * \ref Cy_RTC_IsLeapYear, \ref Cy_RTC_DaysInMonth. *
2.0 -* Enhancement and defect fixes: +* Enhancement and defect fixes: * * Added input parameter(s) validation to all public functions. * * Removed "Cy_RTC_" prefixes from the internal functions names. * * Renamed the elements in the cy_stc_rtc_alarm structure. -* * Changed the type of elements with limited set of values, from +* * Changed the type of elements with limited set of values, from * uint32_t to enumeration. *
* * +* +* +* +* +* * * * @@ -575,7 +580,7 @@ * * -* * * @@ -584,8 +589,8 @@ * * * -* * * @@ -1344,7 +1349,7 @@ typedef struct * \{ */ -/** This macro is for backward compatibility macro for driver v1.10 and before, +/** This macro is for backward compatibility macro for driver v1.10 and before, * the preferred API is \ref Cy_SAR_DeepSleep */ #define Cy_SAR_Sleep Cy_SAR_DeepSleep @@ -2150,4 +2155,3 @@ __STATIC_INLINE void Cy_SAR_SetVssaSarSeqCtrl(SAR_Type *base, cy_en_sar_switch_s /** \} group_sar */ /* [] END OF FILE */ - diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_scb_common.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_scb_common.h index f9554c1d74..ff67c0e5d9 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_scb_common.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_scb_common.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_scb_common.h -* \version 2.40.1 +* \version 2.50 * * Provides common API declarations of the SCB driver. * @@ -25,14 +25,14 @@ /** * \addtogroup group_scb * \{ -* The Serial Communications Block (SCB) supports three serial communication -* protocols: Serial Peripheral Interface (SPI), Universal Asynchronous Receiver -* Transmitter (UART), and Inter Integrated Circuit (I2C or IIC). Only one of +* The Serial Communications Block (SCB) supports three serial communication +* protocols: Serial Peripheral Interface (SPI), Universal Asynchronous Receiver +* Transmitter (UART), and Inter Integrated Circuit (I2C or IIC). Only one of * the protocols is supported by an SCB at any given time. * -* The functions and other declarations used in this driver are in cy_scb_spi.h, -* cy_scb_uart.h, cy_scb_ezi2c.h, cy_scb_i2c.h respectively. Include cy_pdl.h -* (ModusToolbox only) to get access to all functions and declarations in the PDL. +* The functions and other declarations used in this driver are in cy_scb_spi.h, +* cy_scb_uart.h, cy_scb_ezi2c.h, cy_scb_i2c.h respectively. Include cy_pdl.h +* to get access to all functions and declarations in the PDL. * \defgroup group_scb_common Common * \defgroup group_scb_ezi2c EZI2C (SCB) @@ -137,6 +137,17 @@ *
VersionChangesReason for Change
1.20.3Minor documentation updates.Documentation enhancement.
1.20.2Code snippets update.PDL infrastructure update, documentation enhancement.
Added register access layer. Use register access macros instead * of direct register access using dereferenced pointers.Makes register access device-independent, so that the PDL does +* Makes register access device-independent, so that the PDL does * not need to be recompiled for each supported part number.
Correct CAP_TRIM is necessary achieving specified SAR ADC linearity
Turn off the entire hardware block only if the SARMUX is not enabled -* for Deep Sleep operation. +* Turn off the entire hardware block only if the SARMUX is not enabled +* for Deep Sleep operation. * Improvement of the \ref Cy_SAR_DeepSleep flow
* * +* +* +* +* +* +* +* +* +* +* * * * @@ -180,7 +191,7 @@ * * * -* * @@ -188,22 +199,22 @@ * * -* * * -* * * * -* -* +* * @@ -211,9 +222,9 @@ * * -* * * @@ -224,7 +235,7 @@ * master mode configurations. * * -* * * @@ -269,8 +280,8 @@ * * * -* * * * * @@ -312,10 +323,10 @@ * API for the SCB. However, you can use the common SCB API to implement * a custom driver based on the SCB hardware. * -* The functions and other declarations used in this part of the driver are in -* cy_scb_common.h. You can include either of cy_scb_spi.h, cy_scb_uart.h, -* cy_scb_ezi2c.h, cy_scb_i2c.h depending on the desired functionality. -* You can also include cy_pdl.h to get access to all functions and declarations +* The functions and other declarations used in this part of the driver are in +* cy_scb_common.h. You can include either of cy_scb_spi.h, cy_scb_uart.h, +* cy_scb_ezi2c.h, cy_scb_i2c.h depending on the desired functionality. +* You can also include cy_pdl.h to get access to all functions and declarations * in the PDL. * ******************************************************************************* @@ -1989,4 +2000,3 @@ __STATIC_INLINE uint32_t Cy_SCB_GetRxFifoLevel(CySCB_Type const *base) #endif /* (CY_SCB_COMMON_H) */ /* [] END OF FILE */ - diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_scb_ezi2c.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_scb_ezi2c.h index f76d08b7cf..3f1607992b 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_scb_ezi2c.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_scb_ezi2c.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_scb_ezi2c.h -* \version 2.40.1 +* \version 2.50 * * Provides EZI2C API declarations of the SCB driver. * @@ -27,8 +27,8 @@ * \{ * Driver API for EZI2C Slave Peripheral * -* The functions and other declarations used in this part of the driver are in -* cy_scb_ezi2c.h. You can also include cy_pdl.h (ModusToolbox only) to get access +* The functions and other declarations used in this part of the driver are in +* cy_scb_ezi2c.h. You can also include cy_pdl.h to get access * to all functions and declarations in the PDL. * * I2C - The Inter-Integrated Circuit (I2C) bus is an industry-standard. @@ -54,34 +54,34 @@ ******************************************************************************** * \section group_scb_ezi2c_configuration Configuration Considerations ******************************************************************************** -* The EZI2C slave driver configuration can be divided to number of sequential -* steps listed below: +* The EZI2C slave driver configuration can be divided to number of sequential +* steps listed below: * * \ref group_scb_ezi2c_config * * \ref group_scb_ezi2c_pins * * \ref group_scb_ezi2c_clock * * \ref group_scb_ezi2c_data_rate * * \ref group_scb_ezi2c_intr * * \ref group_scb_ezi2c_enable -* -* \note -* EZI2C slave driver is built on top of the SCB hardware block. The SCB3 -* instance is used as an example for all code snippets. Modify the code to +* +* \note +* EZI2C slave driver is built on top of the SCB hardware block. The SCB3 +* instance is used as an example for all code snippets. Modify the code to * match your design. * ******************************************************************************** * \subsection group_scb_ezi2c_config Configure EZI2C slave ******************************************************************************** -* To set up the EZI2C slave driver, provide the configuration parameters in the -* \ref cy_stc_scb_ezi2c_config_t structure. The primary slave address -* slaveAddress1 must be provided. The other parameters are optional for -* operation. To initialize the driver, call \ref Cy_SCB_EZI2C_Init -* function providing a pointer to the populated \ref cy_stc_scb_ezi2c_config_t +* To set up the EZI2C slave driver, provide the configuration parameters in the +* \ref cy_stc_scb_ezi2c_config_t structure. The primary slave address +* slaveAddress1 must be provided. The other parameters are optional for +* operation. To initialize the driver, call \ref Cy_SCB_EZI2C_Init +* function providing a pointer to the populated \ref cy_stc_scb_ezi2c_config_t * structure and the allocated \ref cy_stc_scb_ezi2c_context_t structure. * * \snippet scb/ezi2c_snippet/main.c EZI2C_CFG * -* Set up the EZI2C slave buffer before enabling its -* operation by using \ref Cy_SCB_EZI2C_SetBuffer1 for the primary slave address +* Set up the EZI2C slave buffer before enabling its +* operation by using \ref Cy_SCB_EZI2C_SetBuffer1 for the primary slave address * and \ref Cy_SCB_EZI2C_SetBuffer2 for the secondary (if the secondary is enabled). * * \snippet scb/ezi2c_snippet/main.c EZI2C_CFG_BUFFER @@ -89,17 +89,17 @@ ******************************************************************************** * \subsection group_scb_ezi2c_pins Assign and Configure Pins ******************************************************************************** -* Only dedicated SCB pins can be used for I2C operation. The HSIOM -* register must be configured to connect dedicated SCB I2C pins to the -* SCB block. Also the I2C pins must be configured in Open-Drain, Drives Low mode +* Only dedicated SCB pins can be used for I2C operation. The HSIOM +* register must be configured to connect dedicated SCB I2C pins to the +* SCB block. Also the I2C pins must be configured in Open-Drain, Drives Low mode * (this pin configuration implies usage of external pull-up resistors): * * \snippet scb/ezi2c_snippet/main.c EZI2C_CFG_PINS * * \note -* The alternative pins configuration is Resistive Pull-ups which implies usage -* internal pull-up resistors. This configuration is not recommended because -* resistor value is fixed and cannot be used for all supported data rates. +* The alternative pins configuration is Resistive Pull-ups which implies usage +* internal pull-up resistors. This configuration is not recommended because +* resistor value is fixed and cannot be used for all supported data rates. * Refer to device datasheet parameter RPULLUP for resistor value specifications. * ******************************************************************************** @@ -107,7 +107,7 @@ ******************************************************************************** * A clock source must be connected to the SCB block to oversample input and * output signals, in this document this clock will be referred as clk_scb. -* You must use one of the 8-bit or 16-bit dividers. Use the \ref group_sysclk +* You must use one of the 8-bit or 16-bit dividers. Use the \ref group_sysclk * driver API to do this. * * \snippet scb/ezi2c_snippet/main.c EZI2C_CFG_ASSIGN_CLOCK @@ -115,12 +115,12 @@ ******************************************************************************** * \subsection group_scb_ezi2c_data_rate Configure Data Rate ******************************************************************************** -* To get EZI2C slave to operate at the desired data rate, the clk_scb must be -* fast enough to provide sufficient oversampling. Use the -* \ref group_sysclk driver API to do this. +* To get EZI2C slave to operate at the desired data rate, the clk_scb must be +* fast enough to provide sufficient oversampling. Use the +* \ref group_sysclk driver API to do this. * -* Refer to the technical reference manual (TRM) section I2C sub-section -* Oversampling and Bit Rate to get information about how to configure the +* Refer to the technical reference manual (TRM) section I2C sub-section +* Oversampling and Bit Rate to get information about how to configure the * I2C to run at the desired data rate. * * \snippet scb/ezi2c_snippet/main.c EZI2C_CFG_DATA_RATE @@ -128,9 +128,9 @@ ******************************************************************************** * \subsection group_scb_ezi2c_intr Configure Interrupt ******************************************************************************** -* The interrupt is mandatory for the EZI2C slave operation. -* The \ref Cy_SCB_EZI2C_Interrupt function must be called in the interrupt -* handler for the selected SCB instance. Also, this interrupt must be enabled +* The interrupt is mandatory for the EZI2C slave operation. +* The \ref Cy_SCB_EZI2C_Interrupt function must be called in the interrupt +* handler for the selected SCB instance. Also, this interrupt must be enabled * in the NVIC or it will not work. * * \snippet scb/ezi2c_snippet/main.c EZI2C_INTR_A @@ -139,18 +139,18 @@ ******************************************************************************** * \subsection group_scb_ezi2c_enable Enable EZI2C slave ******************************************************************************** -* Finally, enable the EZI2C slave operation by calling \ref Cy_SCB_EZI2C_Enable. +* Finally, enable the EZI2C slave operation by calling \ref Cy_SCB_EZI2C_Enable. * Now the I2C device responds to the assigned address. * \snippet scb/ezi2c_snippet/main.c EZI2C_ENABLE * ******************************************************************************** -* \section group_scb_ezi2c_use_cases Common Use Cases +* \section group_scb_ezi2c_use_cases Common Use Cases ******************************************************************************** * The EZI2C slave operation might not require calling any EZI2C slave function * because the I2C master is able to access the slave buffer. The application * can directly access it as well. Note that this is an application-level task * to ensure the buffer content integrity. -* +* ******************************************************************************** * \subsection group_scb_ezi2c_master_wr Master Write operation ******************************************************************************** @@ -164,9 +164,9 @@ * read/write region size.\n * When a master attempts to write outside the read/write region or past the * end of the buffer, the last byte is NACKed. -* +* * \image html scb_ezi2c_write.png -* +* ******************************************************************************** * \subsection group_scb_ezi2c_master_rd Master Read operation ******************************************************************************** @@ -182,7 +182,7 @@ * * \image html scb_ezi2c_read.png * -* The I2C master may use the ReStart or Stop/Start conditions to combine the +* The I2C master may use the ReStart or Stop/Start conditions to combine the * operations. The write operation sets only the base address and the following * read operation will start from the new base address. In cases where the base * address remains the same, there is no need for a write operation. @@ -191,39 +191,39 @@ ******************************************************************************** * \section group_scb_ezi2c_lp Low Power Support ******************************************************************************** -* The EZI2C slave provides the callback functions to handle power mode -* transition. The callback \ref Cy_SCB_EZI2C_DeepSleepCallback must be called -* during execution of \ref Cy_SysPm_CpuEnterDeepSleep; -* \ref Cy_SCB_EZI2C_HibernateCallback must be called during execution of -* \ref Cy_SysPm_SystemEnterHibernate. To trigger the callback execution, the -* callback must be registered before calling the power mode transition function. -* Refer to \ref group_syspm driver for more information about power mode +* The EZI2C slave provides the callback functions to handle power mode +* transition. The callback \ref Cy_SCB_EZI2C_DeepSleepCallback must be called +* during execution of \ref Cy_SysPm_CpuEnterDeepSleep; +* \ref Cy_SCB_EZI2C_HibernateCallback must be called during execution of +* \ref Cy_SysPm_SystemEnterHibernate. To trigger the callback execution, the +* callback must be registered before calling the power mode transition function. +* Refer to \ref group_syspm driver for more information about power mode * transitions and callback registration. * -* The EZI2C configured to support two addresses can wakeup the device on -* address match to NACK not supported address. This happens because the -* hardware address-match-logic uses address bit masking to support to two -* addresses. The address mask defines which bits in the address are treated -* as non-significant while performing an address match. One non-significant -* bit results in two matching addresses; two bits will match 4 and so on. -* If the two addresses differ by more than a single bit, then the extra -* addresses that will pass the hardware match and wakeup the device from -* Deep Sleep mode. Then firmware address matching will to generate a NAK. -* Due to this reason, it is preferable to select a secondary address that -* is different from the primary by one bit. The address mask in this case +* The EZI2C configured to support two addresses can wakeup the device on +* address match to NACK not supported address. This happens because the +* hardware address-match-logic uses address bit masking to support to two +* addresses. The address mask defines which bits in the address are treated +* as non-significant while performing an address match. One non-significant +* bit results in two matching addresses; two bits will match 4 and so on. +* If the two addresses differ by more than a single bit, then the extra +* addresses that will pass the hardware match and wakeup the device from +* Deep Sleep mode. Then firmware address matching will to generate a NAK. +* Due to this reason, it is preferable to select a secondary address that +* is different from the primary by one bit. The address mask in this case * makes one bit non-significant. * For example: -* * Primary address = 0x24 and secondary address = 0x34, only one bit differs. +* * Primary address = 0x24 and secondary address = 0x34, only one bit differs. * Only the two addresses are treated as matching by the hardware. -* * Primary address = 0x24 and secondary address = 0x30, two bits differ. -* Four addresses are treated as matching by the hardware: 0x24, 0x34, 0x20 -* and 0x30. Firmware is required to ACK only the primary and secondary +* * Primary address = 0x24 and secondary address = 0x30, two bits differ. +* Four addresses are treated as matching by the hardware: 0x24, 0x34, 0x20 +* and 0x30. Firmware is required to ACK only the primary and secondary * addresses 0x24 and 0x30 and NAK all others 0x20 and 0x34. * * \note * Only applicable for rev-08 of the CY8CKIT-062-BLE. -* For proper operation, when the EZI2C slave is configured to be a wakeup -* source from Deep Sleep mode, the \ref Cy_SCB_EZI2C_DeepSleepCallback must +* For proper operation, when the EZI2C slave is configured to be a wakeup +* source from Deep Sleep mode, the \ref Cy_SCB_EZI2C_DeepSleepCallback must * be copied and modified. Refer to the function description to get the details. * * \defgroup group_scb_ezi2c_macros Macros @@ -330,10 +330,10 @@ typedef struct cy_stc_scb_ezi2c_config } cy_stc_scb_ezi2c_config_t; /** EZI2C slave context structure. -* All fields for the context structure are internal. Firmware never reads or -* writes these values. Firmware allocates the structure and provides the -* address of the structure to the driver in function calls. Firmware must -* ensure that the defined instance of this structure remains in scope +* All fields for the context structure are internal. Firmware never reads or +* writes these values. Firmware allocates the structure and provides the +* address of the structure to the driver in function calls. Firmware must +* ensure that the defined instance of this structure remains in scope * while the drive is in use. */ typedef struct cy_stc_scb_ezi2c_context @@ -421,9 +421,9 @@ cy_en_syspm_status_t Cy_SCB_EZI2C_HibernateCallback(cy_stc_syspm_callback_params /** * \defgroup group_scb_ezi2c_macros_get_activity EZI2C Activity Status -* Macros to check current EZI2C activity slave status returned by -* \ref Cy_SCB_EZI2C_GetActivity function. Each EZI2C slave status is encoded -* in a separate bit, therefore multiple bits may be set to indicate the +* Macros to check current EZI2C activity slave status returned by +* \ref Cy_SCB_EZI2C_GetActivity function. Each EZI2C slave status is encoded +* in a separate bit, therefore multiple bits may be set to indicate the * current status. * \{ */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_scb_i2c.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_scb_i2c.h index 26e40067f0..bf4d0512d1 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_scb_i2c.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_scb_i2c.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_scb_i2c.h -* \version 2.40.1 +* \version 2.50 * * Provides I2C API declarations of the SCB driver. * @@ -29,8 +29,8 @@ * * I2C - The Inter-Integrated Circuit (I2C) bus is an industry-standard. * -* The functions and other declarations used in this part of the driver are in -* cy_scb_i2c.h. You can also include cy_pdl.h (ModusToolbox only) to get access +* The functions and other declarations used in this part of the driver are in +* cy_scb_i2c.h. You can also include cy_pdl.h to get access * to all functions and declarations in the PDL. * * The I2C peripheral driver provides an API to implement I2C slave, master, @@ -68,15 +68,15 @@ ******************************************************************************** * To set up the I2C driver, provide the configuration parameters in the * \ref cy_stc_scb_i2c_config_t structure. Provide i2cMode to the select -* operation mode slave, master or master-slave. The useRxFifo and useTxFifo +* operation mode slave, master or master-slave. The useRxFifo and useTxFifo * parameters specify if RX and TX FIFO is used during operation. Typically, both -* FIFOs should be enabled to reduce possibility of clock stringing. However, -* using RX FIFO has side effects that needs to be taken into account -* (see useRxFifo field description in \ref cy_stc_scb_i2c_config_t structure). -* For master modes, parameters lowPhaseDutyCycle, highPhaseDutyCycle and -* enableDigitalFilter can be used to define output data rate (refer to section +* FIFOs should be enabled to reduce possibility of clock stringing. However, +* using RX FIFO has side effects that needs to be taken into account +* (see useRxFifo field description in \ref cy_stc_scb_i2c_config_t structure). +* For master modes, parameters lowPhaseDutyCycle, highPhaseDutyCycle and +* enableDigitalFilter can be used to define output data rate (refer to section * \ref group_scb_i2c_data_rate for more information). -* For slave mode, provide the slaveAddress and slaveAddressMask. The other +* For slave mode, provide the slaveAddress and slaveAddressMask. The other * parameters are optional for operation.\n * To initialize the driver, call \ref Cy_SCB_I2C_Init * function providing a pointer to the populated \ref cy_stc_scb_i2c_config_t @@ -95,8 +95,8 @@ * \subsection group_scb_i2c_pins Assign and Configure Pins ******************************************************************************** * Only dedicated SCB pins can be used for I2C operation. The HSIOM -* register must be configured to connect dedicated SCB I2C pins to the -* SCB block. Also the I2C pins must be configured in Open-Drain, Drives Low mode +* register must be configured to connect dedicated SCB I2C pins to the +* SCB block. Also the I2C pins must be configured in Open-Drain, Drives Low mode * (this pins configuration implies usage of external pull-up resistors): * * \snippet scb/i2c_snippet/main.c I2C_CFG_PINS @@ -112,7 +112,7 @@ ******************************************************************************** * A clock source must be connected to the SCB block to oversample input and * output signals, in this document this clock will be referred as clk_scb. -* You must use one of the 8-bit or 16-bit dividers. Use the \ref group_sysclk +* You must use one of the 8-bit or 16-bit dividers. Use the \ref group_sysclk * driver API to do this. * * \snippet scb/i2c_snippet/main.c I2C_CFG_ASSIGN_CLOCK @@ -129,14 +129,14 @@ * To get I2C master operation with the desired data rate, the source clock * frequency and SCL low and high phase duration must be configured. Use the * \ref group_sysclk driver API to configure source clock frequency. Then call -* \ref Cy_SCB_I2C_SetDataRate to set the SCL low, high phase duration and -* digital filter. This function sets SCL low and high phase settings based on +* \ref Cy_SCB_I2C_SetDataRate to set the SCL low, high phase duration and +* digital filter. This function sets SCL low and high phase settings based on * source clock frequency. * * \snippet scb/i2c_snippet/main.c I2C_CFG_DATA_RATE_MASTER * -* Alternatively, the low, high phase and digital filter can be set directly -* using configuration structure \ref cy_stc_scb_i2c_config_t fields +* Alternatively, the low, high phase and digital filter can be set directly +* using configuration structure \ref cy_stc_scb_i2c_config_t fields * lowPhaseDutyCycle, highPhaseDutyCycle and enableDigitalFilter appropriately.\n * Refer to the technical reference manual (TRM) section I2C sub-section * Oversampling and Bit Rate to get information how to configure I2C to run with @@ -150,7 +150,7 @@ ******************************************************************************** * \subsection group_scb_i2c_intr Configure Interrupt ******************************************************************************** -* The interrupt is mandatory for I2C operation. The exception is the when only +* The interrupt is mandatory for I2C operation. The exception is the when only * the \ref group_scb_i2c_master_low_level_functions functions are used. * The driver provides three interrupt functions: \ref Cy_SCB_I2C_Interrupt, * \ref Cy_SCB_I2C_SlaveInterrupt, and \ref Cy_SCB_I2C_MasterInterrupt. One of @@ -198,7 +198,7 @@ * Call \ref Cy_SCB_I2C_MasterRead or \ref Cy_SCB_I2C_MasterWrite to * communicate with the slave. These functions do not block and only start a * transaction. After a transaction starts, the \ref Cy_SCB_I2C_Interrupt -* handles further data transaction until its completion (successfully or +* handles further data transaction until its completion (successfully or * with error occurring). To monitor the transaction, * use \ref Cy_SCB_I2C_MasterGetStatus or register callback function using * \ref Cy_SCB_I2C_RegisterEventCallback to be notified about @@ -259,13 +259,13 @@ * All slave API (except \ref Cy_SCB_I2C_SlaveAbortRead and * \ref Cy_SCB_I2C_SlaveAbortWrite) are not interrupt-protected and to * prevent a race condition, they should be protected from the I2C interruption -* in the place where they are called. The code snippet Polling Slave -* Completion Events above shows how to prevent a race condition when detect -* transfer completion and update I2C slave write buffer. -* The simple example of race condition is: application updates slave read -* buffer the I2C master starts read transfer. The I2C interrupts read buffer -* update and I2C interrupt loads current read buffer content in the TX FIFO . -* After I2C interrupt returns the application updates remaining part of the read +* in the place where they are called. The code snippet Polling Slave +* Completion Events above shows how to prevent a race condition when detect +* transfer completion and update I2C slave write buffer. +* The simple example of race condition is: application updates slave read +* buffer the I2C master starts read transfer. The I2C interrupts read buffer +* update and I2C interrupt loads current read buffer content in the TX FIFO . +* After I2C interrupt returns the application updates remaining part of the read * buffer. As a result the mater read partly updated buffer. * ******************************************************************************** @@ -493,12 +493,12 @@ typedef struct cy_stc_scb_i2c_config uint8_t slaveAddress; /** - * The slave address mask is used to mask bits of the slave address during - * the address match procedure (it is used only for the slave mode). - * Bit 0 of the address mask corresponds to the - * read/write direction bit and is always a do not care in the address match - * therefore must be set 0. Bit value 0 - excludes bit from address - * comparison. Bit value 1 - the bit needs to match with the corresponding + * The slave address mask is used to mask bits of the slave address during + * the address match procedure (it is used only for the slave mode). + * Bit 0 of the address mask corresponds to the + * read/write direction bit and is always a do not care in the address match + * therefore must be set 0. Bit value 0 - excludes bit from address + * comparison. Bit value 1 - the bit needs to match with the corresponding * bit of the I2C slave address. */ uint8_t slaveAddressMask; @@ -529,13 +529,13 @@ typedef struct cy_stc_scb_i2c_config bool enableDigitalFilter; /** - * The number of SCB clock cycles in the low phase of SCL. Only applicable + * The number of SCB clock cycles in the low phase of SCL. Only applicable * in master modes. The valid range is 7 to 16. */ uint32_t lowPhaseDutyCycle; /** - * The number of SCB clock cycles in the high phase of SCL. Only applicable + * The number of SCB clock cycles in the high phase of SCL. Only applicable * in master modes. The valid range is 5 to 16. */ uint32_t highPhaseDutyCycle; @@ -601,7 +601,7 @@ typedef struct cy_stc_scb_i2c_master_xfer_config uint8_t slaveAddress; /** - * The pointer to the buffer for data to read from the slave or + * The pointer to the buffer for data to read from the slave or * data to write into the slave */ uint8_t *buffer; @@ -611,16 +611,16 @@ typedef struct cy_stc_scb_i2c_master_xfer_config /** * The transfer operation is pending - the stop condition will not - * be generated. - * A new transfer starts from start condition and ends - * with or without stop condition. The stop condition releases I2C - * bus from master control. When stop is not generated master keeps - * bus control (transfer is pending) and can issue the next transfer - * using restart condition instead of start. The I2C driver - * automatically generates start or restart condition depends on + * be generated. + * A new transfer starts from start condition and ends + * with or without stop condition. The stop condition releases I2C + * bus from master control. When stop is not generated master keeps + * bus control (transfer is pending) and can issue the next transfer + * using restart condition instead of start. The I2C driver + * automatically generates start or restart condition depends on * current state. - * Note if master lost arbitration during transfer it stops control - * the bus and does not send/receive data or generate stop condition - the + * Note if master lost arbitration during transfer it stops control + * the bus and does not send/receive data or generate stop condition - the * transfer ends. */ bool xferPending; @@ -738,9 +738,9 @@ cy_en_syspm_status_t Cy_SCB_I2C_HibernateCallback(cy_stc_syspm_callback_params_t /** * \defgroup group_scb_i2c_macros_slave_status I2C Slave Status -* Macros to check current I2C slave status returned by -* \ref Cy_SCB_I2C_SlaveGetStatus function. Each I2C slave status is encoded -* in a separate bit, therefore multiple bits may be set to indicate the +* Macros to check current I2C slave status returned by +* \ref Cy_SCB_I2C_SlaveGetStatus function. Each I2C slave status is encoded +* in a separate bit, therefore multiple bits may be set to indicate the * current status. * \{ */ @@ -791,9 +791,9 @@ cy_en_syspm_status_t Cy_SCB_I2C_HibernateCallback(cy_stc_syspm_callback_params_t /** * \defgroup group_scb_i2c_macros_master_status I2C Master Status -* Macros to check current I2C master status returned by -* \ref Cy_SCB_I2C_MasterGetStatus function. Each I2C master status is encoded -* in a separate bit, therefore multiple bits may be set to indicate the +* Macros to check current I2C master status returned by +* \ref Cy_SCB_I2C_MasterGetStatus function. Each I2C master status is encoded +* in a separate bit, therefore multiple bits may be set to indicate the * current status. * \{ */ @@ -1374,4 +1374,3 @@ __STATIC_INLINE void Cy_SCB_I2C_RegisterAddrCallback(CySCB_Type const *base, #endif /* (CY_SCB_I2C_H) */ /* [] END OF FILE */ - diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_scb_spi.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_scb_spi.h index 71b62b22a8..29cc50a4a2 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_scb_spi.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_scb_spi.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_scb_spi.h -* \version 2.40.1 +* \version 2.50 * * Provides SPI API declarations of the SCB driver. * @@ -27,13 +27,13 @@ * \{ * Driver API for SPI Peripheral. * -* The functions and other declarations used in this part of the driver are in -* cy_scb_spi.h. You can also include cy_pdl.h (ModusToolbox only) to get access +* The functions and other declarations used in this part of the driver are in +* cy_scb_spi.h. You can also include cy_pdl.h to get access * to all functions and declarations in the PDL. * -* The SPI protocol is a synchronous serial interface protocol. Devices operate -* in either master or slave mode. The master initiates the data transfer. -* The SCB supports single-master-multiple-slaves topology for SPI. Multiple +* The SPI protocol is a synchronous serial interface protocol. Devices operate +* in either master or slave mode. The master initiates the data transfer. +* The SCB supports single-master-multiple-slaves topology for SPI. Multiple * slaves are supported with individual slave select lines. * * Features: @@ -43,7 +43,7 @@ * * National Semiconductor (MicroWire) SPI - mode 0 only * * Master supports up to four slave select lines * * Each slave select has configurable active polarity (high or low) -* * Slave select can be programmed to stay active for a whole transfer, or +* * Slave select can be programmed to stay active for a whole transfer, or * just for each byte * * Master supports late sampling for better timing margin * * Master supports continuous SPI clock @@ -77,7 +77,7 @@ * subMode, sclkMode, oversample, rxDataWidth, and txDataWidth. The other * parameters are optional for operation. To initialize the driver, call * \ref Cy_SCB_SPI_Init function providing a pointer to the populated -* \ref cy_stc_scb_spi_config_t structure and the allocated +* \ref cy_stc_scb_spi_config_t structure and the allocated * \ref cy_stc_scb_spi_context_t structure. * * \snippet scb/spi_snippet/main.c SPI_CFG @@ -86,8 +86,8 @@ * \subsection group_scb_spi_pins Assign and Configure Pins ******************************************************************************** * Only dedicated SCB pins can be used for SPI operation. The HSIOM -* register must be configured to connect dedicated SCB SPI pins to the -* SCB block. Also, the SPI output pins must be configured in Strong Drive Input +* register must be configured to connect dedicated SCB SPI pins to the +* SCB block. Also, the SPI output pins must be configured in Strong Drive Input * Off mode and SPI input pins in Digital High-Z. * * \snippet scb/spi_snippet/main.c SPI_CFG_PINS @@ -97,7 +97,7 @@ ******************************************************************************** * A clock source must be connected to the SCB block to oversample input and * output signals, in this document this clock will be referred as clk_scb. -* You must use one of the 8-bit or 16-bit dividers. Use the \ref group_sysclk +* You must use one of the 8-bit or 16-bit dividers. Use the \ref group_sysclk * driver API to do this. * * \snippet scb/spi_snippet/main.c SPI_CFG_ASSIGN_CLOCK @@ -106,25 +106,25 @@ * \subsection group_scb_spi_data_rate Configure Data Rate ******************************************************************************** * To get the SPI slave to operate with the desired data rate, the clk_scb must be -* fast enough to provide sufficient oversampling. Use the \ref group_sysclk driver +* fast enough to provide sufficient oversampling. Use the \ref group_sysclk driver * API to do that. * * \snippet scb/spi_snippet/main.c SPI_CFG_DATA_RATE_SLAVE * -* To get the SPI master to operate with the desired data rate, multiply the -* oversample factor by the desired data rate to determine the required -* frequency for clk_scb. Use the \ref group_sysclk driver API to configure -* clk_scb frequency. Set the oversample parameter in configuration -* structure to define number of SCB clocks in one SCLK period. -* When this value is even, the first and second phases of the SCLK period are -* the same. Otherwise, the first phase is one SCB clock cycle longer than the +* To get the SPI master to operate with the desired data rate, multiply the +* oversample factor by the desired data rate to determine the required +* frequency for clk_scb. Use the \ref group_sysclk driver API to configure +* clk_scb frequency. Set the oversample parameter in configuration +* structure to define number of SCB clocks in one SCLK period. +* When this value is even, the first and second phases of the SCLK period are +* the same. Otherwise, the first phase is one SCB clock cycle longer than the * second phase. The level of the first phase of the clock period depends on CPOL * settings: 0 - low level and 1 - high level. * * \snippet scb/spi_snippet/main.c SPI_CFG_DATA_RATE_MASTER * * Refer to the technical reference manual (TRM) section SPI sub-section -* Oversampling and Bit Rate to get information about how to configure SPI to run +* Oversampling and Bit Rate to get information about how to configure SPI to run * with desired data rate. * ******************************************************************************** @@ -163,7 +163,7 @@ * The \ref group_scb_spi_low_level_functions functions allow * interacting directly with the hardware and do not use \ref Cy_SCB_SPI_Interrupt. * These functions do not require context for operation. Thus, NULL can be -* passed for context parameter in \ref Cy_SCB_SPI_Init and \ref Cy_SCB_SPI_Disable +* passed for context parameter in \ref Cy_SCB_SPI_Init and \ref Cy_SCB_SPI_Disable * instead of a pointer to the context structure. * * * To write data into the TX FIFO, use one of the provided functions: @@ -173,8 +173,8 @@ * transfer. Due to the nature of SPI, the received data is put into the RX FIFO. * * * To read data from the RX FIFO, use one of the provided functions: -* \ref Cy_SCB_SPI_Read or \ref Cy_SCB_SPI_ReadArray. Again due to the nature -* of SPI these functions do not start a transfer on the bus, they only read +* \ref Cy_SCB_SPI_Read or \ref Cy_SCB_SPI_ReadArray. Again due to the nature +* of SPI these functions do not start a transfer on the bus, they only read * data out of the RX FIFO that has already been received. * * * The statuses can be polled using: \ref Cy_SCB_SPI_GetRxFifoStatus, @@ -194,12 +194,12 @@ * \subsection group_scb_spi_hl High-Level API ******************************************************************************** * The \ref group_scb_spi_high_level_functions API use \ref Cy_SCB_SPI_Interrupt -* to execute the transfer. Call \ref Cy_SCB_SPI_Transfer to start communication: for master -* mode calling this function starts a transaction with the slave. For slave mode +* to execute the transfer. Call \ref Cy_SCB_SPI_Transfer to start communication: for master +* mode calling this function starts a transaction with the slave. For slave mode * the read and write buffers are prepared for the communication with the master. * After a transfer is started, the \ref Cy_SCB_SPI_Interrupt handles the -* transfer until its completion. Therefore, the \ref Cy_SCB_SPI_Interrupt function -* must be called inside the user interrupt handler to make the High-Level API work. +* transfer until its completion. Therefore, the \ref Cy_SCB_SPI_Interrupt function +* must be called inside the user interrupt handler to make the High-Level API work. * To monitor the status of the transfer operation, use \ref Cy_SCB_SPI_GetTransferStatus. * Alternatively, use \ref Cy_SCB_SPI_RegisterCallback to register a callback * function to be notified about \ref group_scb_spi_macros_callback_events. @@ -227,7 +227,7 @@ * parameter to configure TX FIFO level value. \n * For example, the TX FIFO has 0 data elements (empty) and the TX FIFO level * is 7. The TX trigger signal is active until DMA loads TX FIFO -* with 8 data elements (note that after the first TX load operation, the data +* with 8 data elements (note that after the first TX load operation, the data * element goes to the shift register and TX FIFO is empty). * * To route SCB TX or RX trigger signals to the DMA controller, use \ref group_trigmux @@ -248,23 +248,23 @@ * callback execution, the callback must be registered before calling the * power mode transition function. Refer to \ref group_syspm driver for more * information about power mode transitions and callback registration. -* -* The SPI master is disabled during Deep Sleep and Hibernate and stops driving -* the output pins. The state of the SPI master output pins SCLK, SS, and MOSI is -* High-Z, which can cause unexpected behavior of the SPI Slave due to possible -* glitches on these lines. These pins must keep the inactive level (the same state -* when SPI master is enabled and does not transfer data) before entering Deep -* Sleep or Hibernate mode. To do that, write the GPIO data register of each pin -* to the inactive level for each output pin. Then configure High-Speed Input -* Output Multiplexer (HSIOM) of each pin to be controlled by the GPIO (use -* \ref group_gpio driver API). After after exiting Deep Sleep mode the SPI -* master must be enabled and the pins configuration restored to return the -* SPI master control of the pins (after exiting Hibernate mode, the -* system initialization code does the same). Copy either or -* both \ref Cy_SCB_SPI_DeepSleepCallback and \ref Cy_SCB_SPI_HibernateCallback +* +* The SPI master is disabled during Deep Sleep and Hibernate and stops driving +* the output pins. The state of the SPI master output pins SCLK, SS, and MOSI is +* High-Z, which can cause unexpected behavior of the SPI Slave due to possible +* glitches on these lines. These pins must keep the inactive level (the same state +* when SPI master is enabled and does not transfer data) before entering Deep +* Sleep or Hibernate mode. To do that, write the GPIO data register of each pin +* to the inactive level for each output pin. Then configure High-Speed Input +* Output Multiplexer (HSIOM) of each pin to be controlled by the GPIO (use +* \ref group_gpio driver API). After after exiting Deep Sleep mode the SPI +* master must be enabled and the pins configuration restored to return the +* SPI master control of the pins (after exiting Hibernate mode, the +* system initialization code does the same). Copy either or +* both \ref Cy_SCB_SPI_DeepSleepCallback and \ref Cy_SCB_SPI_HibernateCallback * as appropriate, and make the changes described above inside the function. -* Alternately, external pull-up or pull-down resistors can be connected -* to the appropriate SPI lines to keep them inactive during Deep-Sleep or +* Alternately, external pull-up or pull-down resistors can be connected +* to the appropriate SPI lines to keep them inactive during Deep-Sleep or * Hibernate. * * \note @@ -723,8 +723,8 @@ cy_en_syspm_status_t Cy_SCB_SPI_HibernateCallback(cy_stc_syspm_callback_params_t /** * \defgroup group_scb_spi_macros_xfer_status SPI Transfer Status * \{ -* Macros to check current SPI transfer status returned by -* \ref Cy_SCB_SPI_GetTransferStatus function. +* Macros to check current SPI transfer status returned by +* \ref Cy_SCB_SPI_GetTransferStatus function. * Each SPI transfer status is encoded in a separate bit, therefore multiple bits * may be set to indicate the current status. */ @@ -873,7 +873,7 @@ __STATIC_INLINE void Cy_SCB_SPI_Enable(CySCB_Type *base) * slave select line is activated and lasts until the slave select line is * deactivated. * * Texas Instrument sub-modes: The bus is busy the moment of the initial -* pulse on the slave select line and lasts until the transfer is complete +* pulse on the slave select line and lasts until the transfer is complete * (all bytes from the TX FIFO area shifted-out on the bus). * * \param base @@ -887,7 +887,7 @@ __STATIC_INLINE void Cy_SCB_SPI_Enable(CySCB_Type *base) * the first data element is written into the TX FIFO. It takes up to two SCLK * clocks to assign the slave select line. Before this happens, the bus * is considered idle. -* * If the SPI master is configured to transmit each data element separated by +* * If the SPI master is configured to transmit each data element separated by * a de-assertion of the slave select line, the bus is busy during each element * transfer and is free between them. * @@ -954,7 +954,7 @@ __STATIC_INLINE void Cy_SCB_SPI_SetActiveSlaveSelectPolarity(CySCB_Type *base, CY_ASSERT_L3(CY_SCB_SPI_IS_SLAVE_SEL_VALID(slaveSelect)); CY_ASSERT_L3(CY_SCB_SPI_IS_POLARITY_VALID (polarity)); - if (CY_SCB_SPI_ACTIVE_HIGH != polarity) + if (CY_SCB_SPI_ACTIVE_HIGH == polarity) { SCB_SPI_CTRL(base) |= (uint32_t) mask; } @@ -1252,7 +1252,7 @@ __STATIC_INLINE void Cy_SCB_SPI_ClearSlaveMasterStatus(CySCB_Type *base, uint32_ * \note * * This function only reads data available in the RX FIFO. It does not * initiate an SPI transfer. -* * When in the master mode, this function writes data into the TX FIFO and +* * When in the master mode, this function writes data into the TX FIFO and * waits until the transfer is completed before reading data from the RX FIFO. * *******************************************************************************/ @@ -1287,7 +1287,7 @@ __STATIC_INLINE uint32_t Cy_SCB_SPI_Read(CySCB_Type const *base) * \note * * This function only reads data available in the RX FIFO. It does not * initiate an SPI transfer. -* * When in the master mode, this function writes data into the TX FIFO and +* * When in the master mode, this function writes data into the TX FIFO and * waits until the transfer is completed before reading data from the RX FIFO. * *******************************************************************************/ @@ -1502,4 +1502,3 @@ __STATIC_INLINE uint32_t CY_SCB_SPI_GetSclkMode(cy_en_scb_spi_sub_mode_t subMode #endif /* (CY_SCB_SPI_H) */ /* [] END OF FILE */ - diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_scb_uart.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_scb_uart.h index 6ea5ede08b..9f54f412a1 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_scb_uart.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_scb_uart.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_scb_uart.h -* \version 2.40.1 +* \version 2.50 * * Provides UART API declarations of the SCB driver. * @@ -27,22 +27,22 @@ * \{ * Driver API for UART * -* The functions and other declarations used in this part of the driver are in -* cy_scb_uart.h. You can also include cy_pdl.h (ModusToolbox only) to get access +* The functions and other declarations used in this part of the driver are in +* cy_scb_uart.h. You can also include cy_pdl.h to get access * to all functions and declarations in the PDL. * -* The Universal Asynchronous Receiver/Transmitter (UART) protocol is an -* asynchronous serial interface protocol. UART communication is typically +* The Universal Asynchronous Receiver/Transmitter (UART) protocol is an +* asynchronous serial interface protocol. UART communication is typically * point-to-point. The UART interface consists of two signals: * * TX: Transmitter output * * RX: Receiver input * -* Additionally, two side-band signals are used to implement flow control in +* Additionally, two side-band signals are used to implement flow control in * UART. Note that the flow control applies only to TX functionality. -* * Clear to Send (CTS): This is an input signal to the transmitter. -* When active, it indicates that the slave is ready for the master to +* * Clear to Send (CTS): This is an input signal to the transmitter. +* When active, it indicates that the slave is ready for the master to * transmit data. -* * Ready to Send (RTS): This is an output signal from the receiver. When +* * Ready to Send (RTS): This is an output signal from the receiver. When * active, it indicates that the receiver is ready to receive data * * Features: @@ -52,7 +52,7 @@ * * SmartCard (ISO7816) reader * * IrDA * * Data frame size programmable from 4 to 16 bits -* * Programmable number of STOP bits, which can be set in terms of half bit +* * Programmable number of STOP bits, which can be set in terms of half bit * periods between 1 and 4 * * Parity support (odd and even parity) * * Median filter on Rx input @@ -82,8 +82,8 @@ * To set up the UART driver, provide the configuration parameters in the * \ref cy_stc_scb_uart_config_t structure. For example: provide uartMode, * oversample, dataWidth, enableMsbFirst, parity, and stopBits. The other -* parameters are optional. To initialize the driver, call \ref Cy_SCB_UART_Init -* function providing a pointer to the populated \ref cy_stc_scb_uart_config_t +* parameters are optional. To initialize the driver, call \ref Cy_SCB_UART_Init +* function providing a pointer to the populated \ref cy_stc_scb_uart_config_t * structure and the allocated \ref cy_stc_scb_uart_context_t structure. * * \snippet scb/uart_snippet/main.c UART_CFG @@ -92,8 +92,8 @@ * \subsection group_scb_uart_pins Assign and Configure Pins ******************************************************************************** * Only dedicated SCB pins can be used for UART operation. The HSIOM -* register must be configured to connect dedicated SCB UART pins to the -* SCB block. Also, the UART output pins must be configured in Strong Drive +* register must be configured to connect dedicated SCB UART pins to the +* SCB block. Also, the UART output pins must be configured in Strong Drive * Input Off mode and UART input pins in Digital High-Z: * * \snippet scb/uart_snippet/main.c UART_CFG_PINS @@ -103,7 +103,7 @@ ******************************************************************************** * A clock source must be connected to the SCB block to oversample input and * output signals, in this document this clock will be referred as clk_scb. -* You must use one of available integer or fractional dividers. Use the +* You must use one of available integer or fractional dividers. Use the * \ref group_sysclk driver API to do this. * * \snippet scb/uart_snippet/main.c UART_CFG_ASSIGN_CLOCK @@ -156,7 +156,7 @@ * The \ref group_scb_uart_low_level_functions functions allow * interacting directly with the hardware and do not use \ref Cy_SCB_UART_Interrupt. * These functions do not require context for operation. Thus, NULL can be -* passed for context parameter in \ref Cy_SCB_UART_Init and \ref Cy_SCB_UART_Disable +* passed for context parameter in \ref Cy_SCB_UART_Init and \ref Cy_SCB_UART_Disable * instead of a pointer to the context structure. * * * To write data into the TX FIFO, use one of the provided functions: @@ -189,7 +189,7 @@ * Call \ref Cy_SCB_UART_Receive to start receive operation. After the * operation is started the \ref Cy_SCB_UART_Interrupt handles the data * transfer until its completion. -* Therefore \ref Cy_SCB_UART_Interrupt must be called inside the user +* Therefore \ref Cy_SCB_UART_Interrupt must be called inside the user * interrupt handler to make the High-Level API work. To monitor status * of transmit operation, use \ref Cy_SCB_UART_GetTransmitStatus and * \ref Cy_SCB_UART_GetReceiveStatus to monitor receive status appropriately. @@ -231,7 +231,7 @@ * parameter to configure TX FIFO level value. \n * For example, the TX FIFO has 0 data elements (empty) and the TX FIFO level * is 7. The TX trigger signal is active until DMA loads TX FIFO -* with 8 data elements (note that after the first TX load operation, the data +* with 8 data elements (note that after the first TX load operation, the data * element goes to the shift register and TX FIFO is empty). * * To route SCB TX or RX trigger signals to DMA controller use \ref group_trigmux @@ -253,24 +253,24 @@ * power mode transition function. Refer to \ref group_syspm driver for more * information about power mode transitions and callback registration. * -* The UART is disabled during Deep Sleep and Hibernate and stops driving -* the output pins. The state of the UART output pins TX and RTS is High-Z, +* The UART is disabled during Deep Sleep and Hibernate and stops driving +* the output pins. The state of the UART output pins TX and RTS is High-Z, * which can cause unexpected behavior of the UART receiver due to possible -* glitches on these lines. These pins must be set to the inactive state before +* glitches on these lines. These pins must be set to the inactive state before * entering Deep Sleep or Hibernate mode. -* These pins must keep the inactive level (the same state -* when UART TX is enabled and does not transfer data) before entering Deep -* Sleep or Hibernate mode. To do that, write the GPIO data register of each pin -* to the inactive level for each output pin. Then configure High-Speed Input -* Output Multiplexer (HSIOM) of each pin to be controlled by the GPIO (use -* \ref group_gpio driver API). After exiting Deep Sleep mode the UART -* must be enabled and the pins configuration restored to return the -* UART control of the pins (after exiting Hibernate mode, the -* system initialization code does the same). Copy either or -* both \ref Cy_SCB_UART_DeepSleepCallback and \ref Cy_SCB_UART_HibernateCallback +* These pins must keep the inactive level (the same state +* when UART TX is enabled and does not transfer data) before entering Deep +* Sleep or Hibernate mode. To do that, write the GPIO data register of each pin +* to the inactive level for each output pin. Then configure High-Speed Input +* Output Multiplexer (HSIOM) of each pin to be controlled by the GPIO (use +* \ref group_gpio driver API). After exiting Deep Sleep mode the UART +* must be enabled and the pins configuration restored to return the +* UART control of the pins (after exiting Hibernate mode, the +* system initialization code does the same). Copy either or +* both \ref Cy_SCB_UART_DeepSleepCallback and \ref Cy_SCB_UART_HibernateCallback * as appropriate, and make the changes described above inside the function. -* Alternately, external pull-up or pull-down resistors can be connected -* to the appropriate UART lines to keep them inactive during Deep-Sleep or +* Alternately, external pull-up or pull-down resistors can be connected +* to the appropriate UART lines to keep them inactive during Deep-Sleep or * Hibernate. * * \defgroup group_scb_uart_macros Macros @@ -414,8 +414,8 @@ typedef struct stc_scb_uart_config cy_en_scb_uart_parity_t parity; /** - * Enables a digital 3-tap median filter (2 out of 3 voting) to be applied - * to the input of the RX FIFO to filter glitches on the line (for IrDA, + * Enables a digital 3-tap median filter (2 out of 3 voting) to be applied + * to the input of the RX FIFO to filter glitches on the line (for IrDA, * this parameter is ignored) * */ @@ -762,8 +762,8 @@ cy_en_syspm_status_t Cy_SCB_UART_HibernateCallback(cy_stc_syspm_callback_params_ /** * \defgroup group_scb_uart_macros_receive_status UART Receive Statuses * \{ -* Macros to check current UART receive status returned by -* \ref Cy_SCB_UART_GetReceiveStatus function. +* Macros to check current UART receive status returned by +* \ref Cy_SCB_UART_GetReceiveStatus function. * Each UART receive status is encoded in a separate bit, therefore multiple bits * may be set to indicate the current status. */ @@ -791,8 +791,8 @@ cy_en_syspm_status_t Cy_SCB_UART_HibernateCallback(cy_stc_syspm_callback_params_ /** * \defgroup group_scb_uart_macros_transmit_status UART Transmit Status * \{ -* Macros to check current UART transmit status returned by -* \ref Cy_SCB_UART_GetTransmitStatus function. +* Macros to check current UART transmit status returned by +* \ref Cy_SCB_UART_GetTransmitStatus function. * Each UART transmit status is encoded in a separate bit, therefore multiple bits * may be set to indicate the current status. */ @@ -1042,21 +1042,21 @@ __STATIC_INLINE uint32_t Cy_SCB_UART_GetRtsFifoLevel(CySCB_Type const *base) ****************************************************************************//** * * Enables the skip start-bit functionality. -* When skip start is enabled the UART hardware does not synchronize to a -* start bit but synchronizes to the first rising edge. To create a rising edge, -* the first data bit must be a 1. This feature is useful when the start bit +* When skip start is enabled the UART hardware does not synchronize to a +* start bit but synchronizes to the first rising edge. To create a rising edge, +* the first data bit must be a 1. This feature is useful when the start bit * falling edge is used to wake the device through a GPIO interrupt. * * \param base * The pointer to the UART SCB instance. * * \note -* When skip start-bit feature is enabled, it is applied (UART synchronizes -* to the first rising edge after start bit) whenever the SCB is enabled. -* This can cause incorrect UART synchronization and data reception when -* the first data bit is not a 1. Therefore, disable the skip start-bit +* When skip start-bit feature is enabled, it is applied (UART synchronizes +* to the first rising edge after start bit) whenever the SCB is enabled. +* This can cause incorrect UART synchronization and data reception when +* the first data bit is not a 1. Therefore, disable the skip start-bit * when it should not be applied. -* Note that SCB is disabled before enter Deep Sleep mode or after calling +* Note that SCB is disabled before enter Deep Sleep mode or after calling * \ref Cy_SCB_UART_Disable. * *******************************************************************************/ @@ -1523,4 +1523,3 @@ __STATIC_INLINE void Cy_SCB_UART_RegisterCallback(CySCB_Type const *base, #endif /* (CY_SCB_UART_H) */ /* [] END OF FILE */ - diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_sd_host.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_sd_host.h index 989dafbab0..8f869bdbc3 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_sd_host.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_sd_host.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_sd_host.h -* \version 1.50 +* \version 1.50.1 * * This file provides constants and parameter values for * the SD Host Controller driver. @@ -32,7 +32,7 @@ * an SD card, eMMc card or a SDIO device. * * The functions and other declarations used in this driver are in cy_sd_host.h. -* You can include cy_pdl.h (ModusToolbox only) to get access to all functions +* You can include cy_pdl.h to get access to all functions * and declarations in the PDL. * * Features: @@ -275,6 +275,11 @@ *
VersionChangesReason for Change
2.50Fixed the \ref Cy_SCB_SPI_SetActiveSlaveSelectPolarity function to +* properly configure the polarity of the slave select line. \ref Cy_SCB_SPI_SetActiveSlaveSelectPolarity function works incorrectly.
2.40.2Minor documentation updates.Documentation enhancement.
2.40Update level selection logic of RX FIFO trigger in the Cy_SCB_UART_Receive().Fix possible stuck if the RTS level is less than the RX FIFO level.
2.20Flattened the organization of the driver source code into the single +* Flattened the organization of the driver source code into the single * source directory and the single include directory. * Driver library directory-structure simplification.
Added register access layer. Use register access macros instead * of direct register access using dereferenced pointers.Makes register access device-independent, so that the PDL does +* Makes register access device-independent, so that the PDL does * not need to be recompiled for each supported part number.
Added the enableDigitalFilter, highPhaseDutyCycle and lowPhaseDutyCycle +* Added the enableDigitalFilter, highPhaseDutyCycle and lowPhaseDutyCycle * fields to the \ref cy_stc_scb_i2c_config_t configuration structure. * Added the I2C master data rate configuration using the configuration structure. *
Fixed the \ref Cy_SCB_I2C_SetDataRate function to properly configure data rates +* Fixed the \ref Cy_SCB_I2C_SetDataRate function to properly configure data rates * greater than 400 kbps in Master and Master-Slave modes. \n * Added verification that clk_scb is within the valid range for the desired data rate. -* The analog filter was enabled for all data rates in Master and Master-Slave modes. +* The analog filter was enabled for all data rates in Master and Master-Slave modes. * This prevents reaching the maximum supported data rate of 1000 kbps which requires a digital filter. *
2.10Fixed the ReStart condition generation sequence for a write * transaction in the \ref Cy_SCB_I2C_MasterWrite function.The driver can notify about a zero length write transaction completion -* before the address byte is sent if the \ref Cy_SCB_I2C_MasterWrite -* function execution was interrupted between setting the restart +* The driver can notify about a zero length write transaction completion +* before the address byte is sent if the \ref Cy_SCB_I2C_MasterWrite +* function execution was interrupted between setting the restart * generation command and writing the address byte into the TX FIFO.
Updated the Start condition generation sequence in the \ref +* Updated the Start condition generation sequence in the \ref * Cy_SCB_I2C_MasterWrite and \ref Cy_SCB_I2C_MasterRead.
The SPI callback passed incorrect event value if error event occurred.
Fixed the \ref Cy_SCB_I2C_MasterSendReStart function to properly -* generate the ReStart condition when the previous transaction was +* Fixed the \ref Cy_SCB_I2C_MasterSendReStart function to properly +* generate the ReStart condition when the previous transaction was * a write.The master interpreted the address byte written into the TX FIFO as a * data byte and continued a write transaction. The ReStart condition was @@ -285,10 +296,10 @@ * firmware.The observed slave operation failure depends on whether Level 2 assert * is enabled or not. Enabled: the device stuck in the fault handler due -* to the assert assignment in the \ref Cy_SCB_I2C_Interrupt. Disabled: -* the slave sets the transaction completion status and notifies on the +* to the assert assignment in the \ref Cy_SCB_I2C_Interrupt. Disabled: +* the slave sets the transaction completion status and notifies on the * transaction completion event after the address was NACKed. The failure -* is observed only when the slave is configured to accept an address in +* is observed only when the slave is configured to accept an address in * the RX FIFO.
* * +* +* +* +* +* * * * * * * @@ -117,7 +117,7 @@ * * * -* * * @@ -137,17 +137,17 @@ * operation. * * \subsection group_smartio_comb_feedback LUT Combinatorial Feedback -* +* * Since the LUTs can be configured as purely (or partially) combinatorial elements and since they * can chain to each other in any fashion, combinatorial timing loops can occur. This causes * oscillations that burn power and create unpredictable behavior. If a feedback is required, the * signals should always go through a flip-flop before feeding back. For example, the following is a * potentially problematic design; LUT1 and LUT2 are configured in combinatorial mode, where their -* respective outputs feed into the inputs of the other. This will result in oscillations. +* respective outputs feed into the inputs of the other. This will result in oscillations. * To prevent it, one of the LUTs should be configured to Gated Output mode. * * \subsection group_smartio_lpm Low Power Mode -* +* * The Smart I/O hardware is capable of operating during chip Deep-Sleep mode. The block has * the following requirements when operating in this mode: * @@ -155,7 +155,7 @@ * \ref group_smartio_clk_rst for more details. * - All signals in the block (including the clock) must be less than 1 MHz when in Deep-Sleep * mode. -* - The hold override functionality should be enabled when entering Deep-Sleep mode. +* - The hold override functionality should be enabled when entering Deep-Sleep mode. * This functionality should then be disabled when the chip is not in this mode. * * \section group_smartio_more_information More Information @@ -188,7 +188,7 @@ * * -* * *
VersionChangesReason for Change
1.50.1Minor documentation updates.Documentation enhancement.
1.50The default value of the SD-clock rump-up time during a wakeup * from Deep Sleep is reduced to 1 us, for details, diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_smartio.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_smartio.h index 1d9d7a52ba..4510beb2ee 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_smartio.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_smartio.h @@ -1,13 +1,13 @@ /***************************************************************************//** * \file cy_smartio.h -* \version 1.0 +* \version 1.0.1 * * \brief * Provides an API declaration of the Smart I/O driver * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -27,11 +27,11 @@ * \addtogroup group_smartio * \{ * The Smart I/O driver provides an API to configure and access the Smart I/O hardware -* present between the GPIOs (pins) and HSIOMs (pin muxes) on select device ports. +* present between the GPIOs (pins) and HSIOMs (pin muxes) on select device ports. * -* The functions and other declarations used in this driver are in cy_smartio.h. -* You can include cy_pdl.h (ModusToolbox only) to get access to all functions -* and declarations in the PDL. +* The functions and other declarations used in this driver are in cy_smartio.h. +* You can include cy_pdl.h to get access to all functions +* and declarations in the PDL. * * It can be used to perform simple logic operations on peripheral and GPIO signals at * the GPIO port. Features include, @@ -44,7 +44,7 @@ * \section group_smartio_configuration Configuration Considerations * * \subsection group_smartio_routing_fabric Routing Fabric -* +* * The Smart I/O routing fabric is divided into two portions, where each portion is capable * of accepting half of the data or GPIO signals. The LUTs have the following structure. * @@ -55,21 +55,21 @@ * example, LUT 0 can go to either io0 terminal output or chip0 terminal output or both. * * \subsection group_smartio_single_lut Single Source LUT Input -* +* * If a LUT is used, all three inputs to the LUT must be designated. For example, even If a LUT is * used to accept a single source as its input, all three inputs must accept that same signal. The * lookup table should then be designed such that it only changes the output value when all -* three inputs satisfy the same condition. For example, consider the case where the signal on -* data0 must be inverted before being passed to io0. LUT0 accepts chip0 as input 0, 1 and 2. +* three inputs satisfy the same condition. For example, consider the case where the signal on +* data0 must be inverted before being passed to io0. LUT0 accepts chip0 as input 0, 1 and 2. * The truth table is defined such that it outputs a logic 1 only when the inputs are all 0. * * \subsection group_smartio_clk_rst Clock and Reset Behavior * -* The Smart I/O hardware drives its synchronous elements using a single clock source. +* The Smart I/O hardware drives its synchronous elements using a single clock source. * Depending on the clock source, the Smart I/O will have different reset behaviors, which * will reset all the flip-flops in the LUTs and synchronizers to logic 0. The configuration * registers will retain their values unless coming out of Power on Reset (POR). Notes: -* +* * - If the block is only disabled, the values in the LUT flip-flips and I/O synchronizers are * held as long as the chip remains in a valid power mode. * - The selected clock for the fabric's synchronous logic is not phase aligned with other @@ -90,7 +90,7 @@ * Reset on POR2 clock edgesIf chosen as the clock source, that particular signal cannot also be used as an input -* to a LUT as it may cause a race condition. The fabric will be enabled after 2 clock +* to a LUT as it may cause a race condition. The fabric will be enabled after 2 clock * edges of the signal on the gpio terminal.
LFCLKReset when going to Hibernate and POR2 clock edgesThe fabric will be enabled after 2 clock edges of the low frequency clock (LFCLK). +* The fabric will be enabled after 2 clock edges of the low frequency clock (LFCLK). * Any synchronous logic in the LUTs will be reset to 0 when in hibernate mode.
AA pointer parameter in a function prototype should be declared as pointer to const * if the pointer is not used to modify the addressed object.Base address pointers are always constant in drivers. No need to pick and choose +* Base address pointers are always constant in drivers. No need to pick and choose * const declaration based on function construction.
@@ -197,6 +197,11 @@ * * * +* +* +* +* +* * * * @@ -283,7 +288,7 @@ extern "C" { /** * Smart I/O driver error codes */ -typedef enum +typedef enum { CY_SMARTIO_SUCCESS = 0x00u, /**< Returned successful */ CY_SMARTIO_BAD_PARAM = CY_SMARTIO_ID | CY_PDL_STATUS_ERROR | 0x01u, /**< Bad parameter was passed */ @@ -796,8 +801,8 @@ __STATIC_INLINE uint8_t Cy_SmartIO_GetLutMap(SMARTIO_PRT_Type* base, cy_en_smart *******************************************************************************/ __STATIC_INLINE cy_en_smartio_dudata_t Cy_SmartIO_GetDuData(SMARTIO_PRT_Type* base, cy_en_smartio_datanum_t dataNum) { - return ((dataNum == CY_SMARTIO_DATA0) ? - (cy_en_smartio_dudata_t)_FLD2VAL(SMARTIO_PRT_DU_SEL_DU_DATA0_SEL, SMARTIO_PRT_DU_SEL(base)) : + return ((dataNum == CY_SMARTIO_DATA0) ? + (cy_en_smartio_dudata_t)_FLD2VAL(SMARTIO_PRT_DU_SEL_DU_DATA0_SEL, SMARTIO_PRT_DU_SEL(base)) : (cy_en_smartio_dudata_t)_FLD2VAL(SMARTIO_PRT_DU_SEL_DU_DATA1_SEL, SMARTIO_PRT_DU_SEL(base))); } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_smif.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_smif.h index 606d8204c5..25a1b162ed 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_smif.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_smif.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_smif.h -* \version 1.50 +* \version 1.50.1 * * Provides an API declaration of the Cypress SMIF driver. * @@ -214,6 +214,11 @@ *
VersionChangesReason for Change
1.0.1Minor documentation updates.Documentation enhancement.
1.0The initial version.
* * +* +* +* +* +* * *
VersionChangesReason for Change
1.50.1Minor documentation updates. Documentation improvement.
1.50Added a new function: \ref Cy_SMIF_MemLocateHybridRegion.\n * Added a new structure \ref cy_stc_smif_hybrid_region_info_t.\n diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_smif_memslot.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_smif_memslot.h index 69341a275f..30c5e86f99 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_smif_memslot.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_smif_memslot.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_smif_memslot.h -* \version 1.50 +* \version 1.50.1 * * \brief * This file provides the constants and parameter values for the memory-level diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_sysanalog.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_sysanalog.h index 083eca4243..4c9da78043 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_sysanalog.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_sysanalog.h @@ -1,12 +1,12 @@ /***************************************************************************//** * \file cy_sysanalog.h -* \version 1.10 +* \version 1.10.1 * * Header file for the system level analog reference driver. * ******************************************************************************** * \copyright -* Copyright 2017-2019 Cypress Semiconductor Corporation +* Copyright 2017-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -29,9 +29,9 @@ * This driver provides an interface for configuring the Analog Reference (AREF) block * and querying the INTR_CAUSE register of the PASS. * -* The functions and other declarations used in this driver are in cy_sysanalog.h. -* You can include cy_pdl.h (ModusToolbox only) to get access to all functions -* and declarations in the PDL. +* The functions and other declarations used in this driver are in cy_sysanalog.h. +* You can include cy_pdl.h to get access to all functions +* and declarations in the PDL. * * The AREF block has the following features: * @@ -140,8 +140,13 @@ * * * +* +* +* +* +* * -* * @@ -149,7 +154,7 @@ * * -* * * @@ -616,4 +621,3 @@ __STATIC_INLINE void Cy_SysAnalog_IztatSelect(cy_en_sysanalog_iztat_source_t izt /** \} group_sysanalog */ /* [] END OF FILE */ - diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_sysclk.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_sysclk.h index a0e966367e..6871aee155 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_sysclk.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_sysclk.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_sysclk.h -* \version 2.0 +* \version 2.10 * * Provides an API declaration of the sysclk driver. * @@ -26,20 +26,20 @@ * \addtogroup group_sysclk * \{ * The System Clock (SysClk) driver contains the API for configuring system and -* peripheral clocks. +* peripheral clocks. * -* The functions and other declarations used in this driver are in cy_sysclk.h. -* You can include cy_pdl.h (ModusToolbox only) to get access to all functions -* and declarations in the PDL. +* The functions and other declarations used in this driver are in cy_sysclk.h. +* You can include cy_pdl.h to get access to all functions +* and declarations in the PDL. * * Firmware uses the API to configure , enable, or disable a clock. -* +* * The clock system includes a variety of resources that can vary per device, including: * - Internal clock sources such as internal oscillators * - External clock sources such as crystal oscillators or a signal on an I/O pin * - Generated clocks such as an FLL, a PLL, and peripheral clocks * -* Consult the Technical Reference Manual for your device for details of the +* Consult the Technical Reference Manual for your device for details of the * clock system. * * The PDL defines clock system capabilities in:\n @@ -52,7 +52,7 @@ * Consult the Technical Reference Manual for your device for details. * ![](sysclk_tree.png) * -* The sysclk driver supports multiple peripheral clocks, as well as the fast +* The sysclk driver supports multiple peripheral clocks, as well as the fast * clock, slow clock, backup domain clock, timer clock, and pump clock. The API * for any given clock contains the functions to manage that clock. Functions * for clock measurement and trimming are also provided. @@ -61,6 +61,8 @@ * The availability of clock functions depend on the availability of the chip * resources that support those functions. Consult the device TRM before * attempting to use these functions. +* For PSoC 64 devices the clocks configurations are restricted and limited. +* Refer to the PRA driver, and the TRM and datasheet for details. * * PSoC 6 power modes limit the maximum clock frequency. * Refer to the SysPm driver and the TRM for details. @@ -100,10 +102,38 @@ * *
VersionChangesReason for Change
1.10.1Minor documentation updates.Documentation enhancement.
1.10Flattened the organization of the driver source code into the single +* Flattened the organization of the driver source code into the single * source directory and the single include directory. * Driver library directory-structure simplification.
Added register access layer. Use register access macros instead * of direct register access using dereferenced pointers.Makes register access device-independent, so that the PDL does +* Makes register access device-independent, so that the PDL does * not need to be recompiled for each supported part number.
* +* \section group_sysclk_errata Known Issues +* +* +* +* +* +* +*
IssueWorkaround
The CLKLF does not work if after transition to the new clock +* source the previous one is immediately disabled. +* Wait 4 clock cycles of previous CLKLF clock source before disabling it.
+* * \section group_sysclk_changelog Changelog * * * +* +* +* +* +* +* +* +* +* +* +* +* +* * * * * @@ -140,7 +170,7 @@ * * * -* @@ -177,7 +207,7 @@ * * * -* * @@ -197,12 +227,12 @@ * * -* * * * -* -* * * @@ -287,7 +317,7 @@ * \{ * Clock paths are a series of multiplexers that allow a source clock * to drive multiple clocking resources down the chain. These paths are -* used for active domain clocks that are not operational during chip +* used for active domain clocks that are not operational during chip * Deep Sleep, hibernate and off modes. Illustrated below is a diagram * of the clock paths for the PSoC 63 series, showing the first three * clock paths. The source clocks for these paths are highlighted in @@ -300,8 +330,8 @@ * - Digital Signal (DSI): Digital signal from a UDB source * * Some clock paths such as path 0 and path 1 have additional resources -* that can be utilized to provide a higher frequency clock. For example, -* path 0 source clock can be used as the reference clock for the FLL and +* that can be utilized to provide a higher frequency clock. For example, +* path 0 source clock can be used as the reference clock for the FLL and * path 1 source clock can be used as the reference clock for the PLL. * * ![](sysclk_path_source.png) @@ -324,7 +354,7 @@ * * - They may have different frequency ranges. * - The FLL starts up (locks) faster and consumes less current than the PLL. -* - The FLL accepts a source clock with lower frequency than PLL, such as the WCO (32 KHz). +* - The FLL accepts a source clock with lower frequency than PLL, such as the WCO (32 KHz). * - The FLL does not lock phase. The hardware consist of a counter with a * current-controlled oscillator (CCO). The counter counts the number of output * clock edges in a reference clock period and adjusts the CCO until the @@ -334,11 +364,11 @@ * ![](sysclk_fll.png) * * The SysClk driver supports two models for configuring the FLL. The first -* model is to call the Cy_SysClk_FllConfigure() function, which calculates the +* model is to call the Cy_SysClk_FllConfigure() function, which calculates the * necessary parameters for the FLL at run-time. This may be necessary for dynamic -* run-time changes to the FLL. However this method is slow as it needs to perform -* the calculation before configuring the FLL. The other model is to call -* Cy_SysClk_FllManualConfigure() function with pre-calculated parameter values. +* run-time changes to the FLL. However this method is slow as it needs to perform +* the calculation before configuring the FLL. The other model is to call +* Cy_SysClk_FllManualConfigure() function with pre-calculated parameter values. * This method is faster but requires prior knowledge of the necessary parameters. * Consult the device TRM for the FLL calculation equations. * @@ -356,15 +386,15 @@ * * - They may have different frequency ranges. * - The PLL starts up more slowly and consumes more current than the FLL. -* - The PLL requires a higher frequency source clock than PLL. +* - The PLL requires a higher frequency source clock than PLL. * ![](sysclk_pll.png) * * The SysClk driver supports two models for configuring the PLL. The first -* model is to call the Cy_SysClk_PllConfigure() function, which calculates the +* model is to call the Cy_SysClk_PllConfigure() function, which calculates the * necessary parameters for the PLL at run-time. This may be necessary for dynamic -* run-time changes to the PLL. However this method is slow as it needs to perform -* the calculation before configuring the PLL. The other model is to call -* Cy_SysClk_PllManualConfigure() function with pre-calculated parameter values. +* run-time changes to the PLL. However this method is slow as it needs to perform +* the calculation before configuring the PLL. The other model is to call +* Cy_SysClk_PllManualConfigure() function with pre-calculated parameter values. * This method is faster but requires prior knowledge of the necessary parameters. * Consult the device TRM for the PLL calculation equations. * @@ -374,15 +404,15 @@ * \defgroup group_sysclk_ilo Internal Low-Speed Oscillator (ILO) * \{ * The ILO operates with no external components and outputs a stable clock at -* 32.768 kHz nominal. The ILO is relatively low power and low accuracy. It is +* 32.768 kHz nominal. The ILO is relatively low power and low accuracy. It is * available in all power modes and can be used as a source for the Backup domain clock. * ![](sysclk_backup.png) * * To ensure the ILO remains active in Hibernate mode, and across power-on-reset -* (POR) or brown out detect (BOD), firmware must call Cy_SysClk_IloHibernateOn(). +* (POR) or brown out detect (BOD), firmware must call Cy_SysClk_IloHibernateOn(). * * Additionally, the ILO clock can be trimmed to +/- 1.5% of nominal frequency using -* a higher precision clock source. Use the \ref group_sysclk_calclk API to measure +* a higher precision clock source. Use the \ref group_sysclk_calclk API to measure * the current ILO frequency before trimming. * * \note The ILO is always the source clock for the \ref group_wdt. Therefore: @@ -396,18 +426,18 @@ * PILO provides a higher accuracy 32.768 kHz clock than the \ref group_sysclk_ilo "ILO". * When periodically calibrated using a high-accuracy clock such as the * \ref group_sysclk_eco "ECO", the PILO can achieve 250 ppm accuracy of nominal frequency. -* The PILO is capable of operating in device Active, Sleep and Deep-Sleep power modes. +* The PILO is capable of operating in device Active, Sleep and Deep-Sleep power modes. * It is not available in Hibernate mode. * * The PILO can be used as a source for the \ref group_sysclk_clk_lf. However, * because PILO is disabled in Hibernate mode, RTC timers cannot operate in this mode * when clocked using the PILO. Instead, either the \ref group_sysclk_ilo "ILO" or -* \ref group_sysclk_wco "WCO" should be used when hibernate operation is required. +* \ref group_sysclk_wco "WCO" should be used when hibernate operation is required. * * ![](sysclk_backup.png) * * Periodic calibration to a high-accuracy clock (such as ECO) is required to -* maintain accuracy. The application should use the functions described in the +* maintain accuracy. The application should use the functions described in the * \ref group_sysclk_calclk API to measure the current PILO frequency before trimming. * * \defgroup group_sysclk_pilo_funcs Functions @@ -450,11 +480,11 @@ * Deep Sleep mode entry. * * This function can be called either by itself before initiating low-power mode -* entry or it can be used in conjunction with the SysPm driver as a registered -* callback. To do so, register this function as a callback before calling -* Cy_SysPm_DeepSleep(). Specify \ref CY_SYSPM_DEEPSLEEP as the callback type, +* entry or it can be used in conjunction with the SysPm driver as a registered +* callback. To do so, register this function as a callback before calling +* Cy_SysPm_DeepSleep(). Specify \ref CY_SYSPM_DEEPSLEEP as the callback type, * and call Cy_SysPm_RegisterCallback(). -* +* * \note If the FLL or PLL source is the ECO, this function must be called. * * \defgroup group_sysclk_pm_funcs Functions @@ -463,7 +493,7 @@ * \{ * The WCO is a highly accurate 32.768 kHz clock source capable of operating * in all power modes (excluding the Off mode). It is the primary clock source for -* the backup domain clock, which is used by the real-time clock (RTC). The +* the backup domain clock, which is used by the real-time clock (RTC). The * WCO can also be used as a source for the low-frequency clock to support other * low power mode peripherals. * @@ -472,7 +502,7 @@ * The WCO requires the configuration of the dedicated WCO pins (SRSS_WCO_IN_PIN, * SRSS_WCO_OUT_PIN). These must be configured as Analog Hi-Z drive modes and the * HSIOM selection set to GPIO. The WCO can also be used in bypass mode, where -* an external 32.768 kHz square wave is brought in directly through the +* an external 32.768 kHz square wave is brought in directly through the * SRSS_WCO_OUT_PIN pin. * * \defgroup group_sysclk_wco_funcs Functions @@ -496,9 +526,9 @@ * * Note this is a particular example. The actual tree may vary depending on the device series. * Consult the Technical Reference Manual for your device for details. -* +* * High frequency clocks are sourced by path clocks, which should be configured -* first. An exception to this rule is CLK_HF[0], which cannot be disabled. +* first. An exception to this rule is CLK_HF[0], which cannot be disabled. * This divided clock drives the core processors and the peripherals in the system. * In order to update its clock source, CLK_HF[0] source must be selected without * disabling the clock. @@ -523,7 +553,7 @@ * \{ * The peripheral clock is a divided clock of CLK_HF0 (\ref group_sysclk_clk_hf "HF Clocks"). * It is the source clock for the \ref group_sysclk_clk_slow, and most active domain -* peripheral clocks (\ref group_sysclk_clk_peripheral). A divider value of 1~256 +* peripheral clocks (\ref group_sysclk_clk_peripheral). A divider value of 1~256 * can be used to further divide the CLK_HF[0] to a desired clock speed for the peripherals. * * ![](sysclk_peri.png) @@ -532,8 +562,8 @@ * \} * \defgroup group_sysclk_clk_peripheral Peripherals Clock Dividers * \{ -* There are multiple peripheral clock dividers that, in effect, create -* multiple separate peripheral clocks. The available dividers vary per device +* There are multiple peripheral clock dividers that, in effect, create +* multiple separate peripheral clocks. The available dividers vary per device * series. As an example, for the PSoC 63 series there are 29 dividers: * * - eight 8-bit dividers @@ -542,7 +572,7 @@ * - one fractional 24.5-bit divider (24 integer bits, 5 fractional bits) * * -* The 8-bit and 16-bit dividers are integer dividers. A divider value of 1 +* The 8-bit and 16-bit dividers are integer dividers. A divider value of 1 * means the output frequency matches the input frequency (that is, there is * no change). Otherwise the frequency is divided by the value of the divider. * For example, if the input frequency is 50 MHz, and the divider is value 10, @@ -558,7 +588,7 @@ * * Each peripheral can connect to any one of the programmable dividers. A * particular peripheral clock divider can drive multiple peripherals. -* +* * The SysClk driver also supports phase aligning two peripheral clock dividers using * Cy_SysClk_PeriphEnablePhaseAlignDivider(). Alignment works for both integer * and fractional dividers. The divider to which a second divider is aligned @@ -570,8 +600,8 @@ * \defgroup group_sysclk_clk_slow Slow Clock * \{ * The slow clock is the source clock for the "slow" processor (e.g. Cortex-M0+ in PSoC 6). -* This clock is a divided version of the \ref group_sysclk_clk_peri, which in turn is -* a divided version of CLK_HF[0] (\ref group_sysclk_clk_hf "HF Clocks"). A divider +* This clock is a divided version of the \ref group_sysclk_clk_peri, which in turn is +* a divided version of CLK_HF[0] (\ref group_sysclk_clk_hf "HF Clocks"). A divider * value of 1~256 can be used to further divide the Peri clock to a desired clock speed * for the processor. * @@ -581,7 +611,7 @@ * \} * \defgroup group_sysclk_alt_hf Alternative High-Frequency Clock * \{ -* In the BLE-enabled PSoC6 devices, the \ref group_ble_clk clock is +* In the BLE-enabled PSoC6 devices, the \ref group_ble_clk clock is * connected to the system Alternative High-Frequency Clock input. * * \defgroup group_sysclk_alt_hf_funcs Functions @@ -591,7 +621,7 @@ * The low-frequency clock is the source clock for the \ref group_mcwdt * and can be the source clock for \ref group_sysclk_clk_bak, which drives the * \ref group_rtc. -* +* * The low-frequency clock has three possible source clocks: * \ref group_sysclk_ilo "ILO", \ref group_sysclk_pilo "PILO", and * \ref group_sysclk_wco "WCO". @@ -603,10 +633,10 @@ * \} * \defgroup group_sysclk_clk_timer Timer Clock * \{ -* The timer clock can be a source for the alternative clock driving -* the \ref group_arm_system_timer. It can also be used as a reference clock +* The timer clock can be a source for the alternative clock driving +* the \ref group_arm_system_timer. It can also be used as a reference clock * for a counter in the \ref group_energy_profiler "Energy Profiler". -* +* * The timer clock is a divided clock of either the IMO or CLK_HF[0] * (\ref group_sysclk_clk_hf "HF Clocks"). * @@ -617,8 +647,8 @@ * \{ * The pump clock is a clock source used to provide analog precision in low voltage * applications. Depending on the usage scenario, it may be required to drive the -* internal voltage pump for the Continuous Time Block mini (CTBm) in the analog -* subsystem. The pump clock is a divided clock of one of the clock paths +* internal voltage pump for the Continuous Time Block mini (CTBm) in the analog +* subsystem. The pump clock is a divided clock of one of the clock paths * (\ref group_sysclk_path_src). * * \defgroup group_sysclk_clk_pump_funcs Functions @@ -655,6 +685,9 @@ #include "cy_device_headers.h" #include "cy_syslib.h" #include "cy_syspm.h" +#if defined(CY_DEVICE_SECURE) + #include "cy_pra.h" +#endif /* defined(CY_DEVICE_SECURE) */ #if defined(__cplusplus) @@ -668,7 +701,7 @@ extern "C" { /** Driver major version */ #define CY_SYSCLK_DRV_VERSION_MAJOR 2 /** Driver minor version */ -#define CY_SYSCLK_DRV_VERSION_MINOR 0 +#define CY_SYSCLK_DRV_VERSION_MINOR 10 /** Sysclk driver identifier */ #define CY_SYSCLK_ID CY_PDL_DRV_ID(0x12U) @@ -732,7 +765,16 @@ uint32_t Cy_SysClk_ExtClkGetFrequency(void); #define CY_SYSCLK_ECOSTAT_INACCURATE 1UL /**< \brief ECO may not be meeting accuracy and duty cycle specs */ #define CY_SYSCLK_ECOSTAT_STABLE 2UL /**< \brief ECO has fully stabilized */ /** \} */ - +# if (defined(CY_DEVICE_SECURE)) +/** PRA structure for Cy_SysClk_EcoConfigure function parameters */ +typedef struct +{ + uint32_t praClkEcofreq; /**< freq */ + uint32_t praCsum; /**< cSum */ + uint32_t praEsr; /**< esr */ + uint32_t praDriveLevel; /**< drivelevel */ +} cy_stc_pra_clk_eco_configure_t; +#endif /* (defined(CY_DEVICE_SECURE)) */ /** \} group_sysclk_macros */ /** \cond */ @@ -740,6 +782,7 @@ uint32_t Cy_SysClk_ExtClkGetFrequency(void); /** \endcond */ + /** * \addtogroup group_sysclk_eco_funcs * \{ @@ -763,7 +806,11 @@ __STATIC_INLINE uint32_t Cy_SysClk_EcoGetStatus(void); *******************************************************************************/ __STATIC_INLINE void Cy_SysClk_EcoDisable(void) { +#if ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) + CY_PRA_FUNCTION_CALL_VOID_PARAM(CY_PRA_MSG_TYPE_FUNC_POLICY, CY_PRA_CLK_FUNC_ECO_DISABLE, 0UL); +#else SRSS_CLK_ECO_CONFIG &= ~SRSS_CLK_ECO_CONFIG_ECO_EN_Msk; +#endif /* ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) */ } @@ -822,6 +869,14 @@ typedef enum * Make sure the PILO clock sources in available on used device. */ } cy_en_clkpath_in_sources_t; +#if (defined(CY_DEVICE_SECURE)) +/** PRA structure for Cy_SysClk_ClkPathSetSource function parameters */ +typedef struct +{ + uint32_t clk_path; /**< clkpath */ + cy_en_clkpath_in_sources_t source; /**< Source */ +} cy_stc_pra_clkpathsetsource_t; +#endif /** \} group_sysclk_path_src_enums */ /** @@ -887,6 +942,7 @@ typedef struct cy_en_fll_pll_output_mode_t outputMode; /**< CLK_FLL_CONFIG3 register, BYPASS_SEL bits */ uint16_t cco_Freq; /**< CLK_FLL_CONFIG4 register, CCO_FREQ bits */ } cy_stc_fll_manual_config_t; + /** \} group_sysclk_fll_structs */ /** @@ -929,12 +985,12 @@ __STATIC_INLINE bool Cy_SysClk_FllIsEnabled(void) * Reports whether the FLL is locked first time during FLL starting. * Intended to be used with \ref Cy_SysClk_FllEnable with zero timeout. * -* \return +* \return * false = not locked \n * true = locked * * \note -* The unlock occurrence may appear during FLL normal operation, so this function +* The unlock occurrence may appear during FLL normal operation, so this function * is not recommended to check the FLL normal operation stability. * * \funcusage @@ -954,9 +1010,14 @@ __STATIC_INLINE bool Cy_SysClk_FllLocked(void) * Disables the FLL and the CCO. * * \return \ref cy_en_sysclk_status_t +* CY_SYSCLK_INVALID_STATE - ECO already enabled +* For the PSoC 64 devices there are possible situations when function returns +* the PRA error status code. This is because for PSoC 64 devices the function +* uses the PRA driver to change the protected registers. Refer to +* \ref cy_en_pra_status_t for more details. * -* \note -* Call \ref SystemCoreClockUpdate after this function calling +* \note +* Call \ref SystemCoreClockUpdate after this function calling * if it affects the CLK_HF0 frequency. * * \note @@ -969,10 +1030,15 @@ __STATIC_INLINE bool Cy_SysClk_FllLocked(void) *******************************************************************************/ __STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_FllDisable(void) { +#if ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) + return (cy_en_sysclk_status_t)CY_PRA_FUNCTION_CALL_RETURN_PARAM(CY_PRA_MSG_TYPE_FUNC_POLICY, CY_PRA_CLK_FUNC_FLL_DISABLE, 0UL); + +#else CY_REG32_CLR_SET(SRSS_CLK_FLL_CONFIG3, SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, CY_SYSCLK_FLLPLL_OUTPUT_INPUT); SRSS_CLK_FLL_CONFIG &= ~SRSS_CLK_FLL_CONFIG_FLL_ENABLE_Msk; SRSS_CLK_FLL_CONFIG4 &= ~SRSS_CLK_FLL_CONFIG4_CCO_ENABLE_Msk; return (CY_SYSCLK_SUCCESS); +#endif /* ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) */ } /** \} group_sysclk_fll_funcs */ @@ -1004,6 +1070,16 @@ typedef struct bool lfMode; /**< CLK_PLL_CONFIG register, PLL_LF_MODE bit */ cy_en_fll_pll_output_mode_t outputMode; /**< CLK_PLL_CONFIG register, BYPASS_SEL bits */ } cy_stc_pll_manual_config_t; + +#if (defined(CY_DEVICE_SECURE)) + +/** PRA structure for Cy_SysClk_PllManualConfigure function parameters */ +typedef struct +{ + uint32_t clkPath; /**< clkPath */ + cy_stc_pll_manual_config_t *praConfig; /**< config */ +} cy_stc_pra_clk_pll_manconfigure_t; +#endif /* (defined(CY_DEVICE_SECURE)) */ /** \} group_sysclk_pll_structs */ /** @@ -1052,7 +1128,7 @@ __STATIC_INLINE bool Cy_SysClk_PllIsEnabled(uint32_t clkPath) * * \param clkPath Selects which PLL to check. 1 is the first PLL; 0 is invalid. * -* \return +* \return * false = not locked \n * true = locked * @@ -1077,7 +1153,7 @@ __STATIC_INLINE bool Cy_SysClk_PllLocked(uint32_t clkPath) * * \param clkPath Selects which PLL to check. 1 is the first PLL; 0 is invalid. * -* \return +* \return * false = did not lose lock \n * true = lost lock * @@ -1087,12 +1163,18 @@ __STATIC_INLINE bool Cy_SysClk_PllLocked(uint32_t clkPath) *******************************************************************************/ __STATIC_INLINE bool Cy_SysClk_PllLostLock(uint32_t clkPath) { +#if ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) + (void) clkPath; + return false; + +#else clkPath--; /* to correctly access PLL config and status registers structures */ CY_ASSERT_L1(clkPath < CY_SRSS_NUM_PLL); bool retVal = _FLD2BOOL(SRSS_CLK_PLL_STATUS_UNLOCK_OCCURRED, SRSS_CLK_PLL_STATUS[clkPath]); /* write a 1 to clear the unlock occurred bit */ SRSS_CLK_PLL_STATUS[clkPath] = SRSS_CLK_PLL_STATUS_UNLOCK_OCCURRED_Msk; return (retVal); +#endif /* ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) */ } @@ -1107,9 +1189,14 @@ __STATIC_INLINE bool Cy_SysClk_PllLostLock(uint32_t clkPath) * \return Error / status code: \n * CY_SYSCLK_SUCCESS - PLL successfully disabled \n * CY_SYSCLK_BAD_PARAM - invalid clock path number +* CY_SYSCLK_INVALID_STATE - ECO already enabled +* For the PSoC 64 devices there are possible situations when function returns +* the PRA error status code. This is because for PSoC 64 devices the function +* uses the PRA driver to change the protected registers. Refer to +* \ref cy_en_pra_status_t for more details. * -* \note -* Call \ref SystemCoreClockUpdate after this function calling +* \note +* Call \ref SystemCoreClockUpdate after this function calling * if it affects the CLK_HF0 frequency. * * \note @@ -1130,6 +1217,9 @@ __STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_PllDisable(uint32_t clkPath) clkPath--; /* to correctly access PLL config and status registers structures */ if (clkPath < CY_SRSS_NUM_PLL) { +#if ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) + retVal = (cy_en_sysclk_status_t)CY_PRA_FUNCTION_CALL_RETURN_PARAM(CY_PRA_MSG_TYPE_FUNC_POLICY, CY_PRA_CLK_FUNC_PLL_DISABLE, (clkPath + 1U)); +#else /* First bypass PLL */ CY_REG32_CLR_SET(SRSS_CLK_PLL_CONFIG[clkPath], SRSS_CLK_PLL_CONFIG_BYPASS_SEL, CY_SYSCLK_FLLPLL_OUTPUT_INPUT); /* Wait at least 6 PLL clock cycles */ @@ -1137,6 +1227,7 @@ __STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_PllDisable(uint32_t clkPath) /* And now disable the PLL itself */ SRSS_CLK_PLL_CONFIG[clkPath] &= ~SRSS_CLK_PLL_CONFIG_ENABLE_Msk; retVal = CY_SYSCLK_SUCCESS; +#endif /* ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE)))*/ } return (retVal); } @@ -1170,7 +1261,12 @@ __STATIC_INLINE void Cy_SysClk_IloHibernateOn(bool on); *******************************************************************************/ __STATIC_INLINE void Cy_SysClk_IloEnable(void) { +#if ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) + CY_PRA_FUNCTION_CALL_VOID_PARAM(CY_PRA_MSG_TYPE_FUNC_POLICY, CY_PRA_CLK_FUNC_ILO_ENABLE, 1UL); + +#else SRSS_CLK_ILO_CONFIG |= SRSS_CLK_ILO_CONFIG_ENABLE_Msk; +#endif /* ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) */ } @@ -1201,6 +1297,11 @@ __STATIC_INLINE bool Cy_SysClk_IloIsEnabled(void) * \return Error / status code: \n * CY_SYSCLK_SUCCESS - ILO successfully disabled \n * CY_SYSCLK_INVALID_STATE - Cannot disable the ILO if the WDT is enabled. +* CY_SYSCLK_INVALID_STATE - ECO already enabled +* For the PSoC 64 devices there are possible situations when function returns +* the PRA error status code. This is because for PSoC 64 devices the function +* uses the PRA driver to change the protected registers. Refer to +* \ref cy_en_pra_status_t for more details. * * \note The watchdog timer (WDT) must be unlocked before calling this function. * Do not call this function if the WDT is enabled, because the WDT is clocked by @@ -1212,6 +1313,10 @@ __STATIC_INLINE bool Cy_SysClk_IloIsEnabled(void) *******************************************************************************/ __STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_IloDisable(void) { +#if ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) + return (cy_en_sysclk_status_t)CY_PRA_FUNCTION_CALL_RETURN_PARAM(CY_PRA_MSG_TYPE_FUNC_POLICY, CY_PRA_CLK_FUNC_ILO_DISABLE, 0UL); + +#else cy_en_sysclk_status_t retVal = CY_SYSCLK_INVALID_STATE; if (!_FLD2BOOL(SRSS_WDT_CTL_WDT_EN, SRSS_WDT_CTL)) /* if disabled */ { @@ -1219,6 +1324,7 @@ __STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_IloDisable(void) retVal = CY_SYSCLK_SUCCESS; } return (retVal); +#endif /* ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) */ } @@ -1230,7 +1336,7 @@ __STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_IloDisable(void) * brown-out detect (BOD) event. * * \param on -* true = ILO stays on during hibernate or across XRES/BOD. \n +* true = ILO stays on during hibernate or across XRES/BOD. \n * false = ILO turns off for hibernate or XRES/BOD. * * \note Writes to the register/bit are ignored if the watchdog (WDT) is locked. @@ -1241,7 +1347,11 @@ __STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_IloDisable(void) *******************************************************************************/ __STATIC_INLINE void Cy_SysClk_IloHibernateOn(bool on) { +#if ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) + CY_PRA_FUNCTION_CALL_VOID_PARAM(CY_PRA_MSG_TYPE_FUNC_POLICY, CY_PRA_CLK_FUNC_ILO_HIBERNATE_ON, on); +#else CY_REG32_CLR_SET(SRSS_CLK_ILO_CONFIG, SRSS_CLK_ILO_CONFIG_ILO_BACKUP, ((on) ? 1UL : 0UL)); +#endif /* ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) */ } /** \} group_sysclk_ilo_funcs */ @@ -1263,9 +1373,9 @@ __STATIC_INLINE uint32_t Cy_SysClk_PiloGetTrim(void); * Function Name: Cy_SysClk_PiloEnable ****************************************************************************//** * -* Enables the PILO. +* Enables the PILO. * -* \note This function blocks for 1 millisecond between enabling the PILO and +* \note This function blocks for 1 millisecond between enabling the PILO and * releasing the PILO reset. * * \funcusage @@ -1274,11 +1384,15 @@ __STATIC_INLINE uint32_t Cy_SysClk_PiloGetTrim(void); *******************************************************************************/ __STATIC_INLINE void Cy_SysClk_PiloEnable(void) { +#if ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) + CY_PRA_FUNCTION_CALL_VOID_PARAM(CY_PRA_MSG_TYPE_FUNC_POLICY, CY_PRA_CLK_FUNC_PILO_ENABLE, 1UL); +#else SRSS_CLK_PILO_CONFIG |= SRSS_CLK_PILO_CONFIG_PILO_EN_Msk; /* 1 = enable */ Cy_SysLib_Delay(1U/*msec*/); /* release the reset and enable clock output */ SRSS_CLK_PILO_CONFIG |= SRSS_CLK_PILO_CONFIG_PILO_RESET_N_Msk | SRSS_CLK_PILO_CONFIG_PILO_CLK_EN_Msk; +#endif /* ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) */ } @@ -1312,11 +1426,15 @@ __STATIC_INLINE bool Cy_SysClk_PiloIsEnabled(void) *******************************************************************************/ __STATIC_INLINE void Cy_SysClk_PiloDisable(void) { +#if ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) + CY_PRA_FUNCTION_CALL_VOID_PARAM(CY_PRA_MSG_TYPE_FUNC_POLICY, CY_PRA_CLK_FUNC_PILO_DISABLE, 0UL); +#else /* Clear PILO_EN, PILO_RESET_N, and PILO_CLK_EN bitfields. This disables the PILO and holds the PILO in a reset state. */ SRSS_CLK_PILO_CONFIG &= (uint32_t)~(SRSS_CLK_PILO_CONFIG_PILO_EN_Msk | SRSS_CLK_PILO_CONFIG_PILO_RESET_N_Msk | SRSS_CLK_PILO_CONFIG_PILO_CLK_EN_Msk); +#endif /* ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) */ } @@ -1333,7 +1451,11 @@ __STATIC_INLINE void Cy_SysClk_PiloDisable(void) *******************************************************************************/ __STATIC_INLINE void Cy_SysClk_PiloSetTrim(uint32_t trimVal) { +#if ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) + (void) trimVal; +#else CY_REG32_CLR_SET(SRSS_CLK_PILO_CONFIG, SRSS_CLK_PILO_CONFIG_PILO_FFREQ, trimVal); +#endif /* ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) */ } @@ -1368,7 +1490,7 @@ __STATIC_INLINE uint32_t Cy_SysClk_AltHfGetFrequency(void); * Function Name: Cy_SysClk_AltHfGetFrequency ****************************************************************************//** * -* Reports the frequency of the Alternative High-Frequency Clock +* Reports the frequency of the Alternative High-Frequency Clock * * \funcusage * \snippet bleclk/snippet/main.c BLE ECO clock API: Cy_BLE_EcoConfigure() @@ -1487,7 +1609,11 @@ uint32_t Cy_SysClk_ClkMeasurementCountersGetFreq(bool measuredClock, uint32_t re *******************************************************************************/ __STATIC_INLINE bool Cy_SysClk_ClkMeasurementCountersDone(void) { +#if ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) + return false; +#else return (_FLD2BOOL(SRSS_CLK_CAL_CNT1_CAL_COUNTER_DONE, SRSS_CLK_CAL_CNT1)); +#endif /* ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) */ } /** \} group_sysclk_calclk_funcs */ @@ -1590,6 +1716,11 @@ __STATIC_INLINE void Cy_SysClk_WcoBypass(cy_en_wco_bypass_modes_t bypass); * \return Error / status code: \n * CY_SYSCLK_SUCCESS - WCO successfully enabled \n * CY_SYSCLK_TIMEOUT - Timeout waiting for WCO to stabilize +* CY_SYSCLK_INVALID_STATE - ECO already enabled +* For the PSoC 64 devices there are possible situations when function returns +* the PRA error status code. This is because for PSoC 64 devices the function +* uses the PRA driver to change the protected registers. Refer to +* \ref cy_en_pra_status_t for more details. * * \funcusage * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_WcoEnable @@ -1597,6 +1728,9 @@ __STATIC_INLINE void Cy_SysClk_WcoBypass(cy_en_wco_bypass_modes_t bypass); *******************************************************************************/ __STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_WcoEnable(uint32_t timeoutus) { +#if ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) + return (cy_en_sysclk_status_t)CY_PRA_FUNCTION_CALL_RETURN_PARAM(CY_PRA_MSG_TYPE_FUNC_POLICY, CY_PRA_CLK_FUNC_WCO_ENABLE, timeoutus); +#else cy_en_sysclk_status_t retVal = CY_SYSCLK_TIMEOUT; /* first set the WCO enable bit */ @@ -1614,6 +1748,7 @@ __STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_WcoEnable(uint32_t timeoutus) } return (retVal); +#endif /* ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) */ } @@ -1623,7 +1758,7 @@ __STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_WcoEnable(uint32_t timeoutus) * * Reports the status of the WCO_OK bit. * -* \return +* \return * true = okay \n * false = not okay * @@ -1649,7 +1784,11 @@ __STATIC_INLINE bool Cy_SysClk_WcoOkay(void) *******************************************************************************/ __STATIC_INLINE void Cy_SysClk_WcoDisable(void) { +#if ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) + CY_PRA_FUNCTION_CALL_VOID_PARAM(CY_PRA_MSG_TYPE_FUNC_POLICY, CY_PRA_CLK_FUNC_WCO_DISABLE, 0UL); +#else BACKUP_CTL &= (uint32_t)~BACKUP_CTL_WCO_EN_Msk; +#endif /* ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) */ } @@ -1668,7 +1807,11 @@ __STATIC_INLINE void Cy_SysClk_WcoDisable(void) *******************************************************************************/ __STATIC_INLINE void Cy_SysClk_WcoBypass(cy_en_wco_bypass_modes_t bypass) { +#if ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) + CY_PRA_FUNCTION_CALL_VOID_PARAM(CY_PRA_MSG_TYPE_FUNC_POLICY, CY_PRA_CLK_FUNC_WCO_BYPASS, bypass); +#else CY_REG32_CLR_SET(BACKUP_CTL, BACKUP_CTL_WCO_BYPASS, bypass); +#endif /* ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) */ } /** \} group_sysclk_wco_funcs */ @@ -1701,7 +1844,11 @@ __STATIC_INLINE void Cy_SysClk_MfoEnable(bool deepSleepEnable) { if (CY_SRSS_MFO_PRESENT) { + #if CY_CPU_CORTEX_M4 && defined(CY_DEVICE_SECURE) + CY_PRA_REG32_SET(CY_PRA_INDX_SRSS_CLK_MFO_CONFIG, (SRSS_CLK_MFO_CONFIG_ENABLE_Msk | (deepSleepEnable ? SRSS_CLK_MFO_CONFIG_DPSLP_ENABLE_Msk : 0UL))); + #else SRSS_CLK_MFO_CONFIG = SRSS_CLK_MFO_CONFIG_ENABLE_Msk | (deepSleepEnable ? SRSS_CLK_MFO_CONFIG_DPSLP_ENABLE_Msk : 0UL); + #endif /* CY_CPU_CORTEX_M4 && defined(CY_DEVICE_SECURE) */ } } @@ -1740,7 +1887,11 @@ __STATIC_INLINE void Cy_SysClk_MfoDisable(void) { if (CY_SRSS_MFO_PRESENT) { + #if CY_CPU_CORTEX_M4 && defined(CY_DEVICE_SECURE) + CY_PRA_REG32_SET(CY_PRA_INDX_SRSS_CLK_MFO_CONFIG, 0UL); + #else SRSS_CLK_MFO_CONFIG = 0UL; + #endif /* CY_CPU_CORTEX_M4 && defined(CY_DEVICE_SECURE) */ } } @@ -1767,7 +1918,11 @@ __STATIC_INLINE void Cy_SysClk_ClkMfEnable(void) { if (CY_SRSS_MFO_PRESENT) { + #if CY_CPU_CORTEX_M4 && defined(CY_DEVICE_SECURE) + CY_PRA_REG32_CLR_SET(CY_PRA_INDX_SRSS_CLK_MF_SELECT, SRSS_CLK_MF_SELECT_ENABLE, 1U); + #else SRSS_CLK_MF_SELECT |= SRSS_CLK_MF_SELECT_ENABLE_Msk; + #endif /* CY_CPU_CORTEX_M4 && defined(CY_DEVICE_SECURE) */ } } @@ -1806,7 +1961,11 @@ __STATIC_INLINE void Cy_SysClk_ClkMfDisable(void) { if (CY_SRSS_MFO_PRESENT) { + #if CY_CPU_CORTEX_M4 && defined(CY_DEVICE_SECURE) + CY_PRA_REG32_CLR_SET(CY_PRA_INDX_SRSS_CLK_MF_SELECT, SRSS_CLK_MF_SELECT_ENABLE, 0U); + #else SRSS_CLK_MF_SELECT &= ~SRSS_CLK_MF_SELECT_ENABLE_Msk; + #endif /* CY_CPU_CORTEX_M4 && defined(CY_DEVICE_SECURE) */ } } @@ -1836,10 +1995,14 @@ __STATIC_INLINE void Cy_SysClk_ClkMfDisable(void) __STATIC_INLINE void Cy_SysClk_ClkMfSetDivider(uint32_t divider) { if ((CY_SRSS_MFO_PRESENT) && CY_SYSCLK_IS_MF_DIVIDER_VALID(divider)) - { + { if (!Cy_SysClk_ClkMfIsEnabled()) { + #if CY_CPU_CORTEX_M4 && defined(CY_DEVICE_SECURE) + CY_PRA_REG32_CLR_SET(CY_PRA_INDX_SRSS_CLK_MF_SELECT, SRSS_CLK_MF_SELECT_MFCLK_DIV, divider - 1UL); + #else CY_REG32_CLR_SET(SRSS_CLK_MF_SELECT, SRSS_CLK_MF_SELECT_MFCLK_DIV, divider - 1UL); + #endif /* CY_CPU_CORTEX_M4 && defined(CY_DEVICE_SECURE) */ } } } @@ -1953,6 +2116,22 @@ typedef struct cy_en_csv_error_actions_t lossAction; } cy_stc_clkhf_csv_config_t; +#if (defined(CY_DEVICE_SECURE)) +/** PRA structure for Cy_SysClk_ClkHfSetSource function parameters */ +typedef struct +{ + uint32_t clkHf; /**< clkHF */ + cy_en_clkhf_in_sources_t source; /**< Source */ +} cy_stc_pra_clkhfsetsource_t; + +/** PRA structure for Cy_SysClk_ClkHfSetSource function parameters */ +typedef struct +{ + uint32_t clkHf; /**< clkHF */ + cy_en_clkhf_dividers_t divider; /**< divider */ +} cy_stc_pra_clkhfsetdivider_t; +#endif /* (defined(CY_DEVICE_SECURE)) */ + #define altHfFreq (cy_BleEcoClockFreqHz) /** \endcond */ @@ -1979,6 +2158,11 @@ __STATIC_INLINE cy_en_clkhf_dividers_t Cy_SysClk_ClkHfGetDivider(uint32_t clkHf) * \param clkHf Selects which clkHf to enable. * * \return \ref cy_en_sysclk_status_t +* CY_SYSCLK_INVALID_STATE - ECO already enabled +* For the PSoC 64 devices there are possible situations when function returns +* the PRA error status code. This is because for PSoC 64 devices the function +* uses the PRA driver to change the protected registers. Refer to +* \ref cy_en_pra_status_t for more details. * * \funcusage * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkPathSetSource @@ -1989,10 +2173,15 @@ __STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_ClkHfEnable(uint32_t clkHf) cy_en_sysclk_status_t retVal = CY_SYSCLK_BAD_PARAM; if (clkHf < CY_SRSS_NUM_HFROOT) { +#if ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) + retVal = (cy_en_sysclk_status_t)CY_PRA_FUNCTION_CALL_RETURN_PARAM(CY_PRA_MSG_TYPE_FUNC_POLICY, CY_PRA_CLK_FUNC_HF_ENABLE, clkHf); +#else SRSS_CLK_ROOT_SELECT[clkHf] |= SRSS_CLK_ROOT_SELECT_ENABLE_Msk; retVal = CY_SYSCLK_SUCCESS; +#endif /* ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) */ } return (retVal); + } @@ -2043,8 +2232,12 @@ __STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_ClkHfDisable(uint32_t clkHf) if ((0UL < clkHf) /* prevent CLK_HF0 disabling */ && (clkHf < CY_SRSS_NUM_HFROOT)) { +#if ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) + retVal = (cy_en_sysclk_status_t)CY_PRA_FUNCTION_CALL_RETURN_PARAM(CY_PRA_MSG_TYPE_FUNC_POLICY, CY_PRA_CLK_FUNC_HF_DISABLE, clkHf); +#else SRSS_CLK_ROOT_SELECT[clkHf] &= ~SRSS_CLK_ROOT_SELECT_ENABLE_Msk; retVal = CY_SYSCLK_SUCCESS; +#endif /* ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) */ } return (retVal); } @@ -2061,12 +2254,17 @@ __STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_ClkHfDisable(uint32_t clkHf) * \param source \ref cy_en_clkhf_in_sources_t * * \return \ref cy_en_sysclk_status_t +* CY_SYSCLK_INVALID_STATE - ECO already enabled +* For the PSoC 64 devices there are possible situations when function returns +* the PRA error status code. This is because for PSoC 64 devices the function +* uses the PRA driver to change the protected registers. Refer to +* \ref cy_en_pra_status_t for more details. * -* \note -* Call \ref SystemCoreClockUpdate after this function calling +* \note +* Call \ref SystemCoreClockUpdate after this function calling * if it affects the CLK_HF0 frequency. * -* \note +* \note * Call \ref Cy_SysLib_SetWaitStates before calling this function if * CLK_HF0 frequency is increasing. * @@ -2083,10 +2281,18 @@ __STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_ClkHfSetSource(uint32_t clkHf, c cy_en_sysclk_status_t retVal = CY_SYSCLK_BAD_PARAM; if ((clkHf < CY_SRSS_NUM_HFROOT) && (source <= CY_SYSCLK_CLKHF_IN_CLKPATH15)) { +#if ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) + cy_stc_pra_clkhfsetsource_t set_source; + set_source.clkHf = clkHf; + set_source.source = source; + retVal = (cy_en_sysclk_status_t)CY_PRA_FUNCTION_CALL_RETURN_PARAM(CY_PRA_MSG_TYPE_FUNC_POLICY, CY_PRA_CLK_FUNC_HF_SET_SOURCE, &set_source); +#else CY_REG32_CLR_SET(SRSS_CLK_ROOT_SELECT[clkHf], SRSS_CLK_ROOT_SELECT_ROOT_MUX, source); retVal = CY_SYSCLK_SUCCESS; +#endif /* ((CY_CPU_CORTEX_M4) && (!defined(CY_DEVICE_SECURE))) */ } return (retVal); + } @@ -2122,14 +2328,19 @@ __STATIC_INLINE cy_en_clkhf_in_sources_t Cy_SysClk_ClkHfGetSource(uint32_t clkHf * \param divider \ref cy_en_clkhf_dividers_t * * \return \ref cy_en_sysclk_status_t +* CY_SYSCLK_INVALID_STATE - ECO already enabled +* For the PSoC 64 devices there are possible situations when function returns +* the PRA error status code. This is because for PSoC 64 devices the function +* uses the PRA driver to change the protected registers. Refer to +* \ref cy_en_pra_status_t for more details. * * \note Also call \ref Cy_SysClk_ClkHfSetSource to set the clkHf source. * -* \note -* Call \ref SystemCoreClockUpdate after this function calling +* \note +* Call \ref SystemCoreClockUpdate after this function calling * if it affects the CLK_HF0 frequency. * -* \note +* \note * Call \ref Cy_SysLib_SetWaitStates before calling this function if * CLK_HF0 frequency is increasing. * @@ -2146,10 +2357,18 @@ __STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_ClkHfSetDivider(uint32_t clkHf, cy_en_sysclk_status_t retVal = CY_SYSCLK_BAD_PARAM; if ((clkHf < CY_SRSS_NUM_HFROOT) && (divider <= CY_SYSCLK_CLKHF_DIVIDE_BY_8)) { +#if ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) + cy_stc_pra_clkhfsetdivider_t set_divider; + set_divider.clkHf = clkHf; + set_divider.divider = divider; + retVal = (cy_en_sysclk_status_t)CY_PRA_FUNCTION_CALL_RETURN_PARAM(CY_PRA_MSG_TYPE_FUNC_POLICY, CY_PRA_CLK_FUNC_HF_SET_DIVIDER, &set_divider); +#else CY_REG32_CLR_SET(SRSS_CLK_ROOT_SELECT[clkHf], SRSS_CLK_ROOT_SELECT_ROOT_DIV, divider); retVal = CY_SYSCLK_SUCCESS; +#endif /* ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) */ } return (retVal); + } @@ -2219,10 +2438,10 @@ __STATIC_INLINE uint32_t Cy_SysClk_ClkFastGetFrequency(void) * \param divider divider value between 0 and 255. * Causes integer division of (divider value + 1), or division by 1 to 256. * -* \note +* \note * Call \ref SystemCoreClockUpdate after this function calling. * -* \note +* \note * Call \ref Cy_SysLib_SetWaitStates before calling this function if * CLK_FAST frequency is increasing. * @@ -2236,7 +2455,11 @@ __STATIC_INLINE uint32_t Cy_SysClk_ClkFastGetFrequency(void) *******************************************************************************/ __STATIC_INLINE void Cy_SysClk_ClkFastSetDivider(uint8_t divider) { +#if ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) + CY_PRA_FUNCTION_CALL_VOID_PARAM(CY_PRA_MSG_TYPE_FUNC_POLICY, CY_PRA_CLK_FUNC_FAST_SET_DIVIDER, divider); +#else CY_REG32_CLR_SET(CPUSS_CM4_CLOCK_CTL, CPUSS_CM4_CLOCK_CTL_FAST_INT_DIV, divider); +#endif /* ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) */ } @@ -2305,7 +2528,7 @@ __STATIC_INLINE uint32_t Cy_SysClk_ClkPeriGetFrequency(void) * \param divider divider value between 0 and 255 * Causes integer division of (divider value + 1), or division by 1 to 256. * -* \note +* \note * Call \ref SystemCoreClockUpdate after this function calling. * * \funcusage @@ -2314,7 +2537,11 @@ __STATIC_INLINE uint32_t Cy_SysClk_ClkPeriGetFrequency(void) *******************************************************************************/ __STATIC_INLINE void Cy_SysClk_ClkPeriSetDivider(uint8_t divider) { +#if ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) + CY_PRA_FUNCTION_CALL_VOID_PARAM(CY_PRA_MSG_TYPE_FUNC_POLICY, CY_PRA_CLK_FUNC_PERI_SET_DIVIDER, divider); +#else CY_REG32_CLR_SET(CPUSS_CM0_CLOCK_CTL, CPUSS_CM0_CLOCK_CTL_PERI_INT_DIV, divider); +#endif /* ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) */ } @@ -2858,7 +3085,7 @@ __STATIC_INLINE uint32_t Cy_SysClk_ClkSlowGetFrequency(void) * \param divider Divider value between 0 and 255. * Causes integer division of (divider value + 1), or division by 1 to 256. * -* \note +* \note * Call \ref SystemCoreClockUpdate after this function calling. * * \funcusage @@ -2867,7 +3094,11 @@ __STATIC_INLINE uint32_t Cy_SysClk_ClkSlowGetFrequency(void) *******************************************************************************/ __STATIC_INLINE void Cy_SysClk_ClkSlowSetDivider(uint8_t divider) { +#if ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) + CY_PRA_FUNCTION_CALL_VOID_PARAM(CY_PRA_MSG_TYPE_FUNC_POLICY, CY_PRA_CLK_FUNC_SLOW_SET_DIVIDER, divider); +#else CY_REG32_CLR_SET(CPUSS_CM0_CLOCK_CTL, CPUSS_CM0_CLOCK_CTL_SLOW_INT_DIV, divider); +#endif /* ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) */ } @@ -2935,8 +3166,12 @@ __STATIC_INLINE cy_en_clklf_in_sources_t Cy_SysClk_ClkLfGetSource(void); *******************************************************************************/ __STATIC_INLINE void Cy_SysClk_ClkLfSetSource(cy_en_clklf_in_sources_t source) { +#if ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) + CY_PRA_FUNCTION_CALL_VOID_PARAM(CY_PRA_MSG_TYPE_FUNC_POLICY, CY_PRA_CLK_FUNC_LF_SET_SOURCE, source); +#else CY_ASSERT_L3(source <= CY_SYSCLK_CLKLF_IN_PILO); CY_REG32_CLR_SET(SRSS_CLK_SELECT, SRSS_CLK_SELECT_LFCLK_SEL, source); +#endif /* ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) */ } @@ -3004,7 +3239,7 @@ __STATIC_INLINE void Cy_SysClk_ClkTimerDisable(void); ****************************************************************************//** * * Sets the source for the timer clock (clk_timer). The timer clock can be used -* as a source for SYSTICK as an alternate clock and one or more of the energy +* as a source for SYSTICK as an alternate clock and one or more of the energy * profiler counters. * * \param source \ref cy_en_clktimer_in_sources_t @@ -3015,9 +3250,13 @@ __STATIC_INLINE void Cy_SysClk_ClkTimerDisable(void); *******************************************************************************/ __STATIC_INLINE void Cy_SysClk_ClkTimerSetSource(cy_en_clktimer_in_sources_t source) { +#if ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) + CY_PRA_FUNCTION_CALL_VOID_PARAM(CY_PRA_MSG_TYPE_FUNC_POLICY, CY_PRA_CLK_FUNC_TIMER_SET_SOURCE, source); +#else CY_ASSERT_L3(source <= CY_SYSCLK_CLKTIMER_IN_HF0_DIV8); /* set both fields TIMER_SEL and TIMER_HF0_DIV with the same input value */ CY_REG32_CLR_SET(SRSS_CLK_TIMER_CTL, CY_SRSS_CLK_TIMER_CTL_TIMER, source); +#endif /* ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) */ } @@ -3058,7 +3297,11 @@ __STATIC_INLINE cy_en_clktimer_in_sources_t Cy_SysClk_ClkTimerGetSource(void) *******************************************************************************/ __STATIC_INLINE void Cy_SysClk_ClkTimerSetDivider(uint8_t divider) { +#if ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) + CY_PRA_FUNCTION_CALL_VOID_PARAM(CY_PRA_MSG_TYPE_FUNC_POLICY, CY_PRA_CLK_FUNC_TIMER_SET_DIVIDER, divider); +#else CY_REG32_CLR_SET(SRSS_CLK_TIMER_CTL, SRSS_CLK_TIMER_CTL_TIMER_DIV, divider); +#endif /* ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) */ } @@ -3093,7 +3336,11 @@ __STATIC_INLINE uint8_t Cy_SysClk_ClkTimerGetDivider(void) *******************************************************************************/ __STATIC_INLINE void Cy_SysClk_ClkTimerEnable(void) { +#if ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) + CY_PRA_FUNCTION_CALL_VOID_PARAM(CY_PRA_MSG_TYPE_FUNC_POLICY, CY_PRA_CLK_FUNC_TIMER_ENABLE, 1UL); +#else SRSS_CLK_TIMER_CTL |= SRSS_CLK_TIMER_CTL_ENABLE_Msk; +#endif /* ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) */ } @@ -3127,7 +3374,11 @@ __STATIC_INLINE bool Cy_SysClk_ClkTimerIsEnabled(void) *******************************************************************************/ __STATIC_INLINE void Cy_SysClk_ClkTimerDisable(void) { +#if ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) + CY_PRA_FUNCTION_CALL_VOID_PARAM(CY_PRA_MSG_TYPE_FUNC_POLICY, CY_PRA_CLK_FUNC_TIMER_DISABLE, 0UL); +#else SRSS_CLK_TIMER_CTL &= ~SRSS_CLK_TIMER_CTL_ENABLE_Msk; +#endif /* ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) */ } /** \} group_sysclk_clk_timer_funcs */ @@ -3220,8 +3471,12 @@ __STATIC_INLINE uint32_t Cy_SysClk_ClkPumpGetFrequency(void); *******************************************************************************/ __STATIC_INLINE void Cy_SysClk_ClkPumpSetSource(cy_en_clkpump_in_sources_t source) { +#if ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) + CY_PRA_FUNCTION_CALL_VOID_PARAM(CY_PRA_MSG_TYPE_FUNC_POLICY, CY_PRA_CLK_FUNC_PUMP_SET_SOURCE, source); +#else CY_ASSERT_L3(source <= CY_SYSCLK_PUMP_IN_CLKPATH15); CY_REG32_CLR_SET(SRSS_CLK_SELECT, SRSS_CLK_SELECT_PUMP_SEL, source); +#endif /* ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) */ } @@ -3260,8 +3515,12 @@ __STATIC_INLINE cy_en_clkpump_in_sources_t Cy_SysClk_ClkPumpGetSource(void) *******************************************************************************/ __STATIC_INLINE void Cy_SysClk_ClkPumpSetDivider(cy_en_clkpump_divide_t divider) { +#if ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) + CY_PRA_FUNCTION_CALL_VOID_PARAM(CY_PRA_MSG_TYPE_FUNC_POLICY, CY_PRA_CLK_FUNC_PUMP_SET_DIVIDER, divider); +#else CY_ASSERT_L3(CY_SYSCLK_FLL_IS_DIVIDER_VALID(divider)); CY_REG32_CLR_SET(SRSS_CLK_SELECT, SRSS_CLK_SELECT_PUMP_DIV, divider); +#endif /* ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) */ } @@ -3296,7 +3555,11 @@ __STATIC_INLINE cy_en_clkpump_divide_t Cy_SysClk_ClkPumpGetDivider(void) *******************************************************************************/ __STATIC_INLINE void Cy_SysClk_ClkPumpEnable(void) { +#if ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) + CY_PRA_FUNCTION_CALL_VOID_PARAM(CY_PRA_MSG_TYPE_FUNC_POLICY, CY_PRA_CLK_FUNC_PUMP_ENABLE, 1UL); +#else SRSS_CLK_SELECT |= SRSS_CLK_SELECT_PUMP_ENABLE_Msk; +#endif /* ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) */ } @@ -3330,7 +3593,11 @@ __STATIC_INLINE bool Cy_SysClk_ClkPumpIsEnabled(void) *******************************************************************************/ __STATIC_INLINE void Cy_SysClk_ClkPumpDisable(void) { +#if ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) + CY_PRA_FUNCTION_CALL_VOID_PARAM(CY_PRA_MSG_TYPE_FUNC_POLICY, CY_PRA_CLK_FUNC_PUMP_DISABLE, 0UL); +#else SRSS_CLK_SELECT &= ~SRSS_CLK_SELECT_PUMP_ENABLE_Msk; +#endif /* ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) */ } @@ -3401,8 +3668,12 @@ __STATIC_INLINE cy_en_clkbak_in_sources_t Cy_SysClk_ClkBakGetSource(void); *******************************************************************************/ __STATIC_INLINE void Cy_SysClk_ClkBakSetSource(cy_en_clkbak_in_sources_t source) { +#if ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) + CY_PRA_FUNCTION_CALL_VOID_PARAM(CY_PRA_MSG_TYPE_FUNC_POLICY, CY_PRA_CLK_FUNC_BAK_SET_SOURCE, source); +#else CY_ASSERT_L3(source <= CY_SYSCLK_BAK_IN_CLKLF); CY_REG32_CLR_SET(BACKUP_CTL, BACKUP_CTL_CLK_SEL, source); +#endif /* ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) */ } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_sysint.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_sysint.h index ba6977eae7..d7ad781ee5 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_sysint.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_sysint.h @@ -1,13 +1,13 @@ /***************************************************************************//** * \file cy_sysint.h -* \version 1.30 +* \version 1.30.1 * * \brief * Provides an API declaration of the SysInt driver * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -33,9 +33,9 @@ * be used to configure and connect device peripheral interrupts to one or more * cores. * -* The functions and other declarations used in this driver are in cy_sysint.h. -* You can include cy_pdl.h (ModusToolbox only) to get access to all functions -* and declarations in the PDL. +* The functions and other declarations used in this driver are in cy_sysint.h. +* You can include cy_pdl.h to get access to all functions +* and declarations in the PDL. * * \section group_sysint_vector_table Vector Table * The vector table defines the entry addresses of the processor exceptions and @@ -47,7 +47,7 @@ * * The default interrupt handler functions are defined as weak functions to a dummy handler * in the startup file. The naming convention is \_IRQHandler. -* Defining these in the user application allows the linker to place them in +* Defining these in the user application allows the linker to place them in * the vector table in flash. For example: * \code * void ioss_interrupts_gpio_0_IRQHandler(void) @@ -57,7 +57,7 @@ * \endcode * And can be used like this: * \snippet sysint/snippet/main.c snippet_Cy_SysInt_flashVT -* Using this method avoids the need for a RAM vector table. However in this scenario, +* Using this method avoids the need for a RAM vector table. However in this scenario, * interrupt handler re-location at run-time is not possible, unless the vector table is * relocated to RAM. @@ -65,8 +65,8 @@ * * \subsection group_sysint_initialization Initialization * -* Interrupt numbers are defined in a device-specific header file, such as -* cy8c68237bz_ble.h, and are consistent with interrupt handlers defined in the +* Interrupt numbers are defined in a device-specific header file, such as +* cy8c68237bz_ble.h, and are consistent with interrupt handlers defined in the * vector table. * * To configure an interrupt, call Cy_SysInt_Init(). Populate @@ -77,33 +77,33 @@ * must specify the device interrupt source (cm0pSrc) that feeds into the CM0+ NVIC * mux (intrSrc). * -* For CM4 core, system interrupt source 'n' is connected to the +* For CM4 core, system interrupt source 'n' is connected to the * corresponding IRQn. Deep-sleep capable interrupts are allocated to Deep Sleep -* capable IRQn channels. +* capable IRQn channels. * -* For CM0+ core, deep Sleep wakeup-capability is determined by the CPUSS_CM0_DPSLP_IRQ_NR -* parameter, where the first N number of muxes (NvicMux0 ... NvicMuxN-1) have the -* capability to trigger Deep Sleep interrupts. A Deep Sleep capable interrupt source -* must be connected to one of these muxes to be able to trigger in Deep Sleep. +* For CM0+ core, deep Sleep wakeup-capability is determined by the CPUSS_CM0_DPSLP_IRQ_NR +* parameter, where the first N number of muxes (NvicMux0 ... NvicMuxN-1) have the +* capability to trigger Deep Sleep interrupts. A Deep Sleep capable interrupt source +* must be connected to one of these muxes to be able to trigger in Deep Sleep. * Refer to the IRQn_Type definition in the device header. * * 1. For CPUSS_ver1 the CM0+ core supports up to 32 interrupt channels (IRQn 0-31). To allow all device * interrupts to be routable to the NVIC of this core, there is a 240:1 multiplexer -* at each of the 32 NVIC channels. +* at each of the 32 NVIC channels. * * 2. For CPUSS_ver2 the CM0+ core supports up to 8 hardware interrupt channels (IRQn 0-7) and software-only * interrupt channels (IRQn 8-15). The device has up to 1023 interrupts that can be connected to any of the -* hardware interrupt channels. In this structure, multiple interrupt sources can be connected +* hardware interrupt channels. In this structure, multiple interrupt sources can be connected * simultaneously to one NVIC channel. The application must then query the interrupt source on the * channel and service the active interrupt(s). The priority of these interrupts is determined by the * interrupt number as defined in the cy_en_intr_t enum, where the lower number denotes higher priority * over the higher number. * * \subsection group_sysint_enable Enable -* +* * After initializing an interrupt, use the CMSIS Core * NVIC_EnableIRQ() function -* to enable it. Given an initialization structure named config, +* to enable it. Given an initialization structure named config, * the function should be called as follows: * \code * NVIC_EnableIRQ(config.intrSrc) @@ -170,6 +170,11 @@ *
VersionChangesReason for Change
2.10Updated SysClk functions for PSoC 64 devices. Now the SysClk functions can return +* PRA driver status value.The SysClk driver uses the PRA driver to change the protected registers. +* A SysClk driver function that calls a PRA driver function will return the PRA +* error status code if the called PRA function returns an error. In these cases, +* refer to PRA return statuses. Refer to functions description for details.
Updated the code of \ref Cy_SysClk_ClkPathGetFrequency function.Make the code more error-resistant to user errors for some corner cases.
Minor documentation updates.Documentation enhancement.
2.0Updated the ECO trimming values calculation algorithm in the \ref Cy_SysClk_EcoConfigure implementation. \n * This change may invalidate the already used crystals, in cases: \n @@ -116,7 +146,7 @@ *
1.60Added the following functions: \ref Cy_SysClk_ExtClkGetFrequency, \ref Cy_SysClk_EcoGetFrequency,\n -* \ref Cy_SysClk_ClkPathMuxGetFrequency, \ref Cy_SysClk_ClkPathGetFrequency, \ref Cy_SysClk_IloIsEnabled.\n +* \ref Cy_SysClk_ClkPathMuxGetFrequency, \ref Cy_SysClk_ClkPathGetFrequency, \ref Cy_SysClk_IloIsEnabled.\n * \ref Cy_SysClk_PiloIsEnabled, \ref Cy_SysClk_AltHfGetFrequency, \ref Cy_SysClk_ClkHfIsEnabled,\n * \ref Cy_SysClk_ClkTimerIsEnabled, \ref Cy_SysClk_ClkTimerGetFrequency, \ref Cy_SysClk_ClkPumpIsEnabled and\n * \ref Cy_SysClk_ClkPumpGetFrequency.
1.40Updated the following functions implementation: \ref Cy_SysClk_PllConfigure and \ref Cy_SysClk_PllEnable. +* * Fixed the \ref Cy_SysClk_PllConfigure API function behaviour when it is called with a bypass mode, \n * Fixed the \ref Cy_SysClk_PllEnable API function behaviour when it is called with a zero timeout. *
1.20Flattened the organization of the driver source code into the single +* Flattened the organization of the driver source code into the single * source directory and the single include directory. * Driver library directory-structure simplification.
Added register access layer. Use register access macros instead * of direct register access using dereferenced pointers.Makes register access device-independent, so that the PDL does +* Makes register access device-independent, so that the PDL does * not need to be recompiled for each supported part number.
1.11Updated the following functions. Now they use a semaphore when +* Updated the following functions. Now they use a semaphore when * try to read the status or configure the SysClk measurement counters: * * Cy_SysClk_StartClkMeasurementCounters() * * Cy_SysClk_ClkMeasurementCountersGetFreq() @@ -210,7 +240,7 @@ * Now Cy_SysClk_ClkMeasurementCountersGetFreq() returns zero value, * if during measurement device was in the Deep Sleep or partially * blocking flash operation occurred Added arbiter mechanism for correct usage of the SysClk measurement +* Added arbiter mechanism for correct usage of the SysClk measurement * counters
* * +* +* +* +* +* * * * @@ -189,12 +194,12 @@ * - \ref Cy_SysInt_SetInterruptSource * - \ref Cy_SysInt_SetNmiSource * - \ref Cy_SysInt_GetNmiSource -* +* * Added new API functions: * - \ref Cy_SysInt_DisconnectInterruptSource * - \ref Cy_SysInt_GetNvicConnection * - \ref Cy_SysInt_GetInterruptActive -* +* * Deprecated following functions: * - Cy_SysInt_SetIntSource * - Cy_SysInt_GetIntSource @@ -206,7 +211,7 @@ * * -* * * @@ -268,7 +273,7 @@ extern cy_israddress __ramVectors[]; /**< Relocated vector table in SRAM */ /** Driver major version */ #define CY_SYSINT_DRV_VERSION_MAJOR 1 - + /** Driver minor version */ #define CY_SYSINT_DRV_VERSION_MINOR 30 @@ -290,7 +295,7 @@ extern cy_israddress __ramVectors[]; /**< Relocated vector table in SRAM */ /** * SysInt Driver error codes */ -typedef enum +typedef enum { CY_SYSINT_SUCCESS = 0x0UL, /**< Returned successful */ CY_SYSINT_BAD_PARAM = CY_SYSINT_ID | CY_PDL_STATUS_ERROR | 0x1UL, /**< Bad parameter was passed */ @@ -419,7 +424,7 @@ cy_israddress Cy_SysInt_GetVector(IRQn_Type IRQn); * \param nmiNum * NMI source number. * CPUSS_ver2 allows up to 4 sources to trigger the core NMI. -* CPUSS_ver1 allows only one source to trigger the core NMI and +* CPUSS_ver1 allows only one source to trigger the core NMI and * the specified NMI number is ignored. * * \param intrSrc @@ -444,12 +449,12 @@ __STATIC_INLINE void Cy_SysInt_SetNmiSource(cy_en_sysint_nmi_t nmiNum, cy_en_int #if (CY_CPU_CORTEX_M0P) CY_ASSERT_L1(CY_SYSINT_IS_PC_0); #endif - + if (CY_CPUSS_V1) { nmiNum = CY_SYSINT_NMI1; /* For CPUSS_ver1 the NMI number is 1 */ } - + #if (CY_CPU_CORTEX_M0P) CPUSS_CM0_NMI_CTL((uint32_t)nmiNum - 1UL) = (uint32_t)devIntrSrc; #else @@ -485,7 +490,7 @@ __STATIC_INLINE cy_en_intr_t Cy_SysInt_GetNmiSource(cy_en_sysint_nmi_t nmiNum) #endif { CY_ASSERT_L3(CY_SYSINT_IS_NMI_NUM_VALID(nmiNum)); - + if (CY_CPUSS_V1) { nmiNum = CY_SYSINT_NMI1; /* For CPUSS_ver1 the NMI number is 1 */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_syslib.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_syslib.h index c865e7e436..c61aad00e1 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_syslib.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_syslib.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_syslib.h -* \version 2.50.3 +* \version 2.60 * * Provides an API declaration of the SysLib driver. * @@ -29,7 +29,7 @@ * to handle the timing, logical checking or register. * * The functions and other declarations used in this driver are in cy_syslib.h. -* You can include cy_pdl.h (ModusToolbox only) to get access to all functions +* You can include cy_pdl.h to get access to all functions * and declarations in the PDL. * * The SysLib driver contains a set of different system functions. These functions @@ -153,6 +153,17 @@ *
VersionChangesReason for Change
1.30.1Minor documentation updates.Documentation enhancement.
1.30The Cy_SysInt_SetNmiSource is updated with Protection Context check for CM0+.User experience enhancement.
Added register access layer. Use register access macros instead * of direct register access using dereferenced pointers.Makes register access device-independent, so that the PDL does +* Makes register access device-independent, so that the PDL does * not need to be recompiled for each supported part number.
* * +* +* +* +* +* +* +* +* * * @@ -482,7 +493,7 @@ typedef enum #define CY_SYSLIB_DRV_VERSION_MAJOR 2 /** The driver minor version */ -#define CY_SYSLIB_DRV_VERSION_MINOR 50 +#define CY_SYSLIB_DRV_VERSION_MINOR 60 typedef void (* cy_israddress)(void); /**< Type of ISR callbacks */ #if defined (__ICCARM__) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_syspm.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_syspm.h index 6d071770b2..01b483f9a8 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_syspm.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_syspm.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_syspm.h -* \version 5.0 +* \version 5.10 * * Provides the function definitions for the power management API. * @@ -27,14 +27,14 @@ * \addtogroup group_syspm * \{ * -* Use the System Power Management (SysPm) driver to change power modes and -* reduce system power consumption in power sensitive designs. +* Use the System Power Management (SysPm) driver to change power modes and +* reduce system power consumption in power sensitive designs. * -* The functions and other declarations used in this driver are in cy_syspm.h. -* You can include cy_pdl.h (ModusToolbox only) to get access to all functions -* and declarations in the PDL. +* The functions and other declarations used in this driver are in cy_syspm.h. +* You can include cy_pdl.h to get access to all functions +* and declarations in the PDL. * -* For multi-CPU devices, this library allows you to individually enter low power +* For multi-CPU devices, this library allows you to individually enter low power * modes for each CPU. * * This document contains the following topics: @@ -73,52 +73,52 @@ * are intended to minimize average power consumption in an application. * System power modes: * * Low Power - All peripheral and CPU power modes -* are available to be used at maximum device frequency and current +* are available to be used at maximum device frequency and current * consumption. -* * Ultra Low Power - All peripheral and -* CPU power modes are available, but the frequency and current consumption +* * Ultra Low Power - All peripheral and +* CPU power modes are available, but the frequency and current consumption * are limited to a device specific number. -* * Deep Sleep - Device and I/O states is retained. Low-frequency -* peripherals are available. Both CPUs are in CPU Deep Sleep power mode. -* * Hibernate - The device and I/O states are frozen and the device +* * Deep Sleep - Device and I/O states is retained. Low-frequency +* peripherals are available. Both CPUs are in CPU Deep Sleep power mode. +* * Hibernate - The device and I/O states are frozen and the device * resets on wakeup. * -* The CPU Active, Sleep and Deep Sleep power modes are -* Arm-defined power modes supported by the Arm CPU instruction -* set architecture (ISA). -* +* The CPU Active, Sleep and Deep Sleep power modes are +* Arm-defined power modes supported by the Arm CPU instruction +* set architecture (ISA). +* * \subsection group_syspm_system_power_modes System Power Modes -* * LP - In this mode, code is executed and all logic and -* memories are powered. Firmware may disable/reduce clocks for specific +* * LP - In this mode, code is executed and all logic and +* memories are powered. Firmware may disable/reduce clocks for specific * peripherals and power down specific analog power domains. * -* * ULP - This power mode is like LP mode, but +* * ULP - This power mode is like LP mode, but * with clock restrictions and limited/slower peripherals to achieve lower -* current consumption. Refer to \ref group_syspm_switching_into_ulp in +* current consumption. Refer to \ref group_syspm_switching_into_ulp in * Configuration considerations. * -* * Deep Sleep - Is a lower power mode where high-frequency clocks are -* disabled. Refer to \ref group_syspm_switching_into_deepsleep in -* Configuration considerations. Deep-sleep-capable peripherals are available. -* A normal wakeup from Deep Sleep returns to either system LP or ULP mode, -* depending on the previous state and programmed behavior for the configured -* wakeup interrupt. Likewise, a debug wakes up from system Deep Sleep and -* woken CPU returns to CPU Sleep. Refer -* to \ref group_syspm_wakingup_from_sleep_deepsleep in Configuration +* * Deep Sleep - Is a lower power mode where high-frequency clocks are +* disabled. Refer to \ref group_syspm_switching_into_deepsleep in +* Configuration considerations. Deep-sleep-capable peripherals are available. +* A normal wakeup from Deep Sleep returns to either system LP or ULP mode, +* depending on the previous state and programmed behavior for the configured +* wakeup interrupt. Likewise, a debug wakes up from system Deep Sleep and +* woken CPU returns to CPU Sleep. Refer +* to \ref group_syspm_wakingup_from_sleep_deepsleep in Configuration * considerations. * -* * Hibernate - Is the lowest power mode that is entered from -* firmware. Refer to \ref group_syspm_switching_into_hibernate in -* Configuration considerations. On wakeup the CPU(s) and all peripherals -* go through a full reset. The I/O's state is frozen so that the -* output driver state is held in system Hibernate. Note that in this mode, +* * Hibernate - Is the lowest power mode that is entered from +* firmware. Refer to \ref group_syspm_switching_into_hibernate in +* Configuration considerations. On wakeup the CPU(s) and all peripherals +* go through a full reset. The I/O's state is frozen so that the +* output driver state is held in system Hibernate. Note that in this mode, * the CPU(s) and all peripherals lose their states, so the system and firmware -* reboot on a wakeup event. Backup memory (if present) can be used to store -* limited system state for use on the next reboot. Refer to +* reboot on a wakeup event. Backup memory (if present) can be used to store +* limited system state for use on the next reboot. Refer to * \ref group_syspm_wakingup_from_hibernate in Configuration considerations. * * \subsubsection group_syspm_switching_into_lp Switching the System into Low Power -* To set system LP mode you need to set LP voltage for the active core +* To set system LP mode you need to set LP voltage for the active core * regulator: * * If active core regulator is the LDO, call: * \code{.c} @@ -129,109 +129,109 @@ * Cy_SysPm_BuckSetVoltage1(CY_SYSPM_BUCK_OUT1_VOLTAGE_LP) * \endcode * -* After switching into system LP mode, the operating frequency and current +* After switching into system LP mode, the operating frequency and current * consumption may now be increased up to \ref group_syspm_lp_limitations. -* The wait states for flash may be changed to increase device performance by -* calling SysLib function Cy_SysLib_SetWaitStates(true, hfClkFreqMz), where +* The wait states for flash may be changed to increase device performance by +* calling SysLib function Cy_SysLib_SetWaitStates(true, hfClkFreqMz), where * hfClkFreqMz is the frequency of HfClk0 in MHz. * * \subsubsection group_syspm_lp_limitations LP Limitations * When the system is in LP mode, the core regulator voltage is set to * 1.1 V (nominal) and the following limitations must be met: * -* - The maximum operating frequency for all Clk_HF paths must not exceed -* 150 MHz*, and peripheral and slow clock must +* - The maximum operating frequency for all Clk_HF paths must not exceed +* 150 MHz*, and peripheral and slow clock must * not exceed 100 MHz * * -* - The total current consumption must be less than or equal to +* - The total current consumption must be less than or equal to * 250 mA * * * \warning * - Numbers shown are approximate and real limit values may be -* different because they are device specific. You should refer to the device +* different because they are device specific. You should refer to the device * datasheet for exact values of maximum frequency and current in system LP mode. * * \subsubsection group_syspm_switching_into_ulp Switching the System into Ultra Low Power -* Before switching into system ULP mode, ensure that the device meets -* \ref group_syspm_ulp_limitations. Decrease the clock frequencies, -* and slow or disable peripherals. Also ensure that appropriate wait state -* values are set for the flash. Flash wait states can be set by calling -* SysLib function Cy_SysLib_SetWaitStates(true, hfClkFreqMz), where hfClkFreqMz +* Before switching into system ULP mode, ensure that the device meets +* \ref group_syspm_ulp_limitations. Decrease the clock frequencies, +* and slow or disable peripherals. Also ensure that appropriate wait state +* values are set for the flash. Flash wait states can be set by calling +* SysLib function Cy_SysLib_SetWaitStates(true, hfClkFreqMz), where hfClkFreqMz * is the frequency of HfClk0 in MHz. * -* After the \ref group_syspm_ulp_limitations are met and appropriate wait +* After the \ref group_syspm_ulp_limitations are met and appropriate wait * states are set, you must set ULP voltage for the active core regulator: -* * If active core regulator is the LDO Core Voltage Regulator, call +* * If active core regulator is the LDO Core Voltage Regulator, call * Cy_SysPm_LdoSetVoltage(CY_SYSPM_LDO_VOLTAGE_ULP) -* * If active core regulator is the Buck Core Voltage Regulator, then call +* * If active core regulator is the Buck Core Voltage Regulator, then call * Cy_SysPm_BuckSetVoltage1(CY_SYSPM_BUCK_OUT1_VOLTAGE_ULP) * * \subsubsection group_syspm_ulp_limitations ULP Limitations -* When the system is in ULP mode the core regulator voltage is set to 0.9 V +* When the system is in ULP mode the core regulator voltage is set to 0.9 V * (nominal) and the following limitations must be meet: * -* - The maximum operating frequency for all Clk_HF paths must not exceed -* 50 MHz *, whereas the peripheral and slow clock must not exceed -* 25 MHz *. +* - The maximum operating frequency for all Clk_HF paths must not exceed +* 50 MHz *, whereas the peripheral and slow clock must not exceed +* 25 MHz *. * -* - The total current consumption must be less than or equal +* - The total current consumption must be less than or equal * to 20 mA* * -* - the flash write operations are prohibited. The flash works in the +* - the flash write operations are prohibited. The flash works in the * Read-only operation. If Write operations are required, you must switch to * the system LP mode. * * \warning * - Numbers shown are approximate and real limit values may be -* different because they are device specific. You should refer to the device +* different because they are device specific. You should refer to the device * datasheet for exact values of maximum frequency and current in system * ULP mode. * * \subsubsection group_syspm_switching_into_sleep Switching CPU into Sleep -* For multi-CPU devices, the Cy_SysPm_CpuEnterSleep() switches only the CPU -* that calls the function into the CPU Sleep power mode. +* For multi-CPU devices, the Cy_SysPm_CpuEnterSleep() switches only the CPU +* that calls the function into the CPU Sleep power mode. * -* All pending interrupts must be cleared before the CPU is put into a +* All pending interrupts must be cleared before the CPU is put into a * Sleep mode, even if they are masked. * -* The CPU event register can be set in the past, for example, as a result of -* internal system calls. So an old event can cause the CPU to not enter -* Sleep mode upon WFE(). Therefore usually the WFE() is used in an idle loop or -* polling loop as it might or might not cause entering of CPU Sleep mode. If -* the idle loop or polling loop is not used, then it is recommended to use +* The CPU event register can be set in the past, for example, as a result of +* internal system calls. So an old event can cause the CPU to not enter +* Sleep mode upon WFE(). Therefore usually the WFE() is used in an idle loop or +* polling loop as it might or might not cause entering of CPU Sleep mode. If +* the idle loop or polling loop is not used, then it is recommended to use * WFI() instruction. * * \subsubsection group_syspm_switching_into_deepsleep Switching the System or CPU into Deep Sleep -* For multi-CPU devices, the Cy_SysPm_CpuEnterDeepSleep() function switches -* only the CPU that calls the function into the CPU Deep Sleep power mode. -* To set the whole system into Deep Sleep power mode, ensure that all CPUs call +* For multi-CPU devices, the Cy_SysPm_CpuEnterDeepSleep() function switches +* only the CPU that calls the function into the CPU Deep Sleep power mode. +* To set the whole system into Deep Sleep power mode, ensure that all CPUs call * the Cy_SysPm_CpuEnterDeepSleep() function. * -* There are situations when the system does not switch into the Deep Sleep -* power mode immediately after the last CPU calls Cy_SysPm_CpuEnterDeepSleep(). -* The system will switch into Deep Sleep mode automatically a short time later, -* after the low power circuits are ready to switch into Deep Sleep. Refer to +* There are situations when the system does not switch into the Deep Sleep +* power mode immediately after the last CPU calls Cy_SysPm_CpuEnterDeepSleep(). +* The system will switch into Deep Sleep mode automatically a short time later, +* after the low power circuits are ready to switch into Deep Sleep. Refer to * the Cy_SysPm_CpuEnterDeepSleep() description for more detail. * -* All pending interrupts must be cleared before the system is put into a +* All pending interrupts must be cleared before the system is put into a * Deep Sleep mode, even if they are masked. * -* The CPU event register can be set in the past, for example, as a result of -* internal system calls. So an old event can cause the CPU to not enter Deep -* Sleep mode upon WFE(). Therefore usually the WFE() is used in an idle loop or -* polling loop as it might or might not cause entering of CPU Deep Sleep mode. -* If the idle loop or polling loop is not used, then it is recommended to use -* WFI() instruction. +* The CPU event register can be set in the past, for example, as a result of +* internal system calls. So an old event can cause the CPU to not enter Deep +* Sleep mode upon WFE(). Therefore usually the WFE() is used in an idle loop or +* polling loop as it might or might not cause entering of CPU Deep Sleep mode. +* If the idle loop or polling loop is not used, then it is recommended to use +* WFI() instruction. * -* For single-CPU devices, SysPm functions that return the status of the +* For single-CPU devices, SysPm functions that return the status of the * unsupported CPU always return CY_SYSPM_STATUS__DEEPSLEEP. * * \subsubsection group_syspm_wakingup_from_sleep_deepsleep Waking Up from Sleep or Deep Sleep -* For Arm-based devices, an interrupt is required for the CPU to wake up. -* For multi-CPU devices, one CPU can wake up the other CPU by sending the +* For Arm-based devices, an interrupt is required for the CPU to wake up. +* For multi-CPU devices, one CPU can wake up the other CPU by sending the * event instruction. Use the Cy_SysPm_CpuSendWakeupEvent() function. * * \subsubsection group_syspm_switching_into_hibernate Switching System to Hibernate * If you call Cy_SysPm_SystemEnterHibernate() from either CPU, the system will -* be switched into the Hibernate power mode directly, because there is no +* be switched into the Hibernate power mode directly, because there is no * handshake between CPUs. * * \subsubsection group_syspm_wakingup_from_hibernate Waking Up from Hibernate @@ -243,75 +243,75 @@ * - RTC alarm * - WDT interrupt * -* Wakeup is supported from device specific pin(s) with programmable polarity. -* Additionally, unregulated peripherals can wake the system under some -* conditions. For example, a low power comparator can wake the system by -* comparing two external voltages, but does not support comparison to an -* internally-generated voltage. The backup power domain remains functional, and -* if present it can schedule an alarm to wake the system from Hibernate using -* the RTC. Alternatively, the Watchdog Timer (WDT) can be configured to wake-up +* Wakeup is supported from device specific pin(s) with programmable polarity. +* Additionally, unregulated peripherals can wake the system under some +* conditions. For example, a low power comparator can wake the system by +* comparing two external voltages, but does not support comparison to an +* internally-generated voltage. The backup power domain remains functional, and +* if present it can schedule an alarm to wake the system from Hibernate using +* the RTC. Alternatively, the Watchdog Timer (WDT) can be configured to wake-up * the system by WDT interrupt. Refer to \ref Cy_SysPm_SetHibernateWakeupSource() * for more detail. * * \subsection group_syspm_system_reg_curr_mode System Regulator Current Mode -* In addition to system ULP and LP modes, the five different resource +* In addition to system ULP and LP modes, the five different resource * power settings can be configured to reduce current consumption: * -# Linear regulator low power mode. Can be used only if core current * is below the LDO regulator LP threshold. -* -# POR/BOD circuit low power mode. Requires compatible power supply +* -# POR/BOD circuit low power mode. Requires compatible power supply * stability due to stability increase response time. -* -# Bandgap reference circuits low power mode (turns on Deep Sleep -* Bandgap). Requires design to accept reduced Vref accuracy. Active ref can +* -# Bandgap reference circuits low power mode (turns on Deep Sleep +* Bandgap). Requires design to accept reduced Vref accuracy. Active ref can * be turned off after this feature is enabled. -* -# Reference buffer circuit low power mode. Requires design to accept +* -# Reference buffer circuit low power mode. Requires design to accept * reduced Vref accuracy. -* -# Current reference circuit low power mode. Require design to accept +* -# Current reference circuit low power mode. Require design to accept * reduced Iref accuracy. * -* These five sub features can modify both system LP or ULP modes as they are -* independent from LP/ULP settings. -* When all five sub features are set to their low power modes, the system +* These five sub features can modify both system LP or ULP modes as they are +* independent from LP/ULP settings. +* When all five sub features are set to their low power modes, the system * operates in regulator minimum current mode. In regulator minimum current mode, -* the system current consumption is limited to a device-specific value. Refer to -* the device datasheet for the exact current consumption value in regulator +* the system current consumption is limited to a device-specific value. Refer to +* the device datasheet for the exact current consumption value in regulator * minimum current mode. -* +* * When all five sub features are set to their normal mode, the system operates -* in regulator normal current mode. When regulator normal current mode is set, +* in regulator normal current mode. When regulator normal current mode is set, * the system may operate at device maximum current. -* +* * \subsection group_syspm_system_set_min_reg_curr_mode Setting Minimum System Regulator Current Mode * -* Before setting the regulator minimum current mode ensure that current limits -* are be met. After current limits are met, call the +* Before setting the regulator minimum current mode ensure that current limits +* are be met. After current limits are met, call the * Cy_SysPm_SystemSetMinRegulatorCurrent() function. -* +* * \subsection group_syspm_system_set_normal_reg_curr_mode Setting Normal System Regulator Current Mode * -* To set regulator normal current mode, call the -* Cy_SysPm_SystemSetNormalRegulatorCurrent() function. After the function call, -* the current limits can be increased to a maximum current, depending on what +* To set regulator normal current mode, call the +* Cy_SysPm_SystemSetNormalRegulatorCurrent() function. After the function call, +* the current limits can be increased to a maximum current, depending on what * system power mode is set: LP or ULP. * * \subsection group_syspm_managing_pmic Managing PMIC * -* The SysPm driver also provides an API to configure the internal power -* management integrated circuit (PMIC) controller for an external PMIC that +* The SysPm driver also provides an API to configure the internal power +* management integrated circuit (PMIC) controller for an external PMIC that * supplies Vddd. Use the API to enable the internal PMIC controller output that -* is routed to pmic_wakeup_out pin, and configure the polarity of the PMIC +* is routed to pmic_wakeup_out pin, and configure the polarity of the PMIC * controller input (pmic_wakeup_in) that is used to wake up the PMIC. * * The PMIC controller is automatically enabled when: * * The PMIC is locked by a call to Cy_SysPm_PmicLock() -* * The configured polarity of the PMIC input and the polarity driven to +* * The configured polarity of the PMIC input and the polarity driven to * pmic_wakeup_in pin matches. * * Because a call to Cy_SysPm_PmicLock() automatically enables the PMIC -* controller, the PMIC can remain disabled only when it is unlocked. See Cy_SysPm_PmicUnlock() +* controller, the PMIC can remain disabled only when it is unlocked. See Cy_SysPm_PmicUnlock() * for more detail. * * Use Cy_SysPm_PmicIsLocked() to read the current PMIC lock status. -* +* * To enable the PMIC, use these functions in this order: * \code{.c} * Cy_SysPm_PmicUnlock(); @@ -319,8 +319,8 @@ * Cy_SysPm_PmicLock(); * \endcode * -* To disable the PMIC controller, unlock the PMIC. Then call -* Cy_SysPm_PmicDisable() with the inverted value of the current active state of +* To disable the PMIC controller, unlock the PMIC. Then call +* Cy_SysPm_PmicDisable() with the inverted value of the current active state of * the pmic_wakeup_in pin. * For example, assume the current state of the pmic_wakeup_in pin is active low. * To disable the PMIC controller, call these functions in this order: @@ -328,20 +328,20 @@ * Cy_SysPm_PmicUnlock(); * Cy_SysPm_PmicDisable(CY_SYSPM_PMIC_POLARITY_HIGH); * \endcode -* Note that you do not call Cy_SysPm_PmicLock(), because that automatically +* Note that you do not call Cy_SysPm_PmicLock(), because that automatically * enables the PMIC. -* -* While disabled, the PMIC controller is automatically enabled when the +* +* While disabled, the PMIC controller is automatically enabled when the * pmic_wakeup_in pin state is changed into a high state. * * To disable the PMIC controller output, call these functions in this order: * Cy_SysPm_PmicUnlock(); * Cy_SysPm_PmicDisableOutput(); * -* Do not call Cy_SysPm_PmicLock() (which automatically enables the PMIC +* Do not call Cy_SysPm_PmicLock() (which automatically enables the PMIC * controller output). -* -* When disabled, the PMIC controller output is enabled when the PMIC is locked, +* +* When disabled, the PMIC controller output is enabled when the PMIC is locked, * or by calling Cy_SysPm_PmicEnableOutput(). * * \subsection group_syspm_managing_backup_domain Managing the Backup Domain @@ -350,139 +350,139 @@ * * Configure Supercapacitor charging * * Select power supply source (Vbackup or Vddd) for Vddbackup * * Measure Vddbackup using the ADC -* +* * Refer to the \ref group_syspm_functions_backup functions for more detail. * * \subsection group_syspm_cb SysPm Callbacks -* The SysPm driver handles low power callbacks declared in the application. +* The SysPm driver handles low power callbacks declared in the application. * -* If there are no callbacks registered, the device executes the power mode -* transition. However, frequently your application firmware must make -* modifications for low power mode. For example, you may need to disable a +* If there are no callbacks registered, the device executes the power mode +* transition. However, frequently your application firmware must make +* modifications for low power mode. For example, you may need to disable a * peripheral, or ensure that a message is not being transmitted or received. * * To enable this, the SysPm driver implements a callback mechanism. When a lower -* power mode transition is about to take place (either entering or exiting -* \ref group_syspm_system_power_modes), the registered callbacks for that +* power mode transition is about to take place (either entering or exiting +* \ref group_syspm_system_power_modes), the registered callbacks for that * transition are called. * -* The SysPm driver organizes all the callbacks into a linked list. While -* entering a low power mode, SysPm goes through that linked list from first to +* The SysPm driver organizes all the callbacks into a linked list. While +* entering a low power mode, SysPm goes through that linked list from first to * last, executing the callbacks one after another. While exiting low power mode, -* SysPm goes through that linked list again, but in the opposite direction from -* last to first. This ordering supports prioritization of callbacks relative to -* the transition event. +* SysPm goes through that linked list again, but in the opposite direction from +* last to first. This ordering supports prioritization of callbacks relative to +* the transition event. * -* For example, the picture below shows three callback structures organized into -* a linked list: myDeepSleep1, myDeepSleep2, myDeepSleep3 (represented with the -* \ref cy_stc_syspm_callback_t configuration structure). Each structure -* contains, among other fields, the address of the callback function. The code -* snippets below set this up so that myDeepSleep1 is called first when entering -* the low power mode. This also means that myDeepSleep1 will be the last one to +* For example, the picture below shows three callback structures organized into +* a linked list: myDeepSleep1, myDeepSleep2, myDeepSleep3 (represented with the +* \ref cy_stc_syspm_callback_t configuration structure). Each structure +* contains, among other fields, the address of the callback function. The code +* snippets below set this up so that myDeepSleep1 is called first when entering +* the low power mode. This also means that myDeepSleep1 will be the last one to * execute when exiting the low power mode. * * The callback structures after registration: * \image html syspm_register_eq.png * -* Your application must register each callback, so that SysPm can execute it. -* Upon registration, the linked list is built by the SysPm driver. Notice -* the &myDeepSleep1 address in the myDeepSleep1 +* Your application must register each callback, so that SysPm can execute it. +* Upon registration, the linked list is built by the SysPm driver. Notice +* the &myDeepSleep1 address in the myDeepSleep1 * \ref cy_stc_syspm_callback_t structure. This is filled in by the SysPm driver, -* when you register myDeepSleep1. The cy_stc_syspm_callback_t.order element +* when you register myDeepSleep1. The cy_stc_syspm_callback_t.order element * defines the order of their execution by the SysPm driver. -* Call \ref Cy_SysPm_RegisterCallback() to register each callback function. -* -* A callback function is typically associated with a particular driver that -* handles the peripheral. So the callback mechanism enables a peripheral to -* prepare for a low power mode (for instance, shutting down the analog part); -* or to perform tasks while exiting a low power mode (like enabling the analog +* Call \ref Cy_SysPm_RegisterCallback() to register each callback function. +* +* A callback function is typically associated with a particular driver that +* handles the peripheral. So the callback mechanism enables a peripheral to +* prepare for a low power mode (for instance, shutting down the analog part); +* or to perform tasks while exiting a low power mode (like enabling the analog * part again). * * With the callback mechanism you can prevent switching into a low power mode if -* a peripheral is not ready. For example, driver X is in the process of -* receiving a message. In the callback function implementation simply return +* a peripheral is not ready. For example, driver X is in the process of +* receiving a message. In the callback function implementation simply return * CY_SYSPM_FAIL in a response to CY_SYSPM_CHECK_READY. * -* If success is returned while executing a callback, the SysPm driver calls the -* next callback and so on to the end of the list. If at some point a callback -* returns CY_SYSPM_FAIL in response to the CY_SYSPM_CHECK_READY step, all the -* callbacks that have already executed are executed in reverse order, with the -* CY_SYSPM_CHECK_FAIL mode parameter. This allows each callback to know that +* If success is returned while executing a callback, the SysPm driver calls the +* next callback and so on to the end of the list. If at some point a callback +* returns CY_SYSPM_FAIL in response to the CY_SYSPM_CHECK_READY step, all the +* callbacks that have already executed are executed in reverse order, with the +* CY_SYSPM_CHECK_FAIL mode parameter. This allows each callback to know that * entering the low power mode has failed. The callback can then undo whatever it -* did to prepare for low power mode, if required. For example, if the driver X +* did to prepare for low power mode, if required. For example, if the driver X * callback shut down the analog part, it can re-enable the analog part. -* -* Let's switch to an example explaining the implementation, setup, and -* registration of three callbacks (myDeepSleep1, myDeepSleep2, myDeepSleep2) in -* the application. The \ref group_syspm_cb_config_consideration are provided +* +* Let's switch to an example explaining the implementation, setup, and +* registration of three callbacks (myDeepSleep1, myDeepSleep2, myDeepSleep2) in +* the application. The \ref group_syspm_cb_config_consideration are provided * after the \ref group_syspm_cb_example. -* +* * \subsection group_syspm_cb_example SysPm Callbacks Example * * The following code snippets demonstrate how use the SysPm callbacks mechanism. -* We will build the prototype for an application that registers +* We will build the prototype for an application that registers * three callback functions: * -# myDeepSleep1 - Handles CPU Deep Sleep. -* -# myDeepSleep2 - Handles CPU Deep Sleep and is associated with peripheral -* HW1_address (see PDL Design +* -# myDeepSleep2 - Handles CPU Deep Sleep and is associated with peripheral +* HW1_address (see PDL Design * section to learn about the base hardware address). -* -# myDeepSleep3 - Handles entering and exiting system Deep Sleep and is +* -# myDeepSleep3 - Handles entering and exiting system Deep Sleep and is * associated with peripheral HW2_address. * -* We set things up so that the myDeepSleep1 and myDeepSleep2 callbacks do -* nothing while entering the low power mode (skip on -* CY_SYSPM_SKIP_BEFORE_TRANSITION - -* see \ref group_syspm_cb_function_implementation in +* We set things up so that the myDeepSleep1 and myDeepSleep2 callbacks do +* nothing while entering the low power mode (skip on +* CY_SYSPM_SKIP_BEFORE_TRANSITION - +* see \ref group_syspm_cb_function_implementation in * \ref group_syspm_cb_config_consideration). -* Skipping the actions while entering low power might be useful if you need +* Skipping the actions while entering low power might be useful if you need * to save time while switching low power modes. This is because the callback * function with a skipped mode is not even called avoiding the call and return * overhead. -* -* Let's first declare the callback functions. Each gets the pointer to the +* +* Let's first declare the callback functions. Each gets the pointer to the * \ref cy_stc_syspm_callback_params_t structure as the argument. * * \snippet syspm/snippet/main.c snippet_Cy_SysPm_Callback_Func_Declaration * * Now we setup the \ref cy_stc_syspm_callback_params_t structures that we will -* pass to the callback functions. Note that for the myDeepSleep2 and -* myDeepSleep3 callbacks we also pass pointers to the peripherals related to -* that callback (see PDL Design section -* to learn about base hardware addresses). -* The configuration considerations related to this structure are described +* pass to the callback functions. Note that for the myDeepSleep2 and +* myDeepSleep3 callbacks we also pass pointers to the peripherals related to +* that callback (see PDL Design section +* to learn about base hardware addresses). +* The configuration considerations related to this structure are described * in \ref group_syspm_cb_parameters in \ref group_syspm_cb_config_consideration. * * \snippet syspm/snippet/main.c snippet_Cy_SysPm_Callback_Params_Declaration * -* Now we setup the actual callback configuration structures. Each of these -* contains, among the other fields, the address of the -* \ref cy_stc_syspm_callback_params_t we just set up. We will use the callback -* configuration structures later in the code to register the callbacks in the -* SysPm driver. Again, we set things up so that the myDeepSleep1 and -* myDeepSleep2 callbacks do nothing while entering the low power mode -* (skip on CY_SYSPM_SKIP_BEFORE_TRANSITION) - see -* \ref group_syspm_cb_function_implementation in +* Now we setup the actual callback configuration structures. Each of these +* contains, among the other fields, the address of the +* \ref cy_stc_syspm_callback_params_t we just set up. We will use the callback +* configuration structures later in the code to register the callbacks in the +* SysPm driver. Again, we set things up so that the myDeepSleep1 and +* myDeepSleep2 callbacks do nothing while entering the low power mode +* (skip on CY_SYSPM_SKIP_BEFORE_TRANSITION) - see +* \ref group_syspm_cb_function_implementation in * \ref group_syspm_cb_config_consideration. * * \snippet syspm/snippet/main.c snippet_Cy_SysPm_Callback_Structure_Declaration * -* Note that in each case the last two fields are NULL. These are fields used by +* Note that in each case the last two fields are NULL. These are fields used by * the SysPm driver to set up the linked list of callback functions. -* -* The callback structures are now defined and allocated in the user's +* +* The callback structures are now defined and allocated in the user's * memory space: * \image html syspm_before_registration.png * -* Now we implement the callback functions. See -* \ref group_syspm_cb_function_implementation in -* \ref group_syspm_cb_config_consideration for the instructions on how the +* Now we implement the callback functions. See +* \ref group_syspm_cb_function_implementation in +* \ref group_syspm_cb_config_consideration for the instructions on how the * callback functions should be implemented. * * \snippet syspm/snippet/main.c snippet_Cy_SysPm_Callback_Func_Implementation * -* Finally, we register the callbacks so that the SysPm driver knows about them. -* The order in which the callbacks will be called depends upon the order in -* which the callbacks are registered. If there are no callbacks registered, +* Finally, we register the callbacks so that the SysPm driver knows about them. +* The order in which the callbacks will be called depends upon the order in +* which the callbacks are registered. If there are no callbacks registered, * the device just executes the power mode transition. * * Callbacks that reconfigure global resources, such as clock frequencies, should @@ -493,149 +493,149 @@ * \snippet syspm/snippet/main.c snippet_Cy_SysPm_RegisterCallback * * We are done configuring three callbacks. Now the SysPm driver will execute the -* callbacks appropriately whenever there is a call to a power mode transition -* function: \ref Cy_SysPm_CpuEnterSleep(), \ref Cy_SysPm_CpuEnterDeepSleep(), -* \ref Cy_SysPm_SystemEnterUlp(), \ref Cy_SysPm_SystemEnterLp(), and +* callbacks appropriately whenever there is a call to a power mode transition +* function: \ref Cy_SysPm_CpuEnterSleep(), \ref Cy_SysPm_CpuEnterDeepSleep(), +* \ref Cy_SysPm_SystemEnterUlp(), \ref Cy_SysPm_SystemEnterLp(), and * \ref Cy_SysPm_SystemEnterHibernate(). -* \note On a wakeup from hibernate the device goes through a reset, so the -* callbacks with CY_SYSPM_AFTER_TRANSITION are not executed. Refer to +* \note On a wakeup from hibernate the device goes through a reset, so the +* callbacks with CY_SYSPM_AFTER_TRANSITION are not executed. Refer to * \ref Cy_SysPm_SystemEnterHibernate() for more detail. -* -* Refer to \ref group_syspm_cb_unregistering in -* \ref group_syspm_cb_config_consideration to learn what to do if you need to -* remove the callback from the linked list. You might want to unregister the +* +* Refer to \ref group_syspm_cb_unregistering in +* \ref group_syspm_cb_config_consideration to learn what to do if you need to +* remove the callback from the linked list. You might want to unregister the * callback for debug purposes. -* -* Refer to \ref group_syspm_cb_flow in \ref group_syspm_cb_config_consideration +* +* Refer to \ref group_syspm_cb_flow in \ref group_syspm_cb_config_consideration * to learn about how the SysPm processes the callbacks. * * \subsection group_syspm_cb_config_consideration Callback Configuration Considerations * * \subsubsection group_syspm_cb_parameters Callback Function Parameters -* -* The callbackParams parameter of the callback function is a -* \ref cy_stc_syspm_callback_params_t structure. The second parameter -* (mode) is for internal use. In the example code we used a -* dummy value CY_SYSPM_CHECK_READY to eliminate compilation errors associated -* with the enumeration. The driver sets the mode field to the correct -* value when calling the callback functions (the mode is referred to as step in -* the \ref group_syspm_cb_function_implementation). The callback function reads -* the value and executes code based on the mode set by the SysPm driver. -* The base and context fields are optional and can be NULL. -* Some drivers require a base hardware address and context to store information -* about the mode transition. If your callback routine requires access to the -* driver registers or context, provide those values -* (see PDL Design section -* to learn about Base Hardware Address). Be aware of MISRA warnings if these +* +* The callbackParams parameter of the callback function is a +* \ref cy_stc_syspm_callback_params_t structure. The second parameter +* (mode) is for internal use. In the example code we used a +* dummy value CY_SYSPM_CHECK_READY to eliminate compilation errors associated +* with the enumeration. The driver sets the mode field to the correct +* value when calling the callback functions (the mode is referred to as step in +* the \ref group_syspm_cb_function_implementation). The callback function reads +* the value and executes code based on the mode set by the SysPm driver. +* The base and context fields are optional and can be NULL. +* Some drivers require a base hardware address and context to store information +* about the mode transition. If your callback routine requires access to the +* driver registers or context, provide those values +* (see PDL Design section +* to learn about Base Hardware Address). Be aware of MISRA warnings if these * parameters are NULL. * * \subsubsection group_syspm_cb_structures Callback Function Structure -* For each callback, provide a \ref cy_stc_syspm_callback_t structure. Some -* fields in this structure are maintained by the driver. Use NULL for -* cy_stc_syspm_callback_t.prevItm and cy_stc_syspm_callback_t.nextItm. +* For each callback, provide a \ref cy_stc_syspm_callback_t structure. Some +* fields in this structure are maintained by the driver. Use NULL for +* cy_stc_syspm_callback_t.prevItm and cy_stc_syspm_callback_t.nextItm. * Driver uses these fields to build a linked list of callback functions. * The value of cy_stc_syspm_callback_t.order element is used to define the order -* how the callbacks are put into linked list, and sequentially, how the +* how the callbacks are put into linked list, and sequentially, how the * callbacks are executed. See \ref group_syspm_cb_registering section. * -* \warning The Cy_SysPm_RegisterCallback() function stores a pointer to the -* cy_stc_syspm_callback_t structure. Do not modify elements of the -* cy_stc_syspm_callback_t structure after the callback is registered. -* You are responsible for ensuring that the structure remains in scope. -* Typically the structure is declared as a global or static variable, or as a +* \warning The Cy_SysPm_RegisterCallback() function stores a pointer to the +* cy_stc_syspm_callback_t structure. Do not modify elements of the +* cy_stc_syspm_callback_t structure after the callback is registered. +* You are responsible for ensuring that the structure remains in scope. +* Typically the structure is declared as a global or static variable, or as a * local variable in the main() function. * * \subsubsection group_syspm_cb_function_implementation Callback Function Implementation * -* Every callback function should handle four possible steps (referred to as +* Every callback function should handle four possible steps (referred to as * "mode") defined in \ref cy_en_syspm_callback_mode_t : * * CY_SYSPM_CHECK_READY - Check if ready to enter a power mode. -* * CY_SYSPM_BEFORE_TRANSITION - The actions to be done before entering +* * CY_SYSPM_BEFORE_TRANSITION - The actions to be done before entering * the low power mode. -* * CY_SYSPM_AFTER_TRANSITION - The actions to be done after exiting the +* * CY_SYSPM_AFTER_TRANSITION - The actions to be done after exiting the * low power mode. -* * CY_SYSPM_CHECK_FAIL - Roll back any actions performed in the callback +* * CY_SYSPM_CHECK_FAIL - Roll back any actions performed in the callback * executed previously with CY_SYSPM_CHECK_READY. * * A callback function can skip steps (see \ref group_syspm_skip_callback_modes). -* In our example myDeepSleep1 and myDeepSleep2 callbacks do nothing while +* In our example myDeepSleep1 and myDeepSleep2 callbacks do nothing while * entering the low power mode (skip on CY_SYSPM_BEFORE_TRANSITION). If there is * anything preventing low power mode entry - return CY_SYSPM_FAIL in response to -* CY_SYSPM_CHECK_READY in your callback implementation. Note that the callback -* should return CY_SYSPM_FAIL only in response to CY_SYSPM_CHECK_READY. The -* callback function should always return CY_SYSPM_PASS for other modes: +* CY_SYSPM_CHECK_READY in your callback implementation. Note that the callback +* should return CY_SYSPM_FAIL only in response to CY_SYSPM_CHECK_READY. The +* callback function should always return CY_SYSPM_PASS for other modes: * CY_SYSPM_CHECK_FAIL, CY_SYSPM_BEFORE_TRANSITION, and CY_SYSPM_AFTER_TRANSITION * (see \ref group_syspm_cb_flow). -* +* * \subsubsection group_syspm_cb_flow Callbacks Execution Flow * -* This section explains what happens during a power transition, when callbacks +* This section explains what happens during a power transition, when callbacks * are implemented and set up correctly. The following discussion assumes: * * All required callback functions are defined and implemented * * All cy_stc_syspm_callback_t structures are filled with required values -* * All callbacks are successfully registered +* * All callbacks are successfully registered * -* User calls one of the power mode transition functions: \ref Cy_SysPm_CpuEnterSleep(), -* \ref Cy_SysPm_CpuEnterDeepSleep(), \ref Cy_SysPm_SystemEnterUlp(), -* \ref Cy_SysPm_SystemEnterLp(), or \ref Cy_SysPm_SystemEnterHibernate(). -* It calls each callback with the mode set to CY_SYSPM_CHECK_READY. This +* User calls one of the power mode transition functions: \ref Cy_SysPm_CpuEnterSleep(), +* \ref Cy_SysPm_CpuEnterDeepSleep(), \ref Cy_SysPm_SystemEnterUlp(), +* \ref Cy_SysPm_SystemEnterLp(), or \ref Cy_SysPm_SystemEnterHibernate(). +* It calls each callback with the mode set to CY_SYSPM_CHECK_READY. This * triggers execution of the code for that mode inside of each user callback. -* +* * The intent of CY_SYSPM_CHECK_READY is to only signal if the resources is ready -* to transition. Ideally, no transition changes should be made at this time. -* In some cases a small change may be required. For example a communication -* resource callback may set a flag telling firmware not to start any new +* to transition. Ideally, no transition changes should be made at this time. +* In some cases a small change may be required. For example a communication +* resource callback may set a flag telling firmware not to start any new * transition. -* If that process is successful for all callbacks, then -* \ref Cy_SysPm_ExecuteCallback() calls each callback with the mode set to -* CY_SYSPM_BEFORE_TRANSITION. This triggers execution of the code for that mode +* If that process is successful for all callbacks, then +* \ref Cy_SysPm_ExecuteCallback() calls each callback with the mode set to +* CY_SYSPM_BEFORE_TRANSITION. This triggers execution of the code for that mode * inside each user callback. We then enter the low power mode after all callback * are executed. -* -* When exiting the low power mode, the SysPm driver executes -* \ref Cy_SysPm_ExecuteCallback() again. This time it calls each callback in -* reverse order, with the mode set to CY_SYSPM_AFTER_TRANSITION. This triggers -* execution of the code for that mode inside each user callback. The final -* execution of callbacks depends on the low power mode in which callbacks were +* +* When exiting the low power mode, the SysPm driver executes +* \ref Cy_SysPm_ExecuteCallback() again. This time it calls each callback in +* reverse order, with the mode set to CY_SYSPM_AFTER_TRANSITION. This triggers +* execution of the code for that mode inside each user callback. The final +* execution of callbacks depends on the low power mode in which callbacks were * called: -* * For CPU Sleep or Deep Sleep power modes, the CY_SYSPM_AFTER_TRANSITION mode +* * For CPU Sleep or Deep Sleep power modes, the CY_SYSPM_AFTER_TRANSITION mode * is called after the CPU wakes from Sleep or Deep Sleep. -* * For system Hibernate, the CY_SYSPM_AFTER_TRANSITION mode is not executed +* * For system Hibernate, the CY_SYSPM_AFTER_TRANSITION mode is not executed * because the device reboots after the wakeup from the Hibernate. -* * For system LP and ULP modes, after the CY_SYSPM_AFTER_TRANSITION mode was +* * For system LP and ULP modes, after the CY_SYSPM_AFTER_TRANSITION mode was * called the system remains in the new power mode: LP or ULP. -* -* A callback can return CY_SYSPM_FAIL only while executing the -* CY_SYSPM_CHECK_READY mode. If that happens, then the remaining callbacks are -* not executed. Any callbacks that have already executed are called again, in -* reverse order, with CY_SYSPM_CHECK_FAIL. This allows the system to return to -* the previous state. If a callback returns a fail then any of the functions -* (\ref Cy_SysPm_CpuEnterSleep(), \ref Cy_SysPm_CpuEnterDeepSleep(), -* \ref Cy_SysPm_SystemEnterUlp(), \ref Cy_SysPm_SystemEnterLp(), or -* \ref Cy_SysPm_SystemEnterHibernate()) that attempt to switch the device into +* +* A callback can return CY_SYSPM_FAIL only while executing the +* CY_SYSPM_CHECK_READY mode. If that happens, then the remaining callbacks are +* not executed. Any callbacks that have already executed are called again, in +* reverse order, with CY_SYSPM_CHECK_FAIL. This allows the system to return to +* the previous state. If a callback returns a fail then any of the functions +* (\ref Cy_SysPm_CpuEnterSleep(), \ref Cy_SysPm_CpuEnterDeepSleep(), +* \ref Cy_SysPm_SystemEnterUlp(), \ref Cy_SysPm_SystemEnterLp(), or +* \ref Cy_SysPm_SystemEnterHibernate()) that attempt to switch the device into * a low power mode will also return CY_SYSPM_FAIL. * -* Callbacks that reconfigure global resources, such as clock frequencies, -* should be registered last. They then modify global resources as the final -* step before entering the low power mode, and restore those resources first, +* Callbacks that reconfigure global resources, such as clock frequencies, +* should be registered last. They then modify global resources as the final +* step before entering the low power mode, and restore those resources first, * as the system returns from low power mode. * * \subsubsection group_syspm_cb_registering Callback Registering -* While registration the callback is put into the linked list. The -* place where the callback structure is put into the linked list is based on -* cy_stc_syspm_callback_t.order. The callback with the lowest -* cy_stc_syspm_callback_t.order value will be placed at the beginning of linked -* list. The callback with the highest cy_stc_syspm_callback_t.order value will +* While registration the callback is put into the linked list. The +* place where the callback structure is put into the linked list is based on +* cy_stc_syspm_callback_t.order. The callback with the lowest +* cy_stc_syspm_callback_t.order value will be placed at the beginning of linked +* list. The callback with the highest cy_stc_syspm_callback_t.order value will * be placed at the end of the linked list. * If there is already a callback structure in the linked list with the same -* cy_stc_syspm_callback_t.order value as you attend to register, then your +* cy_stc_syspm_callback_t.order value as you attend to register, then your * callback will be placed right after such a callback. * -* Such a registration order defines how the callbacks are executed: -* * Callbacks with the lower cy_stc_syspm_callback_t.order are executed first +* Such a registration order defines how the callbacks are executed: +* * Callbacks with the lower cy_stc_syspm_callback_t.order are executed first * when entering into low power and last when exiting from low power. -* * Callbacks with the higher cy_stc_syspm_callback_t.order are executed last +* * Callbacks with the higher cy_stc_syspm_callback_t.order are executed last * when entering into low power and first when exiting from low power. * * \snippet syspm/snippet/main.c snippet_Cy_SysPm_RegisterCallback @@ -644,14 +644,14 @@ * registered in the same order as they are registered: * \image html syspm_register_eq.png -* Callbacks with a different cy_stc_syspm_callback_t.order value will be -* stored based on the cy_stc_syspm_callback_t.order value, with no matter when +* Callbacks with a different cy_stc_syspm_callback_t.order value will be +* stored based on the cy_stc_syspm_callback_t.order value, with no matter when * they when registered: * * \image html syspm_register_dif.png * -* This can be useful to ensure that system resources (clock dividers, etc) are -* changed right before entering low power mode and immediately after exiting +* This can be useful to ensure that system resources (clock dividers, etc) are +* changed right before entering low power mode and immediately after exiting * from low power. * * \subsubsection group_syspm_cb_unregistering Callback Unregistering @@ -673,42 +673,42 @@ * * * -* * * * * -* * * * * -* * * * -* * * * * -* * * * * -* * *
VersionChangesReason for Change
2.60Updated the following functions for the PSoC 64 devices: +* \ref Cy_SysLib_ClearFlashCacheAndBuffer, \ref Cy_SysLib_ClearResetReason, +* \ref Cy_SysLib_SetWaitStates. +* Added PSoC 64 device support.
Minor documentation updates.Documentation enhancement.
2.50.3Add section Known Issues * Documentation update and clarification.
LDOLow dropout linear regulator. The functions that manage this -* block are grouped as \ref group_syspm_functions_ldo under +* Low dropout linear regulator. The functions that manage this +* block are grouped as \ref group_syspm_functions_ldo under * \ref group_syspm_functions_core_regulators
SIMO BuckSingle inductor multiple Output Buck regulator, referred as -* "Buck regulator" throughout the documentation. The functions that +* Single inductor multiple Output Buck regulator, referred as +* "Buck regulator" throughout the documentation. The functions that * manage this block are grouped as \ref group_syspm_functions_buck under * \ref group_syspm_functions_core_regulators
SISO BuckSingle inductor single output Buck regulator, referred as -* "Buck regulator" throughout the documentation. The functions that +* Single inductor single output Buck regulator, referred as +* "Buck regulator" throughout the documentation. The functions that * manage this block are grouped as \ref group_syspm_functions_buck under * \ref group_syspm_functions_core_regulators
PMICPower management integrated circuit. The functions that manage this +* Power management integrated circuit. The functions that manage this * block are grouped as \ref group_syspm_functions_pmic
LPSystem low power mode. See the \ref group_syspm_switching_into_lp +* System low power mode. See the \ref group_syspm_switching_into_lp * section for details.
ULPSystem ultra low power mode. See the +* System ultra low power mode. See the * \ref group_syspm_switching_into_ulp section for details.
@@ -724,38 +724,87 @@ * * * +* +* +* +* +* +* +* +* +* +* +* +* +* * * * * * * * -* * * * * * @@ -776,34 +825,34 @@ * * * * * * * * -* * * -* -* * * @@ -813,7 +862,7 @@ * * * * * * -* @@ -835,13 +884,13 @@ * * * * * * -* * @@ -849,7 +898,7 @@ * * * * @@ -857,8 +906,8 @@ * * * * -* * -* * * @@ -928,33 +977,33 @@ * - CY_SYSPM_STATUS_CM4_LOWPOWER * * * * * * * * * -* -* * @@ -962,13 +1011,13 @@ * * -* * * *
VersionChangesReason for Change
5.10 +* Updated the following functions for the PSoC 64 devices: +* \ref Cy_SysPm_CpuEnterDeepSleep(), \ref Cy_SysPm_SystemEnterLp(), +* \ref Cy_SysPm_SystemEnterUlp, \ref Cy_SysPm_SystemEnterHibernate, +* \ref Cy_SysPm_SetHibernateWakeupSource, +* \ref Cy_SysPm_ClearHibernateWakeupSource, +* \ref Cy_SysPm_SystemSetMinRegulatorCurrent, +* \ref Cy_SysPm_SystemSetNormalRegulatorCurrent, +* \ref Cy_SysPm_LdoSetVoltage, \ref Cy_SysPm_LdoSetMode, +* \ref Cy_SysPm_BuckEnable, \ref Cy_SysPm_BuckSetVoltage1, +* Following functions are updated as unavailble for PSoC 64 devices: +* \ref Cy_SysPm_WriteVoltageBitForFlash, \ref Cy_SysPm_SaveRegisters, +* \ref Cy_SysPm_RestoreRegisters, +* \ref Cy_SysPm_BuckSetVoltage2, \ref Cy_SysPm_BuckEnableVoltage2, +* \ref Cy_SysPm_BuckDisableVoltage2, +* \ref Cy_SysPm_BuckSetVoltage2HwControl, SetReadMarginTrimUlp, +* SetReadMarginTrimLp, SetWriteAssistTrimUlp, IsVoltageChangePossible. +* +* Added PSoC 64 device support. +*
+* For PSoC 64 devices the following functions can return PRA driver +* status value: +* \ref Cy_SysPm_CpuEnterDeepSleep(), +* \ref Cy_SysPm_SystemEnterHibernate(), +* \ref Cy_SysPm_SystemEnterLp(), +* \ref Cy_SysPm_SystemEnterUlp(), +* \ref Cy_SysPm_SystemSetMinRegulatorCurrent(), +* \ref Cy_SysPm_SystemSetNormalRegulatorCurrent(), +* \ref Cy_SysPm_LdoSetVoltage(), \ref Cy_SysPm_LdoSetMode(), +* \ref Cy_SysPm_BuckEnable(), \ref Cy_SysPm_BuckSetVoltage1(), +* +* For PSoC 64 devices the SysPm driver uses the PRA driver to change +* the protected registers. A SysPm driver function that calls a PRA +* driver function will return the PRA error status code if the called +* PRA function returns an error. In these cases, refer to PRA return +* statuses \ref cy_en_pra_status_t. +*
Minor documentation updates.Documentation enhancement.
5.0 -* Updated the internal IsVoltageChangePossible() function -* (\ref Cy_SysPm_LdoSetVoltage(), \ref Cy_SysPm_BuckEnable(), +* Updated the internal IsVoltageChangePossible() function +* (\ref Cy_SysPm_LdoSetVoltage(), \ref Cy_SysPm_BuckEnable(), * \ref Cy_SysPm_BuckSetVoltage1(), \ref Cy_SysPm_SystemEnterUlp() * and \ref Cy_SysPm_SystemEnterLp() functions are affected). -* For all the devices except CY8C6xx6 and CY8C6xx7 added the check if +* For all the devices except CY8C6xx6 and CY8C6xx7 added the check if * modifying the RAM trim register is allowed. * -* Protecting the system from a possible CPU hard-fault cause. If you -* are using PC > 0 in your project and you want to switch the power -* modes (LP<->ULP), you need to unprotect the CPUSS_TRIM_RAM_CTL and +* Protecting the system from a possible CPU hard-fault cause. If you +* are using PC > 0 in your project and you want to switch the power +* modes (LP<->ULP), you need to unprotect the CPUSS_TRIM_RAM_CTL and * CPUSS_TRIM_ROM_CTL registers and can use a programmable PPU for that. *
4.50Updated the \ref Cy_SysPm_CpuEnterDeepSleep() function. +* * Updated the mechanism for saving/restoring not retained UDB and clock * registers in the Cy_SysPm_CpuEnterDeepSleep() function. *
-* Updated the \ref Cy_SysPm_CpuEnterDeepSleep() function to use values -* stored into the variable instead of reading them directly from +* Updated the \ref Cy_SysPm_CpuEnterDeepSleep() function to use values +* stored into the variable instead of reading them directly from * SFLASH memory. * -* SFLASH memory can be unavailable to read the correct value after +* SFLASH memory can be unavailable to read the correct value after * a Deep sleep state on the CY8C6xx6 and CY8C6xx7 devices. *
4.30 -* Corrected the \ref Cy_SysPm_CpuEnterDeepSleep() function. -* Removed early access to flash values after system Deep Sleep, when +* Corrected the \ref Cy_SysPm_CpuEnterDeepSleep() function. +* Removed early access to flash values after system Deep Sleep, when * flash is not ready to be used. Now the \ref Cy_SysPm_CpuEnterDeepSleep() * function does not access flash until the flash is ready. -* This behavior is applicable only on multi-CPU devices CY8C6xx6 and +* This behavior is applicable only on multi-CPU devices CY8C6xx6 and * CY8C6xx7. * -* For CY8C6xx6 and CY8C6xx7 early access to flash values after -* system Deep Sleep could potentially cause hard fault. -* Now after system Deep Sleep only ram values are used before +* For CY8C6xx6 and CY8C6xx7 early access to flash values after +* system Deep Sleep could potentially cause hard fault. +* Now after system Deep Sleep only ram values are used before * flash is ready. *
4.20Updated the \ref Cy_SysPm_RegisterCallback() function. -* Added a new element to callback structure - +* Added a new element to callback structure - * cy_stc_syspm_callback_t.orderEnhanced the mechanism of callbacks registration and execution. Now +* Enhanced the mechanism of callbacks registration and execution. Now * callbacks can be ordered during registration. This means the * execution flow now is based on cy_stc_syspm_callback_t.order. * For more details, see the \ref group_syspm_cb_registering section.
Updated \ref group_syspm_cb section. +* Updated \ref group_syspm_cb section. * Added \ref group_syspm_cb_registering sectionAdded explanations how to use updated callbacks registration +* Added explanations how to use updated callbacks registration * mechanism.
4.10.1 -* Updated the Cy_SysPm_BackupEnableVoltageMeasurement() description +* Updated the Cy_SysPm_BackupEnableVoltageMeasurement() description * * Changed the scale number from 40% to 10% to correctly reflect a real value. @@ -822,12 +871,12 @@ *
4.10Updated the \ref Cy_SysPm_CpuEnterDeepSleep() function. +* * Corrected the mechanism for saving/restoring not retained UDB * registers in the Cy_SysPm_CpuEnterDeepSleep() function. * * Now, the \ref Cy_SysPm_CpuEnterDeepSleep() function does not put CM0+ CPU -* into Deep Sleep and returns \ref CY_SYSPM_SYSCALL_PENDING status, if a +* into Deep Sleep and returns \ref CY_SYSPM_SYSCALL_PENDING status, if a * syscall operation is pending. This behavior is applicable on multi-CPU * devices except CY8C6xx6 and CY8C6xx7. *
Updated the \ref Cy_SysPm_CpuEnterSleep() function.Removed the redundant second call of the WFE() instruction on CM4 CPU. -* This change is applicable for all devices except CY8C6xx6, +* This change is applicable for all devices except CY8C6xx6, * CY8C6xx7. *
Added a new \ref CY_SYSPM_SYSCALL_PENDING return status. Expanded driver return statuses for indicating new possible events in +* Expanded driver return statuses for indicating new possible events in * the driver. *
4.0 -* Flattened the organization of the driver source code into the single +* Flattened the organization of the driver source code into the single * source directory and the single include directory. * Driver library directory-structure simplification.
* Changed power modes names. See \ref group_syspm_system_power_modes. -* -* Renamed the following functions: +* +* Renamed the following functions: * - Cy_SysPm_Sleep to Cy_SysPm_CpuEnterSleep * - Cy_SysPm_DeepSleep to Cy_SysPm_CpuEnterDeepSleep * - Cy_SysPm_Hibernate to Cy_SysPm_SystemEnterHibernate @@ -888,17 +937,17 @@ * Added new functionality to configure device power modes
+* * Callback mechanism changes: -* - Removed the limitation for numbers of registered callbacks. Previously it -* was possible to register up to 32 callbacks. Now the maximum registered +* - Removed the limitation for numbers of registered callbacks. Previously it +* was possible to register up to 32 callbacks. Now the maximum registered * callbacks is not limited by the SysPm driver. * - Internal enhancement in callback execution flow. * - Changes with BWC issues: * -# Removed the mode element from cy_stc_syspm_callback_params_t -* structure. Now this element is a separate parameter in the +* structure. Now this element is a separate parameter in the * callback function. -* -# Changed the interface of the callback function, +* -# Changed the interface of the callback function, * added the cy_en_syspm_callback_mode_t mode parameter: * - was cy_en_syspm_status_t FuncName (cy_stc_syspm_callback_params_t *callbackParams); * - now cy_en_syspm_status_t FuncName (cy_stc_syspm_callback_params_t *callbackParams, @@ -909,7 +958,7 @@ *
Added register access layer. Use register access macros instead * of direct register access using dereferenced pointers.Makes register access device-independent, so that the PDL does +* Makes register access device-independent, so that the PDL does * not need to be recompiled for each supported part number.
-* Removed the two functions Cy_SysPm_Cm4IsLowPower, -* Cy_SysPm_Cm0IsLowPower because low power mode is related to the +* Removed the two functions Cy_SysPm_Cm4IsLowPower, +* Cy_SysPm_Cm0IsLowPower because low power mode is related to the * device and not to the CPU. -* The function Cy_SysPm_IsSystemUlp must be used instead of these two +* The function Cy_SysPm_IsSystemUlp must be used instead of these two * functions. * -* Removed Cy_SysPm_IoFreeze because the are no known use cases with IOs +* Removed Cy_SysPm_IoFreeze because the are no known use cases with IOs * freeze in power modes, except Hibernate. In Hibernate power mode, the * IOs are frozen automatically. *
-* Corrected the syspm callback mechanism behavior. Now callbacks with +* Corrected the syspm callback mechanism behavior. Now callbacks with * CY_SYSPM_AFTER_TRANSITION mode are executed from the last registered -* to the first registered. Previously callbacks with -* CY_SYSPM_AFTER_TRANSITION mode were executed from last executed to +* to the first registered. Previously callbacks with +* CY_SYSPM_AFTER_TRANSITION mode were executed from last executed to * the first registered. * Corrected the syspm callbacks execution sequence
2.21Removed saving/restoring the SysClk measurement counters while +* Removed saving/restoring the SysClk measurement counters while * in Deep Sleep routine * Removed possible corruption of SysClk measurement counters if the +* Removed possible corruption of SysClk measurement counters if the * core wakes up from the Deep Sleep. *
2.20 \n * * Added support for changing core voltage when the protection context -* is other that zero. Such support is available only for devices +* is other that zero. Such support is available only for devices * that support modifying registers via syscall. * * * For preproduction PSoC 6 devices the changing core voltage * is prohibited when the protection context is other than zero. * -* * Updated the following functions. They now have a +* * Updated the following functions. They now have a * \ref cy_en_syspm_status_t return value and use a syscall: * - Cy_SysPm_LdoSetVoltage * - Cy_SysPm_BuckSetVoltage1 @@ -976,16 +1025,16 @@ * * No backward compatibility issues. * -* * Added new CY_SYSPM_CANCELED element in +* * Added new CY_SYSPM_CANCELED element in * the \ref cy_en_syspm_status_t. * * * Documentation updates. * * * Added warning that -* Cy_SysPm_PmicDisable(CY_SYSPM_PMIC_POLARITY_LOW) is not +* Cy_SysPm_PmicDisable(CY_SYSPM_PMIC_POLARITY_LOW) is not * supported by hardware. * Added support for changing the core voltage in protection context +* Added support for changing the core voltage in protection context * higher than zero (PC > 0). * * Documentation update and clarification @@ -994,7 +1043,7 @@ *
2.10 \n -* * Changed names for all Backup, Buck-related functions, defines, +* * Changed names for all Backup, Buck-related functions, defines, * and enums * * Changed next power mode function names: * Cy_SysPm_EnterLowPowerMode @@ -1008,7 +1057,7 @@ * cy_en_syspm_simo_buck_voltage2_t * * Updated Power Modes documentation section * * Added Low Power Callback Managements section -* * Documentation edits +* * Documentation edits * \n * * Improvements made based on usability feedback @@ -1020,7 +1069,7 @@ * Enhancement and defect fixes: * * Added input parameter(s) validation to all public functions * * Removed "_SysPm_" prefixes from the internal functions names -* * Changed the type of elements with limited set of values, from +* * Changed the type of elements with limited set of values, from * uint32_t to enumeration * * Enhanced syspm callback mechanism * * Added functions to control: @@ -1039,24 +1088,24 @@ * * \subsection group_syspm_migration_guide_for_syspm_4_0 Migration Guide: Moving to SysPm v4.0 * -* This section provides a guideline to migrate from v2.21 to v4.0 of the SysPm +* This section provides a guideline to migrate from v2.21 to v4.0 of the SysPm * driver. * * \subsubsection group_syspm_migration_into_4_0_intro Introduction -* +* * If your application currently uses SysPm v2.21 APIs, you must * migrate to SysPm v4.0 so that your application continues to operate. -* +* * Take a few minutes to review the following information: -* - The APIs related to PSoC 6 \ref group_syspm_power_modes are changed. Old -* power modes APIs function names are now deprecated and should not be used +* - The APIs related to PSoC 6 \ref group_syspm_power_modes are changed. Old +* power modes APIs function names are now deprecated and should not be used * in new applications. -* - The \ref group_syspm_cb mechanism is changed. The mode element is removed -* from cy_stc_syspm_callback_params_t structure. Now this element is a +* - The \ref group_syspm_cb mechanism is changed. The mode element is removed +* from cy_stc_syspm_callback_params_t structure. Now this element is a * separate parameter in the callback function. * * \subsubsection group_syspm_migration_into_4_0_names Migrating to new power modes APIs. -* The table below shows the new APIs names that should be used in the +* The table below shows the new APIs names that should be used in the * application instead of old names: * * @@ -1089,13 +1138,13 @@ * * * -* * * * * -* * * @@ -1118,25 +1167,25 @@ * *
Cy_SysPm_EnterLowPowerMode\ref Cy_SysPm_SystemSetMinRegulatorCurrentThe low power active mode does not exist anymore. +* The low power active mode does not exist anymore. * The \ref group_syspm_system_reg_curr_mode is implemented instead
Cy_SysPm_ExitLowPowerMode\ref Cy_SysPm_SystemSetNormalRegulatorCurrentThe low power active mode does not exist anymore. +* The low power active mode does not exist anymore. * The \ref group_syspm_system_reg_curr_mode is implemented instead
* -* In addition to renamed power modes APIs, the following defines and enum +* In addition to renamed power modes APIs, the following defines and enum * elements names are changed: * * * * * -* * * * * -* * * * -* * *
SysPm v2.21 definesSysPm v4.0 definesComment
CY_SYSPM_ENTER_LP_MODECY_SYSPM_ULPThe \ref cy_en_syspm_callback_type_t element is renamed to align +* The \ref cy_en_syspm_callback_type_t element is renamed to align * callback types names to new power modes names
CY_SYSPM_EXIT_LP_MODECY_SYSPM_LPThe \ref cy_en_syspm_callback_type_t element is renamed to align +* The \ref cy_en_syspm_callback_type_t element is renamed to align * callback types names to new power modes names
CY_SYSPM_STATUS_SYSTEM_LOWPOWERCY_SYSPM_STATUS_SYSTEM_ULPStatus define, renamed to align new power modes names +* Status define, renamed to align new power modes names * and abbreviations
@@ -1146,12 +1195,12 @@ * Review this section if your application is using the syspm callback mechanism. * * To migrate to SysPm v4.0 callbacks you need to perform the following steps: -* -# Remove mode element from all \ref cy_stc_syspm_callback_params_t +* -# Remove mode element from all \ref cy_stc_syspm_callback_params_t * structures defined in your application. In SysPm v2.21 this structure is: * \code{.c} -* cy_stc_syspm_callback_params_t deepSleepParam1 = +* cy_stc_syspm_callback_params_t deepSleepParam1 = * { -* CY_SYSPM_CHECK_READY, +* CY_SYSPM_CHECK_READY, * &HW1_address, * &context * }; @@ -1159,13 +1208,13 @@ * * In SysPm v4.0 this structure should be: * \code{.c} -* cy_stc_syspm_callback_params_t deepSleepParam1 = +* cy_stc_syspm_callback_params_t deepSleepParam1 = * { * &HW1_address, * &context * }; * \endcode -* -# Update all defined syspm callback function prototypes to have two +* -# Update all defined syspm callback function prototypes to have two * parameters instead of one. The SysPm v2.21 callback function prototype is: * \code{.c} * cy_en_syspm_status_t Func1 (cy_stc_syspm_callback_params_t *callbackParams); @@ -1175,7 +1224,7 @@ * cy_en_syspm_status_t Func1 (cy_stc_syspm_callback_params_t *callbackParams, cy_en_syspm_callback_mode_t mode); * \endcode * -# Change the syspm callback function implementation to not use a mode -* value as an element of the callbackParams structure, but, as separate +* value as an element of the callbackParams structure, but, as separate * function parameter: * SysPm v2.21 callback function implementation: * \code{.c} @@ -1188,7 +1237,7 @@ * case CY_SYSPM_CHECK_READY: * ... * } -* +* * return (retVal); * } * \endcode @@ -1203,13 +1252,13 @@ * case CY_SYSPM_CHECK_READY: * ... * } -* +* * return (retVal); * } * \endcode * After the changes above are done, you have successfully migrated to SysPm v4.0. * -* Do not forget to review newly added functionality for SysPm v4.0 in the +* Do not forget to review newly added functionality for SysPm v4.0 in the * \ref group_syspm_changelog. * \defgroup group_syspm_macros Macros @@ -1219,7 +1268,7 @@ * \defgroup group_syspm_functions_power Power Modes * \defgroup group_syspm_functions_power_status Power Status * \defgroup group_syspm_functions_iofreeze I/Os Freeze -* \defgroup group_syspm_functions_core_regulators Core Voltage Regulation +* \defgroup group_syspm_functions_core_regulators Core Voltage Regulation * \{ * \defgroup group_syspm_functions_ldo LDO * \defgroup group_syspm_functions_buck Buck @@ -1241,6 +1290,9 @@ #include "cy_device.h" #include "cy_device_headers.h" #include "cy_syslib.h" +#if ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) + #include "cy_pra.h" +#endif /* #if ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) */ #ifdef __cplusplus extern "C" { @@ -1259,7 +1311,7 @@ extern "C" { #define CY_SYSPM_DRV_VERSION_MAJOR 5 /** Driver minor version */ -#define CY_SYSPM_DRV_VERSION_MINOR 0 +#define CY_SYSPM_DRV_VERSION_MINOR 10 /** SysPm driver identifier */ #define CY_SYSPM_ID (CY_PDL_DRV_ID(0x10U)) @@ -1321,7 +1373,7 @@ extern "C" { /* Macro to validate parameters in Cy_SysPm_BackupSetSupply() function */ #define CY_SYSPM_IS_VDDBACKUP_VALID(vddBackControl) (((vddBackControl) == CY_SYSPM_VDDBACKUP_DEFAULT) || \ ((vddBackControl) == CY_SYSPM_VDDBACKUP_VBACKUP)) - + /* Macro to validate parameters in Cy_SysPm_BackupSuperCapCharge() function */ #define CY_SYSPM_IS_SC_CHARGE_KEY_VALID(key) (((key) == CY_SYSPM_SC_CHARGE_ENABLE) || \ ((key) == CY_SYSPM_SC_CHARGE_DISABLE)) @@ -1343,43 +1395,43 @@ extern "C" { */ #define CY_SYSPM_HIB_WAKEUP_PIN0_POS (1UL) -/** The internal define of the second wakeup pin bit +/** The internal define of the second wakeup pin bit * used in the Cy_SysPm_SetHibernateWakeupSource() function */ #define CY_SYSPM_HIB_WAKEUP_PIN1_POS (2UL) /** -* The internal define of the first LPComparator bit +* The internal define of the first LPComparator bit * used in the Cy_SysPm_SetHibernateWakeupSource() function */ #define CY_SYSPM_HIB_WAKEUP_LPCOMP0_POS (4UL) /** -* The internal define for the second LPComparator bit +* The internal define for the second LPComparator bit * used in the Cy_SysPm_SetHibernateWakeupSource() function */ #define CY_SYSPM_HIB_WAKEUP_LPCOMP1_POS (8UL) /** -* The internal define of the first LPComparator value +* The internal define of the first LPComparator value * used in the Cy_SysPm_SetHibernateWakeupSource() function */ #define CY_SYSPM_HIB_WAKEUP_LPCOMP0_MASK (_VAL2FLD(SRSS_PWR_HIBERNATE_MASK_HIBPIN, CY_SYSPM_HIB_WAKEUP_LPCOMP0_POS)) /** -* The internal define of the second LPComparator value +* The internal define of the second LPComparator value * used in the Cy_SysPm_SetHibernateWakeupSource() function */ #define CY_SYSPM_HIB_WAKEUP_LPCOMP1_MASK (_VAL2FLD(SRSS_PWR_HIBERNATE_MASK_HIBPIN, CY_SYSPM_HIB_WAKEUP_LPCOMP1_POS)) /** -* The internal define of the first wake-up pin value +* The internal define of the first wake-up pin value * used in the Cy_SysPm_SetHibernateWakeupSource() function */ #define CY_SYSPM_HIB_WAKEUP_PIN0_MASK (_VAL2FLD(SRSS_PWR_HIBERNATE_MASK_HIBPIN, CY_SYSPM_HIB_WAKEUP_PIN0_POS)) /** -* The internal define of the second wake-up pin value used +* The internal define of the second wake-up pin value used * in the Cy_SysPm_SetHibernateWakeupSource() function */ #define CY_SYSPM_HIB_WAKEUP_PIN1_MASK (_VAL2FLD(SRSS_PWR_HIBERNATE_MASK_HIBPIN, CY_SYSPM_HIB_WAKEUP_PIN1_POS)) @@ -1405,13 +1457,13 @@ extern "C" { CY_SYSPM_HIBERNATE_RTC_ALARM | CY_SYSPM_HIBERNATE_WDT |\ CY_SYSPM_HIBERNATE_PIN0_HIGH | CY_SYSPM_HIBERNATE_PIN1_HIGH) -/* The mask for low power modes the power circuits (POR/BOD, Bandgap +/* The mask for low power modes the power circuits (POR/BOD, Bandgap * reference, Reference buffer, Current reference) when active core regulator is * LDO */ #define CY_SYSPM_PWR_CIRCUITS_LPMODE_ACTIVE_LDO_MASK (SRSS_PWR_CTL_LINREG_LPMODE_Msk | CY_SYSPM_PWR_CIRCUITS_LPMODE_ACTIVE_BUCK_MASK) -/* The mask for low power modes the power circuits (POR/BOD, Bandgap +/* The mask for low power modes the power circuits (POR/BOD, Bandgap * reference, Reference buffer, Current reference) when active core regulator is * Buck */ @@ -1479,7 +1531,7 @@ typedef enum } cy_en_syspm_status_t; /** -* This enumeration is used to initialize the functions wait action. The wait actions can be - +* This enumeration is used to initialize the functions wait action. The wait actions can be - * an interrupt or an event. Refer to the CMSIS for WFE and WFI instruction explanations. */ typedef enum @@ -1488,7 +1540,7 @@ typedef enum CY_SYSPM_WAIT_FOR_EVENT /**< Wait for an event. */ } cy_en_syspm_waitfor_t; -/** This enumeration is used to configure wakeup sources for the System Hibernate +/** This enumeration is used to configure wakeup sources for the System Hibernate * power mode. */ typedef enum @@ -1498,22 +1550,22 @@ typedef enum /** Wake on a high logic level for the LPComp0. */ CY_SYSPM_HIBERNATE_LPCOMP0_HIGH = CY_SYSPM_HIB_WAKEUP_LPCOMP0_MASK | CY_SYSPM_HIB_WAKEUP_LPCOMP0_POLARITY_HIGH_MASK, - + /** Wake on a low logic level for the LPComp1. */ CY_SYSPM_HIBERNATE_LPCOMP1_LOW = CY_SYSPM_HIB_WAKEUP_LPCOMP1_MASK, - + /** Wake on a high logic level for the LPComp1. */ CY_SYSPM_HIBERNATE_LPCOMP1_HIGH = CY_SYSPM_HIB_WAKEUP_LPCOMP1_MASK | CY_SYSPM_HIB_WAKEUP_LPCOMP1_POLARITY_HIGH_MASK, /** Configure the RTC alarm as wakeup source. */ CY_SYSPM_HIBERNATE_RTC_ALARM = SRSS_PWR_HIBERNATE_MASK_HIBALARM_Msk, - + /** Configure the WDT interrupt as wakeup source. */ CY_SYSPM_HIBERNATE_WDT = SRSS_PWR_HIBERNATE_MASK_HIBWDT_Msk, /** Configure a low logic level for the first wakeup-pin. See device datasheet for specific pin. */ CY_SYSPM_HIBERNATE_PIN0_LOW = CY_SYSPM_HIB_WAKEUP_PIN0_MASK, - + /** Configure a high logic level for the first wakeup-pin. See device datasheet for specific pin.*/ CY_SYSPM_HIBERNATE_PIN0_HIGH = CY_SYSPM_HIB_WAKEUP_PIN0_MASK | CY_SYSPM_HIB_WAKEUP_PIN0_POLARITY_HIGH_MASK, @@ -1527,7 +1579,7 @@ typedef enum /** This enumeration is used to select LDO regulator output voltage. */ typedef enum { - CY_SYSPM_LDO_VOLTAGE_ULP = 0U, /**< System ULP nominal LDO voltage. + CY_SYSPM_LDO_VOLTAGE_ULP = 0U, /**< System ULP nominal LDO voltage. See device datasheet for specific voltage. */ CY_SYSPM_LDO_VOLTAGE_LP = 1U, /**< System LP nominal LDO voltage. See device datasheet for specific voltage. */ @@ -1539,9 +1591,9 @@ typedef enum typedef enum { CY_SYSPM_LDO_MODE_DISABLED = 0U, /**< Disables the LDO. */ - CY_SYSPM_LDO_MODE_NORMAL = 1U, /**< Sets normal current mode. See device datasheet for + CY_SYSPM_LDO_MODE_NORMAL = 1U, /**< Sets normal current mode. See device datasheet for specific maximum current limit. */ - CY_SYSPM_LDO_MODE_MIN = 2U /**< Sets minimum current mode. See device datasheet for + CY_SYSPM_LDO_MODE_MIN = 2U /**< Sets minimum current mode. See device datasheet for specific current limit. */ } cy_en_syspm_ldo_mode_t; @@ -1550,9 +1602,9 @@ typedef enum */ typedef enum { - CY_SYSPM_BUCK_OUT1_VOLTAGE_ULP = 0x02U, /**< System ULP nominal Buck voltage. + CY_SYSPM_BUCK_OUT1_VOLTAGE_ULP = 0x02U, /**< System ULP nominal Buck voltage. See device datasheet for specific voltage. */ - CY_SYSPM_BUCK_OUT1_VOLTAGE_LP = 0x05U, /**< LP nominal Buck voltage. + CY_SYSPM_BUCK_OUT1_VOLTAGE_LP = 0x05U, /**< LP nominal Buck voltage. See device datasheet for specific voltage. */ CY_SYSPM_BUCK_OUT1_VOLTAGE_0_9V = 0x02U, /**< 0.9 V nominal Buck voltage */ CY_SYSPM_BUCK_OUT1_VOLTAGE_1_1V = 0x05U /**< 1.1 V nominal Buck voltage */ @@ -1561,9 +1613,9 @@ typedef enum /** This enumeration is used to select the Buck regulator outputs. */ typedef enum { - CY_SYSPM_BUCK_VBUCK_1 = 0x0U, /**< Buck output 1 Voltage (Vbuck1). Typically used to + CY_SYSPM_BUCK_VBUCK_1 = 0x0U, /**< Buck output 1 Voltage (Vbuck1). Typically used to supply the PSoC digital core logic. */ - CY_SYSPM_BUCK_VRF /**< Buck out 2 Voltage (Vbuckrf). Typically used to + CY_SYSPM_BUCK_VRF /**< Buck out 2 Voltage (Vbuckrf). Typically used to supply the BLE radio logic. */ } cy_en_syspm_buck_out_t; @@ -1584,11 +1636,11 @@ typedef enum } cy_en_syspm_buck_voltage2_t; /** -* This enumeration is used to set the polarity for the PMIC input. The PMIC output is +* This enumeration is used to set the polarity for the PMIC input. The PMIC output is * automatically enabled when the configured polarity of the PMIC input and the logic level * driven to the pmic_wakeup_in pin match. * -* \warning +* \warning * Do not use CY_SYSPM_PMIC_POLARITY_LOW as it is not supported by hardware. */ typedef enum @@ -1600,7 +1652,7 @@ typedef enum /** This enumeration selects Vbackup or Vddd to supply Vddbackup. */ typedef enum { - CY_SYSPM_VDDBACKUP_DEFAULT = 0U, /**< Logic automatically selects Vddd if present or + CY_SYSPM_VDDBACKUP_DEFAULT = 0U, /**< Logic automatically selects Vddd if present or Vbackup if Vddd is not present to supply Vddbackup */ CY_SYSPM_VDDBACKUP_VBACKUP = 2U /**< Sets only Vbackup to supply Vddbackup */ } cy_en_syspm_vddbackup_control_t; @@ -1637,19 +1689,19 @@ typedef enum /** This enumeration specifies the associated callback mode. This enum defines the callback mode. */ typedef enum { - CY_SYSPM_CHECK_READY = 0x01U, /**< Callbacks with this mode are executed before entering into the - low power mode. The purpose of his callback function is to check + CY_SYSPM_CHECK_READY = 0x01U, /**< Callbacks with this mode are executed before entering into the + low power mode. The purpose of his callback function is to check if the device is ready to enter the low power mode. */ - CY_SYSPM_CHECK_FAIL = 0x02U, /**< Callbacks with this mode are executed after the CY_SYSPM_CHECK_READY - callbacks execution returns CY_SYSPM_FAIL. - The callback with the CY_SYSPM_CHECK_FAIL mode should roll back the - actions performed in the previously executed callback with + CY_SYSPM_CHECK_FAIL = 0x02U, /**< Callbacks with this mode are executed after the CY_SYSPM_CHECK_READY + callbacks execution returns CY_SYSPM_FAIL. + The callback with the CY_SYSPM_CHECK_FAIL mode should roll back the + actions performed in the previously executed callback with CY_SYSPM_CHECK_READY */ - CY_SYSPM_BEFORE_TRANSITION = 0x04U, /**< Callbacks with this mode are executed after the CY_SYSPM_CHECK_READY + CY_SYSPM_BEFORE_TRANSITION = 0x04U, /**< Callbacks with this mode are executed after the CY_SYSPM_CHECK_READY callbacks execution returns CY_SYSPM_SUCCESS. - Performs the actions to be done before entering into the + Performs the actions to be done before entering into the low power mode. */ - CY_SYSPM_AFTER_TRANSITION = 0x08U /**< Performs the actions to be done after exiting the low power mode + CY_SYSPM_AFTER_TRANSITION = 0x08U /**< Performs the actions to be done after exiting the low power mode if entered. */ } cy_en_syspm_callback_mode_t; @@ -1663,7 +1715,7 @@ typedef enum * \defgroup group_syspm_skip_callback_modes Defines to skip the callbacks modes * \{ * Defines for the SysPm callbacks modes that can be skipped during execution. -* For more information about callbacks modes, refer +* For more information about callbacks modes, refer * to \ref cy_en_syspm_callback_mode_t. */ #define CY_SYSPM_SKIP_CHECK_READY (0x01U) /**< Define to skip check ready mode in the syspm callback */ @@ -1682,9 +1734,9 @@ typedef enum typedef struct { void *base; /**< Base address of a HW instance, matches name of the driver in - the API for the base address. Can be undefined if not required. Base address is not + the API for the base address. Can be undefined if not required. Base address is not required for the SysPm driver as the device has only one set of power modes */ - void *context; /**< Context for the handler function. This item can be + void *context; /**< Context for the handler function. This item can be skipped if not required. Can be undefined if not required. */ } cy_stc_syspm_callback_params_t; @@ -1697,31 +1749,31 @@ typedef struct cy_stc_syspm_callback { Cy_SysPmCallback callback; /**< The callback handler function. */ cy_en_syspm_callback_type_t type; /**< The callback type, see \ref cy_en_syspm_callback_type_t. */ - uint32_t skipMode; /**< The mask of modes to be skipped during callback + uint32_t skipMode; /**< The mask of modes to be skipped during callback execution, see \ref group_syspm_skip_callback_modes. The - corresponding callback mode won't execute if the + corresponding callback mode won't execute if the appropriate define is set. These values can be ORed. If all modes are required to be executed this element - should be equal to zero. Skipping unneeded callback modes speeds up + should be equal to zero. Skipping unneeded callback modes speeds up power mode transitions by skipping unneeded operations. */ - cy_stc_syspm_callback_params_t *callbackParams; /**< The address of a cy_stc_syspm_callback_params_t, + cy_stc_syspm_callback_params_t *callbackParams; /**< The address of a cy_stc_syspm_callback_params_t, the callback is executed with these parameters. */ - struct cy_stc_syspm_callback *prevItm; /**< The previous list item. This element should not be - defined, or defined as NULL. It is for internal - usage to link this structure to the next registered - structure. It will be updated during callback + struct cy_stc_syspm_callback *prevItm; /**< The previous list item. This element should not be + defined, or defined as NULL. It is for internal + usage to link this structure to the next registered + structure. It will be updated during callback registration. Do not modify this element at run-time. */ - - struct cy_stc_syspm_callback *nextItm; /**< The next list item. This element should not be - defined, or defined as NULL. It is for internal usage to + + struct cy_stc_syspm_callback *nextItm; /**< The next list item. This element should not be + defined, or defined as NULL. It is for internal usage to link this structure to the previous registered structure. - It will be updated during callback registration. Do not + It will be updated during callback registration. Do not modify this element at run-time. */ - uint8_t order; /**< Holds the callback execution order value. Range: 0-255. + uint8_t order; /**< Holds the callback execution order value. Range: 0-255. While entering low power mode, callbacks with lower order values - are executed first. While exiting low power mode, + are executed first. While exiting low power mode, the callbacks are executed in the opposite order. Callbacks with the same order value are executed in the order they are registered in the application. */ @@ -1741,10 +1793,19 @@ typedef struct uint32_t CY_SYSPM_UDB_BCTL_QCLK_EN0_REG; /**< UDB bank QCLK_EN0 register */ uint32_t CY_SYSPM_UDB_BCTL_QCLK_EN1_REG; /**< UDB bank QCLK_EN1 register */ uint32_t CY_SYSPM_UDB_BCTL_QCLK_EN2_REG; /**< UDB bank QCLK_EN2 register */ - + uint32_t CY_SYSPM_CM0_CLOCK_CTL_REG; /**< CPUSS CM0+ clock control register */ - uint32_t CY_SYSPM_CM4_CLOCK_CTL_REG; /**< CPUSS CM4 clock control register */ + uint32_t CY_SYSPM_CM4_CLOCK_CTL_REG; /**< CPUSS CM4 clock control register */ } cy_stc_syspm_backup_regs_t; + +#if (defined(CY_DEVICE_SECURE)) +/** PRA structure for Cy_SysPm_BuckSetVoltage2 function parameters */ +typedef struct +{ + cy_en_syspm_buck_voltage2_t praVoltage; /**< The voltage of the Buck regulator output 2 */ + bool praWaitToSettle; /**< Enable/disable the delay after setting a higher voltage */ +} cy_stc_pra_voltage2_t; +#endif /* (defined(CY_DEVICE_SECURE)) */ /** \} group_syspm_data_structures */ /** @@ -1757,8 +1818,10 @@ typedef struct * \{ */ cy_en_syspm_status_t Cy_SysPm_WriteVoltageBitForFlash(cy_en_syspm_flash_voltage_bit_t value); +#if !((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) void Cy_SysPm_SaveRegisters(cy_stc_syspm_backup_regs_t *regs); void Cy_SysPm_RestoreRegisters(cy_stc_syspm_backup_regs_t const *regs); +#endif /* !((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) */ /** \} group_syspm_functions_general */ @@ -1795,6 +1858,7 @@ void Cy_SysPm_ClearHibernateWakeupSource(uint32_t wakeupSource); cy_en_syspm_status_t Cy_SysPm_SystemSetMinRegulatorCurrent(void); cy_en_syspm_status_t Cy_SysPm_SystemSetNormalRegulatorCurrent(void); + __STATIC_INLINE bool Cy_SysPm_SystemIsMinRegulatorCurrentSet(void); void Cy_SysPm_CpuSleepOnExit(bool enable); @@ -1827,11 +1891,11 @@ cy_en_syspm_ldo_mode_t Cy_SysPm_LdoGetMode(void); * \{ */ __STATIC_INLINE void Cy_SysPm_PmicEnable(void); -__STATIC_INLINE void Cy_SysPm_PmicDisable(cy_en_syspm_pmic_wakeup_polarity_t polarity); +__STATIC_INLINE void Cy_SysPm_PmicDisable(cy_en_syspm_pmic_wakeup_polarity_t polarity); __STATIC_INLINE bool Cy_SysPm_PmicIsEnabled(void); __STATIC_INLINE void Cy_SysPm_PmicAlwaysEnable(void); __STATIC_INLINE void Cy_SysPm_PmicEnableOutput(void); -__STATIC_INLINE void Cy_SysPm_PmicDisableOutput(void); +__STATIC_INLINE void Cy_SysPm_PmicDisableOutput(void); __STATIC_INLINE bool Cy_SysPm_PmicIsOutputEnabled(void); __STATIC_INLINE void Cy_SysPm_PmicLock(void); __STATIC_INLINE void Cy_SysPm_PmicUnlock(void); @@ -2111,11 +2175,11 @@ __STATIC_INLINE bool Cy_SysPm_BuckIsEnabled(void) * Function Name: Cy_SysPm_BuckGetVoltage1 ****************************************************************************//** * -* Gets the current nominal output 1 voltage (Vccbuck1) of +* Gets the current nominal output 1 voltage (Vccbuck1) of * the Buck regulator. * * \note The actual device output 1 voltage (Vccbuck1) can be different from -* the nominal voltage because the actual voltage value depends on conditions +* the nominal voltage because the actual voltage value depends on conditions * including load current. * * \return @@ -2139,20 +2203,20 @@ __STATIC_INLINE cy_en_syspm_buck_voltage1_t Cy_SysPm_BuckGetVoltage1(void) * Function Name: Cy_SysPm_BuckGetVoltage2 ****************************************************************************//** * -* Gets the current output 2 nominal voltage (Vbuckrf) of the SIMO +* Gets the current output 2 nominal voltage (Vbuckrf) of the SIMO * Buck regulator. * -* \note The actual device output 2 voltage (Vbuckrf) can be different from the -* nominal voltage because the actual voltage value depends on conditions +* \note The actual device output 2 voltage (Vbuckrf) can be different from the +* nominal voltage because the actual voltage value depends on conditions * including load current. * * \return -* The nominal output voltage of the Buck SIMO regulator output 2 +* The nominal output voltage of the Buck SIMO regulator output 2 * voltage (Vbuckrf). See \ref cy_en_syspm_buck_voltage2_t. * * \note * Function returns zero for devices without a SIMO Buck regulator. -* Refer to the device datasheet about information on whether device contains +* Refer to the device datasheet about information on whether device contains * a SIMO Buck. * * \funcusage @@ -2176,19 +2240,19 @@ __STATIC_INLINE cy_en_syspm_buck_voltage2_t Cy_SysPm_BuckGetVoltage2(void) * Function Name: Cy_SysPm_BuckDisableVoltage2 ****************************************************************************//** * -* Disables the output 2 voltage (Vbuckrf) of the SIMO Buck regulator. The -* output 2 voltage (Vbuckrf) of the Buck regulator is typically used to supply +* Disables the output 2 voltage (Vbuckrf) of the SIMO Buck regulator. The +* output 2 voltage (Vbuckrf) of the Buck regulator is typically used to supply * the BLE radio. * * \note The function does not have effect, if the Buck regulator is * switched off. * -* \note If you are switching the voltage supply source for BLE radio, ensure -* that the new voltage supply for the BLE HW block is settled +* \note If you are switching the voltage supply source for BLE radio, ensure +* that the new voltage supply for the BLE HW block is settled * and is stable before calling the Cy_SysPm_BuckDisableVoltage2() function. * * This function is applicable for devices with the SIMO Buck regulator. -* Refer to the device datasheet for information about whether the device +* Refer to the device datasheet for information about whether the device * contains a SIMO Buck. * * \funcusage @@ -2197,23 +2261,29 @@ __STATIC_INLINE cy_en_syspm_buck_voltage2_t Cy_SysPm_BuckGetVoltage2(void) *******************************************************************************/ __STATIC_INLINE void Cy_SysPm_BuckDisableVoltage2(void) { +#if ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) + CY_PRA_FUNCTION_CALL_VOID_VOID(CY_PRA_MSG_TYPE_SECURE_ONLY, + CY_PRA_PM_FUNC_BUCK_DISABLE_VOLTAGE2); +#else if (0U != cy_device->sysPmSimoPresent) { /* Disable the Vbuck2 output */ SRSS_PWR_BUCK_CTL2 &= (uint32_t) ~_VAL2FLD(SRSS_PWR_BUCK_CTL2_BUCK_OUT2_EN, 1U); } +#endif /* ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) */ } + /******************************************************************************* * Function Name: Cy_SysPm_BuckSetVoltage2HwControl ****************************************************************************//** * * Sets the hardware control for SIMO Buck output 2 (Vbuckrf). * -* When hardware control is enabled for the Vbuckrf output, the firmware -* controlled enable register setting is ignored and the hardware signal is used -* instead. If the product has supporting hardware like BLE radio, it can +* When hardware control is enabled for the Vbuckrf output, the firmware +* controlled enable register setting is ignored and the hardware signal is used +* instead. If the product has supporting hardware like BLE radio, it can * directly control the enable signal for Vbuckrf. * * \param hwControl @@ -2222,7 +2292,7 @@ __STATIC_INLINE void Cy_SysPm_BuckDisableVoltage2(void) * Function does not have an effect if SIMO Buck regulator is disabled. * * The function is applicable for devices with the SIMO Buck regulator. -* Refer to the device datasheet for information about whether the device +* Refer to the device datasheet for information about whether the device * contains a SIMO Buck. * * \funcusage @@ -2231,8 +2301,13 @@ __STATIC_INLINE void Cy_SysPm_BuckDisableVoltage2(void) *******************************************************************************/ __STATIC_INLINE void Cy_SysPm_BuckSetVoltage2HwControl(bool hwControl) { +#if ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) + CY_PRA_FUNCTION_CALL_VOID_PARAM(CY_PRA_MSG_TYPE_SECURE_ONLY, + CY_PRA_PM_FUNC_BUCK_VOLTAGE2_HW_CTRL, + hwControl); +#else bool isBuckEnabled = Cy_SysPm_BuckIsEnabled(); - + if ((0U != cy_device->sysPmSimoPresent) && isBuckEnabled) { if(hwControl) @@ -2244,6 +2319,7 @@ __STATIC_INLINE void Cy_SysPm_BuckSetVoltage2HwControl(bool hwControl) SRSS_PWR_BUCK_CTL2 &= (uint32_t) ~_VAL2FLD(SRSS_PWR_BUCK_CTL2_BUCK_OUT2_HW_SEL, 1U); } } +#endif /* ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) */ } @@ -2253,9 +2329,9 @@ __STATIC_INLINE void Cy_SysPm_BuckSetVoltage2HwControl(bool hwControl) * * Returns the hardware control state for Buck output 2 (Vbuckrf). * -* When hardware control is enabled for the Vbuckrf output, the firmware -* controlled enable register setting is ignored and the hardware signal is used -* instead. If the product has supporting hardware like BLE radio, it can +* When hardware control is enabled for the Vbuckrf output, the firmware +* controlled enable register setting is ignored and the hardware signal is used +* instead. If the product has supporting hardware like BLE radio, it can * directly control the enable signal for Vbuckrf. * * \return @@ -2263,7 +2339,7 @@ __STATIC_INLINE void Cy_SysPm_BuckSetVoltage2HwControl(bool hwControl) * - False if FW control is set for the Buck output 2. * * The function is applicable for devices with the SIMO Buck regulator. -* Refer to device datasheet about information if device contains +* Refer to device datasheet about information if device contains * SIMO Buck. * * \funcusage @@ -2294,8 +2370,8 @@ __STATIC_INLINE bool Cy_SysPm_BuckIsVoltage2HwControlled(void) * * Gets the current output voltage value of the core LDO regulator. * -* \note The actual device Vccd voltage can be different from the -* nominal voltage because the actual voltage value depends on conditions +* \note The actual device Vccd voltage can be different from the +* nominal voltage because the actual voltage value depends on conditions * including the load current. * * \return @@ -2322,7 +2398,7 @@ __STATIC_INLINE cy_en_syspm_ldo_voltage_t Cy_SysPm_LdoGetVoltage(void) * Reads the current status of the core LDO regulator. * * \return -* - True means the LDO is enabled. +* - True means the LDO is enabled. * - False means it is disabled. * * \funcusage @@ -2346,7 +2422,7 @@ __STATIC_INLINE bool Cy_SysPm_LdoIsEnabled(void) * * Checks whether IOs are frozen. * -* \return +* \return * - True if IOs are frozen. * - False if IOs are unfrozen. * @@ -2372,10 +2448,10 @@ __STATIC_INLINE bool Cy_SysPm_IoIsFrozen(void) * * Enable the external PMIC controller that supplies Vddd (if present). * -* For information about the PMIC controller input and output pins and their +* For information about the PMIC controller input and output pins and their * assignment in specific devices, refer to the appropriate device TRM. -* -* This function is not effective when the PMIC controller is locked. Call +* +* This function is not effective when the PMIC controller is locked. Call * Cy_SysPm_PmicUnlock() before enabling the PMIC. * * \funcusage @@ -2399,39 +2475,39 @@ __STATIC_INLINE void Cy_SysPm_PmicEnable(void) ****************************************************************************//** * * Disable the external PMIC controller that supplies Vddd (if present). -* This function does not affect the PMIC controller output pin. The PMIC -* controller input pin has programmable polarity to +* This function does not affect the PMIC controller output pin. The PMIC +* controller input pin has programmable polarity to * enable the external PMIC using different input polarities. The PMIC controller -* is automatically enabled when the input pin polarity and configured polarity +* is automatically enabled when the input pin polarity and configured polarity * match. This function is not effective when the active level of PMIC controller * input pin is equal to the configured PMIC controller polarity. * -* The function is not effective when the PMIC controller is locked. Call +* The function is not effective when the PMIC controller is locked. Call * Cy_SysPm_PmicUnlock() before enabling the PMIC controller. * * \param polarity -* Configures the PMIC controller wakeup input pin to be active low or active -* high. The PMIC will be automatically enabled when the set polarity and the -* active level of PMIC input pin match. +* Configures the PMIC controller wakeup input pin to be active low or active +* high. The PMIC will be automatically enabled when the set polarity and the +* active level of PMIC input pin match. * See \ref cy_en_syspm_pmic_wakeup_polarity_t. * -* The PMIC controller will be enabled automatically by any of RTC alarm or +* The PMIC controller will be enabled automatically by any of RTC alarm or * PMIC wakeup events, regardless of the PMIC controller lock state. * * \note -* Before disabling the PMIC controller, ensure that PMIC input and PMIC output +* Before disabling the PMIC controller, ensure that PMIC input and PMIC output * pins are configured correctly to enable expected PMIC operation. * * \warning -* The PMIC is enabled automatically when you call Cy_SysPm_PmicLock(). +* The PMIC is enabled automatically when you call Cy_SysPm_PmicLock(). * To keep the external PMIC disabled, the PMIC controller must remain unlocked. * -* \warning -* Do not call Cy_SysPm_PmicDisable(CY_SYSPM_PMIC_POLARITY_LOW) because this +* \warning +* Do not call Cy_SysPm_PmicDisable(CY_SYSPM_PMIC_POLARITY_LOW) because this * is not supported by hardware. * -* For information about the PMIC controller input and output pins and their -* assignment in the specific devices, refer to the appropriate +* For information about the PMIC controller input and output pins and their +* assignment in the specific devices, refer to the appropriate * device TRM. * * \funcusage @@ -2441,11 +2517,11 @@ __STATIC_INLINE void Cy_SysPm_PmicEnable(void) __STATIC_INLINE void Cy_SysPm_PmicDisable(cy_en_syspm_pmic_wakeup_polarity_t polarity) { CY_ASSERT_L3(CY_SYSPM_IS_POLARITY_VALID(polarity)); - + if (CY_SYSPM_PMIC_UNLOCK_KEY == _FLD2VAL(BACKUP_PMIC_CTL_UNLOCK, BACKUP_PMIC_CTL)) { - BACKUP_PMIC_CTL = - (_VAL2FLD(BACKUP_PMIC_CTL_UNLOCK, CY_SYSPM_PMIC_UNLOCK_KEY) | + BACKUP_PMIC_CTL = + (_VAL2FLD(BACKUP_PMIC_CTL_UNLOCK, CY_SYSPM_PMIC_UNLOCK_KEY) | _CLR_SET_FLD32U(BACKUP_PMIC_CTL, BACKUP_PMIC_CTL_POLARITY, (uint32_t) polarity)) & ((uint32_t) ~ _VAL2FLD(BACKUP_PMIC_CTL_PMIC_EN, 1U)); } @@ -2456,11 +2532,11 @@ __STATIC_INLINE void Cy_SysPm_PmicDisable(cy_en_syspm_pmic_wakeup_polarity_t pol * Function Name: Cy_SysPm_PmicAlwaysEnable ****************************************************************************//** * -* Enable the external PMIC controller that supplies Vddd (if present) and force -* active. This is a Write once API. It ensures that the PMIC controller cannot +* Enable the external PMIC controller that supplies Vddd (if present) and force +* active. This is a Write once API. It ensures that the PMIC controller cannot * be disabled or polarity changed until a next device reset. -* -* For information about the PMIC controller input and output pins and their +* +* For information about the PMIC controller input and output pins and their * assignment in the specific devices, refer to the appropriate device TRM. * * \funcusage @@ -2477,12 +2553,12 @@ __STATIC_INLINE void Cy_SysPm_PmicAlwaysEnable(void) * Function Name: Cy_SysPm_PmicEnableOutput ****************************************************************************//** * -* Enables the PMIC controller output pin. +* Enables the PMIC controller output pin. * -* The function is not effective when the PMIC controller is locked. Call +* The function is not effective when the PMIC controller is locked. Call * Cy_SysPm_PmicUnlock() before enabling the PMIC controller. * -* For information about the PMIC controller output pin and its assignment in +* For information about the PMIC controller output pin and its assignment in * specific devices, refer to the appropriate device TRM. * * \funcusage @@ -2503,23 +2579,23 @@ __STATIC_INLINE void Cy_SysPm_PmicEnableOutput(void) * Function Name: Cy_SysPm_PmicDisableOutput ****************************************************************************//** * -* Disables the PMIC controller output pin. +* Disables the PMIC controller output pin. * -* When the PMIC controller output pin is disabled and is unlocked, the PMIC +* When the PMIC controller output pin is disabled and is unlocked, the PMIC * controller output pin can be used for the another purpose. * -* The function has no effect when the PMIC is locked. Call +* The function has no effect when the PMIC is locked. Call * Cy_SysPm_PmicUnlock() before enabling the PMIC. * -* For information about the PMIC controller output pin and its assignment in +* For information about the PMIC controller output pin and its assignment in * specific devices, refer to the appropriate device TRM. * * \note -* After the PMIC controller output is disabled, the PMIC output pin returns to -* its GPIO configured state. +* After the PMIC controller output is disabled, the PMIC output pin returns to +* its GPIO configured state. * * \warning -* The PMIC controller output is enabled automatically when you call +* The PMIC controller output is enabled automatically when you call * Cy_SysPm_PmicLock(). To keep the PMIC controller output disabled, the PMIC * controller must remain unlocked. * @@ -2531,10 +2607,10 @@ __STATIC_INLINE void Cy_SysPm_PmicDisableOutput(void) { if (CY_SYSPM_PMIC_UNLOCK_KEY == _FLD2VAL(BACKUP_PMIC_CTL_UNLOCK, BACKUP_PMIC_CTL)) { - BACKUP_PMIC_CTL = + BACKUP_PMIC_CTL = (BACKUP_PMIC_CTL | _VAL2FLD(BACKUP_PMIC_CTL_UNLOCK, CY_SYSPM_PMIC_UNLOCK_KEY)) & ((uint32_t) ~ _VAL2FLD(BACKUP_PMIC_CTL_PMIC_EN_OUTEN, 1U)); - } + } } @@ -2542,13 +2618,13 @@ __STATIC_INLINE void Cy_SysPm_PmicDisableOutput(void) * Function Name: Cy_SysPm_PmicLock ****************************************************************************//** * -* Locks the PMIC control controller register so that no changes can be made. -* The changes are related to PMIC enabling/disabling and PMIC output pin +* Locks the PMIC control controller register so that no changes can be made. +* The changes are related to PMIC enabling/disabling and PMIC output pin * enabling/disabling. * * \warning -* The PMIC controller and/or the PMIC output are enabled automatically when -* you call Cy_SysPm_PmicLock(). To keep the PMIC or PMIC controller output +* The PMIC controller and/or the PMIC output are enabled automatically when +* you call Cy_SysPm_PmicLock(). To keep the PMIC or PMIC controller output * disabled, the PMIC controller must remain unlocked. * * \funcusage @@ -2566,12 +2642,12 @@ __STATIC_INLINE void Cy_SysPm_PmicLock(void) ****************************************************************************//** * * Unlocks the PMIC control register so that changes can be made. The changes are -* related to the PMIC controller enabling/disabling and PMIC output pin +* related to the PMIC controller enabling/disabling and PMIC output pin * enabling/disabling. * * \warning -* The PMIC controller and/or the PMIC output are enabled automatically when -* you call Cy_SysPm_PmicLock(). To keep the PMIC controller or PMIC output +* The PMIC controller and/or the PMIC output are enabled automatically when +* you call Cy_SysPm_PmicLock(). To keep the PMIC controller or PMIC output * disabled, the PMIC must remain unlocked. * * \funcusage @@ -2587,7 +2663,7 @@ __STATIC_INLINE void Cy_SysPm_PmicUnlock(void) /******************************************************************************* * Function Name: Cy_SysPm_PmicIsEnabled ****************************************************************************//** -* +* * This function returns the status of the PMIC controller. * * \return @@ -2607,7 +2683,7 @@ __STATIC_INLINE bool Cy_SysPm_PmicIsEnabled(void) /******************************************************************************* * Function Name: Cy_SysPm_PmicIsOutputEnabled ****************************************************************************//** -* +* * This function returns the status of the PMIC controller output. * * \return @@ -2656,7 +2732,7 @@ __STATIC_INLINE bool Cy_SysPm_PmicIsLocked(void) * Sets the backup supply (Vddback) operation mode. * * \param -* vddBackControl +* vddBackControl * Selects backup supply (Vddback) operation mode. * See \ref cy_en_syspm_vddbackup_control_t. * @@ -2681,7 +2757,7 @@ __STATIC_INLINE void Cy_SysPm_BackupSetSupply(cy_en_syspm_vddbackup_control_t vd * Returns the current backup supply (Vddback) operation mode. * * \return -* The current backup supply (Vddback) operation mode, +* The current backup supply (Vddback) operation mode, * see \ref cy_en_syspm_status_t. * * Refer to device TRM for more detail about backup supply modes. @@ -2703,9 +2779,9 @@ __STATIC_INLINE cy_en_syspm_vddbackup_control_t Cy_SysPm_BackupGetSupply(void) * Function Name: Cy_SysPm_BackupEnableVoltageMeasurement ****************************************************************************//** * -* This function enables Vbackup supply measurement by the ADC. The function -* connects the Vbackup supply to AMuxBusA. The ADC input can then be connected -* to AMuxBusA. Note that the measured signal is scaled by 10% to allow full +* This function enables Vbackup supply measurement by the ADC. The function +* connects the Vbackup supply to AMuxBusA. The ADC input can then be connected +* to AMuxBusA. Note that the measured signal is scaled by 10% to allow full * range measurement by the ADC. * * Refer to device TRM for more detail about Vbackup supply measurement. @@ -2745,13 +2821,13 @@ __STATIC_INLINE void Cy_SysPm_BackupDisableVoltageMeasurement(void) * * Configures the supercapacitor charger circuit. * -* \param key +* \param key * Passes the key to enable or disable the supercapacitor charger circuit. * See \ref cy_en_syspm_sc_charge_key_t. * * \warning * This function is used only for charging the supercapacitor. -* Do not use this function to charge a battery. Refer to device TRM for more +* Do not use this function to charge a battery. Refer to device TRM for more * detail. * * \funcusage @@ -2761,7 +2837,7 @@ __STATIC_INLINE void Cy_SysPm_BackupDisableVoltageMeasurement(void) __STATIC_INLINE void Cy_SysPm_BackupSuperCapCharge(cy_en_syspm_sc_charge_key_t key) { CY_ASSERT_L3(CY_SYSPM_IS_SC_CHARGE_KEY_VALID(key)); - + if(key == CY_SYSPM_SC_CHARGE_ENABLE) { BACKUP_CTL = _CLR_SET_FLD32U((BACKUP_CTL), BACKUP_CTL_EN_CHARGE_KEY, (uint32_t) CY_SYSPM_SC_CHARGE_ENABLE); @@ -2778,7 +2854,7 @@ __STATIC_INLINE void Cy_SysPm_BackupSuperCapCharge(cy_en_syspm_sc_charge_key_t k /** \cond INTERNAL */ /******************************************************************************* -* Backward compatibility macro. The following code is DEPRECATED and must +* Backward compatibility macro. The following code is DEPRECATED and must * not be used in new projects *******************************************************************************/ @@ -2796,9 +2872,9 @@ typedef cy_en_syspm_buck_voltage2_t cy_en_syspm_simo_buck_voltage2_t; #define CY_SYSPM_SIMO_BUCK_OUT2_VOLTAGE_1_15V CY_SYSPM_BUCK_OUT2_VOLTAGE_1_15V #define CY_SYSPM_SIMO_BUCK_OUT2_VOLTAGE_1_2V CY_SYSPM_BUCK_OUT2_VOLTAGE_1_2V #define CY_SYSPM_SIMO_BUCK_OUT2_VOLTAGE_1_25V CY_SYSPM_BUCK_OUT2_VOLTAGE_1_25V -#define CY_SYSPM_SIMO_BUCK_OUT2_VOLTAGE_1_3V CY_SYSPM_BUCK_OUT2_VOLTAGE_1_3V +#define CY_SYSPM_SIMO_BUCK_OUT2_VOLTAGE_1_3V CY_SYSPM_BUCK_OUT2_VOLTAGE_1_3V #define CY_SYSPM_SIMO_BUCK_OUT2_VOLTAGE_1_35V CY_SYSPM_BUCK_OUT2_VOLTAGE_1_35V -#define CY_SYSPM_SIMO_BUCK_OUT2_VOLTAGE_1_4V CY_SYSPM_BUCK_OUT2_VOLTAGE_1_4V +#define CY_SYSPM_SIMO_BUCK_OUT2_VOLTAGE_1_4V CY_SYSPM_BUCK_OUT2_VOLTAGE_1_4V #define CY_SYSPM_SIMO_BUCK_OUT2_VOLTAGE_1_45V CY_SYSPM_BUCK_OUT2_VOLTAGE_1_45V #define CY_SYSPM_SIMO_BUCK_OUT2_VOLTAGE_1_5V CY_SYSPM_BUCK_OUT2_VOLTAGE_1_5V diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_systick.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_systick.h index a368d26108..f78f333504 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_systick.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_systick.h @@ -1,12 +1,12 @@ /***************************************************************************//** * \file cy_systick.h -* \version 1.10 +* \version 1.20 * * Provides the API declarations of the SysTick driver. * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -30,8 +30,8 @@ * \{ * Provides vendor-specific SysTick API. * -* The functions and other declarations used in this driver are in cy_systick.h. -* You can include cy_pdl.h (ModusToolbox only) to get access to all functions and declarations in the PDL. +* The functions and other declarations used in this driver are in cy_systick.h. +* You can include cy_pdl.h to get access to all functions and declarations in the PDL. * * The SysTick timer is part of the CPU. The timer is a down counter with a 24-bit reload/tick value that is clocked by * the FastClk/SlowClk. The timer has the capability to generate an interrupt when the set number of ticks expires and @@ -81,8 +81,25 @@ * * * +* +* +* +* +* +* +* +* +* +* +* +* +* +* * -* * @@ -90,13 +107,13 @@ * * -* * * * * +* enabled. * * * @@ -120,7 +137,6 @@ extern "C" { #endif /** \cond */ -extern cy_israddress __ramVectors[]; typedef void (*Cy_SysTick_Callback)(void); /** \endcond */ @@ -173,7 +189,7 @@ __STATIC_INLINE void Cy_SysTick_Clear(void); #define SYSTICK_DRV_VERSION_MAJOR 1 /** Driver minor version */ -#define SYSTICK_DRV_VERSION_MINOR 10 +#define SYSTICK_DRV_VERSION_MINOR 20 /** Number of the callbacks assigned to the SysTick interrupt */ #define CY_SYS_SYST_NUM_OF_CALLBACKS (5u) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_tcpwm.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_tcpwm.h index 7fbc9830f6..158b9ec903 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_tcpwm.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_tcpwm.h @@ -1,12 +1,12 @@ /***************************************************************************//** * \file cy_tcpwm.h -* \version 1.10.1 +* \version 1.10.2 * * The header file of the TCPWM driver. * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -34,21 +34,21 @@ /** * \addtogroup group_tcpwm * \{ -* -* The TCPWM driver is a multifunction driver that implements Timer Counter, +* +* The TCPWM driver is a multifunction driver that implements Timer Counter, * PWM, and Quadrature Decoder functionality using the TCPWM block. * -* The functions and other declarations used in this driver are in cy_tcpwm_counter.h, -* cy_tcpwm_pwm.h, cy_tcpwm_quaddec.h respectively. Include cy_pdl.h -* (ModusToolbox only) to get access to all functions and declarations in the PDL. +* The functions and other declarations used in this driver are in cy_tcpwm_counter.h, +* cy_tcpwm_pwm.h, cy_tcpwm_quaddec.h respectively. Include cy_pdl.h +* to get access to all functions and declarations in the PDL. * -* Each TCPWM block is a collection of counters that can all be triggered -* simultaneously. For each function call, the base register address of -* the TCPWM being used must be passed first, followed by the index of -* the counter you want to touch next. -* For some functions, you can manage multiple counters simultaneously. You -* provide a bit field representing each counter, rather than the single counter -* index). +* Each TCPWM block is a collection of counters that can all be triggered +* simultaneously. For each function call, the base register address of +* the TCPWM being used must be passed first, followed by the index of +* the counter you want to touch next. +* For some functions, you can manage multiple counters simultaneously. You +* provide a bit field representing each counter, rather than the single counter +* index). * * The TCPWM supports three operating modes: * * Timer/Counter @@ -58,7 +58,7 @@ * \n * \b Timer/Counter * -* Use this mode whenever a specific timing interval or measurement is +* Use this mode whenever a specific timing interval or measurement is * needed. Examples include: * * Creating a periodic interrupt for running other system tasks * * Measuring frequency of an input signal @@ -71,18 +71,18 @@ * The Timer/Counter has the following features: * * 16- or 32-bit Timer/Counter * * Programmable Period Register -* * Programmable Compare Register. Compare value can be swapped with a +* * Programmable Compare Register. Compare value can be swapped with a * buffered compare value on comparison event * * Capture with buffer register * * Count Up, Count Down, or Count Up and Down Counting modes * * Continuous or One Shot Run modes -* * Interrupt and Output on Overflow, Underflow, Capture, or Compare +* * Interrupt and Output on Overflow, Underflow, Capture, or Compare * * Start, Reload, Stop, Capture, and Count Inputs * * \n * \b PWM * -* Use this mode when an output square wave is needed with a specific +* Use this mode when an output square wave is needed with a specific * period and duty cycle, such as: * * Creating arbitrary square wave outputs * * Driving an LED (changing the brightness) @@ -91,30 +91,30 @@ * The PWM has the following features: * * 16- or 32-bit Counter * * Two Programmable Period registers that can be swapped -* * Two Output Compare registers that can be swapped on overflow and/or +* * Two Output Compare registers that can be swapped on overflow and/or * underflow * * Left Aligned, Right Aligned, Center Aligned, and Asymmetric Aligned modes * * Continuous or One Shot run modes * * Pseudo Random mode * * Two PWM outputs with Dead Time insertion, and programmable polarity -* * Interrupt and Output on Overflow, Underflow, or Compare +* * Interrupt and Output on Overflow, Underflow, or Compare * * Start, Reload, Stop, Swap (Capture), and Count Inputs -* * Multiple Components can be synchronized together for applications +* * Multiple Components can be synchronized together for applications * such as three phase motor control * * \n * \b Quadrature \b Decoder * -* A quadrature decoder is used to decode the output of a quadrature encoder. -* A quadrature encoder senses the position, velocity, and direction of -* an object (for example a rotating axle, or a spinning mouse ball). -* A quadrature decoder can also be used for precision measurement of speed, -* acceleration, and position of a motor's rotor, or with a rotary switch to +* A quadrature decoder is used to decode the output of a quadrature encoder. +* A quadrature encoder senses the position, velocity, and direction of +* an object (for example a rotating axle, or a spinning mouse ball). +* A quadrature decoder can also be used for precision measurement of speed, +* acceleration, and position of a motor's rotor, or with a rotary switch to * determine user input. \n -* +* * The Quadrature Decoder has the following features: * * 16- or 32-bit Counter -* * Counter Resolution of x1, x2, and x4 the frequency of the phiA (Count) and +* * Counter Resolution of x1, x2, and x4 the frequency of the phiA (Count) and * phiB (Start) inputs * * Index Input to determine absolute position * * A positive edge on phiA increments the counter when phiB is 0 and decrements @@ -122,40 +122,40 @@ * * \section group_tcpwm_configuration Configuration Considerations * -* For each mode, the TCPWM driver has a configuration structure, an Init -* function, and an Enable function. +* For each mode, the TCPWM driver has a configuration structure, an Init +* function, and an Enable function. * * Provide the configuration parameters in the appropriate structure (see -* Counter \ref group_tcpwm_data_structures_counter, PWM -* \ref group_tcpwm_data_structures_pwm, or QuadDec -* \ref group_tcpwm_data_structures_quaddec). -* Then call the appropriate Init function: -* \ref Cy_TCPWM_Counter_Init, \ref Cy_TCPWM_PWM_Init, or -* \ref Cy_TCPWM_QuadDec_Init. Provide the address of the filled structure as a -* parameter. To enable the counter, call the appropriate Enable function: -* \ref Cy_TCPWM_Counter_Enable, \ref Cy_TCPWM_PWM_Enable, or +* Counter \ref group_tcpwm_data_structures_counter, PWM +* \ref group_tcpwm_data_structures_pwm, or QuadDec +* \ref group_tcpwm_data_structures_quaddec). +* Then call the appropriate Init function: +* \ref Cy_TCPWM_Counter_Init, \ref Cy_TCPWM_PWM_Init, or +* \ref Cy_TCPWM_QuadDec_Init. Provide the address of the filled structure as a +* parameter. To enable the counter, call the appropriate Enable function: +* \ref Cy_TCPWM_Counter_Enable, \ref Cy_TCPWM_PWM_Enable, or * \ref Cy_TCPWM_QuadDec_Enable). * -* Many functions work with an individual counter. You can also manage multiple -* counters simultaneously for certain functions. These are listed in the -* \ref group_tcpwm_functions_common -* section of the TCPWM. You can enable, disable, or trigger (in various ways) -* multiple counters simultaneously. For these functions you provide a bit field -* representing each counter in the TCPWM you want to control. You can -* represent the bit field as an ORed mask of each counter, like -* ((1U << cntNumX) | (1U << cntNumX) | (1U << cntNumX)), where X is the counter +* Many functions work with an individual counter. You can also manage multiple +* counters simultaneously for certain functions. These are listed in the +* \ref group_tcpwm_functions_common +* section of the TCPWM. You can enable, disable, or trigger (in various ways) +* multiple counters simultaneously. For these functions you provide a bit field +* representing each counter in the TCPWM you want to control. You can +* represent the bit field as an ORed mask of each counter, like +* ((1U << cntNumX) | (1U << cntNumX) | (1U << cntNumX)), where X is the counter * number from 0 to 31. * * \note -* * If none of the input terminals (start, reload(index)) are used, the -* software event \ref Cy_TCPWM_TriggerStart or +* * If none of the input terminals (start, reload(index)) are used, the +* software event \ref Cy_TCPWM_TriggerStart or * \ref Cy_TCPWM_TriggerReloadOrIndex must be called to start the counting. -* * If count input terminal is not used, the \ref CY_TCPWM_INPUT_LEVEL macro -* should be set for the countInputMode parameter and the \ref CY_TCPWM_INPUT_1 -* macro should be set for the countInput parameter in the configuration -* structure of the appropriate mode(Counter -* \ref group_tcpwm_data_structures_counter, PWM -* \ref group_tcpwm_data_structures_pwm, or QuadDec +* * If count input terminal is not used, the \ref CY_TCPWM_INPUT_LEVEL macro +* should be set for the countInputMode parameter and the \ref CY_TCPWM_INPUT_1 +* macro should be set for the countInput parameter in the configuration +* structure of the appropriate mode(Counter +* \ref group_tcpwm_data_structures_counter, PWM +* \ref group_tcpwm_data_structures_pwm, or QuadDec * \ref group_tcpwm_data_structures_quaddec). * * \subsection group_tcpwm_pins Assign and Configure Pins @@ -166,17 +166,17 @@ * * \subsection group_tcpwm_clock Assign Clock Divider * The clock source must be connected to proper working. -* Any of the peripheral clock dividers could be used. Use the +* Any of the peripheral clock dividers could be used. Use the * \ref group_sysclk driver API to do that. * * \snippet tcpwm/counter/snippet/main.c snippet_Cy_TCPWM_Clock * * \section group_tcpwm_more_information More Information * -* For more information on the TCPWM peripheral, refer to the technical +* For more information on the TCPWM peripheral, refer to the technical * reference manual (TRM). * -* \section group_tcpwm_MISRA MISRA-C Compliance +* \section group_tcpwm_MISRA MISRA-C Compliance *
VersionChangesReason for Change
1.20.Updated Cy_SysTick_SetClockSource() for the PSoC 64 devices, +* so that passing any other value than CY_SYSTICK_CLOCK_SOURCE_CLK_CPU +* will not affect clock source and it will be as +* \ref Cy_SysTick_GetClockSource() reports.Added PSoC 64 devices support.
Minor documentation updates.Documentation enhancement.
1.10.1Updated include files.Improve pdl usability.
1.10Flattened the organization of the driver source code into the single +* Flattened the organization of the driver source code into the single * source directory and the single include directory. * Driver library directory-structure simplification.
Added register access layer. Use register access macros instead * of direct register access using dereferenced pointers.Makes register access device-independent, so that the PDL does +* Makes register access device-independent, so that the PDL does * not need to be recompiled for each supported part number.
1.0.1Fixed a warning issued when the compilation of C++ source code was -* enabled.
* * @@ -198,13 +198,18 @@ *
MISRA Rule
* * +* +* +* +* +* * * * * * * -* * @@ -212,7 +217,7 @@ * * -* * * @@ -240,9 +245,9 @@ * Most users will use individual drivers and do not need to use the common * API for the TCPWM. * -* The functions and other declarations used in this part of the driver are in cy_tcpwm.h. -* Include either of cy_tcpwm_counter.h, cy_tcpwm_pwm.h, cy_tcpwm_quaddec.h -* depending on the desired functionality. You can also include cy_pdl.h +* The functions and other declarations used in this part of the driver are in cy_tcpwm.h. +* Include either of cy_tcpwm_counter.h, cy_tcpwm_pwm.h, cy_tcpwm_quaddec.h +* depending on the desired functionality. You can also include cy_pdl.h * to get access to all functions and declarations in the PDL. * * \{ @@ -331,7 +336,7 @@ extern "C" { /** * \defgroup group_tcpwm_interrupt_sources Interrupt Sources * \{ -* Interrupt Sources +* Interrupt Sources */ #define CY_TCPWM_INT_ON_TC (1U) /**< Interrupt on Terminal count(TC) */ #define CY_TCPWM_INT_ON_CC (2U) /**< Interrupt on Compare/Capture(CC) */ @@ -382,13 +387,13 @@ extern "C" { */ /** TCPWM status definitions */ -typedef enum +typedef enum { CY_TCPWM_SUCCESS = 0x00U, /**< Successful */ CY_TCPWM_BAD_PARAM = CY_TCPWM_ID | CY_PDL_STATUS_ERROR | 0x01U, /**< One or more invalid parameters */ } cy_en_tcpwm_status_t; /** \} group_tcpwm_enums */ - + /******************************************************************************* * Function Prototypes *******************************************************************************/ @@ -416,7 +421,7 @@ __STATIC_INLINE uint32_t Cy_TCPWM_GetInterruptStatusMasked(TCPWM_Type const *bas * Function Name: Cy_TCPWM_Enable_Multiple ****************************************************************************//** * -* Enables the counter(s) in the TCPWM block. Multiple blocks can be started +* Enables the counter(s) in the TCPWM block. Multiple blocks can be started * simultaneously. * * \param base @@ -439,7 +444,7 @@ __STATIC_INLINE void Cy_TCPWM_Enable_Multiple(TCPWM_Type *base, uint32_t counter * Function Name: Cy_TCPWM_Disable_Multiple ****************************************************************************//** * -* Disables the counter(s) in the TCPWM block. Multiple TCPWM can be disabled +* Disables the counter(s) in the TCPWM block. Multiple TCPWM can be disabled * simultaneously. * * \param base @@ -555,10 +560,10 @@ __STATIC_INLINE void Cy_TCPWM_TriggerCaptureOrSwap(TCPWM_Type *base, uint32_t co * \param base * The pointer to a TCPWM instance. * -* \param cntNum +* \param cntNum * The Counter instance number in the selected TCPWM. * -* \return +* \return * See \ref group_tcpwm_interrupt_sources * * \funcusage @@ -580,7 +585,7 @@ __STATIC_INLINE uint32_t Cy_TCPWM_GetInterruptStatus(TCPWM_Type const *base, uin * \param base * The pointer to a TCPWM instance. * -* \param cntNum +* \param cntNum * The Counter instance number in the selected TCPWM. * * \param source @@ -606,7 +611,7 @@ __STATIC_INLINE void Cy_TCPWM_ClearInterrupt(TCPWM_Type *base, uint32_t cntNum, * \param base * The pointer to a TCPWM instance. * -* \param cntNum +* \param cntNum * The Counter instance number in the selected TCPWM. * * \param source @@ -626,13 +631,13 @@ __STATIC_INLINE void Cy_TCPWM_SetInterrupt(TCPWM_Type *base, uint32_t cntNum, u * Function Name: Cy_TCPWM_SetInterruptMask ****************************************************************************//** * -* Sets an interrupt mask. A 1 means that when the event occurs, it will cause an +* Sets an interrupt mask. A 1 means that when the event occurs, it will cause an * interrupt; a 0 means no interrupt will be triggered. * * \param base * The pointer to a TCPWM instance. * -* \param cntNum +* \param cntNum * The Counter instance number in the selected TCPWM. * * \param mask @@ -657,10 +662,10 @@ __STATIC_INLINE void Cy_TCPWM_SetInterruptMask(TCPWM_Type *base, uint32_t cntNum * \param base * The pointer to a TCPWM instance. * -* \param cntNum +* \param cntNum * The Counter instance number in the selected TCPWM. * -* \return +* \return * Interrupt Mask. See \ref group_tcpwm_interrupt_sources * * \funcusage @@ -682,10 +687,10 @@ __STATIC_INLINE uint32_t Cy_TCPWM_GetInterruptMask(TCPWM_Type const *base, uint3 * \param base * The pointer to a TCPWM instance. * -* \param cntNum +* \param cntNum * The Counter instance number in the selected TCPWM. * -* \return +* \return * Interrupt Mask. See \ref group_tcpwm_interrupt_sources * * \funcusage diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_tcpwm_counter.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_tcpwm_counter.h index 939055fe25..4e2917e3ab 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_tcpwm_counter.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_tcpwm_counter.h @@ -1,13 +1,13 @@ /***************************************************************************//** * \file cy_tcpwm_counter.h -* \version 1.10.1 +* \version 1.10.2 * * \brief * The header file of the TCPWM Timer Counter driver. * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -37,9 +37,9 @@ extern "C" { * \addtogroup group_tcpwm_counter * \{ * Driver API for Timer/Counter. -* -* The functions and other declarations used in this part of the driver are -* in cy_tcpwm_counter.h. You can also include cy_pdl.h (ModusToolbox only) +* +* The functions and other declarations used in this part of the driver are +* in cy_tcpwm_counter.h. You can also include cy_pdl.h * to get access to all functions and declarations in the PDL. */ @@ -59,11 +59,11 @@ typedef struct cy_stc_tcpwm_counter_config { uint32_t period; /**< Sets the period of the counter */ /** Sets the clock prescaler inside the TCWPM block. See \ref group_tcpwm_counter_clk_prescalers */ - uint32_t clockPrescaler; + uint32_t clockPrescaler; uint32_t runMode; /**< Sets the run mode. See \ref group_tcpwm_counter_run_modes */ uint32_t countDirection; /**< Sets the counter direction. See \ref group_tcpwm_counter_direction */ /** The counter can either compare or capture a value. See \ref group_tcpwm_counter_compare_capture */ - uint32_t compareOrCapture; + uint32_t compareOrCapture; uint32_t compare0; /**< Sets the value for Compare0*/ uint32_t compare1; /**< Sets the value for Compare1*/ bool enableCompareSwap; /**< If enabled, the compare values are swapped each time the comparison is true */ @@ -153,7 +153,7 @@ typedef struct cy_stc_tcpwm_counter_config * \addtogroup group_tcpwm_functions_counter * \{ */ -cy_en_tcpwm_status_t Cy_TCPWM_Counter_Init(TCPWM_Type *base, uint32_t cntNum, +cy_en_tcpwm_status_t Cy_TCPWM_Counter_Init(TCPWM_Type *base, uint32_t cntNum, cy_stc_tcpwm_counter_config_t const *config); void Cy_TCPWM_Counter_DeInit(TCPWM_Type *base, uint32_t cntNum, cy_stc_tcpwm_counter_config_t const *config); __STATIC_INLINE void Cy_TCPWM_Counter_Enable(TCPWM_Type *base, uint32_t cntNum); @@ -181,7 +181,7 @@ __STATIC_INLINE uint32_t Cy_TCPWM_Counter_GetPeriod(TCPWM_Type const *base, uint * \param base * The pointer to a TCPWM instance. * -* \param cntNum +* \param cntNum * The Counter instance number in the selected TCPWM. * * \funcusage @@ -203,7 +203,7 @@ __STATIC_INLINE void Cy_TCPWM_Counter_Enable(TCPWM_Type *base, uint32_t cntNum) * \param base * The pointer to a TCPWM instance. * -* \param cntNum +* \param cntNum * The Counter instance number in the selected TCPWM. * * \funcusage @@ -225,7 +225,7 @@ __STATIC_INLINE void Cy_TCPWM_Counter_Disable(TCPWM_Type *base, uint32_t cntNum) * \param base * The pointer to a TCPWM instance. * -* \param cntNum +* \param cntNum * The Counter instance number in the selected TCPWM. * * \return @@ -238,10 +238,10 @@ __STATIC_INLINE void Cy_TCPWM_Counter_Disable(TCPWM_Type *base, uint32_t cntNum) __STATIC_INLINE uint32_t Cy_TCPWM_Counter_GetStatus(TCPWM_Type const *base, uint32_t cntNum) { uint32_t status = TCPWM_CNT_STATUS(base, cntNum); - + /* Generates proper up counting status. Is not generated by HW */ status &= ~CY_TCPWM_COUNTER_STATUS_UP_COUNTING; - status |= ((~status & CY_TCPWM_COUNTER_STATUS_DOWN_COUNTING & (status >> TCPWM_CNT_STATUS_RUNNING_Pos)) << + status |= ((~status & CY_TCPWM_COUNTER_STATUS_DOWN_COUNTING & (status >> TCPWM_CNT_STATUS_RUNNING_Pos)) << CY_TCPWM_CNT_STATUS_UP_POS); return(status); @@ -257,7 +257,7 @@ __STATIC_INLINE uint32_t Cy_TCPWM_Counter_GetStatus(TCPWM_Type const *base, uin * \param base * The pointer to a TCPWM instance. * -* \param cntNum +* \param cntNum * The Counter instance number in the selected TCPWM. * * \return @@ -282,7 +282,7 @@ __STATIC_INLINE uint32_t Cy_TCPWM_Counter_GetCapture(TCPWM_Type const *base, ui * \param base * The pointer to a TCPWM instance. * -* \param cntNum +* \param cntNum * The Counter instance number in the selected TCPWM. * * \return @@ -307,7 +307,7 @@ __STATIC_INLINE uint32_t Cy_TCPWM_Counter_GetCaptureBuf(TCPWM_Type const *base, * \param base * The pointer to a TCPWM instance. * -* \param cntNum +* \param cntNum * The Counter instance number in the selected TCPWM. * * \param compare0 @@ -332,7 +332,7 @@ __STATIC_INLINE void Cy_TCPWM_Counter_SetCompare0(TCPWM_Type *base, uint32_t cnt * \param base * The pointer to a TCPWM instance. * -* \param cntNum +* \param cntNum * The Counter instance number in the selected TCPWM. * * \return @@ -357,7 +357,7 @@ __STATIC_INLINE uint32_t Cy_TCPWM_Counter_GetCompare0(TCPWM_Type const *base, u * \param base * The pointer to a TCPWM instance. * -* \param cntNum +* \param cntNum * The Counter instance number in the selected TCPWM. * * \param compare1 @@ -382,7 +382,7 @@ __STATIC_INLINE void Cy_TCPWM_Counter_SetCompare1(TCPWM_Type *base, uint32_t cnt * \param base * The pointer to a TCPWM instance. * -* \param cntNum +* \param cntNum * The Counter instance number in the selected TCPWM. * * \return @@ -407,7 +407,7 @@ __STATIC_INLINE uint32_t Cy_TCPWM_Counter_GetCompare1(TCPWM_Type const *base, u * \param base * The pointer to a TCPWM instance. * -* \param cntNum +* \param cntNum * The Counter instance number in the selected TCPWM. * * \param enable @@ -439,7 +439,7 @@ __STATIC_INLINE void Cy_TCPWM_Counter_EnableCompareSwap(TCPWM_Type *base, uint32 * \param base * The pointer to a TCPWM instance. * -* \param cntNum +* \param cntNum * The Counter instance number in the selected TCPWM. * * \param count @@ -464,7 +464,7 @@ __STATIC_INLINE void Cy_TCPWM_Counter_SetCounter(TCPWM_Type *base, uint32_t cntN * \param base * The pointer to a TCPWM instance. * -* \param cntNum +* \param cntNum * The Counter instance number in the selected TCPWM. * * \return @@ -489,7 +489,7 @@ __STATIC_INLINE uint32_t Cy_TCPWM_Counter_GetCounter(TCPWM_Type const *base, ui * \param base * The pointer to a TCPWM instance. * -* \param cntNum +* \param cntNum * The Counter instance number in the selected TCPWM. * * \param period @@ -514,7 +514,7 @@ __STATIC_INLINE void Cy_TCPWM_Counter_SetPeriod(TCPWM_Type *base, uint32_t cntNu * \param base * The pointer to a TCPWM instance. * -* \param cntNum +* \param cntNum * The Counter instance number in the selected TCPWM. * * \return diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_tcpwm_pwm.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_tcpwm_pwm.h index b2dafd039e..16f14d136d 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_tcpwm_pwm.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_tcpwm_pwm.h @@ -1,13 +1,13 @@ /***************************************************************************//** * \file cy_tcpwm_pwm.h -* \version 1.10.1 +* \version 1.10.2 * * \brief * The header file of the TCPWM PWM driver. * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -38,8 +38,8 @@ extern "C" { * \addtogroup group_tcpwm_pwm * Driver API for PWM. * -* The functions and other declarations used in this part of the driver are in cy_tcpwm_pwm.h. -* You can also include cy_pdl.h (ModusToolbox only) to get access to all +* The functions and other declarations used in this part of the driver are in cy_tcpwm_pwm.h. +* You can also include cy_pdl.h to get access to all * functions and declarations in the PDL. * \{ */ @@ -76,14 +76,14 @@ typedef struct cy_stc_tcpwm_pwm_config uint32_t invertPWMOutN; /**< Inverts the PWM_n output */ uint32_t killMode; /**< Configures the PWM kill modes. See \ref group_tcpwm_pwm_kill_modes */ uint32_t swapInputMode; /**< Configures how the swap input behaves. See \ref group_tcpwm_input_modes */ - /** Selects which input the swap uses. Inputs are device-specific. See \ref group_tcpwm_input_selection */ + /** Selects which input the swap uses. Inputs are device-specific. See \ref group_tcpwm_input_selection */ uint32_t swapInput; uint32_t reloadInputMode; /**< Configures how the reload input behaves. See \ref group_tcpwm_input_modes */ /** Selects which input the reload uses. The inputs are device-specific. See \ref group_tcpwm_input_selection */ - uint32_t reloadInput; + uint32_t reloadInput; uint32_t startInputMode; /**< Configures how the start input behaves. See \ref group_tcpwm_input_modes */ /** Selects which input the start uses. The inputs are device-specific. See \ref group_tcpwm_input_selection */ - uint32_t startInput; + uint32_t startInput; uint32_t killInputMode; /**< Configures how the kill input behaves. See \ref group_tcpwm_input_modes */ /** Selects which input the kill uses. The inputs are device-specific. See \ref group_tcpwm_input_selection */ uint32_t killInput; @@ -104,7 +104,7 @@ typedef struct cy_stc_tcpwm_pwm_config #define CY_TCPWM_PWM_CONTINUOUS (0U) /**< Counter runs forever */ /** \} group_tcpwm_pwm_run_modes */ -/** \defgroup group_tcpwm_pwm_modes PWM modes +/** \defgroup group_tcpwm_pwm_modes PWM modes * \{ * Sets the PWM modes. */ @@ -239,7 +239,7 @@ __STATIC_INLINE void Cy_TCPWM_PWM_EnablePeriodSwap(TCPWM_Type *base, uint32_t cn * \param base * The pointer to a TCPWM instance. * -* \param cntNum +* \param cntNum * The Counter instance number in the selected TCPWM. * * \funcusage @@ -260,7 +260,7 @@ __STATIC_INLINE void Cy_TCPWM_PWM_Enable(TCPWM_Type *base, uint32_t cntNum) * \param base * The pointer to a TCPWM instance. * -* \param cntNum +* \param cntNum * The Counter instance number in the selected TCPWM. * * \funcusage @@ -282,7 +282,7 @@ __STATIC_INLINE void Cy_TCPWM_PWM_Disable(TCPWM_Type *base, uint32_t cntNum) * \param base * The pointer to a TCPWM instance. * -* \param cntNum +* \param cntNum * The Counter instance number in the selected TCPWM. * * \return @@ -295,12 +295,12 @@ __STATIC_INLINE void Cy_TCPWM_PWM_Disable(TCPWM_Type *base, uint32_t cntNum) __STATIC_INLINE uint32_t Cy_TCPWM_PWM_GetStatus(TCPWM_Type const *base, uint32_t cntNum) { uint32_t status = TCPWM_CNT_STATUS(base, cntNum); - + /* Generates proper up counting status, does not generated by HW */ status &= ~CY_TCPWM_PWM_STATUS_UP_COUNTING; - status |= ((~status & CY_TCPWM_PWM_STATUS_DOWN_COUNTING & (status >> TCPWM_CNT_STATUS_RUNNING_Pos)) << + status |= ((~status & CY_TCPWM_PWM_STATUS_DOWN_COUNTING & (status >> TCPWM_CNT_STATUS_RUNNING_Pos)) << CY_TCPWM_CNT_STATUS_UP_POS); - + return(status); } @@ -314,7 +314,7 @@ __STATIC_INLINE uint32_t Cy_TCPWM_PWM_GetStatus(TCPWM_Type const *base, uint32_t * \param base * The pointer to a TCPWM instance. * -* \param cntNum +* \param cntNum * The Counter instance number in the selected TCPWM. * * \param compare0 @@ -339,7 +339,7 @@ __STATIC_INLINE void Cy_TCPWM_PWM_SetCompare0(TCPWM_Type *base, uint32_t cntNum, * \param base * The pointer to a TCPWM instance. * -* \param cntNum +* \param cntNum * The Counter instance number in the selected TCPWM. * * \return @@ -364,7 +364,7 @@ __STATIC_INLINE uint32_t Cy_TCPWM_PWM_GetCompare0(TCPWM_Type const *base, uint32 * \param base * The pointer to a TCPWM instance. * -* \param cntNum +* \param cntNum * The Counter instance number in the selected TCPWM. * * \param compare1 @@ -389,7 +389,7 @@ __STATIC_INLINE void Cy_TCPWM_PWM_SetCompare1(TCPWM_Type *base, uint32_t cntNum, * \param base * The pointer to a TCPWM instance. * -* \param cntNum +* \param cntNum * The Counter instance number in the selected TCPWM. * * \return @@ -414,7 +414,7 @@ __STATIC_INLINE uint32_t Cy_TCPWM_PWM_GetCompare1(TCPWM_Type const *base, uint32 * \param base * The pointer to a TCPWM instance. * -* \param cntNum +* \param cntNum * The Counter instance number in the selected TCPWM. * * \param enable @@ -446,7 +446,7 @@ __STATIC_INLINE void Cy_TCPWM_PWM_EnableCompareSwap(TCPWM_Type *base, uint32_t c * \param base * The pointer to a TCPWM instance. * -* \param cntNum +* \param cntNum * The Counter instance number in the selected TCPWM. * * \param count @@ -471,7 +471,7 @@ __STATIC_INLINE void Cy_TCPWM_PWM_SetCounter(TCPWM_Type *base, uint32_t cntNum, * \param base * The pointer to a TCPWM instance. * -* \param cntNum +* \param cntNum * The Counter instance number in the selected TCPWM. * * \return @@ -496,7 +496,7 @@ __STATIC_INLINE uint32_t Cy_TCPWM_PWM_GetCounter(TCPWM_Type const *base, uint32_ * \param base * The pointer to a TCPWM instance. * -* \param cntNum +* \param cntNum * The Counter instance number in the selected TCPWM. * * \param period0 @@ -521,7 +521,7 @@ __STATIC_INLINE void Cy_TCPWM_PWM_SetPeriod0(TCPWM_Type *base, uint32_t cntNum, * \param base * The pointer to a TCPWM instance. * -* \param cntNum +* \param cntNum * The Counter instance number in the selected TCPWM. * * \return @@ -546,7 +546,7 @@ __STATIC_INLINE uint32_t Cy_TCPWM_PWM_GetPeriod0(TCPWM_Type const *base, uint32_ * \param base * The pointer to a TCPWM instance. * -* \param cntNum +* \param cntNum * The Counter instance number in the selected TCPWM. * * \param period1 @@ -571,7 +571,7 @@ __STATIC_INLINE void Cy_TCPWM_PWM_SetPeriod1(TCPWM_Type *base, uint32_t cntNum, * \param base * The pointer to a COUNTER PWM instance. * -* \param cntNum +* \param cntNum * The Counter instance number in the selected TCPWM. * * \return @@ -596,7 +596,7 @@ __STATIC_INLINE uint32_t Cy_TCPWM_PWM_GetPeriod1(TCPWM_Type const *base, uint32_ * \param base * The pointer to a TCPWM instance. * -* \param cntNum +* \param cntNum * The Counter instance number in the selected TCPWM. * * \param enable @@ -615,7 +615,7 @@ __STATIC_INLINE void Cy_TCPWM_PWM_EnablePeriodSwap(TCPWM_Type *base, uint32_t cn else { TCPWM_CNT_CTRL(base, cntNum) &= ~TCPWM_CNT_CTRL_AUTO_RELOAD_PERIOD_Msk; - } + } } /** \} group_tcpwm_functions_pwm */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_tcpwm_quaddec.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_tcpwm_quaddec.h index 23be6bfcb7..c843bece56 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_tcpwm_quaddec.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_tcpwm_quaddec.h @@ -1,13 +1,13 @@ /***************************************************************************//** * \file cy_tcpwm_quaddec.h -* \version 1.10.1 +* \version 1.10.2 * * \brief * The header file of the TCPWM Quadrature Decoder driver. * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -37,8 +37,8 @@ extern "C" { * \addtogroup group_tcpwm_quaddec * Driver API for Quadrature Decoder. * -* The functions and other declarations used in this part of the driver are in cy_tcpwm_quaddec.h. -* You can also include cy_pdl.h (ModusToolbox only) to get access to all functions and declarations in the PDL. +* The functions and other declarations used in this part of the driver are in cy_tcpwm_quaddec.h. +* You can also include cy_pdl.h to get access to all functions and declarations in the PDL. * \{ */ @@ -72,14 +72,14 @@ typedef struct cy_stc_tcpwm_quaddec_config uint32_t phiAInput; /** Selects which input the phiB uses. The inputs are device specific. See \ref group_tcpwm_input_selection */ uint32_t phiBInput; - + }cy_stc_tcpwm_quaddec_config_t; /** \} group_tcpwm_data_structures_quaddec */ /** * \addtogroup group_tcpwm_macros_quaddec * \{ -* \defgroup group_tcpwm_quaddec_resolution QuadDec Resolution +* \defgroup group_tcpwm_quaddec_resolution QuadDec Resolution * \{ * The quadrature decoder resolution. */ @@ -117,7 +117,7 @@ typedef struct cy_stc_tcpwm_quaddec_config * \{ */ -cy_en_tcpwm_status_t Cy_TCPWM_QuadDec_Init(TCPWM_Type *base, uint32_t cntNum, +cy_en_tcpwm_status_t Cy_TCPWM_QuadDec_Init(TCPWM_Type *base, uint32_t cntNum, cy_stc_tcpwm_quaddec_config_t const *config); void Cy_TCPWM_QuadDec_DeInit(TCPWM_Type *base, uint32_t cntNum, cy_stc_tcpwm_quaddec_config_t const *config); __STATIC_INLINE void Cy_TCPWM_QuadDec_Enable(TCPWM_Type *base, uint32_t cntNum); @@ -138,7 +138,7 @@ __STATIC_INLINE uint32_t Cy_TCPWM_QuadDec_GetCounter(TCPWM_Type const *base, uin * \param base * The pointer to a TCPWM instance. * -* \param cntNum +* \param cntNum * The Counter instance number in the selected TCPWM. * * \funcusage @@ -159,7 +159,7 @@ __STATIC_INLINE void Cy_TCPWM_QuadDec_Enable(TCPWM_Type *base, uint32_t cntNum) * \param base * The pointer to a TCPWM instance. * -* \param cntNum +* \param cntNum * The Counter instance number in the selected TCPWM. * * \funcusage @@ -181,7 +181,7 @@ __STATIC_INLINE void Cy_TCPWM_QuadDec_Disable(TCPWM_Type *base, uint32_t cntNum) * \param base * The pointer to a TCPWM instance. * -* \param cntNum +* \param cntNum * The Counter instance number in the selected TCPWM. * * \return @@ -194,10 +194,10 @@ __STATIC_INLINE void Cy_TCPWM_QuadDec_Disable(TCPWM_Type *base, uint32_t cntNum) __STATIC_INLINE uint32_t Cy_TCPWM_QuadDec_GetStatus(TCPWM_Type const *base, uint32_t cntNum) { uint32_t status = TCPWM_CNT_STATUS(base, cntNum); - + /* Generates proper up counting status, does not generated by HW */ status &= ~CY_TCPWM_QUADDEC_STATUS_UP_COUNTING; - status |= ((~status & CY_TCPWM_QUADDEC_STATUS_DOWN_COUNTING & (status >> TCPWM_CNT_STATUS_RUNNING_Pos)) << + status |= ((~status & CY_TCPWM_QUADDEC_STATUS_DOWN_COUNTING & (status >> TCPWM_CNT_STATUS_RUNNING_Pos)) << CY_TCPWM_CNT_STATUS_UP_POS); return(status); @@ -213,7 +213,7 @@ __STATIC_INLINE uint32_t Cy_TCPWM_QuadDec_GetStatus(TCPWM_Type const *base, uint * \param base * The pointer to a TCPWM instance. * -* \param cntNum +* \param cntNum * The Counter instance number in the selected TCPWM. * * \return @@ -238,7 +238,7 @@ __STATIC_INLINE uint32_t Cy_TCPWM_QuadDec_GetCapture(TCPWM_Type const *base, uin * \param base * The pointer to a TCPWM instance. * -* \param cntNum +* \param cntNum * The Counter instance number in the selected TCPWM. * * \return @@ -263,7 +263,7 @@ __STATIC_INLINE uint32_t Cy_TCPWM_QuadDec_GetCaptureBuf(TCPWM_Type const *base, * \param base * The pointer to a TCPWM instance. * -* \param cntNum +* \param cntNum * The Counter instance number in the selected TCPWM. * * \param count @@ -288,7 +288,7 @@ __STATIC_INLINE void Cy_TCPWM_QuadDec_SetCounter(TCPWM_Type *base, uint32_t cntN * \param base * The pointer to a TCPWM instance. * -* \param cntNum +* \param cntNum * The Counter instance number in the selected TCPWM. * * \return diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_trigmux.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_trigmux.h index e8a12c1b9f..9f58114de1 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_trigmux.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_trigmux.h @@ -1,12 +1,12 @@ /******************************************************************************* * \file cy_trigmux.h -* \version 1.20.1 +* \version 1.20.2 * * This file provides constants and parameter values for the Trigger multiplexer driver. * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -25,53 +25,53 @@ /** * \addtogroup group_trigmux * \{ -* The trigger multiplexer provides access to the multiplexer that selects a set -* of trigger output signals from different peripheral blocks to route them to the +* The trigger multiplexer provides access to the multiplexer that selects a set +* of trigger output signals from different peripheral blocks to route them to the * specific trigger input of another peripheral block. * -* The functions and other declarations used in this driver are in cy_trigmux.h. -* You can include cy_pdl.h (ModusToolbox only) to get access to all functions -* and declarations in the PDL. +* The functions and other declarations used in this driver are in cy_trigmux.h. +* You can include cy_pdl.h to get access to all functions +* and declarations in the PDL. * -* The TrigMux driver is based on the trigger multiplexer's hardware block. -* The Trigger multiplexer block consists of multiple trigger multiplexers. -* These trigger multiplexers are grouped in trigger groups. All the trigger -* multiplexers in the trigger group share similar input options. +* The TrigMux driver is based on the trigger multiplexer's hardware block. +* The Trigger multiplexer block consists of multiple trigger multiplexers. +* These trigger multiplexers are grouped in trigger groups. All the trigger +* multiplexers in the trigger group share similar input options. * * For PERI_ver1: -* The trigger multiplexer groups are either reduction multiplexers or distribution +* The trigger multiplexer groups are either reduction multiplexers or distribution * multiplexers. The figure below illustrates a generic trigger multiplexer block * implementation with a reduction multiplexer layer of N trigger groups and a * distribution multiplexer layer of M trigger groups. * \image html trigmux_architecture.png -* The reduction multiplexer groups have input options that are the trigger outputs -* coming from the different peripheral blocks and the reduction multiplexer groups -* route them to intermediate signals. The distribution multiplexer groups have input -* options from these intermediate signals and route them back to multiple peripheral +* The reduction multiplexer groups have input options that are the trigger outputs +* coming from the different peripheral blocks and the reduction multiplexer groups +* route them to intermediate signals. The distribution multiplexer groups have input +* options from these intermediate signals and route them back to multiple peripheral * blocks as their trigger inputs. * * For PERI_ver2: * The trigger multiplexer groups structure is flat - all the groups are essentially * distribution multiplexers (there are no any intermediate trigger signals), so the * structure is simpler in comparison with PERI_ver1, however a bit less flexible. -* Additionally there are another type of trigger interconnections: one-to-one +* Additionally there are another type of trigger interconnections: one-to-one * trigger lines. These are not multiplexers, only single trigger wires from/to * the dedicated peripherals. Multiple groups of one-to-one trigger lines * significantly improve the whole triggering interconnect system flexibility. * -* The trigger architecture of the PSoC device is explained in the technical reference +* The trigger architecture of the PSoC device is explained in the technical reference * manual (TRM). Refer to the TRM to better understand the trigger multiplexer routing * architecture available. -* +* * \section group_trigmux_section_Configuration_Considerations Configuration Considerations * * For PERI_ver1: -* To route a trigger signal from one peripheral in the PSoC -* to another, the user must configure a reduction multiplexer and a distribution +* To route a trigger signal from one peripheral in the PSoC +* to another, the user must configure a reduction multiplexer and a distribution * multiplexer. The \ref Cy_TrigMux_Connect is used to configure a trigger multiplexer connection. * The user will need two calls of this API, one for the reduction multiplexer and another * for the distribution multiplexer, to achieve the trigger connection from a source -* peripheral to a destination peripheral. +* peripheral to a destination peripheral. * * For PERI_ver2: * To route a trigger signal from one peripheral in the PSoC device to another, the user can configure @@ -87,26 +87,26 @@ * For PERI_ver2: * \image html trigmux_parameter_30_2.png * In addition, the \ref Cy_TrigMux_Connect function also has an invert and trigger type parameter. -* Refer to the API reference for a detailed description of this parameter. -* All the constants associated with the different trigger signals in the system +* Refer to the API reference for a detailed description of this parameter. +* All the constants associated with the different trigger signals in the system * (input and output) are defined as constants in the device configuration header file. * * For PERI_ver1: -* The constants for TrigMux in the device configuration header file are divided into four -* types based on the signal being input/output and being part of a reduction/distribution +* The constants for TrigMux in the device configuration header file are divided into four +* types based on the signal being input/output and being part of a reduction/distribution * trigger multiplexer. * -* The four types of the input/output parameters are: -* 1) The parameters for the reduction multiplexer's inputs (input signals of TrigMux); -* 2) The parameters for the reduction multiplexer's outputs (intermediate signals); -* 3) The parameters for the distribution multiplexer's inputs (intermediate signals); -* 4) The parameters for the distribution multiplexer's outputs (output signals of TrigMux). +* The four types of the input/output parameters are: +* 1) The parameters for the reduction multiplexer's inputs (input signals of TrigMux); +* 2) The parameters for the reduction multiplexer's outputs (intermediate signals); +* 3) The parameters for the distribution multiplexer's inputs (intermediate signals); +* 4) The parameters for the distribution multiplexer's outputs (output signals of TrigMux). * * For PERI_ver2: * There are two types of TrigMux signal definitions in the device configuration header: * 1) The parameters for the trigger interconnection system input signals. * 2) The parameters for the trigger interconnection system output signals. -* Also there are separate groups of trigger multiplexer input/outputs and groups of +* Also there are separate groups of trigger multiplexer input/outputs and groups of * trigger one-to-one line input/outputs. * * Refer to the TRM for a more detailed description of this architecture and different options. @@ -114,48 +114,48 @@ * The steps to connect one peripheral block to the other: * * For PERI_ver1: -* Step 1. Find the trigger group number in the Trigger Group Inputs section of the device -* configuration header file that corresponds to the output of the source peripheral block. +* Step 1. Find the trigger group number in the Trigger Group Inputs section of the device +* configuration header file that corresponds to the output of the source peripheral block. * For example, TRIG11_IN_TCPWM0_TR_OVERFLOW0 (see \ref group_trigmux_red_in_enums and the diagram * at the top of this section) input of the Reduction multiplexers belongs to Trigger Group 11. * * Step 2. Find the trigger group number in the Trigger Group Outputs section of the device -* configuration header file that corresponds to the input of the destination peripheral block. -* For example, TRIG0_OUT_CPUSS_DW0_TR_IN0 (see \ref group_trigmux_dst_out_enums) output of the +* configuration header file that corresponds to the input of the destination peripheral block. +* For example, TRIG0_OUT_CPUSS_DW0_TR_IN0 (see \ref group_trigmux_dst_out_enums) output of the * Distribution multiplexer belongs to Trigger Group 0. * -* Step 3. Find the same trigger group number in the Trigger Group Inputs section of the -* device configuration header file that corresponds to the trigger group number found in -* Step 1. Select the Reduction multiplexer output that can be connected to the trigger group -* found in Step 2. For example, TRIG0_IN_TR_GROUP11_OUTPUT0 (see \ref group_trigmux_dst_in_enums) -* means that Reduction Multiplexer Output 0 of Trigger Group 11 can be connected to +* Step 3. Find the same trigger group number in the Trigger Group Inputs section of the +* device configuration header file that corresponds to the trigger group number found in +* Step 1. Select the Reduction multiplexer output that can be connected to the trigger group +* found in Step 2. For example, TRIG0_IN_TR_GROUP11_OUTPUT0 (see \ref group_trigmux_dst_in_enums) +* means that Reduction Multiplexer Output 0 of Trigger Group 11 can be connected to * Trigger Group 0. * -* Step 4. Find the same trigger group number in the Trigger Group Outputs section of the +* Step 4. Find the same trigger group number in the Trigger Group Outputs section of the * device configuration header file that corresponds to the trigger group number found in Step 2. * Select the distribution multiplexer input that can be connected to the trigger group found -* in Step 1. For example, TRIG11_OUT_TR_GROUP0_INPUT9 (see \ref group_trigmux_red_out_enums) -* means that the Distribution Multiplexer Input 9 of Trigger Group 0 can be connected to the +* in Step 1. For example, TRIG11_OUT_TR_GROUP0_INPUT9 (see \ref group_trigmux_red_out_enums) +* means that the Distribution Multiplexer Input 9 of Trigger Group 0 can be connected to the * output of the Reduction multiplexer in Trigger Group 11 found in Step 3. * -* Step 5. Call Cy_TrigMux_Connect() API twice: the first call - with the constants for the -* inTrig and outTrig parameters found in Steps 1 and Step 4, the second call - with the -* constants for the inTrig and outTrig parameters found in Steps 2 and Step 3. +* Step 5. Call Cy_TrigMux_Connect() API twice: the first call - with the constants for the +* inTrig and outTrig parameters found in Steps 1 and Step 4, the second call - with the +* constants for the inTrig and outTrig parameters found in Steps 2 and Step 3. * For example: -* \snippet trigmux/snippet/main.c snippet_Cy_TrigMux_PERI_ver1 +* \snippet trigmux/snippet/main.c snippet_Cy_TrigMux_PERI_ver1 * * For PERI_ver2: -* Step 1. Find the trigger group number in the Trigger Group Inputs section of the device +* Step 1. Find the trigger group number in the Trigger Group Inputs section of the device * configuration header file that corresponds to the output of the source peripheral block. -* For example, TRIG_IN_MUX_0_TCPWM0_TR_OVERFLOW0 (see \ref group_trigmux_in_enums) TrigMux -* input belongs to Trigger Group 0. It is the same TCPWM0 counter 0 overflow output +* For example, TRIG_IN_MUX_0_TCPWM0_TR_OVERFLOW0 (see \ref group_trigmux_in_enums) TrigMux +* input belongs to Trigger Group 0. It is the same TCPWM0 counter 0 overflow output * (as in the example for PERI_ver1). * -* Step 2. Find the same trigger group number in the Trigger Group Outputs section of the -* device configuration header file that corresponds to the trigger group number found in +* Step 2. Find the same trigger group number in the Trigger Group Outputs section of the +* device configuration header file that corresponds to the trigger group number found in * Step 1. Select the TrigMux output that can be connected to the destination peripheral block. -* For example, TRIG_OUT_MUX_0_PDMA0_TR_IN0 (see \ref group_trigmux_out_enums) means that the -* trigger multiplexer Output 0 of Trigger Group 0 can be connected to the DW0 channel 0 trigger +* For example, TRIG_OUT_MUX_0_PDMA0_TR_IN0 (see \ref group_trigmux_out_enums) means that the +* trigger multiplexer Output 0 of Trigger Group 0 can be connected to the DW0 channel 0 trigger * input (the same DMA channel as mentioned in the example for PERI_ver1). * * Step 3. Call Cy_TrigMux_Connect() API once: @@ -171,21 +171,26 @@ *
VersionChangesReason for Change
1.10.2Minor documentation updates.Documentation enhancement.
1.10.1Added header guards CY_IP_MXTCPWM.To enable the PDL compilation with wounded out IP blocks.
1.10Flattened the organization of the driver source code into the single +* Flattened the organization of the driver source code into the single * source directory and the single include directory. * Driver library directory-structure simplification.
Added register access layer. Use register access macros instead * of direct register access using dereferenced pointers.Makes register access device-independent, so that the PDL does +* Makes register access device-independent, so that the PDL does * not need to be recompiled for each supported part number.
* * +* +* +* +* +* * * * -* +* * * * * * * -* * @@ -193,7 +198,7 @@ * * -* * * @@ -204,7 +209,7 @@ * * * -* @@ -299,7 +304,7 @@ extern "C" { *****************************************************************************/ /** The TRIGMUX error codes. */ -typedef enum +typedef enum { CY_TRIGMUX_SUCCESS = 0x0UL, /**< Successful */ CY_TRIGMUX_BAD_PARAM = CY_TRIGMUX_ID | CY_PDL_STATUS_ERROR | 0x1UL, /**< One or more invalid parameters */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_usbfs_dev_drv.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_usbfs_dev_drv.h index ef485ccf9d..cd00a3f64c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_usbfs_dev_drv.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_usbfs_dev_drv.h @@ -1,12 +1,12 @@ /***************************************************************************//** * \file cy_usbfs_dev_drv.h -* \version 2.20 +* \version 2.20.1 * * Provides API declarations of the USBFS driver. * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -28,16 +28,16 @@ * \{ * The USBFS driver provides an API to interact with a fixed-function USB block. * -* The functions and other declarations used in this driver are in cy_usbfs_dev_drv.h. -* You can include cy_pdl.h (ModusToolbox only) to get access to all functions -* and declarations in the PDL. -* +* The functions and other declarations used in this driver are in cy_usbfs_dev_drv.h. +* You can include cy_pdl.h to get access to all functions +* and declarations in the PDL. +* * The USB block supports Host and Device modes of operation. This version of the * driver supports only Device mode. * * Features: * * Complies with USB Specification 2.0 -* * Supports full-speed peripheral device operation with a signaling bit +* * Supports full-speed peripheral device operation with a signaling bit * rate of 12 Mbps. * * Supports eight data endpoints and one control endpoint. * * Provides a shared 512-byte buffer for data endpoints. @@ -45,14 +45,14 @@ * * Supports four types of transfers: bulk, interrupt, isochronous, and control * * Supports bus- and self-powered configurations * * Supports USB suspend, resume, and remove wakeup. -* * Supports three types of logical transfer modes: +* * Supports three types of logical transfer modes: * * CPU (No DMA) mode (Mode 1). * * Manual DMA mode (Mode 2). * * Automatic DMA mode (Mode 3). -* * Supports the maximum packet size: +* * Supports the maximum packet size: * * 512 bytes using Mode 1 and Mode 2. * * 1023 bytes for isochronous transfer using Mode 3. -* * Provides integrated 22 Ohm USB termination resistors on D+ and D- lines, +* * Provides integrated 22 Ohm USB termination resistors on D+ and D- lines, * and 1.5 kOhm pull-up resistor on the D+ line. * * Supports USB 2.0 Link Power Management (LPM). * @@ -61,12 +61,12 @@ * \section group_usbfs_dev_drv_use_cases Common Use Cases ******************************************************************************** * -* The primary usage model for the USBFS driver is to provide a defined API -* interface to +* The primary usage model for the USBFS driver is to provide a defined API +* interface to * * USB Device Middleware component that works on top of it. \n -* The driver also provides an API interface for the application to implement the required -* functionality: +* The driver also provides an API interface for the application to implement the required +* functionality: * * \ref group_usbfs_dev_drv_callbacks * * \ref group_usbfs_dev_drv_low_power * * \ref group_usbfs_dev_drv_lpm @@ -75,86 +75,86 @@ ******************************************************************************** * \section group_usbfs_dev_drv_configuration Configuration Considerations ******************************************************************************** -* -* This section explains how to configure the USBFS driver and system resources to -* enable USB Device operation. The pointers to the populated \ref cy_stc_usbfs_dev_drv_config_t configuration +* +* This section explains how to configure the USBFS driver and system resources to +* enable USB Device operation. The pointers to the populated \ref cy_stc_usbfs_dev_drv_config_t configuration * structure and allocated context are passed in the middleware initialization. -* function Cy_USB_Dev_Init. After middleware initialization, it calls +* function Cy_USB_Dev_Init. After middleware initialization, it calls * \ref Cy_USBFS_Dev_Drv_Init to initialize the USBFS driver for Device operation. ******************************************************************************** * \subsection group_usbfs_dev_drv_config Configure Driver ******************************************************************************** -* -* To configure the USBFS driver in Device mode, the configuration structure -* \ref cy_stc_usbfs_dev_drv_config_t parameters must be populated. -* The configuration structure content significantly depends on the selected +* +* To configure the USBFS driver in Device mode, the configuration structure +* \ref cy_stc_usbfs_dev_drv_config_t parameters must be populated. +* The configuration structure content significantly depends on the selected * endpoints management mode parameter: * * * \ref CY_USBFS_DEV_DRV_EP_MANAGEMENT_CPU \n -* The epAccess, intrLevelSel and enableLpm must be provided. All -* other parameters are do not cares for this mode. Refer to section -* \ref group_usbfs_dev_drv_intr to get information about intrLevelSel +* The epAccess, intrLevelSel and enableLpm must be provided. All +* other parameters are do not cares for this mode. Refer to section +* \ref group_usbfs_dev_drv_intr to get information about intrLevelSel * configuration. * * \snippet usbfs/snippet/main.c snipped_Cy_USBFS_Dev_Drv_CfgCpu * * * \ref CY_USBFS_DEV_DRV_EP_MANAGEMENT_DMA \n -* To enable DMA operation, the DMA channels must be assigned for each endpoint -* to be used. Each DMA channel needs a single DMA descriptor to -* operate. The USBFS driver defines the DMA configuration structure -* \ref cy_stc_usbfs_dev_drv_dma_config_t to be populated for each DMA +* To enable DMA operation, the DMA channels must be assigned for each endpoint +* to be used. Each DMA channel needs a single DMA descriptor to +* operate. The USBFS driver defines the DMA configuration structure +* \ref cy_stc_usbfs_dev_drv_dma_config_t to be populated for each DMA * channel. -* The code example below provides an initialized USBFS driver DMA configuration +* The code example below provides an initialized USBFS driver DMA configuration * structure: -* +* * \snippet usbfs/snippet/main.c snipped_Cy_USBFS_Dev_Drv_CfgDma_DmaInit * -* The pointers to the DMA configuration structure are required into the +* The pointers to the DMA configuration structure are required into the * \ref cy_stc_usbfs_dev_drv_config_t USBFS driver configuration structure -* to allow the USBFS driver to use DMA channels for used endpoints. -* The dmaConfig[0] field expects a pointer to the DMA configuration for -* data endpoint 1, the dmaConfig[1] field pointer to the DMA configuration +* to allow the USBFS driver to use DMA channels for used endpoints. +* The dmaConfig[0] field expects a pointer to the DMA configuration for +* data endpoint 1, the dmaConfig[1] field pointer to the DMA configuration * for data endpoint 2, and so on up to data endpoint 8. -* The code example below provides an initialized USBFS driver configuration +* The code example below provides an initialized USBFS driver configuration * structure which uses endpoint 1: * * \snippet usbfs/snippet/main.c snipped_Cy_USBFS_Dev_Drv_CfgDma -* +* * * \ref CY_USBFS_DEV_DRV_EP_MANAGEMENT_DMA_AUTO \n -* DMA Automatic mode needs a DMA channels configuration similar to the described -* above. But it also requires one more DMA descriptor for each DMA channel and +* DMA Automatic mode needs a DMA channels configuration similar to the described +* above. But it also requires one more DMA descriptor for each DMA channel and * DMA output trigger multiplexer. Refer to the \ref group_usbfs_dev_drv_dma section, * for more detail about the trigger multiplexer . -* The code example below provides an initialized USBFS driver DMA configuration +* The code example below provides an initialized USBFS driver DMA configuration * structure: -* +* * \snippet usbfs/snippet/main.c snipped_Cy_USBFS_Dev_Drv_CfgDmaAuto_DmaInit * * The driver requires a buffer for data endpoints to operate. This buffer must be -* allocated by the user. The buffer size is equal to the sum of all used -* endpoints maximum packet sizes. If an endpoint belongs to more than -* one alternate setting, select the greatest maximum packet size for this -* endpoint. The driver configuration structure \ref cy_stc_usbfs_dev_drv_config_t +* allocated by the user. The buffer size is equal to the sum of all used +* endpoints maximum packet sizes. If an endpoint belongs to more than +* one alternate setting, select the greatest maximum packet size for this +* endpoint. The driver configuration structure \ref cy_stc_usbfs_dev_drv_config_t * parameters epBuffer and epBufferSize pass the buffer to the driver. * -* The code example below provides an initialized USBFS driver configuration -* structure that uses data endpoint 1 with a maximum packet size of 63 bytes and +* The code example below provides an initialized USBFS driver configuration +* structure that uses data endpoint 1 with a maximum packet size of 63 bytes and * set 16-bit access: -* +* * \snippet usbfs/snippet/main.c snipped_Cy_USBFS_Dev_Drv_CfgDmaAuto * * * \note -* The endpoint buffer allocation depends on the access type used: 8-bit or 16-bit. +* The endpoint buffer allocation depends on the access type used: 8-bit or 16-bit. * Refer to \ref group_usbfs_dev_drv_ep_management_buf_access for more information. * ******************************************************************************** * \subsection group_usbfs_dev_drv_pins Assign and Configure Pins ******************************************************************************** * -* Only dedicated USB pins can be used for USB operation. Keep the default -* USB pins configuration because after the USBFS driver initializes, the +* Only dedicated USB pins can be used for USB operation. Keep the default +* USB pins configuration because after the USBFS driver initializes, the * USB block takes control over the pins and drives them properly. * ******************************************************************************** @@ -162,26 +162,26 @@ ******************************************************************************** * * The USB hardware block requires two clock sources for operation: -* * Clk_HF3 (USB clock) must be 48 MHz. The accuracy of the USB clock must be -* within -/+ 0.25%. Note that Clk_HF3 has an integer divider so the input -* clock can be a multiple of 48. The valid options to get an internal USB +* * Clk_HF3 (USB clock) must be 48 MHz. The accuracy of the USB clock must be +* within -/+ 0.25%. Note that Clk_HF3 has an integer divider so the input +* clock can be a multiple of 48. The valid options to get an internal USB * clock are PLL or ECO.\n -* The typical configuration is: the IMO output is used by the PLL to -* generate Clk_HF3 (USB clock). To meet USB clock accuracy requirements -* the IMO must be trimmed with USB SOF signal. Therefore, the driver +* The typical configuration is: the IMO output is used by the PLL to +* generate Clk_HF3 (USB clock). To meet USB clock accuracy requirements +* the IMO must be trimmed with USB SOF signal. Therefore, the driver * \ref Cy_USBFS_Dev_Drv_Init function enables the IMO trim from USB. * -* * Divided Clk_Peri clock (PCLK_USB_CLOCK_DEV_BRS) equal to 100 kHz -* used to detect a Bus Reset event. Use one of the 8-bit or 16-bit dividers +* * Divided Clk_Peri clock (PCLK_USB_CLOCK_DEV_BRS) equal to 100 kHz +* used to detect a Bus Reset event. Use one of the 8-bit or 16-bit dividers * to provide required clock frequency. * -* The code example below shows the connection source path 1 -* (which expected provide 48 MHz -/+ 0.25% clock) to Clk_HF3 and Bus Reset clock +* The code example below shows the connection source path 1 +* (which expected provide 48 MHz -/+ 0.25% clock) to Clk_HF3 and Bus Reset clock * (Clk_Peri assumed to be 50 MHz): -* +* * \snippet usbfs/snippet/main.c snipped_Cy_USBFS_Dev_Drv_ClockInit * -* Refer to \ref group_sysclk driver API for more detail about clock +* Refer to \ref group_sysclk driver API for more detail about clock * configuration. * * The FLL (Clock Path 0) with ECO also can be used as an alternative USB source @@ -195,21 +195,21 @@ * \subsection group_usbfs_dev_drv_dma Assign and Route DMA Channels ******************************************************************************** * -* The USBFS driver requires a DMA controller to operate in DMA Manual and Automatic modes. -* The USB hardware block supports the DMA request and feedback lines for each -* data endpoint. Therefore, up to eight DMA channels serve eight data endpoints. -* The connection between the USB block and the DMA channels is set using the trigger -* muxes infrastructure. The USB block output DMA request line is connected to -* the DMA channel trigger input. This allows the USB block to request a DMA transfer. -* The DMA completion output is connected to the USB block burst end input. -* This allows the USB block to get notification that a DMA transfer has been completed -* and a next DMA request can be sent. The USBFS driver DMA configuration -* structure requires the outTrigMux field to provide the trigger mux that +* The USBFS driver requires a DMA controller to operate in DMA Manual and Automatic modes. +* The USB hardware block supports the DMA request and feedback lines for each +* data endpoint. Therefore, up to eight DMA channels serve eight data endpoints. +* The connection between the USB block and the DMA channels is set using the trigger +* muxes infrastructure. The USB block output DMA request line is connected to +* the DMA channel trigger input. This allows the USB block to request a DMA transfer. +* The DMA completion output is connected to the USB block burst end input. +* This allows the USB block to get notification that a DMA transfer has been completed +* and a next DMA request can be sent. The USBFS driver DMA configuration +* structure requires the outTrigMux field to provide the trigger mux that * performs DMA completion and USB block burst end connection. * * Refer to \ref group_trigmux for more detail on the routing capabilities. -* -* The code examples below shows a connection DMA channel and USB block and the define +* +* The code examples below shows a connection DMA channel and USB block and the define * for outTrigMux field initialization for the CY8C6xx6 or CY8C6xx7 devices. * * \snippet usbfs/snippet/main.c snipped_Cy_USBFS_Dev_Drv_DmaConnect @@ -219,93 +219,93 @@ ******************************************************************************** * * The interrupts are mandatory for the USBFS driver operation. -* The USBFS block provides multiple interrupt sources to be assigned to -* trigger one of the three interrupts: Low, Medium, or High. This allows to +* The USBFS block provides multiple interrupt sources to be assigned to +* trigger one of the three interrupts: Low, Medium, or High. This allows to * assign different priority to the interrupt sources handling. -* The \ref cy_stc_usbfs_dev_drv_config_t structure provides the -* intrLevelSel field which initializes the INTR_LVL_SEL +* The \ref cy_stc_usbfs_dev_drv_config_t structure provides the +* intrLevelSel field which initializes the INTR_LVL_SEL * register. This register configures which interrupt the interrupt source will trigger. -* +* * \note -* The interrupt name (Low, Medium, or High) does not specify the interrupt +* The interrupt name (Low, Medium, or High) does not specify the interrupt * priority. The interrupt priority is configured in NVIC. * -* The recommended/default configuration is: +* The recommended/default configuration is: * * Interrupt Low: Bus Reset, Control Endpoint and SOF. -* * Interrupt Medium: Endpoint 1-8 Completion. -* * Interrupt High: Arbiter and LPM. +* * Interrupt Medium: Endpoint 1-8 Completion. +* * Interrupt High: Arbiter and LPM. * * However, the final configuration must be defined by the application. * * \snippet usbfs/snippet/main.c snipped_Cy_USBFS_Dev_Drv_UserLvlSel * -* The \ref Cy_USBFS_Dev_Drv_Interrupt function must be called in the interrupt -* handler for the selected USB block instance. Note that -* the \ref Cy_USBFS_Dev_Drv_Interrupt has the parameter intrCause that -* must be assigned by calling the appropriate interrupt cause function: -* * \ref Cy_USBFS_Dev_Drv_GetInterruptCauseHi -* * \ref Cy_USBFS_Dev_Drv_GetInterruptCauseMed +* The \ref Cy_USBFS_Dev_Drv_Interrupt function must be called in the interrupt +* handler for the selected USB block instance. Note that +* the \ref Cy_USBFS_Dev_Drv_Interrupt has the parameter intrCause that +* must be assigned by calling the appropriate interrupt cause function: +* * \ref Cy_USBFS_Dev_Drv_GetInterruptCauseHi +* * \ref Cy_USBFS_Dev_Drv_GetInterruptCauseMed * * \ref Cy_USBFS_Dev_Drv_GetInterruptCauseLo * * \snippet usbfs/snippet/main.c snipped_Cy_USBFS_Dev_Drv_IntrHandlers * -* Finally, the interrupts must be configured and interrupt handler routines -* hook up to NVIC. The code below assigns the interrupt priorities accordingly +* Finally, the interrupts must be configured and interrupt handler routines +* hook up to NVIC. The code below assigns the interrupt priorities accordingly * to interrupt names. The priorities among the USBFS interrupts are as follows: * High - the greatest; Medium - the middle; Low - the lowest. * * \note -* For proper operation in Manual DMA mode (Mode 2) the Arbiter interrupt source -* must be assigned to interrupt which priority is greater than interrupt +* For proper operation in Manual DMA mode (Mode 2) the Arbiter interrupt source +* must be assigned to interrupt which priority is greater than interrupt * triggered by Data Endpoint 1-8 Completion interrupt sources. \n * For Automatic DMA mode (Mode 3) the rule above is recommend to follow. * * \snippet usbfs/snippet/main.c snipped_Cy_USBFS_Dev_Drv_IntrCfg * \snippet usbfs/snippet/main.c snipped_Cy_USBFS_Dev_Drv_IntrCfgHook -* +* ******************************************************************************** * \section group_usbfs_dev_drv_ep_management Endpoint Buffer Management Modes ******************************************************************************** -* +* * The USBFS hardware block supports three endpoint buffer management modes: * CPU (No DMA) mode (Mode 1), Manual DMA mode (Mode 2), and Automatic DMA mode (Mode 3). * These modes are listed using enum \ref cy_en_usbfs_dev_drv_ep_management_mode_t. -* The following sub-sections provide more information about the endpoint buffer +* The following sub-sections provide more information about the endpoint buffer * management. * ******************************************************************************** * \subsection group_usbfs_dev_drv_ep_management_buff Hardware buffers ******************************************************************************** * -* The USBFS block has a 512-byte hardware buffer that is divided between all -* data endpoints used in the selected configuration. How the hardware buffer +* The USBFS block has a 512-byte hardware buffer that is divided between all +* data endpoints used in the selected configuration. How the hardware buffer * is divided between endpoints depends on the selected endpoint buffer management * modes: -* +* * * \ref group_usbfs_dev_drv_ep_management_mode1 and \ref group_usbfs_dev_drv_ep_management_mode2 -* Each data endpoint consumes space (number of bytes) in the hardware buffer -* that is equal to the endpoint maximum packet size defined in the endpoint +* Each data endpoint consumes space (number of bytes) in the hardware buffer +* that is equal to the endpoint maximum packet size defined in the endpoint * descriptor. The total space consumed by all endpoints is restricted -* by the size of hardware buffer (512 bytes). When an endpoint appears in the -* different alternate settings and has a different maximum packet size, the greatest -* value is selected to the allocate space of the endpoint in the -* hardware buffer. This is to ensure correct USB Device operation when interface -* alternate settings are changed. Note that endpoint can consume extra byte in -* the hardware buffer when 16-bit access is used (See \ref +* by the size of hardware buffer (512 bytes). When an endpoint appears in the +* different alternate settings and has a different maximum packet size, the greatest +* value is selected to the allocate space of the endpoint in the +* hardware buffer. This is to ensure correct USB Device operation when interface +* alternate settings are changed. Note that endpoint can consume extra byte in +* the hardware buffer when 16-bit access is used (See \ref * group_usbfs_dev_drv_ep_management_buf_access for more information). * * * \ref group_usbfs_dev_drv_ep_management_mode3 -* Each data endpoint consumes 32 bytes in the hardware buffer (if all eight -* endpoints are used, the consumed buffer space is 32 * 8 = 256 byte). -* This buffer is called "dedicated endpoint buffer". It acts as an endpoint -* FIFO. The remaining space (256 bytes, if all eight endpoints are -* used) in the hardware buffer is used by any endpoint that currently -* communicates. This part of the buffer is called "common area". This hardware -* buffer configuration gives a sufficient dedicated buffer size for each used -* endpoint and common area for operation. The total space consumed by all +* Each data endpoint consumes 32 bytes in the hardware buffer (if all eight +* endpoints are used, the consumed buffer space is 32 * 8 = 256 byte). +* This buffer is called "dedicated endpoint buffer". It acts as an endpoint +* FIFO. The remaining space (256 bytes, if all eight endpoints are +* used) in the hardware buffer is used by any endpoint that currently +* communicates. This part of the buffer is called "common area". This hardware +* buffer configuration gives a sufficient dedicated buffer size for each used +* endpoint and common area for operation. The total space consumed by all * endpoints is not restricted by the size of the hardware buffer. * -* To access the hardware buffer, the endpoint data register is read or written by +* To access the hardware buffer, the endpoint data register is read or written by * CPU or DMA. On each read or write, buffer pointers are updated to access * a next data element. * @@ -314,48 +314,48 @@ ******************************************************************************** * * The USBFS block provides two sets of data registers: 8-bit and 16-bit. Either -* the 8-bit endpoint data register or the 16-bit endpoint data register can -* be used to read/write to the endpoint buffer. The buffer access is controlled -* by the epAccess field of the driver configuration structure -* \ref cy_stc_usbfs_dev_drv_config_t. -* The endpoint hardware buffer and SRAM buffer must be allocated using the +* the 8-bit endpoint data register or the 16-bit endpoint data register can +* be used to read/write to the endpoint buffer. The buffer access is controlled +* by the epAccess field of the driver configuration structure +* \ref cy_stc_usbfs_dev_drv_config_t. +* The endpoint hardware buffer and SRAM buffer must be allocated using the * rules below when the 16-bit access is used: -* * The buffer size must be even. If the endpoint maximum packet size is odd +* * The buffer size must be even. If the endpoint maximum packet size is odd * the allocated buffer size must be equal to (maximum packet size + 1). * * The buffer must be aligned to the 2-byte boundary. * -* The driver provides the \ref CY_USBFS_DEV_DRV_ALLOC_ENDPOINT_BUFFER macro that -* applies the rules above to allocate the SRAM buffer for an endpoint. This macro -* should be used by application to hide configuration differences. +* The driver provides the \ref CY_USBFS_DEV_DRV_ALLOC_ENDPOINT_BUFFER macro that +* applies the rules above to allocate the SRAM buffer for an endpoint. This macro +* should be used by application to hide configuration differences. * However, in this case the application must ignore extra bytes in the buffer. * Alternately, apply the rules above only for the 16-bits access type configuration. * -* The driver firmware allocates an endpoint hardware buffer (dividing hardware buffer -* between utilized endpoints). Therefore, for \ref group_usbfs_dev_drv_ep_management_mode1 -* and \ref group_usbfs_dev_drv_ep_management_mode2, an endpoint whose -* maximum packet size is odd, consumes an extra byte in the hardware buffer -* when the 16-bit access is used. This is not applicable for \ref group_usbfs_dev_drv_ep_management_mode3 +* The driver firmware allocates an endpoint hardware buffer (dividing hardware buffer +* between utilized endpoints). Therefore, for \ref group_usbfs_dev_drv_ep_management_mode1 +* and \ref group_usbfs_dev_drv_ep_management_mode2, an endpoint whose +* maximum packet size is odd, consumes an extra byte in the hardware buffer +* when the 16-bit access is used. This is not applicable for \ref group_usbfs_dev_drv_ep_management_mode3 * because endpoints dedicated buffer are even and aligned. * -* In addition, to operate in \ref group_usbfs_dev_drv_ep_management_mode3, -* the driver needs an internal SRAM buffer for endpoints. The buffer size is a -* sum of all endpoint buffers. When the 16-bit access is used, each endpoint buffer -* must be allocated using the rules above. The driver configuration structure -* \ref cy_stc_usbfs_dev_drv_config_t has epBuffer and epBufferSize fields +* In addition, to operate in \ref group_usbfs_dev_drv_ep_management_mode3, +* the driver needs an internal SRAM buffer for endpoints. The buffer size is a +* sum of all endpoint buffers. When the 16-bit access is used, each endpoint buffer +* must be allocated using the rules above. The driver configuration structure +* \ref cy_stc_usbfs_dev_drv_config_t has epBuffer and epBufferSize fields * to pass the allocated buffer to the driver. \n * For example: the USB Device uses three data endpoints whose max packets are -* 63 bytes, 63 bytes, and 8 bytes. The endpoints buffer for the driver must be +* 63 bytes, 63 bytes, and 8 bytes. The endpoints buffer for the driver must be * allocated as follows: * * 8-bits: uint8_t endpointsBuffer[63 + 63 + 8]; -* * 16-bits: uint8_t endpointsBuffer[(63+1) + (63+1) + 8] CY_ALLIGN(2); or +* * 16-bits: uint8_t endpointsBuffer[(63+1) + (63+1) + 8] CY_ALLIGN(2); or * CY_USBFS_DEV_DRV_ALLOC_ENDPOINT_BUFFER((63+1) + (63+1) + 8); -* +* ******************************************************************************** * \subsection group_usbfs_dev_drv_ep_management_mode1 CPU mode (Mode 1) ******************************************************************************** * -* CPU handles data transfers between the user-provided SRAM endpoint-buffer -* and the USB block hardware-buffer when \ref Cy_USBFS_Dev_Drv_ReadOutEndpoint +* CPU handles data transfers between the user-provided SRAM endpoint-buffer +* and the USB block hardware-buffer when \ref Cy_USBFS_Dev_Drv_ReadOutEndpoint * or \ref Cy_USBFS_Dev_Drv_LoadInEndpoint is called. * * \image html usbfs_ep_mngmnt_mode1.png @@ -364,9 +364,9 @@ * \subsection group_usbfs_dev_drv_ep_management_mode2 Manual DMA mode (Mode 2) ******************************************************************************** * -* DMA handles data transfers between the user-provided SRAM endpoint -* buffer and the USB block hardware buffer. The DMA request is issued by CPU -* to execute a data transfer when \ref Cy_USBFS_Dev_Drv_ReadOutEndpoint or +* DMA handles data transfers between the user-provided SRAM endpoint +* buffer and the USB block hardware buffer. The DMA request is issued by CPU +* to execute a data transfer when \ref Cy_USBFS_Dev_Drv_ReadOutEndpoint or * \ref Cy_USBFS_Dev_Drv_LoadInEndpoint. * * \image html usbfs_ep_mngmnt_mode2.png @@ -374,31 +374,31 @@ ******************************************************************************** * \subsection group_usbfs_dev_drv_ep_management_mode3 Automatic DMA mode (Mode 3) ******************************************************************************** -* -* DMA handles data transfers between the driver SRAM endpoints buffer and -* the USB block hardware buffer. The USB block generates DMA requests -* automatically. When USB transfer starts, the USB block triggers DMA -* requests to transfer data between the driver endpoint buffer and the hardware -* buffer until transfer completion. The common area acts as a FIFO to (and keeps -* data that does not fit into) the endpoint dedicated buffer. For IN endpoints, -* the dedicated buffer is pre-loaded before enabling USB Host access to the endpoint. -* This gives time for the DMA to provide remaining data before underflow -* occurs. The USB block hardware has a feedback connection with the DMA -* and does not issue new DMA request until it receives notification that the -* previous DMA transfer completed. -* When the \ref Cy_USBFS_Dev_Drv_ReadOutEndpoint or \ref Cy_USBFS_Dev_Drv_LoadInEndpoint +* +* DMA handles data transfers between the driver SRAM endpoints buffer and +* the USB block hardware buffer. The USB block generates DMA requests +* automatically. When USB transfer starts, the USB block triggers DMA +* requests to transfer data between the driver endpoint buffer and the hardware +* buffer until transfer completion. The common area acts as a FIFO to (and keeps +* data that does not fit into) the endpoint dedicated buffer. For IN endpoints, +* the dedicated buffer is pre-loaded before enabling USB Host access to the endpoint. +* This gives time for the DMA to provide remaining data before underflow +* occurs. The USB block hardware has a feedback connection with the DMA +* and does not issue new DMA request until it receives notification that the +* previous DMA transfer completed. +* When the \ref Cy_USBFS_Dev_Drv_ReadOutEndpoint or \ref Cy_USBFS_Dev_Drv_LoadInEndpoint * function is called, the memcpy function is used to copy data from/into the * driver endpoints buffer to the user-provided endpoint buffer. -* The driver provides the \ref Cy_USBFS_Dev_Drv_OverwriteMemcpy function to +* The driver provides the \ref Cy_USBFS_Dev_Drv_OverwriteMemcpy function to * replace memcpy function by one that has been custom implemented (the DMA can be used for data copy). -* +* * \image html usbfs_ep_mngmnt_mode3.png * -* \warning -* When DMA data transfer is not fast enough, an overflow or underflow -* interrupt triggers for the impacted endpoint. This must never happen -* because this error condition indicates a system failure with no recovery. -* To fix this, get the DMA channel assigned to this endpoint greater priority or +* \warning +* When DMA data transfer is not fast enough, an overflow or underflow +* interrupt triggers for the impacted endpoint. This must never happen +* because this error condition indicates a system failure with no recovery. +* To fix this, get the DMA channel assigned to this endpoint greater priority or * increase the clock the DMA operates at. * ******************************************************************************** @@ -406,170 +406,170 @@ ******************************************************************************** * * The driver provides the following callbacks that can be used by the application: -* 1. Data endpoint 1-8 completion. This callback is invoked when the USB Host -* completed communication with the endpoint. For IN endpoints, it means that data has -* been read by the USB Host. For OUT endpoints, it means that data has been written -* by the USB Host. Call \ref Cy_USBFS_Dev_Drv_RegisterEndpointCallback to +* 1. Data endpoint 1-8 completion. This callback is invoked when the USB Host +* completed communication with the endpoint. For IN endpoints, it means that data has +* been read by the USB Host. For OUT endpoints, it means that data has been written +* by the USB Host. Call \ref Cy_USBFS_Dev_Drv_RegisterEndpointCallback to * register callback function. -* -* 2. Start Of Frame packet received. This can be used in the application to -* synchronize with SOF packets or for monitoring the bus activity. -* Call \ref Cy_USBFS_Dev_Drv_RegisterSofCallback to register callback function. -* -* 3. LPM (Link Power Management) packet received. This must be used to implement -* LPM power optimization. Call \ref Cy_USBFS_Dev_Drv_RegisterLpmCallback to +* +* 2. Start Of Frame packet received. This can be used in the application to +* synchronize with SOF packets or for monitoring the bus activity. +* Call \ref Cy_USBFS_Dev_Drv_RegisterSofCallback to register callback function. +* +* 3. LPM (Link Power Management) packet received. This must be used to implement +* LPM power optimization. Call \ref Cy_USBFS_Dev_Drv_RegisterLpmCallback to * register callback function. -* -* Also, the driver provides callbacks for a Bus Reset event and Control Endpoint 0 -* communication events (setup packet, in packet, out packet). But these -* callbacks are used by middleware and must not be used by the application directly. +* +* Also, the driver provides callbacks for a Bus Reset event and Control Endpoint 0 +* communication events (setup packet, in packet, out packet). But these +* callbacks are used by middleware and must not be used by the application directly. * The middleware provides appropriate hooks for these events. * ******************************************************************************** * \section group_usbfs_dev_drv_vbus VBUS Detection ******************************************************************************** * -* The USB specification requires that no device supplies current on VBUS at its -* upstream facing port at any time. To meet this requirement, the device must -* monitors for the presence or absence of VBUS and removes power from the Dp/Dm -* pull-up resistor if VBUS is absent. The USBFS driver does not provide any -* support of VBUS monitoring or detection. The application firmware must implement -* the required functionality using a VDDUSB power pad or GPIO. Refer to the -* Universal Serial Bus (USB) Device Mode section, sub-section VBUS Detection +* The USB specification requires that no device supplies current on VBUS at its +* upstream facing port at any time. To meet this requirement, the device must +* monitors for the presence or absence of VBUS and removes power from the Dp/Dm +* pull-up resistor if VBUS is absent. The USBFS driver does not provide any +* support of VBUS monitoring or detection. The application firmware must implement +* the required functionality using a VDDUSB power pad or GPIO. Refer to the +* Universal Serial Bus (USB) Device Mode section, sub-section VBUS Detection * in the technical reference manual (TRM). -* -* Connect the VBUS through a resistive network when the -* regular GPIO is used for VBUS detection to save the pin from voltage picks on VBUS, +* +* Connect the VBUS through a resistive network when the +* regular GPIO is used for VBUS detection to save the pin from voltage picks on VBUS, * or use GPIO tolerant over the voltage. An example schematic is shown below. -* +* * \image html usbfs_vbus_connect_schem.png -* -* \note Power is removed when the USB cable is removed from the USB Host -* for bus-powered USB Device. Therefore, such a USB Device complies with +* +* \note Power is removed when the USB cable is removed from the USB Host +* for bus-powered USB Device. Therefore, such a USB Device complies with * specification requirement above. * ******************************************************************************** * \section group_usbfs_dev_drv_low_power Low Power Support ******************************************************************************** * -* The USBFS driver supports the USB Suspend, Resume, and Remote Wakeup functionality. -* This functionality is tightly related with the user application. The USBFS -* driver provides only the API interface which helps the user achieve the desired -* low-power behavior. The additional processing is required from the user application. +* The USBFS driver supports the USB Suspend, Resume, and Remote Wakeup functionality. +* This functionality is tightly related with the user application. The USBFS +* driver provides only the API interface which helps the user achieve the desired +* low-power behavior. The additional processing is required from the user application. * The description of application processing is provided below. * * Normally, the USB Host sends an SOF packet every 1 ms (at full speed), and this -* keeps the USB Device awake. The USB Host suspends the USB Device by not -* sending anything to the USB Device for 3 ms. To recognize this condition, the bus -* activity must be checked. This can be done using the \ref Cy_USBFS_Dev_Drv_CheckActivity -* function or by monitoring the SOF interrupt. A suspended device may draw no +* keeps the USB Device awake. The USB Host suspends the USB Device by not +* sending anything to the USB Device for 3 ms. To recognize this condition, the bus +* activity must be checked. This can be done using the \ref Cy_USBFS_Dev_Drv_CheckActivity +* function or by monitoring the SOF interrupt. A suspended device may draw no * more than 0.5 mA from VBUS. Therefore, put the device into low-power -* mode to consume less current. -* The \ref Cy_USBFS_Dev_Drv_Suspend function must be called before entering -* low-power mode. When the USB Host wants to wake the device after a suspend, -* it does so by reversing the polarity of the signal on the data lines for at -* least 20 ms. The resume signaling is completed with a low-speed end-of-packet -* signal. The USB block is disabled during Deep Sleep or Hibernate low-power modes. -* To exit a low-power mode when USB Host drives resume, a falling edge interrupt -* on Dp must be configured before entering these modes. The \ref Cy_USBFS_Dev_Drv_Resume -* function must be called after exiting the low-power mode. To resume communication with -* the USB Host, the data endpoints must be managed: the OUT endpoints must be +* mode to consume less current. +* The \ref Cy_USBFS_Dev_Drv_Suspend function must be called before entering +* low-power mode. When the USB Host wants to wake the device after a suspend, +* it does so by reversing the polarity of the signal on the data lines for at +* least 20 ms. The resume signaling is completed with a low-speed end-of-packet +* signal. The USB block is disabled during Deep Sleep or Hibernate low-power modes. +* To exit a low-power mode when USB Host drives resume, a falling edge interrupt +* on Dp must be configured before entering these modes. The \ref Cy_USBFS_Dev_Drv_Resume +* function must be called after exiting the low-power mode. To resume communication with +* the USB Host, the data endpoints must be managed: the OUT endpoints must be * enabled and IN endpoints must be loaded with data. -* -* \note After entering low-power mode, the data which was left in the IN or OUT -* endpoint buffers is not restored after the device's wake-up and is lost. -* Therefore, it must be stored in the SRAM for OUT endpoint or read by the Host for +* +* \note After entering low-power mode, the data which was left in the IN or OUT +* endpoint buffers is not restored after the device's wake-up and is lost. +* Therefore, it must be stored in the SRAM for OUT endpoint or read by the Host for * the IN endpoint before entering Low-power mode. * -* If the USB Device supports remote wakeup functionality, the application has -* to use middleware function Cy_USB_Dev_IsRemoteWakeupEnabled to determine whether -* remote wakeup was enabled by the USB Host. When the device is suspended and -* it determines the conditions to initiate a remote wakeup are met, +* If the USB Device supports remote wakeup functionality, the application has +* to use middleware function Cy_USB_Dev_IsRemoteWakeupEnabled to determine whether +* remote wakeup was enabled by the USB Host. When the device is suspended and +* it determines the conditions to initiate a remote wakeup are met, * the application must call the \ref Cy_USBFS_Dev_Drv_Force -* function to force the appropriate J and K states onto the USB bus, signaling a -* remote wakeup condition. Note that \ref Cy_USBFS_Dev_Drv_Resume must be called +* function to force the appropriate J and K states onto the USB bus, signaling a +* remote wakeup condition. Note that \ref Cy_USBFS_Dev_Drv_Resume must be called * first to restore the condition. -* +* ******************************************************************************** * \section group_usbfs_dev_drv_lpm Link Power Management (LPM) ******************************************************************************** * -* Link Power Management is a USB low-power mode feature that provides more -* flexibility in terms of features than the existing resume mode. This feature -* is similar to the existing Suspend/Resume, but has transitional latencies of -* tens of microseconds between power states (instead of 3 to greater than 20 +* Link Power Management is a USB low-power mode feature that provides more +* flexibility in terms of features than the existing resume mode. This feature +* is similar to the existing Suspend/Resume, but has transitional latencies of +* tens of microseconds between power states (instead of 3 to greater than 20 * millisecond latencies of the USB 2.0 Suspend/Resume). -* -* USB2.0 Power states are re-arranged as below with the introduction of LPM. +* +* USB2.0 Power states are re-arranged as below with the introduction of LPM. * The existing power states are re-named with LPM: -* * L0 (On) -* * L1 (Sleep) -- Newly Introduced State in LPM -* * L2 (Suspend) +* * L0 (On) +* * L1 (Sleep) -- Newly Introduced State in LPM +* * L2 (Suspend) * * L3 (Powered-Off) -* +* * LPM state transitions between is shown below: * * \image html usbfs_lpm_state_transition.png -* -* For example, a USB Host must transition a link from L1 (Sleep) to L0 before +* +* For example, a USB Host must transition a link from L1 (Sleep) to L0 before * transitioning it to L2 (Suspend), and similarly when transitioning from L2 to L1. -* -* When a USB Host is ready to transition a USB Device from L0 to a deeper power -* savings state, it issues an LPM transaction to the USB Device. The USB Device -* function responds with an ACK if it is ready to make the transition or a NYET -* (Not Yet) if it is not ready (usually because it is has data pending for the -* USB Host). A USB Device will transmit a STALL handshake if it does not support -* the requested link state. If the USB Device detects errors in either of the -* token packets or does not understand the protocol extension transaction, +* +* When a USB Host is ready to transition a USB Device from L0 to a deeper power +* savings state, it issues an LPM transaction to the USB Device. The USB Device +* function responds with an ACK if it is ready to make the transition or a NYET +* (Not Yet) if it is not ready (usually because it is has data pending for the +* USB Host). A USB Device will transmit a STALL handshake if it does not support +* the requested link state. If the USB Device detects errors in either of the +* token packets or does not understand the protocol extension transaction, * no handshake is returned. * * \image html usbfs_lpm_responses.png -* -* After USB Device is initialized, the LPM transaction is to be acknowledged (ACKed) -* meaning that the device is ready to enter the requested low-power mode. To override this +* +* After USB Device is initialized, the LPM transaction is to be acknowledged (ACKed) +* meaning that the device is ready to enter the requested low-power mode. To override this * behavior, use \ref Cy_USBFS_Dev_Drv_Lpm_SetResponse. \n -* -* The USB block provides an interrupt source to define that an LPM transaction was -* received and acknowledged (ACKed). Use the \ref Cy_USBFS_Dev_Drv_RegisterLpmCallback -* function to register the application level callback function to serve the LPM +* +* The USB block provides an interrupt source to define that an LPM transaction was +* received and acknowledged (ACKed). Use the \ref Cy_USBFS_Dev_Drv_RegisterLpmCallback +* function to register the application level callback function to serve the LPM * transaction. The callback function can notify the application about an LPM transaction -* and can use \ref Cy_USBFS_Dev_Drv_Lpm_GetBeslValue read to read Best Effort Service -* Latency (BESL) values provided as part of an LPM transaction. The BESL value -* indicates the amount of time from the start of a resume to when the USB Host -* attempts to begin issuing transactions to the USB Device. The +* and can use \ref Cy_USBFS_Dev_Drv_Lpm_GetBeslValue read to read Best Effort Service +* Latency (BESL) values provided as part of an LPM transaction. The BESL value +* indicates the amount of time from the start of a resume to when the USB Host +* attempts to begin issuing transactions to the USB Device. The * application must use the value BESL to decide which low-power mode is entered * to meet wakeup timing. The LPM transaction also contains the field that allows a -* remote to wake up. Use \ref Cy_USBFS_Dev_Drv_Lpm_RemoteWakeUpAllowed to get its +* remote to wake up. Use \ref Cy_USBFS_Dev_Drv_Lpm_RemoteWakeUpAllowed to get its * value. -* -* LPM related USB 2.0 Extension Descriptor provides attributes fields named +* +* LPM related USB 2.0 Extension Descriptor provides attributes fields named * baseline BESL and deep BESL to provide a range of values for different low-power -* optimization. The recommended use of these fields is that the -* baseline BESL field will have a value less than the deep BESL field. The -* expected use is the baseline BESL value communicates a nominal power savings -* design point and the deep BESL value communicates a significant power saving +* optimization. The recommended use of these fields is that the +* baseline BESL field will have a value less than the deep BESL field. The +* expected use is the baseline BESL value communicates a nominal power savings +* design point and the deep BESL value communicates a significant power saving * design point. -* For example, when the received BESL is less than baseline BESL, leave the device in -* Active mode. When it is between baseline BESL and deep BESL, put the device into -* Deep Sleep mode. When it is greater than deep BESL, put the device into +* For example, when the received BESL is less than baseline BESL, leave the device in +* Active mode. When it is between baseline BESL and deep BESL, put the device into +* Deep Sleep mode. When it is greater than deep BESL, put the device into * Hibernate mode. -* -* \note -* The driver implements the USB Full-Speed device which does not support the LPM +* +* \note +* The driver implements the USB Full-Speed device which does not support the LPM * NYET response. * -* \note -* The device will restart after Hibernate mode and the USB Device must -* be initialized at the application level. Call the initialization functions -* instead of \ref Cy_USBFS_Dev_Drv_Resume. The application must ensure that -* the device will resume within the time defined in the BESL value of LPM request. +* \note +* The device will restart after Hibernate mode and the USB Device must +* be initialized at the application level. Call the initialization functions +* instead of \ref Cy_USBFS_Dev_Drv_Resume. The application must ensure that +* the device will resume within the time defined in the BESL value of LPM request. * ******************************************************************************** * \section group_usbfs_drv_more_information More Information ******************************************************************************** -* -* For more detail on the USB Full-Speed Device peripheral, refer to the -* section Universal Serial Bus (USB) Device Mode in the technical reference +* +* For more detail on the USB Full-Speed Device peripheral, refer to the +* section Universal Serial Bus (USB) Device Mode in the technical reference * manual (TRM). * ******************************************************************************** @@ -588,11 +588,11 @@ * * -* * * @@ -601,11 +601,11 @@ * * * @@ -614,8 +614,8 @@ * * -* * * @@ -624,11 +624,11 @@ * -* * *
VersionChangesReason for Change
1.20.2Minor documentation updates.Documentation enhancement.
1.20.1Documentation is extended/improved.Enhancement based on usability feedback.
1.20Flattened the organization of the driver source code into the single source directory and the single include directory.Driver library directory-structure simplification.
Added new API functions: +* Added new API functions: * - \ref Cy_TrigMux_Select * - \ref Cy_TrigMux_Deselect * - \ref Cy_TrigMux_SetDebugFreeze -* +* * Modified the \ref Cy_TrigMux_SwTrigger API function logic. * New devices support.
Added register access layer. Use register access macros instead * of direct register access using dereferenced pointers.Makes register access device-independent, so that the PDL does +* Makes register access device-independent, so that the PDL does * not need to be recompiled for each supported part number.
1.10The input/output bit in the trigLine parameter of the +* The input/output bit in the trigLine parameter of the * Cy_TrigMux_SwTrigger() function is changed to 30.
* The invert parameter type is changed to bool.
* Added input parameter validation to the API functions.		AA cast should not be performed between a pointer to object type and * a different pointer to object type.The function \ref Cy_USBFS_Dev_Drv_LoadInEndpoint and -* \ref Cy_USBFS_Dev_Drv_ReadOutEndpoint cast buffer parameters from -* (uint8_t *) to (uint16_t *) when 16-bit access is enabled. -* To handle alignment issues the macro -* \ref CY_USBFS_DEV_DRV_ALLOC_ENDPOINT_BUFFER must be used to +* The function \ref Cy_USBFS_Dev_Drv_LoadInEndpoint and +* \ref Cy_USBFS_Dev_Drv_ReadOutEndpoint cast buffer parameters from +* (uint8_t *) to (uint16_t *) when 16-bit access is enabled. +* To handle alignment issues the macro +* \ref CY_USBFS_DEV_DRV_ALLOC_ENDPOINT_BUFFER must be used to * allocate the buffer for the endpoint.
A cast shall not be performed that removes any const or volatile * qualification from the type addressed by a pointer. -* 1. The register access-macros cast base-pointers to the USBFS peripheral -* registers lose the const qualification. Despite the qualification being +* 1. The register access-macros cast base-pointers to the USBFS peripheral +* registers lose the const qualification. Despite the qualification being * lost, the driver ensures the proper registers access. -* 2. The volatile qualification is lost when a register address is passed -* as a source or destination to the DMA channel. This does not cause any +* 2. The volatile qualification is lost when a register address is passed +* as a source or destination to the DMA channel. This does not cause any * negative impact because the DMA does not optimize any memory access. *
RA function shall have a single point of exit at the end of the * function.The functions can return from several points. This is typically -* done to improve code clarity when returning error status code if +* The functions can return from several points. This is typically +* done to improve code clarity when returning error status code if * input parameters validation fail.
A pointer parameter in a function prototype should be declared as * pointer to const if the pointer is not used to modify the addressed * object.The middleware and USBFS driver define the general function -* prototypes and pointers to the function types but the function's -* implementation depends on the configuration. Therefore, -* some functions' implementations require parameters to be a pointer to -* const but this is not met because of the generalized implementation +* The middleware and USBFS driver define the general function +* prototypes and pointers to the function types but the function's +* implementation depends on the configuration. Therefore, +* some functions' implementations require parameters to be a pointer to +* const but this is not met because of the generalized implementation * approach.
@@ -640,16 +640,21 @@ * * * +* +* +* +* +* * -* -* * * -* * * * -* -* * @@ -670,18 +675,18 @@ * -* * * * * -* * * @@ -728,10 +733,10 @@ * \defgroup group_usbfs_dev_hal_functions_data_xfer Data Endpoint Transfer Functions * \defgroup group_usbfs_dev_drv_functions_low_power Low Power Functions * \defgroup group_usbfs_dev_drv_functions_lpm LPM (Link Power Management) Functions -* \} +* \} * \defgroup group_usbfs_dev_drv_data_structures Data Structures * \defgroup group_usbfs_dev_drv_enums Enumerated Types -* \} +* \} */ @@ -787,46 +792,46 @@ typedef enum { /** Operation completed successfully */ CY_USBFS_DEV_DRV_SUCCESS = 0U, - - /** One or more input parameters are invalid */ - CY_USBFS_DEV_DRV_BAD_PARAM = (CY_USBFS_ID | CY_PDL_STATUS_ERROR | CY_USBFS_DEV_DRV_STATUS_CODE | 1U), - - /** There is not enough space in the buffer to be allocated for the endpoint (hardware or RAM) */ - CY_USBFS_DEV_DRV_BUF_ALLOC_FAILED = (CY_USBFS_ID | CY_PDL_STATUS_ERROR | CY_USBFS_DEV_DRV_STATUS_CODE | 2U), - - /** Failure during DMA configuration */ - CY_USBFS_DEV_DRV_DMA_CFG_FAILED = (CY_USBFS_ID | CY_PDL_STATUS_ERROR | CY_USBFS_DEV_DRV_STATUS_CODE | 3U), - - /** Timeout during dynamic reconfiguration */ - CY_USBFS_DEV_DRV_EP_DYN_RECONFIG_TIMEOUT = (CY_USBFS_ID | CY_PDL_STATUS_ERROR | CY_USBFS_DEV_DRV_STATUS_CODE | 4U), - - /** Timeout during execution of the DMA read request for the OUT endpoint - * (only applicable in \ref group_usbfs_dev_drv_ep_management_mode2) - */ - CY_USBFS_DEV_DRV_EP_DMA_READ_TIMEOUT = (CY_USBFS_ID | CY_PDL_STATUS_ERROR | CY_USBFS_DEV_DRV_STATUS_CODE | 5U), - /** Timeout during execution of the DMA read request for the OUT endpoint - * (only applicable in \ref group_usbfs_dev_drv_ep_management_mode2) + /** One or more input parameters are invalid */ + CY_USBFS_DEV_DRV_BAD_PARAM = (CY_USBFS_ID | CY_PDL_STATUS_ERROR | CY_USBFS_DEV_DRV_STATUS_CODE | 1U), + + /** There is not enough space in the buffer to be allocated for the endpoint (hardware or RAM) */ + CY_USBFS_DEV_DRV_BUF_ALLOC_FAILED = (CY_USBFS_ID | CY_PDL_STATUS_ERROR | CY_USBFS_DEV_DRV_STATUS_CODE | 2U), + + /** Failure during DMA configuration */ + CY_USBFS_DEV_DRV_DMA_CFG_FAILED = (CY_USBFS_ID | CY_PDL_STATUS_ERROR | CY_USBFS_DEV_DRV_STATUS_CODE | 3U), + + /** Timeout during dynamic reconfiguration */ + CY_USBFS_DEV_DRV_EP_DYN_RECONFIG_TIMEOUT = (CY_USBFS_ID | CY_PDL_STATUS_ERROR | CY_USBFS_DEV_DRV_STATUS_CODE | 4U), + + /** Timeout during execution of the DMA read request for the OUT endpoint + * (only applicable in \ref group_usbfs_dev_drv_ep_management_mode2) + */ + CY_USBFS_DEV_DRV_EP_DMA_READ_TIMEOUT = (CY_USBFS_ID | CY_PDL_STATUS_ERROR | CY_USBFS_DEV_DRV_STATUS_CODE | 5U), + + /** Timeout during execution of the DMA read request for the OUT endpoint + * (only applicable in \ref group_usbfs_dev_drv_ep_management_mode2) */ CY_USBFS_DEV_DRV_EP_DMA_WRITE_TIMEOUT = (CY_USBFS_ID | CY_PDL_STATUS_ERROR | CY_USBFS_DEV_DRV_STATUS_CODE | 6U), -} cy_en_usbfs_dev_drv_status_t; +} cy_en_usbfs_dev_drv_status_t; /** Data Endpoints Buffer Management Mode */ typedef enum { - /** CPU manages a data transfer between the hardware endpoints buffer + /** CPU manages a data transfer between the hardware endpoints buffer * and the user SRAM */ CY_USBFS_DEV_DRV_EP_MANAGEMENT_CPU = 0, - + /** DMA manages data transfer between the hardware endpoints buffer and * the user SRAM */ CY_USBFS_DEV_DRV_EP_MANAGEMENT_DMA = 1, - /** The DMA automatically manages a data transfer between the hardware endpoints + /** The DMA automatically manages a data transfer between the hardware endpoints * FIFO buffer and the user SRAM */ CY_USBFS_DEV_DRV_EP_MANAGEMENT_DMA_AUTO = 2, @@ -887,7 +892,7 @@ typedef enum typedef enum { /** The next LPM request will be responded with NACK */ - CY_USBFS_DEV_DRV_LPM_REQ_NACK = 0x0U, + CY_USBFS_DEV_DRV_LPM_REQ_NACK = 0x0U, /** The next LPM request will be responded with ACK */ CY_USBFS_DEV_DRV_LPM_REQ_ACK = 0x1U, @@ -924,7 +929,7 @@ typedef struct uint16_t bufferSize; /**< The endpoint buffer size (the biggest max packet size across all alternate for this endpoint) */ uint8_t endpointAddr; /**< The endpoint address (number plus direction bit) */ - uint8_t attributes; /**< The endpoint attributes */ + uint8_t attributes; /**< The endpoint attributes */ } cy_stc_usb_dev_ep_config_t; /** @@ -937,25 +942,25 @@ struct cy_stc_usbfs_dev_drv_context; * Provides the typedef for the callback function called in the * \ref Cy_USBFS_Dev_Drv_Interrupt to notify the user interrupt events. */ -typedef void (* cy_cb_usbfs_dev_drv_callback_t)(USBFS_Type *base, +typedef void (* cy_cb_usbfs_dev_drv_callback_t)(USBFS_Type *base, struct cy_stc_usbfs_dev_drv_context *context); /** * Provides the typedef for the callback function called in the -* \ref Cy_USBFS_Dev_Drv_Interrupt to notify the user about endpoint transfer +* \ref Cy_USBFS_Dev_Drv_Interrupt to notify the user about endpoint transfer * completion event. */ -typedef void (* cy_cb_usbfs_dev_drv_ep_callback_t)(USBFS_Type *base, +typedef void (* cy_cb_usbfs_dev_drv_ep_callback_t)(USBFS_Type *base, uint32_t endpointAddr, - uint32_t errorType, + uint32_t errorType, struct cy_stc_usbfs_dev_drv_context *context); /** -* Provides the typedef for the user defined function to replace library provided +* Provides the typedef for the user defined function to replace library provided * memcpy function to copy data from endpoint buffer to the user buffer. */ -typedef uint8_t * (* cy_fn_usbfs_dev_drv_memcpy_ptr_t)(uint8_t *dest, - const uint8_t *src, +typedef uint8_t * (* cy_fn_usbfs_dev_drv_memcpy_ptr_t)(uint8_t *dest, + const uint8_t *src, uint32_t size); /** \cond INTERNAL*/ @@ -1000,7 +1005,7 @@ typedef struct uint32_t priority; /**< Channel's priority */ bool preemptable; /**< Specifies whether the channel is preempt-able by another higher-priority channel */ - /** DMA out trigger mux (applicable only when mode is + /** DMA out trigger mux (applicable only when mode is * \ref CY_USBFS_DEV_DRV_EP_MANAGEMENT_DMA_AUTO) */ uint32_t outTrigMux; @@ -1008,8 +1013,8 @@ typedef struct /** The pointer to the 1st allocated DMA descriptor (required for DMA operation) */ cy_stc_dma_descriptor_t *descr0; - /** The pointer to the 2nd allocated DMA descriptor (required when mode is - * \ref CY_USBFS_DEV_DRV_EP_MANAGEMENT_DMA_AUTO) + /** The pointer to the 2nd allocated DMA descriptor (required when mode is + * \ref CY_USBFS_DEV_DRV_EP_MANAGEMENT_DMA_AUTO) */ cy_stc_dma_descriptor_t *descr1; @@ -1022,26 +1027,26 @@ typedef struct cy_stc_usbfs_dev_drv_config cy_en_usbfs_dev_drv_ep_management_mode_t mode; /** DMA channels configuration for the endpoints. - * Only DMChannels for active endpoints must be configured. Provide NULL - * pointer if endpoint is not used. Applicable when \ref mode is + * Only DMChannels for active endpoints must be configured. Provide NULL + * pointer if endpoint is not used. Applicable when \ref mode is * \ref CY_USBFS_DEV_DRV_EP_MANAGEMENT_DMA or \ref CY_USBFS_DEV_DRV_EP_MANAGEMENT_DMA_AUTO. */ const cy_stc_usbfs_dev_drv_dma_config_t *dmaConfig[CY_USBFS_DEV_DRV_NUM_EPS_MAX]; - /** - * The pointer to the buffer allocated for the OUT endpoints (applicable only when \ref mode + /** + * The pointer to the buffer allocated for the OUT endpoints (applicable only when \ref mode * is \ref CY_USBFS_DEV_DRV_EP_MANAGEMENT_DMA_AUTO) */ uint8_t *epBuffer; - - /** - * The size of the buffer for the OUT endpoints (applicable only when \ref mode + + /** + * The size of the buffer for the OUT endpoints (applicable only when \ref mode * is \ref CY_USBFS_DEV_DRV_EP_MANAGEMENT_DMA_AUTO) */ uint16_t epBufferSize; /** The mask that assigns interrupt sources to trigger: Low, Medium, or High interrupt. - * Use the macros provided in group_usbfs_dev_drv_macros_intr_level to initialize the + * Use the macros provided in group_usbfs_dev_drv_macros_intr_level to initialize the * intrLevelSel mask. */ uint32_t intrLevelSel; @@ -1077,7 +1082,7 @@ typedef struct cy_stc_dma_descriptor_t* descr0; /**< The pointer to the descriptor 0 */ cy_stc_dma_descriptor_t* descr1; /**< The pointer to the descriptor 1 */ - + cy_fn_usbfs_dev_drv_memcpy_ptr_t copyData; /**< The pointer to the user memcpy function */ } cy_stc_usbfs_dev_drv_endpoint_data_t; @@ -1086,7 +1091,7 @@ typedef struct /** USBFS Device context structure. * All fields for the context structure are internal. The firmware never reads or * writes these values. The firmware allocates a structure and provides the -* address of the structure to the middleware in HID function calls. The firmware +* address of the structure to the middleware in HID function calls. The firmware * must ensure that the defined instance of this structure remains in scope while * the middleware is in use. */ @@ -1172,62 +1177,62 @@ typedef struct cy_stc_usbfs_dev_drv_context /** * \addtogroup group_usbfs_dev_hal_functions_common * \{ -* The Initialization functions provide an API to begin the USBFS driver operation +* The Initialization functions provide an API to begin the USBFS driver operation * (configure and enable) and to stop operation (disable and de-initialize). */ cy_en_usbfs_dev_drv_status_t Cy_USBFS_Dev_Drv_Init(USBFS_Type *base, cy_stc_usbfs_dev_drv_config_t const *config, cy_stc_usbfs_dev_drv_context_t *context); -void Cy_USBFS_Dev_Drv_DeInit(USBFS_Type *base, +void Cy_USBFS_Dev_Drv_DeInit(USBFS_Type *base, cy_stc_usbfs_dev_drv_context_t *context); -void Cy_USBFS_Dev_Drv_Enable(USBFS_Type *base, +void Cy_USBFS_Dev_Drv_Enable(USBFS_Type *base, cy_stc_usbfs_dev_drv_context_t const *context); -void Cy_USBFS_Dev_Drv_Disable(USBFS_Type *base, +void Cy_USBFS_Dev_Drv_Disable(USBFS_Type *base, cy_stc_usbfs_dev_drv_context_t *context); -__STATIC_INLINE void Cy_USBFS_Dev_Drv_SetAddress(USBFS_Type *base, uint8_t address, +__STATIC_INLINE void Cy_USBFS_Dev_Drv_SetAddress(USBFS_Type *base, uint8_t address, cy_stc_usbfs_dev_drv_context_t *context); __STATIC_INLINE void Cy_USBFS_Dev_Drv_SetDeviceAddress(USBFS_Type *base, uint8_t address); __STATIC_INLINE uint32_t Cy_USBFS_Dev_Drv_GetDeviceAddress(USBFS_Type const *base); __STATIC_INLINE void Cy_USBFS_Dev_Drv_SetDevContext(USBFS_Type const *base, - void *devContext, + void *devContext, cy_stc_usbfs_dev_drv_context_t *context); __STATIC_INLINE void* Cy_USBFS_Dev_Drv_GetDevContext(USBFS_Type const *base, cy_stc_usbfs_dev_drv_context_t *context); -void Cy_USBFS_Dev_Drv_ConfigDevice(USBFS_Type *base, +void Cy_USBFS_Dev_Drv_ConfigDevice(USBFS_Type *base, cy_stc_usbfs_dev_drv_context_t *context); -void Cy_USBFS_Dev_Drv_UnConfigureDevice(USBFS_Type *base, +void Cy_USBFS_Dev_Drv_UnConfigureDevice(USBFS_Type *base, cy_stc_usbfs_dev_drv_context_t *context); /** \} group_usbfs_dev_hal_functions_common */ /** * \addtogroup group_usbfs_dev_hal_functions_ep0_service * \{ -* The Endpoint 0 Service functions provide an API to establish communication with +* The Endpoint 0 Service functions provide an API to establish communication with * the USB Host using control endpoint 0. */ void Cy_USBFS_Dev_Drv_Ep0GetSetup(USBFS_Type const *base, uint8_t *buffer, cy_stc_usbfs_dev_drv_context_t const *context); -uint32_t Cy_USBFS_Dev_Drv_Ep0Write(USBFS_Type *base, - uint8_t const *buffer, - uint32_t size, +uint32_t Cy_USBFS_Dev_Drv_Ep0Write(USBFS_Type *base, + uint8_t const *buffer, + uint32_t size, cy_stc_usbfs_dev_drv_context_t *context); void Cy_USBFS_Dev_Drv_Ep0Read(USBFS_Type *base, - uint8_t *buffer, - uint32_t size, + uint8_t *buffer, + uint32_t size, cy_stc_usbfs_dev_drv_context_t *context); -uint32_t Cy_USBFS_Dev_Drv_Ep0ReadResult(USBFS_Type const *base, +uint32_t Cy_USBFS_Dev_Drv_Ep0ReadResult(USBFS_Type const *base, cy_stc_usbfs_dev_drv_context_t *context); __STATIC_INLINE void Cy_USBFS_Dev_Drv_Ep0Stall(USBFS_Type *base); @@ -1239,7 +1244,7 @@ __STATIC_INLINE uint32_t Cy_USBFS_Dev_Drv_GetEp0MaxPacket(USBFS_Type const *base /** * \addtogroup group_usbfs_dev_hal_functions_endpoint_config * \{ -* The Data Endpoint Configuration Functions provide an API to allocate and release +* The Data Endpoint Configuration Functions provide an API to allocate and release * hardware resources and override the memcpy function for the data endpoints. */ __STATIC_INLINE cy_en_usbfs_dev_drv_status_t Cy_USBFS_Dev_Drv_AddEndpoint(USBFS_Type *base, @@ -1250,15 +1255,15 @@ cy_en_usbfs_dev_drv_status_t Cy_USBFS_Dev_Drv_RemoveEndpoint(USBFS_Type *base, uint32_t endpointAddr, cy_stc_usbfs_dev_drv_context_t *context); -__STATIC_INLINE void Cy_USBFS_Dev_Drv_OverwriteMemcpy(USBFS_Type const *base, - uint32_t endpoint, - cy_fn_usbfs_dev_drv_memcpy_ptr_t memcpyFunc, +__STATIC_INLINE void Cy_USBFS_Dev_Drv_OverwriteMemcpy(USBFS_Type const *base, + uint32_t endpoint, + cy_fn_usbfs_dev_drv_memcpy_ptr_t memcpyFunc, cy_stc_usbfs_dev_drv_context_t *context); /** \} group_usbfs_dev_hal_functions_endpoint_config */ /** * \addtogroup group_usbfs_dev_hal_functions_data_xfer -* The Data Endpoint Transfer functions provide an API to establish +* The Data Endpoint Transfer functions provide an API to establish * communication with the USB Host using data endpoint. * \{ */ @@ -1302,7 +1307,7 @@ cy_en_usbfs_dev_drv_status_t Cy_USBFS_Dev_Drv_UnStallEndpoint(USBFS_Type *base, /** * \addtogroup group_usbfs_dev_drv_functions_interrupts -* The Functions Interrupt functions provide an API to register callbacks +* The Functions Interrupt functions provide an API to register callbacks * for interrupt events provided by the USB block, interrupt handler, and configuration functions. * \{ */ @@ -1317,16 +1322,16 @@ void Cy_USBFS_Dev_Drv_RegisterServiceCallback(USBFS_Type const *base, cy_cb_usbfs_dev_drv_callback_t callback, cy_stc_usbfs_dev_drv_context_t *context); -__STATIC_INLINE void Cy_USBFS_Dev_Drv_RegisterSofCallback(USBFS_Type *base, - cy_cb_usbfs_dev_drv_callback_t callback, +__STATIC_INLINE void Cy_USBFS_Dev_Drv_RegisterSofCallback(USBFS_Type *base, + cy_cb_usbfs_dev_drv_callback_t callback, cy_stc_usbfs_dev_drv_context_t *context); -__STATIC_INLINE void Cy_USBFS_Dev_Drv_RegisterLpmCallback(USBFS_Type *base, - cy_cb_usbfs_dev_drv_callback_t callback, +__STATIC_INLINE void Cy_USBFS_Dev_Drv_RegisterLpmCallback(USBFS_Type *base, + cy_cb_usbfs_dev_drv_callback_t callback, cy_stc_usbfs_dev_drv_context_t *context); -__STATIC_INLINE void Cy_USBFS_Dev_Drv_RegisterEndpointCallback(USBFS_Type const *base, - uint32_t endpoint, +__STATIC_INLINE void Cy_USBFS_Dev_Drv_RegisterEndpointCallback(USBFS_Type const *base, + uint32_t endpoint, cy_cb_usbfs_dev_drv_ep_callback_t callback, cy_stc_usbfs_dev_drv_context_t *context); @@ -1338,7 +1343,7 @@ __STATIC_INLINE void Cy_USBFS_Dev_Drv_EnableEp0Interrupt(USBFS_Type *base); /** \} group_usbfs_dev_drv_functions_interrupts */ /** -* \addtogroup group_usbfs_dev_drv_functions_low_power +* \addtogroup group_usbfs_dev_drv_functions_low_power * The Low-power functions provide an API to implement Low-power callback at the application level. * \{ */ @@ -1350,7 +1355,7 @@ __STATIC_INLINE void Cy_USBFS_Dev_Drv_Force (USBFS_Type *base, cy_en_usbf /** * \addtogroup group_usbfs_dev_drv_functions_lpm -* The LPM functions provide an API to use the LPM feature available in the USB block. +* The LPM functions provide an API to use the LPM feature available in the USB block. * \{ */ __STATIC_INLINE uint32_t Cy_USBFS_Dev_Drv_Lpm_GetBeslValue (USBFS_Type const *base); @@ -1368,10 +1373,10 @@ __STATIC_INLINE cy_en_usbfs_dev_drv_lpm_req_t Cy_USBFS_Dev_Drv_Lpm_GetResponse(U * \addtogroup group_usbfs_dev_drv_macros * \{ */ -/** Allocates a static buffer for the data endpoint. The size parameter must be a constant. -* The allocated buffer is aligned to a 2-byte boundary. An odd buffer size is -* converted to even, consuming 1 extra byte. The application must discard this -* extra byte to support different 8-bit and 16-bit hardware buffer access types +/** Allocates a static buffer for the data endpoint. The size parameter must be a constant. +* The allocated buffer is aligned to a 2-byte boundary. An odd buffer size is +* converted to even, consuming 1 extra byte. The application must discard this +* extra byte to support different 8-bit and 16-bit hardware buffer access types * in the driver. For more detail, refer to \ref group_usbfs_dev_drv_ep_management_buf_access. */ #define CY_USBFS_DEV_DRV_ALLOC_ENDPOINT_BUFFER(buf, size) uint8_t buf[(0U != ((size) & 0x1U)) ? ((size) + 1U) : (size)] CY_ALIGN(2) @@ -1441,17 +1446,17 @@ __STATIC_INLINE cy_en_usbfs_dev_drv_lpm_req_t Cy_USBFS_Dev_Drv_Lpm_GetResponse(U * \addtogroup group_usbfs_dev_drv_macros_ep_xfer_err * \{ */ -/** -* An error occurred during a USB transfer. -* For an IN transaction, this indicates a "no response" from the HOST scenario. -* For an OUT transaction, this represents a "PID or CRC error" or the bit-stuff +/** +* An error occurred during a USB transfer. +* For an IN transaction, this indicates a "no response" from the HOST scenario. +* For an OUT transaction, this represents a "PID or CRC error" or the bit-stuff * error scenario. */ #define CY_USBFS_DEV_ENDPOINT_TRANSFER_ERROR (0x1U) -/** +/** * The data toggle bit remains the same. -* The received OUT packet has the same data toggle bit that the previous +* The received OUT packet has the same data toggle bit that the previous * packet had. This indicates that the Host retransmitted the packet. */ #define CY_USBFS_DEV_ENDPOINT_SAME_DATA_TOGGLE (0x2U) @@ -1504,8 +1509,8 @@ __STATIC_INLINE cy_en_usbfs_dev_drv_lpm_req_t Cy_USBFS_Dev_Drv_Lpm_GetResponse(U * Function Name: Cy_USBFS_Dev_Drv_SetAddress ****************************************************************************//** * -* Posts a request to set the device address after the completion status stage of -* the control transfer. This function must be used if a higher level requests +* Posts a request to set the device address after the completion status stage of +* the control transfer. This function must be used if a higher level requests * to set an address before the status stage of the control transfer. * * \param base @@ -1516,12 +1521,12 @@ __STATIC_INLINE cy_en_usbfs_dev_drv_lpm_req_t Cy_USBFS_Dev_Drv_Lpm_GetResponse(U * * \param context * The pointer to the context structure \ref cy_stc_usbfs_dev_drv_context_t -* allocated by the user. The structure is used during the USBFS Device -* operation for internal configuration and data retention. The user must not +* allocated by the user. The structure is used during the USBFS Device +* operation for internal configuration and data retention. The user must not * modify anything in this structure. * *******************************************************************************/ -__STATIC_INLINE void Cy_USBFS_Dev_Drv_SetAddress(USBFS_Type *base, uint8_t address, +__STATIC_INLINE void Cy_USBFS_Dev_Drv_SetAddress(USBFS_Type *base, uint8_t address, cy_stc_usbfs_dev_drv_context_t *context) { (void)base; /* Suppress warning */ @@ -1561,7 +1566,7 @@ __STATIC_INLINE void Cy_USBFS_Dev_Drv_SetDeviceAddress(USBFS_Type *base, uint8_t * * \return * The device address. -* The device address is assigned by the Host during device enumeration. +* The device address is assigned by the Host during device enumeration. * Zero means that the device address is not assigned. * *******************************************************************************/ @@ -1585,8 +1590,8 @@ __STATIC_INLINE uint32_t Cy_USBFS_Dev_Drv_GetDeviceAddress(USBFS_Type const *bas * * \param context * The pointer to the context structure \ref cy_stc_usbfs_dev_drv_context_t -* allocated by the user. The structure is used during the USBFS Device -* operation for internal configuration and data retention. The user must not +* allocated by the user. The structure is used during the USBFS Device +* operation for internal configuration and data retention. The user must not * modify anything in this structure. * * \note @@ -1594,7 +1599,7 @@ __STATIC_INLINE uint32_t Cy_USBFS_Dev_Drv_GetDeviceAddress(USBFS_Type const *bas * *******************************************************************************/ __STATIC_INLINE void Cy_USBFS_Dev_Drv_SetDevContext(USBFS_Type const *base, - void *devContext, + void *devContext, cy_stc_usbfs_dev_drv_context_t *context) { /* Suppresses a compiler warning about unused variables. */ @@ -1615,8 +1620,8 @@ __STATIC_INLINE void Cy_USBFS_Dev_Drv_SetDevContext(USBFS_Type const *base, * * \param context * The pointer to the context structure \ref cy_stc_usbfs_dev_drv_context_t -* allocated by the user. The structure is used during USBFS Device -* operation for internal configuration and data retention. The user must not +* allocated by the user. The structure is used during USBFS Device +* operation for internal configuration and data retention. The user must not * modify anything in this structure. * * \return @@ -1645,8 +1650,8 @@ __STATIC_INLINE void* Cy_USBFS_Dev_Drv_GetDevContext(USBFS_Type const *base, * Function Name: Cy_USBFS_Dev_Drv_RegisterSofCallback ****************************************************************************//** * -* Registers a callback function to notify about an SOF event in -* \ref Cy_USBFS_Dev_Drv_Interrupt. The SOF interrupt source is enabled after +* Registers a callback function to notify about an SOF event in +* \ref Cy_USBFS_Dev_Drv_Interrupt. The SOF interrupt source is enabled after * registration. To remove callback function, pass NULL as the function pointer. * When the callback is removed, the interrupt source is disabled. * @@ -1658,25 +1663,25 @@ __STATIC_INLINE void* Cy_USBFS_Dev_Drv_GetDevContext(USBFS_Type const *base, * * \param context * The pointer to the context structure \ref cy_stc_usbfs_dev_drv_context_t -* allocated by the user. The structure is used during the USBFS Device -* operation for internal configuration and data retention. The user must not +* allocated by the user. The structure is used during the USBFS Device +* operation for internal configuration and data retention. The user must not * modify anything in this structure. * * \note * To remove the callback, pass NULL as the pointer to a callback function. * *******************************************************************************/ -__STATIC_INLINE void Cy_USBFS_Dev_Drv_RegisterSofCallback(USBFS_Type *base, - cy_cb_usbfs_dev_drv_callback_t callback, +__STATIC_INLINE void Cy_USBFS_Dev_Drv_RegisterSofCallback(USBFS_Type *base, + cy_cb_usbfs_dev_drv_callback_t callback, cy_stc_usbfs_dev_drv_context_t *context) { uint32_t mask; - + context->cbSof = callback; - + /* Enables/Disables SOF interrupt */ mask = Cy_USBFS_Dev_Drv_GetSieInterruptMask(base); - + if (NULL != callback) { mask |= CY_USBFS_DEV_DRV_INTR_SIE_SOF; @@ -1685,7 +1690,7 @@ __STATIC_INLINE void Cy_USBFS_Dev_Drv_RegisterSofCallback(USBFS_Type *base, { mask &= ~CY_USBFS_DEV_DRV_INTR_SIE_SOF; } - + Cy_USBFS_Dev_Drv_ClearSieInterrupt(base, CY_USBFS_DEV_DRV_INTR_SIE_SOF); Cy_USBFS_Dev_Drv_SetSieInterruptMask(base, mask); } @@ -1695,8 +1700,8 @@ __STATIC_INLINE void Cy_USBFS_Dev_Drv_RegisterSofCallback(USBFS_Type *base, * Function Name: Cy_USBFS_Dev_Drv_RegisterLpmCallback ****************************************************************************//** * -* Registers a callback function to notify about an LPM event in -* \ref Cy_USBFS_Dev_Drv_Interrupt. The LPM interrupt source is enabled after +* Registers a callback function to notify about an LPM event in +* \ref Cy_USBFS_Dev_Drv_Interrupt. The LPM interrupt source is enabled after * registration. To remove the callback function, pass NULL as the function pointer. * When the callback is removed, the interrupt source is disabled. * @@ -1708,26 +1713,26 @@ __STATIC_INLINE void Cy_USBFS_Dev_Drv_RegisterSofCallback(USBFS_Type *base, * * \param context * The pointer to the context structure \ref cy_stc_usbfs_dev_drv_context_t -* allocated by the user. The structure is used during the USBFS Device -* operation for internal configuration and data retention. The user must not +* allocated by the user. The structure is used during the USBFS Device +* operation for internal configuration and data retention. The user must not * modify anything in this structure. * * \note * To remove the callback, pass NULL as the pointer to the callback function. * *******************************************************************************/ -__STATIC_INLINE void Cy_USBFS_Dev_Drv_RegisterLpmCallback(USBFS_Type *base, - cy_cb_usbfs_dev_drv_callback_t callback, +__STATIC_INLINE void Cy_USBFS_Dev_Drv_RegisterLpmCallback(USBFS_Type *base, + cy_cb_usbfs_dev_drv_callback_t callback, cy_stc_usbfs_dev_drv_context_t *context) { uint32_t mask; - + context->cbLpm = callback; - + /* Enables/Disables the LPM interrupt source */ mask = Cy_USBFS_Dev_Drv_GetSieInterruptMask(base); - + if (NULL != callback) { mask |= CY_USBFS_DEV_DRV_INTR_SIE_LPM; @@ -1736,7 +1741,7 @@ __STATIC_INLINE void Cy_USBFS_Dev_Drv_RegisterLpmCallback(USBFS_Type *base, { mask &= ~CY_USBFS_DEV_DRV_INTR_SIE_LPM; } - + Cy_USBFS_Dev_Drv_ClearSieInterrupt(base, CY_USBFS_DEV_DRV_INTR_SIE_LPM); Cy_USBFS_Dev_Drv_SetSieInterruptMask(base, mask); } @@ -1746,11 +1751,11 @@ __STATIC_INLINE void Cy_USBFS_Dev_Drv_RegisterLpmCallback(USBFS_Type *base, * Function Name: Cy_USBFS_Dev_Drv_RegisterEndpointCallback ****************************************************************************//** * -* Registers a callback function to notify of an endpoint transfer completion -* event in \ref Cy_USBFS_Dev_Drv_Interrupt. -* * IN endpoint - The Host read data from the endpoint and new data can be -* loaded. -* * OUT endpoint - The Host has written data into the endpoint and the data is +* Registers a callback function to notify of an endpoint transfer completion +* event in \ref Cy_USBFS_Dev_Drv_Interrupt. +* * IN endpoint - The Host read data from the endpoint and new data can be +* loaded. +* * OUT endpoint - The Host has written data into the endpoint and the data is * ready to be read. * To remove the callback function, pass NULL as function pointer. * @@ -1765,25 +1770,25 @@ __STATIC_INLINE void Cy_USBFS_Dev_Drv_RegisterLpmCallback(USBFS_Type *base, * * \param context * The pointer to the context structure \ref cy_stc_usbfs_dev_drv_context_t -* allocated by the user. The structure is used during the USBFS Device -* operation for internal configuration and data retention. The user must not +* allocated by the user. The structure is used during the USBFS Device +* operation for internal configuration and data retention. The user must not * modify anything in this structure. * * \note * To remove the callback, pass NULL as the pointer to the callback function. * *******************************************************************************/ -__STATIC_INLINE void Cy_USBFS_Dev_Drv_RegisterEndpointCallback(USBFS_Type const *base, - uint32_t endpoint, - cy_cb_usbfs_dev_drv_ep_callback_t callback, +__STATIC_INLINE void Cy_USBFS_Dev_Drv_RegisterEndpointCallback(USBFS_Type const *base, + uint32_t endpoint, + cy_cb_usbfs_dev_drv_ep_callback_t callback, cy_stc_usbfs_dev_drv_context_t *context) { /* Suppresses a compiler warning about unused variables */ (void) base; - + CY_ASSERT_L1(CY_USBFS_DEV_DRV_IS_EP_VALID(endpoint)); - + endpoint = CY_USBFS_DEV_DRV_EP2PHY(endpoint); context->epPool[endpoint].epComplete = callback; } @@ -1935,10 +1940,10 @@ __STATIC_INLINE void Cy_USBFS_Dev_Drv_EnableEp0Interrupt(USBFS_Type *base) * Function Name: Cy_USBFS_Dev_Drv_CheckActivity ****************************************************************************//** * -* Returns the activity status of the bus. -* It clears the hardware status to provide an updated status on the next call of -* this function. This function is useful to determine whether there is any USB bus -* activity between function calls. A typical use case is to determine whether +* Returns the activity status of the bus. +* It clears the hardware status to provide an updated status on the next call of +* this function. This function is useful to determine whether there is any USB bus +* activity between function calls. A typical use case is to determine whether * the USB suspend conditions are met. * * \param base @@ -1964,7 +1969,7 @@ __STATIC_INLINE bool Cy_USBFS_Dev_Drv_CheckActivity(USBFS_Type *base) * Function Name: Cy_USBFS_Dev_Drv_Force ****************************************************************************//** * -* Forces a USB J, K, or SE0 state on the USB lines. +* Forces a USB J, K, or SE0 state on the USB lines. * A typical use case is to signal a Remote Wakeup condition on the USB bus. * * \param base @@ -1991,7 +1996,7 @@ __STATIC_INLINE void Cy_USBFS_Dev_Drv_Force(USBFS_Type *base, cy_en_usbfs_dev_dr * Function Name: Cy_USBFS_Dev_Drv_Lpm_GetBeslValue ****************************************************************************//** * -* Returns the Best Effort Service Latency (BESL) value sent by the host as +* Returns the Best Effort Service Latency (BESL) value sent by the host as * part of the LPM token transaction. * * \param base @@ -2011,7 +2016,7 @@ __STATIC_INLINE uint32_t Cy_USBFS_Dev_Drv_Lpm_GetBeslValue(USBFS_Type const *bas * Function Name: Cy_USBFS_Dev_Drv_Lpm_RemoteWakeUpAllowed ****************************************************************************//** * -* Returns the remote wakeup permission set by the Host as part of the +* Returns the remote wakeup permission set by the Host as part of the * LPM token transaction. * * \param base @@ -2031,7 +2036,7 @@ __STATIC_INLINE bool Cy_USBFS_Dev_Drv_Lpm_RemoteWakeUpAllowed(USBFS_Type const * * Function Name: Cy_USBFS_Dev_Drv_Lpm_SetResponse ****************************************************************************//** * -* Configures the response in the handshake packet that the device sends when +* Configures the response in the handshake packet that the device sends when * an LPM token packet is received. * * \param base @@ -2044,7 +2049,7 @@ __STATIC_INLINE bool Cy_USBFS_Dev_Drv_Lpm_RemoteWakeUpAllowed(USBFS_Type const * *******************************************************************************/ __STATIC_INLINE void Cy_USBFS_Dev_Drv_Lpm_SetResponse(USBFS_Type *base, cy_en_usbfs_dev_drv_lpm_req_t response) { - USBFS_DEV_LPM_LPM_CTL(base) = _CLR_SET_FLD32U(USBFS_DEV_LPM_LPM_CTL(base), + USBFS_DEV_LPM_LPM_CTL(base) = _CLR_SET_FLD32U(USBFS_DEV_LPM_LPM_CTL(base), USBFS_USBLPM_LPM_CTL_LPM_RESP, ((uint32_t) response)); } @@ -2053,7 +2058,7 @@ __STATIC_INLINE void Cy_USBFS_Dev_Drv_Lpm_SetResponse(USBFS_Type *base, cy_en_us * Function Name: Cy_USBFS_Dev_Drv_Lpm_GetResponse ****************************************************************************//** * -* Returns the response value that the device sends as part of the handshake +* Returns the response value that the device sends as part of the handshake * packet when an LPM token packet is received. * * \param base @@ -2080,7 +2085,7 @@ __STATIC_INLINE cy_en_usbfs_dev_drv_lpm_req_t Cy_USBFS_Dev_Drv_Lpm_GetResponse(U * Function Name: Cy_USBFS_Dev_Drv_AddEndpoint ****************************************************************************//** * -* Configures a data endpoint for the following operation (allocates hardware +* Configures a data endpoint for the following operation (allocates hardware * resources for data endpoint). * * \param base @@ -2091,8 +2096,8 @@ __STATIC_INLINE cy_en_usbfs_dev_drv_lpm_req_t Cy_USBFS_Dev_Drv_Lpm_GetResponse(U * * \param context * The pointer to the context structure \ref cy_stc_usbfs_dev_drv_context_t -* allocated by the user. The structure is used during the USBFS Device -* operation for internal configuration and data retention. The user must not +* allocated by the user. The structure is used during the USBFS Device +* operation for internal configuration and data retention. The user must not * modify anything in this structure. * * \return @@ -2123,17 +2128,17 @@ __STATIC_INLINE cy_en_usbfs_dev_drv_status_t Cy_USBFS_Dev_Drv_AddEndpoint(USBFS_ * * Overwrites the memory copy (memcpy) function used to copy data with the user- * implemented: -* * \ref Cy_USBFS_Dev_Drv_ReadOutEndpoint copies data from from the internal +* * \ref Cy_USBFS_Dev_Drv_ReadOutEndpoint copies data from from the internal * buffer to the application buffer for OUT endpoint. -* * \ref Cy_USBFS_Dev_Drv_LoadInEndpoint copies data from the application buffer +* * \ref Cy_USBFS_Dev_Drv_LoadInEndpoint copies data from the application buffer * for IN endpoint to the the internal buffer. -* Only applicable when endpoint management mode is +* Only applicable when endpoint management mode is * \ref CY_USBFS_DEV_DRV_EP_MANAGEMENT_DMA_AUTO. * * \param base * The pointer to the USBFS instance. * -* \param endpoint +* \param endpoint * The data endpoint number. * * \param memcpyFunc @@ -2141,21 +2146,21 @@ __STATIC_INLINE cy_en_usbfs_dev_drv_status_t Cy_USBFS_Dev_Drv_AddEndpoint(USBFS_ * * \param context * The pointer to the context structure \ref cy_stc_usbfs_dev_drv_context_t -* allocated by the user. The structure is used during the USBFS Device -* operation for internal configuration and data retention. The user must not +* allocated by the user. The structure is used during the USBFS Device +* operation for internal configuration and data retention. The user must not * modify anything in this structure. * *******************************************************************************/ -__STATIC_INLINE void Cy_USBFS_Dev_Drv_OverwriteMemcpy(USBFS_Type const *base, - uint32_t endpoint, - cy_fn_usbfs_dev_drv_memcpy_ptr_t memcpyFunc, +__STATIC_INLINE void Cy_USBFS_Dev_Drv_OverwriteMemcpy(USBFS_Type const *base, + uint32_t endpoint, + cy_fn_usbfs_dev_drv_memcpy_ptr_t memcpyFunc, cy_stc_usbfs_dev_drv_context_t *context) { /* Suppress a compiler warning about unused variables */ (void) base; - + CY_ASSERT_L1(CY_USBFS_DEV_DRV_IS_EP_VALID(endpoint)); - + endpoint = CY_USBFS_DEV_DRV_EP2PHY(endpoint); context->epPool[endpoint].copyData = memcpyFunc; } @@ -2180,8 +2185,8 @@ __STATIC_INLINE void Cy_USBFS_Dev_Drv_OverwriteMemcpy(USBFS_Type const *base, * * \param context * The pointer to the context structure \ref cy_stc_usbfs_dev_drv_context_t -* allocated by the user. The structure is used during the USBFS Device -* operation for internal configuration and data retention. The user must not +* allocated by the user. The structure is used during the USBFS Device +* operation for internal configuration and data retention. The user must not * modify anything in this structure. * * \return @@ -2195,14 +2200,14 @@ __STATIC_INLINE cy_en_usb_dev_ep_state_t Cy_USBFS_Dev_Drv_GetEndpointState( { cy_en_usb_dev_ep_state_t retState = CY_USB_DEV_EP_INVALID; - + (void)base; /* Suppress warning */ if (CY_USBFS_DEV_DRV_IS_EP_VALID(endpoint)) { retState = context->epPool[CY_USBFS_DEV_DRV_EP2PHY(endpoint)].state; } - + return retState; } @@ -2211,7 +2216,7 @@ __STATIC_INLINE cy_en_usb_dev_ep_state_t Cy_USBFS_Dev_Drv_GetEndpointState( * Function Name: Cy_USBFS_Dev_Drv_LoadInEndpoint ****************************************************************************//** * -* Loads data into the IN endpoint buffer. After data loads, the +* Loads data into the IN endpoint buffer. After data loads, the * endpoint is ready to be read by the host. * * \param base @@ -2229,8 +2234,8 @@ __STATIC_INLINE cy_en_usb_dev_ep_state_t Cy_USBFS_Dev_Drv_GetEndpointState( * * \param context * The pointer to the context structure \ref cy_stc_usbfs_dev_drv_context_t -* allocated by the user. The structure is used during the USBFS Device -* operation for internal configuration and data retention. The user must not +* allocated by the user. The structure is used during the USBFS Device +* operation for internal configuration and data retention. The user must not * modify anything in this structure. * * \return @@ -2255,8 +2260,8 @@ __STATIC_INLINE cy_en_usbfs_dev_drv_status_t Cy_USBFS_Dev_Drv_LoadInEndpoint( * Function Name: Cy_USBFS_Dev_Drv_ReadOutEndpoint ****************************************************************************//** * -* Reads data from the OUT endpoint buffer. -* Before executing a next read, the \ref Cy_USBFS_Dev_Drv_EnableOutEndpoint must be +* Reads data from the OUT endpoint buffer. +* Before executing a next read, the \ref Cy_USBFS_Dev_Drv_EnableOutEndpoint must be * called to allow the Host to write data into the endpoint. * * \param base @@ -2277,8 +2282,8 @@ __STATIC_INLINE cy_en_usbfs_dev_drv_status_t Cy_USBFS_Dev_Drv_LoadInEndpoint( * * \param context * The pointer to the context structure \ref cy_stc_usbfs_dev_drv_context_t -* allocated by the user. The structure is used during the USBFS Device -* operation for internal configuration and data retention. The user must not +* allocated by the user. The structure is used during the USBFS Device +* operation for internal configuration and data retention. The user must not * modify anything in this structure. * * \return @@ -2319,7 +2324,7 @@ __STATIC_INLINE cy_en_usbfs_dev_drv_status_t Cy_USBFS_Dev_Drv_ReadOutEndpoint( __STATIC_INLINE bool Cy_USBFS_Dev_Drv_GetEndpointAckState(USBFS_Type const *base, uint32_t endpoint) { CY_ASSERT_L1(CY_USBFS_DEV_DRV_IS_EP_VALID(endpoint)); - + endpoint = CY_USBFS_DEV_DRV_EP2PHY(endpoint); return _FLD2BOOL(USBFS_USBDEV_SIE_EP1_CR0_ACKED_TXN, USBFS_DEV_SIE_EP_CR0(base, endpoint)); } @@ -2329,13 +2334,13 @@ __STATIC_INLINE bool Cy_USBFS_Dev_Drv_GetEndpointAckState(USBFS_Type const *base * Function Name: Cy_USBFS_Dev_Drv_GetEndpointCount ****************************************************************************//** * -* Returns the number of data bytes in the transaction for a certain endpoint. -* Before calling this function, ensure the Host has written data into the -* endpoint. The returned value is updated after the Host access to the -* endpoint but remains unchanged after data has been read from the endpoint +* Returns the number of data bytes in the transaction for a certain endpoint. +* Before calling this function, ensure the Host has written data into the +* endpoint. The returned value is updated after the Host access to the +* endpoint but remains unchanged after data has been read from the endpoint * buffer. -* A typical use case is to read the number of bytes that the Host wrote into the -* OUT endpoint. +* A typical use case is to read the number of bytes that the Host wrote into the +* OUT endpoint. * * \param base * The pointer to the USBFS instance. diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_usbfs_dev_drv_pvt.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_usbfs_dev_drv_pvt.h index ad42bfc277..b54df01178 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_usbfs_dev_drv_pvt.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_usbfs_dev_drv_pvt.h @@ -1,12 +1,12 @@ /***************************************************************************//** * \file cy_usbfs_dev_drv_pvt.h -* \version 2.20 +* \version 2.20.1 * * Provides API declarations of the USBFS driver. * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -48,23 +48,23 @@ cy_en_usbfs_dev_drv_status_t DmaInit(cy_stc_usbfs_dev_drv_config_t const *config void DmaDisable(cy_stc_usbfs_dev_drv_context_t *context); -cy_en_usbfs_dev_drv_status_t DmaEndpointInit(USBFS_Type *base, - cy_en_usbfs_dev_drv_ep_management_mode_t mode, - bool useReg16, +cy_en_usbfs_dev_drv_status_t DmaEndpointInit(USBFS_Type *base, + cy_en_usbfs_dev_drv_ep_management_mode_t mode, + bool useReg16, cy_stc_usbfs_dev_drv_endpoint_data_t *endpointData); void DmaOutEndpointRestore(cy_stc_usbfs_dev_drv_endpoint_data_t *endpoint); -cy_en_usbfs_dev_drv_status_t GetEndpointBuffer(uint32_t size, - uint32_t *idx, +cy_en_usbfs_dev_drv_status_t GetEndpointBuffer(uint32_t size, + uint32_t *idx, cy_stc_usbfs_dev_drv_context_t *context); /* Endpoint restore functions (driver specific) */ -void RestoreEndpointHwBuffer(USBFS_Type *base, +void RestoreEndpointHwBuffer(USBFS_Type *base, cy_en_usbfs_dev_drv_ep_management_mode_t mode, cy_stc_usbfs_dev_drv_endpoint_data_t *endpointData); -void RestoreEndpointRamBuffer(USBFS_Type *base, +void RestoreEndpointRamBuffer(USBFS_Type *base, cy_stc_usbfs_dev_drv_endpoint_data_t *endpointData); /* Endpoint buffer allocation functions (driver specific) */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_usbfs_dev_drv_reg.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_usbfs_dev_drv_reg.h index 3f87d10b22..b3946c5183 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_usbfs_dev_drv_reg.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_usbfs_dev_drv_reg.h @@ -1,12 +1,12 @@ /***************************************************************************//** * \file cy_usbfs_dev_drv_reg.h -* \version 2.20 +* \version 2.20.1 * * Provides register access API implementation of the USBFS driver. * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -51,7 +51,7 @@ * \defgroup group_usbfs_drv_drv_reg_sie_access SIE Data Endpoint Registers Access * \defgroup group_usbfs_drv_drv_reg_arbiter Arbiter Endpoint Registers Access * \defgroup group_usbfs_drv_drv_reg_arbiter_data Arbiter Endpoint Data Registers Access -* \defgroup group_usbfs_drv_drv_reg_misc Miscellaneous Functions +* \defgroup group_usbfs_drv_drv_reg_misc Miscellaneous Functions * \} * * \} @@ -178,7 +178,7 @@ __STATIC_INLINE uint32_t Cy_USBFS_Dev_Drv_GetArbReadAddr (USBFS_Type const *base /** \} group_usbfs_drv_drv_reg_arbiter */ /** -* \addtogroup group_usbfs_drv_drv_reg_arbiter_data +* \addtogroup group_usbfs_drv_drv_reg_arbiter_data * \{ */ /* Access data endpoints data registers. Used to get/put data into endpoint buffer */ @@ -253,7 +253,7 @@ __STATIC_INLINE uint32_t Cy_USBFS_Dev_Drv_GetSofNubmer(USBFS_Type const *base); */ /** Data endpoint IN buffer full interrupt source */ -#define USBFS_USBDEV_ARB_EP_IN_BUF_FULL_Msk USBFS_USBDEV_ARB_EP1_INT_EN_IN_BUF_FULL_EN_Msk +#define USBFS_USBDEV_ARB_EP_IN_BUF_FULL_Msk USBFS_USBDEV_ARB_EP1_INT_EN_IN_BUF_FULL_EN_Msk /** Data endpoint grant interrupt source (DMA complete read/write) */ #define USBFS_USBDEV_ARB_EP_DMA_GNT_Msk USBFS_USBDEV_ARB_EP1_INT_EN_DMA_GNT_EN_Msk /** Data endpoint overflow interrupt source (applicable only for Automatic DMA mode) */ @@ -609,15 +609,15 @@ __STATIC_INLINE uint32_t Cy_USBFS_Dev_Drv_ReadEp0Data(USBFS_Type const *base, ui * Function Name: Cy_USBFS_Dev_Drv_SetSieEpMode ****************************************************************************//** * -* Sets SIE mode in the CR0 register of the endpoint (does not touch other bits). -* All other bits except NAK_INT_EN are cleared by the hardware on any write +* Sets SIE mode in the CR0 register of the endpoint (does not touch other bits). +* All other bits except NAK_INT_EN are cleared by the hardware on any write * in the register. * * \param base * The pointer to the USBFS instance. * * \param endpoint -* Physical endpoint number. +* Physical endpoint number. * Valid range: 0 - ( \ref CY_USBFS_DEV_DRV_NUM_EPS_MAX - 1 ). * * \param mode @@ -643,7 +643,7 @@ __STATIC_INLINE void Cy_USBFS_Dev_Drv_SetSieEpMode(USBFS_Type *base, uint32_t en * The pointer to the USBFS instance. * * \param endpoint -* Physical endpoint number. +* Physical endpoint number. * Valid range: 0 - ( \ref CY_USBFS_DEV_DRV_NUM_EPS_MAX - 1 ). * * \return @@ -670,15 +670,15 @@ __STATIC_INLINE uint32_t Cy_USBFS_Dev_Drv_GetSieEpMode(USBFS_Type const *base, u * Defines whether endpoint direction is IN (true) or OUT (false). * * \param endpoint -* Physical endpoint number. +* Physical endpoint number. * Valid range: 0 - ( \ref CY_USBFS_DEV_DRV_NUM_EPS_MAX - 1 ). * *******************************************************************************/ __STATIC_INLINE void Cy_USBFS_Dev_Drv_SetSieEpStall(USBFS_Type *base, bool inDirection, uint32_t endpoint) { /* STALL endpoint */ - USBFS_DEV_SIE_EP_CR0(base, endpoint) = USBFS_USBDEV_SIE_EP1_CR0_STALL_Msk | - (inDirection ? CY_USBFS_DEV_DRV_EP_CR_ACK_IN : + USBFS_DEV_SIE_EP_CR0(base, endpoint) = USBFS_USBDEV_SIE_EP1_CR0_STALL_Msk | + (inDirection ? CY_USBFS_DEV_DRV_EP_CR_ACK_IN : CY_USBFS_DEV_DRV_EP_CR_ACK_OUT); (void) USBFS_DEV_SIE_EP_CR0(base, endpoint); } @@ -695,7 +695,7 @@ __STATIC_INLINE void Cy_USBFS_Dev_Drv_SetSieEpStall(USBFS_Type *base, bool inDir * The pointer to the USBFS instance. * * \param endpoint -* Physical endpoint number. +* Physical endpoint number. * Valid range: 0 - ( \ref CY_USBFS_DEV_DRV_NUM_EPS_MAX - 1 ). * * \param mode @@ -728,7 +728,7 @@ __STATIC_INLINE void Cy_USBFS_Dev_Drv_ClearSieEpStall(USBFS_Type *base, uint32_t * The pointer to the USBFS instance. * * \param endpoint -* Physical endpoint number. +* Physical endpoint number. * Valid range: 0 - ( \ref CY_USBFS_DEV_DRV_NUM_EPS_MAX - 1 ). * * \return @@ -751,7 +751,7 @@ __STATIC_INLINE uint32_t Cy_USBFS_Dev_Drv_GetSieEpError(USBFS_Type const *base, * The pointer to the USBFS instance. * * \param endpoint -* Physical endpoint number. +* Physical endpoint number. * Valid range: 0 - ( \ref CY_USBFS_DEV_DRV_NUM_EPS_MAX - 1 ). * * \return @@ -775,7 +775,7 @@ __STATIC_INLINE uint32_t Cy_USBFS_Dev_Drv_GetSieEpToggle(USBFS_Type const *base, * The pointer to the USBFS instance. * * \param endpoint -* Physical endpoint number. +* Physical endpoint number. * Valid range: 0 - ( \ref CY_USBFS_DEV_DRV_NUM_EPS_MAX - 1 ). * * \return @@ -800,7 +800,7 @@ __STATIC_INLINE void Cy_USBFS_Dev_Drv_ClearSieEpToggle(USBFS_Type *base, uint32_ * The pointer to the USBFS instance. * * \param endpoint -* Physical endpoint number. +* Physical endpoint number. * Valid range: 0 - ( \ref CY_USBFS_DEV_DRV_NUM_EPS_MAX - 1 ). * * \return @@ -831,7 +831,7 @@ __STATIC_INLINE uint32_t Cy_USBFS_Dev_Drv_GetSieEpCount(USBFS_Type const *base, * The pointer to the USBFS instance. * * \param endpoint -* Physical endpoint number. +* Physical endpoint number. * Valid range: 0 - ( \ref CY_USBFS_DEV_DRV_NUM_EPS_MAX - 1 ). * * \param count @@ -884,7 +884,7 @@ __STATIC_INLINE uint32_t Cy_USBFS_Dev_Drv_GetSieAllEpsInterruptStatus(USBFS_Type * The pointer to the USBFS instance. * * \param endpoint -* Physical endpoint number. +* Physical endpoint number. * Valid range: 0 - ( \ref CY_USBFS_DEV_DRV_NUM_EPS_MAX - 1 ). * *******************************************************************************/ @@ -904,7 +904,7 @@ __STATIC_INLINE void Cy_USBFS_Dev_Drv_EnableSieEpInterrupt(USBFS_Type *base, uin * The pointer to the USBFS instance. * * \param endpoint -* Physical endpoint number. +* Physical endpoint number. * Valid range: 0 - ( \ref CY_USBFS_DEV_DRV_NUM_EPS_MAX - 1 ). * *******************************************************************************/ @@ -924,7 +924,7 @@ __STATIC_INLINE void Cy_USBFS_Dev_Drv_DisableSieEpInterrupt(USBFS_Type *base, ui * The pointer to the USBFS instance. * * \param endpoint -* Physical endpoint number. +* Physical endpoint number. * Valid range: 0 - ( \ref CY_USBFS_DEV_DRV_NUM_EPS_MAX - 1 ). * *******************************************************************************/ @@ -975,7 +975,7 @@ __STATIC_INLINE uint32_t Cy_USBFS_Dev_Drv_GetArbAllEpsInterruptStatus(USBFS_Type * The pointer to the USBFS instance. * * \param endpoint -* Physical endpoint number. +* Physical endpoint number. * Valid range: 0 - ( \ref CY_USBFS_DEV_DRV_NUM_EPS_MAX - 1 ). * *******************************************************************************/ @@ -995,7 +995,7 @@ __STATIC_INLINE void Cy_USBFS_Dev_Drv_EnableArbEpInterrupt(USBFS_Type *base, uin * The pointer to the USBFS instance. * * \param endpoint -* Physical endpoint number. +* Physical endpoint number. * Valid range: 0 - ( \ref CY_USBFS_DEV_DRV_NUM_EPS_MAX - 1 ). * *******************************************************************************/ @@ -1016,7 +1016,7 @@ __STATIC_INLINE void Cy_USBFS_Dev_Drv_DisableArbEpInterrupt(USBFS_Type *base, ui * The pointer to the USBFS instance. * * \param endpoint -* Physical endpoint number. +* Physical endpoint number. * Valid range: 0 - ( \ref CY_USBFS_DEV_DRV_NUM_EPS_MAX - 1 ). * * \param mask @@ -1041,7 +1041,7 @@ __STATIC_INLINE void Cy_USBFS_Dev_Drv_SetArbEpInterruptMask(USBFS_Type *base, ui * The pointer to the USBFS instance. * * \param endpoint -* Physical endpoint number. +* Physical endpoint number. * Valid range: 0 - ( \ref CY_USBFS_DEV_DRV_NUM_EPS_MAX - 1 ). * * \return @@ -1066,7 +1066,7 @@ __STATIC_INLINE uint32_t Cy_USBFS_Dev_Drv_GetArbEpInterruptMask(USBFS_Type const * The pointer to the USBFS instance. * * \param endpoint -* Physical endpoint number. +* Physical endpoint number. * Valid range: 0 - ( \ref CY_USBFS_DEV_DRV_NUM_EPS_MAX - 1 ). * * \return @@ -1092,7 +1092,7 @@ __STATIC_INLINE uint32_t Cy_USBFS_Dev_Drv_GetArbEpInterruptStatusMasked(USBFS_Ty * The pointer to the USBFS instance. * * \param endpoint -* Physical endpoint number. +* Physical endpoint number. * Valid range: 0 - ( \ref CY_USBFS_DEV_DRV_NUM_EPS_MAX - 1 ). * * \param mask @@ -1117,7 +1117,7 @@ __STATIC_INLINE void Cy_USBFS_Dev_Drv_ClearArbEpInterrupt(USBFS_Type *base, uint * The pointer to the USBFS instance. * * \param endpoint -* Physical endpoint number. +* Physical endpoint number. * Valid range: 0 - ( \ref CY_USBFS_DEV_DRV_NUM_EPS_MAX - 1 ). * * \param cfg @@ -1141,7 +1141,7 @@ __STATIC_INLINE void Cy_USBFS_Dev_Drv_SetArbEpConfig(USBFS_Type *base, uint32_t * The pointer to the USBFS instance. * * \param endpoint -* Physical endpoint number. +* Physical endpoint number. * Valid range: 0 - ( \ref CY_USBFS_DEV_DRV_NUM_EPS_MAX - 1 ). * *******************************************************************************/ @@ -1163,7 +1163,7 @@ __STATIC_INLINE void Cy_USBFS_Dev_Drv_SetArbCfgEpInReady(USBFS_Type *base, uint3 * The pointer to the USBFS instance. * * \param endpoint -* Physical endpoint number. +* Physical endpoint number. * Valid range: 0 - ( \ref CY_USBFS_DEV_DRV_NUM_EPS_MAX - 1 ). * @@ -1184,7 +1184,7 @@ __STATIC_INLINE void Cy_USBFS_Dev_Drv_ClearArbCfgEpInReady(USBFS_Type *base, uin * The pointer to the USBFS instance. * * \param endpoint -* Physical endpoint number. +* Physical endpoint number. * Valid range: 0 - ( \ref CY_USBFS_DEV_DRV_NUM_EPS_MAX - 1 ). * *******************************************************************************/ @@ -1209,7 +1209,7 @@ __STATIC_INLINE void Cy_USBFS_Dev_Drv_TriggerArbCfgEpDmaReq(USBFS_Type *base, ui * The pointer to the USBFS instance. * * \param endpoint -* Physical endpoint number. +* Physical endpoint number. * Valid range: 0 - ( \ref CY_USBFS_DEV_DRV_NUM_EPS_MAX - 1 ). * * \param wa @@ -1233,7 +1233,7 @@ __STATIC_INLINE void Cy_USBFS_Dev_Drv_SetArbWriteAddr(USBFS_Type *base, uint32_t * The pointer to the USBFS instance. * * \param endpoint -* Physical endpoint number. +* Physical endpoint number. * Valid range: 0 - ( \ref CY_USBFS_DEV_DRV_NUM_EPS_MAX - 1 ). * * \param ra @@ -1257,7 +1257,7 @@ __STATIC_INLINE void Cy_USBFS_Dev_Drv_SetArbReadAddr(USBFS_Type *base, uint32_t * The pointer to the USBFS instance. * * \param endpoint -* Physical endpoint number. +* Physical endpoint number. * Valid range: 0 - ( \ref CY_USBFS_DEV_DRV_NUM_EPS_MAX - 1 ). * * \return @@ -1281,7 +1281,7 @@ __STATIC_INLINE uint32_t Cy_USBFS_Dev_Drv_GetArbWriteAddr(USBFS_Type const *base * The pointer to the USBFS instance. * * \param endpoint -* Physical endpoint number. +* Physical endpoint number. * Valid range: 0 - ( \ref CY_USBFS_DEV_DRV_NUM_EPS_MAX - 1 ). * * \return @@ -1310,7 +1310,7 @@ __STATIC_INLINE uint32_t Cy_USBFS_Dev_Drv_GetArbReadAddr(USBFS_Type const *base, * The pointer to the USBFS instance. * * \param endpoint -* Physical endpoint number. +* Physical endpoint number. * Valid range: 0 - ( \ref CY_USBFS_DEV_DRV_NUM_EPS_MAX - 1 ). * * \param byte @@ -1333,7 +1333,7 @@ __STATIC_INLINE void Cy_USBFS_Dev_Drv_WriteData(USBFS_Type *base, uint32_t endpo * The pointer to the USBFS instance. * * \param endpoint -* Physical endpoint number. +* Physical endpoint number. * Valid range: 0 - ( \ref CY_USBFS_DEV_DRV_NUM_EPS_MAX - 1 ). * * \param halfword @@ -1356,7 +1356,7 @@ __STATIC_INLINE void Cy_USBFS_Dev_Drv_WriteData16(USBFS_Type *base, uint32_t end * The pointer to the USBFS instance. * * \param endpoint -* Physical endpoint number. +* Physical endpoint number. * Valid range: 0 - ( \ref CY_USBFS_DEV_DRV_NUM_EPS_MAX - 1 ). * * \return @@ -1379,7 +1379,7 @@ __STATIC_INLINE uint8_t Cy_USBFS_Dev_Drv_ReadData(USBFS_Type const *base, uint32 * The pointer to the USBFS instance. * * \param endpoint -* Physical endpoint number. +* Physical endpoint number. * Valid range: 0 - ( \ref CY_USBFS_DEV_DRV_NUM_EPS_MAX - 1 ). * * \return @@ -1402,7 +1402,7 @@ __STATIC_INLINE uint16_t Cy_USBFS_Dev_Drv_ReadData16(USBFS_Type const *base, uin * The pointer to the USBFS instance. * * \param endpoint -* Physical endpoint number. +* Physical endpoint number. * Valid range: 0 - ( \ref CY_USBFS_DEV_DRV_NUM_EPS_MAX - 1 ). * * \return @@ -1425,7 +1425,7 @@ __STATIC_INLINE volatile uint32_t * Cy_USBFS_Dev_Drv_GetDataRegAddr(USBFS_Type * * The pointer to the USBFS instance. * * \param endpoint -* Physical endpoint number. +* Physical endpoint number. * Valid range (0 - \ref CY_USBFS_DEV_DRV_NUM_EPS_MAX - 1). * * \return @@ -1442,20 +1442,20 @@ __STATIC_INLINE volatile uint32_t * Cy_USBFS_Dev_Drv_GetDataReg16Addr(USBFS_Type * Function Name: Cy_USBFS_Dev_Drv_FlushInBuffer ****************************************************************************//** * -* Flushes IN endpoint buffer: sets WA pointer (controlled by CPU/DMA) to equal +* Flushes IN endpoint buffer: sets WA pointer (controlled by CPU/DMA) to equal * RA (controlled by SIE; gets automatically reset on transfer completion). * * \param base * The pointer to the USBFS instance. * * \param endpoint -* Physical endpoint number. +* Physical endpoint number. * Valid range: 0 - ( \ref CY_USBFS_DEV_DRV_NUM_EPS_MAX - 1 ). * *******************************************************************************/ __STATIC_INLINE void Cy_USBFS_Dev_Drv_FlushInBuffer(USBFS_Type *base, uint32_t endpoint) { - Cy_USBFS_Dev_Drv_SetArbWriteAddr(base, endpoint, + Cy_USBFS_Dev_Drv_SetArbWriteAddr(base, endpoint, Cy_USBFS_Dev_Drv_GetArbReadAddr(base, endpoint)); } /** \} group_usbfs_drv_drv_reg_arbiter_data */ @@ -1479,7 +1479,7 @@ __STATIC_INLINE void Cy_USBFS_Dev_Drv_FlushInBuffer(USBFS_Type *base, uint32_t e * Defines whether endpoint direction is IN (true) or OUT (false). * * \param endpoint -* Physical endpoint number. +* Physical endpoint number. * Valid range: 0 - ( \ref CY_USBFS_DEV_DRV_NUM_EPS_MAX - 1 ). * *******************************************************************************/ @@ -1487,7 +1487,7 @@ __STATIC_INLINE void Cy_USBFS_Dev_Drv_SetEpType(USBFS_Type *base, bool inDirecti { uint32_t mask = (uint32_t) (0x1UL << endpoint); uint32_t regValue = CY_USBFS_DEV_READ_ODD(USBFS_DEV_EP_TYPE(base)); - + if (inDirection) { /* IN direction: clear bit */ @@ -1498,7 +1498,7 @@ __STATIC_INLINE void Cy_USBFS_Dev_Drv_SetEpType(USBFS_Type *base, bool inDirecti /* OUT direction: set bit */ regValue |= mask; } - + USBFS_DEV_EP_TYPE(base) = CY_USBFS_DEV_DRV_WRITE_ODD(regValue); } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_wdt.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_wdt.h index bc64ce9c77..2586e2493b 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_wdt.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_wdt.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_wdt.h -* \version 1.20 +* \version 1.30 * * This file provides constants and parameter values for the WDT driver. * @@ -27,13 +27,13 @@ * \addtogroup group_wdt * \{ * -* The Watchdog timer (WDT) has a 16-bit free-running up-counter. +* The Watchdog timer (WDT) has a 16-bit free-running up-counter. * -* The functions and other declarations used in this driver are in cy_wdt.h. -* You can include cy_pdl.h (ModusToolbox only) to get access to all functions -* and declarations in the PDL. +* The functions and other declarations used in this driver are in cy_wdt.h. +* You can include cy_pdl.h to get access to all functions +* and declarations in the PDL. * -* The WDT can issue counter match interrupts, and a device reset if its interrupts are not +* The WDT can issue counter match interrupts, and a device reset if its interrupts are not * handled. Use the Watchdog timer for two main purposes: * * The First use case is recovering from a CPU or firmware failure. @@ -43,110 +43,110 @@ * It is strongly recommended not to use the WDT for periodic interrupt * generation. However, if absolutely required, see information below. * -* A "reset cause" register exists, and the firmware should check this register +* A "reset cause" register exists, and the firmware should check this register * at a start-up. An appropriate action can be taken if a WRES reset is detected. * -* The user's firmware periodically resets the timeout period (clears or "feeds" +* The user's firmware periodically resets the timeout period (clears or "feeds" * the watchdog) before a timeout occurs. If the firmware fails to do so, that is -* considered to be a CPU crash or a firmware failure, and the reason for a +* considered to be a CPU crash or a firmware failure, and the reason for a * device reset. -* The WDT can generate an interrupt instead of a device reset. The Interrupt +* The WDT can generate an interrupt instead of a device reset. The Interrupt * Service Routine (ISR) can handle the interrupt either as a periodic interrupt, * or as an early indication of a firmware failure and respond accordingly. -* However, it is not recommended to use the WDT for periodic interrupt -* generation. The Multi-counter Watchdog Timers (MCWDT) can be used to generate +* However, it is not recommended to use the WDT for periodic interrupt +* generation. The Multi-counter Watchdog Timers (MCWDT) can be used to generate * periodic interrupts if such are presented in the device. * * Functional Description * -* The WDT generates an interrupt when the count value in the counter equals the +* The WDT generates an interrupt when the count value in the counter equals the * configured match value. * * Note that the counter is not reset on a match. In such case the WDT * reset period is: * WDT_Reset_Period = ILO_Period * (2*2^(16-IgnoreBits) + MatchValue); -* When the counter reaches a match value, it generates an interrupt and then -* keeps counting up until it overflows and rolls back to zero and reaches the +* When the counter reaches a match value, it generates an interrupt and then +* keeps counting up until it overflows and rolls back to zero and reaches the * match value again, at which point another interrupt is generated. * -* To use a WDT to generate a periodic interrupt, the match value should be -* incremented in the ISR. As a result, the next WDT interrupt is generated when +* To use a WDT to generate a periodic interrupt, the match value should be +* incremented in the ISR. As a result, the next WDT interrupt is generated when * the counter reaches a new match value. * -* You can also reduce the entire WDT counter period by -* specifying the number of most significant bits that are ignored in the WDT +* You can also reduce the entire WDT counter period by +* specifying the number of most significant bits that are ignored in the WDT * counter. For example, if the Cy_WDT_SetIgnoreBits() function is called with * parameter 3, the WDT counter becomes a 13-bit free-running up-counter. * -* Power Modes +* Power Modes * -* WDT can operate in all possible low power modes. -* Operation during Hibernate mode is possible because the logic and -* high-voltage internal low oscillator (ILO) are supplied by the external -* high-voltage supply (Vddd). The WDT can be configured to wake the device from +* WDT can operate in all possible low power modes. +* Operation during Hibernate mode is possible because the logic and +* high-voltage internal low oscillator (ILO) are supplied by the external +* high-voltage supply (Vddd). The WDT can be configured to wake the device from * Hibernate mode. * -* In CPU Active mode, an interrupt request from the WDT is sent to the -* CPU. In CPU Sleep, CPU Deep Sleep mode, the CPU subsystem +* In CPU Active mode, an interrupt request from the WDT is sent to the +* CPU. In CPU Sleep, CPU Deep Sleep mode, the CPU subsystem * is powered down, so the interrupt request from the WDT is sent directly to the -* WakeUp Interrupt Controller (WIC) which will then wake up the CPU. The +* WakeUp Interrupt Controller (WIC) which will then wake up the CPU. The * CPU then acknowledges the interrupt request and executes the ISR. * * Clock Source * -* The WDT is clocked by the ILO. The WDT must be disabled before disabling -* the ILO. According to the device datasheet, the ILO accuracy is +/-30% over -* voltage and temperature. This means that the timeout period may vary by 30% -* from the configured value. Appropriate margins should be added while -* configuring WDT intervals to make sure that unwanted device resets do not +* The WDT is clocked by the ILO. The WDT must be disabled before disabling +* the ILO. According to the device datasheet, the ILO accuracy is +/-30% over +* voltage and temperature. This means that the timeout period may vary by 30% +* from the configured value. Appropriate margins should be added while +* configuring WDT intervals to make sure that unwanted device resets do not * occur on some devices. -* +* * Refer to the device datasheet for more information on the oscillator accuracy. * * Register Locking * -* You can prevent accidental corruption of the WDT configuration by calling -* the Cy_WDT_Lock() function. When the WDT is locked, any writing to the WDT_*, -* CLK_ILO_CONFIG, CLK_SELECT.LFCLK_SEL, and CLK_TRIM_ILO_CTL registers is +* You can prevent accidental corruption of the WDT configuration by calling +* the Cy_WDT_Lock() function. When the WDT is locked, any writing to the WDT_*, +* CLK_ILO_CONFIG, CLK_SELECT.LFCLK_SEL, and CLK_TRIM_ILO_CTL registers is * ignored. -* Call the Cy_WDT_Unlock() function to allow registers modification, mentioned +* Call the Cy_WDT_Unlock() function to allow registers modification, mentioned * above. * -* Note that the WDT lock state is not retained during system Deep Sleep. After +* Note that the WDT lock state is not retained during system Deep Sleep. After * the wakeup from system Deep Sleep the WDT is locked. * * Clearing WDT * -* The ILO clock is asynchronous to the SysClk. Therefore it generally -* takes three ILO cycles for WDT register changes to come into effect. It is -* important to remember that a WDT should be cleared at least four cycles -* (3 + 1 for sure) before a timeout occurs, especially when small +* The ILO clock is asynchronous to the SysClk. Therefore it generally +* takes three ILO cycles for WDT register changes to come into effect. It is +* important to remember that a WDT should be cleared at least four cycles +* (3 + 1 for sure) before a timeout occurs, especially when small * match values / low-toggle bit numbers are used. * -* \warning It may happen that a WDT reset can be generated -* faster than a device start-up. To prevent this, calculate the +* \warning It may happen that a WDT reset can be generated +* faster than a device start-up. To prevent this, calculate the * start-up time and WDT reset time. The WDT reset time should be always greater * than device start-up time. * -* Reset Detection +* Reset Detection * -* Use the Cy_SysLib_GetResetReason() function to detect whether the WDT has +* Use the Cy_SysLib_GetResetReason() function to detect whether the WDT has * triggered a device reset. * * Interrupt Configuration * -* If the WDT is configured to generate an interrupt, pending -* interrupts must be cleared within the ISR (otherwise, the interrupt will be +* If the WDT is configured to generate an interrupt, pending +* interrupts must be cleared within the ISR (otherwise, the interrupt will be * generated continuously). -* A pending interrupt to the WDT block must be cleared by calling the -* Cy_WDT_ClearInterrupt() function. The call to the function will clear the +* A pending interrupt to the WDT block must be cleared by calling the +* Cy_WDT_ClearInterrupt() function. The call to the function will clear the * unhandled WDT interrupt counter. * -* Use the WDT ISR as a timer to trigger certain actions +* Use the WDT ISR as a timer to trigger certain actions * and to change a next WDT match value. * -* Ensure that the interrupts from the WDT are passed to the CPU to avoid -* unregistered interrupts. Unregistered WDT interrupts result in a continuous +* Ensure that the interrupts from the WDT are passed to the CPU to avoid +* unregistered interrupts. Unregistered WDT interrupts result in a continuous * device reset. To avoid this, call Cy_WDT_UnmaskInterrupt(). * After that, call the WDT API functions for interrupt * handling/clearing. @@ -154,24 +154,24 @@ * \section group_wdt_configuration Configuration Considerations * * To start the WDT, make sure that ILO is enabled. -* After the ILO is enabled, ensure that the WDT is unlocked and disabled by -* calling the Cy_WDT_Unlock() and Cy_WDT_Disable() functions. Set the WDT match -* value by calling Cy_WDT_SetMatch() with the required match value. If needed, -* set the ignore bits for reducing the WDT counter period by calling -* Cy_WDT_SetIgnoreBits() function. After the WDT configuration is set, +* After the ILO is enabled, ensure that the WDT is unlocked and disabled by +* calling the Cy_WDT_Unlock() and Cy_WDT_Disable() functions. Set the WDT match +* value by calling Cy_WDT_SetMatch() with the required match value. If needed, +* set the ignore bits for reducing the WDT counter period by calling +* Cy_WDT_SetIgnoreBits() function. After the WDT configuration is set, * call Cy_WDT_Enable(). * * \note Enable a WDT if the power supply can produce -* sudden brownout events that may compromise the CPU functionality. This +* sudden brownout events that may compromise the CPU functionality. This * ensures that the system can recover after a brownout. * -* When the WDT is used to protect against system crashes, the -* WDT interrupt should be cleared by a portion of the code that is not directly +* When the WDT is used to protect against system crashes, the +* WDT interrupt should be cleared by a portion of the code that is not directly * associated with the WDT interrupt. -* Otherwise, it is possible that the main firmware loop has crashed or is in an -* endless loop, but the WDT interrupt vector continues to operate and service +* Otherwise, it is possible that the main firmware loop has crashed or is in an +* endless loop, but the WDT interrupt vector continues to operate and service * the WDT. The user should: -* * Feed the watchdog by clearing the interrupt bit regularly in the main body +* * Feed the watchdog by clearing the interrupt bit regularly in the main body * of the firmware code. * * * Guarantee that the interrupt is cleared at least once every WDT period. @@ -191,6 +191,16 @@ *
VersionChangesReason for Change
2.20.1Minor documentation updates.Documentation enhancement.
2.20Fix configuration register value restoring in resume routine after +* Fix configuration register value restoring in resume routine after * Deep Sleep. * Fix issue that USB Device stops working in DMA modes after wake up +* Fix issue that USB Device stops working in DMA modes after wake up * from Deep Sleep. *
The LPM requests are ignored after wake up from Deep Sleep and the +* The LPM requests are ignored after wake up from Deep Sleep and the * host starts sending SOFs.Updated \ref Cy_USBFS_Dev_Drv_Resume function to restore LPM control * register after exit Deep Sleep. @@ -657,11 +662,11 @@ *
2.10Returns the data toggle bit into the previous state after detecting +* Returns the data toggle bit into the previous state after detecting * that the host is retrying an OUT transaction.The device was not able to recover the data toggle bit and -* continues communication through the endpoint after the host retried -* the OUT transaction (the retried transaction has the same toggle bit +* The device was not able to recover the data toggle bit and +* continues communication through the endpoint after the host retried +* the OUT transaction (the retried transaction has the same toggle bit * as the previous had). *
The list of changes to support the MBED-OS USB Device stack is provided below: * - Changed the processing of the control transfers. * - Updated the endpoint 0 service functions to update the endpoint 0 registers -* before the function returns. +* before the function returns. * - Moved the set-device-address processing into the driver from the middleware. -* - Changed the flow to configure endpoints after configuration change: -* unconfigure the device or remove all endpoints, add endpoints, configure +* - Changed the flow to configure endpoints after configuration change: +* unconfigure the device or remove all endpoints, add endpoints, configure * the device. Updated the functions: -* \ref Cy_USBFS_Dev_Drv_UnConfigureDevice, \ref Cy_USBFS_Dev_Drv_AddEndpoint -* and \ref Cy_USBFS_Dev_Drv_ConfigDevice. +* \ref Cy_USBFS_Dev_Drv_UnConfigureDevice, \ref Cy_USBFS_Dev_Drv_AddEndpoint +* and \ref Cy_USBFS_Dev_Drv_ConfigDevice. * Removed the Cy_USBFS_Dev_Drv_ConfigDeviceComplete function because it is no needed anymore. * - Added the functions: \ref Cy_USBFS_Dev_Drv_Ep0ReadResult(), \ref Cy_USBFS_Dev_Drv_SetAddress() -* and \ref Cy_USBFS_Dev_Drv_GetEp0MaxPacket(). +* and \ref Cy_USBFS_Dev_Drv_GetEp0MaxPacket(). * - Changed the function signature \ref Cy_USBFS_Dev_Drv_Ep0Stall(). -* - Obsolete function Cy_USBFS_Dev_Drv_GetEndpointStallState; the \ref +* - Obsolete function Cy_USBFS_Dev_Drv_GetEndpointStallState; the \ref * Cy_USBFS_Dev_Drv_GetEndpointState() updated to be used instead of the obsolete function. * - Reduced the time required to complete abort operation in function \ref Cy_USBFS_Dev_Drv_Abort. * Obsolete function Cy_USBFS_Dev_Drv_AbortComplete because entire abort operation is handled by @@ -689,14 +694,14 @@ * - Added the endpoint address argument to the \ref cy_cb_usbfs_dev_drv_ep_callback_t to simplify * endpoint transfer complete event processing for the MBED-OS USB Device stack. * Updated the driver to support the MBED-OS USB Device stack and Cypress +* Updated the driver to support the MBED-OS USB Device stack and Cypress * USB Device middleware.
1.10Fixed the \ref Cy_USBFS_Dev_Drv_Disable function to not disable DMA * in CPU mode.Calling this function triggers assert because DMA for endpoints is not +* Calling this function triggers assert because DMA for endpoints is not * initialized/used in the CPU mode.
* * +* +* +* +* +* +* +* +* +* * * * @@ -204,7 +214,7 @@ * * * -* * @@ -224,7 +234,7 @@ * * -* * * @@ -257,6 +267,10 @@ #include "cy_device_headers.h" #include "cy_device.h" #include "cy_syslib.h" +#if defined(CY_DEVICE_SECURE) + #include "cy_pra.h" +#endif /* defined(CY_DEVICE_SECURE) */ + #if defined(__cplusplus) extern "C" { @@ -276,7 +290,7 @@ extern "C" { #define CY_WDT_DRV_VERSION_MAJOR 1 /** The driver minor version */ -#define CY_WDT_DRV_VERSION_MINOR 20 +#define CY_WDT_DRV_VERSION_MINOR 30 /** The internal define for the first iteration of WDT unlocking */ #define CY_SRSS_WDT_LOCK_BIT0 ((uint32_t)0x01U << 30U) @@ -328,6 +342,7 @@ __STATIC_INLINE void Cy_WDT_Enable(void); __STATIC_INLINE void Cy_WDT_Disable(void); void Cy_WDT_Lock(void); void Cy_WDT_Unlock(void); +bool Cy_WDT_Locked(void); __STATIC_INLINE uint32_t Cy_WDT_GetCount(void); void Cy_WDT_SetMatch(uint32_t match); __STATIC_INLINE uint32_t Cy_WDT_GetMatch(void); @@ -376,7 +391,7 @@ __STATIC_INLINE void Cy_WDT_Disable(void) * * Reports an enable/disable state of the Watchdog timer. * -* \return +* \return * - true - if the timer is enabled * - false - if the timer is disabled * @@ -421,7 +436,7 @@ __STATIC_INLINE uint32_t Cy_WDT_GetCount(void) * Function Name: Cy_WDT_GetIgnoreBits ****************************************************************************//** * -* Reads the number of the most significant bits of the Watchdog timer that are +* Reads the number of the most significant bits of the Watchdog timer that are * not checked against the match. * * \return The number of the most significant bits. @@ -443,7 +458,11 @@ __STATIC_INLINE uint32_t Cy_WDT_GetIgnoreBits(void) *******************************************************************************/ __STATIC_INLINE void Cy_WDT_MaskInterrupt(void) { - SRSS_SRSS_INTR_MASK &= (uint32_t)(~ _VAL2FLD(SRSS_SRSS_INTR_MASK_WDT_MATCH, 1U)); + #if CY_CPU_CORTEX_M4 && defined(CY_DEVICE_SECURE) + CY_PRA_REG32_CLR_SET(CY_PRA_INDX_SRSS_SRSS_INTR_MASK, SRSS_SRSS_INTR_MASK_WDT_MATCH, 0U); + #else + SRSS_SRSS_INTR_MASK &= (uint32_t)(~ _VAL2FLD(SRSS_SRSS_INTR_MASK_WDT_MATCH, 1U)); + #endif /* CY_CPU_CORTEX_M4 && defined(CY_DEVICE_SECURE) */ } @@ -457,7 +476,11 @@ __STATIC_INLINE void Cy_WDT_MaskInterrupt(void) *******************************************************************************/ __STATIC_INLINE void Cy_WDT_UnmaskInterrupt(void) { - SRSS_SRSS_INTR_MASK |= _VAL2FLD(SRSS_SRSS_INTR_MASK_WDT_MATCH, 1U); + #if CY_CPU_CORTEX_M4 && defined(CY_DEVICE_SECURE) + CY_PRA_REG32_CLR_SET(CY_PRA_INDX_SRSS_SRSS_INTR_MASK, SRSS_SRSS_INTR_MASK_WDT_MATCH, 1U); + #else + SRSS_SRSS_INTR_MASK |= _VAL2FLD(SRSS_SRSS_INTR_MASK_WDT_MATCH, 1U); + #endif /* CY_CPU_CORTEX_M4 && defined(CY_DEVICE_SECURE) */ } /** \} group_wdt_functions */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_ble_clk.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_ble_clk.c index b9aefd8089..5ecbd59c53 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_ble_clk.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_ble_clk.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_ble_clk.c -* \version 3.40 +* \version 3.40.1 * * \brief * This driver provides the source code for API BLE ECO clock. @@ -43,7 +43,7 @@ extern "C" { static cy_en_ble_eco_status_t Cy_BLE_HAL_RcbRegRead(uint16_t addr, uint16_t *data); static cy_en_ble_eco_status_t Cy_BLE_HAL_RcbRegWrite(uint16_t addr, uint16_t data); static cy_en_ble_eco_status_t Cy_BLE_HAL_EcoSetTrim(uint32_t trim, uint32_t startUpTime); -static cy_en_ble_eco_status_t Cy_BLE_HAL_MxdRadioEnableClocks(cy_en_ble_eco_freq_t ecoFreq, +static cy_en_ble_eco_status_t Cy_BLE_HAL_MxdRadioEnableClocks(cy_en_ble_eco_freq_t ecoFreq, cy_en_ble_eco_sys_clk_div_t sysClkDiv); /******************************************************************************* @@ -202,7 +202,7 @@ static cy_en_ble_eco_status_t Cy_BLE_HAL_MxdRadioEnableClocks(cy_en_ble_eco_freq * CY_BLE_ECO_ALREADY_STARTED | The BLE ECO clock is already started. * CY_BLE_ECO_HARDWARE_ERROR | The RCB or BLE ECO operation failed. * -* \funcusage +* \funcusage * \snippet bleclk/snippet/main.c BLE ECO clock API: Cy_BLE_EcoConfigure() * * \sideeffect @@ -630,7 +630,7 @@ static cy_en_ble_eco_status_t Cy_BLE_HAL_RcbRegWrite(uint16_t addr, uint16_t dat BLE_RCB_INTR |= BLE_RCB_INTR_RCB_DONE_Msk; status = CY_BLE_ECO_SUCCESS; } - + return(status); } @@ -658,21 +658,21 @@ static cy_en_ble_eco_status_t Cy_BLE_HAL_EcoSetTrim(uint32_t trim, uint32_t star { uint16_t reg = CY_BLE_RF_DCXO_CFG_REG_VALUE; cy_en_ble_eco_status_t status; - + /* Load the new CAP TRIM value */ reg |= (uint16_t)((uint16_t)trim << CY_BLE_RF_DCXO_CFG_REG_DCXO_CAP_SHIFT); /* Write the new value to the register */ status = Cy_BLE_HAL_RcbRegWrite(CY_BLE_RF_DCXO_CFG_REG, reg); - + if(status == CY_BLE_ECO_SUCCESS) { /* Write the new value to the CFG2 register */ status = Cy_BLE_HAL_RcbRegWrite(CY_BLE_RF_DCXO_CFG2_REG, CY_BLE_RF_DCXO_CFG2_REG_VALUE); } - + Cy_SysLib_DelayUs((uint16_t)startUpTime * CY_BLE_ECO_SET_TRIM_DELAY_COEF); - + return(status); } @@ -682,7 +682,7 @@ static cy_en_ble_eco_status_t Cy_BLE_HAL_EcoSetTrim(uint32_t trim, uint32_t star ****************************************************************************//** * * Enables and configures radio clock. -* +* * \param ecoFreq : ECO Frequency. * sysClkDiv : System divider for ECO clock. * @@ -696,7 +696,7 @@ static cy_en_ble_eco_status_t Cy_BLE_HAL_EcoSetTrim(uint32_t trim, uint32_t star * CY_BLE_ECO_HARDWARE_ERROR | If RCB operation failed * *******************************************************************************/ -static cy_en_ble_eco_status_t Cy_BLE_HAL_MxdRadioEnableClocks(cy_en_ble_eco_freq_t ecoFreq, +static cy_en_ble_eco_status_t Cy_BLE_HAL_MxdRadioEnableClocks(cy_en_ble_eco_freq_t ecoFreq, cy_en_ble_eco_sys_clk_div_t sysClkDiv) { uint16_t temp; @@ -728,7 +728,7 @@ static cy_en_ble_eco_status_t Cy_BLE_HAL_MxdRadioEnableClocks(cy_en_ble_eco_freq { retries = CY_BLE_RCB_RETRIES; status = Cy_BLE_HAL_RcbRegRead(CY_BLE_PMU_PMU_CTRL_REG, &temp); - if((status == CY_BLE_ECO_SUCCESS) && ((temp & CY_BLE_MXD_RADIO_DIG_CLK_OUT_EN_VAL) == 0U)) + if((status == CY_BLE_ECO_SUCCESS) && ((temp & CY_BLE_MXD_RADIO_DIG_CLK_OUT_EN_VAL) == 0U)) { /* Enable digital ECO clock output from MXD Radio to BLESS */ do @@ -807,10 +807,10 @@ static cy_en_ble_eco_status_t Cy_BLE_HAL_MxdRadioEnableClocks(cy_en_ble_eco_freq } temp |= (uint16_t)(blerdDivider << CY_BLE_RF_DCXO_BUF_CFG_REG_CLK_DIV_SHIFT); - + /* Write the MXD Radio register */ status = Cy_BLE_HAL_RcbRegWrite(CY_BLE_RF_DCXO_BUF_CFG_REG, temp); - + /* Reduce BLESS divider by BLERD divider value */ ecoSysDivider = (uint16_t)sysClkDiv - blerdDivider; temp = (uint16_t)(ecoSysDivider & BLE_BLESS_XTAL_CLK_DIV_CONFIG_SYSCLK_DIV_Msk); @@ -819,7 +819,7 @@ static cy_en_ble_eco_status_t Cy_BLE_HAL_MxdRadioEnableClocks(cy_en_ble_eco_freq /* Set clock divider */ BLE_BLESS_XTAL_CLK_DIV_CONFIG = temp; } - + /* Update RADIO LDO trim values */ if((Cy_SysLib_GetDeviceRevision() != CY_SYSLIB_DEVICE_REV_0A) && (SFLASH->RADIO_LDO_TRIMS != 0U)) { @@ -827,39 +827,39 @@ static cy_en_ble_eco_status_t Cy_BLE_HAL_MxdRadioEnableClocks(cy_en_ble_eco_freq { status = Cy_BLE_HAL_RcbRegRead(CY_BLE_RF_LDO_CFG_REG, &temp); } - - if(status == CY_BLE_ECO_SUCCESS) + + if(status == CY_BLE_ECO_SUCCESS) { /* Update LDO_IF value */ temp &= (uint16_t)~((uint16_t) ((uint16_t)CY_BLE_RF_LDO_CFG_REG_LDO_IF_CFG_MASK << CY_BLE_RF_LDO_CFG_REG_LDO_IF_CFG_SHIFT)); temp |= (uint16_t)(((SFLASH->RADIO_LDO_TRIMS & SFLASH_RADIO_LDO_TRIMS_LDO_IF_Msk) >> SFLASH_RADIO_LDO_TRIMS_LDO_IF_Pos) << CY_BLE_RF_LDO_CFG_REG_LDO_IF_CFG_SHIFT); - + /* Update LDO_ACT value */ temp &= (uint16_t)~((uint16_t) ((uint16_t)CY_BLE_RF_LDO_CFG_REG_LDO_ACT_CFG_MASK << CY_BLE_RF_LDO_CFG_REG_LDO_ACT_CFG_SHIFT)); temp |= (uint16_t)(((SFLASH->RADIO_LDO_TRIMS & SFLASH_RADIO_LDO_TRIMS_LDO_ACT_Msk) >> SFLASH_RADIO_LDO_TRIMS_LDO_ACT_Pos) << CY_BLE_RF_LDO_CFG_REG_LDO_ACT_CFG_SHIFT); - + /* Update LDO_DIG value */ temp &= (uint16_t)~((uint16_t) ((uint16_t)CY_BLE_RF_LDO_CFG_REG_LDO10_CFG_MASK << CY_BLE_RF_LDO_CFG_REG_LDO10_CFG_SHIFT)); temp |= (uint16_t)(((SFLASH->RADIO_LDO_TRIMS & SFLASH_RADIO_LDO_TRIMS_LDO_DIG_Msk) >> SFLASH_RADIO_LDO_TRIMS_LDO_DIG_Pos) << CY_BLE_RF_LDO_CFG_REG_LDO10_CFG_SHIFT); - + status = Cy_BLE_HAL_RcbRegWrite(CY_BLE_RF_LDO_CFG_REG, temp); } - + if(status == CY_BLE_ECO_SUCCESS) { status = Cy_BLE_HAL_RcbRegRead(CY_BLE_RF_LDO_EN_REG, &temp); } - + if(status == CY_BLE_ECO_SUCCESS) - { + { /* Update LDO_LNA value */ temp &= (uint16_t)~(CY_BLE_RF_LDO_EN_REG_LDO_RF_CFG_MASK << CY_BLE_RF_LDO_EN_REG_LDO_RF_CFG_SHIFT); temp |= (uint16_t)(((SFLASH->RADIO_LDO_TRIMS & SFLASH_RADIO_LDO_TRIMS_LDO_LNA_Msk) >> - SFLASH_RADIO_LDO_TRIMS_LDO_LNA_Pos) << CY_BLE_RF_LDO_EN_REG_LDO_RF_CFG_SHIFT); - + SFLASH_RADIO_LDO_TRIMS_LDO_LNA_Pos) << CY_BLE_RF_LDO_EN_REG_LDO_RF_CFG_SHIFT); + status = Cy_BLE_HAL_RcbRegWrite(CY_BLE_RF_LDO_EN_REG, temp); } } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto.c index 60808613dc..1daa6feea8 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto.c -* \version 2.30.2 +* \version 2.30.3 * * \brief * Provides API implementation of the Cypress PDL Crypto driver. diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_aes_v1.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_aes_v1.c index 6ada7c2a40..cbdec5989b 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_aes_v1.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_aes_v1.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_aes_v1.c -* \version 2.30.2 +* \version 2.30.3 * * \brief * This file provides the source code fro the API for the AES method @@ -540,7 +540,7 @@ cy_en_crypto_status_t Cy_Crypto_Core_V1_Aes_Ctr(CRYPTO_Type *base, uint32_t *srcBuff = (uint32_t*)(&aesBuffers->block0); uint32_t *dstBuff = (uint32_t*)(&aesBuffers->block1); uint32_t *streamBuff = (uint32_t*)(&aesBuffers->block2); - + (void)streamBlock; /* Suppress warning */ Cy_Crypto_Core_V1_MemCpy(base, blockCounter, ivPtr, CY_CRYPTO_AES_BLOCK_SIZE); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_aes_v2.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_aes_v2.c index 1ce942cdaa..3438a10b5f 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_aes_v2.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_aes_v2.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_aes_v2.c -* \version 2.30.2 +* \version 2.30.3 * * \brief * This file provides the source code fro the API for the AES method @@ -493,7 +493,7 @@ cy_en_crypto_status_t Cy_Crypto_Core_V2_Aes_Ctr(CRYPTO_Type *base, uint64_t counter; uint32_t cnt; uint32_t i; - + (void)streamBlock; /* Suppress warning */ blockCounter[ 0] = (uint32_t) CY_CRYPTO_MERGE_BYTES(ivPtr[ 3], ivPtr[ 2], ivPtr[ 1], ivPtr[ 0]); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_cmac_v1.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_cmac_v1.c index eb8465fd83..538a110413 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_cmac_v1.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_cmac_v1.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_cmac_v1.c -* \version 2.30.2 +* \version 2.30.3 * * \brief * This file provides the source code to the API for the CMAC method diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_cmac_v2.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_cmac_v2.c index 01c3968667..b55a368ff6 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_cmac_v2.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_cmac_v2.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_cmac_v2.c -* \version 2.30.2 +* \version 2.30.3 * * \brief * This file provides the source code to the API for the CMAC method diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_crc_v1.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_crc_v1.c index 80a507e963..aa5aaf5f08 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_crc_v1.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_crc_v1.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_crc_v1.c -* \version 2.30.2 +* \version 2.30.3 * * \brief * This file provides the source code for CRC API diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_crc_v2.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_crc_v2.c index ab7deb2b97..4386f9592f 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_crc_v2.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_crc_v2.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_crc_v2.c -* \version 2.30.2 +* \version 2.30.3 * * \brief * This file provides the source code for CRC API diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_des_v1.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_des_v1.c index 90de924277..6fa6a2d522 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_des_v1.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_des_v1.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_des_v1.c -* \version 2.30.2 +* \version 2.30.3 * * \brief * This file provides the source code fro the API for the DES method diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_des_v2.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_des_v2.c index cafad7280a..a8d2904414 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_des_v2.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_des_v2.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_des_v2.c -* \version 2.30.2 +* \version 2.30.3 * * \brief * This file provides the source code fro the API for the DES method diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_ecc_domain_params.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_ecc_domain_params.c index 996627ccd3..e36c462a63 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_ecc_domain_params.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_ecc_domain_params.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_ecc_domain_params.c -* \version 2.30.2 +* \version 2.30.3 * * \brief * This file provides constant and parameters for the API for the ECC diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_ecc_ecdsa.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_ecc_ecdsa.c index 541cfed99e..0431b81392 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_ecc_ecdsa.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_ecc_ecdsa.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_ecc_ecdsa.c -* \version 2.30.2 +* \version 2.30.3 * * \brief * This file provides constant and parameters for the API for the ECC ECDSA diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_ecc_key_gen.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_ecc_key_gen.c index 70362e5604..04f72e4d2b 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_ecc_key_gen.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_ecc_key_gen.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_ecc_key_gen.c -* \version 2.30.2 +* \version 2.30.3 * * \brief * This file provides constant and parameters for the API for the ECC key diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_ecc_nist_p.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_ecc_nist_p.c index 0b350ad869..b2d4c28a69 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_ecc_nist_p.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_ecc_nist_p.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_ecc.h -* \version 2.30.2 +* \version 2.30.3 * * \brief * This file provides Elliptic Curve (EC) Scalar Multiplication using (X,Y)-only, @@ -643,7 +643,7 @@ static void Cy_Crypto_Core_EC_CS_MUL_Red_P521(CRYPTO_Type *base, uint32_t z, uin static void Cy_Crypto_Core_EC_CS_MulRed(CRYPTO_Type *base, uint32_t z, uint32_t x, uint32_t size) { (void)size; /* Suppress warning */ - + switch (eccMode) { case CY_CRYPTO_ECC_ECP_SECP192R1: @@ -1078,7 +1078,7 @@ static void Cy_Crypto_Core_EC_SM_MUL_Red_P521(CRYPTO_Type *base, uint32_t z, uin static void Cy_Crypto_Core_EC_SM_MulRed(CRYPTO_Type *base, uint32_t z, uint32_t x, uint32_t size) { (void)size; /* Suppress warning */ - + switch (eccMode) { case CY_CRYPTO_ECC_ECP_SECP192R1: Cy_Crypto_Core_EC_SM_MUL_Red_P192(base, z, x); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_hmac_v1.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_hmac_v1.c index 34613fd9d5..be5421c414 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_hmac_v1.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_hmac_v1.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_hmac_v1.c -* \version 2.30.2 +* \version 2.30.3 * * \brief * This file provides the source code to the API for the HMAC method diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_hmac_v2.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_hmac_v2.c index fbf0f6949a..cf7b160dbd 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_hmac_v2.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_hmac_v2.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_hmac_v2.c -* \version 2.30.2 +* \version 2.30.3 * * \brief * This file provides the source code to the API for the HMAC method diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_hw.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_hw.c index 24daee84bf..78e42da2fc 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_hw.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_hw.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_hw.c -* \version 2.30.2 +* \version 2.30.3 * * \brief * This file provides the source code to the API for the utils @@ -564,4 +564,3 @@ void Cy_Crypto_Core_InvertEndianness(void *inArrPtr, uint32_t byteSize) /* [] END OF FILE */ - diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_hw_v1.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_hw_v1.c index 95a2ff04b7..cb5116c838 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_hw_v1.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_hw_v1.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_hw_v1.c -* \version 2.30.2 +* \version 2.30.3 * * \brief * This file provides the source code for the HAL API for the diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_mem_v1.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_mem_v1.c index dc9abd965d..50aa836a6a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_mem_v1.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_mem_v1.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_mem_v1.c -* \version 2.30.2 +* \version 2.30.3 * * \brief * This file provides the source code to the API for the PRNG diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_mem_v2.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_mem_v2.c index b8f50b4fa0..e681cc6cc9 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_mem_v2.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_mem_v2.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_mem_v2.c -* \version 2.30.2 +* \version 2.30.3 * * \brief * This file provides the source code to the API for the PRNG diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_prng_v1.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_prng_v1.c index a767c6a3bc..ef3d8e6bff 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_prng_v1.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_prng_v1.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_prng_v1.c -* \version 2.30.2 +* \version 2.30.3 * * \brief * This file provides the source code to the API for the PRNG diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_prng_v2.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_prng_v2.c index 5398b04d71..fa598b740a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_prng_v2.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_prng_v2.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_prng_v2.c -* \version 2.30.2 +* \version 2.30.3 * * \brief * This file provides the source code to the API for the PRNG diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_rsa.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_rsa.c index e2f286d850..2aacb1020b 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_rsa.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_rsa.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_rsa.c -* \version 2.30.2 +* \version 2.30.3 * * \brief * This file provides the source code to the API to calculate diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_sha_v1.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_sha_v1.c index d907af770c..b7cdca0b37 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_sha_v1.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_sha_v1.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_sha_v1.c -* \version 2.30.2 +* \version 2.30.3 * * \brief * This file provides the source code to the API for the SHA method @@ -127,7 +127,7 @@ cy_en_crypto_status_t Cy_Crypto_Core_V1_Sha_Init(CRYPTO_Type *base, void *shaBuffers) { cy_en_crypto_status_t tmpResult = CY_CRYPTO_SUCCESS; - + (void)base; /* Suppress warning */ /* Initialization vectors for different modes of the SHA algorithm */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_sha_v2.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_sha_v2.c index f3834012c3..03cf0de33c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_sha_v2.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_sha_v2.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_sha_v2.c -* \version 2.30.2 +* \version 2.30.3 * * \brief * This file provides the source code to the API for the SHA method @@ -68,7 +68,7 @@ cy_en_crypto_status_t Cy_Crypto_Core_V2_Sha_Init(CRYPTO_Type *base, void *shaBuffers) { cy_en_crypto_status_t tmpResult = CY_CRYPTO_SUCCESS; - + (void)base; /* Suppress warning */ /* Initialization vectors for different modes of the SHA algorithm */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_trng_v1.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_trng_v1.c index 8a656bf1d4..a060d9a291 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_trng_v1.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_trng_v1.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_trng_v1.c -* \version 2.30.2 +* \version 2.30.3 * * \brief * This file provides the source code to the API for the TRNG diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_trng_v2.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_trng_v2.c index b64caafe3a..5fee8695cd 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_trng_v2.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_trng_v2.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_trng_v2.c -* \version 2.30.2 +* \version 2.30.3 * * \brief * This file provides the source code to the API for the TRNG diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_vu.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_vu.c index 64213fd5f4..34e7053e29 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_vu.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_core_vu.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_core_vu.c -* \version 2.30.2 +* \version 2.30.3 * * \brief * This file provides the source code to the API for the Vector Unit helpers @@ -223,4 +223,3 @@ void Cy_Crypto_Core_VU_RegInvertEndianness(CRYPTO_Type *base, uint32_t srcReg) /* [] END OF FILE */ - diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_server.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_server.c index 03aa848301..e24e7c24e1 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_server.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_crypto_server.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_crypto_server.c -* \version 2.30.2 +* \version 2.30.3 * * \brief * This file provides the source code to the API for Crypto Server diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_csd.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_csd.c index c43e41f3af..f0986ecd5a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_csd.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_csd.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_csd.c -* \version 1.10 +* \version 1.10.1 * * The source file of the CSD driver. * diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_ctb.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_ctb.c index 9caed72c4c..6b169b91d3 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_ctb.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_ctb.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_ctb.c -* \version 1.10.2 +* \version 1.20 * * \brief * Provides the public functions for the CTB driver. @@ -153,8 +153,8 @@ const cy_stc_ctb_fast_config_oa1_t Cy_CTB_Fast_Opamp1_Vdac_Ref_Pin5 = * * Initialize or restore the CTB and both opamps according to the * provided settings. Parameters are usually set only once, at initialization. -* -* \note This function call disables a whole CTB block, +* +* \note This function call disables a whole CTB block, * call \ref Cy_CTB_Enable after this function call. * * \param base @@ -238,10 +238,10 @@ cy_en_ctb_status_t Cy_CTB_Init(CTBM_Type *base, const cy_stc_ctb_config_t *confi CTBM_INTR_MASK(base) = (config->oa0CompIntrEn ? CTBM_INTR_MASK_COMP0_MASK_Msk : CY_CTB_DEINIT) \ | (config->oa1CompIntrEn ? CTBM_INTR_MASK_COMP1_MASK_Msk : CY_CTB_DEINIT); CTBM_INTR(base) = (CTBM_INTR_MASK_COMP0_MASK_Msk | CTBM_INTR_MASK_COMP1_MASK_Msk); - + CTBM_OA0_COMP_TRIM(base) = (uint32_t) ((config->oa0Mode == CY_CTB_MODE_OPAMP10X) ? CY_CTB_OPAMP_COMPENSATION_CAP_MAX: CY_CTB_OPAMP_COMPENSATION_CAP_MIN); - CTBM_OA1_COMP_TRIM(base) = (uint32_t) ((config->oa1Mode == CY_CTB_MODE_OPAMP10X) ? CY_CTB_OPAMP_COMPENSATION_CAP_MAX: CY_CTB_OPAMP_COMPENSATION_CAP_MIN); - + CTBM_OA1_COMP_TRIM(base) = (uint32_t) ((config->oa1Mode == CY_CTB_MODE_OPAMP10X) ? CY_CTB_OPAMP_COMPENSATION_CAP_MAX: CY_CTB_OPAMP_COMPENSATION_CAP_MIN); + if (config->configRouting) { CTBM_OA0_SW(base) = config->oa0SwitchCtrl; @@ -307,7 +307,7 @@ cy_en_ctb_status_t Cy_CTB_OpampInit(CTBM_Type *base, cy_en_ctb_opamp_sel_t opamp CY_ASSERT_L3(CY_CTB_COMPBYPASS(config->oaCompBypass)); CY_ASSERT_L3(CY_CTB_COMPHYST(config->oaCompHyst)); - CTBM_CTB_CTRL(base) = (uint32_t) config->deepSleep; + CY_REG32_CLR_SET(CTBM_CTB_CTRL(base), CTBM_CTB_CTRL_DEEPSLEEP_ON, (CY_CTB_DEEPSLEEP_DISABLE != config->deepSleep) ? 1UL : 0UL); /* The two opamp control registers are symmetrical */ oaResCtrl = (uint32_t) config->oaPower \ @@ -415,7 +415,10 @@ cy_en_ctb_status_t Cy_CTB_DeInit(CTBM_Type *base, bool deInitRouting) * - .oaCompBypass = \ref CY_CTB_COMP_BYPASS_SYNC * - .oaCompHyst = \ref CY_CTB_COMP_HYST_10MV * - .oaCompIntrEn = true - +* +* \note This function call disables a whole CTB block, +* call \ref Cy_CTB_Enable after this function call. +* * \param base * Pointer to structure describing registers * @@ -1377,4 +1380,3 @@ uint32_t Cy_CTB_CompGetStatus(const CTBM_Type *base, cy_en_ctb_opamp_sel_t compN #endif /* CY_IP_MXS40PASS */ /* [] END OF FILE */ - diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_ctdac.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_ctdac.c index 64bc58c1be..42dc8d516d 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_ctdac.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_ctdac.c @@ -1,12 +1,12 @@ /***************************************************************************//** * \file cy_ctdac.c -* \version 2.0 +* \version 2.0.1 * * Provides the public functions for the API for the CTDAC driver. * ******************************************************************************** * \copyright -* Copyright 2017-2019 Cypress Semiconductor Corporation +* Copyright 2017-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -735,4 +735,3 @@ cy_en_syspm_status_t Cy_CTDAC_DeepSleepCallback(cy_stc_syspm_callback_params_t * #endif /* CY_IP_MXS40PASS_CTDAC */ /* [] END OF FILE */ - diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_device.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_device.c index a3358e3dde..7d9e3a2748 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_device.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_device.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_device.c -* \version 2.10 +* \version 2.20 * * This file provides the definitions for core and peripheral block HW base * addresses, versions, and parameters. @@ -69,6 +69,7 @@ const cy_stc_device_t cy_deviceIpBlockCfgPSoC6_01 = /* srssNumClkpath */ 5U, /* srssNumPll */ 1U, /* srssNumHfroot */ 5U, + /* srssIsPiloPresent */ 1U, /* periClockNr */ 59U, /* smifDeviceNr */ 4U, /* passSarChannels */ 16U, @@ -177,6 +178,7 @@ const cy_stc_device_t cy_deviceIpBlockCfgPSoC6_02 = /* srssNumClkpath */ 6U, /* srssNumPll */ 2U, /* srssNumHfroot */ 6U, + /* srssIsPiloPresent */ 0U, /* periClockNr */ 54U, /* smifDeviceNr */ 4U, /* passSarChannels */ 16U, @@ -284,6 +286,7 @@ const cy_stc_device_t cy_deviceIpBlockCfgPSoC6_03 = /* srssNumClkpath */ 5U, /* srssNumPll */ 1U, /* srssNumHfroot */ 5U, + /* srssIsPiloPresent */ 0U, /* periClockNr */ 28U, /* smifDeviceNr */ 3U, /* passSarChannels */ 16U, @@ -391,6 +394,7 @@ const cy_stc_device_t cy_deviceIpBlockCfgPSoC6_04 = /* srssNumClkpath */ 5U, /* srssNumPll */ 1U, /* srssNumHfroot */ 4U, + /* srssIsPiloPresent */ 0U, /* periClockNr */ 28U, /* smifDeviceNr */ 3U, /* passSarChannels */ 16U, diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_dma.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_dma.c index cd8ac0c097..a12423a341 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_dma.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_dma.c @@ -1,13 +1,13 @@ /***************************************************************************//** * \file cy_dma.c -* \version 2.20 +* \version 2.20.1 * * \brief * The source code file for the DMA driver. * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -41,14 +41,14 @@ * * \return The status /ref cy_en_dma_status_t. * -* \funcusage +* \funcusage * \snippet dma/snippet/main.c snippet_Cy_DMA_Crc_Init * *******************************************************************************/ cy_en_dma_status_t Cy_DMA_Crc_Init(DW_Type * base, cy_stc_dma_crc_config_t const * crcConfig) { cy_en_dma_status_t ret = CY_DMA_BAD_PARAM; - + if((NULL != base) && (NULL != crcConfig) && CY_DW_CRC) { DW_CRC_CTL(base) = _BOOL2FLD(DW_V2_CRC_CTL_DATA_REVERSE, crcConfig->dataReverse) | @@ -84,7 +84,7 @@ cy_en_dma_status_t Cy_DMA_Crc_Init(DW_Type * base, cy_stc_dma_crc_config_t const * \return * The status /ref cy_en_dma_status_t. * -* \funcusage +* \funcusage * \snippet dma/snippet/main.c snippet_Cy_DMA_Enable * *******************************************************************************/ @@ -199,7 +199,7 @@ cy_en_dma_status_t Cy_DMA_Descriptor_Init(cy_stc_dma_descriptor_t * descriptor, * \param descriptor * The descriptor structure instance declared by the user/component. * -* \funcusage +* \funcusage * \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_Deinit * *******************************************************************************/ @@ -233,7 +233,7 @@ void Cy_DMA_Descriptor_DeInit(cy_stc_dma_descriptor_t * descriptor) * \return * The status /ref cy_en_dma_status_t. * -* \funcusage +* \funcusage * \snippet dma/snippet/main.c snippet_Cy_DMA_Enable * *******************************************************************************/ @@ -242,12 +242,12 @@ cy_en_dma_status_t Cy_DMA_Channel_Init(DW_Type * base, uint32_t channel, cy_stc_ cy_en_dma_status_t ret = CY_DMA_BAD_PARAM; if ((NULL != base) && - (NULL != channelConfig) && + (NULL != channelConfig) && (NULL != channelConfig->descriptor) && (CY_DMA_IS_CH_NR_VALID(base, channel))) { CY_ASSERT_L2(CY_DMA_IS_PRIORITY_VALID(channelConfig->priority)); - + /* Set the current descriptor */ Cy_DMA_Channel_SetDescriptor(base, channel, channelConfig->descriptor); @@ -276,14 +276,14 @@ cy_en_dma_status_t Cy_DMA_Channel_Init(DW_Type * base, uint32_t channel, cy_stc_ * \param channel * A channel number. * -* \funcusage +* \funcusage * \snippet dma/snippet/main.c snippet_Cy_DMA_Disable * *******************************************************************************/ void Cy_DMA_Channel_DeInit(DW_Type * base, uint32_t channel) { CY_ASSERT_L1(CY_DMA_IS_CH_NR_VALID(base, channel)); - + DW_CH_CTL(base, channel) = 0UL; DW_CH_IDX(base, channel) = 0UL; DW_CH_CURR_PTR(base, channel) = 0UL; @@ -299,8 +299,8 @@ void Cy_DMA_Channel_DeInit(DW_Type * base, uint32_t channel) * * Based on the descriptor type, the offset of the address for the next descriptor may * vary. For the single-transfer descriptor type, this register is at offset 0x0c. -* For the 1D-transfer descriptor type, this register is at offset 0x10. -* For the 2D-transfer descriptor type, this register is at offset 0x14. +* For the 1D-transfer descriptor type, this register is at offset 0x10. +* For the 2D-transfer descriptor type, this register is at offset 0x14. * * \param descriptor * The descriptor structure instance declared by the user/component. @@ -308,12 +308,12 @@ void Cy_DMA_Channel_DeInit(DW_Type * base, uint32_t channel) * \param nextDescriptor * The pointer to the next descriptor. * -* \funcusage +* \funcusage * \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_SetterFunctions * *******************************************************************************/ void Cy_DMA_Descriptor_SetNextDescriptor(cy_stc_dma_descriptor_t * descriptor, cy_stc_dma_descriptor_t const * nextDescriptor) -{ +{ switch((cy_en_dma_descriptor_type_t) _FLD2VAL(CY_DMA_CTL_TYPE, descriptor->ctl)) { case CY_DMA_SINGLE_TRANSFER: @@ -324,11 +324,11 @@ void Cy_DMA_Descriptor_SetNextDescriptor(cy_stc_dma_descriptor_t * descriptor, c case CY_DMA_1D_TRANSFER: descriptor->yCtl = (uint32_t)nextDescriptor; break; - + case CY_DMA_2D_TRANSFER: descriptor->nextPtr = (uint32_t)nextDescriptor; break; - + default: /* Unsupported type of descriptor */ break; @@ -344,8 +344,8 @@ void Cy_DMA_Descriptor_SetNextDescriptor(cy_stc_dma_descriptor_t * descriptor, c * * Based on the descriptor type, the offset of the address for the next descriptor may * vary. For a single-transfer descriptor type, this register is at offset 0x0c. -* For the 1D-transfer descriptor type, this register is at offset 0x10. -* For the 2D-transfer descriptor type, this register is at offset 0x14. +* For the 1D-transfer descriptor type, this register is at offset 0x10. +* For the 2D-transfer descriptor type, this register is at offset 0x14. * * \param descriptor * The descriptor structure instance declared by the user/component. @@ -353,7 +353,7 @@ void Cy_DMA_Descriptor_SetNextDescriptor(cy_stc_dma_descriptor_t * descriptor, c * \return * The pointer to the next descriptor. * -* \funcusage +* \funcusage * \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_GetterFunctions * *******************************************************************************/ @@ -371,16 +371,16 @@ cy_stc_dma_descriptor_t * Cy_DMA_Descriptor_GetNextDescriptor(cy_stc_dma_descrip case CY_DMA_1D_TRANSFER: retVal = (cy_stc_dma_descriptor_t*) descriptor->yCtl; break; - + case CY_DMA_2D_TRANSFER: retVal = (cy_stc_dma_descriptor_t*) descriptor->nextPtr; break; - + default: /* An unsupported type of the descriptor */ break; } - + return (retVal); } @@ -392,29 +392,29 @@ cy_stc_dma_descriptor_t * Cy_DMA_Descriptor_GetNextDescriptor(cy_stc_dma_descrip * Sets the descriptor's type for the specified descriptor. * Moves the next descriptor register value into the proper place in accordance * to the actual descriptor type. -* During the descriptor's type changing, the Xloop and Yloop settings, such as -* data count and source/destination increment (i.e. the content of the -* xCtl and yCtl descriptor registers) might be lost (overridden by the +* During the descriptor's type changing, the Xloop and Yloop settings, such as +* data count and source/destination increment (i.e. the content of the +* xCtl and yCtl descriptor registers) might be lost (overridden by the * next descriptor value) because of the different descriptor registers structures * for different descriptor types. Carefully set up the Xloop * (and Yloop, if used) data count and source/destination increment if the -* descriptor type is changed from a simpler to a more complicated type +* descriptor type is changed from a simpler to a more complicated type * ("single transfer" -> "1D", "1D" -> "2D", etc.). -* +* * \param descriptor * The descriptor structure instance declared by the user/component. * -* \param descriptorType +* \param descriptorType * The descriptor type \ref cy_en_dma_descriptor_type_t. * -* \funcusage +* \funcusage * \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_SetterFunctions * *******************************************************************************/ void Cy_DMA_Descriptor_SetDescriptorType(cy_stc_dma_descriptor_t * descriptor, cy_en_dma_descriptor_type_t descriptorType) { CY_ASSERT_L3(CY_DMA_IS_TYPE_VALID(descriptorType)); - + if ((CY_DMA_CRC_TRANSFER != descriptorType) || CY_DW_CRC) { if (descriptorType != Cy_DMA_Descriptor_GetDescriptorType(descriptor)) /* Do not perform if the type is not changed */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_dmac.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_dmac.c index a67ed711f6..f546c33076 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_dmac.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_dmac.c @@ -1,13 +1,13 @@ /***************************************************************************//** * \file cy_dmac.c -* \version 1.10 +* \version 1.10.1 * * \brief * The source code file for the DMAC driver. * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -46,7 +46,7 @@ * \return * The status /ref cy_en_dmac_status_t. * -* \funcusage +* \funcusage * \snippet dmac/snippet/main.c snippet_Cy_DMAC_Enable * *******************************************************************************/ @@ -65,7 +65,7 @@ cy_en_dmac_status_t Cy_DMAC_Descriptor_Init(cy_stc_dmac_descriptor_t * descripto CY_ASSERT_L3(CY_DMAC_IS_CHANNEL_STATE_VALID(config->channelState)); CY_ASSERT_L3(CY_DMAC_IS_DATA_SIZE_VALID(config->dataSize)); CY_ASSERT_L3(CY_DMAC_IS_TYPE_VALID(config->descriptorType)); - + descriptor->ctl = _VAL2FLD(DMAC_CH_V2_DESCR_CTL_WAIT_FOR_DEACT, config->retrigger) | _VAL2FLD(DMAC_CH_V2_DESCR_CTL_INTR_TYPE, config->interruptType) | @@ -129,7 +129,7 @@ cy_en_dmac_status_t Cy_DMAC_Descriptor_Init(cy_stc_dmac_descriptor_t * descripto * \param descriptor * The descriptor structure instance. * -* \funcusage +* \funcusage * \snippet dmac/snippet/main.c snippet_Cy_DMAC_Descriptor_Deinit * *******************************************************************************/ @@ -165,7 +165,7 @@ void Cy_DMAC_Descriptor_DeInit(cy_stc_dmac_descriptor_t * descriptor) * \return * The status /ref cy_en_dmac_status_t. * -* \funcusage +* \funcusage * \snippet dmac/snippet/main.c snippet_Cy_DMAC_Enable * *******************************************************************************/ @@ -176,7 +176,7 @@ cy_en_dmac_status_t Cy_DMAC_Channel_Init(DMAC_Type * base, uint32_t channel, cy_ if ((NULL != base) && (CY_DMAC_IS_CH_NR_VALID(channel)) && (NULL != config) && (NULL != config->descriptor)) { CY_ASSERT_L2(CY_DMAC_IS_PRIORITY_VALID(config->priority)); - + /* Set the current descriptor */ DMAC_CH_CURR(base, channel) = (uint32_t)config->descriptor; @@ -203,14 +203,14 @@ cy_en_dmac_status_t Cy_DMAC_Channel_Init(DMAC_Type * base, uint32_t channel, cy_ * \param channel * A channel number. * -* \funcusage +* \funcusage * \snippet dmac/snippet/main.c snippet_Cy_DMAC_Disable * *******************************************************************************/ void Cy_DMAC_Channel_DeInit(DMAC_Type * base, uint32_t channel) { CY_ASSERT_L1(CY_DMAC_IS_CH_NR_VALID(channel)); - + DMAC_CH_CTL(base, channel) = 0UL; DMAC_CH_CURR(base, channel) = 0UL; DMAC_CH_INTR_MASK(base, channel) = 0UL; @@ -330,14 +330,14 @@ void Cy_DMAC_Descriptor_SetXloopDataCount(cy_stc_dmac_descriptor_t * descriptor, * \param nextDescriptor * The pointer to the next descriptor. * -* \funcusage +* \funcusage * \snippet dmac/snippet/main.c snippet_Cy_DMAC_Descriptor_SetterFunctions * *******************************************************************************/ void Cy_DMAC_Descriptor_SetNextDescriptor(cy_stc_dmac_descriptor_t * descriptor, cy_stc_dmac_descriptor_t const * nextDescriptor) { CY_ASSERT_L1(NULL != descriptor); - + switch((cy_en_dmac_descriptor_type_t)_FLD2VAL(DMAC_CH_V2_DESCR_CTL_DESCR_TYPE, descriptor->ctl)) { case CY_DMAC_SINGLE_TRANSFER: @@ -345,7 +345,7 @@ void Cy_DMAC_Descriptor_SetNextDescriptor(cy_stc_dmac_descriptor_t * descriptor, /* The next pointer is on the same offset for single and scatter descriptors */ ((cy_stc_dmac_dscr_single_t*)descriptor)->nextPtr = (uint32_t)nextDescriptor; break; - + case CY_DMAC_MEMORY_COPY: ((cy_stc_dmac_dscr_memcpy_t*)descriptor)->nextPtr = (uint32_t)nextDescriptor; break; @@ -353,7 +353,7 @@ void Cy_DMAC_Descriptor_SetNextDescriptor(cy_stc_dmac_descriptor_t * descriptor, case CY_DMAC_1D_TRANSFER: ((cy_stc_dmac_dscr_1d_t*)descriptor)->nextPtr = (uint32_t)nextDescriptor; break; - + case CY_DMAC_2D_TRANSFER: ((cy_stc_dmac_dscr_2d_t*)descriptor)->nextPtr = (uint32_t)nextDescriptor; break; @@ -384,14 +384,14 @@ void Cy_DMAC_Descriptor_SetNextDescriptor(cy_stc_dmac_descriptor_t * descriptor, * \return * The pointer to the next descriptor. * -* \funcusage +* \funcusage * \snippet dmac/snippet/main.c snippet_Cy_DMAC_Descriptor_GetterFunctions * *******************************************************************************/ cy_stc_dmac_descriptor_t * Cy_DMAC_Descriptor_GetNextDescriptor(cy_stc_dmac_descriptor_t const * descriptor) { uint32_t retVal = 0UL; - + switch((cy_en_dmac_descriptor_type_t)_FLD2VAL(DMAC_CH_V2_DESCR_CTL_DESCR_TYPE, descriptor->ctl)) { case CY_DMAC_SINGLE_TRANSFER: @@ -399,7 +399,7 @@ cy_stc_dmac_descriptor_t * Cy_DMAC_Descriptor_GetNextDescriptor(cy_stc_dmac_desc /* The next pointer is on the same offset for single and scatter descriptors */ retVal = ((cy_stc_dmac_dscr_single_t const*)descriptor)->nextPtr; break; - + case CY_DMAC_MEMORY_COPY: retVal = ((cy_stc_dmac_dscr_memcpy_t const*)descriptor)->nextPtr; break; @@ -416,7 +416,7 @@ cy_stc_dmac_descriptor_t * Cy_DMAC_Descriptor_GetNextDescriptor(cy_stc_dmac_desc /* An unsupported type of the descriptor */ break; } - + return ((cy_stc_dmac_descriptor_t*)retVal); } @@ -426,7 +426,7 @@ cy_stc_dmac_descriptor_t * Cy_DMAC_Descriptor_GetNextDescriptor(cy_stc_dmac_desc ****************************************************************************//** * * Sets the descriptor's type for the specified descriptor. -* Moves the next descriptor pointer and X data count values into the proper +* Moves the next descriptor pointer and X data count values into the proper * offset in accordance to the actual descriptor type. * * During the descriptor's type change, carefully set up the settings starting @@ -434,21 +434,21 @@ cy_stc_dmac_descriptor_t * Cy_DMAC_Descriptor_GetNextDescriptor(cy_stc_dmac_desc * structure. This is because the content of the descriptor registers might be * lost/overridden by other descriptor settings due to the * different registers structure for different descriptor types. -* +* * \param descriptor * The descriptor structure instance. * -* \param descriptorType +* \param descriptorType * The descriptor type \ref cy_en_dmac_descriptor_type_t. * -* \funcusage +* \funcusage * \snippet dmac/snippet/main.c snippet_Cy_DMAC_Descriptor_SetterFunctions * *******************************************************************************/ void Cy_DMAC_Descriptor_SetDescriptorType(cy_stc_dmac_descriptor_t * descriptor, cy_en_dmac_descriptor_type_t descriptorType) { CY_ASSERT_L3(CY_DMAC_IS_TYPE_VALID(descriptorType)); - + if (descriptorType != Cy_DMAC_Descriptor_GetDescriptorType(descriptor)) /* Do not perform if the type is not changed */ { /* Store the current nextDescriptor pointer. */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_efuse.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_efuse.c index 55e985f761..5e95338775 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_efuse.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_efuse.c @@ -1,13 +1,13 @@ /***************************************************************************//** * \file cy_efuse.c -* \version 1.10.2 +* \version 1.10.3 * * \brief * Provides API implementation of the eFuse driver. * ******************************************************************************** * \copyright -* Copyright 2017-2019 Cypress Semiconductor Corporation +* Copyright 2017-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -63,11 +63,11 @@ static cy_en_efuse_status_t ProcessOpcode(void); * * The EFUSE_EFUSE_NR macro is defined in the series-specific header file, e.g * \e \/devices/include/psoc6_01_config.\e h -* -* \param bitVal +* +* \param bitVal * The pointer to the location to store the bit value. * -* \return +* \return * \ref cy_en_efuse_status_t * * \funcusage @@ -79,16 +79,16 @@ static cy_en_efuse_status_t ProcessOpcode(void); cy_en_efuse_status_t Cy_EFUSE_GetEfuseBit(uint32_t bitNum, bool *bitVal) { cy_en_efuse_status_t result = CY_EFUSE_BAD_PARAM; - + if (bitVal != NULL) { uint32_t offset = bitNum / CY_EFUSE_BITS_PER_BYTE; uint8_t byteVal; *bitVal = false; - + /* Read the eFuse byte */ result = Cy_EFUSE_GetEfuseByte(offset, &byteVal); - + if (result == CY_EFUSE_SUCCESS) { uint32_t bitPos = bitNum % CY_EFUSE_BITS_PER_BYTE; @@ -124,7 +124,7 @@ cy_en_efuse_status_t Cy_EFUSE_GetEfuseBit(uint32_t bitNum, bool *bitVal) * \param byteVal * The pointer to the location to store eFuse data. * -* \return +* \return * \ref cy_en_efuse_status_t * * \funcusage @@ -136,20 +136,20 @@ cy_en_efuse_status_t Cy_EFUSE_GetEfuseBit(uint32_t bitNum, bool *bitVal) cy_en_efuse_status_t Cy_EFUSE_GetEfuseByte(uint32_t offset, uint8_t *byteVal) { cy_en_efuse_status_t result = CY_EFUSE_BAD_PARAM; - + if (byteVal != NULL) { /* Prepare opcode before calling the SROM API */ opcode = CY_EFUSE_OPCODE_READ_FUSE_BYTE | (offset << CY_EFUSE_OPCODE_OFFSET_Pos); - + /* Send the IPC message */ if (Cy_IPC_Drv_SendMsgPtr(CY_EFUSE_IPC_STRUCT, CY_EFUSE_IPC_NOTIFY_STRUCT0, (void*)&opcode) == CY_IPC_DRV_SUCCESS) - { + { /* Wait until the IPC structure is locked */ while(Cy_IPC_Drv_IsLockAcquired(CY_EFUSE_IPC_STRUCT) != false) { } - + /* The result of the SROM API call is returned to the opcode variable */ if ((opcode & CY_EFUSE_OPCODE_STS_Msk) == CY_EFUSE_OPCODE_SUCCESS) { @@ -199,7 +199,7 @@ uint32_t Cy_EFUSE_GetExternalStatus(void) * Function Name: ProcessOpcode ****************************************************************************//** * -* Converts System Call returns to the eFuse driver return defines. If +* Converts System Call returns to the eFuse driver return defines. If * an unknown error was returned, the error code can be accessed via the * Cy_EFUSE_GetExternalStatus() function. * diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_flash.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_flash.c index 7d27558521..013ddea6b1 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_flash.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_flash.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_flash.c -* \version 3.30.5 +* \version 3.40 * * \brief * Provides the public functions for the API for the PSoC 6 Flash Driver. @@ -30,6 +30,9 @@ #include "cy_ipc_pipe.h" #include "cy_device.h" #include "cy_syslib.h" +#if defined(CY_DEVICE_SECURE) + #include "cy_pra.h" +#endif /* defined(CY_DEVICE_SECURE) */ /*************************************** @@ -184,7 +187,7 @@ typedef cy_en_flashdrv_status_t (*Cy_Flash_Proxy)(cy_stc_flash_context_t *contex #endif static void Cy_Flash_NotifyHandler(uint32_t * msgPtr); - + static cy_stc_flash_notify_t * ipcWaitMessage; #else @@ -194,7 +197,7 @@ typedef cy_en_flashdrv_status_t (*Cy_Flash_Proxy)(cy_stc_flash_context_t *contex #define CY_FLASH_START_PROGRAM_DELAY (CY_FLASH_NO_DELAY) /** Delay time for Start Erase function in uS with corrective time */ #define CY_FLASH_START_ERASE_DELAY (CY_FLASH_NO_DELAY) - + #endif /* !defined(CY_FLASH_RWW_DRV_SUPPORT_DISABLED) */ /** \endcond */ @@ -216,24 +219,24 @@ static volatile cy_stc_flash_context_t flashContext; * Initiates all needed prerequisites to support flash erase/write. * Should be called from each core. Defines the address of the message structure. * - * Requires a call to Cy_IPC_Sema_Init(), Cy_IPC_Pipe_Config() and + * Requires a call to Cy_IPC_Sema_Init(), Cy_IPC_Pipe_Config() and * Cy_IPC_Pipe_Init() functions before use. * - * This function is called in the Cy_Flash_Init() function - see the + * This function is called in the Cy_Flash_Init() function - see the * \ref Cy_Flash_Init usage considerations. * *******************************************************************************/ void Cy_Flash_InitExt(cy_stc_flash_notify_t *ipcWaitMessageAddr) { ipcWaitMessage = ipcWaitMessageAddr; - + if(ipcWaitMessage != NULL) { ipcWaitMessage->clientID = CY_FLASH_IPC_CLIENT_ID; ipcWaitMessage->pktType = CY_FLASH_ENTER_WAIT_LOOP; - ipcWaitMessage->intrRelMask = 0U; - } - + ipcWaitMessage->intrRelMask = 0U; + } + if (cy_device->flashRwwRequired != 0U) { #if (CY_CPU_CORTEX_M4) @@ -254,8 +257,8 @@ static volatile cy_stc_flash_context_t flashContext; } } } - - + + /******************************************************************************* * Function Name: Cy_Flash_NotifyHandler ****************************************************************************//** @@ -269,7 +272,9 @@ static volatile cy_stc_flash_context_t flashContext; #endif static void Cy_Flash_NotifyHandler(uint32_t * msgPtr) { + #if !((CY_CPU_CORTEX_M0P) && (defined(CY_DEVICE_SECURE))) uint32_t intr; + #endif /* !((CY_CPU_CORTEX_M0P) && (defined(CY_DEVICE_SECURE))) */ static uint32_t semaIndex; static uint32_t semaMask; static volatile uint32_t *semaPtr; @@ -279,7 +284,9 @@ static volatile cy_stc_flash_context_t flashContext; if (CY_FLASH_ENTER_WAIT_LOOP == ipcMsgPtr->pktType) { + #if !((CY_CPU_CORTEX_M0P) && (defined(CY_DEVICE_SECURE))) intr = Cy_SysLib_EnterCriticalSection(); + #endif /* !((CY_CPU_CORTEX_M0P) && (defined(CY_DEVICE_SECURE))) */ /* Get pointer to structure */ semaStruct = (cy_stc_ipc_sema_t *)Cy_IPC_Drv_ReadDataValue(Cy_IPC_Drv_GetIpcBaseAddress(CY_IPC_CHAN_SEMA)); @@ -297,7 +304,9 @@ static volatile cy_stc_flash_context_t flashContext; { } + #if !((CY_CPU_CORTEX_M0P) && (defined(CY_DEVICE_SECURE))) Cy_SysLib_ExitCriticalSection(intr); + #endif /* !((CY_CPU_CORTEX_M0P) && (defined(CY_DEVICE_SECURE))) */ } } CY_RAMFUNC_END @@ -311,22 +320,22 @@ static volatile cy_stc_flash_context_t flashContext; * Initiates all needed prerequisites to support flash erase/write. * Should be called from each core. * -* Requires a call to Cy_IPC_Sema_Init(), Cy_IPC_Pipe_Config() and +* Requires a call to Cy_IPC_Sema_Init(), Cy_IPC_Pipe_Config() and * Cy_IPC_Pipe_Init() functions before use. * * This function is called in the SystemInit() function, for proper flash write * and erase operations. If the default startup file is not used, or the function -* SystemInit() is not called in your project, ensure to perform the following steps +* SystemInit() is not called in your project, ensure to perform the following steps * before any flash or EmEEPROM write/erase operations: * \snippet flash/snippet/main.c Flash Initialization * *******************************************************************************/ void Cy_Flash_Init(void) { - #if !defined(CY_FLASH_RWW_DRV_SUPPORT_DISABLED) + #if !defined(CY_FLASH_RWW_DRV_SUPPORT_DISABLED) CY_SECTION(".cy_sharedmem") CY_ALIGN(4) static cy_stc_flash_notify_t ipcWaitMessageStc; - + Cy_Flash_InitExt(&ipcWaitMessageStc); #endif /* !defined(CY_FLASH_RWW_DRV_SUPPORT_DISABLED) */ } @@ -364,7 +373,7 @@ static cy_en_flashdrv_status_t Cy_Flash_SendCmd(uint32_t mode, uint32_t microsec #if !defined(CY_FLASH_RWW_DRV_SUPPORT_DISABLED) uint32_t intr; uint32_t semaTryCount = 0uL; - + if (cy_device->flashRwwRequired != 0U) { /* Check for active core is CM0+, or CM4 on single core device */ @@ -372,13 +381,13 @@ static cy_en_flashdrv_status_t Cy_Flash_SendCmd(uint32_t mode, uint32_t microsec bool isPeerCoreEnabled = (CY_SYS_CM4_STATUS_ENABLED == Cy_SysGetCM4Status()); #else bool isPeerCoreEnabled = false; - + if (SFLASH_SINGLE_CORE == 0U) { isPeerCoreEnabled = true; } #endif - + if (!isPeerCoreEnabled) { result = CY_FLASH_DRV_SUCCESS; @@ -444,7 +453,7 @@ static cy_en_flashdrv_status_t Cy_Flash_SendCmd(uint32_t mode, uint32_t microsec /* SysClk measurement counter is busy */ result = CY_FLASH_DRV_IPC_BUSY; } - + if (isPeerCoreEnabled) { while (CY_IPC_SEMA_SUCCESS != Cy_IPC_Sema_Clear(CY_FLASH_WAIT_SEMA, true)) @@ -557,7 +566,7 @@ CY_RAMFUNC_END #define CY_FLASH_FINAL_STAGE_DELAY_TICKS (1000UL) #define CY_FLASH_FINAL_STAGE_DELAY (130UL + CY_FLASH_DELAY_CORRECTIVE(CY_FLASH_FINAL_STAGE_DELAY_TICKS)) - + /******************************************************************************* * Function Name: Cy_Flash_ResumeIrqHandler ****************************************************************************//** @@ -575,7 +584,11 @@ CY_RAMFUNC_END IPC_STRUCT_Type * locIpcBase = Cy_IPC_Drv_GetIpcBaseAddress(CY_IPC_CHAN_CYPIPE_EP0); uint32_t bookmark; - bookmark = FLASHC_FM_CTL_BOOKMARK & 0xffffUL; + #if ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) + bookmark = CY_PRA_REG32_GET(CY_PRA_INDX_FLASHC_FM_CTL_BOOKMARK) & 0xffffUL; + #else + bookmark = FLASHC_FM_CTL_BOOKMARK & 0xffffUL; + #endif /* ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) */ uint32_t intr = Cy_SysLib_EnterCriticalSection(); @@ -617,7 +630,7 @@ CY_RAMFUNC_END * detect circuits should be configured to generate an interrupt instead of a * reset. Otherwise, portions of flash may undergo unexpected changes. * -* \param rowAddr Address of the flash row number. +* \param rowAddr Address of the flash row number. * The Read-while-Write violation occurs when the flash read operation is * initiated in the same flash sector where the flash write operation is * performing. Refer to the device datasheet for the details. @@ -668,12 +681,12 @@ cy_en_flashdrv_status_t Cy_Flash_EraseRow(uint32_t rowAddr) * XRES pin, a software reset, and watchdog reset sources. Also, the low-voltage * detect circuits should be configured to generate an interrupt instead of a reset. * Otherwise, portions of flash may undergo unexpected changes. -* \note To avoid situation of reading data from cache memory - before -* reading data from previously programmed/erased flash rows, the user must +* \note To avoid situation of reading data from cache memory - before +* reading data from previously programmed/erased flash rows, the user must * clear the flash cache with the Cy_SysLib_ClearFlashCacheAndBuffer() * function. * -* \param rowAddr Address of the flash row number. +* \param rowAddr Address of the flash row number. * The Read-while-Write violation occurs when the flash read operation is * initiated in the same flash sector where the flash erase operation is * performing. Refer to the device datasheet for the details. @@ -697,7 +710,7 @@ cy_en_flashdrv_status_t Cy_Flash_StartEraseRow(uint32_t rowAddr) { flashContext.opcode |= CY_FLASH_BLOCKING_MODE; } - + flashContext.arg1 = rowAddr; flashContext.arg2 = 0UL; flashContext.arg3 = 0UL; @@ -731,7 +744,7 @@ cy_en_flashdrv_status_t Cy_Flash_StartEraseRow(uint32_t rowAddr) * detect circuits should be configured to generate an interrupt instead of a * reset. Otherwise, portions of flash may undergo unexpected changes. * -* \param sectorAddr Address of the flash row number. +* \param sectorAddr Address of the flash row number. * The Read-while-Write violation occurs when the flash read operation is * initiated in the same flash sector where the flash write operation is * performing. Refer to the device datasheet for the details. @@ -786,7 +799,7 @@ cy_en_flashdrv_status_t Cy_Flash_EraseSector(uint32_t sectorAddr) * user must clear the flash cache with the Cy_SysLib_ClearFlashCacheAndBuffer() * function. * -* \param sectorAddr Address of the flash row number. +* \param sectorAddr Address of the flash row number. * The Read-while-Write violation occurs when the flash read operation is * initiated in the same flash sector where the flash erase operation is * performing. Refer to the device datasheet for the details. @@ -810,7 +823,7 @@ cy_en_flashdrv_status_t Cy_Flash_StartEraseSector(uint32_t sectorAddr) { flashContext.opcode |= CY_FLASH_BLOCKING_MODE; } - + flashContext.arg1 = sectorAddr; flashContext.arg2 = 0UL; flashContext.arg3 = 0UL; @@ -844,7 +857,7 @@ cy_en_flashdrv_status_t Cy_Flash_StartEraseSector(uint32_t sectorAddr) * detect circuits should be configured to generate an interrupt instead of a * reset. Otherwise, portions of flash may undergo unexpected changes. * -* \param subSectorAddr Address of the flash row number. +* \param subSectorAddr Address of the flash row number. * The Read-while-Write violation occurs when the flash read operation is * initiated in the same flash sector where the flash write operation is * performing. Refer to the device datasheet for the details. @@ -899,7 +912,7 @@ cy_en_flashdrv_status_t Cy_Flash_EraseSubsector(uint32_t subSectorAddr) * user must clear the flash cache with the Cy_SysLib_ClearFlashCacheAndBuffer() * function. * -* \param subSectorAddr Address of the flash row number. +* \param subSectorAddr Address of the flash row number. * The Read-while-Write violation occurs when the flash read operation is * initiated in the same flash sector where the flash erase operation is * performing. Refer to the device datasheet for the details. @@ -923,7 +936,7 @@ cy_en_flashdrv_status_t Cy_Flash_StartEraseSubsector(uint32_t subSectorAddr) { flashContext.opcode |= CY_FLASH_BLOCKING_MODE; } - + flashContext.arg1 = subSectorAddr; flashContext.arg2 = 0UL; flashContext.arg3 = 0UL; @@ -964,7 +977,7 @@ cy_en_flashdrv_status_t Cy_Flash_StartEraseSubsector(uint32_t subSectorAddr) * user must clear the flash cache with the Cy_SysLib_ClearFlashCacheAndBuffer() * function. * -* \param rowAddr Address of the flash row number. +* \param rowAddr Address of the flash row number. * The Read-while-Write violation occurs when the flash read operation is * initiated in the same flash sector where the flash write operation is * performing. Refer to the device datasheet for the details. @@ -1088,7 +1101,7 @@ cy_en_flashdrv_status_t Cy_Flash_WriteRow(uint32_t rowAddr, const uint32_t* data * user must clear the flash cache with the Cy_SysLib_ClearFlashCacheAndBuffer() * function. * -* \param rowAddr Address of the flash row number. +* \param rowAddr Address of the flash row number. * The Read-while-Write violation occurs when the flash read operation is * initiated in the same flash sector where the flash write operation is * performing. Refer to the device datasheet for the details. @@ -1168,7 +1181,7 @@ cy_en_flashdrv_status_t Cy_Flash_IsOperationComplete(void) * user must clear the flash cache with the Cy_SysLib_ClearFlashCacheAndBuffer() * function. * -* \param rowAddr The address of the flash row number. +* \param rowAddr The address of the flash row number. * The Read-while-Write violation occurs when the Flash Write operation is * performing. Refer to the device datasheet for the details. * The address must match the row start address. @@ -1192,12 +1205,12 @@ cy_en_flashdrv_status_t Cy_Flash_StartProgram(uint32_t rowAddr, const uint32_t* /* Prepares arguments to be passed to SROM API */ flashContext.opcode = CY_FLASH_OPCODE_PROGRAM_ROW; - + if (SFLASH_SINGLE_CORE != 0U) { flashContext.opcode |= CY_FLASH_BLOCKING_MODE; } - + flashContext.arg1 = CY_FLASH_DATA_LOC_SRAM; flashContext.arg2 = rowAddr; flashContext.arg3 = (uint32_t)data; @@ -1522,11 +1535,17 @@ static cy_en_flashdrv_status_t Cy_Flash_OperationStatus(void) result = Cy_Flash_ProcessOpcode(flashContext.opcode); /* Clear pre-fetch cache after flash operation */ - FLASHC_FLASH_CMD = FLASHC_FLASH_CMD_INV_Msk; - - while (FLASHC_FLASH_CMD != 0U) - { - } + #if CY_CPU_CORTEX_M4 && defined(CY_DEVICE_SECURE) + CY_PRA_REG32_SET(CY_PRA_INDX_FLASHC_FLASH_CMD, FLASHC_FLASH_CMD_INV_Msk); + while (CY_PRA_REG32_GET(CY_PRA_INDX_FLASHC_FLASH_CMD) != 0U) + { + } + #else + FLASHC_FLASH_CMD = FLASHC_FLASH_CMD_INV_Msk; + while (FLASHC_FLASH_CMD != 0U) + { + } + #endif /* CY_CPU_CORTEX_M4 && defined(CY_DEVICE_SECURE) */ } return (result); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_gpio.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_gpio.c index 938875698a..7a9ca0ef2a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_gpio.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_gpio.c @@ -1,12 +1,12 @@ /***************************************************************************//** * \file cy_gpio.c -* \version 1.20 +* \version 1.20.1 * * Provides an API implementation of the GPIO driver * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -59,7 +59,7 @@ extern "C" { * \return * Initialization status * -* \note +* \note * This function modifies port registers in read-modify-write operations. It is * not thread safe as the resource is shared among multiple pins on a port. * @@ -75,12 +75,12 @@ cy_en_gpio_status_t Cy_GPIO_Pin_Init(GPIO_PRT_Type *base, uint32_t pinNum, const { uint32_t maskCfgOut; uint32_t tempReg; - + CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum)); CY_ASSERT_L2(CY_GPIO_IS_VALUE_VALID(config->outVal)); CY_ASSERT_L2(CY_GPIO_IS_DM_VALID(config->driveMode)); - CY_ASSERT_L2(CY_GPIO_IS_HSIOM_VALID(config->hsiom)); - CY_ASSERT_L2(CY_GPIO_IS_INT_EDGE_VALID(config->intEdge)); + CY_ASSERT_L2(CY_GPIO_IS_HSIOM_VALID(config->hsiom)); + CY_ASSERT_L2(CY_GPIO_IS_INT_EDGE_VALID(config->intEdge)); CY_ASSERT_L2(CY_GPIO_IS_VALUE_VALID(config->intMask)); CY_ASSERT_L2(CY_GPIO_IS_VALUE_VALID(config->vtrip)); CY_ASSERT_L2(CY_GPIO_IS_VALUE_VALID(config->slewRate)); @@ -90,7 +90,7 @@ cy_en_gpio_status_t Cy_GPIO_Pin_Init(GPIO_PRT_Type *base, uint32_t pinNum, const CY_ASSERT_L2(CY_GPIO_IS_VALUE_VALID(config->vtripSel)); CY_ASSERT_L2(CY_GPIO_IS_VREF_SEL_VALID(config->vrefSel)); CY_ASSERT_L2(CY_GPIO_IS_VOH_SEL_VALID(config->vohSel)); - + Cy_GPIO_Write(base, pinNum, config->outVal); Cy_GPIO_SetDrivemode(base, pinNum, config->driveMode); Cy_GPIO_SetHSIOM(base, pinNum, config->hsiom); @@ -100,10 +100,10 @@ cy_en_gpio_status_t Cy_GPIO_Pin_Init(GPIO_PRT_Type *base, uint32_t pinNum, const Cy_GPIO_SetVtrip(base, pinNum, config->vtrip); /* Slew rate and Driver strength */ - maskCfgOut = (CY_GPIO_CFG_OUT_SLOW_MASK << pinNum) + maskCfgOut = (CY_GPIO_CFG_OUT_SLOW_MASK << pinNum) | (CY_GPIO_CFG_OUT_DRIVE_SEL_MASK << ((uint32_t)(pinNum << 1U) + CY_GPIO_CFG_OUT_DRIVE_OFFSET)); tempReg = GPIO_PRT_CFG_OUT(base) & ~(maskCfgOut); - + GPIO_PRT_CFG_OUT(base) = tempReg | ((config->slewRate & CY_GPIO_CFG_OUT_SLOW_MASK) << pinNum) | ((config->driveSel & CY_GPIO_CFG_OUT_DRIVE_SEL_MASK) << ((uint32_t)(pinNum << 1U) + CY_GPIO_CFG_OUT_DRIVE_OFFSET)); @@ -142,9 +142,9 @@ cy_en_gpio_status_t Cy_GPIO_Pin_Init(GPIO_PRT_Type *base, uint32_t pinNum, const * \return * Initialization status * -* \note -* If using the PSoC Creator IDE, there is no need to initialize the pins when -* using the GPIO component on the schematic. Ports are configured in +* \note +* If using the PSoC Creator IDE, there is no need to initialize the pins when +* using the GPIO component on the schematic. Ports are configured in * Cy_SystemInit() before main() entry. * * \funcusage @@ -159,14 +159,14 @@ cy_en_gpio_status_t Cy_GPIO_Port_Init(GPIO_PRT_Type* base, const cy_stc_gpio_prt { uint32_t portNum; HSIOM_PRT_V1_Type* baseHSIOM; - + CY_ASSERT_L2(CY_GPIO_IS_PIN_BIT_VALID(config->out)); CY_ASSERT_L2(CY_GPIO_IS_PIN_BIT_VALID(config->cfgIn)); CY_ASSERT_L2(CY_GPIO_IS_INTR_CFG_VALID(config->intrCfg)); CY_ASSERT_L2(CY_GPIO_IS_INTR_MASK_VALID(config->intrMask)); CY_ASSERT_L2(CY_GPIO_IS_SEL_ACT_VALID(config->sel0Active)); CY_ASSERT_L2(CY_GPIO_IS_SEL_ACT_VALID(config->sel1Active)); - + portNum = ((uint32_t)(base) - CY_GPIO_BASE) / GPIO_PRT_SECTION_SIZE; baseHSIOM = (HSIOM_PRT_V1_Type*)(CY_HSIOM_BASE + (HSIOM_PRT_SECTION_SIZE * portNum)); @@ -179,10 +179,10 @@ cy_en_gpio_status_t Cy_GPIO_Port_Init(GPIO_PRT_Type* base, const cy_stc_gpio_prt GPIO_PRT_CFG_SIO(base) = config->cfgSIO; HSIOM_PRT_PORT_SEL0(baseHSIOM) = config->sel0Active; HSIOM_PRT_PORT_SEL1(baseHSIOM) = config->sel1Active; - + status = CY_GPIO_SUCCESS; } - + return (status); } @@ -210,11 +210,11 @@ cy_en_gpio_status_t Cy_GPIO_Port_Init(GPIO_PRT_Type* base, const cy_stc_gpio_prt * \param hsiom * HSIOM input selection * -* \note +* \note * This function modifies port registers in read-modify-write operations. It is * not thread safe as the resource is shared among multiple pins on a port. -* You can use the Cy_SysLib_EnterCriticalSection() and -* Cy_SysLib_ExitCriticalSection() functions to ensure that +* You can use the Cy_SysLib_EnterCriticalSection() and +* Cy_SysLib_ExitCriticalSection() functions to ensure that * Cy_GPIO_Pin_FastInit() function execution is not interrupted. * * \funcusage @@ -278,12 +278,12 @@ void Cy_GPIO_Port_Deinit(GPIO_PRT_Type* base) * Function Name: Cy_GPIO_SetAmuxSplit ****************************************************************************//** * -* Configure a specific AMux bus splitter switch cell into a specific +* Configure a specific AMux bus splitter switch cell into a specific * configuration. * * \param switchCtrl * Selects specific AMux bus splitter cell between two segments. -* The cy_en_amux_split_t enumeration can be found in the GPIO header file +* The cy_en_amux_split_t enumeration can be found in the GPIO header file * for the device package. * * \param amuxConnect @@ -293,7 +293,7 @@ void Cy_GPIO_Port_Deinit(GPIO_PRT_Type* base) * Selects which AMux bus within the splitter is being configured * *******************************************************************************/ -void Cy_GPIO_SetAmuxSplit(cy_en_amux_split_t switchCtrl, cy_en_gpio_amuxconnect_t amuxConnect, +void Cy_GPIO_SetAmuxSplit(cy_en_amux_split_t switchCtrl, cy_en_gpio_amuxconnect_t amuxConnect, cy_en_gpio_amuxselect_t amuxBus) { CY_ASSERT_L2(CY_GPIO_IS_AMUX_SPLIT_VALID(switchCtrl)); @@ -310,7 +310,7 @@ void Cy_GPIO_SetAmuxSplit(cy_en_amux_split_t switchCtrl, cy_en_gpio_amuxconnect_ else { tmpReg = HSIOM_AMUX_SPLIT_CTL(switchCtrl) & GPIO_AMUXA_SPLITTER_MASK; - HSIOM_AMUX_SPLIT_CTL(switchCtrl) = + HSIOM_AMUX_SPLIT_CTL(switchCtrl) = tmpReg | (((uint32_t) amuxConnect << HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SL_Pos) & GPIO_AMUXB_SPLITTER_MASK); } } @@ -324,7 +324,7 @@ void Cy_GPIO_SetAmuxSplit(cy_en_amux_split_t switchCtrl, cy_en_gpio_amuxconnect_ * * \param switchCtrl * Selects specific AMux bus splitter cell between two segments. -* The cy_en_amux_split_t enumeration can be found in the GPIO header file +* The cy_en_amux_split_t enumeration can be found in the GPIO header file * for the device package. * * \param amuxBus @@ -338,19 +338,19 @@ cy_en_gpio_amuxconnect_t Cy_GPIO_GetAmuxSplit(cy_en_amux_split_t switchCtrl, cy_ { CY_ASSERT_L2(CY_GPIO_IS_AMUX_SPLIT_VALID(switchCtrl)); CY_ASSERT_L3(CY_GPIO_IS_AMUX_SELECT_VALID(amuxBus)); - + uint32_t retVal; - + if (amuxBus != CY_GPIO_AMUXBUSB) { retVal = HSIOM_AMUX_SPLIT_CTL(switchCtrl) & GPIO_AMUXA_SPLITTER_MASK; } else { - retVal = ((uint32_t) ((HSIOM_AMUX_SPLIT_CTL(switchCtrl) & GPIO_AMUXB_SPLITTER_MASK) + retVal = ((uint32_t) ((HSIOM_AMUX_SPLIT_CTL(switchCtrl) & GPIO_AMUXB_SPLITTER_MASK) >> HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SL_Pos)); } - + return ((cy_en_gpio_amuxconnect_t) retVal); } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_i2s.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_i2s.c index f89905ba8f..f31013e7e0 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_i2s.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_i2s.c @@ -1,12 +1,12 @@ /***************************************************************************//** * \file cy_i2s.c -* \version 2.10 +* \version 2.10.1 * * The source code file for the I2S driver. * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -49,21 +49,21 @@ cy_en_i2s_status_t Cy_I2S_Init(I2S_Type * base, cy_stc_i2s_config_t const * config) { cy_en_i2s_status_t ret = CY_I2S_BAD_PARAM; - + if((NULL != base) && (NULL != config)) { cy_en_i2s_ws_pw_t wsPulseWidth; cy_en_i2s_len_t channelLength; uint32_t channels; uint32_t clockDiv = (uint32_t)config->clkDiv - 1U; - + CY_ASSERT_L2(CY_I2S_IS_CLK_DIV_VALID(clockDiv)); - + REG_I2S_INTR_MASK(base) = 0UL; /* Disable interrupts prior to stopping the operation */ REG_I2S_CMD(base) = 0UL; /* Stop any communication */ REG_I2S_TR_CTL(base) = 0UL; /* Disable any DMA triggers */ REG_I2S_CTL(base) = 0UL; /* Disable TX/RX sub-blocks before clock changing */ - + /* The clock setting */ REG_I2S_CLOCK_CTL(base) = _VAL2FLD(I2S_CLOCK_CTL_CLOCK_DIV, clockDiv) | _BOOL2FLD(I2S_CLOCK_CTL_CLOCK_SEL, config->extClk); @@ -73,13 +73,13 @@ cy_en_i2s_status_t Cy_I2S_Init(I2S_Type * base, cy_stc_i2s_config_t const * conf { CY_ASSERT_L3(CY_I2S_IS_ALIGNMENT_VALID(config->txAlignment)); CY_ASSERT_L3(CY_I2S_IS_OVHDATA_VALID(config->txOverheadValue)); - + if ((CY_I2S_TDM_MODE_A == config->txAlignment) || (CY_I2S_TDM_MODE_B == config->txAlignment)) { channels = (uint32_t)config->txChannels - 1UL; wsPulseWidth = config->txWsPulseWidth; channelLength = CY_I2S_LEN32; - + CY_ASSERT_L2(CY_I2S_IS_CHANNELS_VALID(channels)); CY_ASSERT_L3(CY_I2S_IS_WSPULSE_VALID(wsPulseWidth)); CY_ASSERT_L3(CY_I2S_IS_LEN_VALID(config->txWordLength)); @@ -89,12 +89,12 @@ cy_en_i2s_status_t Cy_I2S_Init(I2S_Type * base, cy_stc_i2s_config_t const * conf channels = 1UL; wsPulseWidth = CY_I2S_WS_ONE_CHANNEL_LENGTH; channelLength = config->txChannelLength; - + CY_ASSERT_L3(CY_I2S_IS_CHAN_WORD_VALID(channelLength, config->txWordLength)); } - + CY_ASSERT_L2(CY_I2S_IS_TRIG_LEVEL_VALID(config->txFifoTriggerLevel, channels)); - + REG_I2S_TX_WATCHDOG(base) = config->txWatchdogValue; REG_I2S_TX_CTL(base) = _VAL2FLD(I2S_TX_CTL_I2S_MODE, config->txAlignment) | @@ -114,13 +114,13 @@ cy_en_i2s_status_t Cy_I2S_Init(I2S_Type * base, cy_stc_i2s_config_t const * conf if (config->rxEnabled) { CY_ASSERT_L3(CY_I2S_IS_ALIGNMENT_VALID(config->rxAlignment)); - + if ((CY_I2S_TDM_MODE_A == config->rxAlignment) || (CY_I2S_TDM_MODE_B == config->rxAlignment)) { channels = (uint32_t)config->rxChannels - 1UL; wsPulseWidth = config->rxWsPulseWidth; channelLength = CY_I2S_LEN32; - + CY_ASSERT_L2(CY_I2S_IS_CHANNELS_VALID(channels)); CY_ASSERT_L3(CY_I2S_IS_WSPULSE_VALID(wsPulseWidth)); CY_ASSERT_L3(CY_I2S_IS_LEN_VALID(config->rxWordLength)); @@ -130,10 +130,10 @@ cy_en_i2s_status_t Cy_I2S_Init(I2S_Type * base, cy_stc_i2s_config_t const * conf channels = 1UL; wsPulseWidth = CY_I2S_WS_ONE_CHANNEL_LENGTH; channelLength = config->rxChannelLength; - + CY_ASSERT_L3(CY_I2S_IS_CHAN_WORD_VALID(channelLength, config->rxWordLength)); } - + CY_ASSERT_L2(CY_I2S_IS_TRIG_LEVEL_VALID(config->rxFifoTriggerLevel, channels)); REG_I2S_RX_WATCHDOG(base) = config->rxWatchdogValue; @@ -176,7 +176,7 @@ cy_en_i2s_status_t Cy_I2S_Init(I2S_Type * base, cy_stc_i2s_config_t const * conf REG_I2S_TR_CTL(base) |= _BOOL2FLD(I2S_TR_CTL_RX_REQ_EN, config->rxDmaTrigger); } - + ret = CY_I2S_SUCCESS; } @@ -217,13 +217,13 @@ void Cy_I2S_DeInit(I2S_Type * base) ****************************************************************************//** * * This is a callback function to be used at the application layer to -* manage an I2S operation during the Deep Sleep cycle. It stores the I2S state -* (Tx/Rx enabled/disabled/paused) into the context structure and stops the +* manage an I2S operation during the Deep Sleep cycle. It stores the I2S state +* (Tx/Rx enabled/disabled/paused) into the context structure and stops the * communication before entering into Deep Sleep power mode and restores the I2S * state after waking up. * -* \param -* callbackParams - The pointer to the callback parameters structure, +* \param +* callbackParams - The pointer to the callback parameters structure, * see \ref cy_stc_syspm_callback_params_t. * * \param mode @@ -231,7 +231,7 @@ void Cy_I2S_DeInit(I2S_Type * base) * * \return the SysPm callback status \ref cy_en_syspm_status_t. * -* \note Use the \ref cy_stc_i2s_context_t data type for definition of the +* \note Use the \ref cy_stc_i2s_context_t data type for definition of the * *context element of the \ref cy_stc_syspm_callback_params_t structure. * * \funcusage @@ -245,13 +245,13 @@ cy_en_syspm_status_t Cy_I2S_DeepSleepCallback (cy_stc_syspm_callback_params_t *c I2S_Type * locBase = (I2S_Type*) callbackParams->base; uint32_t * locInterruptMask = (uint32_t*) &(((cy_stc_i2s_context_t*)(callbackParams->context))->interruptMask); uint32_t * locState = (uint32_t*) &(((cy_stc_i2s_context_t*)(callbackParams->context))->enableState); - + switch(mode) { case CY_SYSPM_CHECK_READY: case CY_SYSPM_CHECK_FAIL: break; - + case CY_SYSPM_BEFORE_TRANSITION: *locInterruptMask = Cy_I2S_GetInterruptMask(locBase); /* Store I2S interrupts */ *locState = Cy_I2S_GetCurrentState(locBase); /* Store I2S state */ @@ -266,7 +266,7 @@ cy_en_syspm_status_t Cy_I2S_DeepSleepCallback (cy_stc_syspm_callback_params_t *c Cy_I2S_SetInterruptMask(locBase, 0UL); /* Disable I2S interrupts */ /* Unload FIFOs to not lose data (if needed) */ break; - + case CY_SYSPM_AFTER_TRANSITION: if (0UL != (*locState & I2S_CMD_RX_START_Msk)) { @@ -287,12 +287,12 @@ cy_en_syspm_status_t Cy_I2S_DeepSleepCallback (cy_stc_syspm_callback_params_t *c Cy_I2S_ClearInterrupt(locBase, *locInterruptMask); /* Clear possible pending I2S interrupts */ Cy_I2S_SetInterruptMask(locBase, *locInterruptMask); /* Restore I2S interrupts */ break; - + default: ret = CY_SYSPM_FAIL; break; } - + return(ret); } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_ipc_drv.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_ipc_drv.c index c70eed7b77..28820825b4 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_ipc_drv.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_ipc_drv.c @@ -1,13 +1,13 @@ /***************************************************************************//** * \file cy_ipc_drv.c -* \version 1.40 +* \version 1.40.1 * * \brief * IPC Driver - This source file contains the low-level driver code for * the IPC hardware. * ******************************************************************************** -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_ipc_pipe.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_ipc_pipe.c index 5800baa614..b31b325c4e 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_ipc_pipe.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_ipc_pipe.c @@ -1,13 +1,13 @@ /***************************************************************************//** * \file cy_ipc_pipe.c -* \version 1.40 +* \version 1.40.1 * * Description: * IPC Pipe Driver - This source file includes code for the Pipe layer on top * of the IPC driver. * ******************************************************************************** -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_ipc_sema.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_ipc_sema.c index b5120d15d6..6f327463cf 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_ipc_sema.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_ipc_sema.c @@ -1,13 +1,13 @@ /***************************************************************************//** * \file cy_ipc_sema.c -* \version 1.40 +* \version 1.40.1 * * Description: * IPC Semaphore Driver - This source file contains the source code for the * semaphore level APIs for the IPC interface. * ******************************************************************************** -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -93,7 +93,7 @@ cy_en_ipcsema_status_t Cy_IPC_Sema_Init(uint32_t ipcChannel, retStatus = Cy_IPC_Sema_InitExt(ipcChannel, &cy_semaData); } - + else { retStatus = CY_IPC_SEMA_BAD_PARAM; @@ -121,7 +121,7 @@ cy_en_ipcsema_status_t Cy_IPC_Sema_Init(uint32_t ipcChannel, * The IPC channel number used for semaphores * * \param ipcSema -* This is configuration structure of the IPC semaphore. +* This is configuration structure of the IPC semaphore. * See \ref cy_stc_ipc_sema_t. * * \return Status of the operation @@ -129,7 +129,7 @@ cy_en_ipcsema_status_t Cy_IPC_Sema_Init(uint32_t ipcChannel, * \retval CY_IPC_SEMA_BAD_PARAM: Memory pointer is NULL and count is not zero, * or count not multiple of 32 * \retval CY_IPC_SEMA_ERROR_LOCKED: Could not acquire semaphores IPC channel -* +* *******************************************************************************/ cy_en_ipcsema_status_t Cy_IPC_Sema_InitExt(uint32_t ipcChannel, cy_stc_ipc_sema_t *ipcSema) { diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_lpcomp.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_lpcomp.c index 67f3719dd3..8514e3e5ca 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_lpcomp.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_lpcomp.c @@ -1,6 +1,6 @@ /******************************************************************************* * \file cy_lpcomp.c -* \version 1.20 +* \version 1.20.1 * * \brief * This file provides the driver code to the API for the Low Power Comparator @@ -8,7 +8,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -55,7 +55,7 @@ static cy_stc_lpcomp_context_t cy_lpcomp_context; cy_en_lpcomp_status_t Cy_LPComp_Init(LPCOMP_Type* base, cy_en_lpcomp_channel_t channel, const cy_stc_lpcomp_config_t* config) { cy_en_lpcomp_status_t ret = CY_LPCOMP_BAD_PARAM; - + CY_ASSERT_L3(CY_LPCOMP_IS_CHANNEL_VALID(channel)); CY_ASSERT_L3(CY_LPCOMP_IS_OUT_MODE_VALID(config->outputMode)); CY_ASSERT_L3(CY_LPCOMP_IS_HYSTERESIS_VALID(config->hysteresis)); @@ -67,7 +67,7 @@ cy_en_lpcomp_status_t Cy_LPComp_Init(LPCOMP_Type* base, cy_en_lpcomp_channel_t c Cy_LPComp_GlobalEnable(base); if (CY_LPCOMP_CHANNEL_0 == channel) - { + { LPCOMP_CMP0_CTRL(base) = _VAL2FLD(LPCOMP_CMP0_CTRL_HYST0, (uint32_t)config->hysteresis) | _VAL2FLD(LPCOMP_CMP0_CTRL_DSI_BYPASS0, (uint32_t)config->outputMode) | _VAL2FLD(LPCOMP_CMP0_CTRL_DSI_LEVEL0, (uint32_t)config->outputMode >> 1u); @@ -78,16 +78,16 @@ cy_en_lpcomp_status_t Cy_LPComp_Init(LPCOMP_Type* base, cy_en_lpcomp_channel_t c _VAL2FLD(LPCOMP_CMP1_CTRL_DSI_BYPASS1, (uint32_t)config->outputMode) | _VAL2FLD(LPCOMP_CMP1_CTRL_DSI_LEVEL1, (uint32_t)config->outputMode >> 1u); } - + /* Save intType to use it in the Cy_LPComp_Enable() function */ cy_lpcomp_context.intType[(uint8_t)channel - 1u] = config->intType; - + /* Save power to use it in the Cy_LPComp_Enable() function */ cy_lpcomp_context.power[(uint8_t)channel - 1u] = config->power; - + ret = CY_LPCOMP_SUCCESS; } - + return (ret); } @@ -110,14 +110,14 @@ cy_en_lpcomp_status_t Cy_LPComp_Init(LPCOMP_Type* base, cy_en_lpcomp_channel_t c void Cy_LPComp_Enable(LPCOMP_Type* base, cy_en_lpcomp_channel_t channel) { cy_en_lpcomp_pwr_t powerSpeed; - + CY_ASSERT_L3(CY_LPCOMP_IS_CHANNEL_VALID(channel)); - + powerSpeed = cy_lpcomp_context.power[(uint8_t)channel - 1u]; - + /* Set power */ Cy_LPComp_SetPower(base, channel, powerSpeed); - + /* Make delay before enabling the comparator interrupt to prevent false triggering */ if (CY_LPCOMP_MODE_ULP == powerSpeed) { @@ -129,9 +129,9 @@ void Cy_LPComp_Enable(LPCOMP_Type* base, cy_en_lpcomp_channel_t channel) } else { - Cy_SysLib_DelayUs(CY_LPCOMP_NORMAL_POWER_DELAY); + Cy_SysLib_DelayUs(CY_LPCOMP_NORMAL_POWER_DELAY); } - + /* Enable the comparator interrupt */ Cy_LPComp_SetInterruptTriggerMode(base, channel, cy_lpcomp_context.intType[(uint8_t)channel - 1u]); } @@ -153,12 +153,12 @@ void Cy_LPComp_Enable(LPCOMP_Type* base, cy_en_lpcomp_channel_t channel) * *******************************************************************************/ void Cy_LPComp_Disable(LPCOMP_Type* base, cy_en_lpcomp_channel_t channel) -{ +{ CY_ASSERT_L3(CY_LPCOMP_IS_CHANNEL_VALID(channel)); /* Disable the comparator interrupt */ Cy_LPComp_SetInterruptTriggerMode(base, channel, CY_LPCOMP_INTR_DISABLE); - + /* Set power off */ Cy_LPComp_SetPower(base, channel, CY_LPCOMP_MODE_OFF); } @@ -168,9 +168,9 @@ void Cy_LPComp_Disable(LPCOMP_Type* base, cy_en_lpcomp_channel_t channel) * Function Name: Cy_LPComp_SetInterruptTriggerMode ****************************************************************************//** * -* Sets the interrupt edge-detect mode. +* Sets the interrupt edge-detect mode. * This also controls the value provided on the output. -* \note Interrupts can be enabled after the block is enabled and the appropriate +* \note Interrupts can be enabled after the block is enabled and the appropriate * start-up time has elapsed: * 3 us for the normal power mode; * 6 us for the LP mode; @@ -183,17 +183,17 @@ void Cy_LPComp_Disable(LPCOMP_Type* base, cy_en_lpcomp_channel_t channel) * The LPCOMP channel index. * * \param intType -* Interrupt edge trigger selection -* CY_LPCOMP_INTR_DISABLE (=0) - Disabled, no interrupt will be detected -* CY_LPCOMP_INTR_RISING (=1) - Rising edge -* CY_LPCOMP_INTR_FALLING (=2) - Falling edge +* Interrupt edge trigger selection +* CY_LPCOMP_INTR_DISABLE (=0) - Disabled, no interrupt will be detected +* CY_LPCOMP_INTR_RISING (=1) - Rising edge +* CY_LPCOMP_INTR_FALLING (=2) - Falling edge * CY_LPCOMP_INTR_BOTH (=3) - Both rising and falling edges. * * \return None * *******************************************************************************/ void Cy_LPComp_SetInterruptTriggerMode(LPCOMP_Type* base, cy_en_lpcomp_channel_t channel, cy_en_lpcomp_int_t intType) -{ +{ CY_ASSERT_L3(CY_LPCOMP_IS_CHANNEL_VALID(channel)); CY_ASSERT_L3(CY_LPCOMP_IS_INTR_MODE_VALID(intType)); @@ -216,11 +216,11 @@ void Cy_LPComp_SetInterruptTriggerMode(LPCOMP_Type* base, cy_en_lpcomp_channel_t ****************************************************************************//** * * Sets the drive power and speeds to one of the four settings. -* \note Interrupts can be enabled after the block is enabled and the appropriate +* \note Interrupts can be enabled after the block is enabled and the appropriate * start-up time has elapsed: * 3 us for the normal power mode; * 6 us for the LP mode; -* 50 us for the ULP mode. +* 50 us for the ULP mode. * Otherwise, unexpected interrupts events can occur. * * \param *base @@ -231,9 +231,9 @@ void Cy_LPComp_SetInterruptTriggerMode(LPCOMP_Type* base, cy_en_lpcomp_channel_t * * \param power * The power setting sets an operation mode of the component: -* CY_LPCOMP_OFF_POWER (=0) - Off power -* CY_LPCOMP_MODE_ULP (=1) - Slow/ultra low power -* CY_LPCOMP_MODE_LP (=2) - Medium/low power +* CY_LPCOMP_OFF_POWER (=0) - Off power +* CY_LPCOMP_MODE_ULP (=1) - Slow/ultra low power +* CY_LPCOMP_MODE_LP (=2) - Medium/low power * CY_LPCOMP_MODE_NORMAL(=3) - Fast/normal power * * \return None @@ -268,8 +268,8 @@ void Cy_LPComp_SetPower(LPCOMP_Type* base, cy_en_lpcomp_channel_t channel, cy_en * The LPCOMP channel index. * * \param hysteresis -* Sets an operation mode of the component -* CY_LPCOMP_HYST_ENABLE (=1) - Enables HYST +* Sets an operation mode of the component +* CY_LPCOMP_HYST_ENABLE (=1) - Enables HYST * CY_LPCOMP_HYST_DISABLE(=0) - Disable HYST. * * \return None @@ -295,15 +295,15 @@ void Cy_LPComp_SetHysteresis(LPCOMP_Type* base, cy_en_lpcomp_channel_t channel, * Function Name: Cy_LPComp_SetInputs ****************************************************************************//** * -* Sets the comparator input sources. The comparator inputs can be connected -* to the dedicated GPIO pins or AMUXBUSA/AMUXBUSB. Additionally, the negative -* comparator input can be connected to the local VREF. +* Sets the comparator input sources. The comparator inputs can be connected +* to the dedicated GPIO pins or AMUXBUSA/AMUXBUSB. Additionally, the negative +* comparator input can be connected to the local VREF. * At least one unconnected input causes a comparator undefined output. * * \note Connection to AMUXBUSA/AMUXBUSB requires closing the additional -* switches which are a part of the IO system. These switches can be configured -* using the HSIOM->AMUX_SPLIT_CTL[3] register. -* Refer to the appropriate Technical Reference Manual (TRM) of a device +* switches which are a part of the IO system. These switches can be configured +* using the HSIOM->AMUX_SPLIT_CTL[3] register. +* Refer to the appropriate Technical Reference Manual (TRM) of a device * for a detailed description. * * \param *base @@ -313,16 +313,16 @@ void Cy_LPComp_SetHysteresis(LPCOMP_Type* base, cy_en_lpcomp_channel_t channel, * The LPCOMP channel index. * * \param inputP -* Positive input selection -* CY_LPCOMP_SW_GPIO (0x01u) -* CY_LPCOMP_SW_AMUXBUSA (0x02u) - Hi-Z in hibernate mode +* Positive input selection +* CY_LPCOMP_SW_GPIO (0x01u) +* CY_LPCOMP_SW_AMUXBUSA (0x02u) - Hi-Z in hibernate mode * CY_LPCOMP_SW_AMUXBUSB (0x04u) - Hi-Z in the hibernate mode. * * \param inputN -* Negative input selection -* CY_LPCOMP_SW_GPIO (0x01u) -* CY_LPCOMP_SW_AMUXBUSA (0x02u) - Hi-Z in hibernate mode -* CY_LPCOMP_SW_AMUXBUSB (0x04u) - Hi-Z in hibernate mode +* Negative input selection +* CY_LPCOMP_SW_GPIO (0x01u) +* CY_LPCOMP_SW_AMUXBUSA (0x02u) - Hi-Z in hibernate mode +* CY_LPCOMP_SW_AMUXBUSB (0x04u) - Hi-Z in hibernate mode * CY_LPCOMP_SW_LOCAL_VREF (0x08u) - the negative input only for a crude REF. * * \return None @@ -356,7 +356,7 @@ void Cy_LPComp_SetInputs(LPCOMP_Type* base, cy_en_lpcomp_channel_t channel, cy_e break; } } - + switch(inputN) { case CY_LPCOMP_SW_AMUXBUSA: @@ -409,14 +409,14 @@ void Cy_LPComp_SetInputs(LPCOMP_Type* base, cy_en_lpcomp_channel_t channel, cy_e * The LPCOMP channel index. * * \param outType -* Interrupt edge trigger selection -* CY_LPCOMP_OUT_PULSE (=0) - the DSI output with the pulse option, no bypass -* CY_LPCOMP_OUT_DIRECT (=1) - the bypass mode, the direct output of the comparator +* Interrupt edge trigger selection +* CY_LPCOMP_OUT_PULSE (=0) - the DSI output with the pulse option, no bypass +* CY_LPCOMP_OUT_DIRECT (=1) - the bypass mode, the direct output of the comparator * CY_LPCOMP_OUT_SYNC (=2) - DSI output with the level option, it is similar to the -* bypass mode but it is 1 cycle slow than the bypass. -* [DSI_LEVELx : DSI_BYPASSx] = [Bit11 : Bit10] -* 0 : 0 = 0x00 -> Pulse (PULSE) -* 1 : 0 = 0x02 -> Level (SYNC) +* bypass mode but it is 1 cycle slow than the bypass. +* [DSI_LEVELx : DSI_BYPASSx] = [Bit11 : Bit10] +* 0 : 0 = 0x00 -> Pulse (PULSE) +* 1 : 0 = 0x02 -> Level (SYNC) * x : 1 = 0x01 -> Bypass (Direct). * * \return None @@ -442,26 +442,26 @@ void Cy_LPComp_SetOutputMode(LPCOMP_Type* base, cy_en_lpcomp_channel_t channel, * Function Name: Cy_LPComp_DeepSleepCallback ****************************************************************************//** * -* This function checks the current power mode of LPComp and then disables the -* LPComp block if there is no wake-up source from LPComp in the deep-sleep mode. -* It stores the state of the LPComp enable and then disables the LPComp block +* This function checks the current power mode of LPComp and then disables the +* LPComp block if there is no wake-up source from LPComp in the deep-sleep mode. +* It stores the state of the LPComp enable and then disables the LPComp block * before going to the low power modes, and recovers the LPComp power state after * wake-up using the stored value. * * \param *callbackParams -* The \ref cy_stc_syspm_callback_params_t structure with the callback +* The \ref cy_stc_syspm_callback_params_t structure with the callback * parameters which consists of mode, base and context fields: * *base - LPComp register structure pointer; * *context - Context for the call-back function; * mode * CY_SYSPM_CHECK_READY - No action for this state. * CY_SYSPM_CHECK_FAIL - No action for this state. -* CY_SYSPM_BEFORE_TRANSITION - Checks the LPComp interrupt mask and the power -* mode, and then disables or enables the LPComp block +* CY_SYSPM_BEFORE_TRANSITION - Checks the LPComp interrupt mask and the power +* mode, and then disables or enables the LPComp block * according to the condition. * Stores the LPComp state to recover the state after * wake up. -* CY_SYSPM_AFTER_TRANSITION - Enables the LPComp block, if it was disabled +* CY_SYSPM_AFTER_TRANSITION - Enables the LPComp block, if it was disabled * before the sleep mode. * * \param mode @@ -499,11 +499,11 @@ cy_en_syspm_status_t Cy_LPComp_DeepSleepCallback(cy_stc_syspm_callback_params_t if (0u != enabled_status) { /* Disable the LPComp block when there is no wake-up source from any channel. */ - if( !(((_FLD2VAL(LPCOMP_CMP0_CTRL_MODE0, LPCOMP_CMP0_CTRL(locBase)) == (uint32_t)CY_LPCOMP_MODE_ULP) && + if( !(((_FLD2VAL(LPCOMP_CMP0_CTRL_MODE0, LPCOMP_CMP0_CTRL(locBase)) == (uint32_t)CY_LPCOMP_MODE_ULP) && _FLD2BOOL(LPCOMP_INTR_MASK_COMP0_MASK, LPCOMP_INTR_MASK(locBase))) || - ((_FLD2VAL(LPCOMP_CMP1_CTRL_MODE1, LPCOMP_CMP1_CTRL(locBase)) == (uint32_t)CY_LPCOMP_MODE_ULP) && + ((_FLD2VAL(LPCOMP_CMP1_CTRL_MODE1, LPCOMP_CMP1_CTRL(locBase)) == (uint32_t)CY_LPCOMP_MODE_ULP) && _FLD2BOOL(LPCOMP_INTR_MASK_COMP1_MASK, LPCOMP_INTR_MASK(locBase))))) - + { /* Disable the LPComp block to avoid leakage. */ Cy_LPComp_GlobalDisable(locBase); @@ -516,7 +516,7 @@ cy_en_syspm_status_t Cy_LPComp_DeepSleepCallback(cy_stc_syspm_callback_params_t } else { - /* The LPComp block was already disabled and + /* The LPComp block was already disabled and * the system is allowed to go to the low power mode. */ } @@ -527,8 +527,8 @@ cy_en_syspm_status_t Cy_LPComp_DeepSleepCallback(cy_stc_syspm_callback_params_t case CY_SYSPM_AFTER_TRANSITION: { - /* Enable LPComp to operate if it was enabled - * before entering to the low power mode. + /* Enable LPComp to operate if it was enabled + * before entering to the low power mode. */ if (0u != enabled_status) { @@ -536,7 +536,7 @@ cy_en_syspm_status_t Cy_LPComp_DeepSleepCallback(cy_stc_syspm_callback_params_t } else { - /* The LPComp block was disabled before calling this API + /* The LPComp block was disabled before calling this API * with mode = CY_SYSPM_CHECK_READY. */ } @@ -557,19 +557,19 @@ cy_en_syspm_status_t Cy_LPComp_DeepSleepCallback(cy_stc_syspm_callback_params_t * Function Name: Cy_LPComp_HibernateCallback ****************************************************************************//** * -* This function checks the current power mode of LPComp and then disable the -* LPComp block, if there is no wake-up source from LPComp in the hibernate mode. +* This function checks the current power mode of LPComp and then disable the +* LPComp block, if there is no wake-up source from LPComp in the hibernate mode. * * \param *callbackParams -* The \ref cy_stc_syspm_callback_params_t structure with the callback +* The \ref cy_stc_syspm_callback_params_t structure with the callback * parameters which consists of mode, base and context fields: * *base - LPComp register structure pointer; * *context - Context for the call-back function; * mode * CY_SYSPM_CHECK_READY - No action for this state. * CY_SYSPM_CHECK_FAIL - No action for this state. -* CY_SYSPM_BEFORE_TRANSITION - Checks the wake-up source from the hibernate mode -* of the LPComp block, and then disables or enables +* CY_SYSPM_BEFORE_TRANSITION - Checks the wake-up source from the hibernate mode +* of the LPComp block, and then disables or enables * the LPComp block according to the condition. * * \param mode @@ -594,7 +594,7 @@ cy_en_syspm_status_t Cy_LPComp_HibernateCallback(cy_stc_syspm_callback_params_t break; case CY_SYSPM_CHECK_FAIL: - { + { ret = CY_SYSPM_SUCCESS; } break; @@ -607,11 +607,11 @@ cy_en_syspm_status_t Cy_LPComp_HibernateCallback(cy_stc_syspm_callback_params_t if (0u != enabled_status) { /* Disable the LPComp block when there is no wake-up source from any channel. */ - if( (!(((_FLD2VAL(LPCOMP_CMP0_CTRL_MODE0, LPCOMP_CMP0_CTRL(locBase))) == (uint32_t)CY_LPCOMP_MODE_ULP) && + if( (!(((_FLD2VAL(LPCOMP_CMP0_CTRL_MODE0, LPCOMP_CMP0_CTRL(locBase))) == (uint32_t)CY_LPCOMP_MODE_ULP) && _FLD2BOOL(CY_LPCOMP_WAKEUP_PIN0, SRSS_PWR_HIBERNATE))) || - ((_FLD2VAL(LPCOMP_CMP1_CTRL_MODE1, LPCOMP_CMP1_CTRL(locBase)) == (uint32_t)CY_LPCOMP_MODE_ULP) && + ((_FLD2VAL(LPCOMP_CMP1_CTRL_MODE1, LPCOMP_CMP1_CTRL(locBase)) == (uint32_t)CY_LPCOMP_MODE_ULP) && _FLD2BOOL(CY_LPCOMP_WAKEUP_PIN1, SRSS_PWR_HIBERNATE))) - + { /* Disable the LPComp block to avoid leakage. */ Cy_LPComp_GlobalDisable(locBase); @@ -624,7 +624,7 @@ cy_en_syspm_status_t Cy_LPComp_HibernateCallback(cy_stc_syspm_callback_params_t } else { - /* The LPComp block was already disabled and + /* The LPComp block was already disabled and * the system is allowed to go to the low power mode. */ } @@ -636,7 +636,7 @@ cy_en_syspm_status_t Cy_LPComp_HibernateCallback(cy_stc_syspm_callback_params_t default: break; } - + return (ret); } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_lvd.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_lvd.c index ed1f900f01..eea207e846 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_lvd.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_lvd.c @@ -1,12 +1,12 @@ /***************************************************************************//** * \file cy_lvd.c -* \version 1.10 +* \version 1.20 * * The source code file for the LVD driver. * ******************************************************************************** * \copyright -* Copyright 2017-2019 Cypress Semiconductor Corporation +* Copyright 2017-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -36,7 +36,7 @@ extern "C" { * When this function is registered by \ref Cy_SysPm_RegisterCallback - it * automatically enables the LVD after wake up from Deep-Sleep mode. * -* \param callbackParams The pointer to the callback parameters structure, +* \param callbackParams The pointer to the callback parameters structure, * see \ref cy_stc_syspm_callback_params_t. * * \param mode @@ -48,7 +48,7 @@ extern "C" { cy_en_syspm_status_t Cy_LVD_DeepSleepCallback(cy_stc_syspm_callback_params_t * callbackParams, cy_en_syspm_callback_mode_t mode) { cy_en_syspm_status_t ret = CY_SYSPM_SUCCESS; - + if (callbackParams != NULL) { switch(mode) @@ -57,11 +57,11 @@ cy_en_syspm_status_t Cy_LVD_DeepSleepCallback(cy_stc_syspm_callback_params_t * c case CY_SYSPM_CHECK_FAIL: case CY_SYSPM_BEFORE_TRANSITION: break; - + case CY_SYSPM_AFTER_TRANSITION: Cy_LVD_Enable(); break; - + default: ret = CY_SYSPM_FAIL; break; diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_mcwdt.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_mcwdt.c index 12ce39d25f..e3d4534475 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_mcwdt.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_mcwdt.c @@ -1,12 +1,12 @@ /***************************************************************************//** * \file cy_mcwdt.c -* \version 1.30 +* \version 1.30.1 * * Description: * Provides a system API for the MCWDT driver. * ******************************************************************************** -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -74,10 +74,10 @@ cy_en_mcwdt_status_t Cy_MCWDT_Init(MCWDT_STRUCT_Type *base, cy_stc_mcwdt_config_ _VAL2FLD(MCWDT_STRUCT_MCWDT_CONFIG_WDT_MODE1, config->c1Mode) | (config->c0c1Cascade ? MCWDT_STRUCT_MCWDT_CONFIG_WDT_CASCADE0_1_Msk : 0UL) | _VAL2FLD(MCWDT_STRUCT_MCWDT_CONFIG_WDT_MODE0, config->c0Mode); - + ret = CY_MCWDT_SUCCESS; } - + return (ret); } @@ -121,14 +121,14 @@ void Cy_MCWDT_DeInit(MCWDT_STRUCT_Type *base) * The base pointer to a structure that describes the registers. * * \note -* The user must enable both counters, and cascade C0 to C1, -* before calling this function. C2 is not reported. +* The user must enable both counters, and cascade C0 to C1, +* before calling this function. C2 is not reported. * Instead, to get a 64-bit C2-C1-C0 cascaded value, the * user must call this function followed by * Cy_MCWDT_GetCount(base, CY_MCWDT_COUNTER2), and then combine the results. -* \note This function does not return the correct result when it is called -* after the Cy_MCWDT_Enable() or Cy_MCWDT_ResetCounters() function with -* a delay less than two lf_clk cycles. The recommended waitUs parameter +* \note This function does not return the correct result when it is called +* after the Cy_MCWDT_Enable() or Cy_MCWDT_ResetCounters() function with +* a delay less than two lf_clk cycles. The recommended waitUs parameter * value is 100 us. * * \return The value of combined C1-C0 cascaded counters. @@ -141,14 +141,14 @@ uint32_t Cy_MCWDT_GetCountCascaded(MCWDT_STRUCT_Type const *base) uint32_t counter0 = countVal & MCWDT_STRUCT_MCWDT_CNTLOW_WDT_CTR0_Msk; uint32_t match0 = _FLD2VAL(MCWDT_STRUCT_MCWDT_MATCH_WDT_MATCH0, MCWDT_STRUCT_MCWDT_MATCH(base)); uint32_t match1 = _FLD2VAL(MCWDT_STRUCT_MCWDT_MATCH_WDT_MATCH1, MCWDT_STRUCT_MCWDT_MATCH(base)); - - /* - * The counter counter0 goes to zero when it reaches the match0 - * value (c0ClearOnMatch = 1) or reaches the maximum - * value (c0ClearOnMatch = 0). The counter counter1 increments on - * the next rising edge of the MCWDT clock after - * the Clear On Match event takes place. - * The software increments counter1 to eliminate the case + + /* + * The counter counter0 goes to zero when it reaches the match0 + * value (c0ClearOnMatch = 1) or reaches the maximum + * value (c0ClearOnMatch = 0). The counter counter1 increments on + * the next rising edge of the MCWDT clock after + * the Clear On Match event takes place. + * The software increments counter1 to eliminate the case * when the both counter0 and counter1 counters have zeros. */ if (0UL == counter0) @@ -160,17 +160,17 @@ uint32_t Cy_MCWDT_GetCountCascaded(MCWDT_STRUCT_Type const *base) if (0UL == _FLD2VAL(MCWDT_STRUCT_MCWDT_CONFIG_WDT_CLEAR0, MCWDT_STRUCT_MCWDT_CONFIG(base))) { /* Save match0 value with the correction when counter0 - * goes to zero when it reaches the match0 value. + * goes to zero when it reaches the match0 value. */ countVal = match0 + 1UL; - - if (0UL != counter1) + + if (0UL != counter1) { /* Set match to the maximum value */ - match0 = MCWDT_STRUCT_MCWDT_CNTLOW_WDT_CTR0_Msk; + match0 = MCWDT_STRUCT_MCWDT_CNTLOW_WDT_CTR0_Msk; } - - if (countVal < counter0) + + if (countVal < counter0) { /* Decrement counter1 when the counter0 is great than match0 value */ counter1--; @@ -179,7 +179,7 @@ uint32_t Cy_MCWDT_GetCountCascaded(MCWDT_STRUCT_Type const *base) /* Add the correction to counter0 */ counter0 += counter1; - + /* Set counter1 match value to 65535 when the counter1 is free running */ if (0UL == _FLD2VAL(MCWDT_STRUCT_MCWDT_CONFIG_WDT_CLEAR1, MCWDT_STRUCT_MCWDT_CONFIG(base))) { @@ -191,9 +191,9 @@ uint32_t Cy_MCWDT_GetCountCascaded(MCWDT_STRUCT_Type const *base) { /* Reset counter0 to disable the added correction of the counter1 value */ counter0 = 0UL; - - /* Reset counter1 to prevent the wrong cascaded value calculation - * because counter1 is updated only on the following clock edge after clearing counter0 + + /* Reset counter1 to prevent the wrong cascaded value calculation + * because counter1 is updated only on the following clock edge after clearing counter0 */ counter1 = 0UL; } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_pdm_pcm.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_pdm_pcm.c index 43146b8cd1..7031bb58d0 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_pdm_pcm.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_pdm_pcm.c @@ -1,12 +1,12 @@ /***************************************************************************//** * \file cy_pdm_pcm.c -* \version 2.20.1 +* \version 2.20.2 * * The source code file for the PDM_PCM driver. * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -68,11 +68,11 @@ cy_en_pdm_pcm_status_t Cy_PDM_PCM_Init(PDM_Type * base, cy_stc_pdm_pcm_config_t CY_ASSERT_L3(CY_PDM_PCM_IS_HPF_GAIN_VALID(config->highPassFilterGain)); CY_ASSERT_L3(CY_PDM_PCM_IS_WORD_LEN_VALID(config->wordLen)); CY_ASSERT_L3(CY_PDM_PCM_IS_TRIG_LEVEL(config->rxFifoTriggerLevel, config->chanSelect)); - + ret = CY_PDM_PCM_SUCCESS; PDM_PCM_CTL(base) &= (uint32_t) ~PDM_CTL_ENABLED_Msk; /* Disable the PDM_PCM block */ - + /* The clock setting */ PDM_PCM_CLOCK_CTL(base) = _VAL2FLD(PDM_CLOCK_CTL_CLK_CLOCK_DIV, config->clkDiv) | _VAL2FLD(PDM_CLOCK_CTL_MCLKQ_CLOCK_DIV, config->mclkDiv) | @@ -148,7 +148,7 @@ void Cy_PDM_PCM_SetGain(PDM_Type * base, cy_en_pdm_pcm_chan_select_t chan, cy_en { CY_ASSERT_L3(CY_PDM_PCM_IS_CHAN_VALID(chan)); CY_ASSERT_L3(CY_PDM_PCM_IS_GAIN_VALID(gain)); - + if (chan == CY_PDM_PCM_CHAN_LEFT) { CY_REG32_CLR_SET(PDM_PCM_CTL(base), PDM_CTL_PGA_L, ((uint32_t) gain)); @@ -178,7 +178,7 @@ void Cy_PDM_PCM_SetGain(PDM_Type * base, cy_en_pdm_pcm_chan_select_t chan, cy_en cy_en_pdm_pcm_gain_t Cy_PDM_PCM_GetGain(PDM_Type const * base, cy_en_pdm_pcm_chan_select_t chan) { cy_en_pdm_pcm_gain_t ret; - + CY_ASSERT_L3(CY_PDM_PCM_IS_CHAN_VALID(chan)); if (chan == CY_PDM_PCM_CHAN_LEFT) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_pra.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_pra.c new file mode 100644 index 0000000000..fe93891641 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_pra.c @@ -0,0 +1,1921 @@ +/***************************************************************************//** +* \file cy_pra.c +* \version 1.0 +* +* \brief The source code file for the PRA driver. The API is not intended to +* be used directly by the user application. +* +******************************************************************************** +* \copyright +* Copyright 2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#include "cy_pra.h" +#include "cy_pra_cfg.h" +#include "cy_sysint.h" +#include "cy_ipc_drv.h" +#include "cy_gpio.h" +#include "cy_device.h" +#include "cy_syspm.h" + +#if defined (CY_DEVICE_SECURE) || defined (CY_DOXYGEN) + +#define CY_PRA_REG_POLICY_WRITE_ALL (0x00000000UL) +#define CY_PRA_REG_POLICY_WRITE_NONE (0xFFFFFFFFUL) + +/* The table to get a register address based on its index */ +cy_stc_pra_reg_policy_t regIndexToAddr[CY_PRA_REG_INDEX_COUNT]; + +#if (CY_CPU_CORTEX_M4) + static IPC_STRUCT_Type *ipcPraBase = NULL; +#endif /* (CY_CPU_CORTEX_M0P) */ + + +#if (CY_CPU_CORTEX_M0P) || defined (CY_DOXYGEN) + static void Cy_PRA_Handler(void); + static void Cy_PRA_ProcessCmd(cy_stc_pra_msg_t *message); + static void Cy_PRA_PmHibernate(uint32_t funcProc); + static void Cy_PRA_PmCm4DpFlagSet(void); + static cy_en_pra_status_t Cy_PRA_ClkDSBeforeTransition(void); + static cy_en_pra_status_t Cy_PRA_ClkDSAfterTransition(void); + static bool Cy_PRA_RegAccessRangeValid(uint16_t index); +#endif /* (CY_CPU_CORTEX_M0P) || defined (CY_DOXYGEN) */ + + +/******************************************************************************* +* Function Name: Cy_PRA_Init +****************************************************************************//** +* +* Initializes the PRA driver: +* - Initializes the register access array with the register addresses (Cortex-M0+) +* - Sets up the IPC communication between CPU cores +* +* Call the function before accessing any protected registers. +* It is called during a device startup from \ref SystemInit(). +* +*******************************************************************************/ +void Cy_PRA_Init(void) +{ + +#if (CY_CPU_CORTEX_M0P) + for (uint32_t i = 0UL; i < CY_PRA_REG_INDEX_COUNT; i++) + { + regIndexToAddr[i].writeMask = CY_PRA_REG_POLICY_WRITE_ALL; + } + regIndexToAddr[CY_PRA_INDX_SRSS_PWR_LVD_CTL].addr = &SRSS_PWR_LVD_CTL; + regIndexToAddr[CY_PRA_INDX_SRSS_SRSS_INTR].addr = &SRSS_SRSS_INTR; + regIndexToAddr[CY_PRA_INDX_SRSS_SRSS_INTR_SET].addr = &SRSS_SRSS_INTR_SET; + regIndexToAddr[CY_PRA_INDX_SRSS_SRSS_INTR_MASK].addr = &SRSS_SRSS_INTR_MASK; + regIndexToAddr[CY_PRA_INDX_SRSS_SRSS_INTR_CFG].addr = &SRSS_SRSS_INTR_CFG; + regIndexToAddr[CY_PRA_INDX_SRSS_CLK_ROOT_SELECT_1].addr = &SRSS_CLK_ROOT_SELECT[1U]; + regIndexToAddr[CY_PRA_INDX_SRSS_CLK_ROOT_SELECT_2].addr = &SRSS_CLK_ROOT_SELECT[2U]; + regIndexToAddr[CY_PRA_INDX_SRSS_CLK_ROOT_SELECT_3].addr = &SRSS_CLK_ROOT_SELECT[3U]; + regIndexToAddr[CY_PRA_INDX_SRSS_CLK_ROOT_SELECT_4].addr = &SRSS_CLK_ROOT_SELECT[4U]; + regIndexToAddr[CY_PRA_INDX_SRSS_CLK_ROOT_SELECT_5].addr = (CY_SRSS_NUM_HFROOT > 4U) ? &SRSS_CLK_ROOT_SELECT[5U] : 0U; + regIndexToAddr[CY_PRA_INDX_SRSS_CLK_ROOT_SELECT_6].addr = (CY_SRSS_NUM_HFROOT > 5U) ? &SRSS_CLK_ROOT_SELECT[6U] : 0U; + regIndexToAddr[CY_PRA_INDX_FLASHC_FLASH_CMD].addr = &FLASHC_FLASH_CMD; + regIndexToAddr[CY_PRA_INDX_SRSS_PWR_HIBERNATE].addr = &SRSS_PWR_HIBERNATE; + regIndexToAddr[CY_PRA_INDX_SRSS_PWR_HIBERNATE].writeMask = (uint32_t) ~ (SRSS_PWR_HIBERNATE_TOKEN_Msk | + SRSS_PWR_HIBERNATE_POLARITY_HIBPIN_Msk | + SRSS_PWR_HIBERNATE_MASK_HIBPIN_Msk | + SRSS_PWR_HIBERNATE_MASK_HIBALARM_Msk | + SRSS_PWR_HIBERNATE_MASK_HIBWDT_Msk); + regIndexToAddr[CY_PRA_INDX_SRSS_CLK_MFO_CONFIG].addr = &SRSS_CLK_MFO_CONFIG; + regIndexToAddr[CY_PRA_INDX_SRSS_CLK_MF_SELECT].addr = &SRSS_CLK_MF_SELECT; + regIndexToAddr[CY_PRA_INDX_FLASHC_FM_CTL_BOOKMARK].addr = &FLASHC_FM_CTL_BOOKMARK; + regIndexToAddr[CY_PRA_INDX_FLASHC_FM_CTL_BOOKMARK].writeMask= CY_PRA_REG_POLICY_WRITE_NONE; + + /* Configures the IPC interrupt handler. */ + Cy_IPC_Drv_SetInterruptMask(Cy_IPC_Drv_GetIntrBaseAddr(CY_IPC_INTR_PRA), CY_PRA_IPC_NONE_INTR, CY_PRA_IPC_CHAN_INTR); + cy_stc_sysint_t intr = { + .intrSrc = (IRQn_Type)CY_SYSINT_CM0P_MUX4, + .cm0pSrc = (cy_en_intr_t)(int32_t) CY_IPC_INTR_NUM_TO_VECT((int32_t) CY_IPC_INTR_PRA), + .intrPriority = 0UL + }; + (void) Cy_SysInt_Init(&intr, &Cy_PRA_Handler); + NVIC_EnableIRQ(intr.intrSrc); +#else + + /* Need to get this address in RAM, because there are use cases + * where this address is used but flash is not accessible + */ + ipcPraBase = Cy_IPC_Drv_GetIpcBaseAddress(CY_IPC_CHAN_PRA); +#endif /* (CY_CPU_CORTEX_M0P) */ +} + + +#if (CY_CPU_CORTEX_M0P) || defined (CY_DOXYGEN) +/******************************************************************************* +* Function Name: Cy_PRA_Handler +****************************************************************************//** +* +* The IPC interrupt handler on Cortex-M0+ core is called after there is a +* request from the Cortex-M4 core. +* +*******************************************************************************/ +static void Cy_PRA_Handler(void) +{ + cy_stc_pra_msg_t msgLocal; + cy_stc_pra_msg_t* msgRemote; + + /* Processes an internal command copy and updates the original value */ + msgRemote = (cy_stc_pra_msg_t *)Cy_IPC_Drv_ReadDataValue(Cy_IPC_Drv_GetIpcBaseAddress(CY_IPC_CHAN_PRA)); + + msgLocal = *msgRemote; + Cy_PRA_ProcessCmd(&msgLocal); + *msgRemote = msgLocal; + + /* Clears the interrupt logic to detect a next interrupt */ + Cy_IPC_Drv_ClearInterrupt(Cy_IPC_Drv_GetIntrBaseAddr(CY_IPC_INTR_PRA), CY_PRA_IPC_NONE_INTR, CY_PRA_IPC_CHAN_INTR); + + (void) Cy_IPC_Drv_LockRelease(Cy_IPC_Drv_GetIpcBaseAddress(CY_IPC_CHAN_PRA), CY_PRA_IPC_NONE_INTR); +} + + +/******************************************************************************* +* Function Name: Cy_PRA_ProcessCmd +****************************************************************************//** +* +* Processes and executes the command on Cortex-M0+ which was received from +* the Cortex-M4 application. +* +* \param message cy_stc_pra_msg_t +* +*******************************************************************************/ +static void Cy_PRA_ProcessCmd(cy_stc_pra_msg_t *message) +{ + static uint32_t structInit = CY_PRA_STRUCT_NOT_INITIALIZED; + static cy_stc_pra_system_config_t structCpy = {0UL}; + + CY_ASSERT_L1(NULL != message); + + + switch (message->praCommand) + { + case CY_PRA_MSG_TYPE_REG32_CLR_SET: + /* Reports an error if any of the following conditions is false: + * - A new value (message->praData2) has zeros in the write-protected fields + * - The register index is within the valid range. + */ + if ((0U == (message->praData2 & regIndexToAddr[message->praIndex].writeMask)) && + (CY_PRA_REG_POLICY_WRITE_NONE != regIndexToAddr[message->praIndex].writeMask) && + (Cy_PRA_RegAccessRangeValid(message->praIndex))) + { + uint32_t tmp; + + tmp = CY_GET_REG32(regIndexToAddr[message->praIndex].addr); + + tmp &= (message->praData1 | regIndexToAddr[message->praIndex].writeMask); + tmp |= message->praData2; + CY_SET_REG32(regIndexToAddr[message->praIndex].addr, tmp); + message->praStatus = CY_PRA_STATUS_SUCCESS; + } + else + { + message->praStatus = CY_PRA_STATUS_ACCESS_DENIED; + } + break; + + case CY_PRA_MSG_TYPE_REG32_SET: + /* Reports an error if any of the following conditions is false: + * - A new value (message->praData1) has zeros in the write-protected fields + * - The register index is within the valid range. + */ + if ((0U == (message->praData1 & regIndexToAddr[message->praIndex].writeMask)) && + (CY_PRA_REG_POLICY_WRITE_NONE != regIndexToAddr[message->praIndex].writeMask) && + (Cy_PRA_RegAccessRangeValid(message->praIndex))) + { + uint32_t tmp; + + tmp = CY_GET_REG32(regIndexToAddr[message->praIndex].addr); + + /* Clears the bits allowed to write */ + tmp &= regIndexToAddr[message->praIndex].writeMask; + + /* Sets the allowed bits based on the new value. + * The write-protected fields have zeros in the new value, so no additional checks needed + */ + tmp |= message->praData1; + CY_SET_REG32(regIndexToAddr[message->praIndex].addr, tmp); + message->praStatus = CY_PRA_STATUS_SUCCESS; + } + else + { + message->praStatus = CY_PRA_STATUS_ACCESS_DENIED; + } + break; + + case CY_PRA_MSG_TYPE_REG32_GET: + if (Cy_PRA_RegAccessRangeValid(message->praIndex)) + { + message->praData1 = CY_GET_REG32(regIndexToAddr[message->praIndex].addr); + message->praStatus = CY_PRA_STATUS_SUCCESS; + } + else + { + message->praStatus = CY_PRA_STATUS_ACCESS_DENIED; + } + break; + + case CY_PRA_MSG_TYPE_CM0_WAKEUP: + message->praStatus = CY_PRA_STATUS_SUCCESS; + break; + + case CY_PRA_MSG_TYPE_SYS_CFG_FUNC: + CY_ASSERT_L1((cy_stc_pra_system_config_t *)(message->praData1) != NULL); + if( NULL != (cy_stc_pra_system_config_t *)(message->praData1)) + { + structCpy = *((cy_stc_pra_system_config_t *)(message->praData1)); + message->praStatus = Cy_PRA_SystemConfig(&structCpy); + if((CY_PRA_STRUCT_NOT_INITIALIZED == structInit) && (CY_PRA_STATUS_SUCCESS == message->praStatus)) + { + structInit = CY_PRA_STRUCT_INITIALIZED; + } + } + else + { + message->praStatus = CY_PRA_STATUS_INVALID_PARAM; + } + break; + + case CY_PRA_MSG_TYPE_SECURE_ONLY: + switch (message->praIndex) + { + case CY_PRA_PM_FUNC_HIBERNATE: + Cy_PRA_PmHibernate(message->praData1); + message->praStatus = CY_PRA_STATUS_SUCCESS; + break; + + case CY_PRA_PM_FUNC_CM4_DP_FLAG_SET: + Cy_PRA_PmCm4DpFlagSet(); + message->praStatus = CY_PRA_STATUS_SUCCESS; + break; + + case CY_PRA_CLK_FUNC_DS_BEFORE_TRANSITION: + message->praStatus = Cy_PRA_ClkDSBeforeTransition(); + break; + + case CY_PRA_CLK_FUNC_DS_AFTER_TRANSITION: + message->praStatus = Cy_PRA_ClkDSAfterTransition(); + break; + + case CY_PRA_PM_FUNC_BUCK_ENABLE_VOLTAGE2: + Cy_SysPm_BuckEnableVoltage2(); + message->praStatus = CY_PRA_STATUS_SUCCESS; + break; + + case CY_PRA_PM_FUNC_BUCK_DISABLE_VOLTAGE2: + Cy_SysPm_BuckDisableVoltage2(); + message->praStatus = CY_PRA_STATUS_SUCCESS; + break; + + case CY_PRA_PM_FUNC_BUCK_VOLTAGE2_HW_CTRL: + Cy_SysPm_BuckSetVoltage2HwControl((bool) message->praData1); + message->praStatus = CY_PRA_STATUS_SUCCESS; + break; + + case CY_PRA_PM_FUNC_BUCK_SET_VOLTAGE2: + if (CY_SYSPM_IS_BUCK_VOLTAGE2_VALID(((cy_stc_pra_voltage2_t *) message->praData1)->praVoltage)) + { + Cy_SysPm_BuckSetVoltage2(((cy_stc_pra_voltage2_t *) message->praData1)->praVoltage, + ((cy_stc_pra_voltage2_t *) message->praData1)->praWaitToSettle); + message->praStatus = CY_PRA_STATUS_SUCCESS; + } + else + { + message->praStatus = CY_PRA_STATUS_INVALID_PARAM; + } + break; + + default: + message->praStatus = CY_PRA_STATUS_ACCESS_DENIED; + break; + } + break; + + case CY_PRA_MSG_TYPE_FUNC_POLICY: + if(CY_PRA_STRUCT_NOT_INITIALIZED != structInit) + { + switch (message->praIndex) + { + case CY_PRA_PM_FUNC_LDO_SET_VOLTAGE: + { + bool powerEnableTmp, ldoEnableTmp, ulpEnableTmp; + powerEnableTmp = structCpy.powerEnable; /* old value backup */ + ldoEnableTmp = structCpy.ldoEnable; /* old value backup */ + ulpEnableTmp = structCpy.ulpEnable; /* old value backup */ + structCpy.powerEnable = true; + structCpy.ldoEnable = true; + structCpy.ldoVoltage = (cy_en_syspm_ldo_voltage_t)message->praData1; + if (structCpy.ldoVoltage == CY_SYSPM_LDO_VOLTAGE_0_9V) + { + structCpy.ulpEnable = true; + } + else + { + structCpy.ulpEnable = false; + } + message->praStatus = Cy_PRA_SystemConfig(&structCpy); + if (message->praStatus != CY_PRA_STATUS_SUCCESS) + { + /* On failure, previous values are restored */ + structCpy.powerEnable = powerEnableTmp; + structCpy.ldoEnable = ldoEnableTmp; + structCpy.ulpEnable = ulpEnableTmp; + } + } + break; + + case CY_PRA_PM_FUNC_BUCK_ENABLE: + { + bool powerEnableTmp, ldoEnableTmp, ulpEnableTmp; + powerEnableTmp = structCpy.powerEnable; /* Old value backup */ + ldoEnableTmp = structCpy.ldoEnable; /* Old value backup */ + ulpEnableTmp = structCpy.ulpEnable; /* Old value backup */ + structCpy.powerEnable = true; + structCpy.ldoEnable = false; + structCpy.buckVoltage = (cy_en_syspm_buck_voltage1_t)message->praData1; + if (structCpy.buckVoltage == CY_SYSPM_BUCK_OUT1_VOLTAGE_0_9V) + { + structCpy.ulpEnable = true; + } + else + { + structCpy.ulpEnable = false; + } + message->praStatus = Cy_PRA_SystemConfig(&structCpy); + if (message->praStatus != CY_PRA_STATUS_SUCCESS) + { + /* On failure, previous values are restored */ + structCpy.powerEnable = powerEnableTmp; + structCpy.ldoEnable = ldoEnableTmp; + structCpy.ulpEnable = ulpEnableTmp; + } + } + break; + + case CY_PRA_PM_FUNC_SET_MIN_CURRENT: + { + bool powerEnableTmp, pwrCurrentModeMinTmp; + /* Backups old values */ + powerEnableTmp = structCpy.powerEnable; + pwrCurrentModeMinTmp = structCpy.pwrCurrentModeMin; + structCpy.powerEnable = true; + structCpy.pwrCurrentModeMin = true; + message->praStatus = Cy_PRA_SystemConfig(&structCpy); + if (message->praStatus != CY_PRA_STATUS_SUCCESS) + { + /* On failure, previous values are restored */ + structCpy.powerEnable = powerEnableTmp; + structCpy.pwrCurrentModeMin = pwrCurrentModeMinTmp; + } + } + break; + + case CY_PRA_PM_FUNC_SET_NORMAL_CURRENT: + { + bool powerEnableTmp, pwrCurrentModeMinTmp; + /* Backups old values */ + powerEnableTmp = structCpy.powerEnable; + pwrCurrentModeMinTmp = structCpy.pwrCurrentModeMin; + structCpy.powerEnable = true; + structCpy.pwrCurrentModeMin = false; + message->praStatus = Cy_PRA_SystemConfig(&structCpy); + if (message->praStatus != CY_PRA_STATUS_SUCCESS) + { + /* On failure, previous values are restored */ + structCpy.powerEnable = powerEnableTmp; + structCpy.pwrCurrentModeMin = pwrCurrentModeMinTmp; + } + } + break; + + case CY_PRA_CLK_FUNC_ECO_DISABLE: + { + bool ecoEnableTmp; + /* Backups old values */ + ecoEnableTmp = structCpy.ecoEnable; + structCpy.ecoEnable = false; + message->praStatus = Cy_PRA_SystemConfig(&structCpy); + if (message->praStatus != CY_PRA_STATUS_SUCCESS) + { + /* On failure, previous values are restored */ + structCpy.ecoEnable = ecoEnableTmp; + } + } + break; + + case CY_PRA_CLK_FUNC_FLL_DISABLE: + { + bool fllEnableTmp; + uint32_t fllOutFreqHzTmp; + /* Backups old values */ + fllOutFreqHzTmp = structCpy.fllOutFreqHz; + fllEnableTmp = structCpy.fllEnable; + structCpy.fllEnable = false; + structCpy.fllOutFreqHz = CY_PRA_DEFAULT_ZERO; + message->praStatus = Cy_PRA_SystemConfig(&structCpy); + if (message->praStatus != CY_PRA_STATUS_SUCCESS) + { + /* On failure, previous values are restored */ + structCpy.fllEnable = fllEnableTmp; + structCpy.fllOutFreqHz = fllOutFreqHzTmp; + } + } + break; + + case CY_PRA_CLK_FUNC_PLL_DISABLE: + { + bool pllEnable; + if (((message->praData1) > CY_PRA_CLKPATH_0) && ((message->praData1) <= CY_SRSS_NUM_PLL)) /* 0 is invalid pll number */ + { + /* Backups old values */ + ((message->praData1) == CY_PRA_CLKPLL_1) ? (pllEnable = structCpy.pll0Enable) : (pllEnable = structCpy.pll1Enable); + + ((message->praData1) == CY_PRA_CLKPLL_1) ? (structCpy.pll0Enable = false) : (structCpy.pll1Enable = false); + + message->praStatus = Cy_PRA_SystemConfig(&structCpy); + + if (message->praStatus != CY_PRA_STATUS_SUCCESS) + { + /* On failure, previous values are restored */ + ((message->praData1) == CY_PRA_CLKPLL_1) ? (structCpy.pll0Enable = pllEnable) : (structCpy.pll1Enable = pllEnable); + } + } + else + { + message->praStatus = CY_PRA_STATUS_INVALID_PARAM_PLL_NUM; + } + } + break; + + case CY_PRA_CLK_FUNC_ILO_ENABLE: + { + bool iloEnableTmp; + /* Backups old values */ + iloEnableTmp = structCpy.iloEnable; + structCpy.iloEnable = true; + message->praStatus = Cy_PRA_SystemConfig(&structCpy); + if (message->praStatus != CY_PRA_STATUS_SUCCESS) + { + /* On failure, previous values are restored */ + structCpy.iloEnable = iloEnableTmp; + } + } + break; + + case CY_PRA_CLK_FUNC_ILO_DISABLE: + { + bool iloEnableTmp; + /* Backups old values */ + iloEnableTmp = structCpy.iloEnable; + structCpy.iloEnable = false; + message->praStatus = Cy_PRA_SystemConfig(&structCpy); + if (message->praStatus != CY_PRA_STATUS_SUCCESS) + { + /* On failure, previous values are restored */ + structCpy.iloEnable = iloEnableTmp; + } + } + break; + + case CY_PRA_CLK_FUNC_ILO_HIBERNATE_ON: + { + bool iloHibernateOnTmp; + /* Backups old values */ + iloHibernateOnTmp = structCpy.iloHibernateON; + structCpy.iloHibernateON = (CY_PRA_DATA_DISABLE != message->praData1); + message->praStatus = Cy_PRA_SystemConfig(&structCpy); + if (message->praStatus != CY_PRA_STATUS_SUCCESS) + { + /* On failure, previous values are restored */ + structCpy.iloHibernateON = iloHibernateOnTmp; + } + } + break; + + case CY_PRA_CLK_FUNC_PILO_ENABLE: + { + bool piloEnableTmp; + /* Backups old values */ + piloEnableTmp = structCpy.piloEnable; + structCpy.piloEnable = true; + message->praStatus = Cy_PRA_SystemConfig(&structCpy); + if (message->praStatus != CY_PRA_STATUS_SUCCESS) + { + /* On failure, previous values are restored */ + structCpy.piloEnable = piloEnableTmp; + } + } + break; + + case CY_PRA_CLK_FUNC_PILO_DISABLE: + { + bool piloEnableTmp; + /* Backups old values */ + piloEnableTmp = structCpy.piloEnable; + structCpy.piloEnable = false; + message->praStatus = Cy_PRA_SystemConfig(&structCpy); + if (message->praStatus != CY_PRA_STATUS_SUCCESS) + { + /* On failure, previous values are restored */ + structCpy.piloEnable = piloEnableTmp; + } + } + break; + + case CY_PRA_CLK_FUNC_WCO_ENABLE: + { + bool wcoEnableTmp; + /* Backups old values */ + wcoEnableTmp = structCpy.wcoEnable; + structCpy.wcoEnable = true; + message->praStatus = Cy_PRA_SystemConfig(&structCpy); + if (message->praStatus != CY_PRA_STATUS_SUCCESS) + { + /* On failure, previous values are restored */ + structCpy.wcoEnable = wcoEnableTmp; + } + } + break; + + case CY_PRA_CLK_FUNC_WCO_DISABLE: + { + bool wcoEnableTmp; + /* Backups old values */ + wcoEnableTmp = structCpy.wcoEnable; + structCpy.wcoEnable = false; + message->praStatus = Cy_PRA_SystemConfig(&structCpy); + if (message->praStatus != CY_PRA_STATUS_SUCCESS) + { + /* On failure, previous values are restored */ + structCpy.wcoEnable = wcoEnableTmp; + } + } + break; + + case CY_PRA_CLK_FUNC_WCO_BYPASS: + { + bool bypassEnableTmp; + /* Backups old values */ + bypassEnableTmp = structCpy.bypassEnable; + structCpy.bypassEnable = ((cy_en_wco_bypass_modes_t) message->praData1 == CY_SYSCLK_WCO_BYPASSED) ? true : false; + message->praStatus = CY_PRA_STATUS_SUCCESS; + /* The bypass value will be written to the register only when WCO is enabled */ + if (structCpy.wcoEnable) + { + message->praStatus = Cy_PRA_SystemConfig(&structCpy); + if (message->praStatus != CY_PRA_STATUS_SUCCESS) + { + /* On failure, previous values are restored */ + structCpy.bypassEnable = bypassEnableTmp; + } + } + } + break; + + case CY_PRA_CLK_FUNC_HF_ENABLE: + { + bool clkHFEnable; + message->praStatus = CY_PRA_STATUS_SUCCESS; + /* Backups old values */ + switch (message->praData1) + { + case CY_PRA_CLKHF_0: + clkHFEnable = structCpy.clkHF0Enable; + structCpy.clkHF0Enable = true; + break; + + case CY_PRA_CLKHF_1: + clkHFEnable = structCpy.clkHF1Enable; + structCpy.clkHF1Enable = true; + break; + + case CY_PRA_CLKHF_2: + clkHFEnable = structCpy.clkHF2Enable; + structCpy.clkHF2Enable = true; + break; + + case CY_PRA_CLKHF_3: + clkHFEnable = structCpy.clkHF3Enable; + structCpy.clkHF3Enable = true; + break; + + case CY_PRA_CLKHF_4: + clkHFEnable = structCpy.clkHF4Enable; + structCpy.clkHF4Enable = true; + break; + + case CY_PRA_CLKHF_5: + clkHFEnable = structCpy.clkHF5Enable; + structCpy.clkHF5Enable = true; + break; + + default: + clkHFEnable = false; + message->praStatus = CY_PRA_STATUS_ACCESS_DENIED; + break; + + } + if (message->praStatus == CY_PRA_STATUS_SUCCESS) + { + message->praStatus = Cy_PRA_SystemConfig(&structCpy); + if (message->praStatus != CY_PRA_STATUS_SUCCESS) + { + /* On failure, previous values are restored */ + switch (message->praData1) + { + case CY_PRA_CLKHF_0: + structCpy.clkHF0Enable = clkHFEnable; + break; + + case CY_PRA_CLKHF_1: + structCpy.clkHF1Enable = clkHFEnable; + break; + + case CY_PRA_CLKHF_2: + structCpy.clkHF2Enable = clkHFEnable; + break; + + case CY_PRA_CLKHF_3: + structCpy.clkHF3Enable = clkHFEnable; + break; + + case CY_PRA_CLKHF_4: + structCpy.clkHF4Enable = clkHFEnable; + break; + + case CY_PRA_CLKHF_5: + structCpy.clkHF5Enable = clkHFEnable; + break; + + default: + break; + } + } + } + } + break; + + case CY_PRA_CLK_FUNC_HF_DISABLE: + { + bool clkHFEnable; + message->praStatus = CY_PRA_STATUS_SUCCESS; + /* Backups old values */ + switch (message->praData1) + { + case CY_PRA_CLKHF_0: + clkHFEnable = structCpy.clkHF0Enable; + structCpy.clkHF0Enable = false; + break; + + case CY_PRA_CLKHF_1: + clkHFEnable = structCpy.clkHF1Enable; + structCpy.clkHF1Enable = false; + break; + + case CY_PRA_CLKHF_2: + clkHFEnable = structCpy.clkHF2Enable; + structCpy.clkHF2Enable = false; + break; + + case CY_PRA_CLKHF_3: + clkHFEnable = structCpy.clkHF3Enable; + structCpy.clkHF3Enable = false; + break; + + case CY_PRA_CLKHF_4: + clkHFEnable = structCpy.clkHF4Enable; + structCpy.clkHF4Enable = false; + break; + + case CY_PRA_CLKHF_5: + clkHFEnable = structCpy.clkHF5Enable; + structCpy.clkHF5Enable = false; + break; + + default: + clkHFEnable = false; + message->praStatus = CY_PRA_STATUS_ACCESS_DENIED; + break; + + } + if (message->praStatus == CY_PRA_STATUS_SUCCESS) + { + message->praStatus = Cy_PRA_SystemConfig(&structCpy); + if (message->praStatus != CY_PRA_STATUS_SUCCESS) + { + /* On failure, previous values are restored */ + switch (message->praData1) + { + case CY_PRA_CLKHF_0: + structCpy.clkHF0Enable = clkHFEnable; + break; + + case CY_PRA_CLKHF_1: + structCpy.clkHF1Enable = clkHFEnable; + break; + + case CY_PRA_CLKHF_2: + structCpy.clkHF2Enable = clkHFEnable; + break; + + case CY_PRA_CLKHF_3: + structCpy.clkHF3Enable = clkHFEnable; + break; + + case CY_PRA_CLKHF_4: + structCpy.clkHF4Enable = clkHFEnable; + break; + + case CY_PRA_CLKHF_5: + structCpy.clkHF5Enable = clkHFEnable; + break; + + default: + break; + } + } + } + } + break; + + case CY_PRA_CLK_FUNC_HF_SET_SOURCE: + { + cy_en_clkhf_in_sources_t hfSource; + uint32_t hfOutFreqMHz; + bool hfEnabled; + message->praStatus = CY_PRA_STATUS_SUCCESS; + /* Backups old values */ + switch (((cy_stc_pra_clkhfsetsource_t *) message->praData1)->clkHf) + { + case CY_PRA_CLKHF_0: + hfSource = structCpy.hf0Source; + structCpy.hf0Source = ((cy_stc_pra_clkhfsetsource_t *) message->praData1)->source; + hfOutFreqMHz = structCpy.hf0OutFreqMHz; + hfEnabled = structCpy.clkHF0Enable; + /* The HF output frequency is not present in the PDL API argument. Update the system config structure with the current HF output frequency value */ + structCpy.hf0OutFreqMHz = (Cy_SysClk_ClkPathGetFrequency((uint32_t) structCpy.hf0Source)/(1UL << structCpy.hf0Divider))/CY_PRA_FREQUENCY_HZ_CONVERSION; + break; + + case CY_PRA_CLKHF_1: + hfSource = structCpy.hf1Source; + structCpy.hf1Source = ((cy_stc_pra_clkhfsetsource_t *) message->praData1)->source; + hfOutFreqMHz = structCpy.hf1OutFreqMHz; + hfEnabled = structCpy.clkHF1Enable; + /* The HF output frequency is not present in the PDL API argument. Update the system config structure with thecurrent HF output frequency value */ + structCpy.hf1OutFreqMHz = (Cy_SysClk_ClkPathGetFrequency((uint32_t) structCpy.hf1Source)/(1UL << structCpy.hf1Divider))/CY_PRA_FREQUENCY_HZ_CONVERSION; + break; + + case CY_PRA_CLKHF_2: + hfSource = structCpy.hf2Source; + structCpy.hf2Source = ((cy_stc_pra_clkhfsetsource_t *) message->praData1)->source; + hfOutFreqMHz = structCpy.hf2OutFreqMHz; + hfEnabled = structCpy.clkHF2Enable; + /* The HF output frequency is not present in the PDL API argument. Update the system config structure with the current HF output frequency value */ + structCpy.hf2OutFreqMHz = (Cy_SysClk_ClkPathGetFrequency((uint32_t) structCpy.hf2Source)/(1UL << structCpy.hf2Divider))/CY_PRA_FREQUENCY_HZ_CONVERSION; + break; + + case CY_PRA_CLKHF_3: + hfSource = structCpy.hf3Source; + structCpy.hf3Source = ((cy_stc_pra_clkhfsetsource_t *) message->praData1)->source; + hfOutFreqMHz = structCpy.hf3OutFreqMHz; + hfEnabled = structCpy.clkHF3Enable; + /* The HF output frequency is not present in the PDL API argument. Update the system config structure with the current HF output frequency value */ + structCpy.hf3OutFreqMHz = (Cy_SysClk_ClkPathGetFrequency((uint32_t) structCpy.hf3Source)/(1UL << structCpy.hf3Divider))/CY_PRA_FREQUENCY_HZ_CONVERSION; + break; + + case CY_PRA_CLKHF_4: + hfSource = structCpy.hf4Source; + structCpy.hf4Source = ((cy_stc_pra_clkhfsetsource_t *) message->praData1)->source; + hfOutFreqMHz = structCpy.hf4OutFreqMHz; + hfEnabled = structCpy.clkHF4Enable; + /* The HF output frequency is not present in the PDL API argument. Update the system config structure with the current HF output frequency value */ + structCpy.hf4OutFreqMHz = (Cy_SysClk_ClkPathGetFrequency((uint32_t) structCpy.hf4Source)/(1UL << structCpy.hf4Divider))/CY_PRA_FREQUENCY_HZ_CONVERSION; + break; + + case CY_PRA_CLKHF_5: + hfSource = structCpy.hf5Source; + structCpy.hf5Source = ((cy_stc_pra_clkhfsetsource_t *) message->praData1)->source; + hfOutFreqMHz = structCpy.hf5OutFreqMHz; + hfEnabled = structCpy.clkHF5Enable; + /* The HF output frequency is not present in the PDL API argument. Update the system config structure with the current HF output frequency value */ + structCpy.hf5OutFreqMHz = (Cy_SysClk_ClkPathGetFrequency((uint32_t) structCpy.hf5Source)/(1UL << structCpy.hf5Divider))/CY_PRA_FREQUENCY_HZ_CONVERSION; + break; + + default: + hfEnabled = false; + message->praStatus = CY_PRA_STATUS_ACCESS_DENIED; + break; + } + /* The HF source value is updated in the register only when + * that particular HF is enabled. Otherwise, it is stored in + * the system config structure + */ + if ((message->praStatus == CY_PRA_STATUS_SUCCESS) && (hfEnabled)) + { + message->praStatus = Cy_PRA_SystemConfig(&structCpy); + if (message->praStatus != CY_PRA_STATUS_SUCCESS) + { + /* On failure, previous values are restored */ + switch (((cy_stc_pra_clkhfsetsource_t *) message->praData1)->clkHf) + { + case CY_PRA_CLKHF_0: + structCpy.hf0Source = hfSource; + structCpy.hf0OutFreqMHz = hfOutFreqMHz; + break; + + case CY_PRA_CLKHF_1: + structCpy.hf1Source = hfSource; + structCpy.hf1OutFreqMHz = hfOutFreqMHz; + break; + + case CY_PRA_CLKHF_2: + structCpy.hf2Source = hfSource; + structCpy.hf2OutFreqMHz = hfOutFreqMHz; + break; + + case CY_PRA_CLKHF_3: + structCpy.hf3Source = hfSource; + structCpy.hf3OutFreqMHz = hfOutFreqMHz; + break; + + case CY_PRA_CLKHF_4: + structCpy.hf4Source = hfSource; + structCpy.hf4OutFreqMHz = hfOutFreqMHz; + break; + + case CY_PRA_CLKHF_5: + structCpy.hf5Source = hfSource; + structCpy.hf5OutFreqMHz = hfOutFreqMHz; + break; + + default: + break; + } + } + } + } + break; + + case CY_PRA_CLK_FUNC_HF_SET_DIVIDER: + { + cy_en_clkhf_dividers_t hfDivider; + uint32_t hfOutFreqMHz; + bool hfEnabled; + message->praStatus = CY_PRA_STATUS_SUCCESS; + /* Backups old values */ + switch (((cy_stc_pra_clkhfsetdivider_t *) message->praData1)->clkHf) + { + case CY_PRA_CLKHF_0: + hfDivider = structCpy.hf0Divider; + structCpy.hf0Divider = ((cy_stc_pra_clkhfsetdivider_t *) message->praData1)->divider; + hfOutFreqMHz = structCpy.hf0OutFreqMHz; + hfEnabled = structCpy.clkHF0Enable; + /* The HF output frequency is not present in the PDL API argument. Update the system config structure with the current HF output frequency value */ + structCpy.hf0OutFreqMHz = (Cy_SysClk_ClkPathGetFrequency((uint32_t) structCpy.hf0Source)/(1UL << structCpy.hf0Divider))/CY_PRA_FREQUENCY_HZ_CONVERSION; + break; + + case CY_PRA_CLKHF_1: + hfDivider = structCpy.hf1Divider; + structCpy.hf1Divider = ((cy_stc_pra_clkhfsetdivider_t *) message->praData1)->divider; + hfOutFreqMHz = structCpy.hf1OutFreqMHz; + hfEnabled = structCpy.clkHF1Enable; + /* The HF output frequency is not present in the PDL API argument. Update the system config structure with the current HF output frequency value */ + structCpy.hf1OutFreqMHz = (Cy_SysClk_ClkPathGetFrequency((uint32_t) structCpy.hf1Source)/(1UL << structCpy.hf1Divider))/CY_PRA_FREQUENCY_HZ_CONVERSION; + break; + + case CY_PRA_CLKHF_2: + hfDivider = structCpy.hf2Divider; + structCpy.hf2Divider = ((cy_stc_pra_clkhfsetdivider_t *) message->praData1)->divider; + hfOutFreqMHz = structCpy.hf2OutFreqMHz; + hfEnabled = structCpy.clkHF2Enable; + /* The HF output frequency is not present in the PDL API argument. Update the system config structure with the current HF output frequency value */ + structCpy.hf2OutFreqMHz = (Cy_SysClk_ClkPathGetFrequency((uint32_t) structCpy.hf2Source)/(1UL << structCpy.hf2Divider))/CY_PRA_FREQUENCY_HZ_CONVERSION; + break; + + case CY_PRA_CLKHF_3: + hfDivider = structCpy.hf3Divider; + structCpy.hf3Divider = ((cy_stc_pra_clkhfsetdivider_t *) message->praData1)->divider; + hfOutFreqMHz = structCpy.hf3OutFreqMHz; + hfEnabled = structCpy.clkHF3Enable; + /* The HF output frequency is not present in the PDL API argument. Update the system config structure with the current HF output frequency value */ + structCpy.hf3OutFreqMHz = (Cy_SysClk_ClkPathGetFrequency((uint32_t) structCpy.hf3Source)/(1UL << structCpy.hf3Divider))/CY_PRA_FREQUENCY_HZ_CONVERSION; + break; + + case CY_PRA_CLKHF_4: + hfDivider = structCpy.hf4Divider; + structCpy.hf4Divider = ((cy_stc_pra_clkhfsetdivider_t *) message->praData1)->divider; + hfOutFreqMHz = structCpy.hf4OutFreqMHz; + hfEnabled = structCpy.clkHF4Enable; + /* The HF output frequency is not present in the PDL API argument. Update the system config structure with the current HF output frequency value */ + structCpy.hf4OutFreqMHz = (Cy_SysClk_ClkPathGetFrequency((uint32_t) structCpy.hf4Source)/(1UL << structCpy.hf4Divider))/CY_PRA_FREQUENCY_HZ_CONVERSION; + break; + + case CY_PRA_CLKHF_5: + hfDivider = structCpy.hf5Divider; + structCpy.hf5Divider = ((cy_stc_pra_clkhfsetdivider_t *) message->praData1)->divider; + hfOutFreqMHz = structCpy.hf5OutFreqMHz; + hfEnabled = structCpy.clkHF5Enable; + /* The HF output frequency is not present in PDL API argument. So updated the system config structure with current HF output frequency value */ + structCpy.hf5OutFreqMHz = (Cy_SysClk_ClkPathGetFrequency((uint32_t) structCpy.hf5Source)/(1UL << structCpy.hf5Divider))/CY_PRA_FREQUENCY_HZ_CONVERSION; + break; + + default: + hfEnabled = false; + message->praStatus = CY_PRA_STATUS_ACCESS_DENIED; + break; + } + /* The HF divider value is updated in the register only when + * that particular HF is enabled. Otherwise, it is stored in + * the system config structure + */ + if ((message->praStatus == CY_PRA_STATUS_SUCCESS) && (hfEnabled)) + { + message->praStatus = Cy_PRA_SystemConfig(&structCpy); + if (message->praStatus != CY_PRA_STATUS_SUCCESS) + { + /* On failure, previous values are restored */ + switch (((cy_stc_pra_clkhfsetdivider_t *) message->praData1)->clkHf) + { + case CY_PRA_CLKHF_0: + structCpy.hf0Divider = hfDivider; + structCpy.hf0OutFreqMHz = hfOutFreqMHz; + break; + + case CY_PRA_CLKHF_1: + structCpy.hf1Divider = hfDivider; + structCpy.hf1OutFreqMHz = hfOutFreqMHz; + break; + + case CY_PRA_CLKHF_2: + structCpy.hf2Divider = hfDivider; + structCpy.hf2OutFreqMHz = hfOutFreqMHz; + break; + + case CY_PRA_CLKHF_3: + structCpy.hf3Divider = hfDivider; + structCpy.hf3OutFreqMHz = hfOutFreqMHz; + break; + + case CY_PRA_CLKHF_4: + structCpy.hf4Divider = hfDivider; + structCpy.hf4OutFreqMHz = hfOutFreqMHz; + break; + + case CY_PRA_CLKHF_5: + structCpy.hf5Divider = hfDivider; + structCpy.hf5OutFreqMHz = hfOutFreqMHz; + break; + + default: + break; + } + } + } + } + break; + + case CY_PRA_CLK_FUNC_FAST_SET_DIVIDER: + { + uint8_t clkFastDivTmp; + bool clkFastEnableTmp; + /* Backups old values */ + clkFastEnableTmp = structCpy.clkFastEnable; + clkFastDivTmp = structCpy.clkFastDiv; + structCpy.clkFastEnable = true; + structCpy.clkFastDiv = (uint8_t)(message->praData1); + message->praStatus = Cy_PRA_SystemConfig(&structCpy); + if (message->praStatus != CY_PRA_STATUS_SUCCESS) + { + /* On failure, previous values are restored */ + structCpy.clkFastDiv = clkFastDivTmp; + structCpy.clkFastEnable = clkFastEnableTmp; + } + } + break; + + case CY_PRA_CLK_FUNC_PERI_SET_DIVIDER: + { + uint8_t clkPeriDivTmp; + bool clkPeriEnableTmp; + /* Backups old values */ + clkPeriDivTmp = structCpy.clkPeriDiv; + clkPeriEnableTmp = structCpy.clkPeriEnable; + structCpy.clkPeriEnable = true; + structCpy.clkPeriDiv = (uint8_t)(message->praData1); + message->praStatus = Cy_PRA_SystemConfig(&structCpy); + if (message->praStatus != CY_PRA_STATUS_SUCCESS) + { + /* On failure, previous values are restored */ + structCpy.clkPeriDiv = clkPeriDivTmp; + structCpy.clkPeriEnable = clkPeriEnableTmp; + } + } + break; + + case CY_PRA_CLK_FUNC_LF_SET_SOURCE: + { + cy_en_clklf_in_sources_t clkLfSourceTmp; + bool clkLFEnableTmp; + /* Backups old values */ + clkLFEnableTmp = structCpy.clkLFEnable; + clkLfSourceTmp = structCpy.clkLfSource; + structCpy.clkLFEnable = true; + structCpy.clkLfSource = (cy_en_clklf_in_sources_t)message->praData1; + message->praStatus = Cy_PRA_SystemConfig(&structCpy); + if (message->praStatus != CY_PRA_STATUS_SUCCESS) + { + /* On failure, previous values are restored */ + structCpy.clkLfSource = clkLfSourceTmp; + structCpy.clkLFEnable = clkLFEnableTmp; + } + } + break; + + case CY_PRA_CLK_FUNC_TIMER_SET_SOURCE: + { + cy_en_clktimer_in_sources_t clkTimerSourceTmp; + /* Backups old values */ + clkTimerSourceTmp = structCpy.clkTimerSource; + structCpy.clkTimerSource = (cy_en_clktimer_in_sources_t)message->praData1; + message->praStatus = CY_PRA_STATUS_SUCCESS; + if (structCpy.clkTimerEnable) + { + message->praStatus = Cy_PRA_SystemConfig(&structCpy); + if (message->praStatus != CY_PRA_STATUS_SUCCESS) + { + /* On failure, previous values are restored */ + structCpy.clkTimerSource = clkTimerSourceTmp; + } + } + } + break; + + case CY_PRA_CLK_FUNC_TIMER_SET_DIVIDER: + { + uint8_t clkTimerDividerTmp; + /* Backups old values */ + clkTimerDividerTmp = structCpy.clkTimerDivider; + structCpy.clkTimerDivider = (uint8_t)(message->praData1); + message->praStatus = CY_PRA_STATUS_SUCCESS; + /* The timer divider value is updated in the register only + * when CLK_TIMER is enabled. Otherwise, it is only + * stored in the system config structure + */ + if (structCpy.clkTimerEnable) + { + message->praStatus = Cy_PRA_SystemConfig(&structCpy); + if (message->praStatus != CY_PRA_STATUS_SUCCESS) + { + /* On failure, previous values are restored */ + structCpy.clkTimerDivider = clkTimerDividerTmp; + } + } + } + break; + + case CY_PRA_CLK_FUNC_TIMER_ENABLE: + { + bool clkTimerEnableTmp; + /* Backups old values */ + clkTimerEnableTmp = structCpy.clkTimerEnable; + structCpy.clkTimerEnable = true; + message->praStatus = Cy_PRA_SystemConfig(&structCpy); + if (message->praStatus != CY_PRA_STATUS_SUCCESS) + { + /* On failure, previous values are restored */ + structCpy.clkTimerEnable = clkTimerEnableTmp; + } + } + break; + + case CY_PRA_CLK_FUNC_TIMER_DISABLE: + { + bool clkTimerEnableTmp; + /* Backups old values */ + clkTimerEnableTmp = structCpy.clkTimerEnable; + structCpy.clkTimerEnable = false; + message->praStatus = Cy_PRA_SystemConfig(&structCpy); + if (message->praStatus != CY_PRA_STATUS_SUCCESS) + { + /* On failure, previous values are restored */ + structCpy.clkTimerEnable = clkTimerEnableTmp; + } + } + break; + + case CY_PRA_CLK_FUNC_PUMP_SET_SOURCE: + { + cy_en_clkpump_in_sources_t pumpSourceTmp; + /* Backups old values */ + pumpSourceTmp = structCpy.pumpSource; + structCpy.pumpSource = (cy_en_clkpump_in_sources_t)message->praData1; + message->praStatus = CY_PRA_STATUS_SUCCESS; + /* The PUMP source value is updated in the register only + * when PUMP is enabled. Otherwise, it is only + * stored in the system config structure + */ + if (structCpy.clkPumpEnable) + { + message->praStatus = Cy_PRA_SystemConfig(&structCpy); + if (message->praStatus != CY_PRA_STATUS_SUCCESS) + { + /* On failure, previous values are restored */ + structCpy.pumpSource = pumpSourceTmp; + } + } + } + break; + + case CY_PRA_CLK_FUNC_PUMP_SET_DIVIDER: + { + cy_en_clkpump_divide_t pumpDividerTmp; + /* Backups old values */ + pumpDividerTmp = structCpy.pumpDivider; + structCpy.pumpDivider = (cy_en_clkpump_divide_t)message->praData1; + message->praStatus = CY_PRA_STATUS_SUCCESS; + /* The PUMP divider value is updated in the register only + * when PUMP is enabled. Otherwise, it is only + * stored in the system config structure + */ + if (structCpy.clkPumpEnable) + { + message->praStatus = Cy_PRA_SystemConfig(&structCpy); + if (message->praStatus != CY_PRA_STATUS_SUCCESS) + { + /* On failure, previous values are restored */ + structCpy.pumpDivider = pumpDividerTmp; + } + } + } + break; + + case CY_PRA_CLK_FUNC_PUMP_ENABLE: + { + bool clkPumpEnableTmp; + /* Backups old values */ + clkPumpEnableTmp = structCpy.clkPumpEnable; + structCpy.clkPumpEnable = true; + message->praStatus = Cy_PRA_SystemConfig(&structCpy); + if (message->praStatus != CY_PRA_STATUS_SUCCESS) + { + /* On failure, previous values are restored */ + structCpy.clkPumpEnable = clkPumpEnableTmp; + } + } + break; + + case CY_PRA_CLK_FUNC_PUMP_DISABLE: + { + bool clkPumpEnableTmp; + /* Backups old values */ + clkPumpEnableTmp = structCpy.clkPumpEnable; + structCpy.clkPumpEnable = false; + message->praStatus = Cy_PRA_SystemConfig(&structCpy); + if (message->praStatus != CY_PRA_STATUS_SUCCESS) + { + /* On failure, previous values are restored */ + structCpy.clkPumpEnable = clkPumpEnableTmp; + } + } + break; + + case CY_PRA_CLK_FUNC_BAK_SET_SOURCE: + { + cy_en_clkbak_in_sources_t clkBakSourceTmp; + bool clkBakEnableTmp; + /* Backups old values */ + clkBakEnableTmp = structCpy.clkBakEnable; + clkBakSourceTmp = structCpy.clkBakSource; + structCpy.clkBakEnable = true; + structCpy.clkBakSource = (cy_en_clkbak_in_sources_t)message->praData1; + message->praStatus = Cy_PRA_SystemConfig(&structCpy); + if (message->praStatus != CY_PRA_STATUS_SUCCESS) + { + /* On failure, previous values are restored */ + structCpy.clkBakSource = clkBakSourceTmp; + structCpy.clkBakEnable = clkBakEnableTmp; + } + } + break; + + case CY_PRA_CLK_FUNC_ECO_CONFIGURE: + { + /* ECO configuration is not allowed if ECO is already enabled. + * The correct sequence is ECO_DISABLE -> ECO_CONFIGURE -> ECO_ENABLE + */ + if (structCpy.ecoEnable) + { + message->praStatus = CY_PRA_STATUS_ERROR_PROCESSING_ECO_ENABLED; + } + else + { + /* Stored the ECO config values into the system config structure. + * These values are applied to the register after a call from ECO_ENABLE. + */ + structCpy.ecoFreqHz = ((cy_stc_pra_clk_eco_configure_t *) message->praData1)->praClkEcofreq; + structCpy.ecoLoad = ((cy_stc_pra_clk_eco_configure_t *) message->praData1)->praCsum; + structCpy.ecoEsr = ((cy_stc_pra_clk_eco_configure_t *) message->praData1)->praEsr; + structCpy.ecoDriveLevel = ((cy_stc_pra_clk_eco_configure_t *) message->praData1)->praDriveLevel; + message->praStatus = CY_PRA_STATUS_SUCCESS; + } + } + break; + + case CY_PRA_CLK_FUNC_ECO_ENABLE: + { + bool ecoEnableTmp; + /* Backups old values */ + ecoEnableTmp = structCpy.ecoEnable; + structCpy.ecoEnable = true; + message->praStatus = Cy_PRA_SystemConfig(&structCpy); + if (message->praStatus != CY_PRA_STATUS_SUCCESS) + { + /* On failure, previous values are restored */ + structCpy.ecoEnable = ecoEnableTmp; + } + } + break; + + case CY_PRA_CLK_FUNC_PATH_SET_SOURCE: + { + bool pathEnable = false; + cy_en_clkpath_in_sources_t pathSrc = CY_SYSCLK_CLKPATH_IN_IMO; + message->praStatus = CY_PRA_STATUS_SUCCESS; + /* Backups old values */ + switch (((cy_stc_pra_clkpathsetsource_t *) message->praData1)->clk_path) + { + case CY_PRA_CLKPATH_0: + pathEnable = structCpy.path0Enable; + pathSrc = structCpy.path0Src; + structCpy.path0Enable = true; + structCpy.path0Src = ((cy_stc_pra_clkpathsetsource_t *) message->praData1)->source; + break; + + case CY_PRA_CLKPATH_1: + pathEnable = structCpy.path1Enable; + pathSrc = structCpy.path1Src; + structCpy.path1Enable = true; + structCpy.path1Src = ((cy_stc_pra_clkpathsetsource_t *) message->praData1)->source; + break; + + case CY_PRA_CLKPATH_2: + pathEnable = structCpy.path2Enable; + pathSrc = structCpy.path2Src; + structCpy.path2Enable = true; + structCpy.path2Src = ((cy_stc_pra_clkpathsetsource_t *) message->praData1)->source; + break; + + case CY_PRA_CLKPATH_3: + pathEnable = structCpy.path3Enable; + pathSrc = structCpy.path3Src; + structCpy.path3Enable = true; + structCpy.path3Src = ((cy_stc_pra_clkpathsetsource_t *) message->praData1)->source; + break; + + case CY_PRA_CLKPATH_4: + pathEnable = structCpy.path4Enable; + pathSrc = structCpy.path4Src; + structCpy.path4Enable = true; + structCpy.path4Src = ((cy_stc_pra_clkpathsetsource_t *) message->praData1)->source; + break; + + case CY_PRA_CLKPATH_5: + pathEnable = structCpy.path5Enable; + pathSrc = structCpy.path5Src; + structCpy.path5Enable = true; + structCpy.path5Src = ((cy_stc_pra_clkpathsetsource_t *) message->praData1)->source; + break; + + default: + message->praStatus = CY_PRA_STATUS_ACCESS_DENIED; + break; + } + if (message->praStatus == CY_PRA_STATUS_SUCCESS) + { + message->praStatus = Cy_PRA_SystemConfig(&structCpy); + if (message->praStatus != CY_PRA_STATUS_SUCCESS) + { + /* On failure, previous path values are restored */ + switch (((cy_stc_pra_clkpathsetsource_t *) message->praData1)->clk_path) + { + case CY_PRA_CLKPATH_0: + structCpy.path0Enable = pathEnable; + structCpy.path0Src = pathSrc; + break; + + case CY_PRA_CLKPATH_1: + structCpy.path1Enable = pathEnable; + structCpy.path1Src = pathSrc; + break; + + case CY_PRA_CLKPATH_2: + structCpy.path2Enable = pathEnable; + structCpy.path2Src = pathSrc; + break; + + case CY_PRA_CLKPATH_3: + structCpy.path3Enable = pathEnable; + structCpy.path3Src = pathSrc; + break; + + case CY_PRA_CLKPATH_4: + structCpy.path4Enable = pathEnable; + structCpy.path4Src = pathSrc; + break; + + case CY_PRA_CLKPATH_5: + structCpy.path5Enable = pathEnable; + structCpy.path5Src = pathSrc; + break; + + default: + message->praStatus = CY_PRA_STATUS_ACCESS_DENIED; + break; + } + } + } + } + break; + + case CY_PRA_CLK_FUNC_FLL_MANCONFIG: + { + /* FLL manual configuration values are not written to the + * register but stored in the system config structure. + * These values are applied to the register + * after a call from CY_PRA_CLK_FUNC_FLL_ENABLE */ + structCpy.fllMult = ((cy_stc_fll_manual_config_t *) message->praData1)->fllMult; + structCpy.fllRefDiv = ((cy_stc_fll_manual_config_t *) message->praData1)->refDiv; + structCpy.fllCcoRange = ((cy_stc_fll_manual_config_t *) message->praData1)->ccoRange; + structCpy.enableOutputDiv = ((cy_stc_fll_manual_config_t *) message->praData1)->enableOutputDiv; + structCpy.lockTolerance = ((cy_stc_fll_manual_config_t *) message->praData1)->lockTolerance; + structCpy.igain = ((cy_stc_fll_manual_config_t *) message->praData1)->igain; + structCpy.pgain = ((cy_stc_fll_manual_config_t *) message->praData1)->pgain; + structCpy.settlingCount = ((cy_stc_fll_manual_config_t *) message->praData1)->settlingCount; + structCpy.outputMode = ((cy_stc_fll_manual_config_t *) message->praData1)->outputMode; + structCpy.ccoFreq = ((cy_stc_fll_manual_config_t *) message->praData1)->cco_Freq; + message->praStatus = CY_PRA_STATUS_SUCCESS; + } + break; + + case CY_PRA_CLK_FUNC_FLL_ENABLE: + { + /* FLL Enable is not allowed if it is already enabled */ + if (structCpy.fllEnable == true) /* FLL is already enabled */ + { + message->praStatus = CY_PRA_STATUS_ERROR_PROCESSING_FLL0_ENABLED; + } + else + { + structCpy.fllEnable = true; + /* FLL Enable API does not contain the FLL output value + * as the argument. So, calculate and update the FLL output value */ + structCpy.fllOutFreqHz = Cy_PRA_CalculateFLLOutFreq(&structCpy); + message->praStatus = Cy_PRA_SystemConfig(&structCpy); + if (message->praStatus != CY_PRA_STATUS_SUCCESS) + { + structCpy.fllOutFreqHz = CY_PRA_DEFAULT_ZERO; + structCpy.fllEnable = false; + } + } + } + break; + + case CY_PRA_CLK_FUNC_PLL_MANCONFIG: + { + /* Checks for the valid PLL number */ + if((((cy_stc_pra_clk_pll_manconfigure_t *) message->praData1)->clkPath == CY_PRA_CLKPATH_0) || + (((cy_stc_pra_clk_pll_manconfigure_t *) message->praData1)->clkPath > CY_SRSS_NUM_PLL)) + { + message->praStatus = CY_PRA_STATUS_INVALID_PARAM_PLL_NUM; + } + else + { + /* PLL manual configuration values are not written to + * the register but stored in the system config structure. + * These values are applied to the register + * after a call from CY_PRA_CLK_FUNC_PLL_ENABLE. */ + if(((cy_stc_pra_clk_pll_manconfigure_t *) message->praData1)->clkPath == CY_PRA_CLKPATH_1) + { + structCpy.pll0FeedbackDiv = ((cy_stc_pra_clk_pll_manconfigure_t *) message->praData1)->praConfig->feedbackDiv; + structCpy.pll0ReferenceDiv = ((cy_stc_pra_clk_pll_manconfigure_t *) message->praData1)->praConfig->referenceDiv; + structCpy.pll0OutputDiv = ((cy_stc_pra_clk_pll_manconfigure_t *) message->praData1)->praConfig->outputDiv; + structCpy.pll0LfMode = ((cy_stc_pra_clk_pll_manconfigure_t *) message->praData1)->praConfig->lfMode; + structCpy.pll0OutputMode = ((cy_stc_pra_clk_pll_manconfigure_t *) message->praData1)->praConfig->outputMode; + } + else + { + structCpy.pll1FeedbackDiv = ((cy_stc_pra_clk_pll_manconfigure_t *) message->praData1)->praConfig->feedbackDiv; + structCpy.pll1ReferenceDiv = ((cy_stc_pra_clk_pll_manconfigure_t *) message->praData1)->praConfig->referenceDiv; + structCpy.pll1OutputDiv = ((cy_stc_pra_clk_pll_manconfigure_t *) message->praData1)->praConfig->outputDiv; + structCpy.pll1LfMode = ((cy_stc_pra_clk_pll_manconfigure_t *) message->praData1)->praConfig->lfMode; + structCpy.pll1OutputMode = ((cy_stc_pra_clk_pll_manconfigure_t *) message->praData1)->praConfig->outputMode; + } + message->praStatus = CY_PRA_STATUS_SUCCESS; + } + } + break; + + case CY_PRA_CLK_FUNC_PLL_ENABLE: + { + if ((((message->praData1) == CY_PRA_CLKPLL_1) && (structCpy.pll0Enable == true)) + || (((message->praData1) == CY_PRA_CLKPLL_2) && (structCpy.pll1Enable == true)) + || (message->praData1 > CY_SRSS_NUM_PLL) || (message->praData1 == 0UL)) + { + message->praStatus = CY_PRA_STATUS_ERROR_PROCESSING_PLL_ENABLED; + } + else + { + /* PLL Enable API does not contain the PLL output value + * as the argument. So, calculate and update the PLL output value */ + if ((message->praData1) == CY_PRA_CLKPLL_1) + { + structCpy.pll0OutFreqHz = Cy_PRA_CalculatePLLOutFreq(CY_PRA_CLKPLL_1, &structCpy); + structCpy.pll0Enable = true; + } + else + { + structCpy.pll1OutFreqHz = Cy_PRA_CalculatePLLOutFreq(CY_PRA_CLKPLL_2, &structCpy); + structCpy.pll1Enable = true; + } + + message->praStatus = Cy_PRA_SystemConfig(&structCpy); + + if (message->praStatus != CY_PRA_STATUS_SUCCESS) + { + if ((message->praData1) == CY_PRA_CLKPLL_1) + { + structCpy.pll0OutFreqHz = CY_PRA_DEFAULT_ZERO; + structCpy.pll0Enable = false; + } + else + { + structCpy.pll1OutFreqHz = CY_PRA_DEFAULT_ZERO; + structCpy.pll1Enable = false; + } + } + } + } + break; + + case CY_PRA_CLK_FUNC_SLOW_SET_DIVIDER: + { + uint8_t clkSlowDivTmp; + bool clkSlowEnableTmp; + /* Backups old values */ + clkSlowEnableTmp = structCpy.clkSlowEnable; + clkSlowDivTmp = structCpy.clkSlowDiv; + structCpy.clkSlowEnable = true; + structCpy.clkSlowDiv = (uint8_t)(message->praData1); + message->praStatus = Cy_PRA_SystemConfig(&structCpy); + if (message->praStatus != CY_PRA_STATUS_SUCCESS) + { + /* On failure, previous path values are restored */ + structCpy.clkSlowDiv = clkSlowDivTmp; + structCpy.clkSlowEnable = clkSlowEnableTmp; + } + } + break; + + case CY_PRA_CLK_FUNC_EXT_CLK_SET_FREQUENCY: + { + structCpy.extClkFreqHz = (uint32_t)(message->praData1); + message->praStatus = CY_PRA_STATUS_SUCCESS; + } + break; + + default: + message->praStatus = CY_PRA_STATUS_ACCESS_DENIED; + break; + } + } + else + { + message->praStatus = CY_PRA_STATUS_ACCESS_DENIED; + } + break; + + default: + message->praStatus = CY_PRA_STATUS_ACCESS_DENIED; + break; + } + +} +#endif /* (CY_CPU_CORTEX_M0P) */ + + +#if (CY_CPU_CORTEX_M4) || defined (CY_DOXYGEN) + +/******************************************************************************* +* Function Name: Cy_PRA_SendCmd +****************************************************************************//** +* +* Takes the parameters, passes them to the secure Cortex-M0+ via IPC, waits for +* Cortex-M0+ to finish and reports the status. +* +* \param cmd The command to execute on the secure side. The macros for this +* parameter are defined in the cy_pra.h file with the CY_PRA_MSG_TYPE_ prefix. +* \param regIndex The index of the function or register depending on the command +* parameter. The macros for this parameter are defined in the cy_pra.h file with +* the CY_PRA_INDX_ prefix. +* \param clearMask Data sent to secure the core. +* \param setMask Additional data send to secure the core. +* +* \return The command execution status. For the register read command, the read +* value is returned. +* +*******************************************************************************/ +#if defined(CY_DEVICE_PSOC6ABLE2) + + CY_RAMFUNC_BEGIN + #if !defined (__ICCARM__) + CY_NOINLINE + #endif +#endif /* defined(CY_DEVICE_PSOC6ABLE2) */ + cy_en_pra_status_t Cy_PRA_SendCmd(uint16_t cmd, uint16_t regIndex, uint32_t clearMask, uint32_t setMask) + { + CY_ASSERT_L1(NULL != ipcPraBase); + + cy_en_pra_status_t status; + CY_ALIGN(4UL) cy_stc_pra_msg_t ipcMsg; + uint32_t interruptState; + + ipcMsg.praCommand = cmd; + ipcMsg.praStatus = CY_PRA_STATUS_REQUEST_SENT; + ipcMsg.praIndex = regIndex; + ipcMsg.praData1 = clearMask; + ipcMsg.praData2 = setMask; + + interruptState = Cy_SysLib_EnterCriticalSection(); + + while (0U == _FLD2VAL(IPC_STRUCT_ACQUIRE_SUCCESS, REG_IPC_STRUCT_ACQUIRE(ipcPraBase))) + { + /* Waits until the PRA IPC structure is acquired */ + } + + /* Sends the message */ + REG_IPC_STRUCT_DATA(ipcPraBase) = (uint32_t) &ipcMsg; + + /* Generates an acquire notification event by the PRA IPC interrupt structure */ + REG_IPC_STRUCT_NOTIFY(ipcPraBase) = _VAL2FLD(IPC_STRUCT_NOTIFY_INTR_NOTIFY, CY_PRA_IPC_NOTIFY_INTR); + + while (0U != _FLD2VAL(IPC_STRUCT_ACQUIRE_SUCCESS, REG_IPC_STRUCT_LOCK_STATUS(ipcPraBase))) + { + /* Waits until the PRA IPC structure is released */ + } + + Cy_SysLib_ExitCriticalSection(interruptState); + + /* Cortex-M0+ has an updated ipcMsg variable */ + + status = (cy_en_pra_status_t) ipcMsg.praStatus; + + if (CY_PRA_STATUS_ACCESS_DENIED == status) + { + CY_HALT(); + } + + if (CY_PRA_MSG_TYPE_SYS_CFG_FUNC == ipcMsg.praCommand) + { + SystemCoreClockUpdate(); + } + + if (CY_PRA_MSG_TYPE_REG32_GET == ipcMsg.praCommand) + { + status = (cy_en_pra_status_t)ipcMsg.praData1; + } + + return status; + } +#if defined(CY_DEVICE_PSOC6ABLE2) + CY_RAMFUNC_END +#endif /* defined(CY_DEVICE_PSOC6ABLE2) */ + +#endif /* (CY_CPU_CORTEX_M4) */ + + +#if (CY_CPU_CORTEX_M0P) || defined (CY_DOXYGEN) + +/* The mask to unlock Hibernate power mode */ +#define HIBERNATE_UNLOCK_VAL ((uint32_t) 0x3Au << SRSS_PWR_HIBERNATE_UNLOCK_Pos) + +/* The mask to set Hibernate power mode */ +#define SET_HIBERNATE_MODE ((HIBERNATE_UNLOCK_VAL |\ + SRSS_PWR_HIBERNATE_FREEZE_Msk |\ + SRSS_PWR_HIBERNATE_HIBERNATE_Msk)) + +/* The mask to retain Hibernate power mode status */ +#define HIBERNATE_RETAIN_STATUS_MASK ((SRSS_PWR_HIBERNATE_TOKEN_Msk |\ + SRSS_PWR_HIBERNATE_MASK_HIBALARM_Msk |\ + SRSS_PWR_HIBERNATE_MASK_HIBWDT_Msk |\ + SRSS_PWR_HIBERNATE_POLARITY_HIBPIN_Msk |\ + SRSS_PWR_HIBERNATE_MASK_HIBPIN_Msk)) + +/** The mask for Hibernate wakeup sources */ +#define HIBERNATE_WAKEUP_MASK ((SRSS_PWR_HIBERNATE_MASK_HIBALARM_Msk |\ + SRSS_PWR_HIBERNATE_MASK_HIBWDT_Msk |\ + SRSS_PWR_HIBERNATE_POLARITY_HIBPIN_Msk |\ + SRSS_PWR_HIBERNATE_MASK_HIBPIN_Msk)) + +/** The define to update the token to indicate the transition into Hibernate */ +#define HIBERNATE_TOKEN ((uint32_t) 0x1BU << SRSS_PWR_HIBERNATE_TOKEN_Pos) + + +/******************************************************************************* +* Function Name: Cy_PRA_PmHibernate +****************************************************************************//** +* +* Updates the SRSS_PWR_HIBERNATE register for the Cy_SysPm_SystemEnterHibernate and +* Cy_SysPm_IoUnfreeze functions. +* +*******************************************************************************/ +static void Cy_PRA_PmHibernate(uint32_t funcProc) +{ + + if(0UL == funcProc) + { + /* Saves the token to be retained through a wakeup sequence. + * This could be used by Cy_SysLib_GetResetReason() to differentiate + * Wakeup from a general reset event. + * Saves the wakeup source(s) configuration. + */ + SRSS_PWR_HIBERNATE = (SRSS_PWR_HIBERNATE & HIBERNATE_WAKEUP_MASK) | HIBERNATE_TOKEN; + + /* Disables the overriding the next pin-freeze command by the peripherals */ + SRSS_PWR_HIBERNATE |= SET_HIBERNATE_MODE; + + /* The second write causes freezing of I/O cells to save the I/O-cell state */ + SRSS_PWR_HIBERNATE |= SET_HIBERNATE_MODE; + + /* The third write cause system to enter Hibernate */ + SRSS_PWR_HIBERNATE |= SET_HIBERNATE_MODE; + } + else + { + /* Saves the last reset reason and wakeup polarity. Then, unfreeze I/O: + * writes PWR_HIBERNATE.FREEZE=0, .UNLOCK=0x3A, .HIBERANTE=0 + */ + SRSS_PWR_HIBERNATE = (SRSS_PWR_HIBERNATE & HIBERNATE_RETAIN_STATUS_MASK) | HIBERNATE_UNLOCK_VAL; + + /* Locks Hibernate mode: + * write PWR_HIBERNATE.HIBERNATE=0, UNLOCK=0x00, HIBERANTE=0 + */ + SRSS_PWR_HIBERNATE &= HIBERNATE_RETAIN_STATUS_MASK; + } +} + + +/******************************************************************************* +* Function Name: Cy_PRA_PmCm4DpFlagSet +****************************************************************************//** +* +* Sets Deep Sleep Flag for the CM4 core. +* +*******************************************************************************/ +static void Cy_PRA_PmCm4DpFlagSet(void) +{ + uint32_t ddftStructData; + + /* Acquires the IPC to prevent the changing of the shared resources at the same time */ + while (0U == _FLD2VAL(IPC_STRUCT_ACQUIRE_SUCCESS, REG_IPC_STRUCT_ACQUIRE(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)))) + { + /* Waits until the IPC structure is released by another CPU */ + } + + ddftStructData = REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)); + + /* Updates the CM4 core Deep Sleep mask */ + ddftStructData |= (0x01UL << 28u); + + /* Updates the pointer to the latest saved structure */ + REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = ddftStructData; + + /* Releases the IPC */ + REG_IPC_STRUCT_RELEASE(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = 0U; + + /* Reads the release value to make sure it is set */ + (void) REG_IPC_STRUCT_RELEASE(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)); +} + +/* The timeout count for function Cy_PRA_ClkDeepSleepCallback() is sufficiently large for ~1 second */ +#define CY_PRA_TIMEOUT (1000000UL) +/* These variables act as locks to prevent collisions between clock measurement and entry into + Deep Sleep mode. See Cy_SysClk_DeepSleep(). */ +static uint16_t changedSourcePaths = CY_PRA_DEFAULT_ZERO; +static uint16_t pllAutoModes = CY_PRA_DEFAULT_ZERO; + + +/******************************************************************************* +* Function Name: Cy_PRA_ClkDSBeforeTransition +****************************************************************************//** +* +* SysClock before deep sleep transition. +* +*******************************************************************************/ +static cy_en_pra_status_t Cy_PRA_ClkDSBeforeTransition(void) +{ + uint32_t fllPll; /* 0 = FLL, all other values = a PLL */ + + /* Initializes the storage of changed paths */ + changedSourcePaths = CY_PRA_DEFAULT_ZERO; + pllAutoModes = CY_PRA_DEFAULT_ZERO; + + /* For FLL and each PLL */ + for (fllPll = 0UL; fllPll <= CY_SRSS_NUM_PLL; fllPll++) + { + /* If FLL or PLL is enabled */ + if ((0UL == fllPll) ? Cy_SysClk_FllIsEnabled() : Cy_SysClk_PllIsEnabled(fllPll)) + { + /* And the FLL/PLL has ECO as a source */ + if (Cy_SysClk_ClkPathGetSource(fllPll) == CY_SYSCLK_CLKPATH_IN_ECO) + { + /* Bypasses the FLL/PLL */ + if (0UL == fllPll) + { + CY_REG32_CLR_SET(SRSS_CLK_FLL_CONFIG3, SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, CY_SYSCLK_FLLPLL_OUTPUT_INPUT); + } + else + { + if (((uint32_t)CY_SYSCLK_FLLPLL_OUTPUT_AUTO == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS_CLK_PLL_CONFIG[fllPll - 1UL])) || + ((uint32_t)CY_SYSCLK_FLLPLL_OUTPUT_AUTO1 == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS_CLK_PLL_CONFIG[fllPll - 1UL]))) + { + pllAutoModes |= (uint16_t)(1UL << fllPll); + } + + CY_REG32_CLR_SET(SRSS_CLK_PLL_CONFIG[fllPll - 1UL], SRSS_CLK_PLL_CONFIG_BYPASS_SEL, CY_SYSCLK_FLLPLL_OUTPUT_INPUT); + } + + /* Changes this path source to IMO */ + (void)Cy_SysClk_ClkPathSetSource(fllPll, CY_SYSCLK_CLKPATH_IN_IMO); + + /* Stores a record that this path source was changed from ECO */ + changedSourcePaths |= (uint16_t)(1UL << fllPll); + } + else if (0UL == fllPll) + { + CY_REG32_CLR_SET(SRSS_CLK_FLL_CONFIG3, SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, CY_SYSCLK_FLLPLL_OUTPUT_INPUT); + } + else + { + /* Does nothing */ + } + } + } + + return CY_PRA_STATUS_SUCCESS; +} + +/******************************************************************************* +* Function Name: Cy_PRA_ClkDSAfterTransition +****************************************************************************//** +* +* SysClock after Deep Sleep transition. +* +*******************************************************************************/ +static cy_en_pra_status_t Cy_PRA_ClkDSAfterTransition(void) +{ + /* Bit-mapped paths with enabled FLL/PLL sourced by ECO */ + uint32_t timeout = CY_PRA_TIMEOUT; + cy_en_pra_status_t retVal = CY_PRA_STATUS_ERROR_SYSPM_TIMEOUT; + + /* After return from Deep Sleep, for each FLL/PLL, if needed, restore the source to ECO. + * And block until the FLL/PLL has regained its frequency lock. + */ + if (0U != changedSourcePaths) + { + /* If any FLL/PLL was sourced by the ECO, the timeout waits for the ECO to become fully stabilized again */ + while ((CY_SYSCLK_ECOSTAT_STABLE != Cy_SysClk_EcoGetStatus()) && (0UL != timeout)) + { + timeout--; + } + + if (0UL != timeout) + { + uint32_t fllPll; /* 0 = FLL, all other values = PLL */ + + for (fllPll = 0UL; fllPll <= CY_SRSS_NUM_PLL; fllPll++) + { + /* If there is a correspondent record about a changed clock source */ + if (0U != (changedSourcePaths & (uint16_t)(1UL << fllPll))) + { + /* Changes this path source back to ECO */ + (void)Cy_SysClk_ClkPathSetSource(fllPll, CY_SYSCLK_CLKPATH_IN_ECO); + + /* The timeout waits for FLL/PLL to regain a lock. + * Split FLL and PLL lock polling loops into two separate threads to minimize one polling loop duration. + */ + if (0UL == fllPll) + { + while ((!Cy_SysClk_FllLocked()) && (0UL != timeout)) + { + timeout--; + } + } + else + { + while ((!Cy_SysClk_PllLocked(fllPll)) && (0UL != timeout)) + { + timeout--; + } + } + + if (0UL != timeout) + { + /* Undoes the bypass for FLL/PLL */ + if (0UL == fllPll) + { + CY_REG32_CLR_SET(SRSS_CLK_FLL_CONFIG3, SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT); + } + else + { + if (0U != (pllAutoModes & (uint16_t)(1UL << fllPll))) + { + CY_REG32_CLR_SET(SRSS_CLK_PLL_CONFIG[fllPll - 1UL], SRSS_CLK_PLL_CONFIG_BYPASS_SEL, CY_SYSCLK_FLLPLL_OUTPUT_AUTO); + } + else + { + CY_REG32_CLR_SET(SRSS_CLK_PLL_CONFIG[fllPll - 1UL], SRSS_CLK_PLL_CONFIG_BYPASS_SEL, CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT); + } + } + + retVal = CY_PRA_STATUS_SUCCESS; + } + } + } + } + } + else if (Cy_SysClk_FllIsEnabled()) + { + /* The timeout waits for FLL to regain a lock */ + while ((!Cy_SysClk_FllLocked()) && (0UL != timeout)) + { + timeout--; + } + + if (0UL != timeout) + { + /* Undoes the bypass for FLL */ + CY_REG32_CLR_SET(SRSS_CLK_FLL_CONFIG3, SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT); + retVal = CY_PRA_STATUS_SUCCESS; + } + } + else + { + retVal = CY_PRA_STATUS_SUCCESS; + } + + return (retVal); +} + + +/******************************************************************************* +* Function Name: Cy_PRA_RegAccessRangeValid +****************************************************************************//** +* +* Checks if the access is within the valid range and the access address is non-zero. +* +* \param index The index of the accessed register. +* +* \return Returns true for the valid access. +* +*******************************************************************************/ +static bool Cy_PRA_RegAccessRangeValid(uint16_t index) +{ + bool accessValid = true; + + /* Checks if access is within the array range */ + if (index >= CY_PRA_REG_INDEX_COUNT) + { + accessValid = false; + } + + /* Some registers do not exist for some families */ + if (regIndexToAddr[index].addr == (const volatile uint32_t *) 0U) + { + accessValid = false; + } + + return accessValid; +} + + +#endif /* (CY_CPU_CORTEX_M0P) */ + +#endif /* (CY_DEVICE_SECURE) */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_pra_cfg.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_pra_cfg.c new file mode 100644 index 0000000000..a11e34f233 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_pra_cfg.c @@ -0,0 +1,3078 @@ +/***************************************************************************//** +* \file cy_pra_cfg.c +* \version 1.0 +* +* \brief The source code file for the PRA driver. The API is not intented to +* be used directly by user application. +* +******************************************************************************** +* \copyright +* Copyright 2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ +#include "cy_pra_cfg.h" +#include "cy_gpio.h" +#include "cy_device.h" +#include "cy_gpio.h" +#include "cy_wdt.h" + +#if defined (CY_DEVICE_SECURE) || defined (CY_DOXYGEN) + +#if (CY_CPU_CORTEX_M0P) + #include "cy_prot.h" +#endif /* (CY_CPU_CORTEX_M0P) */ + +#if (CY_CPU_CORTEX_M0P) || defined (CY_DOXYGEN) + +/******************************************************************************* +* Function Prototypes +*******************************************************************************/ +__STATIC_INLINE cy_en_pra_status_t Cy_PRA_IloEnable(void); +__STATIC_INLINE cy_en_pra_status_t Cy_PRA_IloDisable(void); +__STATIC_INLINE cy_en_pra_status_t Cy_PRA_IloHibernateOn(bool hibernateEnable); +__STATIC_INLINE void Cy_PRA_ClkPumpInit(cy_en_clkpump_in_sources_t source, cy_en_clkpump_divide_t divider); +__STATIC_INLINE void Cy_PRA_ClkTimerInit(cy_en_clktimer_in_sources_t source, uint8_t divider); +__STATIC_INLINE cy_en_pra_status_t Cy_PRA_PllInit(uint32_t clkPath, const cy_stc_pll_manual_config_t *pllConfig); +__STATIC_INLINE cy_en_pra_status_t Cy_PRA_ClkHfInit( uint32_t clkHf, cy_en_clkhf_in_sources_t hfClkPath, cy_en_clkhf_dividers_t divider); +__STATIC_INLINE cy_en_pra_status_t Cy_PRA_FllInit(const cy_stc_pra_system_config_t *devConfig); +__STATIC_INLINE void Cy_PRA_ExtClkInit( const cy_stc_pra_system_config_t *devConfig ); +__STATIC_INLINE cy_en_pra_status_t Cy_PRA_EcoInit(const cy_stc_pra_system_config_t *devConfig); +#if defined(CY_IP_MXBLESS) +__STATIC_INLINE cy_en_pra_status_t Cy_PRA_AltHfInit(const cy_stc_pra_system_config_t *devConfig); +__STATIC_INLINE void Cy_PRA_AltHfReset(const cy_stc_pra_system_config_t *devConfig); +static cy_en_pra_status_t Cy_PRA_ValidateAltHf(const cy_stc_pra_system_config_t *devConfig); +#endif +__STATIC_INLINE void Cy_PRA_PiloInit(void); +__STATIC_INLINE cy_en_pra_status_t Cy_PRA_ClkLfInit(cy_en_clklf_in_sources_t clkLfSource); +__STATIC_INLINE cy_en_pra_status_t Cy_PRA_WcoInit(const cy_stc_pra_system_config_t *devConfig); +__STATIC_INLINE cy_en_pra_status_t Cy_PRA_PowerInit(const cy_stc_pra_system_config_t *devConfig); +static uint32_t Cy_PRA_GetInputPathMuxFrq(cy_en_clkpath_in_sources_t pathMuxSrc, const cy_stc_pra_system_config_t *devConfig); +static cy_en_pra_status_t Cy_PRA_GetInputSourceFreq(uint32_t clkPath, const cy_stc_pra_system_config_t *devConfig, uint32_t *srcFreq ); +static uint32_t Cy_PRA_GetClkLfFreq(const cy_stc_pra_system_config_t *devConfig); +static uint32_t Cy_PRA_GetClkBakFreq(const cy_stc_pra_system_config_t *devConfig); +static cy_en_clkpath_in_sources_t Cy_PRA_GetInputSourceClock(uint32_t clkPath, const cy_stc_pra_system_config_t *devConfig, cy_en_pra_status_t *status); +static cy_en_pra_status_t Cy_PRA_ValidateECO(const cy_stc_pra_system_config_t *devConfig); +static cy_en_pra_status_t Cy_PRA_ValidateEXTClk(const cy_stc_pra_system_config_t *devConfig); +static cy_en_pra_status_t Cy_PRA_ValidateFLL(const cy_stc_pra_system_config_t *devConfig); +static cy_en_pra_status_t Cy_PRA_ValidatePLL(const cy_stc_pra_system_config_t *devConfig, uint8_t pll); +static cy_en_pra_status_t Cy_PRA_ValidateAllPLL(const cy_stc_pra_system_config_t *devConfig); +static cy_en_pra_status_t Cy_PRA_ValidateClkLf(const cy_stc_pra_system_config_t *devConfig); +static cy_en_pra_status_t Cy_PRA_ValidateClkPathMux(cy_en_clkpath_in_sources_t pathSrc, const cy_stc_pra_system_config_t *devConfig); +static cy_en_pra_status_t Cy_PRA_ValidateClkPath(uint32_t clkPath, const cy_stc_pra_system_config_t *devConfig); +static cy_en_pra_status_t Cy_PRA_ValidateAllClkPathMux(const cy_stc_pra_system_config_t *devConfig); +static cy_en_pra_status_t Cy_PRA_ValidateClkHfFreqDiv(uint32_t outFreqMHz, cy_en_clkhf_dividers_t divider); +static cy_en_pra_status_t Cy_PRA_ValidateClkHFs(const cy_stc_pra_system_config_t *devConfig); +static cy_en_pra_status_t Cy_PRA_ValidateClkPump(const cy_stc_pra_system_config_t *devConfig); +static cy_en_pra_status_t Cy_PRA_ValidateClkBak(const cy_stc_pra_system_config_t *devConfig); +static cy_en_pra_status_t Cy_PRA_ValidateClkFast(const cy_stc_pra_system_config_t *devConfig); +static cy_en_pra_status_t Cy_PRA_ValidateClkPeri(const cy_stc_pra_system_config_t *devConfig); +static cy_en_pra_status_t Cy_PRA_ValidateClkTimer(const cy_stc_pra_system_config_t *devConfig); +static cy_en_pra_status_t Cy_PRA_ValidateClkSlow(const cy_stc_pra_system_config_t *devConfig); +static cy_en_pra_status_t Cy_PRA_ValidateSystemConfig(const cy_stc_pra_system_config_t *devConfig); + + +/******************************************************************************* +* Function Name: Cy_PRA_IloEnable +****************************************************************************//** +* +* Enables ILO Clock +* +* \return +* CY_PRA_STATUS_SUCCESS when success. +* CY_PRA_STATUS_ERROR_PROCESSING_ILO when failure. +*******************************************************************************/ +__STATIC_INLINE cy_en_pra_status_t Cy_PRA_IloEnable(void) +{ + cy_en_pra_status_t retStatus = CY_PRA_STATUS_ERROR_PROCESSING_ILO; + + if (Cy_SysClk_IloIsEnabled()) /* No change in ILO configuration */ + { + retStatus = CY_PRA_STATUS_SUCCESS; + } + else + { + /* ILO cannot be enabled when WDT is locked */ + if (!Cy_WDT_Locked()) + { + Cy_SysClk_IloEnable(); + retStatus = CY_PRA_STATUS_SUCCESS; + } + } + return retStatus; +} + +/******************************************************************************* +* Function Name: Cy_PRA_IloDisable +****************************************************************************//** +* +* Disables ILO Clock +* +* \return +* CY_PRA_STATUS_SUCCESS when success. +* CY_PRA_STATUS_ERROR_PROCESSING_ILO when failure. +*******************************************************************************/ +__STATIC_INLINE cy_en_pra_status_t Cy_PRA_IloDisable(void) +{ + cy_en_pra_status_t retStatus = CY_PRA_STATUS_ERROR_PROCESSING_ILO; + + if (!Cy_SysClk_IloIsEnabled()) /* No change in ILO configuration */ + { + retStatus = CY_PRA_STATUS_SUCCESS; + } + else + { + /* ILO cannot be disabled when WDT is locked */ + if (!Cy_WDT_Locked()) + { + if (CY_SYSCLK_SUCCESS == Cy_SysClk_IloDisable()) + { + retStatus = CY_PRA_STATUS_SUCCESS; + } + } + } + return retStatus; +} + +/******************************************************************************* +* Function Name: Cy_PRA_IloHibernateOn +****************************************************************************//** +* +* Controls whether the ILO stays on during a hibernate, or through an XRES or +* a brown-out detect (BOD) event. +* +* \param hibernateEnable +* true = ILO stays on during hibernate or across XRES/BOD. \n +* false = ILO turns off for hibernate or XRES/BOD. +* +* \return +* CY_PRA_STATUS_SUCCESS when success. +* CY_PRA_STATUS_ERROR_PROCESSING_ILO when failure. +*******************************************************************************/ +__STATIC_INLINE cy_en_pra_status_t Cy_PRA_IloHibernateOn(bool hibernateEnable) +{ + cy_en_pra_status_t retStatus = CY_PRA_STATUS_ERROR_PROCESSING_ILO; + static bool hibernateOn = false; /* Default hibernate state is false */ + + if (hibernateOn == hibernateEnable) /* No change in ILO configuration */ + { + retStatus = CY_PRA_STATUS_SUCCESS; + } + else + { + /* ILO hibernate cannot be ON when WDT is locked */ + if (!Cy_WDT_Locked()) + { + Cy_SysClk_IloHibernateOn(hibernateEnable); + hibernateOn = hibernateEnable; + retStatus = CY_PRA_STATUS_SUCCESS; + } + } + return retStatus; +} + +/******************************************************************************* +* Function Name: Cy_PRA_ClkPumpInit +****************************************************************************//** +* +* Initializes PUMP Clock. +* +* \param source \ref cy_en_clkpump_in_sources_t +* \param divider \ref cy_en_clkpump_divide_t +* +*******************************************************************************/ +__STATIC_INLINE void Cy_PRA_ClkPumpInit(cy_en_clkpump_in_sources_t source, cy_en_clkpump_divide_t divider) +{ + Cy_SysClk_ClkPumpDisable(); + Cy_SysClk_ClkPumpSetSource(source); + Cy_SysClk_ClkPumpSetDivider(divider); + Cy_SysClk_ClkPumpEnable(); +} + + +/******************************************************************************* +* Function Name: Cy_PRA_ClkTimerInit +****************************************************************************//** +* +* Initializes Timer Clock. +* +* \param source \ref cy_en_clktimer_in_sources_t +* \param divider Divider value; valid range is 0 to 255. Divides the selected +* source (\ref Cy_SysClk_ClkTimerSetSource) by the (value + 1). +* +*******************************************************************************/ +__STATIC_INLINE void Cy_PRA_ClkTimerInit(cy_en_clktimer_in_sources_t source, uint8_t divider) +{ + Cy_SysClk_ClkTimerDisable(); + Cy_SysClk_ClkTimerSetSource(source); + Cy_SysClk_ClkTimerSetDivider(divider); + Cy_SysClk_ClkTimerEnable(); +} + + +/******************************************************************************* +* Function Name: Cy_PRA_PllInit +****************************************************************************//** +* +* Initializes Phase Locked Loop. This function configures and enables PLL. +* +* \param clkPath Selects which PLL to configure. 1 is the first PLL; 0 is invalid. +* \param pllConfig \ref cy_stc_pll_manual_config_t +* +* \return +* CY_PRA_STATUS_SUCCESS PLL init is success. +* CY_PRA_STATUS_ERROR_PROCESSING PLL init is failure. +* +*******************************************************************************/ +__STATIC_INLINE cy_en_pra_status_t Cy_PRA_PllInit(uint32_t clkPath, const cy_stc_pll_manual_config_t *pllConfig) +{ + if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllManualConfigure(clkPath, pllConfig)) + { + return CY_PRA_STATUS_ERROR_PROCESSING; + } + if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllEnable(clkPath, 10000u)) + { + return CY_PRA_STATUS_ERROR_PROCESSING; + } + + return CY_PRA_STATUS_SUCCESS; +} + + +/******************************************************************************* +* Function Name: Cy_PRA_ClkHfInit +****************************************************************************//** +* +* Initializes High Frequency Clock. +* +* \param clkHf selects which clkHf mux to configure. +* \param hfClkPath \ref cy_en_clkhf_in_sources_t +* \param divider \ref cy_en_clkhf_dividers_t +* +* \return +* CY_PRA_STATUS_SUCCESS CLK_HF init is success. +* CY_PRA_STATUS_ERROR_PROCESSING CLK_HF init is failure. +* +* \note +* There is no separate PRA function for CLK_HF set, divide, and enable. +* They are wrapped into a single PRA function. +*******************************************************************************/ +__STATIC_INLINE cy_en_pra_status_t Cy_PRA_ClkHfInit( uint32_t clkHf, cy_en_clkhf_in_sources_t hfClkPath, cy_en_clkhf_dividers_t divider) +{ + if (CY_SYSCLK_SUCCESS != Cy_SysClk_ClkHfSetSource(clkHf, hfClkPath)) + { + return CY_PRA_STATUS_ERROR_PROCESSING; + } + if (CY_SYSCLK_SUCCESS != Cy_SysClk_ClkHfSetDivider(clkHf, divider)) + { + return CY_PRA_STATUS_ERROR_PROCESSING; + } + if (CY_SYSCLK_SUCCESS != Cy_SysClk_ClkHfEnable(clkHf)) + { + return CY_PRA_STATUS_ERROR_PROCESSING; + } + + return CY_PRA_STATUS_SUCCESS; +} + + +/******************************************************************************* +* Function Name: Cy_PRA_FllInit +****************************************************************************//** +* +* Initializes Frequency Locked Loop. This function configures FLL manually +* and enables FLL. +* +* \param devConfig +* +* \return +* CY_PRA_STATUS_SUCCESS FLL init is success +* CY_PRA_STATUS_ERROR_PROCESSING_FLL0 FLL init fails +* +*******************************************************************************/ +__STATIC_INLINE cy_en_pra_status_t Cy_PRA_FllInit(const cy_stc_pra_system_config_t *devConfig) +{ + const cy_stc_fll_manual_config_t fllconfig = + { + .ccoRange = devConfig->fllCcoRange, + .cco_Freq = devConfig->ccoFreq, + .enableOutputDiv = devConfig->enableOutputDiv, + .fllMult = devConfig->fllMult, + .igain = devConfig->igain, + .lockTolerance = devConfig->lockTolerance, + .outputMode = devConfig->outputMode, + .pgain = devConfig->pgain, + .refDiv = devConfig->fllRefDiv, + .settlingCount = devConfig->settlingCount, + }; + + if (CY_SYSCLK_SUCCESS != Cy_SysClk_FllManualConfigure(&fllconfig)) + { + return CY_PRA_STATUS_ERROR_PROCESSING_FLL0; + } + if (CY_SYSCLK_SUCCESS != Cy_SysClk_FllEnable(CY_PRA_FLL_ENABLE_TIMEOUT)) + { + return CY_PRA_STATUS_ERROR_PROCESSING_FLL0; + } + + return CY_PRA_STATUS_SUCCESS; +} + + +/******************************************************************************* +* Function Name: Cy_PRA_ExtClkInit +****************************************************************************//** +* +* Initializes External Clock Source. This function initializes external pin and +* sets EXT_CLK frequency. +* +* \param devConfig +* +*******************************************************************************/ +__STATIC_INLINE void Cy_PRA_ExtClkInit( const cy_stc_pra_system_config_t *devConfig ) +{ + if (devConfig->extClkPort != NULL) + { + Cy_GPIO_Pin_FastInit(devConfig->extClkPort, devConfig->extClkPinNum, CY_GPIO_DM_HIGHZ, 0UL, devConfig->extClkHsiom); + } + Cy_SysClk_ExtClkSetFrequency(devConfig->extClkFreqHz); +} + + +/******************************************************************************* +* Function Name: Cy_PRA_EcoInit +****************************************************************************//** +* +* Initializes External Crystal Oscillator. This function initializes input and +* output pins. Also configures and Enables ECO. +* +* \param devConfig +* +* \return +* CY_PRA_STATUS_SUCCESS CLK_ECO init is success. +* CY_PRA_STATUS_ERROR_PROCESSING_ECO CLK_ECO init is failure. +* +*******************************************************************************/ +__STATIC_INLINE cy_en_pra_status_t Cy_PRA_EcoInit(const cy_stc_pra_system_config_t *devConfig) +{ + if ((devConfig->ecoInPort != NULL) && (devConfig->ecoOutPort != NULL)) + { + Cy_GPIO_Pin_FastInit(devConfig->ecoInPort, devConfig->ecoInPinNum, CY_GPIO_DM_ANALOG, 0UL, HSIOM_SEL_GPIO); + Cy_GPIO_Pin_FastInit(devConfig->ecoOutPort, devConfig->ecoOutPinNum, CY_GPIO_DM_ANALOG, 0UL, HSIOM_SEL_GPIO); + } + if (CY_SYSCLK_SUCCESS != Cy_SysClk_EcoConfigure(devConfig->ecoFreqHz, devConfig->ecoLoad, devConfig->ecoEsr, devConfig->ecoDriveLevel)) + { + return CY_PRA_STATUS_ERROR_PROCESSING_ECO; + } + if (CY_SYSCLK_SUCCESS != Cy_SysClk_EcoEnable(CY_PRA_ECO_ENABLE_TIMEOUT)) + { + return CY_PRA_STATUS_ERROR_PROCESSING_ECO; + } + + return CY_PRA_STATUS_SUCCESS; +} + + +/******************************************************************************* +* Function Name: Cy_PRA_PiloInit +****************************************************************************//** +* +* Initializes PILO. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_PRA_PiloInit(void) +{ + Cy_SysClk_PiloEnable(); +} + +#if defined(CY_IP_MXBLESS) +/******************************************************************************* +* Function Name: Cy_PRA_AltHfInit +****************************************************************************//** +* +* Initializes Alternative High-Frequency Clock. +* +* \param devConfig +* +* \return +* CY_PRA_STATUS_SUCCESS AltHF init is success +* CY_PRA_STATUS_ERROR_PROCESSING_ALTHF AltHF init failed +* +*******************************************************************************/ +__STATIC_INLINE cy_en_pra_status_t Cy_PRA_AltHfInit(const cy_stc_pra_system_config_t *devConfig) +{ + cy_en_ble_eco_status_t status; + status = Cy_BLE_EcoConfigure((cy_en_ble_eco_freq_t)devConfig->altHFfreq, (cy_en_ble_eco_sys_clk_div_t)devConfig->altHFsysClkDiv, devConfig->altHFcLoad, devConfig->altHFxtalStartUpTime, (cy_en_ble_eco_voltage_reg_t)devConfig->altHFvoltageReg); + if ((CY_BLE_ECO_SUCCESS != status) && (CY_BLE_ECO_ALREADY_STARTED !=status)) + { + return CY_PRA_STATUS_ERROR_PROCESSING_ALTHF; + } + + return CY_PRA_STATUS_SUCCESS; +} + +/******************************************************************************* +* Function Name: Cy_PRA_AltHfReset +****************************************************************************//** +* +* Reset Alternative High-Frequency Clock. +* +* \param devConfig +* +*******************************************************************************/ +__STATIC_INLINE void Cy_PRA_AltHfReset(const cy_stc_pra_system_config_t *devConfig) +{ + static bool firstEntryAfterReset = true; + + /* Cy_BLE_EcoReset is called when this function is called the first time + * after a reset or ECO state change from ENABLE to DISABLE at runtime. */ + if (firstEntryAfterReset || (Cy_BLE_EcoIsEnabled() && !(devConfig->clkAltHfEnable))) + { + Cy_BLE_EcoReset(); + firstEntryAfterReset = false; + } +} + +#endif /* CY_IP_MXBLESS */ + + +/******************************************************************************* +* Function Name: Cy_PRA_ClkLfInit +****************************************************************************//** +* +* Initializes Low-Frequency Clock. +* +* \param clkLfSource \ref cy_en_clklf_in_sources_t +* +* \return +* CY_PRA_STATUS_SUCCESS LF init is success. +* CY_PRA_STATUS_ERROR_PROCESSING_CLKLF LF init is failure. +* +*******************************************************************************/ +__STATIC_INLINE cy_en_pra_status_t Cy_PRA_ClkLfInit(cy_en_clklf_in_sources_t clkLfSource) +{ + cy_en_pra_status_t retStatus = CY_PRA_STATUS_ERROR_PROCESSING_CLKLF; + + if (clkLfSource == Cy_SysClk_ClkLfGetSource()) /* No change in CLK_LF */ + { + retStatus = CY_PRA_STATUS_SUCCESS; + } + else + { + /* Cannot set an LF source when WDT is locked */ + if (!Cy_WDT_Locked()) + { + Cy_SysClk_ClkLfSetSource(clkLfSource); + retStatus = CY_PRA_STATUS_SUCCESS; + } + } + return retStatus; +} + + +/******************************************************************************* +* Function Name: Cy_PRA_WcoInit +****************************************************************************//** +* +* Initializes Watch Crystal Oscillator. +* +* \param devConfig +* +* \return +* CY_PRA_STATUS_SUCCESS WCO init is success. +* CY_PRA_STATUS_ERROR_PROCESSING_WCO WCO init is failure. +* +*******************************************************************************/ +__STATIC_INLINE cy_en_pra_status_t Cy_PRA_WcoInit(const cy_stc_pra_system_config_t *devConfig) +{ + if ((devConfig->wcoInPort != NULL) && (devConfig->wcoOutPort != NULL)) + { + Cy_GPIO_Pin_FastInit(devConfig->wcoInPort , devConfig->wcoInPinNum, 0x00U, 0x00U, HSIOM_SEL_GPIO); + Cy_GPIO_Pin_FastInit(devConfig->wcoOutPort , devConfig->wcoOutPinNum, 0x00U, 0x00U, HSIOM_SEL_GPIO); + } + if (devConfig->bypassEnable) + { + Cy_SysClk_WcoBypass(CY_SYSCLK_WCO_BYPASSED); + } + else + { + Cy_SysClk_WcoBypass(CY_SYSCLK_WCO_NOT_BYPASSED); + } + + if (CY_SYSCLK_SUCCESS != Cy_SysClk_WcoEnable(CY_PRA_WCO_ENABLE_TIMEOUT)) + { + return CY_PRA_STATUS_ERROR_PROCESSING_WCO; + } + + return CY_PRA_STATUS_SUCCESS; +} + + +/******************************************************************************* +* Function Name: Cy_PRA_PowerInit +****************************************************************************//** +* +* Initializes Power +* +* \param devConfig +* +* \return +* CY_PRA_STATUS_SUCCESS Power init is success. +* CY_PRA_STATUS_ERROR_PROCESSING_PWR Power init is failure. +* +*******************************************************************************/ +__STATIC_INLINE cy_en_pra_status_t Cy_PRA_PowerInit(const cy_stc_pra_system_config_t *devConfig) +{ + static bool firstCallAfterReset = true; + cy_en_pra_status_t status; + + /* Resets the Backup domain on POR, XRES, BOD only if Backup domain is supplied by VDDD */ + if ((devConfig->vBackupVDDDEnable) && firstCallAfterReset) + { + if (devConfig->iloEnable) + { + if (0u == Cy_SysLib_GetResetReason() /* POR, XRES, or BOD */) + { + if (CY_SYSLIB_SUCCESS != Cy_SysLib_ResetBackupDomain()) + { + return CY_PRA_STATUS_ERROR_PROCESSING_PWR; + } + status = Cy_PRA_IloDisable(); + if (CY_PRA_STATUS_SUCCESS != status) + { + return status; + } + status = Cy_PRA_IloEnable(); + if (CY_PRA_STATUS_SUCCESS != status) + { + return status; + } + status = Cy_PRA_IloHibernateOn(devConfig->iloHibernateON); + if (CY_PRA_STATUS_SUCCESS != status) + { + return status; + } + } + } + } + firstCallAfterReset = false; + + if (devConfig->ldoEnable) + { + /* LDO valid voltage */ + if ((devConfig->ldoVoltage == CY_SYSPM_LDO_VOLTAGE_0_9V) || + (devConfig->ldoVoltage == CY_SYSPM_LDO_VOLTAGE_1_1V)) + { + if (CY_SYSPM_SUCCESS != Cy_SysPm_LdoSetVoltage(devConfig->ldoVoltage)) + { + return CY_PRA_STATUS_ERROR_PROCESSING_PWR; + } + } + } + else + { + if ((devConfig->buckVoltage == CY_SYSPM_BUCK_OUT1_VOLTAGE_0_9V) || + (devConfig->buckVoltage == CY_SYSPM_BUCK_OUT1_VOLTAGE_1_1V)) + { + if (CY_SYSPM_SUCCESS != Cy_SysPm_BuckEnable(devConfig->buckVoltage)) + { + return CY_PRA_STATUS_ERROR_PROCESSING_PWR; + } + } + } + + if (devConfig->pwrCurrentModeMin) + { + /* Sets the system into Minimum current mode of the core regulator */ + if (CY_SYSPM_SUCCESS != Cy_SysPm_SystemSetMinRegulatorCurrent()) + { + return CY_PRA_STATUS_ERROR_PROCESSING_PWR; + } + } + else + { + /* Sets the system into Normal current mode of the core regulator */ + if (CY_SYSPM_SUCCESS != Cy_SysPm_SystemSetNormalRegulatorCurrent()) + { + return CY_PRA_STATUS_ERROR_PROCESSING_PWR; + } + } + + /* Configures PMIC */ + Cy_SysPm_UnlockPmic(); + if (devConfig->pmicEnable) + { + Cy_SysPm_PmicEnableOutput(); + } + else + { + Cy_SysPm_PmicDisableOutput(); + } + + return CY_PRA_STATUS_SUCCESS; +} + +/******************************************************************************* +* Function Name: Cy_PRA_GetInputPathMuxFrq +****************************************************************************//** +* +* Gets Source clock frequency for the path mux. +* +* \param pathMuxSrc The source clock for PATH_MUX. +* \param devConfig System Configuration Parameter +* +* \return +* Returns the source frequency of the path mux. +* +*******************************************************************************/ +static uint32_t Cy_PRA_GetInputPathMuxFrq(cy_en_clkpath_in_sources_t pathMuxSrc, const cy_stc_pra_system_config_t *devConfig) +{ + uint32_t srcFreq = CY_PRA_DEFAULT_SRC_FREQUENCY; /* Hz */ + + switch (pathMuxSrc) + { + case CY_SYSCLK_CLKPATH_IN_IMO: + { + srcFreq = CY_PRA_IMO_SRC_FREQUENCY; /* IMO Freq = 8 MHz */ + } + break; + case CY_SYSCLK_CLKPATH_IN_EXT: + { + srcFreq = devConfig->extClkFreqHz; + } + break; + case CY_SYSCLK_CLKPATH_IN_ECO: + { + srcFreq = devConfig->ecoFreqHz; + } + break; + case CY_SYSCLK_CLKPATH_IN_ALTHF: + { + srcFreq = devConfig->altHFfreq; + } + break; + case CY_SYSCLK_CLKPATH_IN_ILO: + { + srcFreq = CY_PRA_ILO_SRC_FREQUENCY; /* ILO Freq = 32 KHz */ + } + break; + case CY_SYSCLK_CLKPATH_IN_WCO: + { + srcFreq = CY_PRA_WCO_SRC_FREQUENCY; /* WCO Freq = 32.768 KHz */ + } + break; + case CY_SYSCLK_CLKPATH_IN_PILO: + { + if(CY_SRSS_PILO_PRESENT) + { + srcFreq = CY_PRA_PILO_SRC_FREQUENCY; /* PILO Freq = 32.768 KHz */ + } + } + break; + default: + { + srcFreq = CY_PRA_DEFAULT_SRC_FREQUENCY; + } + break; + } /* End Switch */ + + return srcFreq; +} + +/******************************************************************************* +* Function Name: Cy_PRA_GetInputSourceFreq +****************************************************************************//** +* +* Gets the source clock frequency for the clock path. This function is called from the HF +* level. +* +* \param clkPath Clock Path +* \param devConfig System Configuration Parameter +* \param srcFreq The source frequency of the clock path which is updated in this function. +* +* \return +* CY_PRA_STATUS_SUCCESS If the frequency is updated. +* CY_PRA_STATUS_INVALID_PARAM If clkpaht is not the valid path. +* +*******************************************************************************/ +static cy_en_pra_status_t Cy_PRA_GetInputSourceFreq(uint32_t clkPath, const cy_stc_pra_system_config_t *devConfig, uint32_t *srcFreq ) +{ + cy_en_pra_status_t status = CY_PRA_STATUS_INVALID_PARAM; + *srcFreq = CY_PRA_DEFAULT_SRC_FREQUENCY; + + if(clkPath >= CY_SRSS_NUM_CLKPATH) + { + return status; + } + + switch (clkPath) + { + case (uint32_t)CY_SYSCLK_CLKHF_IN_CLKPATH0: /* CLK_PATH0 */ + { + if (devConfig->path0Enable) + { + /* Checks for FLL, if FLL is enabled, returns the FLL output frequency */ + if ((devConfig->fllEnable) && (devConfig->outputMode != CY_SYSCLK_FLLPLL_OUTPUT_INPUT)) + { + *srcFreq = devConfig->fllOutFreqHz; + status = CY_PRA_STATUS_SUCCESS; + } + else + { + *srcFreq = Cy_PRA_GetInputPathMuxFrq(devConfig->path0Src, devConfig); + status = CY_PRA_STATUS_SUCCESS; + } + } + } + break; + case (uint32_t)CY_SYSCLK_CLKHF_IN_CLKPATH1: /* CLK_PATH1 */ + { + if (devConfig->path1Enable) + { + /* Checks for PLL0, if PLL0 is enabled, returns the PLL0 output frequency */ + if ((CY_SRSS_NUM_PLL >= CY_PRA_CLKPLL_1) && (devConfig->pll0Enable) && (devConfig->pll0OutputMode != CY_SYSCLK_FLLPLL_OUTPUT_INPUT)) + { + *srcFreq = devConfig->pll0OutFreqHz; + status = CY_PRA_STATUS_SUCCESS; + } + else + { + *srcFreq = Cy_PRA_GetInputPathMuxFrq(devConfig->path1Src, devConfig); + status = CY_PRA_STATUS_SUCCESS; + } + } + } + break; + case (uint32_t)CY_SYSCLK_CLKHF_IN_CLKPATH2: /* CLK_PATH2 */ + { + if (devConfig->path2Enable) + { + /* Checks for PLL1, if PLL1 is enabled, returns the PLL1 output frequency */ + if ((CY_SRSS_NUM_PLL >= CY_PRA_CLKPLL_2) && (devConfig->pll1Enable) && (devConfig->pll1OutputMode != CY_SYSCLK_FLLPLL_OUTPUT_INPUT)) + { + *srcFreq = devConfig->pll1OutFreqHz; + status = CY_PRA_STATUS_SUCCESS; + } + else + { + *srcFreq = Cy_PRA_GetInputPathMuxFrq(devConfig->path2Src, devConfig); + status = CY_PRA_STATUS_SUCCESS; + } + } + } + break; + case (uint32_t)CY_SYSCLK_CLKHF_IN_CLKPATH3: /* CLK_PATH3 */ + { + if (devConfig->path3Enable) + { + *srcFreq = Cy_PRA_GetInputPathMuxFrq(devConfig->path3Src, devConfig); + status = CY_PRA_STATUS_SUCCESS; + } + } + break; + case (uint32_t)CY_SYSCLK_CLKHF_IN_CLKPATH4: /* CLK_PATH4 */ + { + if (devConfig->path4Enable) + { + *srcFreq = Cy_PRA_GetInputPathMuxFrq(devConfig->path4Src, devConfig); + status = CY_PRA_STATUS_SUCCESS; + } + } + break; + case (uint32_t)CY_SYSCLK_CLKHF_IN_CLKPATH5: /* CLK_PATH5 */ + { + if (devConfig->path5Enable) + { + *srcFreq = Cy_PRA_GetInputPathMuxFrq(devConfig->path5Src, devConfig); + status = CY_PRA_STATUS_SUCCESS; + } + } + break; + default: + { + *srcFreq = CY_PRA_DEFAULT_SRC_FREQUENCY; + } + break; + } + + return status; +} + + +/******************************************************************************* +* Function Name: Cy_PRA_GetClkLfFreq +****************************************************************************//** +* +* Gets Low-Frequency Clock (CLK_LF). +* +* \param devConfig System Configuration Parameter +* +* \return CLK_LF The frequency. +* +*******************************************************************************/ +static uint32_t Cy_PRA_GetClkLfFreq(const cy_stc_pra_system_config_t *devConfig) +{ + uint32_t freq = CY_PRA_DEFAULT_SRC_FREQUENCY; + + if (devConfig->clkLFEnable) + { + switch (devConfig->clkLfSource) + { + case CY_SYSCLK_CLKLF_IN_ILO: + { + if (devConfig->iloEnable) + { + freq = CY_PRA_ILO_SRC_FREQUENCY; + } + } + break; + case CY_SYSCLK_CLKLF_IN_WCO: + { + if (devConfig->wcoEnable) + { + freq = CY_PRA_WCO_SRC_FREQUENCY; + } + } + break; + case CY_SYSCLK_CLKLF_IN_PILO: + { + if ((devConfig->piloEnable) && (CY_SRSS_PILO_PRESENT)) + { + freq = CY_PRA_PILO_SRC_FREQUENCY; + } + } + break; + default: + { + freq = CY_PRA_DEFAULT_SRC_FREQUENCY; + } + break; + } /* End Switch */ + } + + return freq; +} + +/******************************************************************************* +* Function Name: Cy_PRA_GetClkBakFreq +****************************************************************************//** +* +* Gets the BAK Clock (CLK_BAK) frequency. +* +* \param devConfig System Configuration Parameter +* +* \return CLK_LF The frequency. +* +*******************************************************************************/ +static uint32_t Cy_PRA_GetClkBakFreq(const cy_stc_pra_system_config_t *devConfig) +{ + uint32_t freq = CY_PRA_DEFAULT_SRC_FREQUENCY; + + if (devConfig->clkBakEnable) + { + switch (devConfig->clkBakSource) + { + case CY_SYSCLK_BAK_IN_WCO: + { + if (devConfig->wcoEnable) + { + freq = CY_PRA_WCO_SRC_FREQUENCY; + } + } + break; + case CY_SYSCLK_BAK_IN_CLKLF: + { + if (devConfig->clkLFEnable) + { + freq = Cy_PRA_GetClkLfFreq(devConfig); + } + } + break; + default: + { + freq = CY_PRA_DEFAULT_SRC_FREQUENCY; + } + break; + } /* End Switch */ + } + + return freq; +} + +/******************************************************************************* +* Function Name: Cy_PRA_GetInputSourceClock +****************************************************************************//** +* +* Gets the source clock for the clock path. +* +* \param clkPath Clock Path +* \param devConfig System Configuration Parameter +* \param status +* CY_PRA_STATUS_SUCCESS for valid input configuration +* CY_PRA_STATUS_INVALID_PARAM for bad parameter +* +* \return +* Returns the source clock. +* +*******************************************************************************/ +static cy_en_clkpath_in_sources_t Cy_PRA_GetInputSourceClock(uint32_t clkPath, const cy_stc_pra_system_config_t *devConfig, cy_en_pra_status_t *status) +{ + cy_en_clkpath_in_sources_t srcClock = CY_SYSCLK_CLKPATH_IN_IMO; + + if(clkPath >= CY_SRSS_NUM_CLKPATH) + { + *status = CY_PRA_STATUS_INVALID_PARAM; + return srcClock; + } + + *status = CY_PRA_STATUS_INVALID_PARAM; + + switch (clkPath) + { + case (uint32_t)CY_SYSCLK_CLKHF_IN_CLKPATH0: /* CLK_PATH0 */ + { + if (devConfig->path0Enable) /* Checks for PATH_MUX0 enable/disable */ + { + srcClock = devConfig->path0Src; + *status = CY_PRA_STATUS_SUCCESS; + } + } + break; + case (uint32_t)CY_SYSCLK_CLKHF_IN_CLKPATH1: /* CLK_PATH1 */ + { + if (devConfig->path1Enable) /* Checks for PATH_MUX1 enable/disable */ + { + srcClock = devConfig->path1Src; + *status = CY_PRA_STATUS_SUCCESS; + } + } + break; + case (uint32_t)CY_SYSCLK_CLKHF_IN_CLKPATH2: /* CLK_PATH2 */ + { + if (devConfig->path2Enable) /* Checks for PATH_MUX2 enable/disable */ + { + srcClock = devConfig->path2Src; + *status = CY_PRA_STATUS_SUCCESS; + } + } + break; + case (uint32_t)CY_SYSCLK_CLKHF_IN_CLKPATH3: /* CLK_PATH3 */ + { + if (devConfig->path3Enable) /* Checks for PATH_MUX3 enable/disable */ + { + srcClock = devConfig->path3Src; + *status = CY_PRA_STATUS_SUCCESS; + } + } + break; + case (uint32_t)CY_SYSCLK_CLKHF_IN_CLKPATH4: /* CLK_PATH4 */ + { + if (devConfig->path4Enable) /* Checks for PATH_MUX4 enable/disable */ + { + srcClock = devConfig->path4Src; + *status = CY_PRA_STATUS_SUCCESS; + } + } + break; + case (uint32_t)CY_SYSCLK_CLKHF_IN_CLKPATH5: /* CLK_PATH5 */ + { + if (devConfig->path5Enable) /* Checks for PATH_MUX5 enable/disable */ + { + srcClock = devConfig->path5Src; + *status = CY_PRA_STATUS_SUCCESS; + } + } + break; + default: + { + /* Returns CY_PRA_STATUS_INVALID_PARAM */ + } + break; + } + + return srcClock; +} + +#define CY_PRA_SYSCLK_ECO_FREQ_MIN (16000000UL) /* 16 MHz */ +#define CY_PRA_SYSCLK_ECO_FREQ_MAX (35000000UL) /* 35 MHz */ +#define CY_PRA_SYSCLK_ECO_CSM_MIN (1UL) /* 1 pF */ +#define CY_PRA_SYSCLK_ECO_CSM_MAX (100UL) /* 100 pF */ +#define CY_PRA_SYSCLK_ECO_ESR_MIN (1UL) /* 1 Ohm */ +#define CY_PRA_SYSCLK_ECO_ESR_MAX (1000UL) /* 1000 Ohm */ +#define CY_PRA_SYSCLK_ECO_DRV_MIN (1UL) /* 1 kW */ +#define CY_PRA_SYSCLK_ECO_DRV_MAX (1000UL) /* 1 mW */ + + +/******************************************************************************* +* Function Name: Cy_PRA_ValidateECO +****************************************************************************//** +* +* Validates the ECO. +* +* \param devConfig System Configuration Parameter +* +* \return +* CY_PRA_STATUS_SUCCESS For valid input configuration. +* CY_PRA_STATUS_INVALID_PARAM_ECO For the invalid parameter. +* +*******************************************************************************/ +static cy_en_pra_status_t Cy_PRA_ValidateECO(const cy_stc_pra_system_config_t *devConfig) +{ + cy_en_pra_status_t retStatus = CY_PRA_STATUS_SUCCESS; + + /* ECO cannot be the source for HF0. HF0 validation will check that. */ + /* The parameter validation will be implemented in DRIVERS-2751 */ + if ((CY_SYSCLK_ECOSTAT_STABLE != Cy_SysClk_EcoGetStatus()) && (devConfig->ecoEnable)) + { + if (((devConfig->ecoFreqHz >= CY_PRA_SYSCLK_ECO_FREQ_MIN) && (devConfig->ecoFreqHz <= CY_PRA_SYSCLK_ECO_FREQ_MAX)) /* The legal range of the ECO frequecy is [16.0000-35.0000] */ + && ((devConfig->ecoLoad >= CY_PRA_SYSCLK_ECO_CSM_MIN) && (devConfig->ecoLoad <= CY_PRA_SYSCLK_ECO_CSM_MAX)) /* The ECO cLoad range [1 - 100] */ + && ((devConfig->ecoEsr >= CY_PRA_SYSCLK_ECO_ESR_MIN) && (devConfig->ecoEsr <= CY_PRA_SYSCLK_ECO_ESR_MAX)) /* The ECO ESR range [1 - 1000] */ + && ((devConfig->ecoDriveLevel >= CY_PRA_SYSCLK_ECO_DRV_MIN) && (devConfig->ecoDriveLevel <= CY_PRA_SYSCLK_ECO_DRV_MAX))) /* The ECO Drive Level range [1 - 1000] */ + { + retStatus = CY_PRA_STATUS_SUCCESS; + } + else + { + retStatus = CY_PRA_STATUS_INVALID_PARAM_ECO; + } + } + + return retStatus; +} + +/******************************************************************************* +* Function Name: Cy_PRA_ValidateEXTClk +****************************************************************************//** +* +* Validates External Clock Source. +* +* \param devConfig System Configuration Parameter +* +* \return +* CY_PRA_STATUS_SUCCESS For valid input configuration. +* CY_PRA_STATUS_INVALID_PARAM_EXTCLK For the invalid parameter. +* +*******************************************************************************/ +static cy_en_pra_status_t Cy_PRA_ValidateEXTClk(const cy_stc_pra_system_config_t *devConfig) +{ + uint32_t maxFreq; + + /* For ULP mode, Fextclk_max = 50 MHz. For LP mode, Fextclk_max = 100 MHz or Fcpu_max (if Fcpu_max < 100 MHz) */ + if (devConfig->extClkEnable) + { + if (devConfig->ulpEnable) + { + if (devConfig->extClkFreqHz > CY_PRA_ULP_MODE_MAX_FREQUENCY) + { + return CY_PRA_STATUS_INVALID_PARAM_EXTCLK; + } + } + else + { + (CY_HF_CLK_MAX_FREQ > CY_PRA_LP_MODE_MAX_FREQUENCY) ? (maxFreq = CY_PRA_LP_MODE_MAX_FREQUENCY) : (maxFreq = CY_HF_CLK_MAX_FREQ); + if (devConfig->extClkFreqHz > maxFreq) + { + return CY_PRA_STATUS_INVALID_PARAM_EXTCLK; + } + } /*usingULP*/ + + /* GPIO port cannot be NULL */ + if (devConfig->extClkPort == NULL) + { + return CY_PRA_STATUS_INVALID_PARAM_EXTCLK; + } + } + + return CY_PRA_STATUS_SUCCESS; +} + +#if defined(CY_IP_MXBLESS) + +/******************************************************************************* +* Function Name: Cy_PRA_ValidateAltHf +****************************************************************************//** +* +* Validates Alternative High-Frequency Clock. +* +* \param devConfig System Configuration Parameter +* +* \return +* CY_PRA_STATUS_SUCCESS For the valid input configuration. +* CY_PRA_STATUS_INVALID_PARAM_ALTHF For the invalid parameter. +* +*******************************************************************************/ +static cy_en_pra_status_t Cy_PRA_ValidateAltHf(const cy_stc_pra_system_config_t *devConfig) +{ + + if (devConfig->clkAltHfEnable) + { + uint32_t startupTime; + /* Validates the frequency */ + if ((devConfig->altHFfreq < CY_PRA_ALTHF_MIN_FREQUENCY) || (devConfig->altHFfreq > CY_PRA_ALTHF_MAX_FREQUENCY)) + { + return CY_PRA_STATUS_INVALID_PARAM_ALTHF; + } + /* Startup Time */ + startupTime = devConfig->altHFxtalStartUpTime << 5U; + if ((startupTime < CY_PRA_ALTHF_MIN_STARTUP_TIME) || (startupTime > CY_PRA_ALTHF_MAX_STARTUP_TIME)) + { + return CY_PRA_STATUS_INVALID_PARAM_ALTHF; + } + /* Load Cap Range min="7.5" max="26.325" */ + if ((devConfig->altHFcLoad < CY_PRA_ALTHF_MIN_LOAD) || (devConfig->altHFcLoad > CY_PRA_ALTHF_MAX_LOAD)) + { + return CY_PRA_STATUS_INVALID_PARAM_ALTHF; + } + /* Validates the clock divider */ + if (devConfig->altHFsysClkDiv > CY_BLE_SYS_ECO_CLK_DIV_8) + { + return CY_PRA_STATUS_INVALID_PARAM_ALTHF; + } + } + return CY_PRA_STATUS_SUCCESS; +} +#endif /* CY_IP_MXBLESS */ + +/******************************************************************************* +* Function Name: Cy_PRA_ValidateFLL +****************************************************************************//** +* +* Validates the Frequency Locked Loop (FLL). +* +* \param devConfig System Configuration Parameter +* +* \return +* CY_PRA_STATUS_SUCCESS For the valid input configuration. +* CY_PRA_STATUS_INVALID_PARAM_FLL For the invalid parameter. +* +*******************************************************************************/ +static cy_en_pra_status_t Cy_PRA_ValidateFLL(const cy_stc_pra_system_config_t *devConfig) +{ + uint32_t srcFreq; + + /* Validates FLL only when its state changes Disable -> Enable */ + if ((!Cy_SysClk_FllIsEnabled()) && (devConfig->fllEnable)) + { + /* FLL is always sourced from PATH_MUX0 */ + /* If FLL is sourced from ECO, WCO, ALTHF, EXTCLK, ILO, PILO clocks, then FLL output cannot source + * to HF0. HF0 validation will check that. */ + if (devConfig->path0Enable) + { + /* The source clock for the FLL valid range is 1 kHz - 100 MHz */ + srcFreq = Cy_PRA_GetInputPathMuxFrq(devConfig->path0Src, devConfig); + if ((srcFreq < CY_PRA_FLL_SRC_MIN_FREQUENCY) || (srcFreq > CY_PRA_FLL_SRC_MAX_FREQUENCY)) + { + return CY_PRA_STATUS_INVALID_PARAM_FLL0; + } + + /* For ULP mode, the out frequency range is 24 - 50 MHz */ + /* For LP mode, theout frequency range is 24 - 100 MHz */ + if (devConfig->ulpEnable) + { + if ((devConfig->fllOutFreqHz < CY_PRA_FLL_OUT_MIN_FREQUENCY) || (devConfig->fllOutFreqHz > CY_PRA_FLL_ULP_OUT_MAX_FREQUENCY)) + { + return CY_PRA_STATUS_INVALID_PARAM_FLL0; + } + } + else + { + if ((devConfig->fllOutFreqHz < CY_PRA_FLL_OUT_MIN_FREQUENCY) || (devConfig->fllOutFreqHz > CY_PRA_FLL_OUT_MAX_FREQUENCY)) + { + return CY_PRA_STATUS_INVALID_PARAM_FLL0; + } + } /*usingULP*/ + + /* Validates multiplier min="1" max="262143" */ + if ((devConfig->fllMult < CY_PRA_FLL_MIN_MULTIPLIER) || (devConfig->fllMult > CY_PRA_FLL_MAX_MULTIPLIER)) + { + return CY_PRA_STATUS_INVALID_PARAM_FLL0; + } + /* Validates reference min="1" max="8191" */ + if ((devConfig->fllRefDiv < CY_PRA_FLL_MIN_REFDIV) || (devConfig->fllRefDiv > CY_PRA_FLL_MAX_REFDIV)) + { + return CY_PRA_STATUS_INVALID_PARAM_FLL0; + } + /* ccoRange */ + if (devConfig->fllCcoRange > CY_SYSCLK_FLL_CCO_RANGE4) + { + return CY_PRA_STATUS_INVALID_PARAM_FLL0; + } + /* lockTolerance min="0" max="511" */ + if (devConfig->lockTolerance > CY_PRA_FLL_MAX_LOCK_TOLERENCE) + { + return CY_PRA_STATUS_INVALID_PARAM_FLL0; + } + if (devConfig->igain > (SRSS_CLK_FLL_CONFIG3_FLL_LF_IGAIN_Msk >> SRSS_CLK_FLL_CONFIG3_FLL_LF_IGAIN_Pos)) + { + return CY_PRA_STATUS_INVALID_PARAM_FLL0; + } + if (devConfig->pgain > (SRSS_CLK_FLL_CONFIG3_FLL_LF_PGAIN_Msk >> SRSS_CLK_FLL_CONFIG3_FLL_LF_PGAIN_Pos)) + { + return CY_PRA_STATUS_INVALID_PARAM_FLL0; + } + if (devConfig->settlingCount > (SRSS_CLK_FLL_CONFIG3_SETTLING_COUNT_Msk >> SRSS_CLK_FLL_CONFIG3_SETTLING_COUNT_Pos)) + { + return CY_PRA_STATUS_INVALID_PARAM_FLL0; + } + if (devConfig->ccoFreq > (SRSS_CLK_FLL_CONFIG4_CCO_FREQ_Msk >> SRSS_CLK_FLL_CONFIG4_CCO_FREQ_Pos)) + { + return CY_PRA_STATUS_INVALID_PARAM_FLL0; + } + + /* Validates the FLL output frequency */ + if ((devConfig->fllOutFreqHz) != Cy_PRA_CalculateFLLOutFreq(devConfig)) + { + return CY_PRA_STATUS_INVALID_PARAM_FLL0; + } + + return CY_PRA_STATUS_SUCCESS; + } + else + { + return CY_PRA_STATUS_INVALID_PARAM_FLL0; + } + } + + return CY_PRA_STATUS_SUCCESS; +} + +/******************************************************************************* +* Function Name: Cy_PRA_ValidatePLL +****************************************************************************//** +* +* Validates Phase Locked Loop (PLL). +* +* \param devConfig System Configuration Parameter +* \param pll The PLL number. +* +* \return +* CY_PRA_STATUS_SUCCESS For the valid input configuration. +* CY_PRA_STATUS_INVALID_PARAM For the invalid parameter. +* +*******************************************************************************/ +static cy_en_pra_status_t Cy_PRA_ValidatePLL(const cy_stc_pra_system_config_t *devConfig, uint8_t pll) +{ + uint32_t srcFreq, outFreq, minDesiredOutFreq; + bool pllEnable, pathEnable, lowFreqMode; + cy_en_clkpath_in_sources_t pathSrc; + + if ((pll == CY_PRA_DEFAULT_ZERO) || (pll > CY_SRSS_NUM_PLL)) + { + return CY_PRA_STATUS_INVALID_PARAM; + } + + if (pll == CY_PRA_CLKPLL_1) + { + pllEnable = devConfig->pll0Enable; + pathEnable = devConfig->path1Enable; + pathSrc = devConfig->path1Src; + outFreq = devConfig->pll0OutFreqHz; + lowFreqMode = devConfig->pll0LfMode; + } + else if (pll == CY_PRA_CLKPLL_2) + { + pllEnable = devConfig->pll1Enable; + pathEnable = devConfig->path2Enable; + pathSrc = devConfig->path2Src; + outFreq = devConfig->pll1OutFreqHz; + lowFreqMode = devConfig->pll1LfMode; + } + else + { + return CY_PRA_STATUS_INVALID_PARAM; + } + + /* If PLL is sourced from ECO, WCO, ALTHF, EXTCLK, ILO, PILO clocks, then the PLL output cannot source + * to HF0. This check is performed at HF0 validation */ + if (pllEnable) + { + if (pathEnable) + { + /* The PLL source clock valid range is 4 MHz - 64 MHz */ + srcFreq = Cy_PRA_GetInputPathMuxFrq(pathSrc, devConfig); + if ((srcFreq < CY_PRA_PLL_SRC_MIN_FREQUENCY) || (srcFreq > CY_PRA_PLL_SRC_MAX_FREQUENCY)) + { + return CY_PRA_STATUS_INVALID_PARAM; + } + + /* If Low frequency mode is enabled, the PLL minimum output frequency is 10.625 MHz otherwise 12.5 MHz */ + (lowFreqMode) ? (minDesiredOutFreq = CY_PRA_PLL_LOW_OUT_MIN_FREQUENCY) : (minDesiredOutFreq = CY_PRA_PLL_OUT_MIN_FREQUENCY); + /* For ULP mode, the out frequency is < 50 MHz */ + /* For LP mode, the out frequency is < CY_HF_CLK_MAX_FREQ */ + if (devConfig->ulpEnable) + { + if ((outFreq < minDesiredOutFreq) || (outFreq > CY_PRA_PLL_ULP_OUT_MAX_FREQUENCY)) + { + return CY_PRA_STATUS_INVALID_PARAM; + } + } + else + { + if ((outFreq < minDesiredOutFreq) || (outFreq > CY_PRA_PLL_OUT_MAX_FREQUENCY)) + { + return CY_PRA_STATUS_INVALID_PARAM; + } + } /*usingULP*/ + + /* Checks the PLL output frequency */ + if (outFreq != Cy_PRA_CalculatePLLOutFreq(pll, devConfig)) + { + return CY_PRA_STATUS_INVALID_PARAM; + } + } + else + { + return CY_PRA_STATUS_INVALID_PARAM; + } + } + + return CY_PRA_STATUS_SUCCESS; +} + +/******************************************************************************* +* Function Name: Cy_PRA_ValidateAllPLL +****************************************************************************//** +* +* Validates All Phase Locked Loop (PLL). +* +* \param devConfig System Configuration Parameter +* +* \return +* CY_PRA_STATUS_SUCCESS For the valid input configuration. +* CY_PRA_STATUS_INVALID_PARAM_PLL0 For the PLLO invalid parameter. +* CY_PRA_STATUS_INVALID_PARAM_PLL1 For the PLL1 invalid parameter. +* +*******************************************************************************/ +static cy_en_pra_status_t Cy_PRA_ValidateAllPLL(const cy_stc_pra_system_config_t *devConfig) +{ + cy_en_pra_status_t retStatus = CY_PRA_STATUS_SUCCESS; + + /* PLL0 is always sourced from PATH_MUX1 */ + if ((CY_SRSS_NUM_PLL >= CY_PRA_CLKPLL_1) && (devConfig->pll0Enable)) + { + /* Validates PLL1 only when its state changes Disable -> Enable */ + if (!Cy_SysClk_PllIsEnabled(CY_PRA_CLKPLL_1)) + { + retStatus = Cy_PRA_ValidatePLL(devConfig, CY_PRA_CLKPLL_1); + } + + if (CY_PRA_STATUS_SUCCESS != retStatus) + { + retStatus = CY_PRA_STATUS_INVALID_PARAM_PLL0; + } + } + /* PLL1 is always sourced from PATH_MUX2 */ + if ((CY_SRSS_NUM_PLL >= CY_PRA_CLKPLL_2) && (devConfig->pll1Enable) && (retStatus == CY_PRA_STATUS_SUCCESS)) + { + /* Validates PLL2 only when its state changes Disable -> Enable */ + if (!Cy_SysClk_PllIsEnabled(CY_PRA_CLKPLL_2)) + { + retStatus = Cy_PRA_ValidatePLL(devConfig, CY_PRA_CLKPLL_2); + } + + if (CY_PRA_STATUS_SUCCESS != retStatus) + { + retStatus = CY_PRA_STATUS_INVALID_PARAM_PLL1; + } + } + return retStatus; +} + +/******************************************************************************* +* Function Name: Cy_PRA_ValidateClkLf +****************************************************************************//** +* +* Validates Low-Frequency Clock (CLK_LF). +* +* \param devConfig System Configuration Parameter +* +* \return +* CY_PRA_STATUS_SUCCESS For the valid input configuration. +* CY_PRA_STATUS_INVALID_PARAM_CLKLF For the invalid parameter. +* +*******************************************************************************/ +static cy_en_pra_status_t Cy_PRA_ValidateClkLf(const cy_stc_pra_system_config_t *devConfig) +{ + cy_en_pra_status_t retStatus = CY_PRA_STATUS_SUCCESS; + + /* output frequency = input frequency [range min="0" max="100000"] */ + if (devConfig->clkLFEnable) + { + switch (devConfig->clkLfSource) + { + case CY_SYSCLK_CLKLF_IN_ILO: + { + (devConfig->iloEnable) ? (retStatus = CY_PRA_STATUS_SUCCESS) : (retStatus = CY_PRA_STATUS_INVALID_PARAM_CLKLF); + } + break; + case CY_SYSCLK_CLKLF_IN_WCO: + { + (devConfig->wcoEnable) ? (retStatus = CY_PRA_STATUS_SUCCESS) : (retStatus = CY_PRA_STATUS_INVALID_PARAM_CLKLF); + } + break; + case CY_SYSCLK_CLKLF_IN_PILO: + { + ((devConfig->piloEnable) && (CY_SRSS_PILO_PRESENT)) ? (retStatus = CY_PRA_STATUS_SUCCESS) : (retStatus = CY_PRA_STATUS_INVALID_PARAM_CLKLF); + } + break; + default: + { + retStatus = CY_PRA_STATUS_INVALID_PARAM_CLKLF; + } + break; + } /* End of Switch */ + } + + return retStatus; +} + +/******************************************************************************* +* Function Name: Cy_PRA_ValidateClkPathMux +****************************************************************************//** +* +* Returns an error if the specified path source is disabled. +* +* \param pathSrc Source clock for the PATH_MUX +* \param devConfig System Configuration Parameter +* +* \return +* CY_PRA_STATUS_SUCCESS For the valid input configuration. +* CY_PRA_STATUS_INVALID_PARAM For the invalid parameter. +* +*******************************************************************************/ +static cy_en_pra_status_t Cy_PRA_ValidateClkPathMux(cy_en_clkpath_in_sources_t pathSrc, const cy_stc_pra_system_config_t *devConfig) +{ + cy_en_pra_status_t status; + + /* The Check Source clock is enabled */ + switch (pathSrc) + { + case CY_SYSCLK_CLKPATH_IN_IMO: + { + status = CY_PRA_STATUS_SUCCESS; + } + break; + case CY_SYSCLK_CLKPATH_IN_EXT: + { + (devConfig->extClkEnable) ? (status = CY_PRA_STATUS_SUCCESS) : (status = CY_PRA_STATUS_INVALID_PARAM); + } + break; + case CY_SYSCLK_CLKPATH_IN_ECO: + { + (devConfig->ecoEnable) ? (status = CY_PRA_STATUS_SUCCESS) : (status = CY_PRA_STATUS_INVALID_PARAM); + } + break; + case CY_SYSCLK_CLKPATH_IN_ALTHF: + { + (devConfig->clkAltHfEnable) ? (status = CY_PRA_STATUS_SUCCESS) : (status = CY_PRA_STATUS_INVALID_PARAM); + } + break; + case CY_SYSCLK_CLKPATH_IN_ILO: + { + (devConfig->iloEnable) ? (status = CY_PRA_STATUS_SUCCESS) : (status = CY_PRA_STATUS_INVALID_PARAM); + } + break; + case CY_SYSCLK_CLKPATH_IN_WCO: + { + (devConfig->wcoEnable) ? (status = CY_PRA_STATUS_SUCCESS) : (status = CY_PRA_STATUS_INVALID_PARAM); + } + break; + case CY_SYSCLK_CLKPATH_IN_PILO: + { + ((devConfig->piloEnable) && (CY_SRSS_PILO_PRESENT)) ? (status = CY_PRA_STATUS_SUCCESS) : (status = CY_PRA_STATUS_INVALID_PARAM); + } + break; + default: + { + status = CY_PRA_STATUS_INVALID_PARAM; + } + break; + } + + return status; +} + + +/******************************************************************************* +* Function Name: Cy_PRA_ValidateClkPath +****************************************************************************//** +* +* Validates the clock path. Checks whether the source clock of the clock path +* is enabled. +* +* \param clkPath Clock path +* \param devConfig System Configuration Parameter +* +* \return +* CY_PRA_STATUS_SUCCESS For the valid input configuration. +* CY_PRA_STATUS_INVALID_PARAM For the invalid parameter. +* +*******************************************************************************/ +static cy_en_pra_status_t Cy_PRA_ValidateClkPath(uint32_t clkPath, const cy_stc_pra_system_config_t *devConfig) +{ + cy_en_pra_status_t retStatus = CY_PRA_STATUS_INVALID_PARAM; + if(clkPath >= CY_SRSS_NUM_CLKPATH) + { + return retStatus; + } + + switch (clkPath) + { + case (uint32_t)CY_SYSCLK_CLKHF_IN_CLKPATH0: /* CLK_PATH0 */ + { + /* PATH_MUX0 must be enabled */ + if (devConfig->path0Enable) + { + retStatus = Cy_PRA_ValidateClkPathMux(devConfig->path0Src, devConfig); + } + } + break; + case (uint32_t)CY_SYSCLK_CLKHF_IN_CLKPATH1: /* CLK_PATH1 */ + { + /* PATH_MUX1 must be enabled */ + if (devConfig->path1Enable) + { + retStatus = Cy_PRA_ValidateClkPathMux(devConfig->path1Src, devConfig); + } + } + break; + case (uint32_t)CY_SYSCLK_CLKHF_IN_CLKPATH2: /* CLK_PATH2 */ + { + /* PATH_MUX2 must be enabled */ + if (devConfig->path2Enable) + { + retStatus = Cy_PRA_ValidateClkPathMux(devConfig->path2Src, devConfig); + } + } + break; + case (uint32_t)CY_SYSCLK_CLKHF_IN_CLKPATH3: /* CLK_PATH3 */ + { + /* PATH_MUX3 must be enabled */ + if (devConfig->path3Enable) + { + retStatus = Cy_PRA_ValidateClkPathMux(devConfig->path3Src, devConfig); + } + } + break; + case (uint32_t)CY_SYSCLK_CLKHF_IN_CLKPATH4: /* CLK_PATH4 */ + { + /* PATH_MUX4 must be enabled */ + if (devConfig->path4Enable) + { + retStatus = Cy_PRA_ValidateClkPathMux(devConfig->path4Src, devConfig); + } + } + break; + case (uint32_t)CY_SYSCLK_CLKHF_IN_CLKPATH5: /* CLK_PATH5 */ + { + /* PATH_MUX5 must be enabled */ + if (devConfig->path5Enable) + { + retStatus = Cy_PRA_ValidateClkPathMux(devConfig->path5Src, devConfig); + } + } + break; + default: + { + retStatus = CY_PRA_STATUS_INVALID_PARAM; + } + break; + } + + return retStatus; +} + +/******************************************************************************* +* Function Name: Cy_PRA_ValidateAllClkPathMux +****************************************************************************//** +* +* Validates All PATH MUXes. +* +* \param devConfig System Configuration Parameter +* +* \return +* CY_PRA_STATUS_SUCCESS For the valid input configuration. +* CY_PRA_STATUS_INVALID_PARAM_PATHMUX0 For the path-mux0 invalid parameter. +* CY_PRA_STATUS_INVALID_PARAM_PATHMUX1 For the path-mux1 invalid parameter. +* CY_PRA_STATUS_INVALID_PARAM_PATHMUX2 For the path-mux2 invalid parameter. +* CY_PRA_STATUS_INVALID_PARAM_PATHMUX3 For the path-mux3 invalid parameter. +* CY_PRA_STATUS_INVALID_PARAM_PATHMUX4 For the path-mux4 invalid parameter. +* CY_PRA_STATUS_INVALID_PARAM_PATHMUX5 For the path-mux5 invalid parameter. +* +*******************************************************************************/ +static cy_en_pra_status_t Cy_PRA_ValidateAllClkPathMux(const cy_stc_pra_system_config_t *devConfig) +{ + + if ((devConfig->path0Enable) && (CY_PRA_CLKPATH_0 < CY_SRSS_NUM_CLKPATH)) /* path_mux0 is enabled */ + { + if (CY_PRA_STATUS_SUCCESS != Cy_PRA_ValidateClkPathMux(devConfig->path0Src, devConfig)) + { + return CY_PRA_STATUS_INVALID_PARAM_PATHMUX0; + } + } + if ((devConfig->path1Enable) && (CY_PRA_CLKPATH_1 < CY_SRSS_NUM_CLKPATH)) /* path_mux1 is enabled */ + { + if (CY_PRA_STATUS_SUCCESS != Cy_PRA_ValidateClkPathMux(devConfig->path1Src, devConfig)) + { + return CY_PRA_STATUS_INVALID_PARAM_PATHMUX1; + } + } + if ((devConfig->path2Enable) && (CY_PRA_CLKPATH_2 < CY_SRSS_NUM_CLKPATH)) /* path_mux2 is enabled */ + { + if (CY_PRA_STATUS_SUCCESS != Cy_PRA_ValidateClkPathMux(devConfig->path2Src, devConfig)) + { + return CY_PRA_STATUS_INVALID_PARAM_PATHMUX2; + } + } + if ((devConfig->path3Enable) && (CY_PRA_CLKPATH_3 < CY_SRSS_NUM_CLKPATH)) /* path_mux3 is enabled */ + { + if (CY_PRA_STATUS_SUCCESS != Cy_PRA_ValidateClkPathMux(devConfig->path3Src, devConfig)) + { + return CY_PRA_STATUS_INVALID_PARAM_PATHMUX3; + } + } + if ((devConfig->path4Enable) && (CY_PRA_CLKPATH_4 < CY_SRSS_NUM_CLKPATH)) /* path_mux4 is enabled */ + { + if (CY_PRA_STATUS_SUCCESS != Cy_PRA_ValidateClkPathMux(devConfig->path4Src, devConfig)) + { + return CY_PRA_STATUS_INVALID_PARAM_PATHMUX4; + } + } + if ((devConfig->path5Enable) && (CY_PRA_CLKPATH_5 < CY_SRSS_NUM_CLKPATH))/* path_mux5 is enabled */ + { + if (CY_PRA_STATUS_SUCCESS != Cy_PRA_ValidateClkPathMux(devConfig->path5Src, devConfig)) + { + return CY_PRA_STATUS_INVALID_PARAM_PATHMUX5; + } + } + + return CY_PRA_STATUS_SUCCESS; +} + +/******************************************************************************* +* Function Name: Cy_PRA_ValidateClkHfFreqDiv +****************************************************************************//** +* +* Validates the High Frequency Clock's output frequency and divider. +* +* \param outFreqMHz Output frequency +* \param divider Frequency divider +* +* \return +* CY_PRA_STATUS_SUCCESS For the valid input configuration. +* CY_PRA_STATUS_INVALID_PARAM For the invalid parameter. +* +*******************************************************************************/ +static cy_en_pra_status_t Cy_PRA_ValidateClkHfFreqDiv(uint32_t outFreqMHz, cy_en_clkhf_dividers_t divider) +{ + /* min="1" max="CY_HF_CLK_MAX_FREQ" */ + if ((outFreqMHz*CY_PRA_FREQUENCY_HZ_CONVERSION) > CY_HF_CLK_MAX_FREQ) + { + return CY_PRA_STATUS_INVALID_PARAM; + } + if (divider > CY_SYSCLK_CLKHF_DIVIDE_BY_8) + { + return CY_PRA_STATUS_INVALID_PARAM; + } + + return CY_PRA_STATUS_SUCCESS; +} + +/******************************************************************************* +* Function Name: Cy_PRA_ValidateClkHFs +****************************************************************************//** +* +* Validates All High Frequency Clocks. +* +* \param devConfig System Configuration Parameter +* +* \return +* CY_PRA_STATUS_SUCCESS for valid input configuration +* CY_PRA_STATUS_INVALID_PARAM_CLKHF0 for bad parameter for HF0 +* CY_PRA_STATUS_INVALID_PARAM_CLKHF1 for bad parameter for HF1 +* CY_PRA_STATUS_INVALID_PARAM_CLKHF2 for bad parameter for HF2 +* CY_PRA_STATUS_INVALID_PARAM_CLKHF3 for bad parameter for HF3 +* CY_PRA_STATUS_INVALID_PARAM_CLKHF4 for bad parameter for HF4 +* CY_PRA_STATUS_INVALID_PARAM_CLKHF5 for bad parameter for HF5 +* +*******************************************************************************/ +static cy_en_pra_status_t Cy_PRA_ValidateClkHFs(const cy_stc_pra_system_config_t *devConfig) +{ + cy_en_clkpath_in_sources_t clkSource; + cy_en_pra_status_t status; + uint32_t freq; + + /* Validates HF0 */ + if ((devConfig->clkHF0Enable) && (CY_PRA_CLKHF_0 < CY_SRSS_NUM_HFROOT)) + { + /* The input source clock should be enabled */ + if (CY_PRA_STATUS_SUCCESS != Cy_PRA_ValidateClkPath((uint32_t)(devConfig->hf0Source), devConfig)) + { + return CY_PRA_STATUS_INVALID_PARAM_CLKHF0; + } + + /* ECO, WCO, ALTHF, EXTCLK, ILO, PILO cannot act as the source to HF0 */ + clkSource = Cy_PRA_GetInputSourceClock((uint32_t) devConfig->hf0Source, devConfig, &status); + if ((clkSource != CY_SYSCLK_CLKPATH_IN_IMO) || (status != CY_PRA_STATUS_SUCCESS)) + { + return CY_PRA_STATUS_INVALID_PARAM_CLKHF0; + } + + /* HF0: the input source cannot be slower than legal min 200 kHz */ + status = Cy_PRA_GetInputSourceFreq((uint32_t) devConfig->hf0Source, devConfig, &freq); + if ((freq < CY_PRA_HF0_MIN_FREQUENCY) || (status != CY_PRA_STATUS_SUCCESS)) + { + return CY_PRA_STATUS_INVALID_PARAM_CLKHF0; + } + + /* Validates the output frequency and divider */ + /* The HF0 output frequency cannot be 0 MHz because the current LF + * clocks are not allowed to source HF0 */ + if ((devConfig->hf0OutFreqMHz == 0UL) || (CY_PRA_STATUS_SUCCESS != Cy_PRA_ValidateClkHfFreqDiv(devConfig->hf0OutFreqMHz, devConfig->hf0Divider))) + { + return CY_PRA_STATUS_INVALID_PARAM_CLKHF0; + } + } + else + { + /* This cannot be disabled */ + return CY_PRA_STATUS_INVALID_PARAM_CLKHF0; + } + + /* Validates HF1 */ + if ((devConfig->clkHF1Enable) && (CY_PRA_CLKHF_1 < CY_SRSS_NUM_HFROOT)) + { + /* The input source clock should be enabled */ + if (CY_PRA_STATUS_SUCCESS != Cy_PRA_ValidateClkPath((uint32_t)(devConfig->hf1Source), devConfig)) + { + return CY_PRA_STATUS_INVALID_PARAM_CLKHF1; + } + /* Validates the output frequency and divider */ + if (CY_PRA_STATUS_SUCCESS != Cy_PRA_ValidateClkHfFreqDiv(devConfig->hf1OutFreqMHz, devConfig->hf1Divider)) + { + return CY_PRA_STATUS_INVALID_PARAM_CLKHF1; + } + } + + /* Validates HF2 */ + if ((devConfig->clkHF2Enable) && (CY_PRA_CLKHF_2 < CY_SRSS_NUM_HFROOT)) + { + /* The input source clock should be enabled */ + if (CY_PRA_STATUS_SUCCESS != Cy_PRA_ValidateClkPath((uint32_t)(devConfig->hf2Source), devConfig)) + { + return CY_PRA_STATUS_INVALID_PARAM_CLKHF2; + } + + /* Validates the output frequency and divider */ + if (CY_PRA_STATUS_SUCCESS != Cy_PRA_ValidateClkHfFreqDiv(devConfig->hf2OutFreqMHz, devConfig->hf2Divider)) + { + return CY_PRA_STATUS_INVALID_PARAM_CLKHF2; + } + } + + /* Validates HF3 */ + if ((devConfig->clkHF3Enable) && (CY_PRA_CLKHF_3 < CY_SRSS_NUM_HFROOT)) + { + /* The input source clock should be enabled */ + if (CY_PRA_STATUS_SUCCESS != Cy_PRA_ValidateClkPath((uint32_t) devConfig->hf3Source, devConfig)) + { + return CY_PRA_STATUS_INVALID_PARAM_CLKHF3; + } + + /* Validates the output frequency and divider */ + if (CY_PRA_STATUS_SUCCESS != Cy_PRA_ValidateClkHfFreqDiv(devConfig->hf3OutFreqMHz, devConfig->hf3Divider)) + { + return CY_PRA_STATUS_INVALID_PARAM_CLKHF3; + } + } + + /* Validates HF4 */ + if ((devConfig->clkHF4Enable) && (CY_PRA_CLKHF_4 < CY_SRSS_NUM_HFROOT)) + { + /* The input source clock should be enabled */ + if (CY_PRA_STATUS_SUCCESS != Cy_PRA_ValidateClkPath((uint32_t) devConfig->hf4Source, devConfig)) + { + return CY_PRA_STATUS_INVALID_PARAM_CLKHF4; + } + + /* Validates the output frequency and divider */ + if (CY_PRA_STATUS_SUCCESS != Cy_PRA_ValidateClkHfFreqDiv(devConfig->hf4OutFreqMHz, devConfig->hf4Divider)) + { + return CY_PRA_STATUS_INVALID_PARAM_CLKHF4; + } + } + + /* Validates HF5 */ + if ((devConfig->clkHF5Enable) && (CY_PRA_CLKHF_5 < CY_SRSS_NUM_HFROOT)) + { + /* The input source clock should be enabled */ + if (CY_PRA_STATUS_SUCCESS != Cy_PRA_ValidateClkPath((uint32_t) devConfig->hf5Source, devConfig)) + { + return CY_PRA_STATUS_INVALID_PARAM_CLKHF5; + } + + /* Validates the output frequency and divider */ + if (CY_PRA_STATUS_SUCCESS != Cy_PRA_ValidateClkHfFreqDiv(devConfig->hf5OutFreqMHz, devConfig->hf5Divider)) + { + return CY_PRA_STATUS_INVALID_PARAM_CLKHF5; + } + } + + return CY_PRA_STATUS_SUCCESS; +} + +/******************************************************************************* +* Function Name: Cy_PRA_ValidateClkPump +****************************************************************************//** +* +* Validates the PUMP Clock. +* +* \param devConfig System Configuration Parameter +* +* \return +* CY_PRA_STATUS_SUCCESS For the valid input configuration. +* CY_PRA_STATUS_INVALID_PARAM_CLKPUMP For the invalid parameter. +* +*******************************************************************************/ +static cy_en_pra_status_t Cy_PRA_ValidateClkPump(const cy_stc_pra_system_config_t *devConfig) +{ + uint32_t freq; + cy_en_pra_status_t status = CY_PRA_STATUS_SUCCESS; + /* Validates PUMP */ + if (devConfig->clkPumpEnable) + { + /* The input source clock should be enabled */ + if (CY_PRA_STATUS_SUCCESS != Cy_PRA_ValidateClkPath((uint32_t) devConfig->pumpSource, devConfig)) + { + return CY_PRA_STATUS_INVALID_PARAM_CLKPUMP; + } + + /* Validates the divider */ + if (devConfig->pumpDivider > CY_SYSCLK_PUMP_DIV_16) + { + return CY_PRA_STATUS_INVALID_PARAM_CLKPUMP; + } + + /* Output frequency range min="0" max="400000000" */ + status = Cy_PRA_GetInputSourceFreq((uint32_t) devConfig->pumpSource,devConfig, &freq); + if( status == CY_PRA_STATUS_SUCCESS ) + { + freq = freq / (1UL << devConfig->pumpDivider); /* Calculates the output frequency */ + if (freq > CY_PRA_PUMP_OUT_MAX_FREQUENCY) + { + return CY_PRA_STATUS_INVALID_PARAM_CLKPUMP; + } + } + else + { + status = CY_PRA_STATUS_INVALID_PARAM_CLKPUMP; + } + } + + return status; +} + +/******************************************************************************* +* Function Name: Cy_PRA_ValidateClkBak +****************************************************************************//** +* +* Validates Backup Domain Clock. +* +* \param devConfig System Configuration Parameter +* +* \return +* CY_PRA_STATUS_SUCCESS for valid input configuration +* CY_PRA_STATUS_INVALID_PARAM_CLKBAK for bad parameter +* +*******************************************************************************/ +static cy_en_pra_status_t Cy_PRA_ValidateClkBak(const cy_stc_pra_system_config_t *devConfig) +{ + cy_en_pra_status_t retStatus = CY_PRA_STATUS_SUCCESS; + uint32_t freq; + + if (devConfig->clkBakEnable) + { + /* If CLK_BAK is enabled, the source clock, either CLK_LF or CLK_WCO, + * must be enabled */ + switch (devConfig->clkBakSource) + { + case CY_SYSCLK_BAK_IN_WCO: + { + (devConfig->wcoEnable) ? (retStatus = CY_PRA_STATUS_SUCCESS) : (retStatus = CY_PRA_STATUS_INVALID_PARAM_CLKBAK); + } + break; + case CY_SYSCLK_BAK_IN_CLKLF: + { + (devConfig->clkLFEnable) ? (retStatus = CY_PRA_STATUS_SUCCESS) : (retStatus = CY_PRA_STATUS_INVALID_PARAM_CLKBAK); + } + break; + default: + { + retStatus = CY_PRA_STATUS_INVALID_PARAM_CLKBAK; + } + break; + } + + if (CY_PRA_STATUS_SUCCESS != retStatus) + { + return retStatus; + } + + /* Validates Output Frequency min="0" max="100000" */ + /* There is no divider for CLK_BAK. So, output frequency = input frequency */ + freq = Cy_PRA_GetClkBakFreq(devConfig); + if (freq > CY_PRA_BAK_OUT_MAX_FREQUENCY) + { + retStatus = CY_PRA_STATUS_INVALID_PARAM_CLKBAK; + } + } + + return retStatus; +} + +/******************************************************************************* +* Function Name: Cy_PRA_ValidateClkFast +****************************************************************************//** +* +* Validate Fast Clock. +* +* \param devConfig System Configuration Parameter +* +* \return +* CY_PRA_STATUS_SUCCESS For the valid input configuration. +* CY_PRA_STATUS_INVALID_PARAM_CLKFAST For the invalid parameter. +* +*******************************************************************************/ +static cy_en_pra_status_t Cy_PRA_ValidateClkFast(const cy_stc_pra_system_config_t *devConfig) +{ + uint32_t freq; + + /* The HF0 source clock must be enabled */ + if (devConfig->clkFastEnable) + { + if (!(devConfig->clkHF0Enable)) + { + return CY_PRA_STATUS_INVALID_PARAM_CLKFAST; + } + + /* Validates the frequency range. min="0" max="400000000" */ + freq = devConfig->hf0OutFreqMHz*CY_PRA_FREQUENCY_HZ_CONVERSION; /* input frequency */ + freq = freq / (devConfig->clkFastDiv+1UL); /* Calculate Output frequency */ + if (freq > CY_PRA_FAST_OUT_MAX_FREQUENCY) + { + return CY_PRA_STATUS_INVALID_PARAM_CLKFAST; + } + + /* Validates divider min="1" max="256". The user must pass actual divider-1 */ + /* No need to validate the divider because the max value input cannot be more than 255 */ + } + + return CY_PRA_STATUS_SUCCESS; +} + +/******************************************************************************* +* Function Name: Cy_PRA_ValidateClkPeri +****************************************************************************//** +* +* Validate Peripheral Clock +* +* \param devConfig System Configuration Parameter +* +* \return +* CY_PRA_STATUS_SUCCESS for valid input configuration +* CY_PRA_STATUS_INVALID_PARAM_CLKPERI for bad parameter +* +*******************************************************************************/ +static cy_en_pra_status_t Cy_PRA_ValidateClkPeri(const cy_stc_pra_system_config_t *devConfig) +{ + uint32_t freq; + + /* The HF0 source clock must be enabled */ + if (devConfig->clkPeriEnable) + { + if (!(devConfig->clkHF0Enable)) + { + return CY_PRA_STATUS_INVALID_PARAM_CLKPERI; + } + + freq = devConfig->hf0OutFreqMHz*CY_PRA_FREQUENCY_HZ_CONVERSION; /* input frequency */ + if (freq > CY_HF_CLK_MAX_FREQ) + { + return CY_PRA_STATUS_INVALID_PARAM_CLKPERI; + } + + freq = freq / (devConfig->clkPeriDiv+1UL); /* Calculate Output frequency */ + + /* Maximum 25 MHz for ULP mode and 100 MHz for LP mode */ + if (devConfig->ulpEnable) + { + if (freq > CY_PRA_ULP_MODE_HF0_MAX_FREQUENCY) + { + return CY_PRA_STATUS_INVALID_PARAM_CLKPERI; + } + } + else + { + if (freq > CY_PRA_LP_MODE_MAX_FREQUENCY) + { + return CY_PRA_STATUS_INVALID_PARAM_CLKPERI; + } + } + + /* Validates divider min="1" max="256". The user must pass actual divider-1 */ + /* No need to validate the divider because the max value input cannot be more than 255 */ + } + else + { + /* Checks if this clock is always on */ + return CY_PRA_STATUS_INVALID_PARAM_CLKPERI; + } + + return CY_PRA_STATUS_SUCCESS; +} + +/******************************************************************************* +* Function Name: Cy_PRA_ValidateClkTimer +****************************************************************************//** +* +* Validates Timer Clock. +* +* \param devConfig System Configuration Parameter +* +* \return +* CY_PRA_STATUS_SUCCESS For the valid input configuration. +* CY_PRA_STATUS_INVALID_PARAM For the invalid parameter. +* +*******************************************************************************/ +static cy_en_pra_status_t Cy_PRA_ValidateClkTimer(const cy_stc_pra_system_config_t *devConfig) +{ + uint32_t freq; + uint8_t srcDiv; + + /* The source clock must be enabled */ + if (devConfig->clkTimerEnable) + { + /* Calculates the source frequency and divider */ + switch (devConfig->clkTimerSource) + { + case CY_SYSCLK_CLKTIMER_IN_IMO: + { + /* IMO is always on */ + freq = CY_PRA_IMO_SRC_FREQUENCY; /* 8 MHz */ + srcDiv = CY_PRA_DIVIDER_1; + } + break; + case CY_SYSCLK_CLKTIMER_IN_HF0_NODIV: + case CY_SYSCLK_CLKTIMER_IN_HF0_DIV2: + case CY_SYSCLK_CLKTIMER_IN_HF0_DIV4: + case CY_SYSCLK_CLKTIMER_IN_HF0_DIV8: + { + if ( devConfig->clkHF0Enable ) + { + srcDiv = CY_PRA_DIVIDER_1; + if (devConfig->clkTimerSource == CY_SYSCLK_CLKTIMER_IN_HF0_DIV2) + { + srcDiv = CY_PRA_DIVIDER_2; + } + if (devConfig->clkTimerSource == CY_SYSCLK_CLKTIMER_IN_HF0_DIV4) + { + srcDiv = CY_PRA_DIVIDER_4; + } + if (devConfig->clkTimerSource == CY_SYSCLK_CLKTIMER_IN_HF0_DIV8) + { + srcDiv = CY_PRA_DIVIDER_8; + } + freq = devConfig->hf0OutFreqMHz*CY_PRA_FREQUENCY_HZ_CONVERSION; + } + else + { + return CY_PRA_STATUS_INVALID_PARAM_CLKTIMER; + } + } + break; + default: + { + return CY_PRA_STATUS_INVALID_PARAM_CLKTIMER; + } + } + + /* Output frequency = source frequency / divider */ + freq = (freq / (devConfig->clkTimerDivider + 1UL)) / srcDiv; + /* Output frequency range min="0" max="400000000" */ + if (freq > CY_PRA_TIMER_OUT_MAX_FREQUENCY) + { + return CY_PRA_STATUS_INVALID_PARAM_CLKTIMER; + } + } + + return CY_PRA_STATUS_SUCCESS; +} + +/******************************************************************************* +* Function Name: Cy_PRA_ValidateClkSlow +****************************************************************************//** +* +* Validates Slow Clock. +* +* \param devConfig System Configuration Parameter +* +* \return +* CY_PRA_STATUS_SUCCESS For the valid input configuration. +* CY_PRA_STATUS_INVALID_PARAM_CLKPERI For the invalid parameter. +* +*******************************************************************************/ +static cy_en_pra_status_t Cy_PRA_ValidateClkSlow(const cy_stc_pra_system_config_t *devConfig) +{ + uint32_t freq; + + /* The source clock must be enabled */ + if (devConfig->clkSlowEnable) + { + if (!(devConfig->clkPeriEnable)) + { + return CY_PRA_STATUS_INVALID_PARAM_CLKSLOW; + } + + /* outFreq = (sourceFreq / divider) range is min="0" max="400000000" */ + freq = devConfig->hf0OutFreqMHz*CY_PRA_FREQUENCY_HZ_CONVERSION; /* input frequency */ + if (freq > CY_HF_CLK_MAX_FREQ) + { + return CY_PRA_STATUS_INVALID_PARAM_CLKPERI; + } + + freq = freq / (devConfig->clkPeriDiv+1UL); /* Calculates the output frequency for PERI and input frequency for SLOW_CLK */ + + freq = freq / (devConfig->clkSlowDiv+1UL); /* Output CLK_SLOW frequency */ + + if (freq > CY_PRA_SLOW_OUT_MAX_FREQUENCY) + { + return CY_PRA_STATUS_INVALID_PARAM_CLKSLOW; + } + } + else + { + /* Checks if this clock is always on */ + return CY_PRA_STATUS_INVALID_PARAM_CLKSLOW; + } + + return CY_PRA_STATUS_SUCCESS; +} + +/******************************************************************************* +* Function Name: Cy_PRA_ValidateSystemConfig +****************************************************************************//** +* +* Validate System Configuration +* +* \param devConfig System Configuration Parameter +* +* \return +* CY_PRA_STATUS_SUCCESS For the valid input configuration. +* CY_PRA_STATUS_INVALID_PARAM Generic failure in validation. +* CY_PRA_STATUS_INVALID_PARAM_ECO Error in ECO validation. +* CY_PRA_STATUS_INVALID_PARAM_EXTCLK Error in EXTCLK validation. +* CY_PRA_STATUS_INVALID_PARAM_ALTHF Error in ALTHF validation. +* CY_PRA_STATUS_INVALID_PARAM_ILO Error in ILO validation. +* CY_PRA_STATUS_INVALID_PARAM_PILO Error in PILO validation. +* CY_PRA_STATUS_INVALID_PARAM_WCO Error in WCO validation. +* CY_PRA_STATUS_INVALID_PARAM_PATHMUX0 Error in PATHMUX0 validation. +* CY_PRA_STATUS_INVALID_PARAM_PATHMUX1 Error in PATHMUX1 validation. +* CY_PRA_STATUS_INVALID_PARAM_PATHMUX2 Error in PATHMUX2 validation. +* CY_PRA_STATUS_INVALID_PARAM_PATHMUX3 Error in PATHMUX3 validation. +* CY_PRA_STATUS_INVALID_PARAM_PATHMUX4 Error in PATHMUX4 validation. +* CY_PRA_STATUS_INVALID_PARAM_PATHMUX5 Error in PATHMUX5 validation. +* CY_PRA_STATUS_INVALID_PARAM_FLL0 Error in FLL validation. +* CY_PRA_STATUS_INVALID_PARAM_PLL0 Error in PLL0 validation. +* CY_PRA_STATUS_INVALID_PARAM_PLL1 Error in PLL1 validation. +* CY_PRA_STATUS_INVALID_PARAM_CLKLF Error in CLKLF validation. +* CY_PRA_STATUS_INVALID_PARAM_CLKHF0 Error in CLKHF0 validation. +* CY_PRA_STATUS_INVALID_PARAM_CLKHF1 Error in CLKHF1 validation. +* CY_PRA_STATUS_INVALID_PARAM_CLKHF2 Error in CLKHF2 validation. +* CY_PRA_STATUS_INVALID_PARAM_CLKHF3 Error in CLKHF3 validation. +* CY_PRA_STATUS_INVALID_PARAM_CLKHF4 Error in CLKHF4 validation. +* CY_PRA_STATUS_INVALID_PARAM_CLKHF5 Error in CLKHF5 validation. +* CY_PRA_STATUS_INVALID_PARAM_CLKPUMP Error in CLKPUMP validation. +* CY_PRA_STATUS_INVALID_PARAM_CLKBAK Error in CLKBAK validation. +* CY_PRA_STATUS_INVALID_PARAM_CLKFAST Error in CLKFAST validation. +* CY_PRA_STATUS_INVALID_PARAM_CLKPERI Error in CLKPERI validation. +* CY_PRA_STATUS_INVALID_PARAM_CLKSLOW Error in CLKSLOW validation. +* CY_PRA_STATUS_INVALID_PARAM_CLKTIMER Error in CLKTIMER validation. +* +*******************************************************************************/ +static cy_en_pra_status_t Cy_PRA_ValidateSystemConfig(const cy_stc_pra_system_config_t *devConfig) +{ + + cy_en_pra_status_t retStatus; + + if (devConfig == NULL ) + { + return CY_PRA_STATUS_INVALID_PARAM; + } + + /* Validates IMO */ + /* Enables IMO for proper chip operation. So, the user option is not given for IMO. + * The output frequency of IMO is fixed to 8MHz. + */ + + /* Validates ECO */ + retStatus = Cy_PRA_ValidateECO(devConfig); + if (CY_PRA_STATUS_SUCCESS != retStatus) + { + return retStatus; + } + + /* Validates EXTCLK */ + retStatus = Cy_PRA_ValidateEXTClk(devConfig); + if (CY_PRA_STATUS_SUCCESS != retStatus) + { + return retStatus; + } + + /* Validates ALTHF (BLE ECO) */ +#if defined(CY_IP_MXBLESS) + retStatus = Cy_PRA_ValidateAltHf(devConfig); + if (CY_PRA_STATUS_SUCCESS != retStatus) + { + return retStatus; + } +#endif + + /* Validates ILO */ + /* ILO frequency fixed to 32KHz */ + + /* Validate PILO */ + /* The PILO frequency is fixed to 32.768KHz */ + + /* Validates WCO */ + /* The WCO frequency is fixed to 32.768KHz */ + + /* Validates Path Mux */ + retStatus = Cy_PRA_ValidateAllClkPathMux(devConfig); + if (CY_PRA_STATUS_SUCCESS != retStatus) + { + return retStatus; + } + + /* Validates FLL */ + /* For ULP mode, Ffll_max = 50 MHz. For LP mode, Ffll_max = 100 MHz or Fcpu_max (if Fcpu_max < 100 MHz) */ + retStatus = Cy_PRA_ValidateFLL(devConfig); + if (CY_PRA_STATUS_SUCCESS != retStatus) + { + return retStatus; + } + + /* Validates PLLs */ + retStatus = Cy_PRA_ValidateAllPLL(devConfig); + if (CY_PRA_STATUS_SUCCESS != retStatus) + { + return retStatus; + } + + /* Validates CLK_LF */ + retStatus = Cy_PRA_ValidateClkLf(devConfig); + if (CY_PRA_STATUS_SUCCESS != retStatus) + { + return retStatus; + } + + /* Validates CLK_HF */ + retStatus = Cy_PRA_ValidateClkHFs(devConfig); + if (CY_PRA_STATUS_SUCCESS != retStatus) + { + return retStatus; + } + + /* Validates CLK_PUMP */ + retStatus = Cy_PRA_ValidateClkPump(devConfig); + if (CY_PRA_STATUS_SUCCESS != retStatus) + { + return retStatus; + } + + /* Validates CLK_BAK */ + retStatus = Cy_PRA_ValidateClkBak(devConfig); + if (CY_PRA_STATUS_SUCCESS != retStatus) + { + return retStatus; + } + + /* Validates CLK_FAST */ + retStatus = Cy_PRA_ValidateClkFast(devConfig); + if (CY_PRA_STATUS_SUCCESS != retStatus) + { + return retStatus; + } + + /* Validate CLK_PERI */ + retStatus = Cy_PRA_ValidateClkPeri(devConfig); + if (CY_PRA_STATUS_SUCCESS != retStatus) + { + return retStatus; + } + + /* Validates CLK_TIMER */ + retStatus = Cy_PRA_ValidateClkTimer(devConfig); + if (CY_PRA_STATUS_SUCCESS != retStatus) + { + return retStatus; + } + + /* Validate CLK_SLOW */ + retStatus = Cy_PRA_ValidateClkSlow(devConfig); + if (CY_PRA_STATUS_SUCCESS != retStatus) + { + return retStatus; + } + + return CY_PRA_STATUS_SUCCESS; +} + + +/******************************************************************************* +* Function Name: Cy_PRA_CalculateFLLOutFreq +****************************************************************************//** +* +* Calculates and returns the FLL output frequency. +* +* \param devConfig System Configuration Parameter +* +* \return +* The FLL output frequency. +* +*******************************************************************************/ +uint32_t Cy_PRA_CalculateFLLOutFreq(const cy_stc_pra_system_config_t *devConfig) +{ + uint32_t srcFreq; + uint32_t outFreq=0UL; + + /* Gets the input source frequency to FLL */ + srcFreq = Cy_PRA_GetInputPathMuxFrq(devConfig->path0Src, devConfig); + if ((srcFreq != CY_PRA_DEFAULT_SRC_FREQUENCY) && (devConfig->fllRefDiv != 0UL)) + { + outFreq = ((srcFreq * devConfig->fllMult) / devConfig->fllRefDiv) / (devConfig->enableOutputDiv ? 2UL : 1UL); + } + + return outFreq; +} + +/******************************************************************************* +* Function Name: Cy_PRA_CalculatePLLOutFreq +****************************************************************************//** +* +* Calculates and returns the PLL output frequency. +* +* \param pll PLL number +* \param devConfig System Configuration Parameter +* +* \return +* The PLL output frequency. +* +*******************************************************************************/ +uint32_t Cy_PRA_CalculatePLLOutFreq(uint8_t pll, const cy_stc_pra_system_config_t *devConfig) +{ + uint32_t srcFreq; + uint32_t outFreq; + uint32_t feedback; + uint32_t reference; + uint32_t pllOutputDiv; + + if ((pll > CY_PRA_DEFAULT_ZERO) && (pll <= CY_SRSS_NUM_PLL)) /* 0 is invalid pll number */ + { + if (pll == CY_PRA_CLKPLL_1) + { + /* Gets the input source frequency to PLL1 */ + srcFreq = Cy_PRA_GetInputPathMuxFrq(devConfig->path1Src, devConfig); + feedback = devConfig->pll0FeedbackDiv; + reference = devConfig->pll0ReferenceDiv; + pllOutputDiv = devConfig->pll0OutputDiv; + } + else if (pll == CY_PRA_CLKPLL_2) + { + /* Gets the input source frequency to PLL2 */ + srcFreq = Cy_PRA_GetInputPathMuxFrq(devConfig->path2Src, devConfig); + feedback = devConfig->pll1FeedbackDiv; + reference = devConfig->pll1ReferenceDiv; + pllOutputDiv = devConfig->pll1OutputDiv; + } + else + { + srcFreq = CY_PRA_DEFAULT_SRC_FREQUENCY; + } + + if ((srcFreq != CY_PRA_DEFAULT_SRC_FREQUENCY) && (reference != CY_PRA_DIVIDER_0) && (pllOutputDiv != CY_PRA_DIVIDER_0)) + { + outFreq = ((srcFreq * feedback) / reference) / pllOutputDiv; + } + else + { + outFreq = CY_PRA_DEFAULT_ZERO; + } + } + else + { + outFreq = CY_PRA_DEFAULT_ZERO; + } + + return outFreq; +} + +#endif /* (CY_CPU_CORTEX_M0P) */ + +/* +* Delay of 4 WCO clock cycles. This delay is used before the WCO is disabled. +* 1 WCO cycle is 30.5 uS. +*/ +#define WCO_DISABLE_DELAY_US (123U) + +/* +* Delay of 4 ILO clock cycles. This delay is used before the ILO is disabled. +* 1 ILO cycle is 40.6 uS. This is a worst case for ILO which is 32 kHz +/- 30%. +*/ +#define ILO_DISABLE_DELAY_US (163U) + +/******************************************************************************* +* Function Name: Cy_PRA_SystemConfig +****************************************************************************//** +* +* Validates \ref cy_stc_pra_system_config_t and applies the provided +* settings. +* +* \param devConfig The device configuration structure initialized with +* Device Configurator. +* +* \return \ref cy_en_pra_status_t +* +* \funcusage +* \snippet pra/snippet/main.c snippet_Cy_PRA_SystemConfig +* +*******************************************************************************/ +cy_en_pra_status_t Cy_PRA_SystemConfig(const cy_stc_pra_system_config_t *devConfig) +{ + cy_en_pra_status_t status; + +#if (CY_CPU_CORTEX_M4) + (void) devConfig; + status = CY_PRA_STATUS_SUCCESS; +#else + + cy_en_sysclk_status_t sysClkStatus; + bool tmp, tmp1, tmp2; + + + /* Validates the input parameters */ + status = Cy_PRA_ValidateSystemConfig(devConfig); + if (CY_PRA_STATUS_SUCCESS != status) + { + return status; + } + + /* Sets the worst case memory wait states (! ultra low power, 150 MHz), update - at the end */ + Cy_SysLib_SetWaitStates(false, CY_PRA_150MHZ_FREQUENCY); + if (devConfig->powerEnable) + { + status = Cy_PRA_PowerInit(devConfig); + if (CY_PRA_STATUS_SUCCESS != status) + { + return status; + } + } + + /* Resets the core clock path to default */ + sysClkStatus = Cy_SysClk_ClkHfSetDivider(CY_PRA_CLKHF_0, CY_SYSCLK_CLKHF_NO_DIVIDE); + if (CY_SYSCLK_SUCCESS != sysClkStatus) + { + return CY_PRA_STATUS_ERROR_PROCESSING_CLKHF0; + } + + + tmp = Cy_SysClk_FllIsEnabled(); + if (CY_SRSS_NUM_PLL >= CY_PRA_CLKPLL_1) + { + tmp1 = Cy_SysClk_PllIsEnabled(CY_PRA_CLKPLL_1); + } + if (CY_SRSS_NUM_PLL >= CY_PRA_CLKPLL_2) + { + tmp2 = Cy_SysClk_PllIsEnabled(CY_PRA_CLKPLL_2); + } + + /* When FLL and PLLs change their states, i.e, ENABLE -> DISABLE + * or DISABLE -> ENABLE then disable all PLLs and FLL */ + if ((tmp != (devConfig->fllEnable)) || + ((CY_SRSS_NUM_PLL >= CY_PRA_CLKPLL_1) && (tmp1 != (devConfig->pll0Enable))) || + ((CY_SRSS_NUM_PLL >= CY_PRA_CLKPLL_2) && (tmp2 != (devConfig->pll1Enable)))) + { + /* Sets the default divider for FAST, PERI and SLOW clocks */ + Cy_SysClk_ClkFastSetDivider(CY_PRA_DIVIDER_0); + Cy_SysClk_ClkPeriSetDivider(CY_PRA_DIVIDER_1); + Cy_SysClk_ClkSlowSetDivider(CY_PRA_DIVIDER_0); + + /* Disables All PLLs */ + if ((CY_SRSS_NUM_PLL >= CY_PRA_CLKPLL_1) && (!devConfig->pll0Enable)) + { + SystemCoreClockUpdate(); + sysClkStatus = Cy_SysClk_PllDisable(CY_PRA_CLKPLL_1); + } + + if (CY_SYSCLK_SUCCESS != sysClkStatus) + { + return CY_PRA_STATUS_ERROR_PROCESSING_PLL0; + } + + if ((CY_SRSS_NUM_PLL >= CY_PRA_CLKPLL_2) && (!devConfig->pll1Enable)) + { + SystemCoreClockUpdate(); + sysClkStatus = Cy_SysClk_PllDisable(CY_PRA_CLKPLL_2); + } + + if (CY_SYSCLK_SUCCESS != sysClkStatus) + { + return CY_PRA_STATUS_ERROR_PROCESSING_PLL1; + } + + /* Sets the CLK_PATH1 source to IMO */ + sysClkStatus = Cy_SysClk_ClkPathSetSource((uint32_t) CY_SYSCLK_CLKHF_IN_CLKPATH1, CY_SYSCLK_CLKPATH_IN_IMO); + if (CY_SYSCLK_SUCCESS != sysClkStatus) + { + return CY_PRA_STATUS_ERROR_PROCESSING_PATHMUX1; + } + + /* Set the HF0 source to IMO if it is sourced from WCO */ + if (CY_SYSCLK_CLKHF_IN_CLKPATH0 == Cy_SysClk_ClkHfGetSource(CY_PRA_CLKHF_0)) + { + if (CY_SYSCLK_CLKPATH_IN_WCO == Cy_SysClk_ClkPathGetSource((uint32_t) CY_SYSCLK_CLKHF_IN_CLKPATH0)) + { + sysClkStatus = Cy_SysClk_ClkHfSetSource(CY_PRA_CLKHF_0, CY_SYSCLK_CLKHF_IN_CLKPATH1); + if (CY_SYSCLK_SUCCESS != sysClkStatus) + { + return CY_PRA_STATUS_ERROR_PROCESSING_CLKHF0; + } + } + } + + /* Disables FLL when its state changes ENABLE -> DISABLE */ + if (!devConfig->fllEnable) + { + sysClkStatus = Cy_SysClk_FllDisable(); + } + if (CY_SYSCLK_SUCCESS != sysClkStatus) + { + return CY_PRA_STATUS_ERROR_PROCESSING_FLL0; + } + + /* Sets the CLK_PATH0 source to IMO */ + sysClkStatus = Cy_SysClk_ClkPathSetSource((uint32_t) CY_SYSCLK_CLKHF_IN_CLKPATH0, CY_SYSCLK_CLKPATH_IN_IMO); + if (CY_SYSCLK_SUCCESS != sysClkStatus) + { + return CY_PRA_STATUS_ERROR_PROCESSING_PATHMUX0; + } + + /* Sets the HF0 source to IMO via CLK_PATH0 */ + sysClkStatus = Cy_SysClk_ClkHfSetSource(CY_PRA_CLKHF_0, CY_SYSCLK_CLKHF_IN_CLKPATH0); + if (CY_SYSCLK_SUCCESS != sysClkStatus) + { + return CY_PRA_STATUS_ERROR_PROCESSING_CLKHF0; + } + } + +#ifdef CY_IP_MXBLESS + /* BLE_ECO reset */ + Cy_PRA_AltHfReset(devConfig); +#endif + + if(CY_SRSS_PILO_PRESENT) + { + /* Enables all source clocks */ + if (devConfig->piloEnable) + { + SystemCoreClockUpdate(); + Cy_PRA_PiloInit(); + } + else + { + Cy_SysClk_PiloDisable(); + } + } + + if (devConfig->wcoEnable) + { + SystemCoreClockUpdate(); + status = Cy_PRA_WcoInit(devConfig); + if (CY_PRA_STATUS_SUCCESS != status) + { + return status; + } + } + else + { + if (_FLD2BOOL(BACKUP_CTL_WCO_EN, BACKUP_CTL)) + { + /* Wait 4 WCO cycles before it is disabled */ + Cy_SysLib_DelayUs(WCO_DISABLE_DELAY_US); + Cy_SysClk_WcoDisable(); + } + } + + if (devConfig->clkLFEnable) + { + status = Cy_PRA_ClkLfInit(devConfig->clkLfSource); + if (CY_PRA_STATUS_SUCCESS != status) + { + return status; + } + } +#if defined(CY_IP_MXBLESS) + if (devConfig->clkAltHfEnable) + { + SystemCoreClockUpdate(); + status = Cy_PRA_AltHfInit(devConfig); + if (CY_PRA_STATUS_SUCCESS != status) + { + return status; + } + } +#endif /* CY_IP_MXBLESS */ + tmp = (CY_SYSCLK_ECOSTAT_STABLE == Cy_SysClk_EcoGetStatus()); + if (tmp != (devConfig->ecoEnable)) + { + if (devConfig->ecoEnable) + { + SystemCoreClockUpdate(); + status = Cy_PRA_EcoInit(devConfig); + if (CY_PRA_STATUS_SUCCESS != status) + { + return status; + } + } + else + { + Cy_SysClk_EcoDisable(); + } + } + + if (devConfig->extClkEnable) + { + Cy_PRA_ExtClkInit(devConfig); + } + + if (devConfig->clkFastEnable) + { + Cy_SysClk_ClkFastSetDivider(devConfig->clkFastDiv); + } + + if (devConfig->clkPeriEnable) + { + Cy_SysClk_ClkPeriSetDivider(devConfig->clkPeriDiv); + } + + if (devConfig->clkSlowEnable) + { + Cy_SysClk_ClkSlowSetDivider(devConfig->clkSlowDiv); + } + + if ((devConfig->path0Src == CY_SYSCLK_CLKPATH_IN_WCO) && + (devConfig->hf0Source == CY_SYSCLK_CLKHF_IN_CLKPATH0)) + { + /* Configure HFCLK0 to temporarily run from IMO to initialize other clocks */ + sysClkStatus = Cy_SysClk_ClkPathSetSource(CY_PRA_CLKPATH_1, CY_SYSCLK_CLKPATH_IN_IMO); + if (CY_SYSCLK_SUCCESS != sysClkStatus) + { + return CY_PRA_STATUS_ERROR_PROCESSING_PATHMUX1; + } + sysClkStatus = Cy_SysClk_ClkHfSetSource(CY_PRA_CLKHF_0, CY_SYSCLK_CLKHF_IN_CLKPATH1); + if (CY_SYSCLK_SUCCESS != sysClkStatus) + { + return CY_PRA_STATUS_ERROR_PROCESSING_CLKHF0; + } + } + else + { + sysClkStatus = Cy_SysClk_ClkPathSetSource(CY_PRA_CLKPATH_1, devConfig->path1Src); + if (CY_SYSCLK_SUCCESS != sysClkStatus) + { + return CY_PRA_STATUS_ERROR_PROCESSING_PATHMUX1; + } + } + + /* Configures Path Clocks */ + + if (devConfig->path0Enable) + { + sysClkStatus = Cy_SysClk_ClkPathSetSource(CY_PRA_CLKPATH_0, devConfig->path0Src); + if (CY_SYSCLK_SUCCESS != sysClkStatus) + { + return CY_PRA_STATUS_ERROR_PROCESSING_PATHMUX0; + } + } + + if (devConfig->path2Enable) + { + sysClkStatus = Cy_SysClk_ClkPathSetSource(CY_PRA_CLKPATH_2, devConfig->path2Src); + if (CY_SYSCLK_SUCCESS != sysClkStatus) + { + return CY_PRA_STATUS_ERROR_PROCESSING_PATHMUX2; + } + } + + if ((devConfig->path3Enable) && (CY_PRA_CLKPATH_3 < CY_SRSS_NUM_CLKPATH)) + { + sysClkStatus = Cy_SysClk_ClkPathSetSource(CY_PRA_CLKPATH_3, devConfig->path3Src); + if (CY_SYSCLK_SUCCESS != sysClkStatus) + { + return CY_PRA_STATUS_ERROR_PROCESSING_PATHMUX3; + } + } + + if ((devConfig->path4Enable) && (CY_PRA_CLKPATH_4 < CY_SRSS_NUM_CLKPATH)) + { + sysClkStatus = Cy_SysClk_ClkPathSetSource(CY_PRA_CLKPATH_4, devConfig->path4Src); + if (CY_SYSCLK_SUCCESS != sysClkStatus) + { + return CY_PRA_STATUS_ERROR_PROCESSING_PATHMUX4; + } + } + + if ((devConfig->path5Enable) && (CY_PRA_CLKPATH_5 < CY_SRSS_NUM_CLKPATH)) + { + sysClkStatus = Cy_SysClk_ClkPathSetSource(CY_PRA_CLKPATH_5, devConfig->path5Src); + if (CY_SYSCLK_SUCCESS != sysClkStatus) + { + return CY_PRA_STATUS_ERROR_PROCESSING_PATHMUX5; + } + } + + /* When the FLL state changes DISABLE -> ENABLE, enable only FLL. + * Ignore, if FLL is already enabled */ + if ((!Cy_SysClk_FllIsEnabled()) && (devConfig->fllEnable)) + { + SystemCoreClockUpdate(); + status = Cy_PRA_FllInit(devConfig); + if (CY_PRA_STATUS_SUCCESS != status) + { + return status; + } + } + + /* CLK_HF0 Init */ + sysClkStatus = Cy_SysClk_ClkHfSetSource(CY_PRA_CLKHF_0, devConfig->hf0Source); + if (CY_SYSCLK_SUCCESS != sysClkStatus) + { + return CY_PRA_STATUS_ERROR_PROCESSING_CLKHF0; + } + sysClkStatus = Cy_SysClk_ClkHfSetDivider(CY_PRA_CLKHF_0, devConfig->hf0Divider); + if (CY_SYSCLK_SUCCESS != sysClkStatus) + { + return CY_PRA_STATUS_ERROR_PROCESSING_CLKHF0; + } + + if ((devConfig->path0Src == CY_SYSCLK_CLKPATH_IN_WCO) && (devConfig->hf0Source == CY_SYSCLK_CLKHF_IN_CLKPATH0)) + { + if (devConfig->path1Enable) + { + sysClkStatus = Cy_SysClk_ClkPathSetSource(CY_PRA_CLKPATH_1, devConfig->path1Src); + if (CY_SYSCLK_SUCCESS != sysClkStatus) + { + return CY_PRA_STATUS_ERROR_PROCESSING_PATHMUX1; + } + } + else + { + return CY_PRA_STATUS_ERROR_PROCESSING_PATHMUX1; + } + + } + + /* When the PLL1 state changes DISABLE -> ENABLE, enable only PLL. + * Ignore, if PLL1 is already enabled */ + if ((CY_SRSS_NUM_PLL >= CY_PRA_CLKPLL_1) && (devConfig->pll0Enable)) + { + if (!Cy_SysClk_PllIsEnabled(CY_PRA_CLKPLL_1)) + { + const cy_stc_pll_manual_config_t pll0Config = + { + .feedbackDiv = devConfig->pll0FeedbackDiv, + .referenceDiv = devConfig->pll0ReferenceDiv, + .outputDiv = devConfig->pll0OutputDiv, + .lfMode = devConfig->pll0LfMode, + .outputMode = devConfig->pll0OutputMode, + }; + + SystemCoreClockUpdate(); + status = Cy_PRA_PllInit(CY_PRA_CLKPLL_1, &pll0Config); + if (CY_PRA_STATUS_SUCCESS != status) + { + return CY_PRA_STATUS_ERROR_PROCESSING_PLL0; + } + } + } + + /* When the PLL2 state changes DISABLE -> ENABLE, enable only PLL. + * Ignore, if PLL2 is already enabled */ + if((CY_SRSS_NUM_PLL >= CY_PRA_CLKPLL_2) && (devConfig->pll1Enable)) + { + if (!Cy_SysClk_PllIsEnabled(CY_PRA_CLKPLL_2)) + { + const cy_stc_pll_manual_config_t pll1Config = + { + .feedbackDiv = devConfig->pll1FeedbackDiv, + .referenceDiv = devConfig->pll1ReferenceDiv, + .outputDiv = devConfig->pll1OutputDiv, + .lfMode = devConfig->pll1LfMode, + .outputMode = devConfig->pll1OutputMode, + }; + + SystemCoreClockUpdate(); + status = Cy_PRA_PllInit(CY_PRA_CLKPLL_2, &pll1Config); + if (CY_PRA_STATUS_SUCCESS != status) + { + return CY_PRA_STATUS_ERROR_PROCESSING_PLL1; + } + } + } + + /* Configures the HF clocks */ + if (devConfig->clkHF1Enable) + { + status = Cy_PRA_ClkHfInit(CY_PRA_CLKHF_1, devConfig->hf1Source, devConfig->hf1Divider); + if (CY_PRA_STATUS_SUCCESS != status) + { + return CY_PRA_STATUS_INVALID_PARAM_CLKHF1; + } + } + else + { + status = (cy_en_pra_status_t)Cy_SysClk_ClkHfDisable(CY_PRA_CLKHF_1); + if (CY_PRA_STATUS_SUCCESS != status) + { + return CY_PRA_STATUS_INVALID_PARAM_CLKHF1; + } + } + if (devConfig->clkHF2Enable) + { + status = Cy_PRA_ClkHfInit(CY_PRA_CLKHF_2, devConfig->hf2Source, devConfig->hf2Divider); + if (CY_PRA_STATUS_SUCCESS != status) + { + return CY_PRA_STATUS_INVALID_PARAM_CLKHF2; + } + } + else + { + status = (cy_en_pra_status_t)Cy_SysClk_ClkHfDisable(CY_PRA_CLKHF_2); + if (CY_PRA_STATUS_SUCCESS != status) + { + return CY_PRA_STATUS_INVALID_PARAM_CLKHF2; + } + + } + if ((devConfig->clkHF3Enable) && (CY_PRA_CLKHF_3 < CY_SRSS_NUM_HFROOT)) + { + status = Cy_PRA_ClkHfInit(CY_PRA_CLKHF_3, devConfig->hf3Source, devConfig->hf3Divider); + if (CY_PRA_STATUS_SUCCESS != status) + { + return CY_PRA_STATUS_INVALID_PARAM_CLKHF3; + } + } + else + { + if (CY_PRA_CLKHF_3 < CY_SRSS_NUM_HFROOT) + { + status = (cy_en_pra_status_t)Cy_SysClk_ClkHfDisable(CY_PRA_CLKHF_3); + if (CY_PRA_STATUS_SUCCESS != status) + { + return CY_PRA_STATUS_INVALID_PARAM_CLKHF3; + } + } + + } + if ((devConfig->clkHF4Enable) && (CY_PRA_CLKHF_4 < CY_SRSS_NUM_HFROOT)) + { + status = Cy_PRA_ClkHfInit(CY_PRA_CLKHF_4, devConfig->hf4Source, devConfig->hf4Divider); + if (CY_PRA_STATUS_SUCCESS != status) + { + return CY_PRA_STATUS_INVALID_PARAM_CLKHF4; + } + } + else + { + if(CY_PRA_CLKHF_4 < CY_SRSS_NUM_HFROOT) + { + status = (cy_en_pra_status_t)Cy_SysClk_ClkHfDisable(CY_PRA_CLKHF_4); + if (CY_PRA_STATUS_SUCCESS != status) + { + return CY_PRA_STATUS_INVALID_PARAM_CLKHF4; + } + } + } + if ((devConfig->clkHF5Enable) && (CY_PRA_CLKHF_5 < CY_SRSS_NUM_HFROOT)) + { + status = Cy_PRA_ClkHfInit(CY_PRA_CLKHF_5, devConfig->hf5Source, devConfig->hf5Divider); + if (CY_PRA_STATUS_SUCCESS != status) + { + return CY_PRA_STATUS_INVALID_PARAM_CLKHF5; + } + } + else + { + if(CY_PRA_CLKHF_5 < CY_SRSS_NUM_HFROOT) + { + status = (cy_en_pra_status_t)Cy_SysClk_ClkHfDisable(CY_PRA_CLKHF_5); + if (CY_PRA_STATUS_SUCCESS != status) + { + return CY_PRA_STATUS_INVALID_PARAM_CLKHF5; + } + } + } + /* Configures miscellaneous clocks */ + if (devConfig->clkTimerEnable) + { + Cy_PRA_ClkTimerInit(devConfig->clkTimerSource, devConfig->clkTimerDivider); + } + else + { + Cy_SysClk_ClkTimerDisable(); + } + + if (devConfig->clkPumpEnable) + { + Cy_PRA_ClkPumpInit(devConfig->pumpSource, devConfig->pumpDivider); + } + else + { + Cy_SysClk_ClkPumpDisable(); + } + + if (devConfig->clkBakEnable) + { + Cy_SysClk_ClkBakSetSource(devConfig->clkBakSource); + } + + status = Cy_PRA_IloHibernateOn(devConfig->iloHibernateON); + if (CY_PRA_STATUS_SUCCESS != status) + { + return status; + } + + /* Configures the default-enabled clocks */ + if (devConfig->iloEnable) + { + status = Cy_PRA_IloEnable(); + if (CY_PRA_STATUS_SUCCESS != status) + { + return status; + } + } + else + { + if (Cy_SysClk_IloIsEnabled()) + { + /* Wait 4 ILO cycles before it is disabled */ + Cy_SysLib_DelayUs(ILO_DISABLE_DELAY_US); + + status = Cy_PRA_IloDisable(); + if (CY_PRA_STATUS_SUCCESS != status) + { + return status; + } + } + } + + /* SYSCLK MFO INIT */ + /* SYSCLK MF INIT */ + + /* Sets accurate flash wait states */ + if ((devConfig->powerEnable) && (devConfig->clkHF0Enable)) + { + Cy_SysLib_SetWaitStates(devConfig->ulpEnable, devConfig->hf0OutFreqMHz); + } + + /* Updates the System Core Clock values for the correct Cy_SysLib_Delay functioning. + * This function is called before every PDL function where the Cy_SysLib_Delay + * function is used. + */ + SystemCoreClockUpdate(); + +#endif /* (CY_CPU_CORTEX_M4) */ + + return (status); +} + + +#if (CY_CPU_CORTEX_M0P) || defined (CY_DOXYGEN) + + #if !defined(CY_DEVICE_PSOC6ABLE2) + #define CY_PRA_ALL_PC_MASK (CY_PROT_PCMASK1 + CY_PROT_PCMASK2 + \ + CY_PROT_PCMASK3 + CY_PROT_PCMASK4 + \ + CY_PROT_PCMASK5 + CY_PROT_PCMASK6 + \ + CY_PROT_PCMASK7) + + #define CY_PRA_SECURE_PC_MASK (CY_PROT_PCMASK1 + CY_PROT_PCMASK2 + \ + CY_PROT_PCMASK3 + CY_PROT_PCMASK4) + #endif /* !defined(CY_DEVICE_PSOC6ABLE2) */ + + +/******************************************************************************* +* Function Name: Cy_PRA_CloseSrssMain2 +****************************************************************************//** +* +* Restricts the access to the SRSS_MAIN2 region, which includes the following +* registers: SRSS_TST_DDFT_FAST_CTL_REG, SRSS_TST_DDFT_FAST_CTL_REG. +* +*******************************************************************************/ +void Cy_PRA_CloseSrssMain2(void) +{ + #if defined(CY_DEVICE_PSOC6ABLE2) + /* Will be implemented for the BLE device per DRIVERS-3084 */ + #else + (void) Cy_Prot_ConfigPpuFixedSlaveAtt(PERI_MS_PPU_FX_SRSS_MAIN2, + (uint16_t) CY_PRA_SECURE_PC_MASK, + CY_PROT_PERM_RW, + CY_PROT_PERM_RW, + false); + + (void) Cy_Prot_ConfigPpuFixedSlaveAtt(PERI_MS_PPU_FX_SRSS_MAIN2, + (uint16_t) (CY_PRA_ALL_PC_MASK ^ CY_PRA_SECURE_PC_MASK), + CY_PROT_PERM_DISABLED, + CY_PROT_PERM_DISABLED, + false); + #endif /* defined(CY_DEVICE_PSOC6ABLE2) */ +} + + +/******************************************************************************* +* Function Name: Cy_PRA_OpenSrssMain2 +****************************************************************************//** +* +* Restores the access to the SRSS_MAIN2 region, which was restricted by +* Cy_PRA_CloseSrssMain2. +* +*******************************************************************************/ +void Cy_PRA_OpenSrssMain2(void) +{ + #if defined(CY_DEVICE_PSOC6ABLE2) + /* Will be implemented for the BLE device per DRIVERS-3084 */ + #else + (void) Cy_Prot_ConfigPpuFixedSlaveAtt(PERI_MS_PPU_FX_SRSS_MAIN2, + (uint16_t) CY_PRA_ALL_PC_MASK, + CY_PROT_PERM_RW, + CY_PROT_PERM_RW, + false); + #endif /* defined(CY_DEVICE_PSOC6ABLE2) */ +} + +#endif /* (CY_CPU_CORTEX_M0P) */ + + +#endif /* (CY_DEVICE_SECURE) */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_profile.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_profile.c index d78de380aa..6612da0e24 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_profile.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_profile.c @@ -1,12 +1,12 @@ -/***************************************************************************//** +/***************************************************************************//** * \file cy_profile.c -* \version 1.20 -* -* Provides an API declaration of the energy profiler (EP) driver. +* \version 1.20.1 * -******************************************************************************** -* \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Provides an API declaration of the energy profiler (EP) driver. +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -51,7 +51,7 @@ static cy_stc_profile_ctr_t cy_ep_ctrs[CY_EP_CNT_NR]; * the cy_ep_ctrs[] array, and (2) whether the counter has been assigned. * * \param ctrAddr The handle to (address of) the assigned counter -* +* * \return CY_PROFILE_SUCCESS, or CY_PROFILE_BAD_PARAM for invalid ctrAddr or counter not * in use. * @@ -83,12 +83,12 @@ static cy_en_profile_status_t Cy_Profile_IsPtrValid(const cy_stc_profile_ctr_ptr * EP interrupt handler: Increments the overflow member of the counter structure, * for each counter that is in use and has an overflow. * -* This handler is not configured or used automatically. You must configure the -* interrupt handler for the EP, using Cy_SysInt_Init(). Typically you configure +* This handler is not configured or used automatically. You must configure the +* interrupt handler for the EP, using Cy_SysInt_Init(). Typically you configure * the system to use \ref Cy_Profile_ISR() as the overflow interrupt handler. You * can provide a custom interrupt handler to perform additional operations if * required. Your handler can call \ref Cy_Profile_ISR() to handle counter -* overflow. +* overflow. * *******************************************************************************/ void Cy_Profile_ISR(void) @@ -151,7 +151,7 @@ void Cy_Profile_StartProfiling(void) * Function Name: Cy_Profile_ClearConfiguration ****************************************************************************//** * -* Clears all counter configurations and sets all counters and overflow counters +* Clears all counter configurations and sets all counters and overflow counters * to 0. Calls Cy_Profile_ClearCounters() to clear counter registers. * * \funcusage @@ -171,12 +171,12 @@ void Cy_Profile_ClearConfiguration(void) * * Configures and assigns a hardware profile counter to the list of used counters. * -* This function assigns an available profile counter to a slot in the internal +* This function assigns an available profile counter to a slot in the internal * software data structure and returns the handle for that slot location. The data * structure is used to keep track of the counter status and to implement a 64-bit * profile counter. If no counter slots are available, the function returns a * NULL pointer. -* +* * \param monitor The monitor source number * * \param duration Events are monitored (0), or duration is monitored (1) @@ -184,7 +184,7 @@ void Cy_Profile_ClearConfiguration(void) * \param refClk Counter reference clock * * \param weight Weighting factor for the counter value -* +* * \return A pointer to the counter data structure. NULL if no counter is * available. * @@ -198,10 +198,10 @@ cy_stc_profile_ctr_ptr_t Cy_Profile_ConfigureCounter(en_ep_mon_sel_t monitor, cy CY_ASSERT_L1(CY_PROFILE_IS_MONITOR_VALID(monitor)); CY_ASSERT_L3(CY_PROFILE_IS_DURATION_VALID(duration)); CY_ASSERT_L3(CY_PROFILE_IS_REFCLK_VALID(refClk)); - + cy_stc_profile_ctr_ptr_t retVal = NULL; /* error value if no counter is available */ volatile uint8_t i; - + /* Scan through the counters for an unused one */ for (i = 0u; (cy_ep_ctrs[i].used != 0u) && (i < (CY_N_ELMTS(cy_ep_ctrs))); i++){} if (i < CY_N_ELMTS(cy_ep_ctrs)) @@ -216,7 +216,7 @@ cy_stc_profile_ctr_ptr_t Cy_Profile_ConfigureCounter(en_ep_mon_sel_t monitor, cy cy_ep_ctrs[i].weight = weight; /* Pass back the handle to (address of) the counter data structure */ retVal = &cy_ep_ctrs[i]; - + /* Load the CTL register bitfields of the assigned counter. */ retVal->cntAddr->CTL = _VAL2FLD(PROFILE_CNT_STRUCT_CTL_CNT_DURATION, retVal->ctlRegVals.cntDuration) | @@ -239,8 +239,8 @@ cy_stc_profile_ctr_ptr_t Cy_Profile_ConfigureCounter(en_ep_mon_sel_t monitor, cy * * \param ctrAddr The handle to the assigned counter (returned by calling * \ref Cy_Profile_ConfigureCounter()). -* -* \return +* +* \return * Status of the operation. * * \note The counter is not disabled by this function. @@ -252,7 +252,7 @@ cy_stc_profile_ctr_ptr_t Cy_Profile_ConfigureCounter(en_ep_mon_sel_t monitor, cy cy_en_profile_status_t Cy_Profile_FreeCounter(cy_stc_profile_ctr_ptr_t ctrAddr) { cy_en_profile_status_t retStatus = CY_PROFILE_BAD_PARAM; - + retStatus = Cy_Profile_IsPtrValid(ctrAddr); if (retStatus == CY_PROFILE_SUCCESS) { @@ -266,15 +266,15 @@ cy_en_profile_status_t Cy_Profile_FreeCounter(cy_stc_profile_ctr_ptr_t ctrAddr) * Function Name: Cy_Profile_EnableCounter ****************************************************************************//** * -* Enables an assigned counter. +* Enables an assigned counter. * * \ref Cy_Profile_ConfigureCounter() must have been called for this counter * before calling this function. * * \param ctrAddr The handle to the assigned counter, (returned by calling * \ref Cy_Profile_ConfigureCounter()). -* -* \return +* +* \return * Status of the operation. * * \funcusage @@ -284,7 +284,7 @@ cy_en_profile_status_t Cy_Profile_FreeCounter(cy_stc_profile_ctr_ptr_t ctrAddr) cy_en_profile_status_t Cy_Profile_EnableCounter(cy_stc_profile_ctr_ptr_t ctrAddr) { cy_en_profile_status_t retStatus = Cy_Profile_IsPtrValid(ctrAddr); - + if (CY_PROFILE_SUCCESS == retStatus) { /* set the ENABLED bit */ @@ -292,7 +292,7 @@ cy_en_profile_status_t Cy_Profile_EnableCounter(cy_stc_profile_ctr_ptr_t ctrAddr /* set the INTR_MASK bit for the counter being used */ PROFILE_INTR_MASK |= (1UL << (ctrAddr->ctrNum)); } - + return (retStatus); } @@ -308,8 +308,8 @@ cy_en_profile_status_t Cy_Profile_EnableCounter(cy_stc_profile_ctr_ptr_t ctrAddr * * \param ctrAddr The handle to the assigned counter, (returned by calling * \ref Cy_Profile_ConfigureCounter()). -* -* \return +* +* \return * Status of the operation. * * \funcusage @@ -319,7 +319,7 @@ cy_en_profile_status_t Cy_Profile_EnableCounter(cy_stc_profile_ctr_ptr_t ctrAddr cy_en_profile_status_t Cy_Profile_DisableCounter(cy_stc_profile_ctr_ptr_t ctrAddr) { cy_en_profile_status_t retStatus = Cy_Profile_IsPtrValid(ctrAddr); - + if (CY_PROFILE_SUCCESS == retStatus) { /* clear the ENABLED bit */ @@ -327,7 +327,7 @@ cy_en_profile_status_t Cy_Profile_DisableCounter(cy_stc_profile_ctr_ptr_t ctrAdd /* clear the INTR_MASK bit for the counter being used */ PROFILE_INTR_MASK &= ~(1UL << (ctrAddr->ctrNum)); } - + return (retStatus); } @@ -345,8 +345,8 @@ cy_en_profile_status_t Cy_Profile_DisableCounter(cy_stc_profile_ctr_ptr_t ctrAdd * \ref Cy_Profile_ConfigureCounter()). * * \param result Output parameter used to write in the result. -* -* \return +* +* \return * Status of the operation. * * \funcusage @@ -356,7 +356,7 @@ cy_en_profile_status_t Cy_Profile_DisableCounter(cy_stc_profile_ctr_ptr_t ctrAdd cy_en_profile_status_t Cy_Profile_GetRawCount(cy_stc_profile_ctr_ptr_t ctrAddr, uint64_t *result) { cy_en_profile_status_t retStatus = Cy_Profile_IsPtrValid(ctrAddr); - + if ((result != NULL) && (CY_PROFILE_SUCCESS == retStatus)) { /* read the counter control register, and the counter current value */ @@ -366,7 +366,7 @@ cy_en_profile_status_t Cy_Profile_GetRawCount(cy_stc_profile_ctr_ptr_t ctrAddr, /* report the count with overflow */ *result = ((uint64_t)(ctrAddr->overflow) << 32) | (uint64_t)(ctrAddr->cntReg); } - + return (retStatus); } @@ -381,8 +381,8 @@ cy_en_profile_status_t Cy_Profile_GetRawCount(cy_stc_profile_ctr_ptr_t ctrAddr, * \ref Cy_Profile_ConfigureCounter()). * * \param result Output parameter used to write in the result. -* -* \return +* +* \return * Status of the operation. * * \funcusage @@ -393,13 +393,13 @@ cy_en_profile_status_t Cy_Profile_GetWeightedCount(cy_stc_profile_ctr_ptr_t ctrA { uint64_t temp; cy_en_profile_status_t retStatus = Cy_Profile_GetRawCount(ctrAddr, &temp); - + if ((result != NULL) && (CY_PROFILE_SUCCESS == retStatus)) { /* calculate weighted count */ *result = temp * (uint64_t)(ctrAddr->weight); } - + return (retStatus); } @@ -428,9 +428,9 @@ uint64_t Cy_Profile_GetSumWeightedCounts(cy_stc_profile_ctr_ptr_t ptrsArray[], uint32_t numCounters) { uint64_t daSum = (uint64_t)0UL; - + CY_ASSERT_L2(CY_PROFILE_IS_CNT_VALID(numCounters)); - + if(ptrsArray != NULL) { uint64_t num; @@ -445,7 +445,7 @@ uint64_t Cy_Profile_GetSumWeightedCounts(cy_stc_profile_ctr_ptr_t ptrsArray[], } } } - + return (daSum); } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_prot.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_prot.c index 6ea05a012a..a4b0ab6bb8 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_prot.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_prot.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_prot.c -* \version 1.30.2 +* \version 1.30.3 * * \brief * Provides an API implementation of the Protection Unit driver @@ -31,7 +31,7 @@ extern "C" { static bool Prot_IsSmpuStructDisabled(uint32_t smpuStcIndex); static bool Prot_IsPpuProgStructDisabled(uint32_t ppuStcIndex); -static cy_en_prot_status_t Prot_ConfigPpuAtt(volatile uint32_t * reg, uint16_t pcMask, +static cy_en_prot_status_t Prot_ConfigPpuAtt(volatile uint32_t * reg, uint16_t pcMask, cy_en_prot_perm_t userPermission, cy_en_prot_perm_t privPermission, bool secure); /* Define to enable all attributes for SMPU slave structure */ @@ -66,21 +66,21 @@ static cy_en_prot_status_t Prot_ConfigPpuAtt(volatile uint32_t * reg, uint16_t p * \param busMaster * Indicates which master needs to be configured. Refer to the CPUSS_MS_ID_X * defines in the device config header file. -* +* * \param privileged * Boolean to define the privilege level of all subsequent bus transfers. * True - privileged, False - not privileged. -* Note that this is an inherited value. If not inherited, then this bit will +* Note that this is an inherited value. If not inherited, then this bit will * be used. * * \param secure * Security setting for the master. True - Secure, False - Not secure. -* +* * \param pcMask * This is a 16 bit value of the allowed contexts, it is an OR'ed (|) field of the * provided defines in cy_prot.h. For example: (CY_PROT_PCMASK1 | CY_PROT_PCMASK3 | CY_PROT_PCMASK4) -* \note The function accepts pcMask values from CY_PROT_PCMASK1 to CY_PROT_PCMASK15. -* But each device has its own number of available protection contexts. +* \note The function accepts pcMask values from CY_PROT_PCMASK1 to CY_PROT_PCMASK15. +* But each device has its own number of available protection contexts. * That number is defined by PERI_PC_NR in the config file. * * \return @@ -99,13 +99,13 @@ cy_en_prot_status_t Cy_Prot_ConfigBusMaster(en_prot_master_t busMaster, bool pri { cy_en_prot_status_t status = CY_PROT_SUCCESS; uint32_t regVal; - volatile uint32_t *addrMsCtl; /* addrMsCtl is pointer to a register that is volatile by - * nature as can be changed outside of firmware control. + volatile uint32_t *addrMsCtl; /* addrMsCtl is pointer to a register that is volatile by + * nature as can be changed outside of firmware control. */ CY_ASSERT_L1(CY_PROT_IS_BUS_MASTER_VALID(busMaster)); CY_ASSERT_L2(CY_PROT_IS_PC_MASK_VALID(pcMask)); - + /* Get the address of Master x protection context control register (MSx_CTL) */ addrMsCtl = (uint32_t *)(CY_PROT_BASE + (uint32_t)((uint32_t)busMaster << CY_PROT_MSX_CTL_SHIFT)); @@ -113,15 +113,15 @@ cy_en_prot_status_t Cy_Prot_ConfigBusMaster(en_prot_master_t busMaster, bool pri regVal = _VAL2FLD(PROT_SMPU_MS0_CTL_NS, !secure) /* Security setting */ | _VAL2FLD(PROT_SMPU_MS0_CTL_P, privileged) /* Privileged setting */ | _VAL2FLD(PROT_SMPU_MS0_CTL_PC_MASK_15_TO_1, pcMask); /* Protection context mask */ - + /* Set the value of MSx_CTL */ *addrMsCtl = regVal; - /* Check if the MSx_CTL register is successfully updated with the new register value. - * The register will not be updated for the invalid master-protection context. - */ + /* Check if the MSx_CTL register is successfully updated with the new register value. + * The register will not be updated for the invalid master-protection context. + */ status = (*addrMsCtl != regVal) ? CY_PROT_FAILURE : CY_PROT_SUCCESS; - + return status; } @@ -131,8 +131,8 @@ cy_en_prot_status_t Cy_Prot_ConfigBusMaster(en_prot_master_t busMaster, bool pri ****************************************************************************//** * * Sets the current/active protection context of the specified bus master. -* -* Allowed PC values are 1-15. If this value is not inherited from another bus +* +* Allowed PC values are 1-15. If this value is not inherited from another bus * master, the value set through this function is used. * * \note This function is applicable for both CPUSS ver_1 and ver_2. @@ -140,13 +140,13 @@ cy_en_prot_status_t Cy_Prot_ConfigBusMaster(en_prot_master_t busMaster, bool pri * \param busMaster * The bus master to configure. Refer to the CPUSS_MS_ID_X defines in the device * config header file. -* +* * \param pc -* Active protection context of the specified master \ref cy_en_prot_pc_t. -* \note that only those protection contexts allowed by the pcMask (which was -* configured in \ref Cy_Prot_ConfigBusMaster) will take effect. -* \note The function accepts pcMask values from CY_PROT_PC1 to CY_PROT_PC15. -* But each device has its own number of available protection contexts. +* Active protection context of the specified master \ref cy_en_prot_pc_t. +* \note that only those protection contexts allowed by the pcMask (which was +* configured in \ref Cy_Prot_ConfigBusMaster) will take effect. +* \note The function accepts pcMask values from CY_PROT_PC1 to CY_PROT_PC15. +* But each device has its own number of available protection contexts. * That number is defined by PERI_PC_NR in the config file. * * \return @@ -164,13 +164,13 @@ cy_en_prot_status_t Cy_Prot_ConfigBusMaster(en_prot_master_t busMaster, bool pri cy_en_prot_status_t Cy_Prot_SetActivePC(en_prot_master_t busMaster, uint32_t pc) { cy_en_prot_status_t status; - + CY_ASSERT_L1(CY_PROT_IS_BUS_MASTER_VALID(busMaster)); CY_ASSERT_L2(CY_PROT_IS_PC_VALID(pc)); - + PROT_MPU_MS_CTL(busMaster) = _VAL2FLD(PROT_MPU_MS_CTL_PC, pc) | _VAL2FLD(PROT_MPU_MS_CTL_PC_SAVED, pc); status = (_FLD2VAL(PROT_MPU_MS_CTL_PC, PROT_MPU_MS_CTL(busMaster)) != pc) ? CY_PROT_FAILURE : CY_PROT_SUCCESS; - + return status; } @@ -181,12 +181,12 @@ cy_en_prot_status_t Cy_Prot_SetActivePC(en_prot_master_t busMaster, uint32_t pc) * * \note This function is applicable for both CPUSS ver_1 and ver_2. * -* Returns the active protection context of a master. +* Returns the active protection context of a master. * * \param busMaster -* The bus master, whose protection context is being read. Refer to the +* The bus master, whose protection context is being read. Refer to the * CPUSS_MS_ID_X defines in the device config header file. -* +* * \return * Active protection context of the master \ref cy_en_prot_pc_t. * @@ -196,9 +196,9 @@ cy_en_prot_status_t Cy_Prot_SetActivePC(en_prot_master_t busMaster, uint32_t pc) *******************************************************************************/ uint32_t Cy_Prot_GetActivePC(en_prot_master_t busMaster) { - + CY_ASSERT_L1(CY_PROT_IS_BUS_MASTER_VALID(busMaster)); - + return ((uint32_t)_FLD2VAL(PROT_MPU_MS_CTL_PC, PROT_MPU_MS_CTL(busMaster))); } @@ -207,8 +207,8 @@ uint32_t Cy_Prot_GetActivePC(en_prot_master_t busMaster) * Function Name: Cy_Prot_ConfigMpuStruct ****************************************************************************//** * -* This function configures a memory protection unit (MPU) struct with its -* protection attributes. +* This function configures a memory protection unit (MPU) struct with its +* protection attributes. * * The protection structs act like the gatekeepers for a master's accesses to * memory, allowing only the permitted transactions to go through. @@ -216,11 +216,11 @@ uint32_t Cy_Prot_GetActivePC(en_prot_master_t busMaster) * \note This function is applicable for both CPUSS ver_1 and ver_2. * * \param base -* The base address for the MPU struct being configured. -* +* The base address for the MPU struct being configured. +* * \param config * Initialization structure containing all the protection attributes. -* +* * \return * Status of the function call. * @@ -253,7 +253,7 @@ cy_en_prot_status_t Cy_Prot_ConfigMpuStruct(PROT_MPU_MPU_STRUCT_Type* base, cons PROT_MPU_MPU_STRUCT_ATT(base) = attReg; PROT_MPU_MPU_STRUCT_ADDR(base) = addrReg; status = ((PROT_MPU_MPU_STRUCT_ADDR(base) != addrReg) || (PROT_MPU_MPU_STRUCT_ATT(base) != attReg)) ? CY_PROT_FAILURE : CY_PROT_SUCCESS; - + return status; } @@ -262,13 +262,13 @@ cy_en_prot_status_t Cy_Prot_ConfigMpuStruct(PROT_MPU_MPU_STRUCT_Type* base, cons * Function Name: Cy_Prot_EnableMpuStruct ****************************************************************************//** * -* Enables the MPU struct, which allows the MPU protection attributes to -* take effect. +* Enables the MPU struct, which allows the MPU protection attributes to +* take effect. * * \note This function is applicable for both CPUSS ver_1 and ver_2. * * \param base -* The base address of the MPU struct being configured. +* The base address of the MPU struct being configured. * * \return * Status of the function call. @@ -285,13 +285,13 @@ cy_en_prot_status_t Cy_Prot_ConfigMpuStruct(PROT_MPU_MPU_STRUCT_Type* base, cons cy_en_prot_status_t Cy_Prot_EnableMpuStruct(PROT_MPU_MPU_STRUCT_Type* base) { cy_en_prot_status_t status; - + CY_ASSERT_L1(NULL != base); - + PROT_MPU_MPU_STRUCT_ATT(base) |= _VAL2FLD(PROT_MPU_MPU_STRUCT_ATT_ENABLED, CY_PROT_STRUCT_ENABLE); status = (_FLD2VAL(PROT_MPU_MPU_STRUCT_ATT_ENABLED, PROT_MPU_MPU_STRUCT_ATT(base)) != CY_PROT_STRUCT_ENABLE) ? CY_PROT_FAILURE : CY_PROT_SUCCESS; - + return status; } @@ -306,7 +306,7 @@ cy_en_prot_status_t Cy_Prot_EnableMpuStruct(PROT_MPU_MPU_STRUCT_Type* base) * \note This function is applicable for both CPUSS ver_1 and ver_2. * * \param base -* The base address of the MPU struct being configured. +* The base address of the MPU struct being configured. * * \return * Status of the function call. @@ -325,11 +325,11 @@ cy_en_prot_status_t Cy_Prot_DisableMpuStruct(PROT_MPU_MPU_STRUCT_Type* base) cy_en_prot_status_t status; CY_ASSERT_L1(NULL != base); - + PROT_MPU_MPU_STRUCT_ATT(base) &= ~_VAL2FLD(PROT_MPU_MPU_STRUCT_ATT_ENABLED, CY_PROT_STRUCT_ENABLE); status = (_FLD2VAL(PROT_MPU_MPU_STRUCT_ATT_ENABLED, PROT_MPU_MPU_STRUCT_ATT(base)) == CY_PROT_STRUCT_ENABLE) ? CY_PROT_FAILURE : CY_PROT_SUCCESS; - + return status; } @@ -338,25 +338,25 @@ cy_en_prot_status_t Cy_Prot_DisableMpuStruct(PROT_MPU_MPU_STRUCT_Type* base) * Function Name: Cy_Prot_ConfigSmpuMasterStruct ****************************************************************************//** * -* Configures a Shared Memory Protection Unit (SMPU) master protection -* struct with its protection attributes. +* Configures a Shared Memory Protection Unit (SMPU) master protection +* struct with its protection attributes. * * This function configures the master struct governing the corresponding slave * struct pair. It is a mechanism to protect the slave SMPU struct. Since the * memory location of the slave struct is known, the address, regionSize and * subregions of the configuration struct are not applicable. * -* Note that only the user/privileged write permissions are configurable. The +* Note that only the user/privileged write permissions are configurable. The * read and execute permissions are read-only and cannot be configured. * * \note This function is applicable for both CPUSS ver_1 and ver_2. * * \param base * The register base address of the protection struct being configured. -* +* * \param config * Initialization structure with all the protection attributes. -* +* * \return * Status of the function call. * @@ -374,13 +374,13 @@ cy_en_prot_status_t Cy_Prot_ConfigSmpuMasterStruct(PROT_SMPU_SMPU_STRUCT_Type* b { cy_en_prot_status_t status; uint32_t attReg; - + CY_ASSERT_L1(NULL != base); CY_ASSERT_L2(CY_PROT_IS_PC_MASK_VALID(config->pcMask)); CY_ASSERT_L3(CY_PROT_IS_SMPU_MS_PERM_VALID(config->userPermission)); CY_ASSERT_L3(CY_PROT_IS_SMPU_MS_PERM_VALID(config->privPermission)); - - if(((uint32_t)config->pcMask & CY_PROT_SMPU_PC_LIMIT_MASK) != 0UL) + + if(((uint32_t)config->pcMask & CY_PROT_SMPU_PC_LIMIT_MASK) != 0UL) { /* PC mask out of range - not supported in device */ status = CY_PROT_BAD_PARAM; @@ -405,7 +405,7 @@ cy_en_prot_status_t Cy_Prot_ConfigSmpuMasterStruct(PROT_SMPU_SMPU_STRUCT_Type* b status = ((PROT_SMPU_SMPU_STRUCT_ATT1(base) & CY_PROT_SMPU_ATT1_MASK) != attReg) ? CY_PROT_FAILURE : CY_PROT_SUCCESS; } } - + return status; } @@ -414,9 +414,9 @@ cy_en_prot_status_t Cy_Prot_ConfigSmpuMasterStruct(PROT_SMPU_SMPU_STRUCT_Type* b * Function Name: Cy_Prot_ConfigSmpuSlaveStruct ****************************************************************************//** * -* Configures a Shared Memory Protection Unit (SMPU) slave protection -* struct with its protection attributes. -* +* Configures a Shared Memory Protection Unit (SMPU) slave protection +* struct with its protection attributes. +* * This function configures the slave struct of an SMPU pair, which can protect * any memory region in a device from invalid bus master accesses. * @@ -424,10 +424,10 @@ cy_en_prot_status_t Cy_Prot_ConfigSmpuMasterStruct(PROT_SMPU_SMPU_STRUCT_Type* b * * \param base * The register base address of the protection structure being configured. -* +* * \param config * Initialization structure with all the protection attributes. -* +* * \return * Status of the function call. * @@ -446,14 +446,14 @@ cy_en_prot_status_t Cy_Prot_ConfigSmpuSlaveStruct(PROT_SMPU_SMPU_STRUCT_Type* ba cy_en_prot_status_t status = CY_PROT_SUCCESS; uint32_t addrReg; uint32_t attReg; - + CY_ASSERT_L1(NULL != base); CY_ASSERT_L2(CY_PROT_IS_PC_MASK_VALID(config->pcMask)); CY_ASSERT_L3(CY_PROT_IS_SMPU_SL_PERM_VALID(config->userPermission)); CY_ASSERT_L3(CY_PROT_IS_SMPU_SL_PERM_VALID(config->privPermission)); CY_ASSERT_L3(CY_PROT_IS_REGION_SIZE_VALID(config->regionSize)); - if(((uint32_t)config->pcMask & CY_PROT_SMPU_PC_LIMIT_MASK) != 0UL) + if(((uint32_t)config->pcMask & CY_PROT_SMPU_PC_LIMIT_MASK) != 0UL) { /* PC mask out of range - not supported in device */ status = CY_PROT_BAD_PARAM; @@ -473,7 +473,7 @@ cy_en_prot_status_t Cy_Prot_ConfigSmpuSlaveStruct(PROT_SMPU_SMPU_STRUCT_Type* ba status = ((PROT_SMPU_SMPU_STRUCT_ADDR0(base) != addrReg) || ((PROT_SMPU_SMPU_STRUCT_ATT0(base) & CY_PROT_SMPU_ATT0_MASK) != attReg)) ? CY_PROT_FAILURE : CY_PROT_SUCCESS; } - + return status; } @@ -490,7 +490,7 @@ cy_en_prot_status_t Cy_Prot_ConfigSmpuSlaveStruct(PROT_SMPU_SMPU_STRUCT_Type* ba * \note This function is applicable for both CPUSS ver_1 and ver_2. * * \param base -* The base address for the protection unit structure being configured. +* The base address for the protection unit structure being configured. * * \return * Status of the function call. @@ -507,13 +507,13 @@ cy_en_prot_status_t Cy_Prot_ConfigSmpuSlaveStruct(PROT_SMPU_SMPU_STRUCT_Type* ba cy_en_prot_status_t Cy_Prot_EnableSmpuMasterStruct(PROT_SMPU_SMPU_STRUCT_Type* base) { cy_en_prot_status_t status; - + CY_ASSERT_L1(NULL != base); - + PROT_SMPU_SMPU_STRUCT_ATT1(base) |= _VAL2FLD(PROT_SMPU_SMPU_STRUCT_ATT1_ENABLED, CY_PROT_STRUCT_ENABLE); status = (_FLD2VAL(PROT_SMPU_SMPU_STRUCT_ATT1_ENABLED, PROT_SMPU_SMPU_STRUCT_ATT1(base)) != CY_PROT_STRUCT_ENABLE) ? CY_PROT_FAILURE : CY_PROT_SUCCESS; - + return status; } @@ -530,7 +530,7 @@ cy_en_prot_status_t Cy_Prot_EnableSmpuMasterStruct(PROT_SMPU_SMPU_STRUCT_Type* b * \note This function is applicable for both CPUSS ver_1 and ver_2. * * \param base -* The base address for the protection unit structure being configured. +* The base address for the protection unit structure being configured. * * \return * Status of the function call. @@ -547,13 +547,13 @@ cy_en_prot_status_t Cy_Prot_EnableSmpuMasterStruct(PROT_SMPU_SMPU_STRUCT_Type* b cy_en_prot_status_t Cy_Prot_DisableSmpuMasterStruct(PROT_SMPU_SMPU_STRUCT_Type* base) { cy_en_prot_status_t status; - + CY_ASSERT_L1(NULL != base); - + PROT_SMPU_SMPU_STRUCT_ATT1(base) &= ~_VAL2FLD(PROT_SMPU_SMPU_STRUCT_ATT1_ENABLED, CY_PROT_STRUCT_ENABLE); status = (_FLD2VAL(PROT_SMPU_SMPU_STRUCT_ATT1_ENABLED, PROT_SMPU_SMPU_STRUCT_ATT1(base)) == CY_PROT_STRUCT_ENABLE) ? CY_PROT_FAILURE : CY_PROT_SUCCESS; - + return status; } @@ -570,7 +570,7 @@ cy_en_prot_status_t Cy_Prot_DisableSmpuMasterStruct(PROT_SMPU_SMPU_STRUCT_Type* * \note This function is applicable for both CPUSS ver_1 and ver_2. * * \param base -* The base address for the protection unit structure being configured. +* The base address for the protection unit structure being configured. * * \return * Status of the function call. @@ -587,13 +587,13 @@ cy_en_prot_status_t Cy_Prot_DisableSmpuMasterStruct(PROT_SMPU_SMPU_STRUCT_Type* cy_en_prot_status_t Cy_Prot_EnableSmpuSlaveStruct(PROT_SMPU_SMPU_STRUCT_Type* base) { cy_en_prot_status_t status; - + CY_ASSERT_L1(NULL != base); - + PROT_SMPU_SMPU_STRUCT_ATT0(base) |= _VAL2FLD(PROT_SMPU_SMPU_STRUCT_ATT0_ENABLED, CY_PROT_STRUCT_ENABLE); status = (_FLD2VAL(PROT_SMPU_SMPU_STRUCT_ATT0_ENABLED, PROT_SMPU_SMPU_STRUCT_ATT0(base)) != CY_PROT_STRUCT_ENABLE) ? CY_PROT_FAILURE : CY_PROT_SUCCESS; - + return status; } @@ -610,7 +610,7 @@ cy_en_prot_status_t Cy_Prot_EnableSmpuSlaveStruct(PROT_SMPU_SMPU_STRUCT_Type* ba * \note This function is applicable for both CPUSS ver_1 and ver_2. * * \param base -* The base address for the protection unit structure being configured. +* The base address for the protection unit structure being configured. * * \return * Status of the function call. @@ -627,13 +627,13 @@ cy_en_prot_status_t Cy_Prot_EnableSmpuSlaveStruct(PROT_SMPU_SMPU_STRUCT_Type* ba cy_en_prot_status_t Cy_Prot_DisableSmpuSlaveStruct(PROT_SMPU_SMPU_STRUCT_Type* base) { cy_en_prot_status_t status; - + CY_ASSERT_L1(NULL != base); - + PROT_SMPU_SMPU_STRUCT_ATT0(base) &= ~_VAL2FLD(PROT_SMPU_SMPU_STRUCT_ATT0_ENABLED, CY_PROT_STRUCT_ENABLE); status = (_FLD2VAL(PROT_SMPU_SMPU_STRUCT_ATT0_ENABLED, PROT_SMPU_SMPU_STRUCT_ATT0(base)) == CY_PROT_STRUCT_ENABLE) ? CY_PROT_FAILURE : CY_PROT_SUCCESS; - + return status; } @@ -642,23 +642,23 @@ cy_en_prot_status_t Cy_Prot_DisableSmpuSlaveStruct(PROT_SMPU_SMPU_STRUCT_Type* b * Function Name: Cy_Prot_GetSmpuStruct ****************************************************************************//** * -* Functions returns a pointer of the requested unused SMPU structure. It +* Functions returns a pointer of the requested unused SMPU structure. It * searches the SMPU structures until it finds one that both the slave and master -* sections are disabled. After an available structure is located, function -* enables the slave structure and set the ATT0[7:0] bits to 0xFF, to make sure -* that a subsequent call will not see this as an available (unused) SMPU. +* sections are disabled. After an available structure is located, function +* enables the slave structure and set the ATT0[7:0] bits to 0xFF, to make sure +* that a subsequent call will not see this as an available (unused) SMPU. * -* It is up to the user to implement, if needed, a system in which a semaphore +* It is up to the user to implement, if needed, a system in which a semaphore * will lock-out all but one CPU from calling this function at once. * * \note This function is applicable for both CPUSS ver_1 and ver_2. * * \param base -* The base address for the SMPU structure returned if an unused structure was +* The base address for the SMPU structure returned if an unused structure was * found. If an empty structure was not found, the returned pointer is NULL. * * \param reqMode -* This parameter (request mode) selects how the user wants to select a SMPU +* This parameter (request mode) selects how the user wants to select a SMPU * structure. * * reqMode | Description @@ -668,7 +668,7 @@ cy_en_prot_status_t Cy_Prot_DisableSmpuSlaveStruct(PROT_SMPU_SMPU_STRUCT_Type* b * CY_PROT_REQMODE_INDEX | Return the SMPU structure with the specific index. * * \param smpuIndex -* This is the index of the requested SMPU structure. It is only used if the +* This is the index of the requested SMPU structure. It is only used if the * request mode is reqMode = CY_PROT_REQMODE_INDEX. * * \return @@ -684,7 +684,7 @@ cy_en_prot_status_t Cy_Prot_DisableSmpuSlaveStruct(PROT_SMPU_SMPU_STRUCT_Type* b * \snippet prot/snippet/main.c snippet_Cy_Prot_GetSmpuStruct * *******************************************************************************/ -cy_en_prot_status_t Cy_Prot_GetSmpuStruct(PROT_SMPU_SMPU_STRUCT_Type** base, +cy_en_prot_status_t Cy_Prot_GetSmpuStruct(PROT_SMPU_SMPU_STRUCT_Type** base, cy_en_prot_req_mode_t reqMode, uint32_t smpuIndex) { CY_ASSERT_L3(CY_PROT_IS_SMPU_REQ_MODE_VALID(reqMode)); @@ -697,7 +697,7 @@ cy_en_prot_status_t Cy_Prot_GetSmpuStruct(PROT_SMPU_SMPU_STRUCT_Type** base, switch (reqMode) { - /* The SMPU priority goes from PROT_SMPU_STRUCT_HIGHEST_PR + /* The SMPU priority goes from PROT_SMPU_STRUCT_HIGHEST_PR * (highest priority) to 0 (lowest priority) */ case CY_PROT_REQMODE_HIGHPRIOR: @@ -715,7 +715,7 @@ cy_en_prot_status_t Cy_Prot_GetSmpuStruct(PROT_SMPU_SMPU_STRUCT_Type** base, } } while ((stcIdx >= 0) && (CY_PROT_SUCCESS != status)); break; - + case CY_PROT_REQMODE_LOWPRIOR: stcIdx = 0; do @@ -730,7 +730,7 @@ cy_en_prot_status_t Cy_Prot_GetSmpuStruct(PROT_SMPU_SMPU_STRUCT_Type** base, } } while ((stcIdx <= PROT_SMPU_STRUCT_WTH_HIGHEST_PR) && (CY_PROT_SUCCESS != status)); break; - + case CY_PROT_REQMODE_INDEX: if (Prot_IsSmpuStructDisabled((uint32_t)stcIdx)) { @@ -747,8 +747,8 @@ cy_en_prot_status_t Cy_Prot_GetSmpuStruct(PROT_SMPU_SMPU_STRUCT_Type** base, { /* Enable Slave SMPU struct */ PROT_SMPU_SMPU_STRUCT_IDX_ATT0(stcIdx) |= _VAL2FLD(PROT_SMPU_SMPU_STRUCT_ATT0_ENABLED, CY_PROT_STRUCT_ENABLE); - - status = + + status = (_FLD2VAL(PROT_SMPU_SMPU_STRUCT_ATT0_ENABLED, PROT_SMPU_SMPU_STRUCT_IDX_ATT0(stcIdx)) != CY_PROT_STRUCT_ENABLE) ? CY_PROT_FAILURE : CY_PROT_SUCCESS; @@ -767,7 +767,7 @@ cy_en_prot_status_t Cy_Prot_GetSmpuStruct(PROT_SMPU_SMPU_STRUCT_Type** base, * Function Name: Prot_ConfigPpuAtt ******************************************************************************** * -* An internal function to hold the common code for +* An internal function to hold the common code for * Cy_Prot_ConfigPpu[Prog/Fixed][Master/Slave]Att API functions * * \note This function is applicable for CPUSS ver_2 only. @@ -790,7 +790,7 @@ cy_en_prot_status_t Cy_Prot_GetSmpuStruct(PROT_SMPU_SMPU_STRUCT_Type** base, * \param privPermission * The privileged permissions for the region. * -* \param secure +* \param secure * Non Secure = false, Secure = true * * \return @@ -803,7 +803,7 @@ cy_en_prot_status_t Cy_Prot_GetSmpuStruct(PROT_SMPU_SMPU_STRUCT_Type** base, * CY_PROT_INVALID_STATE | The function was called on the device with an unsupported PERI HW version. * *******************************************************************************/ -static cy_en_prot_status_t Prot_ConfigPpuAtt(volatile uint32_t * reg, uint16_t pcMask, +static cy_en_prot_status_t Prot_ConfigPpuAtt(volatile uint32_t * reg, uint16_t pcMask, cy_en_prot_perm_t userPermission, cy_en_prot_perm_t privPermission, bool secure) { cy_en_prot_status_t status = CY_PROT_INVALID_STATE; @@ -814,9 +814,9 @@ static cy_en_prot_status_t Prot_ConfigPpuAtt(volatile uint32_t * reg, uint16_t p uint32_t attReg; uint32_t regIdx; uint32_t fldIdx; - + status = CY_PROT_SUCCESS; - + /* Populate the ATT values */ for(regIdx = 0U; regIdx < CY_PROT_ATT_REGS_MAX; regIdx++) { @@ -824,7 +824,7 @@ static cy_en_prot_status_t Prot_ConfigPpuAtt(volatile uint32_t * reg, uint16_t p { break; } - + /* Get the attributes register value */ attReg = reg[regIdx]; @@ -836,8 +836,8 @@ static cy_en_prot_status_t Prot_ConfigPpuAtt(volatile uint32_t * reg, uint16_t p attReg &= ~((_VAL2FLD(CY_PROT_ATT_PERI_USER_PERM, CY_PROT_PERM_RW) | _VAL2FLD(CY_PROT_ATT_PERI_PRIV_PERM, CY_PROT_PERM_RW) | _BOOL2FLD(PERI_MS_PPU_PR_V2_MS_ATT0_PC0_NS, true)) << - (PERI_MS_PPU_PR_V2_MS_ATT0_PC1_UR_Pos * fldIdx)); - + (PERI_MS_PPU_PR_V2_MS_ATT0_PC1_UR_Pos * fldIdx)); + /* Set the bitfield for the PCx attributes */ attReg |= (_VAL2FLD(CY_PROT_ATT_PERI_USER_PERM, userPermission) | _VAL2FLD(CY_PROT_ATT_PERI_PRIV_PERM, privPermission) | @@ -846,12 +846,12 @@ static cy_en_prot_status_t Prot_ConfigPpuAtt(volatile uint32_t * reg, uint16_t p } tmpMask = tmpMask >> CY_PROT_PCMASK_CHECK; } - + /* Update the attributes register */ reg[regIdx] = attReg; /* Check the result */ - if ((0UL == regIdx) && + if ((0UL == regIdx) && ((reg[regIdx] & PROT_PERI_PPU_PROG_PC1_PC3_MASK) != (attReg & PROT_PERI_PPU_PROG_PC1_PC3_MASK))) { status = CY_PROT_FAILURE; @@ -875,8 +875,8 @@ static cy_en_prot_status_t Prot_ConfigPpuAtt(volatile uint32_t * reg, uint16_t p * Function Name: Cy_Prot_ConfigPpuProgMasterAtt ****************************************************************************//** * -* Configures the protection-structure attributes of the -* Programmable Peripheral Protection Unit (PPU PROG) master. +* Configures the protection-structure attributes of the +* Programmable Peripheral Protection Unit (PPU PROG) master. * * This function configures the master structure governing the corresponding slave * structure pair. It is a mechanism to protect the slave PPU PROG structure. @@ -898,16 +898,16 @@ static cy_en_prot_status_t Prot_ConfigPpuAtt(volatile uint32_t * reg, uint16_t p * That number is defined by PERI_PC_NR in the config file. * * \param userPermission -* The user permission setting. The CY_PROT_PERM_R or CY_PROT_PERM_RW values +* The user permission setting. The CY_PROT_PERM_R or CY_PROT_PERM_RW values * are valid for the master. * * \param privPermission -* The privileged permission setting. CY_PROT_PERM_R or CY_PROT_PERM_RW values +* The privileged permission setting. CY_PROT_PERM_R or CY_PROT_PERM_RW values * are valid for the master. * * \param secure * The secure flag. -* +* * \return * The status of the function call. * @@ -917,23 +917,23 @@ static cy_en_prot_status_t Prot_ConfigPpuAtt(volatile uint32_t * reg, uint16_t p * CY_PROT_FAILURE | The attributes were not set up because the structure is possibly locked. * CY_PROT_INVALID_STATE | The function was called on the device with an unsupported PERI HW version. * -* \note Only the user's/privileged Write permissions are configurable. The +* \note Only the user's/privileged Write permissions are configurable. The * Read permissions are read-only and cannot be configured. * -* \note PC0 accesses are read-only and are always enabled. +* \note PC0 accesses are read-only and are always enabled. * * \funcusage * \snippet prot/snippet/main.c snippet_Cy_Prot_ConfigPpuProgMasterAtt * *******************************************************************************/ -cy_en_prot_status_t Cy_Prot_ConfigPpuProgMasterAtt(PERI_MS_PPU_PR_Type* base, uint16_t pcMask, +cy_en_prot_status_t Cy_Prot_ConfigPpuProgMasterAtt(PERI_MS_PPU_PR_Type* base, uint16_t pcMask, cy_en_prot_perm_t userPermission, cy_en_prot_perm_t privPermission, bool secure) -{ +{ /* The parameter checks */ CY_ASSERT_L1(NULL != base); CY_ASSERT_L3(CY_PROT_IS_PROG_MS_PERM_VALID(userPermission)); CY_ASSERT_L3(CY_PROT_IS_PROG_MS_PERM_VALID(privPermission)); - + return (Prot_ConfigPpuAtt(PERI_MS_PPU_PR_MS_ATT(base), pcMask, userPermission, privPermission, secure)); } @@ -942,24 +942,24 @@ cy_en_prot_status_t Cy_Prot_ConfigPpuProgMasterAtt(PERI_MS_PPU_PR_Type* base, ui * Function Name: Cy_Prot_ConfigPpuProgSlaveAddr ****************************************************************************//** * -* Configures the protection-structure address settings of the -* Programmable Peripheral Protection Unit (PPU PROG) slave. -* -* This function configures the slave structure of the PPU PROG pair, which can -* protect any peripheral memory region in a device from an invalid bus-master +* Configures the protection-structure address settings of the +* Programmable Peripheral Protection Unit (PPU PROG) slave. +* +* This function configures the slave structure of the PPU PROG pair, which can +* protect any peripheral memory region in a device from an invalid bus-master * access. * * \note This function is applicable for CPUSS ver_2 only. * * \param base * The register base address of the protection structure is being configured. -* +* * \param address * The address. -* +* * \param regionSize * The region size. -* +* * \return * The status of the function call. * @@ -967,33 +967,33 @@ cy_en_prot_status_t Cy_Prot_ConfigPpuProgMasterAtt(PERI_MS_PPU_PR_Type* base, ui * ----------------------| --------------------------------------- * CY_PROT_SUCCESS | The address settings were set up. * CY_PROT_FAILURE | The address settings were not set up because the structure is possibly locked. -* CY_PROT_INVALID_STATE | The function was called on the device with an unsupported PERI HW version. +* CY_PROT_INVALID_STATE | The function was called on the device with an unsupported PERI HW version. * -* \note PC0 accesses are Read-only and are always enabled. +* \note PC0 accesses are Read-only and are always enabled. * * \funcusage * \ref Cy_Prot_ConfigPpuProgSlaveAtt * *******************************************************************************/ -cy_en_prot_status_t Cy_Prot_ConfigPpuProgSlaveAddr(PERI_MS_PPU_PR_Type* base, uint32_t address, +cy_en_prot_status_t Cy_Prot_ConfigPpuProgSlaveAddr(PERI_MS_PPU_PR_Type* base, uint32_t address, cy_en_prot_size_t regionSize) { cy_en_prot_status_t status = CY_PROT_INVALID_STATE; - + /* The parameter checks */ CY_ASSERT_L1(NULL != base); CY_ASSERT_L3(CY_PROT_IS_PPU_V2_SIZE_VALID(regionSize)); - + if (!CY_PERI_V1) { PERI_MS_PPU_PR_SL_ADDR(base) = address & PERI_MS_PPU_PR_V2_SL_ADDR_ADDR30_Msk; PERI_MS_PPU_PR_SL_SIZE(base) = _CLR_SET_FLD32U((PERI_MS_PPU_PR_SL_SIZE(base)), PERI_MS_PPU_PR_V2_SL_SIZE_REGION_SIZE, regionSize); - + status = ((PERI_MS_PPU_PR_SL_ADDR(base) != (address & PERI_MS_PPU_PR_V2_SL_ADDR_ADDR30_Msk)) || (_FLD2VAL(PERI_MS_PPU_PR_V2_SL_SIZE_REGION_SIZE, PERI_MS_PPU_PR_SL_SIZE(base)) != (uint32_t)regionSize)) ? CY_PROT_FAILURE : CY_PROT_SUCCESS; } - + return status; } @@ -1002,11 +1002,11 @@ cy_en_prot_status_t Cy_Prot_ConfigPpuProgSlaveAddr(PERI_MS_PPU_PR_Type* base, ui * Function Name: Cy_Prot_ConfigPpuProgSlaveAtt ****************************************************************************//** * -* Configures the protection structure with its protection attributes of the -* Programmable Peripheral Protection Unit (PPU PROG) slave. -* -* This function configures the slave structure of the PPU PROG pair, which can -* protect any peripheral memory region in a device from invalid bus-master +* Configures the protection structure with its protection attributes of the +* Programmable Peripheral Protection Unit (PPU PROG) slave. +* +* This function configures the slave structure of the PPU PROG pair, which can +* protect any peripheral memory region in a device from invalid bus-master * access. * * \note This function is applicable for CPUSS ver_2 only. @@ -1031,7 +1031,7 @@ cy_en_prot_status_t Cy_Prot_ConfigPpuProgSlaveAddr(PERI_MS_PPU_PR_Type* base, ui * * \param secure * The secure flag. -* +* * \return * The status of the function call. * @@ -1041,13 +1041,13 @@ cy_en_prot_status_t Cy_Prot_ConfigPpuProgSlaveAddr(PERI_MS_PPU_PR_Type* base, ui * CY_PROT_FAILURE | The attributes were not set up because the structure is possibly locked. * CY_PROT_INVALID_STATE | The function was called on the device with an unsupported PERI HW version. * -* \note PC0 accesses are read-only and are always enabled. +* \note PC0 accesses are read-only and are always enabled. * * \funcusage * \snippet prot/snippet/main.c snippet_Cy_Prot_ConfigPpuProgSlaveAtt * *******************************************************************************/ -cy_en_prot_status_t Cy_Prot_ConfigPpuProgSlaveAtt(PERI_MS_PPU_PR_Type* base, uint16_t pcMask, +cy_en_prot_status_t Cy_Prot_ConfigPpuProgSlaveAtt(PERI_MS_PPU_PR_Type* base, uint16_t pcMask, cy_en_prot_perm_t userPermission, cy_en_prot_perm_t privPermission, bool secure) { /* The parameter checks */ @@ -1065,13 +1065,13 @@ cy_en_prot_status_t Cy_Prot_ConfigPpuProgSlaveAtt(PERI_MS_PPU_PR_Type* base, uin * * Enables the Slave PPU PROG structure. * -* This is the PPU PROG slave-structure enable function. The PPU PROG protection +* This is the PPU PROG slave-structure enable function. The PPU PROG protection * settings will take effect after a successful completion of this function call. * * \note This function is applicable for CPUSS ver_2 only. * * \param base -* The base address for the protection unit structure is being configured. +* The base address for the protection unit structure is being configured. * * \return * The status of the function call. @@ -1080,27 +1080,27 @@ cy_en_prot_status_t Cy_Prot_ConfigPpuProgSlaveAtt(PERI_MS_PPU_PR_Type* base, uin * ----------------------| --------------------------------------- * CY_PROT_SUCCESS | The structure was enabled. * CY_PROT_FAILURE | The structure is disabled and possibly locked. -* CY_PROT_INVALID_STATE | The function was called on the device with an unsupported PERI HW version. +* CY_PROT_INVALID_STATE | The function was called on the device with an unsupported PERI HW version. * * \funcusage * \ref Cy_Prot_ConfigPpuProgSlaveAtt * *******************************************************************************/ cy_en_prot_status_t Cy_Prot_EnablePpuProgSlaveRegion(PERI_MS_PPU_PR_Type* base) -{ +{ cy_en_prot_status_t status = CY_PROT_INVALID_STATE; - + CY_ASSERT_L1(NULL != base); - + if (!CY_PERI_V1) { - PERI_MS_PPU_PR_SL_SIZE(base) = + PERI_MS_PPU_PR_SL_SIZE(base) = _CLR_SET_FLD32U((PERI_MS_PPU_PR_SL_SIZE(base)), PERI_MS_PPU_PR_V2_SL_SIZE_VALID, CY_PROT_STRUCT_ENABLE); - - status = (_FLD2VAL(PERI_MS_PPU_PR_V2_SL_SIZE_VALID, PERI_MS_PPU_PR_SL_SIZE(base)) != CY_PROT_STRUCT_ENABLE) ? + + status = (_FLD2VAL(PERI_MS_PPU_PR_V2_SL_SIZE_VALID, PERI_MS_PPU_PR_SL_SIZE(base)) != CY_PROT_STRUCT_ENABLE) ? CY_PROT_FAILURE : CY_PROT_SUCCESS; } - + return status; } @@ -1111,14 +1111,14 @@ cy_en_prot_status_t Cy_Prot_EnablePpuProgSlaveRegion(PERI_MS_PPU_PR_Type* base) * * Disables the Slave PPU PROG structure. * -* This is the PPU PROG slave-structure disable function. The PPU PROG protection -* settings will seize to take effect after successful completion of this +* This is the PPU PROG slave-structure disable function. The PPU PROG protection +* settings will seize to take effect after successful completion of this * function call. * * \note This function is applicable for CPUSS ver_2 only. * * \param base -* The base address for the protection unit structure is being configured. +* The base address for the protection unit structure is being configured. * * \return * The status of the function call. @@ -1136,18 +1136,18 @@ cy_en_prot_status_t Cy_Prot_EnablePpuProgSlaveRegion(PERI_MS_PPU_PR_Type* base) cy_en_prot_status_t Cy_Prot_DisablePpuProgSlaveRegion(PERI_MS_PPU_PR_Type* base) { cy_en_prot_status_t status = CY_PROT_INVALID_STATE; - + CY_ASSERT_L1(NULL != base); - + if (!CY_PERI_V1) { - PERI_MS_PPU_PR_SL_SIZE(base) = + PERI_MS_PPU_PR_SL_SIZE(base) = _CLR_SET_FLD32U((PERI_MS_PPU_PR_SL_SIZE(base)), PERI_MS_PPU_PR_V2_SL_SIZE_VALID, CY_PROT_STRUCT_DISABLE); - status = (_FLD2VAL(PERI_MS_PPU_PR_V2_SL_SIZE_VALID, PERI_MS_PPU_PR_SL_SIZE(base)) != CY_PROT_STRUCT_DISABLE) ? + status = (_FLD2VAL(PERI_MS_PPU_PR_V2_SL_SIZE_VALID, PERI_MS_PPU_PR_SL_SIZE(base)) != CY_PROT_STRUCT_DISABLE) ? CY_PROT_FAILURE : CY_PROT_SUCCESS; } - + return status; } @@ -1157,7 +1157,7 @@ cy_en_prot_status_t Cy_Prot_DisablePpuProgSlaveRegion(PERI_MS_PPU_PR_Type* base) ****************************************************************************//** * * Configures the protection structure with its protection attributes of the -* Fixed Peripheral Protection Unit (PPU FIXED) master. +* Fixed Peripheral Protection Unit (PPU FIXED) master. * * This function configures the master structure governing the corresponding slave * structure pair. It is a mechanism to protect the slave PPU FIXED structure. @@ -1179,16 +1179,16 @@ cy_en_prot_status_t Cy_Prot_DisablePpuProgSlaveRegion(PERI_MS_PPU_PR_Type* base) * That number is defined by PERI_PC_NR in the config file. * * \param userPermission -* The user permission setting. The CY_PROT_PERM_R or CY_PROT_PERM_RW values +* The user permission setting. The CY_PROT_PERM_R or CY_PROT_PERM_RW values * are valid for the master. * * \param privPermission -* The privileged permission setting. The CY_PROT_PERM_R or CY_PROT_PERM_RW values +* The privileged permission setting. The CY_PROT_PERM_R or CY_PROT_PERM_RW values * are valid for the master. * * \param secure * The secure flag. -* +* * \return * The status of the function call. * @@ -1198,10 +1198,10 @@ cy_en_prot_status_t Cy_Prot_DisablePpuProgSlaveRegion(PERI_MS_PPU_PR_Type* base) * CY_PROT_FAILURE | The attributes were not setup and the structure is possibly locked. * CY_PROT_INVALID_STATE | The function was called on the device with an unsupported PERI HW version. * -* \note Only the user/privileged write permissions are configurable. The +* \note Only the user/privileged write permissions are configurable. The * read permissions are read-only and cannot be configured. * -* \note PC0 accesses are read-only and are always enabled. +* \note PC0 accesses are read-only and are always enabled. * * \funcusage * \snippet prot/snippet/main.c snippet_Cy_Prot_ConfigPpuFixedMasterAtt @@ -1224,10 +1224,10 @@ cy_en_prot_status_t Cy_Prot_ConfigPpuFixedMasterAtt(PERI_MS_PPU_FX_Type* base, u ****************************************************************************//** * * Configures the protection structure with its protection attributes of -* the Fixed Peripheral Protection Unit (PPU FIXED) slave. -* -* This function configures the slave structure of the PPU FIXED pair, which can -* protect any peripheral memory region in a device from invalid bus-master +* the Fixed Peripheral Protection Unit (PPU FIXED) slave. +* +* This function configures the slave structure of the PPU FIXED pair, which can +* protect any peripheral memory region in a device from invalid bus-master * access. * * \note This function is applicable for CPUSS ver_2 only. @@ -1252,7 +1252,7 @@ cy_en_prot_status_t Cy_Prot_ConfigPpuFixedMasterAtt(PERI_MS_PPU_FX_Type* base, u * * \param secure * The secure flag. -* +* * \return * The status of the function call. * @@ -1262,13 +1262,13 @@ cy_en_prot_status_t Cy_Prot_ConfigPpuFixedMasterAtt(PERI_MS_PPU_FX_Type* base, u * CY_PROT_FAILURE | The attributes were not setup and the structure is possibly locked. * CY_PROT_INVALID_STATE | The function was called on the device with an unsupported PERI HW version. * -* \note PC0 accesses are read-only and are always enabled. +* \note PC0 accesses are read-only and are always enabled. * * \funcusage * \snippet prot/snippet/main.c snippet_Cy_Prot_ConfigPpuFixedSlaveAtt * *******************************************************************************/ -cy_en_prot_status_t Cy_Prot_ConfigPpuFixedSlaveAtt(PERI_MS_PPU_FX_Type* base, uint16_t pcMask, +cy_en_prot_status_t Cy_Prot_ConfigPpuFixedSlaveAtt(PERI_MS_PPU_FX_Type* base, uint16_t pcMask, cy_en_prot_perm_t userPermission, cy_en_prot_perm_t privPermission, bool secure) { /* The parameter checks */ @@ -1284,25 +1284,25 @@ cy_en_prot_status_t Cy_Prot_ConfigPpuFixedSlaveAtt(PERI_MS_PPU_FX_Type* base, ui * Function Name: Cy_Prot_ConfigPpuProgMasterStruct ****************************************************************************//** * -* Configures a Programmable Peripheral Protection Unit (PPU PROG) master -* protection struct with its protection attributes. +* Configures a Programmable Peripheral Protection Unit (PPU PROG) master +* protection struct with its protection attributes. * * This function configures the master struct governing the corresponding slave * struct pair. It is a mechanism to protect the slave PPU PROG struct. Since * the memory location of the slave struct is known, the address, regionSize and * subregions of the configuration struct are not applicable. * -* Note that only the user/privileged write permissions are configurable. The +* Note that only the user/privileged write permissions are configurable. The * read and execute permissions are read-only and cannot be configured. * * \note This function is applicable for CPUSS ver_1 only. * * \param base * The register base address of the protection struct being configured. -* +* * \param config * Initialization structure with all the protection attributes. -* +* * \return * Status of the function call. * @@ -1321,14 +1321,14 @@ cy_en_prot_status_t Cy_Prot_ConfigPpuProgMasterStruct(PERI_PPU_PR_Type* base, co { cy_en_prot_status_t status = CY_PROT_INVALID_STATE; uint32_t attReg; - + CY_ASSERT_L1(NULL != base); CY_ASSERT_L3(CY_PROT_IS_PROG_MS_PERM_VALID(config->userPermission)); CY_ASSERT_L3(CY_PROT_IS_PROG_MS_PERM_VALID(config->privPermission)); - + if (CY_PERI_V1) { - if(((uint32_t)config->pcMask & CY_PROT_PPU_PROG_PC_LIMIT_MASK) != 0UL) + if(((uint32_t)config->pcMask & CY_PROT_PPU_PROG_PC_LIMIT_MASK) != 0UL) { /* PC mask out of range - not supported in device */ status = CY_PROT_BAD_PARAM; @@ -1363,23 +1363,23 @@ cy_en_prot_status_t Cy_Prot_ConfigPpuProgMasterStruct(PERI_PPU_PR_Type* base, co ****************************************************************************//** * * Configures a Programmable Peripheral Protection Unit (PPU PROG) slave -* protection struct with its protection attributes. -* -* This function configures the slave struct of a PPU PROG pair, which can -* protect any peripheral memory region in a device from invalid bus master +* protection struct with its protection attributes. +* +* This function configures the slave struct of a PPU PROG pair, which can +* protect any peripheral memory region in a device from invalid bus master * accesses. * -* Note that the user/privileged execute accesses are read-only and are always -* enabled. +* Note that the user/privileged execute accesses are read-only and are always +* enabled. * * \note This function is applicable for CPUSS ver_1 only. * * \param base * The register base address of the protection structure being configured. -* +* * \param config * Initialization structure with all the protection attributes. -* +* * \return * Status of the function call. * @@ -1399,7 +1399,7 @@ cy_en_prot_status_t Cy_Prot_ConfigPpuProgSlaveStruct(PERI_PPU_PR_Type* base, con cy_en_prot_status_t status = CY_PROT_INVALID_STATE; uint32_t addrReg; uint32_t attReg; - + CY_ASSERT_L1(NULL != base); CY_ASSERT_L3(CY_PROT_IS_PROG_SL_PERM_VALID(config->userPermission)); CY_ASSERT_L3(CY_PROT_IS_PROG_SL_PERM_VALID(config->privPermission)); @@ -1407,7 +1407,7 @@ cy_en_prot_status_t Cy_Prot_ConfigPpuProgSlaveStruct(PERI_PPU_PR_Type* base, con if (CY_PERI_V1) { - if(((uint32_t)config->pcMask & CY_PROT_PPU_PROG_PC_LIMIT_MASK) != 0UL) + if(((uint32_t)config->pcMask & CY_PROT_PPU_PROG_PC_LIMIT_MASK) != 0UL) { /* PC mask out of range - not supported in device */ status = CY_PROT_BAD_PARAM; @@ -1436,7 +1436,7 @@ cy_en_prot_status_t Cy_Prot_ConfigPpuProgSlaveStruct(PERI_PPU_PR_Type* base, con } } } - + return status; } @@ -1447,13 +1447,13 @@ cy_en_prot_status_t Cy_Prot_ConfigPpuProgSlaveStruct(PERI_PPU_PR_Type* base, con * * Enables the Master PPU PROG structure. * -* This is a PPU PROG master struct enable function. The PPU PROG protection +* This is a PPU PROG master struct enable function. The PPU PROG protection * settings will take effect after successful completion of this function call. * * \note This function is applicable for CPUSS ver_1 only. * * \param base -* The base address for the protection unit structure being configured. +* The base address for the protection unit structure being configured. * * \return * Status of the function call. @@ -1471,9 +1471,9 @@ cy_en_prot_status_t Cy_Prot_ConfigPpuProgSlaveStruct(PERI_PPU_PR_Type* base, con cy_en_prot_status_t Cy_Prot_EnablePpuProgMasterStruct(PERI_PPU_PR_Type* base) { cy_en_prot_status_t status = CY_PROT_INVALID_STATE; - + CY_ASSERT_L1(NULL != base); - + if (CY_PERI_V1) { PERI_PPU_PR_ATT1(base) |= _VAL2FLD(PERI_PPU_PR_ATT1_ENABLED, CY_PROT_STRUCT_ENABLE); @@ -1491,14 +1491,14 @@ cy_en_prot_status_t Cy_Prot_EnablePpuProgMasterStruct(PERI_PPU_PR_Type* base) * * Disables the Master PPU PROG structure. * -* This is a PPU PROG master struct disable function. The PPU PROG protection -* settings will seize to take effect after successful completion of this +* This is a PPU PROG master struct disable function. The PPU PROG protection +* settings will seize to take effect after successful completion of this * function call. * * \note This function is applicable for CPUSS ver_1 only. * * \param base -* The base address for the protection unit structure being configured. +* The base address for the protection unit structure being configured. * * \return * Status of the function call. @@ -1516,9 +1516,9 @@ cy_en_prot_status_t Cy_Prot_EnablePpuProgMasterStruct(PERI_PPU_PR_Type* base) cy_en_prot_status_t Cy_Prot_DisablePpuProgMasterStruct(PERI_PPU_PR_Type* base) { cy_en_prot_status_t status = CY_PROT_INVALID_STATE; - + CY_ASSERT_L1(NULL != base); - + if (CY_PERI_V1) { PERI_PPU_PR_ATT1(base) &= ~_VAL2FLD(PERI_PPU_PR_ATT1_ENABLED, CY_PROT_STRUCT_ENABLE); @@ -1536,13 +1536,13 @@ cy_en_prot_status_t Cy_Prot_DisablePpuProgMasterStruct(PERI_PPU_PR_Type* base) * * Enables the Slave PPU PROG structure. * -* This is a PPU PROG slave struct enable function. The PPU PROG protection +* This is a PPU PROG slave struct enable function. The PPU PROG protection * settings will take effect after successful completion of this function call. * * \note This function is applicable for CPUSS ver_1 only. * * \param base -* The base address for the protection unit structure being configured. +* The base address for the protection unit structure being configured. * * \return * Status of the function call. @@ -1558,11 +1558,11 @@ cy_en_prot_status_t Cy_Prot_DisablePpuProgMasterStruct(PERI_PPU_PR_Type* base) * *******************************************************************************/ cy_en_prot_status_t Cy_Prot_EnablePpuProgSlaveStruct(PERI_PPU_PR_Type* base) -{ +{ cy_en_prot_status_t status = CY_PROT_INVALID_STATE; - + CY_ASSERT_L1(NULL != base); - + if (CY_PERI_V1) { PERI_PPU_PR_ATT0(base) |= _VAL2FLD(PERI_PPU_PR_ATT0_ENABLED, CY_PROT_STRUCT_ENABLE); @@ -1580,14 +1580,14 @@ cy_en_prot_status_t Cy_Prot_EnablePpuProgSlaveStruct(PERI_PPU_PR_Type* base) * * Disables the Slave PPU PROG structure. * -* This is a PPU PROG slave struct disable function. The PPU PROG protection -* settings will seize to take effect after successful completion of this +* This is a PPU PROG slave struct disable function. The PPU PROG protection +* settings will seize to take effect after successful completion of this * function call. * * \note This function is applicable for CPUSS ver_1 only. * * \param base -* The base address for the protection unit structure being configured. +* The base address for the protection unit structure being configured. * * \return * Status of the function call. @@ -1605,9 +1605,9 @@ cy_en_prot_status_t Cy_Prot_EnablePpuProgSlaveStruct(PERI_PPU_PR_Type* base) cy_en_prot_status_t Cy_Prot_DisablePpuProgSlaveStruct(PERI_PPU_PR_Type* base) { cy_en_prot_status_t status = CY_PROT_INVALID_STATE; - + CY_ASSERT_L1(NULL != base); - + if (CY_PERI_V1) { PERI_PPU_PR_ATT0(base) &= ~_VAL2FLD(PERI_PPU_PR_ATT0_ENABLED, CY_PROT_STRUCT_ENABLE); @@ -1623,25 +1623,25 @@ cy_en_prot_status_t Cy_Prot_DisablePpuProgSlaveStruct(PERI_PPU_PR_Type* base) * Function Name: Cy_Prot_GetPpuProgStruct ****************************************************************************//** * -* Functions returns a pointer of the requested unused Programmable PPU -* structure. Function searches the Programmable PPU structure until it finds +* Functions returns a pointer of the requested unused Programmable PPU +* structure. Function searches the Programmable PPU structure until it finds * one that both the slave and master sections are disabled. After an available -* structure is located, function enables the slave structure and enables all +* structure is located, function enables the slave structure and enables all * attributes, to make sure that a subsequent call will not see this -* as an available (unused) Programmable PPU. +* as an available (unused) Programmable PPU. * -* It is up to the user to implement, if needed, a system in which a semaphore +* It is up to the user to implement, if needed, a system in which a semaphore * will lock-out all but one CPU from calling this function at once. * * \note This function is applicable for CPUSS ver_1 only. * * \param base -* The base address for the Programmable PPU structure returned if an unused -* structure was found. If an empty structure was not found, the returned +* The base address for the Programmable PPU structure returned if an unused +* structure was found. If an empty structure was not found, the returned * pointer is NULL. * * \param reqMode -* This parameter (request mode) selects how the user wants to select a +* This parameter (request mode) selects how the user wants to select a * Programmable PPU structure. * * reqMode | Description @@ -1651,7 +1651,7 @@ cy_en_prot_status_t Cy_Prot_DisablePpuProgSlaveStruct(PERI_PPU_PR_Type* base) * CY_PROT_REQMODE_INDEX | Return the Programmable PPU structure with the specific index. * * \param ppuProgIndex -* This is the index of the requested Programmable PPU structure. It is only +* This is the index of the requested Programmable PPU structure. It is only * used if the request mode is reqMode = CY_PROT_REQMODE_INDEX. * * \return @@ -1671,7 +1671,7 @@ cy_en_prot_status_t Cy_Prot_DisablePpuProgSlaveStruct(PERI_PPU_PR_Type* base) cy_en_prot_status_t Cy_Prot_GetPpuProgStruct(PERI_PPU_PR_Type** base, cy_en_prot_req_mode_t reqMode, uint32_t ppuProgIndex) { cy_en_prot_status_t status = CY_PROT_INVALID_STATE; - + if (CY_PERI_V1) { CY_ASSERT_L3(CY_PROT_IS_PPU_PROG_REQ_MODE_VALID(reqMode)); @@ -1685,7 +1685,7 @@ cy_en_prot_status_t Cy_Prot_GetPpuProgStruct(PERI_PPU_PR_Type** base, cy_en_prot switch (reqMode) { /* Programmed structures priority goes from 0 (highest) to - * PROT_PPU_PROG_STRUCT_WTH_LOWEST_PR (lowest) + * PROT_PPU_PROG_STRUCT_WTH_LOWEST_PR (lowest) */ case CY_PROT_REQMODE_LOWPRIOR: @@ -1703,7 +1703,7 @@ cy_en_prot_status_t Cy_Prot_GetPpuProgStruct(PERI_PPU_PR_Type** base, cy_en_prot } while ((stcIdx >= 0) && (CY_PROT_SUCCESS != status)); break; - /* Programmed structures priority goes from 0 (highest) to + /* Programmed structures priority goes from 0 (highest) to * PROT_PPU_PROG_STRUCT_WTH_LOWEST_PR (lowest) */ case CY_PROT_REQMODE_HIGHPRIOR: @@ -1720,7 +1720,7 @@ cy_en_prot_status_t Cy_Prot_GetPpuProgStruct(PERI_PPU_PR_Type** base, cy_en_prot } } while ((stcIdx <= PROT_PPU_PROG_STRUCT_WTH_LOWEST_PR) && (CY_PROT_SUCCESS != status)); break; - + case CY_PROT_REQMODE_INDEX: if (Prot_IsPpuProgStructDisabled((uint32_t)stcIdx)) @@ -1728,7 +1728,7 @@ cy_en_prot_status_t Cy_Prot_GetPpuProgStruct(PERI_PPU_PR_Type** base, cy_en_prot status = CY_PROT_SUCCESS; } break; - + default: break; } @@ -1737,11 +1737,11 @@ cy_en_prot_status_t Cy_Prot_GetPpuProgStruct(PERI_PPU_PR_Type** base, cy_en_prot if (CY_PROT_SUCCESS == status) { PROT_PERI_PPU_PR_STRUCT_IDX_ATT0(stcIdx) |= _VAL2FLD(PERI_PPU_PR_ATT0_ENABLED, CY_PROT_STRUCT_ENABLE); - - status = + + status = (_FLD2VAL(PERI_PPU_PR_ATT0_ENABLED, PROT_PERI_PPU_PR_STRUCT_IDX_ATT0(stcIdx)) != CY_PROT_STRUCT_ENABLE) ? CY_PROT_FAILURE : CY_PROT_SUCCESS; - + /* Enable all attributes only if Slave struct was enabled */ if (CY_PROT_SUCCESS == status) { @@ -1760,25 +1760,25 @@ cy_en_prot_status_t Cy_Prot_GetPpuProgStruct(PERI_PPU_PR_Type** base, cy_en_prot * Function Name: Cy_Prot_ConfigPpuFixedGrMasterStruct ****************************************************************************//** * -* Configures a Fixed Peripheral Group Protection Unit (PPU GR) master -* protection struct with its protection attributes. +* Configures a Fixed Peripheral Group Protection Unit (PPU GR) master +* protection struct with its protection attributes. * * This function configures the master struct governing the corresponding slave * struct pair. It is a mechanism to protect the slave PPU GR struct. Since * the memory location of the slave struct is known, the address, regionSize and * subregions of the configuration struct are not applicable. * -* Note that only the user/privileged write permissions are configurable. The +* Note that only the user/privileged write permissions are configurable. The * read and execute permissions are read-only and cannot be configured. * * \note This function is applicable for CPUSS ver_1 only. * * \param base * The register base address of the protection struct being configured. -* +* * \param config * Initialization structure with all the protection attributes. -* +* * \return * Status of the function call. * @@ -1797,14 +1797,14 @@ cy_en_prot_status_t Cy_Prot_ConfigPpuFixedGrMasterStruct(PERI_PPU_GR_Type* base, { cy_en_prot_status_t status = CY_PROT_INVALID_STATE; uint32_t attReg; - + CY_ASSERT_L1(NULL != base); CY_ASSERT_L3(CY_PROT_IS_FIXED_MS_PERM_VALID(config->userPermission)); CY_ASSERT_L3(CY_PROT_IS_FIXED_MS_PERM_VALID(config->privPermission)); - + if (CY_PERI_V1) { - if(((uint32_t)config->pcMask & CY_PROT_PPU_FIXED_PC_LIMIT_MASK) != 0UL) + if(((uint32_t)config->pcMask & CY_PROT_PPU_FIXED_PC_LIMIT_MASK) != 0UL) { /* PC mask out of range - not supported in device */ status = CY_PROT_BAD_PARAM; @@ -1840,27 +1840,27 @@ cy_en_prot_status_t Cy_Prot_ConfigPpuFixedGrMasterStruct(PERI_PPU_GR_Type* base, ****************************************************************************//** * * Configures a Fixed Peripheral Group Protection Unit (PPU GR) slave -* protection struct with its protection attributes. -* -* This function configures the slave struct of a PPU GR pair, which can +* protection struct with its protection attributes. +* +* This function configures the slave struct of a PPU GR pair, which can * protect an entire peripheral MMIO group from invalid bus master accesses. * Refer to the device Technical Reference manual for details on peripheral * MMIO grouping and which peripherals belong to which groups. * -* Each fixed PPU GR is devoted to a defined MMIO group. Hence the address, +* Each fixed PPU GR is devoted to a defined MMIO group. Hence the address, * regionSize and subregions of the configuration struct are not applicable. * -* Note that the user/privileged execute accesses are read-only and are always -* enabled. +* Note that the user/privileged execute accesses are read-only and are always +* enabled. * * \note This function is applicable for CPUSS ver_1 only. * * \param base * The register base address of the protection structure being configured. -* +* * \param config * Initialization structure with all the protection attributes. -* +* * \return * Status of the function call. * @@ -1879,14 +1879,14 @@ cy_en_prot_status_t Cy_Prot_ConfigPpuFixedGrSlaveStruct(PERI_PPU_GR_Type* base, { cy_en_prot_status_t status = CY_PROT_INVALID_STATE; uint32_t attReg; - + CY_ASSERT_L1(NULL != base); CY_ASSERT_L3(CY_PROT_IS_FIXED_SL_PERM_VALID(config->userPermission)); CY_ASSERT_L3(CY_PROT_IS_FIXED_SL_PERM_VALID(config->privPermission)); - + if (CY_PERI_V1) { - if(((uint32_t)config->pcMask & CY_PROT_PPU_FIXED_PC_LIMIT_MASK) != 0UL) + if(((uint32_t)config->pcMask & CY_PROT_PPU_FIXED_PC_LIMIT_MASK) != 0UL) { /* PC mask out of range - not supported in device */ status = CY_PROT_BAD_PARAM; @@ -1923,13 +1923,13 @@ cy_en_prot_status_t Cy_Prot_ConfigPpuFixedGrSlaveStruct(PERI_PPU_GR_Type* base, * * Enables the Master PPU GR structure. * -* This is a PPU GR master struct enable function. The PPU GR protection +* This is a PPU GR master struct enable function. The PPU GR protection * settings will take effect after successful completion of this function call. * * \note This function is applicable for CPUSS ver_1 only. * * \param base -* The base address for the protection unit structure being configured. +* The base address for the protection unit structure being configured. * * \return * Status of the function call. @@ -1947,9 +1947,9 @@ cy_en_prot_status_t Cy_Prot_ConfigPpuFixedGrSlaveStruct(PERI_PPU_GR_Type* base, cy_en_prot_status_t Cy_Prot_EnablePpuFixedGrMasterStruct(PERI_PPU_GR_Type* base) { cy_en_prot_status_t status = CY_PROT_INVALID_STATE; - + CY_ASSERT_L1(NULL != base); - + if (CY_PERI_V1) { PERI_PPU_GR_ATT1(base) |= _VAL2FLD(PERI_PPU_GR_ATT1_ENABLED, CY_PROT_STRUCT_ENABLE); @@ -1967,14 +1967,14 @@ cy_en_prot_status_t Cy_Prot_EnablePpuFixedGrMasterStruct(PERI_PPU_GR_Type* base) * * Disables the Master PPU GR structure. * -* This is a PPU GR master struct disable function. The PPU GR protection -* settings will seize to take effect after successful completion of this +* This is a PPU GR master struct disable function. The PPU GR protection +* settings will seize to take effect after successful completion of this * function call. * * \note This function is applicable for CPUSS ver_1 only. * * \param base -* The base address for the protection unit structure being configured. +* The base address for the protection unit structure being configured. * * \return * Status of the function call. @@ -1992,9 +1992,9 @@ cy_en_prot_status_t Cy_Prot_EnablePpuFixedGrMasterStruct(PERI_PPU_GR_Type* base) cy_en_prot_status_t Cy_Prot_DisablePpuFixedGrMasterStruct(PERI_PPU_GR_Type* base) { cy_en_prot_status_t status = CY_PROT_INVALID_STATE; - + CY_ASSERT_L1(NULL != base); - + if (CY_PERI_V1) { PERI_PPU_GR_ATT1(base) &= ~_VAL2FLD(PERI_PPU_GR_ATT1_ENABLED, CY_PROT_STRUCT_ENABLE); @@ -2012,13 +2012,13 @@ cy_en_prot_status_t Cy_Prot_DisablePpuFixedGrMasterStruct(PERI_PPU_GR_Type* base * * Enables the Slave PPU GR structure. * -* This is a PPU GR slave struct enable function. The PPU GR protection +* This is a PPU GR slave struct enable function. The PPU GR protection * settings will take effect after successful completion of this function call. * * \note This function is applicable for CPUSS ver_1 only. * * \param base -* The base address for the protection unit structure being configured. +* The base address for the protection unit structure being configured. * * \return * Status of the function call. @@ -2034,11 +2034,11 @@ cy_en_prot_status_t Cy_Prot_DisablePpuFixedGrMasterStruct(PERI_PPU_GR_Type* base * *******************************************************************************/ cy_en_prot_status_t Cy_Prot_EnablePpuFixedGrSlaveStruct(PERI_PPU_GR_Type* base) -{ +{ cy_en_prot_status_t status = CY_PROT_INVALID_STATE; - + CY_ASSERT_L1(NULL != base); - + if (CY_PERI_V1) { PERI_PPU_GR_ATT0(base) |= _VAL2FLD(PERI_PPU_GR_ATT0_ENABLED, CY_PROT_STRUCT_ENABLE); @@ -2056,14 +2056,14 @@ cy_en_prot_status_t Cy_Prot_EnablePpuFixedGrSlaveStruct(PERI_PPU_GR_Type* base) * * Disables the Slave PPU GR structure. * -* This is a PPU GR slave struct disable function. The PPU GR protection -* settings will seize to take effect after successful completion of this +* This is a PPU GR slave struct disable function. The PPU GR protection +* settings will seize to take effect after successful completion of this * function call. * * \note This function is applicable for CPUSS ver_1 only. * * \param base -* The base address for the protection unit structure being configured. +* The base address for the protection unit structure being configured. * * \return * Status of the function call. @@ -2081,9 +2081,9 @@ cy_en_prot_status_t Cy_Prot_EnablePpuFixedGrSlaveStruct(PERI_PPU_GR_Type* base) cy_en_prot_status_t Cy_Prot_DisablePpuFixedGrSlaveStruct(PERI_PPU_GR_Type* base) { cy_en_prot_status_t status = CY_PROT_INVALID_STATE; - + CY_ASSERT_L1(NULL != base); - + if (CY_PERI_V1) { PERI_PPU_GR_ATT0(base) &= ~_VAL2FLD(PERI_PPU_GR_ATT0_ENABLED, CY_PROT_STRUCT_ENABLE); @@ -2099,25 +2099,25 @@ cy_en_prot_status_t Cy_Prot_DisablePpuFixedGrSlaveStruct(PERI_PPU_GR_Type* base) * Function Name: Cy_Prot_ConfigPpuFixedSlMasterStruct ****************************************************************************//** * -* Configures a Fixed Peripheral Slave Protection Unit (PPU SL) master -* protection struct with its protection attributes. +* Configures a Fixed Peripheral Slave Protection Unit (PPU SL) master +* protection struct with its protection attributes. * * This function configures the master struct governing the corresponding slave * struct pair. It is a mechanism to protect the slave PPU SL struct. Since * the memory location of the slave struct is known, the address, regionSize and * subregions of the configuration struct are not applicable. * -* Note that only the user/privileged write permissions are configurable. The +* Note that only the user/privileged write permissions are configurable. The * read and execute permissions are read-only and cannot be configured. * * \note This function is applicable for CPUSS ver_1 only. * * \param base * The register base address of the protection struct being configured. -* +* * \param config * Initialization structure with all the protection attributes. -* +* * \return * Status of the function call. * @@ -2136,14 +2136,14 @@ cy_en_prot_status_t Cy_Prot_ConfigPpuFixedSlMasterStruct(PERI_GR_PPU_SL_Type* ba { cy_en_prot_status_t status = CY_PROT_INVALID_STATE; uint32_t attReg; - + CY_ASSERT_L1(NULL != base); CY_ASSERT_L3(CY_PROT_IS_FIXED_MS_PERM_VALID(config->userPermission)); CY_ASSERT_L3(CY_PROT_IS_FIXED_MS_PERM_VALID(config->privPermission)); - + if (CY_PERI_V1) { - if(((uint32_t)config->pcMask & CY_PROT_PPU_FIXED_PC_LIMIT_MASK) != 0UL) + if(((uint32_t)config->pcMask & CY_PROT_PPU_FIXED_PC_LIMIT_MASK) != 0UL) { /* PC mask out of range - not supported in device */ status = CY_PROT_BAD_PARAM; @@ -2179,26 +2179,26 @@ cy_en_prot_status_t Cy_Prot_ConfigPpuFixedSlMasterStruct(PERI_GR_PPU_SL_Type* ba ****************************************************************************//** * * Configures a Fixed Peripheral Slave Protection Unit (PPU SL) slave -* protection struct with its protection attributes. -* -* This function configures the slave struct of a PPU SL pair, which can +* protection struct with its protection attributes. +* +* This function configures the slave struct of a PPU SL pair, which can * protect an entire peripheral slave instance from invalid bus master accesses. * For example, TCPWM0, TCPWM1, SCB0 and SCB1 etc. * -* Each fixed PPU SL is devoted to a defined peripheral slave. Hence the address, +* Each fixed PPU SL is devoted to a defined peripheral slave. Hence the address, * regionSize and subregions of the configuration struct are not applicable. * -* Note that the user/privileged execute accesses are read-only and are always -* enabled. +* Note that the user/privileged execute accesses are read-only and are always +* enabled. * * \note This function is applicable for CPUSS ver_1 only. * * \param base * The register base address of the protection structure being configured. -* +* * \param config * Initialization structure with all the protection attributes. -* +* * \return * Status of the function call. * @@ -2217,14 +2217,14 @@ cy_en_prot_status_t Cy_Prot_ConfigPpuFixedSlSlaveStruct(PERI_GR_PPU_SL_Type* bas { cy_en_prot_status_t status = CY_PROT_INVALID_STATE; uint32_t attReg; - + CY_ASSERT_L1(NULL != base); CY_ASSERT_L3(CY_PROT_IS_FIXED_SL_PERM_VALID(config->userPermission)); CY_ASSERT_L3(CY_PROT_IS_FIXED_SL_PERM_VALID(config->privPermission)); - + if (CY_PERI_V1) { - if(((uint32_t)config->pcMask & CY_PROT_PPU_FIXED_PC_LIMIT_MASK) != 0UL) + if(((uint32_t)config->pcMask & CY_PROT_PPU_FIXED_PC_LIMIT_MASK) != 0UL) { /* PC mask out of range - not supported in device */ status = CY_PROT_BAD_PARAM; @@ -2261,13 +2261,13 @@ cy_en_prot_status_t Cy_Prot_ConfigPpuFixedSlSlaveStruct(PERI_GR_PPU_SL_Type* bas * * Enables the Master PPU SL structure. * -* This is a PPU SL master struct enable function. The PPU SL protection +* This is a PPU SL master struct enable function. The PPU SL protection * settings will take effect after successful completion of this function call. * * \note This function is applicable for CPUSS ver_1 only. * * \param base -* The base address for the protection unit structure being configured. +* The base address for the protection unit structure being configured. * * \return * Status of the function call. @@ -2285,9 +2285,9 @@ cy_en_prot_status_t Cy_Prot_ConfigPpuFixedSlSlaveStruct(PERI_GR_PPU_SL_Type* bas cy_en_prot_status_t Cy_Prot_EnablePpuFixedSlMasterStruct(PERI_GR_PPU_SL_Type* base) { cy_en_prot_status_t status = CY_PROT_INVALID_STATE; - + CY_ASSERT_L1(NULL != base); - + if (CY_PERI_V1) { PERI_GR_PPU_SL_ATT1(base) |= _VAL2FLD(PERI_GR_PPU_SL_ATT1_ENABLED, CY_PROT_STRUCT_ENABLE); @@ -2305,14 +2305,14 @@ cy_en_prot_status_t Cy_Prot_EnablePpuFixedSlMasterStruct(PERI_GR_PPU_SL_Type* ba * * Disables the Master PPU SL structure. * -* This is a PPU SL master struct disable function. The PPU SL protection -* settings will seize to take effect after successful completion of this +* This is a PPU SL master struct disable function. The PPU SL protection +* settings will seize to take effect after successful completion of this * function call. * * \note This function is applicable for CPUSS ver_1 only. * * \param base -* The base address for the protection unit structure being configured. +* The base address for the protection unit structure being configured. * * \return * Status of the function call. @@ -2330,9 +2330,9 @@ cy_en_prot_status_t Cy_Prot_EnablePpuFixedSlMasterStruct(PERI_GR_PPU_SL_Type* ba cy_en_prot_status_t Cy_Prot_DisablePpuFixedSlMasterStruct(PERI_GR_PPU_SL_Type* base) { cy_en_prot_status_t status = CY_PROT_INVALID_STATE; - + CY_ASSERT_L1(NULL != base); - + if (CY_PERI_V1) { PERI_GR_PPU_SL_ATT1(base) &= ~_VAL2FLD(PERI_GR_PPU_SL_ATT1_ENABLED, CY_PROT_STRUCT_ENABLE); @@ -2350,13 +2350,13 @@ cy_en_prot_status_t Cy_Prot_DisablePpuFixedSlMasterStruct(PERI_GR_PPU_SL_Type* b * * Enables the Slave PPU SL structure. * -* This is a PPU SL slave struct enable function. The PPU SL protection +* This is a PPU SL slave struct enable function. The PPU SL protection * settings will take effect after successful completion of this function call. * * \note This function is applicable for CPUSS ver_1 only. * * \param base -* The base address for the protection unit structure being configured. +* The base address for the protection unit structure being configured. * * \return * Status of the function call. @@ -2372,11 +2372,11 @@ cy_en_prot_status_t Cy_Prot_DisablePpuFixedSlMasterStruct(PERI_GR_PPU_SL_Type* b * *******************************************************************************/ cy_en_prot_status_t Cy_Prot_EnablePpuFixedSlSlaveStruct(PERI_GR_PPU_SL_Type* base) -{ +{ cy_en_prot_status_t status = CY_PROT_INVALID_STATE; - + CY_ASSERT_L1(NULL != base); - + if (CY_PERI_V1) { PERI_GR_PPU_SL_ATT0(base) |= _VAL2FLD(PERI_GR_PPU_SL_ATT0_ENABLED, CY_PROT_STRUCT_ENABLE); @@ -2394,14 +2394,14 @@ cy_en_prot_status_t Cy_Prot_EnablePpuFixedSlSlaveStruct(PERI_GR_PPU_SL_Type* bas * * Disables the Slave PPU SL structure. * -* This is a PPU SL slave struct disable function. The PPU SL protection -* settings will seize to take effect after successful completion of this +* This is a PPU SL slave struct disable function. The PPU SL protection +* settings will seize to take effect after successful completion of this * function call. * * \note This function is applicable for CPUSS ver_1 only. * * \param base -* The base address for the protection unit structure being configured. +* The base address for the protection unit structure being configured. * * \return * Status of the function call. @@ -2419,9 +2419,9 @@ cy_en_prot_status_t Cy_Prot_EnablePpuFixedSlSlaveStruct(PERI_GR_PPU_SL_Type* bas cy_en_prot_status_t Cy_Prot_DisablePpuFixedSlSlaveStruct(PERI_GR_PPU_SL_Type* base) { cy_en_prot_status_t status = CY_PROT_INVALID_STATE; - + CY_ASSERT_L1(NULL != base); - + if (CY_PERI_V1) { PERI_GR_PPU_SL_ATT0(base) &= ~_VAL2FLD(PERI_GR_PPU_SL_ATT0_ENABLED, CY_PROT_STRUCT_ENABLE); @@ -2437,25 +2437,25 @@ cy_en_prot_status_t Cy_Prot_DisablePpuFixedSlSlaveStruct(PERI_GR_PPU_SL_Type* ba * Function Name: Cy_Prot_ConfigPpuFixedRgMasterStruct ****************************************************************************//** * -* Configures a Fixed Peripheral Region Protection Unit (PPU RG) master -* protection struct with its protection attributes. +* Configures a Fixed Peripheral Region Protection Unit (PPU RG) master +* protection struct with its protection attributes. * * This function configures the master struct governing the corresponding slave * struct pair. It is a mechanism to protect the slave PPU RG struct. Since * the memory location of the slave struct is known, the address, regionSize and * subregions of the configuration struct are not applicable. * -* Note that only the user/privileged write permissions are configurable. The +* Note that only the user/privileged write permissions are configurable. The * read and execute permissions are read-only and cannot be configured. * * \note This function is applicable for CPUSS ver_1 only. * * \param base * The register base address of the protection struct being configured. -* +* * \param config * Initialization structure with all the protection attributes. -* +* * \return * Status of the function call. * @@ -2474,14 +2474,14 @@ cy_en_prot_status_t Cy_Prot_ConfigPpuFixedRgMasterStruct(PERI_GR_PPU_RG_Type* ba { cy_en_prot_status_t status = CY_PROT_INVALID_STATE; uint32_t attReg; - + CY_ASSERT_L1(NULL != base); CY_ASSERT_L3(CY_PROT_IS_FIXED_MS_PERM_VALID(config->userPermission)); CY_ASSERT_L3(CY_PROT_IS_FIXED_MS_PERM_VALID(config->privPermission)); - + if (CY_PERI_V1) { - if(((uint32_t)config->pcMask & CY_PROT_PPU_FIXED_PC_LIMIT_MASK) != 0UL) + if(((uint32_t)config->pcMask & CY_PROT_PPU_FIXED_PC_LIMIT_MASK) != 0UL) { /* PC mask out of range - not supported in device */ status = CY_PROT_BAD_PARAM; @@ -2517,26 +2517,26 @@ cy_en_prot_status_t Cy_Prot_ConfigPpuFixedRgMasterStruct(PERI_GR_PPU_RG_Type* ba ****************************************************************************//** * * Configures a Fixed Peripheral Region Protection Unit (PPU RG) slave -* protection struct with its protection attributes. -* -* This function configures the slave struct of a PPU RG pair, which can +* protection struct with its protection attributes. +* +* This function configures the slave struct of a PPU RG pair, which can * protect specified regions of peripheral instances. For example, individual * DW channel structs, SMPU structs, and IPC structs etc. * -* Each fixed PPU RG is devoted to a defined peripheral region. Hence the address, +* Each fixed PPU RG is devoted to a defined peripheral region. Hence the address, * regionSize and subregions of the configuration struct are not applicable. * -* Note that the user/privileged execute accesses are read-only and are always -* enabled. +* Note that the user/privileged execute accesses are read-only and are always +* enabled. * * \note This function is applicable for CPUSS ver_1 only. * * \param base * The register base address of the protection structure being configured. -* +* * \param config * Initialization structure with all the protection attributes. -* +* * \return * Status of the function call. * @@ -2555,14 +2555,14 @@ cy_en_prot_status_t Cy_Prot_ConfigPpuFixedRgSlaveStruct(PERI_GR_PPU_RG_Type* bas { cy_en_prot_status_t status = CY_PROT_INVALID_STATE; uint32_t attReg; - + CY_ASSERT_L1(NULL != base); CY_ASSERT_L3(CY_PROT_IS_FIXED_SL_PERM_VALID(config->userPermission)); CY_ASSERT_L3(CY_PROT_IS_FIXED_SL_PERM_VALID(config->privPermission)); - + if (CY_PERI_V1) { - if(((uint32_t)config->pcMask & CY_PROT_PPU_FIXED_PC_LIMIT_MASK) != 0UL) + if(((uint32_t)config->pcMask & CY_PROT_PPU_FIXED_PC_LIMIT_MASK) != 0UL) { /* PC mask out of range - not supported in device */ status = CY_PROT_BAD_PARAM; @@ -2599,13 +2599,13 @@ cy_en_prot_status_t Cy_Prot_ConfigPpuFixedRgSlaveStruct(PERI_GR_PPU_RG_Type* bas * * Enables the Master PPU RG structure. * -* This is a PPU RG master struct enable function. The PPU RG protection +* This is a PPU RG master struct enable function. The PPU RG protection * settings will take effect after successful completion of this function call. * * \note This function is applicable for CPUSS ver_1 only. * * \param base -* The base address for the protection unit structure being configured. +* The base address for the protection unit structure being configured. * * \return * Status of the function call. @@ -2641,14 +2641,14 @@ cy_en_prot_status_t Cy_Prot_EnablePpuFixedRgMasterStruct(PERI_GR_PPU_RG_Type* ba * * Disables the Master PPU RG structure. * -* This is a PPU RG master struct disable function. The PPU RG protection -* settings will seize to take effect after successful completion of this +* This is a PPU RG master struct disable function. The PPU RG protection +* settings will seize to take effect after successful completion of this * function call. * * \note This function is applicable for CPUSS ver_1 only. * * \param base -* The base address for the protection unit structure being configured. +* The base address for the protection unit structure being configured. * * \return * Status of the function call. @@ -2666,7 +2666,7 @@ cy_en_prot_status_t Cy_Prot_EnablePpuFixedRgMasterStruct(PERI_GR_PPU_RG_Type* ba cy_en_prot_status_t Cy_Prot_DisablePpuFixedRgMasterStruct(PERI_GR_PPU_RG_Type* base) { cy_en_prot_status_t status = CY_PROT_INVALID_STATE; - + if (CY_PERI_V1) { PERI_GR_PPU_RG_ATT1(base) &= ~_VAL2FLD(PERI_GR_PPU_RG_ATT1_ENABLED, CY_PROT_STRUCT_ENABLE); @@ -2684,13 +2684,13 @@ cy_en_prot_status_t Cy_Prot_DisablePpuFixedRgMasterStruct(PERI_GR_PPU_RG_Type* b * * Enables the Slave PPU RG structure. * -* This is a PPU RG slave struct enable function. The PPU RG protection +* This is a PPU RG slave struct enable function. The PPU RG protection * settings will take effect after successful completion of this function call. * * \note This function is applicable for CPUSS ver_1 only. * * \param base -* The base address for the protection unit structure being configured. +* The base address for the protection unit structure being configured. * * \return * Status of the function call. @@ -2706,9 +2706,9 @@ cy_en_prot_status_t Cy_Prot_DisablePpuFixedRgMasterStruct(PERI_GR_PPU_RG_Type* b * *******************************************************************************/ cy_en_prot_status_t Cy_Prot_EnablePpuFixedRgSlaveStruct(PERI_GR_PPU_RG_Type* base) -{ +{ cy_en_prot_status_t status = CY_PROT_INVALID_STATE; - + if (CY_PERI_V1) { PERI_GR_PPU_RG_ATT0(base) |= _VAL2FLD(PERI_GR_PPU_RG_ATT0_ENABLED, CY_PROT_STRUCT_ENABLE); @@ -2726,14 +2726,14 @@ cy_en_prot_status_t Cy_Prot_EnablePpuFixedRgSlaveStruct(PERI_GR_PPU_RG_Type* bas * * Disables the Slave PPU RG structure. * -* This is a PPU RG slave struct disable function. The PPU RG protection -* settings will seize to take effect after successful completion of this +* This is a PPU RG slave struct disable function. The PPU RG protection +* settings will seize to take effect after successful completion of this * function call. * * \note This function is applicable for CPUSS ver_1 only. * * \param base -* The base address for the protection unit structure being configured. +* The base address for the protection unit structure being configured. * * \return * Status of the function call. @@ -2751,7 +2751,7 @@ cy_en_prot_status_t Cy_Prot_EnablePpuFixedRgSlaveStruct(PERI_GR_PPU_RG_Type* bas cy_en_prot_status_t Cy_Prot_DisablePpuFixedRgSlaveStruct(PERI_GR_PPU_RG_Type* base) { cy_en_prot_status_t status = CY_PROT_INVALID_STATE; - + if (CY_PERI_V1) { PERI_GR_PPU_RG_ATT0(base) &= ~_VAL2FLD(PERI_GR_PPU_RG_ATT0_ENABLED, CY_PROT_STRUCT_ENABLE); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_rtc.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_rtc.c index 8c9f953ee6..403fcb2792 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_rtc.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_rtc.c @@ -1,8 +1,8 @@ /***************************************************************************//** * \file cy_rtc.c -* \version 2.30 +* \version 2.30.1 * -* This file provides constants and parameter values for the APIs for the +* This file provides constants and parameter values for the APIs for the * Real-Time Clock (RTC). * ******************************************************************************** @@ -82,7 +82,7 @@ cy_en_rtc_status_t Cy_RTC_Init(cy_stc_rtc_config_t const *config) * The pointer to the RTC configuration structure, see \ref cy_stc_rtc_config_t. * * \return -* A validation check result of date and month. Returns an +* A validation check result of date and month. Returns an * error, if the date range is invalid. See \ref cy_en_rtc_status_t. * *******************************************************************************/ @@ -121,7 +121,7 @@ cy_en_rtc_status_t Cy_RTC_SetDateAndTime(cy_stc_rtc_config_t const *dateTime) { BACKUP_RTC_TIME = tmpTime; BACKUP_RTC_DATE = tmpDate; - + /* Clear the RTC Write bit to finish RTC register update */ retVal = Cy_RTC_WriteEnable(CY_RTC_WRITE_DISABLED); } @@ -136,7 +136,7 @@ cy_en_rtc_status_t Cy_RTC_SetDateAndTime(cy_stc_rtc_config_t const *dateTime) * Function Name: Cy_RTC_GetDateAndTime ****************************************************************************//** * -* Gets the current RTC time and date. The AHB RTC Time and Date register values +* Gets the current RTC time and date. The AHB RTC Time and Date register values * are stored into the *dateTime structure. * * \param dateTime @@ -153,7 +153,7 @@ void Cy_RTC_GetDateAndTime(cy_stc_rtc_config_t* dateTime) /* Read the current RTC time and date to validate the input parameters */ Cy_RTC_SyncFromRtc(); - /* Write the AHB RTC registers date and time into the local variables and + /* Write the AHB RTC registers date and time into the local variables and * updating the dateTime structure elements */ tmpTime = BACKUP_RTC_TIME; @@ -164,14 +164,14 @@ void Cy_RTC_GetDateAndTime(cy_stc_rtc_config_t* dateTime) dateTime->hrFormat = ((_FLD2BOOL(BACKUP_RTC_TIME_CTRL_12HR, tmpTime)) ? CY_RTC_12_HOURS : CY_RTC_24_HOURS); /* Read the current hour mode to know how many hour bits should be converted - * In the 24-hour mode, the hour value is presented in [21:16] bits in the + * In the 24-hour mode, the hour value is presented in [21:16] bits in the * BCD format. * In the 12-hour mode the hour value is presented in [20:16] bits in the BCD - * format and bit [21] is present: 0 - AM; 1 - PM. + * format and bit [21] is present: 0 - AM; 1 - PM. */ if (dateTime->hrFormat != CY_RTC_24_HOURS) { - dateTime->hour = + dateTime->hour = Cy_RTC_ConvertBcdToDec((tmpTime & CY_RTC_BACKUP_RTC_TIME_RTC_12HOUR) >> BACKUP_RTC_TIME_RTC_HOUR_Pos); dateTime->amPm = ((0U != (tmpTime & CY_RTC_BACKUP_RTC_TIME_RTC_PM)) ? CY_RTC_PM : CY_RTC_AM); @@ -183,7 +183,7 @@ void Cy_RTC_GetDateAndTime(cy_stc_rtc_config_t* dateTime) dateTime->amPm = CY_RTC_AM; } dateTime->dayOfWeek = Cy_RTC_ConvertBcdToDec(_FLD2VAL(BACKUP_RTC_TIME_RTC_DAY, tmpTime)); - + dateTime->date = Cy_RTC_ConvertBcdToDec(_FLD2VAL(BACKUP_RTC_DATE_RTC_DATE, tmpDate)); dateTime->month = Cy_RTC_ConvertBcdToDec(_FLD2VAL(BACKUP_RTC_DATE_RTC_MON, tmpDate)); dateTime->year = Cy_RTC_ConvertBcdToDec(_FLD2VAL(BACKUP_RTC_DATE_RTC_YEAR, tmpDate)); @@ -240,7 +240,7 @@ cy_en_rtc_status_t Cy_RTC_SetAlarmDateAndTime(cy_stc_rtc_alarm_t const *alarmDat /* Read the current RTC year to validate alarmDateTime->date */ Cy_RTC_SyncFromRtc(); - tmpYear = + tmpYear = CY_RTC_TWO_THOUSAND_YEARS + Cy_RTC_ConvertBcdToDec(_FLD2VAL(BACKUP_RTC_DATE_RTC_YEAR, BACKUP_RTC_DATE)); tmpDaysInMonth = Cy_RTC_DaysInMonth(alarmDateTime->month, tmpYear); @@ -250,9 +250,9 @@ cy_en_rtc_status_t Cy_RTC_SetAlarmDateAndTime(cy_stc_rtc_alarm_t const *alarmDat uint32_t interruptState; uint32_t tmpAlarmTime; uint32_t tmpAlarmDate; - + ConstructAlarmTimeDate(alarmDateTime, &tmpAlarmTime, &tmpAlarmDate); - + /* The RTC AHB registers can be updated only under condition that the * Write bit is set and the RTC busy bit is cleared (RTC_BUSY = 0). */ @@ -286,7 +286,7 @@ cy_en_rtc_status_t Cy_RTC_SetAlarmDateAndTime(cy_stc_rtc_alarm_t const *alarmDat * Function Name: Cy_RTC_GetAlarmDateAndTime ****************************************************************************//** * -* Returns the current alarm time and date values from the ALMx_TIME and +* Returns the current alarm time and date values from the ALMx_TIME and * ALMx_DATE registers. * * \param alarmDateTime @@ -319,37 +319,37 @@ void Cy_RTC_GetAlarmDateAndTime(cy_stc_rtc_alarm_t *alarmDateTime, cy_en_rtc_a tmpAlarmDate = BACKUP_ALM1_DATE; alarmDateTime->sec = Cy_RTC_ConvertBcdToDec(_FLD2VAL(BACKUP_ALM1_TIME_ALM_SEC, tmpAlarmTime)); - alarmDateTime->secEn = + alarmDateTime->secEn = ((_FLD2BOOL(BACKUP_ALM1_TIME_ALM_SEC_EN, tmpAlarmTime)) ? CY_RTC_ALARM_ENABLE : CY_RTC_ALARM_DISABLE); alarmDateTime->min = Cy_RTC_ConvertBcdToDec(_FLD2VAL(BACKUP_ALM1_TIME_ALM_MIN, tmpAlarmTime)); - alarmDateTime->minEn = + alarmDateTime->minEn = ((_FLD2BOOL(BACKUP_ALM1_TIME_ALM_MIN_EN, tmpAlarmTime)) ? CY_RTC_ALARM_ENABLE : CY_RTC_ALARM_DISABLE); /* Read the current hour mode to know how many hour bits to convert. - * In the 24-hour mode, the hour value is presented in [21:16] bits in + * In the 24-hour mode, the hour value is presented in [21:16] bits in * the BCD format. - * In the 12-hour mode, the hour value is presented in [20:16] bits in + * In the 12-hour mode, the hour value is presented in [20:16] bits in * the BCD format and bit [21] is present: 0 - AM; 1 - PM. */ if (curHoursFormat != CY_RTC_24_HOURS) { - alarmDateTime->hour = - Cy_RTC_ConvertBcdToDec((tmpAlarmTime & CY_RTC_BACKUP_RTC_TIME_RTC_12HOUR) + alarmDateTime->hour = + Cy_RTC_ConvertBcdToDec((tmpAlarmTime & CY_RTC_BACKUP_RTC_TIME_RTC_12HOUR) >> BACKUP_ALM1_TIME_ALM_HOUR_Pos); - /* In the structure, the hour value should be presented in the 24-hour mode. In - * that condition the firmware checks the AM/PM status and adds 12 hours to + /* In the structure, the hour value should be presented in the 24-hour mode. In + * that condition the firmware checks the AM/PM status and adds 12 hours to * the converted hour value if the PM bit is set. */ - if ((alarmDateTime->hour < CY_RTC_HOURS_PER_HALF_DAY) && + if ((alarmDateTime->hour < CY_RTC_HOURS_PER_HALF_DAY) && (0U != (BACKUP_ALM1_TIME & CY_RTC_BACKUP_RTC_TIME_RTC_PM))) { alarmDateTime->hour += CY_RTC_HOURS_PER_HALF_DAY; } /* Set zero hour, as the 12 A hour is zero hour in 24-hour format */ - if ((alarmDateTime->hour == CY_RTC_HOURS_PER_HALF_DAY) && + if ((alarmDateTime->hour == CY_RTC_HOURS_PER_HALF_DAY) && (0U == (BACKUP_ALM1_TIME & CY_RTC_BACKUP_RTC_TIME_RTC_PM))) { alarmDateTime->hour = 0U; @@ -360,22 +360,22 @@ void Cy_RTC_GetAlarmDateAndTime(cy_stc_rtc_alarm_t *alarmDateTime, cy_en_rtc_a { alarmDateTime->hour = Cy_RTC_ConvertBcdToDec(_FLD2VAL(BACKUP_ALM1_TIME_ALM_HOUR, tmpAlarmTime)); } - alarmDateTime->hourEn = + alarmDateTime->hourEn = ((_FLD2BOOL(BACKUP_ALM1_TIME_ALM_HOUR_EN, tmpAlarmTime)) ? CY_RTC_ALARM_ENABLE : CY_RTC_ALARM_DISABLE); - + alarmDateTime->dayOfWeek = Cy_RTC_ConvertBcdToDec(_FLD2VAL(BACKUP_ALM1_TIME_ALM_DAY, tmpAlarmTime)); alarmDateTime->dayOfWeekEn = ((_FLD2BOOL(BACKUP_ALM1_TIME_ALM_DAY_EN, tmpAlarmTime)) ? CY_RTC_ALARM_ENABLE : CY_RTC_ALARM_DISABLE); alarmDateTime->date = Cy_RTC_ConvertBcdToDec(_FLD2VAL(BACKUP_ALM1_DATE_ALM_DATE, tmpAlarmDate)); - alarmDateTime->dateEn = + alarmDateTime->dateEn = ((_FLD2BOOL(BACKUP_ALM1_DATE_ALM_DATE_EN, tmpAlarmDate)) ? CY_RTC_ALARM_ENABLE : CY_RTC_ALARM_DISABLE); - alarmDateTime->month = Cy_RTC_ConvertBcdToDec(_FLD2VAL(BACKUP_ALM1_DATE_ALM_MON, tmpAlarmDate)); - alarmDateTime->monthEn = + alarmDateTime->month = Cy_RTC_ConvertBcdToDec(_FLD2VAL(BACKUP_ALM1_DATE_ALM_MON, tmpAlarmDate)); + alarmDateTime->monthEn = ((_FLD2BOOL(BACKUP_ALM1_DATE_ALM_MON_EN, tmpAlarmDate)) ? CY_RTC_ALARM_ENABLE : CY_RTC_ALARM_DISABLE); - alarmDateTime->almEn = + alarmDateTime->almEn = ((_FLD2BOOL(BACKUP_ALM1_DATE_ALM_EN, tmpAlarmDate)) ? CY_RTC_ALARM_ENABLE : CY_RTC_ALARM_DISABLE); } else @@ -384,17 +384,17 @@ void Cy_RTC_GetAlarmDateAndTime(cy_stc_rtc_alarm_t *alarmDateTime, cy_en_rtc_a tmpAlarmDate = BACKUP_ALM2_DATE; alarmDateTime->sec = Cy_RTC_ConvertBcdToDec(_FLD2VAL(BACKUP_ALM2_TIME_ALM_SEC, tmpAlarmTime)); - alarmDateTime->secEn = + alarmDateTime->secEn = ((_FLD2BOOL(BACKUP_ALM2_TIME_ALM_SEC_EN, tmpAlarmTime)) ? CY_RTC_ALARM_ENABLE : CY_RTC_ALARM_DISABLE); alarmDateTime->min = Cy_RTC_ConvertBcdToDec(_FLD2VAL(BACKUP_ALM2_TIME_ALM_MIN, tmpAlarmTime)); - alarmDateTime->minEn = + alarmDateTime->minEn = ((_FLD2BOOL(BACKUP_ALM2_TIME_ALM_MIN_EN, tmpAlarmTime)) ? CY_RTC_ALARM_ENABLE : CY_RTC_ALARM_DISABLE); /* Read the current hour mode to know how many hour bits to convert. - * In the 24-hour mode, the hour value is presented in [21:16] bits in + * In the 24-hour mode, the hour value is presented in [21:16] bits in * the BCD format. - * In the 12-hour mode the hour value is presented in [20:16] bits in + * In the 12-hour mode the hour value is presented in [20:16] bits in * the BCD format and bit [21] is present: 0 - AM; 1 - PM. */ if (curHoursFormat != CY_RTC_24_HOURS) @@ -402,17 +402,17 @@ void Cy_RTC_GetAlarmDateAndTime(cy_stc_rtc_alarm_t *alarmDateTime, cy_en_rtc_a alarmDateTime->hour = Cy_RTC_ConvertBcdToDec((tmpAlarmTime & CY_RTC_BACKUP_RTC_TIME_RTC_12HOUR) >> BACKUP_ALM2_TIME_ALM_HOUR_Pos); - /* In the structure, the hour value should be presented in the 24-hour mode. In - * that condition the firmware checks the AM/PM status and adds 12 hours to + /* In the structure, the hour value should be presented in the 24-hour mode. In + * that condition the firmware checks the AM/PM status and adds 12 hours to * the converted hour value if the PM bit is set. */ - if ((alarmDateTime->hour < CY_RTC_HOURS_PER_HALF_DAY) && + if ((alarmDateTime->hour < CY_RTC_HOURS_PER_HALF_DAY) && (0U != (BACKUP_ALM2_TIME & CY_RTC_BACKUP_RTC_TIME_RTC_PM))) { alarmDateTime->hour += CY_RTC_HOURS_PER_HALF_DAY; } /* Set zero hour, as the 12 am hour is zero hour in 24-hour format */ - else if ((alarmDateTime->hour == CY_RTC_HOURS_PER_HALF_DAY) && + else if ((alarmDateTime->hour == CY_RTC_HOURS_PER_HALF_DAY) && (0U == (BACKUP_ALM2_TIME & CY_RTC_BACKUP_RTC_TIME_RTC_PM))) { alarmDateTime->hour = 0U; @@ -426,22 +426,22 @@ void Cy_RTC_GetAlarmDateAndTime(cy_stc_rtc_alarm_t *alarmDateTime, cy_en_rtc_a { alarmDateTime->hour = Cy_RTC_ConvertBcdToDec(_FLD2VAL(BACKUP_ALM2_TIME_ALM_HOUR, tmpAlarmTime)); } - alarmDateTime->hourEn = + alarmDateTime->hourEn = ((_FLD2BOOL(BACKUP_ALM2_TIME_ALM_HOUR_EN, tmpAlarmTime)) ? CY_RTC_ALARM_ENABLE : CY_RTC_ALARM_DISABLE); - + alarmDateTime->dayOfWeek = Cy_RTC_ConvertBcdToDec(_FLD2VAL(BACKUP_ALM2_TIME_ALM_DAY, tmpAlarmTime)); alarmDateTime->dayOfWeekEn = ((_FLD2BOOL(BACKUP_ALM2_TIME_ALM_DAY_EN, tmpAlarmTime)) ? CY_RTC_ALARM_ENABLE : CY_RTC_ALARM_DISABLE); alarmDateTime->date = Cy_RTC_ConvertBcdToDec(_FLD2VAL(BACKUP_ALM2_DATE_ALM_DATE, tmpAlarmDate)); - alarmDateTime->dateEn = + alarmDateTime->dateEn = ((_FLD2BOOL(BACKUP_ALM2_DATE_ALM_DATE_EN, tmpAlarmDate)) ? CY_RTC_ALARM_ENABLE : CY_RTC_ALARM_DISABLE); - alarmDateTime->month = Cy_RTC_ConvertBcdToDec(_FLD2VAL(BACKUP_ALM2_DATE_ALM_MON, tmpAlarmDate)); - alarmDateTime->monthEn = + alarmDateTime->month = Cy_RTC_ConvertBcdToDec(_FLD2VAL(BACKUP_ALM2_DATE_ALM_MON, tmpAlarmDate)); + alarmDateTime->monthEn = ((_FLD2BOOL(BACKUP_ALM2_DATE_ALM_MON_EN, tmpAlarmDate)) ? CY_RTC_ALARM_ENABLE : CY_RTC_ALARM_DISABLE); - alarmDateTime->almEn = + alarmDateTime->almEn = ((_FLD2BOOL(BACKUP_ALM2_DATE_ALM_EN, tmpAlarmDate)) ? CY_RTC_ALARM_ENABLE : CY_RTC_ALARM_DISABLE); } } @@ -451,7 +451,7 @@ void Cy_RTC_GetAlarmDateAndTime(cy_stc_rtc_alarm_t *alarmDateTime, cy_en_rtc_a * Function Name: Cy_RTC_SetDateAndTimeDirect ****************************************************************************//** * -* Sets the time and date values into the RTC_TIME and RTC_DATE registers using +* Sets the time and date values into the RTC_TIME and RTC_DATE registers using * direct time parameters. * * \param sec The second valid range is [0-59]. @@ -459,14 +459,14 @@ void Cy_RTC_GetAlarmDateAndTime(cy_stc_rtc_alarm_t *alarmDateTime, cy_en_rtc_a * \param min The minute valid range is [0-59]. * * \param hour -* The hour valid range is [0-23]. This parameter should be presented in the +* The hour valid range is [0-23]. This parameter should be presented in the * 24-hour format. * * The function reads the current 12/24-hour mode, then converts the hour value * properly as the mode. * * \param date -* The date valid range is [1-31], if the month of February is +* The date valid range is [1-31], if the month of February is * selected as the Month parameter, then the valid range is [0-29]. * * \param month The month valid range is [1-12]. @@ -474,13 +474,13 @@ void Cy_RTC_GetAlarmDateAndTime(cy_stc_rtc_alarm_t *alarmDateTime, cy_en_rtc_a * \param year The year valid range is [0-99]. * * \return -* A validation check result of date and month. Returns an -* error, if the date range is invalid or the RTC time and date set was +* A validation check result of date and month. Returns an +* error, if the date range is invalid or the RTC time and date set was * cancelled: the RTC Write bit was not set, the RTC was synchronizing. * See \ref cy_en_rtc_status_t. * *******************************************************************************/ -cy_en_rtc_status_t Cy_RTC_SetDateAndTimeDirect(uint32_t sec, uint32_t min, uint32_t hour, +cy_en_rtc_status_t Cy_RTC_SetDateAndTimeDirect(uint32_t sec, uint32_t min, uint32_t hour, uint32_t date, uint32_t month, uint32_t year) { uint32_t tmpDaysInMonth; @@ -501,14 +501,14 @@ cy_en_rtc_status_t Cy_RTC_SetDateAndTimeDirect(uint32_t sec, uint32_t min, uint3 uint32_t tmpTime; uint32_t tmpDate; uint32_t interruptState; - + /* Fill the date and time structure */ curTimeAndDate.sec = sec; curTimeAndDate.min = min; - + /* Read the current hour mode */ Cy_RTC_SyncFromRtc(); - + if (CY_RTC_12_HOURS != Cy_RTC_GetHoursFormat()) { curTimeAndDate.hrFormat = CY_RTC_24_HOURS; @@ -521,18 +521,18 @@ cy_en_rtc_status_t Cy_RTC_SetDateAndTimeDirect(uint32_t sec, uint32_t min, uint3 /* Convert the 24-hour format input value into the 12-hour format */ if (hour >= CY_RTC_HOURS_PER_HALF_DAY) { - /* The current hour is more than 12 or equal 12, in the 24-hour - * format. Set the PM bit and convert the hour: hour = hour - 12, + /* The current hour is more than 12 or equal 12, in the 24-hour + * format. Set the PM bit and convert the hour: hour = hour - 12, * except that the hour is 12. */ - curTimeAndDate.hour = + curTimeAndDate.hour = (hour > CY_RTC_HOURS_PER_HALF_DAY) ? ((uint32_t) hour - CY_RTC_HOURS_PER_HALF_DAY) : hour; curTimeAndDate.amPm = CY_RTC_PM; } else { - /* The current hour is less than 12 AM. The zero hour is equal + /* The current hour is less than 12 AM. The zero hour is equal * to 12:00 AM */ curTimeAndDate.hour = ((hour == 0U) ? CY_RTC_HOURS_PER_HALF_DAY : hour); @@ -570,8 +570,8 @@ cy_en_rtc_status_t Cy_RTC_SetDateAndTimeDirect(uint32_t sec, uint32_t min, uint3 * Function Name: Cy_RTC_SetAlarmDateAndTimeDirect ****************************************************************************//** * -* Sets alarm time and date values into the ALMx_TIME and ALMx_DATE -* registers using direct time parameters. ALM_DAY_EN is default 0 (=ignore) for +* Sets alarm time and date values into the ALMx_TIME and ALMx_DATE +* registers using direct time parameters. ALM_DAY_EN is default 0 (=ignore) for * this function. * * \param sec The alarm second valid range is [0-59]. @@ -580,7 +580,7 @@ cy_en_rtc_status_t Cy_RTC_SetDateAndTimeDirect(uint32_t sec, uint32_t min, uint3 * * \param hour * The valid range is [0-23]. -* This parameter type is always in the 24-hour type. This function reads the +* This parameter type is always in the 24-hour type. This function reads the * current 12/24-hour mode, then converts the hour value properly as the mode. * * \param date @@ -593,11 +593,11 @@ cy_en_rtc_status_t Cy_RTC_SetDateAndTimeDirect(uint32_t sec, uint32_t min, uint3 * The alarm index to be configured, see \ref cy_en_rtc_alarm_t. * * \return -* A validation check result of date and month. Returns an +* A validation check result of date and month. Returns an * error, if the date range is invalid. See \ref cy_en_rtc_status_t. * *******************************************************************************/ -cy_en_rtc_status_t Cy_RTC_SetAlarmDateAndTimeDirect(uint32_t sec, uint32_t min, uint32_t hour, +cy_en_rtc_status_t Cy_RTC_SetAlarmDateAndTimeDirect(uint32_t sec, uint32_t min, uint32_t hour, uint32_t date, uint32_t month, cy_en_rtc_alarm_t alarmIndex) { uint32_t tmpDaysInMonth; @@ -609,7 +609,7 @@ cy_en_rtc_status_t Cy_RTC_SetAlarmDateAndTimeDirect(uint32_t sec, uint32_t min, CY_ASSERT_L3(CY_RTC_IS_HOUR_VALID(hour)); CY_ASSERT_L3(CY_RTC_IS_MONTH_VALID(month)); CY_ASSERT_L3(CY_RTC_IS_ALARM_IDX_VALID(alarmIndex)); - + /* Read the current time to validate the input parameters */ Cy_RTC_SyncFromRtc(); @@ -625,7 +625,7 @@ cy_en_rtc_status_t Cy_RTC_SetAlarmDateAndTimeDirect(uint32_t sec, uint32_t min, uint32_t tmpAlarmDate; uint32_t interruptState; cy_stc_rtc_alarm_t alarmDateTime; - + /* Fill the alarm structure */ alarmDateTime.sec = sec; alarmDateTime.secEn = CY_RTC_ALARM_ENABLE; @@ -678,7 +678,7 @@ cy_en_rtc_status_t Cy_RTC_SetAlarmDateAndTimeDirect(uint32_t sec, uint32_t min, * * Sets the 12/24-hour mode. * -* \param hoursFormat +* \param hoursFormat * The current hour format, see \ref cy_en_rtc_hours_format_t. * * \return @@ -691,12 +691,12 @@ cy_en_rtc_status_t Cy_RTC_SetHoursFormat(cy_en_rtc_hours_format_t hoursFormat) cy_en_rtc_status_t retVal = CY_RTC_BAD_PARAM; CY_ASSERT_L3(CY_RTC_IS_HRS_FORMAT_VALID(hoursFormat)); - + /* Read the current time to validate the input parameters */ Cy_RTC_SyncFromRtc(); curTime = BACKUP_RTC_TIME; - /* Hour format can be changed in condition that current hour format is not + /* Hour format can be changed in condition that current hour format is not * the same as requested in function argument */ if (hoursFormat != Cy_RTC_GetHoursFormat()) @@ -709,7 +709,7 @@ cy_en_rtc_status_t Cy_RTC_SetHoursFormat(cy_en_rtc_hours_format_t hoursFormat) hourValue = Cy_RTC_ConvertBcdToDec(_FLD2VAL(BACKUP_RTC_TIME_RTC_HOUR, curTime)); if (hourValue >= CY_RTC_HOURS_PER_HALF_DAY) { - /* The current hour is more than 12 or equal 12 in the 24-hour + /* The current hour is more than 12 or equal 12 in the 24-hour * mode. Set the PM bit and convert the hour: hour = hour - 12. */ hourValue = (uint32_t) (hourValue - CY_RTC_HOURS_PER_HALF_DAY); @@ -720,11 +720,11 @@ cy_en_rtc_status_t Cy_RTC_SetHoursFormat(cy_en_rtc_hours_format_t hoursFormat) } else if (hourValue < 1U) { - /* The current hour in the 24-hour mode is 0 which is equal + /* The current hour in the 24-hour mode is 0 which is equal * to 12:00 AM */ curTime = - (_CLR_SET_FLD32U(curTime, BACKUP_RTC_TIME_RTC_HOUR, + (_CLR_SET_FLD32U(curTime, BACKUP_RTC_TIME_RTC_HOUR, Cy_RTC_ConvertDecToBcd(CY_RTC_HOURS_PER_HALF_DAY))); /* Set the AM bit */ @@ -743,8 +743,8 @@ cy_en_rtc_status_t Cy_RTC_SetHoursFormat(cy_en_rtc_hours_format_t hoursFormat) else { /* Mask the AM/PM bit as the hour value is in [20:16] bits */ - hourValue = - Cy_RTC_ConvertBcdToDec(_FLD2VAL(BACKUP_RTC_TIME_RTC_HOUR, + hourValue = + Cy_RTC_ConvertBcdToDec(_FLD2VAL(BACKUP_RTC_TIME_RTC_HOUR, (curTime & (uint32_t) ~CY_RTC_BACKUP_RTC_TIME_RTC_PM))); /* Add 12 hours in condition that current time is in PM period */ @@ -763,8 +763,8 @@ cy_en_rtc_status_t Cy_RTC_SetHoursFormat(cy_en_rtc_hours_format_t hoursFormat) curTime &= (uint32_t) ~BACKUP_RTC_TIME_CTRL_12HR_Msk; } - /* Writing corrected hour value and hour format bit into the RTC AHB - * register. The RTC AHB register can be updated only under condition + /* Writing corrected hour value and hour format bit into the RTC AHB + * register. The RTC AHB register can be updated only under condition * that the Write bit is set and the RTC busy bit is cleared * (CY_RTC_BUSY = 0). */ @@ -788,31 +788,31 @@ cy_en_rtc_status_t Cy_RTC_SetHoursFormat(cy_en_rtc_hours_format_t hoursFormat) * Function Name: Cy_RTC_SelectFrequencyPrescaler() ****************************************************************************//** * -* Selects the RTC pre-scaler value and changes its clock frequency. +* Selects the RTC pre-scaler value and changes its clock frequency. * If the external 32.768 kHz WCO is absent on the board, the RTC can -* be driven by a 32.768kHz square clock source or an external 50-Hz or 60-Hz +* be driven by a 32.768kHz square clock source or an external 50-Hz or 60-Hz * sine-wave clock source, for example the wall AC frequency. * * \param clkSel clock frequency, see \ref cy_en_rtc_clock_freq_t. * * In addition to generating the 32.768 kHz clock from external crystals, the WCO -* can be sourced by an external clock source (50 Hz or 60Hz), even the wall AC +* can be sourced by an external clock source (50 Hz or 60Hz), even the wall AC * frequency as a timebase. The API helps select between the RTC sources: * * A 32.768 kHz digital clock source. * * An external 50-Hz or 60-Hz sine-wave clock source. * -* If you want to use an external 50-Hz or 60-Hz sine-wave clock source to +* If you want to use an external 50-Hz or 60-Hz sine-wave clock source to * drive the RTC, the next procedure is required: * -# Disable the WCO
* -# Bypass the WCO using the Cy_SysClk_WcoBypass() function. -* -# Configure both wco_out and wco_in pins. Note that only one of the wco pins -* should be driven and the other wco pin should be floating, which depends on +* -# Configure both wco_out and wco_in pins. Note that only one of the wco pins +* should be driven and the other wco pin should be floating, which depends on * the source that drives the RTC (*1). -* -# Call Cy_RTC_SelectFrequencyPrescaler(CY_RTC_FREQ_60_HZ), if you want to +* -# Call Cy_RTC_SelectFrequencyPrescaler(CY_RTC_FREQ_60_HZ), if you want to * drive the WCO, for example, with a 60 Hz source. -* -# Enable the WCO. +* -# Enable the WCO. * -* If you want to use the WCO after using an external 50-Hz or 60-Hz sine-wave +* If you want to use the WCO after using an external 50-Hz or 60-Hz sine-wave * clock source: * -# Disable the WCO. * -# Switch-off the WCO bypass using the Cy_SysClk_WcoBypass() function. @@ -820,14 +820,14 @@ cy_en_rtc_status_t Cy_RTC_SetHoursFormat(cy_en_rtc_hours_format_t hoursFormat) * -# Call Cy_RTC_SelectFrequencyPrescaler(CY_RTC_FREQ_WCO_32768_HZ). * -# Enable the WCO. * -* (1) - Refer to the device TRM to know how to configure the wco pins properly +* (1) - Refer to the device TRM to know how to configure the wco pins properly * and which wco pin should be driven/floating. * -* \warning -* There is a limitation to the external clock source frequencies. Only two +* \warning +* There is a limitation to the external clock source frequencies. Only two * frequencies are allowed - 50 Hz or 60 Hz. Note that this limitation is related -* to the RTC pre-scaling feature presented in this function. This -* limitation is not related to WCO external clock sources which can drive the +* to the RTC pre-scaling feature presented in this function. This +* limitation is not related to WCO external clock sources which can drive the * WCO in Bypass mode. * *******************************************************************************/ @@ -842,19 +842,19 @@ void Cy_RTC_SelectFrequencyPrescaler(cy_en_rtc_clock_freq_t clkSel) /******************************************************************************* * Function Name: Cy_RTC_EnableDstTime ****************************************************************************//** -* -* The function sets the DST time and configures the ALARM2 interrupt register -* with the appropriate DST time. This function sets the DST stop time if the -* current time is already in the DST period. The DST period is a period of time -* between the DST start time and DST stop time. The DST start time and DST stop -* time is presented in the DST configuration structure, +* +* The function sets the DST time and configures the ALARM2 interrupt register +* with the appropriate DST time. This function sets the DST stop time if the +* current time is already in the DST period. The DST period is a period of time +* between the DST start time and DST stop time. The DST start time and DST stop +* time is presented in the DST configuration structure, * see \ref cy_stc_rtc_dst_t. * * \param dstTime * The DST configuration structure, see \ref cy_stc_rtc_dst_t. * * \param timeDate -* The time and date structure. The the appropriate DST time is +* The time and date structure. The the appropriate DST time is * set based on this time and date, see \ref cy_stc_rtc_config_t. * * \return @@ -892,11 +892,11 @@ cy_en_rtc_status_t Cy_RTC_EnableDstTime(cy_stc_rtc_dst_t const *dstTime, cy_stc_ * the DST stop, then this function should be called with the DST stop time. * Used by the \ref Cy_RTC_EnableDstTime and \ref Cy_RTC_DstInterrupt functions. * -* If the time format(.format) is relative option(=0), the -* RelativeToFixed() is called to convert to a fixed date. +* If the time format(.format) is relative option(=0), the +* RelativeToFixed() is called to convert to a fixed date. * -* \param nextDst -* The structure with time at which a next DST event should occur +* \param nextDst +* The structure with time at which a next DST event should occur * (ALARM2 interrupt should occur). See \ref cy_stc_rtc_config_t. * * \return @@ -916,7 +916,7 @@ cy_en_rtc_status_t Cy_RTC_SetNextDstTime(cy_stc_rtc_dst_format_t const *nextDst) /* Configure an alarm structure based on the DST structure */ dstAlarmTimeAndDate.sec = 0U; - dstAlarmTimeAndDate.secEn = CY_RTC_ALARM_ENABLE; + dstAlarmTimeAndDate.secEn = CY_RTC_ALARM_ENABLE; dstAlarmTimeAndDate.min = 0U; dstAlarmTimeAndDate.minEn = CY_RTC_ALARM_ENABLE; dstAlarmTimeAndDate.hour = nextDst->hour; @@ -942,7 +942,7 @@ cy_en_rtc_status_t Cy_RTC_SetNextDstTime(cy_stc_rtc_dst_format_t const *nextDst) { retVal = Cy_RTC_SetAlarmDateAndTime(&dstAlarmTimeAndDate, CY_RTC_ALARM_2); --tryesToSetup; - + /* Delay after try to set the DST */ Cy_SysLib_DelayUs(CY_RTC_DELAY_AFTER_DST_US); } @@ -963,14 +963,14 @@ cy_en_rtc_status_t Cy_RTC_SetNextDstTime(cy_stc_rtc_dst_format_t const *nextDst) * * A low-level DST function returns the current DST status using given time * information. This function is used in the initial state of a system. -* If the DST is enabled, the system sets the DST start or stop as a result of +* If the DST is enabled, the system sets the DST start or stop as a result of * this function. * Used by the \ref Cy_RTC_EnableDstTime and \ref Cy_RTC_DstInterrupt functions. * * \param dstTime The DST configuration structure, see \ref cy_stc_rtc_dst_t. * * \param timeDate -* The time and date structure. The the appropriate DST time is +* The time and date structure. The the appropriate DST time is * set based on this time and date, see \ref cy_stc_rtc_config_t. * * \return @@ -982,14 +982,14 @@ bool Cy_RTC_GetDstStatus(cy_stc_rtc_dst_t const *dstTime, cy_stc_rtc_config_t co { uint32_t dstStartTime; uint32_t currentTime; - uint32_t dstStopTime; + uint32_t dstStopTime; uint32_t dstStartDayOfMonth; uint32_t dstStopDayOfMonth; bool status = false; CY_ASSERT_L1(NULL != dstTime); CY_ASSERT_L1(NULL != timeDate); - + /* Calculate a day-of-month value for the relative DST start structure */ if (CY_RTC_DST_RELATIVE != dstTime->startDst.format) { @@ -1010,9 +1010,9 @@ bool Cy_RTC_GetDstStatus(cy_stc_rtc_dst_t const *dstTime, cy_stc_rtc_config_t co dstStopDayOfMonth = RelativeToFixed(&dstTime->stopDst); } - /* The function forms the date and time values for the DST start time, - * the DST Stop Time and for the Current Time. The function that compares - * the three formed values returns "true" under condition that: + /* The function forms the date and time values for the DST start time, + * the DST Stop Time and for the Current Time. The function that compares + * the three formed values returns "true" under condition that: * dstStartTime < currentTime < dstStopTime. * The date and time value are formed this way: * [13-10] - Month @@ -1066,14 +1066,14 @@ bool Cy_RTC_GetDstStatus(cy_stc_rtc_dst_t const *dstTime, cy_stc_rtc_config_t co * Function Name: Cy_RTC_Alarm1Interrupt ****************************************************************************//** * -* A blank weak interrupt handler function which indicates assert of the RTC +* A blank weak interrupt handler function which indicates assert of the RTC * alarm 1 interrupt. -* -* Function implementation should be defined in user source code in condition -* that such event handler is required. If such event is not required user +* +* Function implementation should be defined in user source code in condition +* that such event handler is required. If such event is not required user * should not do any actions. * -* This function is called in the general RTC interrupt handler +* This function is called in the general RTC interrupt handler * Cy_RTC_Interrupt() function. * *******************************************************************************/ @@ -1087,16 +1087,16 @@ __WEAK void Cy_RTC_Alarm1Interrupt(void) * Function Name: Cy_RTC_Alarm2Interrupt ****************************************************************************//** * -* A blank weak interrupt handler function which indicates assert of the RTC +* A blank weak interrupt handler function which indicates assert of the RTC * alarm 2 interrupt. -* -* Function implementation should be defined in user source code in condition -* that such event handler is required. If such event is not required user +* +* Function implementation should be defined in user source code in condition +* that such event handler is required. If such event is not required user * should not do any actions. * -* This function is called in the general RTC interrupt handler -* Cy_RTC_Interrupt() function. Cy_RTC_Alarm2Interrupt() function is -* ignored in Cy_RTC_Interrupt() function if DST is enabled. Refer to +* This function is called in the general RTC interrupt handler +* Cy_RTC_Interrupt() function. Cy_RTC_Alarm2Interrupt() function is +* ignored in Cy_RTC_Interrupt() function if DST is enabled. Refer to * Cy_RTC_Interrupt() description. * *******************************************************************************/ @@ -1109,11 +1109,11 @@ __WEAK void Cy_RTC_Alarm2Interrupt(void) /******************************************************************************* * Function Name: Cy_RTC_DstInterrupt ****************************************************************************//** -* -* This is a processing handler against the DST event. It adjusts the current +* +* This is a processing handler against the DST event. It adjusts the current * time using the DST start/stop parameters and registers the next DST event time * into the ALARM2 interrupt. -* +* * \param dstTime The DST configuration structure, see \ref cy_stc_rtc_dst_t. * *******************************************************************************/ @@ -1125,40 +1125,40 @@ void Cy_RTC_DstInterrupt(cy_stc_rtc_dst_t const *dstTime) if (Cy_RTC_GetDstStatus(dstTime, &curDateTime)) { - /* Under condition that the DST start time was selected as 23:00, and - * the time adjusting occurs, the other time and date values should be + /* Under condition that the DST start time was selected as 23:00, and + * the time adjusting occurs, the other time and date values should be * corrected (day of the week, date, month and year). */ if (curDateTime.hour > CY_RTC_MAX_HOURS_24H) { - /* Incrementing day of the week value as hour adjusted next day of - * the week and date. Correcting hour value as its incrementation + /* Incrementing day of the week value as hour adjusted next day of + * the week and date. Correcting hour value as its incrementation * adjusted it out of valid range [0-23]. */ curDateTime.dayOfWeek++; curDateTime.hour = 0U; - /* Correct a day of the week if its incrementation adjusted it out + /* Correct a day of the week if its incrementation adjusted it out * of valid range [1-7]. */ if (curDateTime.dayOfWeek > CY_RTC_SATURDAY) { curDateTime.dayOfWeek = CY_RTC_SUNDAY; } - + curDateTime.date++; /* Correct a day of a month if its incrementation adjusted it out of * the valid range [1-31]. Increment month value. */ - if (curDateTime.date > Cy_RTC_DaysInMonth(curDateTime.month, + if (curDateTime.date > Cy_RTC_DaysInMonth(curDateTime.month, (curDateTime.year + CY_RTC_TWO_THOUSAND_YEARS))) { curDateTime.date = CY_RTC_FIRST_DAY_OF_MONTH; curDateTime.month++; } - /* Correct a month if its incrementation adjusted it out of the + /* Correct a month if its incrementation adjusted it out of the * valid range [1-12]. Increment year value. */ if (curDateTime.month > CY_RTC_MONTHS_PER_YEAR) @@ -1171,7 +1171,7 @@ void Cy_RTC_DstInterrupt(cy_stc_rtc_dst_t const *dstTime) { curDateTime.hour++; } - + (void) Cy_RTC_SetDateAndTime(&curDateTime); (void) Cy_RTC_SetNextDstTime(&dstTime->stopDst); } @@ -1179,14 +1179,14 @@ void Cy_RTC_DstInterrupt(cy_stc_rtc_dst_t const *dstTime) { if (curDateTime.hour < 1U) { - /* Decrementing day of the week time and date values as hour - * adjusted next day of the week and date. Correct hour value as - * its incrementation adjusted it out of valid range [0-23]. + /* Decrementing day of the week time and date values as hour + * adjusted next day of the week and date. Correct hour value as + * its incrementation adjusted it out of valid range [0-23]. */ curDateTime.hour = CY_RTC_MAX_HOURS_24H; curDateTime.dayOfWeek--; - /* Correct a day of the week if its incrementation adjusted it out + /* Correct a day of the week if its incrementation adjusted it out * of the valid range [1-7]. */ if (curDateTime.dayOfWeek < CY_RTC_SUNDAY) @@ -1201,12 +1201,12 @@ void Cy_RTC_DstInterrupt(cy_stc_rtc_dst_t const *dstTime) */ if (curDateTime.date < CY_RTC_FIRST_DAY_OF_MONTH) { - curDateTime.date = + curDateTime.date = Cy_RTC_DaysInMonth(curDateTime.month, (curDateTime.year + CY_RTC_TWO_THOUSAND_YEARS)); curDateTime.month--; } - /* Correct a month if its increment pushed it out of the valid + /* Correct a month if its increment pushed it out of the valid * range [1-12]. Decrement year value. */ if (curDateTime.month < CY_RTC_JANUARY) @@ -1219,7 +1219,7 @@ void Cy_RTC_DstInterrupt(cy_stc_rtc_dst_t const *dstTime) { curDateTime.hour--; } - + (void) Cy_RTC_SetDateAndTime(&curDateTime); (void) Cy_RTC_SetNextDstTime(&dstTime->startDst); } @@ -1232,11 +1232,11 @@ void Cy_RTC_DstInterrupt(cy_stc_rtc_dst_t const *dstTime) * * This is a weak function and it should be redefined in user source code * in condition that such event handler is required. -* By calling this function, it indicates the year reached 2100. It +* By calling this function, it indicates the year reached 2100. It * should add an adjustment to avoid the Y2K problem. * -* Function implementation should be defined in user source code in condition -* that such event handler is required. If such event is not required user +* Function implementation should be defined in user source code in condition +* that such event handler is required. If such event is not required user * should not do any actions. * *******************************************************************************/ @@ -1266,8 +1266,8 @@ uint32_t Cy_RTC_GetInterruptStatus(void) * Function Name: Cy_RTC_GetInterruptStatusMasked ****************************************************************************//** * -* Returns an interrupt request register masked by the interrupt mask. Returns a -* result of the bitwise AND operation between the corresponding interrupt +* Returns an interrupt request register masked by the interrupt mask. Returns a +* result of the bitwise AND operation between the corresponding interrupt * request and mask bits. * * \return @@ -1318,7 +1318,7 @@ void Cy_RTC_SetInterrupt(uint32_t interruptMask) * Function Name: Cy_RTC_ClearInterrupt ****************************************************************************//** * -* Clears RTC interrupts by setting each bit. +* Clears RTC interrupts by setting each bit. * * \param * interruptMask The bit mask of interrupts to set, @@ -1339,7 +1339,7 @@ void Cy_RTC_ClearInterrupt(uint32_t interruptMask) * Function Name: Cy_RTC_SetInterruptMask ****************************************************************************//** * -* Configures which bits of the interrupt request register that triggers an +* Configures which bits of the interrupt request register that triggers an * interrupt event. * * \param interruptMask @@ -1361,18 +1361,18 @@ void Cy_RTC_SetInterruptMask(uint32_t interruptMask) * The interrupt handler function which should be called in user provided * RTC interrupt function. * -* This is the handler of the RTC interrupt in CPU NVIC. The handler checks -* which RTC interrupt was asserted and calls the respective RTC interrupt -* handler functions: Cy_RTC_Alarm1Interrupt(), Cy_RTC_Alarm2Interrupt() or +* This is the handler of the RTC interrupt in CPU NVIC. The handler checks +* which RTC interrupt was asserted and calls the respective RTC interrupt +* handler functions: Cy_RTC_Alarm1Interrupt(), Cy_RTC_Alarm2Interrupt() or * Cy_RTC_DstInterrupt(), and Cy_RTC_CenturyInterrupt(). -* -* The order of the RTC handler functions execution is incremental. +* +* The order of the RTC handler functions execution is incremental. * Cy_RTC_Alarm1Interrupt() is run as the first one and Cy_RTC_CenturyInterrupt() * is called as the last one. * * This function clears the RTC interrupt every time when it is called. * -* Cy_RTC_DstInterrupt() function is called instead of Cy_RTC_Alarm2Interrupt() +* Cy_RTC_DstInterrupt() function is called instead of Cy_RTC_Alarm2Interrupt() * in condition that the mode parameter is true. * * \param dstTime @@ -1420,11 +1420,11 @@ void Cy_RTC_Interrupt(cy_stc_rtc_dst_t const *dstTime, bool mode) * Function Name: Cy_RTC_DeepSleepCallback ****************************************************************************//** * -* This function checks the RTC_BUSY bit to avoid data corruption before +* This function checks the RTC_BUSY bit to avoid data corruption before * enters the Deep Sleep mode. * * \param callbackParams -* The structure with the SysPm callback parameters, +* The structure with the SysPm callback parameters, * see \ref cy_stc_syspm_callback_params_t * * \param mode @@ -1433,13 +1433,13 @@ void Cy_RTC_Interrupt(cy_stc_rtc_dst_t const *dstTime, bool mode) * \return * The SysPm return status, see \ref cy_en_syspm_status_t. * -* \note The *base and *context elements are required to be present in -* the parameter structure because this function uses the SysPm driver +* \note The *base and *context elements are required to be present in +* the parameter structure because this function uses the SysPm driver * callback type. -* The SysPm driver callback function type requires implementing the function +* The SysPm driver callback function type requires implementing the function * with next parameters and return value: * -* cy_en_syspm_status_t (*Cy_SysPmCallback) +* cy_en_syspm_status_t (*Cy_SysPmCallback) * (cy_stc_syspm_callback_params_t *callbackParams, cy_en_syspm_callback_mode_t mode); * *******************************************************************************/ @@ -1459,25 +1459,25 @@ cy_en_syspm_status_t Cy_RTC_DeepSleepCallback(const cy_stc_syspm_callback_params } } break; - + case CY_SYSPM_CHECK_FAIL: { retVal = CY_SYSPM_SUCCESS; } break; - + case CY_SYSPM_BEFORE_TRANSITION: { retVal = CY_SYSPM_SUCCESS; } break; - + case CY_SYSPM_AFTER_TRANSITION: { retVal = CY_SYSPM_SUCCESS; } break; - + default: break; } @@ -1490,11 +1490,11 @@ cy_en_syspm_status_t Cy_RTC_DeepSleepCallback(const cy_stc_syspm_callback_params * Function Name: Cy_RTC_HibernateCallback ****************************************************************************//** * -* This function checks the RTC_BUSY bit to avoid data corruption before +* This function checks the RTC_BUSY bit to avoid data corruption before * enters the Hibernate mode. * * \param callbackParams -* structure with the syspm callback parameters, +* structure with the syspm callback parameters, * see \ref cy_stc_syspm_callback_params_t. * * \param mode @@ -1503,13 +1503,13 @@ cy_en_syspm_status_t Cy_RTC_DeepSleepCallback(const cy_stc_syspm_callback_params * \return * The syspm return status, see \ref cy_en_syspm_status_t * -* \note The *base and *context elements are required to be present in -* the parameter structure because this function uses the SysPm driver +* \note The *base and *context elements are required to be present in +* the parameter structure because this function uses the SysPm driver * callback type. -* The SysPm driver callback function type requires implementing the function +* The SysPm driver callback function type requires implementing the function * with next parameters and return value: * -* cy_en_syspm_status_t (*Cy_SysPmCallback) +* cy_en_syspm_status_t (*Cy_SysPmCallback) * (cy_stc_syspm_callback_params_t *callbackParams, cy_en_syspm_callback_mode_t mode); * *******************************************************************************/ @@ -1523,16 +1523,16 @@ cy_en_syspm_status_t Cy_RTC_HibernateCallback(const cy_stc_syspm_callback_params * Function Name: ConstructTimeDate ****************************************************************************//** * -* Returns BCD time and BCD date in the format used in APIs from individual +* Returns BCD time and BCD date in the format used in APIs from individual * elements passed. -* Converted BCD time(*timeBcd) and BCD date(*dateBcd) are matched with RTC_TIME +* Converted BCD time(*timeBcd) and BCD date(*dateBcd) are matched with RTC_TIME * and RTC_DATE bit fields format. * -* \param timeDate +* \param timeDate * The structure of time and date, see \ref cy_stc_rtc_config_t. * * \param timeBcd -* The BCD-formatted time variable which has the same bit masks as the +* The BCD-formatted time variable which has the same bit masks as the * RTC_TIME register: * * [0:6] - Calendar seconds in BCD, the range 0-59. \n @@ -1544,7 +1544,7 @@ cy_en_syspm_status_t Cy_RTC_HibernateCallback(const cy_stc_syspm_callback_params * [26:24] - A calendar day of the week, the range 1 - 7, where 1 - Sunday. \n * * \param dateBcd -* The BCD-formatted time variable which has the same bit masks as the +* The BCD-formatted time variable which has the same bit masks as the * RTC_DATE register: * * [5:0] - A calendar day of a month in BCD, the range 1-31. \n @@ -1562,9 +1562,9 @@ static void ConstructTimeDate(cy_stc_rtc_config_t const *timeDate, uint32_t *tim tmpTime |= (_VAL2FLD(BACKUP_RTC_TIME_RTC_MIN, Cy_RTC_ConvertDecToBcd(timeDate->min))); /* Read the current hour mode to know how many hour bits to convert. - * In the 24-hour mode, the hour value is presented in [21:16] bits in the + * In the 24-hour mode, the hour value is presented in [21:16] bits in the * BCD format. - * In the 12-hour mode, the hour value is presented in [20:16] bits in the + * In the 12-hour mode, the hour value is presented in [20:16] bits in the * BCD format and bit [21] is present: 0 - AM; 1 - PM. */ if (timeDate->hrFormat != CY_RTC_24_HOURS) @@ -1577,11 +1577,11 @@ static void ConstructTimeDate(cy_stc_rtc_config_t const *timeDate, uint32_t *tim else { /* Set the AM bit */ - tmpTime &= ((uint32_t) ~CY_RTC_BACKUP_RTC_TIME_RTC_PM); + tmpTime &= ((uint32_t) ~CY_RTC_BACKUP_RTC_TIME_RTC_PM); } tmpTime |= BACKUP_RTC_TIME_CTRL_12HR_Msk; - tmpTime |= - (_VAL2FLD(BACKUP_RTC_TIME_RTC_HOUR, + tmpTime |= + (_VAL2FLD(BACKUP_RTC_TIME_RTC_HOUR, (Cy_RTC_ConvertDecToBcd(timeDate->hour) & ((uint32_t) ~CY_RTC_12HRS_PM_BIT)))); } else @@ -1606,23 +1606,23 @@ static void ConstructTimeDate(cy_stc_rtc_config_t const *timeDate, uint32_t *tim * Function Name: ConstructAlarmTimeDate ****************************************************************************//** * -* Returns the BCD time and BCD date in the format used in APIs from individual +* Returns the BCD time and BCD date in the format used in APIs from individual * elements passed for alarm. -* Converted BCD time(*alarmTimeBcd) and BCD date(*alarmDateBcd) should be +* Converted BCD time(*alarmTimeBcd) and BCD date(*alarmDateBcd) should be * matched with the ALMx_TIME and ALMx_DATE bit fields format. * * \param timeDate * The structure of time and date, see \ref cy_stc_rtc_alarm_t. * * \param alarmTimeBcd -* The BCD-formatted time variable which has the same bit masks as the +* The BCD-formatted time variable which has the same bit masks as the * ALMx_TIME register time fields: * * [0:6] - Alarm seconds in BCD, the range 0-59. \n * [7] - Alarm seconds Enable: 0 - ignore, 1 - match. \n * [14:8] - Alarm minutes in BCD, the range 0-59. \n * [15] - Alarm minutes Enable: 0 - ignore, 1 - match. \n -* [21:16] - Alarm hours in BCD, value depending on the 12/24-hour mode +* [21:16] - Alarm hours in BCD, value depending on the 12/24-hour mode * (RTC_CTRL_12HR) \n * 12HR: [21]:0 = AM, 1 = PM, [20:16] = 1 - 12; \n * 24HR: [21:16] = the range 0-23. \n @@ -1631,7 +1631,7 @@ static void ConstructTimeDate(cy_stc_rtc_config_t const *timeDate, uint32_t *tim * [31] - An alarm day of the week Enable: 0 - ignore, 1 - match. \n * * \param alarmDateBcd -* The BCD-formatted date variable which has the same bit masks as the +* The BCD-formatted date variable which has the same bit masks as the * ALMx_DATE register date fields: * * [5:0] - An alarm day of a month in BCD, the range 1-31. \n @@ -1641,9 +1641,9 @@ static void ConstructTimeDate(cy_stc_rtc_config_t const *timeDate, uint32_t *tim * [31] - The Enable alarm: 0 - Alarm is disabled, 1 - Alarm is enabled. \n * * This function reads current AHB register RTC_TIME value to know hour mode. -* It is recommended to call Cy_RTC_SyncFromRtc() function before calling the +* It is recommended to call Cy_RTC_SyncFromRtc() function before calling the * ConstructAlarmTimeDate() functions. -* +* * Construction is based on RTC_ALARM1 register bit fields. * *******************************************************************************/ @@ -1661,9 +1661,9 @@ static void ConstructAlarmTimeDate(cy_stc_rtc_alarm_t const *alarmDateTime, uint tmpAlarmTime |= (_VAL2FLD(BACKUP_ALM1_TIME_ALM_MIN_EN, alarmDateTime->minEn)); /* Read the current hour mode to know how many hour bits to convert. - * In the 24-hour mode, the hour value is presented in [21:16] bits in the + * In the 24-hour mode, the hour value is presented in [21:16] bits in the * BCD format. - * In the 12-hour mode, the hour value is presented in [20:16] bits in the + * In the 12-hour mode, the hour value is presented in [20:16] bits in the * BCD format and bit [21] is present: 0 - AM; 1 - PM */ Cy_RTC_SyncFromRtc(); @@ -1672,18 +1672,18 @@ static void ConstructAlarmTimeDate(cy_stc_rtc_alarm_t const *alarmDateTime, uint /* Convert the hour from the 24-hour mode into the 12-hour mode */ if (alarmDateTime->hour >= CY_RTC_HOURS_PER_HALF_DAY) { - /* The current hour is more than 12 in the 24-hour mode. Set the PM + /* The current hour is more than 12 in the 24-hour mode. Set the PM * bit and converting hour: hour = hour - 12 */ hourValue = (uint32_t) alarmDateTime->hour - CY_RTC_HOURS_PER_HALF_DAY; hourValue = ((0U != hourValue) ? hourValue : CY_RTC_HOURS_PER_HALF_DAY); - tmpAlarmTime |= + tmpAlarmTime |= CY_RTC_BACKUP_RTC_TIME_RTC_PM | (_VAL2FLD(BACKUP_ALM1_TIME_ALM_HOUR, Cy_RTC_ConvertDecToBcd(hourValue))); } else if (alarmDateTime->hour < 1U) { /* The current hour in the 24-hour mode is 0 which is equal to 12:00 AM */ - tmpAlarmTime = (tmpAlarmTime & ((uint32_t) ~CY_RTC_BACKUP_RTC_TIME_RTC_PM)) | + tmpAlarmTime = (tmpAlarmTime & ((uint32_t) ~CY_RTC_BACKUP_RTC_TIME_RTC_PM)) | (_VAL2FLD(BACKUP_ALM1_TIME_ALM_HOUR, CY_RTC_HOURS_PER_HALF_DAY)); } else @@ -1740,7 +1740,7 @@ static uint32_t RelativeToFixed(cy_stc_rtc_dst_format_t const *convertDst) /* Read the current year */ Cy_RTC_SyncFromRtc(); - currentYear = + currentYear = CY_RTC_TWO_THOUSAND_YEARS + Cy_RTC_ConvertBcdToDec(_FLD2VAL(BACKUP_RTC_DATE_RTC_YEAR, BACKUP_RTC_DATE)); currentDay = CY_RTC_FIRST_DAY_OF_MONTH; diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_sar.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_sar.c index 29acc37e1b..a2c2cd5a62 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_sar.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_sar.c @@ -1,12 +1,12 @@ /***************************************************************************//** * \file cy_sar.c -* \version 1.20.2 +* \version 1.20.3 * * Provides the public functions for the API for the SAR driver. * ******************************************************************************** * \copyright -* Copyright 2017-2019 Cypress Semiconductor Corporation +* Copyright 2017-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -152,7 +152,7 @@ cy_en_sar_status_t Cy_SAR_Init(SAR_Type *base, const cy_stc_sar_config_t *config { SAR_ANA_TRIM0(base) = CY_SAR_CAP_TRIM; } - + /* Set the REFBUF_EN bit as this is required for proper operation. */ SAR_CTRL(base) = config->ctrl | SAR_CTRL_REFBUF_EN_Msk; @@ -1193,7 +1193,7 @@ void Cy_SAR_SetAnalogSwitch(SAR_Type *base, cy_en_sar_switch_register_sel_t swit CY_ASSERT_L2(CY_SAR_SWITCHMASK(switchMask)); CY_ASSERT_L3(CY_SAR_SWITCHSTATE(state)); (void)switchSelect; /* Suppress warning */ - + __IOM uint32_t *switchReg; __IOM uint32_t *switchClearReg; @@ -1332,4 +1332,3 @@ cy_en_syspm_status_t Cy_SAR_DeepSleepCallback(cy_stc_syspm_callback_params_t *ca #endif /* CY_IP_MXS40PASS_SAR */ /* [] END OF FILE */ - diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_scb_common.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_scb_common.c index 718d7ec3d1..f1021185b5 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_scb_common.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_scb_common.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_scb_common.c -* \version 2.40.1 +* \version 2.50 * * Provides common API implementation of the SCB driver. * @@ -424,4 +424,3 @@ uint32_t Cy_SCB_WriteDefaultArray(CySCB_Type *base, uint32_t txData, uint32_t si #endif /* CY_IP_MXSCB */ /* [] END OF FILE */ - diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_scb_ezi2c.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_scb_ezi2c.c index 3c86ee8a41..03c9d7ab56 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_scb_ezi2c.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_scb_ezi2c.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_scb_ezi2c.c -* \version 2.40.1 +* \version 2.50 * * Provides EZI2C API implementation of the SCB driver. * @@ -212,7 +212,7 @@ void Cy_SCB_EZI2C_Disable(CySCB_Type *base, cy_stc_scb_ezi2c_context_t *context) ****************************************************************************//** * * This function handles the transition of the EZI2C SCB into and out of -* Deep Sleep mode. It prevents the device from entering Deep Sleep mode if +* Deep Sleep mode. It prevents the device from entering Deep Sleep mode if * the EZI2C slave is actively communicating. * The following behavior of the EZI2C depends on whether the SCB block is * wakeup-capable: @@ -220,7 +220,7 @@ void Cy_SCB_EZI2C_Disable(CySCB_Type *base, cy_stc_scb_ezi2c_context_t *context) * receives the address and stretches the clock until the device is woken from * Deep Sleep mode. If the slave address occurs before the device enters * Deep Sleep mode, the device will not enter Deep Sleep mode. -* * Not wakeup-capable: the EZI2C is disabled. It is enabled +* * Not wakeup-capable: the EZI2C is disabled. It is enabled * when the device fails to enter Deep Sleep mode or it is woken from Deep Sleep * mode. While the EZI2C is disabled, it stops driving the outputs and * ignores the input lines. The slave NACKs all incoming addresses. @@ -245,7 +245,7 @@ void Cy_SCB_EZI2C_Disable(CySCB_Type *base, cy_stc_scb_ezi2c_context_t *context) * For proper operation, when the EZI2C slave is configured to be a wakeup source * from Deep Sleep mode, this function must be copied and modified by the user. * The EZI2C clock disable code must be inserted in the -* \ref CY_SYSPM_BEFORE_TRANSITION and clock enable code in the +* \ref CY_SYSPM_BEFORE_TRANSITION and clock enable code in the * \ref CY_SYSPM_AFTER_TRANSITION mode processing. * *******************************************************************************/ @@ -345,10 +345,10 @@ cy_en_syspm_status_t Cy_SCB_EZI2C_DeepSleepCallback(cy_stc_syspm_callback_params /* Disable SCB clock */ SCB_I2C_CFG(locBase) &= (uint32_t) ~CY_SCB_I2C_CFG_CLK_ENABLE_Msk; - - /* IMPORTANT (replace line above for the CY8CKIT-062 rev-08): - * for proper entering Deep Sleep mode the I2C clock must be disabled. - * This code must be inserted by the user because the driver + + /* IMPORTANT (replace line above for the CY8CKIT-062 rev-08): + * for proper entering Deep Sleep mode the I2C clock must be disabled. + * This code must be inserted by the user because the driver * does not have access to the clock. */ } @@ -363,10 +363,10 @@ cy_en_syspm_status_t Cy_SCB_EZI2C_DeepSleepCallback(cy_stc_syspm_callback_params { /* Enable SCB clock */ SCB_I2C_CFG(locBase) |= CY_SCB_I2C_CFG_CLK_ENABLE_Msk; - - /* IMPORTANT (replace line above for the CY8CKIT-062 rev-08): - * for proper exiting Deep Sleep mode, the I2C clock must be enabled. - * This code must be inserted by the user because the driver + + /* IMPORTANT (replace line above for the CY8CKIT-062 rev-08): + * for proper exiting Deep Sleep mode, the I2C clock must be enabled. + * This code must be inserted by the user because the driver * does not have access to the clock. */ @@ -399,7 +399,7 @@ cy_en_syspm_status_t Cy_SCB_EZI2C_DeepSleepCallback(cy_stc_syspm_callback_params ****************************************************************************//** * * This function handles the transition of the EZI2C SCB block into Hibernate -* mode. It prevents the device from entering Hibernate mode if the EZI2C slave +* mode. It prevents the device from entering Hibernate mode if the EZI2C slave * is actively communicating. * If the EZI2C is ready to enter Hibernate mode, it is disabled. If the device * fails to enter Hibernate mode, the EZI2C is enabled. While the EZI2C @@ -769,11 +769,11 @@ void Cy_SCB_EZI2C_Interrupt(CySCB_Type *base, cy_stc_scb_ezi2c_context_t *contex /* Handle an I2C wake-up event */ if (0UL != (CY_SCB_I2C_INTR_WAKEUP & Cy_SCB_GetI2CInterruptStatusMasked(base))) { - /* Move from IDLE state, the slave was addressed. Following address match + /* Move from IDLE state, the slave was addressed. Following address match * interrupt continue transfer. */ context->state = CY_SCB_EZI2C_STATE_ADDR; - + Cy_SCB_ClearI2CInterrupt(base, CY_SCB_I2C_INTR_WAKEUP); } @@ -1310,4 +1310,3 @@ static void UpdateAddressMask(CySCB_Type *base, cy_stc_scb_ezi2c_context_t const #endif /* CY_IP_MXSCB */ /* [] END OF FILE */ - diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_scb_i2c.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_scb_i2c.c index e8383bba9d..206cdbbce7 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_scb_i2c.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_scb_i2c.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_scb_i2c.c -* \version 2.40.1 +* \version 2.50 * * Provides I2C API implementation of the SCB driver. * @@ -99,11 +99,11 @@ cy_en_scb_i2c_status_t Cy_SCB_I2C_Init(CySCB_Type *base, cy_stc_scb_i2c_config_t _VAL2FLD(SCB_I2C_CTRL_HIGH_PHASE_OVS, (config->highPhaseDutyCycle - 1U)) | _VAL2FLD(SCB_I2C_CTRL_LOW_PHASE_OVS, (config->lowPhaseDutyCycle - 1U)) | _VAL2FLD(CY_SCB_I2C_CTRL_MODE, (uint32_t) config->i2cMode); - + { /* Enable digital filter for only for master modes */ bool enableDigFilter = (CY_SCB_I2C_SLAVE != config->i2cMode) && (config->enableDigitalFilter); - + /* Configure the RX direction */ SCB_RX_CTRL(base) = _BOOL2FLD(SCB_RX_CTRL_MEDIAN, enableDigFilter) | CY_SCB_I2C_RX_CTRL; @@ -239,14 +239,14 @@ void Cy_SCB_I2C_Disable(CySCB_Type *base, cy_stc_scb_i2c_context_t *context) * mode if the I2C slave or master is actively communicating. * The behavior of the I2C SCB in Deep Sleep depends on whether the SCB block is * wakeup-capable or not: -* * Wakeup-capable: during Deep Sleep mode on incoming I2C slave address -* the slave receives address and stretches the clock until the device is -* awoken from Deep Sleep mode. If the slave address occurs before the device +* * Wakeup-capable: during Deep Sleep mode on incoming I2C slave address +* the slave receives address and stretches the clock until the device is +* awoken from Deep Sleep mode. If the slave address occurs before the device * enters Deep Sleep mode, the device will not enter Deep Sleep mode. * Only the I2C slave can be configured to be a wakeup source from Deep Sleep * mode. -* * Not wakeup-capable: the SCB is disabled in Deep Sleep mode. -* It is re-enabled if the device fails to enter Deep Sleep mode or when the +* * Not wakeup-capable: the SCB is disabled in Deep Sleep mode. +* It is re-enabled if the device fails to enter Deep Sleep mode or when the * device is awoken from Deep Sleep mode. While the SCB is disabled it stops * driving the outputs and ignores the inputs. The slave NACKs all incoming * addresses. @@ -424,9 +424,9 @@ cy_en_syspm_status_t Cy_SCB_I2C_DeepSleepCallback(cy_stc_syspm_callback_params_t * This function handles the transition of the I2C SCB block into Hibernate * mode. It prevents the device from entering Hibernate mode if the I2C slave or * master is actively communicating. -* If the I2C is ready to enter Hibernate mode it is disabled. If the device -* failed to enter Hibernate mode, the SCB is enabled. After the SCB is disabled, -* it stops driving the outputs and ignores the inputs. The slave NACKs all +* If the I2C is ready to enter Hibernate mode it is disabled. If the device +* failed to enter Hibernate mode, the SCB is enabled. After the SCB is disabled, +* it stops driving the outputs and ignores the inputs. The slave NACKs all * incoming addresses. * * This function must be called during execution of \ref Cy_SysPm_SystemEnterHibernate. @@ -525,7 +525,7 @@ cy_en_syspm_status_t Cy_SCB_I2C_HibernateCallback(cy_stc_syspm_callback_params_t * * \return * The achieved data rate in Hz. \n -* When zero value is returned there is an error in the input parameters: +* When zero value is returned there is an error in the input parameters: * data rate or clk_scb is out of valid range. * * \note @@ -554,14 +554,14 @@ uint32_t Cy_SCB_I2C_SetDataRate(CySCB_Type *base, uint32_t dataRateHz, uint32_t } else { - bool errorRange = true; + bool errorRange = true; uint32_t sclLow; uint32_t sclHigh; - + uint32_t lowPhase = 8U; uint32_t highPhase = 8U; bool enableMedian = false; - + /* Get duration of SCL low and high for the selected data rate */ if ((0U == dataRateHz) || (dataRateHz > CY_SCB_I2C_FSTP_DATA_RATE)) { @@ -576,7 +576,7 @@ uint32_t Cy_SCB_I2C_SetDataRate(CySCB_Type *base, uint32_t dataRateHz, uint32_t sclHigh = CY_SCB_I2C_MASTER_STD_SCL_HIGH; enableMedian = false; - errorRange = false; + errorRange = false; } } else if (dataRateHz <= CY_SCB_I2C_FST_DATA_RATE) @@ -588,7 +588,7 @@ uint32_t Cy_SCB_I2C_SetDataRate(CySCB_Type *base, uint32_t dataRateHz, uint32_t sclHigh = CY_SCB_I2C_MASTER_FST_SCL_HIGH; enableMedian = false; - errorRange = false; + errorRange = false; } } else @@ -601,7 +601,7 @@ uint32_t Cy_SCB_I2C_SetDataRate(CySCB_Type *base, uint32_t dataRateHz, uint32_t sclHigh = CY_SCB_I2C_MASTER_FSTP_SCL_HIGH; enableMedian = true; - errorRange = false; + errorRange = false; } } @@ -625,7 +625,7 @@ uint32_t Cy_SCB_I2C_SetDataRate(CySCB_Type *base, uint32_t dataRateHz, uint32_t { lowPhase = CY_SCB_I2C_LOW_PHASE_MAX; } - + /* Define if update low phase */ updateLowPhase = (lowPhase < CY_SCB_I2C_LOW_PHASE_MAX); @@ -641,10 +641,10 @@ uint32_t Cy_SCB_I2C_SetDataRate(CySCB_Type *base, uint32_t dataRateHz, uint32_t { highPhase = CY_SCB_I2C_HIGH_PHASE_MAX; } - + /* Get actual data rate */ actualDataRateHz = scbClockHz / (lowPhase + highPhase); - + /* Find desired data rate */ while ((actualDataRateHz > dataRateHz) && ((lowPhase + highPhase) < CY_SCB_I2C_DUTY_CYCLE_MAX)) { @@ -710,7 +710,7 @@ uint32_t Cy_SCB_I2C_SetDataRate(CySCB_Type *base, uint32_t dataRateHz, uint32_t * * \return * The data rate in Hz. \n -* For slave mode when zero value is returned the clk_scb is out of valid +* For slave mode when zero value is returned the clk_scb is out of valid * range. * *******************************************************************************/ @@ -1034,7 +1034,7 @@ void Cy_SCB_I2C_SlaveConfigWriteBuf(CySCB_Type const *base, uint8_t *buffer, uin ****************************************************************************//** * * Aborts the configured slave write buffer to be written by the master. -* If master writes and an "abort operation" is requested, the next incoming +* If master writes and an "abort operation" is requested, the next incoming * byte will be NAKed. * * \param base @@ -1225,8 +1225,8 @@ uint32_t Cy_SCB_I2C_MasterGetStatus(CySCB_Type const *base, cy_stc_scb_i2c_conte * completion. * * * \ref Cy_SCB_I2C_MasterRead requests the SCB hardware to generate a start -* condition when there is no pending transfer and returns (does not wait -* until hardware generate a start condition). If the I2C bus is busy the +* condition when there is no pending transfer and returns (does not wait +* until hardware generate a start condition). If the I2C bus is busy the * hardware will not generate the until bus becomes free. * The SCB hardware sets the busy status after the Start detection, and clears * it on the Stop detection. Noise caused by the ESD or other events may cause @@ -1277,8 +1277,8 @@ cy_en_scb_i2c_status_t Cy_SCB_I2C_MasterRead(CySCB_Type *base, if (CY_SCB_I2C_IDLE == context->state) { - /* Put the address in the TX FIFO, then generate a Start condition. - * This sequence ensures that after the Start condition generation + /* Put the address in the TX FIFO, then generate a Start condition. + * This sequence ensures that after the Start condition generation * the address is available to be sent onto the bus. */ Cy_SCB_WriteTxFifo(base, address); @@ -1453,8 +1453,8 @@ void Cy_SCB_I2C_MasterAbortRead(CySCB_Type *base, cy_stc_scb_i2c_context_t *cont * copied into the TX FIFO. * * * \ref Cy_SCB_I2C_MasterWrite requests the SCB hardware to generate a start -* condition when there is no pending transfer and returns (does not wait -* until hardware generate a start condition). If the I2C bus is busy the +* condition when there is no pending transfer and returns (does not wait +* until hardware generate a start condition). If the I2C bus is busy the * hardware will not generate the until bus becomes free. * The SCB hardware sets the busy status after the Start detection, and clears * it on the Stop detection. Noise caused by the ESD or other events may cause @@ -1504,8 +1504,8 @@ cy_en_scb_i2c_status_t Cy_SCB_I2C_MasterWrite(CySCB_Type *base, if (CY_SCB_I2C_IDLE == context->state) { - /* Put the address in the TX FIFO, then generate a Start condition. - * This sequence ensures that after the Start condition generation + /* Put the address in the TX FIFO, then generate a Start condition. + * This sequence ensures that after the Start condition generation * the address is available to be sent onto the bus. */ Cy_SCB_WriteTxFifo (base, address); @@ -1524,9 +1524,9 @@ cy_en_scb_i2c_status_t Cy_SCB_I2C_MasterWrite(CySCB_Type *base, if (0U == context->masterBufferSize) { /* The address is the last byte to transfer. - * Put the address byte in the TX FIFO and clear the TX - * Underflow interrupt source inside the critical section - * to ensure that the TX Underflow interrupt will trigger + * Put the address byte in the TX FIFO and clear the TX + * Underflow interrupt source inside the critical section + * to ensure that the TX Underflow interrupt will trigger * after the address byte is sent onto the bus. */ intrState = Cy_SysLib_EnterCriticalSection(); @@ -1868,8 +1868,8 @@ cy_en_scb_i2c_status_t Cy_SCB_I2C_MasterSendReStart(CySCB_Type *base, if (false == _FLD2BOOL(SCB_I2C_STATUS_M_READ, SCB_I2C_STATUS(base))) { /* Cypress ID #295908: Wait until ReStart is generated to complete - * the previous write transfer. This ensures that the address byte - * will not be interpreted as the data byte of the previous + * the previous write transfer. This ensures that the address byte + * will not be interpreted as the data byte of the previous * transfer. */ while ((0U == locStatus) && @@ -2551,9 +2551,9 @@ static void SlaveHandleDataTransmit(CySCB_Type *base, cy_stc_scb_i2c_context_t * { uint32_t intrStatus; - /* Put the last data byte in the TX FIFO and clear the TX Underflow - * interrupt source inside the critical section to ensure that the - * TX Underflow interrupt will trigger after all data bytes from the + /* Put the last data byte in the TX FIFO and clear the TX Underflow + * interrupt source inside the critical section to ensure that the + * TX Underflow interrupt will trigger after all data bytes from the * TX FIFO are transferred onto the bus. */ intrStatus = Cy_SysLib_EnterCriticalSection(); @@ -2945,9 +2945,9 @@ static void MasterHandleDataTransmit(CySCB_Type *base, cy_stc_scb_i2c_context_t { uint32_t intrStatus; - /* Put the last data byte in the TX FIFO and clear the TX Underflow - * interrupt source inside the critical section to ensure that the - * TX Underflow interrupt will trigger after all data bytes from the + /* Put the last data byte in the TX FIFO and clear the TX Underflow + * interrupt source inside the critical section to ensure that the + * TX Underflow interrupt will trigger after all data bytes from the * TX FIFO are transferred onto the bus. */ intrStatus = Cy_SysLib_EnterCriticalSection(); @@ -3287,4 +3287,3 @@ static cy_en_scb_i2c_status_t HandleStatus(CySCB_Type *base, uint32_t status, cy #endif /* CY_IP_MXSCB */ /* [] END OF FILE */ - diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_scb_spi.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_scb_spi.c index 943cd865cc..4203bc95c0 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_scb_spi.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_scb_spi.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_scb_spi.c -* \version 2.40.1 +* \version 2.50 * * Provides SPI API implementation of the SCB driver. * @@ -52,7 +52,7 @@ static void DiscardArrayNoCheck(CySCB_Type const *base, uint32_t size); * by the user. The structure is used during the SPI operation for internal * configuration and data retention. The user must not modify anything * in this structure. -* If only SPI \ref group_scb_spi_ll will be used pass NULL as pointer to +* If only SPI \ref group_scb_spi_ll will be used pass NULL as pointer to * context. * * \return @@ -194,7 +194,7 @@ void Cy_SCB_SPI_DeInit(CySCB_Type *base) * TX and RX interrupt sources. * Note that after the block is disabled, the TX and RX FIFOs and * hardware statuses are cleared. Also, the hardware stops driving the output -* and ignores the input. Refer to section \ref group_scb_spi_lp for more +* and ignores the input. Refer to section \ref group_scb_spi_lp for more * information about SPI pins when SCB disabled. * * \param base @@ -245,30 +245,30 @@ void Cy_SCB_SPI_Disable(CySCB_Type *base, cy_stc_scb_spi_context_t *context) * * This function handles the transition of the SCB SPI into and out of * Deep Sleep mode. It prevents the device from entering Deep Sleep mode -* if the SPI slave or master is actively communicating, or there is any data +* if the SPI slave or master is actively communicating, or there is any data * in the TX or RX FIFOs. * The following behavior of the SPI SCB depends on whether the SCB block is * wakeup-capable or not: -* * Wakeup-capable: any transfer intended to the slave wakes up -* the device from Deep Sleep mode. The slave responds with 0xFF to the -* transfer and incoming data is ignored. +* * Wakeup-capable: any transfer intended to the slave wakes up +* the device from Deep Sleep mode. The slave responds with 0xFF to the +* transfer and incoming data is ignored. * If the transfer occurs before the device enters Deep Sleep mode, the device * will not enter Deep Sleep mode and incoming data is stored in the RX FIFO. -* The SCB clock is disabled before entering Deep Sleep and enabled after the -* device exits Deep Sleep mode. The SCB clock disabling may lead to -* corrupted data in the RX FIFO. Clear the RX FIFO after this callback is +* The SCB clock is disabled before entering Deep Sleep and enabled after the +* device exits Deep Sleep mode. The SCB clock disabling may lead to +* corrupted data in the RX FIFO. Clear the RX FIFO after this callback is * executed. -* Note that for proper SPI operation after Deep Sleep the source of -* hf_clk[0] must be stable, this includes the FLL/PLL. The SysClk callback -* ensures that hf_clk[0] gets stable and it must be called before -* \ref Cy_SCB_SPI_DeepSleepCallback. +* Note that for proper SPI operation after Deep Sleep the source of +* hf_clk[0] must be stable, this includes the FLL/PLL. The SysClk callback +* ensures that hf_clk[0] gets stable and it must be called before +* \ref Cy_SCB_SPI_DeepSleepCallback. * Only the SPI slave can be configured to be a wakeup source from Deep Sleep * mode. -* * Not wakeup-capable: the SPI is disabled. It is enabled when -* the device fails to enter Deep Sleep mode or it is awakened from Deep Sleep -* mode. While the SPI is disabled, it stops driving the outputs and ignores +* * Not wakeup-capable: the SPI is disabled. It is enabled when +* the device fails to enter Deep Sleep mode or it is awakened from Deep Sleep +* mode. While the SPI is disabled, it stops driving the outputs and ignores * the inputs. Any incoming data is ignored. -* Refer to section \ref group_scb_spi_lp for more information about SPI pins +* Refer to section \ref group_scb_spi_lp for more information about SPI pins * when SCB disabled. * * This function must be called during execution of \ref Cy_SysPm_CpuEnterDeepSleep. @@ -386,13 +386,13 @@ cy_en_syspm_status_t Cy_SCB_SPI_DeepSleepCallback(cy_stc_syspm_callback_params_t * becomes pending and prevents entering Deep Sleep mode. */ Cy_SCB_SetSpiInterruptMask(locBase, CY_SCB_I2C_INTR_WAKEUP); - + /* Disable SCB clock */ SCB_I2C_CFG(locBase) &= (uint32_t) ~CY_SCB_I2C_CFG_CLK_ENABLE_Msk; - - /* IMPORTANT (replace line above for the CY8CKIT-062 rev-08): - * for proper entering Deep Sleep mode the SPI clock must be disabled. - * This code must be inserted by the user because the driver + + /* IMPORTANT (replace line above for the CY8CKIT-062 rev-08): + * for proper entering Deep Sleep mode the SPI clock must be disabled. + * This code must be inserted by the user because the driver * does not have access to the clock. */ } @@ -407,13 +407,13 @@ cy_en_syspm_status_t Cy_SCB_SPI_DeepSleepCallback(cy_stc_syspm_callback_params_t { /* Enable SCB clock */ SCB_I2C_CFG(locBase) |= CY_SCB_I2C_CFG_CLK_ENABLE_Msk; - - /* IMPORTANT (replace line above for the CY8CKIT-062 rev-08): - * for proper exiting Deep Sleep mode, the SPI clock must be enabled. - * This code must be inserted by the user because the driver + + /* IMPORTANT (replace line above for the CY8CKIT-062 rev-08): + * for proper exiting Deep Sleep mode, the SPI clock must be enabled. + * This code must be inserted by the user because the driver * does not have access to the clock. */ - + /* The SCB is wakeup-capable: disable the SPI wakeup interrupt * source */ @@ -442,18 +442,18 @@ cy_en_syspm_status_t Cy_SCB_SPI_DeepSleepCallback(cy_stc_syspm_callback_params_t ****************************************************************************//** * * This function handles the transition of the SCB SPI into Hibernate mode. -* It prevents the device from entering Hibernate mode if the SPI slave or +* It prevents the device from entering Hibernate mode if the SPI slave or * master is actively communicating, or there is any data in the TX or RX FIFOs. * If the SPI is ready to enter Hibernate mode, it is disabled. If the device * failed to enter Hibernate mode, the SPI is re-enabled. While the SPI is -* disabled, it stops driving the outputs and ignores the inputs. Any incoming -* data is ignored. Refer to section \ref group_scb_spi_lp for more information +* disabled, it stops driving the outputs and ignores the inputs. Any incoming +* data is ignored. Refer to section \ref group_scb_spi_lp for more information * about SPI pins when SCB disabled. * * This function must be called during execution of \ref Cy_SysPm_SystemEnterHibernate. * To do it, register this function as a callback before calling * \ref Cy_SysPm_SystemEnterHibernate : specify \ref CY_SYSPM_HIBERNATE as the callback -* type and call \ref Cy_SysPm_RegisterCallback. +* type and call \ref Cy_SysPm_RegisterCallback. * * \param callbackParams * The pointer to the callback parameters structure @@ -685,8 +685,8 @@ cy_en_scb_spi_status_t Cy_SCB_SPI_Transfer(CySCB_Type *base, void *txBuffer, voi * in this structure. * * \note -* If slave aborts transfer and the master is still transferring data, -* that data will be placed in the RX FIFO, and the TX underflow will be set. +* If slave aborts transfer and the master is still transferring data, +* that data will be placed in the RX FIFO, and the TX underflow will be set. * To drop data received into the RX FIFO, RX FIFO must be cleared when * the transfer is complete. Otherwise, received data will be kept and * copied to the buffer when \ref Cy_SCB_SPI_Transfer is called. @@ -1043,4 +1043,3 @@ static void DiscardArrayNoCheck(CySCB_Type const *base, uint32_t size) #endif /* CY_IP_MXSCB */ /* [] END OF FILE */ - diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_scb_uart.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_scb_uart.c index 8ea9cfc7bc..0603780a80 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_scb_uart.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_scb_uart.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_scb_uart.c -* \version 2.40.1 +* \version 2.50 * * Provides UART API implementation of the SCB driver. * @@ -54,7 +54,7 @@ static uint32_t SelectRxFifoLevel(CySCB_Type const *base); * by the user. The structure is used during the UART operation for internal * configuration and data retention. The user must not modify anything * in this structure. -* If only UART \ref group_scb_uart_ll will be used pass NULL as pointer to +* If only UART \ref group_scb_uart_ll will be used pass NULL as pointer to * context. * * \return @@ -232,7 +232,7 @@ void Cy_SCB_UART_DeInit(CySCB_Type *base) * Disables the SCB block and clears context statuses. * Note that after the block is disabled, the TX and RX FIFOs and * hardware statuses are cleared. Also, the hardware stops driving the -* output and ignores the input. Refer to section \ref group_scb_uart_lp for more +* output and ignores the input. Refer to section \ref group_scb_uart_lp for more * information about UART pins when SCB disabled. * \param base @@ -274,12 +274,12 @@ void Cy_SCB_UART_Disable(CySCB_Type *base, cy_stc_scb_uart_context_t *context) ****************************************************************************//** * * This function handles the transition of the SCB UART into and out of -* Deep Sleep mode. It prevents the device from entering Deep Sleep +* Deep Sleep mode. It prevents the device from entering Deep Sleep * mode if the UART is transmitting data or has any data in the RX FIFO. If the * UART is ready to enter Deep Sleep mode, it is disabled. The UART is enabled * when the device fails to enter Deep Sleep mode or it is awakened from * Deep Sleep mode. While the UART is disabled, it stops driving the outputs -* and ignores the inputs. Any incoming data is ignored. Refer to section +* and ignores the inputs. Any incoming data is ignored. Refer to section * \ref group_scb_uart_lp for more information about UART pins when SCB disabled. * * This function must be called during execution of \ref Cy_SysPm_CpuEnterDeepSleep, @@ -378,13 +378,13 @@ cy_en_syspm_status_t Cy_SCB_UART_DeepSleepCallback(cy_stc_syspm_callback_params_ * Function Name: Cy_SCB_UART_HibernateCallback ****************************************************************************//** * -* This function handles the transition of the SCB UART into Hibernate mode. +* This function handles the transition of the SCB UART into Hibernate mode. * It prevents the device from entering Hibernate mode if the UART is * transmitting data or has any data in the RX FIFO. If the UART is ready * to enter Hibernate mode, it is disabled. If the device fails to enter * Hibernate mode, the UART is enabled. While the UART is disabled, it stops * driving the outputs and ignores the inputs. Any incoming data is ignored. -* Refer to section \ref group_scb_uart_lp for more information about UART pins +* Refer to section \ref group_scb_uart_lp for more information about UART pins * when SCB disabled. * * This function must be called during execution of \ref Cy_SysPm_SystemEnterHibernate. @@ -423,7 +423,7 @@ cy_en_syspm_status_t Cy_SCB_UART_HibernateCallback(cy_stc_syspm_callback_params_ * * Starts the receive ring buffer operation. * The RX interrupt source is configured to get data from the RX -* FIFO and put into the ring buffer. +* FIFO and put into the ring buffer. * * \param base * The pointer to the UART SCB instance. @@ -1099,7 +1099,7 @@ void Cy_SCB_UART_SendBreakBlocking(CySCB_Type *base, uint32_t breakWidth) * This is the interrupt function for the SCB configured in the UART mode. * This function must be called inside a user-defined interrupt service * routine to make \ref Cy_SCB_UART_Transmit and \ref Cy_SCB_UART_Receive -* work. The ring buffer operation that enabled by calling \ref Cy_SCB_UART_StartRingBuffer +* work. The ring buffer operation that enabled by calling \ref Cy_SCB_UART_StartRingBuffer * also requires interrupt processing. * * \param base @@ -1458,4 +1458,3 @@ static void HandleDataTransmit(CySCB_Type *base, cy_stc_scb_uart_context_t *cont #endif /* CY_IP_MXSCB */ /* [] END OF FILE */ - diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_sd_host.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_sd_host.c index ee2830eebf..62c7be9cdd 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_sd_host.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_sd_host.c @@ -1,6 +1,6 @@ /******************************************************************************* * \file cy_sd_host.c -* \version 1.50 +* \version 1.50.1 * * \brief * This file provides the driver code to the API for the SD Host Controller @@ -35,7 +35,7 @@ extern "C" { /** \cond internal */ -/* Timeouts. */ +/* Timeouts. */ #define CY_SD_HOST_INT_CLK_STABLE_TIMEOUT_MS (150U) /* The Internal Clock Stable timeout. */ #define CY_SD_HOST_1_8_REG_STABLE_TIME_MS (30UL) /* The 1.8 voltage regulator stable time. */ #define CY_SD_HOST_SUPPLY_RAMP_UP_TIME_MS (35UL) /* The host supply ramp up time. */ @@ -53,12 +53,12 @@ extern "C" { #define CY_SD_HOST_READ_TIMEOUT_MS (100U) /* The Read timeout for one block. */ #define CY_SD_HOST_WRITE_TIMEOUT_MS (250U) /* The Write timeout for one block. */ #define CY_SD_HOST_MAX_TIMEOUT (0x0EU) /* The data max timeout for TOUT_CTRL_R. */ -#define CY_SD_HOST_NCC_MIN_CYCLES (8U) /* The period (clock cycles) between an end bit - * of the command and a start bit of the next command. +#define CY_SD_HOST_NCC_MIN_CYCLES (8U) /* The period (clock cycles) between an end bit + * of the command and a start bit of the next command. */ #define CY_SD_HOST_NCC_MIN_US ((1000U * CY_SD_HOST_NCC_MIN_CYCLES) / CY_SD_HOST_INIT_CLK_FREQUENCY_KHZ) -/* Commands codes. */ +/* Commands codes. */ #define CY_SD_HOST_SD_CMD0 (0UL) #define CY_SD_HOST_SD_CMD1 (1UL) #define CY_SD_HOST_SD_CMD2 (2UL) @@ -111,7 +111,7 @@ extern "C" { #define CY_SD_HOST_CMD5_MP_MASK (0x08000000UL) /* The Memory Present mask. */ #define CY_SD_HOST_IO_OCR_MASK (0x00FFFFFFUL) /* The IO OCR register mask. */ #define CY_SD_HOST_IO_OCR_C (0x80000000UL) /* The IO power up status (IORDY). */ -#define CY_SD_HOST_MIN_SDXC_SECTORS (67108864UL) /* Minimum sectors for SDXC: 32 Gbytes / 512. */ +#define CY_SD_HOST_MIN_SDXC_SECTORS (67108864UL) /* Minimum sectors for SDXC: 32 Gbytes / 512. */ #define CY_SD_HOST_MMC_LEGACY_SIZE_BYTES (0x200000UL) #define CY_SD_HOST_CMD8_VHS_27_36 (0x100UL) /* CMD8 voltage supplied 2.7-3.6 V. */ #define CY_SD_HOST_CMD8_PATTERN_MASK (0xFFUL) @@ -119,7 +119,7 @@ extern "C" { #define CY_SD_HOST_ACMD41_S18R (1UL << 24U) /* The 1.8 V request. */ #define CY_SD_HOST_ACMD41_HCS (1UL << 30U) /* SDHC or SDXC supported. */ #define CY_SD_HOST_OCR_S18A (1UL << 24U) /* The 1.8 V accepted. */ -#define CY_SD_HOST_OCR_35_36_V (1UL << 23U) /* The 3.5 - 3.6 voltage window. */ +#define CY_SD_HOST_OCR_35_36_V (1UL << 23U) /* The 3.5 - 3.6 voltage window. */ #define CY_SD_HOST_OCR_34_35_V (1UL << 22U) /* The 3.4 - 3.5 voltage window. */ #define CY_SD_HOST_OCR_33_34_V (1UL << 21U) /* The 3.3 - 3.4 voltage window. */ #define CY_SD_HOST_OCR_32_33_V (1UL << 20U) /* The 3.2 - 3.3 voltage window. */ @@ -138,8 +138,8 @@ extern "C" { CY_SD_HOST_OCR_28_29_V |\ CY_SD_HOST_OCR_27_28_V) #define CY_SD_HOST_ARG_ACMD41_BUSY (0x80000000UL) -#define CY_SD_HOST_OCR_BUSY_BIT (0x80000000UL) /* The Card power up status bit (busy). */ -#define CY_SD_HOST_OCR_CAPACITY_MASK (0x40000000UL) /* The OCR sector access mode bit. */ +#define CY_SD_HOST_OCR_BUSY_BIT (0x80000000UL) /* The Card power up status bit (busy). */ +#define CY_SD_HOST_OCR_CAPACITY_MASK (0x40000000UL) /* The OCR sector access mode bit. */ #define CY_SD_HOST_ACMD_OFFSET_MASK (0x3FUL) #define CY_SD_HOST_EMMC_DUAL_VOLTAGE (0x00000080UL) #define CY_SD_HOST_EMMC_VOLTAGE_WINDOW (CY_SD_HOST_OCR_CAPACITY_MASK |\ @@ -150,9 +150,9 @@ extern "C" { #define CY_SD_HOST_SWITCH_FUNCTION_BIT (31U) #define CY_SD_HOST_DEFAULT_SPEED (0UL) #define CY_SD_HOST_HIGH_SPEED (1UL) -#define CY_SD_HOST_SDR12_SPEED (0UL) /* The SDR12/Legacy speed. */ -#define CY_SD_HOST_SDR25_SPEED (1UL) /* The SDR25/High Speed SDR speed. */ -#define CY_SD_HOST_SDR50_SPEED (2UL) /* The SDR50 speed. */ +#define CY_SD_HOST_SDR12_SPEED (0UL) /* The SDR12/Legacy speed. */ +#define CY_SD_HOST_SDR25_SPEED (1UL) /* The SDR25/High Speed SDR speed. */ +#define CY_SD_HOST_SDR50_SPEED (2UL) /* The SDR50 speed. */ #define CY_SD_HOST_EMMC_BUS_WIDTH_ADDR (0xB7UL) #define CY_SD_HOST_EMMC_HS_TIMING_ADDR (0xB9UL) #define CY_SD_HOST_CMD23_BLOCKS_NUM_MASK (0xFFFFUL) @@ -168,7 +168,7 @@ extern "C" { #define CY_SD_HOST_FREQ_SEL_MSK (0xFFUL) #define CY_SD_HOST_UPPER_FREQ_SEL_POS (8U) -/* CMD6 SWITCH command bitfields. */ +/* CMD6 SWITCH command bitfields. */ #define CY_SD_HOST_EMMC_CMD6_ACCESS_OFFSET (24U) #define CY_SD_HOST_EMMC_CMD6_IDX_OFFSET (16U) #define CY_SD_HOST_EMMC_CMD6_VALUE_OFFSET (8U) @@ -180,7 +180,7 @@ extern "C" { #define CY_SD_HOST_EXTCSD_GENERIC_CMD6_TIME_MSK (0xFFUL) #define CY_SD_HOST_EXTCSD_SIZE (128U) -/* CSD register masks/positions. */ +/* CSD register masks/positions. */ #define CY_SD_HOST_CSD_V1_C_SIZE_MSB_MASK (0x00000003UL) #define CY_SD_HOST_CSD_V1_C_SIZE_ISB_MASK (0xFF000000UL) #define CY_SD_HOST_CSD_V1_C_SIZE_LSB_MASK (0x00C00000UL) @@ -208,13 +208,13 @@ extern "C" { #define CY_SD_HOST_CSD_MSB_MASK (0xFF000000UL) #define CY_SD_HOST_CSD_ISB_SHIFT (16U) -/* CMD6 EXT_CSD access mode. */ +/* CMD6 EXT_CSD access mode. */ #define CY_SD_HOST_EMMC_ACCESS_COMMAND_SET (0x0U) #define CY_SD_HOST_EMMC_ACCESS_SET_BITS (0x1U) #define CY_SD_HOST_EMMC_ACCESS_CLEAR_BITS (0x2U) #define CY_SD_HOST_EMMC_ACCESS_WRITE_BYTE (0x3UL) -/* CCCR register values. */ +/* CCCR register values. */ #define CY_SD_HOST_CCCR_SPEED_CONTROL (0x00013UL) #define CY_SD_HOST_CCCR_IO_ABORT (0x00006UL) #define CY_SD_HOST_CCCR_SPEED_SHS_MASK (0x1UL) @@ -226,7 +226,7 @@ extern "C" { #define CY_SD_HOST_CCCR_BUS_WIDTH_1 (0x2UL) #define CY_SD_HOST_CCCR_S8B (0x4UL) -/* SDMA constants. */ +/* SDMA constants. */ #define CY_SD_HOST_SDMA_BUF_BYTES_4K (0x0U) /* 4K bytes SDMA Buffer Boundary. */ #define CY_SD_HOST_SDMA_BUF_BYTES_8K (0x1U) /* 8K bytes SDMA Buffer Boundary. */ #define CY_SD_HOST_SDMA_BUF_BYTES_16K (0x2U) /* 16K bytes SDMA Buffer Boundary. */ @@ -257,8 +257,8 @@ extern "C" { /* Interrupt masks. */ #define CY_SD_HOST_NORMAL_INT_MSK (0x1FFFU) /* The enabled Normal Interrupts. */ -#define CY_SD_HOST_ERROR_INT_MSK (0x07FFU) /* The enabled Error Interrupts. */ - +#define CY_SD_HOST_ERROR_INT_MSK (0x07FFU) /* The enabled Error Interrupts. */ + /* SD output clock. */ #define CY_SD_HOST_CLK_400K (400UL * 1000UL) /* 400 kHz. */ #define CY_SD_HOST_CLK_10M (10UL * 1000UL * 1000UL) /* 10 MHz. */ @@ -273,7 +273,7 @@ extern "C" { #define CY_SD_HOST_IS_SD_BUS_WIDTH_VALID(width) ((CY_SD_HOST_BUS_WIDTH_1_BIT == (width)) || \ (CY_SD_HOST_BUS_WIDTH_4_BIT == (width))) - + #define CY_SD_HOST_IS_EMMC_BUS_WIDTH_VALID(width) ((CY_SD_HOST_BUS_WIDTH_1_BIT == (width)) || \ (CY_SD_HOST_BUS_WIDTH_4_BIT == (width)) || \ (CY_SD_HOST_BUS_WIDTH_8_BIT == (width))) @@ -286,8 +286,8 @@ extern "C" { (CY_SD_HOST_AUTO_CMD_12 == (cmd)) || \ (CY_SD_HOST_AUTO_CMD_23 == (cmd)) || \ (CY_SD_HOST_AUTO_CMD_AUTO == (cmd))) - -#define CY_SD_HOST_IS_TIMEOUT_VALID(timeout) (CY_SD_HOST_MAX_TIMEOUT >= (timeout)) + +#define CY_SD_HOST_IS_TIMEOUT_VALID(timeout) (CY_SD_HOST_MAX_TIMEOUT >= (timeout)) #define CY_SD_HOST_BLK_SIZE_MAX (2048UL) /* The maximum block size. */ #define CY_SD_HOST_IS_BLK_SIZE_VALID(size) (CY_SD_HOST_BLK_SIZE_MAX >= (size)) @@ -315,15 +315,15 @@ extern "C" { (CY_SD_HOST_BUS_SPEED_SDR50 == (speedMode)) || \ (CY_SD_HOST_BUS_SPEED_EMMC_LEGACY == (speedMode)) || \ (CY_SD_HOST_BUS_SPEED_EMMC_HIGHSPEED_SDR == (speedMode))) - + #define CY_SD_HOST_IS_DMA_WR_RD_VALID(dmaType) ((CY_SD_HOST_DMA_SDMA == (dmaType)) || \ (CY_SD_HOST_DMA_ADMA2 == (dmaType))) - + #define CY_SD_HOST_IS_CMD_TYPE_VALID(cmdType) ((CY_SD_HOST_CMD_NORMAL == (cmdType)) || \ (CY_SD_HOST_CMD_SUSPEND == (cmdType)) || \ (CY_SD_HOST_CMD_RESUME == (cmdType)) || \ (CY_SD_HOST_CMD_ABORT == (cmdType))) - + #define CY_SD_HOST_IS_RELIABLE_WRITE(cardType, rw) ((CY_SD_HOST_EMMC != (cardType)) && \ (false == (rw))) @@ -383,7 +383,7 @@ __STATIC_INLINE cy_en_sd_host_status_t Cy_SD_Host_IoOcr(SDHC_Type *base, bool lowVoltageSignaling, uint32_t *s18aFlag, uint32_t *sdioFlag, - bool *mpFlag, + bool *mpFlag, uint32_t *ocrReg); __STATIC_INLINE cy_en_sd_host_status_t Cy_SD_Host_SdOcr(SDHC_Type *base, bool lowVoltageSignaling, @@ -436,7 +436,7 @@ __STATIC_INLINE cy_en_sd_host_status_t Cy_SD_Host_eMMC_InitCard(SDHC_Type *base, /* Reset Card (CMD0). */ ret = Cy_SD_Host_OpsGoIdle(base); /* The Idle state. */ - + /* Software reset for the CMD line */ Cy_SD_Host_SoftwareReset(base, CY_SD_HOST_RESET_DATALINE); Cy_SD_Host_SoftwareReset(base, CY_SD_HOST_RESET_CMD_LINE); @@ -474,9 +474,9 @@ __STATIC_INLINE cy_en_sd_host_status_t Cy_SD_Host_eMMC_InitCard(SDHC_Type *base, { /* Power down the MMC bus */ Cy_SD_Host_DisableCardVoltage(base); - + Cy_SysLib_Delay(CY_SD_HOST_1_8_REG_STABLE_TIME_MS); - + /* Switch the bus to 1.8 V */ Cy_SD_Host_ChangeIoVoltage(base, CY_SD_HOST_IO_VOLT_1_8V); @@ -508,7 +508,7 @@ __STATIC_INLINE cy_en_sd_host_status_t Cy_SD_Host_eMMC_InitCard(SDHC_Type *base, { /* Get CID (CMD2). */ ret = Cy_SD_Host_GetCid(base, cidReg); - + Cy_SysLib_DelayUs(CY_SD_HOST_NCC_MIN_US); if (CY_SD_HOST_SUCCESS == ret) /* The Identification state. */ @@ -520,7 +520,7 @@ __STATIC_INLINE cy_en_sd_host_status_t Cy_SD_Host_eMMC_InitCard(SDHC_Type *base, /* Get CSD (CMD9) */ ret = Cy_SD_Host_GetCsd(base, csdReg, context); - + if (CY_SD_HOST_SUCCESS == ret) { /* Select the card (CMD7). */ @@ -534,8 +534,8 @@ __STATIC_INLINE cy_en_sd_host_status_t Cy_SD_Host_eMMC_InitCard(SDHC_Type *base, ret = Cy_SD_Host_GetExtCsd(base, extCsd, context); /* Get GENERIC_CMD6_TIME [248] of the EXTCSD register */ - genericCmd6Time = CY_SD_HOST_EMMC_CMD6_TIMEOUT_MULT * - (extCsd[CY_SD_HOST_EXTCSD_GENERIC_CMD6_TIME] & + genericCmd6Time = CY_SD_HOST_EMMC_CMD6_TIMEOUT_MULT * + (extCsd[CY_SD_HOST_EXTCSD_GENERIC_CMD6_TIME] & CY_SD_HOST_EXTCSD_GENERIC_CMD6_TIME_MSK); if ((CY_SD_HOST_SUCCESS == ret) && @@ -593,9 +593,9 @@ __STATIC_INLINE cy_en_sd_host_status_t Cy_SD_Host_eMMC_InitCard(SDHC_Type *base, * * \return \ref cy_en_sd_host_status_t * -* \note When lowVoltageSignaling is True, this function negotiates with +* \note When lowVoltageSignaling is True, this function negotiates with * the card to change the bus signaling level to 1.8V. -* The dedicated io_volt_sel pin is used to change the regulator supplying voltage +* The dedicated io_volt_sel pin is used to change the regulator supplying voltage * to the VDDIO of the SD block in order to operate at 1.8V. To configure * the custom IO pin in order to control (using the GPIO driver) the regulator * supplying voltage, the user must implement weak Cy_SD_Host_ChangeIoVoltage(). @@ -603,16 +603,16 @@ __STATIC_INLINE cy_en_sd_host_status_t Cy_SD_Host_eMMC_InitCard(SDHC_Type *base, * register when ioVoltage = CY_SD_HOST_IO_VOLT_1_8V. * * \note After calling this function, the SD Host is configured in -* Default Speed mode (for the SD card), or SDR12 Speed mode +* Default Speed mode (for the SD card), or SDR12 Speed mode * (when lowVoltageSignaling is true), or eMMC legacy (for the eMMC card) * with SD clock = 25 MHz. The Power Limit and Driver Strength functions of * the CMD6 command are set into the default state (0.72 W and Type B). * It is the user's responsibility to set Power Limit and Driver Strength * depending on the capacitance load of the host system. -* To change Speed mode, the user must call the Cy_SD_Host_SetBusSpeedMode() +* To change Speed mode, the user must call the Cy_SD_Host_SetBusSpeedMode() * and Cy_SD_Host_SdCardChangeClock() functions. -* Additionally, SD SDR25, SD SDR50, eMMC High Speed SDR modes require -* settings CLOCK_OUT_DLY and CLOCK_IN_DLY bit-fields of the GP_OUT_R register. +* Additionally, SD SDR25, SD SDR50, eMMC High Speed SDR modes require +* settings CLOCK_OUT_DLY and CLOCK_IN_DLY bit-fields of the GP_OUT_R register. * For more information about Speed modes, refer to Part 1 Physical Layer * SD Specification. *******************************************************************************/ @@ -629,30 +629,30 @@ cy_en_sd_host_status_t Cy_SD_Host_InitCard(SDHC_Type *base, uint32_t s18aFlag = 0UL; /* The S18A flag. */ bool f8Flag = false; /* The CMD8 flag. */ bool mpFlag = false; /* The MEM flag. */ - + if ((NULL != base) && (NULL != context) && (NULL != config)) { - CY_ASSERT_L3(CY_SD_HOST_IS_BUS_WIDTH_VALID(config->busWidth, context->cardType)); - + CY_ASSERT_L3(CY_SD_HOST_IS_BUS_WIDTH_VALID(config->busWidth, context->cardType)); + /* Wait until the card is stable and check if it is connected. */ - if ((true == Cy_SD_Host_IsCardConnected(base)) || + if ((true == Cy_SD_Host_IsCardConnected(base)) || (CY_SD_HOST_EMMC == context->cardType)) - { + { Cy_SD_Host_EnableCardVoltage(base); Cy_SD_Host_ChangeIoVoltage(base, CY_SD_HOST_IO_VOLT_3_3V); - + /* Set the host bus width to 1 bit. */ (void)Cy_SD_Host_SetHostBusWidth(base, CY_SD_HOST_BUS_WIDTH_1_BIT); - + /* Change the host SD clock to 400 kHz. */ (void)Cy_SD_Host_SdCardChangeClock(base, CY_SD_HOST_CLK_400K); /* Wait until the voltage and clock are stable. */ Cy_SysLib_Delay(CY_SD_HOST_BUS_RAMP_UP_TIME_MS); - + context->RCA = 0UL; - + if (CY_SD_HOST_EMMC != context->cardType) { /* Send CMD0 and CMD8 commands. */ @@ -663,16 +663,16 @@ cy_en_sd_host_status_t Cy_SD_Host_InitCard(SDHC_Type *base, { context->cardCapacity = CY_SD_HOST_SDHC; } - + /* Clear the insert event */ Cy_SD_Host_NormalReset(base); - /* Send CMD5 to get IO OCR */ + /* Send CMD5 to get IO OCR */ ret = Cy_SD_Host_IoOcr(base, config->lowVoltageSignaling, &s18aFlag, &sdioFlag, - &mpFlag, + &mpFlag, &ocrReg); /* Check if CMD5 has no response or MP = 1. @@ -689,21 +689,21 @@ cy_en_sd_host_status_t Cy_SD_Host_InitCard(SDHC_Type *base, &ocrReg, context); } - + /* Set the card type */ if (CY_SD_HOST_ERROR_UNUSABLE_CARD != ret) /* The Ready state. */ { if (true == mpFlag) { if (0UL != sdioFlag) - { + { context->cardType = CY_SD_HOST_COMBO; } else { - context->cardType = CY_SD_HOST_SD; + context->cardType = CY_SD_HOST_SD; } - } + } else if (0UL != sdioFlag) { context->cardType = CY_SD_HOST_SDIO; @@ -722,17 +722,17 @@ cy_en_sd_host_status_t Cy_SD_Host_InitCard(SDHC_Type *base, { /* Voltage switch (CMD11). */ ret = Cy_SD_Host_OpsVoltageSwitch(base, context); - + if (CY_SD_HOST_SUCCESS != ret) /* Initialize again at 3.3 V. */ - { + { Cy_SD_Host_ChangeIoVoltage(base, CY_SD_HOST_IO_VOLT_3_3V); /* Wait until the voltage and clock are stable. */ Cy_SysLib_Delay(CY_SD_HOST_BUS_RAMP_UP_TIME_MS); - + /* Send CMD0 and CMD8 commands. */ - f8Flag = Cy_SD_Host_VoltageCheck(base); - + f8Flag = Cy_SD_Host_VoltageCheck(base); + if (0UL < sdioFlag) { /* Send CMD5 to get IO OCR. */ @@ -740,7 +740,7 @@ cy_en_sd_host_status_t Cy_SD_Host_InitCard(SDHC_Type *base, config->lowVoltageSignaling, &s18aFlag, &sdioFlag, - &mpFlag, + &mpFlag, &ocrReg); } @@ -755,36 +755,36 @@ cy_en_sd_host_status_t Cy_SD_Host_InitCard(SDHC_Type *base, &ocrReg, context); } - + s18aFlag = 0UL; } } - + if (CY_SD_HOST_SDIO != context->cardType) { /* Get CID (CMD2). */ ret = Cy_SD_Host_GetCid(base, cidReg); - + Cy_SysLib_DelayUs(CY_SD_HOST_NCC_MIN_US); } /* The Identification state. */ /* Get RCA (CMD3). */ context->RCA = Cy_SD_Host_GetRca(base); - + Cy_SysLib_DelayUs(CY_SD_HOST_NCC_MIN_US); - + if (CY_SD_HOST_SDIO != context->cardType) /* The stand-by state. */ { /* Get CSD (CMD9) to save * Max Sector Number in the context. */ ret = Cy_SD_Host_GetCsd(base, csdReg, context); - + if (CY_SD_HOST_MIN_SDXC_SECTORS <= context->maxSectorNum) { context->cardCapacity = CY_SD_HOST_SDXC; } - + Cy_SysLib_DelayUs(CY_SD_HOST_NCC_MIN_US); } @@ -803,7 +803,7 @@ cy_en_sd_host_status_t Cy_SD_Host_InitCard(SDHC_Type *base, ret = Cy_SD_Host_SetBusWidth(base, CY_SD_HOST_BUS_WIDTH_4_BIT, context); - Cy_SysLib_Delay(CY_SD_HOST_READ_TIMEOUT_MS); + Cy_SysLib_Delay(CY_SD_HOST_READ_TIMEOUT_MS); } if (CY_SD_HOST_SUCCESS == ret) @@ -817,7 +817,7 @@ cy_en_sd_host_status_t Cy_SD_Host_InitCard(SDHC_Type *base, ret = Cy_SD_Host_SetBusSpeedMode(base, speedMode, context); - Cy_SysLib_Delay(CY_SD_HOST_READ_TIMEOUT_MS); + Cy_SysLib_Delay(CY_SD_HOST_READ_TIMEOUT_MS); if (CY_SD_HOST_SUCCESS == ret) { @@ -834,7 +834,7 @@ cy_en_sd_host_status_t Cy_SD_Host_InitCard(SDHC_Type *base, { ret = Cy_SD_Host_eMMC_InitCard(base, config, context); } - + *config->rca = context->RCA; *config->cardType = context->cardType; *config->cardCapacity = context->cardCapacity; @@ -856,10 +856,10 @@ cy_en_sd_host_status_t Cy_SD_Host_InitCard(SDHC_Type *base, * * Reads single- or multiple-block data from the SD card / eMMC. If DMA is not used * this function blocks until all data is read. -* If DMA is used all data is read when the Transfer complete event is set. -* It is the user responsibility to check and reset the transfer complete event -* (using \ref Cy_SD_Host_GetNormalInterruptStatus and -* \ref Cy_SD_Host_ClearNormalInterruptStatus functions). +* If DMA is used all data is read when the Transfer complete event is set. +* It is the user responsibility to check and reset the transfer complete event +* (using \ref Cy_SD_Host_GetNormalInterruptStatus and +* \ref Cy_SD_Host_ClearNormalInterruptStatus functions). * * \param *base * The SD host registers structure pointer. @@ -894,7 +894,7 @@ cy_en_sd_host_status_t Cy_SD_Host_Read(SDHC_Type *base, CY_ASSERT_L3(CY_SD_HOST_IS_AUTO_CMD_VALID(config->autoCommand)); CY_ASSERT_L2(CY_SD_HOST_IS_TIMEOUT_VALID(config->dataTimeout)); CY_ASSERT_L3(CY_SD_HOST_IS_DMA_WR_RD_VALID(context->dmaType)); - + /* 0 < maxSectorNum check is needed for legacy cards. */ if (!((0UL < context->maxSectorNum) && ((context->maxSectorNum - dataAddress) < config->numberOfBlocks))) @@ -923,7 +923,7 @@ cy_en_sd_host_status_t Cy_SD_Host_Read(SDHC_Type *base, dataConfig.dataTimeout = config->dataTimeout; dataConfig.enReliableWrite = config->enReliableWrite; - if ((true == dataConfig.enableDma) && + if ((true == dataConfig.enableDma) && (CY_SD_HOST_DMA_ADMA2 == context->dmaType)) { length = CY_SD_HOST_BLOCK_SIZE * config->numberOfBlocks; @@ -958,13 +958,13 @@ cy_en_sd_host_status_t Cy_SD_Host_Read(SDHC_Type *base, cmd.cmdType = CY_SD_HOST_CMD_NORMAL; ret = Cy_SD_Host_SendCommand(base, &cmd); - + if (CY_SD_HOST_SUCCESS == ret) { /* Wait for the Command Complete event. */ ret = Cy_SD_Host_PollCmdComplete(base); } - + if ((CY_SD_HOST_SUCCESS == ret) && (false == dataConfig.enableDma)) { @@ -983,11 +983,11 @@ cy_en_sd_host_status_t Cy_SD_Host_Read(SDHC_Type *base, * Function Name: Cy_SD_Host_Write ****************************************************************************//** * -* Writes single- or multiple-block data to the SD card / eMMC. If DMA is not +* Writes single- or multiple-block data to the SD card / eMMC. If DMA is not * used this function blocks until all data is written. -* If DMA is used all data is written when the Transfer complete event is set. -* It is the user responsibility to check and reset the transfer complete event -* (using \ref Cy_SD_Host_GetNormalInterruptStatus and +* If DMA is used all data is written when the Transfer complete event is set. +* It is the user responsibility to check and reset the transfer complete event +* (using \ref Cy_SD_Host_GetNormalInterruptStatus and * \ref Cy_SD_Host_ClearNormalInterruptStatus functions). * * \param *base @@ -1044,7 +1044,7 @@ cy_en_sd_host_status_t Cy_SD_Host_Write(SDHC_Type *base, cmd.commandIndex = CY_SD_HOST_SD_CMD24; dataConfig.enableIntAtBlockGap = false; } - + dataConfig.blockSize = CY_SD_HOST_BLOCK_SIZE; dataConfig.numberOfBlock = config->numberOfBlocks; dataConfig.enableDma = config->enableDma; @@ -1054,7 +1054,7 @@ cy_en_sd_host_status_t Cy_SD_Host_Write(SDHC_Type *base, dataConfig.dataTimeout = config->dataTimeout; dataConfig.enReliableWrite = config->enReliableWrite; - if ((true == dataConfig.enableDma) && + if ((true == dataConfig.enableDma) && (CY_SD_HOST_DMA_ADMA2 == context->dmaType)) { length = CY_SD_HOST_BLOCK_SIZE * config->numberOfBlocks; @@ -1088,13 +1088,13 @@ cy_en_sd_host_status_t Cy_SD_Host_Write(SDHC_Type *base, cmd.cmdType = CY_SD_HOST_CMD_NORMAL; ret = Cy_SD_Host_SendCommand(base, &cmd); - + if (CY_SD_HOST_SUCCESS == ret) { /* Wait for the Command Complete event. */ ret = Cy_SD_Host_PollCmdComplete(base); } - + if ((CY_SD_HOST_SUCCESS == ret) && (false == dataConfig.enableDma)) { @@ -1120,7 +1120,7 @@ cy_en_sd_host_status_t Cy_SD_Host_Write(SDHC_Type *base, * The erase operation completes when ref\ Cy_SD_Host_GetCardStatus returns * the status value where both ready-for-data (CY_SD_HOST_CMD13_READY_FOR_DATA) * and card-transition (CY_SD_HOST_CARD_TRAN) bits are set. -* Also it is the user's responsibility to clear the CY_SD_HOST_CMD_COMPLETE flag +* Also it is the user's responsibility to clear the CY_SD_HOST_CMD_COMPLETE flag * after calling this function. * * \param *base @@ -1156,7 +1156,7 @@ cy_en_sd_host_status_t Cy_SD_Host_Erase(SDHC_Type *base, cy_stc_sd_host_cmd_config_t cmd; if ((NULL != context) && (NULL != base)) - { + { /* 0maxSectorNum) && ((context->maxSectorNum < (startAddr)) || @@ -1188,7 +1188,7 @@ cy_en_sd_host_status_t Cy_SD_Host_Erase(SDHC_Type *base, cmd.commandArgument = startAddr; ret = Cy_SD_Host_SendCommand(base, &cmd); - + if (CY_SD_HOST_SUCCESS == ret) { /* Wait for the Command Complete event. */ @@ -1213,7 +1213,7 @@ cy_en_sd_host_status_t Cy_SD_Host_Erase(SDHC_Type *base, cmd.commandArgument = endAddr; ret = Cy_SD_Host_SendCommand(base, &cmd); - + if (CY_SD_HOST_SUCCESS == ret) { /* Wait for the Command Complete event. */ @@ -1358,7 +1358,7 @@ __STATIC_INLINE cy_en_sd_host_status_t Cy_SD_Host_PollDataLineFree(SDHC_Type con cy_en_sd_host_status_t ret = CY_SD_HOST_SUCCESS; uint32_t retry = CY_SD_HOST_RETRY_TIME; - while ((true == _FLD2BOOL(SDHC_CORE_PSTATE_REG_DAT_LINE_ACTIVE, SDHC_CORE_PSTATE_REG(base))) && + while ((true == _FLD2BOOL(SDHC_CORE_PSTATE_REG_DAT_LINE_ACTIVE, SDHC_CORE_PSTATE_REG(base))) && (retry > 0UL)) { Cy_SysLib_DelayUs(CY_SD_HOST_WRITE_TIMEOUT_MS); @@ -1530,8 +1530,8 @@ __STATIC_INLINE cy_en_sd_host_status_t Cy_SD_Host_PollTransferComplete(SDHC_Type * Function Name: Cy_SD_Host_CmdRxData ****************************************************************************//** * -* Reads the command data using a non-DMA data transfer. -* This function is blocking (it exits after all data is read). +* Reads the command data using a non-DMA data transfer. +* This function is blocking (it exits after all data is read). * * \param *base * The SD host registers structure pointer. @@ -1572,7 +1572,7 @@ static cy_en_sd_host_status_t Cy_SD_Host_CmdRxData(SDHC_Type *base, SDHC_CORE_PSTATE_REG(base))) && (retry > 0UL)) { - Cy_SysLib_DelayUs(CY_SD_HOST_RD_WR_ENABLE_TIMEOUT); + Cy_SysLib_DelayUs(CY_SD_HOST_RD_WR_ENABLE_TIMEOUT); retry--; } @@ -1603,7 +1603,7 @@ static cy_en_sd_host_status_t Cy_SD_Host_CmdRxData(SDHC_Type *base, * Function Name: Cy_SD_Host_CmdTxData ****************************************************************************//** * -* Writes the command data using a non-DMA data transfer. +* Writes the command data using a non-DMA data transfer. * This function is blocking (it exits after all data is written). * * \param *base @@ -1685,7 +1685,7 @@ __STATIC_INLINE cy_en_sd_host_status_t Cy_SD_Host_CmdTxData(SDHC_Type *base, * and check the CMD_COMPLETE flag. To determine if the entire transfer is done * check the XFER_COMPLETE flag. Also the interrupt is used and flags are set * on these events in an ISR. -* \note It is the user's responsibility to clear the CY_SD_HOST_CMD_COMPLETE flag +* \note It is the user's responsibility to clear the CY_SD_HOST_CMD_COMPLETE flag * after calling this function. * * \param *base @@ -1712,10 +1712,10 @@ cy_en_sd_host_status_t Cy_SD_Host_SendCommand(SDHC_Type *base, { if ((true == config->dataPresent) && (CY_SD_HOST_CMD_ABORT != config->cmdType)) { - /* Check the DAT line inhibits only commands with the DAT line is used - * and when the command is not the ABORT type. + /* Check the DAT line inhibits only commands with the DAT line is used + * and when the command is not the ABORT type. */ - ret = Cy_SD_Host_PollDataLineNotInhibit(base); + ret = Cy_SD_Host_PollDataLineNotInhibit(base); } if (CY_SD_HOST_SUCCESS == ret) @@ -1908,13 +1908,13 @@ static cy_en_sd_host_status_t Cy_SD_Host_OpsGoIdle(SDHC_Type *base) cmd.cmdType = CY_SD_HOST_CMD_ABORT; ret = Cy_SD_Host_SendCommand(base, &cmd); - + if (CY_SD_HOST_SUCCESS == ret) { /* Wait for the Command Complete event. */ ret = Cy_SD_Host_PollCmdComplete(base); } - + Cy_SysLib_DelayUs(CY_SD_HOST_NCC_MIN_US); return ret; @@ -1949,15 +1949,15 @@ static cy_en_sd_host_status_t Cy_SD_Host_OpsVoltageSwitch(SDHC_Type *base, cmd.enableIdxCheck = true; cmd.dataPresent = false; cmd.cmdType = CY_SD_HOST_CMD_NORMAL; - + ret = Cy_SD_Host_SendCommand(base, &cmd); - + if (CY_SD_HOST_SUCCESS == ret) { /* Wait for the Command Complete event. */ ret = Cy_SD_Host_PollCmdComplete(base); } - + Cy_SysLib_DelayUs(CY_SD_HOST_NCC_MIN_US); if ((CY_SD_HOST_SUCCESS == ret) && (CY_SD_HOST_SDIO != context->cardType)) @@ -2044,9 +2044,9 @@ static cy_en_sd_host_status_t Cy_SD_Host_OpsSendIoRwDirectCmd(SDHC_Type *base, cmd.enableCrcCheck = true; cmd.enableIdxCheck = true; cmd.cmdType = CY_SD_HOST_CMD_NORMAL; - + ret = Cy_SD_Host_SendCommand(base, &cmd); - + if (CY_SD_HOST_SUCCESS == ret) { /* Wait for the Command Complete event. */ @@ -2098,13 +2098,13 @@ static cy_en_sd_host_status_t Cy_SD_Host_OpsSendAppCmd(SDHC_Type *base, cmd.cmdType = CY_SD_HOST_CMD_NORMAL; ret = Cy_SD_Host_SendCommand(base, &cmd); - + if (CY_SD_HOST_SUCCESS == ret) { /* Wait for the Command Complete event. */ ret = Cy_SD_Host_PollCmdComplete(base); } - + Cy_SysLib_DelayUs(CY_SD_HOST_NCC_MIN_US); return ret; @@ -2155,13 +2155,13 @@ __STATIC_INLINE cy_en_sd_host_status_t Cy_SD_Host_OpsSendIfCond(SDHC_Type *base, } ret = Cy_SD_Host_SendCommand(base, &cmd); - + if (CY_SD_HOST_SUCCESS == ret) { /* Wait for the Command Complete event. */ ret = Cy_SD_Host_PollCmdComplete(base); } - + Cy_SysLib_DelayUs(CY_SD_HOST_NCC_MIN_US); return ret; @@ -2189,20 +2189,20 @@ static cy_en_sd_host_status_t Cy_SD_Host_OpsSelectCard(SDHC_Type *base, cmd.commandIndex = CY_SD_HOST_SD_CMD7; cmd.commandArgument = context->RCA << CY_SD_HOST_RCA_SHIFT; cmd.dataPresent = false; - cmd.enableAutoResponseErrorCheck = false; + cmd.enableAutoResponseErrorCheck = false; cmd.respType = CY_SD_HOST_RESPONSE_LEN_48B; cmd.enableCrcCheck = false; cmd.enableIdxCheck = false; cmd.cmdType = CY_SD_HOST_CMD_NORMAL; ret = Cy_SD_Host_SendCommand(base, &cmd); - + if (CY_SD_HOST_SUCCESS == ret) { /* Wait for the Command Complete event. */ ret = Cy_SD_Host_PollCmdComplete(base); } - + Cy_SysLib_DelayUs(CY_SD_HOST_NCC_MIN_US); /* The R1b response requires sending an optional busy @@ -2256,13 +2256,13 @@ __STATIC_INLINE cy_en_sd_host_status_t Cy_SD_Host_OpsSetSdBusWidth(SDHC_Type *ba if (CY_SD_HOST_SUCCESS == ret) { ret = Cy_SD_Host_SendCommand(base, &cmd); - + if (CY_SD_HOST_SUCCESS == ret) { /* Wait for the Command Complete event. */ ret = Cy_SD_Host_PollCmdComplete(base); } - + Cy_SysLib_DelayUs(CY_SD_HOST_NCC_MIN_US); } @@ -2297,13 +2297,13 @@ static cy_en_sd_host_status_t Cy_SD_Host_OpsSwitchFunc(SDHC_Type *base, uint32_t cmd.cmdType = CY_SD_HOST_CMD_NORMAL; ret = Cy_SD_Host_SendCommand(base, &cmd); - + if (CY_SD_HOST_SUCCESS == ret) { /* Wait for the Command Complete event. */ ret = Cy_SD_Host_PollCmdComplete(base); } - + Cy_SysLib_DelayUs(CY_SD_HOST_NCC_MIN_US); return ret; @@ -2343,13 +2343,13 @@ __STATIC_INLINE cy_en_sd_host_status_t Cy_SD_Host_OpsSetBlockCount(SDHC_Type *ba cmd.cmdType = CY_SD_HOST_CMD_NORMAL; ret = Cy_SD_Host_SendCommand(base, &cmd); - + if (CY_SD_HOST_SUCCESS == ret) { /* Wait for the Command Complete event. */ ret = Cy_SD_Host_PollCmdComplete(base); } - + Cy_SysLib_DelayUs(CY_SD_HOST_NCC_MIN_US); return ret; @@ -2400,13 +2400,13 @@ __STATIC_INLINE cy_en_sd_host_status_t Cy_SD_Host_OpsProgramCsd(SDHC_Type *base, dataConfig.dataTimeout = CY_SD_HOST_MAX_TIMEOUT; dataConfig.enableIntAtBlockGap = false; dataConfig.enReliableWrite = false; - + /* The CSD register is sent using DAT lines. Initialize a data transfer in Non-DMA mode. */ (void)Cy_SD_Host_InitDataTransfer(base, &dataConfig); /* Send the program CSD command (CMD27) */ ret = Cy_SD_Host_SendCommand(base, &cmd); - + if (CY_SD_HOST_SUCCESS == ret) { /* Wait for the Command Complete event. */ @@ -2422,27 +2422,27 @@ __STATIC_INLINE cy_en_sd_host_status_t Cy_SD_Host_OpsProgramCsd(SDHC_Type *base, { /* The CSD register is sent a using usual data (8-bit width) type of the Data packet format. * The usual data (8-bit width) is sent in the LSB (Least Significant Byte) first, - * MSB (Most Significant Byte) last. The bytes in each context->csd[] element + * MSB (Most Significant Byte) last. The bytes in each context->csd[] element * should be reordered and shifted right to one byte. */ csdTepm = ((context->csd[i-1UL] & CY_SD_HOST_CSD_ISBL_MASK) >> CY_SD_HOST_CSD_ISB_SHIFT) | (context->csd[i-1UL] & CY_SD_HOST_CSD_ISBR_MASK) | ((context->csd[i-1UL] & CY_SD_HOST_CSD_LSB_MASK) << CY_SD_HOST_CSD_ISB_SHIFT); - + if (i > 1UL) { - csdTepm |= (context->csd[i-2UL] & CY_SD_HOST_CSD_MSB_MASK); + csdTepm |= (context->csd[i-2UL] & CY_SD_HOST_CSD_MSB_MASK); } else { csdTepm &= ~((1UL << CY_SD_HOST_CSD_TEMP_WRITE_PROTECT) | /* Clear TMP_WRITE_PROTECT bit in the CSD register. */ - CY_SD_HOST_CSD_MSB_MASK); + CY_SD_HOST_CSD_MSB_MASK); csdTepm |= csd; /* Set writable bits of the CSD register. */ } (void)Cy_SD_Host_BufferWrite(base, csdTepm); } - + /* Wait for the transfer complete */ ret = Cy_SD_Host_PollTransferComplete(base); @@ -2491,19 +2491,19 @@ static cy_en_sd_host_status_t Cy_SD_Host_OpsSdioSendOpCond(SDHC_Type *base, /* Send the SDIO operation condition command (CMD5) */ ret = Cy_SD_Host_SendCommand(base, &cmd); - + if (CY_SD_HOST_SUCCESS == ret) { /* Wait for the Command Complete event. */ ret = Cy_SD_Host_PollCmdComplete(base); } - + Cy_SysLib_DelayUs(CY_SD_HOST_NCC_MIN_US); (void)Cy_SD_Host_GetResponse(base, (uint32_t *)&response, false); *ocrReg = response; - + return ret; } @@ -2555,7 +2555,7 @@ static cy_en_sd_host_status_t Cy_SD_Host_OpsSdSendOpCond(SDHC_Type *base, if (CY_SD_HOST_SUCCESS == ret) { ret = Cy_SD_Host_SendCommand(base, &cmd); - + if (CY_SD_HOST_SUCCESS == ret) { /* Wait for the Command Complete event. */ @@ -2563,7 +2563,7 @@ static cy_en_sd_host_status_t Cy_SD_Host_OpsSdSendOpCond(SDHC_Type *base, } Cy_SysLib_DelayUs(CY_SD_HOST_NCC_MIN_US); - + (void)Cy_SD_Host_GetResponse(base, (uint32_t *)&response, false); *ocrReg = response; @@ -2628,13 +2628,13 @@ static cy_en_sd_host_status_t Cy_SD_Host_MmcOpsSendOpCond(SDHC_Type *base, cmd.cmdType = CY_SD_HOST_CMD_NORMAL; ret = Cy_SD_Host_SendCommand(base, &cmd); - + if (CY_SD_HOST_SUCCESS == ret) { /* Wait for the Command Complete event. */ ret = Cy_SD_Host_PollCmdComplete(base); } - + Cy_SysLib_DelayUs(CY_SD_HOST_NCC_MIN_US); /* Get the OCR register */ @@ -2720,14 +2720,14 @@ cy_en_sd_host_status_t Cy_SD_Host_Init(SDHC_Type *base, if ((NULL != base) && (NULL != config) && (NULL != context)) { CY_ASSERT_L3(CY_SD_HOST_IS_DMA_VALID(config->dmaType)); - + SDHC_CORE_GP_OUT_R(base) = _VAL2FLD(SDHC_CORE_GP_OUT_R_IO_VOLT_SEL_OE, 1u) | /* The IO voltage selection signal. */ _VAL2FLD(SDHC_CORE_GP_OUT_R_CARD_MECH_WRITE_PROT_EN, 1u) | /* The mechanical write protection. */ _VAL2FLD(SDHC_CORE_GP_OUT_R_LED_CTRL_OE, config->enableLedControl ? 1u : 0u) | /* The LED Control. */ _VAL2FLD(SDHC_CORE_GP_OUT_R_CARD_CLOCK_OE, 1u) | /* The Sd Clk. */ _VAL2FLD(SDHC_CORE_GP_OUT_R_CARD_IF_PWR_EN_OE, 1u) | /* Enable the card_if_pwr_en. */ _VAL2FLD(SDHC_CORE_GP_OUT_R_CARD_DETECT_EN, 1u); /* Enable the card detection. */ - + SDHC_CORE_XFER_MODE_R(base) = 0U; context->dmaType = config->dmaType; @@ -2748,9 +2748,9 @@ cy_en_sd_host_status_t Cy_SD_Host_Init(SDHC_Type *base, /* Save the card type. */ context->cardType = CY_SD_HOST_NOT_EMMC; } - + if (config->enableLedControl) - { + { /* LED Control. */ SDHC_CORE_HOST_CTRL1_R(base) = (uint8_t)_CLR_SET_FLD8U(SDHC_CORE_HOST_CTRL1_R(base), SDHC_CORE_HOST_CTRL1_R_LED_CTRL, @@ -2761,7 +2761,7 @@ cy_en_sd_host_status_t Cy_SD_Host_Init(SDHC_Type *base, SDHC_CORE_HOST_CTRL1_R(base) = (uint8_t)_CLR_SET_FLD8U(SDHC_CORE_HOST_CTRL1_R(base), SDHC_CORE_HOST_CTRL1_R_DMA_SEL, config->dmaType); - + /* Set the data timeout to the max. */ SDHC_CORE_TOUT_CTRL_R(base) = _CLR_SET_FLD8U(SDHC_CORE_TOUT_CTRL_R(base), SDHC_CORE_TOUT_CTRL_R_TOUT_CNT, @@ -2778,7 +2778,7 @@ cy_en_sd_host_status_t Cy_SD_Host_Init(SDHC_Type *base, /* Wait for the Host stable voltage. */ Cy_SysLib_Delay(CY_SD_HOST_SUPPLY_RAMP_UP_TIME_MS); - + /* Reset normal events. */ Cy_SD_Host_NormalReset(base); } @@ -2810,7 +2810,7 @@ void Cy_SD_Host_DeInit(SDHC_Type *base) (void)Cy_SD_Host_PollDataLineNotInhibit(base); Cy_SD_Host_SoftwareReset(base, CY_SD_HOST_RESET_ALL); - + /* Disable the SDHC block. */ SDHC_WRAP_CTL(base) = _CLR_SET_FLD32U(SDHC_WRAP_CTL(base), SDHC_WRAP_CTL_ENABLE, @@ -2873,7 +2873,7 @@ cy_en_sd_host_status_t Cy_SD_Host_AbortTransfer(SDHC_Type *base, cmd.commandIndex = CY_SD_HOST_SD_CMD12; cmd.cmdType = CY_SD_HOST_CMD_ABORT; ret = Cy_SD_Host_SendCommand(base, &cmd); - + if (CY_SD_HOST_SUCCESS == ret) { /* Wait for the Command Complete event. */ @@ -2883,60 +2883,60 @@ cy_en_sd_host_status_t Cy_SD_Host_AbortTransfer(SDHC_Type *base, Cy_SysLib_DelayUs(CY_SD_HOST_NCC_MIN_US); Cy_SD_Host_ErrorReset(base); - + /* Issue CMD13. */ cmd.commandIndex = CY_SD_HOST_SD_CMD13; cmd.cmdType = CY_SD_HOST_CMD_NORMAL; ret = Cy_SD_Host_SendCommand(base, &cmd); - + if (CY_SD_HOST_SUCCESS == ret) { /* Wait for the Command Complete event. */ ret = Cy_SD_Host_PollCmdComplete(base); } - + Cy_SysLib_DelayUs(CY_SD_HOST_NCC_MIN_US); /* Get R1 */ (void)Cy_SD_Host_GetResponse(base, (uint32_t *)&response, false); /* Check if the card is in the transition state. */ - if ((CY_SD_HOST_CARD_TRAN << CY_SD_HOST_CMD13_CURRENT_STATE) != + if ((CY_SD_HOST_CARD_TRAN << CY_SD_HOST_CMD13_CURRENT_STATE) != (response & CY_SD_HOST_CMD13_CURRENT_STATE_MSK)) { /* Issue CMD12 */ cmd.commandIndex = CY_SD_HOST_SD_CMD12; cmd.cmdType = CY_SD_HOST_CMD_ABORT; ret = Cy_SD_Host_SendCommand(base, &cmd); - + if (CY_SD_HOST_SUCCESS == ret) { /* Wait for the Command Complete event. */ ret = Cy_SD_Host_PollCmdComplete(base); } - + Cy_SysLib_DelayUs(CY_SD_HOST_NCC_MIN_US); - + Cy_SD_Host_ErrorReset(base); - + /* Issue CMD13. */ cmd.commandIndex = CY_SD_HOST_SD_CMD13; cmd.cmdType = CY_SD_HOST_CMD_NORMAL; ret = Cy_SD_Host_SendCommand(base, &cmd); - + if (CY_SD_HOST_SUCCESS == ret) { /* Wait for the Command Complete event. */ ret = Cy_SD_Host_PollCmdComplete(base); } - + Cy_SysLib_DelayUs(CY_SD_HOST_NCC_MIN_US); - + /* Get R1. */ (void)Cy_SD_Host_GetResponse(base, (uint32_t *)&response, false); /* Check if the card is in the transition state. */ - if ((CY_SD_HOST_CARD_TRAN << CY_SD_HOST_CMD13_CURRENT_STATE) != + if ((CY_SD_HOST_CARD_TRAN << CY_SD_HOST_CMD13_CURRENT_STATE) != (response & CY_SD_HOST_CMD13_CURRENT_STATE_MSK)) { ret = CY_SD_HOST_ERROR; @@ -3055,7 +3055,7 @@ uint32_t Cy_SD_Host_GetCardStatus(SDHC_Type *base, cmd.cmdType = CY_SD_HOST_CMD_NORMAL; ret = Cy_SD_Host_SendCommand(base, &cmd); - + if (CY_SD_HOST_SUCCESS == ret) { /* Wait for the Command Complete event. */ @@ -3136,7 +3136,7 @@ cy_en_sd_host_status_t Cy_SD_Host_GetSdStatus(SDHC_Type *base, (void)Cy_SD_Host_InitDataTransfer(base, &dataConfig); ret = Cy_SD_Host_SendCommand(base, &cmd); - + if (CY_SD_HOST_SUCCESS == ret) { /* Wait for the Command Complete event. */ @@ -3243,7 +3243,7 @@ cy_en_sd_host_status_t Cy_SD_Host_GetCid(SDHC_Type *base, cmd.cmdType = CY_SD_HOST_CMD_NORMAL; ret = Cy_SD_Host_SendCommand(base, &cmd); - + if (CY_SD_HOST_SUCCESS == ret) { /* Wait for the Command Complete event. */ @@ -3316,7 +3316,7 @@ cy_en_sd_host_status_t Cy_SD_Host_GetCsd(SDHC_Type *base, cmd.cmdType = CY_SD_HOST_CMD_NORMAL; ret = Cy_SD_Host_SendCommand(base, &cmd); - + if (CY_SD_HOST_SUCCESS == ret) { /* Wait for the Command Complete event. */ @@ -3434,7 +3434,7 @@ cy_en_sd_host_status_t Cy_SD_Host_GetExtCsd(SDHC_Type *base, uint32_t *extCsd, (void)Cy_SD_Host_InitDataTransfer(base, &dataConfig); ret = Cy_SD_Host_SendCommand(base, &cmd); - + if (CY_SD_HOST_SUCCESS == ret) { /* Wait for the Command Complete event. */ @@ -3471,7 +3471,7 @@ cy_en_sd_host_status_t Cy_SD_Host_GetExtCsd(SDHC_Type *base, uint32_t *extCsd, * * Reads the Relative Card Address (RCA) register from the card. * -* \note This function can be used only if the card is in the Identification or +* \note This function can be used only if the card is in the Identification or * Stand-by state. * * \param *base @@ -3494,14 +3494,14 @@ uint32_t Cy_SD_Host_GetRca(SDHC_Type *base) cmd.enableCrcCheck = true; cmd.enableIdxCheck = true; cmd.cmdType = CY_SD_HOST_CMD_NORMAL; - + (void)Cy_SD_Host_SendCommand(base, &cmd); - + /* Wait for the Command Complete event. */ (void)Cy_SD_Host_PollCmdComplete(base); Cy_SysLib_DelayUs(CY_SD_HOST_NCC_MIN_US); - + (void)Cy_SD_Host_GetResponse(base, (uint32_t *)&response, false); return (response >> CY_SD_HOST_RCA_SHIFT); @@ -3555,7 +3555,7 @@ cy_en_sd_host_status_t Cy_SD_Host_GetScr(SDHC_Type *base, cmd.enableCrcCheck = true; cmd.enableIdxCheck = true; cmd.cmdType = CY_SD_HOST_CMD_NORMAL; - + dataConfig.blockSize = CY_SD_HOST_SCR_BLOCKS; dataConfig.numberOfBlock = 1UL; dataConfig.enableDma = false; @@ -3569,7 +3569,7 @@ cy_en_sd_host_status_t Cy_SD_Host_GetScr(SDHC_Type *base, (void)Cy_SD_Host_InitDataTransfer(base, &dataConfig); ret = Cy_SD_Host_SendCommand(base, &cmd); - + if (CY_SD_HOST_SUCCESS == ret) { /* Wait for the Command Complete event. */ @@ -3662,7 +3662,7 @@ __STATIC_INLINE bool Cy_SD_Host_VoltageCheck(SDHC_Type *base) { /* Reset Card (CMD0). */ ret = Cy_SD_Host_OpsGoIdle(base); /* The Idle state. */ - + /* Software reset for the CMD line. */ Cy_SD_Host_SoftwareReset(base, CY_SD_HOST_RESET_CMD_LINE); @@ -3693,13 +3693,13 @@ __STATIC_INLINE bool Cy_SD_Host_VoltageCheck(SDHC_Type *base) /* The unusable card or the SDIO card. */ ret = CY_SD_HOST_ERROR_UNUSABLE_CARD; } - + if ((CY_SD_HOST_ERROR_TIMEOUT == ret) || (f8Flag)) { /* The pattern is valid or voltage mismatch (No response). */ - break; + break; } - + retry--; } @@ -3746,7 +3746,7 @@ __STATIC_INLINE cy_en_sd_host_status_t Cy_SD_Host_IoOcr(SDHC_Type *base, bool lowVoltageSignaling, uint32_t *s18aFlag, uint32_t *sdioFlag, - bool *mpFlag, + bool *mpFlag, uint32_t *ocrReg) { cy_en_sd_host_status_t ret; @@ -3756,8 +3756,8 @@ __STATIC_INLINE cy_en_sd_host_status_t Cy_SD_Host_IoOcr(SDHC_Type *base, ret = Cy_SD_Host_OpsSdioSendOpCond(base, ocrReg, 0UL); /* Get the number of IO functions. */ - *sdioFlag = *ocrReg & CY_SD_HOST_CMD5_IO_NUM_MASK; - + *sdioFlag = *ocrReg & CY_SD_HOST_CMD5_IO_NUM_MASK; + if (0UL < *sdioFlag) { if (true == lowVoltageSignaling) @@ -3795,7 +3795,7 @@ __STATIC_INLINE cy_en_sd_host_status_t Cy_SD_Host_IoOcr(SDHC_Type *base, /* IO > 0. */ break; } - + Cy_SysLib_DelayUs(CY_SD_HOST_SDIO_CMD5_TIMEOUT_MS); /* 1 sec timeout. */ retry--; } @@ -3810,12 +3810,12 @@ __STATIC_INLINE cy_en_sd_host_status_t Cy_SD_Host_IoOcr(SDHC_Type *base, { /* Software reset for the DAT line. */ Cy_SD_Host_SoftwareReset(base, CY_SD_HOST_RESET_DATALINE); - + /* IO = 0. We have the SD memory card. Reset errors. */ Cy_SD_Host_ErrorReset(base); - + } - + Cy_SysLib_DelayUs(CY_SD_HOST_NCC_MIN_US); return ret; @@ -3941,7 +3941,7 @@ __STATIC_INLINE cy_en_sd_host_status_t Cy_SD_Host_SdOcr(SDHC_Type *base, { /* The card is not present or busy */ } - + Cy_SysLib_DelayUs(CY_SD_HOST_NCC_MIN_US); return ret; @@ -4046,15 +4046,15 @@ cy_en_sd_host_status_t Cy_SD_Host_SetSdClkDiv(SDHC_Type *base, uint16_t clkDiv) /* Check for the NULL pointer */ if (NULL != base) { - SDHC_CORE_CLK_CTRL_R(base) = (uint16_t)(((uint32_t)SDHC_CORE_CLK_CTRL_R(base) & + SDHC_CORE_CLK_CTRL_R(base) = (uint16_t)(((uint32_t)SDHC_CORE_CLK_CTRL_R(base) & ~(SDHC_CORE_CLK_CTRL_R_FREQ_SEL_Msk | /* Clear the first LSB 8 bits */ SDHC_CORE_CLK_CTRL_R_UPPER_FREQ_SEL_Msk)) | /* Clear the upper 2 bits */ _VAL2FLD(SDHC_CORE_CLK_CTRL_R_FREQ_SEL, ((uint32_t)clkDiv & CY_SD_HOST_FREQ_SEL_MSK)) | /* Set the first LSB 8 bits */ - _VAL2FLD(SDHC_CORE_CLK_CTRL_R_UPPER_FREQ_SEL, ((uint32_t)clkDiv >> CY_SD_HOST_UPPER_FREQ_SEL_POS))); /* Set the upper 2 bits */ + _VAL2FLD(SDHC_CORE_CLK_CTRL_R_UPPER_FREQ_SEL, ((uint32_t)clkDiv >> CY_SD_HOST_UPPER_FREQ_SEL_POS))); /* Set the upper 2 bits */ /* Wait for at least 3 card clock periods */ Cy_SysLib_DelayUs(CY_SD_HOST_3_PERIODS_US); - + ret = CY_SD_HOST_SUCCESS; } @@ -4105,7 +4105,7 @@ cy_en_sd_host_status_t Cy_SD_Host_SetHostBusWidth(SDHC_Type *base, /* Check for the NULL pointer */ if (NULL != base) - { + { SDHC_CORE_HOST_CTRL1_R(base) = (uint8_t)(((uint32_t)SDHC_CORE_HOST_CTRL1_R(base) & ~(SDHC_CORE_HOST_CTRL1_R_EXT_DAT_XFER_Msk | SDHC_CORE_HOST_CTRL1_R_DAT_XFER_WIDTH_Msk)) | @@ -4179,7 +4179,7 @@ cy_en_sd_host_status_t Cy_SD_Host_SetHostSpeedMode(SDHC_Type *base, } else { - ret = CY_SD_HOST_ERROR_INVALID_PARAMETER; + ret = CY_SD_HOST_ERROR_INVALID_PARAMETER; } return ret; @@ -4226,8 +4226,8 @@ cy_en_sd_host_status_t Cy_SD_Host_SetBusSpeedMode(SDHC_Type *base, CY_ASSERT_L3(CY_SD_HOST_IS_SPEED_MODE_VALID(speedMode)); /* 1. Does the card support memory? */ - if ((CY_SD_HOST_SD == context->cardType) || - (CY_SD_HOST_EMMC == context->cardType) || + if ((CY_SD_HOST_SD == context->cardType) || + (CY_SD_HOST_EMMC == context->cardType) || (CY_SD_HOST_COMBO == context->cardType)) { /* 2. Change Bus Speed Mode: Issue CMD6 with mode 1 */ @@ -4269,14 +4269,14 @@ cy_en_sd_host_status_t Cy_SD_Host_SetBusSpeedMode(SDHC_Type *base, (highSpeedValue << CY_SD_HOST_EMMC_CMD6_VALUE_OFFSET) | (0x0UL << CY_SD_HOST_EMMC_CMD6_CMD_SET_OFFSET); } - + /* Send CMD6 */ ret = Cy_SD_Host_OpsSwitchFunc(base, cmdArgument); } } /* 5. Is SDIO Supported? */ - if ((CY_SD_HOST_SDIO == context->cardType) || + if ((CY_SD_HOST_SDIO == context->cardType) || (CY_SD_HOST_COMBO == context->cardType)) { /* 6. Change Bus Speed Mode: Set EHS or BSS[2:0] in CCCR */ @@ -4367,8 +4367,8 @@ cy_en_sd_host_status_t Cy_SD_Host_SetBusSpeedMode(SDHC_Type *base, * * \note The host needs to change the regulator supplying voltage to * the VDDIO of the SD block in order to operate at 1.8V. -* \note This function changes RCA to 0 in the context. RCA in the context -* should be updated (context.RCA = Cy_SD_Host_GetRca();) +* \note This function changes RCA to 0 in the context. RCA in the context +* should be updated (context.RCA = Cy_SD_Host_GetRca();) * when the card is in the Identification state. * \note This function is applicable for SD cards only. * @@ -4388,10 +4388,10 @@ cy_en_sd_host_status_t Cy_SD_Host_SetBusSpeedMode(SDHC_Type *base, * * \return \ref cy_en_sd_host_status_t * -* \note The SD card power supply should be disabled and initialized again when +* \note The SD card power supply should be disabled and initialized again when * this function returns CY_SD_HOST_ERROR_UNUSABLE_CARD. * -* \note The dedicated io_volt_sel pin is used to change the regulator supplying +* \note The dedicated io_volt_sel pin is used to change the regulator supplying * voltage to the VDDIO of the SD block in order to operate at 1.8V. To configure * the custom IO pin in order to control (using the GPIO driver) the regulator * supplying voltage, the user must implement weak Cy_SD_Host_ChangeIoVoltage(). @@ -4407,9 +4407,9 @@ cy_en_sd_host_status_t Cy_SD_Host_SelBusVoltage(SDHC_Type *base, uint32_t s18aFlag = 0UL; /* The S18A flag. */ bool f8Flag = false; /* The CMD8 flag. */ bool mpFlag = false; /* The MEM flag. */ - + context->RCA = 0UL; - + /* Send CMD0 and CMD8 commands. */ f8Flag = Cy_SD_Host_VoltageCheck(base); @@ -4439,7 +4439,7 @@ cy_en_sd_host_status_t Cy_SD_Host_SelBusVoltage(SDHC_Type *base, * Function Name: Cy_SD_Host_EnableCardVoltage ****************************************************************************//** * -* Sets the card_if_pwr_en pin high. +* Sets the card_if_pwr_en pin high. * This pin can be used to enable a voltage regulator used to power the card. * * \param *base @@ -4447,7 +4447,7 @@ cy_en_sd_host_status_t Cy_SD_Host_SelBusVoltage(SDHC_Type *base, * *******************************************************************************/ __WEAK void Cy_SD_Host_EnableCardVoltage(SDHC_Type *base) -{ +{ SDHC_CORE_PWR_CTRL_R(base) = _CLR_SET_FLD8U(SDHC_CORE_PWR_CTRL_R(base), SDHC_CORE_PWR_CTRL_R_SD_BUS_PWR_VDD1, 1UL); } @@ -4456,7 +4456,7 @@ __WEAK void Cy_SD_Host_EnableCardVoltage(SDHC_Type *base) * Function Name: Cy_SD_Host_DisableCardVoltage ****************************************************************************//** * -* Sets the card_if_pwr_en pin low. +* Sets the card_if_pwr_en pin low. * This pin can be used to disable a voltage regulator used to power the card. * * \param *base @@ -4465,7 +4465,7 @@ __WEAK void Cy_SD_Host_EnableCardVoltage(SDHC_Type *base) *******************************************************************************/ __WEAK void Cy_SD_Host_DisableCardVoltage(SDHC_Type *base) { - + SDHC_CORE_PWR_CTRL_R(base) = _CLR_SET_FLD8U(SDHC_CORE_PWR_CTRL_R(base), SDHC_CORE_PWR_CTRL_R_SD_BUS_PWR_VDD1, 0UL); } @@ -4548,12 +4548,12 @@ cy_en_sd_host_status_t Cy_SD_Host_InitDataTransfer(SDHC_Type *base, CY_ASSERT_L3(CY_SD_HOST_IS_AUTO_CMD_VALID(dataConfig->autoCommand)); CY_ASSERT_L2(CY_SD_HOST_IS_TIMEOUT_VALID(dataConfig->dataTimeout)); CY_ASSERT_L2(CY_SD_HOST_IS_BLK_SIZE_VALID(dataConfig->blockSize)); - + dmaMode = _FLD2VAL(SDHC_CORE_HOST_CTRL1_R_DMA_SEL, SDHC_CORE_HOST_CTRL1_R(base)); SDHC_CORE_BLOCKSIZE_R(base) = 0U; SDHC_CORE_XFER_MODE_R(base) = 0U; - + if (((uint32_t)CY_SD_HOST_DMA_ADMA2_ADMA3 == dmaMode) && (dataConfig->enableDma)) { /* ADMA3 Integrated Descriptor Address. */ @@ -4604,12 +4604,12 @@ cy_en_sd_host_status_t Cy_SD_Host_InitDataTransfer(SDHC_Type *base, /* Set the block count. */ SDHC_CORE_BLOCKCOUNT_R(base) = (uint16_t)dataConfig->numberOfBlock; - - + + /* Set a multi- or single-block transfer.*/ transferMode = _BOOL2FLD(SDHC_CORE_XFER_MODE_R_MULTI_BLK_SEL, (1U < dataConfig->numberOfBlock)); - /* Set the data transfer direction. */ + /* Set the data transfer direction. */ transferMode |= _BOOL2FLD(SDHC_CORE_XFER_MODE_R_DATA_XFER_DIR, dataConfig->read); /* Set the block count enable. */ @@ -4655,7 +4655,7 @@ cy_en_sd_host_status_t Cy_SD_Host_InitDataTransfer(SDHC_Type *base, ret = CY_SD_HOST_ERROR_INVALID_PARAMETER; break; } - + SDHC_CORE_XFER_MODE_R(base) = (uint16_t)transferMode; } } @@ -4668,11 +4668,11 @@ cy_en_sd_host_status_t Cy_SD_Host_InitDataTransfer(SDHC_Type *base, * Function Name: Cy_SD_Host_ChangeIoVoltage ****************************************************************************//** * -* Changes the logic level on the sd_io_volt_sel line. It assumes that -* this line is used to control a regulator connected to the VDDIO of the PSoC. +* Changes the logic level on the sd_io_volt_sel line. It assumes that +* this line is used to control a regulator connected to the VDDIO of the PSoC. * This regulator allows for switching between the 3.3V and 1.8V signaling. * -* \note The dedicated io_volt_sel pin is used to change the regulator supplying +* \note The dedicated io_volt_sel pin is used to change the regulator supplying * voltage to the VDDIO of the SD block in order to operate at 1.8V. To configure * the custom IO pin in order to control (using the GPIO driver) the regulator * supplying voltage, the user must implement weak Cy_SD_Host_ChangeIoVoltage(). @@ -4689,8 +4689,8 @@ cy_en_sd_host_status_t Cy_SD_Host_InitDataTransfer(SDHC_Type *base, __WEAK void Cy_SD_Host_ChangeIoVoltage(SDHC_Type *base, cy_en_sd_host_io_voltage_t ioVoltage) { /* Set the 1.8V signaling enable. */ - SDHC_CORE_HOST_CTRL2_R(base) = _CLR_SET_FLD16U(SDHC_CORE_HOST_CTRL2_R(base), - SDHC_CORE_HOST_CTRL2_R_SIGNALING_EN, + SDHC_CORE_HOST_CTRL2_R(base) = _CLR_SET_FLD16U(SDHC_CORE_HOST_CTRL2_R(base), + SDHC_CORE_HOST_CTRL2_R_SIGNALING_EN, (CY_SD_HOST_IO_VOLT_1_8V == ioVoltage) ? 1UL : 0UL); } @@ -4701,7 +4701,7 @@ __WEAK void Cy_SD_Host_ChangeIoVoltage(SDHC_Type *base, cy_en_sd_host_io_voltage * * Checks to see if a card is currently connected. * -* \note You can use any GPIO custom pin for Card Detect. Add the SD Host driver +* \note You can use any GPIO custom pin for Card Detect. Add the SD Host driver * Cy_SD_Host_IsCardConnected() function with the __WEAK type to your code. * This function could read the value from any GPIO pin and return true when * the card is connected. @@ -4756,24 +4756,24 @@ void Cy_SD_Host_SoftwareReset(SDHC_Type *base, while(false != _FLD2BOOL(SDHC_CORE_SW_RST_R_SW_RST_CMD, SDHC_CORE_SW_RST_R(base))) { - /* Wait until the reset completes. */ + /* Wait until the reset completes. */ } break; case CY_SD_HOST_RESET_ALL: - + SDHC_CORE_CLK_CTRL_R(base) = 0U; - + /* Wait for at least 3 card clock periods */ Cy_SysLib_DelayUs(CY_SD_HOST_3_PERIODS_US); - + SDHC_CORE_SW_RST_R(base) = (uint8_t)_VAL2FLD(SDHC_CORE_SW_RST_R_SW_RST_ALL, 1UL); while(false != _FLD2BOOL(SDHC_CORE_SW_RST_R_SW_RST_ALL, SDHC_CORE_SW_RST_R(base))) { - /* Wait until the reset completes. */ + /* Wait until the reset completes. */ } - + /* Enable the Internal clock. */ SDHC_CORE_CLK_CTRL_R(base) = (uint16_t)_CLR_SET_FLD16U(SDHC_CORE_CLK_CTRL_R(base), SDHC_CORE_CLK_CTRL_R_INTERNAL_CLK_EN, @@ -4819,9 +4819,9 @@ uint32_t Cy_SD_Host_GetPresentState(SDHC_Type const *base) ****************************************************************************//** * * This function handles the transition of the SD Host into and out of -* Deep Sleep mode. It disables SD CLK before going to Deep Sleep mode and +* Deep Sleep mode. It disables SD CLK before going to Deep Sleep mode and * enables SD CLK after wake up from Deep Sleep mode. -* If the DAT line is active, or a read (write) transfer is being executed on +* If the DAT line is active, or a read (write) transfer is being executed on * the bus, the device cannot enter Deep Sleep mode. * * This function must be called during execution of \ref Cy_SysPm_CpuEnterDeepSleep. @@ -4853,7 +4853,7 @@ uint32_t Cy_SD_Host_GetPresentState(SDHC_Type const *base) * \ref cy_en_syspm_status_t * *******************************************************************************/ -cy_en_syspm_status_t Cy_SD_Host_DeepSleepCallback(cy_stc_syspm_callback_params_t *callbackParams, +cy_en_syspm_status_t Cy_SD_Host_DeepSleepCallback(cy_stc_syspm_callback_params_t *callbackParams, cy_en_syspm_callback_mode_t mode) { cy_en_syspm_status_t ret = CY_SYSPM_FAIL; @@ -4862,14 +4862,14 @@ cy_en_syspm_status_t Cy_SD_Host_DeepSleepCallback(cy_stc_syspm_callback_params_t switch(mode) { case CY_SYSPM_CHECK_READY: - { + { /* Check DAT Line Active */ uint32_t pState = Cy_SD_Host_GetPresentState(locBase); if ((CY_SD_HOST_DAT_LINE_ACTIVE != (pState & CY_SD_HOST_DAT_LINE_ACTIVE)) && (CY_SD_HOST_CMD_CMD_INHIBIT_DAT != (pState & CY_SD_HOST_CMD_CMD_INHIBIT_DAT))) { ret = CY_SYSPM_SUCCESS; - } + } } break; @@ -4892,7 +4892,7 @@ cy_en_syspm_status_t Cy_SD_Host_DeepSleepCallback(cy_stc_syspm_callback_params_t { /* Enable SD CLK after wake up from Deep Sleep mode */ Cy_SD_Host_EnableSdClk(locBase); - + /* Wait for the stable CLK */ Cy_SysLib_DelayUs(CY_SD_HOST_CLK_RAMP_UP_TIME_US_WAKEUP); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_smartio.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_smartio.c index 9b9f120e12..c01c595c4b 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_smartio.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_smartio.c @@ -1,13 +1,13 @@ /***************************************************************************//** * \file cy_smartio.c -* \version 1.0 +* \version 1.0.1 * * \brief * Provides an API implementation of the Smart I/O driver * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -51,13 +51,13 @@ extern "C" { cy_en_smartio_status_t Cy_SmartIO_Init(SMARTIO_PRT_Type* base, const cy_stc_smartio_config_t* config) { cy_en_smartio_status_t status = CY_SMARTIO_SUCCESS; - + if(NULL != config) { SMARTIO_PRT_CTL(base) = _VAL2FLD(SMARTIO_PRT_CTL_BYPASS, config->bypassMask) | _VAL2FLD(SMARTIO_PRT_CTL_CLOCK_SRC, config->clkSrc) | _VAL2FLD(SMARTIO_PRT_CTL_HLD_OVR, config->hldOvr) - | _VAL2FLD(SMARTIO_PRT_CTL_PIPELINE_EN, CY_SMARTIO_ENABLE) + | _VAL2FLD(SMARTIO_PRT_CTL_PIPELINE_EN, CY_SMARTIO_ENABLE) | _VAL2FLD(SMARTIO_PRT_CTL_ENABLED, CY_SMARTIO_DISABLE); SMARTIO_PRT_SYNC_CTL(base) = _VAL2FLD(SMARTIO_PRT_SYNC_CTL_IO_SYNC_EN, config->ioSyncEn) | _VAL2FLD(SMARTIO_PRT_SYNC_CTL_CHIP_SYNC_EN, config->chipSyncEn); @@ -145,7 +145,7 @@ cy_en_smartio_status_t Cy_SmartIO_Init(SMARTIO_PRT_Type* base, const cy_stc_smar { status = CY_SMARTIO_BAD_PARAM; } - + return(status); } @@ -167,7 +167,7 @@ void Cy_SmartIO_Deinit(SMARTIO_PRT_Type* base) { SMARTIO_PRT_CTL(base) = _VAL2FLD(SMARTIO_PRT_CTL_BYPASS, CY_SMARTIO_CHANNEL_ALL) | _VAL2FLD(SMARTIO_PRT_CTL_CLOCK_SRC, CY_SMARTIO_CLK_GATED) - | _VAL2FLD(SMARTIO_PRT_CTL_PIPELINE_EN, CY_SMARTIO_ENABLE) + | _VAL2FLD(SMARTIO_PRT_CTL_PIPELINE_EN, CY_SMARTIO_ENABLE) | _VAL2FLD(SMARTIO_PRT_CTL_ENABLED, CY_SMARTIO_DISABLE); SMARTIO_PRT_SYNC_CTL(base) = CY_SMARTIO_DEINIT; for(uint8_t idx = 0u; idx < CY_SMARTIO_LUTMAX; idx++) @@ -197,10 +197,10 @@ void Cy_SmartIO_Deinit(SMARTIO_PRT_Type* base) void Cy_SmartIO_Enable(SMARTIO_PRT_Type* base) { uint32_t tempReg; - + tempReg = (SMARTIO_PRT_CTL(base) & (~(SMARTIO_PRT_CTL_PIPELINE_EN_Msk | SMARTIO_PRT_CTL_ENABLED_Msk))); - SMARTIO_PRT_CTL(base) = tempReg - | _VAL2FLD(SMARTIO_PRT_CTL_PIPELINE_EN, CY_SMARTIO_DISABLE) + SMARTIO_PRT_CTL(base) = tempReg + | _VAL2FLD(SMARTIO_PRT_CTL_PIPELINE_EN, CY_SMARTIO_DISABLE) | _VAL2FLD(SMARTIO_PRT_CTL_ENABLED, CY_SMARTIO_ENABLE); } @@ -221,10 +221,10 @@ void Cy_SmartIO_Enable(SMARTIO_PRT_Type* base) void Cy_SmartIO_Disable(SMARTIO_PRT_Type* base) { uint32_t tempReg; - + tempReg = (SMARTIO_PRT_CTL(base) & (~(SMARTIO_PRT_CTL_PIPELINE_EN_Msk | SMARTIO_PRT_CTL_ENABLED_Msk))); - SMARTIO_PRT_CTL(base) = tempReg - | _VAL2FLD(SMARTIO_PRT_CTL_PIPELINE_EN, CY_SMARTIO_ENABLE) + SMARTIO_PRT_CTL(base) = tempReg + | _VAL2FLD(SMARTIO_PRT_CTL_PIPELINE_EN, CY_SMARTIO_ENABLE) | _VAL2FLD(SMARTIO_PRT_CTL_ENABLED, CY_SMARTIO_DISABLE); } @@ -266,14 +266,14 @@ cy_en_smartio_status_t Cy_SmartIO_SetChBypass(SMARTIO_PRT_Type* base, uint8_t by { cy_en_smartio_status_t status = CY_SMARTIO_LOCKED; uint32_t tempReg; - + if(CY_SMARTIO_DISABLE == _FLD2VAL(SMARTIO_PRT_CTL_ENABLED, SMARTIO_PRT_CTL(base))) { tempReg = (SMARTIO_PRT_CTL(base) & (~SMARTIO_PRT_CTL_BYPASS_Msk)); SMARTIO_PRT_CTL(base) = tempReg | _VAL2FLD(SMARTIO_PRT_CTL_BYPASS, bypassMask); status = CY_SMARTIO_SUCCESS; } - + return(status); } @@ -303,14 +303,14 @@ cy_en_smartio_status_t Cy_SmartIO_SetClock(SMARTIO_PRT_Type* base, cy_en_smartio { cy_en_smartio_status_t status = CY_SMARTIO_LOCKED; uint32_t tempReg; - + if(CY_SMARTIO_DISABLE == _FLD2VAL(SMARTIO_PRT_CTL_ENABLED, SMARTIO_PRT_CTL(base))) { tempReg = (SMARTIO_PRT_CTL(base) & (~SMARTIO_PRT_CTL_CLOCK_SRC_Msk)); SMARTIO_PRT_CTL(base) = tempReg | _VAL2FLD(SMARTIO_PRT_CTL_CLOCK_SRC, clkSrc); status = CY_SMARTIO_SUCCESS; } - + return(status); } @@ -352,14 +352,14 @@ cy_en_smartio_status_t Cy_SmartIO_SetIoSync(SMARTIO_PRT_Type* base, uint8_t ioSy { cy_en_smartio_status_t status = CY_SMARTIO_LOCKED; uint32_t tempReg; - + if(CY_SMARTIO_DISABLE == _FLD2VAL(SMARTIO_PRT_CTL_ENABLED, SMARTIO_PRT_CTL(base))) { tempReg = (SMARTIO_PRT_SYNC_CTL(base) & (~SMARTIO_PRT_SYNC_CTL_IO_SYNC_EN_Msk)); SMARTIO_PRT_SYNC_CTL(base) = tempReg | _VAL2FLD(SMARTIO_PRT_SYNC_CTL_IO_SYNC_EN, ioSyncEn); status = CY_SMARTIO_SUCCESS; } - + return(status); } @@ -401,14 +401,14 @@ cy_en_smartio_status_t Cy_SmartIO_SetChipSync(SMARTIO_PRT_Type* base, uint8_t ch { cy_en_smartio_status_t status = CY_SMARTIO_LOCKED; uint32_t tempReg; - + if(CY_SMARTIO_DISABLE == _FLD2VAL(SMARTIO_PRT_CTL_ENABLED, SMARTIO_PRT_CTL(base))) { tempReg = (SMARTIO_PRT_SYNC_CTL(base) & (~SMARTIO_PRT_SYNC_CTL_CHIP_SYNC_EN_Msk)); SMARTIO_PRT_SYNC_CTL(base) = tempReg | _VAL2FLD(SMARTIO_PRT_SYNC_CTL_CHIP_SYNC_EN, chipSyncEn); status = CY_SMARTIO_SUCCESS; } - + return(status); } @@ -422,7 +422,7 @@ cy_en_smartio_status_t Cy_SmartIO_SetChipSync(SMARTIO_PRT_Type* base, uint8_t ch * In Deep-Sleep power mode, the HSIOM holds the GPIO output and output enable * signals for all signals that operate in chip active domain. Enabling the hold * override allows the Smart I/O to deliver Deep-Sleep output functionality -* on these GPIO terminals. If the Smart I/O should not drive any of the GPIO +* on these GPIO terminals. If the Smart I/O should not drive any of the GPIO * outputs, the hold override should be disabled. * * \param base @@ -445,14 +445,14 @@ cy_en_smartio_status_t Cy_SmartIO_HoldOverride(SMARTIO_PRT_Type* base, bool hldO { cy_en_smartio_status_t status = CY_SMARTIO_LOCKED; uint32_t tempReg; - + if(CY_SMARTIO_DISABLE == _FLD2VAL(SMARTIO_PRT_CTL_ENABLED, SMARTIO_PRT_CTL(base))) { tempReg = (SMARTIO_PRT_CTL(base) & (~SMARTIO_PRT_CTL_HLD_OVR_Msk)); SMARTIO_PRT_CTL(base) = tempReg | _VAL2FLD(SMARTIO_PRT_CTL_HLD_OVR, hldOvr); status = CY_SMARTIO_SUCCESS; } - + return(status); } @@ -482,7 +482,7 @@ cy_en_smartio_status_t Cy_SmartIO_HoldOverride(SMARTIO_PRT_Type* base, bool hldO cy_en_smartio_luttr_t Cy_SmartIO_GetLutTr(SMARTIO_PRT_Type* base, cy_en_smartio_lutnum_t lutNum, cy_en_smartio_trnum_t trNum) { cy_en_smartio_luttr_t trSrc; - + switch(trNum) { case(CY_SMARTIO_TR0): @@ -506,7 +506,7 @@ cy_en_smartio_luttr_t Cy_SmartIO_GetLutTr(SMARTIO_PRT_Type* base, cy_en_smartio_ break; } } - + return(trSrc); } @@ -542,7 +542,7 @@ cy_en_smartio_status_t Cy_SmartIO_SetLutTr(SMARTIO_PRT_Type* base, cy_en_smartio { cy_en_smartio_status_t status = CY_SMARTIO_LOCKED; uint32_t tempReg; - + if(CY_SMARTIO_DISABLE == _FLD2VAL(SMARTIO_PRT_CTL_ENABLED, SMARTIO_PRT_CTL(base))) { status = CY_SMARTIO_SUCCESS; @@ -573,7 +573,7 @@ cy_en_smartio_status_t Cy_SmartIO_SetLutTr(SMARTIO_PRT_Type* base, cy_en_smartio } } } - + return(status); } @@ -606,20 +606,20 @@ cy_en_smartio_status_t Cy_SmartIO_SetLutTrAll(SMARTIO_PRT_Type* base, cy_en_smar { cy_en_smartio_status_t status = CY_SMARTIO_LOCKED; uint32_t tempReg; - + if(CY_SMARTIO_DISABLE == _FLD2VAL(SMARTIO_PRT_CTL_ENABLED, SMARTIO_PRT_CTL(base))) { - tempReg = (SMARTIO_PRT_LUT_SEL(base, lutNum) - & (~(SMARTIO_PRT_LUT_SEL_LUT_TR0_SEL_Msk - | SMARTIO_PRT_LUT_SEL_LUT_TR1_SEL_Msk + tempReg = (SMARTIO_PRT_LUT_SEL(base, lutNum) + & (~(SMARTIO_PRT_LUT_SEL_LUT_TR0_SEL_Msk + | SMARTIO_PRT_LUT_SEL_LUT_TR1_SEL_Msk | SMARTIO_PRT_LUT_SEL_LUT_TR2_SEL_Msk))); - SMARTIO_PRT_LUT_SEL(base, lutNum) = tempReg + SMARTIO_PRT_LUT_SEL(base, lutNum) = tempReg | _VAL2FLD(SMARTIO_PRT_LUT_SEL_LUT_TR0_SEL, trSrc) | _VAL2FLD(SMARTIO_PRT_LUT_SEL_LUT_TR1_SEL, trSrc) | _VAL2FLD(SMARTIO_PRT_LUT_SEL_LUT_TR2_SEL, trSrc); status = CY_SMARTIO_SUCCESS; } - + return(status); } @@ -652,14 +652,14 @@ cy_en_smartio_status_t Cy_SmartIO_SetLutOpcode(SMARTIO_PRT_Type* base, cy_en_sma { cy_en_smartio_status_t status = CY_SMARTIO_LOCKED; uint32_t tempReg; - + if(CY_SMARTIO_DISABLE == _FLD2VAL(SMARTIO_PRT_CTL_ENABLED, SMARTIO_PRT_CTL(base))) { tempReg = (SMARTIO_PRT_LUT_CTL(base, lutNum) & (~SMARTIO_PRT_LUT_CTL_LUT_OPC_Msk)); SMARTIO_PRT_LUT_CTL(base, lutNum) = tempReg | _VAL2FLD(SMARTIO_PRT_LUT_CTL_LUT_OPC, opcode); status = CY_SMARTIO_SUCCESS; } - + return(status); } @@ -704,14 +704,14 @@ cy_en_smartio_status_t Cy_SmartIO_SetLutMap(SMARTIO_PRT_Type* base, cy_en_smarti { cy_en_smartio_status_t status = CY_SMARTIO_LOCKED; uint32_t tempReg; - + if(CY_SMARTIO_DISABLE == _FLD2VAL(SMARTIO_PRT_CTL_ENABLED, SMARTIO_PRT_CTL(base))) { tempReg = (SMARTIO_PRT_LUT_CTL(base, lutNum) & (~SMARTIO_PRT_LUT_CTL_LUT_Msk)); SMARTIO_PRT_LUT_CTL(base, lutNum) = tempReg | _VAL2FLD(SMARTIO_PRT_LUT_CTL_LUT, lutMap); status = CY_SMARTIO_SUCCESS; } - + return(status); } @@ -738,7 +738,7 @@ cy_en_smartio_status_t Cy_SmartIO_SetLutMap(SMARTIO_PRT_Type* base, cy_en_smarti cy_en_smartio_dutr_t Cy_SmartIO_GetDuTr(SMARTIO_PRT_Type* base, cy_en_smartio_trnum_t trNum) { cy_en_smartio_dutr_t trSrc; - + switch(trNum) { case(CY_SMARTIO_TR0): @@ -762,7 +762,7 @@ cy_en_smartio_dutr_t Cy_SmartIO_GetDuTr(SMARTIO_PRT_Type* base, cy_en_smartio_tr break; } } - + return(trSrc); } @@ -795,7 +795,7 @@ cy_en_smartio_status_t Cy_SmartIO_SetDuTr(SMARTIO_PRT_Type* base, cy_en_smartio_ { cy_en_smartio_status_t status = CY_SMARTIO_LOCKED; uint32_t tempReg; - + if(CY_SMARTIO_DISABLE == _FLD2VAL(SMARTIO_PRT_CTL_ENABLED, SMARTIO_PRT_CTL(base))) { status = CY_SMARTIO_SUCCESS; @@ -826,7 +826,7 @@ cy_en_smartio_status_t Cy_SmartIO_SetDuTr(SMARTIO_PRT_Type* base, cy_en_smartio_ } } } - + return status; } @@ -856,20 +856,20 @@ cy_en_smartio_status_t Cy_SmartIO_SetDuTrAll(SMARTIO_PRT_Type* base, cy_en_smart { cy_en_smartio_status_t status = CY_SMARTIO_LOCKED; uint32_t tempReg; - + if(CY_SMARTIO_DISABLE == _FLD2VAL(SMARTIO_PRT_CTL_ENABLED, SMARTIO_PRT_CTL(base))) { tempReg = (SMARTIO_PRT_DU_SEL(base) - & (~(SMARTIO_PRT_DU_SEL_DU_TR0_SEL_Msk - | SMARTIO_PRT_DU_SEL_DU_TR1_SEL_Msk + & (~(SMARTIO_PRT_DU_SEL_DU_TR0_SEL_Msk + | SMARTIO_PRT_DU_SEL_DU_TR1_SEL_Msk | SMARTIO_PRT_DU_SEL_DU_TR2_SEL_Msk))); - SMARTIO_PRT_DU_SEL(base) = tempReg + SMARTIO_PRT_DU_SEL(base) = tempReg | _VAL2FLD(SMARTIO_PRT_DU_SEL_DU_TR0_SEL, trSrc) | _VAL2FLD(SMARTIO_PRT_DU_SEL_DU_TR1_SEL, trSrc) | _VAL2FLD(SMARTIO_PRT_DU_SEL_DU_TR2_SEL, trSrc); status = CY_SMARTIO_SUCCESS; } - + return status; } @@ -902,7 +902,7 @@ cy_en_smartio_status_t Cy_SmartIO_SetDuData(SMARTIO_PRT_Type* base, cy_en_smarti { cy_en_smartio_status_t status = CY_SMARTIO_LOCKED; uint32_t tempReg; - + if(CY_SMARTIO_DISABLE == _FLD2VAL(SMARTIO_PRT_CTL_ENABLED, SMARTIO_PRT_CTL(base))) { if(dataNum == CY_SMARTIO_DATA0) @@ -913,11 +913,11 @@ cy_en_smartio_status_t Cy_SmartIO_SetDuData(SMARTIO_PRT_Type* base, cy_en_smarti else { tempReg = (SMARTIO_PRT_DU_SEL(base) & (~SMARTIO_PRT_DU_SEL_DU_DATA1_SEL_Msk)); - SMARTIO_PRT_DU_SEL(base) = tempReg | _VAL2FLD(SMARTIO_PRT_DU_SEL_DU_DATA1_SEL, dataSrc); + SMARTIO_PRT_DU_SEL(base) = tempReg | _VAL2FLD(SMARTIO_PRT_DU_SEL_DU_DATA1_SEL, dataSrc); } status = CY_SMARTIO_SUCCESS; } - + return status; } @@ -949,14 +949,14 @@ cy_en_smartio_status_t Cy_SmartIO_SetDuData(SMARTIO_PRT_Type* base, cy_en_smarti cy_en_smartio_status_t Cy_SmartIO_SetDuOperation(SMARTIO_PRT_Type* base, cy_en_smartio_duopc_t opcode, cy_en_smartio_dusize_t size) { cy_en_smartio_status_t status = CY_SMARTIO_LOCKED; - + if(CY_SMARTIO_DISABLE == _FLD2VAL(SMARTIO_PRT_CTL_ENABLED, SMARTIO_PRT_CTL(base))) { SMARTIO_PRT_DU_CTL(base) = _VAL2FLD(SMARTIO_PRT_DU_CTL_DU_SIZE, size) | _VAL2FLD(SMARTIO_PRT_DU_CTL_DU_OPC, opcode); status = CY_SMARTIO_SUCCESS; } - + return status; } @@ -985,13 +985,13 @@ cy_en_smartio_status_t Cy_SmartIO_SetDuOperation(SMARTIO_PRT_Type* base, cy_en_s cy_en_smartio_status_t Cy_SmartIO_SetDataReg(SMARTIO_PRT_Type* base, uint8_t dataReg) { cy_en_smartio_status_t status = CY_SMARTIO_LOCKED; - + if(CY_SMARTIO_DISABLE == _FLD2VAL(SMARTIO_PRT_CTL_ENABLED, SMARTIO_PRT_CTL(base))) { SMARTIO_PRT_DATA(base) = dataReg; status = CY_SMARTIO_SUCCESS; } - + return status; } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_smif.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_smif.c index 875573ab63..95f390e927 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_smif.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_smif.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_smif.c -* \version 1.50 +* \version 1.50.1 * * \brief * This file provides the source code for the SMIF driver APIs. diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_smif_memslot.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_smif_memslot.c index 5a28464ea3..6639aca6f8 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_smif_memslot.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_smif_memslot.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_smif_memslot.c -* \version 1.50 +* \version 1.50.1 * * \brief * This file provides the source code for the memory-level APIs of the SMIF driver. @@ -3680,10 +3680,12 @@ cy_en_smif_status_t Cy_SMIF_MemWrite(SMIF_Type *base, cy_stc_smif_mem_config_t c * The memory device configuration. * * \param address -* The address of the block to be erased. +* The address of the block to be erased. The address should be aligned with +* the start address of the sector. * * \param length -* The size of data to erase. +* The size of data to erase. The length should be equal to the sum of all sectors +* length to be erased. * * \param context * This is the pointer to the context structure \ref cy_stc_smif_context_t @@ -3693,8 +3695,8 @@ cy_en_smif_status_t Cy_SMIF_MemWrite(SMIF_Type *base, cy_stc_smif_mem_config_t c * * \return The status of the operation. See \ref cy_en_smif_status_t. * -* \note The address should be aligned with the start address of the sector. \n -* The length should be equal to the sum of all erased sectors. +* \note Memories like hybrid have sectors of different sizes. \n +* Check the adress and length parameters before calling this function. * * \funcusage * \snippet smif/snippet/main.c snippet_Cy_SMIF_MemEraseSector diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_sysanalog.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_sysanalog.c index 431decf9b0..8a1c135fdb 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_sysanalog.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_sysanalog.c @@ -1,12 +1,12 @@ /***************************************************************************//** * \file cy_sysanalog.c -* \version 1.10 +* \version 1.10.1 * * Provides the public functions for the API for the SAR driver. * ******************************************************************************** * \copyright -* Copyright 2017-2019 Cypress Semiconductor Corporation +* Copyright 2017-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -113,4 +113,3 @@ cy_en_sysanalog_status_t Cy_SysAnalog_Init(const cy_stc_sysanalog_config_t *conf #endif /* CY_IP_MXS40PASS */ /* [] END OF FILE */ - diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_sysclk.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_sysclk.c index c96c2e567f..743b2bbf91 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_sysclk.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_sysclk.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_sysclk.c -* \version 2.0 +* \version 2.10 * * Provides an API implementation of the sysclk driver. * @@ -60,8 +60,14 @@ void Cy_SysClk_ExtClkSetFrequency(uint32_t freq) { if (freq <= CY_SYSCLK_EXTCLK_MAX_FREQ) { +#if ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) + CY_PRA_FUNCTION_CALL_VOID_PARAM(CY_PRA_MSG_TYPE_FUNC_POLICY, CY_PRA_CLK_FUNC_EXT_CLK_SET_FREQUENCY, freq); extFreq = freq; +#else + extFreq = freq; +#endif } + } @@ -96,13 +102,13 @@ uint32_t Cy_SysClk_ExtClkGetFrequency(void) SRSS_CLK_TRIM_ECO_CTL_RTRIM_Msk | \ SRSS_CLK_TRIM_ECO_CTL_GTRIM_Msk) - /** \cond ********************************************************************* * Function Name: cy_sqrt * Calculates square root. * The input is 32-bit wide. * The result is 16-bit wide. *******************************************************************************/ +#if !((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) static uint32_t cy_sqrt(uint32_t x); static uint32_t cy_sqrt(uint32_t x) { @@ -124,7 +130,7 @@ static uint32_t cy_sqrt(uint32_t x) return (res); } - +#endif /* !((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) */ static uint32_t ecoFreq = 0UL; /* Internal storage for ECO frequency user setting */ @@ -148,12 +154,12 @@ static uint32_t ecoFreq = 0UL; /* Internal storage for ECO frequency user settin * Function Name: Cy_SysClk_EcoConfigure ****************************************************************************//** * -* Configures the external crystal oscillator (ECO) trim bits based on crystal +* Configures the external crystal oscillator (ECO) trim bits based on crystal * characteristics. This function should be called only when the ECO is disabled. * * \param freq Operating frequency of the crystal in Hz. * Valid range: 16000000...35000000 (16..35 MHz). -* +* * \param cSum The summary capacitance of * C0 (the crystal itself shunt capacitance) and * Cload (the parallel load capacitance), in pF. @@ -170,10 +176,18 @@ static uint32_t ecoFreq = 0UL; /* Internal storage for ECO frequency user settin * CY_SYSCLK_SUCCESS - ECO configuration completed successfully \n * CY_SYSCLK_BAD_PARAM - One or more invalid parameters \n * CY_SYSCLK_INVALID_STATE - ECO already enabled +* For the PSoC 64 devices there are possible situations when function returns +* the PRA error status code. This is because for PSoC 64 devices the function +* uses the PRA driver to change the protected registers. Refer to +* \ref cy_en_pra_status_t for more details. * * \note * The following calculations are implemented in the 32-bit integer math: * +* \note +* On PSoC 64 devices the configuration on the PRA driver will be reflected +* after \ref Cy_SysClk_EcoEnable call. +* * \verbatim * freqKhz = freq / 1000 * maxAmpl = sqrt(drivelevel / 2 / esr) / 3.14 / freqKhz / cSum @@ -199,6 +213,20 @@ cy_en_sysclk_status_t Cy_SysClk_EcoConfigure(uint32_t freq, uint32_t cSum, uint3 { cy_en_sysclk_status_t retVal = CY_SYSCLK_BAD_PARAM; +#if ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) + cy_stc_pra_clk_eco_configure_t ecoConfig; + ecoConfig.praClkEcofreq = freq; + ecoConfig.praCsum = cSum; + ecoConfig.praEsr = esr; + ecoConfig.praDriveLevel = driveLevel; + retVal = (cy_en_sysclk_status_t)CY_PRA_FUNCTION_CALL_RETURN_PARAM(CY_PRA_MSG_TYPE_FUNC_POLICY, CY_PRA_CLK_FUNC_ECO_CONFIGURE, &ecoConfig); + if(CY_SYSCLK_SUCCESS == retVal) + { + ecoFreq = freq; /* Store the ECO frequency */ + } +#else + + if (0UL != (SRSS_CLK_ECO_CONFIG_ECO_EN_Msk & SRSS_CLK_ECO_CONFIG)) { retVal = CY_SYSCLK_INVALID_STATE; @@ -230,7 +258,7 @@ cy_en_sysclk_status_t Cy_SysClk_EcoConfigure(uint32_t freq, uint32_t cSum, uint3 _VAL2FLD(SRSS_CLK_TRIM_ECO_CTL_FTRIM, 3UL) | _VAL2FLD(SRSS_CLK_TRIM_ECO_CTL_RTRIM, 0UL) | _VAL2FLD(SRSS_CLK_TRIM_ECO_CTL_GTRIM, gtrim); - + CY_REG32_CLR_SET(SRSS_CLK_TRIM_ECO_CTL, CY_SYSCLK_TRIM_ECO, reg); SRSS_CLK_ECO_CONFIG |= SRSS_CLK_ECO_CONFIG_AGC_EN_Msk; @@ -244,7 +272,7 @@ cy_en_sysclk_status_t Cy_SysClk_EcoConfigure(uint32_t freq, uint32_t cSum, uint3 { /* Return CY_SYSCLK_BAD_PARAM */ } - +#endif /* ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) */ return (retVal); } @@ -262,9 +290,13 @@ cy_en_sysclk_status_t Cy_SysClk_EcoConfigure(uint32_t freq, uint32_t cSum, uint3 * CY_SYSCLK_SUCCESS - ECO locked \n * CY_SYSCLK_TIMEOUT - ECO timed out and did not lock \n * CY_SYSCLK_INVALID_STATE - ECO already enabled +* For the PSoC 64 devices there are possible situations when function returns +* the PRA error status code. This is because for PSoC 64 devices the function +* uses the PRA driver to change the protected registers. Refer to +* \ref cy_en_pra_status_t for more details. * -* \note -* Call \ref SystemCoreClockUpdate after this function calling +* \note +* Call \ref SystemCoreClockUpdate after this function calling * if it affects the CLK_HF0 frequency. * * \funcusage @@ -273,6 +305,9 @@ cy_en_sysclk_status_t Cy_SysClk_EcoConfigure(uint32_t freq, uint32_t cSum, uint3 *******************************************************************************/ cy_en_sysclk_status_t Cy_SysClk_EcoEnable(uint32_t timeoutus) { +#if ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) + return (cy_en_sysclk_status_t)CY_PRA_FUNCTION_CALL_RETURN_PARAM(CY_PRA_MSG_TYPE_FUNC_POLICY, CY_PRA_CLK_FUNC_ECO_ENABLE, timeoutus); +#else cy_en_sysclk_status_t retVal = CY_SYSCLK_INVALID_STATE; bool zeroTimeout = (0UL == timeoutus); @@ -292,6 +327,7 @@ cy_en_sysclk_status_t Cy_SysClk_EcoEnable(uint32_t timeoutus) } return (retVal); +#endif /* ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) */ } @@ -336,6 +372,11 @@ uint32_t Cy_SysClk_EcoGetFrequency(void) * \param source \ref cy_en_clkpath_in_sources_t * * \return \ref cy_en_sysclk_status_t +* CY_SYSCLK_INVALID_STATE - ECO already enabled +* For the PSoC 64 devices there are possible situations when function returns +* the PRA error status code. This is because for PSoC 64 devices the function +* uses the PRA driver to change the protected registers. Refer to +* \ref cy_en_pra_status_t for more details. * * \note * If calling this function changes an FLL or PLL input frequency, disable the FLL @@ -343,7 +384,7 @@ uint32_t Cy_SysClk_EcoGetFrequency(void) * or PLL configure function, for example \ref Cy_SysClk_FllConfigure(). * * \note -* Call \ref SystemCoreClockUpdate after this function calling +* Call \ref SystemCoreClockUpdate after this function calling * if it affects the CLK_HF0 frequency. * * \note @@ -365,6 +406,13 @@ cy_en_sysclk_status_t Cy_SysClk_ClkPathSetSource(uint32_t clkPath, cy_en_clkpath ((source <= CY_SYSCLK_CLKPATH_IN_DSIMUX) || ((CY_SYSCLK_CLKPATH_IN_DSI <= source) && (source <= CY_SYSCLK_CLKPATH_IN_PILO)))) { +#if ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) + cy_stc_pra_clkpathsetsource_t clkpath_set_source; + clkpath_set_source.clk_path = clkPath; + clkpath_set_source.source = source; + retVal = (cy_en_sysclk_status_t)CY_PRA_FUNCTION_CALL_RETURN_PARAM(CY_PRA_MSG_TYPE_FUNC_POLICY, CY_PRA_CLK_FUNC_PATH_SET_SOURCE, &clkpath_set_source); +#else + if (source >= CY_SYSCLK_CLKPATH_IN_DSI) { SRSS_CLK_DSI_SELECT[clkPath] = _VAL2FLD(SRSS_CLK_DSI_SELECT_DSI_MUX, (uint32_t)source); @@ -375,8 +423,10 @@ cy_en_sysclk_status_t Cy_SysClk_ClkPathSetSource(uint32_t clkPath, cy_en_clkpath SRSS_CLK_PATH_SELECT[clkPath] = _VAL2FLD(SRSS_CLK_PATH_SELECT_PATH_MUX, (uint32_t)source); } retVal = CY_SYSCLK_SUCCESS; +#endif /* ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) */ } return (retVal); + } /******************************************************************************* @@ -427,9 +477,9 @@ cy_en_clkpath_in_sources_t Cy_SysClk_ClkPathGetSource(uint32_t clkPath) uint32_t Cy_SysClk_ClkPathMuxGetFrequency(uint32_t clkPath) { CY_ASSERT_L1(clkPath < CY_SRSS_NUM_CLKPATH); - + uint32_t freq = 0UL; /* The path mux output frequency in Hz, 0 = an unknown frequency */ - + /* Get the frequency of the source, i.e., the path mux input */ switch(Cy_SysClk_ClkPathGetSource(clkPath)) { @@ -460,7 +510,7 @@ uint32_t Cy_SysClk_ClkPathMuxGetFrequency(uint32_t clkPath) case CY_SYSCLK_CLKPATH_IN_PILO: freq = (0UL != (SRSS_CLK_PILO_CONFIG & SRSS_CLK_PILO_CONFIG_PILO_EN_Msk)) ? CY_SYSCLK_PILO_FREQ : 0UL; break; - + case CY_SYSCLK_CLKPATH_IN_ALTLF: freq = Cy_SysClk_AltLfGetFrequency(); break; @@ -493,13 +543,13 @@ uint32_t Cy_SysClk_ClkPathMuxGetFrequency(uint32_t clkPath) uint32_t Cy_SysClk_ClkPathGetFrequency(uint32_t clkPath) { CY_ASSERT_L1(clkPath < CY_SRSS_NUM_CLKPATH); - + uint32_t freq = Cy_SysClk_ClkPathMuxGetFrequency(clkPath); - uint32_t fDiv = 0UL; /* FLL/PLL multiplier/feedback divider */ - uint32_t rDiv = 0UL; /* FLL/PLL reference divider */ - uint32_t oDiv = 0UL; /* FLL/PLL output divider */ + uint32_t fDiv = 1UL; /* FLL/PLL multiplier/feedback divider */ + uint32_t rDiv = 1UL; /* FLL/PLL reference divider */ + uint32_t oDiv = 1UL; /* FLL/PLL output divider */ bool enabled = false; /* FLL or PLL enable status; n/a for direct */ - + if (clkPath == (uint32_t)CY_SYSCLK_CLKHF_IN_CLKPATH0) /* FLL? (always path 0) */ { cy_stc_fll_manual_config_t fllCfg = {0UL,0U,CY_SYSCLK_FLL_CCO_RANGE0,false,0U,0U,0U,0U,CY_SYSCLK_FLLPLL_OUTPUT_AUTO,0U}; @@ -523,12 +573,13 @@ uint32_t Cy_SysClk_ClkPathGetFrequency(uint32_t clkPath) /* Do nothing with the path mux frequency */ } - if (enabled) /* If FLL or PLL is enabled and not bypassed */ + if (enabled && /* If FLL or PLL is enabled and not bypassed */ + (0UL != rDiv) && (0UL != oDiv)) /* to avoid division by zero */ { freq = (uint32_t)CY_SYSLIB_DIV_ROUND(((uint64_t)freq * (uint64_t)fDiv), ((uint64_t)rDiv * (uint64_t)oDiv)); } - + return (freq); } /** \} group_sysclk_path_src_funcs */ @@ -590,11 +641,11 @@ uint32_t Cy_SysClk_ClkPathGetFrequency(uint32_t clkPath) * Do not call this function when the FLL is enabled. If it is called, then this function * returns with an CY_SYSCLK_INVALID_STATE return value and no register updates. * -* \note -* Call \ref SystemCoreClockUpdate after this function calling +* \note +* Call \ref SystemCoreClockUpdate after this function calling * if it affects the CLK_HF0 frequency. * -* \note +* \note * Call \ref Cy_SysLib_SetWaitStates before calling this function if * the FLL is the source of CLK_HF0 and the FLL frequency is increasing. * @@ -602,6 +653,11 @@ uint32_t Cy_SysClk_ClkPathGetFrequency(uint32_t clkPath) * Call \ref Cy_SysLib_SetWaitStates after calling this function if * the FLL is the source of CLK_HF0 and the FLL frequency is decreasing. * +* \note +* On PSoC 64 devices the configuration on the PRA driver will be reflected +* after \ref Cy_SysClk_FllEnable call. Any call to \ref Cy_SysClk_FllGetConfiguration +* before calling \ref Cy_SysClk_FllEnable returns old configuration values. +* * \funcusage * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_FllConfigure * @@ -637,7 +693,7 @@ cy_en_sysclk_status_t Cy_SysClk_FllConfigure(uint32_t inputFreq, uint32_t output ((ccoFreq >= 113009380UL) ? CY_SYSCLK_FLL_CCO_RANGE3 : ((ccoFreq >= 84948700UL) ? CY_SYSCLK_FLL_CCO_RANGE2 : ((ccoFreq >= 63855600UL) ? CY_SYSCLK_FLL_CCO_RANGE1 : CY_SYSCLK_FLL_CCO_RANGE0)))); - + /* 4. Compute the FLL reference divider value. refDiv is a constant if the WCO is the FLL source, otherwise the formula is refDiv = ROUNDUP((inputFreq / outputFreq) * 250) */ @@ -652,7 +708,7 @@ cy_en_sysclk_status_t Cy_SysClk_FllConfigure(uint32_t inputFreq, uint32_t output We assume the source clock accuracy = 1%. This is the accuracy of the IMO. Therefore the formula is lock tolerance = 1.5 * fllMult * 0.012626 = 0.018939 * fllMult */ config.lockTolerance = (uint16_t)CY_SYSLIB_DIV_ROUNDUP(config.fllMult * 18939UL, 1000000UL); - + { /* constants indexed by ccoRange */ const uint32_t trimSteps[] = {110340UL, 110200UL, 110000UL, 110000UL, 117062UL}; /* Scaled by 10^8 */ @@ -678,7 +734,7 @@ cy_en_sysclk_status_t Cy_SysClk_FllConfigure(uint32_t inputFreq, uint32_t output config.igain--; locigain >>= 1U; } - + /* then find the largest PGAIN value that is less than or equal to ki_p - igain */ for(config.pgain = CY_SYSCLK_FLL_GAIN_IDX; (locpgain > (ki_p - locigain)) && (config.pgain != 0UL); config.pgain--) { @@ -690,7 +746,7 @@ cy_en_sysclk_status_t Cy_SysClk_FllConfigure(uint32_t inputFreq, uint32_t output config.pgain--; } } - + /* 8. Compute the CCO_FREQ bits in CLK_FLL_CONFIG4 register */ { uint64_t cmp = CY_SYSLIB_DIV_ROUND(((TRIM_STEPS_SCALE / MARGIN_SCALE) * (uint64_t)ccoFreq), (uint64_t)margin[config.ccoRange]); @@ -707,7 +763,7 @@ cy_en_sysclk_status_t Cy_SysClk_FllConfigure(uint32_t inputFreq, uint32_t output } } } - + /* 9. Compute the settling count, using a 1 usec settling time. Use a constant if the WCO is the FLL source */ { uint64_t fref = CY_SYSLIB_DIV_ROUND(6000ULL * (uint64_t)inputFreq, (uint64_t)config.refDiv); @@ -741,6 +797,11 @@ cy_en_sysclk_status_t Cy_SysClk_FllConfigure(uint32_t inputFreq, uint32_t output * \return Error / status code: \n * CY_SYSCLK_SUCCESS - FLL successfully configured \n * CY_SYSCLK_INVALID_STATE - FLL not configured because it is enabled +* CY_SYSCLK_INVALID_STATE - ECO already enabled +* For the PSoC 64 devices there are possible situations when function returns +* the PRA error status code. This is because for PSoC 64 devices the function +* uses the PRA driver to change the protected registers. Refer to +* \ref cy_en_pra_status_t for more details. * * \note * Call this function after changing the FLL input frequency, for example if @@ -750,11 +811,11 @@ cy_en_sysclk_status_t Cy_SysClk_FllConfigure(uint32_t inputFreq, uint32_t output * Do not call this function when the FLL is enabled. If it is called, then this function * returns immediately with an CY_SYSCLK_INVALID_STATE return value and no register updates. * -* \note -* Call \ref SystemCoreClockUpdate after this function calling +* \note +* Call \ref SystemCoreClockUpdate after this function calling * if it affects the CLK_HF0 frequency. * -* \note +* \note * Call \ref Cy_SysLib_SetWaitStates before calling this function if * the FLL is the source of CLK_HF0 and the FLL frequency is increasing. * @@ -762,17 +823,25 @@ cy_en_sysclk_status_t Cy_SysClk_FllConfigure(uint32_t inputFreq, uint32_t output * Call \ref Cy_SysLib_SetWaitStates after calling this function if * the FLL is the source of CLK_HF0 and the FLL frequency is decreasing. * +* \note +* On PSoC 64 devices the configuration on the PRA driver will be reflected +* after \ref Cy_SysClk_FllEnable call. Any call to \ref Cy_SysClk_FllGetConfiguration +* before calling \ref Cy_SysClk_FllEnable returns old configuration values. +* * \funcusage * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_FllManualConfigure * *******************************************************************************/ cy_en_sysclk_status_t Cy_SysClk_FllManualConfigure(const cy_stc_fll_manual_config_t *config) { +#if ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) + return (cy_en_sysclk_status_t)CY_PRA_FUNCTION_CALL_RETURN_PARAM(CY_PRA_MSG_TYPE_FUNC_POLICY, CY_PRA_CLK_FUNC_FLL_MANCONFIG, config); +#else cy_en_sysclk_status_t retVal = CY_SYSCLK_INVALID_STATE; /* Check for errors */ CY_ASSERT_L1(config != NULL); - + if (!Cy_SysClk_FllIsEnabled()) /* If disabled */ { /* update CLK_FLL_CONFIG register with 2 parameters; FLL_ENABLE is already 0 */ @@ -808,11 +877,12 @@ cy_en_sysclk_status_t Cy_SysClk_FllManualConfigure(const cy_stc_fll_manual_confi CY_REG32_CLR_SET(SRSS_CLK_FLL_CONFIG4, SRSS_CLK_FLL_CONFIG4_CCO_RANGE, (uint32_t)(config->ccoRange)); CY_REG32_CLR_SET(SRSS_CLK_FLL_CONFIG4, SRSS_CLK_FLL_CONFIG4_CCO_FREQ, (uint32_t)(config->cco_Freq)); - + retVal = CY_SYSCLK_SUCCESS; } return (retVal); +#endif /* ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) */ } /******************************************************************************* @@ -823,6 +893,11 @@ cy_en_sysclk_status_t Cy_SysClk_FllManualConfigure(const cy_stc_fll_manual_confi * * \param config \ref cy_stc_fll_manual_config_t * +* \note +* On PSoC 64 devices the configuration on the PRA driver will be reflected +* after \ref Cy_SysClk_FllEnable call. Any call to \ref Cy_SysClk_FllGetConfiguration +* before calling \ref Cy_SysClk_FllEnable returns old configuration values. +* * \funcusage * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_FllGetConfiguration * @@ -863,16 +938,21 @@ void Cy_SysClk_FllGetConfiguration(cy_stc_fll_manual_config_t *config) * \return Error / status code: \n * CY_SYSCLK_SUCCESS - FLL successfully enabled \n * CY_SYSCLK_TIMEOUT - Timeout waiting for FLL lock +* CY_SYSCLK_INVALID_STATE - ECO already enabled +* For the PSoC 64 devices there are possible situations when function returns +* the PRA error status code. This is because for PSoC 64 devices the function +* uses the PRA driver to change the protected registers. Refer to +* \ref cy_en_pra_status_t for more details. * * \note * While waiting for the FLL to lock, the FLL bypass mode is set to \ref CY_SYSCLK_FLLPLL_OUTPUT_INPUT. * After the FLL is locked, the FLL bypass mdoe is then set to \ref CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT. * -* \note -* Call \ref SystemCoreClockUpdate after calling this function +* \note +* Call \ref SystemCoreClockUpdate after calling this function * if it affects the CLK_HF0 frequency. * -* \note +* \note * Call \ref Cy_SysLib_SetWaitStates before calling this function if * the FLL is the source of CLK_HF0 and the CLK_HF0 frequency is increasing. * @@ -882,6 +962,9 @@ void Cy_SysClk_FllGetConfiguration(cy_stc_fll_manual_config_t *config) *******************************************************************************/ cy_en_sysclk_status_t Cy_SysClk_FllEnable(uint32_t timeoutus) { +#if ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) + return (cy_en_sysclk_status_t)CY_PRA_FUNCTION_CALL_RETURN_PARAM(CY_PRA_MSG_TYPE_FUNC_POLICY, CY_PRA_CLK_FUNC_FLL_ENABLE, timeoutus); +#else bool zeroTimeout = (0UL == timeoutus); /* first set the CCO enable bit */ @@ -913,7 +996,7 @@ cy_en_sysclk_status_t Cy_SysClk_FllEnable(uint32_t timeoutus) } if (zeroTimeout || (0UL != timeoutus)) - { + { /* Set the FLL bypass mode to FLL_OUT (ignoring lock indicator) */ CY_REG32_CLR_SET(SRSS_CLK_FLL_CONFIG3, SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT); } @@ -924,6 +1007,7 @@ cy_en_sysclk_status_t Cy_SysClk_FllEnable(uint32_t timeoutus) } return ((zeroTimeout || (0UL != timeoutus)) ? CY_SYSCLK_SUCCESS : CY_SYSCLK_TIMEOUT); +#endif /* ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) */ } /** \} group_sysclk_fll_funcs */ @@ -999,11 +1083,11 @@ cy_en_sysclk_status_t Cy_SysClk_FllEnable(uint32_t timeoutus) * Do not call this function when the PLL is enabled. If it is called, then this function * returns immediately with an error return value and no register updates. * -* \note -* Call \ref SystemCoreClockUpdate after this function calling +* \note +* Call \ref SystemCoreClockUpdate after this function calling * if it affects the CLK_HF0 frequency. * -* \note +* \note * Call \ref Cy_SysLib_SetWaitStates before calling this function if * the PLL is the source of CLK_HF0 and the PLL frequency is increasing. * @@ -1011,6 +1095,11 @@ cy_en_sysclk_status_t Cy_SysClk_FllEnable(uint32_t timeoutus) * Call \ref Cy_SysLib_SetWaitStates after calling this function if * the PLL is the source of CLK_HF0 and the PLL frequency is decreasing. * +* \note +* On PSoC 64 devices the configuration on the PRA driver will be reflected +* after \ref Cy_SysClk_PllEnable call. Any call to \ref Cy_SysClk_PllGetConfiguration +* before calling \ref Cy_SysClk_PllEnable returns old configuration values. +* * \funcusage * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PllConfigure * @@ -1025,10 +1114,10 @@ cy_en_sysclk_status_t Cy_SysClk_PllConfigure(uint32_t clkPath, const cy_stc_pll_ retVal = CY_SYSCLK_BAD_PARAM; } else - { + { cy_stc_pll_manual_config_t manualConfig = {0U, 0U, 0U, false, CY_SYSCLK_FLLPLL_OUTPUT_AUTO}; - /* If output mode is not bypass (input routed directly to output), then + /* If output mode is not bypass (input routed directly to output), then calculate new parameters. */ if (config->outputMode != CY_SYSCLK_FLLPLL_OUTPUT_INPUT) { @@ -1051,7 +1140,7 @@ cy_en_sysclk_status_t Cy_SysClk_PllConfigure(uint32_t clkPath, const cy_stc_pll_ /* OUTPUT_DIV selection */ for (out = CY_SYSCLK_PLL_MIN_OUTPUT_DIV; (out <= CY_SYSCLK_PLL_MAX_OUTPUT_DIV) && (foutBest != (config->outputFreq)); out++) { - /* Calculate what output frequency will actually be produced. + /* Calculate what output frequency will actually be produced. If it's closer to the target than what we have so far, then save it. */ uint32_t fout = ((p * config->inputFreq) / q) / out; if ((uint32_t)abs((int32_t)fout - (int32_t)(config->outputFreq)) < @@ -1101,6 +1190,11 @@ cy_en_sysclk_status_t Cy_SysClk_PllConfigure(uint32_t clkPath, const cy_stc_pll_ * CY_SYSCLK_SUCCESS - PLL successfully configured \n * CY_SYSCLK_INVALID_STATE - PLL not configured because it is enabled \n * CY_SYSCLK_BAD_PARAM - invalid clock path number +* CY_SYSCLK_INVALID_STATE - ECO already enabled +* For the PSoC 64 devices there are possible situations when function returns +* the PRA error status code. This is because for PSoC 64 devices the function +* uses the PRA driver to change the protected registers. Refer to +* \ref cy_en_pra_status_t for more details. * * \note * Call this function after changing the PLL input frequency; for example if @@ -1110,8 +1204,8 @@ cy_en_sysclk_status_t Cy_SysClk_PllConfigure(uint32_t clkPath, const cy_stc_pll_ * Do not call this function when the PLL is enabled. If it is called, then this function * returns immediately with an error return value and no register updates. * -* \note -* Call \ref SystemCoreClockUpdate after this function calling +* \note +* Call \ref SystemCoreClockUpdate after this function calling * if it affects the CLK_HF0 frequency. * * \note @@ -1122,6 +1216,11 @@ cy_en_sysclk_status_t Cy_SysClk_PllConfigure(uint32_t clkPath, const cy_stc_pll_ * Call \ref Cy_SysLib_SetWaitStates after calling this function if * the PLL is the source of CLK_HF0 and the PLL frequency is decreasing. * +* \note +* On PSoC 64 devices the configuration on the PRA driver will be reflected +* after \ref Cy_SysClk_PllEnable call. Any call to \ref Cy_SysClk_PllGetConfiguration +* before calling \ref Cy_SysClk_PllEnable returns old configuration values. +* * \funcusage * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PllManualConfigure * @@ -1148,6 +1247,12 @@ cy_en_sysclk_status_t Cy_SysClk_PllManualConfigure(uint32_t clkPath, const cy_st } else /* no errors */ { +#if ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) + cy_stc_pra_clk_pll_manconfigure_t pll_config; + pll_config.clkPath = clkPath; + pll_config.praConfig = (cy_stc_pll_manual_config_t *)config; + retVal = (cy_en_sysclk_status_t)CY_PRA_FUNCTION_CALL_RETURN_PARAM(CY_PRA_MSG_TYPE_FUNC_POLICY, CY_PRA_CLK_FUNC_PLL_MANCONFIG, &pll_config); +#else clkPath--; /* to correctly access PLL config registers structure */ /* If output mode is bypass (input routed directly to output), then done. The output frequency equals the input frequency regardless of the frequency parameters. */ @@ -1161,6 +1266,7 @@ cy_en_sysclk_status_t Cy_SysClk_PllManualConfigure(uint32_t clkPath, const cy_st } CY_REG32_CLR_SET(SRSS_CLK_PLL_CONFIG[clkPath], SRSS_CLK_PLL_CONFIG_BYPASS_SEL, (uint32_t)config->outputMode); +#endif /* ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) */ } return (retVal); @@ -1179,6 +1285,16 @@ cy_en_sysclk_status_t Cy_SysClk_PllManualConfigure(uint32_t clkPath, const cy_st * \return Error / status code: \n * CY_SYSCLK_SUCCESS - PLL data successfully reported \n * CY_SYSCLK_BAD_PARAM - invalid clock path number +* CY_SYSCLK_INVALID_STATE - ECO already enabled +* For the PSoC 64 devices there are possible situations when function returns +* the PRA error status code. This is because for PSoC 64 devices the function +* uses the PRA driver to change the protected registers. Refer to +* \ref cy_en_pra_status_t for more details. +* +* \note +* On PSoC 64 devices the configuration on the PRA driver will be reflected +* after \ref Cy_SysClk_PllEnable call. Any call to \ref Cy_SysClk_PllGetConfiguration +* before calling \ref Cy_SysClk_PllEnable returns old configuration values. * * \funcusage * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PllGetConfiguration @@ -1217,12 +1333,17 @@ cy_en_sysclk_status_t Cy_SysClk_PllGetConfiguration(uint32_t clkPath, cy_stc_pll * CY_SYSCLK_SUCCESS - PLL successfully enabled \n * CY_SYSCLK_TIMEOUT - Timeout waiting for PLL lock \n * CY_SYSCLK_BAD_PARAM - invalid clock path number +* CY_SYSCLK_INVALID_STATE - ECO already enabled +* For the PSoC 64 devices there are possible situations when function returns +* the PRA error status code. This is because for PSoC 64 devices the function +* uses the PRA driver to change the protected registers. Refer to +* \ref cy_en_pra_status_t for more details. * -* \note -* Call \ref SystemCoreClockUpdate after this function calling +* \note +* Call \ref SystemCoreClockUpdate after this function calling * if it affects the CLK_HF0 frequency. * -* \note +* \note * Call \ref Cy_SysLib_SetWaitStates before calling this function if * the PLL is the source of CLK_HF0 and the CLK_HF0 frequency is increasing. * @@ -1241,6 +1362,11 @@ cy_en_sysclk_status_t Cy_SysClk_PllEnable(uint32_t clkPath, uint32_t timeoutus) clkPath--; /* to correctly access PLL config and status registers structures */ if (clkPath < CY_SRSS_NUM_PLL) { +#if ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) + (void)timeoutus; + (void)nonZeroTimeout; + retVal = (cy_en_sysclk_status_t)CY_PRA_FUNCTION_CALL_RETURN_PARAM(CY_PRA_MSG_TYPE_FUNC_POLICY, CY_PRA_CLK_FUNC_PLL_ENABLE, (clkPath + 1U)); +#else /* first set the PLL enable bit */ SRSS_CLK_PLL_CONFIG[clkPath] |= SRSS_CLK_PLL_CONFIG_ENABLE_Msk; @@ -1252,6 +1378,7 @@ cy_en_sysclk_status_t Cy_SysClk_PllEnable(uint32_t clkPath, uint32_t timeoutus) Cy_SysLib_DelayUs(1U); } retVal = ((nonZeroTimeout && (timeoutus == 0ul)) ? CY_SYSCLK_TIMEOUT : CY_SYSCLK_SUCCESS); +#endif /* ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) */ } return (retVal); } @@ -1304,7 +1431,7 @@ static bool preventCounting = false; * * - One counter (counter1), which is clocked by clock1, is loaded with an initial * value and counts down to zero. -* - The second counter (counter2), which is clocked by clock2, counts up until +* - The second counter (counter2), which is clocked by clock2, counts up until * the first counter reaches zero. * * Either clock1 or clock2 can be a reference clock; the other clock becomes the @@ -1324,6 +1451,11 @@ static bool preventCounting = false; * CY_SYSCLK_INVALID_STATE if already doing a measurement \n * CY_SYSCLK_BAD_PARAM if invalid clock input parameter \n * else CY_SYSCLK_SUCCESS +* CY_SYSCLK_INVALID_STATE - ECO already enabled +* For the PSoC 64 devices there are possible situations when function returns +* the PRA error status code. This is because for PSoC 64 devices the function +* uses the PRA driver to change the protected registers. Refer to +* \ref cy_en_pra_status_t for more details. * * \note The counters are both 24-bit, so the maximum value of count1 is 0xFFFFFF. * If clock2 frequency is greater than clock1, make sure that count1 is low enough @@ -1341,14 +1473,22 @@ static bool preventCounting = false; *******************************************************************************/ cy_en_sysclk_status_t Cy_SysClk_StartClkMeasurementCounters(cy_en_meas_clks_t clock1, uint32_t count1, cy_en_meas_clks_t clock2) { +#if ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) + (void) clock1; + (void) count1; + (void) clock2; + (void) clk1Count1; + (void) preventCounting; + return CY_SYSCLK_BAD_PARAM; +#else cy_en_sysclk_status_t retVal = CY_SYSCLK_BAD_PARAM; uint32_t clkOutputSlowVal = 0UL; uint32_t clkOutputFastVal = 0UL; - + uint32_t clkOutputSlowMask = 0UL; uint32_t clkOutputFastMask = 0UL; - + /* Prepare values for measurement control registers */ /* Connect the indicated clocks to the respective counters: @@ -1468,6 +1608,7 @@ cy_en_sysclk_status_t Cy_SysClk_StartClkMeasurementCounters(cy_en_meas_clks_t cl } return (retVal); +#endif /* ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) */ } /******************************************************************************* @@ -1486,9 +1627,9 @@ cy_en_sysclk_status_t Cy_SysClk_StartClkMeasurementCounters(cy_en_meas_clks_t cl * \param refClkFreq The reference clock frequency (clock1 or clock2). * * \return The frequency of the measured clock, in Hz. -* \warning The function returns zero, if during measurement device was in the -* Deep Sleep or partially blocking flash operation occurred. It means that -* current measurement is not valid and you should call the +* \warning The function returns zero, if during measurement device was in the +* Deep Sleep or partially blocking flash operation occurred. It means that +* current measurement is not valid and you should call the * Cy_SysClk_StartClkMeasurementCounters() function once again. * * \funcusage @@ -1497,6 +1638,13 @@ cy_en_sysclk_status_t Cy_SysClk_StartClkMeasurementCounters(cy_en_meas_clks_t cl *******************************************************************************/ uint32_t Cy_SysClk_ClkMeasurementCountersGetFreq(bool measuredClock, uint32_t refClkFreq) { +#if ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) + (void) measuredClock; + (void) refClkFreq; + (void) clk1Count1; + (void) clkCounting; + return 0UL; +#else uint32_t retVal = 0UL; bool isMeasurementValid = false; @@ -1512,7 +1660,7 @@ uint32_t Cy_SysClk_ClkMeasurementCountersGetFreq(bool measuredClock, uint32_t re /* Check whether the device was in the Deep Sleep mode or the flash partially blocked while the * operation was done */ - isMeasurementValid = ((SRSS_TST_DDFT_SLOW_CTL_REG == TST_DDFT_SLOW_CTL_DEFAULT_VAL) && + isMeasurementValid = ((SRSS_TST_DDFT_SLOW_CTL_REG == TST_DDFT_SLOW_CTL_DEFAULT_VAL) && (SRSS_TST_DDFT_FAST_CTL_REG == TST_DDFT_FAST_CTL_DEFAULT_VAL)); retVal = _FLD2VAL(SRSS_CLK_CAL_CNT2_CAL_COUNTER2, SRSS_CLK_CAL_CNT2); @@ -1535,8 +1683,9 @@ uint32_t Cy_SysClk_ClkMeasurementCountersGetFreq(bool measuredClock, uint32_t re /* Return zero value to indicate invalid measurement */ retVal = 0UL; } - + return (retVal); +#endif /* ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) */ } /** \} group_sysclk_calclk_funcs */ @@ -1575,6 +1724,10 @@ uint32_t Cy_SysClk_ClkMeasurementCountersGetFreq(bool measuredClock, uint32_t re int32_t Cy_SysClk_IloTrim(uint32_t iloFreq) { +#if ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) + (void) iloFreq; + return 0; +#else uint32_t diff; bool sign = false; @@ -1597,9 +1750,9 @@ int32_t Cy_SysClk_IloTrim(uint32_t iloFreq) { /* Get current trim value */ uint32_t trim = _FLD2VAL(SRSS_CLK_TRIM_ILO_CTL_ILO_FTRIM, SRSS_CLK_TRIM_ILO_CTL); - + diff = CY_SYSLIB_DIV_ROUND(diff, CY_SYSCLK_ILO_TRIM_STEP); - + if(sign) { trim += diff; @@ -1612,8 +1765,9 @@ int32_t Cy_SysClk_IloTrim(uint32_t iloFreq) /* Update the trim value */ CY_REG32_CLR_SET(SRSS_CLK_TRIM_ILO_CTL, SRSS_CLK_TRIM_ILO_CTL_ILO_FTRIM, trim); } - + return (sign ? (int32_t)diff : (0L - (int32_t)diff)); +#endif /* ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) */ } /******************************************************************************* @@ -1640,6 +1794,10 @@ int32_t Cy_SysClk_IloTrim(uint32_t iloFreq) int32_t Cy_SysClk_PiloTrim(uint32_t piloFreq) { +#if ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) + (void) piloFreq; + return (int32_t)CY_PRA_STATUS_ACCESS_DENIED; +#else uint32_t diff; bool sign = false; @@ -1686,7 +1844,8 @@ int32_t Cy_SysClk_PiloTrim(uint32_t piloFreq) Cy_SysClk_PiloSetTrim(trim); } - return (sign ? (int32_t)diff : (0L - (int32_t)diff)); + return ((int32_t)(sign ? (int32_t)diff : (0L - (int32_t)diff))); +#endif /* ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) */ } /** \} group_sysclk_trim_funcs */ @@ -1709,17 +1868,17 @@ int32_t Cy_SysClk_PiloTrim(uint32_t piloFreq) * * Callback function to be used when entering system Deep Sleep mode. * This function is applicable if: -* - The FLL is enabled +* - The FLL is enabled * - The PLL is enabled and is driven by ECO * * This function performs the following: * -* 1. Before entering Deep Sleep, the clock configuration is saved in SRAM. -* If the FLL/PLL source is the ECO, then the FLL/PLL is bypassed and the +* 1. Before entering Deep Sleep, the clock configuration is saved in SRAM. +* If the FLL/PLL source is the ECO, then the FLL/PLL is bypassed and the * source is changed to IMO. \n * If the FLL is enabled - it is just bypassed. * 2. Upon wakeup from Deep Sleep, the function waits for ECO stabilization, -* then restores the configuration and waits for the FLL/PLL to regain their +* then restores the configuration and waits for the FLL/PLL to regain their * frequency locks. \n * If ECO is not used and FLL is enabled - it waits for FLL lock and unbypasses it. * @@ -1731,12 +1890,12 @@ int32_t Cy_SysClk_PiloTrim(uint32_t piloFreq) * \ref Cy_SysPm_CpuEnterDeepSleep - specify \ref CY_SYSPM_DEEPSLEEP as the callback * type and call \ref Cy_SysPm_RegisterCallback. * -* \note +* \note * This function is recommended to be the last callback that is registered. * Doing so minimizes the time spent on low power mode entry and exit. \n * This function implements all four SysPm callback modes \ref cy_en_syspm_callback_mode_t. * So the \ref cy_stc_syspm_callback_t::skipMode must be set to 0UL. \n -* This function does not support such cases as, for example, FLL is enabled +* This function does not support such cases as, for example, FLL is enabled * but bypassed by user code before entering Deep Sleep. \n * You can use this callback implementation as an example to design custom low-power * callbacks for certain user application. @@ -1751,6 +1910,11 @@ int32_t Cy_SysClk_PiloTrim(uint32_t piloFreq) * \return Error / status code; see \ref cy_en_syspm_status_t. Pass if not doing * a clock measurement, otherwise Fail. Timeout if timeout waiting for ECO, FLL * or PLL to get stable / regain its frequency lock. +* CY_SYSCLK_INVALID_STATE - ECO already enabled +* For the PSoC 64 devices there are possible situations when function returns +* the PRA error status code. This is because for PSoC 64 devices the function +* uses the PRA driver to change the protected registers. Refer to +* \ref cy_en_pra_status_t for more details. * * \funcusage * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_DeepSleepCallback @@ -1758,6 +1922,7 @@ int32_t Cy_SysClk_PiloTrim(uint32_t piloFreq) *******************************************************************************/ cy_en_syspm_status_t Cy_SysClk_DeepSleepCallback(cy_stc_syspm_callback_params_t * callbackParams, cy_en_syspm_callback_mode_t mode) { + /* Bitmapped paths with enabled FLL/PLL sourced by ECO */ static uint16_t changedSourcePaths; static uint16_t pllAutoModes; @@ -1765,7 +1930,9 @@ cy_en_syspm_status_t Cy_SysClk_DeepSleepCallback(cy_stc_syspm_callback_params_t cy_en_syspm_status_t retVal = CY_SYSPM_FAIL; (void)callbackParams; /* Suppress "not used" warning */ - + (void)changedSourcePaths; + (void)pllAutoModes; + switch (mode) { case CY_SYSPM_CHECK_READY: @@ -1774,7 +1941,7 @@ cy_en_syspm_status_t Cy_SysClk_DeepSleepCallback(cy_stc_syspm_callback_params_t { /* Indicating that we can go into Deep Sleep. * Prevent starting a new clock measurement until - * after we've come back from Deep Sleep. + * after we've come back from Deep Sleep. */ preventCounting = true; retVal = CY_SYSPM_SUCCESS; @@ -1789,6 +1956,9 @@ cy_en_syspm_status_t Cy_SysClk_DeepSleepCallback(cy_stc_syspm_callback_params_t case CY_SYSPM_BEFORE_TRANSITION: { +#if ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) + retVal = (cy_en_syspm_status_t)CY_PRA_FUNCTION_CALL_RETURN_VOID(CY_PRA_MSG_TYPE_SECURE_ONLY, CY_PRA_CLK_FUNC_DS_BEFORE_TRANSITION); +#else uint32_t fllpll; /* 0 = FLL, all other values = a PLL */ /* Initialize the storage of changed paths */ @@ -1838,11 +2008,15 @@ cy_en_syspm_status_t Cy_SysClk_DeepSleepCallback(cy_stc_syspm_callback_params_t } retVal = CY_SYSPM_SUCCESS; +#endif /* ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) */ } break; case CY_SYSPM_AFTER_TRANSITION: { +#if ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) + retVal = (cy_en_syspm_status_t)CY_PRA_FUNCTION_CALL_RETURN_VOID(CY_PRA_MSG_TYPE_SECURE_ONLY, CY_PRA_CLK_FUNC_DS_AFTER_TRANSITION); +#else /* After return from Deep Sleep, for each FLL/PLL, if needed, restore the source to ECO. * And block until the FLL/PLL has regained its frequency lock. */ @@ -1869,7 +2043,7 @@ cy_en_syspm_status_t Cy_SysClk_DeepSleepCallback(cy_stc_syspm_callback_params_t /* Change this path source back to ECO */ (void)Cy_SysClk_ClkPathSetSource(fllpll, CY_SYSCLK_CLKPATH_IN_ECO); - /* Timeout wait for FLL/PLL to regain lock. + /* Timeout wait for FLL/PLL to regain lock. * Split FLL and PLL lock polling loops into two separate threads to minimize one polling loop duration. */ if (0UL == fllpll) @@ -1886,7 +2060,7 @@ cy_en_syspm_status_t Cy_SysClk_DeepSleepCallback(cy_stc_syspm_callback_params_t timeout--; } } - + if (0UL != timeout) { /* Undo bypass the FLL/PLL */ @@ -1933,14 +2107,16 @@ cy_en_syspm_status_t Cy_SysClk_DeepSleepCallback(cy_stc_syspm_callback_params_t } preventCounting = false; /* Allow clock measurement */ +#endif /* ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) */ } break; default: /* Unsupported mode, return CY_SYSPM_FAIL */ break; } - + return (retVal); + } /** \} group_sysclk_pm_funcs */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_sysint.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_sysint.c index 834b111aff..70d511bcb8 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_sysint.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_sysint.c @@ -1,13 +1,13 @@ /***************************************************************************//** * \file cy_sysint.c -* \version 1.30 +* \version 1.30.1 * * \brief * Provides an API implementation of the SysInt driver. * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -41,8 +41,8 @@ * \param userIsr * Address of the ISR * -* \return -* Initialization status +* \return +* Initialization status * * \note The interrupt vector will be relocated only if the vector table was * moved to __ramVectors in SRAM. Otherwise it is ignored. @@ -69,9 +69,9 @@ cy_en_sysint_status_t Cy_SysInt_Init(const cy_stc_sysint_t* config, cy_israddres status = CY_SYSINT_BAD_PARAM; } #endif - + NVIC_SetPriority(config->intrSrc, config->intrPriority); - + /* Set the new vector only if it was moved to __ramVectors */ if (SCB->VTOR == (uint32_t)&__ramVectors) { @@ -82,7 +82,7 @@ cy_en_sysint_status_t Cy_SysInt_Init(const cy_stc_sysint_t* config, cy_israddres { status = CY_SYSINT_BAD_PARAM; } - + return(status); } @@ -111,7 +111,7 @@ cy_en_sysint_status_t Cy_SysInt_Init(const cy_stc_sysint_t* config, cy_israddres * *******************************************************************************/ void Cy_SysInt_SetInterruptSource(IRQn_Type IRQn, cy_en_intr_t devIntrSrc) -{ +{ if (CY_CPUSS_V1) { uint32_t regPos = ((uint32_t)IRQn >> CY_SYSINT_CM0P_MUX_SHIFT); @@ -119,7 +119,7 @@ void Cy_SysInt_SetInterruptSource(IRQn_Type IRQn, cy_en_intr_t devIntrSrc) { uint32_t bitfield_Pos = (uint32_t)((uint32_t)IRQn - (uint32_t)(regPos << CY_SYSINT_CM0P_MUX_SHIFT)) << CY_SYSINT_CM0P_MUX_SCALE; uint32_t bitfield_Msk = (uint32_t)(CY_SYSINT_CM0P_MUX_MASK << bitfield_Pos); - + CY_REG32_CLR_SET(CPUSS_CM0_INT_CTL[regPos], bitfield, devIntrSrc); } } @@ -175,9 +175,9 @@ void Cy_SysInt_DisconnectInterruptSource(IRQn_Type IRQn, cy_en_intr_t devIntrSrc * \param IRQn * NVIC channel number connected to the CPU core * -* \return -* Device interrupt connected to the NVIC channel. A returned value of -* "disconnected_IRQn" indicates that the interrupt source is disconnected. +* \return +* Device interrupt connected to the NVIC channel. A returned value of +* "disconnected_IRQn" indicates that the interrupt source is disconnected. * * \note This function is available for CM0+ core only. * @@ -199,7 +199,7 @@ cy_en_intr_t Cy_SysInt_GetInterruptSource(IRQn_Type IRQn) { uint32_t bitfield_Pos = ((uint32_t)IRQn - (regPos << CY_SYSINT_CM0P_MUX_SHIFT)) << CY_SYSINT_CM0P_MUX_SCALE; uint32_t bitfield_Msk = (uint32_t)(CY_SYSINT_CM0P_MUX_MASK << bitfield_Pos); - + tempReg = _FLD2VAL(bitfield, CPUSS_CM0_INT_CTL[regPos]); } } @@ -207,7 +207,7 @@ cy_en_intr_t Cy_SysInt_GetInterruptSource(IRQn_Type IRQn) return ((cy_en_intr_t)tempReg); } - + /******************************************************************************* * Function Name: Cy_SysInt_GetNvicConnection ****************************************************************************//** @@ -248,7 +248,7 @@ IRQn_Type Cy_SysInt_GetNvicConnection(cy_en_intr_t devIntrSrc) * \brief Gets the highest priority active interrupt for the selected NVIC channel. * * The priority of the interrupt in a given channel is determined by the index -* value of the interrupt in the cy_en_intr_t enum. The lower the index, the +* value of the interrupt in the cy_en_intr_t enum. The lower the index, the * higher the priority. E.g. Consider a case where an interrupt source with value * 29 and an interrupt source with value 46 both source the same NVIC channel. If * both are active (triggered) at the same time, calling Cy_SysInt_GetInterruptActive() @@ -258,9 +258,9 @@ IRQn_Type Cy_SysInt_GetNvicConnection(cy_en_intr_t devIntrSrc) * NVIC channel number connected to the CPU core * * \return -* Device interrupt connected to the NVIC channel. A returned value of -* "disconnected_IRQn" indicates that there are no active (pending) interrupts -* on this NVIC channel. +* Device interrupt connected to the NVIC channel. A returned value of +* "disconnected_IRQn" indicates that there are no active (pending) interrupts +* on this NVIC channel. * * \note This function is available for CM0+ core only. * @@ -314,7 +314,7 @@ cy_en_intr_t Cy_SysInt_GetInterruptActive(IRQn_Type IRQn) cy_israddress Cy_SysInt_SetVector(IRQn_Type IRQn, cy_israddress userIsr) { cy_israddress prevIsr; - + /* Set the new vector only if it was moved to __ramVectors */ if (SCB->VTOR == (uint32_t)&__ramVectors) { @@ -348,7 +348,7 @@ cy_israddress Cy_SysInt_SetVector(IRQn_Type IRQn, cy_israddress userIsr) * \return * Address of the ISR in the interrupt vector table * -* \note For CM0+, this function returns the interrupt vector for the interrupt +* \note For CM0+, this function returns the interrupt vector for the interrupt * channel on the NVIC. * * \funcusage @@ -358,7 +358,7 @@ cy_israddress Cy_SysInt_SetVector(IRQn_Type IRQn, cy_israddress userIsr) cy_israddress Cy_SysInt_GetVector(IRQn_Type IRQn) { cy_israddress currIsr; - + /* Return the SRAM ISR address only if it was moved to __ramVectors */ if (SCB->VTOR == (uint32_t)&__ramVectors) { @@ -368,7 +368,7 @@ cy_israddress Cy_SysInt_GetVector(IRQn_Type IRQn) { currIsr = __Vectors[CY_INT_IRQ_BASE + IRQn]; } - + return (currIsr); } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_syslib.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_syslib.c index 95e9d1482c..7e0eddf3c6 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_syslib.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_syslib.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_syslib.c -* \version 2.50.3 +* \version 2.60 * * Description: * Provides system API implementation for the SysLib driver. @@ -27,6 +27,9 @@ #if !defined(NDEBUG) #include #endif /* NDEBUG */ +#if defined(CY_DEVICE_SECURE) + #include "cy_pra.h" +#endif /* defined(CY_DEVICE_SECURE) */ /* Flash wait states (ULP mode at 0.9v) */ #define CY_SYSLIB_FLASH_ULP_WS_0_FREQ_MAX ( 16UL) @@ -71,7 +74,7 @@ * \param milliseconds The number of milliseconds to delay. * * \note The function calls \ref Cy_SysLib_DelayCycles() API to generate a delay. -* If the function parameter (milliseconds) is bigger than +* If the function parameter (milliseconds) is bigger than * CY_DELAY_MS_OVERFLOW constant, then an additional loop runs to prevent * an overflow in parameter passed to \ref Cy_SysLib_DelayCycles() API. * @@ -203,7 +206,11 @@ __WEAK void Cy_SysLib_AssertFailed(const char_t * file, uint32_t line) *******************************************************************************/ void Cy_SysLib_ClearFlashCacheAndBuffer(void) { - FLASHC_FLASH_CMD = FLASHC_FLASH_CMD_INV_Msk; + #if CY_CPU_CORTEX_M4 && defined(CY_DEVICE_SECURE) + CY_PRA_REG32_SET(CY_PRA_INDX_FLASHC_FLASH_CMD, FLASHC_FLASH_CMD_INV_Msk); + #else + FLASHC_FLASH_CMD = FLASHC_FLASH_CMD_INV_Msk; + #endif /* CY_CPU_CORTEX_M4 && defined(CY_DEVICE_SECURE) */ } @@ -294,15 +301,18 @@ void Cy_SysLib_ClearResetReason(void) */ SRSS_RES_CAUSE = 0xFFFFFFFFU; SRSS_RES_CAUSE2 = 0xFFFFFFFFU; - + if(0U != _FLD2VAL(SRSS_PWR_HIBERNATE_TOKEN, SRSS_PWR_HIBERNATE)) { /* Clears PWR_HIBERNATE token */ - SRSS_PWR_HIBERNATE &= ~SRSS_PWR_HIBERNATE_TOKEN_Msk; + #if CY_CPU_CORTEX_M4 && defined(CY_DEVICE_SECURE) + CY_PRA_REG32_CLR_SET(CY_PRA_INDX_SRSS_PWR_HIBERNATE, SRSS_PWR_HIBERNATE_TOKEN, 0UL); + #else + SRSS_PWR_HIBERNATE &= ~SRSS_PWR_HIBERNATE_TOKEN_Msk; + #endif /* CY_CPU_CORTEX_M4 && defined(CY_DEVICE_SECURE) */ } } - #if (CY_CPU_CORTEX_M0P) || defined(CY_DOXYGEN) /******************************************************************************* * Function Name: Cy_SysLib_SoftResetCM4 @@ -523,6 +533,7 @@ __WEAK void Cy_SysLib_ProcessingFault(void) *******************************************************************************/ void Cy_SysLib_SetWaitStates(bool ulpMode, uint32_t clkHfMHz) { +#if !((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) uint32_t waitStates; uint32_t freqMax; @@ -556,11 +567,15 @@ void Cy_SysLib_SetWaitStates(bool ulpMode, uint32_t clkHfMHz) waitStates = (clkHfMHz <= cy_device->flashCtlMainWs0Freq) ? 0UL : ((clkHfMHz <= cy_device->flashCtlMainWs1Freq) ? 1UL : ((clkHfMHz <= cy_device->flashCtlMainWs2Freq) ? 2UL : - ((clkHfMHz <= cy_device->flashCtlMainWs3Freq) ? 3UL : + ((clkHfMHz <= cy_device->flashCtlMainWs3Freq) ? 3UL : ((clkHfMHz <= cy_device->flashCtlMainWs4Freq) ? 4UL : 5UL)))); } FLASHC_FLASH_CTL = _CLR_SET_FLD32U(FLASHC_FLASH_CTL, FLASHC_FLASH_CTL_MAIN_WS, waitStates); +#else + (void) ulpMode; + (void) clkHfMHz; +#endif /* !((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) */ } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_syspm.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_syspm.c index a2d7434da0..495e164edc 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_syspm.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_syspm.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_syspm.c -* \version 5.0 +* \version 5.10 * * This driver provides the source code for API power management. * @@ -27,17 +27,22 @@ #include "cy_ipc_pipe.h" #include "cy_prot.h" +#if ((CY_CPU_CORTEX_M0P) && (defined(CY_DEVICE_SECURE))) + #include "cy_pra_cfg.h" +#endif /* #if ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) */ /******************************************************************************* * Internal Functions *******************************************************************************/ static void EnterDeepSleepRam(cy_en_syspm_waitfor_t waitFor); +#if !((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) static void SetReadMarginTrimUlp(void); static void SetReadMarginTrimLp(void); static void SetWriteAssistTrimUlp(void); static void SetWriteAssistTrimLp(void); static bool IsVoltageChangePossible(void); +#endif /* !((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) */ /******************************************************************************* @@ -92,7 +97,7 @@ static bool IsVoltageChangePossible(void); /* The UDB placement on MMIO slave level */ #define PERI_UDB_SLAVE_ENABLED ((uint32_t) 1UL << MMIO_UDB_GROUP_NR) -/* The definition for the delay of the LDO after its output +/* The definition for the delay of the LDO after its output * voltage is changed */ #define LDO_STABILIZATION_DELAY_US (9U) @@ -121,12 +126,12 @@ static bool IsVoltageChangePossible(void); /* Define for transitional 1.15 V for the LDO regulator */ #define LDO_OUT_VOLTAGE_1_15V (0x1BU) -/* The definition for the delay of the Buck supply regulator +/* The definition for the delay of the Buck supply regulator * stabilization after it is configured with enabled Buck output 1 */ #define BUCK_INIT_STABILIZATION_US (900U) -/* The definition for the delay of the Buck supply regulator -* stabilization after it is configured with enabled Buck +/* The definition for the delay of the Buck supply regulator +* stabilization after it is configured with enabled Buck * output 2 only */ #define BUCK_OUT2_INIT_DELAY_US (600U) @@ -178,8 +183,13 @@ static bool IsVoltageChangePossible(void); /* The pointer to the Cy_EnterDeepSleep() function in the ROM */ #define ROM_ENTER_DEEP_SLEEP_ADDR (*(uint32_t *) 0x00000D30UL) -/* The define to call the ROM Cy_EnterDeepSleep() function. -* The ROM Cy_EnterDeepSleep() function prepares the system for the Deep Sleep +#if ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) + #define PM_HIBERNATE_ENTER_HIBERNATE (0UL) + #define PM_HIBERNATE_IO_UNFREEZE (1UL) +#endif /* ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) */ + +/* The define to call the ROM Cy_EnterDeepSleep() function. +* The ROM Cy_EnterDeepSleep() function prepares the system for the Deep Sleep * and restores the system after wakeup from the Deep Sleep. */ typedef void (*cy_cb_syspm_deep_sleep_t)(cy_en_syspm_waitfor_t waitFor, bool *wasEventSent); @@ -209,17 +219,17 @@ typedef void (*cy_cb_syspm_deep_sleep_t)(cy_en_syspm_waitfor_t waitFor, bool *wa #define SET_MIN_CURRENT_MODE_DELAY_US (1U) /* The wait delay time that occurs before the active reference is settled. -* Intermediate delay is used in transition into the normal regulator current +* Intermediate delay is used in transition into the normal regulator current * mode */ #define ACT_REF_SETTLE_DELAY_US (8U) -/* The wait delay time that occurs after the active reference is settled. +/* The wait delay time that occurs after the active reference is settled. * Final delay is used in transition into the normal regulator current mode */ #define SET_NORMAL_CURRENT_MODE_DELAY_US (1U) -/* The internal define of the tries number in the +/* The internal define of the tries number in the * Cy_SysPm_SystemSetMinRegulatorCurrent() function */ #define WAIT_DELAY_TRYES (100U) @@ -266,7 +276,7 @@ typedef void (*cy_cb_syspm_deep_sleep_t)(cy_en_syspm_waitfor_t waitFor, bool *wa */ #define PWR_CIRCUITS_SET_LPMODE_LDO_MASK (SRSS_PWR_CTL_LINREG_LPMODE_Msk | PWR_CIRCUITS_SET_LPMODE_BUCK_MASK) -/* The mask for low power modes the power circuits (POR/BOD, Bandgap reference, +/* The mask for low power modes the power circuits (POR/BOD, Bandgap reference, * Reference buffer, Current reference) when active core regulator is Buck */ #define PWR_CIRCUITS_SET_LPMODE_BUCK_MASK (SRSS_PWR_CTL_PORBOD_LPMODE_Msk |\ @@ -296,7 +306,7 @@ static cy_stc_syspm_callback_t* failedCallback[CALLBACK_ROOT_NR] = {NULL, NULL, * * Reads the power modes status of the system and CPU(s). * -* \return +* \return * The current power mode. See \ref group_syspm_return_status. * * \funcusage @@ -337,12 +347,12 @@ uint32_t Cy_SysPm_ReadStatus(void) pmStatus |= CY_SYSPM_STATUS_CM0_ACTIVE; } - /* Check whether the device is in LP mode by reading + /* Check whether the device is in LP mode by reading * the core voltage: * - 0.9V (nominal) - System ULP mode * - 1.1V (nominal) - System LP mode */ - + /* Read current active regulator */ if (Cy_SysPm_LdoIsEnabled()) { @@ -379,7 +389,7 @@ uint32_t Cy_SysPm_ReadStatus(void) * * Sets executing CPU to Sleep mode. * -* Puts the CPU executing this function into CPU Sleep power mode. If callback +* Puts the CPU executing this function into CPU Sleep power mode. If callback * functions were registered they are also executed. * * For more detail about switching into CPU Sleep power mode and debug, @@ -388,59 +398,59 @@ uint32_t Cy_SysPm_ReadStatus(void) * If at least one callback function with the CY_SYSPM_SLEEP type was registered, * the following algorithm is executed: * Prior to entering CPU Sleep mode, all callback functions of the CY_SYSPM_SLEEP -* type with the CY_SYSPM_CHECK_READY parameter are called. This allows the -* driver to signal whether it is ready to enter the low power mode. If any of -* the callbacks of the CY_SYSPM_SLEEP type with the CY_SYSPM_CHECK_READY -* parameter returns CY_SYSPM_FAIL, the remaining callbacks of the +* type with the CY_SYSPM_CHECK_READY parameter are called. This allows the +* driver to signal whether it is ready to enter the low power mode. If any of +* the callbacks of the CY_SYSPM_SLEEP type with the CY_SYSPM_CHECK_READY +* parameter returns CY_SYSPM_FAIL, the remaining callbacks of the * CY_SYSPM_SLEEP type with the CY_SYSPM_CHECK_READY parameter are skipped. -* After the first CY_SYSPM_FAIL, all the CY_SYSPM_SLEEP callbacks that were -* previously executed before getting the CY_SYSPM_CHECK_FAIL are executed with -* the CY_SYSPM_CHECK_FAIL parameter. The CPU Sleep mode is not entered and the +* After the first CY_SYSPM_FAIL, all the CY_SYSPM_SLEEP callbacks that were +* previously executed before getting the CY_SYSPM_CHECK_FAIL are executed with +* the CY_SYSPM_CHECK_FAIL parameter. The CPU Sleep mode is not entered and the * Cy_SysPm_CpuEnterSleep() function returns CY_SYSPM_FAIL. * -* If all of the callbacks of the CY_SYSPM_SLEEP type with the -* CY_SYSPM_CHECK_READY parameter return CY_SYSPM_SUCCESS, then all -* callbacks of the CY_SYSPM_SLEEP type with the CY_SYSPM_CHECK_FAIL parameters +* If all of the callbacks of the CY_SYSPM_SLEEP type with the +* CY_SYSPM_CHECK_READY parameter return CY_SYSPM_SUCCESS, then all +* callbacks of the CY_SYSPM_SLEEP type with the CY_SYSPM_CHECK_FAIL parameters * calls are skipped. All callbacks of the CY_SYSPM_SLEEP type and then -* CY_SYSPM_BEFORE_TRANSITION parameter calls are executed, allowing the +* CY_SYSPM_BEFORE_TRANSITION parameter calls are executed, allowing the * peripherals to prepare for CPU Sleep. The CPU then enters Sleep mode. * This is a CPU-centric power mode. This means that the CPU has entered Sleep -* mode and its main clock is removed. Any enabled interrupt can cause a CPU -* wakeup from Sleep mode. +* mode and its main clock is removed. Any enabled interrupt can cause a CPU +* wakeup from Sleep mode. * -* For multi-core devices, CPU wakeup can also be performed using the Send Event -* (SEV) assembly instruction executed from the other active CPU. Such wakeup is -* expected only if the CPU Sleep power mode is done with WFE assembly +* For multi-core devices, CPU wakeup can also be performed using the Send Event +* (SEV) assembly instruction executed from the other active CPU. Such wakeup is +* expected only if the CPU Sleep power mode is done with WFE assembly * instruction. * -* After a wakeup from CPU Sleep, all of the registered callbacks of the -* CY_SYSPM_SLEEP type and with the CY_SYSPM_AFTER_TRANSITION parameter are -* executed to return the peripherals to CPU active operation. +* After a wakeup from CPU Sleep, all of the registered callbacks of the +* CY_SYSPM_SLEEP type and with the CY_SYSPM_AFTER_TRANSITION parameter are +* executed to return the peripherals to CPU active operation. * The Cy_SysPm_CpuEnterSleep() function returns CY_SYSPM_SUCCESS. -* No callbacks of the CY_SYSPM_SLEEP type with the CY_SYSPM_BEFORE_TRANSITION -* parameter or callbacks of the CY_SYSPM_SLEEP type and -* CY_SYSPM_AFTER_TRANSITION parameter callbacks are executed if CPU Sleep mode +* No callbacks of the CY_SYSPM_SLEEP type with the CY_SYSPM_BEFORE_TRANSITION +* parameter or callbacks of the CY_SYSPM_SLEEP type and +* CY_SYSPM_AFTER_TRANSITION parameter callbacks are executed if CPU Sleep mode * is not entered. * -* \note The last callback that returns CY_SYSPM_FAIL is not executed with the -* CY_SYSPM_CHECK_FAIL parameter because of the FAIL. The callback generating +* \note The last callback that returns CY_SYSPM_FAIL is not executed with the +* CY_SYSPM_CHECK_FAIL parameter because of the FAIL. The callback generating * CY_SYSPM_FAIL is expected to not make any changes that require being undone. * -* To support control of callback execution order th following method is -* implemented. Callback function with the CY_SYSPM_CHECK_READY and -* CY_SYSPM_BEFORE_TRANSITION parameter are executed in the same order they are -* registered. Callback function with the CY_SYSPM_CHECK_FAIL and -* CY_SYSPM_AFTER_TRANSITION parameter are executed in the reverse order they -* are registered. +* To support control of callback execution order th following method is +* implemented. Callback function with the CY_SYSPM_CHECK_READY and +* CY_SYSPM_BEFORE_TRANSITION parameter are executed in the same order they are +* registered. Callback function with the CY_SYSPM_CHECK_FAIL and +* CY_SYSPM_AFTER_TRANSITION parameter are executed in the reverse order they +* are registered. -* The return value from executed callback functions with the +* The return value from executed callback functions with the * CY_SYSPM_CHECK_FAIL, CY_SYSPM_BEFORE_TRANSITION, and CY_SYSPM_AFTER_TRANSITION * modes are ignored. * * \ref cy_en_syspm_callback_mode_t, except the CY_SYSPM_CHECK_READY, are ignored * -* \note The Arm BSD assembly instruction is not required in this function -* because the function implementation ensures the SLEEPDEEP bit of SCS register +* \note The Arm BSD assembly instruction is not required in this function +* because the function implementation ensures the SLEEPDEEP bit of SCS register * is settled prior executing WFI/WFE instruction. * * \param waitFor @@ -450,7 +460,7 @@ uint32_t Cy_SysPm_ReadStatus(void) * Entered status, see \ref cy_en_syspm_status_t. * * \sideeffect -* For CY8C6xx6, CY8C6xx7 devices this function clears the Event Register of the +* For CY8C6xx6, CY8C6xx7 devices this function clears the Event Register of the * CM4 CPU after wakeup from WFE. * * \funcusage @@ -462,7 +472,7 @@ cy_en_syspm_status_t Cy_SysPm_CpuEnterSleep(cy_en_syspm_waitfor_t waitFor) uint32_t interruptState; uint32_t cbSleepRootIdx = (uint32_t) CY_SYSPM_SLEEP; cy_en_syspm_status_t retVal = CY_SYSPM_SUCCESS; - + CY_ASSERT_L3(CY_SYSPM_IS_WAIT_FOR_VALID(waitFor)); /* Call registered callback functions with CY_SYSPM_CHECK_READY parameter */ @@ -472,12 +482,12 @@ cy_en_syspm_status_t Cy_SysPm_CpuEnterSleep(cy_en_syspm_waitfor_t waitFor) } /* The CPU can switch into the Sleep power mode only when - * all executed registered callback functions with the CY_SYSPM_CHECK_READY + * all executed registered callback functions with the CY_SYSPM_CHECK_READY * parameter return CY_SYSPM_SUCCESS. */ if(retVal == CY_SYSPM_SUCCESS) { - /* Call the registered callback functions with + /* Call the registered callback functions with * CY_SYSPM_BEFORE_TRANSITION parameter */ interruptState = Cy_SysLib_EnterCriticalSection(); @@ -500,7 +510,7 @@ cy_en_syspm_status_t Cy_SysPm_CpuEnterSleep(cy_en_syspm_waitfor_t waitFor) #if (CY_CPU_CORTEX_M4) if (Cy_SysLib_GetDevice() == CY_SYSLIB_DEVICE_PSOC6ABLE2) { - /* For the CM4 CPU, the WFE instruction is called twice. + /* For the CM4 CPU, the WFE instruction is called twice. * The second WFE call clears the Event Register of CM4 CPU. * Cypress ID #279077. */ @@ -515,7 +525,7 @@ cy_en_syspm_status_t Cy_SysPm_CpuEnterSleep(cy_en_syspm_waitfor_t waitFor) } Cy_SysLib_ExitCriticalSection(interruptState); - /* Call the registered callback functions with the + /* Call the registered callback functions with the * CY_SYSPM_AFTER_TRANSITION parameter */ if (pmCallbackRoot[cbSleepRootIdx] != NULL) @@ -526,7 +536,7 @@ cy_en_syspm_status_t Cy_SysPm_CpuEnterSleep(cy_en_syspm_waitfor_t waitFor) else { /* Execute callback functions with the CY_SYSPM_CHECK_FAIL parameter to - * undo everything done in the callback with the CY_SYSPM_CHECK_READY + * undo everything done in the callback with the CY_SYSPM_CHECK_READY * parameter */ (void) Cy_SysPm_ExecuteCallback(CY_SYSPM_SLEEP, CY_SYSPM_CHECK_FAIL); @@ -543,32 +553,32 @@ cy_en_syspm_status_t Cy_SysPm_CpuEnterSleep(cy_en_syspm_waitfor_t waitFor) * Sets executing CPU to the Deep Sleep mode. * * Puts the CPU executing the function into CPU Deep Sleep. For a single CPU -* devices the device will immediately transition to system Deep Sleep. For a -* dual CPU devices the device will transition to system Deep Sleep only after -* both CPUs are in CPU Deep Sleep power mode. +* devices the device will immediately transition to system Deep Sleep. For a +* dual CPU devices the device will transition to system Deep Sleep only after +* both CPUs are in CPU Deep Sleep power mode. * -* Prior to entering the CPU Deep Sleep mode, all callbacks of the -* CY_SYSPM_DEEPSLEEP type with the CY_SYSPM_CHECK_READY parameter registered -* callbacks are called, allowing the driver to signal whether it is ready to -* enter the power mode. If any CY_SYSPM_DEEPSLEEP type with the -* CY_SYSPM_CHECK_READY parameter call returns CY_SYSPM_FAIL, the remaining -* callback CY_SYSPM_DEEPSLEEP type with the CY_SYSPM_CHECK_READY parameter are -* skipped. After the first CY_SYSPM_FAIL, all the CY_SYSPM_DEEPSLEEP callbacks -* that were previously executed before getting the CY_SYSPM_CHECK_FAIL are -* executed with the CY_SYSPM_CHECK_FAIL parameter. The CPU Deep Sleep mode is -* not entered and the Cy_SysPm_CpuEnterDeepSleep() function returns +* Prior to entering the CPU Deep Sleep mode, all callbacks of the +* CY_SYSPM_DEEPSLEEP type with the CY_SYSPM_CHECK_READY parameter registered +* callbacks are called, allowing the driver to signal whether it is ready to +* enter the power mode. If any CY_SYSPM_DEEPSLEEP type with the +* CY_SYSPM_CHECK_READY parameter call returns CY_SYSPM_FAIL, the remaining +* callback CY_SYSPM_DEEPSLEEP type with the CY_SYSPM_CHECK_READY parameter are +* skipped. After the first CY_SYSPM_FAIL, all the CY_SYSPM_DEEPSLEEP callbacks +* that were previously executed before getting the CY_SYSPM_CHECK_FAIL are +* executed with the CY_SYSPM_CHECK_FAIL parameter. The CPU Deep Sleep mode is +* not entered and the Cy_SysPm_CpuEnterDeepSleep() function returns * CY_SYSPM_FAIL. * * If all callbacks of the CY_SYSPM_DEEPSLEEP type with the CY_SYSPM_CHECK_READY -* parameter return CY_SYSPM_SUCCESS, then all callbacks of the -* CY_SYSPM_DEEPSLEEP type with the CY_SYSPM_CHECK_FAIL parameter calls are -* skipped. All callbacks of the CY_SYSPM_DEEPSLEEP type with the -* CY_SYSPM_BEFORE_TRANSITION parameter calls are then executed, allowing the -* peripherals to prepare for CPU Deep Sleep. The Deep Sleep mode is then +* parameter return CY_SYSPM_SUCCESS, then all callbacks of the +* CY_SYSPM_DEEPSLEEP type with the CY_SYSPM_CHECK_FAIL parameter calls are +* skipped. All callbacks of the CY_SYSPM_DEEPSLEEP type with the +* CY_SYSPM_BEFORE_TRANSITION parameter calls are then executed, allowing the +* peripherals to prepare for CPU Deep Sleep. The Deep Sleep mode is then * entered. Any enabled interrupt can cause a wakeup from the Deep Sleep mode. * -* \note The last callback that returns CY_SYSPM_FAIL is not executed with the -* CY_SYSPM_CHECK_FAIL parameter because of the FAIL. The callback generating +* \note The last callback that returns CY_SYSPM_FAIL is not executed with the +* CY_SYSPM_CHECK_FAIL parameter because of the FAIL. The callback generating * CY_SYSPM_FAIL is expected to not make any changes that require being undone. * * For multi-CPU devices (except CY8C6xx6 and CY8C6xx7) there is a possible @@ -578,86 +588,90 @@ cy_en_syspm_status_t Cy_SysPm_CpuEnterSleep(cy_en_syspm_waitfor_t waitFor) * with the CY_SYSPM_CHECK_FAIL parameter. Deep Sleep mode is not entered and * the Cy_SysPm_CpuEnterDeepSleep() function returns CY_SYSPM_SYSCALL_PENDING. * -* The return value from executed callback functions with the +* The return value from executed callback functions with the * CY_SYSPM_CHECK_FAIL, CY_SYSPM_BEFORE_TRANSITION, and CY_SYSPM_AFTER_TRANSITION * modes are ignored. * * If the firmware attempts to enter this mode before the system is ready (that * is, when PWR_CONTROL.LPM_READY = 0), then the CPU(s) will go into the CPU * Sleep mode instead and automatically enter system Deep Sleep mode when the -* system is ready. On dual CPU devices, if one CPU enters CPU Deep Sleep and the -* other CPU remains active or is in CPU Sleep the first CPU will remain in CPU +* system is ready. On dual CPU devices, if one CPU enters CPU Deep Sleep and the +* other CPU remains active or is in CPU Sleep the first CPU will remain in CPU * Deep Sleep. A CPU Deep Sleep is functionally identical to CPU Sleep. * -* The device enters system Deep Sleep mode when all the CPU(s) are in CPU +* The device enters system Deep Sleep mode when all the CPU(s) are in CPU * Deep Sleep, there are no busy peripherals, the debugger is not active, and the * Deep Sleep power and reference are ready (PWR_CONTROL.LPM_READY=1). * * The peripherals that do not need a clock or that receive a clock from their * external interface (e.g. I2C/SPI) may continue operating in system Deep Sleep. -* All circuits using current from Vccdpslp supply are limited by its maximum +* All circuits using current from Vccdpslp supply are limited by its maximum * current specification of the Deep Sleep regulator. * * Wakeup occurs when an interrupt asserts from a Deep Sleep active peripheral. * For more detail, see the corresponding peripheral's datasheet. * -* For multi-core devices, CPU wakeup can also be performed using the Send Event -* (SEV) assembly instruction executed from the other active CPU. Such wakeup is -* expected only if the CPU Sleep power mode is done with WFE assembly +* For multi-core devices, CPU wakeup can also be performed using the Send Event +* (SEV) assembly instruction executed from the other active CPU. Such wakeup is +* expected only if the CPU Sleep power mode is done with WFE assembly * instruction. * -* \note -* For multi-CPU devices, the second CPU, if it did not participate in -* system wakeup, remains in CPU Deep Sleep mode. Any Deep Sleep capable +* \note +* For multi-CPU devices, the second CPU, if it did not participate in +* system wakeup, remains in CPU Deep Sleep mode. Any Deep Sleep capable * interrupt routed to this CPU can also wake it. * -* For more detail about switching into the system Deep Sleep power mode and +* For more detail about switching into the system Deep Sleep power mode and * debug, refer to the device TRM. * -* A normal wakeup from the Deep Sleep power mode returns to either ULP or LP -* mode, depending on the previous state and programmed behavior for the -* particular wakeup interrupt. As soon as the system resumes LP or ULP mode the -* CPU(s) return to CPU Active or CPU Deep Sleep mode, depending on their +* A normal wakeup from the Deep Sleep power mode returns to either ULP or LP +* mode, depending on the previous state and programmed behavior for the +* particular wakeup interrupt. As soon as the system resumes LP or ULP mode the +* CPU(s) return to CPU Active or CPU Deep Sleep mode, depending on their * configured wakeup settings. * * After wakeup from CPU Deep Sleep, all of the registered callbacks with -* CY_SYSPM_DEEPSLEEP type with CY_SYSPM_AFTER_TRANSITION are executed to return -* peripherals to active operation. The Cy_SysPm_CpuEnterDeepSleep() function -* returns CY_SYSPM_SUCCESS. No callbacks are executed with CY_SYSPM_DEEPSLEEP -* type with CY_SYSPM_BEFORE_TRANSITION or CY_SYSPM_AFTER_TRANSITION parameter, +* CY_SYSPM_DEEPSLEEP type with CY_SYSPM_AFTER_TRANSITION are executed to return +* peripherals to active operation. The Cy_SysPm_CpuEnterDeepSleep() function +* returns CY_SYSPM_SUCCESS. No callbacks are executed with CY_SYSPM_DEEPSLEEP +* type with CY_SYSPM_BEFORE_TRANSITION or CY_SYSPM_AFTER_TRANSITION parameter, * if Deep Sleep mode was not entered. * -* To support control of callback execution order th following method is -* implemented. Callback function with the CY_SYSPM_CHECK_READY and -* CY_SYSPM_BEFORE_TRANSITION parameter are executed in the same order they are -* registered. Callback function with the CY_SYSPM_CHECK_FAIL and -* CY_SYSPM_AFTER_TRANSITION parameter are executed in the reverse order they +* To support control of callback execution order th following method is +* implemented. Callback function with the CY_SYSPM_CHECK_READY and +* CY_SYSPM_BEFORE_TRANSITION parameter are executed in the same order they are +* registered. Callback function with the CY_SYSPM_CHECK_FAIL and +* CY_SYSPM_AFTER_TRANSITION parameter are executed in the reverse order they * are registered. * -* \param waitFor +* \param waitFor * Selects wait for action. See \ref cy_en_syspm_waitfor_t. * * \sideeffect -* For CY8C6xx6, CY8C6xx7 devices this function clears the Event Register of the +* For CY8C6xx6, CY8C6xx7 devices this function clears the Event Register of the * CM4 CPU after wakeup from WFE. * * \sideeffect -* This function changes the slow and fast clock dividers right before +* This function changes the slow and fast clock dividers right before * entering into system Deep Sleep and restores these dividers after wakeup. * * \return * Entered status, see \ref cy_en_syspm_status_t. +* For the PSoC 64 devices there are possible situations when function returns +* the PRA error status code. This is because for PSoC 64 devices the function +* uses the PRA driver to change the protected registers. Refer to +* \ref cy_en_pra_status_t for more details. * * \note -* The FLL/PLL are not restored right before the CPU(s) start executing the -* instructions after system Deep Sleep. This can affect the peripheral that is +* The FLL/PLL are not restored right before the CPU(s) start executing the +* instructions after system Deep Sleep. This can affect the peripheral that is * driven by PLL/FLL. Ensure that the PLL/FLL are properly restored (locked) -* after wakeup from System Deep Sleep. Refer to the -* \ref group_sysclk driver documentation for information about how to +* after wakeup from System Deep Sleep. Refer to the +* \ref group_sysclk driver documentation for information about how to * read the PLL/FLL lock statuses. * -* \note The Arm BSD assembly instruction is not required in this function -* because the function implementation ensures the SLEEPDEEP bit of SCS register +* \note The Arm BSD assembly instruction is not required in this function +* because the function implementation ensures the SLEEPDEEP bit of SCS register * is settled prior executing the WFI/WFE instruction. * * \funcusage @@ -667,18 +681,18 @@ cy_en_syspm_status_t Cy_SysPm_CpuEnterSleep(cy_en_syspm_waitfor_t waitFor) cy_en_syspm_status_t Cy_SysPm_CpuEnterDeepSleep(cy_en_syspm_waitfor_t waitFor) { /* Structure for registers that should retain while Deep Sleep mode */ +#if ((CY_CPU_CORTEX_M0P) || (!defined(CY_DEVICE_SECURE))) static cy_stc_syspm_backup_regs_t bkpRegs; - + uint8_t deviceRev = Cy_SysLib_GetDeviceRevision(); +#endif /* ((CY_CPU_CORTEX_M0P) || (!defined(CY_DEVICE_SECURE))) */ uint32_t interruptState; uint32_t cbDeepSleepRootIdx = (uint32_t) CY_SYSPM_DEEPSLEEP; uint32_t ddftStructData = 0UL; - uint8_t deviceRev; cy_en_syspm_status_t retVal = CY_SYSPM_SUCCESS; CY_ASSERT_L3(CY_SYSPM_IS_WAIT_FOR_VALID(waitFor)); - deviceRev = Cy_SysLib_GetDeviceRevision(); - /* Call the registered callback functions with the CY_SYSPM_CHECK_READY + /* Call the registered callback functions with the CY_SYSPM_CHECK_READY * parameter */ if (pmCallbackRoot[cbDeepSleepRootIdx] != NULL) @@ -692,7 +706,7 @@ cy_en_syspm_status_t Cy_SysPm_CpuEnterDeepSleep(cy_en_syspm_waitfor_t waitFor) */ if (retVal == CY_SYSPM_SUCCESS) { - /* Call the registered callback functions with the + /* Call the registered callback functions with the * CY_SYSPM_BEFORE_TRANSITION parameter */ interruptState = Cy_SysLib_EnterCriticalSection(); @@ -702,7 +716,8 @@ cy_en_syspm_status_t Cy_SysPm_CpuEnterDeepSleep(cy_en_syspm_waitfor_t waitFor) } /* Preparation for the System Deep Sleep mode */ - + +#if ((CY_CPU_CORTEX_M0P) || (!defined(CY_DEVICE_SECURE))) /* Acquire the IPC to prevent changing of the shared resources at the same time */ while (0U == _FLD2VAL(IPC_STRUCT_ACQUIRE_SUCCESS, REG_IPC_STRUCT_ACQUIRE(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)))) { @@ -748,10 +763,17 @@ cy_en_syspm_status_t Cy_SysPm_CpuEnterDeepSleep(cy_en_syspm_waitfor_t waitFor) /* Release the IPC */ REG_IPC_STRUCT_RELEASE(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = 0U; - + /* Read the release value to make sure it is set */ (void) REG_IPC_STRUCT_RELEASE(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)); +#endif /* ((CY_CPU_CORTEX_M0P) || (!defined(CY_DEVICE_SECURE))) */ + + #if ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) + /* Trigger PRA access to CM0 core to allow CM0 to store configuration */ + CY_PRA_FUNCTION_CALL_VOID_VOID(CY_PRA_MSG_TYPE_SECURE_ONLY, CY_PRA_PM_FUNC_CM4_DP_FLAG_SET); + #endif /* ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) */ + /* Different device families and revisions have a different Deep Sleep entries */ if (Cy_SysLib_GetDevice() == CY_SYSLIB_DEVICE_PSOC6ABLE2) { @@ -760,7 +782,7 @@ cy_en_syspm_status_t Cy_SysPm_CpuEnterDeepSleep(cy_en_syspm_waitfor_t waitFor) } else { - + #if (CY_CPU_CORTEX_M0P) /* Check if there is a pending syscall */ if (Cy_IPC_Drv_IsLockAcquired(Cy_IPC_Drv_GetIpcBaseAddress(CY_IPC_CHAN_SYSCALL)) != false) @@ -772,7 +794,7 @@ cy_en_syspm_status_t Cy_SysPm_CpuEnterDeepSleep(cy_en_syspm_waitfor_t waitFor) #endif /* (CY_CPU_CORTEX_M0P) */ { #if (CY_CPU_CORTEX_M4) - /* Repeat the WFI/WFE instruction if a wake up was not intended. + /* Repeat the WFI/WFE instruction if a wake up was not intended. * Cypress ID #272909 */ do @@ -793,10 +815,13 @@ cy_en_syspm_status_t Cy_SysPm_CpuEnterDeepSleep(cy_en_syspm_waitfor_t waitFor) #if (CY_CPU_CORTEX_M4) } while (_FLD2VAL(CPUSS_CM4_PWR_CTL_PWR_MODE, CPUSS_CM4_PWR_CTL) == CM4_PWR_STS_RETAINED); + #if defined(CY_DEVICE_SECURE) + CY_PRA_CM0_WAKEUP(); + #endif /* (CY_DEVICE_SECURE) */ #endif /* (CY_CPU_CORTEX_M4) */ } } - + /* Acquire the IPC to prevent changing of the shared resources at the same time */ while (0U == _FLD2VAL(IPC_STRUCT_ACQUIRE_SUCCESS, REG_IPC_STRUCT_ACQUIRE(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)))) { @@ -805,6 +830,8 @@ cy_en_syspm_status_t Cy_SysPm_CpuEnterDeepSleep(cy_en_syspm_waitfor_t waitFor) ddftStructData = REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)); + /* Removed for the security devices as this part is done by CM0 only */ + #if !((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) if (0U != (ddftStructData & OTHER_CORE_DP_MASK)) { cy_stc_syspm_backup_regs_t *ptrRegs; @@ -814,6 +841,8 @@ cy_en_syspm_status_t Cy_SysPm_CpuEnterDeepSleep(cy_en_syspm_waitfor_t waitFor) /* Restore saved registers */ Cy_SysPm_RestoreRegisters(ptrRegs); } + #endif /* !((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) */ + ddftStructData &= ~CUR_CORE_DP_MASK; /* Update pointer to the latest saved structure */ @@ -824,32 +853,32 @@ cy_en_syspm_status_t Cy_SysPm_CpuEnterDeepSleep(cy_en_syspm_waitfor_t waitFor) Cy_SysLib_ExitCriticalSection(interruptState); } - + if (retVal == CY_SYSPM_SUCCESS) { - /* Call the registered callback functions with the CY_SYSPM_AFTER_TRANSITION + /* Call the registered callback functions with the CY_SYSPM_AFTER_TRANSITION * parameter */ if (pmCallbackRoot[cbDeepSleepRootIdx] != NULL) { (void) Cy_SysPm_ExecuteCallback(CY_SYSPM_DEEPSLEEP, CY_SYSPM_AFTER_TRANSITION); - } + } } - else + else { - /* Execute callback functions with the CY_SYSPM_CHECK_FAIL parameter to - * undo everything done in the callback with the CY_SYSPM_CHECK_READY + /* Execute callback functions with the CY_SYSPM_CHECK_FAIL parameter to + * undo everything done in the callback with the CY_SYSPM_CHECK_READY * parameter */ if (pmCallbackRoot[cbDeepSleepRootIdx] != NULL) { (void) Cy_SysPm_ExecuteCallback(CY_SYSPM_DEEPSLEEP, CY_SYSPM_CHECK_FAIL); } - + /* Rewrite return value to indicate fail */ if (retVal != CY_SYSPM_SYSCALL_PENDING) { - retVal = CY_SYSPM_FAIL; + retVal = CY_SYSPM_FAIL; } } return retVal; @@ -862,70 +891,74 @@ cy_en_syspm_status_t Cy_SysPm_CpuEnterDeepSleep(cy_en_syspm_waitfor_t waitFor) * * Sets the device into system Hibernate mode. * -* Puts the device into the system Hibernate power mode. Prior to entering -* Hibernate mode, all callbacks of the CY_SYSPM_HIBERNATE type are executed. +* Puts the device into the system Hibernate power mode. Prior to entering +* Hibernate mode, all callbacks of the CY_SYSPM_HIBERNATE type are executed. * -* First, callbacks of the CY_SYSPM_HIBERNATE type are called with the -* CY_SYSPM_CHECK_READY parameter. This allows the callback to signal that the -* driver is not ready to enter the system Hibernate power mode. If any of the -* callback return CY_SYSPM_FAIL, the remaining CY_SYSPM_HIBERNATE callbacks are -* skipped. In this case, all of the callbacks that have already been called are -* called again with the CY_SYSPM_CHECK_FAIL parameter. System Hibernate mode is -* not entered and the Cy_SysPm_SystemEnterHibernate() function returns +* First, callbacks of the CY_SYSPM_HIBERNATE type are called with the +* CY_SYSPM_CHECK_READY parameter. This allows the callback to signal that the +* driver is not ready to enter the system Hibernate power mode. If any of the +* callback return CY_SYSPM_FAIL, the remaining CY_SYSPM_HIBERNATE callbacks are +* skipped. In this case, all of the callbacks that have already been called are +* called again with the CY_SYSPM_CHECK_FAIL parameter. System Hibernate mode is +* not entered and the Cy_SysPm_SystemEnterHibernate() function returns * CY_SYSPM_FAIL. * -* If all CY_SYSPM_HIBERNATE callbacks with the CY_SYSPM_CHECK_READY parameter -* return CY_SYSPM_SUCCESS, then all CY_SYSPM_HIBERNATE callbacks with -* CY_SYSPM_CHECK_FAIL calls are skipped and all CY_SYSPM_HIBERNATE callbacks -* with CY_SYSPM_BEFORE_TRANSITION parameter are executed allowing the -* peripherals to prepare for system Hibernate. +* If all CY_SYSPM_HIBERNATE callbacks with the CY_SYSPM_CHECK_READY parameter +* return CY_SYSPM_SUCCESS, then all CY_SYSPM_HIBERNATE callbacks with +* CY_SYSPM_CHECK_FAIL calls are skipped and all CY_SYSPM_HIBERNATE callbacks +* with CY_SYSPM_BEFORE_TRANSITION parameter are executed allowing the +* peripherals to prepare for system Hibernate. * -* The I/O output state is automatically frozen by hardware system and Hibernate -* mode is then entered. In Hibernate mode, all internal supplies are off and no -* internal state is retained. The only exception is resources powered by the -* Vbackup domain continue to operate, if enabled. For multi-CPU devices, there -* is no handshake with the CPUs and the chip will enter Hibernate power +* The I/O output state is automatically frozen by hardware system and Hibernate +* mode is then entered. In Hibernate mode, all internal supplies are off and no +* internal state is retained. The only exception is resources powered by the +* Vbackup domain continue to operate, if enabled. For multi-CPU devices, there +* is no handshake with the CPUs and the chip will enter Hibernate power * mode immediately. * -* \note The last callback that returns CY_SYSPM_FAIL is not executed with the -* CY_SYSPM_CHECK_FAIL parameter because of the FAIL. The callback generating +* \note The last callback that returns CY_SYSPM_FAIL is not executed with the +* CY_SYSPM_CHECK_FAIL parameter because of the FAIL. The callback generating * CY_SYSPM_FAIL is expected to not make any changes that require being undone. * -* The return value from executed callback functions with the +* The return value from executed callback functions with the * CY_SYSPM_CHECK_FAIL, CY_SYSPM_BEFORE_TRANSITION, and CY_SYSPM_AFTER_TRANSITION * modes are ignored. * * Wakeup from system Hibernate is triggered by toggling the wakeup pin(s), WDT -* match, or back-up domain RTC alarm expiration, depending on how the they are +* match, or back-up domain RTC alarm expiration, depending on how the they are * configured. A wakeup causes a normal boot procedure. * To configure the wakeup pin(s), a digital input pin must be configured, and * resistively pulled up or down to the inverse state of the wakeup polarity. To * distinguish a Hibernate mode from a general reset wakeup event, the -* Cy_SysLib_GetResetReason() function can be used. The wakeup pin and low-power -* comparators are active-low by default. The wakeup pin or the LPComparators -* polarity can be changed with the \ref Cy_SysPm_SetHibernateWakeupSource() +* Cy_SysLib_GetResetReason() function can be used. The wakeup pin and low-power +* comparators are active-low by default. The wakeup pin or the LPComparators +* polarity can be changed with the \ref Cy_SysPm_SetHibernateWakeupSource() * function. -* This function call will not return if system Hibernate mode is entered. +* This function call will not return if system Hibernate mode is entered. * The CY_SYSPM_HIBERNATE callbacks with the CY_SYSPM_AFTER_TRANSITION parameter * are never executed. * -* This function freezes the I/O pins implicitly. Entering system Hibernate mode +* This function freezes the I/O pins implicitly. Entering system Hibernate mode * before freezing the I/O pins is not possible. The I/O pins remain frozen after -* waking from Hibernate mode until the firmware unfreezes them with +* waking from Hibernate mode until the firmware unfreezes them with * a \ref Cy_SysPm_IoUnfreeze() function call. * -* Boot firmware should reconfigure the I/O pins as required by the application +* Boot firmware should reconfigure the I/O pins as required by the application * prior unfreezing them. * -* To support control of callback execution order th following method is -* implemented. Callback function with the CY_SYSPM_CHECK_READY and -* CY_SYSPM_BEFORE_TRANSITION parameter are executed in the same order they are -* registered. Callback function with the CY_SYSPM_CHECK_FAIL and -* CY_SYSPM_AFTER_TRANSITION parameter are executed in the reverse order they +* To support control of callback execution order th following method is +* implemented. Callback function with the CY_SYSPM_CHECK_READY and +* CY_SYSPM_BEFORE_TRANSITION parameter are executed in the same order they are +* registered. Callback function with the CY_SYSPM_CHECK_FAIL and +* CY_SYSPM_AFTER_TRANSITION parameter are executed in the reverse order they * are registered. * * \return * Entered status, see \ref cy_en_syspm_status_t. +* For the PSoC 64 devices there are possible situations when function returns +* the PRA error status code. This is because for PSoC 64 devices the function +* uses the PRA driver to change the protected registers. Refer to +* \ref cy_en_pra_status_t for more details. * * \funcusage * \snippet syspm/snippet/main.c snippet_Cy_SysPm_SystemEnterHibernate @@ -935,7 +968,7 @@ cy_en_syspm_status_t Cy_SysPm_SystemEnterHibernate(void) { cy_en_syspm_status_t retVal = CY_SYSPM_SUCCESS; uint32_t cbHibernateRootIdx = (uint32_t) CY_SYSPM_HIBERNATE; - /* Call the registered callback functions with the + /* Call the registered callback functions with the * CY_SYSPM_CHECK_READY parameter */ if (pmCallbackRoot[cbHibernateRootIdx] != NULL) @@ -949,7 +982,7 @@ cy_en_syspm_status_t Cy_SysPm_SystemEnterHibernate(void) */ if(retVal == CY_SYSPM_SUCCESS) { - /* Call registered callback functions with CY_SYSPM_BEFORE_TRANSITION + /* Call registered callback functions with CY_SYSPM_BEFORE_TRANSITION * parameter */ (void) Cy_SysLib_EnterCriticalSection(); @@ -958,6 +991,11 @@ cy_en_syspm_status_t Cy_SysPm_SystemEnterHibernate(void) (void) Cy_SysPm_ExecuteCallback(CY_SYSPM_HIBERNATE, CY_SYSPM_BEFORE_TRANSITION); } + #if ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) + CY_PRA_FUNCTION_CALL_VOID_PARAM(CY_PRA_MSG_TYPE_SECURE_ONLY, + CY_PRA_PM_FUNC_HIBERNATE, + PM_HIBERNATE_ENTER_HIBERNATE); + #else /* Preserve the token that will be retained through a wakeup sequence. * This could be used by Cy_SysLib_GetResetReason() to differentiate * Wakeup from a general reset event. @@ -973,6 +1011,7 @@ cy_en_syspm_status_t Cy_SysPm_SystemEnterHibernate(void) /* Third write cause system to enter Hibernate */ SRSS_PWR_HIBERNATE |= SET_HIBERNATE_MODE; + #endif /* ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) */ /* Read register to make sure it is settled */ (void) SRSS_PWR_HIBERNATE; @@ -980,22 +1019,22 @@ cy_en_syspm_status_t Cy_SysPm_SystemEnterHibernate(void) /* Wait for transition */ __WFI(); - /* The callback function calls with the CY_SYSPM_AFTER_TRANSITION - * parameter in the Hibernate power mode are not applicable as system + /* The callback function calls with the CY_SYSPM_AFTER_TRANSITION + * parameter in the Hibernate power mode are not applicable as system * wake-up was made on system reboot. */ - /* A wakeup from Hibernate is performed by toggling of the wakeup - * pins, or WDT matches, or Backup domain alarm expires. This depends on - * what item is configured in the Hibernate register. After a wakeup - * event, a normal Boot procedure occurs. + /* A wakeup from Hibernate is performed by toggling of the wakeup + * pins, or WDT matches, or Backup domain alarm expires. This depends on + * what item is configured in the Hibernate register. After a wakeup + * event, a normal Boot procedure occurs. * There is no need to exit from the critical section. */ } else { - /* Execute callback functions with the CY_SYSPM_CHECK_FAIL parameter to - * undo everything done in the callback with the CY_SYSPM_CHECK_READY + /* Execute callback functions with the CY_SYSPM_CHECK_FAIL parameter to + * undo everything done in the callback with the CY_SYSPM_CHECK_READY * parameter. The return value should be CY_SYSPM_SUCCESS. */ (void) Cy_SysPm_ExecuteCallback(CY_SYSPM_HIBERNATE, CY_SYSPM_CHECK_FAIL); @@ -1011,63 +1050,67 @@ cy_en_syspm_status_t Cy_SysPm_SystemEnterHibernate(void) * * Sets device into system Low Power mode. * -* Returns the system to the default LP mode by raising the core voltage. +* Returns the system to the default LP mode by raising the core voltage. * In the LP mode, the clock frequencies can be increased to t -he LP mode -* limitations. Refer to the device datasheet for frequency limitations in the +he LP mode +* limitations. Refer to the device datasheet for frequency limitations in the * LP mode. Approximate LP limit values - \ref group_syspm_lp_limitations. * * Prior to entering the system LP mode, all the registered CY_SYSPM_LP callbacks -* with CY_SYSPM_CHECK_READY parameter are called. This allows the driver to -* signal that it is not ready to enter the system LP mode. If any CY_SYSPM_LP +* with CY_SYSPM_CHECK_READY parameter are called. This allows the driver to +* signal that it is not ready to enter the system LP mode. If any CY_SYSPM_LP * callbacks with the CY_SYSPM_CHECK_READY parameter call return CY_SYSPM_FAIL, -* the remaining CY_SYSPM_LP callbacks with the +* the remaining CY_SYSPM_LP callbacks with the * CY_SYSPM_CHECK_READY parameter calls are skipped. * -* After a CY_SYSPM_FAIL, all of the CY_SYSPM_LP callbacks with -* CY_SYSPM_CHECK_FAIL parameter are executed that correspond to the -* CY_SYSPM_LP callbacks with CY_SYSPM_CHECK_READY parameter that occurred up to -* the point of failure. System LP mode is not entered and the +* After a CY_SYSPM_FAIL, all of the CY_SYSPM_LP callbacks with +* CY_SYSPM_CHECK_FAIL parameter are executed that correspond to the +* CY_SYSPM_LP callbacks with CY_SYSPM_CHECK_READY parameter that occurred up to +* the point of failure. System LP mode is not entered and the * Cy_SysPm_SystemEnterLp() function returns CY_SYSPM_FAIL. * -* If all CY_SYSPM_LP callbacks with the CY_SYSPM_CHECK_READY +* If all CY_SYSPM_LP callbacks with the CY_SYSPM_CHECK_READY * parameter return CY_SYSPM_SUCCESS, then all CY_SYSPM_LP callbacks with -* CY_SYSPM_CHECK_FAIL are skipped and all CY_SYSPM_LP callbacks with the -* CY_SYSPM_BEFORE_TRANSITION parameter are executed. This allows the +* CY_SYSPM_CHECK_FAIL are skipped and all CY_SYSPM_LP callbacks with the +* CY_SYSPM_BEFORE_TRANSITION parameter are executed. This allows the * peripherals to prepare for LP mode. The system LP mode is then entered. * -* After entering the system LP mode, all of the registered -* CY_SYSPM_LP callbacks with the CY_SYSPM_AFTER_TRANSITION parameter -* are executed to complete preparing the peripherals for low power operation. -* The Cy_SysPm_SystemEnterLp() function returns CY_SYSPM_SUCCESS. -* No CY_SYSPM_LP callbacks with the CY_SYSPM_BEFORE_TRANSITION or +* After entering the system LP mode, all of the registered +* CY_SYSPM_LP callbacks with the CY_SYSPM_AFTER_TRANSITION parameter +* are executed to complete preparing the peripherals for low power operation. +* The Cy_SysPm_SystemEnterLp() function returns CY_SYSPM_SUCCESS. +* No CY_SYSPM_LP callbacks with the CY_SYSPM_BEFORE_TRANSITION or * CY_SYSPM_AFTER_TRANSITION parameter are executed if the system LP mode is not * entered. * -* \note The last callback that returns CY_SYSPM_FAIL is not executed with the -* CY_SYSPM_CHECK_FAIL parameter because of the FAIL. The callback generating +* \note The last callback that returns CY_SYSPM_FAIL is not executed with the +* CY_SYSPM_CHECK_FAIL parameter because of the FAIL. The callback generating * CY_SYSPM_FAIL is expected to not make any changes that require being undone. * -* The return value from executed callback functions with the +* The return value from executed callback functions with the * CY_SYSPM_CHECK_FAIL, CY_SYSPM_BEFORE_TRANSITION, and CY_SYSPM_AFTER_TRANSITION * modes are ignored. * -* To support control of callback execution order th following method is -* implemented. Callback function with the CY_SYSPM_CHECK_READY and -* CY_SYSPM_BEFORE_TRANSITION parameter are executed in the same order they are -* registered. Callback function with the CY_SYSPM_CHECK_FAIL and -* CY_SYSPM_AFTER_TRANSITION parameter are executed in the reverse order they +* To support control of callback execution order th following method is +* implemented. Callback function with the CY_SYSPM_CHECK_READY and +* CY_SYSPM_BEFORE_TRANSITION parameter are executed in the same order they are +* registered. Callback function with the CY_SYSPM_CHECK_FAIL and +* CY_SYSPM_AFTER_TRANSITION parameter are executed in the reverse order they * are registered. * * \return * - CY_SYSPM_SUCCESS - Entered the system LP mode or the device is already in LP mode. -* - CY_SYSPM_INVALID_STATE - The system LP mode was not set. The system LP mode -* was not set because the protection context value is higher than zero -* (PC > 0) or the device revision does not support modifying registers +* - CY_SYSPM_INVALID_STATE - The system LP mode was not set. The system LP mode +* was not set because the protection context value is higher than zero +* (PC > 0) or the device revision does not support modifying registers * (to enter LP mode) via syscall. -* - CY_SYSPM_CANCELED - Operation was canceled. Call the function again until +* - CY_SYSPM_CANCELED - Operation was canceled. Call the function again until * the function returns CY_SYSPM_SUCCESS. * - CY_SYSPM_FAIL - The system LP mode is not entered. +* For the PSoC 64 devices there are possible situations when function returns +* the PRA error status code. This is because for PSoC 64 devices the function +* uses the PRA driver to change the protected registers. Refer to +* \ref cy_en_pra_status_t for more details. * * \funcusage * \snippet syspm/snippet/main.c snippet_Cy_SysPm_SystemEnterLp @@ -1079,7 +1122,7 @@ cy_en_syspm_status_t Cy_SysPm_SystemEnterLp(void) uint32_t cbLpRootIdx = (uint32_t) CY_SYSPM_LP; cy_en_syspm_status_t retVal = CY_SYSPM_SUCCESS; - /* Call the registered callback functions with the + /* Call the registered callback functions with the * CY_SYSPM_CHECK_READY parameter */ if (pmCallbackRoot[cbLpRootIdx] != NULL) @@ -1088,13 +1131,13 @@ cy_en_syspm_status_t Cy_SysPm_SystemEnterLp(void) } /* The system can switch into LP only when - * all executed registered callback functions with the + * all executed registered callback functions with the * CY_SYSPM_CHECK_READY parameter return CY_SYSPM_SUCCESS */ if (retVal == CY_SYSPM_SUCCESS) { - - /* Call the registered callback functions with the + + /* Call the registered callback functions with the * CY_SYSPM_BEFORE_TRANSITION parameter */ interruptState = Cy_SysLib_EnterCriticalSection(); @@ -1123,7 +1166,7 @@ cy_en_syspm_status_t Cy_SysPm_SystemEnterLp(void) Cy_SysLib_ExitCriticalSection(interruptState); - /* Call the registered callback functions with the + /* Call the registered callback functions with the * CY_SYSPM_AFTER_TRANSITION parameter */ if (pmCallbackRoot[cbLpRootIdx] != NULL) @@ -1133,8 +1176,8 @@ cy_en_syspm_status_t Cy_SysPm_SystemEnterLp(void) } else { - /* Execute callback functions with the CY_SYSPM_CHECK_FAIL parameter to - * undo everything done in the callback with the CY_SYSPM_CHECK_READY + /* Execute callback functions with the CY_SYSPM_CHECK_FAIL parameter to + * undo everything done in the callback with the CY_SYSPM_CHECK_READY * parameter */ (void) Cy_SysPm_ExecuteCallback(CY_SYSPM_LP, CY_SYSPM_CHECK_FAIL); @@ -1151,65 +1194,69 @@ cy_en_syspm_status_t Cy_SysPm_SystemEnterLp(void) * * Sets device into system Ultra Low Power mode. * -* System ULP mode is similar to system LP mode. The difference is that the +* System ULP mode is similar to system LP mode. The difference is that the * system is put under \ref group_syspm_ulp_limitations. * -* Before entering system ULP mode, the user must configure the system so -* the maximum clock frequencies are less than the ULP mode specifications -* presented in the device datasheet. Refer to the device datasheet for -* the maximum clock limitations in the ULP mode with reduced core supply +* Before entering system ULP mode, the user must configure the system so +* the maximum clock frequencies are less than the ULP mode specifications +* presented in the device datasheet. Refer to the device datasheet for +* the maximum clock limitations in the ULP mode with reduced core supply * regulator voltages. * -* Prior to entering system ULP mode, all the registered CY_SYSPM_ULP callbacks -* with CY_SYSPM_CHECK_READY parameter are called. This allows the driver to -* signal if it is not ready to enter system ULP mode. If any CY_SYSPM_ULP -* callback with the CY_SYSPM_CHECK_READY parameter call returns CY_SYSPM_FAIL, -* the remaining CY_SYSPM_ULP callbacks with the CY_SYSPM_CHECK_READY parameter +* Prior to entering system ULP mode, all the registered CY_SYSPM_ULP callbacks +* with CY_SYSPM_CHECK_READY parameter are called. This allows the driver to +* signal if it is not ready to enter system ULP mode. If any CY_SYSPM_ULP +* callback with the CY_SYSPM_CHECK_READY parameter call returns CY_SYSPM_FAIL, +* the remaining CY_SYSPM_ULP callbacks with the CY_SYSPM_CHECK_READY parameter * are skipped. * * After a CY_SYSPM_FAIL, all of the CY_SYSPM_ULP callbacks with the -* CY_SYSPM_CHECK_FAIL parameter are executed that correspond to the -* CY_SYSPM_ULP callback with CY_SYSPM_CHECK_READY parameter that occurred up to -* the point of failure. System ULP mode is not entered +* CY_SYSPM_CHECK_FAIL parameter are executed that correspond to the +* CY_SYSPM_ULP callback with CY_SYSPM_CHECK_READY parameter that occurred up to +* the point of failure. System ULP mode is not entered * and the Cy_SysPm_SystemEnterUlp() function returns CY_SYSPM_FAIL. * -* If all CY_SYSPM_ULP callbacks with the CY_SYSPM_CHECK_READY -* parameter return CY_SYSPM_SUCCESS, then all CY_SYSPM_ULP -* callbacks with CY_SYSPM_CHECK_FAIL calls are skipped and all CY_SYSPM_ULP -* callbacks with the CY_SYSPM_BEFORE_TRANSITION parameter are executed. This +* If all CY_SYSPM_ULP callbacks with the CY_SYSPM_CHECK_READY +* parameter return CY_SYSPM_SUCCESS, then all CY_SYSPM_ULP +* callbacks with CY_SYSPM_CHECK_FAIL calls are skipped and all CY_SYSPM_ULP +* callbacks with the CY_SYSPM_BEFORE_TRANSITION parameter are executed. This * allows preparation for ULP. The system ULP mode is then entered. * -* After entering system ULP, all of the registered CY_SYSPM_ULP callbacks with -* the CY_SYSPM_AFTER_TRANSITION parameter are executed to complete preparing the -* peripherals for ULP operation. The Cy_SysPm_SystemEnterUlp() function -* returns CY_SYSPM_SUCCESS. No CY_SYSPM_ULP callbacks with the -* CY_SYSPM_BEFORE_TRANSITION or CY_SYSPM_AFTER_TRANSITION parameter are +* After entering system ULP, all of the registered CY_SYSPM_ULP callbacks with +* the CY_SYSPM_AFTER_TRANSITION parameter are executed to complete preparing the +* peripherals for ULP operation. The Cy_SysPm_SystemEnterUlp() function +* returns CY_SYSPM_SUCCESS. No CY_SYSPM_ULP callbacks with the +* CY_SYSPM_BEFORE_TRANSITION or CY_SYSPM_AFTER_TRANSITION parameter are * executed, if ULP mode is not entered. * -* \note The last callback that returns CY_SYSPM_FAIL is not executed with the -* CY_SYSPM_CHECK_FAIL parameter because of the FAIL. The callback generating +* \note The last callback that returns CY_SYSPM_FAIL is not executed with the +* CY_SYSPM_CHECK_FAIL parameter because of the FAIL. The callback generating * CY_SYSPM_FAIL is expected to not make any changes that require being undone. * -* The return value from executed callback functions with the +* The return value from executed callback functions with the * CY_SYSPM_CHECK_FAIL, CY_SYSPM_BEFORE_TRANSITION, and CY_SYSPM_AFTER_TRANSITION * modes are ignored. * -* To support control of callback execution order th following method is -* implemented. Callback function with the CY_SYSPM_CHECK_READY and -* CY_SYSPM_BEFORE_TRANSITION parameter are executed in the same order they are -* registered. Callback function with the CY_SYSPM_CHECK_FAIL and -* CY_SYSPM_AFTER_TRANSITION parameter are executed in the reverse order they +* To support control of callback execution order th following method is +* implemented. Callback function with the CY_SYSPM_CHECK_READY and +* CY_SYSPM_BEFORE_TRANSITION parameter are executed in the same order they are +* registered. Callback function with the CY_SYSPM_CHECK_FAIL and +* CY_SYSPM_AFTER_TRANSITION parameter are executed in the reverse order they * are registered. * * \return * - CY_SYSPM_SUCCESS - Entered the system ULP mode or the device is already in ULP mode. -* - CY_SYSPM_INVALID_STATE - System ULP mode was not set. The ULP mode was not -* set because the protection context value is higher than zero (PC > 0) or the -* device revision does not support modifying registers (to enter system +* - CY_SYSPM_INVALID_STATE - System ULP mode was not set. The ULP mode was not +* set because the protection context value is higher than zero (PC > 0) or the +* device revision does not support modifying registers (to enter system * ULP mode) via syscall. -* - CY_SYSPM_CANCELED - Operation was canceled. Call the function again until +* - CY_SYSPM_CANCELED - Operation was canceled. Call the function again until * the function returns CY_SYSPM_SUCCESS. * - CY_SYSPM_FAIL - The system ULP mode is not entered. +* For the PSoC 64 devices there are possible situations when function returns +* the PRA error status code. This is because for PSoC 64 devices the function +* uses the PRA driver to change the protected registers. Refer to +* \ref cy_en_pra_status_t for more details. * * \funcusage * \snippet syspm/snippet/main.c snippet_Cy_SysPm_SystemEnterUlp @@ -1221,7 +1268,7 @@ cy_en_syspm_status_t Cy_SysPm_SystemEnterUlp(void) cy_en_syspm_status_t retVal = CY_SYSPM_SUCCESS; uint32_t cbUlpRootIdx = (uint32_t) CY_SYSPM_ULP; - /* Call the registered callback functions with the + /* Call the registered callback functions with the * CY_SYSPM_CHECK_READY parameter */ if (pmCallbackRoot[cbUlpRootIdx] != NULL) @@ -1230,12 +1277,12 @@ cy_en_syspm_status_t Cy_SysPm_SystemEnterUlp(void) } /* The system can switch into the ULP only when - * all executed registered callback functions with the + * all executed registered callback functions with the * CY_SYSPM_CHECK_READY parameter return CY_SYSPM_SUCCESS */ if (retVal == CY_SYSPM_SUCCESS) { - /* Call the registered callback functions with the + /* Call the registered callback functions with the * CY_SYSPM_BEFORE_TRANSITION parameter */ interruptState = Cy_SysLib_EnterCriticalSection(); @@ -1264,7 +1311,7 @@ cy_en_syspm_status_t Cy_SysPm_SystemEnterUlp(void) Cy_SysLib_ExitCriticalSection(interruptState); - /* Call the registered callback functions with the + /* Call the registered callback functions with the * CY_SYSPM_AFTER_TRANSITION parameter */ if (pmCallbackRoot[cbUlpRootIdx] != NULL) @@ -1274,8 +1321,8 @@ cy_en_syspm_status_t Cy_SysPm_SystemEnterUlp(void) } else { - /* Execute callback functions with the CY_SYSPM_CHECK_FAIL parameter to - * undo everything done in the callback with the CY_SYSPM_CHECK_READY + /* Execute callback functions with the CY_SYSPM_CHECK_FAIL parameter to + * undo everything done in the callback with the CY_SYSPM_CHECK_READY * parameter */ (void) Cy_SysPm_ExecuteCallback(CY_SYSPM_ULP, CY_SYSPM_CHECK_FAIL); @@ -1290,16 +1337,16 @@ cy_en_syspm_status_t Cy_SysPm_SystemEnterUlp(void) * Function Name: Cy_SysPm_SystemSetMinRegulatorCurrent ****************************************************************************//** * -* Sets the system into minimum core regulator current mode. This mode limits +* Sets the system into minimum core regulator current mode. This mode limits * maximum current available for the system core logic. * -* Minimum regulator current mode modifies operation of the system in LP or ULP -* modes to further reduce current consumption. If the system current is below +* Minimum regulator current mode modifies operation of the system in LP or ULP +* modes to further reduce current consumption. If the system current is below * datasheet current limits for the active core voltage regulator (LDO or Buck), -* this mode may be entered. The user is responsible for ensuring the +* this mode may be entered. The user is responsible for ensuring the * regulator current limit is met in their application. * -* When in minimum regulator current mode, the following system resources are +* When in minimum regulator current mode, the following system resources are * also set to their LP mode: * - Linear regulator (If LDO is active regulator) * - POR/BOD circuit @@ -1307,19 +1354,23 @@ cy_en_syspm_status_t Cy_SysPm_SystemEnterUlp(void) * - Reference buffer circuit * - Current reference circuit * -* The LDO and Buck current limits must be met prior to entering this -* mode. If these are not met, the device may brown out, resulting in an -* exception or reset. These changes also reduce power supply rejection of +* The LDO and Buck current limits must be met prior to entering this +* mode. If these are not met, the device may brown out, resulting in an +* exception or reset. These changes also reduce power supply rejection of * the affected system resources, which can result in increased noise or response * time. These effects must be evaluated in each application. * * \return * See \ref cy_en_syspm_status_t. * - CY_SYSPM_SUCCESS - Minimum regulator current mode was set -* - CY_SYSPM_CANCELED - The power circuits were not ready to enter into +* - CY_SYSPM_CANCELED - The power circuits were not ready to enter into * minimum current mode. You should call the function again. +* For the PSoC 64 devices there are possible situations when function returns +* the PRA error status code. This is because for PSoC 64 devices the function +* uses the PRA driver to change the protected registers. Refer to +* \ref cy_en_pra_status_t for more details. * -* Refer to device datasheet for maximum current value in regulator minimum +* Refer to device datasheet for maximum current value in regulator minimum * current mode. * * \funcusage @@ -1330,7 +1381,11 @@ cy_en_syspm_status_t Cy_SysPm_SystemSetMinRegulatorCurrent(void) { cy_en_syspm_status_t retVal = CY_SYSPM_CANCELED; - /* Check are the power circuits are ready to enter into regulator minimum +#if ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) + retVal = (cy_en_syspm_status_t)CY_PRA_FUNCTION_CALL_RETURN_VOID(CY_PRA_MSG_TYPE_FUNC_POLICY, + CY_PRA_PM_FUNC_SET_MIN_CURRENT); +#else + /* Check are the power circuits are ready to enter into regulator minimum * current mode */ if (0U != _FLD2VAL(SRSS_PWR_CTL_LPM_READY, SRSS_PWR_CTL)) @@ -1353,10 +1408,11 @@ cy_en_syspm_status_t Cy_SysPm_SystemSetMinRegulatorCurrent(void) /* Disable active reference */ SRSS_PWR_CTL |= SRSS_PWR_CTL_ACT_REF_DIS_Msk; - + retVal = CY_SYSPM_SUCCESS; } - +#endif /* ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) */ + return retVal; } @@ -1367,12 +1423,12 @@ cy_en_syspm_status_t Cy_SysPm_SystemSetMinRegulatorCurrent(void) * * Sets the system to normal regulator current mode. * -* Normal regulator current mode modifies operation of the system in LP or ULP -* modes to provide maximum core current consumption. If the LDO core regulator -* is in use, the normal mode output current limits may be used. If the buck +* Normal regulator current mode modifies operation of the system in LP or ULP +* modes to provide maximum core current consumption. If the LDO core regulator +* is in use, the normal mode output current limits may be used. If the buck * regulator is in use, its reduced current output limits still apply. * -* When in normal regulator current mode, the following system resources are set +* When in normal regulator current mode, the following system resources are set * to their normal mode: * - Linear regulator (If LDO is active regulator) * - POR/BOD circuit @@ -1382,8 +1438,12 @@ cy_en_syspm_status_t Cy_SysPm_SystemSetMinRegulatorCurrent(void) * * \return * - CY_SYSPM_SUCCESS - Normal regulator current mode was set -* - CY_SYSPM_TIMEOUT - The timeout occurred because device was not +* - CY_SYSPM_TIMEOUT - The timeout occurred because device was not * ready to enter into the normal regulator current mode +* For the PSoC 64 devices there are possible situations when function returns +* the PRA error status code. This is because for PSoC 64 devices the function +* uses the PRA driver to change the protected registers. Refer to +* \ref cy_en_pra_status_t for more details. * * \funcusage * \snippet syspm/snippet/main.c snippet_Cy_SysPm_SystemSetNormalRegulatorCurrent @@ -1391,10 +1451,15 @@ cy_en_syspm_status_t Cy_SysPm_SystemSetMinRegulatorCurrent(void) *******************************************************************************/ cy_en_syspm_status_t Cy_SysPm_SystemSetNormalRegulatorCurrent(void) { - uint32_t timeOut = WAIT_DELAY_TRYES; cy_en_syspm_status_t retVal = CY_SYSPM_TIMEOUT; - /* Configure the regulator normal current mode for the POR/BOD circuits +#if ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) + retVal = (cy_en_syspm_status_t)CY_PRA_FUNCTION_CALL_RETURN_VOID(CY_PRA_MSG_TYPE_FUNC_POLICY, + CY_PRA_PM_FUNC_SET_NORMAL_CURRENT); +#else + uint32_t timeOut = WAIT_DELAY_TRYES; + + /* Configure the regulator normal current mode for the POR/BOD circuits * and for the Bandgap Voltage and Current References */ if (Cy_SysPm_LdoIsEnabled()) @@ -1418,12 +1483,13 @@ cy_en_syspm_status_t Cy_SysPm_SystemSetNormalRegulatorCurrent(void) { /* Disable the low-power for Bandgap reference circuit */ SRSS_PWR_CTL &= (uint32_t) ~SRSS_PWR_CTL_BGREF_LPMODE_Msk; - + /* Delay to finally set the normal current mode */ Cy_SysLib_DelayUs(SET_NORMAL_CURRENT_MODE_DELAY_US); - + retVal= CY_SYSPM_SUCCESS; } +#endif /* ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) */ return retVal; } @@ -1436,22 +1502,22 @@ cy_en_syspm_status_t Cy_SysPm_SystemSetNormalRegulatorCurrent(void) * This function configures the sleep-on-exit feature of the CPU. * * This API sets the SLEEPONEXIT bit of the SCR register. -* -* When the sleep-on-exit feature is enabled (the SLEEPONEXIT bit is set), +* +* When the sleep-on-exit feature is enabled (the SLEEPONEXIT bit is set), * the CPU wakes up to service the interrupt and then immediately goes -* back to sleep. Because of this, the unstacking process is not carried out, so -* this feature is useful for interrupt driven application and helps to +* back to sleep. Because of this, the unstacking process is not carried out, so +* this feature is useful for interrupt driven application and helps to * reduce unnecessary stack push and pop operations. -* The CPU does not go to sleep if the interrupt handler returns to -* another interrupt handler (nested interrupt). -* You can use this feature in applications that require the CPU to only run +* The CPU does not go to sleep if the interrupt handler returns to +* another interrupt handler (nested interrupt). +* You can use this feature in applications that require the CPU to only run * when an interrupt occurs. * -* When the sleep-on-exit feature is disabled (the SLEEPONEXIT bit is cleared), +* When the sleep-on-exit feature is disabled (the SLEEPONEXIT bit is cleared), * the CPU returns back to the main thread after servicing the interrupt * without going back to sleep. * -* Refer to the Arm documentation about the sleep-on-exit feature and +* Refer to the Arm documentation about the sleep-on-exit feature and * SLEEPONEXIT in the SCR register. * * \param enable @@ -1481,32 +1547,32 @@ void Cy_SysPm_CpuSleepOnExit(bool enable) * Function Name: Cy_SysPm_SetHibernateWakeupSource ****************************************************************************//** * -* This function configures sources to wake up the device from the system +* This function configures sources to wake up the device from the system * Hibernate power mode. Sources can be wakeup pins, LPComparators, Watchdog (WDT) -* interrupt, or a Real-Time clock (RTC) alarm (interrupt). Wakeup from system +* interrupt, or a Real-Time clock (RTC) alarm (interrupt). Wakeup from system * Hibernate always results in a device reset and normal boot process. * * Wakeup pins: * * A wakeup is supported by up to two pins with programmable polarity. These pins -* are typically connected to the GPIO pins or on-chip peripherals under some +* are typically connected to the GPIO pins or on-chip peripherals under some * conditions. See device datasheet for specific pin connections. * Setting the wakeup pin to this level will cause a wakeup from system Hibernate * mode. The wakeup pins are active-low by default. * * LPComparators: * -* A wakeup is supported by up to two LPComps with programmable polarity. +* A wakeup is supported by up to two LPComps with programmable polarity. * Setting the LPComp to this level will cause a wakeup from system Hibernate * mode. The wakeup LPComps are active-low by default. * -* \note The low-power comparators should be configured and enabled before +* \note The low-power comparators should be configured and enabled before * switching to system Hibernate mode. Refer to the LPComp * driver description for more detail. * * Watchdog Timer: -* -* \note The WDT should be configured and enabled before entering to system +* +* \note The WDT should be configured and enabled before entering to system * Hibernate mode. * * A wakeup is performed by a WDT interrupt. @@ -1516,13 +1582,13 @@ void Cy_SysPm_CpuSleepOnExit(bool enable) * A wakeup is performed by the RTC alarm. * Refer to the Real-Time Clock (RTC) driver description for more detail. * -* For information about wakeup sources and their assignment in specific +* For information about wakeup sources and their assignment in specific * devices, refer to the appropriate device TRM. * -* \param wakeupSource -* The source to be configured as a wakeup source from +* \param wakeupSource +* The source to be configured as a wakeup source from * the system Hibernate power mode, see \ref cy_en_syspm_hibernate_wakeup_source_t. -* The input parameter values can be ORed. For example, if you want to enable +* The input parameter values can be ORed. For example, if you want to enable * LPComp0 (active high) and WDT, call this function: * Cy_SysPm_SetHibernateWakeupSource(CY_SYSPM_HIBERNATE_LPCOMP0_HIGH | CY_SYSPM_HIBERNATE_WDT). * @@ -1537,9 +1603,9 @@ void Cy_SysPm_CpuSleepOnExit(bool enable) void Cy_SysPm_SetHibernateWakeupSource(uint32_t wakeupSource) { CY_ASSERT_L3(CY_SYSPM_IS_WAKE_UP_SOURCE_VALID(wakeupSource)); - + uint32_t polarityMask = 0U; - + if (0U != _FLD2VAL(SRSS_PWR_HIBERNATE_POLARITY_HIBPIN, wakeupSource)) { /* Reconfigure the wakeup pins and LPComp polarity based on the input */ @@ -1547,24 +1613,28 @@ void Cy_SysPm_SetHibernateWakeupSource(uint32_t wakeupSource) { polarityMask |= CY_SYSPM_HIB_WAKEUP_LPCOMP0_POLARITY_HIGH_MASK; } - + if (0U != (wakeupSource & CY_SYSPM_HIB_WAKEUP_LPCOMP1_MASK)) { polarityMask |= CY_SYSPM_HIB_WAKEUP_LPCOMP1_POLARITY_HIGH_MASK; } - + if (0U != (wakeupSource & CY_SYSPM_HIB_WAKEUP_PIN0_MASK)) { polarityMask |= CY_SYSPM_HIB_WAKEUP_PIN0_POLARITY_HIGH_MASK; } - + if (0U != (wakeupSource & CY_SYSPM_HIB_WAKEUP_PIN1_MASK)) { polarityMask |= CY_SYSPM_HIB_WAKEUP_PIN1_POLARITY_HIGH_MASK; } } +#if ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) + CY_PRA_REG32_SET(CY_PRA_INDX_SRSS_PWR_HIBERNATE, (SRSS_PWR_HIBERNATE & (uint32_t) ~polarityMask) | wakeupSource); +#else SRSS_PWR_HIBERNATE = (SRSS_PWR_HIBERNATE & (uint32_t) ~polarityMask) | wakeupSource; +#endif /* ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) */ /* Read register to make sure it is settled */ (void) SRSS_PWR_HIBERNATE; @@ -1575,12 +1645,12 @@ void Cy_SysPm_SetHibernateWakeupSource(uint32_t wakeupSource) * Function Name: Cy_SysPm_ClearHibernateWakeupSource ****************************************************************************//** * -* This function disables a wakeup source that was previously configured to +* This function disables a wakeup source that was previously configured to * wake up the device from the system Hibernate mode. * * \param wakeupSource * For the source to be disabled, see \ref cy_en_syspm_hibernate_wakeup_source_t. -* The input parameters values can be ORed. For example, if you want to disable +* The input parameters values can be ORed. For example, if you want to disable * LPComp0 (active high) and WDT call this function: * Cy_SysPm_ClearHibernateWakeupSource(CY_SYSPM_HIBERNATE_LPCOMP0_HIGH | CY_SYSPM_HIBERNATE_WDT). * @@ -1591,7 +1661,7 @@ void Cy_SysPm_SetHibernateWakeupSource(uint32_t wakeupSource) void Cy_SysPm_ClearHibernateWakeupSource(uint32_t wakeupSource) { CY_ASSERT_L3(CY_SYSPM_IS_WAKE_UP_SOURCE_VALID(wakeupSource)); - + uint32_t clearWakeupSourceMask = wakeupSource & (uint32_t) ~SRSS_PWR_HIBERNATE_POLARITY_HIBPIN_Msk; if (0U != _FLD2VAL(SRSS_PWR_HIBERNATE_POLARITY_HIBPIN, wakeupSource)) @@ -1601,24 +1671,28 @@ void Cy_SysPm_ClearHibernateWakeupSource(uint32_t wakeupSource) { clearWakeupSourceMask |= CY_SYSPM_HIB_WAKEUP_LPCOMP0_POLARITY_HIGH_MASK; } - + if ((uint32_t) CY_SYSPM_HIBERNATE_LPCOMP1_HIGH == (wakeupSource & (uint32_t) CY_SYSPM_HIBERNATE_LPCOMP1_HIGH)) { clearWakeupSourceMask |= CY_SYSPM_HIB_WAKEUP_LPCOMP1_POLARITY_HIGH_MASK; } - + if ((uint32_t) CY_SYSPM_HIBERNATE_PIN0_HIGH == (wakeupSource & (uint32_t) CY_SYSPM_HIBERNATE_PIN0_HIGH)) { clearWakeupSourceMask |= CY_SYSPM_HIB_WAKEUP_PIN0_POLARITY_HIGH_MASK; } - + if ((uint32_t) CY_SYSPM_HIBERNATE_PIN1_HIGH == (wakeupSource & (uint32_t) CY_SYSPM_HIBERNATE_PIN1_HIGH)) { clearWakeupSourceMask |= CY_SYSPM_HIB_WAKEUP_PIN1_POLARITY_HIGH_MASK; } } +#if ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) + CY_PRA_REG32_SET(CY_PRA_INDX_SRSS_PWR_HIBERNATE, (SRSS_PWR_HIBERNATE & (uint32_t) ~clearWakeupSourceMask)); +#else SRSS_PWR_HIBERNATE &= (uint32_t) ~clearWakeupSourceMask; +#endif /* ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) */ /* Read register to make sure it is settled */ (void) SRSS_PWR_HIBERNATE; @@ -1629,55 +1703,55 @@ void Cy_SysPm_ClearHibernateWakeupSource(uint32_t wakeupSource) * Function Name: Cy_SysPm_BuckEnable ****************************************************************************//** * -* Switch the core supply regulator to Buck core regulator instead of the LDO +* Switch the core supply regulator to Buck core regulator instead of the LDO * regulator. -* The Buck core regulator provides output voltage(s) using one external +* The Buck core regulator provides output voltage(s) using one external * inductor and can supply Vccd with higher efficiency than the LDO under some * conditions, such as high external supply voltage. * -* Before changing from LDO to Buck, ensure that the circuit board has -* connected Vccbuck1 to Vccd and also populated the -* necessary external components for the Buck regulator, including an +* Before changing from LDO to Buck, ensure that the circuit board has +* connected Vccbuck1 to Vccd and also populated the +* necessary external components for the Buck regulator, including an * inductor and a capacitor for each output. * Refer to the device TRM for more detail. * -* When changing from a higher voltage to a lower voltage -* (from system LP = LDO 1.1 V (nominal) to system ULP = Buck 0.9 V (nominal)), +* When changing from a higher voltage to a lower voltage +* (from system LP = LDO 1.1 V (nominal) to system ULP = Buck 0.9 V (nominal)), * ensure that: * * The device maximum operating frequency for all the Clk_HF paths, peripheral, * and slow clock are under the \ref group_syspm_ulp_limitations. * * The total current consumption is under the \ref group_syspm_ulp_limitations. -* -* * The appropriate wait states values are set for the flash using +* +* * The appropriate wait states values are set for the flash using * the Cy_SysLib_SetWaitStates() function as explained below. * -* Setting wait states values for flash +* Setting wait states values for flash * -* The flash access time when the core output voltage is 0.9 V (nominal) is -* longer than at 1.1 V (nominal). Therefore, the number of the wait states must +* The flash access time when the core output voltage is 0.9 V (nominal) is +* longer than at 1.1 V (nominal). Therefore, the number of the wait states must * be adjusted. Use the Cy_SysLib_SetWaitStates() function to set the appropriate -* wait state values for flash. +* wait state values for flash. * -* To change from a higher voltage (LDO 1.1 V) to a lower voltage (Buck 0.9 V), -* call the Cy_SysLib_SetWaitStates(true, hfClkFreqMz) function before changing +* To change from a higher voltage (LDO 1.1 V) to a lower voltage (Buck 0.9 V), +* call the Cy_SysLib_SetWaitStates(true, hfClkFreqMz) function before changing * the voltage, where hfClkFreqMz is the frequency of HfClk0 in MHz. * -* To change from a lower voltage (LDO 0.9 V (nominal) to a higher voltage -* (Buck 1.1 V (nominal)), call the Cy_SysLib_SetWaitStates(false, -* hfClkFreqMz) function to set the wait states after the voltage change. -* It is optional, but can be done to improve performance. The clock frequency +* To change from a lower voltage (LDO 0.9 V (nominal) to a higher voltage +* (Buck 1.1 V (nominal)), call the Cy_SysLib_SetWaitStates(false, +* hfClkFreqMz) function to set the wait states after the voltage change. +* It is optional, but can be done to improve performance. The clock frequency * may now be increased up to system LP mode limits for the new voltage. -* +* * \note 1. If the final Buck output is set to 0.9 V (nominal) - the system is in * ULP mode and flash allows read-only operations. * \note 2. If the final Buck output is set to 1.1 V (nominal) - the system is in * LP mode flash allows the read and write operations. -* \note 3. The actual device Vccd voltage can be different from the nominal +* \note 3. The actual device Vccd voltage can be different from the nominal * voltage because the actual voltage value depends on conditions * including the load current. * -* \warning There is no safe way to go back to the LDO after the -* Buck regulator supplies a core. The function enabling the BUck regulator +* \warning There is no safe way to go back to the LDO after the +* Buck regulator supplies a core. The function enabling the BUck regulator * switches off the LDO. * * For more detail, refer to the \ref group_syspm_switching_into_ulp and @@ -1688,22 +1762,26 @@ void Cy_SysPm_ClearHibernateWakeupSource(uint32_t wakeupSource) * \param voltage * The desired output 1 regulator voltage (Vccbuck1). * See \ref cy_en_syspm_buck_voltage1_t. -* -* \return -* - CY_SYSPM_SUCCESS - The voltage is set as requested. -* (There is no change if the new voltage is the same as the previous voltage.) -* - CY_SYSPM_INVALID_STATE - The voltage was not set. The voltage cannot be set -* because the protection context value is higher than zero (PC > 0) or the -* device revision does not support modifying registers via syscall. -* - CY_SYSPM_CANCELED - Operation was canceled. Call the function again until -* the function returns CY_SYSPM_SUCCESS. See \ref cy_en_syspm_status_t. * -* \note +* \return +* - CY_SYSPM_SUCCESS - The voltage is set as requested. +* (There is no change if the new voltage is the same as the previous voltage.) +* - CY_SYSPM_INVALID_STATE - The voltage was not set. The voltage cannot be set +* because the protection context value is higher than zero (PC > 0) or the +* device revision does not support modifying registers via syscall. +* - CY_SYSPM_CANCELED - Operation was canceled. Call the function again until +* the function returns CY_SYSPM_SUCCESS. See \ref cy_en_syspm_status_t. +* For the PSoC 64 devices there are possible situations when function returns +* the PRA error status code. This is because for PSoC 64 devices the function +* uses the PRA driver to change the protected registers. Refer to +* \ref cy_en_pra_status_t for more details. +* +* \note * The function is applicable only for devices with a Buck regulator. * * Function uses a critical section to prevent interrupting the regulators * switch. -* +* * \funcusage * \snippet syspm/snippet/main.c snippet_Cy_SysPm_BuckEnable * @@ -1714,6 +1792,12 @@ cy_en_syspm_status_t Cy_SysPm_BuckEnable(cy_en_syspm_buck_voltage1_t voltage) cy_en_syspm_status_t retVal = CY_SYSPM_INVALID_STATE; +#if ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) + retVal = (cy_en_syspm_status_t)CY_PRA_FUNCTION_CALL_RETURN_PARAM(CY_PRA_MSG_TYPE_FUNC_POLICY, + CY_PRA_PM_FUNC_BUCK_ENABLE, + voltage); +#else + /* Enable the Buck regulator only if it was not enabled previously. * If the LDO is disabled, the device is sourced by the Buck regulator */ @@ -1737,7 +1821,7 @@ cy_en_syspm_status_t Cy_SysPm_BuckEnable(cy_en_syspm_buck_voltage1_t voltage) if (CY_SYSPM_SUCCESS == retVal) { /* Increase LDO output voltage to 0.95 V nominal */ - SRSS_PWR_TRIM_PWRSYS_CTL = _CLR_SET_FLD32U((SRSS_PWR_TRIM_PWRSYS_CTL), + SRSS_PWR_TRIM_PWRSYS_CTL = _CLR_SET_FLD32U((SRSS_PWR_TRIM_PWRSYS_CTL), SRSS_PWR_TRIM_PWRSYS_CTL_ACT_REG_TRIM, LDO_OUT_VOLTAGE_0_95V); } } @@ -1757,7 +1841,7 @@ cy_en_syspm_status_t Cy_SysPm_BuckEnable(cy_en_syspm_buck_voltage1_t voltage) if (CY_SYSPM_SUCCESS == retVal) { /* Set the LDO 1.15 V as final Buck output is 1.1 V */ - SRSS_PWR_TRIM_PWRSYS_CTL = _CLR_SET_FLD32U((SRSS_PWR_TRIM_PWRSYS_CTL), + SRSS_PWR_TRIM_PWRSYS_CTL = _CLR_SET_FLD32U((SRSS_PWR_TRIM_PWRSYS_CTL), SRSS_PWR_TRIM_PWRSYS_CTL_ACT_REG_TRIM, LDO_OUT_VOLTAGE_1_15V); } } @@ -1774,7 +1858,7 @@ cy_en_syspm_status_t Cy_SysPm_BuckEnable(cy_en_syspm_buck_voltage1_t voltage) _VAL2FLD(SRSS_PWR_CTL_NWELL_REG_DIS, 1U)); /* Configure the Buck regulator */ - SRSS_PWR_BUCK_CTL = + SRSS_PWR_BUCK_CTL = _CLR_SET_FLD32U((SRSS_PWR_BUCK_CTL), SRSS_PWR_BUCK_CTL_BUCK_OUT1_SEL, (uint32_t) voltage); SRSS_PWR_BUCK_CTL |= _VAL2FLD(SRSS_PWR_BUCK_CTL_BUCK_EN, 1U); @@ -1786,6 +1870,11 @@ cy_en_syspm_status_t Cy_SysPm_BuckEnable(cy_en_syspm_buck_voltage1_t voltage) /* Disable the LDO, because Vbuckout1 and LDO are shorted */ SRSS_PWR_CTL |= _VAL2FLD(SRSS_PWR_CTL_LINREG_DIS, 1U); + + /* Remove additional wakeup delay from Deep Sleep for LDO. + * Cypress ID #290172 + */ + SRSS_PWR_TRIM_WAKE_CTL = 0UL; } Cy_SysLib_ExitCriticalSection(interruptState); @@ -1794,7 +1883,7 @@ cy_en_syspm_status_t Cy_SysPm_BuckEnable(cy_en_syspm_buck_voltage1_t voltage) { /* The Buck is already enabled, so just update the Buck voltage */ cy_en_syspm_buck_voltage1_t curBuckVoltage = Cy_SysPm_BuckGetVoltage1(); - + if (voltage != curBuckVoltage) { retVal = Cy_SysPm_BuckSetVoltage1(voltage); @@ -1804,6 +1893,7 @@ cy_en_syspm_status_t Cy_SysPm_BuckEnable(cy_en_syspm_buck_voltage1_t voltage) retVal = CY_SYSPM_SUCCESS; } } +#endif /* ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) */ return retVal; } @@ -1813,45 +1903,45 @@ cy_en_syspm_status_t Cy_SysPm_BuckEnable(cy_en_syspm_buck_voltage1_t voltage) * Function Name: Cy_SysPm_BuckSetVoltage1 ****************************************************************************//** * -* Sets the output 1 voltage for the Buck regulator that can supply the device +* Sets the output 1 voltage for the Buck regulator that can supply the device * core. This output can supply the device core instead of the LDO regulator. * -* When changing from a higher voltage 1.1 V (nominal) to a lower voltage 0.9 V +* When changing from a higher voltage 1.1 V (nominal) to a lower voltage 0.9 V * (nominal), ensure that: * * The device maximum operating frequency for all the Clk_HF paths, peripheral, * and slow clock are under the \ref group_syspm_ulp_limitations. * * The total current consumption is under the \ref group_syspm_ulp_limitations. -* * The appropriate wait states values are set for the flash using +* * The appropriate wait states values are set for the flash using * the Cy_SysLib_SetWaitStates() function as explained below. * * Setting wait states values for flash * -* The flash access time when the core output voltage is 0.9 V (nominal) is -* longer than at 1.1 V (nominal). Therefore, the number of the wait states must +* The flash access time when the core output voltage is 0.9 V (nominal) is +* longer than at 1.1 V (nominal). Therefore, the number of the wait states must * be adjusted. Use the Cy_SysLib_SetWaitStates() function to set the appropriate -* wait state values for flash. +* wait state values for flash. * -* To change from a higher voltage to a lower voltage 0.9 V (nominal), -* call the Cy_SysLib_SetWaitStates(true, hfClkFreqMz) function before changing +* To change from a higher voltage to a lower voltage 0.9 V (nominal), +* call the Cy_SysLib_SetWaitStates(true, hfClkFreqMz) function before changing * the voltage, where hfClkFreqMz is the frequency of HfClk0 in MHz. * -* To change from a lower voltage to a higher voltage 1.1 V (nominal), call -* the Cy_SysLib_SetWaitStates(false, hfClkFreqMz) function to set the -* wait states. It is optional, but can be done to improve the performance. -* The clock frequency may now be increased up to +* To change from a lower voltage to a higher voltage 1.1 V (nominal), call +* the Cy_SysLib_SetWaitStates(false, hfClkFreqMz) function to set the +* wait states. It is optional, but can be done to improve the performance. +* The clock frequency may now be increased up to * \ref group_syspm_lp_limitations for a new voltage. -* -* \note 1. The output is set to 0.9 V (nominal) - the system is in ULP mode +* +* \note 1. The output is set to 0.9 V (nominal) - the system is in ULP mode * flash allows read-only operations. -* \note 2. The output is set to 1.1 V (nominal) - the system is in LP mode and +* \note 2. The output is set to 1.1 V (nominal) - the system is in LP mode and * flash allows the read and write operations. -* \note 3. The actual device Vccd voltage can be different from the nominal +* \note 3. The actual device Vccd voltage can be different from the nominal * voltage because the actual voltage value depends on the conditions * including the load current. * * For more detail, refer to the \ref group_syspm_switching_into_ulp and * \ref group_syspm_switching_into_lp sections. -* Refer to the \ref group_syslib driver for more detail about setting the +* Refer to the \ref group_syslib driver for more detail about setting the * wait states. * * \param voltage @@ -1860,15 +1950,23 @@ cy_en_syspm_status_t Cy_SysPm_BuckEnable(cy_en_syspm_buck_voltage1_t voltage) * * \return * - CY_SYSPM_SUCCESS - The voltage is set. -* - CY_SYSPM_INVALID_STATE - The voltage was not set. The voltage cannot be set -* because the protection context value is higher than zero (PC > 0) or the +* - CY_SYSPM_INVALID_STATE - The voltage was not set. The voltage cannot be set +* because the protection context value is higher than zero (PC > 0) or the * device revision does not support modifying registers via syscall. -* - CY_SYSPM_CANCELED - Operation was canceled. Call the function again until +* - CY_SYSPM_CANCELED - Operation was canceled. Call the function again until * the function returns CY_SYSPM_SUCCESS. See \ref cy_en_syspm_status_t. +* For the PSoC 64 devices there are possible situations when function returns +* the PRA error status code. This is because for PSoC 64 devices the function +* uses the PRA driver to change the protected registers. Refer to +* \ref cy_en_pra_status_t for more details. * * \funcusage * \snippet syspm/snippet/main.c snippet_Cy_SysPm_VoltageRegulator * +* \sideeffect +* For PSoC 64 series devices Cy_SysPm_BuckSetVoltage1() has the same functional +* behavior as \ref Cy_SysPm_BuckEnable() function. +* *******************************************************************************/ cy_en_syspm_status_t Cy_SysPm_BuckSetVoltage1(cy_en_syspm_buck_voltage1_t voltage) { @@ -1876,7 +1974,13 @@ cy_en_syspm_status_t Cy_SysPm_BuckSetVoltage1(cy_en_syspm_buck_voltage1_t voltag cy_en_syspm_status_t retVal = CY_SYSPM_INVALID_STATE; - /* Change the voltage only if protection context is set to zero (PC = 0) +#if ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) + retVal = (cy_en_syspm_status_t)CY_PRA_FUNCTION_CALL_RETURN_PARAM(CY_PRA_MSG_TYPE_FUNC_POLICY, + CY_PRA_PM_FUNC_BUCK_ENABLE, + voltage); +#else + + /* Change the voltage only if protection context is set to zero (PC = 0) * or the device revision supports modifying registers via syscall */ if (IsVoltageChangePossible()) @@ -1888,7 +1992,7 @@ cy_en_syspm_status_t Cy_SysPm_BuckSetVoltage1(cy_en_syspm_buck_voltage1_t voltag { /* Set bit of the flash voltage control register before ULP mode is set */ retVal = Cy_SysPm_WriteVoltageBitForFlash(CY_SYSPM_FLASH_VOLTAGE_BIT_ULP); - + if (CY_SYSPM_SUCCESS == retVal) { /* Update read-write margin value for the ULP mode */ @@ -1898,12 +2002,12 @@ cy_en_syspm_status_t Cy_SysPm_BuckSetVoltage1(cy_en_syspm_buck_voltage1_t voltag else { /* Increase Buck output voltage to 0.95 V nominal */ - SRSS_PWR_BUCK_CTL = + SRSS_PWR_BUCK_CTL = _CLR_SET_FLD32U((SRSS_PWR_BUCK_CTL), SRSS_PWR_BUCK_CTL_BUCK_OUT1_SEL, BUCK_OUT1_VOLTAGE_0_95V); - + /* Wait until regulator is stable on higher intermediate voltage */ Cy_SysLib_DelayUs(BUCK_OUT1_0_9V_TO_0_95V_DELAY_US); - + /* Update write assist value for the LP mode */ SetWriteAssistTrimLp(); @@ -1913,12 +2017,12 @@ cy_en_syspm_status_t Cy_SysPm_BuckSetVoltage1(cy_en_syspm_buck_voltage1_t voltag /* Proceed only if previous settings were done successfully */ if (CY_SYSPM_SUCCESS == retVal) { - /* The system may continue operating while the voltage on Vccd - * discharges to the new voltage. The time it takes to reach the + /* The system may continue operating while the voltage on Vccd + * discharges to the new voltage. The time it takes to reach the * new voltage depends on the conditions, including the load current * on Vccd and the external capacitor size. */ - SRSS_PWR_BUCK_CTL = + SRSS_PWR_BUCK_CTL = _CLR_SET_FLD32U((SRSS_PWR_BUCK_CTL), SRSS_PWR_BUCK_CTL_BUCK_OUT1_SEL, (uint32_t) voltage); if (CY_SYSPM_BUCK_OUT1_VOLTAGE_0_9V == voltage) @@ -1936,7 +2040,7 @@ cy_en_syspm_status_t Cy_SysPm_BuckSetVoltage1(cy_en_syspm_buck_voltage1_t voltag /* Update read-write margin value for the LP mode */ SetReadMarginTrimLp(); - /* Clear bit of the flash voltage control register after + /* Clear bit of the flash voltage control register after * the LP mode is set */ retVal = Cy_SysPm_WriteVoltageBitForFlash(CY_SYSPM_FLASH_VOLTAGE_BIT_LP); @@ -1945,6 +2049,8 @@ cy_en_syspm_status_t Cy_SysPm_BuckSetVoltage1(cy_en_syspm_buck_voltage1_t voltag Cy_SysLib_ExitCriticalSection(interruptState); } +#endif /* ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) */ + return retVal; } @@ -1995,23 +2101,23 @@ bool Cy_SysPm_BuckIsOutputEnabled(cy_en_syspm_buck_out_t output) * Function Name: Cy_SysPm_BuckEnableVoltage2 ****************************************************************************//** * -* Enable the output 2 voltage (Vbuckrf) of the SIMO Buck regulator. -* The output 2 voltage (Vbuckrf) of the Buck regulator is typically used to +* Enable the output 2 voltage (Vbuckrf) of the SIMO Buck regulator. +* The output 2 voltage (Vbuckrf) of the Buck regulator is typically used to * supply the BLE radio. -* This function does following actions, when the Buck regulator does not -* supply the core: +* This function does following actions, when the Buck regulator does not +* supply the core: * * Enables the Buck regulator * * Enables the output 2, but do not enables the output 1. * * \note The function does not affect Buck output 1 that typically supplies core. * -* \warning The function does not select the Buck output 2 voltage and +* \warning The function does not select the Buck output 2 voltage and * does not set/clear the HW-controlled bit for Buck output 2. Call -* Cy_SysPm_BuckSetVoltage2() or Cy_SysPm_BuckSetVoltage2HwControl() to +* Cy_SysPm_BuckSetVoltage2() or Cy_SysPm_BuckSetVoltage2HwControl() to * configure the Buck output 2. * * The function works only on devices with the SIMO Buck regulator. -* Refer to the device datasheet for information on whether the device contains +* Refer to the device datasheet for information on whether the device contains * the SIMO Buck. * * \funcusage @@ -2020,6 +2126,10 @@ bool Cy_SysPm_BuckIsOutputEnabled(cy_en_syspm_buck_out_t output) *******************************************************************************/ void Cy_SysPm_BuckEnableVoltage2(void) { +#if ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) + CY_PRA_FUNCTION_CALL_VOID_VOID(CY_PRA_MSG_TYPE_SECURE_ONLY, + CY_PRA_PM_FUNC_BUCK_ENABLE_VOLTAGE2); +#else /* Do nothing if device does not have the second Buck output (SIMO) */ if (0U != cy_device->sysPmSimoPresent) { @@ -2035,6 +2145,7 @@ void Cy_SysPm_BuckEnableVoltage2(void) /* Wait until the output is stable */ Cy_SysLib_DelayUs(BUCK_OUT2_INIT_DELAY_US); } +#endif /* ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) */ } @@ -2043,9 +2154,9 @@ void Cy_SysPm_BuckEnableVoltage2(void) ****************************************************************************//** * * This function sets output voltage 2 (Vbuckrf) of the SIMO Buck regulator. -* +* * \param voltage -* The voltage of the Buck regulator output 2 (Vbuckrf). +* The voltage of the Buck regulator output 2 (Vbuckrf). * See \ref cy_en_syspm_buck_voltage2_t. * * \param waitToSettle @@ -2056,11 +2167,11 @@ void Cy_SysPm_BuckEnableVoltage2(void) * while changing from a lower voltage to a higher voltage. * * \note The 200 us delay is required only when changing from a -* lower voltage to a higher voltage. When changing from a higher voltage to a +* lower voltage to a higher voltage. When changing from a higher voltage to a * lower one, the delay is not required. * * The function works only on devices with the SIMO Buck regulator. -* Refer to the device datasheet for information on whether the device contains +* Refer to the device datasheet for information on whether the device contains * SIMO Buck. * * \funcusage @@ -2069,19 +2180,28 @@ void Cy_SysPm_BuckEnableVoltage2(void) *******************************************************************************/ void Cy_SysPm_BuckSetVoltage2(cy_en_syspm_buck_voltage2_t voltage, bool waitToSettle) { +#if ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) + cy_stc_pra_voltage2_t voltageSettings; + voltageSettings.praVoltage = voltage; + voltageSettings.praWaitToSettle = waitToSettle; + + CY_PRA_FUNCTION_CALL_VOID_PARAM(CY_PRA_MSG_TYPE_SECURE_ONLY, + CY_PRA_PM_FUNC_BUCK_SET_VOLTAGE2, + &voltageSettings); +#else /* Do nothing if device does not have the second Buck output (SIMO) */ if (0U != cy_device->sysPmSimoPresent) { uint32_t curVoltage; CY_ASSERT_L3(CY_SYSPM_IS_BUCK_VOLTAGE2_VALID(voltage)); - + /* Get the current voltage */ curVoltage = (uint32_t) Cy_SysPm_BuckGetVoltage2(); if ((uint32_t) voltage != curVoltage) { - SRSS_PWR_BUCK_CTL2 = + SRSS_PWR_BUCK_CTL2 = _CLR_SET_FLD32U((SRSS_PWR_BUCK_CTL2), SRSS_PWR_BUCK_CTL2_BUCK_OUT2_SEL, (uint32_t) voltage); /* Delay stabilizing at the new voltage is required only @@ -2093,6 +2213,7 @@ void Cy_SysPm_BuckSetVoltage2(cy_en_syspm_buck_voltage2_t voltage, bool waitToSe } } } +#endif /* ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) */ } @@ -2100,38 +2221,38 @@ void Cy_SysPm_BuckSetVoltage2(cy_en_syspm_buck_voltage2_t voltage, bool waitToSe * Function Name: Cy_SysPm_LdoSetVoltage ****************************************************************************//** * -* Set output voltage on the core LDO regulator. +* Set output voltage on the core LDO regulator. * -* When changing from a higher voltage to a lower voltage as when the device +* When changing from a higher voltage to a lower voltage as when the device * enters system ULP mode, ensure that: * * The device maximum operating frequency for all the Clk_HF paths, peripheral, * and slow clock are under the \ref group_syspm_ulp_limitations. * * The total current consumption is under the \ref group_syspm_ulp_limitations. -* * The appropriate wait states values are set for the flash using +* * The appropriate wait states values are set for the flash using * The Cy_SysLib_SetWaitStates() function as explained below. * * Setting wait states values for flash * -* The flash access time when the core voltage is 0.9 V (nominal) is -* longer than at 1.1 V (nominal). Therefore, the number of the wait states must +* The flash access time when the core voltage is 0.9 V (nominal) is +* longer than at 1.1 V (nominal). Therefore, the number of the wait states must * be adjusted. Use the Cy_SysLib_SetWaitStates() function to set the appropriate -* wait state values for flash. +* wait state values for flash. * -* To change from a higher voltage to a lower voltage 0.9 V (nominal), -* call the Cy_SysLib_SetWaitStates(true, hfClkFreqMz) function before changing +* To change from a higher voltage to a lower voltage 0.9 V (nominal), +* call the Cy_SysLib_SetWaitStates(true, hfClkFreqMz) function before changing * the voltage, where hfClkFreqMz is the frequency of HfClk0 in MHz. * -* To change from a lower voltage to a higher voltage 1.1 V (nominal), calling -* the Cy_SysLib_SetWaitStates(false, hfClkFreqMz) function to set the -* wait states is optional, but can be done to improve performance. -* The clock frequency may now be increased up to +* To change from a lower voltage to a higher voltage 1.1 V (nominal), calling +* the Cy_SysLib_SetWaitStates(false, hfClkFreqMz) function to set the +* wait states is optional, but can be done to improve performance. +* The clock frequency may now be increased up to * \ref group_syspm_lp_limitations. -* -* \note 1. The output is set to 0.9 V (nominal) - the system is in ULP mode and +* +* \note 1. The output is set to 0.9 V (nominal) - the system is in ULP mode and * flash works for read-only operation. -* \note 2. The output is set to 1.1 V (nominal) - the system is in LP mode +* \note 2. The output is set to 1.1 V (nominal) - the system is in LP mode * and flash works for read and write operations. -* \note 3. The actual device Vccd voltage can be different from the nominal +* \note 3. The actual device Vccd voltage can be different from the nominal * voltage because the actual voltage value depends on conditions * including the load current. * @@ -2145,12 +2266,16 @@ void Cy_SysPm_BuckSetVoltage2(cy_en_syspm_buck_voltage2_t voltage, bool waitToSe * See \ref cy_en_syspm_ldo_voltage_t voltage * * \return -* - CY_SYSPM_SUCCESS - The voltage is set. -* - CY_SYSPM_INVALID_STATE - The voltage was not set. The voltage cannot be set -* because the protection context value is higher than zero (PC > 0) or the +* - CY_SYSPM_SUCCESS - The voltage is set. +* - CY_SYSPM_INVALID_STATE - The voltage was not set. The voltage cannot be set +* because the protection context value is higher than zero (PC > 0) or the * device revision does not support modifying registers via syscall. -* - CY_SYSPM_CANCELED - Operation was canceled. Call the function again until +* - CY_SYSPM_CANCELED - Operation was canceled. Call the function again until * the function returns CY_SYSPM_SUCCESS. See \ref cy_en_syspm_status_t. +* For the PSoC 64 devices there are possible situations when function returns +* the PRA error status code. This is because for PSoC 64 devices the function +* uses the PRA driver to change the protected registers. Refer to +* \ref cy_en_pra_status_t for more details. * * \funcusage * \snippet syspm/snippet/main.c snippet_Cy_SysPm_VoltageRegulator @@ -2162,23 +2287,28 @@ cy_en_syspm_status_t Cy_SysPm_LdoSetVoltage(cy_en_syspm_ldo_voltage_t voltage) cy_en_syspm_status_t retVal = CY_SYSPM_INVALID_STATE; - /* Change the voltage only if protection context is set to zero (PC = 0), +#if ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) + retVal = (cy_en_syspm_status_t)CY_PRA_FUNCTION_CALL_RETURN_PARAM(CY_PRA_MSG_TYPE_FUNC_POLICY, + CY_PRA_PM_FUNC_LDO_SET_VOLTAGE, + voltage); +#else + /* Change the voltage only if protection context is set to zero (PC = 0), * or the device revision supports modifying registers via syscall */ if (IsVoltageChangePossible()) { uint32_t interruptState; uint32_t trimVoltage; - + interruptState = Cy_SysLib_EnterCriticalSection(); if (CY_SYSPM_LDO_VOLTAGE_0_9V == voltage) { - /* Remove additional wakeup delay from Deep Sleep + /* Remove additional wakeup delay from Deep Sleep * for 1.1 V LDO. Cypress ID #290172 */ SRSS_PWR_TRIM_WAKE_CTL = 0UL; - + trimVoltage = SFLASH_LDO_0P9V_TRIM; /* Set bit of the flash voltage control register before the ULP is set */ @@ -2192,19 +2322,19 @@ cy_en_syspm_status_t Cy_SysPm_LdoSetVoltage(cy_en_syspm_ldo_voltage_t voltage) } else { - /* Configure additional wakeup delay from Deep Sleep + /* Configure additional wakeup delay from Deep Sleep * for 1.1 V LDO. Cypress ID #290172 */ SRSS_PWR_TRIM_WAKE_CTL = SFLASH_PWR_TRIM_WAKE_CTL; - + trimVoltage = SFLASH_LDO_1P1V_TRIM; - SRSS_PWR_TRIM_PWRSYS_CTL = + SRSS_PWR_TRIM_PWRSYS_CTL = _CLR_SET_FLD32U((SRSS_PWR_TRIM_PWRSYS_CTL), SRSS_PWR_TRIM_PWRSYS_CTL_ACT_REG_TRIM, LDO_OUT_VOLTAGE_0_95V); /* A delay for the supply to stabilize at the new higher voltage */ Cy_SysLib_DelayUs(LDO_0_9V_TO_0_95V_DELAY_US); - + /* Update write assist value for the LP mode */ SetWriteAssistTrimLp(); @@ -2213,12 +2343,12 @@ cy_en_syspm_status_t Cy_SysPm_LdoSetVoltage(cy_en_syspm_ldo_voltage_t voltage) if (CY_SYSPM_SUCCESS == retVal) { - /* The system may continue operating while the voltage on Vccd - * discharges to the new voltage. The time it takes to reach the + /* The system may continue operating while the voltage on Vccd + * discharges to the new voltage. The time it takes to reach the * new voltage depends on the conditions, including the load current * on Vccd and the external capacitor size. */ - SRSS_PWR_TRIM_PWRSYS_CTL = + SRSS_PWR_TRIM_PWRSYS_CTL = _CLR_SET_FLD32U((SRSS_PWR_TRIM_PWRSYS_CTL), SRSS_PWR_TRIM_PWRSYS_CTL_ACT_REG_TRIM, trimVoltage); if (CY_SYSPM_LDO_VOLTAGE_0_9V == voltage) @@ -2230,11 +2360,11 @@ cy_en_syspm_status_t Cy_SysPm_LdoSetVoltage(cy_en_syspm_ldo_voltage_t voltage) { /* A delay for the supply to stabilize at the new intermediate voltage */ Cy_SysLib_DelayUs(LDO_0_95V_TO_1_1V_DELAY_US); - + /* Update read-write margin value for the LP mode */ SetReadMarginTrimLp(); - - /* Clear bit of the flash voltage control register after + + /* Clear bit of the flash voltage control register after * the LP mode is set */ retVal = Cy_SysPm_WriteVoltageBitForFlash(CY_SYSPM_FLASH_VOLTAGE_BIT_LP); @@ -2243,6 +2373,8 @@ cy_en_syspm_status_t Cy_SysPm_LdoSetVoltage(cy_en_syspm_ldo_voltage_t voltage) Cy_SysLib_ExitCriticalSection(interruptState); } +#endif /* ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) */ + return retVal; } @@ -2251,32 +2383,40 @@ cy_en_syspm_status_t Cy_SysPm_LdoSetVoltage(cy_en_syspm_ldo_voltage_t voltage) * Function Name: Cy_SysPm_LdoSetMode ****************************************************************************//** * -* Configures the core LDO regulator operating mode to one of three modes. -* Disabled - turns off the LDO regulator and should be selected only after the -* Buck regulator is operating. Normal mode configures the LDO for operation at +* Configures the core LDO regulator operating mode to one of three modes. +* Disabled - turns off the LDO regulator and should be selected only after the +* Buck regulator is operating. Normal mode configures the LDO for operation at * the maximum output current limit. Minimal current mode optimizes the LDO at a -* reduced output current limit. Specific device current limits can be found in +* reduced output current limit. Specific device current limits can be found in * the device datasheet. * * \param mode * The desired LDO regulator operating mode. -* See \ref cy_en_syspm_ldo_mode_t voltage +* See \ref cy_en_syspm_ldo_mode_t mode * * \return * - CY_SYSPM_SUCCESS - Requested regulator current mode was set -* - CY_SYSPM_CANCELED - The power circuits were not ready to enter into +* - CY_SYSPM_CANCELED - The power circuits were not ready to enter into * minimum current mode. You should try to call the function again -* - CY_SYSPM_TIMEOUT - Timeout occurred because of active reference was not +* - CY_SYSPM_TIMEOUT - Timeout occurred because of active reference was not * ready to enter into the normal regulator current mode * - CY_SYSPM_FAIL - incorrect mode value was passed +* For the PSoC 64 devices there are possible situations when function returns +* the PRA error status code. This is because for PSoC 64 devices the function +* uses the PRA driver to change the protected registers. Refer to +* \ref cy_en_pra_status_t for more details. +* +* \sideeffect +* For PSoC 64 series devices CY_SYSPM_LDO_MODE_DISABLED mode is not supported. +* Use \ref Cy_SysPm_BuckEnable() instead. * *******************************************************************************/ cy_en_syspm_status_t Cy_SysPm_LdoSetMode(cy_en_syspm_ldo_mode_t mode) { CY_ASSERT_L3(CY_SYSPM_IS_LDO_MODE_VALID(mode)); - + cy_en_syspm_status_t retVal = CY_SYSPM_CANCELED; - + switch (mode) { case CY_SYSPM_LDO_MODE_NORMAL: @@ -2293,6 +2433,7 @@ cy_en_syspm_status_t Cy_SysPm_LdoSetMode(cy_en_syspm_ldo_mode_t mode) case CY_SYSPM_LDO_MODE_DISABLED: { + #if !((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) /* Disable the LDO, Deep Sleep, nWell, and Retention regulators */ SRSS_PWR_CTL |= (_VAL2FLD(SRSS_PWR_CTL_DPSLP_REG_DIS, 1U) | _VAL2FLD(SRSS_PWR_CTL_RET_REG_DIS, 1U) | @@ -2300,9 +2441,10 @@ cy_en_syspm_status_t Cy_SysPm_LdoSetMode(cy_en_syspm_ldo_mode_t mode) _VAL2FLD(SRSS_PWR_CTL_LINREG_DIS, 1U)); retVal = CY_SYSPM_SUCCESS; + #endif /* !(CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) */ } break; - + default: retVal = CY_SYSPM_FAIL; break; @@ -2339,7 +2481,7 @@ cy_en_syspm_ldo_mode_t Cy_SysPm_LdoGetMode(void) { retVal = CY_SYSPM_LDO_MODE_NORMAL; } - + return retVal; } @@ -2352,14 +2494,14 @@ cy_en_syspm_ldo_mode_t Cy_SysPm_LdoGetMode(void) * * A callback is a function called after an event in the driver or * middleware module has occurred. The handler callback API will be executed if -* the specific event occurs. SysPm callbacks are called when changing power +* the specific event occurs. SysPm callbacks are called when changing power * modes. See \ref cy_stc_syspm_callback_t. * -* \note The registered callbacks are executed in two orders, based on callback -* mode \ref cy_en_syspm_callback_mode_t. For modes CY_SYSPM_CHECK_READY and -* CY_SYSPM_BEFORE_TRANSITION, the order is same order as callbacks were +* \note The registered callbacks are executed in two orders, based on callback +* mode \ref cy_en_syspm_callback_mode_t. For modes CY_SYSPM_CHECK_READY and +* CY_SYSPM_BEFORE_TRANSITION, the order is same order as callbacks were * registered. -* For modes CY_SYSPM_AFTER_TRANSITION and CY_SYSPM_CHECK_FAIL, the order is +* For modes CY_SYSPM_AFTER_TRANSITION and CY_SYSPM_CHECK_FAIL, the order is * reverse as the order callbacks were registered. * * \param handler @@ -2371,7 +2513,7 @@ cy_en_syspm_ldo_mode_t Cy_SysPm_LdoGetMode(void) * - False if a callback was not registered. * * \note Do not modify the registered structure in run-time. -* \warning After being registered, the SysPm callback structures must be +* \warning After being registered, the SysPm callback structures must be * allocated during power mode transition. * * \funcusage @@ -2456,7 +2598,7 @@ bool Cy_SysPm_RegisterCallback(cy_stc_syspm_callback_t* handler) * * This function unregisters a callback. * -* The registered callback can be unregistered and the function returns true. +* The registered callback can be unregistered and the function returns true. * Otherwise, false is returned. * * \param handler The item that should be unregistered. @@ -2478,7 +2620,7 @@ bool Cy_SysPm_UnregisterCallback(cy_stc_syspm_callback_t const *handler) { uint32_t callbackRootIdx = (uint32_t) handler->type; cy_stc_syspm_callback_t* curCallback = pmCallbackRoot[callbackRootIdx]; - + /* Search requested callback item in the linked list */ while (curCallback != NULL) { @@ -2488,11 +2630,11 @@ bool Cy_SysPm_UnregisterCallback(cy_stc_syspm_callback_t const *handler) retVal = true; break; } - + /* Go to next callback item in the linked list */ curCallback = curCallback->nextItm; } - + if (retVal) { /* Requested callback is first in the list */ @@ -2514,7 +2656,7 @@ bool Cy_SysPm_UnregisterCallback(cy_stc_syspm_callback_t const *handler) { /* Update links of related to unregistered callback items */ curCallback->prevItm->nextItm = curCallback->nextItm; - + if (curCallback->nextItm != NULL) { curCallback->nextItm->prevItm = curCallback->prevItm; @@ -2533,24 +2675,24 @@ bool Cy_SysPm_UnregisterCallback(cy_stc_syspm_callback_t const *handler) * * The function executes all registered callbacks with provided type and mode. * \note This low-level function is being used by \ref Cy_SysPm_CpuEnterSleep, -* \ref Cy_SysPm_CpuEnterDeepSleep, \ref Cy_SysPm_SystemEnterHibernate, -* \ref Cy_SysPm_SystemEnterUlp and \ref Cy_SysPm_SystemEnterLp API functions. +* \ref Cy_SysPm_CpuEnterDeepSleep, \ref Cy_SysPm_SystemEnterHibernate, +* \ref Cy_SysPm_SystemEnterUlp and \ref Cy_SysPm_SystemEnterLp API functions. * However, it might be also useful as an independent API function in some custom * applications. * -* \note The registered callbacks will be executed in order based on -* \ref cy_en_syspm_callback_type_t value. There are two possible callback +* \note The registered callbacks will be executed in order based on +* \ref cy_en_syspm_callback_type_t value. There are two possible callback * execution orders: -* * From first registered to last registered. This order applies to +* * From first registered to last registered. This order applies to * callbacks with mode CY_SYSPM_CHECK_READY and CY_SYSPM_BEFORE_TRANSITION. -* * Backward flow execution: -* - From last registered to the first registered. This order applies +* * Backward flow execution: +* - From last registered to the first registered. This order applies * to callbacks with mode CY_SYSPM_AFTER_TRANSITION. -* - From last called to the first registered callback. This order applies -* to callbacks with mode CY_SYSPM_CHECK_FAIL. Note that, the last called -* callback function that generated the CY_SYSPM_CHECK_FAIL is skipped when -* mode CY_SYSPM_CHECK_FAIL. This is because the callback that returns -* CY_SYSPM_FAIL already knows that it failed and will not take any action +* - From last called to the first registered callback. This order applies +* to callbacks with mode CY_SYSPM_CHECK_FAIL. Note that, the last called +* callback function that generated the CY_SYSPM_CHECK_FAIL is skipped when +* mode CY_SYSPM_CHECK_FAIL. This is because the callback that returns +* CY_SYSPM_FAIL already knows that it failed and will not take any action * that requires correction. * * If no callbacks are registered, returns CY_SYSPM_SUCCESS. @@ -2562,7 +2704,7 @@ bool Cy_SysPm_UnregisterCallback(cy_stc_syspm_callback_t const *handler) * The callback mode. See \ref cy_en_syspm_callback_mode_t. * * \return -* - CY_SYSPM_SUCCESS if callback successfully completed or nor callbacks +* - CY_SYSPM_SUCCESS if callback successfully completed or nor callbacks * registered. * - CY_SYSPM_FAIL one of the executed callback(s) returned fail. * @@ -2574,16 +2716,16 @@ cy_en_syspm_status_t Cy_SysPm_ExecuteCallback(cy_en_syspm_callback_type_t type, { CY_ASSERT_L3(CY_SYSPM_IS_CALLBACK_TYPE_VALID(type)); CY_ASSERT_L3(CY_SYSPM_IS_CALLBACK_MODE_VALID(mode)); - + static cy_stc_syspm_callback_t* lastExecutedCallback = NULL; cy_en_syspm_status_t retVal = CY_SYSPM_SUCCESS; cy_stc_syspm_callback_t* curCallback = pmCallbackRoot[(uint32_t) type]; cy_stc_syspm_callback_params_t curParams; - + if ((mode == CY_SYSPM_BEFORE_TRANSITION) || (mode == CY_SYSPM_CHECK_READY)) { /* Execute registered callbacks with order from first registered to the - * last registered. Stop executing if CY_SYSPM_FAIL was returned in + * last registered. Stop executing if CY_SYSPM_FAIL was returned in * CY_SYSPM_CHECK_READY mode */ while ((curCallback != NULL) && ((retVal != CY_SYSPM_FAIL) || (mode != CY_SYSPM_CHECK_READY))) @@ -2596,10 +2738,10 @@ cy_en_syspm_status_t Cy_SysPm_ExecuteCallback(cy_en_syspm_callback_type_t type, curParams.context = curCallback->callbackParams->context; retVal = curCallback->callback(&curParams, mode); - - /* Update callback pointer with value of executed callback. - * Such update is required to execute further callbacks in - * backward order after exit from LP mode or to undo + + /* Update callback pointer with value of executed callback. + * Such update is required to execute further callbacks in + * backward order after exit from LP mode or to undo * configuration after callback returned fail: from last called * to first registered. */ @@ -2617,7 +2759,7 @@ cy_en_syspm_status_t Cy_SysPm_ExecuteCallback(cy_en_syspm_callback_type_t type, */ if(retVal == CY_SYSPM_FAIL) { - failedCallback[(uint32_t) type] = lastExecutedCallback; + failedCallback[(uint32_t) type] = lastExecutedCallback; } else { @@ -2627,10 +2769,10 @@ cy_en_syspm_status_t Cy_SysPm_ExecuteCallback(cy_en_syspm_callback_type_t type, } else { - /* Execute registered callbacks with order from lastCallback or last - * executed to the first registered callback. Such a flow is required if - * a previous callback function returned CY_SYSPM_FAIL or a previous - * callback mode was CY_SYSPM_BEFORE_TRANSITION. Such an order is + /* Execute registered callbacks with order from lastCallback or last + * executed to the first registered callback. Such a flow is required if + * a previous callback function returned CY_SYSPM_FAIL or a previous + * callback mode was CY_SYSPM_BEFORE_TRANSITION. Such an order is * required to undo configurations in correct backward order. */ if (mode != CY_SYSPM_CHECK_FAIL) @@ -2642,7 +2784,7 @@ cy_en_syspm_status_t Cy_SysPm_ExecuteCallback(cy_en_syspm_callback_type_t type, } else { - /* Skip last executed callback that returns CY_SYSPM_FAIL, as this + /* Skip last executed callback that returns CY_SYSPM_FAIL, as this * callback already knows that it failed. */ curCallback = lastExecutedCallback; @@ -2676,7 +2818,7 @@ cy_en_syspm_status_t Cy_SysPm_ExecuteCallback(cy_en_syspm_callback_type_t type, /******************************************************************************* * Function Name: Cy_SysPm_GetFailedCallback ****************************************************************************//** -* +* * Reads the result of the callback execution after the power mode functions * execution. * @@ -2708,19 +2850,19 @@ cy_stc_syspm_callback_t* Cy_SysPm_GetFailedCallback(cy_en_syspm_callback_type_t * Function Name: Cy_SysPm_IoUnfreeze ****************************************************************************//** * -* This function unfreezes the I/O cells that are automatically frozen when +* This function unfreezes the I/O cells that are automatically frozen when * Hibernate is entered with the call to \ref Cy_SysPm_SystemEnterHibernate(). * * I/O cells remain frozen after a wakeup from Hibernate mode until the * firmware unfreezes them by calling this function. * * If the firmware must retain the data value on the pin, then the -* value must be read and re-written to the pin's port data register before -* calling this function. Furthermore, the drive mode must be re-programmed -* before the pins are unfrozen. If this is not done, the pin will change to +* value must be read and re-written to the pin's port data register before +* calling this function. Furthermore, the drive mode must be re-programmed +* before the pins are unfrozen. If this is not done, the pin will change to * the default state the moment the freeze is removed. * -* Note that I/O cell configuration can be changed while frozen. The new +* Note that I/O cell configuration can be changed while frozen. The new * configuration becomes effective only after the pins are unfrozen. * * \funcusage @@ -2732,16 +2874,20 @@ void Cy_SysPm_IoUnfreeze(void) uint32_t interruptState; interruptState = Cy_SysLib_EnterCriticalSection(); +#if ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) + CY_PRA_FUNCTION_CALL_VOID_PARAM(CY_PRA_MSG_TYPE_SECURE_ONLY, CY_PRA_PM_FUNC_HIBERNATE, PM_HIBERNATE_IO_UNFREEZE); +#else /* Preserve the last reset reason and wakeup polarity. Then, unfreeze I/O: * write PWR_HIBERNATE.FREEZE=0, .UNLOCK=0x3A, .HIBERANTE=0 */ SRSS_PWR_HIBERNATE = (SRSS_PWR_HIBERNATE & HIBERNATE_RETAIN_STATUS_MASK) | HIBERNATE_UNLOCK_VAL; - /* Lock the Hibernate mode: + /* Lock the Hibernate mode: * write PWR_HIBERNATE.HIBERNATE=0, UNLOCK=0x00, HIBERANTE=0 */ SRSS_PWR_HIBERNATE &= HIBERNATE_RETAIN_STATUS_MASK; - +#endif /* ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) */ + /* Read register to make sure it is settled */ (void) SRSS_PWR_HIBERNATE; @@ -2756,16 +2902,16 @@ void Cy_SysPm_IoUnfreeze(void) * Function that changes the voltage setting for flash. * * \note -* Call this function before system enters ULP mode. Call this function after +* Call this function before system enters ULP mode. Call this function after * the system enters LP mode. -* +* * \param value -* Value to be set in the flash voltage control register. +* Value to be set in the flash voltage control register. * See \ref cy_en_syspm_flash_voltage_bit_t. * * \return -* - CY_SYSPM_SUCCESS - The voltage is set. -* - CY_SYSPM_CANCELED - Operation was canceled. Call the function again until +* - CY_SYSPM_SUCCESS - The voltage is set. +* - CY_SYSPM_CANCELED - Operation was canceled. Call the function again until * the function returns CY_SYSPM_SUCCESS. See \ref cy_en_syspm_status_t. * * \funcusage @@ -2775,19 +2921,21 @@ void Cy_SysPm_IoUnfreeze(void) cy_en_syspm_status_t Cy_SysPm_WriteVoltageBitForFlash(cy_en_syspm_flash_voltage_bit_t value) { CY_ASSERT_L3(CY_SYSPM_IS_BIT_FOR_FLASH_VALID(value)); - + cy_en_syspm_status_t retVal = CY_SYSPM_CANCELED; + +#if !((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) uint16_t curDeviceRevision = Cy_SysLib_GetDeviceRevision(); uint16_t curDevice = Cy_SysLib_GetDevice(); /* Check the current protection context value. We can have a direct register * update if protection context is = 0 */ - if ((Cy_Prot_GetActivePC(ACTIVE_BUS_MASTER) == 0U) && (curDevice == CY_SYSLIB_DEVICE_PSOC6ABLE2) && + if ((Cy_Prot_GetActivePC(ACTIVE_BUS_MASTER) == 0U) && (curDevice == CY_SYSLIB_DEVICE_PSOC6ABLE2) && (curDeviceRevision <= SYSPM_DEVICE_PSOC6ABLE2_REV_0B)) { - FLASHC_FM_CTL_ANA_CTL0 = + FLASHC_FM_CTL_ANA_CTL0 = _CLR_SET_FLD32U((FLASHC_FM_CTL_ANA_CTL0), FLASHC_FM_CTL_ANA_CTL0_VCC_SEL, value); - + retVal = CY_SYSPM_SUCCESS; } @@ -2799,16 +2947,16 @@ cy_en_syspm_status_t Cy_SysPm_WriteVoltageBitForFlash(cy_en_syspm_flash_voltage_ { uint32_t syscallCode; IPC_STRUCT_Type *ipcSyscallBase = Cy_IPC_Drv_GetIpcBaseAddress(CY_IPC_CHAN_SYSCALL); - + /* Set required syscall code */ if (curDevice == CY_SYSLIB_DEVICE_PSOC6ABLE2) { - syscallCode = (CY_SYSPM_FLASH_VOLTAGE_BIT_LP != value) ? + syscallCode = (CY_SYSPM_FLASH_VOLTAGE_BIT_LP != value) ? FLASH_VOLTAGE_BIT_ULP_PSOC6ABLE2_OPCODE : FLASH_VOLTAGE_BIT_LP_PSOC6ABLE2_OPCODE; } else { - syscallCode = (CY_SYSPM_FLASH_VOLTAGE_BIT_LP != value) ? + syscallCode = (CY_SYSPM_FLASH_VOLTAGE_BIT_LP != value) ? FLASH_VOLTAGE_BIT_ULP_OPCODE : FLASH_VOLTAGE_BIT_LP_OPCODE; } @@ -2820,29 +2968,33 @@ cy_en_syspm_status_t Cy_SysPm_WriteVoltageBitForFlash(cy_en_syspm_flash_voltage_ { /* Polls whether the IPC is released */ } - + /* Check the return status of a syscall */ uint32_t syscallStatus = Cy_IPC_Drv_ReadDataValue(ipcSyscallBase); - + if (SYSCALL_STATUS_SUCCESS == (syscallStatus & SYSCALL_STATUS_MASK)) { retVal = CY_SYSPM_SUCCESS; } } } +#else + (void)value; +#endif /* !((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) */ return retVal; } +#if !((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) /******************************************************************************* * Function Name: Cy_SysPm_SaveRegisters ****************************************************************************//** * -* Saves non-retained UDB registers and the slow and fast clock dividers before +* Saves non-retained UDB registers and the slow and fast clock dividers before * system entering system Deep Sleep. -* Must be called if programmable logic or function are implemented in the UDB -* array. +* Must be called if programmable logic or function are implemented in the UDB +* array. * * Cypress ID #280370, #1451. * @@ -2856,7 +3008,7 @@ cy_en_syspm_status_t Cy_SysPm_WriteVoltageBitForFlash(cy_en_syspm_flash_voltage_ void Cy_SysPm_SaveRegisters(cy_stc_syspm_backup_regs_t *regs) { CY_ASSERT_L1(NULL != regs); - + /* Save the registers before Deep Sleep */ regs->CY_SYSPM_CM0_CLOCK_CTL_REG = CPUSS_CM0_CLOCK_CTL; regs->CY_SYSPM_CM4_CLOCK_CTL_REG = CPUSS_CM4_CLOCK_CTL; @@ -2880,15 +3032,15 @@ void Cy_SysPm_SaveRegisters(cy_stc_syspm_backup_regs_t *regs) * Function Name: Cy_SysPm_RestoreRegisters ****************************************************************************//** * -* Restores non-retained UDB registers and the slow and fast clock dividers +* Restores non-retained UDB registers and the slow and fast clock dividers * before system entering system Deep Sleep. -* Must be called if programmable logic or function are implemented in the UDB -* array. -* +* Must be called if programmable logic or function are implemented in the UDB +* array. +* * Cypress ID #280370, #1451. * * \param regs -* The structure with data stored (using Cy_SysPm_SaveRegisters()) into the +* The structure with data stored (using Cy_SysPm_SaveRegisters()) into the * required registers after Deep Sleep. * * \funcusage @@ -2898,7 +3050,7 @@ void Cy_SysPm_SaveRegisters(cy_stc_syspm_backup_regs_t *regs) void Cy_SysPm_RestoreRegisters(cy_stc_syspm_backup_regs_t const *regs) { CY_ASSERT_L1(NULL != regs); - + /* Restore the registers after Deep Sleep */ CPUSS_CM0_CLOCK_CTL = regs->CY_SYSPM_CM0_CLOCK_CTL_REG; CPUSS_CM4_CLOCK_CTL = regs->CY_SYSPM_CM4_CLOCK_CTL_REG; @@ -2916,40 +3068,42 @@ void Cy_SysPm_RestoreRegisters(cy_stc_syspm_backup_regs_t const *regs) UDB_UDBIF_BANK_CTL = regs->CY_SYSPM_UDB_UDBIF_BANK_CTL_REG; } } +#endif /* !((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) */ /******************************************************************************* * Function Name: EnterDeepSleepRam ****************************************************************************//** * -* The internal function that prepares the system for Deep Sleep and +* The internal function that prepares the system for Deep Sleep and * restores the system after a wakeup from Deep Sleep. * * \param waitFor * Selects wait for action. See \ref cy_en_syspm_waitfor_t. * * \return -* - true - System Deep Sleep was occurred. +* - true - System Deep Sleep was occurred. * - false - System Deep Sleep was not occurred. * *******************************************************************************/ -#if defined (__ICCARM__) - #pragma diag_suppress=Ta023 - __ramfunc -#else - CY_SECTION(".cy_ramfunc") CY_NOINLINE +CY_RAMFUNC_BEGIN +#if !defined (__ICCARM__) + CY_NOINLINE #endif static void EnterDeepSleepRam(cy_en_syspm_waitfor_t waitFor) { +#if !((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) + /* Store the address of the Deep Sleep indicator into the RAM */ volatile uint32_t *delayDoneFlag = &FLASHC_BIST_DATA_0; - +#endif /* !((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) */ + #if (CY_CPU_CORTEX_M4) /* Store the address of the CM4 power status register */ volatile uint32_t *cpussCm4PwrCtlAddr = &CPUSS_CM4_PWR_CTL; - /* Repeat the WFI/WFE instruction if a wake up was not intended. + /* Repeat the WFI/WFE instruction if a wake up was not intended. * Cypress ID #272909 */ do @@ -2968,7 +3122,7 @@ static void EnterDeepSleepRam(cy_en_syspm_waitfor_t waitFor) __WFE(); #if (CY_CPU_CORTEX_M4) - /* Call the WFE instruction twice to clear the Event register + /* Call the WFE instruction twice to clear the Event register * of the CM4 CPU. Cypress ID #279077 */ if(wasEventSent) @@ -2981,9 +3135,14 @@ static void EnterDeepSleepRam(cy_en_syspm_waitfor_t waitFor) #if (CY_CPU_CORTEX_M4) } while (_FLD2VAL(CPUSS_CM4_PWR_CTL_PWR_MODE, (*cpussCm4PwrCtlAddr)) == CM4_PWR_STS_RETAINED); + + #if defined(CY_DEVICE_SECURE) + CY_PRA_CM0_WAKEUP(); + #endif /* defined(CY_DEVICE_SECURE) */ #endif /* (CY_CPU_CORTEX_M4) */ - /* Set 10 uS delay only under condition that the FLASHC_BIST_DATA[0] is +#if !((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) + /* Set 10 uS delay only under condition that the FLASHC_BIST_DATA[0] is * cleared. Cypress ID #288510 */ if (*delayDoneFlag == NEED_DELAY) @@ -2992,6 +3151,10 @@ static void EnterDeepSleepRam(cy_en_syspm_waitfor_t waitFor) uint32_t clkOutputSlow; uint32_t ddftFastCtl; + #if defined(CY_DEVICE_SECURE) + Cy_PRA_CloseSrssMain2(); + #endif /* defined(CY_DEVICE_SECURE) */ + /* Save timer configuration */ ddftSlowCtl = SRSS_TST_DDFT_SLOW_CTL_REG; clkOutputSlow = SRSS_CLK_OUTPUT_SLOW; @@ -3012,24 +3175,28 @@ static void EnterDeepSleepRam(cy_en_syspm_waitfor_t waitFor) /* Indicate that delay was done */ *delayDoneFlag = DELAY_DONE; - + /* Restore timer configuration */ SRSS_TST_DDFT_SLOW_CTL_REG = ddftSlowCtl; SRSS_CLK_OUTPUT_SLOW = clkOutputSlow; SRSS_TST_DDFT_FAST_CTL_REG = ddftFastCtl; + + #if defined(CY_DEVICE_SECURE) + Cy_PRA_OpenSrssMain2(); + #endif /* defined(CY_DEVICE_SECURE) */ } +#endif /* !((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) */ } -#if defined (__ICCARM__) - #pragma diag_default=Ta023 -#endif +CY_RAMFUNC_END +#if !((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) /******************************************************************************* * Function Name: SetReadMarginTrimUlp ****************************************************************************//** * * This is the internal function that updates the read-margin trim values for the -* RAM and ROM. The trim update is done during transition of regulator voltage +* RAM and ROM. The trim update is done during transition of regulator voltage * from higher to a lower one. * *******************************************************************************/ @@ -3046,7 +3213,7 @@ static void SetReadMarginTrimUlp(void) } else { - CPUSS_TRIM_RAM_CTL = (SFLASH_CPUSS_TRIM_RAM_CTL_HALF_ULP & ((uint32_t) ~CPUSS_TRIM_RAM_CTL_RA_MASK)) | + CPUSS_TRIM_RAM_CTL = (SFLASH_CPUSS_TRIM_RAM_CTL_HALF_ULP & ((uint32_t) ~CPUSS_TRIM_RAM_CTL_RA_MASK)) | (CPUSS_TRIM_RAM_CTL & CPUSS_TRIM_RAM_CTL_RA_MASK); CPUSS_TRIM_ROM_CTL = SFLASH_CPUSS_TRIM_ROM_CTL_HALF_ULP; @@ -3058,8 +3225,8 @@ static void SetReadMarginTrimUlp(void) * Function Name: SetReadMarginTrimLp ****************************************************************************//** * -* The internal function that updates the read-margin trim values for the -* RAM and ROM. The trim update is done during transition of regulator voltage +* The internal function that updates the read-margin trim values for the +* RAM and ROM. The trim update is done during transition of regulator voltage * from a lower to a higher one. * *******************************************************************************/ @@ -3076,7 +3243,7 @@ static void SetReadMarginTrimLp(void) } else { - CPUSS_TRIM_RAM_CTL = (SFLASH_CPUSS_TRIM_RAM_CTL_LP & ((uint32_t) ~CPUSS_TRIM_RAM_CTL_RA_MASK)) | + CPUSS_TRIM_RAM_CTL = (SFLASH_CPUSS_TRIM_RAM_CTL_LP & ((uint32_t) ~CPUSS_TRIM_RAM_CTL_RA_MASK)) | (CPUSS_TRIM_RAM_CTL & CPUSS_TRIM_RAM_CTL_RA_MASK); CPUSS_TRIM_ROM_CTL = SFLASH_CPUSS_TRIM_ROM_CTL_LP; @@ -3088,8 +3255,8 @@ static void SetReadMarginTrimLp(void) * Function Name: SetWriteAssistTrimUlp ****************************************************************************//** * -* The internal function that updates the write assistant trim value for the -* RAM. The trim update is done during transition of regulator voltage +* The internal function that updates the write assistant trim value for the +* RAM. The trim update is done during transition of regulator voltage * from higher to a lower. * *******************************************************************************/ @@ -3113,8 +3280,8 @@ static void SetWriteAssistTrimUlp(void) * Function Name: SetWriteAssistTrimLp ****************************************************************************//** * -* The internal function that updates the write assistant trim value for the -* RAM. The trim update is done during transition of regulator voltage +* The internal function that updates the write assistant trim value for the +* RAM. The trim update is done during transition of regulator voltage * from lower to a higher one. * *******************************************************************************/ @@ -3140,8 +3307,8 @@ static void SetWriteAssistTrimLp(void) * Function Name: IsVoltageChangePossible ****************************************************************************//** * -* The internal function that checks wherever it is possible to change the core -* voltage. The voltage change is possible only when the protection context is +* The internal function that checks wherever it is possible to change the core +* voltage. The voltage change is possible only when the protection context is * set to zero (PC = 0), or the device supports modifying registers via syscall. * *******************************************************************************/ @@ -3149,7 +3316,7 @@ static bool IsVoltageChangePossible(void) { bool retVal = false; uint32_t trimRamCheckVal = (CPUSS_TRIM_RAM_CTL & CPUSS_TRIM_RAM_CTL_WC_MASK); - + if (Cy_SysLib_GetDevice() == CY_SYSLIB_DEVICE_PSOC6ABLE2) { @@ -3161,12 +3328,13 @@ static bool IsVoltageChangePossible(void) { CPUSS_TRIM_RAM_CTL &= ~CPUSS_TRIM_RAM_CTL_WC_MASK; CPUSS_TRIM_RAM_CTL |= ((~trimRamCheckVal) & CPUSS_TRIM_RAM_CTL_WC_MASK); - + retVal = (trimRamCheckVal != (CPUSS_TRIM_RAM_CTL & CPUSS_TRIM_RAM_CTL_WC_MASK)); } return retVal; } +#endif /* !((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) */ /* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_systick.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_systick.c index c1af99f878..bf39e493ce 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_systick.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_systick.c @@ -1,12 +1,12 @@ /***************************************************************************//** * \file cy_systick.c -* \version 1.10 +* \version 1.20 * * Provides the API definitions of the SisTick driver. * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -22,9 +22,9 @@ * limitations under the License. *******************************************************************************/ -#include "cy_systick.h" #include /* for NULL */ - +#include "cy_systick.h" +#include "cy_sysint.h" static Cy_SysTick_Callback Cy_SysTick_Callbacks[CY_SYS_SYST_NUM_OF_CALLBACKS]; static void Cy_SysTick_ServiceCallbacks(void); @@ -117,6 +117,9 @@ void Cy_SysTick_Disable(void) * called to compensate this change. * * \param clockSource \ref cy_en_systick_clock_source_t Clock source. +* For the PSoC 64 devices, passing any other value than +* CY_SYSTICK_CLOCK_SOURCE_CLK_CPU will not affect clock source +* and it will be as \ref Cy_SysTick_GetClockSource() reports. * *******************************************************************************/ void Cy_SysTick_SetClockSource(cy_en_systick_clock_source_t clockSource) @@ -127,7 +130,9 @@ void Cy_SysTick_SetClockSource(cy_en_systick_clock_source_t clockSource) } else { - CPUSS_SYSTICK_CTL = _VAL2FLD(CPUSS_SYSTICK_CTL_CLOCK_SOURCE, (uint32_t) clockSource); + #if ((CY_CPU_CORTEX_M0P) || (!defined(CY_DEVICE_SECURE))) + CPUSS_SYSTICK_CTL = _VAL2FLD(CPUSS_SYSTICK_CTL_CLOCK_SOURCE, (uint32_t) clockSource); + #endif /* ((CY_CPU_CORTEX_M0P) || (!defined(CY_DEVICE_SECURE))) */ SYSTICK_CTRL &= ~SysTick_CTRL_CLKSOURCE_Msk; } } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_tcpwm_counter.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_tcpwm_counter.c index a6ae1aaa92..6cba605f5f 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_tcpwm_counter.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_tcpwm_counter.c @@ -1,13 +1,13 @@ /***************************************************************************//** * \file cy_tcpwm_counter.c -* \version 1.10.1 +* \version 1.10.2 * * \brief * The source file of the tcpwm driver. * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -54,7 +54,7 @@ extern "C" { * \snippet tcpwm/counter/snippet/main.c snippet_Cy_TCPWM_Counter_Init * *******************************************************************************/ -cy_en_tcpwm_status_t Cy_TCPWM_Counter_Init(TCPWM_Type *base, uint32_t cntNum, +cy_en_tcpwm_status_t Cy_TCPWM_Counter_Init(TCPWM_Type *base, uint32_t cntNum, cy_stc_tcpwm_counter_config_t const *config) { cy_en_tcpwm_status_t status = CY_TCPWM_BAD_PARAM; @@ -116,7 +116,7 @@ cy_en_tcpwm_status_t Cy_TCPWM_Counter_Init(TCPWM_Type *base, uint32_t cntNum, * Function Name: Cy_TCPWM_Counter_DeInit ****************************************************************************//** * -* De-initializes the counter in the TCPWM block, returns register values to +* De-initializes the counter in the TCPWM block, returns register values to * default. * * \param base @@ -145,7 +145,7 @@ void Cy_TCPWM_Counter_DeInit(TCPWM_Type *base, uint32_t cntNum, cy_stc_tcpwm_cou TCPWM_CNT_INTR(base, cntNum) = CY_TCPWM_CNT_INTR_DEFAULT; TCPWM_CNT_INTR_SET(base, cntNum) = CY_TCPWM_CNT_INTR_SET_DEFAULT; TCPWM_CNT_INTR_MASK(base, cntNum) = CY_TCPWM_CNT_INTR_MASK_DEFAULT; - + if (CY_TCPWM_INPUT_CREATOR != config->countInput) { TCPWM_CNT_TR_CTRL0(base, cntNum) = CY_TCPWM_CNT_TR_CTRL0_DEFAULT; diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_tcpwm_pwm.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_tcpwm_pwm.c index 90e675e749..3191c1c4d6 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_tcpwm_pwm.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_tcpwm_pwm.c @@ -1,13 +1,13 @@ /***************************************************************************//** * \file cy_tcpwm_pwm.c -* \version 1.10.1 +* \version 1.10.2 * * \brief * The source file of the tcpwm driver. * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -108,7 +108,7 @@ cy_en_tcpwm_status_t Cy_TCPWM_PWM_Init(TCPWM_Type *base, uint32_t cntNum, cy_st _VAL2FLD(TCPWM_CNT_TR_CTRL0_STOP_SEL, config->killInput) | _VAL2FLD(TCPWM_CNT_TR_CTRL0_COUNT_SEL, config->countInput)); } - + TCPWM_CNT_TR_CTRL1(base, cntNum) = (_VAL2FLD(TCPWM_CNT_TR_CTRL1_CAPTURE_EDGE, config->swapInputMode) | _VAL2FLD(TCPWM_CNT_TR_CTRL1_RELOAD_EDGE, config->reloadInputMode) | _VAL2FLD(TCPWM_CNT_TR_CTRL1_START_EDGE, config->startInputMode) | @@ -127,7 +127,7 @@ cy_en_tcpwm_status_t Cy_TCPWM_PWM_Init(TCPWM_Type *base, uint32_t cntNum, cy_st * Function Name: Cy_TCPWM_PWM_DeInit ****************************************************************************//** * -* De-initializes the counter in the TCPWM block, returns register values to +* De-initializes the counter in the TCPWM block, returns register values to * default. * * \param base @@ -158,7 +158,7 @@ void Cy_TCPWM_PWM_DeInit(TCPWM_Type *base, uint32_t cntNum, cy_stc_tcpwm_pwm_con TCPWM_CNT_INTR_MASK(base, cntNum) = CY_TCPWM_CNT_INTR_MASK_DEFAULT; if (CY_TCPWM_INPUT_CREATOR != config->countInput) - { + { TCPWM_CNT_TR_CTRL0(base, cntNum) = CY_TCPWM_CNT_TR_CTRL0_DEFAULT; } } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_tcpwm_quaddec.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_tcpwm_quaddec.c index 37472a9203..aeb946ee35 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_tcpwm_quaddec.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_tcpwm_quaddec.c @@ -1,13 +1,13 @@ /***************************************************************************//** * \file cy_tcpwm_quaddec.c -* \version 1.10.1 +* \version 1.10.2 * * \brief * The source file of the tcpwm driver. * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -54,7 +54,7 @@ extern "C" { * \snippet tcpwm/quaddec/snippet/main.c snippet_Cy_TCPWM_QuadDec_Init * *******************************************************************************/ -cy_en_tcpwm_status_t Cy_TCPWM_QuadDec_Init(TCPWM_Type *base, uint32_t cntNum, +cy_en_tcpwm_status_t Cy_TCPWM_QuadDec_Init(TCPWM_Type *base, uint32_t cntNum, cy_stc_tcpwm_quaddec_config_t const *config) { cy_en_tcpwm_status_t status = CY_TCPWM_BAD_PARAM; @@ -65,13 +65,13 @@ cy_en_tcpwm_status_t Cy_TCPWM_QuadDec_Init(TCPWM_Type *base, uint32_t cntNum, _VAL2FLD(TCPWM_CNT_CTRL_MODE, CY_TCPWM_QUADDEC_CTRL_QUADDEC_MODE)); if (CY_TCPWM_INPUT_CREATOR != config->phiAInput) - { + { TCPWM_CNT_TR_CTRL0(base, cntNum) = (_VAL2FLD(TCPWM_CNT_TR_CTRL0_COUNT_SEL, config->phiAInput) | _VAL2FLD(TCPWM_CNT_TR_CTRL0_START_SEL, config->phiBInput) | _VAL2FLD(TCPWM_CNT_TR_CTRL0_RELOAD_SEL, config->indexInput) | _VAL2FLD(TCPWM_CNT_TR_CTRL0_STOP_SEL, config->stopInput)); } - + TCPWM_CNT_TR_CTRL1(base, cntNum) = (_VAL2FLD(TCPWM_CNT_TR_CTRL1_CAPTURE_EDGE, CY_TCPWM_INPUT_LEVEL) | _VAL2FLD(TCPWM_CNT_TR_CTRL1_COUNT_EDGE, CY_TCPWM_INPUT_LEVEL) | _VAL2FLD(TCPWM_CNT_TR_CTRL1_START_EDGE, CY_TCPWM_INPUT_LEVEL) | @@ -91,7 +91,7 @@ cy_en_tcpwm_status_t Cy_TCPWM_QuadDec_Init(TCPWM_Type *base, uint32_t cntNum, * Function Name: Cy_TCPWM_QuadDec_DeInit ****************************************************************************//** * -* De-initializes the counter in the TCPWM block, returns register values to +* De-initializes the counter in the TCPWM block, returns register values to * default. * * \param base @@ -122,7 +122,7 @@ void Cy_TCPWM_QuadDec_DeInit(TCPWM_Type *base, uint32_t cntNum, cy_stc_tcpwm_qua TCPWM_CNT_INTR_MASK(base, cntNum) = CY_TCPWM_CNT_INTR_MASK_DEFAULT; if (CY_TCPWM_INPUT_CREATOR != config->phiAInput) - { + { TCPWM_CNT_TR_CTRL0(base, cntNum) = CY_TCPWM_CNT_TR_CTRL0_DEFAULT; } } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_trigmux.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_trigmux.c index 0070b4f86b..6dfd563c30 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_trigmux.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_trigmux.c @@ -1,12 +1,12 @@ /***************************************************************************//** * \file cy_trigmux.c -* \version 1.20.1 +* \version 1.20.2 * * \brief Trigger mux API. * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -93,7 +93,7 @@ * * \funcusage * \snippet trigmux/snippet/main.c snippet_Cy_TrigMux_Connect -* +* *******************************************************************************/ cy_en_trigmux_status_t Cy_TrigMux_Connect(uint32_t inTrig, uint32_t outTrig, bool invert, en_trig_type_t trigType) { @@ -152,12 +152,12 @@ cy_en_trigmux_status_t Cy_TrigMux_Connect(uint32_t inTrig, uint32_t outTrig, boo * * \funcusage * \snippet trigmux/snippet/main.c snippet_Cy_TrigMux_Select -* +* *******************************************************************************/ cy_en_trigmux_status_t Cy_TrigMux_Select(uint32_t outTrig, bool invert, en_trig_type_t trigType) { cy_en_trigmux_status_t retVal = CY_TRIGMUX_BAD_PARAM; - + CY_ASSERT_L3(CY_TRIGMUX_IS_TRIGTYPE_VALID(trigType)); CY_ASSERT_L2(CY_TRIGMUX_IS_ONETRIG_VALID(outTrig)); @@ -202,7 +202,7 @@ cy_en_trigmux_status_t Cy_TrigMux_Select(uint32_t outTrig, bool invert, en_trig_ * * \funcusage * \snippet trigmux/snippet/main.c snippet_Cy_TrigMux_Deselect -* +* *******************************************************************************/ cy_en_trigmux_status_t Cy_TrigMux_Deselect(uint32_t outTrig) { @@ -233,7 +233,7 @@ cy_en_trigmux_status_t Cy_TrigMux_Deselect(uint32_t outTrig) * Function Name: Cy_TrigMux_SetDebugFreeze ****************************************************************************//** * -* Enables/disables the Debug Freeze feature for the specified trigger +* Enables/disables the Debug Freeze feature for the specified trigger * multiplexer or 1-to-1 trigger line. For PERI_ver2 only. * * \param outTrig @@ -252,10 +252,10 @@ cy_en_trigmux_status_t Cy_TrigMux_Deselect(uint32_t outTrig) * * \funcusage * \snippet trigmux/snippet/main.c snippet_Cy_TrigMux_SetDebugFreeze -* +* *******************************************************************************/ cy_en_trigmux_status_t Cy_TrigMux_SetDebugFreeze(uint32_t outTrig, bool enable) -{ +{ cy_en_trigmux_status_t retVal = CY_TRIGMUX_BAD_PARAM; if (!CY_PERI_V1) @@ -286,16 +286,16 @@ cy_en_trigmux_status_t Cy_TrigMux_SetDebugFreeze(uint32_t outTrig, bool enable) * Function Name: Cy_TrigMux_SwTrigger ****************************************************************************//** * -* This function generates a software trigger on an input trigger line. -* All output triggers connected to this input trigger will be triggered. -* The function also verifies that there is no activated trigger before -* generating another activation. +* This function generates a software trigger on an input trigger line. +* All output triggers connected to this input trigger will be triggered. +* The function also verifies that there is no activated trigger before +* generating another activation. * * \param trigLine * The input of the trigger mux. -* - Bit 30 represents if the signal is an input/output. When this bit is set, +* - Bit 30 represents if the signal is an input/output. When this bit is set, * the trigger activation is for an output trigger from the trigger multiplexer. -* When this bit is reset, the trigger activation is for an input trigger to +* When this bit is reset, the trigger activation is for an input trigger to * the trigger multiplexer. * - Bits 12:8 represent the trigger group selection.
* In case of output trigger line (bit 30 is set): @@ -315,7 +315,7 @@ cy_en_trigmux_status_t Cy_TrigMux_SetDebugFreeze(uint32_t outTrig, bool enable) * calling this function with CY_TRIGGER_DEACTIVATE parameter. * - CY_TRIGGER_DEACTIVATE - this is used to deactivate the trigger activated by * calling this function with CY_TRIGGER_INFINITE parameter. -* +* * \return status: * - CY_TRIGMUX_SUCCESS: The trigger is successfully activated/deactivated. * - CY_TRIGMUX_INVALID_STATE: The trigger is already activated/not active. @@ -342,9 +342,9 @@ cy_en_trigmux_status_t Cy_TrigMux_SwTrigger(uint32_t trigLine, uint32_t cycles) PERI_TR_CMD_OUT_SEL_Msk | CY_PERI_TR_CMD_GROUP_SEL_Msk)) | PERI_TR_CMD_ACTIVATE_Msk; - + retVal = CY_TRIGMUX_SUCCESS; - + if (CY_PERI_V1) /* mxperi_v1 */ { PERI_TR_CMD = trCmd | _VAL2FLD(PERI_TR_CMD_COUNT, cycles); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_usbfs_dev_drv.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_usbfs_dev_drv.c index 7bec02a2b6..6a234f1b38 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_usbfs_dev_drv.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_usbfs_dev_drv.c @@ -1,12 +1,12 @@ /***************************************************************************//** * \file cy_usbfs_dev_drv.c -* \version 2.20 +* \version 2.20.1 * * Provides general API implementation of the USBFS driver. * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -78,15 +78,15 @@ static void EndpointTransferComplete(USBFS_Type *base, uint32_t endpoint, * * \param context * The pointer to the context structure \ref cy_stc_usbfs_dev_drv_context_t -* allocated by the user. The structure is used during the USBFS Device -* operation for internal configuration and data retention. The user must not +* allocated by the user. The structure is used during the USBFS Device +* operation for internal configuration and data retention. The user must not * modify anything in this structure. * * \return * The status code of the function execution \ref cy_en_usbfs_dev_drv_status_t. * *******************************************************************************/ -cy_en_usbfs_dev_drv_status_t Cy_USBFS_Dev_Drv_Init(USBFS_Type *base, +cy_en_usbfs_dev_drv_status_t Cy_USBFS_Dev_Drv_Init(USBFS_Type *base, cy_stc_usbfs_dev_drv_config_t const *config, cy_stc_usbfs_dev_drv_context_t *context) { @@ -204,7 +204,7 @@ cy_en_usbfs_dev_drv_status_t Cy_USBFS_Dev_Drv_Init(USBFS_Type *base, * Function Name: Cy_USBFS_Dev_Drv_DeInit ****************************************************************************//** * -* De-initializes the USBFS Device hardware (returns the register values to +* De-initializes the USBFS Device hardware (returns the register values to * default) and removes all registered callbacks. * * \param base @@ -212,8 +212,8 @@ cy_en_usbfs_dev_drv_status_t Cy_USBFS_Dev_Drv_Init(USBFS_Type *base, * * \param context * The pointer to the context structure \ref cy_stc_usbfs_dev_drv_context_t -* allocated by the user. The structure is used during the USBFS Device -* operation for internal configuration and data retention. The user must not +* allocated by the user. The structure is used during the USBFS Device +* operation for internal configuration and data retention. The user must not * modify anything in this structure. * *******************************************************************************/ @@ -238,7 +238,7 @@ void Cy_USBFS_Dev_Drv_DeInit(USBFS_Type *base, cy_stc_usbfs_dev_drv_context_t *c USBFS_DEV_USBIO_CR0(base) = 0UL; USBFS_DEV_USBIO_CR1(base) = (USBFS_DEV_USBIO_CR1(base) & USBFS_USBDEV_USBIO_CR1_RESERVED_2_Msk); regVal = CY_USBFS_DEV_READ_ODD(USBFS_DEV_USBIO_CR2(base)); - USBFS_DEV_USBIO_CR2(base) = (CY_USBFS_DEV_DRV_WRITE_ODD(regVal) & USBFS_USBDEV_USBIO_CR2_RESERVED_7_Msk); + USBFS_DEV_USBIO_CR2(base) = (CY_USBFS_DEV_DRV_WRITE_ODD(regVal) & USBFS_USBDEV_USBIO_CR2_RESERVED_7_Msk); USBFS_DEV_BUS_RST_CNT(base) = BUS_RESET_PERIOD; USBFS_DEV_USB_CLK_EN(base) = CY_USBFS_DEV_DRV_WRITE_ODD(0UL); @@ -258,7 +258,7 @@ void Cy_USBFS_Dev_Drv_DeInit(USBFS_Type *base, cy_stc_usbfs_dev_drv_context_t *c USBFS_DEV_SIE_EP_INT_EN(base) = 0UL; USBFS_DEV_SIE_EP_INT_SR(base) = 0UL; - + for (endpoint = 0UL; endpoint < CY_USBFS_DEV_DRV_NUM_EPS_MAX; ++endpoint) { /* Sets the SIE endpoint register into the default state */ @@ -276,7 +276,7 @@ void Cy_USBFS_Dev_Drv_DeInit(USBFS_Type *base, cy_stc_usbfs_dev_drv_context_t *c /* Cleans the context callbacks */ context->cbSof = NULL; context->cbLpm = NULL; - + for (endpoint = 0UL; endpoint < CY_USBFS_DEV_DRV_NUM_EPS_MAX; ++endpoint) { context->epPool[endpoint].address = 0U; @@ -298,8 +298,8 @@ void Cy_USBFS_Dev_Drv_DeInit(USBFS_Type *base, cy_stc_usbfs_dev_drv_context_t *c * * \param context * The pointer to the context structure \ref cy_stc_usbfs_dev_drv_context_t -* allocated by the user. The structure is used during the USBFS Device -* operation for internal configuration and data retention. The user must not +* allocated by the user. The structure is used during the USBFS Device +* operation for internal configuration and data retention. The user must not * modify anything in this structure. * *******************************************************************************/ @@ -331,8 +331,8 @@ void Cy_USBFS_Dev_Drv_Enable(USBFS_Type *base, cy_stc_usbfs_dev_drv_context_t co * * \param context * The pointer to the context structure \ref cy_stc_usbfs_dev_drv_context_t -* allocated by the user. The structure is used during the USBFS Device -* operation for internal configuration and data retention. The user must not +* allocated by the user. The structure is used during the USBFS Device +* operation for internal configuration and data retention. The user must not * modify anything in this structure. * *******************************************************************************/ @@ -367,8 +367,8 @@ void Cy_USBFS_Dev_Drv_Disable(USBFS_Type *base, cy_stc_usbfs_dev_drv_context_t * * * \param context * The pointer to the context structure \ref cy_stc_usbfs_dev_drv_context_t -* allocated by the user. The structure is used during the USBFS Device -* operation for internal configuration and data retention. The user must not +* allocated by the user. The structure is used during the USBFS Device +* operation for internal configuration and data retention. The user must not * modify anything in this structure. * *******************************************************************************/ @@ -392,8 +392,8 @@ static void LpmIntrHandler(USBFS_Type *base, cy_stc_usbfs_dev_drv_context_t *con * * \param context * The pointer to the context structure \ref cy_stc_usbfs_dev_drv_context_t -* allocated by the user. The structure is used during the USBFS Device -* operation for internal configuration and data retention. The user must not +* allocated by the user. The structure is used during the USBFS Device +* operation for internal configuration and data retention. The user must not * modify anything in this structure. * *******************************************************************************/ @@ -417,8 +417,8 @@ static void SofIntrHandler(USBFS_Type *base, cy_stc_usbfs_dev_drv_context_t *con * * \param context * The pointer to the context structure \ref cy_stc_usbfs_dev_drv_context_t -* allocated by the user. The structure is used during the USBFS Device -* operation for internal configuration and data retention. The user must not +* allocated by the user. The structure is used during the USBFS Device +* operation for internal configuration and data retention. The user must not * modify anything in this structure. * *******************************************************************************/ @@ -435,7 +435,7 @@ static void Ep0IntrHandler(USBFS_Type *base, cy_stc_usbfs_dev_drv_context_t *con { /* A setup packet received */ context->ep0CtrlState = CY_USBFS_DEV_DRV_EP0_CTRL_STATE_SETUP; - + /* Handles SETUP */ if (_FLD2VAL(USBFS_USBDEV_EP0_CR_MODE, ep0Cr) == CY_USBFS_DEV_DRV_EP_CR_NAK_INOUT) { @@ -523,8 +523,8 @@ static void Ep0IntrHandler(USBFS_Type *base, cy_stc_usbfs_dev_drv_context_t *con * * \param context * The pointer to the context structure \ref cy_stc_usbfs_dev_drv_context_t -* allocated by the user. The structure is used during the USBFS Device -* operation for internal configuration and data retention. The user must not +* allocated by the user. The structure is used during the USBFS Device +* operation for internal configuration and data retention. The user must not * modify anything in this structure. * *******************************************************************************/ @@ -562,7 +562,7 @@ static void BusResetIntrHandler(USBFS_Type *base, cy_stc_usbfs_dev_drv_context_t * Function Name: EndpointTransferComplete ****************************************************************************//** * -* Handles the endpoint transfer complete: updates the endpoint state, +* Handles the endpoint transfer complete: updates the endpoint state, * calls a transfer completion callback, handles the abort. * * \param base @@ -576,8 +576,8 @@ static void BusResetIntrHandler(USBFS_Type *base, cy_stc_usbfs_dev_drv_context_t * * \param context * The pointer to the context structure \ref cy_stc_usbfs_dev_drv_context_t -* allocated by the user. The structure is used during the USBFS Device -* operation for internal configuration and data retention. The user must not +* allocated by the user. The structure is used during the USBFS Device +* operation for internal configuration and data retention. The user must not * modify anything in this structure. * *******************************************************************************/ @@ -605,13 +605,13 @@ static void EndpointTransferComplete(USBFS_Type *base, uint32_t endpoint, if (NULL != endpointData->epComplete) { uint32_t errorType = 0UL; - + /* Checks transfer errors (detect by hardware) */ if (0U != Cy_USBFS_Dev_Drv_GetSieEpError(base, endpoint)) { errorType = CY_USBFS_DEV_ENDPOINT_TRANSFER_ERROR; } - + /* Checks the data toggle bit of current transfer (exclude ISOC endpoints) */ if (false == IS_EP_ISOC(endpointData->sieMode)) { @@ -643,8 +643,8 @@ static void EndpointTransferComplete(USBFS_Type *base, uint32_t endpoint, * * \param context * The pointer to the context structure \ref cy_stc_usbfs_dev_drv_context_t -* allocated by the user. The structure is used during the USBFS Device -* operation for internal configuration and data retention. The user must not +* allocated by the user. The structure is used during the USBFS Device +* operation for internal configuration and data retention. The user must not * modify anything in this structure. * *******************************************************************************/ @@ -685,7 +685,7 @@ static void ArbiterIntrHandler(USBFS_Type *base, cy_stc_usbfs_dev_drv_context_t /* Mode 2: Handle DMA completion event for OUT endpoints */ if (0U != (sourceMask & USBFS_USBDEV_ARB_EP_DMA_GNT_Msk)) { - /* Notifies the ReadOutEndpointDma function that the data has been copied from endpoint buffer + /* Notifies the ReadOutEndpointDma function that the data has been copied from endpoint buffer * into the user buffer. */ endpointData->state = CY_USB_DEV_EP_COMPLETED; @@ -704,9 +704,9 @@ static void ArbiterIntrHandler(USBFS_Type *base, cy_stc_usbfs_dev_drv_context_t /* This error condition indicates system failure */ if (0U != (sourceMask & USBFS_USBDEV_ARB_EP_BUF_OVER_Msk)) { - /* The DMA cannot move the data from the mxusbfs IP - * hardware buffer fast enough and so caused an overflow. Give a DMA - * channel for this endpoint greater priority or increase the clock + /* The DMA cannot move the data from the mxusbfs IP + * hardware buffer fast enough and so caused an overflow. Give a DMA + * channel for this endpoint greater priority or increase the clock * at which it operates. */ CY_ASSERT_L1(false); @@ -715,11 +715,11 @@ static void ArbiterIntrHandler(USBFS_Type *base, cy_stc_usbfs_dev_drv_context_t /* This error condition indicates system failure */ if (0U != (sourceMask & USBFS_USBDEV_ARB_EP_BUF_UNDER_Msk)) { - /* The DMA cannot move the data into the mxusbfs IP - * hardware buffer fast enough and so caused an underflow. Give a DMA - * channel for this endpoint greater priority or increase the clock + /* The DMA cannot move the data into the mxusbfs IP + * hardware buffer fast enough and so caused an underflow. Give a DMA + * channel for this endpoint greater priority or increase the clock * at which it operates. - */ + */ CY_ASSERT_L1(false); } } @@ -735,7 +735,7 @@ static void ArbiterIntrHandler(USBFS_Type *base, cy_stc_usbfs_dev_drv_context_t * Function Name: SieEnpointIntrHandler ****************************************************************************//** * -* SIE (Serial Interface Engine) endpoint interrupt handler. +* SIE (Serial Interface Engine) endpoint interrupt handler. * It triggers when communication was completed with data endpoint. * * \param base @@ -746,12 +746,12 @@ static void ArbiterIntrHandler(USBFS_Type *base, cy_stc_usbfs_dev_drv_context_t * * \param context * The pointer to the context structure \ref cy_stc_usbfs_dev_drv_context_t -* allocated by the user. The structure is used during the USBFS Device -* operation for internal configuration and data retention. The user must not +* allocated by the user. The structure is used during the USBFS Device +* operation for internal configuration and data retention. The user must not * modify anything in this structure. * *******************************************************************************/ -static void SieEnpointIntrHandler(USBFS_Type *base, uint32_t endpoint, +static void SieEnpointIntrHandler(USBFS_Type *base, uint32_t endpoint, cy_stc_usbfs_dev_drv_context_t *context) { bool modeDmaAuto; @@ -763,10 +763,10 @@ static void SieEnpointIntrHandler(USBFS_Type *base, uint32_t endpoint, Cy_USBFS_Dev_Drv_ClearSieEpInterrupt(base, endpoint); - /* + /* * DMA Auto requires special processing: * IN endpoints: Updates the endpoint state here to complete the transfer (includes a zero-length packet). - * OUT endpoints: Updates the endpoint state in ArbiterIntrHandler when DMA is done to complete the transfer + * OUT endpoints: Updates the endpoint state in ArbiterIntrHandler when DMA is done to complete the transfer * (interrupt source DMA_TERMIN). * In the case of a zero-length packet, updates the endpoint state here to complete the transfer. * Other modes (CPU mode and DMA mode): Updates the endpoint state here to complete the transfer for the IN and OUT endpoints. @@ -775,7 +775,7 @@ static void SieEnpointIntrHandler(USBFS_Type *base, uint32_t endpoint, inEndpoint = CY_USBFS_DEV_DRV_IS_EP_DIR_IN(endpointData->address); zeroLengthPacket = (0U == Cy_USBFS_Dev_Drv_GetSieEpCount(base, endpoint)); - if ( (!modeDmaAuto) || + if ( (!modeDmaAuto) || (modeDmaAuto && (inEndpoint || zeroLengthPacket)) ) { EndpointTransferComplete(base, endpoint, endpointData, context); @@ -788,27 +788,27 @@ static void SieEnpointIntrHandler(USBFS_Type *base, uint32_t endpoint, ****************************************************************************//** * * Processes interrupt events generated by the USBFS Device. -* The interrupts are mandatory for USBFS Device operation and this function +* The interrupts are mandatory for USBFS Device operation and this function * must be called inside the user-defined interrupt service routine. * * \param base * The pointer to the USBFS instance. * * \param intrCause -* The interrupt cause register value. Call appropriate function to get -* interrupt cause (Low, Medium or High): +* The interrupt cause register value. Call appropriate function to get +* interrupt cause (Low, Medium or High): * * \ref Cy_USBFS_Dev_Drv_GetInterruptCauseLo * * \ref Cy_USBFS_Dev_Drv_GetInterruptCauseMed * * \ref Cy_USBFS_Dev_Drv_GetInterruptCauseHi * * \param context * The pointer to the context structure \ref cy_stc_usbfs_dev_drv_context_t -* allocated by the user. The structure is used during the USBFS Device -* operation for internal configuration and data retention. The user must not +* allocated by the user. The structure is used during the USBFS Device +* operation for internal configuration and data retention. The user must not * modify anything in this structure. * *******************************************************************************/ -void Cy_USBFS_Dev_Drv_Interrupt(USBFS_Type *base, uint32_t intrCause, +void Cy_USBFS_Dev_Drv_Interrupt(USBFS_Type *base, uint32_t intrCause, cy_stc_usbfs_dev_drv_context_t *context) { uint32_t endpoint = 0U; @@ -849,7 +849,7 @@ void Cy_USBFS_Dev_Drv_Interrupt(USBFS_Type *base, uint32_t intrCause, { SofIntrHandler(base, context); } - + /* Controls EP0 */ if (0U != (intrCause & USBFS_USBLPM_INTR_CAUSE_EP0_INTR_Msk)) { @@ -868,7 +868,7 @@ void Cy_USBFS_Dev_Drv_Interrupt(USBFS_Type *base, uint32_t intrCause, * Function Name: WriteEp0Buffer ****************************************************************************//** * -* Writes data into the Endpoint 0 hardware buffer and returns how many bytes +* Writes data into the Endpoint 0 hardware buffer and returns how many bytes * were written. * * \param base @@ -887,19 +887,19 @@ void Cy_USBFS_Dev_Drv_Interrupt(USBFS_Type *base, uint32_t intrCause, static uint32_t WriteEp0Buffer(USBFS_Type *base, uint8_t const *buffer, uint32_t size) { uint32_t idx; - + /* Cuts the message size if too many bytes are requested to write */ if (size > CY_USBFS_DEV_DRV_EP0_BUFFER_SIZE) { size = CY_USBFS_DEV_DRV_EP0_BUFFER_SIZE; } - + /* Writes data into the hardware buffer */ for (idx = 0UL; idx < size; ++idx) { Cy_USBFS_Dev_Drv_WriteEp0Data(base, idx, (uint32_t) buffer[idx]); } - + return idx; } @@ -926,7 +926,7 @@ static uint32_t WriteEp0Buffer(USBFS_Type *base, uint8_t const *buffer, uint32_t static uint32_t ReadEp0Buffer(USBFS_Type const *base, uint8_t *buffer, uint32_t size) { uint32_t idx; - + /* Gets the number of received bytes */ uint32_t numToCopy = Cy_USBFS_Dev_Drv_GetEp0Count(base); @@ -935,13 +935,13 @@ static uint32_t ReadEp0Buffer(USBFS_Type const *base, uint8_t *buffer, uint32_t { size = numToCopy; } - + /* Gets the data from the buffer */ for (idx = 0UL; idx < size; ++idx) { buffer[idx] = (uint8_t) Cy_USBFS_Dev_Drv_ReadEp0Data(base, idx); } - + return idx; } @@ -960,12 +960,12 @@ static uint32_t ReadEp0Buffer(USBFS_Type const *base, uint8_t *buffer, uint32_t * * \param context * The pointer to the context structure \ref cy_stc_usbfs_dev_drv_context_t -* allocated by the user. The structure is used during the USBFS Device -* operation for internal configuration and data retention. The user must not +* allocated by the user. The structure is used during the USBFS Device +* operation for internal configuration and data retention. The user must not * modify anything in this structure. * *******************************************************************************/ -void Cy_USBFS_Dev_Drv_Ep0GetSetup(USBFS_Type const *base, uint8_t *buffer, +void Cy_USBFS_Dev_Drv_Ep0GetSetup(USBFS_Type const *base, uint8_t *buffer, cy_stc_usbfs_dev_drv_context_t const *context) { /* Suppresses a compiler warning about unused variables */ @@ -979,7 +979,7 @@ void Cy_USBFS_Dev_Drv_Ep0GetSetup(USBFS_Type const *base, uint8_t *buffer, * Function Name: Cy_USBFS_Dev_Drv_Ep0Write ****************************************************************************//** * -* Writes data into Endpoint 0 hardware buffer and returns how many bytes were +* Writes data into Endpoint 0 hardware buffer and returns how many bytes were * written. * * \param base @@ -995,15 +995,15 @@ void Cy_USBFS_Dev_Drv_Ep0GetSetup(USBFS_Type const *base, uint8_t *buffer, * * \param context * The pointer to the context structure \ref cy_stc_usbfs_dev_drv_context_t -* allocated by the user. The structure is used during the USBFS Device -* operation for internal configuration and data retention. The user must not +* allocated by the user. The structure is used during the USBFS Device +* operation for internal configuration and data retention. The user must not * modify anything in this structure. * * \return * The number of bytes that were written. * *******************************************************************************/ -uint32_t Cy_USBFS_Dev_Drv_Ep0Write(USBFS_Type *base, uint8_t const *buffer, uint32_t size, +uint32_t Cy_USBFS_Dev_Drv_Ep0Write(USBFS_Type *base, uint8_t const *buffer, uint32_t size, cy_stc_usbfs_dev_drv_context_t *context) { uint32_t numBytes = 0UL; @@ -1020,7 +1020,7 @@ uint32_t Cy_USBFS_Dev_Drv_Ep0Write(USBFS_Type *base, uint8_t const *buffer, uint /* Updates the data toggle and counter */ context->ep0DataToggle ^= (uint8_t) USBFS_USBDEV_EP0_CNT_DATA_TOGGLE_Msk; - + /* Updates the CNT and CR registers to continue the IN transfer */ Cy_USBFS_Dev_Drv_SetEp0Count (base, numBytes, (uint32_t) context->ep0DataToggle); Cy_USBFS_Dev_Drv_WriteEp0Mode(base, CY_USBFS_DEV_DRV_EP_CR_ACK_IN_STATUS_OUT); @@ -1030,7 +1030,7 @@ uint32_t Cy_USBFS_Dev_Drv_Ep0Write(USBFS_Type *base, uint8_t const *buffer, uint else { /* Status stage (IN): Completes the status stage, sends an ACK handshake */ - + /* Updates the CNT and CR registers to continue the IN transfer */ Cy_USBFS_Dev_Drv_SetEp0Count (base, numBytes, USBFS_USBDEV_EP0_CNT_DATA_TOGGLE_Msk); Cy_USBFS_Dev_Drv_WriteEp0Mode(base, CY_USBFS_DEV_DRV_EP_CR_STATUS_IN_ONLY); @@ -1060,18 +1060,18 @@ uint32_t Cy_USBFS_Dev_Drv_Ep0Write(USBFS_Type *base, uint8_t const *buffer, uint * * \param context * The pointer to the context structure \ref cy_stc_usbfs_dev_drv_context_t -* allocated by the user. The structure is used during the USBFS Device -* operation for internal configuration and data retention. The user must not +* allocated by the user. The structure is used during the USBFS Device +* operation for internal configuration and data retention. The user must not * modify anything in this structure. * *******************************************************************************/ void Cy_USBFS_Dev_Drv_Ep0Read(USBFS_Type *base, uint8_t *buffer, uint32_t size, cy_stc_usbfs_dev_drv_context_t *context) -{ +{ if (0U != size) { /* Data stage (OUT): Prepares to receive data */ - + /* Stores the Endpoint 0 buffer to put read operation results */ context->ep0Buffer = buffer; context->ep0BufferSize = (uint8_t) size; /* The Endpoint 0 max packet is 8 bytes */ @@ -1101,8 +1101,8 @@ void Cy_USBFS_Dev_Drv_Ep0Read(USBFS_Type *base, uint8_t *buffer, uint32_t size, * * \param context * The pointer to the context structure \ref cy_stc_usbfs_dev_drv_context_t -* allocated by the user. The structure is used during the USBFS Device -* operation for internal configuration and data retention. The user must not +* allocated by the user. The structure is used during the USBFS Device +* operation for internal configuration and data retention. The user must not * modify anything in this structure. * * \return @@ -1120,7 +1120,7 @@ uint32_t Cy_USBFS_Dev_Drv_Ep0ReadResult(USBFS_Type const *base, cy_stc_usbfs_dev * Function Name: Cy_USBFS_Dev_Drv_RegisterServiceCallback ****************************************************************************//** * -* Registers a callback function to notify about service events (Bus Reset or +* Registers a callback function to notify about service events (Bus Reset or * Endpoint 0 communication) in \ref Cy_USBFS_Dev_Drv_Interrupt. * To remove callback function, pass NULL as function pointer. * @@ -1135,8 +1135,8 @@ uint32_t Cy_USBFS_Dev_Drv_Ep0ReadResult(USBFS_Type const *base, cy_stc_usbfs_dev * * \param context * The pointer to the context structure \ref cy_stc_usbfs_dev_drv_context_t -* allocated by the user. The structure is used during the USBFS Device -* operation for internal configuration and data retention. The user must not +* allocated by the user. The structure is used during the USBFS Device +* operation for internal configuration and data retention. The user must not * modify anything in this structure. * * \return @@ -1156,19 +1156,19 @@ void Cy_USBFS_Dev_Drv_RegisterServiceCallback(USBFS_Type const *base, case CY_USB_DEV_BUS_RESET: context->busReset = callback; break; - + case CY_USB_DEV_EP0_SETUP: context->ep0Setup = callback; break; - + case CY_USB_DEV_EP0_IN: context->ep0In = callback; break; - + case CY_USB_DEV_EP0_OUT: context->ep0Out = callback; break; - + default: break; } @@ -1178,7 +1178,7 @@ void Cy_USBFS_Dev_Drv_RegisterServiceCallback(USBFS_Type const *base, * Function Name: RestoreDeviceConfiguration ****************************************************************************//** * -* Restores device configuration and data endpoints for the active mode +* Restores device configuration and data endpoints for the active mode * operation. * * \param base @@ -1186,8 +1186,8 @@ void Cy_USBFS_Dev_Drv_RegisterServiceCallback(USBFS_Type const *base, * * \param context * The pointer to the context structure \ref cy_stc_usbfs_dev_drv_context_t -* allocated by the user. The structure is used during the USBFS Device -* operation for internal configuration and data retention. The user must not +* allocated by the user. The structure is used during the USBFS Device +* operation for internal configuration and data retention. The user must not * modify anything in this structure. * *******************************************************************************/ @@ -1230,12 +1230,12 @@ static void RestoreDeviceConfiguration(USBFS_Type *base, * * \param context * The pointer to the context structure \ref cy_stc_usbfs_dev_drv_context_t -* allocated by the user. The structure is used during the USBFS Device -* operation for internal configuration and data retention. The user must not +* allocated by the user. The structure is used during the USBFS Device +* operation for internal configuration and data retention. The user must not * modify anything in this structure. * * \note -* After entering low-power mode, the data that is left in the IN or OUT +* After entering low-power mode, the data that is left in the IN or OUT * endpoint buffers is not restored after a wakeup, and is lost. Therefore, it should * be stored in the SRAM for OUT endpoint or read by the host for the IN endpoint * before entering low-power mode. @@ -1266,8 +1266,8 @@ void Cy_USBFS_Dev_Drv_Suspend(USBFS_Type *base, cy_stc_usbfs_dev_drv_context_t * * * \param context * The pointer to the context structure \ref cy_stc_usbfs_dev_drv_context_t -* allocated by the user. The structure is used during the USBFS Device -* operation for internal configuration and data retention. The user must not +* allocated by the user. The structure is used during the USBFS Device +* operation for internal configuration and data retention. The user must not * modify anything in this structure. * *******************************************************************************/ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_usbfs_dev_drv_io.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_usbfs_dev_drv_io.c index 9e73999444..2ea86e3f9b 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_usbfs_dev_drv_io.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_usbfs_dev_drv_io.c @@ -1,12 +1,12 @@ /***************************************************************************//** * \file cy_usbfs_dev_drv_io.c -* \version 2.20 +* \version 2.20.1 * * Provides data transfer API implementation of the USBFS driver. * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -88,8 +88,8 @@ static void DisableEndpoint(USBFS_Type *base, uint32_t endpoint, cy_stc_usbfs_de * * \param context * The pointer to the context structure \ref cy_stc_usbfs_dev_drv_context_t -* allocated by the user. The structure is used during the USBFS Device -* operation for internal configuration and data retention. The user must not +* allocated by the user. The structure is used during the USBFS Device +* operation for internal configuration and data retention. The user must not * modify anything in this structure. * *******************************************************************************/ @@ -105,7 +105,7 @@ static void DisableEndpoint(USBFS_Type *base, uint32_t endpoint, cy_stc_usbfs_de * Function Name: Cy_USBFS_Dev_Drv_ConfigDevice ****************************************************************************//** * -* Sets the basic device configuration (clears previous configuration). +* Sets the basic device configuration (clears previous configuration). * Call this function after the endpoints were configured to complete the * device configuration. * @@ -114,8 +114,8 @@ static void DisableEndpoint(USBFS_Type *base, uint32_t endpoint, cy_stc_usbfs_de * * \param context * The pointer to the context structure \ref cy_stc_usbfs_dev_drv_context_t -* allocated by the user. The structure is used during the USBFS Device -* operation for internal configuration and data retention. The user must not +* allocated by the user. The structure is used during the USBFS Device +* operation for internal configuration and data retention. The user must not * modify anything in this structure. * *******************************************************************************/ @@ -128,7 +128,7 @@ void Cy_USBFS_Dev_Drv_ConfigDevice(USBFS_Type *base, cy_stc_usbfs_dev_drv_contex if (CY_USBFS_DEV_DRV_EP_MANAGEMENT_DMA_AUTO == context->mode) { autoMemMask = USBFS_USBDEV_ARB_CFG_AUTO_MEM_Msk; - + /* Configure DMA burst size */ USBFS_DEV_DMA_THRES16(base) = DMA_YLOOP_INCREMENT; USBFS_DEV_BUF_SIZE(base) = ENDPOINTS_BUFFER_SIZE; @@ -151,7 +151,7 @@ void Cy_USBFS_Dev_Drv_ConfigDevice(USBFS_Type *base, cy_stc_usbfs_dev_drv_contex * Function Name: Cy_USBFS_Dev_Drv_UnConfigureDevice ****************************************************************************//** * -* Clears device configuration. +* Clears device configuration. * Call this function before setting a configuration or a configuration failure * to set the configuration into the default state. * Alternately, call \ref Cy_USBFS_Dev_Drv_RemoveEndpoint for each active endpoint. @@ -161,8 +161,8 @@ void Cy_USBFS_Dev_Drv_ConfigDevice(USBFS_Type *base, cy_stc_usbfs_dev_drv_contex * * \param context * The pointer to the context structure \ref cy_stc_usbfs_dev_drv_context_t -* allocated by the user. The structure is used during the USBFS Device -* operation for internal configuration and data retention. The user must not +* allocated by the user. The structure is used during the USBFS Device +* operation for internal configuration and data retention. The user must not * modify anything in this structure. * *******************************************************************************/ @@ -172,7 +172,7 @@ void Cy_USBFS_Dev_Drv_UnConfigureDevice(USBFS_Type *base, cy_stc_usbfs_dev_drv_c /* Clears the buffer pointer */ context->curBufAddr = 0U; - + /* Removes all active endpoints */ context->activeEpMask = 0U; @@ -203,8 +203,8 @@ void Cy_USBFS_Dev_Drv_UnConfigureDevice(USBFS_Type *base, cy_stc_usbfs_dev_drv_c * * \param context * The pointer to the context structure \ref cy_stc_usbfs_dev_drv_context_t -* allocated by the user. The structure is used during the USBFS Device -* operation for internal configuration and data retention. The user must not +* allocated by the user. The structure is used during the USBFS Device +* operation for internal configuration and data retention. The user must not * modify anything in this structure. * * \return @@ -218,8 +218,8 @@ cy_en_usbfs_dev_drv_status_t GetEndpointBuffer(uint32_t size, uint32_t *idx, cy_ uint32_t nextBufAddr; /* Get max buffer size */ - bufSize = (CY_USBFS_DEV_DRV_EP_MANAGEMENT_DMA_AUTO != context->mode) ? - CY_USBFS_DEV_DRV_HW_BUFFER_SIZE : + bufSize = (CY_USBFS_DEV_DRV_EP_MANAGEMENT_DMA_AUTO != context->mode) ? + CY_USBFS_DEV_DRV_HW_BUFFER_SIZE : context->epSharedBufSize; /* Gets a next buffer address. Note: the end buffer size must be even for the 16-bit access. */ @@ -244,8 +244,8 @@ cy_en_usbfs_dev_drv_status_t GetEndpointBuffer(uint32_t size, uint32_t *idx, cy_ * Function Name: RestoreEndpointHwBuffer ****************************************************************************//** * -* Restores the endpoint active configuration for -* \ref CY_USBFS_DEV_DRV_EP_MANAGEMENT_CPU and +* Restores the endpoint active configuration for +* \ref CY_USBFS_DEV_DRV_EP_MANAGEMENT_CPU and * \ref CY_USBFS_DEV_DRV_EP_MANAGEMENT_DMA modes. * * \param base @@ -253,18 +253,18 @@ cy_en_usbfs_dev_drv_status_t GetEndpointBuffer(uint32_t size, uint32_t *idx, cy_ * * \param mode * Endpoints management mode. -* +* * \param endpointData * The pointer to the endpoint data structure. * * \param context * The pointer to the context structure \ref cy_stc_usbfs_dev_drv_context_t -* allocated by the user. The structure is used during the USBFS Device -* operation for internal configuration and data retention. The user must not +* allocated by the user. The structure is used during the USBFS Device +* operation for internal configuration and data retention. The user must not * modify anything in this structure. * *******************************************************************************/ -void RestoreEndpointHwBuffer(USBFS_Type *base, +void RestoreEndpointHwBuffer(USBFS_Type *base, cy_en_usbfs_dev_drv_ep_management_mode_t mode, cy_stc_usbfs_dev_drv_endpoint_data_t *endpointData) { @@ -299,11 +299,11 @@ void RestoreEndpointHwBuffer(USBFS_Type *base, } /* Enables the SIE interrupt for the endpoint */ - Cy_USBFS_Dev_Drv_EnableSieEpInterrupt(base, endpoint); + Cy_USBFS_Dev_Drv_EnableSieEpInterrupt(base, endpoint); /* Sets an arbiter configuration */ Cy_USBFS_Dev_Drv_SetArbEpConfig(base, endpoint, (USBFS_USBDEV_ARB_EP1_CFG_CRC_BYPASS_Msk | - USBFS_USBDEV_ARB_EP1_CFG_RESET_PTR_Msk)); + USBFS_USBDEV_ARB_EP1_CFG_RESET_PTR_Msk)); /* Set endpoint mode to not respond to host */ Cy_USBFS_Dev_Drv_SetSieEpMode(base, endpoint, GetEndpointInactiveMode((uint32_t) endpointData->sieMode)); @@ -314,8 +314,8 @@ void RestoreEndpointHwBuffer(USBFS_Type *base, * Function Name: AddEndpointHwBuffer ****************************************************************************//** * -* Implements \ref Cy_USBFS_Dev_Drv_AddEndpoint for -* \ref CY_USBFS_DEV_DRV_EP_MANAGEMENT_CPU and +* Implements \ref Cy_USBFS_Dev_Drv_AddEndpoint for +* \ref CY_USBFS_DEV_DRV_EP_MANAGEMENT_CPU and * \ref CY_USBFS_DEV_DRV_EP_MANAGEMENT_DMA modes. * * \param base @@ -326,8 +326,8 @@ void RestoreEndpointHwBuffer(USBFS_Type *base, * * \param context * The pointer to the context structure \ref cy_stc_usbfs_dev_drv_context_t -* allocated by the user. The structure is used during the USBFS Device -* operation for internal configuration and data retention. The user must not +* allocated by the user. The structure is used during the USBFS Device +* operation for internal configuration and data retention. The user must not * modify anything in this structure. * * \return @@ -341,7 +341,7 @@ cy_en_usbfs_dev_drv_status_t AddEndpointHwBuffer(USBFS_Type *base, uint32_t endpoint = EPADDR2PHY(config->endpointAddr); /* Gets a pointer to the endpoint data */ - cy_stc_usbfs_dev_drv_endpoint_data_t *endpointData = &context->epPool[endpoint]; + cy_stc_usbfs_dev_drv_endpoint_data_t *endpointData = &context->epPool[endpoint]; /* Gets a buffer for the endpoint using the hardware buffer */ if (config->allocBuffer) @@ -378,8 +378,8 @@ cy_en_usbfs_dev_drv_status_t AddEndpointHwBuffer(USBFS_Type *base, Cy_USBFS_Dev_Drv_SetArbEpConfig(base, endpoint, (USBFS_USBDEV_ARB_EP1_CFG_CRC_BYPASS_Msk | USBFS_USBDEV_ARB_EP1_CFG_RESET_PTR_Msk)); - /* Flushes the IN endpoint buffer to discard the loaded data. - * It happens when: an alternate settings change is requested and the IN + /* Flushes the IN endpoint buffer to discard the loaded data. + * It happens when: an alternate settings change is requested and the IN * endpoint buffer is full (not read by the Host). */ if (inDirection) @@ -436,8 +436,8 @@ cy_en_usbfs_dev_drv_status_t AddEndpointHwBuffer(USBFS_Type *base, * * \param context * The pointer to the context structure \ref cy_stc_usbfs_dev_drv_context_t -* allocated by the user. The structure is used during the USBFS Device -* operation for internal configuration and data retention. The user must not +* allocated by the user. The structure is used during the USBFS Device +* operation for internal configuration and data retention. The user must not * modify anything in this structure. * * \return @@ -493,8 +493,8 @@ cy_en_usbfs_dev_drv_status_t Cy_USBFS_Dev_Drv_RemoveEndpoint(USBFS_Type *base, * * \param context * The pointer to the context structure \ref cy_stc_usbfs_dev_drv_context_t -* allocated by the user. The structure is used during the USBFS Device -* operation for internal configuration and data retention. The user must not +* allocated by the user. The structure is used during the USBFS Device +* operation for internal configuration and data retention. The user must not * modify anything in this structure. * * \return @@ -519,7 +519,7 @@ void Cy_USBFS_Dev_Drv_EnableOutEndpoint(USBFS_Type *base, /* Clear abort mask for the endpoint (there is no transfer during abort) */ context->epAbortMask &= (uint8_t) ~EP2MASK(endpoint); - + /* Endpoint pending: Waits for the host write data after exiting this function */ endpointData->state = CY_USB_DEV_EP_PENDING; @@ -532,7 +532,7 @@ void Cy_USBFS_Dev_Drv_EnableOutEndpoint(USBFS_Type *base, * Function Name: LoadInEndpointCpu ****************************************************************************//** * -* Implements \ref Cy_USBFS_Dev_Drv_LoadInEndpoint for +* Implements \ref Cy_USBFS_Dev_Drv_LoadInEndpoint for * \ref CY_USBFS_DEV_DRV_EP_MANAGEMENT_CPU mode. * * \param base @@ -550,8 +550,8 @@ void Cy_USBFS_Dev_Drv_EnableOutEndpoint(USBFS_Type *base, * * \param context * The pointer to the context structure \ref cy_stc_usbfs_dev_drv_context_t -* allocated by the user. The structure is used during the USBFS Device -* operation for internal configuration and data retention. The user must not +* allocated by the user. The structure is used during the USBFS Device +* operation for internal configuration and data retention. The user must not * modify anything in this structure. * * \return @@ -581,7 +581,7 @@ cy_en_usbfs_dev_drv_status_t LoadInEndpointCpu(USBFS_Type *base, /* Set count and data toggle */ Cy_USBFS_Dev_Drv_SetSieEpCount(base, endpoint, size, (uint32_t) endpointData->toggle); - + if (0U == size) { /* Arm endpoint: endpoint ACK Host request */ @@ -627,7 +627,7 @@ cy_en_usbfs_dev_drv_status_t LoadInEndpointCpu(USBFS_Type *base, * Function Name: ReadOutEndpointCpu ****************************************************************************//** * -* Implements \ref Cy_USBFS_Dev_Drv_ReadOutEndpoint for +* Implements \ref Cy_USBFS_Dev_Drv_ReadOutEndpoint for * \ref CY_USBFS_DEV_DRV_EP_MANAGEMENT_CPU mode. * * \param base @@ -648,8 +648,8 @@ cy_en_usbfs_dev_drv_status_t LoadInEndpointCpu(USBFS_Type *base, * * \param context * The pointer to the context structure \ref cy_stc_usbfs_dev_drv_context_t -* allocated by the user. The structure is used during the USBFS Device -* operation for internal configuration and data retention. The user must not +* allocated by the user. The structure is used during the USBFS Device +* operation for internal configuration and data retention. The user must not * modify anything in this structure. * * \return @@ -674,7 +674,7 @@ cy_en_usbfs_dev_drv_status_t ReadOutEndpointCpu(USBFS_Type *base, /* Initialize actual number of copied bytes */ *actSize = 0U; - + /* Endpoint received more bytes than provided buffer */ if (numToCopy > size) { @@ -723,7 +723,7 @@ cy_en_usbfs_dev_drv_status_t ReadOutEndpointCpu(USBFS_Type *base, * * Abort operation for data endpoint. * If there is any bus activity after the abort operation requested, the function -* waits for its completion or a timeout. A timeout is the time to transfer the +* waits for its completion or a timeout. A timeout is the time to transfer the * bulk or an interrupt packet of the maximum playload size. If this bus activity is * a transfer to the aborting endpoint, the received data is lost and the endpoint * transfer completion callbacks are not invoked. @@ -737,8 +737,8 @@ cy_en_usbfs_dev_drv_status_t ReadOutEndpointCpu(USBFS_Type *base, * * \param context * The pointer to the context structure \ref cy_stc_usbfs_dev_drv_context_t -* allocated by the user. The structure is used during the USBFS Device -* operation for internal configuration and data retention. The user must not +* allocated by the user. The structure is used during the USBFS Device +* operation for internal configuration and data retention. The user must not * modify anything in this structure. * * \return @@ -791,7 +791,7 @@ cy_en_usbfs_dev_drv_status_t Cy_USBFS_Dev_Drv_Abort(USBFS_Type *base, /* Sets an abort mask to discard the completion events */ context->epAbortMask |= (uint8_t) EP2MASK(endpoint); endpointData->state = CY_USB_DEV_EP_IDLE; - + /* Clears the bus busy activity */ (void) Cy_USBFS_Dev_Drv_CheckActivity(base); @@ -808,7 +808,7 @@ cy_en_usbfs_dev_drv_status_t Cy_USBFS_Dev_Drv_Abort(USBFS_Type *base, /* Does not wait for the ISOC endpoint */ isocEp = true; } - + if (false == isocEp) { /* If there is a bus activity, it could be a transfer to the aborted endpoint */ @@ -834,7 +834,7 @@ cy_en_usbfs_dev_drv_status_t Cy_USBFS_Dev_Drv_Abort(USBFS_Type *base, } } - /* The abort mask is cleared in the endpoint completion interrupt OR + /* The abort mask is cleared in the endpoint completion interrupt OR * on a following call of the endpoint Remove, LoadIn or EnableOut function. */ } @@ -844,21 +844,21 @@ cy_en_usbfs_dev_drv_status_t Cy_USBFS_Dev_Drv_Abort(USBFS_Type *base, flushBuffer = false; retStatus = CY_USBFS_DEV_DRV_SUCCESS; } - + /* Releases the lock */ Cy_SysLib_ExitCriticalSection(intrState); if (flushBuffer) { bool inDirection = IS_EP_DIR_IN(endpointData->address); - + /* Initializes the pointers to functions that work with the data endpoint */ switch(context->mode) { case CY_USBFS_DEV_DRV_EP_MANAGEMENT_CPU: case CY_USBFS_DEV_DRV_EP_MANAGEMENT_DMA: { - /* IN endpoint: Flushes the buffer to discard the loaded data. + /* IN endpoint: Flushes the buffer to discard the loaded data. * OUT endpoint: Leaves the written data in the buffer. */ if (inDirection) @@ -872,7 +872,7 @@ cy_en_usbfs_dev_drv_status_t Cy_USBFS_Dev_Drv_Abort(USBFS_Type *base, case CY_USBFS_DEV_DRV_EP_MANAGEMENT_DMA_AUTO: { - /* IN endpoint: Flushes the buffer to discard the loaded data. + /* IN endpoint: Flushes the buffer to discard the loaded data. * OUT endpoint: Waits for DMA to complete if a transfer has been started. */ retStatus = DynamicEndpointReConfiguration(base, inDirection, endpoint); @@ -902,8 +902,8 @@ cy_en_usbfs_dev_drv_status_t Cy_USBFS_Dev_Drv_Abort(USBFS_Type *base, * * \param context * The pointer to the context structure \ref cy_stc_usbfs_dev_drv_context_t -* allocated by the user. The structure is used during the USBFS Device -* operation for internal configuration and data retention. The user must not +* allocated by the user. The structure is used during the USBFS Device +* operation for internal configuration and data retention. The user must not * modify anything in this structure. * * \return @@ -957,8 +957,8 @@ cy_en_usbfs_dev_drv_status_t Cy_USBFS_Dev_Drv_StallEndpoint(USBFS_Type *base, * * \param context * The pointer to the context structure \ref cy_stc_usbfs_dev_drv_context_t -* allocated by the user. The structure is used during the USBFS Device -* operation for internal configuration and data retention. The user must not +* allocated by the user. The structure is used during the USBFS Device +* operation for internal configuration and data retention. The user must not * modify anything in this structure. * * \return diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_usbfs_dev_drv_io_dma.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_usbfs_dev_drv_io_dma.c index d264894730..a352f0861d 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_usbfs_dev_drv_io_dma.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_usbfs_dev_drv_io_dma.c @@ -1,12 +1,12 @@ /***************************************************************************//** * \file cy_usbfs_dev_drv_io_dma.c -* \version 2.20 +* \version 2.20.1 * * Provides data transfer API implementation of the USBFS driver. * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -72,17 +72,17 @@ extern "C" { * Internal Functions Prototypes *******************************************************************************/ -static void DmaEndpointInit1D(cy_stc_dma_descriptor_t *descr, - bool inDirection, - cy_en_dma_data_size_t dataSize, +static void DmaEndpointInit1D(cy_stc_dma_descriptor_t *descr, + bool inDirection, + cy_en_dma_data_size_t dataSize, volatile uint32_t const *dataReg); -static void DmaEndpointInit2D(cy_stc_dma_descriptor_t *descr, - bool inDirection, +static void DmaEndpointInit2D(cy_stc_dma_descriptor_t *descr, + bool inDirection, int32_t numElements); -static void DmaEndpointSetLength(bool inDirection, - uint32_t size, +static void DmaEndpointSetLength(bool inDirection, + uint32_t size, cy_stc_usbfs_dev_drv_endpoint_data_t *endpoint); @@ -148,8 +148,8 @@ static void DmaEndpointSetLength(bool inDirection, * * \param context * The pointer to the context structure \ref cy_stc_usbfs_dev_drv_context_t -* allocated by the user. The structure is used during the USBFS Device -* operation for internal configuration and data retention. The user must not +* allocated by the user. The structure is used during the USBFS Device +* operation for internal configuration and data retention. The user must not * modify anything in this structure. * * \return @@ -176,7 +176,7 @@ cy_en_usbfs_dev_drv_status_t DmaInit(cy_stc_usbfs_dev_drv_config_t const *config cy_en_usbfs_dev_drv_status_t locStatus = CY_USBFS_DEV_DRV_DMA_CFG_FAILED; cy_stc_dma_channel_config_t chConfig; - + /* Descriptors configurations */ const cy_stc_dma_descriptor_config_t DmaDescr1DCfg = DMA_DESCR_1D_CFG; const cy_stc_dma_descriptor_config_t DmaDescr2DCfg = DMA_DESCR_2D_CFG; @@ -193,7 +193,7 @@ cy_en_usbfs_dev_drv_status_t DmaInit(cy_stc_usbfs_dev_drv_config_t const *config { if (NULL != endpointData->descr0) { - /* Initialize DMA descriptor 0 for 1D operation. + /* Initialize DMA descriptor 0 for 1D operation. * Discard return because descriptor configuration (defined in driver) is valid. */ (void) Cy_DMA_Descriptor_Init(endpointData->descr0, &DmaDescr1DCfg); @@ -205,13 +205,13 @@ cy_en_usbfs_dev_drv_status_t DmaInit(cy_stc_usbfs_dev_drv_config_t const *config { if ((NULL != endpointData->descr0) && (NULL != endpointData->descr1)) { - /* Initialize DMA descriptor 0 for 2D operation. + /* Initialize DMA descriptor 0 for 2D operation. * Discard return because descriptor configuration (defined in driver) is valid. */ (void) Cy_DMA_Descriptor_Init(endpointData->descr0, &DmaDescr2DCfg); - - /* Initialize DMA descriptor 0 for 1D operation. + + /* Initialize DMA descriptor 0 for 1D operation. * Discard return because descriptor configuration (defined in driver) is valid. */ (void)Cy_DMA_Descriptor_Init(endpointData->descr1, &DmaDescr1DCfg); @@ -260,13 +260,13 @@ cy_en_usbfs_dev_drv_status_t DmaInit(cy_stc_usbfs_dev_drv_config_t const *config * Function Name: DmaDisable ****************************************************************************//** * -* Disables all DMA channels used by the USBFS Device. +* Disables all DMA channels used by the USBFS Device. * The channel state is not verified before being disabled. * * \param context * The pointer to the context structure \ref cy_stc_usbfs_dev_drv_context_t -* allocated by the user. The structure is used during the USBFS Device -* operation for internal configuration and data retention. The user must not +* allocated by the user. The structure is used during the USBFS Device +* operation for internal configuration and data retention. The user must not * modify anything in this structure. * *******************************************************************************/ @@ -304,7 +304,7 @@ void DmaDisable(cy_stc_usbfs_dev_drv_context_t *context) * The pointer to the data endpoint data register. * *******************************************************************************/ -static void DmaEndpointInit1D(cy_stc_dma_descriptor_t *descr, bool inDirection, +static void DmaEndpointInit1D(cy_stc_dma_descriptor_t *descr, bool inDirection, cy_en_dma_data_size_t dataSize, volatile uint32_t const *dataReg) { Cy_DMA_Descriptor_SetDataSize(descr, dataSize); @@ -331,7 +331,7 @@ static void DmaEndpointInit1D(cy_stc_dma_descriptor_t *descr, bool inDirection, } /* Link descriptor to itself */ - Cy_DMA_Descriptor_SetNextDescriptor(descr, descr); + Cy_DMA_Descriptor_SetNextDescriptor(descr, descr); } @@ -351,11 +351,11 @@ static void DmaEndpointInit1D(cy_stc_dma_descriptor_t *descr, bool inDirection, * Number of elements to transfer. * *******************************************************************************/ -static void DmaEndpointInit2D(cy_stc_dma_descriptor_t *descr, bool inDirection, +static void DmaEndpointInit2D(cy_stc_dma_descriptor_t *descr, bool inDirection, int32_t numElements) { - /* Descriptor 0 (2D): it transfers number of data elements (X loop count) - * and increments source/destination (depends on direction) by this amount + /* Descriptor 0 (2D): it transfers number of data elements (X loop count) + * and increments source/destination (depends on direction) by this amount * (Y loop increment). */ Cy_DMA_Descriptor_SetXloopDataCount(descr, (uint32_t) numElements); @@ -384,11 +384,11 @@ static void DmaEndpointInit2D(cy_stc_dma_descriptor_t *descr, bool inDirection, * The pointer to the structure that stores endpoint information. * *******************************************************************************/ -static void DmaEndpointSetLength(bool inDirection, uint32_t size, +static void DmaEndpointSetLength(bool inDirection, uint32_t size, cy_stc_usbfs_dev_drv_endpoint_data_t *endpoint) { uint8_t *buf = endpoint->buffer; - + /* * Descriptor 0: get number of Y loops. It transfers data in multiples of 32 bytes. * Descriptor 1: get number of X loops. It transfers data what was left 1-31 bytes. @@ -417,7 +417,7 @@ static void DmaEndpointSetLength(bool inDirection, uint32_t size, } if (numXloops > 0UL) - { + { Cy_DMA_Descriptor_SetXloopDataCount(endpoint->descr1, numXloops); } @@ -438,25 +438,25 @@ static void DmaEndpointSetLength(bool inDirection, uint32_t size, Cy_DMA_Descriptor_SetNextDescriptor(endpoint->descr0, endpoint->descr1); Cy_DMA_Descriptor_SetNextDescriptor(endpoint->descr1, endpoint->descr0); } - + /* Keep channel enabled after execution of Descriptor 0 to execute Descriptor 1 */ Cy_DMA_Descriptor_SetChannelState(endpoint->descr0, ((numYloops > 0UL) && (numXloops > 0UL)) ? CY_DMA_CHANNEL_ENABLED : CY_DMA_CHANNEL_DISABLED); - + /* Start execution from Descriptor 0 (length >= 32) or Descriptor 1 (length < 32) */ Cy_DMA_Channel_SetDescriptor(endpoint->base, endpoint->chNum, ((numYloops > 0UL) ? endpoint->descr0 : endpoint->descr1)); - + /* Configuration complete: enable channel */ Cy_DMA_Channel_Enable(endpoint->base, endpoint->chNum); } - + /******************************************************************************* * Function Name: DmaOutEndpointRestore ****************************************************************************//** -* +* * Restores the DMA channel after transfer is completed for the the OUT data endpoint. * Applicable only when mode is \ref CY_USBFS_DEV_DRV_EP_MANAGEMENT_DMA_AUTO. * @@ -500,17 +500,17 @@ void DmaOutEndpointRestore(cy_stc_usbfs_dev_drv_endpoint_data_t *endpoint) * * \param context * The pointer to the context structure \ref cy_stc_usbfs_dev_drv_context_t -* allocated by the user. The structure is used during the USBFS Device -* operation for internal configuration and data retention. The user must not +* allocated by the user. The structure is used during the USBFS Device +* operation for internal configuration and data retention. The user must not * modify anything in this structure. * * \return * Status code of the function execution \ref cy_en_usbfs_dev_drv_status_t. * *******************************************************************************/ -cy_en_usbfs_dev_drv_status_t DmaEndpointInit(USBFS_Type *base, - cy_en_usbfs_dev_drv_ep_management_mode_t mode, - bool useReg16, +cy_en_usbfs_dev_drv_status_t DmaEndpointInit(USBFS_Type *base, + cy_en_usbfs_dev_drv_ep_management_mode_t mode, + bool useReg16, cy_stc_usbfs_dev_drv_endpoint_data_t *endpointData) { cy_en_dma_data_size_t regSize; @@ -578,8 +578,8 @@ cy_en_usbfs_dev_drv_status_t DmaEndpointInit(USBFS_Type *base, * * \param endpoint * The data endpoint number. -* -* \return +* +* \return * Status code of the function execution \ref cy_en_usbfs_dev_drv_status_t. * *******************************************************************************/ @@ -625,7 +625,7 @@ cy_en_usbfs_dev_drv_status_t DynamicEndpointReConfiguration(USBFS_Type *base, /* Clear register for next re-configuration */ USBFS_DEV_DYN_RECONFIG(base) = 0U; - + return retStatus; } @@ -634,7 +634,7 @@ cy_en_usbfs_dev_drv_status_t DynamicEndpointReConfiguration(USBFS_Type *base, * Function Name: AddEndpointRamBuffer ****************************************************************************//** * -* Implements \ref Cy_USBFS_Dev_Drv_AddEndpoint for +* Implements \ref Cy_USBFS_Dev_Drv_AddEndpoint for * \ref CY_USBFS_DEV_DRV_EP_MANAGEMENT_DMA_AUTO mode. * * \param base @@ -645,8 +645,8 @@ cy_en_usbfs_dev_drv_status_t DynamicEndpointReConfiguration(USBFS_Type *base, * * \param context * The pointer to the context structure \ref cy_stc_usbfs_dev_drv_context_t -* allocated by the user. The structure is used during the USBFS Device -* operation for internal configuration and data retention. The user must not +* allocated by the user. The structure is used during the USBFS Device +* operation for internal configuration and data retention. The user must not * modify anything in this structure. * * \return @@ -672,7 +672,7 @@ cy_en_usbfs_dev_drv_status_t AddEndpointRamBuffer(USBFS_Type *base, /* Configure active endpoint */ context->activeEpMask |= (uint8_t) EP2MASK(endpont); USBFS_DEV_EP_ACTIVE(base) = context->activeEpMask; - + /* Allocate buffer for endpoint */ retStatus = GetEndpointBuffer((uint32_t) config->bufferSize, &startBufIdx, context); if (CY_USBFS_DEV_DRV_SUCCESS != retStatus) @@ -688,7 +688,7 @@ cy_en_usbfs_dev_drv_status_t AddEndpointRamBuffer(USBFS_Type *base, if (config->enableEndpoint) { bool inDirection = IS_EP_DIR_IN(config->endpointAddr); - + /* Clear variables related to endpoint */ endpointData->state = CY_USB_DEV_EP_IDLE; endpointData->address = config->endpointAddr; @@ -701,7 +701,7 @@ cy_en_usbfs_dev_drv_status_t AddEndpointRamBuffer(USBFS_Type *base, Cy_USBFS_Dev_Drv_SetArbEpConfig(base, endpoint, (USBFS_USBDEV_ARB_EP1_CFG_CRC_BYPASS_Msk | USBFS_USBDEV_ARB_EP1_CFG_RESET_PTR_Msk)); - /* Performs dynamic reconfiguration to make sure that the DMA has completed the data transfer. + /* Performs dynamic reconfiguration to make sure that the DMA has completed the data transfer. * Also it flushes endpoint pre-fetch buffer (useful for IN endpoints). */ retStatus = DynamicEndpointReConfiguration(base, inDirection, endpoint); @@ -709,14 +709,14 @@ cy_en_usbfs_dev_drv_status_t AddEndpointRamBuffer(USBFS_Type *base, { return retStatus; } - + /* Configure DMA for endpoint */ retStatus = DmaEndpointInit(base, context->mode, context->useReg16, endpointData); if (CY_USBFS_DEV_DRV_SUCCESS != retStatus) { return retStatus; } - + /* Enable Arbiter interrupt sources for endpoint */ Cy_USBFS_Dev_Drv_SetArbEpInterruptMask(base, endpoint,(inDirection ? IN_ENDPOINT_ARB_INTR_SOURCES : @@ -738,7 +738,7 @@ cy_en_usbfs_dev_drv_status_t AddEndpointRamBuffer(USBFS_Type *base, * Function Name: RestoreEndpointRamBuffer ****************************************************************************//** * -* Restores endpoint active configuration for +* Restores endpoint active configuration for * \ref CY_USBFS_DEV_DRV_EP_MANAGEMENT_DMA_AUTO mode. * * \param base @@ -749,12 +749,12 @@ cy_en_usbfs_dev_drv_status_t AddEndpointRamBuffer(USBFS_Type *base, * * \param context * The pointer to the context structure \ref cy_stc_usbfs_dev_drv_context_t -* allocated by the user. The structure is used during the USBFS Device -* operation for internal configuration and data retention. The user must not +* allocated by the user. The structure is used during the USBFS Device +* operation for internal configuration and data retention. The user must not * modify anything in this structure. * *******************************************************************************/ -void RestoreEndpointRamBuffer(USBFS_Type *base, +void RestoreEndpointRamBuffer(USBFS_Type *base, cy_stc_usbfs_dev_drv_endpoint_data_t *endpointData) { bool inDirection = IS_EP_DIR_IN(endpointData->address); @@ -773,14 +773,14 @@ void RestoreEndpointRamBuffer(USBFS_Type *base, Cy_USBFS_Dev_Drv_SetArbEpInterruptMask(base, endpoint, (inDirection ? IN_ENDPOINT_ARB_INTR_SOURCES : OUT_ENDPOINT_ARB_INTR_SOURCES)); - + /* Enable SIE and arbiter interrupt for endpoint */ Cy_USBFS_Dev_Drv_EnableSieEpInterrupt(base, endpoint); Cy_USBFS_Dev_Drv_EnableArbEpInterrupt(base, endpoint); if (false == inDirection) { - /* OUT Endpoint: enable DMA channel endpoint ready for operation. + /* OUT Endpoint: enable DMA channel endpoint ready for operation. * IN Endpoint: keep disabled, it is enabled in LoadInEndpointDmaAuto. */ Cy_DMA_Channel_Enable(endpointData->base, endpointData->chNum); @@ -799,7 +799,7 @@ void RestoreEndpointRamBuffer(USBFS_Type *base, * Function Name: LoadInEndpointDma ****************************************************************************//** * -* Implements \ref Cy_USBFS_Dev_Drv_LoadInEndpoint for +* Implements \ref Cy_USBFS_Dev_Drv_LoadInEndpoint for * \ref CY_USBFS_DEV_DRV_EP_MANAGEMENT_DMA mode. * * \param base @@ -817,8 +817,8 @@ void RestoreEndpointRamBuffer(USBFS_Type *base, * * \param context * The pointer to the context structure \ref cy_stc_usbfs_dev_drv_context_t -* allocated by the user. The structure is used during the USBFS Device -* operation for internal configuration and data retention. The user must not +* allocated by the user. The structure is used during the USBFS Device +* operation for internal configuration and data retention. The user must not * modify anything in this structure. * * \return @@ -861,7 +861,7 @@ cy_en_usbfs_dev_drv_status_t LoadInEndpointDma(USBFS_Type *base, else { /* Channel is disabled after initialization or descriptor completion */ - + uint32_t timeout = DMA_WRITE_REQUEST_TIMEOUT; /* Get number of data elements to transfer */ @@ -874,16 +874,16 @@ cy_en_usbfs_dev_drv_status_t LoadInEndpointDma(USBFS_Type *base, /* Enable DMA channel: configuration complete */ Cy_DMA_Channel_Enable(endpointData->base, endpointData->chNum); - /* Generate DMA request: the endpoint will be armed when the DMA is - * finished in the Arbiter interrupt + /* Generate DMA request: the endpoint will be armed when the DMA is + * finished in the Arbiter interrupt */ Cy_USBFS_Dev_Drv_TriggerArbCfgEpDmaReq(base, endpoint); - /* Waits until DMA completes the write operation. The current endpoint state is - * idle or completed and DMA completion interrupt changes state to pending + /* Waits until DMA completes the write operation. The current endpoint state is + * idle or completed and DMA completion interrupt changes state to pending * (endpoint waits for the host read data). */ - while ((CY_USB_DEV_EP_PENDING != endpointData->state) && + while ((CY_USB_DEV_EP_PENDING != endpointData->state) && (timeout > 0U)) { Cy_SysLib_DelayUs(DMA_WRITE_REQUEST_ONE_TICK); @@ -905,7 +905,7 @@ cy_en_usbfs_dev_drv_status_t LoadInEndpointDma(USBFS_Type *base, * Function Name: ReadOutEndpointDma ****************************************************************************//** * -* Implements \ref Cy_USBFS_Dev_Drv_ReadOutEndpoint for +* Implements \ref Cy_USBFS_Dev_Drv_ReadOutEndpoint for * \ref CY_USBFS_DEV_DRV_EP_MANAGEMENT_DMA mode. * * \param base @@ -926,8 +926,8 @@ cy_en_usbfs_dev_drv_status_t LoadInEndpointDma(USBFS_Type *base, * * \param context * The pointer to the context structure \ref cy_stc_usbfs_dev_drv_context_t -* allocated by the user. The structure is used during the USBFS Device -* operation for internal configuration and data retention. The user must not +* allocated by the user. The structure is used during the USBFS Device +* operation for internal configuration and data retention. The user must not * modify anything in this structure. * * \return @@ -966,7 +966,7 @@ cy_en_usbfs_dev_drv_status_t ReadOutEndpointDma(USBFS_Type *base, { return CY_USBFS_DEV_DRV_SUCCESS; } - + /* Channel is disabled after initialization or descriptor completion */ /* Get number of data elements to transfer */ @@ -1011,7 +1011,7 @@ cy_en_usbfs_dev_drv_status_t ReadOutEndpointDma(USBFS_Type *base, * Function Name: LoadInEndpointDmaAuto ****************************************************************************//** * -* Implements \ref Cy_USBFS_Dev_Drv_LoadInEndpoint for +* Implements \ref Cy_USBFS_Dev_Drv_LoadInEndpoint for * \ref CY_USBFS_DEV_DRV_EP_MANAGEMENT_DMA_AUTO mode. * * \param base @@ -1029,8 +1029,8 @@ cy_en_usbfs_dev_drv_status_t ReadOutEndpointDma(USBFS_Type *base, * * \param context * The pointer to the context structure \ref cy_stc_usbfs_dev_drv_context_t -* allocated by the user. The structure is used during the USBFS Device -* operation for internal configuration and data retention. The user must not +* allocated by the user. The structure is used during the USBFS Device +* operation for internal configuration and data retention. The user must not * modify anything in this structure. * * \return @@ -1057,7 +1057,7 @@ cy_en_usbfs_dev_drv_status_t LoadInEndpointDmaAuto(USBFS_Type *base, /* Endpoint pending: Waits for the host read data after exiting this function */ endpointData->state = CY_USB_DEV_EP_PENDING; - + /* Set count and data toggle */ Cy_USBFS_Dev_Drv_SetSieEpCount(base, endpoint, size, (uint32_t) endpointData->toggle); @@ -1087,8 +1087,8 @@ cy_en_usbfs_dev_drv_status_t LoadInEndpointDmaAuto(USBFS_Type *base, else { /* Reset DMA channel indexes, they keep value after Resume or Abort */ - Cy_DMA_Channel_SetDescriptor(endpointData->base, endpointData->chNum, - (endpointData->startBuf >= (uint32_t) DMA_YLOOP_INCREMENT) ? + Cy_DMA_Channel_SetDescriptor(endpointData->base, endpointData->chNum, + (endpointData->startBuf >= (uint32_t) DMA_YLOOP_INCREMENT) ? endpointData->descr0 : endpointData->descr1); /* Enable channel: configuration complete */ @@ -1111,7 +1111,7 @@ cy_en_usbfs_dev_drv_status_t LoadInEndpointDmaAuto(USBFS_Type *base, * Function Name: ReadOutEndpointDmaAuto ****************************************************************************//** * -* Implements \ref Cy_USBFS_Dev_Drv_ReadOutEndpoint for +* Implements \ref Cy_USBFS_Dev_Drv_ReadOutEndpoint for * \ref CY_USBFS_DEV_DRV_EP_MANAGEMENT_DMA_AUTO mode. * * \param base @@ -1132,8 +1132,8 @@ cy_en_usbfs_dev_drv_status_t LoadInEndpointDmaAuto(USBFS_Type *base, * * \param context * The pointer to the context structure \ref cy_stc_usbfs_dev_drv_context_t -* allocated by the user. The structure is used during the USBFS Device -* operation for internal configuration and data retention. The user must not +* allocated by the user. The structure is used during the USBFS Device +* operation for internal configuration and data retention. The user must not * modify anything in this structure. * * \return @@ -1149,13 +1149,13 @@ cy_en_usbfs_dev_drv_status_t ReadOutEndpointDmaAuto(USBFS_Type *base, { /* Get pointer to endpoint data */ cy_stc_usbfs_dev_drv_endpoint_data_t *endpointData = &context->epPool[endpoint]; - + /* Get number of received bytes */ uint32_t numToCopy = Cy_USBFS_Dev_Drv_GetSieEpCount(base, endpoint); - + /* Initialize actual number of copied bytes */ *actSize = 0U; - + /* Endpoint received more bytes than provided buffer */ if (numToCopy > size) { @@ -1177,10 +1177,10 @@ cy_en_usbfs_dev_drv_status_t ReadOutEndpointDmaAuto(USBFS_Type *base, { (void) memcpy(buffer, endpointData->buffer, numToCopy); } - + /* Update number of copied bytes */ - *actSize = numToCopy; - + *actSize = numToCopy; + return CY_USBFS_DEV_DRV_SUCCESS; } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_wdt.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_wdt.c index c8789b502e..1854f2e453 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_wdt.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_wdt.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_wdt.c -* \version 1.20 +* \version 1.30 * * This file provides the source code to the API for the WDT driver. * @@ -28,7 +28,6 @@ extern "C" { #endif -static bool Cy_WDT_Locked(void); /******************************************************************************* @@ -40,7 +39,7 @@ static bool Cy_WDT_Locked(void); * The given default setting of the WDT: * The WDT is unlocked and disabled. * The WDT match value is 4096. -* None of ignore bits are set: the whole WDT counter bits are checked against +* None of ignore bits are set: the whole WDT counter bits are checked against * the match value. * * \sideeffect @@ -66,7 +65,7 @@ void Cy_WDT_Init(void) * * Locks out configuration changes to the Watchdog Timer register. * -* After this function is called, the WDT configuration cannot be changed until +* After this function is called, the WDT configuration cannot be changed until * Cy_WDT_Unlock() is called. * * \warning @@ -83,15 +82,15 @@ void Cy_WDT_Lock(void) /******************************************************************************* * Function Name: Cy_WDT_Locked ****************************************************************************//** -* -* Internal function that returns the WDT lock state. +* +* Returns the WDT lock state. * * \return * True - if WDT is locked. * False - if WDT is unlocked. -* +* *******************************************************************************/ -static bool Cy_WDT_Locked(void) +bool Cy_WDT_Locked(void) { /* Prohibits writing to the WDT registers and other CLK_LF */ return (0u != _FLD2VAL(SRSS_WDT_CTL_WDT_LOCK, SRSS_WDT_CTL)); @@ -122,19 +121,19 @@ void Cy_WDT_Unlock(void) * Function Name: Cy_WDT_SetMatch ****************************************************************************//** * -* Configures the WDT counter match comparison value. The Watchdog timer -* should be unlocked before changing the match value. Call the Cy_WDT_Unlock() +* Configures the WDT counter match comparison value. The Watchdog timer +* should be unlocked before changing the match value. Call the Cy_WDT_Unlock() * function to unlock the WDT. * * \param match -* The valid valid range is [0-65535]. The value to be used to match +* The valid valid range is [0-65535]. The value to be used to match * against the counter. * *******************************************************************************/ void Cy_WDT_SetMatch(uint32_t match) { CY_ASSERT_L2(CY_WDT_IS_MATCH_VAL_VALID(match)); - + if (false == Cy_WDT_Locked()) { SRSS_WDT_MATCH = _CLR_SET_FLD32U((SRSS_WDT_MATCH), SRSS_WDT_MATCH_MATCH, match); @@ -146,8 +145,8 @@ void Cy_WDT_SetMatch(uint32_t match) * Function Name: Cy_WDT_SetIgnoreBits ****************************************************************************//** * -* Configures the number of the most significant bits of the Watchdog timer that -* are not checked against the match. Unlock the Watchdog timer before +* Configures the number of the most significant bits of the Watchdog timer that +* are not checked against the match. Unlock the Watchdog timer before * ignoring the bits setting. Call the Cy_WDT_Unlock() API to unlock the WDT. * * \param bitsNum @@ -157,7 +156,7 @@ void Cy_WDT_SetMatch(uint32_t match) * \details The value of bitsNum controls the time-to-reset of the Watchdog timer * This happens after 3 successive matches. * -* \warning This function changes the WDT interrupt period, therefore +* \warning This function changes the WDT interrupt period, therefore * the device can go into an infinite WDT reset loop. This may happen * if a WDT reset occurs faster that a device start-up. * @@ -177,14 +176,18 @@ void Cy_WDT_SetIgnoreBits(uint32_t bitsNum) * Function Name: Cy_WDT_ClearInterrupt ****************************************************************************//** * -* Clears the WDT match flag which is set every time the WDT counter reaches a -* WDT match value. Two unserviced interrupts lead to a system reset +* Clears the WDT match flag which is set every time the WDT counter reaches a +* WDT match value. Two unserviced interrupts lead to a system reset * (i.e. at the third match). * *******************************************************************************/ void Cy_WDT_ClearInterrupt(void) { - SRSS_SRSS_INTR = _VAL2FLD(SRSS_SRSS_INTR_WDT_MATCH, 1U); + #if CY_CPU_CORTEX_M4 && defined(CY_DEVICE_SECURE) + CY_PRA_REG32_SET(CY_PRA_INDX_SRSS_SRSS_INTR, _VAL2FLD(SRSS_SRSS_INTR_WDT_MATCH, 1U)); + #else + SRSS_SRSS_INTR = _VAL2FLD(SRSS_SRSS_INTR_WDT_MATCH, 1U); + #endif /* Read the interrupt register to ensure that the initial clearing write has * been flushed out to the hardware. diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/.cymigration b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/.cymigration index e7a0834a72..ab4bf664a1 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/.cymigration +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/.cymigration @@ -32,23 +32,28 @@ - + - + - + - + + + + + + @@ -64,4 +69,7 @@ + + + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/althf_bleeco-1.0.cypersonality b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/althf_bleeco-1.0.cypersonality index 145e98c0f3..21d2bb8fb4 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/althf_bleeco-1.0.cypersonality +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/althf_bleeco-1.0.cypersonality @@ -64,6 +64,11 @@ - + + + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/bakclk-1.0.cypersonality b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/bakclk-1.0.cypersonality index a1862b315c..50524a2766 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/bakclk-1.0.cypersonality +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/bakclk-1.0.cypersonality @@ -61,6 +61,7 @@ - + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/eco-2.0.cypersonality b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/eco-2.0.cypersonality index 80054b62e7..abd1e00e19 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/eco-2.0.cypersonality +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/eco-2.0.cypersonality @@ -41,7 +41,7 @@ - + @@ -90,6 +90,13 @@ - + + + + + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/extclk-1.1.cypersonality b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/extclk-1.1.cypersonality index 3b697323e4..1c01168ca9 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/extclk-1.1.cypersonality +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/extclk-1.1.cypersonality @@ -62,6 +62,9 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/fastclk-1.0.cypersonality b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/fastclk-1.0.cypersonality index 7ee155c1f1..61eb0dacdb 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/fastclk-1.0.cypersonality +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/fastclk-1.0.cypersonality @@ -64,6 +64,7 @@ - + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/fll-1.0.cypersonality b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/fll-1.0.cypersonality index 62332e5dec..0cf044bef4 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/fll-1.0.cypersonality +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/fll-1.0.cypersonality @@ -91,7 +91,18 @@ - + + + + + + + + + + + + @@ -103,6 +114,6 @@ - + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/hfclk-1.1.cypersonality b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/hfclk-1.1.cypersonality index 3e3a59fd78..38f1132ce6 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/hfclk-1.1.cypersonality +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/hfclk-1.1.cypersonality @@ -138,10 +138,12 @@ + - - + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/hvilo-1.0.cypersonality b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/hvilo-1.0.cypersonality index 7aab5cafe6..d5c1174ec7 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/hvilo-1.0.cypersonality +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/hvilo-1.0.cypersonality @@ -51,6 +51,7 @@ - + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/lfclk-1.1.cypersonality b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/lfclk-1.1.cypersonality index 7659bde17b..89a110dc35 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/lfclk-1.1.cypersonality +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/lfclk-1.1.cypersonality @@ -65,6 +65,7 @@ - + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/pathmux-1.0.cypersonality b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/pathmux-1.0.cypersonality index f27db36c5b..be8a3fbfb3 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/pathmux-1.0.cypersonality +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/pathmux-1.0.cypersonality @@ -60,6 +60,14 @@ sourceClock eq ilo ? "ILO" : sourceClock eq pilo ? "PILO" : "WCO"}`" visible="false" editable="false" desc="" /> + + @@ -79,6 +87,7 @@ + @@ -86,7 +95,7 @@ - + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/periclk-1.0.cypersonality b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/periclk-1.0.cypersonality index 8dcfff40f3..05605c22fe 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/periclk-1.0.cypersonality +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/periclk-1.0.cypersonality @@ -66,6 +66,7 @@ - + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/pilo-1.0.cypersonality b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/pilo-1.0.cypersonality index fdf1726052..ba6a8dc117 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/pilo-1.0.cypersonality +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/pilo-1.0.cypersonality @@ -47,6 +47,6 @@ - + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/pin-1.1.cypersonality b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/pin-1.1.cypersonality index 5237b008fa..fd4c1fa5cb 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/pin-1.1.cypersonality +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/pin-1.1.cypersonality @@ -153,6 +153,7 @@ + - + + + + + + + - + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/power-1.2.cypersonality b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/power-1.2.cypersonality index b2b1538c45..bcdf55f4f0 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/power-1.2.cypersonality +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/power-1.2.cypersonality @@ -71,16 +71,16 @@ - - @@ -157,7 +157,7 @@ - + @@ -166,7 +166,7 @@ - + @@ -186,7 +186,7 @@ - + @@ -197,31 +197,33 @@ + /* Reset the Backup domain on POR, XRES, BOD only if Backup domain is supplied by VDDD */ + #if (CY_CFG_PWR_VBACKUP_USING_VDDD) + #ifdef CY_CFG_SYSCLK_ILO_ENABLED + if (0u == Cy_SysLib_GetResetReason() /* POR, XRES, or BOD */) + { + Cy_SysLib_ResetBackupDomain(); + Cy_SysClk_IloDisable(); + Cy_SysClk_IloInit(); + } + #endif /* CY_CFG_SYSCLK_ILO_ENABLED */ + #endif /* CY_CFG_PWR_VBACKUP_USING_VDDD */ + /* Configure core regulator */ + #if !((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) + #if CY_CFG_PWR_USING_LDO + Cy_SysPm_LdoSetVoltage(CY_SYSPM_LDO_VOLTAGE_`${actPwrMode}`); + Cy_SysPm_LdoSetMode(`${coreRegulator}`); + #else + Cy_SysPm_BuckEnable(CY_SYSPM_BUCK_OUT1_VOLTAGE_`${actPwrMode}`); + #endif /* CY_CFG_PWR_USING_LDO */ + #endif /* !((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) */ + /* Configure PMIC */ + Cy_SysPm_UnlockPmic(); + #if CY_CFG_PWR_USING_PMIC + Cy_SysPm_PmicEnableOutput(); + #else + Cy_SysPm_PmicDisableOutput(); + #endif /* CY_CFG_PWR_USING_PMIC */" + public="false" include="true" guard="((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE)))" /> diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/power-1.3.cypersonality b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/power-1.3.cypersonality new file mode 100644 index 0000000000..6a8d7664cf --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/power-1.3.cypersonality @@ -0,0 +1,234 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/pumpclk-1.0.cypersonality b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/pumpclk-1.0.cypersonality index 657b20a28a..540c78a987 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/pumpclk-1.0.cypersonality +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/pumpclk-1.0.cypersonality @@ -94,6 +94,8 @@ - + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/slowclk-1.0.cypersonality b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/slowclk-1.0.cypersonality index 4adf13f741..2acff2ee0c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/slowclk-1.0.cypersonality +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/slowclk-1.0.cypersonality @@ -63,6 +63,7 @@ - + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/sysclock-1.2.cypersonality b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/sysclock-1.2.cypersonality index 66c39e4696..4a7ede88de 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/sysclock-1.2.cypersonality +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/sysclock-1.2.cypersonality @@ -34,344 +34,870 @@ + + + - + + - + + + + - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - - - + + + + - - - - - - - + + + + + + + - - - - - - - - - - + + + + + + + + + + - - - - - + + + + + - - - - - - + + + + + + - - - - + + + + - - - + + + - - - + + + - - - + + + - - - + + + - - - + + + - - - - + + + + - - - + + + - - - + + + - - - - - - - + + + + + + + + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - - - + + + + - + - - - - + + + + + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - - - + + + + - - - + + + - - - + + + - - - + + + - - - - - - - + + + + - - - + + + - + + + + - - - - - - + - - - - + + + + + + + + + + - - + + + + + + + + + + + + + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/tickclk-1.0.cypersonality b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/tickclk-1.0.cypersonality index 6175452140..8a8df64263 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/tickclk-1.0.cypersonality +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/tickclk-1.0.cypersonality @@ -65,6 +65,7 @@ - + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/timerclk-1.0.cypersonality b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/timerclk-1.0.cypersonality index 7c930fd544..e08bcef96c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/timerclk-1.0.cypersonality +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/timerclk-1.0.cypersonality @@ -69,6 +69,8 @@ - + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/wco-1.0.cypersonality b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/wco-1.0.cypersonality index 0ad0c12000..3ca4541e50 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/wco-1.0.cypersonality +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/wco-1.0.cypersonality @@ -95,12 +95,17 @@ + + + + + - + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/.cymigration b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/.cymigration index 3b6bd4ea08..06b7f8436f 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/.cymigration +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/.cymigration @@ -32,23 +32,28 @@ - + - + - + - + + + + + + @@ -64,7 +69,7 @@ - + @@ -82,4 +87,4 @@ - + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/platform/althf_bleeco-1.0.cypersonality b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/platform/althf_bleeco-1.0.cypersonality index 145e98c0f3..21d2bb8fb4 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/platform/althf_bleeco-1.0.cypersonality +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/platform/althf_bleeco-1.0.cypersonality @@ -64,6 +64,11 @@ - + + + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/platform/bakclk-1.0.cypersonality b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/platform/bakclk-1.0.cypersonality index a1862b315c..50524a2766 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/platform/bakclk-1.0.cypersonality +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/platform/bakclk-1.0.cypersonality @@ -61,6 +61,7 @@ - + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/platform/eco-2.0.cypersonality b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/platform/eco-2.0.cypersonality index 80054b62e7..abd1e00e19 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/platform/eco-2.0.cypersonality +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/platform/eco-2.0.cypersonality @@ -41,7 +41,7 @@ - + @@ -90,6 +90,13 @@ - + + + + + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/platform/extclk-1.1.cypersonality b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/platform/extclk-1.1.cypersonality index 3b697323e4..1c01168ca9 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/platform/extclk-1.1.cypersonality +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/platform/extclk-1.1.cypersonality @@ -62,6 +62,9 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/platform/fastclk-1.0.cypersonality b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/platform/fastclk-1.0.cypersonality index 7ee155c1f1..61eb0dacdb 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/platform/fastclk-1.0.cypersonality +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/platform/fastclk-1.0.cypersonality @@ -64,6 +64,7 @@ - + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/platform/fll-1.0.cypersonality b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/platform/fll-1.0.cypersonality index 62332e5dec..0cf044bef4 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/platform/fll-1.0.cypersonality +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/platform/fll-1.0.cypersonality @@ -91,7 +91,18 @@ - + + + + + + + + + + + + @@ -103,6 +114,6 @@ - + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/platform/fll-2.0.cypersonality b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/platform/fll-2.0.cypersonality index 9e609f74f4..eff4cc82dc 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/platform/fll-2.0.cypersonality +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/platform/fll-2.0.cypersonality @@ -92,7 +92,18 @@ - + + + + + + + + + + + + @@ -104,6 +115,6 @@ - + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/platform/hfclk-1.1.cypersonality b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/platform/hfclk-1.1.cypersonality index 3e3a59fd78..38f1132ce6 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/platform/hfclk-1.1.cypersonality +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/platform/hfclk-1.1.cypersonality @@ -138,10 +138,12 @@ + - - + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/platform/hvilo-1.0.cypersonality b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/platform/hvilo-1.0.cypersonality index 7aab5cafe6..d5c1174ec7 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/platform/hvilo-1.0.cypersonality +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/platform/hvilo-1.0.cypersonality @@ -51,6 +51,7 @@ - + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/platform/lfclk-1.1.cypersonality b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/platform/lfclk-1.1.cypersonality index 7659bde17b..89a110dc35 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/platform/lfclk-1.1.cypersonality +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/platform/lfclk-1.1.cypersonality @@ -65,6 +65,7 @@ - + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/platform/pathmux-1.0.cypersonality b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/platform/pathmux-1.0.cypersonality index f27db36c5b..be8a3fbfb3 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/platform/pathmux-1.0.cypersonality +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/platform/pathmux-1.0.cypersonality @@ -60,6 +60,14 @@ sourceClock eq ilo ? "ILO" : sourceClock eq pilo ? "PILO" : "WCO"}`" visible="false" editable="false" desc="" /> + + @@ -79,6 +87,7 @@ + @@ -86,7 +95,7 @@ - + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/platform/periclk-1.0.cypersonality b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/platform/periclk-1.0.cypersonality index 8dcfff40f3..05605c22fe 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/platform/periclk-1.0.cypersonality +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/platform/periclk-1.0.cypersonality @@ -66,6 +66,7 @@ - + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/platform/pilo-1.0.cypersonality b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/platform/pilo-1.0.cypersonality index fdf1726052..ba6a8dc117 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/platform/pilo-1.0.cypersonality +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/platform/pilo-1.0.cypersonality @@ -47,6 +47,6 @@ - + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/platform/pin-1.1.cypersonality b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/platform/pin-1.1.cypersonality index 5237b008fa..fd4c1fa5cb 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/platform/pin-1.1.cypersonality +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/platform/pin-1.1.cypersonality @@ -153,6 +153,7 @@ + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/platform/pll-1.0.cypersonality b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/platform/pll-1.0.cypersonality index b2886fe05c..f23189cc79 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/platform/pll-1.0.cypersonality +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/platform/pll-1.0.cypersonality @@ -104,13 +104,19 @@ - + + + + + + + - + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/platform/pll-2.0.cypersonality b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/platform/pll-2.0.cypersonality index 4a691efdfe..dfd07a2d95 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/platform/pll-2.0.cypersonality +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/platform/pll-2.0.cypersonality @@ -104,13 +104,19 @@ - + + + + + + + - + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/platform/power-1.2.cypersonality b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/platform/power-1.2.cypersonality index b2b1538c45..bcdf55f4f0 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/platform/power-1.2.cypersonality +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/platform/power-1.2.cypersonality @@ -71,16 +71,16 @@ - - @@ -157,7 +157,7 @@ - + @@ -166,7 +166,7 @@ - + @@ -186,7 +186,7 @@ - + @@ -197,31 +197,33 @@ + /* Reset the Backup domain on POR, XRES, BOD only if Backup domain is supplied by VDDD */ + #if (CY_CFG_PWR_VBACKUP_USING_VDDD) + #ifdef CY_CFG_SYSCLK_ILO_ENABLED + if (0u == Cy_SysLib_GetResetReason() /* POR, XRES, or BOD */) + { + Cy_SysLib_ResetBackupDomain(); + Cy_SysClk_IloDisable(); + Cy_SysClk_IloInit(); + } + #endif /* CY_CFG_SYSCLK_ILO_ENABLED */ + #endif /* CY_CFG_PWR_VBACKUP_USING_VDDD */ + /* Configure core regulator */ + #if !((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) + #if CY_CFG_PWR_USING_LDO + Cy_SysPm_LdoSetVoltage(CY_SYSPM_LDO_VOLTAGE_`${actPwrMode}`); + Cy_SysPm_LdoSetMode(`${coreRegulator}`); + #else + Cy_SysPm_BuckEnable(CY_SYSPM_BUCK_OUT1_VOLTAGE_`${actPwrMode}`); + #endif /* CY_CFG_PWR_USING_LDO */ + #endif /* !((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) */ + /* Configure PMIC */ + Cy_SysPm_UnlockPmic(); + #if CY_CFG_PWR_USING_PMIC + Cy_SysPm_PmicEnableOutput(); + #else + Cy_SysPm_PmicDisableOutput(); + #endif /* CY_CFG_PWR_USING_PMIC */" + public="false" include="true" guard="((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE)))" /> diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/platform/power-1.3.cypersonality b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/platform/power-1.3.cypersonality new file mode 100644 index 0000000000..6a8d7664cf --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/platform/power-1.3.cypersonality @@ -0,0 +1,234 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/platform/pumpclk-1.0.cypersonality b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/platform/pumpclk-1.0.cypersonality index 657b20a28a..540c78a987 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/platform/pumpclk-1.0.cypersonality +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/platform/pumpclk-1.0.cypersonality @@ -94,6 +94,8 @@ - + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/platform/slowclk-1.0.cypersonality b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/platform/slowclk-1.0.cypersonality index 4adf13f741..2acff2ee0c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/platform/slowclk-1.0.cypersonality +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/platform/slowclk-1.0.cypersonality @@ -63,6 +63,7 @@ - + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/platform/sysclock-1.2.cypersonality b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/platform/sysclock-1.2.cypersonality index 66c39e4696..4a7ede88de 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/platform/sysclock-1.2.cypersonality +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/platform/sysclock-1.2.cypersonality @@ -34,344 +34,870 @@ + + + - + + - + + + + - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - - - + + + + - - - - - - - + + + + + + + - - - - - - - - - - + + + + + + + + + + - - - - - + + + + + - - - - - - + + + + + + - - - - + + + + - - - + + + - - - + + + - - - + + + - - - + + + - - - + + + - - - - + + + + - - - + + + - - - + + + - - - - - - - + + + + + + + + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - - - + + + + - + - - - - + + + + + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - - - + + + + - - - + + + - - - + + + - - - + + + - - - - - - - + + + + - - - + + + - + + + + - - - - - - + - - - - + + + + + + + + + + - - + + + + + + + + + + + + + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/platform/tickclk-1.0.cypersonality b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/platform/tickclk-1.0.cypersonality index 6175452140..8a8df64263 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/platform/tickclk-1.0.cypersonality +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/platform/tickclk-1.0.cypersonality @@ -65,6 +65,7 @@ - + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/platform/timerclk-1.0.cypersonality b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/platform/timerclk-1.0.cypersonality index 7c930fd544..e08bcef96c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/platform/timerclk-1.0.cypersonality +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/platform/timerclk-1.0.cypersonality @@ -69,6 +69,8 @@ - + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/platform/wco-1.0.cypersonality b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/platform/wco-1.0.cypersonality index 0ad0c12000..3ca4541e50 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/platform/wco-1.0.cypersonality +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities_2.0/platform/wco-1.0.cypersonality @@ -95,12 +95,17 @@ + + + + + - + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/001-91989.revision b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/001-91989.revision index b2bfbe3c7c..be80172872 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/001-91989.revision +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/001-91989.revision @@ -1 +1 @@ -CI +CM \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012C0/CYW43012C0WKWBG/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012C0/CYW43012C0WKWBG/studio/view.xml index 7067057812..2c8590458a 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012C0/CYW43012C0WKWBG/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012C0/CYW43012C0WKWBG/studio/view.xml @@ -5,6 +5,7 @@ + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012C0/CYW43012TC0EKUBG/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012C0/CYW43012TC0EKUBG/studio/view.xml index bd2a4162c7..886cd7e276 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012C0/CYW43012TC0EKUBG/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012C0/CYW43012TC0EKUBG/studio/view.xml @@ -5,6 +5,7 @@ + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012C0/CYW43012TC0KFFBH/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012C0/CYW43012TC0KFFBH/studio/view.xml index af3d05c708..16f84f847e 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012C0/CYW43012TC0KFFBH/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012C0/CYW43012TC0KFFBH/studio/view.xml @@ -5,6 +5,7 @@ + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012C0/CYW43012WKWBG/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012C0/CYW43012WKWBG/studio/view.xml index 9391b17b7a..277171a8a7 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012C0/CYW43012WKWBG/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012C0/CYW43012WKWBG/studio/view.xml @@ -5,6 +5,7 @@ + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/4343A1/CYW43438KUBG/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/4343A1/CYW43438KUBG/studio/view.xml index 419a6baa1f..e4b8a3cb31 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/4343A1/CYW43438KUBG/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/4343A1/CYW43438KUBG/studio/view.xml @@ -5,6 +5,7 @@ + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/4343A1/CYW4343WKUBG/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/4343A1/CYW4343WKUBG/studio/view.xml index 5b39ddbf31..7e1b030344 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/4343A1/CYW4343WKUBG/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/4343A1/CYW4343WKUBG/studio/view.xml @@ -5,6 +5,7 @@ + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/4343A1/CYW4343WKWBG/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/4343A1/CYW4343WKWBG/studio/view.xml index 28634da81e..f81fb1c16c 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/4343A1/CYW4343WKWBG/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/4343A1/CYW4343WKWBG/studio/view.xml @@ -5,6 +5,7 @@ + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6148AZI-S2F44/base/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6148AZI-S2F44/base/view.xml new file mode 100755 index 0000000000..b336259045 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6148AZI-S2F44/base/view.xml @@ -0,0 +1,11 @@ + + + CortexM4 + Cypress + 1048576 + 524288 + 128-TQFP + 1700 + 3600 + The CY8C6148AZI-S2F44 device. + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6148AZI-S2F44/info.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6148AZI-S2F44/info.xml new file mode 100755 index 0000000000..d9596f1f22 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6148AZI-S2F44/info.xml @@ -0,0 +1,6 @@ + + + CY8C6148AZI-S2F44 + The CY8C6148AZI-S2F44 devices + true + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6148AZI-S2F44/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6148AZI-S2F44/studio/presentation new file mode 100755 index 0000000000..5a9f775be9 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6148AZI-S2F44/studio/presentation @@ -0,0 +1,2 @@ +PSoC 6 +PSoC 61 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6148AZI-S2F44/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6148AZI-S2F44/studio/view.xml new file mode 100755 index 0000000000..8a77a3340b --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6148AZI-S2F44/studio/view.xml @@ -0,0 +1,62 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6148BZI-S2F44/base/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6148BZI-S2F44/base/view.xml new file mode 100755 index 0000000000..9726d863f3 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6148BZI-S2F44/base/view.xml @@ -0,0 +1,11 @@ + + + CortexM4 + Cypress + 1048576 + 524288 + 124-BGA + 1700 + 3600 + The CY8C6148BZI-S2F44 device. + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6148BZI-S2F44/info.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6148BZI-S2F44/info.xml new file mode 100755 index 0000000000..9b0700c770 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6148BZI-S2F44/info.xml @@ -0,0 +1,6 @@ + + + CY8C6148BZI-S2F44 + The CY8C6148BZI-S2F44 devices + true + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6148BZI-S2F44/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6148BZI-S2F44/studio/presentation new file mode 100755 index 0000000000..5a9f775be9 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6148BZI-S2F44/studio/presentation @@ -0,0 +1,2 @@ +PSoC 6 +PSoC 61 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6148BZI-S2F44/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6148BZI-S2F44/studio/view.xml new file mode 100755 index 0000000000..24ba4cc571 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6148BZI-S2F44/studio/view.xml @@ -0,0 +1,62 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6148FNI-S2F43/base/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6148FNI-S2F43/base/view.xml new file mode 100755 index 0000000000..23896f5685 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6148FNI-S2F43/base/view.xml @@ -0,0 +1,11 @@ + + + CortexM4 + Cypress + 1048576 + 524288 + 100-WLCSP + 1700 + 3600 + The CY8C6148FNI-S2F43 device. + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6148FNI-S2F43/info.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6148FNI-S2F43/info.xml new file mode 100755 index 0000000000..dc57614cec --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6148FNI-S2F43/info.xml @@ -0,0 +1,6 @@ + + + CY8C6148FNI-S2F43 + The CY8C6148FNI-S2F43 devices + true + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6148FNI-S2F43/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6148FNI-S2F43/studio/presentation new file mode 100755 index 0000000000..5a9f775be9 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6148FNI-S2F43/studio/presentation @@ -0,0 +1,2 @@ +PSoC 6 +PSoC 61 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6148FNI-S2F43/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6148FNI-S2F43/studio/view.xml new file mode 100755 index 0000000000..578e964a19 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6148FNI-S2F43/studio/view.xml @@ -0,0 +1,62 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614AAZI-S2F04/base/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614AAZI-S2F04/base/view.xml new file mode 100755 index 0000000000..5ffbbf47f4 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614AAZI-S2F04/base/view.xml @@ -0,0 +1,11 @@ + + + CortexM4 + Cypress + 2097152 + 1048576 + 128-TQFP + 1700 + 3600 + The CY8C614AAZI-S2F04 device. + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614AAZI-S2F04/info.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614AAZI-S2F04/info.xml new file mode 100755 index 0000000000..117bde59cb --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614AAZI-S2F04/info.xml @@ -0,0 +1,6 @@ + + + CY8C614AAZI-S2F04 + The CY8C614AAZI-S2F04 devices + true + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614AAZI-S2F04/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614AAZI-S2F04/studio/presentation new file mode 100755 index 0000000000..5a9f775be9 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614AAZI-S2F04/studio/presentation @@ -0,0 +1,2 @@ +PSoC 6 +PSoC 61 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614AAZI-S2F04/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614AAZI-S2F04/studio/view.xml new file mode 100755 index 0000000000..1d66a71ab9 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614AAZI-S2F04/studio/view.xml @@ -0,0 +1,62 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614AAZI-S2F14/base/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614AAZI-S2F14/base/view.xml new file mode 100755 index 0000000000..e55ef035c4 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614AAZI-S2F14/base/view.xml @@ -0,0 +1,11 @@ + + + CortexM4 + Cypress + 2097152 + 1048576 + 128-TQFP + 1700 + 3600 + The CY8C614AAZI-S2F14 device. + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614AAZI-S2F14/info.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614AAZI-S2F14/info.xml new file mode 100755 index 0000000000..fb2a7c07cf --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614AAZI-S2F14/info.xml @@ -0,0 +1,6 @@ + + + CY8C614AAZI-S2F14 + The CY8C614AAZI-S2F14 devices + true + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614AAZI-S2F14/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614AAZI-S2F14/studio/presentation new file mode 100755 index 0000000000..5a9f775be9 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614AAZI-S2F14/studio/presentation @@ -0,0 +1,2 @@ +PSoC 6 +PSoC 61 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614AAZI-S2F14/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614AAZI-S2F14/studio/view.xml new file mode 100755 index 0000000000..016902db8f --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614AAZI-S2F14/studio/view.xml @@ -0,0 +1,62 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614AAZI-S2F44/base/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614AAZI-S2F44/base/view.xml new file mode 100755 index 0000000000..c9c63eaf94 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614AAZI-S2F44/base/view.xml @@ -0,0 +1,11 @@ + + + CortexM4 + Cypress + 2097152 + 1048576 + 128-TQFP + 1700 + 3600 + The CY8C614AAZI-S2F44 device. + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614AAZI-S2F44/info.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614AAZI-S2F44/info.xml new file mode 100755 index 0000000000..009794e379 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614AAZI-S2F44/info.xml @@ -0,0 +1,6 @@ + + + CY8C614AAZI-S2F44 + The CY8C614AAZI-S2F44 devices + true + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614AAZI-S2F44/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614AAZI-S2F44/studio/presentation new file mode 100755 index 0000000000..5a9f775be9 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614AAZI-S2F44/studio/presentation @@ -0,0 +1,2 @@ +PSoC 6 +PSoC 61 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624AAZI-D44/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614AAZI-S2F44/studio/view.xml similarity index 80% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624AAZI-D44/studio/view.xml rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614AAZI-S2F44/studio/view.xml index ee610da3ac..d25a8c6a8c 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624AAZI-D44/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614AAZI-S2F44/studio/view.xml @@ -1,12 +1,12 @@ - + - - + + @@ -27,7 +27,7 @@ - + @@ -38,7 +38,10 @@ - + + + + @@ -49,11 +52,11 @@ - + - + - + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614ABZI-S2F04/base/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614ABZI-S2F04/base/view.xml new file mode 100755 index 0000000000..c15bf0c405 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614ABZI-S2F04/base/view.xml @@ -0,0 +1,11 @@ + + + CortexM4 + Cypress + 2097152 + 1048576 + 124-BGA + 1700 + 3600 + The CY8C614ABZI-S2F04 device. + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614ABZI-S2F04/info.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614ABZI-S2F04/info.xml new file mode 100755 index 0000000000..c4d0f818d5 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614ABZI-S2F04/info.xml @@ -0,0 +1,6 @@ + + + CY8C614ABZI-S2F04 + The CY8C614ABZI-S2F04 devices + true + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614ABZI-S2F04/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614ABZI-S2F04/studio/presentation new file mode 100755 index 0000000000..5a9f775be9 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614ABZI-S2F04/studio/presentation @@ -0,0 +1,2 @@ +PSoC 6 +PSoC 61 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614ABZI-S2F04/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614ABZI-S2F04/studio/view.xml new file mode 100755 index 0000000000..0096375f9b --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614ABZI-S2F04/studio/view.xml @@ -0,0 +1,62 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614ABZI-S2F44/base/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614ABZI-S2F44/base/view.xml new file mode 100755 index 0000000000..9041d1d9c7 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614ABZI-S2F44/base/view.xml @@ -0,0 +1,11 @@ + + + CortexM4 + Cypress + 2097152 + 1048576 + 124-BGA + 1700 + 3600 + The CY8C614ABZI-S2F44 device. + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614ABZI-S2F44/info.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614ABZI-S2F44/info.xml new file mode 100755 index 0000000000..d62601cbb9 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614ABZI-S2F44/info.xml @@ -0,0 +1,6 @@ + + + CY8C614ABZI-S2F44 + The CY8C614ABZI-S2F44 devices + true + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614ABZI-S2F44/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614ABZI-S2F44/studio/presentation new file mode 100755 index 0000000000..5a9f775be9 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614ABZI-S2F44/studio/presentation @@ -0,0 +1,2 @@ +PSoC 6 +PSoC 61 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624ALQI-D42/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614ABZI-S2F44/studio/view.xml similarity index 77% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624ALQI-D42/studio/view.xml rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614ABZI-S2F44/studio/view.xml index 5d2b01a21b..c4887e517e 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624ALQI-D42/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614ABZI-S2F44/studio/view.xml @@ -1,12 +1,12 @@ - + - - - + + + @@ -27,7 +27,7 @@ - + @@ -38,22 +38,25 @@ - + + + + - + - + - + - + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614AFNI-S2F03/base/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614AFNI-S2F03/base/view.xml new file mode 100755 index 0000000000..578236fa1f --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614AFNI-S2F03/base/view.xml @@ -0,0 +1,11 @@ + + + CortexM4 + Cypress + 2097152 + 1048576 + 100-WLCSP + 1700 + 3600 + The CY8C614AFNI-S2F03 device. + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614AFNI-S2F03/info.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614AFNI-S2F03/info.xml new file mode 100755 index 0000000000..94154852a0 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614AFNI-S2F03/info.xml @@ -0,0 +1,6 @@ + + + CY8C614AFNI-S2F03 + The CY8C614AFNI-S2F03 devices + true + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614AFNI-S2F03/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614AFNI-S2F03/studio/presentation new file mode 100755 index 0000000000..5a9f775be9 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614AFNI-S2F03/studio/presentation @@ -0,0 +1,2 @@ +PSoC 6 +PSoC 61 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614AFNI-S2F03/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614AFNI-S2F03/studio/view.xml new file mode 100755 index 0000000000..9bb376409a --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614AFNI-S2F03/studio/view.xml @@ -0,0 +1,62 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614AFNI-S2F43/base/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614AFNI-S2F43/base/view.xml new file mode 100755 index 0000000000..870c15970e --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614AFNI-S2F43/base/view.xml @@ -0,0 +1,11 @@ + + + CortexM4 + Cypress + 2097152 + 1048576 + 100-WLCSP + 1700 + 3600 + The CY8C614AFNI-S2F43 device. + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614AFNI-S2F43/info.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614AFNI-S2F43/info.xml new file mode 100755 index 0000000000..4df60a93c6 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614AFNI-S2F43/info.xml @@ -0,0 +1,6 @@ + + + CY8C614AFNI-S2F43 + The CY8C614AFNI-S2F43 devices + true + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614AFNI-S2F43/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614AFNI-S2F43/studio/presentation new file mode 100755 index 0000000000..5a9f775be9 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614AFNI-S2F43/studio/presentation @@ -0,0 +1,2 @@ +PSoC 6 +PSoC 61 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624AFNI-D43/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614AFNI-S2F43/studio/view.xml similarity index 79% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624AFNI-D43/studio/view.xml rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614AFNI-S2F43/studio/view.xml index deab8317e3..3ca7d4fac5 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624AFNI-D43/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C614AFNI-S2F43/studio/view.xml @@ -1,12 +1,12 @@ - + - - + + @@ -27,7 +27,7 @@ - + @@ -38,22 +38,25 @@ - + + + + - + - + - + - + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6248AZI-S2D14/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6248AZI-S2D14/studio/view.xml index 410481617c..f4e15510b7 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6248AZI-S2D14/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6248AZI-S2D14/studio/view.xml @@ -27,7 +27,7 @@ - + @@ -38,7 +38,10 @@ - + + + + @@ -49,11 +52,11 @@ - + - + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6248AZI-S2D44/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6248AZI-S2D44/studio/view.xml index 6d3e272622..d73eef77d4 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6248AZI-S2D44/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6248AZI-S2D44/studio/view.xml @@ -27,7 +27,7 @@ - + @@ -38,7 +38,10 @@ - + + + + @@ -49,11 +52,11 @@ - + - + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6248BZI-S2D44/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6248BZI-S2D44/studio/view.xml index 2963364cc4..f31edc3704 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6248BZI-S2D44/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6248BZI-S2D44/studio/view.xml @@ -27,7 +27,7 @@ - + @@ -38,22 +38,25 @@ - + + + + - + - + - + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6248FNI-S2D43/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6248FNI-S2D43/studio/view.xml index 12dd36da2a..aafbfcc5c3 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6248FNI-S2D43/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6248FNI-S2D43/studio/view.xml @@ -27,7 +27,7 @@ - + @@ -38,22 +38,25 @@ - + + + + - + - + - + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624AAZI-D44/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624AAZI-D44/studio/presentation deleted file mode 100755 index 33e940a6d9..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624AAZI-D44/studio/presentation +++ /dev/null @@ -1,2 +0,0 @@ -PSoC 6 -PSoC 62 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624AAZI-S2D14/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624AAZI-S2D14/studio/view.xml index 3356c70295..1ce1c60886 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624AAZI-S2D14/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624AAZI-S2D14/studio/view.xml @@ -27,7 +27,7 @@ - + @@ -38,7 +38,10 @@ - + + + + @@ -49,11 +52,11 @@ - + - + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624AAZI-S2D44/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624AAZI-S2D44/studio/view.xml index 5bdcd37bf5..86c155b646 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624AAZI-S2D44/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624AAZI-S2D44/studio/view.xml @@ -27,7 +27,7 @@ - + @@ -38,7 +38,10 @@ - + + + + @@ -49,11 +52,11 @@ - + - + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624ABZI-D44/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624ABZI-D44/studio/view.xml index 44a0fbf217..ff70184fa5 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624ABZI-D44/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624ABZI-D44/studio/view.xml @@ -27,7 +27,7 @@ - + @@ -38,11 +38,14 @@ - + + + + - + @@ -53,7 +56,7 @@ - + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624ABZI-S2D04/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624ABZI-S2D04/studio/view.xml index 3900e92385..2340a24e41 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624ABZI-S2D04/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624ABZI-S2D04/studio/view.xml @@ -27,7 +27,7 @@ - + @@ -38,22 +38,25 @@ - + + + + - + - + - + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624ABZI-S2D14/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624ABZI-S2D14/studio/view.xml index bb12352fa4..fbfb08f0dc 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624ABZI-S2D14/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624ABZI-S2D14/studio/view.xml @@ -27,7 +27,7 @@ - + @@ -38,22 +38,25 @@ - + + + + - + - + - + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624ABZI-S2D44/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624ABZI-S2D44/studio/view.xml index a403ca717b..2b0108c881 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624ABZI-S2D44/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624ABZI-S2D44/studio/view.xml @@ -27,7 +27,7 @@ - + @@ -38,22 +38,25 @@ - + + + + - + - + - + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624ABZI-S2D44A0/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624ABZI-S2D44A0/studio/view.xml index 5c9973b621..091795d0af 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624ABZI-S2D44A0/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624ABZI-S2D44A0/studio/view.xml @@ -27,7 +27,7 @@ - + @@ -38,11 +38,14 @@ - + + + + - + @@ -53,7 +56,7 @@ - + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624AFNI-D43/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624AFNI-D43/studio/presentation deleted file mode 100755 index 33e940a6d9..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624AFNI-D43/studio/presentation +++ /dev/null @@ -1,2 +0,0 @@ -PSoC 6 -PSoC 62 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624AFNI-S2D43/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624AFNI-S2D43/studio/view.xml index 14844d6235..6f32c1d346 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624AFNI-S2D43/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624AFNI-S2D43/studio/view.xml @@ -27,7 +27,7 @@ - + @@ -38,22 +38,25 @@ - + + + + - + - + - + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624ALQI-D42/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624ALQI-D42/studio/presentation deleted file mode 100755 index 33e940a6d9..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624ALQI-D42/studio/presentation +++ /dev/null @@ -1,2 +0,0 @@ -PSoC 6 -PSoC 62 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CYB0644ABZI-S2D44/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CYB0644ABZI-S2D44/studio/view.xml index fbffdcdf40..71aa157292 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CYB0644ABZI-S2D44/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CYB0644ABZI-S2D44/studio/view.xml @@ -27,7 +27,7 @@ - + @@ -38,11 +38,14 @@ - + + + + - + @@ -53,7 +56,7 @@ - + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CYS0644ABZI-S2D44/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CYS0644ABZI-S2D44/studio/view.xml index a4ed804fc6..ae4c3ff4a3 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CYS0644ABZI-S2D44/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CYS0644ABZI-S2D44/studio/view.xml @@ -27,7 +27,7 @@ - + @@ -38,11 +38,14 @@ - + + + + - + @@ -53,7 +56,7 @@ - + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/hobto/pins.cydata b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/hobto/pins.cydata index 26565470aa..a80f871197 100755 Binary files a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/hobto/pins.cydata and b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/hobto/pins.cydata differ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245W-S3D72/base/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145AZI-S3F02/base/view.xml similarity index 68% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245W-S3D72/base/view.xml rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145AZI-S3F02/base/view.xml index 8d06343874..0d5e870182 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245W-S3D72/base/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145AZI-S3F02/base/view.xml @@ -1,11 +1,11 @@  - CortexM0p,CortexM4 + CortexM4 Cypress 524288 262144 100-TQFP 1700 3600 - The CY8C6245W-S3D72 device. + The CY8C6145AZI-S3F02 device. \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145AZI-S3F02/info.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145AZI-S3F02/info.xml new file mode 100755 index 0000000000..a29246d584 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145AZI-S3F02/info.xml @@ -0,0 +1,6 @@ + + + CY8C6145AZI-S3F02 + The CY8C6145AZI-S3F02 devices + true + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145AZI-S3F02/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145AZI-S3F02/studio/presentation new file mode 100755 index 0000000000..5a9f775be9 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145AZI-S3F02/studio/presentation @@ -0,0 +1,2 @@ +PSoC 6 +PSoC 61 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145AZI-S3F02/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145AZI-S3F02/studio/view.xml new file mode 100755 index 0000000000..dd13b175bb --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145AZI-S3F02/studio/view.xml @@ -0,0 +1,63 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145AZI-S3F12/base/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145AZI-S3F12/base/view.xml new file mode 100755 index 0000000000..1d1d61ca5e --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145AZI-S3F12/base/view.xml @@ -0,0 +1,11 @@ + + + CortexM4 + Cypress + 524288 + 262144 + 100-TQFP + 1700 + 3600 + The CY8C6145AZI-S3F12 device. + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145AZI-S3F12/info.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145AZI-S3F12/info.xml new file mode 100755 index 0000000000..b4d733d1df --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145AZI-S3F12/info.xml @@ -0,0 +1,6 @@ + + + CY8C6145AZI-S3F12 + The CY8C6145AZI-S3F12 devices + true + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145AZI-S3F12/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145AZI-S3F12/studio/presentation new file mode 100755 index 0000000000..5a9f775be9 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145AZI-S3F12/studio/presentation @@ -0,0 +1,2 @@ +PSoC 6 +PSoC 61 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145AZI-S3F12/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145AZI-S3F12/studio/view.xml new file mode 100755 index 0000000000..634df9e928 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145AZI-S3F12/studio/view.xml @@ -0,0 +1,63 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145AZI-S3F42/base/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145AZI-S3F42/base/view.xml new file mode 100755 index 0000000000..42b3d79a9a --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145AZI-S3F42/base/view.xml @@ -0,0 +1,11 @@ + + + CortexM4 + Cypress + 524288 + 262144 + 100-TQFP + 1700 + 3600 + The CY8C6145AZI-S3F42 device. + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145AZI-S3F42/info.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145AZI-S3F42/info.xml new file mode 100755 index 0000000000..0e632b7bdd --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145AZI-S3F42/info.xml @@ -0,0 +1,6 @@ + + + CY8C6145AZI-S3F42 + The CY8C6145AZI-S3F42 devices + true + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145AZI-S3F42/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145AZI-S3F42/studio/presentation new file mode 100755 index 0000000000..5a9f775be9 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145AZI-S3F42/studio/presentation @@ -0,0 +1,2 @@ +PSoC 6 +PSoC 61 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145AZI-S3F42/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145AZI-S3F42/studio/view.xml new file mode 100755 index 0000000000..461c93e045 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145AZI-S3F42/studio/view.xml @@ -0,0 +1,63 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145AZI-S3F62/base/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145AZI-S3F62/base/view.xml new file mode 100755 index 0000000000..a1b623d8a2 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145AZI-S3F62/base/view.xml @@ -0,0 +1,11 @@ + + + CortexM4 + Cypress + 524288 + 262144 + 100-TQFP + 1700 + 3600 + The CY8C6145AZI-S3F62 device. + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145AZI-S3F62/info.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145AZI-S3F62/info.xml new file mode 100755 index 0000000000..de518d6d73 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145AZI-S3F62/info.xml @@ -0,0 +1,6 @@ + + + CY8C6145AZI-S3F62 + The CY8C6145AZI-S3F62 devices + true + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145AZI-S3F62/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145AZI-S3F62/studio/presentation new file mode 100755 index 0000000000..5a9f775be9 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145AZI-S3F62/studio/presentation @@ -0,0 +1,2 @@ +PSoC 6 +PSoC 61 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145AZI-S3F62/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145AZI-S3F62/studio/view.xml new file mode 100755 index 0000000000..546999273b --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145AZI-S3F62/studio/view.xml @@ -0,0 +1,63 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145AZI-S3F72/base/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145AZI-S3F72/base/view.xml new file mode 100755 index 0000000000..9da47dde19 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145AZI-S3F72/base/view.xml @@ -0,0 +1,11 @@ + + + CortexM4 + Cypress + 524288 + 262144 + 100-TQFP + 1700 + 3600 + The CY8C6145AZI-S3F72 device. + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145AZI-S3F72/info.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145AZI-S3F72/info.xml new file mode 100755 index 0000000000..51773ff2cb --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145AZI-S3F72/info.xml @@ -0,0 +1,6 @@ + + + CY8C6145AZI-S3F72 + The CY8C6145AZI-S3F72 devices + true + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145AZI-S3F72/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145AZI-S3F72/studio/presentation new file mode 100755 index 0000000000..5a9f775be9 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145AZI-S3F72/studio/presentation @@ -0,0 +1,2 @@ +PSoC 6 +PSoC 61 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245W-S3D72/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145AZI-S3F72/studio/view.xml similarity index 77% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245W-S3D72/studio/view.xml rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145AZI-S3F72/studio/view.xml index 2729e89914..3de5870b92 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245W-S3D72/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145AZI-S3F72/studio/view.xml @@ -1,12 +1,12 @@ - + - - + + @@ -27,7 +27,7 @@ - + @@ -39,10 +39,13 @@ - + + + + - - + + @@ -50,11 +53,11 @@ - + - + - + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145FNI-S3F11/base/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145FNI-S3F11/base/view.xml new file mode 100755 index 0000000000..4b5b8168f0 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145FNI-S3F11/base/view.xml @@ -0,0 +1,11 @@ + + + CortexM4 + Cypress + 524288 + 262144 + 49-WLCSP + 1700 + 3600 + The CY8C6145FNI-S3F11 device. + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145FNI-S3F11/info.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145FNI-S3F11/info.xml new file mode 100755 index 0000000000..c0f9ceb284 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145FNI-S3F11/info.xml @@ -0,0 +1,6 @@ + + + CY8C6145FNI-S3F11 + The CY8C6145FNI-S3F11 devices + true + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145FNI-S3F11/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145FNI-S3F11/studio/presentation new file mode 100755 index 0000000000..5a9f775be9 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145FNI-S3F11/studio/presentation @@ -0,0 +1,2 @@ +PSoC 6 +PSoC 61 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145FNI-S3F11/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145FNI-S3F11/studio/view.xml new file mode 100755 index 0000000000..b1e40f1cf1 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145FNI-S3F11/studio/view.xml @@ -0,0 +1,63 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145FNI-S3F41/base/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145FNI-S3F41/base/view.xml new file mode 100755 index 0000000000..1c60164c11 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145FNI-S3F41/base/view.xml @@ -0,0 +1,11 @@ + + + CortexM4 + Cypress + 524288 + 262144 + 49-WLCSP + 1700 + 3600 + The CY8C6145FNI-S3F41 device. + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145FNI-S3F41/info.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145FNI-S3F41/info.xml new file mode 100755 index 0000000000..73cbd0aef2 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145FNI-S3F41/info.xml @@ -0,0 +1,6 @@ + + + CY8C6145FNI-S3F41 + The CY8C6145FNI-S3F41 devices + true + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145FNI-S3F41/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145FNI-S3F41/studio/presentation new file mode 100755 index 0000000000..5a9f775be9 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145FNI-S3F41/studio/presentation @@ -0,0 +1,2 @@ +PSoC 6 +PSoC 61 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145FNI-S3F41/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145FNI-S3F41/studio/view.xml new file mode 100755 index 0000000000..71a8f76b56 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145FNI-S3F41/studio/view.xml @@ -0,0 +1,63 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145FNI-S3F71/base/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145FNI-S3F71/base/view.xml new file mode 100755 index 0000000000..68d8f20e36 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145FNI-S3F71/base/view.xml @@ -0,0 +1,11 @@ + + + CortexM4 + Cypress + 524288 + 262144 + 49-WLCSP + 1700 + 3600 + The CY8C6145FNI-S3F71 device. + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145FNI-S3F71/info.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145FNI-S3F71/info.xml new file mode 100755 index 0000000000..203a82a05b --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145FNI-S3F71/info.xml @@ -0,0 +1,6 @@ + + + CY8C6145FNI-S3F71 + The CY8C6145FNI-S3F71 devices + true + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145FNI-S3F71/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145FNI-S3F71/studio/presentation new file mode 100755 index 0000000000..5a9f775be9 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145FNI-S3F71/studio/presentation @@ -0,0 +1,2 @@ +PSoC 6 +PSoC 61 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145FNI-S3F71/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145FNI-S3F71/studio/view.xml new file mode 100755 index 0000000000..082ac2f8e6 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145FNI-S3F71/studio/view.xml @@ -0,0 +1,63 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145LQI-S3F02/base/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145LQI-S3F02/base/view.xml new file mode 100755 index 0000000000..8ca085c1fa --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145LQI-S3F02/base/view.xml @@ -0,0 +1,11 @@ + + + CortexM4 + Cypress + 524288 + 262144 + 68-QFN + 1700 + 3600 + The CY8C6145LQI-S3F02 device. + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145LQI-S3F02/info.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145LQI-S3F02/info.xml new file mode 100755 index 0000000000..e304f655ea --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145LQI-S3F02/info.xml @@ -0,0 +1,6 @@ + + + CY8C6145LQI-S3F02 + The CY8C6145LQI-S3F02 devices + true + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145LQI-S3F02/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145LQI-S3F02/studio/presentation new file mode 100755 index 0000000000..5a9f775be9 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145LQI-S3F02/studio/presentation @@ -0,0 +1,2 @@ +PSoC 6 +PSoC 61 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145LQI-S3F02/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145LQI-S3F02/studio/view.xml new file mode 100755 index 0000000000..079b249013 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145LQI-S3F02/studio/view.xml @@ -0,0 +1,63 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145LQI-S3F12/base/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145LQI-S3F12/base/view.xml new file mode 100755 index 0000000000..3be8ad70e6 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145LQI-S3F12/base/view.xml @@ -0,0 +1,11 @@ + + + CortexM4 + Cypress + 524288 + 262144 + 68-QFN + 1700 + 3600 + The CY8C6145LQI-S3F12 device. + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145LQI-S3F12/info.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145LQI-S3F12/info.xml new file mode 100755 index 0000000000..5d7a88d83c --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145LQI-S3F12/info.xml @@ -0,0 +1,6 @@ + + + CY8C6145LQI-S3F12 + The CY8C6145LQI-S3F12 devices + true + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145LQI-S3F12/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145LQI-S3F12/studio/presentation new file mode 100755 index 0000000000..5a9f775be9 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145LQI-S3F12/studio/presentation @@ -0,0 +1,2 @@ +PSoC 6 +PSoC 61 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145LQI-S3F12/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145LQI-S3F12/studio/view.xml new file mode 100755 index 0000000000..7482ff3be5 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145LQI-S3F12/studio/view.xml @@ -0,0 +1,63 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145LQI-S3F42/base/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145LQI-S3F42/base/view.xml new file mode 100755 index 0000000000..64704c1eaa --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145LQI-S3F42/base/view.xml @@ -0,0 +1,11 @@ + + + CortexM4 + Cypress + 524288 + 262144 + 68-QFN + 1700 + 3600 + The CY8C6145LQI-S3F42 device. + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145LQI-S3F42/info.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145LQI-S3F42/info.xml new file mode 100755 index 0000000000..303a4bb1c7 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145LQI-S3F42/info.xml @@ -0,0 +1,6 @@ + + + CY8C6145LQI-S3F42 + The CY8C6145LQI-S3F42 devices + true + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145LQI-S3F42/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145LQI-S3F42/studio/presentation new file mode 100755 index 0000000000..5a9f775be9 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145LQI-S3F42/studio/presentation @@ -0,0 +1,2 @@ +PSoC 6 +PSoC 61 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145LQI-S3F42/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145LQI-S3F42/studio/view.xml new file mode 100755 index 0000000000..54aa0f12ee --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145LQI-S3F42/studio/view.xml @@ -0,0 +1,63 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145LQI-S3F62/base/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145LQI-S3F62/base/view.xml new file mode 100755 index 0000000000..59a43571e3 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145LQI-S3F62/base/view.xml @@ -0,0 +1,11 @@ + + + CortexM4 + Cypress + 524288 + 262144 + 68-QFN + 1700 + 3600 + The CY8C6145LQI-S3F62 device. + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145LQI-S3F62/info.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145LQI-S3F62/info.xml new file mode 100755 index 0000000000..c49f4ab424 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145LQI-S3F62/info.xml @@ -0,0 +1,6 @@ + + + CY8C6145LQI-S3F62 + The CY8C6145LQI-S3F62 devices + true + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145LQI-S3F62/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145LQI-S3F62/studio/presentation new file mode 100755 index 0000000000..5a9f775be9 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145LQI-S3F62/studio/presentation @@ -0,0 +1,2 @@ +PSoC 6 +PSoC 61 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145LQI-S3F62/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145LQI-S3F62/studio/view.xml new file mode 100755 index 0000000000..3b943a683e --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145LQI-S3F62/studio/view.xml @@ -0,0 +1,63 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145LQI-S3F72/base/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145LQI-S3F72/base/view.xml new file mode 100755 index 0000000000..92ffecb55d --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145LQI-S3F72/base/view.xml @@ -0,0 +1,11 @@ + + + CortexM4 + Cypress + 524288 + 262144 + 68-QFN + 1700 + 3600 + The CY8C6145LQI-S3F72 device. + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145LQI-S3F72/info.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145LQI-S3F72/info.xml new file mode 100755 index 0000000000..6d124be9c6 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145LQI-S3F72/info.xml @@ -0,0 +1,6 @@ + + + CY8C6145LQI-S3F72 + The CY8C6145LQI-S3F72 devices + true + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145LQI-S3F72/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145LQI-S3F72/studio/presentation new file mode 100755 index 0000000000..5a9f775be9 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145LQI-S3F72/studio/presentation @@ -0,0 +1,2 @@ +PSoC 6 +PSoC 61 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145LQI-S3F72/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145LQI-S3F72/studio/view.xml new file mode 100755 index 0000000000..caa7c517f3 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6145LQI-S3F72/studio/view.xml @@ -0,0 +1,63 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245AZI-S3D02/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245AZI-S3D02/studio/view.xml index c34eb5902f..4955ba143d 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245AZI-S3D02/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245AZI-S3D02/studio/view.xml @@ -27,7 +27,7 @@ - + @@ -39,10 +39,13 @@ - + + + + - - + + @@ -54,7 +57,7 @@ - + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245AZI-S3D12/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245AZI-S3D12/studio/view.xml index 33a612ad08..7710c14c58 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245AZI-S3D12/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245AZI-S3D12/studio/view.xml @@ -27,7 +27,7 @@ - + @@ -39,10 +39,13 @@ - + + + + - - + + @@ -54,7 +57,7 @@ - + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245AZI-S3D42/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245AZI-S3D42/studio/view.xml index 7434538022..98c605a9cd 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245AZI-S3D42/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245AZI-S3D42/studio/view.xml @@ -27,7 +27,7 @@ - + @@ -39,10 +39,13 @@ - + + + + - - + + @@ -54,7 +57,7 @@ - + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245AZI-S3D62/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245AZI-S3D62/studio/view.xml index 2721a45681..f60b03e33c 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245AZI-S3D62/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245AZI-S3D62/studio/view.xml @@ -27,7 +27,7 @@ - + @@ -39,10 +39,13 @@ - + + + + - - + + @@ -54,7 +57,7 @@ - + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245AZI-S3D72/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245AZI-S3D72/studio/view.xml index 951182cc36..0b0230e5f6 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245AZI-S3D72/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245AZI-S3D72/studio/view.xml @@ -27,7 +27,7 @@ - + @@ -39,10 +39,13 @@ - + + + + - - + + @@ -54,7 +57,7 @@ - + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245FNI-S3D11/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245FNI-S3D11/studio/view.xml index f99a653de3..428528067b 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245FNI-S3D11/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245FNI-S3D11/studio/view.xml @@ -27,7 +27,7 @@ - + @@ -39,11 +39,14 @@ - + + + + - - - + + + @@ -54,7 +57,7 @@ - + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245FNI-S3D41/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245FNI-S3D41/studio/view.xml index 9201578557..60b0852708 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245FNI-S3D41/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245FNI-S3D41/studio/view.xml @@ -27,7 +27,7 @@ - + @@ -39,11 +39,14 @@ - + + + + - - - + + + @@ -54,7 +57,7 @@ - + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245FNI-S3D71/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245FNI-S3D71/studio/view.xml index 2e28ce6934..579cc793b3 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245FNI-S3D71/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245FNI-S3D71/studio/view.xml @@ -27,7 +27,7 @@ - + @@ -39,11 +39,14 @@ - + + + + - - - + + + @@ -54,7 +57,7 @@ - + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245LQI-S3D02/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245LQI-S3D02/studio/view.xml index 86d4f9d781..3a86611345 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245LQI-S3D02/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245LQI-S3D02/studio/view.xml @@ -27,7 +27,7 @@ - + @@ -39,11 +39,14 @@ - + + + + - - - + + + @@ -54,7 +57,7 @@ - + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245LQI-S3D12/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245LQI-S3D12/studio/view.xml index b65ac48554..ac94984ddf 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245LQI-S3D12/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245LQI-S3D12/studio/view.xml @@ -27,7 +27,7 @@ - + @@ -39,11 +39,14 @@ - + + + + - - - + + + @@ -54,7 +57,7 @@ - + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245LQI-S3D42/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245LQI-S3D42/studio/view.xml index b6b60d2b60..7f9b052553 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245LQI-S3D42/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245LQI-S3D42/studio/view.xml @@ -27,7 +27,7 @@ - + @@ -39,11 +39,14 @@ - + + + + - - - + + + @@ -54,7 +57,7 @@ - + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245LQI-S3D62/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245LQI-S3D62/studio/view.xml index 7e9e25700f..e635efe1e5 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245LQI-S3D62/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245LQI-S3D62/studio/view.xml @@ -27,7 +27,7 @@ - + @@ -39,11 +39,14 @@ - + + + + - - - + + + @@ -54,7 +57,7 @@ - + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245LQI-S3D72/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245LQI-S3D72/studio/view.xml index 22a39d4087..10739295a2 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245LQI-S3D72/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245LQI-S3D72/studio/view.xml @@ -27,7 +27,7 @@ - + @@ -39,11 +39,14 @@ - + + + + - - - + + + @@ -54,7 +57,7 @@ - + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245W-S3D72/info.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245W-S3D72/info.xml deleted file mode 100755 index 1204849e13..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245W-S3D72/info.xml +++ /dev/null @@ -1,6 +0,0 @@ - - - CY8C6245W-S3D72 - The CY8C6245W-S3D72 devices - true - \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245W-S3D72/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245W-S3D72/studio/presentation deleted file mode 100755 index 33e940a6d9..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245W-S3D72/studio/presentation +++ /dev/null @@ -1,2 +0,0 @@ -PSoC 6 -PSoC 62 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CYB06445LQI-S3D42/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CYB06445LQI-S3D42/studio/view.xml index 9d4b1e2af3..fbc47ada6d 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CYB06445LQI-S3D42/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CYB06445LQI-S3D42/studio/view.xml @@ -27,7 +27,7 @@ - + @@ -39,11 +39,14 @@ - + + + + - - - + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/hobto/pins.cydata b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/hobto/pins.cydata index 641f225aef..b14e9f3c2b 100755 Binary files a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/hobto/pins.cydata and b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/hobto/pins.cydata differ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/studio/clocks.cysem b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/studio/clocks.cysem index b8d28ed2dc..4a0a448029 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/studio/clocks.cysem +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/studio/clocks.cysem @@ -1,5 +1,5 @@  - + @@ -1224,148 +1224,19 @@ SYS_TICK - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + - - + - + + @@ -1396,261 +1267,6 @@ SYS_TICK - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -1665,136 +1281,10 @@ SYS_TICK - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -1807,380 +1297,890 @@ SYS_TICK - - - - - - - - + + + + + + + + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - + - + - + - + - + - + - + - + - + - - + - + - + - + - + - + - + - + - + - + - - + - + - + - + - + - + - + - + - + - + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/studio/clocks.cyvis b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/studio/clocks.cyvis index f89b6bcede..bd6d60e632 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/studio/clocks.cyvis +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/studio/clocks.cyvis @@ -1,28 +1,28 @@  - + - + - + - + - + - - - - - + + + + + @@ -31,7 +31,7 @@ - + @@ -45,27 +45,27 @@ - + - + - + - + - - - - - + + + + + @@ -74,7 +74,7 @@ - + @@ -87,60 +87,24 @@ - - - + + + - - - - Peripheral Clocks - - - - - - - - - - wl:audioss[0] + + - - - - Quad SPI - - - - - - - wl:smif[0] - - - - - USB - - - - - - - wl:usb[0] - - + - + - + @@ -150,7 +114,7 @@ - + IMO @@ -164,15 +128,15 @@ - + - + - + @@ -182,7 +146,7 @@ - + ECO @@ -196,15 +160,15 @@ - + - + - + @@ -214,7 +178,7 @@ - + EXTCLK @@ -228,23 +192,23 @@ - + - + - + - - - - - + + + + + @@ -253,7 +217,7 @@ - + PATH_MUX3 @@ -267,23 +231,23 @@ - + - + - + - - - - - + + + + + @@ -292,7 +256,7 @@ - + PATH_MUX2 @@ -306,19 +270,19 @@ - + - + - + - + @@ -328,7 +292,7 @@ - + PLL @@ -342,23 +306,23 @@ - + - + - + - - - - - + + + + + @@ -367,7 +331,7 @@ - + PATH_MUX0 @@ -381,23 +345,23 @@ - + - + - + - - - - - + + + + + @@ -406,7 +370,7 @@ - + PATH_MUX1 @@ -419,20 +383,20 @@ - - + + - + - + - + @@ -442,7 +406,7 @@ - + CLK_HF0 @@ -455,20 +419,20 @@ - - + + - + - + - + @@ -478,7 +442,7 @@ - + CLK_HF1 @@ -491,20 +455,20 @@ - - + + - + - + - + @@ -514,7 +478,7 @@ - + CLK_HF2 @@ -527,20 +491,20 @@ - - + + - + - + - + @@ -550,7 +514,7 @@ - + CLK_HF3 @@ -563,16 +527,16 @@ - - + + - + - + @@ -582,7 +546,7 @@ - + CLK_FAST @@ -595,20 +559,20 @@ - - + + - + - + - + @@ -618,7 +582,7 @@ - + CLK_PERI @@ -631,24 +595,24 @@ - - + + - + - + - + - + @@ -658,7 +622,7 @@ - + CLK_TIMER @@ -671,16 +635,16 @@ - - + + - + - + @@ -690,7 +654,7 @@ - + CLK_SLOW @@ -704,19 +668,19 @@ - + - + - + - + @@ -726,7 +690,7 @@ - + FLL @@ -740,15 +704,15 @@ - + - + - + @@ -758,7 +722,7 @@ - + ILO @@ -771,16 +735,16 @@ - - + + - + - + @@ -790,7 +754,7 @@ - + CLK_PUMP @@ -804,37 +768,38 @@ - - + + - - + + - + [3:0] - - + + + wl:srss[0].clock[0].hfclk[1] - + - + - + - + @@ -844,7 +809,7 @@ - + WCO @@ -858,33 +823,33 @@ - - + + - + [0] - + - + - + - + - + @@ -894,7 +859,7 @@ - + CLK_LF @@ -907,20 +872,20 @@ - - + + - + - + - + @@ -930,7 +895,7 @@ - + CLK_BAK @@ -944,63 +909,66 @@ - - + + - - + + + wl:srss[0].clock[0].hfclk[2] - - + + - - - + + + + wl:srss[0].clock[0].hfclk[3] - - - + + + + wl:srss[0].clock[0].hfclk[4] - - + + wl:smif[0] - - - + + + wl:usb[0] - - + + - + [0] - + - + - + - - - - - + + + + + @@ -1009,7 +977,7 @@ - + @@ -1023,10 +991,10 @@ - - + + - + [0] Net_2223[0] @@ -1034,35 +1002,35 @@ - - + + - + [0] - - + + - - + + - + [0] - + - + @@ -1071,21 +1039,21 @@ - + - + - + - + @@ -1094,21 +1062,21 @@ - + - + - + - + @@ -1117,29 +1085,29 @@ - + - + - - + + - - + + - + - + @@ -1148,29 +1116,29 @@ - + - + - - + + - - + + - + - + @@ -1179,90 +1147,90 @@ - + - + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - + [0] - - + + - - + + - + [1] Net_2522[1] @@ -1270,41 +1238,31 @@ - - + + - - + + - - - + + + + wl:sdhc[0] - - - - SDHC0 - - - - - - - - - + + - - + + - - + + - + [1] Net_2522[1] @@ -1312,11 +1270,11 @@ - + - + @@ -1325,20 +1283,20 @@ - + - + - - + + - + [1] Net_2522[1] @@ -1346,11 +1304,11 @@ - + - + @@ -1359,20 +1317,20 @@ - + - + - - + + - + [1] Net_2522[1] @@ -1380,11 +1338,11 @@ - + - + @@ -1393,17 +1351,17 @@ - + - + - + CLK_PATH3 @@ -1413,66 +1371,44 @@ - - - + + + - - - - CM4 - - - - - - - - - - + + + - - - - CM0p - - - - - - - - - - + + + - - - + + + - - + + - + - + - + - + - + @@ -1482,7 +1418,7 @@ - + CLK_ALT_ SYS_TICK @@ -1497,55 +1433,55 @@ SYS_TICK - - + + - - + + - - + + - - - + + + - - + + - - + + - - + + - - + + - - + + - - + + - + - + - + @@ -1555,7 +1491,7 @@ SYS_TICK - + CLK_HF4 @@ -1569,83 +1505,84 @@ SYS_TICK - - + + - - - + + + + wl:srss[0].clock[0].pumpclk[0] - - + + - - + + - - + + - - + + - - + + - - + + - - - + + + - - - + + + - - - + + + - - - + + + - - - + + + - - - + + + - - - + + + - - - + + + - - + + - - + + - - + + - + CLK_PATH4 @@ -1656,31 +1593,31 @@ SYS_TICK - - + + - - + + - - + + - - + + - - + + - - + + - + CLK_PATH2 @@ -1690,40 +1627,29 @@ SYS_TICK - - - - External Pin - - - - - - - - - + + - - + + - - + + - + [0] - - + + - + [3:0] Net_3337[3:0] @@ -1731,73 +1657,73 @@ SYS_TICK - - + + - - - + + + - - + + - - + + - - - + + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - + [4:0] - + - + - + - + @@ -1807,7 +1733,7 @@ SYS_TICK - + MFO @@ -1820,16 +1746,16 @@ SYS_TICK - - + + - + - + @@ -1839,7 +1765,7 @@ SYS_TICK - + CLK_MF @@ -1852,52 +1778,42 @@ SYS_TICK - - - - LCD - - - - - - - wl:usb[0] - - - + + - - + + - - + + - - + + - - + + - - + + - - - + + + + wl:lcd[0] - - - + + + + wl:lcd[0] - - + + CLK_PATH1 @@ -1907,8 +1823,8 @@ SYS_TICK - - + + CLK_PATH0 @@ -1919,35 +1835,120 @@ SYS_TICK - - + + - - + + - - - + + + + wl:lcd[0] + + + LCD + + + + + + + wl:lcd[0] + + + + CM4 + + + + + + + + + + Peripheral Clocks + + + + + + + + + + CM0p + + + + + + + + + + External Pin + + + + + + + + + + Quad SPI + + + + + + + wl:smif[0] + + + + USB + + + + + + + wl:usb[0] + + + + SDHC0 + + + + + + + wl:sdhc[0] + - + - + - + - - - - - + + + + + @@ -1956,7 +1957,7 @@ SYS_TICK - + PATH_MUX4 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6016BZI-F04/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6016BZI-F04/studio/view.xml index 67119b768b..8d2b81143b 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6016BZI-F04/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6016BZI-F04/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6036BZI-F04/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6036BZI-F04/studio/view.xml index 607131a1f2..cbc09d674f 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6036BZI-F04/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6036BZI-F04/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6116BZI-F54/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6116BZI-F54/studio/view.xml index 65937588cb..f81c747ef8 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6116BZI-F54/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6116BZI-F54/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6117BZI-F34/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6117BZI-F34/studio/view.xml index 0eec5ef29e..540fe89bd7 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6117BZI-F34/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6117BZI-F34/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6117FDI-F02/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6117FDI-F02/studio/view.xml index 64cc75026a..907583f3da 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6117FDI-F02/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6117FDI-F02/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6117WI-F34/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6117WI-F34/studio/view.xml index 2652b7739f..76deb98685 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6117WI-F34/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6117WI-F34/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6136BZI-F14/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6136BZI-F14/studio/view.xml index 98d2217c6a..5faa4ba97c 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6136BZI-F14/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6136BZI-F14/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6136BZI-F34/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6136BZI-F34/studio/view.xml index 022ce8bff3..0812ea676e 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6136BZI-F34/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6136BZI-F34/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6136FDI-F42/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6136FDI-F42/studio/view.xml index 80c6d8877f..563fb0c5e1 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6136FDI-F42/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6136FDI-F42/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6136FTI-F42/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6136FTI-F42/studio/view.xml index c82d5714f6..b9e488e88b 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6136FTI-F42/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6136FTI-F42/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6137BZI-F14/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6137BZI-F14/studio/view.xml index 402cee19a4..f505e1d257 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6137BZI-F14/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6137BZI-F14/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6137BZI-F34/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6137BZI-F34/studio/view.xml index 8acedecafa..58d78594fd 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6137BZI-F34/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6137BZI-F34/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6137BZI-F54/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6137BZI-F54/studio/view.xml index b9e269ee2c..a557a0f02e 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6137BZI-F54/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6137BZI-F54/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6137FDI-F02/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6137FDI-F02/studio/view.xml index ada24afd8b..d91c6952ec 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6137FDI-F02/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6137FDI-F02/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6137WI-F54/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6137WI-F54/studio/view.xml index 7d3475d977..9b0581df5e 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6137WI-F54/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6137WI-F54/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6246BZI-D04/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6246BZI-D04/studio/view.xml index e6b33fda98..d0e4b06f0b 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6246BZI-D04/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6246BZI-D04/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247BFI-D54/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247BFI-D54/studio/view.xml index 0fb9e56d7a..1ed97c8487 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247BFI-D54/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247BFI-D54/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247BZI-AUD54/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247BZI-AUD54/studio/view.xml index b1c1248b3b..b170e5371c 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247BZI-AUD54/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247BZI-AUD54/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247BZI-D34/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247BZI-D34/studio/view.xml index b7d95b894a..59bf9166e6 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247BZI-D34/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247BZI-D34/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247BZI-D44/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247BZI-D44/studio/view.xml index 4548961b2e..6c81a44357 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247BZI-D44/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247BZI-D44/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247BZI-D54/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247BZI-D54/studio/view.xml index fe4edc4135..7b14363141 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247BZI-D54/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247BZI-D54/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247FDI-D02/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247FDI-D02/studio/view.xml index 493454bfd3..d004d337c4 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247FDI-D02/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247FDI-D02/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247FDI-D32/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247FDI-D32/studio/view.xml index 3ee96a9bff..dabd587e7c 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247FDI-D32/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247FDI-D32/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247FDI-D52/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247FDI-D52/studio/view.xml index 7efd340464..7da0077bd9 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247FDI-D52/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247FDI-D52/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247FTI-D52/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247FTI-D52/studio/view.xml index 44ec071d7f..63baacb1ff 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247FTI-D52/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247FTI-D52/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247WI-D54/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247WI-D54/studio/view.xml index e58adb5dbd..eb3dfbe0e8 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247WI-D54/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247WI-D54/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6316BZI-BLF03/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6316BZI-BLF03/studio/view.xml index 9975e58450..fec0a2fa74 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6316BZI-BLF03/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6316BZI-BLF03/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6316BZI-BLF04/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6316BZI-BLF04/studio/view.xml index 0b1ad376e0..6d2d86d7fb 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6316BZI-BLF04/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6316BZI-BLF04/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6316BZI-BLF53/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6316BZI-BLF53/studio/view.xml index f29e045e81..578c06a300 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6316BZI-BLF53/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6316BZI-BLF53/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6316BZI-BLF54/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6316BZI-BLF54/studio/view.xml index f378c17c32..b19845419c 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6316BZI-BLF54/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6316BZI-BLF54/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6336BZI-BLD13/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6336BZI-BLD13/studio/view.xml index d3cacc356d..e4453c57b6 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6336BZI-BLD13/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6336BZI-BLD13/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6336BZI-BLD14/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6336BZI-BLD14/studio/view.xml index 84e159f6e9..31d8c18aed 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6336BZI-BLD14/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6336BZI-BLD14/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6336BZI-BLF03/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6336BZI-BLF03/studio/view.xml index 03493ab6fa..5a991843ef 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6336BZI-BLF03/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6336BZI-BLF03/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6336BZI-BLF04/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6336BZI-BLF04/studio/view.xml index 737f025c42..0401ea002f 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6336BZI-BLF04/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6336BZI-BLF04/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6336BZI-BUD13/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6336BZI-BUD13/studio/view.xml index 65c2e46cfe..c670204260 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6336BZI-BUD13/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6336BZI-BUD13/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6336LQI-BLF02/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6336LQI-BLF02/studio/view.xml index fd68bf32a8..ff06c0d603 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6336LQI-BLF02/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6336LQI-BLF02/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6336LQI-BLF42/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6336LQI-BLF42/studio/view.xml index 0d5fab01d1..39798623db 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6336LQI-BLF42/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6336LQI-BLF42/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6337BZI-BLF13/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6337BZI-BLF13/studio/view.xml index 9fe0cdccd5..fa1dfb3c15 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6337BZI-BLF13/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6337BZI-BLF13/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BLD33/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BLD33/studio/view.xml index 226916d729..3e596ad8ae 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BLD33/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BLD33/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BLD34/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BLD34/studio/view.xml index 61af522e29..79f1e2accc 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BLD34/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BLD34/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BLD43/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BLD43/studio/view.xml index 3baba51028..e5373fd860 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BLD43/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BLD43/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BLD44/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BLD44/studio/view.xml index 955cf80e8f..c0011ee6d5 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BLD44/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BLD44/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BLD53/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BLD53/studio/view.xml index 6e72f32f8f..5def549190 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BLD53/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BLD53/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BLD54/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BLD54/studio/view.xml index cb40c6073f..b31840756c 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BLD54/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BLD54/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BUD33/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BUD33/studio/view.xml index 7f401613b3..7950ee0133 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BUD33/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BUD33/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BUD43/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BUD43/studio/view.xml index afcb9f1b34..eb0381e4ca 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BUD43/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BUD43/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BUD53/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BUD53/studio/view.xml index 316ef0718b..88e5bb3f38 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BUD53/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BUD53/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BLD13/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BLD13/studio/view.xml index 232bd19b46..31efde07a9 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BLD13/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BLD13/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BLD33/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BLD33/studio/view.xml index cdc915cf45..35ceda4838 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BLD33/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BLD33/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BLD43/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BLD43/studio/view.xml index 36340b5112..d866e101a5 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BLD43/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BLD43/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BLD53/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BLD53/studio/view.xml index 8022f45319..bcc087757d 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BLD53/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BLD53/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BUD13/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BUD13/studio/view.xml index cfede5daad..aed94c922c 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BUD13/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BUD13/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BUD33/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BUD33/studio/view.xml index fc0cd78720..ba1a54de70 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BUD33/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BUD33/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BUD43/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BUD43/studio/view.xml index e71bfba693..d41824c2bb 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BUD43/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BUD43/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BUD53/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BUD53/studio/view.xml index 0e25d64e94..f3418ad864 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BUD53/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BUD53/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347LQI-BLD52/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347LQI-BLD52/studio/view.xml index 7e2de6c1ef..058cec52e1 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347LQI-BLD52/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347LQI-BLD52/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C637BZI-BLD74/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C637BZI-BLD74/studio/view.xml index 9d20d02774..eec5fe41eb 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C637BZI-BLD74/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C637BZI-BLD74/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C637BZI-MD76/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C637BZI-MD76/studio/view.xml index 46ec52afff..80ed20816b 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C637BZI-MD76/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C637BZI-MD76/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C637FMI-BLD73/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C637FMI-BLD73/studio/view.xml index 9c48742a08..f17ecb0ecd 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C637FMI-BLD73/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C637FMI-BLD73/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C68237BZ-BLE/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C68237BZ-BLE/studio/view.xml index d4c9de2743..2d9743741b 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C68237BZ-BLE/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C68237BZ-BLE/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C68237FM-BLE/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C68237FM-BLE/studio/view.xml index a59eb6f6ff..65b6d8fd74 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C68237FM-BLE/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C68237FM-BLE/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CYB06447BZI-BLD53/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CYB06447BZI-BLD53/studio/view.xml index e38453199e..b7132cbc39 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CYB06447BZI-BLD53/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CYB06447BZI-BLD53/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CYB06447BZI-BLD54/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CYB06447BZI-BLD54/studio/view.xml index 9b78aba279..ac6b682147 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CYB06447BZI-BLD54/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CYB06447BZI-BLD54/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CYB06447BZI-D54/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CYB06447BZI-D54/studio/view.xml index 5bdca55eb7..345a40395b 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CYB06447BZI-D54/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CYB06447BZI-D54/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CYBLE-416045-02/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CYBLE-416045-02/studio/view.xml index 88a4d7a7d6..277ac06765 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CYBLE-416045-02/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CYBLE-416045-02/studio/view.xml @@ -36,7 +36,10 @@ - + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/hobto/pins.cydata b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/hobto/pins.cydata index e2c8abf5ee..384377e099 100755 Binary files a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/hobto/pins.cydata and b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/hobto/pins.cydata differ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/studio/connectivity/mxs40pass_ver2_v1.cydata b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/studio/connectivity/mxs40pass_ver2_v1.cydata deleted file mode 100755 index e1c7bf9e2a..0000000000 Binary files a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/studio/connectivity/mxs40pass_ver2_v1.cydata and /dev/null differ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/studio/connectivity/mxtcpwm_ver2_v1.cydata b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/studio/connectivity/mxtcpwm_ver2_v1.cydata deleted file mode 100755 index d13ca33138..0000000000 Binary files a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/studio/connectivity/mxtcpwm_ver2_v1.cydata and /dev/null differ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/studio/features.mk b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/studio/features.mk index 9ebc6baf81..a8dff07bb6 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/studio/features.mk +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/studio/features.mk @@ -2,36 +2,36 @@ # list of the MPNs that have that capability or feature. # Major device capabilities. -CY_DEVICES_WITH_M0P=CY8C6246BZI-D04 CY8C6247BZI-D44 CY8C6247BZI-D34 CY8C6247BZI-D54 CY8C6336BZI-BLD13 CY8C6347BZI-BLD43 CY8C6347BZI-BLD33 CY8C6347BZI-BLD53 CY8C6347FMI-BLD13 CY8C6347FMI-BLD43 CY8C6347FMI-BLD33 CY8C6347FMI-BLD53 CY8C637BZI-MD76 CY8C637BZI-BLD74 CY8C637FMI-BLD73 CY8C68237BZ-BLE CY8C68237FM-BLE CY8C6247FDI-D02 CY8C6247FDI-D32 CY8C6336BZI-BUD13 CY8C6347BZI-BUD43 CY8C6347BZI-BUD33 CY8C6347BZI-BUD53 CY8C6247FDI-D52 CY8C6247FTI-D52 CY8C6247BZI-AUD54 CY8C6336BZI-BLD14 CY8C6347BZI-BLD44 CY8C6347BZI-BLD34 CY8C6347BZI-BLD54 CY8C6247BFI-D54 CYBLE-416045-02 CY8C6347FMI-BUD53 CY8C6347FMI-BUD13 CY8C6347FMI-BUD43 CY8C6347FMI-BUD33 CY8C6247WI-D54 CY8C6347LQI-BLD52 CYB06447BZI-BLD54 CYB06447BZI-BLD53 CYB06447BZI-D54 CY8C624ABZI-D44 CY8C624AAZI-D44 CY8C624AFNI-D43 CY8C624ABZI-D04 CY8C624ABZI-D14 CY8C624AAZI-D14 CY8C6248AZI-D14 CY8C6248BZI-D44 CY8C6248AZI-D44 CY8C6248FNI-D43 CY8C624ALQI-D42 CYB0644ABZI-S2D44 CYS0644ABZI-S2D44 CY8C624ABZI-S2D44A0 CY8C624ABZI-S2D44 CY8C624AAZI-S2D44 CY8C624AFNI-S2D43 CY8C624ABZI-S2D04 CY8C624ABZI-S2D14 CY8C624AAZI-S2D14 CY8C6248AZI-S2D14 CY8C6248BZI-S2D44 CY8C6248AZI-S2D44 CY8C6248FNI-S2D43 CY8C6245AZI-S3D72 CY8C6245LQI-S3D72 CY8C6245FNI-S3D71 CY8C6245AZI-S3D62 CY8C6245LQI-S3D62 CY8C6245AZI-S3D42 CY8C6245LQI-S3D42 CYB06445LQI-S3D42 CY8C6245FNI-S3D41 CY8C6245AZI-S3D12 CY8C6245LQI-S3D12 CY8C6245FNI-S3D11 CY8C6245AZI-S3D02 CY8C6245LQI-S3D02 CY8C6245W-S3D72 +CY_DEVICES_WITH_M0P=CY8C6246BZI-D04 CY8C6247BZI-D44 CY8C6247BZI-D34 CY8C6247BZI-D54 CY8C6336BZI-BLD13 CY8C6347BZI-BLD43 CY8C6347BZI-BLD33 CY8C6347BZI-BLD53 CY8C6347FMI-BLD13 CY8C6347FMI-BLD43 CY8C6347FMI-BLD33 CY8C6347FMI-BLD53 CY8C637BZI-MD76 CY8C637BZI-BLD74 CY8C637FMI-BLD73 CY8C68237BZ-BLE CY8C68237FM-BLE CY8C6247FDI-D02 CY8C6247FDI-D32 CY8C6336BZI-BUD13 CY8C6347BZI-BUD43 CY8C6347BZI-BUD33 CY8C6347BZI-BUD53 CY8C6247FDI-D52 CY8C6247FTI-D52 CY8C6247BZI-AUD54 CY8C6336BZI-BLD14 CY8C6347BZI-BLD44 CY8C6347BZI-BLD34 CY8C6347BZI-BLD54 CY8C6247BFI-D54 CYBLE-416045-02 CY8C6347FMI-BUD53 CY8C6347FMI-BUD13 CY8C6347FMI-BUD43 CY8C6347FMI-BUD33 CY8C6247WI-D54 CY8C6347LQI-BLD52 CYB06447BZI-BLD54 CYB06447BZI-BLD53 CYB06447BZI-D54 CYB0644ABZI-S2D44 CYS0644ABZI-S2D44 CY8C624ABZI-S2D44A0 CY8C624ABZI-S2D44 CY8C624AAZI-S2D44 CY8C624AFNI-S2D43 CY8C624ABZI-S2D04 CY8C624ABZI-S2D14 CY8C624AAZI-S2D14 CY8C6248AZI-S2D14 CY8C6248BZI-S2D44 CY8C6248AZI-S2D44 CY8C6248FNI-S2D43 CY8C624ABZI-D44 CY8C624AAZI-D44 CY8C624AFNI-D43 CY8C624ABZI-D04 CY8C624ABZI-D14 CY8C624AAZI-D14 CY8C6248AZI-D14 CY8C6248BZI-D44 CY8C6248AZI-D44 CY8C6248FNI-D43 CY8C624ALQI-D42 CY8C6245AZI-S3D72 CY8C6245LQI-S3D72 CY8C6245FNI-S3D71 CY8C6245AZI-S3D62 CY8C6245LQI-S3D62 CY8C6245AZI-S3D42 CY8C6245LQI-S3D42 CYB06445LQI-S3D42 CY8C6245FNI-S3D41 CY8C6245AZI-S3D12 CY8C6245LQI-S3D12 CY8C6245FNI-S3D11 CY8C6245AZI-S3D02 CY8C6245LQI-S3D02 CY8C6245WI-S3D72 CY_DEVICES_WITH_BLE=CY8C6336BZI-BLF03 CY8C6316BZI-BLF03 CY8C6316BZI-BLF53 CY8C6336BZI-BLD13 CY8C6347BZI-BLD43 CY8C6347BZI-BLD33 CY8C6347BZI-BLD53 CY8C6347FMI-BLD13 CY8C6347FMI-BLD43 CY8C6347FMI-BLD33 CY8C6347FMI-BLD53 CY8C637BZI-BLD74 CY8C637FMI-BLD73 CY8C68237BZ-BLE CY8C68237FM-BLE CY8C6336BZI-BUD13 CY8C6347BZI-BUD43 CY8C6347BZI-BUD33 CY8C6347BZI-BUD53 CY8C6337BZI-BLF13 CY8C6336BZI-BLF04 CY8C6316BZI-BLF04 CY8C6316BZI-BLF54 CY8C6336BZI-BLD14 CY8C6347BZI-BLD44 CY8C6347BZI-BLD34 CY8C6347BZI-BLD54 CYBLE-416045-02 CY8C6347FMI-BUD53 CY8C6347FMI-BUD13 CY8C6347FMI-BUD43 CY8C6347FMI-BUD33 CY8C6336LQI-BLF02 CY8C6336LQI-BLF42 CY8C6347LQI-BLD52 CYB06447BZI-BLD54 CYB06447BZI-BLD53 CY_DEVICES_WITH_UDBS=CY8C6116BZI-F54 CY8C6136BZI-F34 CY8C6137BZI-F34 CY8C6137BZI-F54 CY8C6117BZI-F34 CY8C6247BZI-D34 CY8C6247BZI-D54 CY8C6316BZI-BLF53 CY8C6347BZI-BLD33 CY8C6347BZI-BLD53 CY8C6347FMI-BLD33 CY8C6347FMI-BLD53 CY8C637BZI-MD76 CY8C637BZI-BLD74 CY8C637FMI-BLD73 CY8C6247FDI-D32 CY8C6347BZI-BUD33 CY8C6347BZI-BUD53 CY8C6247FDI-D52 CY8C6247FTI-D52 CY8C6247BZI-AUD54 CY8C6316BZI-BLF54 CY8C6347BZI-BLD34 CY8C6347BZI-BLD54 CY8C6247BFI-D54 CYBLE-416045-02 CY8C6347FMI-BUD53 CY8C6347FMI-BUD33 CY8C6137WI-F54 CY8C6117WI-F34 CY8C6247WI-D54 CY8C6347LQI-BLD52 CYB06447BZI-BLD54 CYB06447BZI-BLD53 CYB06447BZI-D54 -CY_DEVICES_WITH_FS_USB=CY8C6036BZI-F04 CY8C6016BZI-F04 CY8C6116BZI-F54 CY8C6136BZI-F14 CY8C6136BZI-F34 CY8C6137BZI-F14 CY8C6137BZI-F34 CY8C6137BZI-F54 CY8C6117BZI-F34 CY8C6246BZI-D04 CY8C6247BZI-D44 CY8C6247BZI-D34 CY8C6247BZI-D54 CY8C637BZI-MD76 CY8C6137FDI-F02 CY8C6117FDI-F02 CY8C6247FDI-D02 CY8C6247FDI-D32 CY8C6336BZI-BUD13 CY8C6347BZI-BUD43 CY8C6347BZI-BUD33 CY8C6347BZI-BUD53 CY8C6136FDI-F42 CY8C6247FDI-D52 CY8C6136FTI-F42 CY8C6247FTI-D52 CY8C6247BZI-AUD54 CY8C6336BZI-BLF04 CY8C6316BZI-BLF04 CY8C6316BZI-BLF54 CY8C6336BZI-BLD14 CY8C6347BZI-BLD44 CY8C6347BZI-BLD34 CY8C6347BZI-BLD54 CY8C6247BFI-D54 CY8C6347FMI-BUD53 CY8C6347FMI-BUD13 CY8C6347FMI-BUD43 CY8C6347FMI-BUD33 CY8C6137WI-F54 CY8C6117WI-F34 CY8C6247WI-D54 CYB06447BZI-BLD54 CYB06447BZI-D54 CY8C624ABZI-D44 CY8C624AAZI-D44 CY8C624AFNI-D43 CY8C624ABZI-D04 CY8C624ABZI-D14 CY8C624AAZI-D14 CY8C6248AZI-D14 CY8C6248BZI-D44 CY8C6248AZI-D44 CY8C6248FNI-D43 CY8C624ALQI-D42 CYB0644ABZI-S2D44 CYS0644ABZI-S2D44 CY8C624ABZI-S2D44A0 CY8C624ABZI-S2D44 CY8C624AAZI-S2D44 CY8C624AFNI-S2D43 CY8C624ABZI-S2D04 CY8C624ABZI-S2D14 CY8C624AAZI-S2D14 CY8C6248AZI-S2D14 CY8C6248BZI-S2D44 CY8C6248AZI-S2D44 CY8C6248FNI-S2D43 CY8C6245AZI-S3D72 CY8C6245LQI-S3D72 CY8C6245AZI-S3D62 CY8C6245LQI-S3D62 CY8C6245AZI-S3D42 CY8C6245LQI-S3D42 CYB06445LQI-S3D42 CY8C6245AZI-S3D12 CY8C6245LQI-S3D12 CY8C6245AZI-S3D02 CY8C6245LQI-S3D02 CY8C6245W-S3D72 -CY_DEVICES_WITH_CAPSENSE=CY8C6116BZI-F54 CY8C6136BZI-F14 CY8C6136BZI-F34 CY8C6137BZI-F14 CY8C6137BZI-F34 CY8C6137BZI-F54 CY8C6117BZI-F34 CY8C6247BZI-D44 CY8C6247BZI-D34 CY8C6247BZI-D54 CY8C6316BZI-BLF53 CY8C6336BZI-BLD13 CY8C6347BZI-BLD43 CY8C6347BZI-BLD33 CY8C6347BZI-BLD53 CY8C6347FMI-BLD13 CY8C6347FMI-BLD43 CY8C6347FMI-BLD33 CY8C6347FMI-BLD53 CY8C637BZI-MD76 CY8C637BZI-BLD74 CY8C637FMI-BLD73 CY8C68237BZ-BLE CY8C68237FM-BLE CY8C6247FDI-D32 CY8C6336BZI-BUD13 CY8C6347BZI-BUD43 CY8C6347BZI-BUD33 CY8C6347BZI-BUD53 CY8C6337BZI-BLF13 CY8C6136FDI-F42 CY8C6247FDI-D52 CY8C6136FTI-F42 CY8C6247FTI-D52 CY8C6247BZI-AUD54 CY8C6316BZI-BLF54 CY8C6336BZI-BLD14 CY8C6347BZI-BLD44 CY8C6347BZI-BLD34 CY8C6347BZI-BLD54 CY8C6247BFI-D54 CYBLE-416045-02 CY8C6347FMI-BUD53 CY8C6347FMI-BUD13 CY8C6347FMI-BUD43 CY8C6347FMI-BUD33 CY8C6137WI-F54 CY8C6117WI-F34 CY8C6247WI-D54 CY8C6336LQI-BLF42 CY8C6347LQI-BLD52 CYB06447BZI-BLD54 CYB06447BZI-BLD53 CYB06447BZI-D54 CY8C624ABZI-D44 CY8C624AAZI-D44 CY8C624AFNI-D43 CY8C624ABZI-D14 CY8C624AAZI-D14 CY8C6248AZI-D14 CY8C6248BZI-D44 CY8C6248AZI-D44 CY8C6248FNI-D43 CY8C624ALQI-D42 CYB0644ABZI-S2D44 CYS0644ABZI-S2D44 CY8C624ABZI-S2D44A0 CY8C624ABZI-S2D44 CY8C624AAZI-S2D44 CY8C624AFNI-S2D43 CY8C624ABZI-S2D14 CY8C624AAZI-S2D14 CY8C6248AZI-S2D14 CY8C6248BZI-S2D44 CY8C6248AZI-S2D44 CY8C6248FNI-S2D43 CY8C6245AZI-S3D72 CY8C6245LQI-S3D72 CY8C6245FNI-S3D71 CY8C6245AZI-S3D42 CY8C6245LQI-S3D42 CYB06445LQI-S3D42 CY8C6245FNI-S3D41 CY8C6245AZI-S3D12 CY8C6245LQI-S3D12 CY8C6245FNI-S3D11 CY8C6245W-S3D72 -CY_DEVICES_WITH_CRYPTO=CY8C6116BZI-F54 CY8C6137BZI-F54 CY8C6247BZI-D44 CY8C6247BZI-D54 CY8C6316BZI-BLF53 CY8C6347BZI-BLD43 CY8C6347BZI-BLD53 CY8C6347FMI-BLD43 CY8C6347FMI-BLD53 CY8C637BZI-MD76 CY8C637BZI-BLD74 CY8C637FMI-BLD73 CY8C68237BZ-BLE CY8C68237FM-BLE CY8C6347BZI-BUD43 CY8C6347BZI-BUD53 CY8C6136FDI-F42 CY8C6247FDI-D52 CY8C6136FTI-F42 CY8C6247FTI-D52 CY8C6247BZI-AUD54 CY8C6316BZI-BLF54 CY8C6347BZI-BLD44 CY8C6347BZI-BLD54 CY8C6247BFI-D54 CYBLE-416045-02 CY8C6347FMI-BUD53 CY8C6347FMI-BUD43 CY8C6137WI-F54 CY8C6247WI-D54 CY8C6336LQI-BLF42 CY8C6347LQI-BLD52 CYB06447BZI-BLD54 CYB06447BZI-BLD53 CYB06447BZI-D54 CY8C624ABZI-D44 CY8C624AAZI-D44 CY8C624AFNI-D43 CY8C6248BZI-D44 CY8C6248AZI-D44 CY8C6248FNI-D43 CY8C624ALQI-D42 CYB0644ABZI-S2D44 CYS0644ABZI-S2D44 CY8C624ABZI-S2D44A0 CY8C624ABZI-S2D44 CY8C624AAZI-S2D44 CY8C624AFNI-S2D43 CY8C6248BZI-S2D44 CY8C6248AZI-S2D44 CY8C6248FNI-S2D43 CY8C6245AZI-S3D72 CY8C6245LQI-S3D72 CY8C6245FNI-S3D71 CY8C6245AZI-S3D42 CY8C6245LQI-S3D42 CYB06445LQI-S3D42 CY8C6245FNI-S3D41 CY8C6245W-S3D72 +CY_DEVICES_WITH_FS_USB=CY8C6036BZI-F04 CY8C6016BZI-F04 CY8C6116BZI-F54 CY8C6136BZI-F14 CY8C6136BZI-F34 CY8C6137BZI-F14 CY8C6137BZI-F34 CY8C6137BZI-F54 CY8C6117BZI-F34 CY8C6246BZI-D04 CY8C6247BZI-D44 CY8C6247BZI-D34 CY8C6247BZI-D54 CY8C637BZI-MD76 CY8C6137FDI-F02 CY8C6117FDI-F02 CY8C6247FDI-D02 CY8C6247FDI-D32 CY8C6336BZI-BUD13 CY8C6347BZI-BUD43 CY8C6347BZI-BUD33 CY8C6347BZI-BUD53 CY8C6136FDI-F42 CY8C6247FDI-D52 CY8C6136FTI-F42 CY8C6247FTI-D52 CY8C6247BZI-AUD54 CY8C6336BZI-BLF04 CY8C6316BZI-BLF04 CY8C6316BZI-BLF54 CY8C6336BZI-BLD14 CY8C6347BZI-BLD44 CY8C6347BZI-BLD34 CY8C6347BZI-BLD54 CY8C6247BFI-D54 CY8C6347FMI-BUD53 CY8C6347FMI-BUD13 CY8C6347FMI-BUD43 CY8C6347FMI-BUD33 CY8C6137WI-F54 CY8C6117WI-F34 CY8C6247WI-D54 CYB06447BZI-BLD54 CYB06447BZI-D54 CYB0644ABZI-S2D44 CYS0644ABZI-S2D44 CY8C624ABZI-S2D44A0 CY8C624ABZI-S2D44 CY8C624AAZI-S2D44 CY8C624AFNI-S2D43 CY8C624ABZI-S2D04 CY8C624ABZI-S2D14 CY8C624AAZI-S2D14 CY8C6248AZI-S2D14 CY8C6248BZI-S2D44 CY8C6248AZI-S2D44 CY8C6248FNI-S2D43 CY8C614ABZI-S2F04 CY8C614AAZI-S2F04 CY8C614AFNI-S2F03 CY8C614AAZI-S2F14 CY8C614ABZI-S2F44 CY8C614AAZI-S2F44 CY8C614AFNI-S2F43 CY8C6148BZI-S2F44 CY8C6148AZI-S2F44 CY8C6148FNI-S2F43 CY8C624ABZI-D44 CY8C624AAZI-D44 CY8C624AFNI-D43 CY8C624ABZI-D04 CY8C624ABZI-D14 CY8C624AAZI-D14 CY8C6248AZI-D14 CY8C6248BZI-D44 CY8C6248AZI-D44 CY8C6248FNI-D43 CY8C624ALQI-D42 CY8C6245AZI-S3D72 CY8C6245LQI-S3D72 CY8C6245AZI-S3D62 CY8C6245LQI-S3D62 CY8C6245AZI-S3D42 CY8C6245LQI-S3D42 CYB06445LQI-S3D42 CY8C6245AZI-S3D12 CY8C6245LQI-S3D12 CY8C6245AZI-S3D02 CY8C6245LQI-S3D02 CY8C6245WI-S3D72 CY8C6145AZI-S3F72 CY8C6145LQI-S3F72 CY8C6145AZI-S3F62 CY8C6145LQI-S3F62 CY8C6145AZI-S3F42 CY8C6145LQI-S3F42 CY8C6145AZI-S3F12 CY8C6145LQI-S3F12 CY8C6145AZI-S3F02 CY8C6145LQI-S3F02 +CY_DEVICES_WITH_CAPSENSE=CY8C6116BZI-F54 CY8C6136BZI-F14 CY8C6136BZI-F34 CY8C6137BZI-F14 CY8C6137BZI-F34 CY8C6137BZI-F54 CY8C6117BZI-F34 CY8C6247BZI-D44 CY8C6247BZI-D34 CY8C6247BZI-D54 CY8C6316BZI-BLF53 CY8C6336BZI-BLD13 CY8C6347BZI-BLD43 CY8C6347BZI-BLD33 CY8C6347BZI-BLD53 CY8C6347FMI-BLD13 CY8C6347FMI-BLD43 CY8C6347FMI-BLD33 CY8C6347FMI-BLD53 CY8C637BZI-MD76 CY8C637BZI-BLD74 CY8C637FMI-BLD73 CY8C68237BZ-BLE CY8C68237FM-BLE CY8C6247FDI-D32 CY8C6336BZI-BUD13 CY8C6347BZI-BUD43 CY8C6347BZI-BUD33 CY8C6347BZI-BUD53 CY8C6337BZI-BLF13 CY8C6136FDI-F42 CY8C6247FDI-D52 CY8C6136FTI-F42 CY8C6247FTI-D52 CY8C6247BZI-AUD54 CY8C6316BZI-BLF54 CY8C6336BZI-BLD14 CY8C6347BZI-BLD44 CY8C6347BZI-BLD34 CY8C6347BZI-BLD54 CY8C6247BFI-D54 CYBLE-416045-02 CY8C6347FMI-BUD53 CY8C6347FMI-BUD13 CY8C6347FMI-BUD43 CY8C6347FMI-BUD33 CY8C6137WI-F54 CY8C6117WI-F34 CY8C6247WI-D54 CY8C6336LQI-BLF42 CY8C6347LQI-BLD52 CYB06447BZI-BLD54 CYB06447BZI-BLD53 CYB06447BZI-D54 CYB0644ABZI-S2D44 CYS0644ABZI-S2D44 CY8C624ABZI-S2D44A0 CY8C624ABZI-S2D44 CY8C624AAZI-S2D44 CY8C624AFNI-S2D43 CY8C624ABZI-S2D14 CY8C624AAZI-S2D14 CY8C6248AZI-S2D14 CY8C6248BZI-S2D44 CY8C6248AZI-S2D44 CY8C6248FNI-S2D43 CY8C614AAZI-S2F14 CY8C614ABZI-S2F44 CY8C614AAZI-S2F44 CY8C614AFNI-S2F43 CY8C6148BZI-S2F44 CY8C6148AZI-S2F44 CY8C6148FNI-S2F43 CY8C624ABZI-D44 CY8C624AAZI-D44 CY8C624AFNI-D43 CY8C624ABZI-D14 CY8C624AAZI-D14 CY8C6248AZI-D14 CY8C6248BZI-D44 CY8C6248AZI-D44 CY8C6248FNI-D43 CY8C624ALQI-D42 CY8C6245AZI-S3D72 CY8C6245LQI-S3D72 CY8C6245FNI-S3D71 CY8C6245AZI-S3D42 CY8C6245LQI-S3D42 CYB06445LQI-S3D42 CY8C6245FNI-S3D41 CY8C6245AZI-S3D12 CY8C6245LQI-S3D12 CY8C6245FNI-S3D11 CY8C6245WI-S3D72 CY8C6145AZI-S3F72 CY8C6145LQI-S3F72 CY8C6145FNI-S3F71 CY8C6145AZI-S3F42 CY8C6145LQI-S3F42 CY8C6145FNI-S3F41 CY8C6145AZI-S3F12 CY8C6145LQI-S3F12 CY8C6145FNI-S3F11 +CY_DEVICES_WITH_CRYPTO=CY8C6116BZI-F54 CY8C6137BZI-F54 CY8C6247BZI-D44 CY8C6247BZI-D54 CY8C6316BZI-BLF53 CY8C6347BZI-BLD43 CY8C6347BZI-BLD53 CY8C6347FMI-BLD43 CY8C6347FMI-BLD53 CY8C637BZI-MD76 CY8C637BZI-BLD74 CY8C637FMI-BLD73 CY8C68237BZ-BLE CY8C68237FM-BLE CY8C6347BZI-BUD43 CY8C6347BZI-BUD53 CY8C6136FDI-F42 CY8C6247FDI-D52 CY8C6136FTI-F42 CY8C6247FTI-D52 CY8C6247BZI-AUD54 CY8C6316BZI-BLF54 CY8C6347BZI-BLD44 CY8C6347BZI-BLD54 CY8C6247BFI-D54 CYBLE-416045-02 CY8C6347FMI-BUD53 CY8C6347FMI-BUD43 CY8C6137WI-F54 CY8C6247WI-D54 CY8C6336LQI-BLF42 CY8C6347LQI-BLD52 CYB06447BZI-BLD54 CYB06447BZI-BLD53 CYB06447BZI-D54 CYB0644ABZI-S2D44 CYS0644ABZI-S2D44 CY8C624ABZI-S2D44A0 CY8C624ABZI-S2D44 CY8C624AAZI-S2D44 CY8C624AFNI-S2D43 CY8C6248BZI-S2D44 CY8C6248AZI-S2D44 CY8C6248FNI-S2D43 CY8C614ABZI-S2F44 CY8C614AAZI-S2F44 CY8C614AFNI-S2F43 CY8C6148BZI-S2F44 CY8C6148AZI-S2F44 CY8C6148FNI-S2F43 CY8C624ABZI-D44 CY8C624AAZI-D44 CY8C624AFNI-D43 CY8C6248BZI-D44 CY8C6248AZI-D44 CY8C6248FNI-D43 CY8C624ALQI-D42 CY8C6245AZI-S3D72 CY8C6245LQI-S3D72 CY8C6245FNI-S3D71 CY8C6245AZI-S3D42 CY8C6245LQI-S3D42 CYB06445LQI-S3D42 CY8C6245FNI-S3D41 CY8C6245WI-S3D72 CY8C6145AZI-S3F72 CY8C6145LQI-S3F72 CY8C6145FNI-S3F71 CY8C6145AZI-S3F42 CY8C6145LQI-S3F42 CY8C6145FNI-S3F41 CY_DEVICES_SECURE=CYB06447BZI-BLD54 CYB06447BZI-BLD53 CYB06447BZI-D54 CYB0644ABZI-S2D44 CYS0644ABZI-S2D44 CYB06445LQI-S3D42 # Different classifications of devices. CY_DEVICES_WITH_DIE_PSOC6ABLE2=CY8C6036BZI-F04 CY8C6016BZI-F04 CY8C6116BZI-F54 CY8C6136BZI-F14 CY8C6136BZI-F34 CY8C6137BZI-F14 CY8C6137BZI-F34 CY8C6137BZI-F54 CY8C6117BZI-F34 CY8C6246BZI-D04 CY8C6247BZI-D44 CY8C6247BZI-D34 CY8C6247BZI-D54 CY8C6336BZI-BLF03 CY8C6316BZI-BLF03 CY8C6316BZI-BLF53 CY8C6336BZI-BLD13 CY8C6347BZI-BLD43 CY8C6347BZI-BLD33 CY8C6347BZI-BLD53 CY8C6347FMI-BLD13 CY8C6347FMI-BLD43 CY8C6347FMI-BLD33 CY8C6347FMI-BLD53 CY8C637BZI-MD76 CY8C637BZI-BLD74 CY8C637FMI-BLD73 CY8C68237BZ-BLE CY8C68237FM-BLE CY8C6137FDI-F02 CY8C6117FDI-F02 CY8C6247FDI-D02 CY8C6247FDI-D32 CY8C6336BZI-BUD13 CY8C6347BZI-BUD43 CY8C6347BZI-BUD33 CY8C6347BZI-BUD53 CY8C6337BZI-BLF13 CY8C6136FDI-F42 CY8C6247FDI-D52 CY8C6136FTI-F42 CY8C6247FTI-D52 CY8C6247BZI-AUD54 CY8C6336BZI-BLF04 CY8C6316BZI-BLF04 CY8C6316BZI-BLF54 CY8C6336BZI-BLD14 CY8C6347BZI-BLD44 CY8C6347BZI-BLD34 CY8C6347BZI-BLD54 CY8C6247BFI-D54 CYBLE-416045-02 CY8C6347FMI-BUD53 CY8C6347FMI-BUD13 CY8C6347FMI-BUD43 CY8C6347FMI-BUD33 CY8C6137WI-F54 CY8C6117WI-F34 CY8C6247WI-D54 CY8C6336LQI-BLF02 CY8C6336LQI-BLF42 CY8C6347LQI-BLD52 CYB06447BZI-BLD54 CYB06447BZI-BLD53 CYB06447BZI-D54 -CY_DEVICES_WITH_DIE_PSOC6A2M=CY8C624ABZI-D44 CY8C624AAZI-D44 CY8C624AFNI-D43 CY8C624ABZI-D04 CY8C624ABZI-D14 CY8C624AAZI-D14 CY8C6248AZI-D14 CY8C6248BZI-D44 CY8C6248AZI-D44 CY8C6248FNI-D43 CY8C624ALQI-D42 CYB0644ABZI-S2D44 CYS0644ABZI-S2D44 CY8C624ABZI-S2D44A0 CY8C624ABZI-S2D44 CY8C624AAZI-S2D44 CY8C624AFNI-S2D43 CY8C624ABZI-S2D04 CY8C624ABZI-S2D14 CY8C624AAZI-S2D14 CY8C6248AZI-S2D14 CY8C6248BZI-S2D44 CY8C6248AZI-S2D44 CY8C6248FNI-S2D43 -CY_DEVICES_WITH_DIE_PSOC6A512K=CY8C6245AZI-S3D72 CY8C6245LQI-S3D72 CY8C6245FNI-S3D71 CY8C6245AZI-S3D62 CY8C6245LQI-S3D62 CY8C6245AZI-S3D42 CY8C6245LQI-S3D42 CYB06445LQI-S3D42 CY8C6245FNI-S3D41 CY8C6245AZI-S3D12 CY8C6245LQI-S3D12 CY8C6245FNI-S3D11 CY8C6245AZI-S3D02 CY8C6245LQI-S3D02 CY8C6245W-S3D72 +CY_DEVICES_WITH_DIE_PSOC6A2M=CYB0644ABZI-S2D44 CYS0644ABZI-S2D44 CY8C624ABZI-S2D44A0 CY8C624ABZI-S2D44 CY8C624AAZI-S2D44 CY8C624AFNI-S2D43 CY8C624ABZI-S2D04 CY8C624ABZI-S2D14 CY8C624AAZI-S2D14 CY8C6248AZI-S2D14 CY8C6248BZI-S2D44 CY8C6248AZI-S2D44 CY8C6248FNI-S2D43 CY8C614ABZI-S2F04 CY8C614AAZI-S2F04 CY8C614AFNI-S2F03 CY8C614AAZI-S2F14 CY8C614ABZI-S2F44 CY8C614AAZI-S2F44 CY8C614AFNI-S2F43 CY8C6148BZI-S2F44 CY8C6148AZI-S2F44 CY8C6148FNI-S2F43 CY8C624ABZI-D44 CY8C624AAZI-D44 CY8C624AFNI-D43 CY8C624ABZI-D04 CY8C624ABZI-D14 CY8C624AAZI-D14 CY8C6248AZI-D14 CY8C6248BZI-D44 CY8C6248AZI-D44 CY8C6248FNI-D43 CY8C624ALQI-D42 +CY_DEVICES_WITH_DIE_PSOC6A512K=CY8C6245AZI-S3D72 CY8C6245LQI-S3D72 CY8C6245FNI-S3D71 CY8C6245AZI-S3D62 CY8C6245LQI-S3D62 CY8C6245AZI-S3D42 CY8C6245LQI-S3D42 CYB06445LQI-S3D42 CY8C6245FNI-S3D41 CY8C6245AZI-S3D12 CY8C6245LQI-S3D12 CY8C6245FNI-S3D11 CY8C6245AZI-S3D02 CY8C6245LQI-S3D02 CY8C6245WI-S3D72 CY8C6145AZI-S3F72 CY8C6145LQI-S3F72 CY8C6145FNI-S3F71 CY8C6145AZI-S3F62 CY8C6145LQI-S3F62 CY8C6145AZI-S3F42 CY8C6145LQI-S3F42 CY8C6145FNI-S3F41 CY8C6145AZI-S3F12 CY8C6145LQI-S3F12 CY8C6145FNI-S3F11 CY8C6145AZI-S3F02 CY8C6145LQI-S3F02 -CY_DEVICES_WITH_FLASH_KB_512=CY8C6036BZI-F04 CY8C6016BZI-F04 CY8C6116BZI-F54 CY8C6136BZI-F14 CY8C6136BZI-F34 CY8C6246BZI-D04 CY8C6336BZI-BLF03 CY8C6316BZI-BLF03 CY8C6316BZI-BLF53 CY8C6336BZI-BLD13 CY8C6336BZI-BUD13 CY8C6136FDI-F42 CY8C6136FTI-F42 CY8C6336BZI-BLF04 CY8C6316BZI-BLF04 CY8C6316BZI-BLF54 CY8C6336BZI-BLD14 CY8C6336LQI-BLF02 CY8C6336LQI-BLF42 CY8C6245AZI-S3D72 CY8C6245LQI-S3D72 CY8C6245FNI-S3D71 CY8C6245AZI-S3D62 CY8C6245LQI-S3D62 CY8C6245AZI-S3D42 CY8C6245LQI-S3D42 CY8C6245FNI-S3D41 CY8C6245AZI-S3D12 CY8C6245LQI-S3D12 CY8C6245FNI-S3D11 CY8C6245AZI-S3D02 CY8C6245LQI-S3D02 CY8C6245W-S3D72 -CY_DEVICES_WITH_FLASH_KB_1024=CY8C6137BZI-F14 CY8C6137BZI-F34 CY8C6137BZI-F54 CY8C6117BZI-F34 CY8C6247BZI-D44 CY8C6247BZI-D34 CY8C6247BZI-D54 CY8C6347BZI-BLD43 CY8C6347BZI-BLD33 CY8C6347BZI-BLD53 CY8C6347FMI-BLD13 CY8C6347FMI-BLD43 CY8C6347FMI-BLD33 CY8C6347FMI-BLD53 CY8C637BZI-MD76 CY8C637BZI-BLD74 CY8C637FMI-BLD73 CY8C68237BZ-BLE CY8C68237FM-BLE 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CY8C6145AZI-S3F42 CY8C6145LQI-S3F42 CY8C6145FNI-S3F41 CY8C6145AZI-S3F12 CY8C6145LQI-S3F12 CY8C6145FNI-S3F11 CY8C6145AZI-S3F02 CY8C6145LQI-S3F02 CY_DEVICES_WITH_MAX_SPEED_MHZ_50=CY8C6016BZI-F04 CY8C6116BZI-F54 CY8C6117BZI-F34 CY8C6316BZI-BLF03 CY8C6316BZI-BLF53 CY8C6117FDI-F02 CY8C6316BZI-BLF04 CY8C6316BZI-BLF54 CY8C6117WI-F34 -CY_DEVICES_WITH_PACKAGE_124-BGA=CY8C6036BZI-F04 CY8C6016BZI-F04 CY8C6116BZI-F54 CY8C6136BZI-F14 CY8C6136BZI-F34 CY8C6137BZI-F14 CY8C6137BZI-F34 CY8C6137BZI-F54 CY8C6117BZI-F34 CY8C6246BZI-D04 CY8C6247BZI-D44 CY8C6247BZI-D34 CY8C6247BZI-D54 CY8C637BZI-MD76 CY8C6247BZI-AUD54 CY8C6247BFI-D54 CY8C6137WI-F54 CY8C6117WI-F34 CY8C6247WI-D54 CYB06447BZI-D54 CY8C624ABZI-D44 CY8C624ABZI-D04 CY8C624ABZI-D14 CY8C6248BZI-D44 CYB0644ABZI-S2D44 CYS0644ABZI-S2D44 CY8C624ABZI-S2D44A0 CY8C624ABZI-S2D44 CY8C624ABZI-S2D04 CY8C624ABZI-S2D14 CY8C6248BZI-S2D44 +CY_DEVICES_WITH_PACKAGE_124-BGA=CY8C6036BZI-F04 CY8C6016BZI-F04 CY8C6116BZI-F54 CY8C6136BZI-F14 CY8C6136BZI-F34 CY8C6137BZI-F14 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CY8C6247FTI-D52 @@ -40,9 +40,10 @@ CY_DEVICES_WITH_PACKAGE_124-BGA-SIP=CY8C6336BZI-BLF04 CY8C6316BZI-BLF04 CY8C6316 CY_DEVICES_WITH_PACKAGE_43-SMT=CYBLE-416045-02 CY_DEVICES_WITH_PACKAGE_104-M-CSP-BLE-USB=CY8C6347FMI-BUD53 CY8C6347FMI-BUD13 CY8C6347FMI-BUD43 CY8C6347FMI-BUD33 CY_DEVICES_WITH_PACKAGE_68-QFN-BLE=CY8C6336LQI-BLF02 CY8C6336LQI-BLF42 CY8C6347LQI-BLD52 -CY_DEVICES_WITH_PACKAGE_128-TQFP=CY8C624AAZI-D44 CY8C624AAZI-D14 CY8C6248AZI-D14 CY8C6248AZI-D44 CY8C624AAZI-S2D44 CY8C624AAZI-S2D14 CY8C6248AZI-S2D14 CY8C6248AZI-S2D44 -CY_DEVICES_WITH_PACKAGE_100-WLCSP=CY8C624AFNI-D43 CY8C6248FNI-D43 CY8C624AFNI-S2D43 CY8C6248FNI-S2D43 -CY_DEVICES_WITH_PACKAGE_68-QFN=CY8C624ALQI-D42 CY8C6245LQI-S3D72 CY8C6245LQI-S3D62 CY8C6245LQI-S3D42 CYB06445LQI-S3D42 CY8C6245LQI-S3D12 CY8C6245LQI-S3D02 -CY_DEVICES_WITH_PACKAGE_100-TQFP=CY8C6245AZI-S3D72 CY8C6245AZI-S3D62 CY8C6245AZI-S3D42 CY8C6245AZI-S3D12 CY8C6245AZI-S3D02 CY8C6245W-S3D72 -CY_DEVICES_WITH_PACKAGE_49-WLCSP=CY8C6245FNI-S3D71 CY8C6245FNI-S3D41 CY8C6245FNI-S3D11 +CY_DEVICES_WITH_PACKAGE_128-TQFP=CY8C624AAZI-S2D44 CY8C624AAZI-S2D14 CY8C6248AZI-S2D14 CY8C6248AZI-S2D44 CY8C614AAZI-S2F04 CY8C614AAZI-S2F14 CY8C614AAZI-S2F44 CY8C6148AZI-S2F44 CY8C624AAZI-D44 CY8C624AAZI-D14 CY8C6248AZI-D14 CY8C6248AZI-D44 +CY_DEVICES_WITH_PACKAGE_100-WLCSP=CY8C624AFNI-S2D43 CY8C6248FNI-S2D43 CY8C614AFNI-S2F03 CY8C614AFNI-S2F43 CY8C6148FNI-S2F43 CY8C624AFNI-D43 CY8C6248FNI-D43 +CY_DEVICES_WITH_PACKAGE_68-QFN=CY8C624ALQI-D42 CY8C6245LQI-S3D72 CY8C6245LQI-S3D62 CY8C6245LQI-S3D42 CYB06445LQI-S3D42 CY8C6245LQI-S3D12 CY8C6245LQI-S3D02 CY8C6145LQI-S3F72 CY8C6145LQI-S3F62 CY8C6145LQI-S3F42 CY8C6145LQI-S3F12 CY8C6145LQI-S3F02 +CY_DEVICES_WITH_PACKAGE_100-TQFP=CY8C6245AZI-S3D72 CY8C6245AZI-S3D62 CY8C6245AZI-S3D42 CY8C6245AZI-S3D12 CY8C6245AZI-S3D02 CY8C6145AZI-S3F72 CY8C6145AZI-S3F62 CY8C6145AZI-S3F42 CY8C6145AZI-S3F12 CY8C6145AZI-S3F02 +CY_DEVICES_WITH_PACKAGE_49-WLCSP=CY8C6245FNI-S3D71 CY8C6245FNI-S3D41 CY8C6245FNI-S3D11 CY8C6145FNI-S3F71 CY8C6145FNI-S3F41 CY8C6145FNI-S3F11 +CY_DEVICES_WITH_PACKAGE_KGD=CY8C6245WI-S3D72 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/version.dat b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/version.dat index 7e8b744354..4e0b7bf12f 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/version.dat +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/version.dat @@ -1 +1 @@ -1.2.0.136 +1.2.0.370 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/version.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/version.xml index bcf3a2501f..a0729c2a6c 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/version.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/version.xml @@ -1 +1 @@ -1.2.0.136 +1.2.0.370 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/version.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/version.xml index 245b239f06..7d09d8f59e 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/version.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/version.xml @@ -1 +1 @@ -1.5.2.3446 +1.6.0.4266 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/.gitignore b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/.gitignore deleted file mode 100644 index 23a0757e7c..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/.gitignore +++ /dev/null @@ -1 +0,0 @@ -packet diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/README.md b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/README.md deleted file mode 100644 index 8819df6bea..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/README.md +++ /dev/null @@ -1,74 +0,0 @@ -#### Version of Python required is 3.7+ - -This directory contains scripts for adding signatures . -These files are relevant to CY8CPROTO_064_SB target. - -**_NOTE_:** Before starting work with Cypress Secure Boot enabled target please read User Guide https://www.cypress.com/secureboot-sdk-user-guide - -## UPGRADE IMAGES - -Secure Boot enabled targets support image upgrades, if specified by policy. There are two types of upgrade images supported: -- signed, non encrypted -- signed, encrypted - -The upgrade images types are determined by the following policy setting (firmware sections): - -- **_"smif_id":_** should be set to 1 for CY8CPROTO_064_SB onboard SMIF, default is 0 - SMIF disabled -- **_"upgrade":_** true/false, - should be set to *true* if UPGRADE supported, *false* - if disabled -- **_"encrypt":_** true/false, - should be set to *true* if encrypted UPGRADE supported, *false* - if disabled -- **_"encrypt_key_id":_** 1, - should remain unchanged, means that Device Key will be used in ECDH/HKDF protocol - -Requirements: -- Policy with **_smif.json** from policy/ folder should be used. -For encrypted image: -- aes.key generated, as described in user guide -- dev_pub_key.pem must be placed in keys/ folder (this key is generated in provisioning procedure) -- secure_image_parameters.json file in the target directory must contain valid keys' paths - -Non encrypted UPGRADE image -**_Example policy for CY8CPROTO_064_SB:_** - - "smif_id": 1, - "upgrade": true, - "encrypt": false, - "encrypt_key_id": 1, - -Encrypted UPGRADE image: - -**_Example policy for CY8CPROTO_064_SB:_** - - "smif_id": 1, - "upgrade": true, - "encrypt": true, - "encrypt_key_id": 1, - -Modified policy file should be used for provisioning the device, as described in User Guide. - -Now mbed-os application or test can be built as described in section **TESTS**. Images for UPGRADE are generated at build time, according to policy. - -- Non enrypted UPGRADE image file name ends with **_upgrade.hex_** -- Enrypted UPGRADE image file name ends with **_enc_upgrade.hex_** - -Upgrade image can be programmed to target board using Daplink. Upgrade procedure is performed after first reset. - -**_Encrypt generic image:_** -The generic HEX file (for example one that is produced by mbed-os build system) can be converted into encrypted image by using encrypted_image_runner.py script located in sb-tools. Usage example: - - python encrypted_image_runner.py --sdk-path . --hex-file someApplication.hex --key-priv keys/MCUBOOT_CM0P_KEY_PRIV.pem --key-pub keys/dev_pub_key.pem --key-aes keys/aes.key --ver 0.1 --img-id 3 --rlb-count 0 --slot-size 0x50000 --pad 1 --img-offset 402653184 - -- **_--sdk-path_** - Path to Secure Boot tools folder -- **_--key-priv_** - ECC Private key used for image signing and for generating shared secret as per ECDH/HKDF. -- **_--key-pub_** - ECC Public key used for image signing and for generating shared secret as per ECDH/HKDF. Only device Key can be used in current implementation. It is generated by provisioning procedure. -- **_--key-aes_** - AES128 key and IV file raw image will be encrypted with. -- **_--img-id_** - Image ID of encrypted image. Must match one mentioned in policy for UPGRADE image. -- **_--slot-size_** - Slot_1 (UPGRADE) size. Must match one mentioned in policy for UPGRADE image. -- **_--ver_** - Version of image. Make sure it matches one defined in secure_image_parameters.json for a given HEX. -- **_--rlb-count_** - Rollback counter. Make sure it matches one defined in secure_image_parameters.json for a given HEX. -- **_--img-offset_** - Starting address offset for UPGRADE image - passed as integer, as represented in policy - -# TESTS - -1. Build and run tests for CY8CPROTO_064_SB target with command: - - Run commands: - mbed test --compile -m CY8CPROTO_064_SB -t GCC_ARM -n tests-mbed* -v diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/encrypted_image_runner.py b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/encrypted_image_runner.py deleted file mode 100644 index 2d50c8e478..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/encrypted_image_runner.py +++ /dev/null @@ -1,215 +0,0 @@ -# Copyright 2019 Cypress Semiconductor Corporation -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. - -import os -import sys -import click -import subprocess -import binascii -from pathlib import Path, PurePath - -from intelhex import IntelHex, hex2bin, bin2hex -from intelhex.compat import asbytes - -HEADER_SIZE = 0x400 -AES_HEADER="aes_header.txt" # near the script file - -def check_file_exist(file): - if not Path(file).exists(): - print("ERROR: File %s not found. Check script arguments."% file) - return False - else: - return True - -def get_final_hex_name(file): - """ - Determine if script is called from mbed-os build system - for Secure Boot target processing or directly - """ - for part in PurePath(file).parts: - if "_unsigned.hex" in part: - # suppose file came from mbed-os build execution - return file[:-13] + "_enc_upgrade.hex" - # suppose stand alone script execution - return file[:-4] + "_enc_upgrade.hex" - -def manage_output(process, input_f, output_f): - """ - Function takes care of subprocess - """ - stderr = process.communicate()[1] - rc = process.wait() - - if rc != 0: - print("ERROR: Encryption script ended with error!") - print("ERROR: " + stderr.decode("utf-8")) - raise Exception("imgtool finished execution with errors!") - - if check_file_exist(output_f): - os.remove(input_f) - -@click.command() -@click.option('--sdk-path', 'sdk_path', - default=Path("."), - type=click.STRING, - help='Path to Secure Boot tools in case running script from outside') -@click.option('--hex-file', 'hex_file', - default=None, - type=click.STRING, - help='Hex file to process') -@click.option('--key-priv', 'key_priv', - default=None, - type=click.STRING, - help='Private key file to use for signing BOOT or UPGRADE image') -@click.option('--key-pub', 'key_pub', - default=None, - type=click.STRING, - help='Path to device public key - obtained from device on provisioning stage') -@click.option('--key-aes', 'key_aes', - default=None, - type=click.STRING, - help='Path to encryption key') -@click.option('--ver', 'version', - default=None, - type=click.STRING, - help='Version') -@click.option('--img-id', 'img_id', - default=None, - type=click.STRING, - help='Image ID - should correspond to values, used in policy file') -@click.option('--rlb-count', 'rlb_count', - default=None, - type=click.STRING, - help='Rollback counter value') -@click.option('--slot-size', 'slot_size', - default=None, - type=click.STRING, - help='Size of slot available for BOOT or UPGRADE image') -@click.option('--pad', 'pad', - default=False, - is_flag=True, - help='Add padding to image - required for UPGRADE image') -@click.option('--img-offset', 'img_offset', - default=None, - type=click.STRING, - help='Offset of hex file for UPGRADE image') - -def main(sdk_path, - hex_file, - key_priv, - key_pub, - key_aes, - version, - img_id, - rlb_count, - slot_size, - pad, - img_offset): - """ - Function consequentially performs operations with provided hex file - and produces an encrypted and signed hex file for UPGRADE - """ - - check_file_exist(key_priv) - check_file_exist(key_pub) - check_file_exist(key_aes) - check_file_exist(hex_file) - - in_f = hex_file[:-4] + "_i.bin" - out_f = hex_file[:-4] + "_o.bin" - - hex_file_final = get_final_hex_name(hex_file) - print("Image UPGRADE:" + hex_file_final) - - # ih = IntelHex(hex_file) - # img_start_addr = ih.start_addr['EIP'] - - hex2bin(hex_file, in_f) #bin_file) - - # $PYTHON $IMGTOOL sign --key $KEY --header-size $HEADER_SIZE --pad-header --align 8 --version $VERSION --image-id $ID --rollback_counter $ROLLBACK_COUNTER --slot-size $SLOT_SIZE --overwrite-only $binFileName $signedFileName is_file_created $signedFileName - - # call imgtool for signature - process = subprocess.Popen([sys.executable, sdk_path + "/imgtool/imgtool.py", "sign", - "--key", key_priv, - "--header-size", str(hex(HEADER_SIZE)), - "--pad-header", - "--align", "8", - "--version", version, - "--image-id", img_id, - "--rollback_counter", rlb_count, - "--slot-size", slot_size, - "--overwrite-only", - in_f, - out_f], - stdout=subprocess.PIPE, stderr=subprocess.PIPE) - manage_output(process, in_f, out_f) - - # AES - # $PYTHON $(dirname "${IMGTOOL}")"/create_aesHeader.py" -k $KEY -p $KEY_DEV --key_to_encrypt "$KEY_AES" $AES_HEADER - # call aesHeader for crypto header generation - process = subprocess.Popen([sys.executable, sdk_path + "/imgtool/create_aesHeader.py", - "-k", key_priv, - "-p", key_pub, - "--key_to_encrypt", key_aes, - AES_HEADER], - stdout=subprocess.PIPE, stderr=subprocess.PIPE) - - # catch stderr outputs - stderr = process.communicate() - rc = process.wait() - check_file_exist(AES_HEADER) - - # aes_cipher.py script file should be in the same folder as imgtool.py - # $PYTHON $(dirname "${IMGTOOL}")"/aes_cipher.py" -k $KEY_AES $signedFileName $aes_encryptedFileName - # is_file_created $aes_encryptedFileName - # encrypt signed image - process = subprocess.Popen([sys.executable, sdk_path + "/imgtool/aes_cipher.py", - "-k", key_aes, - out_f, - in_f], - stdout=subprocess.PIPE, stderr=subprocess.PIPE) - manage_output(process, out_f, in_f) - - # second part - obtain signed image from encrypted file - with padding - for staging area - # $PYTHON $IMGTOOL sign --key $KEY --header-size $HEADER_SIZE --pad-header --align 8 --version $VERSION --image-id $ID --rollback_counter $ROLLBACK_COUNTER --slot-size $SLOT_SIZE --overwrite-only $PAD -a $AES_HEADER $aes_encryptedFileName $signedEncFileName - # is_file_created $signedEncFileName - - # call imgtool for signature - process = subprocess.Popen([sys.executable, sdk_path + "/imgtool/imgtool.py", "sign", - "--key", key_priv, - "--header-size", str(hex(HEADER_SIZE)), - "--pad-header", - "--align", "8", - "--version", version, - "--image-id", img_id, - "--rollback_counter", rlb_count, - "--slot-size", slot_size, - "--overwrite-only", - "--pad", - "-a", AES_HEADER, - in_f, - out_f], - #bin_sig_enc, - #bin_sig_enc_sig], - stdout=subprocess.PIPE, stderr=subprocess.PIPE) - manage_output(process, in_f, out_f) - - bin2hex(out_f, hex_file_final, int(img_offset)) - os.remove(out_f) - - os.remove(AES_HEADER) - -if __name__ == "__main__": - main() diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/aes_cipher.py b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/aes_cipher.py deleted file mode 100644 index 306c2691e5..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/aes_cipher.py +++ /dev/null @@ -1,121 +0,0 @@ - -# Copyright 2019 Cypress Semiconductor Corporation -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. - -import click - -from cryptography.hazmat.primitives.ciphers import Cipher, algorithms, modes -from cryptography.hazmat.primitives.ciphers.aead import AESGCM -from cryptography.hazmat.backends import default_backend -from cryptography.hazmat.primitives import padding - - -class AESCipher(object): - - def __init__(self, key, IV): - - self.backend = default_backend() - self.key = AESCipher.get_bytes(key) - self.iv = AESCipher.get_bytes(IV) - self.block_size = 128 - - @staticmethod - def get_bytes(inputdata): - if type(inputdata) is str: - return str.encode(inputdata,'utf-8') - elif type(inputdata) is bytes: - return inputdata - else: - raise Exception("Unknown input data type...") - - -class AESCipherCBC(AESCipher): - - def __init__(self, key, IV): - super().__init__(key, IV) - self.cipher = Cipher(algorithms.AES(self.key), modes.CBC(self.iv), backend=self.backend) - - def encrypt(self, raw): - encryptor = self.cipher.encryptor() - padder = padding.PKCS7(self.block_size).padder() - return encryptor.update(padder.update(raw) + padder.finalize()) + encryptor.finalize() - - def decrypt(self, enc): - decryptor = self.cipher.decryptor() - unpadder = padding.PKCS7(self.block_size).unpadder() - return unpadder.update(decryptor.update(enc) + decryptor.finalize()) + unpadder.finalize() - - -class AESCipherGCM(AESCipher): - - def __init__(self, key, IV, auth_data): - super().__init__(key, IV) - self.cipher = AESGCM(self.key) - self.auth_data = str.encode(auth_data,'utf-8') - - def encrypt(self, raw): - return self.cipher.encrypt(self.iv, raw, self.auth_data) - - def decrypt(self, enc): - return self.cipher.decrypt(self.iv, enc, self.auth_data) - -def read_key_from_file(keyfile): - - with open(keyfile) as f: - content = f.read().splitlines() - if len(content) < 2: - raise Exception("Not anough AES input data: in the file should be two lines: key, iv ...") - key = bytes.fromhex(content[0]) - iv = bytes.fromhex(content[1]) - - if 8*len(key) not in set([128, 192, 256]): - raise Exception("Invalid AES Key length: should be 128, 192 or 256 bits") - check_iv_length(iv) - - return key, iv - -def check_iv_length(iv): - if 8*len(iv) != 128: - raise Exception("Invalid AES IV length: should be 128 bits") - return True - -@click.command() -@click.option('-k', '--keyfile') -@click.option('-a', '--auth_data', default='default data') -@click.option('-m', '--mode', default='CBC') -@click.argument('inputfile') -@click.argument('outputfile') -def main(keyfile, auth_data, mode, inputfile, outputfile): - - key, iv = read_key_from_file(keyfile) - - if mode == 'CBC': - check_iv_length(iv) - aes = AESCipherCBC(key, iv) - elif mode == 'GCM': - aes = AESCipherGCM(key, iv, auth_data) - else: - raise Exception("Selected mode is not supported...") - - inFile = open(inputfile,"rb") - outFile = open(outputfile,"wb") - - outFile.write(aes.encrypt(inFile.read())) - - inFile.close() - outFile.close() - -if __name__ == "__main__": - main() diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/create_aesHeader.py b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/create_aesHeader.py deleted file mode 100644 index bc8dfec034..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/create_aesHeader.py +++ /dev/null @@ -1,61 +0,0 @@ -# Copyright 2019 Cypress Semiconductor Corporation -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. - -import codecs -import click - -from aes_cipher import * -from ecc_kdf import ECDH_KDF - -def get_header_info(kdf_object, key_to_encrypt_file): - - aes = AESCipherCBC(kdf_object.aes_key, kdf_object.iv) - #print (kdf_object.aes_key.hex()) - - key_to_enc, iv_to_enc = read_key_from_file(key_to_encrypt_file) - key_encrypted = aes.encrypt(key_to_enc + iv_to_enc) - - if kdf_object.salt is None or kdf_object.info is None: - raise Exception('salt and info should be presented...') - if len(kdf_object.salt) != 16 or len(kdf_object.info) != 16: - raise Exception('salt and info fields length should be 16 bytes...') - - return key_encrypted + kdf_object.salt + kdf_object.info - - -@click.command() -@click.option('-a', '--algorithm', default='ECC') #assymetric algorithm for KDF -@click.option('-k', '--private_key') #host side key pair file -@click.option('-p', '--public_key') #device side public key -@click.option('-l', '--key_length', default=16) #derived key (AES) length -@click.option('-s', '--salt', default=None) #salt for KDF -@click.option('-i', '--info', default=b'_handshake_data_') #info data for KDF -@click.option('--key_to_encrypt') #AES key file name (key and iv are used for image encryption), should be AES encrypted, using derived key -@click.argument('outputfile') #AES_header info file name - -def main(algorithm, private_key, public_key, key_length, salt, info, key_to_encrypt, outputfile): - kdf_object = None - if(algorithm == 'ECC'): - kdf_object = ECDH_KDF(private_key, public_key, key_length, salt, info) - else: - raise Exception('Algorithm not supported...') - - aes_header = get_header_info(kdf_object, key_to_encrypt) - - with open(outputfile, 'wb') as header_out: - header_out.write(aes_header) - -if __name__ == "__main__": - main() diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/ecc_kdf.py b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/ecc_kdf.py deleted file mode 100644 index 4ffb561d16..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/ecc_kdf.py +++ /dev/null @@ -1,83 +0,0 @@ - -# Copyright 2019 Cypress Semiconductor Corporation -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. - -from cryptography.hazmat.backends import default_backend -from cryptography.hazmat.primitives import hashes -from cryptography.hazmat.primitives.asymmetric import ec -from cryptography.hazmat.primitives.kdf.hkdf import HKDF - -from cryptography.hazmat.primitives import serialization - -import codecs -import os - -class ECDH_KDF(object): - - def __init__(self, private_key, public_key, key_length, salt, info): - - salt_length = 16 - - self.backend = default_backend() - self.host_key_pair = serialization.load_pem_private_key(self.read_key_bytes(private_key), password=None, backend=self.backend) - - #Deserialize public key: extract from private or directly from pem file - try: - self.device_public_key = serialization.load_pem_private_key(self.read_key_bytes(public_key), password=None, backend=self.backend).public_key() - except: - self.device_public_key = serialization.load_pem_public_key(self.read_key_bytes(public_key), backend=self.backend) - - self.key_length = key_length - self.iv_length = 16 - - if salt is not None: - self.salt = ECDH_KDF.get_bytes(salt) - else: - self.salt = os.urandom(salt_length) - self.info = ECDH_KDF.get_bytes(info) - - self.derived_key = self.derive_key() - self.aes_key = self.derived_key[:self.key_length] - self.iv = self.derived_key[self.key_length:] - - @staticmethod - def get_bytes(inputdata): - if type(inputdata) is str: - return str.encode(inputdata,'utf-8') - elif type(inputdata) is bytes: - return inputdata - else: - raise Exception("Unknown input data type...") - - def read_key_bytes(self, key_file): - with open(key_file, "rb") as key_file: - return key_file.read() - - def derive_key(self): - - shared_key = self.host_key_pair.exchange(ec.ECDH(), self.device_public_key) - derived_key = HKDF(algorithm=hashes.SHA256(), # Perform key derivation. - length=self.key_length + self.iv_length, - salt=self.salt, - info=self.info, - backend=self.backend).derive(shared_key) - - return derived_key - -def main(): - pass - -if __name__ == "__main__": - main() diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/imgtool.py b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/imgtool.py deleted file mode 100644 index ee92438bdd..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/imgtool.py +++ /dev/null @@ -1,198 +0,0 @@ -#! /usr/bin/env python3 -# -# Copyright 2017 Linaro Limited -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. - -import click -import getpass -from imgtool import keys -from imgtool import image -from imgtool.version import decode_version - - -def gen_rsa2048(keyfile, passwd): - keys.RSA2048.generate().export_private(path=keyfile, passwd=passwd) - - -def gen_ecdsa_p256(keyfile, passwd): - keys.ECDSA256P1.generate().export_private(keyfile, passwd=passwd) - - -def gen_ecdsa_p224(keyfile, passwd): - print("TODO: p-224 not yet implemented") - - -valid_langs = ['c', 'rust'] -keygens = { - 'rsa-2048': gen_rsa2048, - 'ecdsa-p256': gen_ecdsa_p256, - 'ecdsa-p224': gen_ecdsa_p224, -} - - -def load_key(keyfile): - # TODO: better handling of invalid pass-phrase - key = keys.load(keyfile) - if key is not None: - return key - passwd = getpass.getpass("Enter key passphrase: ").encode('utf-8') - return keys.load(keyfile, passwd) - - -def get_password(): - while True: - passwd = getpass.getpass("Enter key passphrase: ") - passwd2 = getpass.getpass("Reenter passphrase: ") - if passwd == passwd2: - break - print("Passwords do not match, try again") - - # Password must be bytes, always use UTF-8 for consistent - # encoding. - return passwd.encode('utf-8') - - -@click.option('-p', '--password', is_flag=True, - help='Prompt for password to protect key') -@click.option('-t', '--type', metavar='type', required=True, - type=click.Choice(keygens.keys())) -@click.option('-k', '--key', metavar='filename', required=True) -@click.command(help='Generate pub/private keypair') -def keygen(type, key, password): - password = get_password() if password else None - keygens[type](key, password) - - -@click.option('-l', '--lang', metavar='lang', default=valid_langs[0], - type=click.Choice(valid_langs)) -@click.option('-k', '--key', metavar='filename', required=True) -@click.command(help='Get public key from keypair') -def getpub(key, lang): - key = load_key(key) - if key is None: - print("Invalid passphrase") - elif lang == 'c': - key.emit_c() - elif lang == 'rust': - key.emit_rust() - else: - raise ValueError("BUG: should never get here!") - - -def validate_version(ctx, param, value): - try: - decode_version(value) - return value - except ValueError as e: - raise click.BadParameter("{}".format(e)) - - -class BasedIntParamType(click.ParamType): - name = 'integer' - - def convert(self, value, param, ctx): - try: - if value[:2].lower() == '0x': - return int(value[2:], 16) - elif value[:1] == '0': - return int(value, 8) - return int(value, 10) - except ValueError: - self.fail('%s is not a valid integer' % value, param, ctx) - - -def load_data_from_file(filename): - FileObj = open(filename, 'rb') - data = FileObj.read() - FileObj.close() - return data - - -@click.argument('outfile') -@click.argument('infile') -@click.option('--overwrite-only', default=False, is_flag=True, - help='Use overwrite-only instead of swap upgrades') -@click.option('-M', '--max-sectors', type=int, - help='When padding allow for this amount of sectors (defaults to 128)') -@click.option('--pad', default=False, is_flag=True, - help='Pad image to --slot-size bytes, adding trailer magic') -@click.option('-S', '--slot-size', type=BasedIntParamType(), required=True, - help='Size of the slot where the image will be written') -@click.option('--pad-header', default=False, is_flag=True, - help='Add --header-size zeroed bytes at the beginning of the image') -@click.option('-H', '--header-size', type=BasedIntParamType(), required=True) -@click.option('-v', '--version', callback=validate_version, required=True) -@click.option('--align', type=click.Choice(['1', '2', '4', '8']), - required=True) -@click.option('-k', '--key', metavar='filename') -@click.option('-a', '--aes-header-file', default=None, metavar='filename') -@click.option('--image-id', required=True, type=int, help='Image ID') -@click.option('--rollback_counter', default=None, type=int, help='Rollback monotonic counter value') -@click.command(help='Create a signed or unsigned image') -def sign(key, align, version, header_size, pad_header, slot_size, pad, - max_sectors, overwrite_only, aes_header_file, image_id, rollback_counter, infile, outfile): - - if aes_header_file is not None : - aes_header = load_data_from_file(aes_header_file) - else: - aes_header = None - - img = image.Image.load(infile, version=decode_version(version), - header_size=header_size, pad_header=pad_header, - pad=pad, align=int(align), slot_size=slot_size, - max_sectors=max_sectors, - overwrite_only=overwrite_only, aes_header_data=aes_header, - image_id=image_id, rollback_counter=rollback_counter) - key = load_key(key) if key else None - img.sign(key) - - if pad: - img.pad_to(slot_size) - - img.save(outfile) - - -class AliasesGroup(click.Group): - - _aliases = { - "create": "sign", - } - - def list_commands(self, ctx): - cmds = [k for k in self.commands] - aliases = [k for k in self._aliases] - return sorted(cmds + aliases) - - def get_command(self, ctx, cmd_name): - rv = click.Group.get_command(self, ctx, cmd_name) - if rv is not None: - return rv - if cmd_name in self._aliases: - return click.Group.get_command(self, ctx, self._aliases[cmd_name]) - return None - - -@click.command(cls=AliasesGroup, - context_settings=dict(help_option_names=['-h', '--help'])) -def imgtool(): - pass - - -imgtool.add_command(keygen) -imgtool.add_command(getpub) -imgtool.add_command(sign) - - -if __name__ == '__main__': - imgtool() diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/imgtool/__init__.py b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/imgtool/__init__.py deleted file mode 100644 index 107921f94e..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/imgtool/__init__.py +++ /dev/null @@ -1,13 +0,0 @@ -# Copyright 2017 Linaro Limited -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/imgtool/image.py b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/imgtool/image.py deleted file mode 100644 index 34cf0c02a5..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/imgtool/image.py +++ /dev/null @@ -1,269 +0,0 @@ -# Copyright 2018 Nordic Semiconductor ASA -# Copyright 2017 Linaro Limited -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. - -""" -Image signing and management. -""" - -from . import version as versmod -from intelhex import IntelHex -import hashlib -import struct -import os.path -import os - -IMAGE_MAGIC = 0x96f3b83d -IMAGE_HEADER_SIZE = 32 -BIN_EXT = "bin" -INTEL_HEX_EXT = "hex" -DEFAULT_MAX_SECTORS = 128 - -# Image header flags. -IMAGE_F = { - 'PIC': 0x0000001, - 'NON_BOOTABLE': 0x0000010, } - -TLV_VALUES = { - 'KEYHASH': 0x01, - 'SHA256': 0x10, - 'RSA2048': 0x20, - 'ECDSA224': 0x21, - 'ECDSA256': 0x22, } - -TLV_INFO_SIZE = 4 -TLV_INFO_MAGIC = 0x6907 - -boot_magic = bytes([ - 0x77, 0xc2, 0x95, 0xf3, - 0x60, 0xd2, 0xef, 0x7f, - 0x35, 0x52, 0x50, 0x0f, - 0x2c, 0xb6, 0x79, 0x80, ]) - -class TLV(): - def __init__(self): - self.buf = bytearray() - - def add(self, kind, payload): - """Add a TLV record. Kind should be a string found in TLV_VALUES above.""" - buf = struct.pack(' 0: - if obj.base_addr: - # Adjust base_addr for new header - obj.base_addr -= obj.header_size - obj.payload = (b'\000' * obj.header_size) + obj.payload - - obj.check() - return obj - - def __init__(self, version=None, header_size=IMAGE_HEADER_SIZE, pad=0, - align=1, slot_size=0, max_sectors=DEFAULT_MAX_SECTORS, - overwrite_only=False, aes_header_data=None, image_id=1, rollback_counter=0): - self.version = version or versmod.decode_version("0") - self.header_size = header_size or IMAGE_HEADER_SIZE - self.pad = pad - self.align = align - self.slot_size = slot_size - self.max_sectors = max_sectors - self.overwrite_only = overwrite_only - self.aes_header_data = aes_header_data - self.image_id = image_id - self.rollback_counter = rollback_counter - - def __repr__(self): - return "".format( - self.version, - self.header_size, - self.base_addr if self.base_addr is not None else "N/A", - self.align, - self.slot_size, - self.max_sectors, - self.overwrite_only, - self.__class__.__name__, - len(self.payload)) - - def check(self): - """Perform some sanity checking of the image.""" - # If there is a header requested, make sure that the image - # starts with all zeros. - if self.header_size > 0: - if any(v != 0 for v in self.payload[0:self.header_size]): - raise Exception("Padding requested, but image does not start with zeros") - if self.slot_size > 0: - tsize = self._trailer_size(self.align, self.max_sectors, - self.overwrite_only) - padding = self.slot_size - (len(self.payload) + tsize) - if padding < 0: - msg = "Image size (0x{:x}) + trailer (0x{:x}) exceeds requested size 0x{:x}".format( - len(self.payload), tsize, self.slot_size) - raise Exception(msg) - - def sign(self, key, add_padding = True): - - DECRYPT_BLOCK_SIZE = 256 #future AES decription buffer size, is used for align FW image and trailer size - - if add_padding: - pl_size = len(self.payload) - pad_len = (DECRYPT_BLOCK_SIZE - pl_size % DECRYPT_BLOCK_SIZE) % DECRYPT_BLOCK_SIZE - #self.payload += bytearray(os.urandom(pad_len)) - self.payload += bytearray(pad_len) - - self.add_header(key) - if (self.aes_header_data is not None): - self.add_AES_header() - - tlv = TLV() - - # Note that ecdsa wants to do the hashing itself, which means - # we get to hash it twice. - sha = hashlib.sha256() - sha.update(self.payload) - digest = sha.digest() - - tlv.add('SHA256', digest) - - if key is not None: - pub = key.get_public_bytes() - sha = hashlib.sha256() - sha.update(pub) - pubbytes = sha.digest() - tlv.add('KEYHASH', pubbytes) - - sig = key.sign(bytes(self.payload)) - tlv.add(key.sig_tlv(), sig) - - trailer = tlv.get() - self.payload += trailer - - if add_padding: - trailer_size = len(trailer) - tr_rem_len = (DECRYPT_BLOCK_SIZE - trailer_size % DECRYPT_BLOCK_SIZE ) % DECRYPT_BLOCK_SIZE - #self.payload += bytearray(os.urandom(tr_rem_len)) - self.payload += bytearray(tr_rem_len) - - def add_header(self, key): - """Install the image header. - - The key is needed to know the type of signature, and - approximate the size of the signature.""" - - flags = 0 - - fmt = ('<' + - # type ImageHdr struct { - 'I' + # Magic uint32 - 'I' + # LoadAddr uint32 - 'H' + # HdrSz uint16 - 'B' + # Image ID uint8 - 'B' + # Rollback monotonic counter value uint8 - 'I' + # ImgSz uint32 - 'I' + # Flags uint32 - 'BBHI' + # Vers ImageVersion - 'I' # Pad2 uint32 - ) # } - assert struct.calcsize(fmt) == IMAGE_HEADER_SIZE - header = struct.pack(fmt, - IMAGE_MAGIC, - 0, # LoadAddr - self.header_size, - self.image_id, - self.rollback_counter, - len(self.payload) - self.header_size, # ImageSz - flags, # Flags - self.version.major, - self.version.minor or 0, - self.version.revision or 0, - self.version.build or 0, - 0) # Pad2 - self.payload = bytearray(self.payload) - self.payload[:len(header)] = header - - def add_AES_header(self): - """Install AES header just after main image header - - The header contains: - AES Key, IV (encrypted with AES CBC) - salt - random sequence for ECDH KDF - info - information for ECDH KDF - """ - - aes_header_bytes = self.aes_header_data #str.encode(self.aes_header_data,'utf-8') - headerAES = struct.pack( "@%ds" % (len(aes_header_bytes)), aes_header_bytes ) - self.payload[IMAGE_HEADER_SIZE:IMAGE_HEADER_SIZE + len(headerAES)] = headerAES - - - def _trailer_size(self, write_size, max_sectors, overwrite_only): - # NOTE: should already be checked by the argument parser - if overwrite_only: - return 8 * 2 + 16 - else: - if write_size not in set([1, 2, 4, 8]): - raise Exception("Invalid alignment: {}".format(write_size)) - m = DEFAULT_MAX_SECTORS if max_sectors is None else max_sectors - return m * 3 * write_size + 8 * 2 + 16 - - def pad_to(self, size): - """Pad the image to the given size, with the given flash alignment.""" - tsize = self._trailer_size(self.align, self.max_sectors, - self.overwrite_only) - padding = size - (len(self.payload) + tsize) - pbytes = b'\xff' * padding - pbytes += b'\xff' * (tsize - len(boot_magic)) - pbytes += boot_magic - self.payload += pbytes - - -class HexImage(Image): - - def load(self, path): - ih = IntelHex(path) - return ih.tobinarray(), ih.minaddr() - - def save(self, path): - h = IntelHex() - h.frombytes(bytes = self.payload, offset = self.base_addr) - h.tofile(path, 'hex') - -class BinImage(Image): - - def load(self, path): - with open(path, 'rb') as f: - return f.read(), None - - def save(self, path): - with open(path, 'wb') as f: - f.write(self.payload) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/imgtool/keys/__init__.py b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/imgtool/keys/__init__.py deleted file mode 100644 index da5b083193..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/imgtool/keys/__init__.py +++ /dev/null @@ -1,76 +0,0 @@ -# Copyright 2017 Linaro Limited -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. - -""" -Cryptographic key management for imgtool. -""" - -from cryptography.hazmat.backends import default_backend -from cryptography.hazmat.primitives import serialization -from cryptography.hazmat.primitives.asymmetric.rsa import RSAPrivateKey, RSAPublicKey -from cryptography.hazmat.primitives.asymmetric.ec import EllipticCurvePrivateKey, EllipticCurvePublicKey - -from .rsa import RSA2048, RSA2048Public, RSAUsageError -from .ecdsa import ECDSA256P1, ECDSA256P1Public, ECDSAUsageError - -class PasswordRequired(Exception): - """Raised to indicate that the key is password protected, but a - password was not specified.""" - pass - -def load(path, passwd=None): - """Try loading a key from the given path. Returns None if the password wasn't specified.""" - with open(path, 'rb') as f: - raw_pem = f.read() - try: - pk = serialization.load_pem_private_key( - raw_pem, - password=passwd, - backend=default_backend()) - # Unfortunately, the crypto library raises unhelpful exceptions, - # so we have to look at the text. - except TypeError as e: - msg = str(e) - if "private key is encrypted" in msg: - return None - raise e - except ValueError: - # This seems to happen if the key is a public key, let's try - # loading it as a public key. - pk = serialization.load_pem_public_key( - raw_pem, - backend=default_backend()) - - if isinstance(pk, RSAPrivateKey): - if pk.key_size != 2048: - raise Exception("Unsupported RSA key size: " + pk.key_size) - return RSA2048(pk) - elif isinstance(pk, RSAPublicKey): - if pk.key_size != 2048: - raise Exception("Unsupported RSA key size: " + pk.key_size) - return RSA2048Public(pk) - elif isinstance(pk, EllipticCurvePrivateKey): - if pk.curve.name != 'secp256r1': - raise Exception("Unsupported EC curve: " + pk.curve.name) - if pk.key_size != 256: - raise Exception("Unsupported EC size: " + pk.key_size) - return ECDSA256P1(pk) - elif isinstance(pk, EllipticCurvePublicKey): - if pk.curve.name != 'secp256r1': - raise Exception("Unsupported EC curve: " + pk.curve.name) - if pk.key_size != 256: - raise Exception("Unsupported EC size: " + pk.key_size) - return ECDSA256P1Public(pk) - else: - raise Exception("Unknown key type: " + str(type(pk))) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/imgtool/keys/ecdsa.py b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/imgtool/keys/ecdsa.py deleted file mode 100644 index 7ac66bbf02..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/imgtool/keys/ecdsa.py +++ /dev/null @@ -1,117 +0,0 @@ -# Copyright 2019 Cypress Semiconductor Corporation -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. - -""" -ECDSA key management -""" - -from cryptography.hazmat.backends import default_backend -from cryptography.hazmat.primitives import serialization -from cryptography.hazmat.primitives.asymmetric import ec -from cryptography.hazmat.primitives.hashes import SHA256 - -from .general import KeyClass - -class ECDSAUsageError(Exception): - pass - -class ECDSA256P1Public(KeyClass): - def __init__(self, key): - self.key = key - - def shortname(self): - return "ecdsa" - - def _unsupported(self, name): - raise ECDSAUsageError("Operation {} requires private key".format(name)) - - def _get_public(self): - return self.key - - def get_public_bytes(self): - # The key is embedded into MBUboot in "SubjectPublicKeyInfo" format - return self._get_public().public_bytes( - encoding=serialization.Encoding.DER, - format=serialization.PublicFormat.SubjectPublicKeyInfo) - - def export_private(self, path, passwd=None): - self._unsupported('export_private') - - def export_public(self, path): - """Write the public key to the given file.""" - pem = self._get_public().public_bytes( - encoding=serialization.Encoding.PEM, - format=serialization.PublicFormat.SubjectPublicKeyInfo) - with open(path, 'wb') as f: - f.write(pem) - - def sig_type(self): - return "ECDSA256_SHA256" - - def sig_tlv(self): - return "ECDSA256" - - def sig_len(self): - # The DER encoding depends on the high bit, and can be - # anywhere from 70 to 72 bytes. Because we have to fill in - # the length field before computing the signature, however, - # we'll give the largest, and the sig checking code will allow - # for it to be up to two bytes larger than the actual - # signature. - return 72 - -class ECDSA256P1(ECDSA256P1Public): - """ - Wrapper around an ECDSA private key. - """ - - def __init__(self, key): - """key should be an instance of EllipticCurvePrivateKey""" - self.key = key - - @staticmethod - def generate(): - pk = ec.generate_private_key( - ec.SECP256R1(), - backend=default_backend()) - return ECDSA256P1(pk) - - def _get_public(self): - return self.key.public_key() - - def export_private(self, path, passwd=None): - """Write the private key to the given file, protecting it with the optional password.""" - if passwd is None: - enc = serialization.NoEncryption() - else: - enc = serialization.BestAvailableEncryption(passwd) - pem = self.key.private_bytes( - encoding=serialization.Encoding.PEM, - format=serialization.PrivateFormat.PKCS8, - encryption_algorithm=enc) - with open(path, 'wb') as f: - f.write(pem) - - def raw_sign(self, payload): - """Return the actual signature""" - return self.key.sign( - data=payload, - signature_algorithm=ec.ECDSA(SHA256())) - - def sign(self, payload): - # To make fixed length, pad with one or two zeros. - sig = self.raw_sign(payload) - sig += b'\000' * (self.sig_len() - len(sig)) - return sig diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/imgtool/keys/ecdsa_test.py b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/imgtool/keys/ecdsa_test.py deleted file mode 100644 index 877f33a1b1..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/imgtool/keys/ecdsa_test.py +++ /dev/null @@ -1,114 +0,0 @@ -# Copyright 2019 Cypress Semiconductor Corporation -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. - -""" -Tests for ECDSA keys -""" - -import io -import os.path -import sys -import tempfile -import unittest - -from cryptography.exceptions import InvalidSignature -from cryptography.hazmat.primitives.asymmetric import ec -from cryptography.hazmat.primitives.hashes import SHA256 - -sys.path.insert(0, os.path.abspath(os.path.join(os.path.dirname(__file__), '../..'))) - -from imgtool.keys import load, ECDSA256P1, ECDSAUsageError - -class EcKeyGeneration(unittest.TestCase): - - def setUp(self): - self.test_dir = tempfile.TemporaryDirectory() - - def tname(self, base): - return os.path.join(self.test_dir.name, base) - - def tearDown(self): - self.test_dir.cleanup() - - def test_keygen(self): - name1 = self.tname("keygen.pem") - k = ECDSA256P1.generate() - k.export_private(name1, b'secret') - - self.assertIsNone(load(name1)) - - k2 = load(name1, b'secret') - - pubname = self.tname('keygen-pub.pem') - k2.export_public(pubname) - pk2 = load(pubname) - - # We should be able to export the public key from the loaded - # public key, but not the private key. - pk2.export_public(self.tname('keygen-pub2.pem')) - self.assertRaises(ECDSAUsageError, - pk2.export_private, self.tname('keygen-priv2.pem')) - - def test_emit(self): - """Basic sanity check on the code emitters.""" - k = ECDSA256P1.generate() - - ccode = io.StringIO() - k.emit_c(ccode) - self.assertIn("ecdsa_pub_key", ccode.getvalue()) - self.assertIn("ecdsa_pub_key_len", ccode.getvalue()) - - rustcode = io.StringIO() - k.emit_rust(rustcode) - self.assertIn("ECDSA_PUB_KEY", rustcode.getvalue()) - - def test_emit_pub(self): - """Basic sanity check on the code emitters.""" - pubname = self.tname("public.pem") - k = ECDSA256P1.generate() - k.export_public(pubname) - - k2 = load(pubname) - - ccode = io.StringIO() - k2.emit_c(ccode) - self.assertIn("ecdsa_pub_key", ccode.getvalue()) - self.assertIn("ecdsa_pub_key_len", ccode.getvalue()) - - rustcode = io.StringIO() - k2.emit_rust(rustcode) - self.assertIn("ECDSA_PUB_KEY", rustcode.getvalue()) - - def test_sig(self): - k = ECDSA256P1.generate() - buf = b'This is the message' - sig = k.raw_sign(buf) - - # The code doesn't have any verification, so verify this - # manually. - k.key.public_key().verify( - signature=sig, - data=buf, - signature_algorithm=ec.ECDSA(SHA256())) - - # Modify the message to make sure the signature fails. - self.assertRaises(InvalidSignature, - k.key.public_key().verify, - signature=sig, - data=b'This is thE message', - signature_algorithm=ec.ECDSA(SHA256())) - -if __name__ == '__main__': - unittest.main() diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/imgtool/keys/general.py b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/imgtool/keys/general.py deleted file mode 100644 index aca3fddfc6..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/imgtool/keys/general.py +++ /dev/null @@ -1,50 +0,0 @@ -# Copyright 2019 Cypress Semiconductor Corporation -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. - -"""General key class.""" - -import sys - -AUTOGEN_MESSAGE = "/* Autogenerated by imgtool.py, do not edit. */" - -class KeyClass(object): - def _public_emit(self, header, trailer, indent, file=sys.stdout, len_format=None): - print(AUTOGEN_MESSAGE, file=file) - print(header, end='', file=file) - encoded = self.get_public_bytes() - for count, b in enumerate(encoded): - if count % 8 == 0: - print("\n" + indent, end='', file=file) - else: - print(" ", end='', file=file) - print("0x{:02x},".format(b), end='', file=file) - print("\n" + trailer, file=file) - if len_format is not None: - print(len_format.format(len(encoded)), file=file) - - def emit_c(self, file=sys.stdout): - self._public_emit( - header="const unsigned char {}_pub_key[] = {{".format(self.shortname()), - trailer="};", - indent=" ", - len_format="const unsigned int {}_pub_key_len = {{}};".format(self.shortname()), - file=file) - - def emit_rust(self, file=sys.stdout): - self._public_emit( - header="static {}_PUB_KEY: &'static [u8] = &[".format(self.shortname().upper()), - trailer="];", - indent=" ", - file=file) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/imgtool/keys/rsa.py b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/imgtool/keys/rsa.py deleted file mode 100644 index eb1d0ebc4f..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/imgtool/keys/rsa.py +++ /dev/null @@ -1,110 +0,0 @@ -# Copyright 2019 Cypress Semiconductor Corporation -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. - -""" -RSA Key management -""" - -from cryptography.hazmat.backends import default_backend -from cryptography.hazmat.primitives import serialization -from cryptography.hazmat.primitives.asymmetric import rsa -from cryptography.hazmat.primitives.asymmetric.padding import PSS, MGF1 -from cryptography.hazmat.primitives.hashes import SHA256 - -from .general import KeyClass - -class RSAUsageError(Exception): - pass - -class RSA2048Public(KeyClass): - """The public key can only do a few operations""" - def __init__(self, key): - self.key = key - - def shortname(self): - return "rsa" - - def _unsupported(self, name): - raise RSAUsageError("Operation {} requires private key".format(name)) - - def _get_public(self): - return self.key - - def get_public_bytes(self): - # The key embedded into MCUboot is in PKCS1 format. - return self._get_public().public_bytes( - encoding=serialization.Encoding.DER, - format=serialization.PublicFormat.PKCS1) - - def export_private(self, path, passwd=None): - self._unsupported('export_private') - - def export_public(self, path): - """Write the public key to the given file.""" - pem = self._get_public().public_bytes( - encoding=serialization.Encoding.PEM, - format=serialization.PublicFormat.SubjectPublicKeyInfo) - with open(path, 'wb') as f: - f.write(pem) - - def sig_type(self): - return "PKCS1_PSS_RSA2048_SHA256" - - def sig_tlv(self): - return "RSA2048" - - def sig_len(self): - return 256 - -class RSA2048(RSA2048Public): - """ - Wrapper around an 2048-bit RSA key, with imgtool support. - """ - - def __init__(self, key): - """The key should be a private key from cryptography""" - self.key = key - - @staticmethod - def generate(): - pk = rsa.generate_private_key( - public_exponent=65537, - key_size=2048, - backend=default_backend()) - return RSA2048(pk) - - def _get_public(self): - return self.key.public_key() - - def export_private(self, path, passwd=None): - """Write the private key to the given file, protecting it with the optional password.""" - if passwd is None: - enc = serialization.NoEncryption() - else: - enc = serialization.BestAvailableEncryption(passwd) - pem = self.key.private_bytes( - encoding=serialization.Encoding.PEM, - format=serialization.PrivateFormat.PKCS8, - encryption_algorithm=enc) - with open(path, 'wb') as f: - f.write(pem) - - def sign(self, payload): - # The verification code only allows the salt length to be the - # same as the hash length, 32. - return self.key.sign( - data=payload, - padding=PSS(mgf=MGF1(SHA256()), salt_length=32), - algorithm=SHA256()) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/imgtool/keys/rsa_test.py b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/imgtool/keys/rsa_test.py deleted file mode 100644 index e9bdb86375..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/imgtool/keys/rsa_test.py +++ /dev/null @@ -1,117 +0,0 @@ -# Copyright 2019 Cypress Semiconductor Corporation -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. - -""" -Tests for RSA keys -""" - -import io -import os -import sys -import tempfile -import unittest - -from cryptography.exceptions import InvalidSignature -from cryptography.hazmat.primitives.asymmetric.padding import PSS, MGF1 -from cryptography.hazmat.primitives.hashes import SHA256 - -# Setup sys path so 'imgtool' is in it. -sys.path.insert(0, os.path.abspath(os.path.join(os.path.dirname(__file__), '../..'))) - -from imgtool.keys import load, RSA2048, RSAUsageError - -class KeyGeneration(unittest.TestCase): - - def setUp(self): - self.test_dir = tempfile.TemporaryDirectory() - - def tname(self, base): - return os.path.join(self.test_dir.name, base) - - def tearDown(self): - self.test_dir.cleanup() - - def test_keygen(self): - name1 = self.tname("keygen.pem") - k = RSA2048.generate() - k.export_private(name1, b'secret') - - # Try loading the key without a password. - self.assertIsNone(load(name1)) - - k2 = load(name1, b'secret') - - pubname = self.tname('keygen-pub.pem') - k2.export_public(pubname) - pk2 = load(pubname) - - # We should be able to export the public key from the loaded - # public key, but not the private key. - pk2.export_public(self.tname('keygen-pub2.pem')) - self.assertRaises(RSAUsageError, pk2.export_private, self.tname('keygen-priv2.pem')) - - def test_emit(self): - """Basic sanity check on the code emitters.""" - k = RSA2048.generate() - - ccode = io.StringIO() - k.emit_c(ccode) - self.assertIn("rsa_pub_key", ccode.getvalue()) - self.assertIn("rsa_pub_key_len", ccode.getvalue()) - - rustcode = io.StringIO() - k.emit_rust(rustcode) - self.assertIn("RSA_PUB_KEY", rustcode.getvalue()) - - def test_emit_pub(self): - """Basic sanity check on the code emitters, from public key.""" - pubname = self.tname("public.pem") - k = RSA2048.generate() - k.export_public(pubname) - - k2 = load(pubname) - - ccode = io.StringIO() - k2.emit_c(ccode) - self.assertIn("rsa_pub_key", ccode.getvalue()) - self.assertIn("rsa_pub_key_len", ccode.getvalue()) - - rustcode = io.StringIO() - k2.emit_rust(rustcode) - self.assertIn("RSA_PUB_KEY", rustcode.getvalue()) - - def test_sig(self): - k = RSA2048.generate() - buf = b'This is the message' - sig = k.sign(buf) - - # The code doesn't have any verification, so verify this - # manually. - k.key.public_key().verify( - signature=sig, - data=buf, - padding=PSS(mgf=MGF1(SHA256()), salt_length=32), - algorithm=SHA256()) - - # Modify the message to make sure the signature fails. - self.assertRaises(InvalidSignature, - k.key.public_key().verify, - signature=sig, - data=b'This is thE message', - padding=PSS(mgf=MGF1(SHA256()), salt_length=32), - algorithm=SHA256()) - -if __name__ == '__main__': - unittest.main() diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/imgtool/version.py b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/imgtool/version.py deleted file mode 100644 index 8910e0b1a4..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/imgtool/imgtool/version.py +++ /dev/null @@ -1,53 +0,0 @@ -# Copyright 2017 Linaro Limited -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. - -""" -Semi Semantic Versioning - -Implements a subset of semantic versioning that is supportable by the image -header. -""" - -from collections import namedtuple -import re - -SemiSemVersion = namedtuple('SemiSemVersion', ['major', 'minor', 'revision', - 'build']) - -version_re = re.compile( - r"""^([1-9]\d*|0)(\.([1-9]\d*|0)(\.([1-9]\d*|0)(\+([1-9]\d*|0))?)?)?$""") - - -def decode_version(text): - """Decode the version string, which should be of the form maj.min.rev+build - """ - m = version_re.match(text) - if m: - result = SemiSemVersion( - int(m.group(1)) if m.group(1) else 0, - int(m.group(3)) if m.group(3) else 0, - int(m.group(5)) if m.group(5) else 0, - int(m.group(7)) if m.group(7) else 0) - return result - else: - msg = "Invalid version number, should be maj.min.rev+build with later " - msg += "parts optional" - raise ValueError(msg) - - -if __name__ == '__main__': - print(decode_version("1.2")) - print(decode_version("1.0")) - print(decode_version("0.0.2+75")) - print(decode_version("0.0.0+00")) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/policy/example_cert.pem b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/policy/example_cert.pem deleted file mode 100644 index ebc4b43f9d..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/policy/example_cert.pem +++ /dev/null @@ -1,10 +0,0 @@ ------BEGIN CERTIFICATE----- -MIIBTzCB9qADAgECAhQCJF8kCV5oVGofjI+lrnVsCSI+cjAKBggqhkjOPQQDAjAg -MR4wHAYDVQQDDBVDeXByZXNzIFNlbWljb25kdWN0b3IwHhcNMTkwNzE1MTkzNzQ3 -WhcNMjAwNzE0MTkzNzQ3WjAeMRwwGgYDVQQDDBNFeGFtcGxlIGNlcnRpZmljYXRl -MFkwEwYHKoZIzj0CAQYIKoZIzj0DAQcDQgAEvfb7/jewTxpFVINcXdrZQJBArC5i -grN0BLc783FigrP2sEFQpfOmPUDkrt/E+0Rol2x+jsmP/CwXstNktz6w86MQMA4w -DAYDVR0TAQH/BAIwADAKBggqhkjOPQQDAgNIADBFAiEA3I3zaBbwMzSJ6xU9ngUM -Dyk4XstQF3tLzmvBRUkX8woCICk0YiVqk4tD2wvgUYkPztBKu6tVl/OqF2Ee+aQs -uwQc ------END CERTIFICATE----- diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/policy/policy_single_stage_CM4.json b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/policy/policy_single_stage_CM4.json deleted file mode 100644 index 3655085fe4..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/policy/policy_single_stage_CM4.json +++ /dev/null @@ -1,113 +0,0 @@ -{ - "debug" : - { - "m0p" : { - "permission" : "disabled", - "control" : "firmware", - "key" : 5 - }, - "m4" : { - "permission" : "allowed", - "control" : "firmware", - "key" : 5 - }, - "system" : { - "permission" : "enabled", - "control" : "firmware", - "key" : 5, - "syscall": true, - "mmio": true, - "flash": true, - "workflash": true, - "sflash": true, - "sram": true - }, - "rma" : { - "permission" : "allowed", - "destroy_fuses" : [ - { - "start" : 888, - "size" : 136 - }, - { - "start" : 648, - "size" : 104 - } - ], - "destroy_flash" : [ - { - "start" : 268435456, - "size" : 851968 - }, - { - "start" : 269483520, - "size" : 16 - } - ], - "key" : 5 - } - }, - "wounding" : - { - }, - "boot_upgrade" : - { - "title": "upgrade_policy", - "firmware": [ - { - "boot_auth": [ - 3 - ], - "id": 0, - "launch": 4, - "smif_id": 0, - "upgrade": false, - "upgrade_auth": [ - 3 - ], - "resources": [ - { - "type": "FLASH_PC1_SPM", - "address": 269287424, - "size": 65536 - }, - { - "type": "SRAM_SPM_PRIV", - "address": 134348800, - "size": 65536 - }, - { - "type": "SRAM_DAP", - "address": 134397952, - "size": 16384 - } - ] - }, - { - "boot_auth": [ - 8 - ], - "id": 4, - "monotonic": 0, - "smif_id": 0, - "upgrade": true, - "upgrade_auth": [ - 8 - ], - - "resources": [ - { - "type": "BOOT", - "address": 268435456, - "size": 327680 - }, - { - "type": "UPGRADE", - "address": 268763136, - "size": 327680 - } - ] - } - ] - } -} \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/policy/policy_single_stage_CM4_2m.json b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/policy/policy_single_stage_CM4_2m.json deleted file mode 100644 index b2ec1c87d5..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/policy/policy_single_stage_CM4_2m.json +++ /dev/null @@ -1,113 +0,0 @@ -{ - "debug" : - { - "m0p" : { - "permission" : "disabled", - "control" : "firmware", - "key" : 5 - }, - "m4" : { - "permission" : "allowed", - "control" : "firmware", - "key" : 5 - }, - "system" : { - "permission" : "enabled", - "control" : "firmware", - "key" : 5, - "syscall": true, - "mmio": true, - "flash": true, - "workflash": true, - "sflash": true, - "sram": true - }, - "rma" : { - "permission" : "allowed", - "destroy_fuses" : [ - { - "start" : 888, - "size" : 136 - }, - { - "start" : 648, - "size" : 104 - } - ], - "destroy_flash" : [ - { - "start" : 268435456, - "size" : 851968 - }, - { - "start" : 269483520, - "size" : 16 - } - ], - "key" : 5 - } - }, - "wounding" : - { - }, - "boot_upgrade" : - { - "title": "upgrade_policy", - "firmware": [ - { - "boot_auth": [ - 3 - ], - "id": 0, - "launch": 4, - "smif_id": 0, - "upgrade": false, - "upgrade_auth": [ - 3 - ], - "resources": [ - { - "type": "FLASH_PC1_SPM", - "address": 269287424, - "size": 65536 - }, - { - "type": "SRAM_SPM_PRIV", - "address": 134348800, - "size": 65536 - }, - { - "type": "SRAM_DAP", - "address": 134397952, - "size": 16384 - } - ] - }, - { - "boot_auth": [ - 8 - ], - "id": 4, - "monotonic": 0, - "smif_id": 0, - "upgrade": true, - "upgrade_auth": [ - 8 - ], - - "resources": [ - { - "type": "BOOT", - "address": 268435456, - "size": 655360 - }, - { - "type": "UPGRADE", - "address": 269090816, - "size": 655360 - } - ] - } - ] - } -} \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/policy/policy_single_stage_CM4_smif.json b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/policy/policy_single_stage_CM4_smif.json deleted file mode 100644 index 36bb8fb840..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/policy/policy_single_stage_CM4_smif.json +++ /dev/null @@ -1,115 +0,0 @@ -{ - "debug" : - { - "m0p" : { - "permission" : "disabled", - "control" : "firmware", - "key" : 5 - }, - "m4" : { - "permission" : "allowed", - "control" : "firmware", - "key" : 5 - }, - "system" : { - "permission" : "enabled", - "control" : "firmware", - "key" : 5, - "syscall": true, - "mmio": true, - "flash": true, - "workflash": true, - "sflash": true, - "sram": true - }, - "rma" : { - "permission" : "allowed", - "destroy_fuses" : [ - { - "start" : 888, - "size" : 136 - }, - { - "start" : 648, - "size" : 104 - } - ], - "destroy_flash" : [ - { - "start" : 268435456, - "size" : 851968 - }, - { - "start" : 269483520, - "size" : 16 - } - ], - "key" : 5 - } - }, - "wounding" : - { - }, - "boot_upgrade" : - { - "title": "upgrade_policy", - "firmware": [ - { - "boot_auth": [ - 3 - ], - "id": 0, - "launch": 4, - "smif_id": 0, - "upgrade": false, - "upgrade_auth": [ - 3 - ], - "resources": [ - { - "type": "FLASH_PC1_SPM", - "address": 269287424, - "size": 65536 - }, - { - "type": "SRAM_SPM_PRIV", - "address": 134348800, - "size": 65536 - }, - { - "type": "SRAM_DAP", - "address": 134397952, - "size": 16384 - } - ] - }, - { - "boot_auth": [ - 8 - ], - "id": 4, - "monotonic": 0, - "smif_id": 1, - "upgrade": false, - "encrypt": false, - "encrypt_key_id": 1, - "upgrade_auth": [ - 8 - ], - - "resources": [ - { - "type": "BOOT", - "address": 268435456, - "size": 327680 - }, - { - "type": "UPGRADE", - "address": 402653184, - "size": 327680 - } - ] - } - ] - } -} \ No newline at end of file diff --git a/targets/targets.json b/targets/targets.json index fb3a2871c4..3ca7842539 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -6655,116 +6655,6 @@ "xip-enable": true } }, - "CY8CKIT_064S2_4343W": { - "inherits": [ - "MCU_PSOC6_M4" - ], - "features_add": [ - "BLE", - "PSA" - ], - "components_add": [ - "WHD", - "4343W", - "CYW43XXX" - ], - "components_remove": [ - "QSPIF" - ], - "supported_form_factors": [ - "ARDUINO" - ], - "device_has_remove": [ - "ANALOGOUT", - "QSPI" - ], - "extra_labels_add": [ - "PSOC6_02", - "MXCRYPTO_02", - "CORDIO", - "TFM", - "TFM_DUALCPU" - ], - "macros_add": [ - "CYB0644ABZI_S2D44", - "CYBSP_WIFI_CAPABLE", - "TFM_MULTI_CORE_MULTI_CLIENT_CALL=1" - ], - "detect_code": [ - "190A" - ], - "post_binary_hook": { - "function": "PSOC6Code.sign_image" - }, - "forced_reset_timeout": 5, - "overrides": { - "network-default-interface-type": "WIFI" - }, - "program_cycle_s": 10, - "tfm_target_name": "psoc64", - "tfm_bootloader_supported": false, - "tfm_default_toolchain": "GNUARM", - "tfm_supported_toolchains": [ - "GNUARM" - ], - "tfm_delivery_dir": "TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W", - "TFM_OUTPUT_EXT": "hex" - }, - "CYESKIT_064B0S2_4343W": { - "inherits": [ - "MCU_PSOC6_M4" - ], - "features_add": [ - "BLE", - "PSA" - ], - "components_add": [ - "WHD", - "4343W", - "CYW43XXX" - ], - "components_remove": [ - "QSPIF" - ], - "supported_form_factors": [ - "ARDUINO" - ], - "device_has_remove": [ - "ANALOGOUT", - "QSPI" - ], - "extra_labels_add": [ - "PSOC6_02", - "MXCRYPTO_02", - "CORDIO", - "TFM", - "TFM_DUALCPU" - ], - "macros_add": [ - "CYB0644ABZI_S2D44", - "CYBSP_WIFI_CAPABLE", - "TFM_MULTI_CORE_MULTI_CLIENT_CALL=1" - ], - "detect_code": [ - "190A" - ], - "post_binary_hook": { - "function": "PSOC6Code.sign_image" - }, - "forced_reset_timeout": 5, - "overrides": { - "network-default-interface-type": "WIFI" - }, - "program_cycle_s": 10, - "tfm_target_name": "psoc64", - "tfm_bootloader_supported": false, - "tfm_default_toolchain": "GNUARM", - "tfm_supported_toolchains": [ - "GNUARM" - ], - "tfm_delivery_dir": "TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W", - "TFM_OUTPUT_EXT": "hex" - }, "CY8CKIT_062_WIFI_BT": { "inherits": [ "MCU_PSOC6_M4" @@ -6840,35 +6730,6 @@ ], "bootloader_supported": false }, - "CY8CPROTO_064_SB": { - "inherits": [ - "MCU_PSOC6_M4" - ], - "components_remove": [ - "QSPIF" - ], - "device_has_remove": [ - "QSPI" - ], - "extra_labels_add": [ - "PSOC6_01", - "MXCRYPTO_01" - ], - "macros_add": [ - "CYB06447BZI_D54", - "PSOC6_DYNSRM_DISABLE=1", - "CY_CFG_SYSCLK_WCO_ENABLED=1", - "SEMAPHORE" - ], - "detect_code": [ - "1907" - ], - "forced_reset_timeout": 5, - "reset_method": "default", - "post_binary_hook": { - "function": "PSOC6Code.sign_image" - } - }, "CYW9P62S1_43438EVB_01": { "inherits": [ "MCU_PSOC6_M4" @@ -6956,6 +6817,57 @@ "network-default-interface-type": "WIFI" } }, + "CY8CKIT_064B0S2_4343W": { + "inherits": [ + "MCU_PSOC6_M4" + ], + "supported_form_factors": [ + "ARDUINO" + ], + "features": [ + "BLE" + ], + "components_add": [ + "WHD", + "4343W", + "CYW43XXX", + "CM0P_SECURE" + ], + "components_remove": [ + "QSPIF", + "CM0P_SLEEP" + ], + "device_has_remove": [ + "ANALOGOUT", + "QSPI" + ], + "extra_labels_add": [ + "PSOC6_02", + "MXCRYPTO_02", + "CORDIO" + ], + "macros_add": [ + "CYB0644ABZI_S2D44", + "CY_IPC_DEFAULT_CFG_DISABLE", + "CYBSP_WIFI_CAPABLE" + ], + "detect_code": [ + "1910" + ], + "forced_reset_timeout": 5, + "hex_filename": "psoc6_02_cm0p_secure.hex", + "cm0_img_id": 1, + "cm4_img_id": 16, + "boot_scheme": "single_image", + "policy_file": "policy_single_CM0_CM4.json", + "post_binary_hook": { + "function": "PSOC6Code.sign_image" + }, + "overrides": { + "network-default-interface-type": "WIFI" + }, + "program_cycle_s": 10 + }, "CYSBSYSKIT_01": { "inherits": [ "MCU_PSOC6_M4" diff --git a/tools/targets/PSOC6.py b/tools/targets/PSOC6.py index b906937ccc..a49f78fdc1 100644 --- a/tools/targets/PSOC6.py +++ b/tools/targets/PSOC6.py @@ -24,6 +24,7 @@ from struct import (pack, unpack) from shutil import copy2 import json from intelhex import IntelHex, hex2bin, bin2hex +from pathlib import Path from ..config import ConfigException @@ -145,344 +146,113 @@ def find_cm0_image(toolchain, resources, elf, hexf, hex_filename): return m0hexf -# check if policy parameters are consistent -def check_slots_integrity(toolchain, fw_cyb, target_data, fw_spe=None, fw_nspe=None): - """ - Function checks consistency of parameters presented in - policy file used for build of Secure Boot enabled target. - :param toolchain: Toolchain object of current build session - :param fw_cyb: CyBootloader firmware description from policy - :param target_data: Object contains description of - processing target from target.json - :param fw_spe: CM0p firmware descpription object from policy - :param fw_nspe: CM4 firmware descpription object from policy - :return: List of slots and image id corresponding to them - """ - slot0 = None - slot1 = None - - if fw_spe is None: - img_id = fw_nspe["id"] - - # check single stage scheme - if not (fw_cyb["launch"] == img_id): - # may be PSA NSPE part - if not fw_cyb["launch"] == SPE_IMAGE_ID: - toolchain.notify.debug("[PSOC6.sign_image] WARNING: ID of build image " + str(img_id) + - " does not correspond launch ID in CyBootloader - " + str(fw_cyb["launch"])) - else: - toolchain.notify.info("[PSOC6.sign_image] INFO: NSPE image ID is " + str(img_id) + - ". It will be launched by SPE part.") - - # check slots addresses and sizes if upgrade is set to True - for slot in fw_nspe["resources"]: - if slot["type"] == "BOOT": - slot0 = slot - - if fw_nspe["upgrade"] is True: - slot1 = slot - if slot["type"] == "UPGRADE": - if fw_nspe.get("encrypt") is True: - # mark slot1 image as one, that should be encrypted - slot1.update({'encrypt': True}) - toolchain.notify.info("[PSOC6.sign_image] INFO: Image for UPGRADE NSPE will" - " be ENCRYPTED per policy settings.") - else: - pass - else: - toolchain.notify.info("[PSOC6.sign_image] INFO: Image for UPGRADE will not" - " be built per policy settings.") - break - if slot0 is None: - toolchain.notify.debug("[PSOC6.sign_image] WARNING: BOOT section not found in policy resources") - raise AddSignatureError("PSOC6.sign_image finished execution with errors! Signature is not added.") - - else: - # check if PSA targets flash map correspond to slots addresses and sizes in policy - if not (int(target_data["overrides"]["secure-rom-start"], 16) - MCUBOOT_HEADER_SIZE) ==\ - int(fw_spe["resources"][0]["address"]): - toolchain.notify.debug("[PSOC6.sign_image] WARNING: SPE start address " - "does not correspond BOOT slot start address defined in policy. " - "Check if MCUboot header offset 0x400 is included in SPE flash start") - - if not (int(target_data["overrides"]["non-secure-rom-start"], 16) - MCUBOOT_HEADER_SIZE) ==\ - int(fw_nspe["resources"][0]["address"]): - toolchain.notify.debug("[PSOC6.sign_image] WARNING: NSPE start address " - "does not correspond BOOT slot start address defined in policy. " - "Check if MCUboot header offset 0x400 is included in NSPE flash start") - - if (int(target_data["overrides"]["secure-rom-size"], 16) + MCUBOOT_HEADER_SIZE) >\ - int(fw_spe["resources"][0]["size"]): - toolchain.notify.debug("[PSOC6.sign_image] WARNING: SPE flash size " - "does not fit in BOOT slot size defined in policy.") - - if (int(target_data["overrides"]["non-secure-rom-size"], 16) + MCUBOOT_HEADER_SIZE) >\ - int(fw_nspe["resources"][0]["size"]): - toolchain.notify.debug("[PSOC6.sign_image] WARNING: NSPE flash size " - "does not fit in BOOT slot size defined in policy.") - - img_id = fw_spe["id"] - # check dual stage scheme - if img_id != 1: - toolchain.notify.debug("[PSOC6.sign_image] ERROR: Image ID of SPE image" - " is not equal to 1!") - raise AddSignatureError("PSOC6.sign_image finished execution with errors! Signature is not added.") - - if not (fw_cyb["launch"] == img_id): - toolchain.notify.debug("[PSOC6.sign_image] ERROR: ID of build image" - " does not correspond launch ID in CyBootloader!") - raise AddSignatureError("PSOC6.sign_image finished execution with errors! Signature is not added.") - - if not (fw_spe["launch"] == fw_nspe["id"]): - toolchain.notify.debug("[PSOC6.sign_image] ERROR: ID of NSPE image" - " does not correspond launch ID in SPE part!") - raise AddSignatureError("PSOC6.sign_image finished execution with errors! Signature is not added.") - - # check slots addresses and sizes if upgrade is set to True - for slot in fw_spe["resources"]: - if slot["type"] == "BOOT": - slot0 = slot - if fw_spe["upgrade"] is True: - if slot["type"] == "UPGRADE": - slot1 = slot - if fw_spe.get("encrypt") is True: - # mark slot1 image as one, that should be encrypted - slot1.update({'encrypt': True}) - toolchain.notify.info("[PSOC6.sign_image] INFO: Image for UPGRADE SPE will" - " be ENCRYPTED per policy settings.") - else: - pass - else: - toolchain.notify.info("[PSOC6.sign_image] INFO: Image for UPGRADE will not" - " be produced per policy settings.") - if slot0 is None: - toolchain.notify.debug("[PSOC6.sign_image] WARNING: BOOT section not found in policy resources") - raise AddSignatureError("PSOC6.sign_image finished execution with errors! Signature is not added.") - - if slot1 is not None: - # bigger or equal to 0x18000000 in hex is a start of SMIF memory - if slot1["address"] >= SMIF_MEM_MAP_START: - toolchain.notify.info("[PSOC6.sign_image] INFO: UPGRADE slot will be resided in external flash") - - if slot0["size"] != slot1["size"]: - toolchain.notify.debug("[PSOC6.sign_image] WARNING: BOOT and UPGRADE slots sizes are not equal") - - return (slot0, slot1, img_id) - else: - return (slot0, None, img_id) - - -def process_target(toolchain, target): - """ - Gathers and process information about target being built - :param toolchain: Toolchain object of current build session - :param target: Name of target being built - :return: List with all data needed for adding signature - """ - from pathlib import Path - - targets_json = Path("targets/targets.json") - cy_targets = Path("targets/TARGET_Cypress/TARGET_PSOC6/") - sb_params_file_name = Path("secure_image_parameters.json") - root_dir = Path(os.getcwd()) - - mbed_os_targets = root_dir / targets_json - - if not os.path.isfile(str(mbed_os_targets)): - # try location for tests - mbed_os_targets = root_dir / 'mbed-os' / targets_json - root_dir = root_dir / 'mbed-os' - if not os.path.isfile(str(mbed_os_targets)): - toolchain.notify.debug("[PSOC6.sign_image] ERROR: targets.json not found!") - raise AddSignatureError("PSOC6.sign_image finished execution with errors! Signature is not added.") - - with open(str(mbed_os_targets)) as j: - json_str = j.read() - all_targets = json.loads(json_str) - j.close() - - processing_target = all_targets[target] - sb_params_file_path = root_dir / cy_targets / Path("TARGET_" + str(target)) / sb_params_file_name - - if os.path.isfile(str(sb_params_file_path)): - with open(str(sb_params_file_path)) as f: - json_str = f.read() - sb_config = json.loads(json_str) - f.close() - else: - toolchain.notify.debug("[PSOC6.sign_image] ERROR: secure_image_parametest.json not found!") - raise AddSignatureError("PSOC6.sign_image finished execution with errors! Signature is not added.") - - sdk_path = root_dir / sb_config["sdk_path"] - - priv_key_path = sdk_path / Path(sb_config["priv_key_file"]) - - if not os.path.isfile(str(priv_key_path)): - toolchain.notify.debug("[PSOC6.sign_image] ERROR: Private key file not found in " + str(priv_key_path)) - raise AddSignatureError("PSOC6.sign_image finished execution with errors! Signature is not added.") - - if "_PSA" in target: - # assume dual stage bootloading scheme - with open(sdk_path / Path(sb_config["policy_file"])) as p: - policy_str = p.read() - policy_file = json.loads(policy_str) - p.close() - - firmware_list = policy_file["boot_upgrade"]["firmware"] - - # collect firmware descriptions from policy for corresponding images - firmware_cyb_cm0p = firmware_list[0] - - if "_M0_" in target: - firmware_spe_cm0p = firmware_list[1] - firmware_nspe_cm4 = firmware_list[2] - - slots = check_slots_integrity(toolchain, fw_cyb=firmware_cyb_cm0p, fw_spe=firmware_spe_cm0p, - fw_nspe=firmware_nspe_cm4, target_data=processing_target) - else: - firmware_nspe_cm4 = firmware_list[2] - slots = check_slots_integrity(toolchain, fw_cyb=firmware_cyb_cm0p, fw_nspe=firmware_nspe_cm4, - target_data=processing_target) - else: - # consider single stage bootloading scheme - with open(sdk_path / Path(sb_config["policy_file"])) as p: - policy_str = p.read() - policy_file = json.loads(policy_str) - p.close() - - firmware_list = policy_file["boot_upgrade"]["firmware"] - firmware_cyb_cm0p = firmware_list[0] - firmware_nspe_cm4 = firmware_list[1] - slots = check_slots_integrity(toolchain, fw_cyb=firmware_cyb_cm0p, - fw_nspe=firmware_nspe_cm4, target_data=processing_target) - - target_sig_data = [{"img_data": sb_config["boot0"], "slot_data": slots[0], - "key_file": sb_config["priv_key_file"], "sdk_path": sdk_path, "id": slots[2]}] - - if slots[1] is not None: - target_sig_data.append({"img_data": sb_config["boot1"], "slot_data": slots[1], - "key_file": sb_config["priv_key_file"], "sdk_path": sdk_path, "id": slots[2]}) - # check if slot1 image sould be encrypted - if slots[1].get("encrypt") is True: - - dev_pub_key = sdk_path / Path(sb_config["dev_pub_key_file"]) - if not os.path.isfile(str(dev_pub_key)): - toolchain.notify.debug("[PSOC6.sign_image] ERROR: Device public key file not found in " + str(dev_pub_key)) - raise AddSignatureError("PSOC6.sign_image finished execution with errors! Signature is not added.") - - aes_key_file = sdk_path / Path(sb_config["aes_key_file"]) - if not os.path.isfile(str(aes_key_file)): - toolchain.notify.debug("[PSOC6.sign_image] ERROR: AES-128 key file not found in " + str(aes_key_file)) - raise AddSignatureError("PSOC6.sign_image finished execution with errors! Signature is not added.") - - target_sig_data[1].update({"aes_key": sb_config["aes_key_file"], "dev_pub_key": sb_config["dev_pub_key_file"]}) - - else: - toolchain.notify.info("[PSOC6.sign_image] INFO: Image for slot UPGRADE would not be encrypted per policy settings") - - return target_sig_data - - -def sign_image(toolchain, binf): +def sign_image(toolchain, resourses, elf, binf, m0hex): """ Adds signature to a binary file being built, - prepares some intermediate binary artifacts. + using cysecuretools python package. :param toolchain: Toolchain object of current build session :param binf: Binary file created for target """ - from pathlib import PurePath - target_sig_data = None - # reserve name for separate NSPE image - out_cm4_hex = binf[:-4] + "_cm4.hex" + if m0hex != '': + m0hex_build = os.path.join(toolchain.build_dir, toolchain.target.hex_filename) + copy2(m0hex, m0hex_build) + m0hex = m0hex_build - # preserve original hex file from mbed-os build - mbed_hex = binf[:-4] + "_unsigned.hex" - copy2(binf, mbed_hex) + # Mapping from mbed target to cysecuretools target + TARGET_MAPPING = { + "CY8CKIT_064B0S2_4343W": "cy8ckit-064b0s2-4343w", + "CY8CPROTO_064B0S1_BLE": "cy8cproto-064b0s1-ble", + "CY8CPROTO_064S1_SB" : "cy8cproto-064s1-sb", + "CY8CPROTO_064B0S3" : "cy8cproto-064b0s3" + } - # find target name and type before processing - for part in PurePath(binf).parts: - if "CY" in part: - target_sig_data = process_target(toolchain=toolchain, target=part) + try: + secure_target = TARGET_MAPPING[toolchain.target.name] + except KeyError: + raise ConfigException("[PSOC6.sign_image] Target " + toolchain.target.name + " is not supported in cysecuretools.") - if target_sig_data is None: - toolchain.notify.debug("[PSOC6.sign_image] ERROR: Target not found!") - raise AddSignatureError("PSOC6.sign_image finished execution with errors! Signature is not added.") + policy_file = find_policy(toolchain) - for slot in target_sig_data: - # first check if image for slot under processing should be encrypted - if slot["slot_data"].get("encrypt") is True: - # call encrypt_img to perform encryption - args = [sys.executable, str(slot["sdk_path"] / "encrypted_image_runner.py"), - "--sdk-path", str(slot["sdk_path"]), "--hex-file", os.getcwd() + '/' + mbed_hex, - "--key-priv", str(slot["sdk_path"] / slot["key_file"]), - "--key-pub", str(slot["sdk_path"] / slot["dev_pub_key"]), - "--key-aes", str(slot["sdk_path"] / slot["aes_key"]), - "--ver", str(slot["img_data"]["VERSION"]), "--img-id", str(slot["id"]), - "--rlb-count", str(slot["img_data"]["ROLLBACK_COUNTER"]), - "--slot-size", str(hex(slot["slot_data"]["size"])), - "--img-offset", str(slot["slot_data"]["address"])] - if slot["slot_data"]["type"] != "BOOT": - args.append("--pad") - process = subprocess.Popen(args, stdout=subprocess.PIPE, stderr=subprocess.PIPE) + toolchain.notify.info("[PSOC6.sign_image] Using policy file: " + str(policy_file)) - # catch standard process pipes outputs - stderr = process.communicate()[1] - stdout = process.communicate()[0] - rc = process.wait() - toolchain.notify.info(stdout.decode("utf-8")) + import cysecuretools + + tools = cysecuretools.CySecureTools(secure_target, str(policy_file)) + + if str(toolchain.target.boot_scheme) == 'single_image': + toolchain.notify.info("[PSOC6.sign_image] single image signing") + sign_application(toolchain, tools, binf, image_id=toolchain.target.cm0_img_id) + + elif str(toolchain.target.boot_scheme) == 'multi_image': + sign_application(toolchain, tools, m0hex, image_id=toolchain.target.cm0_img_id) + sign_application(toolchain, tools, binf, image_id=toolchain.target.cm4_img_id) + + complete(toolchain, elf, hexf0=binf, hexf1=m0hex) + + else: + raise ConfigException("[PSOC6.sign_image] Boot scheme " + str(toolchain.target.boot_scheme) + \ + "is not supported. Supported boot schemes are 'single_image' and 'multi_image' ") + + +def sign_application(toolchain, tools, binary, image_id): + """ + Helper function for adding signature to binary + :param tools: CySecureTools object + :param binary: Path to binary file to add signature + :param image_id: ID of image slot in which binary will be flashed + """ + + # Get address and size of image slot from policy for passed image_id + # UPGRADE image will be generated automatically by cysecuretools + address, size = tools.flash_map(image_id=image_id, image_type="BOOT") + + tools.sign_image(binary, image_id) + toolchain.notify.debug("[PSOC6.sign_image] Slot start address and size for image ID " \ + + str(image_id) + " is " + hex(address) + ", " + hex(size)) + + +def find_policy(toolchain): + """ + Locate path to policy file, by name defined in targets.json + :param toolchain: toolchain object from mbed build system + """ + + mbed_os_root = Path(os.getcwd()) + + policy_path = Path(toolchain.target.policy_file) + + # Absolute path provided + if policy_path.is_absolute(): + policy_file = policy_path + + # May also be relative to mbed-os file scturcture + else: + policy_path = mbed_os_root / policy_path + + if os.path.exists(str(policy_path)): + policy_file = policy_path - if rc != 0: - toolchain.notify.debug("[PSOC6.sign_image] ERROR: Encryption script ended with error!") - toolchain.notify.debug("[PSOC6.sign_image] Message from encryption script: " + stderr.decode("utf-8")) - raise AddSignatureError("PSOC6.sign_image finished execution with errors! Signature is not added.") - else: - toolchain.notify.info("[PSOC6.sign_image] SUCCESS: Image for slot " + - slot["slot_data"]["type"] + " is signed and encrypted with no errors!") - # all non ecrypted images take this path else: - if slot["slot_data"]["type"] == "UPGRADE": - out_hex_name = binf[:-4] + "_upgrade.hex" - else: - out_hex_name = binf + default_path = Path("targets/TARGET_Cypress/TARGET_PSOC6/") / \ + Path("TARGET_" + toolchain.target.name) / Path("policy") / \ + toolchain.target.policy_file + + # Consider default location + policy_file = mbed_os_root / default_path - out_bin_name = out_hex_name[:-4] + "_signed.bin" + if not os.path.exists(str(policy_file)): + policy_file = mbed_os_root / "mbed-os" / default_path - # call imgtool for signature - args = [sys.executable, str(slot["sdk_path"] / "imgtool/imgtool.py"), - "sign", "--key", str(slot["sdk_path"] / slot["key_file"]), - "--header-size", str(hex(MCUBOOT_HEADER_SIZE)), "--pad-header", "--align", "8", - "--version", str(slot["img_data"]["VERSION"]), "--image-id", - str(slot["id"]), "--rollback_counter", str(slot["img_data"]["ROLLBACK_COUNTER"]), - "--slot-size", str(hex(slot["slot_data"]["size"])), "--overwrite-only", - mbed_hex, out_hex_name] - if slot["slot_data"]["type"] != "BOOT": - args.append("--pad") - process = subprocess.Popen(args, stdout=subprocess.PIPE, stderr=subprocess.PIPE) - # catch stderr outputs - stderr = process.communicate()[1] - rc = process.wait() + if os.path.exists(str(policy_file)): + toolchain.notify.info("Policy file found: %s." % policy_file) + else: + toolchain.notify.info("Policy file %s not found. Aborting." % policy_path) + raise ConfigException("Required policy file not found.") - if rc != 0: - toolchain.notify.debug("[PSOC6.sign_image] ERROR: Signature is not added!") - toolchain.notify.debug("[PSOC6.sign_image] Message from imgtool: " + stderr.decode("utf-8")) - raise AddSignatureError("PSOC6.sign_image finished execution with errors! Signature is not added.") - else: - toolchain.notify.info("[PSOC6.sign_image] SUCCESS: Image for slot " + - slot["slot_data"]["type"] + " is signed with no errors!") - # preserve signed binary file - hex2bin(out_hex_name, out_bin_name) + return policy_file - # preserve separate hex for cm4 - # 16 is image ID for NSPE image - if slot["id"] == NSPE_IMAGE_ID: - copy2(out_hex_name, out_cm4_hex) - - # produce hex file for slot1 - if slot["slot_data"]["type"] == "UPGRADE": - bin2hex(out_bin_name, out_hex_name, offset=int(slot["slot_data"]["address"])) - toolchain.notify.info("Image UPGRADE: " + out_hex_name + "\n") def complete(toolchain, elf0, hexf0, hexf1=None): diff --git a/tools/targets/__init__.py b/tools/targets/__init__.py index 9bb5467f6b..79d9819ade 100644 --- a/tools/targets/__init__.py +++ b/tools/targets/__init__.py @@ -669,20 +669,17 @@ class PSOC6Code(object): def sign_image(t_self, resources, elf, binf): """ Calls sign_image function to add signature to Secure Boot binary file. + This function is used with Cypress kits, that support cysecuretools signing. """ - version = sys.version_info + from tools.targets.PSOC6 import sign_image as psoc6_sign_image + if hasattr(t_self.target, "hex_filename"): + hex_filename = t_self.target.hex_filename + # Completing main image involves merging M0 image. + from tools.targets.PSOC6 import find_cm0_image + m0hexf = find_cm0_image(t_self, resources, elf, binf, hex_filename) + + psoc6_sign_image(t_self, resources, elf, binf, m0hexf) - # check python version before calling post build as is supports only python3+ - if((version[0] < 3) is True): - t_self.notify.info("[PSOC6.sing_image] Be careful - produced HEX file was not signed and thus " - "is not compatible with Cypress Secure Boot target. " - "You are using Python " + str(sys.version[:5]) + - " which is not supported by CySecureTools. " - "Consider installing Python 3.4+ and rebuild target. " - "For more information refver to User Guide https://www.cypress.com/secureboot-sdk-user-guide") - else: - from tools.targets.PSOC6 import sign_image as psoc6_sign_image - psoc6_sign_image(t_self, binf) class ArmMuscaA1Code(object): """Musca-A1 Hooks"""
VersionChangesReason for Change
1.30Updated the following functions for the PSoC 64 devices: \ref Cy_WDT_ClearInterrupt(), +* \ref Cy_WDT_MaskInterrupt(), and \ref Cy_WDT_UnmaskInterrupt().Added PSoC 64 device support.
Minor documentation updates.Documentation enhancement.
1.20Added a new API function \ref Cy_WDT_IsEnabled() Enhancement based on usability feedback.
1.10Flattened the organization of the driver source code into the single +* Flattened the organization of the driver source code into the single * source directory and the single include directory. * Driver library directory-structure simplification.
Added register access layer. Use register access macros instead * of direct register access using dereferenced pointers.Makes register access device-independent, so that the PDL does +* Makes register access device-independent, so that the PDL does * not need to be recompiled for each supported part number.