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Update GeneratedSource of 064B0S2 with repo-starging 15347 revision

pull/13122/head
Roman Okhrimenko 2020-06-18 21:45:17 +03:00
parent dcc3559a82
commit 00cbc2d54e
16 changed files with 494 additions and 323 deletions
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8
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c
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@ -4,13 +4,11 @@
* Description:
* Wrapper function to initialize all generated code.
* This file was automatically generated and should not be modified.
* Tools Package 2.2.0.1747
* psoc6pdl 1.6.0.4266
* personalities_2.0 2.0.0.0
* udd 1.2.0.370
* cfg-backend-cli: 1.2.0.1483
* Device Support Library (libs/psoc6pdl): 1.6.0.4266
*
********************************************************************************
* Copyright 2020 Cypress Semiconductor Corporation
* Copyright 2017-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");

8
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h
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@ -4,13 +4,11 @@
* Description:
* Simple wrapper header containing all generated files.
* This file was automatically generated and should not be modified.
* Tools Package 2.2.0.1747
* psoc6pdl 1.6.0.4266
* personalities_2.0 2.0.0.0
* udd 1.2.0.370
* cfg-backend-cli: 1.2.0.1483
* Device Support Library (libs/psoc6pdl): 1.6.0.4266
*
********************************************************************************
* Copyright 2020 Cypress Semiconductor Corporation
* Copyright 2017-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");

54
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp
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@ -1,28 +1,26 @@
/*******************************************************************************
* File Name: cycfg.timestamp
*
* Description:
* Sentinel file for determining if generated source is up to date.
* This file was automatically generated and should not be modified.
* Tools Package 2.2.0.1747
* psoc6pdl 1.6.0.4266
* personalities_2.0 2.0.0.0
* udd 1.2.0.370
*
********************************************************************************
* Copyright 2020 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
********************************************************************************/
/*******************************************************************************
* File Name: cycfg.timestamp
*
* Description:
* Sentinel file for determining if generated source is up to date.
* This file was automatically generated and should not be modified.
* cfg-backend-cli: 1.2.0.1483
* Device Support Library (libs/psoc6pdl): 1.6.0.4266
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
********************************************************************************/

10
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c
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@ -4,13 +4,11 @@
* Description:
* Clock configuration
* This file was automatically generated and should not be modified.
* Tools Package 2.2.0.1747
* psoc6pdl 1.6.0.4266
* personalities_2.0 2.0.0.0
* udd 1.2.0.370
* cfg-backend-cli: 1.2.0.1483
* Device Support Library (libs/psoc6pdl): 1.6.0.4266
*
********************************************************************************
* Copyright 2020 Cypress Semiconductor Corporation
* Copyright 2017-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -29,7 +27,7 @@
#include "cycfg_clocks.h"
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj =
const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj =
{
.type = CYHAL_RSC_CLOCK,
.block_num = CYBSP_CSD_CLK_DIV_HW,

8
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h
View File

@ -4,13 +4,11 @@
* Description:
* Clock configuration
* This file was automatically generated and should not be modified.
* Tools Package 2.2.0.1747
* psoc6pdl 1.6.0.4266
* personalities_2.0 2.0.0.0
* udd 1.2.0.370
* cfg-backend-cli: 1.2.0.1483
* Device Support Library (libs/psoc6pdl): 1.6.0.4266
*
********************************************************************************
* Copyright 2020 Cypress Semiconductor Corporation
* Copyright 2017-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");

8
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h
View File

@ -5,13 +5,11 @@
* Contains warnings and errors that occurred while generating code for the
* design.
* This file was automatically generated and should not be modified.
* Tools Package 2.2.0.1747
* psoc6pdl 1.6.0.4266
* personalities_2.0 2.0.0.0
* udd 1.2.0.370
* cfg-backend-cli: 1.2.0.1483
* Device Support Library (libs/psoc6pdl): 1.6.0.4266
*
********************************************************************************
* Copyright 2020 Cypress Semiconductor Corporation
* Copyright 2017-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");

10
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c
View File

@ -4,13 +4,11 @@
* Description:
* Peripheral Hardware Block configuration
* This file was automatically generated and should not be modified.
* Tools Package 2.2.0.1747
* psoc6pdl 1.6.0.4266
* personalities_2.0 2.0.0.0
* udd 1.2.0.370
* cfg-backend-cli: 1.2.0.1483
* Device Support Library (libs/psoc6pdl): 1.6.0.4266
*
********************************************************************************
* Copyright 2020 Cypress Semiconductor Corporation
* Copyright 2017-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -28,7 +26,7 @@
#include "cycfg_peripherals.h"
cy_stc_csd_context_t cy_csd_0_context =
cy_stc_csd_context_t cy_csd_0_context =
{
.lockKey = CY_CSD_NONE_KEY,
};

10
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h
View File

@ -4,13 +4,11 @@
* Description:
* Peripheral Hardware Block configuration
* This file was automatically generated and should not be modified.
* Tools Package 2.2.0.1747
* psoc6pdl 1.6.0.4266
* personalities_2.0 2.0.0.0
* udd 1.2.0.370
* cfg-backend-cli: 1.2.0.1483
* Device Support Library (libs/psoc6pdl): 1.6.0.4266
*
********************************************************************************
* Copyright 2020 Cypress Semiconductor Corporation
* Copyright 2017-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -40,7 +38,7 @@ extern "C" {
#define CYBSP_CSD_ENABLED 1U
#define CY_CAPSENSE_CORE 4u
#define CY_CAPSENSE_CPU_CLK 100000000u
#define CY_CAPSENSE_PERI_CLK 50000000u
#define CY_CAPSENSE_PERI_CLK 100000000u
#define CY_CAPSENSE_VDDA_MV 3300u
#define CY_CAPSENSE_PERI_DIV_TYPE CY_SYSCLK_DIV_8_BIT
#define CY_CAPSENSE_PERI_DIV_INDEX 0u

72
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c
View File

@ -4,13 +4,11 @@
* Description:
* Pin configuration
* This file was automatically generated and should not be modified.
* Tools Package 2.2.0.1747
* psoc6pdl 1.6.0.4266
* personalities_2.0 2.0.0.0
* udd 1.2.0.370
* cfg-backend-cli: 1.2.0.1483
* Device Support Library (libs/psoc6pdl): 1.6.0.4266
*
********************************************************************************
* Copyright 2020 Cypress Semiconductor Corporation
* Copyright 2017-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -28,7 +26,7 @@
#include "cycfg_pins.h"
const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config =
const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
@ -45,14 +43,14 @@ const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config =
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_WCO_IN_obj =
const cyhal_resource_inst_t CYBSP_WCO_IN_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_WCO_IN_PORT_NUM,
.channel_num = CYBSP_WCO_IN_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config =
const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
@ -69,14 +67,14 @@ const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config =
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_WCO_OUT_obj =
const cyhal_resource_inst_t CYBSP_WCO_OUT_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_WCO_OUT_PORT_NUM,
.channel_num = CYBSP_WCO_OUT_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_CSD_RX_config =
const cy_stc_gpio_pin_config_t CYBSP_CSD_RX_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
@ -93,14 +91,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_RX_config =
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CSD_RX_obj =
const cyhal_resource_inst_t CYBSP_CSD_RX_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_CSD_RX_PORT_NUM,
.channel_num = CYBSP_CSD_RX_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_SWO_config =
const cy_stc_gpio_pin_config_t CYBSP_SWO_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
@ -117,14 +115,14 @@ const cy_stc_gpio_pin_config_t CYBSP_SWO_config =
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_SWO_obj =
const cyhal_resource_inst_t CYBSP_SWO_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_SWO_PORT_NUM,
.channel_num = CYBSP_SWO_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config =
const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_PULLUP,
@ -141,14 +139,14 @@ const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config =
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_SWDIO_obj =
const cyhal_resource_inst_t CYBSP_SWDIO_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_SWDIO_PORT_NUM,
.channel_num = CYBSP_SWDIO_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config =
const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_PULLDOWN,
@ -165,14 +163,14 @@ const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config =
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_SWDCK_obj =
const cyhal_resource_inst_t CYBSP_SWDCK_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_SWDCK_PORT_NUM,
.channel_num = CYBSP_SWDCK_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_CINA_config =
const cy_stc_gpio_pin_config_t CYBSP_CINA_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
@ -189,14 +187,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CINA_config =
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CINA_obj =
const cyhal_resource_inst_t CYBSP_CINA_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_CINA_PORT_NUM,
.channel_num = CYBSP_CINA_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_CINB_config =
const cy_stc_gpio_pin_config_t CYBSP_CINB_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
@ -213,14 +211,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CINB_config =
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CINB_obj =
const cyhal_resource_inst_t CYBSP_CINB_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_CINB_PORT_NUM,
.channel_num = CYBSP_CINB_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_CMOD_config =
const cy_stc_gpio_pin_config_t CYBSP_CMOD_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
@ -237,14 +235,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CMOD_config =
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CMOD_obj =
const cyhal_resource_inst_t CYBSP_CMOD_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_CMOD_PORT_NUM,
.channel_num = CYBSP_CMOD_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config =
const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
@ -261,14 +259,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config =
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CSD_BTN0_obj =
const cyhal_resource_inst_t CYBSP_CSD_BTN0_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_CSD_BTN0_PORT_NUM,
.channel_num = CYBSP_CSD_BTN0_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config =
const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
@ -285,14 +283,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config =
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CSD_BTN1_obj =
const cyhal_resource_inst_t CYBSP_CSD_BTN1_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_CSD_BTN1_PORT_NUM,
.channel_num = CYBSP_CSD_BTN1_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config =
const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
@ -309,14 +307,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config =
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CSD_SLD0_obj =
const cyhal_resource_inst_t CYBSP_CSD_SLD0_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_CSD_SLD0_PORT_NUM,
.channel_num = CYBSP_CSD_SLD0_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config =
const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
@ -333,14 +331,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config =
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CSD_SLD1_obj =
const cyhal_resource_inst_t CYBSP_CSD_SLD1_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_CSD_SLD1_PORT_NUM,
.channel_num = CYBSP_CSD_SLD1_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config =
const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
@ -357,14 +355,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config =
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CSD_SLD2_obj =
const cyhal_resource_inst_t CYBSP_CSD_SLD2_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_CSD_SLD2_PORT_NUM,
.channel_num = CYBSP_CSD_SLD2_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config =
const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
@ -381,14 +379,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config =
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CSD_SLD3_obj =
const cyhal_resource_inst_t CYBSP_CSD_SLD3_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_CSD_SLD3_PORT_NUM,
.channel_num = CYBSP_CSD_SLD3_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config =
const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
@ -405,7 +403,7 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config =
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CSD_SLD4_obj =
const cyhal_resource_inst_t CYBSP_CSD_SLD4_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_CSD_SLD4_PORT_NUM,

40
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h
View File

@ -4,13 +4,11 @@
* Description:
* Pin configuration
* This file was automatically generated and should not be modified.
* Tools Package 2.2.0.1747
* psoc6pdl 1.6.0.4266
* personalities_2.0 2.0.0.0
* udd 1.2.0.370
* cfg-backend-cli: 1.2.0.1483
* Device Support Library (libs/psoc6pdl): 1.6.0.4266
*
********************************************************************************
* Copyright 2020 Cypress Semiconductor Corporation
* Copyright 2017-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -62,7 +60,7 @@ extern "C" {
#define CYBSP_WCO_IN_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_WCO_IN_HAL_DIR CYHAL_GPIO_DIR_INPUT
#define CYBSP_WCO_IN_HAL_DIR CYHAL_GPIO_DIR_INPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_WCO_IN_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
@ -89,7 +87,7 @@ extern "C" {
#define CYBSP_WCO_OUT_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_WCO_OUT_HAL_DIR CYHAL_GPIO_DIR_INPUT
#define CYBSP_WCO_OUT_HAL_DIR CYHAL_GPIO_DIR_INPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_WCO_OUT_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
@ -116,7 +114,7 @@ extern "C" {
#define CYBSP_CSD_RX_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_RX_HAL_DIR CYHAL_GPIO_DIR_INPUT
#define CYBSP_CSD_RX_HAL_DIR CYHAL_GPIO_DIR_INPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_RX_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
@ -143,7 +141,7 @@ extern "C" {
#define CYBSP_SWO_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_SWO_HAL_DIR CYHAL_GPIO_DIR_OUTPUT
#define CYBSP_SWO_HAL_DIR CYHAL_GPIO_DIR_OUTPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_SWO_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
@ -170,7 +168,7 @@ extern "C" {
#define CYBSP_SWDIO_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_SWDIO_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL
#define CYBSP_SWDIO_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_SWDIO_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLUP
@ -197,7 +195,7 @@ extern "C" {
#define CYBSP_SWDCK_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_SWDCK_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL
#define CYBSP_SWDCK_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_SWDCK_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLDOWN
@ -224,7 +222,7 @@ extern "C" {
#define CYBSP_CINA_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CINA_HAL_DIR CYHAL_GPIO_DIR_INPUT
#define CYBSP_CINA_HAL_DIR CYHAL_GPIO_DIR_INPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CINA_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
@ -251,7 +249,7 @@ extern "C" {
#define CYBSP_CINB_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CINB_HAL_DIR CYHAL_GPIO_DIR_INPUT
#define CYBSP_CINB_HAL_DIR CYHAL_GPIO_DIR_INPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CINB_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
@ -278,7 +276,7 @@ extern "C" {
#define CYBSP_CMOD_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CMOD_HAL_DIR CYHAL_GPIO_DIR_INPUT
#define CYBSP_CMOD_HAL_DIR CYHAL_GPIO_DIR_INPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CMOD_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
@ -305,7 +303,7 @@ extern "C" {
#define CYBSP_CSD_BTN0_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_BTN0_HAL_DIR CYHAL_GPIO_DIR_INPUT
#define CYBSP_CSD_BTN0_HAL_DIR CYHAL_GPIO_DIR_INPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_BTN0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
@ -332,7 +330,7 @@ extern "C" {
#define CYBSP_CSD_BTN1_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_BTN1_HAL_DIR CYHAL_GPIO_DIR_INPUT
#define CYBSP_CSD_BTN1_HAL_DIR CYHAL_GPIO_DIR_INPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_BTN1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
@ -359,7 +357,7 @@ extern "C" {
#define CYBSP_CSD_SLD0_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD0_HAL_DIR CYHAL_GPIO_DIR_INPUT
#define CYBSP_CSD_SLD0_HAL_DIR CYHAL_GPIO_DIR_INPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
@ -386,7 +384,7 @@ extern "C" {
#define CYBSP_CSD_SLD1_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD1_HAL_DIR CYHAL_GPIO_DIR_INPUT
#define CYBSP_CSD_SLD1_HAL_DIR CYHAL_GPIO_DIR_INPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
@ -413,7 +411,7 @@ extern "C" {
#define CYBSP_CSD_SLD2_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD2_HAL_DIR CYHAL_GPIO_DIR_INPUT
#define CYBSP_CSD_SLD2_HAL_DIR CYHAL_GPIO_DIR_INPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD2_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
@ -440,7 +438,7 @@ extern "C" {
#define CYBSP_CSD_SLD3_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD3_HAL_DIR CYHAL_GPIO_DIR_INPUT
#define CYBSP_CSD_SLD3_HAL_DIR CYHAL_GPIO_DIR_INPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD3_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
@ -467,7 +465,7 @@ extern "C" {
#define CYBSP_CSD_SLD4_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD4_HAL_DIR CYHAL_GPIO_DIR_INPUT
#define CYBSP_CSD_SLD4_HAL_DIR CYHAL_GPIO_DIR_INPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD4_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG

8
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c
View File

@ -4,13 +4,11 @@
* Description:
* Establishes all necessary connections between hardware elements.
* This file was automatically generated and should not be modified.
* Tools Package 2.2.0.1747
* psoc6pdl 1.6.0.4266
* personalities_2.0 2.0.0.0
* udd 1.2.0.370
* cfg-backend-cli: 1.2.0.1483
* Device Support Library (libs/psoc6pdl): 1.6.0.4266
*
********************************************************************************
* Copyright 2020 Cypress Semiconductor Corporation
* Copyright 2017-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");

14
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h
View File

@ -4,13 +4,11 @@
* Description:
* Establishes all necessary connections between hardware elements.
* This file was automatically generated and should not be modified.
* Tools Package 2.2.0.1747
* psoc6pdl 1.6.0.4266
* personalities_2.0 2.0.0.0
* udd 1.2.0.370
* cfg-backend-cli: 1.2.0.1483
* Device Support Library (libs/psoc6pdl): 1.6.0.4266
*
********************************************************************************
* Copyright 2020 Cypress Semiconductor Corporation
* Copyright 2017-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -38,7 +36,7 @@ void init_cycfg_routing(void);
#define init_cycfg_connectivity() init_cycfg_routing()
#define ioss_0_port_0_pin_0_ANALOG P0_0_SRSS_WCO_IN
#define ioss_0_port_0_pin_1_ANALOG P0_1_SRSS_WCO_OUT
#define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_6_pin_4_HSIOM P6_4_CPUSS_SWJ_SWO_TDO
#define ioss_0_port_6_pin_6_HSIOM P6_6_CPUSS_SWJ_SWDIO_TMS
#define ioss_0_port_6_pin_7_HSIOM P6_7_CPUSS_SWJ_SWCLK_TCLK
@ -47,11 +45,11 @@ void init_cycfg_routing(void);
#define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_AMUXB
#if defined(__cplusplus)
}

470
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c
View File

File diff suppressed because it is too large Load Diff

27
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h
View File

@ -4,13 +4,11 @@
* Description:
* System configuration
* This file was automatically generated and should not be modified.
* Tools Package 2.2.0.1747
* psoc6pdl 1.6.0.4266
* personalities_2.0 2.0.0.0
* udd 1.2.0.370
* cfg-backend-cli: 1.2.0.1483
* Device Support Library (libs/psoc6pdl): 1.6.0.4266
*
********************************************************************************
* Copyright 2020 Cypress Semiconductor Corporation
* Copyright 2017-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -51,13 +49,26 @@ extern "C" {
#define srss_0_clock_0_hfclk_0_ENABLED 1U
#define CY_CFG_SYSCLK_CLKHF0 0UL
#define CY_CFG_SYSCLK_CLKHF0_CLKPATH_NUM 0UL
#define srss_0_clock_0_hfclk_2_ENABLED 1U
#define CY_CFG_SYSCLK_CLKHF2 2UL
#define CY_CFG_SYSCLK_CLKHF2_CLKPATH_NUM 0UL
#define srss_0_clock_0_hfclk_3_ENABLED 1U
#define CY_CFG_SYSCLK_CLKHF3 3UL
#define CY_CFG_SYSCLK_CLKHF3_CLKPATH_NUM 0UL
#define srss_0_clock_0_hfclk_4_ENABLED 1U
#define CY_CFG_SYSCLK_CLKHF4 4UL
#define CY_CFG_SYSCLK_CLKHF4_CLKPATH_NUM 0UL
#define srss_0_clock_0_ilo_0_ENABLED 1U
#define srss_0_clock_0_imo_0_ENABLED 1U
#define srss_0_clock_0_lfclk_0_ENABLED 1U
#define CY_CFG_SYSCLK_CLKLF_FREQ_HZ 32768
#define CY_CFG_SYSCLK_CLKLF_SOURCE CY_SYSCLK_CLKLF_IN_WCO
#define srss_0_clock_0_pathmux_0_ENABLED 1U
#define srss_0_clock_0_pathmux_1_ENABLED 1U
#define srss_0_clock_0_pathmux_2_ENABLED 1U
#define srss_0_clock_0_periclk_0_ENABLED 1U
#define srss_0_clock_0_pll_0_ENABLED 1U
#define srss_0_clock_0_pll_1_ENABLED 1U
#define srss_0_clock_0_slowclk_0_ENABLED 1U
#define srss_0_clock_0_timerclk_0_ENABLED 1U
#define srss_0_clock_0_wco_0_ENABLED 1U
@ -81,6 +92,12 @@ extern "C" {
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj;
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj;
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj;
#endif //defined (CY_USING_HAL)
void init_cycfg_system(void);

4
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list
View File

@ -1,5 +1,5 @@
[Device=CY8C624ABZI-D44]
[Device=CYB0644ABZI-S2D44]
[Blocks]
# WIFI
# CYBSP_WIFI_SDIO

66
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/design.modus
View File

@ -1,6 +1,6 @@
<?xml version="1.0" encoding="UTF-8"?>
<Design version="12" device_library_hint_path="../../psoc6pdl/devicesupport.xml" xmlns="http://cypress.com/xsd/cydesignfile_v3">
<ToolInfo version="2.2.0.1747"/>
<Design version="12" xmlns="http://cypress.com/xsd/cydesignfile_v3">
<ToolInfo version="1.0.0"/>
<Devices>
<Device mpn="CYB0644ABZI-S2D44">
<BlockConfig>
@ -270,7 +270,7 @@
</Block>
<Block location="srss[0].clock[0].bakclk[0]">
<Personality template="mxs40bakclk" version="1.0">
<Param id="sourceClock" value="wco"/>
<Param id="sourceClock" value="lfclk"/>
</Personality>
</Block>
<Block location="srss[0].clock[0].fastclk[0]">
@ -279,12 +279,9 @@
</Personality>
</Block>
<Block location="srss[0].clock[0].fll[0]">
<Personality template="mxs40fll" version="2.0">
<Personality template="mxs40fll" version="1.0">
<Param id="configuration" value="auto"/>
<Param id="desiredFrequency" value=""/>
<Param id="multiplier" value=""/>
<Param id="reference" value=""/>
<Param id="tolerance" value=""/>
<Param id="desiredFrequency" value="100.000"/>
</Personality>
</Block>
<Block location="srss[0].clock[0].hfclk[0]">
@ -293,6 +290,24 @@
<Param id="divider" value="1"/>
</Personality>
</Block>
<Block location="srss[0].clock[0].hfclk[2]">
<Personality template="mxs40hfclk" version="1.1">
<Param id="sourceClockNumber" value="0"/>
<Param id="divider" value="2"/>
</Personality>
</Block>
<Block location="srss[0].clock[0].hfclk[3]">
<Personality template="mxs40hfclk" version="1.1">
<Param id="sourceClockNumber" value="0"/>
<Param id="divider" value="1"/>
</Personality>
</Block>
<Block location="srss[0].clock[0].hfclk[4]">
<Personality template="mxs40hfclk" version="1.1">
<Param id="sourceClockNumber" value="0"/>
<Param id="divider" value="1"/>
</Personality>
</Block>
<Block location="srss[0].clock[0].ilo[0]">
<Personality template="mxs40ilo" version="1.0">
<Param id="hibernate" value="true"/>
@ -313,9 +328,35 @@
<Param id="sourceClock" value="imo"/>
</Personality>
</Block>
<Block location="srss[0].clock[0].pathmux[1]">
<Personality template="mxs40pathmux" version="1.0">
<Param id="sourceClock" value="imo"/>
</Personality>
</Block>
<Block location="srss[0].clock[0].pathmux[2]">
<Personality template="mxs40pathmux" version="1.0">
<Param id="sourceClock" value="imo"/>
</Personality>
</Block>
<Block location="srss[0].clock[0].periclk[0]">
<Personality template="mxs40periclk" version="1.0">
<Param id="divider" value="2"/>
<Param id="divider" value="1"/>
</Personality>
</Block>
<Block location="srss[0].clock[0].pll[0]">
<Personality template="mxs40pll" version="1.0">
<Param id="lowFrequencyMode" value="false"/>
<Param id="configuration" value="auto"/>
<Param id="desiredFrequency" value="144.000"/>
<Param id="optimization" value="MinPower"/>
</Personality>
</Block>
<Block location="srss[0].clock[0].pll[1]">
<Personality template="mxs40pll" version="1.0">
<Param id="lowFrequencyMode" value="false"/>
<Param id="configuration" value="auto"/>
<Param id="desiredFrequency" value="48.000"/>
<Param id="optimization" value="MinPower"/>
</Personality>
</Block>
<Block location="srss[0].clock[0].slowclk[0]">
@ -325,7 +366,7 @@
</Block>
<Block location="srss[0].clock[0].timerclk[0]">
<Personality template="mxs40timerclk" version="1.0">
<Param id="sourceClock" value="hfclk"/>
<Param id="sourceClock" value="imo"/>
<Param id="timerDivider" value="1"/>
</Personality>
</Block>
@ -342,8 +383,8 @@
<Block location="srss[0].power[0]">
<Personality template="mxs40power" version="1.3">
<Param id="pwrMode" value="LDO_1_1"/>
<Param id="actPwrMode" value=""/>
<Param id="coreRegulator" value=""/>
<Param id="actPwrMode" value="LP"/>
<Param id="coreRegulator" value="CY_SYSPM_LDO_MODE_NORMAL"/>
<Param id="pmicEnable" value="false"/>
<Param id="backupSrc" value="VDDD"/>
<Param id="idlePwrMode" value="CY_CFG_PWR_MODE_DEEPSLEEP"/>
@ -427,5 +468,6 @@
<Netlist/>
</Device>
</Devices>
<Libraries/>
<ConfiguratorData/>
</Design>