diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c index 695711f473..7b3eac9a81 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c @@ -4,13 +4,11 @@ * Description: * Wrapper function to initialize all generated code. * This file was automatically generated and should not be modified. -* Tools Package 2.2.0.1747 -* psoc6pdl 1.6.0.4266 -* personalities_2.0 2.0.0.0 -* udd 1.2.0.370 +* cfg-backend-cli: 1.2.0.1483 +* Device Support Library (libs/psoc6pdl): 1.6.0.4266 * ******************************************************************************** -* Copyright 2020 Cypress Semiconductor Corporation +* Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h index 15b61913c6..59b32b9018 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h @@ -4,13 +4,11 @@ * Description: * Simple wrapper header containing all generated files. * This file was automatically generated and should not be modified. -* Tools Package 2.2.0.1747 -* psoc6pdl 1.6.0.4266 -* personalities_2.0 2.0.0.0 -* udd 1.2.0.370 +* cfg-backend-cli: 1.2.0.1483 +* Device Support Library (libs/psoc6pdl): 1.6.0.4266 * ******************************************************************************** -* Copyright 2020 Cypress Semiconductor Corporation +* Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp index 626fccf64d..d8d85b9715 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp @@ -1,28 +1,26 @@ -/******************************************************************************* -* File Name: cycfg.timestamp -* -* Description: -* Sentinel file for determining if generated source is up to date. -* This file was automatically generated and should not be modified. -* Tools Package 2.2.0.1747 -* psoc6pdl 1.6.0.4266 -* personalities_2.0 2.0.0.0 -* udd 1.2.0.370 -* -******************************************************************************** -* Copyright 2020 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -********************************************************************************/ - +/******************************************************************************* +* File Name: cycfg.timestamp +* +* Description: +* Sentinel file for determining if generated source is up to date. +* This file was automatically generated and should not be modified. +* cfg-backend-cli: 1.2.0.1483 +* Device Support Library (libs/psoc6pdl): 1.6.0.4266 +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c index 215e2cc2c9..c2836a6951 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c @@ -4,13 +4,11 @@ * Description: * Clock configuration * This file was automatically generated and should not be modified. -* Tools Package 2.2.0.1747 -* psoc6pdl 1.6.0.4266 -* personalities_2.0 2.0.0.0 -* udd 1.2.0.370 +* cfg-backend-cli: 1.2.0.1483 +* Device Support Library (libs/psoc6pdl): 1.6.0.4266 * ******************************************************************************** -* Copyright 2020 Cypress Semiconductor Corporation +* Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -29,7 +27,7 @@ #include "cycfg_clocks.h" #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj = + const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj = { .type = CYHAL_RSC_CLOCK, .block_num = CYBSP_CSD_CLK_DIV_HW, diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h index 8ddb17622c..f00f300b2b 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h @@ -4,13 +4,11 @@ * Description: * Clock configuration * This file was automatically generated and should not be modified. -* Tools Package 2.2.0.1747 -* psoc6pdl 1.6.0.4266 -* personalities_2.0 2.0.0.0 -* udd 1.2.0.370 +* cfg-backend-cli: 1.2.0.1483 +* Device Support Library (libs/psoc6pdl): 1.6.0.4266 * ******************************************************************************** -* Copyright 2020 Cypress Semiconductor Corporation +* Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h index ad95460701..a00457a515 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h @@ -5,13 +5,11 @@ * Contains warnings and errors that occurred while generating code for the * design. * This file was automatically generated and should not be modified. -* Tools Package 2.2.0.1747 -* psoc6pdl 1.6.0.4266 -* personalities_2.0 2.0.0.0 -* udd 1.2.0.370 +* cfg-backend-cli: 1.2.0.1483 +* Device Support Library (libs/psoc6pdl): 1.6.0.4266 * ******************************************************************************** -* Copyright 2020 Cypress Semiconductor Corporation +* Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c index 6bb59a6ef5..3800fe587d 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c @@ -4,13 +4,11 @@ * Description: * Peripheral Hardware Block configuration * This file was automatically generated and should not be modified. -* Tools Package 2.2.0.1747 -* psoc6pdl 1.6.0.4266 -* personalities_2.0 2.0.0.0 -* udd 1.2.0.370 +* cfg-backend-cli: 1.2.0.1483 +* Device Support Library (libs/psoc6pdl): 1.6.0.4266 * ******************************************************************************** -* Copyright 2020 Cypress Semiconductor Corporation +* Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -28,7 +26,7 @@ #include "cycfg_peripherals.h" -cy_stc_csd_context_t cy_csd_0_context = +cy_stc_csd_context_t cy_csd_0_context = { .lockKey = CY_CSD_NONE_KEY, }; diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h index b8992adae9..ef5c2fe9aa 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h @@ -4,13 +4,11 @@ * Description: * Peripheral Hardware Block configuration * This file was automatically generated and should not be modified. -* Tools Package 2.2.0.1747 -* psoc6pdl 1.6.0.4266 -* personalities_2.0 2.0.0.0 -* udd 1.2.0.370 +* cfg-backend-cli: 1.2.0.1483 +* Device Support Library (libs/psoc6pdl): 1.6.0.4266 * ******************************************************************************** -* Copyright 2020 Cypress Semiconductor Corporation +* Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -40,7 +38,7 @@ extern "C" { #define CYBSP_CSD_ENABLED 1U #define CY_CAPSENSE_CORE 4u #define CY_CAPSENSE_CPU_CLK 100000000u -#define CY_CAPSENSE_PERI_CLK 50000000u +#define CY_CAPSENSE_PERI_CLK 100000000u #define CY_CAPSENSE_VDDA_MV 3300u #define CY_CAPSENSE_PERI_DIV_TYPE CY_SYSCLK_DIV_8_BIT #define CY_CAPSENSE_PERI_DIV_INDEX 0u diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c index 626c508fe6..55a7f9565c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c @@ -4,13 +4,11 @@ * Description: * Pin configuration * This file was automatically generated and should not be modified. -* Tools Package 2.2.0.1747 -* psoc6pdl 1.6.0.4266 -* personalities_2.0 2.0.0.0 -* udd 1.2.0.370 +* cfg-backend-cli: 1.2.0.1483 +* Device Support Library (libs/psoc6pdl): 1.6.0.4266 * ******************************************************************************** -* Copyright 2020 Cypress Semiconductor Corporation +* Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -28,7 +26,7 @@ #include "cycfg_pins.h" -const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config = +const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -45,14 +43,14 @@ const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_WCO_IN_obj = + const cyhal_resource_inst_t CYBSP_WCO_IN_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_WCO_IN_PORT_NUM, .channel_num = CYBSP_WCO_IN_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config = +const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -69,14 +67,14 @@ const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_WCO_OUT_obj = + const cyhal_resource_inst_t CYBSP_WCO_OUT_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_WCO_OUT_PORT_NUM, .channel_num = CYBSP_WCO_OUT_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_CSD_RX_config = +const cy_stc_gpio_pin_config_t CYBSP_CSD_RX_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -93,14 +91,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_RX_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CSD_RX_obj = + const cyhal_resource_inst_t CYBSP_CSD_RX_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_CSD_RX_PORT_NUM, .channel_num = CYBSP_CSD_RX_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_SWO_config = +const cy_stc_gpio_pin_config_t CYBSP_SWO_config = { .outVal = 1, .driveMode = CY_GPIO_DM_STRONG_IN_OFF, @@ -117,14 +115,14 @@ const cy_stc_gpio_pin_config_t CYBSP_SWO_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_SWO_obj = + const cyhal_resource_inst_t CYBSP_SWO_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_SWO_PORT_NUM, .channel_num = CYBSP_SWO_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config = +const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config = { .outVal = 1, .driveMode = CY_GPIO_DM_PULLUP, @@ -141,14 +139,14 @@ const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_SWDIO_obj = + const cyhal_resource_inst_t CYBSP_SWDIO_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_SWDIO_PORT_NUM, .channel_num = CYBSP_SWDIO_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config = +const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config = { .outVal = 1, .driveMode = CY_GPIO_DM_PULLDOWN, @@ -165,14 +163,14 @@ const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_SWDCK_obj = + const cyhal_resource_inst_t CYBSP_SWDCK_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_SWDCK_PORT_NUM, .channel_num = CYBSP_SWDCK_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_CINA_config = +const cy_stc_gpio_pin_config_t CYBSP_CINA_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -189,14 +187,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CINA_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CINA_obj = + const cyhal_resource_inst_t CYBSP_CINA_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_CINA_PORT_NUM, .channel_num = CYBSP_CINA_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_CINB_config = +const cy_stc_gpio_pin_config_t CYBSP_CINB_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -213,14 +211,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CINB_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CINB_obj = + const cyhal_resource_inst_t CYBSP_CINB_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_CINB_PORT_NUM, .channel_num = CYBSP_CINB_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_CMOD_config = +const cy_stc_gpio_pin_config_t CYBSP_CMOD_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -237,14 +235,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CMOD_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CMOD_obj = + const cyhal_resource_inst_t CYBSP_CMOD_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_CMOD_PORT_NUM, .channel_num = CYBSP_CMOD_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config = +const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -261,14 +259,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CSD_BTN0_obj = + const cyhal_resource_inst_t CYBSP_CSD_BTN0_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_CSD_BTN0_PORT_NUM, .channel_num = CYBSP_CSD_BTN0_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config = +const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -285,14 +283,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CSD_BTN1_obj = + const cyhal_resource_inst_t CYBSP_CSD_BTN1_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_CSD_BTN1_PORT_NUM, .channel_num = CYBSP_CSD_BTN1_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config = +const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -309,14 +307,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CSD_SLD0_obj = + const cyhal_resource_inst_t CYBSP_CSD_SLD0_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_CSD_SLD0_PORT_NUM, .channel_num = CYBSP_CSD_SLD0_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config = +const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -333,14 +331,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CSD_SLD1_obj = + const cyhal_resource_inst_t CYBSP_CSD_SLD1_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_CSD_SLD1_PORT_NUM, .channel_num = CYBSP_CSD_SLD1_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config = +const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -357,14 +355,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CSD_SLD2_obj = + const cyhal_resource_inst_t CYBSP_CSD_SLD2_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_CSD_SLD2_PORT_NUM, .channel_num = CYBSP_CSD_SLD2_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config = +const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -381,14 +379,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CSD_SLD3_obj = + const cyhal_resource_inst_t CYBSP_CSD_SLD3_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_CSD_SLD3_PORT_NUM, .channel_num = CYBSP_CSD_SLD3_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config = +const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -405,7 +403,7 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CSD_SLD4_obj = + const cyhal_resource_inst_t CYBSP_CSD_SLD4_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_CSD_SLD4_PORT_NUM, diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h index d86a3045ae..3d96f034f5 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h @@ -4,13 +4,11 @@ * Description: * Pin configuration * This file was automatically generated and should not be modified. -* Tools Package 2.2.0.1747 -* psoc6pdl 1.6.0.4266 -* personalities_2.0 2.0.0.0 -* udd 1.2.0.370 +* cfg-backend-cli: 1.2.0.1483 +* Device Support Library (libs/psoc6pdl): 1.6.0.4266 * ******************************************************************************** -* Copyright 2020 Cypress Semiconductor Corporation +* Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -62,7 +60,7 @@ extern "C" { #define CYBSP_WCO_IN_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_WCO_IN_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_WCO_IN_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_WCO_IN_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG @@ -89,7 +87,7 @@ extern "C" { #define CYBSP_WCO_OUT_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_WCO_OUT_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_WCO_OUT_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_WCO_OUT_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG @@ -116,7 +114,7 @@ extern "C" { #define CYBSP_CSD_RX_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_CSD_RX_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CSD_RX_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_RX_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG @@ -143,7 +141,7 @@ extern "C" { #define CYBSP_SWO_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_SWO_HAL_DIR CYHAL_GPIO_DIR_OUTPUT + #define CYBSP_SWO_HAL_DIR CYHAL_GPIO_DIR_OUTPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_SWO_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG @@ -170,7 +168,7 @@ extern "C" { #define CYBSP_SWDIO_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_SWDIO_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL + #define CYBSP_SWDIO_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_SWDIO_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLUP @@ -197,7 +195,7 @@ extern "C" { #define CYBSP_SWDCK_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_SWDCK_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL + #define CYBSP_SWDCK_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_SWDCK_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLDOWN @@ -224,7 +222,7 @@ extern "C" { #define CYBSP_CINA_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_CINA_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CINA_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CINA_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG @@ -251,7 +249,7 @@ extern "C" { #define CYBSP_CINB_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_CINB_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CINB_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CINB_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG @@ -278,7 +276,7 @@ extern "C" { #define CYBSP_CMOD_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_CMOD_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CMOD_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CMOD_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG @@ -305,7 +303,7 @@ extern "C" { #define CYBSP_CSD_BTN0_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_CSD_BTN0_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CSD_BTN0_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_BTN0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG @@ -332,7 +330,7 @@ extern "C" { #define CYBSP_CSD_BTN1_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_CSD_BTN1_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CSD_BTN1_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_BTN1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG @@ -359,7 +357,7 @@ extern "C" { #define CYBSP_CSD_SLD0_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_CSD_SLD0_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CSD_SLD0_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_SLD0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG @@ -386,7 +384,7 @@ extern "C" { #define CYBSP_CSD_SLD1_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_CSD_SLD1_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CSD_SLD1_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_SLD1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG @@ -413,7 +411,7 @@ extern "C" { #define CYBSP_CSD_SLD2_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_CSD_SLD2_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CSD_SLD2_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_SLD2_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG @@ -440,7 +438,7 @@ extern "C" { #define CYBSP_CSD_SLD3_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_CSD_SLD3_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CSD_SLD3_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_SLD3_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG @@ -467,7 +465,7 @@ extern "C" { #define CYBSP_CSD_SLD4_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_CSD_SLD4_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CSD_SLD4_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_SLD4_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c index b18e1c2817..e0ba904bb8 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c @@ -4,13 +4,11 @@ * Description: * Establishes all necessary connections between hardware elements. * This file was automatically generated and should not be modified. -* Tools Package 2.2.0.1747 -* psoc6pdl 1.6.0.4266 -* personalities_2.0 2.0.0.0 -* udd 1.2.0.370 +* cfg-backend-cli: 1.2.0.1483 +* Device Support Library (libs/psoc6pdl): 1.6.0.4266 * ******************************************************************************** -* Copyright 2020 Cypress Semiconductor Corporation +* Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h index ce4cdadd30..e0cfe03b1c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h @@ -4,13 +4,11 @@ * Description: * Establishes all necessary connections between hardware elements. * This file was automatically generated and should not be modified. -* Tools Package 2.2.0.1747 -* psoc6pdl 1.6.0.4266 -* personalities_2.0 2.0.0.0 -* udd 1.2.0.370 +* cfg-backend-cli: 1.2.0.1483 +* Device Support Library (libs/psoc6pdl): 1.6.0.4266 * ******************************************************************************** -* Copyright 2020 Cypress Semiconductor Corporation +* Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -38,7 +36,7 @@ void init_cycfg_routing(void); #define init_cycfg_connectivity() init_cycfg_routing() #define ioss_0_port_0_pin_0_ANALOG P0_0_SRSS_WCO_IN #define ioss_0_port_0_pin_1_ANALOG P0_1_SRSS_WCO_OUT -#define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_AMUXA +#define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_AMUXB #define ioss_0_port_6_pin_4_HSIOM P6_4_CPUSS_SWJ_SWO_TDO #define ioss_0_port_6_pin_6_HSIOM P6_6_CPUSS_SWJ_SWDIO_TMS #define ioss_0_port_6_pin_7_HSIOM P6_7_CPUSS_SWJ_SWCLK_TCLK @@ -47,11 +45,11 @@ void init_cycfg_routing(void); #define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_AMUXA #define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_AMUXB #define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_AMUXB -#define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_AMUXA +#define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_AMUXB #define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_AMUXB #define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_AMUXB #define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_AMUXA -#define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_AMUXA +#define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_AMUXB #if defined(__cplusplus) } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c index 7f66e9a2a8..d3aa57ca05 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c @@ -4,13 +4,11 @@ * Description: * System configuration * This file was automatically generated and should not be modified. -* Tools Package 2.2.0.1747 -* psoc6pdl 1.6.0.4266 -* personalities_2.0 2.0.0.0 -* udd 1.2.0.370 +* cfg-backend-cli: 1.2.0.1483 +* Device Support Library (libs/psoc6pdl): 1.6.0.4266 * ******************************************************************************** -* Copyright 2020 Cypress Semiconductor Corporation +* Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -34,7 +32,7 @@ #define CY_CFG_SYSCLK_FLL_ERROR 4 #define CY_CFG_SYSCLK_WCO_ERROR 5 #define CY_CFG_SYSCLK_CLKBAK_ENABLED 1 -#define CY_CFG_SYSCLK_CLKBAK_SOURCE CY_SYSCLK_BAK_IN_WCO +#define CY_CFG_SYSCLK_CLKBAK_SOURCE CY_SYSCLK_BAK_IN_CLKLF #define CY_CFG_SYSCLK_CLKFAST_ENABLED 1 #define CY_CFG_SYSCLK_CLKFAST_DIVIDER 0 #define CY_CFG_SYSCLK_FLL_ENABLED 1 @@ -45,14 +43,26 @@ #define CY_CFG_SYSCLK_FLL_LOCK_TOLERANCE 10U #define CY_CFG_SYSCLK_FLL_IGAIN 9U #define CY_CFG_SYSCLK_FLL_PGAIN 5U -#define CY_CFG_SYSCLK_FLL_SETTLING_COUNT 8U +#define CY_CFG_SYSCLK_FLL_SETTLING_COUNT 8 #define CY_CFG_SYSCLK_FLL_OUTPUT_MODE CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT -#define CY_CFG_SYSCLK_FLL_CCO_FREQ 355U +#define CY_CFG_SYSCLK_FLL_CCO_FREQ 355 #define CY_CFG_SYSCLK_FLL_OUT_FREQ 100000000 #define CY_CFG_SYSCLK_CLKHF0_ENABLED 1 #define CY_CFG_SYSCLK_CLKHF0_DIVIDER CY_SYSCLK_CLKHF_NO_DIVIDE #define CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ 100UL #define CY_CFG_SYSCLK_CLKHF0_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0 +#define CY_CFG_SYSCLK_CLKHF2_ENABLED 1 +#define CY_CFG_SYSCLK_CLKHF2_DIVIDER CY_SYSCLK_CLKHF_DIVIDE_BY_2 +#define CY_CFG_SYSCLK_CLKHF2_FREQ_MHZ 50UL +#define CY_CFG_SYSCLK_CLKHF2_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0 +#define CY_CFG_SYSCLK_CLKHF3_ENABLED 1 +#define CY_CFG_SYSCLK_CLKHF3_DIVIDER CY_SYSCLK_CLKHF_NO_DIVIDE +#define CY_CFG_SYSCLK_CLKHF3_FREQ_MHZ 100UL +#define CY_CFG_SYSCLK_CLKHF3_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0 +#define CY_CFG_SYSCLK_CLKHF4_ENABLED 1 +#define CY_CFG_SYSCLK_CLKHF4_DIVIDER CY_SYSCLK_CLKHF_NO_DIVIDE +#define CY_CFG_SYSCLK_CLKHF4_FREQ_MHZ 100UL +#define CY_CFG_SYSCLK_CLKHF4_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0 #define CY_CFG_SYSCLK_ILO_ENABLED 1 #define CY_CFG_SYSCLK_ILO_HIBERNATE true #define CY_CFG_SYSCLK_IMO_ENABLED 1 @@ -60,12 +70,32 @@ #define CY_CFG_SYSCLK_CLKPATH0_ENABLED 1 #define CY_CFG_SYSCLK_CLKPATH0_SOURCE CY_SYSCLK_CLKPATH_IN_IMO #define CY_CFG_SYSCLK_CLKPATH0_SOURCE_NUM 0UL +#define CY_CFG_SYSCLK_CLKPATH1_ENABLED 1 +#define CY_CFG_SYSCLK_CLKPATH1_SOURCE CY_SYSCLK_CLKPATH_IN_IMO +#define CY_CFG_SYSCLK_CLKPATH1_SOURCE_NUM 0UL +#define CY_CFG_SYSCLK_CLKPATH2_ENABLED 1 +#define CY_CFG_SYSCLK_CLKPATH2_SOURCE CY_SYSCLK_CLKPATH_IN_IMO +#define CY_CFG_SYSCLK_CLKPATH2_SOURCE_NUM 0UL #define CY_CFG_SYSCLK_CLKPERI_ENABLED 1 -#define CY_CFG_SYSCLK_CLKPERI_DIVIDER 1 +#define CY_CFG_SYSCLK_CLKPERI_DIVIDER 0 +#define CY_CFG_SYSCLK_PLL0_ENABLED 1 +#define CY_CFG_SYSCLK_PLL0_FEEDBACK_DIV 36 +#define CY_CFG_SYSCLK_PLL0_REFERENCE_DIV 1 +#define CY_CFG_SYSCLK_PLL0_OUTPUT_DIV 2 +#define CY_CFG_SYSCLK_PLL0_LF_MODE false +#define CY_CFG_SYSCLK_PLL0_OUTPUT_MODE CY_SYSCLK_FLLPLL_OUTPUT_AUTO +#define CY_CFG_SYSCLK_PLL0_OUTPUT_FREQ 144000000 +#define CY_CFG_SYSCLK_PLL1_ENABLED 1 +#define CY_CFG_SYSCLK_PLL1_FEEDBACK_DIV 30 +#define CY_CFG_SYSCLK_PLL1_REFERENCE_DIV 1 +#define CY_CFG_SYSCLK_PLL1_OUTPUT_DIV 5 +#define CY_CFG_SYSCLK_PLL1_LF_MODE false +#define CY_CFG_SYSCLK_PLL1_OUTPUT_MODE CY_SYSCLK_FLLPLL_OUTPUT_AUTO +#define CY_CFG_SYSCLK_PLL1_OUTPUT_FREQ 48000000 #define CY_CFG_SYSCLK_CLKSLOW_ENABLED 1 #define CY_CFG_SYSCLK_CLKSLOW_DIVIDER 0 #define CY_CFG_SYSCLK_CLKTIMER_ENABLED 1 -#define CY_CFG_SYSCLK_CLKTIMER_SOURCE CY_SYSCLK_CLKTIMER_IN_HF0_NODIV +#define CY_CFG_SYSCLK_CLKTIMER_SOURCE CY_SYSCLK_CLKTIMER_IN_IMO #define CY_CFG_SYSCLK_CLKTIMER_DIVIDER 0U #define CY_CFG_SYSCLK_WCO_ENABLED 1 #define CY_CFG_SYSCLK_WCO_IN_PRT GPIO_PRT0 @@ -85,7 +115,7 @@ static cy_stc_pra_system_config_t srss_0_clock_0_secureConfig; #endif //defined (CY_DEVICE_SECURE) && (CY_CPU_CORTEX_M4) #if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) - static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig = + static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig = { .fllMult = 500U, .refDiv = 20U, @@ -100,13 +130,49 @@ }; #endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) #if defined (CY_USING_HAL) - const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj = + const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj = { .type = CYHAL_RSC_CLKPATH, .block_num = 0U, .channel_num = 0U, }; #endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj = + { + .type = CYHAL_RSC_CLKPATH, + .block_num = 1U, + .channel_num = 0U, + }; +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj = + { + .type = CYHAL_RSC_CLKPATH, + .block_num = 2U, + .channel_num = 0U, + }; +#endif //defined (CY_USING_HAL) +#if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) + static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_0_pllConfig = + { + .feedbackDiv = 36, + .referenceDiv = 1, + .outputDiv = 2, + .lfMode = false, + .outputMode = CY_SYSCLK_FLLPLL_OUTPUT_AUTO, + }; +#endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) +#if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) + static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_1_pllConfig = + { + .feedbackDiv = 30, + .referenceDiv = 1, + .outputDiv = 5, + .lfMode = false, + .outputMode = CY_SYSCLK_FLLPLL_OUTPUT_AUTO, + }; +#endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) __WEAK void cycfg_ClockStartupError(uint32_t error) { @@ -119,467 +185,467 @@ __WEAK void cycfg_ClockStartupError(uint32_t error) #ifdef CY_CFG_PWR_ENABLED secure_config->powerEnable = CY_CFG_PWR_ENABLED; #endif /* CY_CFG_PWR_ENABLED */ - + #ifdef CY_CFG_PWR_USING_LDO secure_config->ldoEnable = CY_CFG_PWR_USING_LDO; #endif /* CY_CFG_PWR_USING_LDO */ - + #ifdef CY_CFG_PWR_USING_PMIC secure_config->pmicEnable = CY_CFG_PWR_USING_PMIC; #endif /* CY_CFG_PWR_USING_PMIC */ - + #ifdef CY_CFG_PWR_VBACKUP_USING_VDDD secure_config->vBackupVDDDEnable = CY_CFG_PWR_VBACKUP_USING_VDDD; #endif /* CY_CFG_PWR_VBACKUP_USING_VDDD */ - + #ifdef CY_CFG_PWR_USING_ULP secure_config->ulpEnable = CY_CFG_PWR_USING_ULP; #endif /* CY_CFG_PWR_USING_ULP */ - + #ifdef CY_CFG_SYSCLK_ECO_ENABLED secure_config->ecoEnable = CY_CFG_SYSCLK_ECO_ENABLED; #endif /* CY_CFG_SYSCLK_ECO_ENABLED */ - + #ifdef CY_CFG_SYSCLK_EXTCLK_ENABLED secure_config->extClkEnable = CY_CFG_SYSCLK_EXTCLK_ENABLED; #endif /* CY_CFG_SYSCLK_EXTCLK_ENABLED */ - + #ifdef CY_CFG_SYSCLK_ILO_ENABLED secure_config->iloEnable = CY_CFG_SYSCLK_ILO_ENABLED; #endif /* CY_CFG_SYSCLK_ILO_ENABLED */ - + #ifdef CY_CFG_SYSCLK_WCO_ENABLED secure_config->wcoEnable = CY_CFG_SYSCLK_WCO_ENABLED; #endif /* CY_CFG_SYSCLK_WCO_ENABLED */ - + #ifdef CY_CFG_SYSCLK_FLL_ENABLED secure_config->fllEnable = CY_CFG_SYSCLK_FLL_ENABLED; #endif /* CY_CFG_SYSCLK_FLL_ENABLED */ - + #ifdef CY_CFG_SYSCLK_PLL0_ENABLED secure_config->pll0Enable = CY_CFG_SYSCLK_PLL0_ENABLED; #endif /* CY_CFG_SYSCLK_PLL0_ENABLED */ - + #ifdef CY_CFG_SYSCLK_PLL1_ENABLED secure_config->pll1Enable = CY_CFG_SYSCLK_PLL1_ENABLED; #endif /* CY_CFG_SYSCLK_PLL1_ENABLED */ - + #ifdef CY_CFG_SYSCLK_CLKPATH0_ENABLED secure_config->path0Enable = CY_CFG_SYSCLK_CLKPATH0_ENABLED; #endif /* CY_CFG_SYSCLK_CLKPATH0_ENABLED */ - + #ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED secure_config->path1Enable = CY_CFG_SYSCLK_CLKPATH1_ENABLED; #endif /* CY_CFG_SYSCLK_CLKPATH1_ENABLED */ - + #ifdef CY_CFG_SYSCLK_CLKPATH2_ENABLED secure_config->path2Enable = CY_CFG_SYSCLK_CLKPATH2_ENABLED; #endif /* CY_CFG_SYSCLK_CLKPATH2_ENABLED */ - + #ifdef CY_CFG_SYSCLK_CLKPATH3_ENABLED secure_config->path3Enable = CY_CFG_SYSCLK_CLKPATH3_ENABLED; #endif /* CY_CFG_SYSCLK_CLKPATH3_ENABLED */ - + #ifdef CY_CFG_SYSCLK_CLKPATH4_ENABLED secure_config->path4Enable = CY_CFG_SYSCLK_CLKPATH4_ENABLED; #endif /* CY_CFG_SYSCLK_CLKPATH4_ENABLED */ - + #ifdef CY_CFG_SYSCLK_CLKPATH5_ENABLED secure_config->path5Enable = CY_CFG_SYSCLK_CLKPATH5_ENABLED; #endif /* CY_CFG_SYSCLK_CLKPATH5_ENABLED */ - + #ifdef CY_CFG_SYSCLK_CLKFAST_ENABLED secure_config->clkFastEnable = CY_CFG_SYSCLK_CLKFAST_ENABLED; #endif /* CY_CFG_SYSCLK_CLKFAST_ENABLED */ - + #ifdef CY_CFG_SYSCLK_CLKPERI_ENABLED secure_config->clkPeriEnable = CY_CFG_SYSCLK_CLKPERI_ENABLED; #endif /* CY_CFG_SYSCLK_CLKPERI_ENABLED */ - + #ifdef CY_CFG_SYSCLK_CLKSLOW_ENABLED secure_config->clkSlowEnable = CY_CFG_SYSCLK_CLKSLOW_ENABLED; #endif /* CY_CFG_SYSCLK_CLKSLOW_ENABLED */ - + #ifdef CY_CFG_SYSCLK_CLKHF0_ENABLED secure_config->clkHF0Enable = CY_CFG_SYSCLK_CLKHF0_ENABLED; #endif /* CY_CFG_SYSCLK_CLKHF0_ENABLED */ - + #ifdef CY_CFG_SYSCLK_CLKHF1_ENABLED secure_config->clkHF1Enable = CY_CFG_SYSCLK_CLKHF1_ENABLED; #endif /* CY_CFG_SYSCLK_CLKHF1_ENABLED */ - + #ifdef CY_CFG_SYSCLK_CLKHF2_ENABLED secure_config->clkHF2Enable = CY_CFG_SYSCLK_CLKHF2_ENABLED; #endif /* CY_CFG_SYSCLK_CLKHF2_ENABLED */ - + #ifdef CY_CFG_SYSCLK_CLKHF3_ENABLED secure_config->clkHF3Enable = CY_CFG_SYSCLK_CLKHF3_ENABLED; #endif /* CY_CFG_SYSCLK_CLKHF3_ENABLED */ - + #ifdef CY_CFG_SYSCLK_CLKHF4_ENABLED secure_config->clkHF4Enable = CY_CFG_SYSCLK_CLKHF4_ENABLED; #endif /* CY_CFG_SYSCLK_CLKHF4_ENABLED */ - + #ifdef CY_CFG_SYSCLK_CLKHF5_ENABLED secure_config->clkHF5Enable = CY_CFG_SYSCLK_CLKHF5_ENABLED; #endif /* CY_CFG_SYSCLK_CLKHF5_ENABLED */ - + #ifdef CY_CFG_SYSCLK_CLKPUMP_ENABLED secure_config->clkPumpEnable = CY_CFG_SYSCLK_CLKPUMP_ENABLED; #endif /* CY_CFG_SYSCLK_CLKPUMP_ENABLED */ - + #ifdef CY_CFG_SYSCLK_CLKLF_ENABLED secure_config->clkLFEnable = CY_CFG_SYSCLK_CLKLF_ENABLED; #endif /* CY_CFG_SYSCLK_CLKLF_ENABLED */ - + #ifdef CY_CFG_SYSCLK_CLKBAK_ENABLED secure_config->clkBakEnable = CY_CFG_SYSCLK_CLKBAK_ENABLED; #endif /* CY_CFG_SYSCLK_CLKBAK_ENABLED */ - + #ifdef CY_CFG_SYSCLK_CLKTIMER_ENABLED secure_config->clkTimerEnable = CY_CFG_SYSCLK_CLKTIMER_ENABLED; #endif /* CY_CFG_SYSCLK_CLKTIMER_ENABLED */ - + #ifdef CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED - #error Configuration Error : ALT SYSTICK cannot be enabled for Secure devices. + #error Configuration Error : ALT SYSTICK cannot be enabled for Secure devices. #endif /* CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED */ - + #ifdef CY_CFG_SYSCLK_PILO_ENABLED secure_config->piloEnable = CY_CFG_SYSCLK_PILO_ENABLED; #endif /* CY_CFG_SYSCLK_PILO_ENABLED */ - + #ifdef CY_CFG_SYSCLK_ALTHF_ENABLED secure_config->clkAltHfEnable = CY_CFG_SYSCLK_ALTHF_ENABLED; #endif /* CY_CFG_SYSCLK_ALTHF_ENABLED */ - + #ifdef CY_CFG_PWR_LDO_VOLTAGE secure_config->ldoVoltage = CY_CFG_PWR_LDO_VOLTAGE; #endif /* CY_CFG_PWR_LDO_VOLTAGE */ - + #ifdef CY_CFG_PWR_REGULATOR_MODE_MIN secure_config->pwrCurrentModeMin = CY_CFG_PWR_REGULATOR_MODE_MIN; #endif /* CY_CFG_PWR_REGULATOR_MODE_MIN */ - + #ifdef CY_CFG_PWR_BUCK_VOLTAGE secure_config->buckVoltage = CY_CFG_PWR_BUCK_VOLTAGE; #endif /* CY_CFG_PWR_BUCK_VOLTAGE */ - + #ifdef CY_CFG_SYSCLK_ECO_FREQ secure_config->ecoFreqHz = CY_CFG_SYSCLK_ECO_FREQ; #endif /* CY_CFG_SYSCLK_ECO_FREQ */ - + #ifdef CY_CFG_SYSCLK_ECO_CLOAD secure_config->ecoLoad = CY_CFG_SYSCLK_ECO_CLOAD; #endif /* CY_CFG_SYSCLK_ECO_CLOAD */ - + #ifdef CY_CFG_SYSCLK_ECO_ESR secure_config->ecoEsr = CY_CFG_SYSCLK_ECO_ESR; #endif /* CY_CFG_SYSCLK_ECO_ESR */ - + #ifdef CY_CFG_SYSCLK_ECO_DRIVE_LEVEL secure_config->ecoDriveLevel = CY_CFG_SYSCLK_ECO_DRIVE_LEVEL; #endif /* CY_CFG_SYSCLK_ECO_DRIVE_LEVEL */ - + #ifdef CY_CFG_SYSCLK_ECO_GPIO_IN_PRT secure_config->ecoInPort = CY_CFG_SYSCLK_ECO_GPIO_IN_PRT; #endif /* CY_CFG_SYSCLK_ECO_GPIO_IN_PRT */ - + #ifdef CY_CFG_SYSCLK_ECO_GPIO_OUT_PRT secure_config->ecoOutPort = CY_CFG_SYSCLK_ECO_GPIO_OUT_PRT; #endif /* CY_CFG_SYSCLK_ECO_GPIO_OUT_PRT */ - + #ifdef CY_CFG_SYSCLK_ECO_GPIO_IN_PIN secure_config->ecoInPinNum = CY_CFG_SYSCLK_ECO_GPIO_IN_PIN; #endif /* CY_CFG_SYSCLK_ECO_GPIO_IN_PIN */ - + #ifdef CY_CFG_SYSCLK_ECO_GPIO_OUT_PIN secure_config->ecoOutPinNum = CY_CFG_SYSCLK_ECO_GPIO_OUT_PIN; #endif /* CY_CFG_SYSCLK_ECO_GPIO_OUT_PIN */ - + #ifdef CY_CFG_SYSCLK_EXTCLK_FREQ secure_config->extClkFreqHz = CY_CFG_SYSCLK_EXTCLK_FREQ; #endif /* CY_CFG_SYSCLK_EXTCLK_FREQ */ - + #ifdef CY_CFG_SYSCLK_EXTCLK_GPIO_PRT secure_config->extClkPort = CY_CFG_SYSCLK_EXTCLK_GPIO_PRT; #endif /* CY_CFG_SYSCLK_EXTCLK_GPIO_PRT */ - + #ifdef CY_CFG_SYSCLK_EXTCLK_GPIO_PIN secure_config->extClkPinNum = CY_CFG_SYSCLK_EXTCLK_GPIO_PIN; #endif /* CY_CFG_SYSCLK_EXTCLK_GPIO_PIN */ - + #ifdef CY_CFG_SYSCLK_EXTCLK_GPIO_HSIOM secure_config->extClkHsiom = CY_CFG_SYSCLK_EXTCLK_GPIO_HSIOM; #endif /* CY_CFG_SYSCLK_EXTCLK_GPIO_HSIOM */ - + #ifdef CY_CFG_SYSCLK_ILO_HIBERNATE secure_config->iloHibernateON = CY_CFG_SYSCLK_ILO_HIBERNATE; #endif /* CY_CFG_SYSCLK_ILO_HIBERNATE */ - + #ifdef CY_CFG_SYSCLK_WCO_BYPASS secure_config->bypassEnable = CY_CFG_SYSCLK_WCO_BYPASS; #endif /* CY_CFG_SYSCLK_WCO_BYPASS */ - + #ifdef CY_CFG_SYSCLK_WCO_IN_PRT secure_config->wcoInPort = CY_CFG_SYSCLK_WCO_IN_PRT; #endif /* CY_CFG_SYSCLK_WCO_IN_PRT */ - + #ifdef CY_CFG_SYSCLK_WCO_OUT_PRT secure_config->wcoOutPort = CY_CFG_SYSCLK_WCO_OUT_PRT; #endif /* CY_CFG_SYSCLK_WCO_OUT_PRT */ - + #ifdef CY_CFG_SYSCLK_WCO_IN_PIN secure_config->wcoInPinNum = CY_CFG_SYSCLK_WCO_IN_PIN; #endif /* CY_CFG_SYSCLK_WCO_IN_PIN */ - + #ifdef CY_CFG_SYSCLK_WCO_OUT_PIN secure_config->wcoOutPinNum = CY_CFG_SYSCLK_WCO_OUT_PIN; #endif /* CY_CFG_SYSCLK_WCO_OUT_PIN */ - + #ifdef CY_CFG_SYSCLK_FLL_OUT_FREQ secure_config->fllOutFreqHz = CY_CFG_SYSCLK_FLL_OUT_FREQ; #endif /* CY_CFG_SYSCLK_FLL_OUT_FREQ */ - + #ifdef CY_CFG_SYSCLK_FLL_MULT secure_config->fllMult = CY_CFG_SYSCLK_FLL_MULT; #endif /* CY_CFG_SYSCLK_FLL_MULT */ - + #ifdef CY_CFG_SYSCLK_FLL_REFDIV secure_config->fllRefDiv = CY_CFG_SYSCLK_FLL_REFDIV; #endif /* CY_CFG_SYSCLK_FLL_REFDIV */ - + #ifdef CY_CFG_SYSCLK_FLL_CCO_RANGE secure_config->fllCcoRange = CY_CFG_SYSCLK_FLL_CCO_RANGE; #endif /* CY_CFG_SYSCLK_FLL_CCO_RANGE */ - + #ifdef CY_CFG_SYSCLK_FLL_ENABLE_OUTDIV secure_config->enableOutputDiv = CY_CFG_SYSCLK_FLL_ENABLE_OUTDIV; #endif /* CY_CFG_SYSCLK_FLL_ENABLE_OUTDIV */ - + #ifdef CY_CFG_SYSCLK_FLL_LOCK_TOLERANCE secure_config->lockTolerance = CY_CFG_SYSCLK_FLL_LOCK_TOLERANCE; #endif /* CY_CFG_SYSCLK_FLL_LOCK_TOLERANCE */ - + #ifdef CY_CFG_SYSCLK_FLL_IGAIN secure_config->igain = CY_CFG_SYSCLK_FLL_IGAIN; #endif /* CY_CFG_SYSCLK_FLL_IGAIN */ - + #ifdef CY_CFG_SYSCLK_FLL_PGAIN secure_config->pgain = CY_CFG_SYSCLK_FLL_PGAIN; #endif /* CY_CFG_SYSCLK_FLL_PGAIN */ - + #ifdef CY_CFG_SYSCLK_FLL_SETTLING_COUNT secure_config->settlingCount = CY_CFG_SYSCLK_FLL_SETTLING_COUNT; #endif /* CY_CFG_SYSCLK_FLL_SETTLING_COUNT */ - + #ifdef CY_CFG_SYSCLK_FLL_OUTPUT_MODE secure_config->outputMode = CY_CFG_SYSCLK_FLL_OUTPUT_MODE; #endif /* CY_CFG_SYSCLK_FLL_OUTPUT_MODE */ - + #ifdef CY_CFG_SYSCLK_FLL_CCO_FREQ secure_config->ccoFreq = CY_CFG_SYSCLK_FLL_CCO_FREQ; #endif /* CY_CFG_SYSCLK_FLL_CCO_FREQ */ - + #ifdef CY_CFG_SYSCLK_PLL0_FEEDBACK_DIV secure_config->pll0FeedbackDiv = CY_CFG_SYSCLK_PLL0_FEEDBACK_DIV; #endif /* CY_CFG_SYSCLK_PLL0_FEEDBACK_DIV */ - + #ifdef CY_CFG_SYSCLK_PLL0_REFERENCE_DIV secure_config->pll0ReferenceDiv = CY_CFG_SYSCLK_PLL0_REFERENCE_DIV; #endif /* CY_CFG_SYSCLK_PLL0_REFERENCE_DIV */ - + #ifdef CY_CFG_SYSCLK_PLL0_OUTPUT_DIV secure_config->pll0OutputDiv = CY_CFG_SYSCLK_PLL0_OUTPUT_DIV; #endif /* CY_CFG_SYSCLK_PLL0_OUTPUT_DIV */ - + #ifdef CY_CFG_SYSCLK_PLL0_LF_MODE secure_config->pll0LfMode = CY_CFG_SYSCLK_PLL0_LF_MODE; #endif /* CY_CFG_SYSCLK_PLL0_LF_MODE */ - + #ifdef CY_CFG_SYSCLK_PLL0_OUTPUT_MODE secure_config->pll0OutputMode = CY_CFG_SYSCLK_PLL0_OUTPUT_MODE; #endif /* CY_CFG_SYSCLK_PLL0_OUTPUT_MODE */ - + #ifdef CY_CFG_SYSCLK_PLL0_OUTPUT_FREQ secure_config->pll0OutFreqHz = CY_CFG_SYSCLK_PLL0_OUTPUT_FREQ; #endif /* CY_CFG_SYSCLK_PLL0_OUTPUT_FREQ */ - + #ifdef CY_CFG_SYSCLK_PLL1_FEEDBACK_DIV secure_config->pll1FeedbackDiv = CY_CFG_SYSCLK_PLL1_FEEDBACK_DIV; #endif /* CY_CFG_SYSCLK_PLL1_FEEDBACK_DIV */ - + #ifdef CY_CFG_SYSCLK_PLL1_REFERENCE_DIV secure_config->pll1ReferenceDiv = CY_CFG_SYSCLK_PLL1_REFERENCE_DIV; #endif /* CY_CFG_SYSCLK_PLL1_REFERENCE_DIV */ - + #ifdef CY_CFG_SYSCLK_PLL1_OUTPUT_DIV secure_config->pll1OutputDiv = CY_CFG_SYSCLK_PLL1_OUTPUT_DIV; #endif /* CY_CFG_SYSCLK_PLL1_OUTPUT_DIV */ - + #ifdef CY_CFG_SYSCLK_PLL1_LF_MODE secure_config->pll1LfMode = CY_CFG_SYSCLK_PLL1_LF_MODE; #endif /* CY_CFG_SYSCLK_PLL1_LF_MODE */ - + #ifdef CY_CFG_SYSCLK_PLL1_OUTPUT_MODE secure_config->pll1OutputMode = CY_CFG_SYSCLK_PLL1_OUTPUT_MODE; #endif /* CY_CFG_SYSCLK_PLL1_OUTPUT_MODE */ - + #ifdef CY_CFG_SYSCLK_PLL1_OUTPUT_FREQ secure_config->pll1OutFreqHz = CY_CFG_SYSCLK_PLL1_OUTPUT_FREQ; #endif /* CY_CFG_SYSCLK_PLL1_OUTPUT_FREQ */ - + #ifdef CY_CFG_SYSCLK_CLKPATH0_SOURCE secure_config->path0Src = CY_CFG_SYSCLK_CLKPATH0_SOURCE; #endif /* CY_CFG_SYSCLK_CLKPATH0_SOURCE */ - + #ifdef CY_CFG_SYSCLK_CLKPATH1_SOURCE secure_config->path1Src = CY_CFG_SYSCLK_CLKPATH1_SOURCE; #endif /* CY_CFG_SYSCLK_CLKPATH1_SOURCE */ - + #ifdef CY_CFG_SYSCLK_CLKPATH2_SOURCE secure_config->path2Src = CY_CFG_SYSCLK_CLKPATH2_SOURCE; #endif /* CY_CFG_SYSCLK_CLKPATH2_SOURCE */ - + #ifdef CY_CFG_SYSCLK_CLKPATH3_SOURCE secure_config->path3Src = CY_CFG_SYSCLK_CLKPATH3_SOURCE; #endif /* CY_CFG_SYSCLK_CLKPATH3_SOURCE */ - + #ifdef CY_CFG_SYSCLK_CLKPATH4_SOURCE secure_config->path4Src = CY_CFG_SYSCLK_CLKPATH4_SOURCE; #endif /* CY_CFG_SYSCLK_CLKPATH4_SOURCE */ - + #ifdef CY_CFG_SYSCLK_CLKPATH5_SOURCE secure_config->path5Src = CY_CFG_SYSCLK_CLKPATH5_SOURCE; #endif /* CY_CFG_SYSCLK_CLKPATH5_SOURCE */ - + #ifdef CY_CFG_SYSCLK_CLKFAST_DIVIDER secure_config->clkFastDiv = CY_CFG_SYSCLK_CLKFAST_DIVIDER; #endif /* CY_CFG_SYSCLK_CLKFAST_DIVIDER */ - + #ifdef CY_CFG_SYSCLK_CLKPERI_DIVIDER secure_config->clkPeriDiv = CY_CFG_SYSCLK_CLKPERI_DIVIDER; #endif /* CY_CFG_SYSCLK_CLKPERI_DIVIDER */ - + #ifdef CY_CFG_SYSCLK_CLKSLOW_DIVIDER secure_config->clkSlowDiv = CY_CFG_SYSCLK_CLKSLOW_DIVIDER; #endif /* CY_CFG_SYSCLK_CLKSLOW_DIVIDER */ - + #ifdef CY_CFG_SYSCLK_CLKHF0_CLKPATH secure_config->hf0Source = CY_CFG_SYSCLK_CLKHF0_CLKPATH; #endif /* CY_CFG_SYSCLK_CLKHF0_CLKPATH */ - + #ifdef CY_CFG_SYSCLK_CLKHF0_DIVIDER secure_config->hf0Divider = CY_CFG_SYSCLK_CLKHF0_DIVIDER; #endif /* CY_CFG_SYSCLK_CLKHF0_DIVIDER */ - + #ifdef CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ secure_config->hf0OutFreqMHz = CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ; #endif /* CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ */ - + #ifdef CY_CFG_SYSCLK_CLKHF1_CLKPATH secure_config->hf1Source = CY_CFG_SYSCLK_CLKHF1_CLKPATH; #endif /* CY_CFG_SYSCLK_CLKHF1_CLKPATH */ - + #ifdef CY_CFG_SYSCLK_CLKHF1_DIVIDER secure_config->hf1Divider = CY_CFG_SYSCLK_CLKHF1_DIVIDER; #endif /* CY_CFG_SYSCLK_CLKHF1_DIVIDER */ - + #ifdef CY_CFG_SYSCLK_CLKHF1_FREQ_MHZ secure_config->hf1OutFreqMHz = CY_CFG_SYSCLK_CLKHF1_FREQ_MHZ; #endif /* CY_CFG_SYSCLK_CLKHF1_FREQ_MHZ */ - + #ifdef CY_CFG_SYSCLK_CLKHF2_CLKPATH secure_config->hf2Source = CY_CFG_SYSCLK_CLKHF2_CLKPATH; #endif /* CY_CFG_SYSCLK_CLKHF2_CLKPATH */ - + #ifdef CY_CFG_SYSCLK_CLKHF2_DIVIDER secure_config->hf2Divider = CY_CFG_SYSCLK_CLKHF2_DIVIDER; #endif /* CY_CFG_SYSCLK_CLKHF2_DIVIDER */ - + #ifdef CY_CFG_SYSCLK_CLKHF2_FREQ_MHZ secure_config->hf2OutFreqMHz = CY_CFG_SYSCLK_CLKHF2_FREQ_MHZ; #endif /* CY_CFG_SYSCLK_CLKHF2_FREQ_MHZ */ - + #ifdef CY_CFG_SYSCLK_CLKHF3_CLKPATH secure_config->hf3Source = CY_CFG_SYSCLK_CLKHF3_CLKPATH; #endif /* CY_CFG_SYSCLK_CLKHF3_CLKPATH */ - + #ifdef CY_CFG_SYSCLK_CLKHF3_DIVIDER secure_config->hf3Divider = CY_CFG_SYSCLK_CLKHF3_DIVIDER; #endif /* CY_CFG_SYSCLK_CLKHF3_DIVIDER */ - + #ifdef CY_CFG_SYSCLK_CLKHF3_FREQ_MHZ secure_config->hf3OutFreqMHz = CY_CFG_SYSCLK_CLKHF3_FREQ_MHZ; #endif /* CY_CFG_SYSCLK_CLKHF3_FREQ_MHZ */ - + #ifdef CY_CFG_SYSCLK_CLKHF4_CLKPATH secure_config->hf4Source = CY_CFG_SYSCLK_CLKHF4_CLKPATH; #endif /* CY_CFG_SYSCLK_CLKHF4_CLKPATH */ - + #ifdef CY_CFG_SYSCLK_CLKHF4_DIVIDER secure_config->hf4Divider = CY_CFG_SYSCLK_CLKHF4_DIVIDER; #endif /* CY_CFG_SYSCLK_CLKHF4_DIVIDER */ - + #ifdef CY_CFG_SYSCLK_CLKHF4_FREQ_MHZ secure_config->hf4OutFreqMHz = CY_CFG_SYSCLK_CLKHF4_FREQ_MHZ; #endif /* CY_CFG_SYSCLK_CLKHF4_FREQ_MHZ */ - + #ifdef CY_CFG_SYSCLK_CLKHF5_CLKPATH secure_config->hf5Source = CY_CFG_SYSCLK_CLKHF5_CLKPATH; #endif /* CY_CFG_SYSCLK_CLKHF5_CLKPATH */ - + #ifdef CY_CFG_SYSCLK_CLKHF5_DIVIDER secure_config->hf5Divider = CY_CFG_SYSCLK_CLKHF5_DIVIDER; #endif /* CY_CFG_SYSCLK_CLKHF5_DIVIDER */ - + #ifdef CY_CFG_SYSCLK_CLKHF5_FREQ_MHZ secure_config->hf5OutFreqMHz = CY_CFG_SYSCLK_CLKHF5_FREQ_MHZ; #endif /* CY_CFG_SYSCLK_CLKHF5_FREQ_MHZ */ - + #ifdef CY_CFG_SYSCLK_CLKPUMP_SOURCE secure_config->pumpSource = CY_CFG_SYSCLK_CLKPUMP_SOURCE; #endif /* CY_CFG_SYSCLK_CLKPUMP_SOURCE */ - + #ifdef CY_CFG_SYSCLK_CLKPUMP_DIVIDER secure_config->pumpDivider = CY_CFG_SYSCLK_CLKPUMP_DIVIDER; #endif /* CY_CFG_SYSCLK_CLKPUMP_DIVIDER */ - + #ifdef CY_CFG_SYSCLK_CLKLF_SOURCE secure_config->clkLfSource = CY_CFG_SYSCLK_CLKLF_SOURCE; #endif /* CY_CFG_SYSCLK_CLKLF_SOURCE */ - + #ifdef CY_CFG_SYSCLK_CLKBAK_SOURCE secure_config->clkBakSource = CY_CFG_SYSCLK_CLKBAK_SOURCE; #endif /* CY_CFG_SYSCLK_CLKBAK_SOURCE */ - + #ifdef CY_CFG_SYSCLK_CLKTIMER_SOURCE secure_config->clkTimerSource = CY_CFG_SYSCLK_CLKTIMER_SOURCE; #endif /* CY_CFG_SYSCLK_CLKTIMER_SOURCE */ - + #ifdef CY_CFG_SYSCLK_CLKTIMER_DIVIDER secure_config->clkTimerDivider = CY_CFG_SYSCLK_CLKTIMER_DIVIDER; #endif /* CY_CFG_SYSCLK_CLKTIMER_DIVIDER */ - + #ifdef CY_CFG_SYSCLK_CLKALTSYSTICK_SOURCE secure_config->clkSrcAltSysTick = CY_CFG_SYSCLK_CLKALTSYSTICK_SOURCE; #endif /* CY_CFG_SYSCLK_CLKALTSYSTICK_SOURCE */ - + #ifdef CY_CFG_SYSCLK_ALTHF_BLE_ECO_CLOAD secure_config->altHFcLoad = CY_CFG_SYSCLK_ALTHF_BLE_ECO_CLOAD; #endif /* CY_CFG_SYSCLK_ALTHF_BLE_ECO_CLOAD */ - + #ifdef CY_CFG_SYSCLK_ALTHF_BLE_ECO_TIME secure_config->altHFxtalStartUpTime = CY_CFG_SYSCLK_ALTHF_BLE_ECO_TIME; #endif /* CY_CFG_SYSCLK_ALTHF_BLE_ECO_TIME */ - + #ifdef CY_CFG_SYSCLK_ALTHF_BLE_ECO_FREQ secure_config->altHFfreq = CY_CFG_SYSCLK_ALTHF_BLE_ECO_FREQ; #endif /* CY_CFG_SYSCLK_ALTHF_BLE_ECO_FREQ */ - + #ifdef CY_CFG_SYSCLK_ALTHF_BLE_ECO_CLK_DIV secure_config->altHFsysClkDiv = CY_CFG_SYSCLK_ALTHF_BLE_ECO_CLK_DIV; #endif /* CY_CFG_SYSCLK_ALTHF_BLE_ECO_CLK_DIV */ - + #ifdef CY_CFG_SYSCLK_ALTHF_BLE_ECO_VOL_REGULATOR secure_config->altHFvoltageReg = CY_CFG_SYSCLK_ALTHF_BLE_ECO_VOL_REGULATOR; #endif /* CY_CFG_SYSCLK_ALTHF_BLE_ECO_VOL_REGULATOR */ @@ -588,7 +654,7 @@ __WEAK void cycfg_ClockStartupError(uint32_t error) #if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) __STATIC_INLINE void Cy_SysClk_ClkBakInit() { - Cy_SysClk_ClkBakSetSource(CY_SYSCLK_BAK_IN_WCO); + Cy_SysClk_ClkBakSetSource(CY_SYSCLK_BAK_IN_CLKLF); } #endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) #if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) @@ -617,6 +683,30 @@ __WEAK void cycfg_ClockStartupError(uint32_t error) Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE); } #endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) +#if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) + __STATIC_INLINE void Cy_SysClk_ClkHf2Init() + { + Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF2, CY_CFG_SYSCLK_CLKHF2_CLKPATH); + Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF2, CY_SYSCLK_CLKHF_DIVIDE_BY_2); + Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF2); + } +#endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) +#if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) + __STATIC_INLINE void Cy_SysClk_ClkHf3Init() + { + Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF3, CY_CFG_SYSCLK_CLKHF3_CLKPATH); + Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF3, CY_SYSCLK_CLKHF_NO_DIVIDE); + Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF3); + } +#endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) +#if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) + __STATIC_INLINE void Cy_SysClk_ClkHf4Init() + { + Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF4, CY_CFG_SYSCLK_CLKHF4_CLKPATH); + Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF4, CY_SYSCLK_CLKHF_NO_DIVIDE); + Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF4); + } +#endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) #if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) __STATIC_INLINE void Cy_SysClk_IloInit() { @@ -638,10 +728,48 @@ __WEAK void cycfg_ClockStartupError(uint32_t error) Cy_SysClk_ClkPathSetSource(0U, CY_CFG_SYSCLK_CLKPATH0_SOURCE); } #endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) +#if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) + __STATIC_INLINE void Cy_SysClk_ClkPath1Init() + { + Cy_SysClk_ClkPathSetSource(1U, CY_CFG_SYSCLK_CLKPATH1_SOURCE); + } +#endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) +#if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) + __STATIC_INLINE void Cy_SysClk_ClkPath2Init() + { + Cy_SysClk_ClkPathSetSource(2U, CY_CFG_SYSCLK_CLKPATH2_SOURCE); + } +#endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) #if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) __STATIC_INLINE void Cy_SysClk_ClkPeriInit() { - Cy_SysClk_ClkPeriSetDivider(1U); + Cy_SysClk_ClkPeriSetDivider(0U); + } +#endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) +#if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) + __STATIC_INLINE void Cy_SysClk_Pll0Init() + { + if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllManualConfigure(1U, &srss_0_clock_0_pll_0_pllConfig)) + { + cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR); + } + if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllEnable(1U, 10000u)) + { + cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR); + } + } +#endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) +#if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) + __STATIC_INLINE void Cy_SysClk_Pll1Init() + { + if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllManualConfigure(2U, &srss_0_clock_0_pll_1_pllConfig)) + { + cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR); + } + if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllEnable(2U, 10000u)) + { + cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR); + } } #endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) #if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) @@ -654,7 +782,7 @@ __WEAK void cycfg_ClockStartupError(uint32_t error) __STATIC_INLINE void Cy_SysClk_ClkTimerInit() { Cy_SysClk_ClkTimerDisable(); - Cy_SysClk_ClkTimerSetSource(CY_SYSCLK_CLKTIMER_IN_HF0_NODIV); + Cy_SysClk_ClkTimerSetSource(CY_SYSCLK_CLKTIMER_IN_IMO); Cy_SysClk_ClkTimerSetDivider(0U); Cy_SysClk_ClkTimerEnable(); } @@ -731,7 +859,7 @@ void init_cycfg_system(void) #if ((CY_CFG_SYSCLK_CLKPATH5_SOURCE_NUM != 0UL) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH_NUM == 5UL)) #error Configuration Error : ECO, WCO, ALTHF, EXTCLK, ILO, PILO cannot drive HF0. #endif - + configStatus = CY_PRA_FUNCTION_CALL_RETURN_PARAM(CY_PRA_MSG_TYPE_SYS_CFG_FUNC, CY_PRA_FUNC_INIT_CYCFG_DEVICE, &srss_0_clock_0_secureConfig); @@ -744,7 +872,7 @@ void init_cycfg_system(void) Cy_SysClk_ExtClkSetFrequency(CY_CFG_SYSCLK_EXTCLK_FREQ); #endif /* CY_CFG_SYSCLK_EXTCLK_FREQ */ #else /* ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) */ - + /* Set worst case memory wait states (! ultra low power, 150 MHz), will update at the end */ Cy_SysLib_SetWaitStates(false, 150UL); #ifdef CY_CFG_PWR_ENABLED @@ -754,7 +882,7 @@ void init_cycfg_system(void) #warning Power system will not be configured. Update power personality to v1.20 or later. #endif /* CY_CFG_PWR_INIT */ #endif /* CY_CFG_PWR_ENABLED */ - + /* Reset the core clock path to default and disable all the FLLs/PLLs */ Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE); Cy_SysClk_ClkFastSetDivider(0U); @@ -765,59 +893,59 @@ void init_cycfg_system(void) (void)Cy_SysClk_PllDisable(pll); } Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH1, CY_SYSCLK_CLKPATH_IN_IMO); - + if ((CY_SYSCLK_CLKHF_IN_CLKPATH0 == Cy_SysClk_ClkHfGetSource(0UL)) && (CY_SYSCLK_CLKPATH_IN_WCO == Cy_SysClk_ClkPathGetSource(CY_SYSCLK_CLKHF_IN_CLKPATH0))) { Cy_SysClk_ClkHfSetSource(0U, CY_SYSCLK_CLKHF_IN_CLKPATH1); } - + Cy_SysClk_FllDisable(); Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH0, CY_SYSCLK_CLKPATH_IN_IMO); Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH0); #ifdef CY_IP_MXBLESS (void)Cy_BLE_EcoReset(); #endif - - + + /* Enable all source clocks */ #ifdef CY_CFG_SYSCLK_PILO_ENABLED Cy_SysClk_PiloInit(); #endif - + #ifdef CY_CFG_SYSCLK_WCO_ENABLED Cy_SysClk_WcoInit(); #endif - + #ifdef CY_CFG_SYSCLK_CLKLF_ENABLED Cy_SysClk_ClkLfInit(); #endif - + #ifdef CY_CFG_SYSCLK_ALTHF_ENABLED Cy_SysClk_AltHfInit(); #endif - + #ifdef CY_CFG_SYSCLK_ECO_ENABLED Cy_SysClk_EcoInit(); #endif - + #ifdef CY_CFG_SYSCLK_EXTCLK_ENABLED Cy_SysClk_ExtClkInit(); #endif - + /* Configure CPU clock dividers */ #ifdef CY_CFG_SYSCLK_CLKFAST_ENABLED Cy_SysClk_ClkFastInit(); #endif - + #ifdef CY_CFG_SYSCLK_CLKPERI_ENABLED Cy_SysClk_ClkPeriInit(); #endif - + #ifdef CY_CFG_SYSCLK_CLKSLOW_ENABLED Cy_SysClk_ClkSlowInit(); #endif - + #if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE_NUM == 0x6UL) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH_NUM == 0U)) /* Configure HFCLK0 to temporarily run from IMO to initialize other clocks */ Cy_SysClk_ClkPathSetSource(1UL, CY_SYSCLK_CLKPATH_IN_IMO); @@ -827,7 +955,7 @@ void init_cycfg_system(void) Cy_SysClk_ClkPath1Init(); #endif #endif - + /* Configure Path Clocks */ #ifdef CY_CFG_SYSCLK_CLKPATH0_ENABLED Cy_SysClk_ClkPath0Init(); @@ -874,21 +1002,21 @@ void init_cycfg_system(void) #ifdef CY_CFG_SYSCLK_CLKPATH15_ENABLED Cy_SysClk_ClkPath15Init(); #endif - + /* Configure and enable FLL */ #ifdef CY_CFG_SYSCLK_FLL_ENABLED Cy_SysClk_FllInit(); #endif - + Cy_SysClk_ClkHf0Init(); - + #if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE_NUM == 0x6UL) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH_NUM == 0U)) #ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED /* Apply the ClkPath1 user setting */ Cy_SysClk_ClkPath1Init(); #endif #endif - + /* Configure and enable PLLs */ #ifdef CY_CFG_SYSCLK_PLL0_ENABLED Cy_SysClk_Pll0Init(); @@ -935,7 +1063,7 @@ void init_cycfg_system(void) #ifdef CY_CFG_SYSCLK_PLL14_ENABLED Cy_SysClk_Pll14Init(); #endif - + /* Configure HF clocks */ #ifdef CY_CFG_SYSCLK_CLKHF1_ENABLED Cy_SysClk_ClkHf1Init(); @@ -982,49 +1110,49 @@ void init_cycfg_system(void) #ifdef CY_CFG_SYSCLK_CLKHF15_ENABLED Cy_SysClk_ClkHf15Init(); #endif - + /* Configure miscellaneous clocks */ #ifdef CY_CFG_SYSCLK_CLKTIMER_ENABLED Cy_SysClk_ClkTimerInit(); #endif - + #ifdef CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED Cy_SysClk_ClkAltSysTickInit(); #endif - + #ifdef CY_CFG_SYSCLK_CLKPUMP_ENABLED Cy_SysClk_ClkPumpInit(); #endif - + #ifdef CY_CFG_SYSCLK_CLKBAK_ENABLED Cy_SysClk_ClkBakInit(); #endif - + /* Configure default enabled clocks */ #ifdef CY_CFG_SYSCLK_ILO_ENABLED Cy_SysClk_IloInit(); #endif - + #ifndef CY_CFG_SYSCLK_IMO_ENABLED #error the IMO must be enabled for proper chip operation #endif - + #endif /* ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) */ - + #ifdef CY_CFG_SYSCLK_MFO_ENABLED Cy_SysClk_MfoInit(); #endif - + #ifdef CY_CFG_SYSCLK_CLKMF_ENABLED Cy_SysClk_ClkMfInit(); #endif - + #if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) /* Set accurate flash wait states */ #if (defined (CY_CFG_PWR_ENABLED) && defined (CY_CFG_SYSCLK_CLKHF0_ENABLED)) Cy_SysLib_SetWaitStates(CY_CFG_PWR_USING_ULP != 0, CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ); #endif - + /* Update System Core Clock values for correct Cy_SysLib_Delay functioning */ SystemCoreClockUpdate(); #ifndef CY_CFG_SYSCLK_ILO_ENABLED @@ -1035,11 +1163,19 @@ void init_cycfg_system(void) Cy_SysClk_IloDisable(); Cy_SysClk_IloHibernateOn(false); #endif - + #endif /* ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) */ - + #if defined (CY_USING_HAL) cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_0_obj); #endif //defined (CY_USING_HAL) + +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_1_obj); +#endif //defined (CY_USING_HAL) + +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_2_obj); +#endif //defined (CY_USING_HAL) } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h index 272629378c..f3c1c9450f 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h @@ -4,13 +4,11 @@ * Description: * System configuration * This file was automatically generated and should not be modified. -* Tools Package 2.2.0.1747 -* psoc6pdl 1.6.0.4266 -* personalities_2.0 2.0.0.0 -* udd 1.2.0.370 +* cfg-backend-cli: 1.2.0.1483 +* Device Support Library (libs/psoc6pdl): 1.6.0.4266 * ******************************************************************************** -* Copyright 2020 Cypress Semiconductor Corporation +* Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -51,13 +49,26 @@ extern "C" { #define srss_0_clock_0_hfclk_0_ENABLED 1U #define CY_CFG_SYSCLK_CLKHF0 0UL #define CY_CFG_SYSCLK_CLKHF0_CLKPATH_NUM 0UL +#define srss_0_clock_0_hfclk_2_ENABLED 1U +#define CY_CFG_SYSCLK_CLKHF2 2UL +#define CY_CFG_SYSCLK_CLKHF2_CLKPATH_NUM 0UL +#define srss_0_clock_0_hfclk_3_ENABLED 1U +#define CY_CFG_SYSCLK_CLKHF3 3UL +#define CY_CFG_SYSCLK_CLKHF3_CLKPATH_NUM 0UL +#define srss_0_clock_0_hfclk_4_ENABLED 1U +#define CY_CFG_SYSCLK_CLKHF4 4UL +#define CY_CFG_SYSCLK_CLKHF4_CLKPATH_NUM 0UL #define srss_0_clock_0_ilo_0_ENABLED 1U #define srss_0_clock_0_imo_0_ENABLED 1U #define srss_0_clock_0_lfclk_0_ENABLED 1U #define CY_CFG_SYSCLK_CLKLF_FREQ_HZ 32768 #define CY_CFG_SYSCLK_CLKLF_SOURCE CY_SYSCLK_CLKLF_IN_WCO #define srss_0_clock_0_pathmux_0_ENABLED 1U +#define srss_0_clock_0_pathmux_1_ENABLED 1U +#define srss_0_clock_0_pathmux_2_ENABLED 1U #define srss_0_clock_0_periclk_0_ENABLED 1U +#define srss_0_clock_0_pll_0_ENABLED 1U +#define srss_0_clock_0_pll_1_ENABLED 1U #define srss_0_clock_0_slowclk_0_ENABLED 1U #define srss_0_clock_0_timerclk_0_ENABLED 1U #define srss_0_clock_0_wco_0_ENABLED 1U @@ -81,6 +92,12 @@ extern "C" { #if defined (CY_USING_HAL) extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj; #endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj; +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj; +#endif //defined (CY_USING_HAL) void init_cycfg_system(void); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list index 8453a4470f..47fe487d31 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list @@ -1,5 +1,5 @@ -[Device=CY8C624ABZI-D44] - +[Device=CYB0644ABZI-S2D44] + [Blocks] # WIFI # CYBSP_WIFI_SDIO diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/design.modus b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/design.modus index 41bce63a01..853df6b348 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/design.modus +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/design.modus @@ -1,6 +1,6 @@ - - + + @@ -270,7 +270,7 @@ - + @@ -279,12 +279,9 @@ - + - - - - + @@ -293,6 +290,24 @@ + + + + + + + + + + + + + + + + + + @@ -313,9 +328,35 @@ + + + + + + + + + + - + + + + + + + + + + + + + + + + + @@ -325,7 +366,7 @@ - + @@ -342,8 +383,8 @@ - - + + @@ -427,5 +468,6 @@ +