I was getting Hard Faults in even the simplest of samples before I made
these fixes.
* WaitUs() did nothing on optimized builds. I added the volatile
qualifier to the cyc variable to make sure that the delay loop
doesn't get optimized out.
* I removed the #ifdef which skipped the fpuInit() call when building
with GCC.
Bugs are as below.
- Add terminal setting of IRQ4 and IRQ6 that leaked.
- When set the interrupt function by rise()/fall(), the interrupt disable state will be released by disable_irq().
- Interrupt will be continued to occur when execute disable_irq() after rise(NULL)/fall(NULL) set.
- Fix the setting timing of PMC register.
- some minor error correction
- add pin definition for 3 tests (MBED_A5,6,7)
- add new target disco_f401vc to travis_build
travis_build and all test are OK except missing STM32F4 target
MTS_MDOT_F405RG
The mcu STM32L053C8 seems to have a problem in the RCC - LSE hardware
block. The Disco_L053 don't have a 32kHz crystal connected to LSE port
pins in contrast to NUCLEO_L053.
During initialization the HAL tests if it can start the LSE oscillator.
The Flag LSERDY in RCC_CSR is set to 1 by RCC clock control when the
oscillator runs stable. Without a crystal the flag shouldn't be set and
the HAL trys to start the internal LSI oscillator.
But the flag is always set to 1 also without a crystal. That's why the
RTC doesn't start.
In case of off-line compiler, there is no problem about the frequency setting processing.
But in case of online compiler, the frequency setting processing will be error.
So, modify frequency setting processing of SPI to pass in online compiler.
Issue originally reported on mbed site here:
https://developer.mbed.org/questions/5695/FRDM-KL05z-hardfault-when-compiled-with-/
The RAM base address was incorrectly set to the beginning of RAM
instead of at a 0xC0 byte offset to reserve room for the interrupt
vectors. Without this fix, the global variables and the interrupt
vectors were occupying the same space in RAM once the user enabled the
timer interrupt.
The user who originally reported the issue on the mbed site has tested
this fix and verified that it corrected the hard fault issue that they
were encountering.
Martin Kojtal
nitin.bhaskar.27.09@gmail.com
Adam Green
Paul Staron
bcostm
Masao Hamanaka
ohagendorf
kazu-zamasu
albert361
Toyomasa Watarai