CMSIS repo does not support pre-processor defines, hence multiple assembly
files are added for secure/non-secure and floating point tools.
Mbed OS tools support assembly file pre-processing, but the build system
does not support multiple assembly files for each target, hence updating
the assembly files.
1. Patch RTX so irq_cm4f.S files work with no FPU targets
2. Patch RTX so irq_armv8mml.S files to work with and without FPU
2. Patch RTX so irq_armv8mml.S and irq_armv8mbl.S files to work with secure and
non-secure builds
(cherry picked from commit 094662790a)
In case of ARM compiler, idle and timer thread stack though assigned
to `.bss.os` section since not zero initialized are part of `data` section.
In this commit, we are moving stacks of idle and timer thread to bss
section and thereby saving ROM space.
(cherry picked from commit ba92372b8d)
Assembler in rtx_core_ca.h is on the whole unified syntax such that it
should work fine if assembled as either ARM or Thumb-2.
The exception was __get_PSP, which uses STM^, which is only available
in ARM state.
Flagging for this function was incorrect, except for IAR - it switched
assembler state without telling the compiler, meaning that the resulting
assembler output could be incorrect, and that the function itself would
not be correctly marked as an ARM function - the CPU would enter in
Thumb state.
Alternative fix would be to switch to System mode, which would work
as either ARM or Thumb-2 assembler, like the rest of the file, but
this is the minimal change.
Fixes#526.
CMSIS repo does not support pre-processor defines, hence multiple assembly
files are added for secure/non-secure and floating point tools.
Mbed OS tools support assembly file pre-processing, but the build system
does not support multiple assembly files for each target, hence updating
the assembly files.
1. Patch RTX so irq_cm4f.S files work with no FPU targets
2. Patch RTX so irq_armv8mml.S files to work with and without FPU
2. Patch RTX so irq_armv8mml.S and irq_armv8mbl.S files to work with secure and
non-secure builds
1. Revert "CMSIS/RTX: __FPU_USED to be set based on HW FPU support"
This reverts commit b4f5bed7e75c21927c954a50d40422b81a1de5a0.
2. Revert "CMSIS/RTX: Update Armv8M IAR 8.x assembly files - add END"
This reverts commit b228cd9db0.
3. Revert "CMSIS/RTX: Pre-processor defines used for assembly"
This reverts commit 287121ffdc.
4. Revert "CMSIS/RTX: Patch RTX so irq_cm4f.s files work with no FPU targets"
This reverts commit cc2e0517e1.
In case of ARM compiler, idle and timer thread stack though assigned
to `.bss.os` section since not zero initialized are part of `data` section.
In this commit, we are moving stacks of idle and timer thread to bss
section and thereby saving ROM space.
Add missing END to the IAR assembly files. In future this commit should be
merged to other assembly file commit, when performing CMSIS update.
287121ffdc
CMSIS repo does not support pre-processor defines, hence multiple assembly
files are added for secure/non-secure and floating point tools.
Mbed OS tools support assembly file pre-processing, but the build system
does not support multiple assembly files for each target, hence updating
the assembly files.
(cherry picked from commit 287121ffdc)
Move the function "mbed_get_a9_tick_irqn()" declared in os_tick.h
to SysTimer.h so it does not get overridden when RTX is updated.
This function was originally added in:
3d3e89097d
Fixes for RZ_A1H issue 6543
Add the OsEventObserver mechanism. A client interested in receiving
notifications on certain OS events can register to receive notifications
with osRegisterForOsEvents. This is useful for clients like the secure
memory allocator, which observes thread switching events in order to
swap in and out different memory allocator objects.
OsEventObserver objects expect a context to be maintained per thread on
their behalf. Add this context to the thread control block and extend
the thread creation functions with the ability to supply a context.
uVisor doesn't set the PSP of the target thread. The RTOS sets the PSP
of the target thread from the target thread's TCB. However, when
interrupts of higher priority than PendSV happen between the call to
uVisor to switch boxes, and the RTOS setting PSP, the uVisor vIRQ
interrupt handler will attempt to use an invalid PSP (the PSP from
before the box and thread switch). This leads to a crash. Make box and
thread switching atomic by disabling interrupts immediately before the
box switching until immediately after the new PSP is set.
CMSIS repo does not support pre-processor defines, hence multiple assembly
files are added for secure/non-secure and floating point tools.
Mbed OS tools support assembly file pre-processing, but the build system
does not support multiple assembly files for each target, hence updating
the assembly files.
Systick handler switch to secure/nonsecure issues addressed:
1. Switch to secure/nonsecure context save/restore is based on 6th bit in
LR register, correct the bug (R7 instead of LR was used for decision)
2. Prevent R7 from being corrupted in Sys_ContextSave
3. Branch when non-secure rather than secure
CMSIS repo does not support pre-processor defines, hence multiple assembly
files are added for secure/non-secure and floating point tools.
Mbed OS tools support assembly file pre-processing, but the build system
does not support multiple assembly files for each target, hence updating
the assembly files.
armcc fopen allocated a mutex using the retargeted system-level
_mutex_initialize function. Interestingly, malloc also uses this
same _mutex_initialization function, which prevents a full solution
relying on malloc. The solution previously implemented involved using
the rtx mutex pool for the first 8 mutexes, then falling back on
malloc.
The previous implementation relied on osMutexNew returning an error
on out-of-memory. An unrelated change causes osMutexNew to instead
assert (except for release mode). This meant if you exceed 8 system-
level mutexes in armcc you will hit an assert. Since the filesystem
code can call fopen an unlimited number of times, this is a problem.
Solution is to keep track of which static mutexes we've allocated, so
we know before calling osMutexNew if we need to call malloc.
Also _mutex_free never deallocated the malloced mutexes, which would
cause fopen to leak memory.
uVisor doesn't set the PSP of the target thread. The RTOS sets the PSP
of the target thread from the target thread's TCB. However, when
interrupts of higher priority than PendSV happen between the call to
uVisor to switch boxes, and the RTOS setting PSP, the uVisor vIRQ
interrupt handler will attempt to use an invalid PSP (the PSP from
before the box and thread switch). This leads to a crash. Make box and
thread switching atomic by disabling interrupts immediately before the
box switching until immediately after the new PSP is set.
Bartek Szatkowski
deepikabhavnani
Kevin Bracey
d-kato
Russ Butler
Oren Cohen
Michael Coulter
Vladimir Umek
Jaeden Amero
Tamas Kaman
Cruz Monrreal
Robert Rostohar
Christopher Haster