mirror of https://github.com/ARMmbed/mbed-os.git
Pulling in CMSIS commit 05fa9d328a
Systick handler switch to secure/nonsecure issues addressed: 1. Switch to secure/nonsecure context save/restore is based on 6th bit in LR register, correct the bug (R7 instead of LR was used for decision) 2. Prevent R7 from being corrupted in Sys_ContextSave 3. Branch when non-secure rather than securepull/6029/head
parent
4076788d51
commit
cf65e2b125
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@ -225,8 +225,9 @@ Sys_ContextSave
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BL TZ_StoreContext_S ; Store secure context
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MOV LR,R7 ; Set EXC_RETURN
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POP {R1,R2,R3,R7} ; Restore registers
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LSLS R7,R7,#25 ; Check domain of interrupted thread
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BMI Sys_ContextSave1 ; Branch if secure
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MOV R0,LR ; Get EXC_RETURN
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LSLS R0,R0,#25 ; Check domain of interrupted thread
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BPL Sys_ContextSave1 ; Branch if non-secure
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MRS R0,PSP ; Get PSP
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STR R0,[R1,#TCB_SP_OFS] ; Store SP
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B Sys_ContextSave2
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@ -229,8 +229,9 @@ Sys_ContextSave:
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BL TZ_StoreContext_S // Store secure context
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MOV LR,R7 // Set EXC_RETURN
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POP {R1,R2,R3,R7} // Restore registers
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LSLS R7,R7,#25 // Check domain of interrupted thread
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BMI Sys_ContextSave1 // Branch if secure
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MOV R0,LR // Get EXC_RETURN
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LSLS R0,R0,#25 // Check domain of interrupted thread
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BPL Sys_ContextSave1 // Branch if not secure
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MRS R0,PSP // Get PSP
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STR R0,[R1,#TCB_SP_OFS] // Store SP
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B Sys_ContextSave2
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@ -218,8 +218,9 @@ Sys_ContextSave
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BL TZ_StoreContext_S ; Store secure context
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MOV LR,R7 ; Set EXC_RETURN
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POP {R1,R2,R3,R7} ; Restore registers
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LSLS R7,R7,#25 ; Check domain of interrupted thread
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BMI Sys_ContextSave1 ; Branch if secure
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MOV R0,LR ; Get EXC_RETURN
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LSLS R0,R0,#25 ; Check domain of interrupted thread
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BPL Sys_ContextSave1 ; Branch if not secure
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MRS R0,PSP ; Get PSP
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STR R0,[R1,#TCB_SP_OFS] ; Store SP
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B Sys_ContextSave2
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