Although the extened RTC is supported by #5363 commit ("Add support and tests for extended RTC"), it seems that the changes was overlooked in RZ_A1H_api.c.
So I added the changes with reference to other rtc_api.c.
I changed disable_irq() / enable_irq() to core_util_critical_section_enter() / core_util_critical_section_exit() by utilizing "mbed_critical" function in the below drivers.
- serial_api.c
- us_ticker.c
I added the below definitions for working "Dynamic Stack" and "Dynamic heap" on Mbed OS by referencing with the codes of Cortex-M target board.
"ISR_STACK_START", "ISR_STACK_SIZE", "INITIAL_SP", "HEAP_START" and "HEAP_SIZE"
By updating to the codes of CMSIS5/RTX5, GIC_SetConfigration() function was added for Cortex-A, this function is set the interrupt configuration using GIC's ICFGR register. Therefore, I added this function to satisfy Cortex-A interrupt spec in the below files.
"can_api.c", "ethernet_api.c", "gpio_irq_api.c", "i2c_api.c", "spi_api.c" and "us_ticker.c"
For supporting tp CMSIS5/RTX5, I changed the start-up processing of 3 toolchains(ARMCC, GCC_ARM, IAR) and updated the register definition of PEACH specific.
In addition,
I changed the linker script files to implement the dynamic HEAP the same as Cortex-M targets.Since GR-PEACH's HEAP was a fixed area, I changed the label name(ZI_DATA to RW_IRAM1) and replaced the allocation of STACK/HEAP.
Set buffer for 1 sample in analogin_read_u16. Before it assumes the
buffer is set outside by the higher layer. Now it's temporarily
located on the stack since only the ADC value is returned.
Most of our IP stacks don't allow removal of interfaces so
interface destructor can not reliably clean up. Therefore we
cannot rely its behaviours in test case.
Instead run interface->disconnect() in case interface was already
created.
When specifying a full channel mask in .lib and setting the channel
to zero, device does proper channel scan.
For Thread, channel must be specified for router.
Sleepy devices don't respect the channel settings but do a full channel
scan at the start.
+ Modified the channel mask print to use hex.
Pending official update from STM, add memory barriers to the Ethernet
HAL code for the STM32F7xx family.
Cortex-M7 has a merging write buffer that is not automatically flushed
by accesses to devices, so without these DMBs, we sometimes lose synch
with the transmitter.
The DMBs are architecturally needed in every version of this HAL, but
adding just to the STM32F7 version for now to clear test, as the
problem has only been observed on Cortex-M7-based devices.
Fixes#5622.
As we have now matrix for targets, there might be some targets that take longer to compile.
It can timeout, if we produce an output after every target that it was build, it
should extend the timeout per target build.
This allows minimal debugging and allows tools like
mbed-os-linker-report to work properly.
Because debugging info is kept in .elf file and not flashed to device
there is no side effects to flash sizes.
TomoYamanaka
Dave Wu
Ashok Rao
Vincent Coubard
Deepika
Seppo Takalo
Martin Kojtal
Dexter Fryar
Kevin Bracey
Christopher Haster
David Walters
Anna Bridge
adustm
Mika Leppänen
jeromecoutant