ARMmbed
/
mbed-os
mirror of https://github.com/ARMmbed/mbed-os.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
32,349 Commits
52 Branches
336 Tags
624 MiB
Commit Graph

66 Commits (ba1e7b53d0cfc9dc8a1be33fea336a75090276f7)

Author SHA1 Message Date
Robert Walton a297a6145e Add library for NUCLEO_G431KB 2021-02-11 09:33:21 +00:00
Martin Kojtal 6bf459e3ce CMake STM32: fix mbed-stm linking libs names 2021-02-10 12:24:10 +00:00
Martin Kojtal 544e5b94c3 CMake STM32: fix targets naming 
Follow the naming for other CMake targets, using prefix mbed-, lower case with dashes
 2021-02-09 17:07:44 +00:00
Robert Walton d9e184b6c6 cmake: Refactor ST targets 
Refactor all ST targets to be CMake buildsystem targets. This removes
the need for checking MBED_TARGET_LABELS repeatedly and allows us to be
more flexible in the way we include MBED_TARGET source in the build.

A side effect of this is it will allow us to support custom targets
without breaking the build for 'standard' targets, as we use CMake's
standard mechanism for adding build rules to the build system, rather
than implementing our own layer of logic to exclude files not needed for
the target being built. Using this approach, if an MBED_TARGET is not
linked to using `target_link_libraries` its source files will not be
added to the build. This means custom target source can be added to the
user's application CMakeLists.txt without polluting the build system
when trying to compile for a standard MBED_TARGET.
 2021-02-04 15:26:36 +00:00
Tauno Magnusson dc969ba1d9 After checking other parts of the code (trng_api.c and a few other board platforms (NUCLEO_F413ZH, ...)) it appears that even though the reset value defaults correctly it may be good practice to keep the HAL_RCCEx_PeriphCLKConfig statement that selects the HSI48CLK as source for USB/RNG. 2021-01-26 03:51:49 +01:00
Tauno Magnusson 21176e903a Removed the HAL_RCCEx_PeriphCLKConfig statement that was selecting the HSI48 CLK for USB. Assumption is that the STM32G4 reset value (defaults to HSI48 selected for USB) is preserved throughout Mbed initialization. 2021-01-26 03:27:37 +01:00
Tauno Magnusson 80f0a378fb Updated to enable HSI48 Clock also for USBDEVICE define in targets.json. Also added so that the CK48 Clock Mux selects HSI48 for both RNG and USB. Without these the RNG/USB will be clocked at PLLQ (170 MHz) and not work. 2021-01-26 02:51:03 +01:00
Tauno Magnusson 99d21b6a92 Fixed whitespaces (a tab that should be spaces) 2021-01-26 01:21:46 +01:00
Tauno Magnusson fa0474239b Autogenerated file using 'python targets/TARGET_STM/tools/STM32_gen_PeripheralPins.py -t M40_Nucleo_NUCLEO-G431KB'. Had to do some modifications since the autogenerated files contained errors. 2021-01-24 04:25:42 +01:00
Tauno Magnusson f871eff405 Reverted to a pure copy of 474RE system_clock.c since it was updated with RNG clock fixes. Removing USB Clock enablement (USB will not work out-of-the box but will require users to modify system_clock.c to enable its clock) - this inline with changes to targets.json where I removed the USBDEVICE define 2021-01-24 03:18:06 +01:00
Tauno Magnusson 173cc1fe29 Cleaning out workaround patches for G431KB now that Flash Bank Switching has been fixed on G4xxx level (ARMmbed/mbed-os patch #14149) 2021-01-24 02:44:09 +01:00
Tauno Magnusson e4fb7402c3 Fixed a typo (incorrectly referring to G474RE instead of G431KB) 2021-01-24 02:41:18 +01:00
Tauno Magnusson 3ff04fa81e Cleaned up and verified file 2021-01-24 02:15:22 +01:00
Tauno Magnusson 1389b1ac9d Adding CMakeLists.txt files for NUCLEO_G431KB 2021-01-24 02:15:21 +01:00
Tauno Magnusson d720792191 G431 only has 1 Flash Bank. Code is written with the assumption all G4 devices has 2 Flash Banks. Fix: Commented out SYSCFG_MEMRMP_FB_MODE since stm32g431KB only has 1 Flash Bank. flash_api.c checks for this #define and if it's set understands it as if the chip has 2 flash banks. STM32G4xx_HAL_Driver/stm32g4xx_hal.c also needs to check for this #define since it has flash bank swapping commands that are called in the startup sequence. Fix: Check for SYSCFG_MEMRMP_FB_MODE in Enable/Disable Flash bank swapping. 2021-01-24 02:15:21 +01:00
Tauno Magnusson 98e48828b1 Fix: Added ALIGN(8) for __etext section. This existed in mbed-6.3.0 version. I have not verified if it is truly needed, but it is better to err on the safe side. 2021-01-24 02:15:21 +01:00
Tauno Magnusson 5bd272aabc Adding support for NUCLEO_G431KB. Created this file based on G474RE file. Added support for USB - connected the HSI48 clock to USB (and RNG). Warning: I'm assuming Flash latency is the same as for G474RE. 2021-01-24 02:15:21 +01:00
Tauno Magnusson 70bd5b916d Adding support for NUCLEO_G431KB. Created this file based on G474RE. I have done a decent effort to port it / check it. However - Warning - Not everything is verified the the G431 Spec Sheets. 2021-01-24 02:15:21 +01:00
Tauno Magnusson 936467ebab Adding support for NUCLEO_G431KB. Created this file based on G474RE. Fully verified with Spec Sheets 2021-01-24 02:15:21 +01:00
Martin Kojtal c4c28773aa
Merge pull request #14149 from jeromecoutant/PR_G4 
STM32G4: enable TRNG and correct dual bank flash detection
 2021-01-19 09:19:37 +00:00
jeromecoutant 61d00d858f STM32G4: dual bank FLASH detection 2021-01-13 16:45:03 +01:00
jeromecoutant eb627788ca STM32G4: TRNG enabled 
+ some cleanup/optimisation in SetSysClock
 2021-01-13 16:44:57 +01:00
pea-pod e1c754b179 Add SPI bitwidths to ST targets where supported 2021-01-11 07:53:07 -06:00
Martin Kojtal fc16d2bae7 STM: fix ARMClang sct files, using proper -E command 
This is required for ARMClang, otherwise there is an error with unknown command.
 2020-11-25 13:35:36 +00:00
Martin Kojtal ced4aa6e2d
Merge pull request #13939 from jeromecoutant/PR_LSEDRIVE 
STM32: LSE DRIVE feature update
 2020-11-24 14:13:52 +00:00
Martin Kojtal a1fc9cdad5
Merge pull request #13915 from 0xc0170/cmake-stm32 
CMake: add all TARGET_STM targets
 2020-11-24 14:09:28 +00:00
jeromecoutant 29af76fcca STM32: LSE DRIVE feature update 2020-11-20 17:31:26 +01:00
reme 16e63dc108 STM32 FLASH API : add critical sections 
See PR #13802 (for F4 board)

Concerned boards are

STM32F0
STM32F1
STM32F2
STM32F3
STM32F4
STM32F7
STM32G0
STM32G4
STM32H7
STM32L0
STM32L1
STM32L4
STM32L5

Adding test of return code of HAL_FLASH_Lock() function
Adding board STM32F4
Running AStyle
 2020-11-20 08:03:24 +00:00
Martin Kojtal fea34ce976 CMake: add STM32G4 targets 2020-11-17 15:17:17 +00:00
jeromecoutant 759a817005 STM32G4: STM32Cube_FW_G4_V1.3.0 
source: https://github.com/STMicroelectronics/STM32CubeG4
 2020-10-16 17:31:04 +02:00
jeromecoutant cd99f641dc STM32G4: cleanup 2020-10-16 17:31:03 +02:00
jeromecoutant 4f95500dc9 STM32G4: target directoty restructuration 
- Alignment with other STM32 families
- Subfamily level in targets.json
 2020-10-16 17:31:03 +02:00
Harrison Mutai 4fad1112e5 Add SPDX license identifier to Arm files 
Add license identifier to files which Arm owns the copyright to,
and contain either BSD-3 or Apache-2.0 licenses. This is to address
license errors raised by scancode analysis.
 2020-10-15 10:47:27 +01:00
George Beckstein 76d488ded1 Revert sampling time decrease and remove todos. 2020-09-22 09:32:14 -04:00
jeromecoutant bbc7355df5 Merge internal ADC channel changes from ST 
Co-authored-by: jeromecoutant <jerome.coutant@st.com>
 2020-09-21 12:26:23 -04:00
George Beckstein bbc15f65c0 Implemented adc deinitialization functionality 2020-09-21 12:19:50 -04:00
George Beckstein e9d6c9c0b1 Fix AnalogIn implementation on STM32G4 series 2020-09-21 12:19:50 -04:00
Martin Kojtal 75544a7ce0
Merge pull request #13565 from m-ecry/feature-stm32g4-can-support 
Feature stm32g4 can support
 2020-09-17 15:08:46 +01:00
m-ecry 73493b909a STM-can-api: Fixed variable name for H7 
- can_frequency uses f instead of hz for can frequency
 - Also added comment to system_clock
 2020-09-16 17:35:32 +02:00
m-ecry 2a13fa199d STMG4-sys-clk: If can PLLQ=160MHz, else 170MHz 
- with 170MHz as can-core-frequency, the accuracy for many baudrates is
too low. 160MHz is better for a broad range of frequencies
 2020-09-14 18:15:41 +02:00
Jaeden Amero 612b148fd4 stack: armc: Workaround config passing bug 
Workaround a bug where the boot stack size configuration option is not
passed on to armlink, the Arm Compiler's linker. Prefer
MBED_CONF_TARGET_BOOT_STACK_SIZE if present, as this is what the
configuration system should provide. Fall back to MBED_BOOT_STACK_SIZE
if MBED_CONF_TARGET_BOOT_STACK_SIZE is not defined, as in the case of
buggy tools. If both MBED_CONF_TARGET_BOOT_STACK_SIZE and
MBED_BOOT_STACK_SIZE are not defined, then we fall back to a hard-coded
value provided by the linkerscript. See
https://github.com/ARMmbed/mbed-os/issues/13474 for more information.
 2020-09-10 10:08:38 +01:00
Jaeden Amero 39e69d328d Use boot stack size from config system 
To allow overriding of the boot stack size from the Mbed configuration
system, consistently use MBED_CONF_TARGET_BOOT_STACK_SIZE rather than
MBED_BOOT_STACK_SIZE.

Fixes #10319
 2020-09-10 10:08:38 +01:00
Robert 14ac4064b7 STM32Gx: LSI clock selection when LSE is not available 2020-09-07 14:47:11 +01:00
Martin Eckardt f32efe4c28 Changed PLL to 160MHz, PLLQ to 80MHz 2020-09-07 02:04:13 +02:00
Martin Eckardt 9bc2deb9aa make G4 target compileable with CAN support 2020-09-07 02:04:13 +02:00
George Beckstein 658d89be8c Apply linker fix as in #12690 to new NUCLEO_G474RE target 2020-05-20 06:39:17 -04:00
George Beckstein 6e2fa616c7 Added spi_api.c implementation 2020-05-20 06:39:17 -04:00
George Beckstein eb8d128a24 Updated system clock settings to run at 170MHz (max for this target). Affects both HSI and HSE modes. 2020-05-20 06:39:17 -04:00
George Beckstein 44ca862af3 Changed us_ticker configuration to use TIM5 instead of TIM2 to be consistent with the allowed PWM peripheral pins. 2020-05-20 06:39:17 -04:00
George Beckstein 2297e1b91e Updated clock configuration settings for NUCLEO_G474RE 2020-05-20 06:39:17 -04:00