Fixes test failure seen with tests-mbed_hal-stack_size_unification
under IAR and ARM toolchain
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Since commit 12c6b1bd8, the i.MX RT1050 has effectively had its data
cache disabled, as the SDRAM was marked Shareable; for the Cortex-M7,
shareable memory is not cached.
This was done to make the Ethernet driver work without any cache
maintenance code. This commit adds cache maintenance and memory barriers
to the Ethernet driver, and removes the Shareable attribute from the
SDRAM, so the data cache is used again.
Cache code in the base fsl_enet.c driver has not been activated - the
bulk of it is in higher-level Read and Write calls that we're not using,
and there is one flawed invalidate in its initialisation. Instead
imx_emac.cpp takes full cache responsibility.
This commit also marks the SDRAM as read/write-allocate. As the
Cortex-M7 has its "Dynamic read allocate mode" to automatically switch
back to read-allocate in cases where write allocate is working poorly
(eg large memset), this should result in a performance boost with no
downside.
Activating write-allocate is also an attempt to provoke any flaws in
cache maintenance - the Ethernet transmit buffers for example will be
more likely to have a little data in the cache that needs cleaning.
--legacyalign, --no_legacyalign are deprecated from ARMC6 compiler, in order to
remove deprecated flags all linker files (GCC and IAR as well to have uniformity)
should strictly align to 8-byte boundary
1. Add Pin defines for missing PWM pins
2. Update the hal to account for the number of PWM instances
3. Fix the register reload policy
4. Configure the XBAR to put the PWM fault inputs in inactive state
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
1. Remove the repeated_start flag and code as this is not needed
for the LPI2C module
2. Enable the SION bit on the I2C pins
3. Enable 22K Pullup option of the I2C pins
4. Update the 0 byte write implementation to ensure the START
command gets flushed out of the FIFO
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Low power functions related to powering off FLEXSPI and SDRAM needs
to be copied to internal memory
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
1. Add the IVT header to the binary as this is required for boot up
This was earlier added by the DAPLink firmware. As it is no longer
handled in DAPLink, the header needs to be added inside mbed.
2. Update drivers
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Martin Kojtal
Mahesh Mahadevan
Kevin Bracey
deepikabhavnani
Przemyslaw Stekiel
Cruz Monrreal
alrodlim
David Saada
Martin Kojtal