Commit Graph

291 Commits (afe8834bb8aa0d094cf629b9c0b11030f48af599)

Author SHA1 Message Date
Martin Kojtal 6776cb726b
Merge pull request #5587 from slashdevteam/thread_terminate
Fix fatal parameter error when deleting/terminating Thread object
2017-12-20 14:49:57 +00:00
Martin Kojtal a762e7a622
Merge pull request #5687 from SenRamakri/sen_MutexErrorFix
Statically allocate ARMCC required mutex objects
2017-12-20 14:36:48 +00:00
Senthil Ramakrishnan d3f2883736 Statically allocate ARMCC required mutex objects 2017-12-11 11:41:47 -06:00
Bartek Szatkowski e8c5d652ef Remove inclusion of an internal RTX header 2017-11-28 12:07:57 +01:00
Maciej Rogozinski c08e0f51ec Fixed whitespace 2017-11-27 09:54:09 +01:00
Maciej Rogozinski c721ed8966 Fatal parameter error when deleting/terminating Thread object
Call to osThreadTerminate is guarded by local_id check, to avoid parameter error fault when deleting or terminating Thread object that was not started.
2017-11-25 18:09:37 +01:00
Christopher Haster 7e45aee8a5 Fixed mutex assert in armcc fopen and related memory leak
armcc fopen allocated a mutex using the retargeted system-level
_mutex_initialize function. Interestingly, malloc also uses this
same _mutex_initialization function, which prevents a full solution
relying on malloc. The solution previously implemented involved using
the rtx mutex pool for the first 8 mutexes, then falling back on
malloc.

The previous implementation relied on osMutexNew returning an error
on out-of-memory. An unrelated change causes osMutexNew to instead
assert (except for release mode). This meant if you exceed 8 system-
level mutexes in armcc you will hit an assert. Since the filesystem
code can call fopen an unlimited number of times, this is a problem.

Solution is to keep track of which static mutexes we've allocated, so
we know before calling osMutexNew if we need to call malloc.

Also _mutex_free never deallocated the malloced mutexes, which would
cause fopen to leak memory.
2017-11-22 16:53:19 -06:00
Russ Butler 93cf15d57c Fix and add test for ConditionVariable
Fix the circular linked list handling in ConditionVariable and add a
test to validate the linked list implementation.
2017-11-15 16:15:27 -06:00
Martin Kojtal 41eb565d9c
Merge pull request #5342 from ARMmbed/feature_cortex_a
Update CMSIS/RTX with Cortex-A support
2017-11-15 11:24:36 +00:00
Bartek Szatkowski 7bee352dd7 Update SysTick API usage for tickless mode 2017-11-10 09:53:42 +00:00
Bartek Szatkowski 4b354f80cf Update include paths to match updated CMSIS 2017-11-10 09:53:41 +00:00
Martin Kojtal fbd9e7eaf2
Merge pull request #5372 from SenRamakri/sen_PlatformDoxygenUpdates
Doxygen comments fixes
2017-11-09 16:38:45 +00:00
Martin Kojtal c45dd269f5
Merge pull request #3648 from c1728p9/condition_variable
Add ConditionVariable to mbed rtos
2017-11-09 16:38:02 +00:00
Martin Kojtal 242c8700a6
Merge pull request #5428 from kjbracey-arm/rtos_attrs
Shrink RTOS classes
2017-11-09 16:29:15 +00:00
Kevin Bracey 130fffaf8b Shrink RTOS classes
Various RTOS classes were storing their CMSIS-RTOS creation attribute
structure as a member, when it's not required after construction. Reduce
memory by eliminating this member.
2017-11-03 15:22:22 +02:00
Russ Butler 0c4e50abb3 Add ConditionVariable to mbed rtos
Add the ConditionVariable class to mbed rtos to provide easier and
safer synchronization.
2017-11-02 21:02:27 -05:00
Jimmy Brisson 3a05b63f1e
Merge pull request #5158 from YarivCol/master
RTOS : added empty and full functions to Mail and Queue
2017-11-02 10:46:06 -05:00
Jaeden Amero 75ad20b65f RTX5: uVisor: Switch threads very carefully
uVisor doesn't set the PSP of the target thread. The RTOS sets the PSP
of the target thread from the target thread's TCB. However, when
interrupts of higher priority than PendSV happen between the call to
uVisor to switch boxes, and the RTOS setting PSP, the uVisor vIRQ
interrupt handler will attempt to use an invalid PSP (the PSP from
before the box and thread switch). This leads to a crash. Make box and
thread switching atomic by disabling interrupts immediately before the
box switching until immediately after the new PSP is set.
2017-11-01 09:25:43 +00:00
Jaeden Amero 474f6c63ba RTX5: uVisor: Use OsEventObserver 2017-11-01 09:25:43 +00:00
Jaeden Amero 12a47f0031 RTX5: uVisor: Extend thread control block with context
OsEventObserver objects expect a context to be maintained per thread on
their behalf. Add this context to the thread control block and extend
the thread creation functions with the ability to supply a context.
2017-11-01 09:25:43 +00:00
Jaeden Amero f363ccbb59 RTX5: uVisor: Add OsEventObserver
Add the OsEventObserver mechanism. A client interested in receiving
notifications on certain OS events can register to receive notifications
with osRegisterForOsEvents. This is useful for clients like the secure
memory allocator, which observes thread switching events in order to
swap in and out different memory allocator objects.
2017-11-01 09:25:42 +00:00
Jaeden Amero 372b7b8b47 RTX5: uVisor: Defer to uVisor for SVCall priority
Only set the SVCall priority if uVisor is not present. If uVisor is
present, keep using whatever priorities it has already set up.
2017-11-01 09:25:42 +00:00
Bartek Szatkowski b8aa068def CMSIS/RTX: Rename asm files to upper case .S 2017-11-01 09:25:42 +00:00
Bartek Szatkowski 4523b5d266 CMSIS/RTX: Allow overwriting _mutex_initialize symbol for ARMC 2017-11-01 09:25:42 +00:00
Bartek Szatkowski 3f97e57364 CMSIS/RTX: Remove os_tick_gtim.c
This implementation of timer conflicts with the default ptim, we will
keep the default and let the timer override the implmenetation if
needed.
2017-11-01 09:25:42 +00:00
Bartek Szatkowski 1b131edd69 CMSIS/RTX: Patch RTX so irq_cm4f.s files work with no FPU targets 2017-11-01 09:25:42 +00:00
Bartek Szatkowski 5d6abd6572 CMSIS/RTX: Patch RTX includes to match mbed OS scheme 2017-11-01 09:25:42 +00:00
Bartek Szatkowski d5933f198c CMSIS/RTX: Patch RTX4 to preserve osThreadDef compatibility
mbed OS used older RTX4 version and with osThreadDef accepting only 3
parameters, to preserve compatibility we hardcode the 'instances'
parameter to 1.
2017-11-01 09:25:42 +00:00
Bartek Szatkowski a03591d6e3 CMSIS/RTX: Update CMSIS and RTX to 22b68c
This includes Cortex A support and directory reshuffle.
2017-11-01 09:25:42 +00:00
Russ Butler d98a011749 Ensure Thread stack is 8 byte aligned
Ensure both the stack and stack size used in the Thread class are
aligned to 8 bytes. This prevents the runtime error
"Thread 0 error -11: Unknown" due to incorrect stack alignment.
2017-10-31 11:58:18 -05:00
Senthil Ramakrishnan 3ad298488c Doxygen comment updates and fixes 2017-10-26 15:36:26 -05:00
Anna Bridge 9c1fd48529 Merge pull request #5278 from maciejbocianski/heap_and_stack_tests
Move heap_and_stack tests to TESTS/mbed_bootstrap
2017-10-20 10:25:07 +01:00
Martin Kojtal cbb8a1f994 Merge pull request #4947 from fkjagodzinski/rtostimer_tests
Rtostimer tests
2017-10-19 16:46:12 +01:00
Maciej Bocianski 9ab2a1df32 Move heap_and_stack tests 2017-10-13 08:23:55 +02:00
Russ Butler 209b9a9e62 Add error if OS tickrate is changed
The current mbed-os drivers rely on a tickrate of 1ms for timing.
This means that if OS_TICK_FREQ is set to any value other than 1000
then mbed-os driver will no longer delay for the correct amount of
time. To prevent this from happening this patch triggers a compile
time error if a tickrate other than 1m is used.
2017-10-05 16:31:14 -05:00
Jimmy Brisson 93459011b0 Merge pull request #5105 from deepikabhavnani/m33_files
Cortex-M33: Add RTX5 context switcher files
2017-10-02 10:38:35 -05:00
Jimmy Brisson b83b0b1678 Merge pull request #5098 from maciejbocianski/signal_fix
Doxygen comment fix for Thread class
2017-10-02 10:37:55 -05:00
Jimmy Brisson 74e592757f Merge pull request #5078 from v2422/master
Enable access to kernel tick information in ISR
2017-09-29 10:10:46 -05:00
Maciej Bocianski a3a73cb281 Doxygen comment fix for Thread class 2017-09-29 15:51:41 +02:00
Martin Kojtal 1fed1d003e Merge pull request #4684 from deepikabhavnani/thread_stack_issue
Add thread terminate hook
2017-09-22 11:31:39 +01:00
YarivCol ba7045392c fix doc in the function empty 2017-09-21 05:07:42 -07:00
YarivCol cf2378ecbd Added empty, full function to Queue and Mail 2017-09-21 03:09:45 -07:00
Anna Bridge 02a10e5974 Merge pull request #5094 from deepikabhavnani/m23_armc6
ARMC6 support for Cortex-M23
2017-09-19 10:25:33 +01:00
Deepika e235772ed5 Replaced older version of assembly file with 2016-2017 version from RTX 2017-09-14 23:15:12 -05:00
Deepika a2b53011be Added thread terminate hook
Hook was added in RTX4 code to assist test framework to log thread info on
thread terminate, which was not working with RTX5.
2017-09-14 16:21:48 -05:00
Jaeden Amero 0d34c3636e mbed_rtx_idle: uVisor: Don't attempt to sleep
When uVisor is enabled, don't attempt to sleep. Attempting to sleep will
fail, as per <https://github.com/ARMmbed/uvisor/issues/420>.
2017-09-14 17:20:23 +01:00
Deepika 1916000472 [Cortex-M33] Added RTX5 context switcher files 2017-09-14 10:07:18 -05:00
Deepika 60c600ac11 ARMC6 support for Cortex-M23 2017-09-13 17:07:05 -05:00
Anna Bridge 7b428916f5 Merge pull request #4949 from theotherjimmy/feature-armc5+armc6
NEW TOOLCHAIN: Add the ARMC6 Compiler
2017-09-13 10:39:15 +01:00
Viller Hsiao 6c5af87c73 Enable access to kernel tick information in ISR
The osKernelGetTickCount() is the only function to get kernel tick information,
however it's not allowed to access in ISR.

It's already enabled in API v2.1.1.
2017-09-12 17:54:35 +08:00