Commit Graph

59 Commits (a628eba212556a652b3b478c6b73312ced70e83d)

Author SHA1 Message Date
Russ Butler d5be92adb1 Fix define around EvrRtxKernelInitialized
Rename the define EVR_RTX_KERNEL_INITIALIZE_COMPLETED_DISABLE to
EVR_RTX_KERNEL_INITIALIZED_DISABLE so it matches the rest of RTX.
2018-08-25 20:41:11 -05:00
Russ Butler 6f7964b23f CMSIS/RTX: Remove the file os_tick_gtim.c
Cortex-A devices in mbed-os supply their own OS timer so the code
from RTX is not needed.
2018-08-25 20:41:11 -05:00
Bartek Szatkowski b7efe36125 CMSIS/RTX: Fix using FALSE/TRUE with preprocesor
(cherry picked from commit 1752803626)
2018-08-25 20:41:10 -05:00
deepikabhavnani 67b677d285 CMSIS/RTX: Pre-processor defines used for assembly
CMSIS repo does not support pre-processor defines, hence multiple assembly
files are added for secure/non-secure and floating point tools.

Mbed OS tools support assembly file pre-processing, but the build system
does not support multiple assembly files for each target, hence updating
the assembly files.

(cherry picked from commit 287121ffdc)
2018-08-25 20:41:09 -05:00
Bartek Szatkowski 4fd0daf9f5 CMSIS/RTX: Allow overwriting mutex ops for ARMC
(cherry picked from commit b88254809e)
2018-08-25 20:41:09 -05:00
Bartek Szatkowski 1be672d5f0 CMSIS/RTX: Patch RTX so irq_cm4f.s files work with no FPU targets
(cherry picked from commit cc2e0517e1)
2018-08-25 20:41:09 -05:00
Russ Butler 342841aa0f [CMSIS_5]: Updated to 0b521765 2018-08-25 20:41:00 -05:00
Russ Butler 5d0aac53bb Move Code to get Cortex A tick irqn
Move the function "mbed_get_a9_tick_irqn()" declared in os_tick.h
to SysTimer.h so it does not get overridden when RTX is updated.

This function was originally added in:
3d3e89097d
Fixes for RZ_A1H issue 6543
2018-08-25 20:40:17 -05:00
Oren Cohen 787317b7eb Remove uVisor from mbed-os 2018-08-22 16:36:59 +03:00
Deepika 357138468a Remove semicolon at the end of #define 2018-06-27 15:47:49 -05:00
Michael Coulter 3d3e89097d Fixes for RZ_A1H issue 6543
Removed debugging code, fixed errors indicated in the comments.
2018-06-11 13:30:17 -05:00
Vladimir Umek 4251af0248 RTX5 (Cortex-A): exception handling restructured, post processing moved after context save. 2018-05-28 19:36:42 +09:00
Vladimir Umek 165c663871 RTX5: fixed nesting interrupt handling (Cortex-A) 2018-05-28 13:55:35 +09:00
Vladimir Umek b6c4139328 RTX5: ignoring CPUID field in GIC implementation
updated interrupt handler for GCC and IAR
2018-05-28 13:54:44 +09:00
Vladimir Umek 0226b11b67 RTX5: disabled OS Tick interrupt during post processing in IRQ handler for Cortex-A devices 2018-05-28 12:52:11 +09:00
Bartek Szatkowski b4d5f0e10f CMSIS: Move non-config includes behind PTIM ifdef
That is to enabled integration with build-it-all Mbed OS type build
system.

Cherry-picked from CMSIS_5 repo: e8d0a476
2018-05-14 12:18:21 +01:00
Bartek Szatkowski 1752803626 CMSIS/RTX: Fix using FALSE/TRUE with preprocesor 2018-05-14 12:18:21 +01:00
Bartek Szatkowski a1fb51c283 RTX5: uVisor: Remove static from svcRtxKernelUnlock/Lock to support uVisor 2018-05-14 12:18:21 +01:00
Jaeden Amero 2f7a841e0e RTX5: uVisor: Defer to uVisor for SVCall priority
Only set the SVCall priority if uVisor is not present. If uVisor is
present, keep using whatever priorities it has already set up.
2018-05-14 12:18:21 +01:00
Jaeden Amero 32d04a08d0 RTX5: uVisor: Add OsEventObserver
Add the OsEventObserver mechanism. A client interested in receiving
notifications on certain OS events can register to receive notifications
with osRegisterForOsEvents. This is useful for clients like the secure
memory allocator, which observes thread switching events in order to
swap in and out different memory allocator objects.
2018-05-14 12:18:21 +01:00
Jaeden Amero 86b91beeca RTX5: uVisor: Extend thread control block with context
OsEventObserver objects expect a context to be maintained per thread on
their behalf. Add this context to the thread control block and extend
the thread creation functions with the ability to supply a context.
2018-05-14 12:18:21 +01:00
Jaeden Amero c250369803 RTX5: uVisor: Use OsEventObserver 2018-05-14 12:18:21 +01:00
Jaeden Amero 73a957997f RTX5: uVisor: Switch threads very carefully
uVisor doesn't set the PSP of the target thread. The RTOS sets the PSP
of the target thread from the target thread's TCB. However, when
interrupts of higher priority than PendSV happen between the call to
uVisor to switch boxes, and the RTOS setting PSP, the uVisor vIRQ
interrupt handler will attempt to use an invalid PSP (the PSP from
before the box and thread switch). This leads to a crash. Make box and
thread switching atomic by disabling interrupts immediately before the
box switching until immediately after the new PSP is set.
2018-05-14 12:18:21 +01:00
deepikabhavnani 287121ffdc CMSIS/RTX: Pre-processor defines used for assembly
CMSIS repo does not support pre-processor defines, hence multiple assembly
files are added for secure/non-secure and floating point tools.

Mbed OS tools support assembly file pre-processing, but the build system
does not support multiple assembly files for each target, hence updating
the assembly files.
2018-05-14 12:18:20 +01:00
Bartek Szatkowski b88254809e CMSIS/RTX: Allow overwriting mutex ops for ARMC 2018-05-14 12:18:20 +01:00
Bartek Szatkowski cc2e0517e1 CMSIS/RTX: Patch RTX so irq_cm4f.s files work with no FPU targets 2018-05-14 12:18:20 +01:00
Bartek Szatkowski 8afbd66763 [CMSIS_5]: Updated to 49ac527a 2018-05-14 12:18:20 +01:00
Tamas Kaman 8cc71dda75 Build issue for M33 core
Fix typo in irq_armv8mml.S

Signed-off-by: Tamas Kaman <tamas.kaman@arm.com>
2018-02-26 16:30:40 +01:00
Cruz Monrreal 4145cc0cf0
Merge pull request #6029 from deepikabhavnani/update_context_switch_files
RTX5: Pre-processor defines used for assembly
2018-02-16 10:15:03 -06:00
Deepika 4e89c9261f RTX changes pulled in from d20b8aad7f5e
RTX5: Added TrustZone Module Identifier configuration for Idle and Timer Thread
2018-02-08 15:52:17 -06:00
Deepika cf65e2b125 Pulling in CMSIS commit 05fa9d328a
Systick handler switch to secure/nonsecure issues addressed:
1. Switch to secure/nonsecure context save/restore is based on 6th bit in
LR register, correct the bug (R7 instead of LR was used for decision)
2. Prevent R7 from being corrupted in Sys_ContextSave
3. Branch when non-secure rather than secure
2018-02-08 12:40:20 -06:00
deepikabhavnani 919282322e RTX5: Pre-processor defines used for assembly
CMSIS repo does not support pre-processor defines, hence multiple assembly
files are added for secure/non-secure and floating point tools.

Mbed OS tools support assembly file pre-processing, but the build system
does not support multiple assembly files for each target, hence updating
the assembly files.
2018-02-06 21:53:55 -06:00
Vladimir Umek 0ff62f6b9e RTX5: fixed __get_PSP function for Cortex-A on IAR (#288) 2017-12-21 14:09:25 +09:00
Robert Rostohar 56602562ad Core(A): Updated __FPU_Enable function (VFP register count detection) 2017-12-21 14:09:25 +09:00
Robert Rostohar 461c215636 RTX5: Cortex-A exception handlers updated (VFP register count detection) 2017-12-21 14:09:24 +09:00
Christopher Haster 7e45aee8a5 Fixed mutex assert in armcc fopen and related memory leak
armcc fopen allocated a mutex using the retargeted system-level
_mutex_initialize function. Interestingly, malloc also uses this
same _mutex_initialization function, which prevents a full solution
relying on malloc. The solution previously implemented involved using
the rtx mutex pool for the first 8 mutexes, then falling back on
malloc.

The previous implementation relied on osMutexNew returning an error
on out-of-memory. An unrelated change causes osMutexNew to instead
assert (except for release mode). This meant if you exceed 8 system-
level mutexes in armcc you will hit an assert. Since the filesystem
code can call fopen an unlimited number of times, this is a problem.

Solution is to keep track of which static mutexes we've allocated, so
we know before calling osMutexNew if we need to call malloc.

Also _mutex_free never deallocated the malloced mutexes, which would
cause fopen to leak memory.
2017-11-22 16:53:19 -06:00
Jaeden Amero 75ad20b65f RTX5: uVisor: Switch threads very carefully
uVisor doesn't set the PSP of the target thread. The RTOS sets the PSP
of the target thread from the target thread's TCB. However, when
interrupts of higher priority than PendSV happen between the call to
uVisor to switch boxes, and the RTOS setting PSP, the uVisor vIRQ
interrupt handler will attempt to use an invalid PSP (the PSP from
before the box and thread switch). This leads to a crash. Make box and
thread switching atomic by disabling interrupts immediately before the
box switching until immediately after the new PSP is set.
2017-11-01 09:25:43 +00:00
Jaeden Amero 474f6c63ba RTX5: uVisor: Use OsEventObserver 2017-11-01 09:25:43 +00:00
Jaeden Amero 12a47f0031 RTX5: uVisor: Extend thread control block with context
OsEventObserver objects expect a context to be maintained per thread on
their behalf. Add this context to the thread control block and extend
the thread creation functions with the ability to supply a context.
2017-11-01 09:25:43 +00:00
Jaeden Amero f363ccbb59 RTX5: uVisor: Add OsEventObserver
Add the OsEventObserver mechanism. A client interested in receiving
notifications on certain OS events can register to receive notifications
with osRegisterForOsEvents. This is useful for clients like the secure
memory allocator, which observes thread switching events in order to
swap in and out different memory allocator objects.
2017-11-01 09:25:42 +00:00
Jaeden Amero 372b7b8b47 RTX5: uVisor: Defer to uVisor for SVCall priority
Only set the SVCall priority if uVisor is not present. If uVisor is
present, keep using whatever priorities it has already set up.
2017-11-01 09:25:42 +00:00
Bartek Szatkowski b8aa068def CMSIS/RTX: Rename asm files to upper case .S 2017-11-01 09:25:42 +00:00
Bartek Szatkowski 4523b5d266 CMSIS/RTX: Allow overwriting _mutex_initialize symbol for ARMC 2017-11-01 09:25:42 +00:00
Bartek Szatkowski 3f97e57364 CMSIS/RTX: Remove os_tick_gtim.c
This implementation of timer conflicts with the default ptim, we will
keep the default and let the timer override the implmenetation if
needed.
2017-11-01 09:25:42 +00:00
Bartek Szatkowski 1b131edd69 CMSIS/RTX: Patch RTX so irq_cm4f.s files work with no FPU targets 2017-11-01 09:25:42 +00:00
Bartek Szatkowski 5d6abd6572 CMSIS/RTX: Patch RTX includes to match mbed OS scheme 2017-11-01 09:25:42 +00:00
Bartek Szatkowski a03591d6e3 CMSIS/RTX: Update CMSIS and RTX to 22b68c
This includes Cortex A support and directory reshuffle.
2017-11-01 09:25:42 +00:00
Anna Bridge 9c1fd48529 Merge pull request #5278 from maciejbocianski/heap_and_stack_tests
Move heap_and_stack tests to TESTS/mbed_bootstrap
2017-10-20 10:25:07 +01:00
Maciej Bocianski 9ab2a1df32 Move heap_and_stack tests 2017-10-13 08:23:55 +02:00
Jimmy Brisson 93459011b0 Merge pull request #5105 from deepikabhavnani/m33_files
Cortex-M33: Add RTX5 context switcher files
2017-10-02 10:38:35 -05:00