On M2351, some spaces like SYS/CLK are hard-wired to secure and cannot change.
To access these spaces from non-secure world, we must provide platform-specific NSC
functions. With TFM introduced, we must synchronize NSC calls into TFM to keep TFM
in sync instead of straight NSC calls. To achieve this goal, we go with the following
approach:
1. Like PSA APIs, enforce locked entry through tfm_ns_lock_dispatch().
2. Run platform-specific secure functions in default secure partition, in which SYS/CLK
spaces have been configured to be accessible.
In this new memory partition, secure program is most simplified and non-secure program can make most use of memory for its large application like Pelion:
- Flash (512KiB in total): 64KiB for secure and 448KiB for nonsecure.
- SRAM (96KiB in total): 8KiB for secure and 88KiB for nonsecure.
Besides, to make secure program fit into 8KiB:
- Decrease boot stack size to 0x600 bytes
- Remove serial support
Fix SPI module index error in modidx_ns_tab table in CLK_SetModuleClock_S().
Need to update secure image for this bugfix.
This is also to fix FPGA CI test mbed_hal_fpga_ci_test_shield-spi/
SPI - init/free test all pins.
Without free-up of peripheral pins, peripheral pins of the same peripheral may
share by multiple ports after port iteration, and this peripheral may fail with
pin interference.
In Nuvoton, only new-design chips support GPIO input pull-high/pull-low modes.
Targets not supporting this feature are listed below:
- NUMAKER_PFM_NANO130
- NUMAKER_PFM_NUC472
- NUMAKER_PFM_M453
Fix logic error on replying NACK at the end of transfer.
This is also to fix FPGA CI test mbed_hal_fpga_ci_test_shield-i2c/
i2c - test single byte read i2c API.
Better IP initialization sequence:
1. Configure IP pins
2. Select IP clock source and then enable it
3. Reset the IP (SYS_ResetModule)
NOTE1: IP reset takes effect regardless of IP clock. So it doesn't matter if
IP clock enable is before IP reset.
NOTE2: Non-configured pins may disturb IP's state, so IP pinout first and then
IP reset.
NOTE3: IP reset at the end of IP initialization sequence can cover unexpected
situation.
1. Add missing header file for mbed_mpu_manager_lock_ram_execution()/
mbed_mpu_manager_unlock_ram_execution() to avoid compile warning.
2. Locate delay_loop_code() on 16-byte boundary (sync to common version).
3. Optimize delay_loop macro (sync to common version).
At high HCLK rate, M2351 cannot provide zero-wait-state flash performance. Besides,
cache is forcibly turned off for non-secure land for internal reason. We locate
'delay_loop_code' from flash to SRAM to achieve zero-wait-state performance.
Reimplement atomic code in inline assembly. This can improve
optimisation, and avoids potential architectural problems with using
LDREX/STREX intrinsics.
API further extended:
* Bitwise operations (fetch_and/fetch_or/fetch_xor)
* fetch_add and fetch_sub (like incr/decr, but returning old value -
aligning with C++11)
* compare_exchange_weak
* Explicit memory order specification
* Basic freestanding template overloads for C++
This gives our existing C implementation essentially all the functionality
needed by C++11.
An actual Atomic<T> template based upon these C functions could follow.
Nuvoton M2351 was including generic core_armv8mbl.h from CMSIS - we
need it to be more specific to identify the specific core for
wait_ns. Change to core_cm23.h.
Chun-Chieh Li
Martin Kojtal
cyliangtw
Anna Bridge
Kevin Bracey
Cruz Monrreal
Deepika