mirror of https://github.com/ARMmbed/mbed-os.git
Merge pull request #10959 from OpenNuvoton/nuvoton_m2351_psa
M2351: Support TFM level 1pull/12154/head
Martin Kojtal
GitHub
commit
af03f839e2
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@ -42,6 +42,7 @@ static const osMutexAttr_t ns_lock_attrib = {
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/**
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* \brief NS world, NS lock based dispatcher
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*/
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__attribute__((weak))
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uint32_t tfm_ns_lock_dispatch(veneer_fn fn,
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uint32_t arg0, uint32_t arg1,
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uint32_t arg2, uint32_t arg3)
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@ -70,6 +71,7 @@ uint32_t tfm_ns_lock_dispatch(veneer_fn fn,
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/**
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* \brief NS world, Init NS lock
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*/
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__attribute__((weak))
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enum tfm_status_e tfm_ns_lock_init()
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{
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if (ns_lock.init == false) {
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@ -31,6 +31,10 @@
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"internal_size": "0x200000",
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"internal_base_address": "0x00200000"
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},
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"NU_PFM_M2351_S": {
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"internal_size": "0x8000",
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"internal_base_address": "(PSA_SECURE_ROM_START + PSA_SECURE_ROM_SIZE - 0x1000 - MBED_CONF_STORAGE_TDB_INTERNAL_INTERNAL_SIZE)"
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},
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"MCU_PSOC6": {
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"internal_size": "0x10000"
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}
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@ -216,6 +216,9 @@
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"crash-capture-enabled": true,
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"fatal-error-auto-reboot-enabled": true
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},
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"NU_PFM_M2351": {
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"stdio-baud-rate": 115200
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},
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"NRF52840_DK": {
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"crash-capture-enabled": true,
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"fatal-error-auto-reboot-enabled": true
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@ -0,0 +1,49 @@
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Permissive Binary License
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Version 1.0, September 2015
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Redistribution. Redistribution and use in binary form, without
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modification, are permitted provided that the following conditions are
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met:
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1) Redistributions must reproduce the above copyright notice and the
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following disclaimer in the documentation and/or other materials
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provided with the distribution.
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2) Unless to the extent explicitly permitted by law, no reverse
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engineering, decompilation, or disassembly of this software is
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permitted.
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3) Redistribution as part of a software development kit must include the
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accompanying file named "DEPENDENCIES" and any dependencies listed in
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that file.
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4) Neither the name of the copyright holder nor the names of its
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contributors may be used to endorse or promote products derived from
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this software without specific prior written permission.
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Limited patent license. The copyright holders (and contributors) grant a
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worldwide, non-exclusive, no-charge, royalty-free patent license to
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make, have made, use, offer to sell, sell, import, and otherwise
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transfer this software, where such license applies only to those patent
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claims licensable by the copyright holders (and contributors) that are
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necessarily infringed by this software. This patent license shall not
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apply to any combinations that include this software. No hardware is
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licensed hereunder.
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If you institute patent litigation against any entity (including a
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cross-claim or counterclaim in a lawsuit) alleging that the software
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itself infringes your patent(s), then your rights granted under this
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license shall terminate as of the date such litigation is filed.
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DISCLAIMER. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
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CONTRIBUTORS "AS IS." ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT
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NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
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TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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@ -0,0 +1,11 @@
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# M2351 pre-built secure images for PSA
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This directory tree contains secure images released under Permissive Binary License.
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Built using Arm Compiler - version 6.10 or afterwards
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These images were compiled by the following command:
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```sh
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python ./tools/psa/release.py -m NU_PFM_M2351_S -t ARMC6
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```
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Load Diff
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@ -0,0 +1,157 @@
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/*
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* Copyright (c) 2019, Nuvoton Technology Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include <stdint.h>
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#include <stdbool.h>
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#include "cmsis.h"
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#include "cmsis_os2.h"
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#include "tfm_ns_lock.h"
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#include "mbed_critical.h"
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#include "mbed_assert.h"
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#include "mbed_error.h"
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/* Approach to serialization of NS secure calls required by TF-M secure world
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*
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* Default implementation of NS interface uses mutex to meet the requirement,
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* but it cannot support NS secure call in interrupt-disabled context. Instead,
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* in this override, NS secure call is guaranteed to be non-preemptive during
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* this period by locking kernel scheduler. Apparently, this approach has one
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* weakness: all other threads are also locked during this period. Until there's
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* a better approach coming out, we can just use this expedient one.
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*
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* For the 'lock kernel scheduler' approach to work thoroughly, we must also
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* address some side issues:
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*
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* - Prohibit NS secure call from ISR except SVC, so non-preemptive doesn't break.
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* - Allow NS secure call in SVC context because it is synchronous. Here, we lock
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* interrupt instead of kernel scheduler because svcRtxKernelLock()/svcRtxKernelRestoreLock(...)
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* are inaccessible outside rtx_kernel.c. Currently, this is rare case and would cause
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* little trouble (see known paths below).
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* - Call into secure world straight in interrupt-disabled context. When in
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* interrupt-disabled context, NS secure call is guaranteed to be non-preemptive
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* naturally.
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* - Call into secure world straight at pre-rtos stage. When at pre-rtos stage,
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* NS secure call is guaranteed to be non-preemptive naturally.
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* - osKernelLock() will error when kernel state is 'osKernelSuspended'. Address
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* it separately. Known path of NS secure call when kernel state is 'osKernelSuspended':
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* - default idle thread > osKernelSuspend() > lp_ticker_init > SYS_ResetModule_S/
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* CLK_SetModuleClock_S/CLK_EnableModuleClock_S
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*
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* Known paths of NS secure call in interrupt-disabled context:
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* - mbed-os/platform/mbed_sleep_manager.c > sleep_manager_sleep_auto >
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* hal_sleep/hal_deepsleep > nu_idle_s/nu_powerdown_s
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* - mbed-os/hal/LowPowerTickerWrapper.cpp > LowPowerTickerWrapper::init >
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* lp_ticker_init > SYS_ResetModule_S/CLK_SetModuleClock_S/CLK_EnableModuleClock_S
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* - mbed-os/platform/mbed_board.c > mbed_die > pin_function_s
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* - mbed-os-tests-mbed_hal-rtc > rtc_write_read_test > rtc_write >
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* CLK_IsRTCClockEnabled_S
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*
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* Known paths of NS secure call in SVC context:
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* - In tickless mode, osKernelStart > svcRtxKernelStart > OS_Tick_Enable >
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* us_ticker_init/lp_ticker_init > SYS_ResetModule_S/CLK_SetModuleClock_S/
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* CLK_EnableModuleClock_S
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*/
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struct ns_interface_state
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{
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bool init; // Flag if kernel has initialized (and then scheduler
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// has started)
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};
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static struct ns_interface_state ns_interface = {
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.init = false
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};
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/* Override tfm_ns_lock_init()
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*
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* On Mbed OS, we expect this function is called before kernel scheduler is
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* started so that we can distinguish pre-rtos and rtos stage to meet the
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* requirement of serialization of NS secure calls.
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*/
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enum tfm_status_e tfm_ns_lock_init()
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{
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if (!ns_interface.init) {
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osKernelState_t kernel_state = osKernelGetState();
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MBED_ASSERT(kernel_state == osKernelInactive || kernel_state == osKernelReady);
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ns_interface.init = true;
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}
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return TFM_SUCCESS;
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}
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/* Override tfm_ns_lock_dispatch(...) */
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uint32_t tfm_ns_lock_dispatch(veneer_fn fn,
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uint32_t arg0, uint32_t arg1,
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uint32_t arg2, uint32_t arg3)
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{
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/* Prohibit NS secure call from ISR except SVC, so non-preemptive doesn't break */
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uint32_t ipsr = __get_IPSR();
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if (ipsr == 11U) {
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/* Allow NS secure call in SVC context because it is synchronous. Here,
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* we lock interrupt instead of kernel scheduler because svcRtxKernelLock()/
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* svcRtxKernelRestoreLock(...) are inaccessible outside rtx_kernel.c. */
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core_util_critical_section_enter();
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uint32_t result = fn(arg0, arg1, arg2, arg3);
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core_util_critical_section_exit();
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return result;
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} else if (ipsr) {
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MBED_ERROR1(MBED_MAKE_ERROR(MBED_MODULE_KERNEL, MBED_ERROR_CODE_PROHIBITED_IN_ISR_CONTEXT), "Prohibited in ISR context", (uintptr_t) fn);
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}
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/* Call into secure world straight in interrupt-disabled context because
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* NS secure call is non-preemptive naturally */
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if (!core_util_are_interrupts_enabled()) {
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return fn(arg0, arg1, arg2, arg3);
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}
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/* Call into secure world straight at pre-rtos stage because NS secure
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* call is non-preemptive naturally */
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if (!ns_interface.init) {
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return fn(arg0, arg1, arg2, arg3);
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}
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/* osKernelLock() will error when kernel state is 'osKernelSuspended'. Address
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* it separately. */
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osKernelState_t kernel_state = osKernelGetState();
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if (kernel_state == osKernelSuspended) {
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return fn(arg0, arg1, arg2, arg3);
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} else if (kernel_state == osKernelError) {
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MBED_ERROR1(MBED_MAKE_ERROR(MBED_MODULE_KERNEL, MBED_ERROR_CODE_UNKNOWN), "RTX kernel state error", (uintptr_t) fn);
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}
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/* Lock kernel scheduler and save previous lock state for restore */
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int32_t lock_state = osKernelLock();
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if (lock_state == osError) {
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MBED_ERROR1(MBED_MAKE_ERROR(MBED_MODULE_KERNEL, MBED_ERROR_CODE_UNKNOWN), "Unknown RTX error", (uintptr_t) fn);
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}
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MBED_ASSERT(lock_state >= 0);
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/* NS secure call is non-preemptive because kernel scheduler is locked */
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uint32_t result = fn(arg0, arg1, arg2, arg3);
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/* Restore previous lock state */
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lock_state = osKernelRestoreLock(lock_state);
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if (lock_state == osError) {
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MBED_ERROR1(MBED_MAKE_ERROR(MBED_MODULE_KERNEL, MBED_ERROR_CODE_UNKNOWN), "Unknown RTX error", (uintptr_t) fn);
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}
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MBED_ASSERT(lock_state >= 0);
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return result;
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}
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@ -0,0 +1,26 @@
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/*
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* Copyright (c) 2018-2019, Nuvoton Technology Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
|
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* You may obtain a copy of the License at
|
||||
*
|
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
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*/
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#include "cmsis.h"
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#include "cmsis_nvic_virtual.h"
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#include "psa/lifecycle.h"
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void NVIC_SystemReset(void)
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{
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mbed_psa_system_reset();
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}
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@ -0,0 +1,50 @@
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/*
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* Copyright (c) 2018-2019, Nuvoton Technology Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
|
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*
|
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* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
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#ifndef NVIC_VIRTUAL_H
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#define NVIC_VIRTUAL_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* NVIC functions */
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#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
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#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
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#define NVIC_EnableIRQ __NVIC_EnableIRQ
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#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
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#define NVIC_DisableIRQ __NVIC_DisableIRQ
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#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
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#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
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#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
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#define NVIC_GetActive __NVIC_GetActive
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#define NVIC_SetPriority __NVIC_SetPriority
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#define NVIC_GetPriority __NVIC_GetPriority
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/**
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* \brief Overriding the default CMSIS system reset implementation by calling
|
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* secure TFM service.
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*
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*/
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void NVIC_SystemReset(void);
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#ifdef __cplusplus
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}
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#endif
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#endif
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@ -0,0 +1,60 @@
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#! armclang -E
|
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|
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/*
|
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* Copyright (c) 2018-2019, Nuvoton Technology Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
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#include "../../../device/partition_M2351_mem.h"
|
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|
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#if !defined(MBED_BOOT_STACK_SIZE)
|
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#define MBED_BOOT_STACK_SIZE 0x400
|
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#endif
|
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|
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LR_IROM1 MBED_APP_START
|
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{
|
||||
/* load address = execution address */
|
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ER_IROM1 +0
|
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{
|
||||
*(RESET, +First)
|
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*(InRoot$$Sections)
|
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.ANY (+RO)
|
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}
|
||||
|
||||
ARM_LIB_STACK MBED_RAM_APP_START EMPTY MBED_BOOT_STACK_SIZE
|
||||
{
|
||||
}
|
||||
|
||||
/* Reserve for vectors
|
||||
*
|
||||
* Vector table base address is required to be 128-byte aligned at a minimum.
|
||||
* A PE might impose further restrictions on it. */
|
||||
ER_IRAMVEC AlignExpr(+0, 128) EMPTY (4*(16 + 102))
|
||||
{
|
||||
}
|
||||
|
||||
RW_IRAM1 AlignExpr(+0, 16)
|
||||
{
|
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.ANY (+RW +ZI)
|
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}
|
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|
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ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_APP_START + MBED_RAM_APP_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16))
|
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{
|
||||
}
|
||||
}
|
||||
|
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ScatterAssert(LoadLimit(LR_IROM1) <= (MBED_APP_START + MBED_APP_SIZE))
|
||||
ScatterAssert(ImageLimit(ARM_LIB_HEAP) <= MBED_RAM_APP_START + MBED_RAM_APP_SIZE)
|
||||
|
|
@ -0,0 +1,223 @@
|
|||
/*
|
||||
* Copyright (c) 2018-2019, Nuvoton Technology Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Nuvoton M2351 GCC linker script file
|
||||
*/
|
||||
|
||||
#include "../../../device/partition_M2351_mem.h"
|
||||
|
||||
#if !defined(MBED_BOOT_STACK_SIZE)
|
||||
#define MBED_BOOT_STACK_SIZE 0x400
|
||||
#endif
|
||||
|
||||
StackSize = MBED_BOOT_STACK_SIZE;
|
||||
|
||||
MEMORY
|
||||
{
|
||||
VECTORS (rx) : ORIGIN = MBED_APP_START, LENGTH = 0x00000400
|
||||
FLASH (rx) : ORIGIN = MBED_APP_START + 0x400, LENGTH = MBED_APP_SIZE - 0x400
|
||||
RAM_INTERN (rwx) : ORIGIN = MBED_RAM_APP_START, LENGTH = MBED_RAM_APP_SIZE
|
||||
}
|
||||
|
||||
/**
|
||||
* Must match cmsis_nvic.h
|
||||
*/
|
||||
__vector_size = 4 * (16 + 102);
|
||||
|
||||
|
||||
/* Linker script to place sections and symbol values. Should be used together
|
||||
* with other linker script that defines memory regions FLASH and RAM.
|
||||
* It references following symbols, which must be defined in code:
|
||||
* Reset_Handler : Entry of reset handler
|
||||
*
|
||||
* It defines following symbols, which code can use without definition:
|
||||
* __exidx_start
|
||||
* __exidx_end
|
||||
* __etext
|
||||
* __data_start__
|
||||
* __preinit_array_start
|
||||
* __preinit_array_end
|
||||
* __init_array_start
|
||||
* __init_array_end
|
||||
* __fini_array_start
|
||||
* __fini_array_end
|
||||
* __data_end__
|
||||
* __bss_start__
|
||||
* __bss_end__
|
||||
* __end__
|
||||
* end
|
||||
* __HeapLimit
|
||||
* __StackLimit
|
||||
* __StackTop
|
||||
* __stack
|
||||
*/
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
.isr_vector :
|
||||
{
|
||||
__vector_table = .;
|
||||
KEEP(*(.vector_table))
|
||||
. = ALIGN(8);
|
||||
} > VECTORS
|
||||
|
||||
.copy.table : ALIGN(4)
|
||||
{
|
||||
__copy_table_start__ = .;
|
||||
LONG (LOADADDR(.data))
|
||||
LONG (ADDR(.data))
|
||||
LONG (SIZEOF(.data))
|
||||
__copy_table_end__ = .;
|
||||
} > FLASH
|
||||
|
||||
.zero.table : ALIGN(4)
|
||||
{
|
||||
__zero_table_start__ = .;
|
||||
LONG (ADDR(.bss))
|
||||
LONG (SIZEOF(.bss))
|
||||
__zero_table_end__ = .;
|
||||
} > FLASH
|
||||
|
||||
.text :
|
||||
{
|
||||
*(.text*)
|
||||
|
||||
KEEP(*(.init))
|
||||
KEEP(*(.fini))
|
||||
|
||||
/* .ctors */
|
||||
*crtbegin.o(.ctors)
|
||||
*crtbegin?.o(.ctors)
|
||||
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
|
||||
*(SORT(.ctors.*))
|
||||
*(.ctors)
|
||||
|
||||
/* .dtors */
|
||||
*crtbegin.o(.dtors)
|
||||
*crtbegin?.o(.dtors)
|
||||
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
|
||||
*(SORT(.dtors.*))
|
||||
*(.dtors)
|
||||
|
||||
*(.rodata*)
|
||||
|
||||
KEEP(*(.eh_frame*))
|
||||
} > FLASH
|
||||
|
||||
/* Stack Pointer (SP) configuration with GCC_ARM
|
||||
*
|
||||
* SP would go through the following configuration sequence:
|
||||
* (1) SP(MSP) <- Entry 0 of vector table (on H/W reset)
|
||||
* (2) Switch SP from MSP to PSP in startup file (as TFM requests)
|
||||
* (3) SP(PSP) <- __stack (in _start(), C/C++ runtime initialization)
|
||||
*
|
||||
* S(3) may cause SP(PSP) incorrectly configured. To avoid this error, __stack
|
||||
* is assigned conditionally according to Secure PSA or not.
|
||||
*/
|
||||
|
||||
.stack (NOLOAD) :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
__StackLimit = .;
|
||||
. += StackSize;
|
||||
__StackTop = .;
|
||||
} > RAM_INTERN
|
||||
|
||||
PROVIDE(__stack = __StackTop);
|
||||
|
||||
.ARM.extab :
|
||||
{
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
} > FLASH
|
||||
|
||||
.ARM.exidx :
|
||||
{
|
||||
__exidx_start = .;
|
||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||
__exidx_end = .;
|
||||
} > FLASH
|
||||
|
||||
/* Relocate vector table in SRAM */
|
||||
.isr_vector.reloc (NOLOAD) :
|
||||
{
|
||||
. = ALIGN(1 << LOG2CEIL(__vector_size));
|
||||
PROVIDE(__start_vector_table__ = .);
|
||||
. += __vector_size;
|
||||
PROVIDE(__end_vector_table__ = .);
|
||||
} > RAM_INTERN
|
||||
|
||||
.data :
|
||||
{
|
||||
PROVIDE( __etext = LOADADDR(.data) );
|
||||
|
||||
__data_start__ = .;
|
||||
*(vtable)
|
||||
*(.data*)
|
||||
|
||||
. = ALIGN(8);
|
||||
/* preinit data */
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP(*(.preinit_array))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
|
||||
. = ALIGN(8);
|
||||
/* init data */
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP(*(SORT(.init_array.*)))
|
||||
KEEP(*(.init_array))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
|
||||
. = ALIGN(8);
|
||||
/* finit data */
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP(*(SORT(.fini_array.*)))
|
||||
KEEP(*(.fini_array))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
|
||||
/* All data end */
|
||||
. = ALIGN(32);
|
||||
__data_end__ = .;
|
||||
|
||||
} >RAM_INTERN AT>FLASH
|
||||
|
||||
.bss (NOLOAD):
|
||||
{
|
||||
__bss_start__ = .;
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
__bss_end__ = .;
|
||||
} > RAM_INTERN
|
||||
|
||||
.heap (NOLOAD) :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
__end__ = .;
|
||||
end = __end__;
|
||||
*(.heap*);
|
||||
. += (ORIGIN(RAM_INTERN) + LENGTH(RAM_INTERN) - .);
|
||||
__HeapLimit = .;
|
||||
} > RAM_INTERN
|
||||
Image$$ARM_LIB_HEAP$$ZI$$Base = ADDR(.heap);
|
||||
Image$$ARM_LIB_HEAP$$ZI$$Limit = ADDR(.heap) + SIZEOF(.heap);
|
||||
|
||||
PROVIDE(__heap_size = SIZEOF(.heap));
|
||||
PROVIDE(__mbed_sbrk_start = ADDR(.heap));
|
||||
PROVIDE(__mbed_krbs_start = ADDR(.heap) + SIZEOF(.heap));
|
||||
}
|
||||
|
|
@ -0,0 +1,64 @@
|
|||
/*
|
||||
* Copyright (c) 2018-2019, Nuvoton Technology Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
|
||||
include "../../../device/partition_M2351_mem.icf";
|
||||
|
||||
if (! isdefinedsymbol(MBED_BOOT_STACK_SIZE)) {
|
||||
define symbol MBED_BOOT_STACK_SIZE = 0x400;
|
||||
}
|
||||
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = MBED_APP_START;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_ROM_start__ = MBED_APP_START;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = MBED_APP_START + MBED_APP_SIZE - 1;
|
||||
define symbol __ICFEDIT_region_IRAM_start__ = MBED_RAM_APP_START;
|
||||
define symbol __ICFEDIT_region_IRAM_end__ = MBED_RAM_APP_START + MBED_RAM_APP_SIZE - 1;
|
||||
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x400;
|
||||
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
define region IRAM_region = mem:[from __ICFEDIT_region_IRAM_start__ to __ICFEDIT_region_IRAM_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { };
|
||||
/* NOTE: Vector table base requires to be aligned to the power of vector table size. Give a safe value here. */
|
||||
define block IRAMVEC with alignment = 1024, size = 4 * (16 + 102) { };
|
||||
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem: __ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
place in ROM_region { readonly };
|
||||
place at address mem: NU_TZ_NSC_START { block Image$$ER_IROM_NSC }
|
||||
|
||||
place at start of IRAM_region { block CSTACK };
|
||||
place in IRAM_region { block IRAMVEC };
|
||||
place in IRAM_region { readwrite };
|
||||
place in IRAM_region { block HEAP };
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2018-2020, Nuvoton Technology Corporation
|
||||
* Copyright (c) 2018-2019, Nuvoton Technology Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
|
|
|
|||
|
|
@ -0,0 +1,58 @@
|
|||
/*
|
||||
* Copyright (c) 2018-2019, Nuvoton Technology Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef __FLASH_LAYOUT_H__
|
||||
#define __FLASH_LAYOUT_H__
|
||||
|
||||
#if TFM_LVL > 0
|
||||
|
||||
/* Shared data area between bootloader and runtime firmware
|
||||
*
|
||||
* Shared data area is allocated at the beginning of the RAM. It is overlapping
|
||||
* with TF-M Secure code's MSP stack on purpose:
|
||||
* 1. MSP stack grows to the beginning of RAM
|
||||
* 2. Shared data reads out by partitions from the beginning of RAM
|
||||
*
|
||||
* In Nuvoton's TFM port, TFM's bootloader is not used. These macros defined here are
|
||||
* just to pass TFM compile.
|
||||
*/
|
||||
#if (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
|
||||
extern uint32_t Image$$ARM_LIB_STACK_MSP$$ZI$$Base;
|
||||
extern uint32_t Image$$ARM_LIB_STACK_MSP$$ZI$$Length;
|
||||
#define MSP_STACK_LIMIT ((uint32_t) &Image$$ARM_LIB_STACK_MSP$$ZI$$Base)
|
||||
#define MSP_STACK_SIZE ((uint32_t) &Image$$ARM_LIB_STACK_MSP$$ZI$$Length)
|
||||
|
||||
#elif defined(__ICCARM__)
|
||||
extern uint32_t CSTACK$$Base;
|
||||
extern uint32_t CSTACK$$Length;
|
||||
#define MSP_STACK_LIMIT ((uint32_t) &CSTACK$$Base)
|
||||
#define MSP_STACK_SIZE ((uint32_t) &CSTACK$$Length)
|
||||
|
||||
#elif defined(__GNUC__)
|
||||
extern uint32_t __StackLimit;
|
||||
extern uint32_t __StackTop;
|
||||
#define MSP_STACK_LIMIT ((uint32_t) &__StackLimit)
|
||||
#define MSP_STACK_SIZE (((uint32_t) &__StackTop) - ((uint32_t) &__StackLimit))
|
||||
|
||||
#endif
|
||||
|
||||
#define BOOT_TFM_SHARED_DATA_BASE MSP_STACK_LIMIT
|
||||
#define BOOT_TFM_SHARED_DATA_SIZE 0x400
|
||||
|
||||
#endif /* #if TFM_LVL > 0 */
|
||||
#endif /* __FLASH_LAYOUT_H__ */
|
||||
|
|
@ -0,0 +1,24 @@
|
|||
/*
|
||||
* Copyright (c) 2018-2019, Nuvoton Technology Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef __PLATFORM_RETARGET_H__
|
||||
#define __PLATFORM_RETARGET_H__
|
||||
|
||||
/* Dummy for Nuvoton's M2351 TFM port */
|
||||
|
||||
#endif /* __PLATFORM_RETARGET_H__ */
|
||||
|
|
@ -0,0 +1,39 @@
|
|||
/*
|
||||
* Copyright (c) 2018-2019, Nuvoton Technology Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef __REGION_DEFS_H__
|
||||
#define __REGION_DEFS_H__
|
||||
|
||||
#include "partition_M2351_mem.h"
|
||||
|
||||
#define S_CODE_START (NU_ROM_START_S)
|
||||
#define S_CODE_SIZE (NU_ROM_SIZE_S)
|
||||
|
||||
#define S_DATA_START (NU_RAM_START_S)
|
||||
#define S_DATA_SIZE (NU_RAM_SIZE_S)
|
||||
#define S_DATA_LIMIT (NU_RAM_START_S + NU_RAM_SIZE_S - 1)
|
||||
|
||||
#define NS_CODE_START (NU_ROM_START_NS)
|
||||
#define NS_CODE_SIZE (NU_ROM_SIZE_NS)
|
||||
#define NS_CODE_LIMIT (NU_ROM_START_NS + NU_ROM_SIZE_NS - 1)
|
||||
|
||||
#define NS_DATA_START (NU_RAM_START_NS)
|
||||
#define NS_DATA_SIZE (NU_RAM_SIZE_NS)
|
||||
#define NS_DATA_LIMIT (NU_RAM_START_NS + NU_RAM_SIZE_NS - 1)
|
||||
|
||||
#endif /* __REGION_DEFS_H__ */
|
||||
|
|
@ -0,0 +1,87 @@
|
|||
/*
|
||||
* Copyright (c) 2018-2019, Nuvoton Technology Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#include <stdio.h>
|
||||
#include "platform/include/tfm_spm_hal.h"
|
||||
#include "spm_api.h"
|
||||
#include "spm_db.h"
|
||||
#include "target_cfg.h"
|
||||
#include "secure_utilities.h"
|
||||
#include "mbed_error.h"
|
||||
|
||||
void tfm_spm_hal_init_isolation_hw(void)
|
||||
{
|
||||
TZ_SAU_Setup();
|
||||
SCU_Setup();
|
||||
FMC_NSBA_Setup();
|
||||
}
|
||||
|
||||
void tfm_spm_hal_configure_default_isolation(
|
||||
const struct tfm_spm_partition_platform_data_t *platform_data)
|
||||
{
|
||||
if (platform_data) {
|
||||
/* TODO */
|
||||
}
|
||||
}
|
||||
|
||||
#if TFM_LVL > 1
|
||||
|
||||
/* TODO */
|
||||
#error("TFM level 2/3 are not supported yet")
|
||||
|
||||
#endif
|
||||
|
||||
void tfm_spm_hal_setup_isolation_hw(void)
|
||||
{
|
||||
#if TFM_LVL > 1
|
||||
|
||||
/* TODO */
|
||||
#error("TFM level 2/3 are not supported yet")
|
||||
|
||||
#endif
|
||||
}
|
||||
|
||||
void SCU_IRQHandler(void)
|
||||
{
|
||||
uint32_t scu_sv_ints = SCU_GET_INT_FLAG(NU_SCU_SV_MSAK);
|
||||
|
||||
/* TODO: More detailed debug message */
|
||||
LOG_MSG("Oops... MPC fault!!!");
|
||||
|
||||
/* Clear SCU interrupt flag and pending SCU IRQ */
|
||||
SCU_CLR_INT_FLAG(scu_sv_ints);
|
||||
NVIC_ClearPendingIRQ(SCU_IRQn);
|
||||
|
||||
/* Inform TF-M core that isolation boundary has been violated */
|
||||
tfm_access_violation_handler();
|
||||
}
|
||||
|
||||
uint32_t tfm_spm_hal_get_ns_VTOR(void)
|
||||
{
|
||||
return memory_regions.non_secure_code_start;
|
||||
}
|
||||
|
||||
uint32_t tfm_spm_hal_get_ns_MSP(void)
|
||||
{
|
||||
return *((uint32_t *)memory_regions.non_secure_code_start);
|
||||
}
|
||||
|
||||
uint32_t tfm_spm_hal_get_ns_entry_point(void)
|
||||
{
|
||||
return *((uint32_t *)(memory_regions.non_secure_code_start+ 4));
|
||||
}
|
||||
|
|
@ -0,0 +1,99 @@
|
|||
/*
|
||||
* Copyright (c) 2018-2019, Nuvoton Technology Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#include "cmsis.h"
|
||||
#include "target_cfg.h"
|
||||
#include "tfm_secure_api.h"
|
||||
|
||||
/* Why rename this file to .cpp from .c
|
||||
*
|
||||
* NU_TZ_NSC_REGION_START/NU_TZ_NSC_REGION_SIZE would consist of linker-generated symbols.
|
||||
* To avoid compile error 'initializer element is not a compile-time constant' with
|
||||
* 'memory_regions' by emitted by C compiler, we rename this file to .cpp.
|
||||
*
|
||||
* With renaming to .cpp, to avoid name mangling for TFM HAL functions by C++ compiler, we
|
||||
* declare these functions with modifier 'extern "C"'.
|
||||
*/
|
||||
|
||||
/* Check relevant macro has been defined */
|
||||
#if (! defined(TZ_START_NS))
|
||||
#error("TZ_START_NS not defined")
|
||||
#endif
|
||||
#if (! defined(NU_ROM_START_NS))
|
||||
#error("NU_ROM_START_NS not defined")
|
||||
#endif
|
||||
#if (! defined(NU_ROM_SIZE_NS))
|
||||
#error("NU_ROM_SIZE_NS not defined")
|
||||
#endif
|
||||
#if (! defined(NU_TZ_NSC_REGION_START))
|
||||
#error("NU_TZ_NSC_REGION_START not defined")
|
||||
#endif
|
||||
#if (! defined(NU_TZ_NSC_REGION_SIZE))
|
||||
#error("NU_TZ_NSC_REGION_SIZE not defined")
|
||||
#endif
|
||||
#if (! defined(SCB_AIRCR_SYSRESETREQS_VAL))
|
||||
#error("SCB_AIRCR_SYSRESETREQS_VAL not defined")
|
||||
#endif
|
||||
|
||||
const struct memory_region_limits memory_regions = {
|
||||
.non_secure_code_start = TZ_START_NS,
|
||||
|
||||
.non_secure_partition_base = NU_ROM_START_NS,
|
||||
.non_secure_partition_limit = NU_ROM_START_NS + NU_ROM_SIZE_NS - 1,
|
||||
|
||||
.veneer_base = NU_TZ_NSC_REGION_START,
|
||||
.veneer_limit = NU_TZ_NSC_REGION_START + NU_TZ_NSC_REGION_SIZE - 1
|
||||
};
|
||||
|
||||
extern "C" void enable_fault_handlers(void)
|
||||
{
|
||||
/* M2351 doesn't implement Main Extension, so BUS, MEM, USG and Secure faults (SCB->SHCSR) are not supported. */
|
||||
}
|
||||
|
||||
extern "C" void system_reset_cfg(void)
|
||||
{
|
||||
SCB_Setup();
|
||||
}
|
||||
|
||||
extern "C" void tfm_spm_hal_init_debug(void)
|
||||
{
|
||||
/* Configure debug authentication
|
||||
*
|
||||
* Support macros: DAUTH_NONE/DAUTH_NS_ONLY/DAUTH_FULL/DAUTH_CHIP_DEFAULT
|
||||
*
|
||||
* On Nuvoton's M2351, there's no need to configure debug authentication because
|
||||
* it depends on input signals.
|
||||
*/
|
||||
#warning("Ignore debug authentication option because it depends on input signals")
|
||||
}
|
||||
|
||||
/* Configures all interrupts of non-secure peripherals to target NS state */
|
||||
extern "C" void nvic_interrupt_target_state_cfg()
|
||||
{
|
||||
TZ_NVIC_Setup();
|
||||
}
|
||||
|
||||
/* Enables the interrupts associated to the secure peripherals (plus the isolation
|
||||
* boundary violation interrupts). */
|
||||
extern "C" void nvic_interrupt_enable()
|
||||
{
|
||||
/* Enable SCU security violation (isolation boundary violation) interrupts */
|
||||
SCU_ENABLE_INT(NU_SCU_SV_MSAK);
|
||||
|
||||
/* FIXME: Enable interrupts of secure peripherals */
|
||||
}
|
||||
|
|
@ -0,0 +1,49 @@
|
|||
/*
|
||||
* Copyright (c) 2018-2019, Nuvoton Technology Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef __TARGET_CFG_H__
|
||||
#define __TARGET_CFG_H__
|
||||
|
||||
#include "tfm_peripherals_def.h"
|
||||
|
||||
/* Mask for SCU security violation interrupts */
|
||||
#define NU_SCU_SV_MSAK (((1 << 18) - 1) & ~(3 << 2))
|
||||
|
||||
extern const struct memory_region_limits memory_regions;
|
||||
|
||||
/**
|
||||
* \brief Store the addresses of memory regions
|
||||
*/
|
||||
struct memory_region_limits {
|
||||
uint32_t non_secure_code_start;
|
||||
uint32_t non_secure_partition_base;
|
||||
uint32_t non_secure_partition_limit;
|
||||
uint32_t veneer_base;
|
||||
uint32_t veneer_limit;
|
||||
};
|
||||
|
||||
/**
|
||||
* \brief Holds the data necessary to do isolation for a specific peripheral.
|
||||
*/
|
||||
struct tfm_spm_partition_platform_data_t
|
||||
{
|
||||
uint32_t periph_start;
|
||||
uint32_t periph_limit;
|
||||
};
|
||||
|
||||
#endif /* __TARGET_CFG_H__ */
|
||||
|
|
@ -0,0 +1,22 @@
|
|||
/*
|
||||
* Copyright (c) 2018-2019, Nuvoton Technology Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef __TFM_PERIPHERALS_DEF_H__
|
||||
#define __TFM_PERIPHERALS_DEF_H__
|
||||
|
||||
#endif /* __TFM_PERIPHERALS_DEF_H__ */
|
||||
|
|
@ -0,0 +1,139 @@
|
|||
#! armclang -E
|
||||
|
||||
/*
|
||||
* Copyright (c) 2018-2019, Nuvoton Technology Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#include "../../../device/partition_M2351_mem.h"
|
||||
|
||||
#if !defined(MBED_BOOT_STACK_SIZE)
|
||||
#define MBED_BOOT_STACK_SIZE 0x400
|
||||
#endif
|
||||
|
||||
LR_IROM1 MBED_APP_START
|
||||
{
|
||||
/* load address = execution address */
|
||||
ER_IROM1 +0
|
||||
{
|
||||
*(RESET, +First)
|
||||
*(InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
}
|
||||
|
||||
/* Boot stack requirement
|
||||
*
|
||||
* Secure non-PSA/Non-secure non-PSA/Non-secure PSA requires just one boot stack (MSP).
|
||||
* Secure PSA(TFM) requires two boot stacks (MSP/PSP).
|
||||
*/
|
||||
#if TFM_LVL == 0
|
||||
|
||||
ARM_LIB_STACK MBED_RAM_APP_START EMPTY MBED_BOOT_STACK_SIZE
|
||||
{
|
||||
}
|
||||
|
||||
#else
|
||||
|
||||
/* Stack Pointer (SP) configuration with ARM/ARMC6
|
||||
*
|
||||
* SP would go through the following configuration sequence:
|
||||
* (1) SP(MSP) <- Entry 0 of vector table (on H/W reset)
|
||||
* (2) Switch SP from MSP to PSP in startup file (as TFM requests)
|
||||
* (3.1) SP(PSP) <- ARM_LIB_STACK (C/C++ runtime initialization)
|
||||
* (3.2) SP(PSP) reconfigured in __user_setup_stackheap()
|
||||
*
|
||||
* S(3.1) or S(3.2) may cause SP(PSP) incorrectly configured. We name ARM_LIB_STACK for
|
||||
* PSP stack rather than MSP stack to get around this error. MSP stack is named separately
|
||||
* with ARM_LIB_STACK_MSP.
|
||||
*/
|
||||
|
||||
#warning("Ignore MBED_BOOT_STACK_SIZE in Secure PSA build")
|
||||
ARM_LIB_STACK_MSP MBED_RAM_APP_START EMPTY 0x800
|
||||
{
|
||||
}
|
||||
|
||||
ARM_LIB_STACK AlignExpr(+0, 32) EMPTY 0x800
|
||||
{
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
/* Reserve for vectors
|
||||
*
|
||||
* Vector table base address is required to be 128-byte aligned at a minimum.
|
||||
* A PE might impose further restrictions on it. */
|
||||
ER_IRAMVEC AlignExpr(+0, 128) EMPTY (4*(16 + 102))
|
||||
{
|
||||
}
|
||||
|
||||
#if TFM_LVL == 0
|
||||
|
||||
/* 16 byte-aligned */
|
||||
RW_IRAM1 AlignExpr(+0, 16)
|
||||
{
|
||||
.ANY (+RW +ZI)
|
||||
}
|
||||
|
||||
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_APP_START + MBED_RAM_APP_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16))
|
||||
{
|
||||
}
|
||||
|
||||
#elif TFM_LVL == 1
|
||||
|
||||
TFM_SECURE_STACK AlignExpr(+0, 128) EMPTY 0x1000
|
||||
{
|
||||
}
|
||||
|
||||
TFM_UNPRIV_SCRATCH AlignExpr(+0, 32) EMPTY 0x400
|
||||
{
|
||||
}
|
||||
|
||||
/* 16 byte-aligned */
|
||||
ER_TFM_DATA AlignExpr(+0, 16)
|
||||
{
|
||||
.ANY (+RW +ZI)
|
||||
}
|
||||
|
||||
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_APP_START + MBED_RAM_APP_SIZE - AlignExpr(ImageLimit(ER_TFM_DATA), 16))
|
||||
{
|
||||
}
|
||||
|
||||
#elif TFM_LVL > 1
|
||||
|
||||
#error("TFM level 2/3 are not supported yet")
|
||||
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
LR_IROM_NSC NU_TZ_NSC_START NU_TZ_NSC_SIZE
|
||||
{
|
||||
ER_IROM_NSC NU_TZ_NSC_START FIXED PADVALUE 0xFFFFFFFF NU_TZ_NSC_SIZE
|
||||
{
|
||||
*(Veneer$$CMSE)
|
||||
}
|
||||
}
|
||||
|
||||
/* By IDAU, 0~0x4000 is secure. NSC can only locate in 0x4000~0x10000000. */
|
||||
ScatterAssert(ImageBase(ER_IROM_NSC) >= 0x4000)
|
||||
|
||||
/* Heap must be allocated in RAM. */
|
||||
ScatterAssert(ImageLimit(ARM_LIB_HEAP) <= (MBED_RAM_APP_START + MBED_RAM_APP_SIZE))
|
||||
|
||||
#if (TFM_LVL > 0)
|
||||
/* Application ROM code cannot overlap with TDB internal storage area. */
|
||||
ScatterAssert(LoadLimit(LR_IROM1) <= NU_TDB_INTERNAL_STORAGE_START)
|
||||
#endif
|
||||
|
|
@ -0,0 +1,398 @@
|
|||
/*
|
||||
* Copyright (c) 2018-2019, Nuvoton Technology Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Nuvoton M2351 GCC linker script file
|
||||
*/
|
||||
|
||||
#include "../../../device/partition_M2351_mem.h"
|
||||
|
||||
#ifndef MBED_BOOT_STACK_SIZE
|
||||
#define MBED_BOOT_STACK_SIZE 0x400
|
||||
#endif
|
||||
|
||||
#if (TFM_LVL == 0)
|
||||
|
||||
StackSize = MBED_BOOT_STACK_SIZE;
|
||||
|
||||
#else
|
||||
|
||||
#warning("Ignore MBED_BOOT_STACK_SIZE in Secure PSA build")
|
||||
__msp_stack_size__ = 0x00000800;
|
||||
__psp_stack_size__ = 0x00000800;
|
||||
|
||||
#endif
|
||||
|
||||
MEMORY
|
||||
{
|
||||
VECTORS (rx) : ORIGIN = MBED_APP_START, LENGTH = 0x00000400
|
||||
FLASH (rx) : ORIGIN = MBED_APP_START + 0x400, LENGTH = MBED_APP_SIZE - 0x400
|
||||
FLASH_NSC (rx) : ORIGIN = NU_TZ_NSC_START, LENGTH = NU_TZ_NSC_SIZE
|
||||
RAM_INTERN (rwx) : ORIGIN = MBED_RAM_APP_START, LENGTH = MBED_RAM_APP_SIZE
|
||||
}
|
||||
|
||||
/**
|
||||
* Must match cmsis_nvic.h
|
||||
*/
|
||||
__vector_size = 4 * (16 + 102);
|
||||
|
||||
|
||||
/* Linker script to place sections and symbol values. Should be used together
|
||||
* with other linker script that defines memory regions FLASH and RAM.
|
||||
* It references following symbols, which must be defined in code:
|
||||
* Reset_Handler : Entry of reset handler
|
||||
*
|
||||
* It defines following symbols, which code can use without definition:
|
||||
* __exidx_start
|
||||
* __exidx_end
|
||||
* __etext
|
||||
* __data_start__
|
||||
* __preinit_array_start
|
||||
* __preinit_array_end
|
||||
* __init_array_start
|
||||
* __init_array_end
|
||||
* __fini_array_start
|
||||
* __fini_array_end
|
||||
* __data_end__
|
||||
* __bss_start__
|
||||
* __bss_end__
|
||||
* __end__
|
||||
* end
|
||||
* __HeapLimit
|
||||
* __StackLimit
|
||||
* __StackTop
|
||||
* __stack
|
||||
*/
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
.isr_vector :
|
||||
{
|
||||
__vector_table = .;
|
||||
KEEP(*(.vector_table))
|
||||
. = ALIGN(8);
|
||||
} > VECTORS
|
||||
|
||||
#if (TFM_LVL == 0)
|
||||
|
||||
.copy.table : ALIGN(4)
|
||||
{
|
||||
__copy_table_start__ = .;
|
||||
LONG (LOADADDR(.data))
|
||||
LONG (ADDR(.data))
|
||||
LONG (SIZEOF(.data))
|
||||
__copy_table_end__ = .;
|
||||
} > FLASH
|
||||
|
||||
.zero.table : ALIGN(4)
|
||||
{
|
||||
__zero_table_start__ = .;
|
||||
LONG (ADDR(.bss))
|
||||
LONG (SIZEOF(.bss))
|
||||
__zero_table_end__ = .;
|
||||
} > FLASH
|
||||
|
||||
#elif (TFM_LVL == 1)
|
||||
|
||||
.copy.table : ALIGN(4)
|
||||
{
|
||||
__copy_table_start__ = .;
|
||||
LONG (LOADADDR(.TFM_DATA))
|
||||
LONG (ADDR(.TFM_DATA))
|
||||
LONG (SIZEOF(.TFM_DATA))
|
||||
__copy_table_end__ = .;
|
||||
} > FLASH
|
||||
|
||||
.zero.table : ALIGN(4)
|
||||
{
|
||||
__zero_table_start__ = .;
|
||||
LONG (ADDR(.TFM_BSS))
|
||||
LONG (SIZEOF(.TFM_BSS))
|
||||
LONG (ADDR(.TFM_SECURE_STACK))
|
||||
LONG (SIZEOF(.TFM_SECURE_STACK))
|
||||
LONG (ADDR(.TFM_UNPRIV_SCRATCH))
|
||||
LONG (SIZEOF(.TFM_UNPRIV_SCRATCH))
|
||||
__zero_table_end__ = .;
|
||||
} > FLASH
|
||||
|
||||
#else
|
||||
|
||||
#error("TFM level 2/3 are not supported yet")
|
||||
|
||||
#endif
|
||||
|
||||
.text :
|
||||
{
|
||||
*(.text*)
|
||||
|
||||
KEEP(*(.init))
|
||||
KEEP(*(.fini))
|
||||
|
||||
/* .ctors */
|
||||
*crtbegin.o(.ctors)
|
||||
*crtbegin?.o(.ctors)
|
||||
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
|
||||
*(SORT(.ctors.*))
|
||||
*(.ctors)
|
||||
|
||||
/* .dtors */
|
||||
*crtbegin.o(.dtors)
|
||||
*crtbegin?.o(.dtors)
|
||||
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
|
||||
*(SORT(.dtors.*))
|
||||
*(.dtors)
|
||||
|
||||
*(.rodata*)
|
||||
|
||||
KEEP(*(.eh_frame*))
|
||||
} > FLASH
|
||||
|
||||
/* Stack Pointer (SP) configuration with GCC_ARM
|
||||
*
|
||||
* SP would go through the following configuration sequence:
|
||||
* (1) SP(MSP) <- Entry 0 of vector table (on H/W reset)
|
||||
* (2) Switch SP from MSP to PSP in startup file (as TFM requests)
|
||||
* (3) SP(PSP) <- __stack (in _start(), C/C++ runtime initialization)
|
||||
*
|
||||
* S(3) may cause SP(PSP) incorrectly configured. To avoid this error, __stack
|
||||
* is assigned conditionally according to Secure PSA or not.
|
||||
*/
|
||||
|
||||
#if (TFM_LVL == 0)
|
||||
|
||||
.stack (NOLOAD) :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
__StackLimit = .;
|
||||
. += StackSize;
|
||||
__StackTop = .;
|
||||
} > RAM_INTERN
|
||||
|
||||
PROVIDE(__stack = __StackTop);
|
||||
|
||||
#else
|
||||
|
||||
.msp_stack (NOLOAD) :
|
||||
{
|
||||
. = ALIGN(32);
|
||||
. += __msp_stack_size__;
|
||||
} > RAM_INTERN
|
||||
Image$$ARM_LIB_STACK_MSP$$ZI$$Base = ADDR(.msp_stack);
|
||||
Image$$ARM_LIB_STACK_MSP$$ZI$$Limit = ADDR(.msp_stack) + SIZEOF(.msp_stack);
|
||||
__StackLimit = Image$$ARM_LIB_STACK_MSP$$ZI$$Base;
|
||||
__StackTop = Image$$ARM_LIB_STACK_MSP$$ZI$$Limit;
|
||||
|
||||
.psp_stack (NOLOAD) :
|
||||
{
|
||||
. = ALIGN(32);
|
||||
. += __psp_stack_size__;
|
||||
} > RAM_INTERN
|
||||
Image$$ARM_LIB_STACK$$ZI$$Base = ADDR(.psp_stack);
|
||||
Image$$ARM_LIB_STACK$$ZI$$Limit = ADDR(.psp_stack) + SIZEOF(.psp_stack);
|
||||
|
||||
PROVIDE(__stack = Image$$ARM_LIB_STACK$$ZI$$Limit);
|
||||
|
||||
#endif
|
||||
|
||||
#if (TFM_LVL == 1)
|
||||
|
||||
.TFM_SECURE_STACK (NOLOAD) :
|
||||
{
|
||||
. = ALIGN(128);
|
||||
. += 0x1000;
|
||||
} > RAM_INTERN
|
||||
Image$$TFM_SECURE_STACK$$ZI$$Base = ADDR(.TFM_SECURE_STACK);
|
||||
Image$$TFM_SECURE_STACK$$ZI$$Limit = ADDR(.TFM_SECURE_STACK) + SIZEOF(.TFM_SECURE_STACK);
|
||||
|
||||
.TFM_UNPRIV_SCRATCH (NOLOAD) :
|
||||
{
|
||||
. = ALIGN(32);
|
||||
. += 0x400;
|
||||
} > RAM_INTERN
|
||||
Image$$TFM_UNPRIV_SCRATCH$$ZI$$Base = ADDR(.TFM_UNPRIV_SCRATCH);
|
||||
Image$$TFM_UNPRIV_SCRATCH$$ZI$$Limit = ADDR(.TFM_UNPRIV_SCRATCH) + SIZEOF(.TFM_UNPRIV_SCRATCH);
|
||||
|
||||
#elif (TFM_LVL > 1)
|
||||
|
||||
#error("TFM level 2/3 are not supported yet")
|
||||
|
||||
#endif
|
||||
|
||||
.ARM.extab :
|
||||
{
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
} > FLASH
|
||||
|
||||
.ARM.exidx :
|
||||
{
|
||||
__exidx_start = .;
|
||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||
__exidx_end = .;
|
||||
} > FLASH
|
||||
|
||||
/* Relocate vector table in SRAM */
|
||||
.isr_vector.reloc (NOLOAD) :
|
||||
{
|
||||
. = ALIGN(1 << LOG2CEIL(__vector_size));
|
||||
PROVIDE(__start_vector_table__ = .);
|
||||
. += __vector_size;
|
||||
PROVIDE(__end_vector_table__ = .);
|
||||
} > RAM_INTERN
|
||||
|
||||
#if (TFM_LVL == 0)
|
||||
|
||||
.data :
|
||||
{
|
||||
PROVIDE( __etext = LOADADDR(.data) );
|
||||
|
||||
__data_start__ = .;
|
||||
*(vtable)
|
||||
*(.data*)
|
||||
|
||||
. = ALIGN(8);
|
||||
/* preinit data */
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP(*(.preinit_array))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
|
||||
. = ALIGN(8);
|
||||
/* init data */
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP(*(SORT(.init_array.*)))
|
||||
KEEP(*(.init_array))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
|
||||
. = ALIGN(8);
|
||||
/* finit data */
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP(*(SORT(.fini_array.*)))
|
||||
KEEP(*(.fini_array))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
|
||||
/* All data end */
|
||||
. = ALIGN(32);
|
||||
__data_end__ = .;
|
||||
|
||||
} >RAM_INTERN AT>FLASH
|
||||
|
||||
.bss (NOLOAD):
|
||||
{
|
||||
__bss_start__ = .;
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
__bss_end__ = .;
|
||||
} > RAM_INTERN
|
||||
|
||||
#else
|
||||
|
||||
.TFM_DATA :
|
||||
{
|
||||
PROVIDE( __etext = LOADADDR(.TFM_DATA) );
|
||||
|
||||
. = ALIGN(4);
|
||||
|
||||
__data_start__ = .;
|
||||
|
||||
*(.data*)
|
||||
|
||||
. = ALIGN(4);
|
||||
/* preinit data */
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP(*(.preinit_array))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
|
||||
. = ALIGN(4);
|
||||
/* init data */
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP(*(SORT(.init_array.*)))
|
||||
KEEP(*(.init_array))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
|
||||
. = ALIGN(4);
|
||||
/* finit data */
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP(*(SORT(.fini_array.*)))
|
||||
KEEP(*(.fini_array))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
|
||||
KEEP(*(.jcr*))
|
||||
. = ALIGN(4);
|
||||
|
||||
__data_end__ = .;
|
||||
|
||||
} > RAM_INTERN AT>FLASH
|
||||
Image$$ER_TFM_DATA$$RW$$Base = ADDR(.TFM_DATA);
|
||||
Image$$ER_TFM_DATA$$RW$$Limit = ADDR(.TFM_DATA) + SIZEOF(.TFM_DATA);
|
||||
|
||||
.TFM_BSS (NOLOAD) :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__bss_start__ = .;
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
__bss_end__ = .;
|
||||
} > RAM_INTERN
|
||||
Image$$ER_TFM_DATA$$ZI$$Base = ADDR(.TFM_BSS);
|
||||
Image$$ER_TFM_DATA$$ZI$$Limit = ADDR(.TFM_BSS) + SIZEOF(.TFM_BSS);
|
||||
|
||||
#endif
|
||||
|
||||
#if (TFM_LVL > 0)
|
||||
/* Application ROM code cannot overlap with TDB internal storage area. */
|
||||
ASSERT((LOADADDR(.TFM_DATA) + SIZEOF(.TFM_DATA)) <= NU_TDB_INTERNAL_STORAGE_START, "Application ROM code cannot overlap with TDB internal storage area.")
|
||||
#endif
|
||||
|
||||
/* Veneer$$CMSE : */
|
||||
.gnu.sgstubs NU_TZ_NSC_START :
|
||||
{
|
||||
. = ALIGN(32);
|
||||
|
||||
__sgstubs_start = .;
|
||||
*(.gnu.sgstubs.*)
|
||||
__sgstubs_end = .;
|
||||
|
||||
. = ALIGN(32);
|
||||
} > FLASH_NSC
|
||||
|
||||
/* NOTE: __sgstubs_end is not updated with *(.gnu.sgstubs.*). __sgstubs_start and
|
||||
* __sgstubs_end are the same. GCC bug? */
|
||||
Image$$ER_IROM_NSC$$Base = ADDR(.gnu.sgstubs);
|
||||
ASSERT(SIZEOF(.gnu.sgstubs) <= NU_TZ_NSC_SIZE, "Size of .gnu.sgstubs region cannot exceed NU_TZ_NSC_SIZE.")
|
||||
|
||||
/* By IDAU, 0~0x4000 is secure. NSC can only locate in 0x4000~0x10000000. */
|
||||
ASSERT(((__sgstubs_start % 32) == 0), "Requested by SAU, NSC region must start at 32 byte-aligned boundary.")
|
||||
ASSERT(__sgstubs_start >= 0x4000, "By IDAU, 0~0x4000 is secure. NSC can only locate in 0x4000~0x10000000.")
|
||||
|
||||
.heap (NOLOAD) :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
__end__ = .;
|
||||
end = __end__;
|
||||
*(.heap*);
|
||||
. += (ORIGIN(RAM_INTERN) + LENGTH(RAM_INTERN) - .);
|
||||
__HeapLimit = .;
|
||||
} > RAM_INTERN
|
||||
Image$$ARM_LIB_HEAP$$ZI$$Base = ADDR(.heap);
|
||||
Image$$ARM_LIB_HEAP$$ZI$$Limit = ADDR(.heap) + SIZEOF(.heap);
|
||||
|
||||
PROVIDE(__heap_size = SIZEOF(.heap));
|
||||
PROVIDE(__mbed_sbrk_start = ADDR(.heap));
|
||||
PROVIDE(__mbed_krbs_start = ADDR(.heap) + SIZEOF(.heap));
|
||||
}
|
||||
|
|
@ -0,0 +1,73 @@
|
|||
/*
|
||||
* Copyright (c) 2018-2019, Nuvoton Technology Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
|
||||
include "../../../device/partition_M2351_mem.icf";
|
||||
|
||||
if (! isdefinedsymbol(MBED_BOOT_STACK_SIZE)) {
|
||||
define symbol MBED_BOOT_STACK_SIZE = 0x400;
|
||||
}
|
||||
|
||||
/* FIXME: Check NSC area requirement */
|
||||
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = MBED_APP_START;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_ROM_start__ = MBED_APP_START;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = MBED_APP_START + MBED_APP_SIZE - 1;
|
||||
define symbol __ICFEDIT_region_IRAM_start__ = MBED_RAM_APP_START;
|
||||
define symbol __ICFEDIT_region_IRAM_end__ = MBED_RAM_APP_START + MBED_RAM_APP_SIZE - 1;
|
||||
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x400;
|
||||
|
||||
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
define region IRAM_region = mem:[from __ICFEDIT_region_IRAM_start__ to __ICFEDIT_region_IRAM_end__];
|
||||
|
||||
define block Image$$ER_IROM_NSC with alignment = 32 { readonly section Veneer$$CMSE };
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { };
|
||||
/* NOTE: Vector table base requires to be aligned to the power of vector table size. Give a safe value here. */
|
||||
define block IRAMVEC with alignment = 1024, size = 4 * (16 + 102) { };
|
||||
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem: __ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
place in ROM_region { readonly };
|
||||
place at address mem: NU_TZ_NSC_START { block Image$$ER_IROM_NSC }
|
||||
|
||||
place at start of IRAM_region { block CSTACK };
|
||||
place in IRAM_region { block IRAMVEC };
|
||||
place in IRAM_region { readwrite };
|
||||
place in IRAM_region { block HEAP };
|
||||
|
||||
if (TFM_LVL > 0) {
|
||||
/* TODO: Check if TDB internal storage area overlaps with application ROM code */
|
||||
}
|
||||
|
|
@ -180,14 +180,7 @@ typedef enum IRQn
|
|||
|
||||
|
||||
/* -------- Configuration of the Cortex-ARMv8MBL Processor and Core Peripherals ------- */
|
||||
#define __ARMv8MBL_REV 0x0000U /* Core revision r0p0 */
|
||||
#define __SAU_PRESENT 1U /* SAU present */
|
||||
#define __SAUREGION_PRESENT 1U /* SAU present */
|
||||
#define __MPU_PRESENT 1U /* MPU present */
|
||||
#define __VTOR_PRESENT 1U /* VTOR present */
|
||||
#define __NVIC_PRIO_BITS 2U /* Number of Bits used for Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */
|
||||
#define USE_ASSERT 0U /* Define to use Assert function or not */
|
||||
#include "system_core_M2351.h"
|
||||
|
||||
/*@}*/ /* end of group CMSIS */
|
||||
|
||||
|
|
|
|||
|
|
@ -1,173 +0,0 @@
|
|||
#! armclang -E
|
||||
|
||||
/*
|
||||
* Copyright (c) 2019-2020, Nuvoton Technology Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#include "../partition_M2351_mem.h"
|
||||
|
||||
#ifndef NU_TZ_NSC_SIZE
|
||||
#define NU_TZ_NSC_SIZE (0x1000)
|
||||
#endif
|
||||
|
||||
#if defined(DOMAIN_NS) && DOMAIN_NS
|
||||
|
||||
#ifndef MBED_APP_START
|
||||
#define MBED_APP_START NU_ROM_START_NS
|
||||
#endif
|
||||
|
||||
#ifndef MBED_APP_SIZE
|
||||
#define MBED_APP_SIZE NU_ROM_SIZE_NS
|
||||
#endif
|
||||
|
||||
#ifndef MBED_RAM_APP_START
|
||||
#define MBED_RAM_APP_START NU_RAM_START_NS
|
||||
#endif
|
||||
|
||||
#ifndef MBED_RAM_APP_SIZE
|
||||
#define MBED_RAM_APP_SIZE NU_RAM_SIZE_NS
|
||||
#endif
|
||||
|
||||
#if !defined(MBED_BOOT_STACK_SIZE)
|
||||
#define MBED_BOOT_STACK_SIZE 0x400
|
||||
#endif
|
||||
|
||||
#else
|
||||
|
||||
#ifndef MBED_APP_START
|
||||
#define MBED_APP_START NU_ROM_START_S
|
||||
#endif
|
||||
|
||||
#ifndef MBED_APP_SIZE
|
||||
#define MBED_APP_SIZE NU_ROM_SIZE_S
|
||||
#endif
|
||||
|
||||
#ifndef MBED_RAM_APP_START
|
||||
#define MBED_RAM_APP_START NU_RAM_START_S
|
||||
#endif
|
||||
|
||||
#ifndef MBED_RAM_APP_SIZE
|
||||
#define MBED_RAM_APP_SIZE NU_RAM_SIZE_S
|
||||
#endif
|
||||
|
||||
#if !defined(MBED_BOOT_STACK_SIZE)
|
||||
#define MBED_BOOT_STACK_SIZE 0x400
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
/* Requirements for NSC location
|
||||
*
|
||||
* 1. By IDAU, 0~0x4000 is secure. NSC can only locate in 0x4000~0x10000000.
|
||||
* 2. Greentea flash IAP uses last 4 sectors for its test. Avoid this range.
|
||||
* 3. Greentea NVSTORE uses last 2 sectors or 4KiB x 2 for its test. Avoid this range.
|
||||
* 4. NSC region size defaults to 4KiB if not defined.
|
||||
*/
|
||||
#define NU_TZ_NSC_START (MBED_APP_START + MBED_APP_SIZE - 0x2000 - NU_TZ_NSC_SIZE)
|
||||
|
||||
#if defined(DOMAIN_NS) && DOMAIN_NS
|
||||
|
||||
LR_IROM1 MBED_APP_START
|
||||
{
|
||||
/* load address = execution address */
|
||||
ER_IROM1 +0
|
||||
{
|
||||
*(RESET, +First)
|
||||
*(InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
}
|
||||
|
||||
ARM_LIB_STACK MBED_RAM_APP_START EMPTY MBED_BOOT_STACK_SIZE
|
||||
{
|
||||
}
|
||||
|
||||
/* Reserve for vectors
|
||||
*
|
||||
* Vector table base address is required to be 128-byte aligned at a minimum.
|
||||
* A PE might impose further restrictions on it. */
|
||||
ER_IRAMVEC AlignExpr(+0, 128) EMPTY (4*(16 + 102))
|
||||
{
|
||||
}
|
||||
|
||||
/* 16 byte-aligned */
|
||||
RW_IRAM1 AlignExpr(+0, 16)
|
||||
{
|
||||
.ANY (+RW +ZI)
|
||||
}
|
||||
|
||||
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_APP_START + MBED_RAM_APP_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16))
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
ScatterAssert(LoadLimit(LR_IROM1) <= (MBED_APP_START + MBED_APP_SIZE))
|
||||
ScatterAssert(ImageLimit(ARM_LIB_HEAP) <= MBED_RAM_APP_START + MBED_RAM_APP_SIZE)
|
||||
|
||||
#else
|
||||
|
||||
LR_IROM1 MBED_APP_START
|
||||
{
|
||||
/* load address = execution address */
|
||||
ER_IROM1 +0
|
||||
{
|
||||
*(RESET, +First)
|
||||
*(InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
}
|
||||
|
||||
ARM_LIB_STACK 0x20000000 EMPTY MBED_BOOT_STACK_SIZE
|
||||
{
|
||||
}
|
||||
|
||||
/* Reserve for vectors
|
||||
*
|
||||
* Vector table base address is required to be 128-byte aligned at a minimum.
|
||||
* A PE might impose further restrictions on it. */
|
||||
ER_IRAMVEC AlignExpr(+0, 128) EMPTY (4*(16 + 102))
|
||||
{
|
||||
}
|
||||
|
||||
/* 16 byte-aligned */
|
||||
RW_IRAM1 AlignExpr(+0, 16)
|
||||
{
|
||||
.ANY (+RW +ZI)
|
||||
}
|
||||
|
||||
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_APP_START + MBED_RAM_APP_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16))
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
LR_IROM_NSC NU_TZ_NSC_START NU_TZ_NSC_SIZE
|
||||
{
|
||||
ER_IROM_NSC +0
|
||||
{
|
||||
*(Veneer$$CMSE)
|
||||
}
|
||||
|
||||
ER_IROM_NSC_PAD +0 FILL 0xFFFFFFFF (NU_TZ_NSC_START + NU_TZ_NSC_SIZE - ImageLimit(ER_IROM_NSC))
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
ScatterAssert(LoadLimit(LR_IROM1) <= NU_TZ_NSC_START)
|
||||
ScatterAssert(LoadLimit(LR_IROM_NSC) <= (NU_TZ_NSC_START + NU_TZ_NSC_SIZE))
|
||||
/* By IDAU, 0~0x4000 is secure. NSC can only locate in 0x4000~0x10000000 */
|
||||
ScatterAssert(LoadBase(LR_IROM_NSC) >= 0x4000)
|
||||
ScatterAssert(ImageLimit(ARM_LIB_HEAP) <= (MBED_RAM_APP_START + MBED_RAM_APP_SIZE))
|
||||
|
||||
#endif
|
||||
|
|
@ -1,368 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2019-2020, Nuvoton Technology Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Nuvoton M2351 GCC linker script file
|
||||
*/
|
||||
|
||||
#include "../partition_M2351_mem.h"
|
||||
|
||||
#ifndef NU_TZ_NSC_SIZE
|
||||
#define NU_TZ_NSC_SIZE (0x1000)
|
||||
#endif
|
||||
|
||||
#if defined(DOMAIN_NS) && DOMAIN_NS
|
||||
|
||||
#ifndef MBED_APP_START
|
||||
#define MBED_APP_START NU_ROM_START_NS
|
||||
#endif
|
||||
|
||||
#ifndef MBED_APP_SIZE
|
||||
#define MBED_APP_SIZE NU_ROM_SIZE_NS
|
||||
#endif
|
||||
|
||||
#ifndef MBED_RAM_APP_START
|
||||
#define MBED_RAM_APP_START NU_RAM_START_NS
|
||||
#endif
|
||||
|
||||
#ifndef MBED_RAM_APP_SIZE
|
||||
#define MBED_RAM_APP_SIZE NU_RAM_SIZE_NS
|
||||
#endif
|
||||
|
||||
#if !defined(MBED_BOOT_STACK_SIZE)
|
||||
#define MBED_BOOT_STACK_SIZE 0x400
|
||||
#endif
|
||||
|
||||
#else
|
||||
|
||||
#ifndef MBED_APP_START
|
||||
#define MBED_APP_START NU_ROM_START_S
|
||||
#endif
|
||||
|
||||
#ifndef MBED_APP_SIZE
|
||||
#define MBED_APP_SIZE NU_ROM_SIZE_S
|
||||
#endif
|
||||
|
||||
#ifndef MBED_RAM_APP_START
|
||||
#define MBED_RAM_APP_START NU_RAM_START_S
|
||||
#endif
|
||||
|
||||
#ifndef MBED_RAM_APP_SIZE
|
||||
#define MBED_RAM_APP_SIZE NU_RAM_SIZE_S
|
||||
#endif
|
||||
|
||||
#ifndef MBED_BOOT_STACK_SIZE
|
||||
#define MBED_BOOT_STACK_SIZE 0x400
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
StackSize = MBED_BOOT_STACK_SIZE;
|
||||
|
||||
/* Requirements for NSC location
|
||||
*
|
||||
* 1. By IDAU, 0~0x4000 is secure. NSC can only locate in 0x4000~0x10000000.
|
||||
* 2. Greentea flash IAP uses last 4 sectors for its test. Avoid this range.
|
||||
* 3. Greentea NVSTORE uses last 2 sectors or 4KiB x 2 for its test. Avoid this range.
|
||||
* 4. NSC region size defaults to 4KiB if not defined.
|
||||
*/
|
||||
#ifndef NU_TZ_NSC_START
|
||||
#define NU_TZ_NSC_START (MBED_APP_START + MBED_APP_SIZE - 0x2000 - NU_TZ_NSC_SIZE)
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(DOMAIN_NS) && DOMAIN_NS
|
||||
|
||||
MEMORY
|
||||
{
|
||||
VECTORS (rx) : ORIGIN = MBED_APP_START, LENGTH = 0x00000400
|
||||
FLASH (rx) : ORIGIN = MBED_APP_START + 0x400, LENGTH = MBED_APP_SIZE - 0x400
|
||||
RAM_INTERN (rwx) : ORIGIN = MBED_RAM_APP_START, LENGTH = MBED_RAM_APP_SIZE
|
||||
}
|
||||
|
||||
#else
|
||||
|
||||
MEMORY
|
||||
{
|
||||
VECTORS (rx) : ORIGIN = MBED_APP_START, LENGTH = 0x00000400
|
||||
FLASH (rx) : ORIGIN = MBED_APP_START + 0x400, LENGTH = NU_TZ_NSC_START - MBED_APP_START - 0x400
|
||||
NSC_FLASH (rx) : ORIGIN = NU_TZ_NSC_START, LENGTH = NU_TZ_NSC_SIZE
|
||||
RAM_INTERN (rwx) : ORIGIN = MBED_RAM_APP_START, LENGTH = MBED_RAM_APP_SIZE
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
/**
|
||||
* Must match cmsis_nvic.h
|
||||
*/
|
||||
__vector_size = 4 * (16 + 102);
|
||||
|
||||
|
||||
/* Linker script to place sections and symbol values. Should be used together
|
||||
* with other linker script that defines memory regions FLASH and RAM.
|
||||
* It references following symbols, which must be defined in code:
|
||||
* Reset_Handler : Entry of reset handler
|
||||
*
|
||||
* It defines following symbols, which code can use without definition:
|
||||
* __exidx_start
|
||||
* __exidx_end
|
||||
* __etext
|
||||
* __data_start__
|
||||
* __preinit_array_start
|
||||
* __preinit_array_end
|
||||
* __init_array_start
|
||||
* __init_array_end
|
||||
* __fini_array_start
|
||||
* __fini_array_end
|
||||
* __data_end__
|
||||
* __bss_start__
|
||||
* __bss_end__
|
||||
* __end__
|
||||
* end
|
||||
* __HeapLimit
|
||||
* __StackLimit
|
||||
* __StackTop
|
||||
* __stack
|
||||
*/
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
.isr_vector :
|
||||
{
|
||||
__vector_table = .;
|
||||
KEEP(*(.vector_table))
|
||||
. = ALIGN(8);
|
||||
} > VECTORS
|
||||
|
||||
/* ensure that uvisor bss is at the beginning of memory */
|
||||
|
||||
.uvisor.bss (NOLOAD):
|
||||
{
|
||||
. = ALIGN(32);
|
||||
__uvisor_bss_start = .;
|
||||
|
||||
/* protected uvisor main bss */
|
||||
. = ALIGN(32);
|
||||
__uvisor_bss_main_start = .;
|
||||
KEEP(*(.keep.uvisor.bss.main))
|
||||
. = ALIGN(32);
|
||||
__uvisor_bss_main_end = .;
|
||||
|
||||
/* protected uvisor secure boxes bss */
|
||||
. = ALIGN(32);
|
||||
__uvisor_bss_boxes_start = .;
|
||||
KEEP(*(.keep.uvisor.bss.boxes))
|
||||
. = ALIGN(32);
|
||||
__uvisor_bss_boxes_end = .;
|
||||
|
||||
/* Ensure log2(size) alignment of the uvisor region, to ensure that the region can be effectively protected by the MPU. */
|
||||
. = ALIGN(1 << LOG2CEIL(__uvisor_bss_boxes_end - __uvisor_bss_start));
|
||||
__uvisor_bss_end = .;
|
||||
} > RAM_INTERN
|
||||
|
||||
.text :
|
||||
{
|
||||
/* uVisor code and data */
|
||||
. = ALIGN(8);
|
||||
__uvisor_main_start = .;
|
||||
*(.uvisor.main)
|
||||
__uvisor_main_end = .;
|
||||
*(.text*)
|
||||
|
||||
KEEP(*(.init))
|
||||
KEEP(*(.fini))
|
||||
|
||||
/* .ctors */
|
||||
*crtbegin.o(.ctors)
|
||||
*crtbegin?.o(.ctors)
|
||||
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
|
||||
*(SORT(.ctors.*))
|
||||
*(.ctors)
|
||||
|
||||
/* .dtors */
|
||||
*crtbegin.o(.dtors)
|
||||
*crtbegin?.o(.dtors)
|
||||
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
|
||||
*(SORT(.dtors.*))
|
||||
*(.dtors)
|
||||
|
||||
*(.rodata*)
|
||||
|
||||
KEEP(*(.eh_frame*))
|
||||
} > FLASH
|
||||
|
||||
#if (! defined(DOMAIN_NS)) || (! DOMAIN_NS)
|
||||
/* Veneer$$CMSE : */
|
||||
.gnu.sgstubs :
|
||||
{
|
||||
__sgstubs_start = .;
|
||||
*(.gnu.sgstubs.*)
|
||||
__sgstubs_end = .;
|
||||
} > NSC_FLASH
|
||||
|
||||
__nu_tz_nsc_start = NU_TZ_NSC_START;
|
||||
__nu_tz_nsc_size = NU_TZ_NSC_SIZE;
|
||||
|
||||
/* By IDAU, 0~0x4000 is secure. NSC can only locate in 0x4000~0x10000000. */
|
||||
ASSERT(__sgstubs_start >= 0x4000, "By IDAU, 0~0x4000 is secure. NSC can only locate in 0x4000~0x10000000.")
|
||||
#endif
|
||||
.ARM.extab :
|
||||
{
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
} > FLASH
|
||||
|
||||
.ARM.exidx :
|
||||
{
|
||||
__exidx_start = .;
|
||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||
__exidx_end = .;
|
||||
} > FLASH
|
||||
|
||||
/* .stack section doesn't contains any symbols. It is only
|
||||
* used for linker to reserve space for the main stack section
|
||||
* WARNING: .stack should come immediately after the last secure memory
|
||||
* section. This provides stack overflow detection. */
|
||||
.stack (NOLOAD):
|
||||
{
|
||||
__StackLimit = .;
|
||||
*(.stack*);
|
||||
. += StackSize - (. - __StackLimit);
|
||||
} > RAM_INTERN
|
||||
|
||||
/* Set stack top to end of RAM, and stack limit move down by
|
||||
* size of stack_dummy section */
|
||||
__StackTop = ADDR(.stack) + SIZEOF(.stack);
|
||||
__StackLimit = ADDR(.stack);
|
||||
PROVIDE(__stack = __StackTop);
|
||||
|
||||
/* Relocate vector table in SRAM */
|
||||
.isr_vector.reloc (NOLOAD) :
|
||||
{
|
||||
. = ALIGN(1 << LOG2CEIL(__vector_size));
|
||||
PROVIDE(__start_vector_table__ = .);
|
||||
. += __vector_size;
|
||||
PROVIDE(__end_vector_table__ = .);
|
||||
} > RAM_INTERN
|
||||
|
||||
.data :
|
||||
{
|
||||
PROVIDE( __etext = LOADADDR(.data) );
|
||||
|
||||
__data_start__ = .;
|
||||
*(vtable)
|
||||
*(.data*)
|
||||
|
||||
. = ALIGN(8);
|
||||
/* preinit data */
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP(*(.preinit_array))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
|
||||
. = ALIGN(8);
|
||||
/* init data */
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP(*(SORT(.init_array.*)))
|
||||
KEEP(*(.init_array))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
|
||||
. = ALIGN(8);
|
||||
/* finit data */
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP(*(SORT(.fini_array.*)))
|
||||
KEEP(*(.fini_array))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
|
||||
/* All data end */
|
||||
. = ALIGN(32);
|
||||
__data_end__ = .;
|
||||
|
||||
} >RAM_INTERN AT>FLASH
|
||||
|
||||
/* uvisor configuration data */
|
||||
.uvisor.secure :
|
||||
{
|
||||
. = ALIGN(32);
|
||||
__uvisor_secure_start = .;
|
||||
|
||||
/* uvisor secure boxes configuration tables */
|
||||
. = ALIGN(32);
|
||||
__uvisor_cfgtbl_start = .;
|
||||
KEEP(*(.keep.uvisor.cfgtbl))
|
||||
. = ALIGN(32);
|
||||
__uvisor_cfgtbl_end = .;
|
||||
|
||||
/* pointers to uvisor secure boxes configuration tables */
|
||||
/* note: no further alignment here, we need to have the exact list of pointers */
|
||||
__uvisor_cfgtbl_ptr_start = .;
|
||||
KEEP(*(.keep.uvisor.cfgtbl_ptr_first))
|
||||
KEEP(*(.keep.uvisor.cfgtbl_ptr))
|
||||
__uvisor_cfgtbl_ptr_end = .;
|
||||
|
||||
/* the following symbols are kept for backward compatibility and will be soon
|
||||
* deprecated; applications actively using uVisor (__uvisor_mode == UVISOR_ENABLED)
|
||||
* will need to use uVisor 0.8.x or above, or the security assertions will halt the
|
||||
* system */
|
||||
/************************/
|
||||
__uvisor_data_src = .;
|
||||
__uvisor_data_start = .;
|
||||
__uvisor_data_end = .;
|
||||
/************************/
|
||||
|
||||
. = ALIGN(32);
|
||||
__uvisor_secure_end = .;
|
||||
} >FLASH
|
||||
|
||||
.uninitialized (NOLOAD):
|
||||
{
|
||||
. = ALIGN(32);
|
||||
__uninitialized_start = .;
|
||||
*(.uninitialized)
|
||||
KEEP(*(.keep.uninitialized))
|
||||
. = ALIGN(32);
|
||||
__uninitialized_end = .;
|
||||
} > RAM_INTERN
|
||||
|
||||
.bss (NOLOAD):
|
||||
{
|
||||
__bss_start__ = .;
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
__bss_end__ = .;
|
||||
} > RAM_INTERN
|
||||
|
||||
.heap (NOLOAD):
|
||||
{
|
||||
__end__ = .;
|
||||
end = __end__;
|
||||
*(.heap*);
|
||||
. += (ORIGIN(RAM_INTERN) + LENGTH(RAM_INTERN) - .);
|
||||
__HeapLimit = .;
|
||||
} > RAM_INTERN
|
||||
|
||||
PROVIDE(__heap_size = SIZEOF(.heap));
|
||||
PROVIDE(__mbed_sbrk_start = ADDR(.heap));
|
||||
PROVIDE(__mbed_krbs_start = ADDR(.heap) + SIZEOF(.heap));
|
||||
|
||||
/* Provide physical memory boundaries for uVisor. */
|
||||
__uvisor_flash_start = ORIGIN(VECTORS);
|
||||
__uvisor_flash_end = ORIGIN(FLASH) + LENGTH(FLASH);
|
||||
__uvisor_sram_start = ORIGIN(RAM_INTERN);
|
||||
__uvisor_sram_end = ORIGIN(RAM_INTERN) + LENGTH(RAM_INTERN);
|
||||
|
||||
}
|
||||
|
|
@ -1,138 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2019-2020, Nuvoton Technology Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
|
||||
include "../partition_M2351_mem.icf";
|
||||
|
||||
if (! isdefinedsymbol(NU_TZ_NSC_SIZE)) {
|
||||
define symbol NU_TZ_NSC_SIZE = 0x1000;
|
||||
}
|
||||
|
||||
if (isdefinedsymbol(DOMAIN_NS)) {
|
||||
|
||||
if (! isdefinedsymbol(MBED_APP_START)) {
|
||||
define symbol MBED_APP_START = NU_ROM_START_NS;
|
||||
}
|
||||
|
||||
if (! isdefinedsymbol(MBED_APP_SIZE)) {
|
||||
define symbol MBED_APP_SIZE = NU_ROM_SIZE_NS;
|
||||
}
|
||||
|
||||
if (! isdefinedsymbol(MBED_RAM_APP_START)) {
|
||||
define symbol MBED_RAM_APP_START = NU_RAM_START_NS;
|
||||
}
|
||||
|
||||
if (! isdefinedsymbol(MBED_RAM_APP_SIZE)) {
|
||||
define symbol MBED_RAM_APP_SIZE = NU_RAM_SIZE_NS;
|
||||
}
|
||||
|
||||
if (! isdefinedsymbol(MBED_BOOT_STACK_SIZE)) {
|
||||
define symbol MBED_BOOT_STACK_SIZE = 0x400;
|
||||
}
|
||||
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = MBED_APP_START;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_ROM_start__ = MBED_APP_START;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = MBED_APP_START + MBED_APP_SIZE - 1;
|
||||
define symbol __ICFEDIT_region_IRAM_start__ = MBED_RAM_APP_START;
|
||||
define symbol __ICFEDIT_region_IRAM_end__ = MBED_RAM_APP_START + MBED_RAM_APP_SIZE - 1;
|
||||
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x8000;
|
||||
|
||||
} else {
|
||||
|
||||
if (! isdefinedsymbol(MBED_APP_START)) {
|
||||
define symbol MBED_APP_START = NU_ROM_START_S;
|
||||
}
|
||||
|
||||
if (! isdefinedsymbol(MBED_APP_SIZE)) {
|
||||
define symbol MBED_APP_SIZE = NU_ROM_SIZE_S;
|
||||
}
|
||||
|
||||
if (! isdefinedsymbol(MBED_RAM_APP_START)) {
|
||||
define symbol MBED_RAM_APP_START = NU_RAM_START_S;
|
||||
}
|
||||
|
||||
if (! isdefinedsymbol(MBED_RAM_APP_SIZE)) {
|
||||
define symbol MBED_RAM_APP_SIZE = NU_RAM_SIZE_S;
|
||||
}
|
||||
|
||||
if (! isdefinedsymbol(MBED_BOOT_STACK_SIZE)) {
|
||||
define symbol MBED_BOOT_STACK_SIZE = 0x400;
|
||||
}
|
||||
|
||||
/* Requirements for NSC location
|
||||
*
|
||||
* 1. By IDAU, 0~0x4000 is secure. NSC can only locate in 0x4000~0x10000000.
|
||||
* 2. Greentea flash IAP uses last 4 sectors for its test. Avoid this range.
|
||||
* 3. Greentea NVSTORE uses last 2 sectors or 4KiB x 2 for its test. Avoid this range.
|
||||
* 4. NSC region size defaults to 4KiB if not defined.
|
||||
*/
|
||||
if (! isdefinedsymbol(NU_TZ_NSC_START)) {
|
||||
define symbol NU_TZ_NSC_START = MBED_APP_START + MBED_APP_SIZE - 0x2000 - NU_TZ_NSC_SIZE;
|
||||
}
|
||||
define exported symbol __NU_TZ_NSC_start__ = NU_TZ_NSC_START;
|
||||
define exported symbol __NU_TZ_NSC_size__ = NU_TZ_NSC_SIZE;
|
||||
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = MBED_APP_START;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_ROM_start__ = MBED_APP_START;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = MBED_APP_START + MBED_APP_SIZE - 1;
|
||||
define symbol __ICFEDIT_region_NSCROM_start__ = NU_TZ_NSC_START;
|
||||
define symbol __ICFEDIT_region_NSCROM_end__ = NU_TZ_NSC_START + NU_TZ_NSC_SIZE - 1;
|
||||
define symbol __ICFEDIT_region_IRAM_start__ = MBED_RAM_APP_START;
|
||||
define symbol __ICFEDIT_region_IRAM_end__ = MBED_RAM_APP_START + MBED_RAM_APP_SIZE - 1;
|
||||
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x4000;
|
||||
}
|
||||
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
define region IRAM_region = mem:[from __ICFEDIT_region_IRAM_start__ to __ICFEDIT_region_IRAM_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
/* NOTE: Vector table base requires to be aligned to the power of vector table size. Give a safe value here. */
|
||||
define block IRAMVEC with alignment = 1024, size = 4 * (16 + 102) { };
|
||||
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in ROM_region { readonly };
|
||||
if (! isdefinedsymbol(DOMAIN_NS)) {
|
||||
place at address mem:__ICFEDIT_region_NSCROM_start__ { readonly section Veneer$$CMSE };
|
||||
}
|
||||
place at start of IRAM_region { block CSTACK };
|
||||
place in IRAM_region { block IRAMVEC };
|
||||
place in IRAM_region { readwrite };
|
||||
place in IRAM_region { block HEAP };
|
||||
|
|
@ -1,5 +1,7 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2015-2017 Nuvoton
|
||||
/*
|
||||
* Copyright (c) 2018-2019, Nuvoton Technology Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
|
|
@ -23,10 +25,31 @@
|
|||
#include "partition_M2351.h"
|
||||
|
||||
/* Check relevant macro has been defined */
|
||||
#if (! defined(NU_TZ_SECURE_FLASH_SIZE))
|
||||
#error("NU_TZ_SECURE_FLASH_SIZE not defined")
|
||||
#if (! defined(NU_ROM_SIZE_S))
|
||||
#error("NU_ROM_SIZE_S not defined")
|
||||
#endif
|
||||
|
||||
/* Determine vector table management
|
||||
*
|
||||
* 1. Non-secure non-PSA/Non-secure PSA
|
||||
* 2. Secure non-PSA (TFM_LVL == 0)
|
||||
* 3. Secure PSA (TFM_LVL > 0)
|
||||
*
|
||||
* In Case 1/2, Mbed OS takes over vector table.
|
||||
* In Case 3, TFM takes over vector table.
|
||||
*
|
||||
* If TFM_LVL isn't defined, it is equivalent to TFM_LVL == 0.
|
||||
*
|
||||
* FIXME: Currently, we still go mbed relocating vector table sequence. When TFM (Secure PSA)
|
||||
* updates to take over NVIC itself, we must disable this sequence:
|
||||
* 1. Do not allocate vector RAM (cmsis.h/cmsis_nvic.h/linker files):
|
||||
* Image$$ER_IRAMVEC$$ZI$$Base
|
||||
* __section_begin("IRAMVEC")
|
||||
* __start_vector_table__
|
||||
* 2. Secure PSA may go mbed boot sequence. We must leave NVIC_RAM_VECTOR_ADDRESS
|
||||
* undefined to make the mbed_copy_nvic() function dummy (cmsis_nvic.h).
|
||||
*/
|
||||
|
||||
// Support linker-generated symbol as start of relocated vector table.
|
||||
#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
|
||||
extern uint32_t Image$$ER_IRAMVEC$$ZI$$Base;
|
||||
|
|
@ -38,7 +61,7 @@ extern uint32_t __start_vector_table__;
|
|||
|
||||
/* TZ_START_NS: Start address of non-secure application */
|
||||
#ifndef TZ_START_NS
|
||||
#define TZ_START_NS (NS_OFFSET + NU_TZ_SECURE_FLASH_SIZE)
|
||||
#define TZ_START_NS (NS_OFFSET + NU_ROM_SIZE_S)
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -0,0 +1,22 @@
|
|||
/*
|
||||
* Copyright (c) 2018 ARM Limited
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef __CMSIS_CPU_H__
|
||||
#define __CMSIS_CPU_H__
|
||||
|
||||
#include "system_core_M2351.h"
|
||||
|
||||
#endif /* __CMSIS_CPU_H__ */
|
||||
|
|
@ -1,5 +1,7 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2015-2017 Nuvoton
|
||||
/*
|
||||
* Copyright (c) 2018-2019, Nuvoton Technology Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
|
|
|
|||
|
|
@ -0,0 +1,231 @@
|
|||
/*
|
||||
* Copyright (c) 2018-2019, Nuvoton Technology Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#include "cmsis.h"
|
||||
#include "partition_M2351.h"
|
||||
|
||||
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
|
||||
|
||||
#if TFM_LVL > 0
|
||||
|
||||
#include "tfm_secure_api.h"
|
||||
#include "platform/mbed_assert.h"
|
||||
|
||||
/* The configuration of TDB internal storage area defined in "partition_M2351_mem.h"
|
||||
* must match "tdb_internal/mbed_lib.json", so it can pass to linker files for
|
||||
* memory layout check. */
|
||||
MBED_STATIC_ASSERT(NU_TDB_INTERNAL_STORAGE_START == MBED_CONF_STORAGE_TDB_INTERNAL_INTERNAL_BASE_ADDRESS,
|
||||
"NU_TDB_INTERNAL_STORAGE_START must be equal to MBED_CONF_STORAGE_TDB_INTERNAL_INTERNAL_BASE_ADDRESS");
|
||||
MBED_STATIC_ASSERT(NU_TDB_INTERNAL_STORAGE_SIZE == MBED_CONF_STORAGE_TDB_INTERNAL_INTERNAL_SIZE,
|
||||
"NU_TDB_INTERNAL_STORAGE_SIZE must be equal to MBED_CONF_STORAGE_TDB_INTERNAL_INTERNAL_SIZE");
|
||||
|
||||
#endif
|
||||
|
||||
void FMC_NSBA_Setup(void)
|
||||
{
|
||||
/* Skip NSBA Setupt according config */
|
||||
if(FMC_INIT_NSBA == 0)
|
||||
return;
|
||||
|
||||
/* Check if NSBA value with current active NSBA */
|
||||
if(SCU->FNSADDR != FMC_SECURE_ROM_SIZE)
|
||||
{
|
||||
/* Unlock Protected Register */
|
||||
SYS_UnlockReg();
|
||||
|
||||
/* Enable ISP and config update */
|
||||
FMC->ISPCTL = FMC_ISPCTL_ISPEN_Msk | FMC_ISPCTL_CFGUEN_Msk;
|
||||
|
||||
/* Config Base of NSBA */
|
||||
FMC->ISPADDR = 0x200800;
|
||||
|
||||
/* Read Non-secure base address config */
|
||||
FMC->ISPCMD = FMC_ISPCMD_READ;
|
||||
FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
|
||||
while(FMC->ISPTRG);
|
||||
|
||||
/* Setting NSBA when it is empty */
|
||||
if(FMC->ISPDAT == 0xfffffffful)
|
||||
{
|
||||
FMC->ISPDAT = FMC_SECURE_ROM_SIZE;
|
||||
FMC->ISPCMD = FMC_ISPCMD_PROGRAM;
|
||||
FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
|
||||
while(FMC->ISPTRG);
|
||||
|
||||
/* Force Chip Reset to valid new setting */
|
||||
SYS->IPRST0 = SYS_IPRST0_CHIPRST_Msk;
|
||||
}
|
||||
|
||||
/* Fatal Error:
|
||||
FMC NSBA setting is different to FMC_INIT_NSBA_VAL.
|
||||
User must double confirm which one is wrong.
|
||||
|
||||
If user need to change NSBA config of FMC, user must do Mess-erase by
|
||||
ISP or ICP.
|
||||
*/
|
||||
while(1);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
void SCU_Setup(void)
|
||||
{
|
||||
int32_t i;
|
||||
|
||||
SCU->PNSSET[0] = SCU_INIT_PNSSET0_VAL;
|
||||
SCU->PNSSET[1] = SCU_INIT_PNSSET1_VAL;
|
||||
SCU->PNSSET[2] = SCU_INIT_PNSSET2_VAL;
|
||||
SCU->PNSSET[3] = SCU_INIT_PNSSET3_VAL;
|
||||
SCU->PNSSET[4] = SCU_INIT_PNSSET4_VAL;
|
||||
SCU->PNSSET[5] = SCU_INIT_PNSSET5_VAL;
|
||||
SCU->PNSSET[6] = SCU_INIT_PNSSET6_VAL;
|
||||
|
||||
SCU->IONSSET = SCU_INIT_IONSSET_VAL;
|
||||
|
||||
/* Set Non-secure SRAM */
|
||||
for(i = 11; i >= SCU_SECURE_SRAM_SIZE / 8192; i--)
|
||||
{
|
||||
SCU->SRAMNSSET |= (1U << i);
|
||||
}
|
||||
}
|
||||
|
||||
void TZ_SAU_Setup(void)
|
||||
{
|
||||
#if defined (__SAU_PRESENT) && (__SAU_PRESENT == 1U)
|
||||
|
||||
#if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U)
|
||||
#if TFM_LVL == 0
|
||||
SAU_INIT_REGION(0);
|
||||
#else
|
||||
#error("TFM doesn't support SAU_INIT_REGION0")
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U)
|
||||
#if TFM_LVL == 0
|
||||
SAU_INIT_REGION(1);
|
||||
#else
|
||||
#error("TFM doesn't support SAU_INIT_REGION1")
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U)
|
||||
#if TFM_LVL == 0
|
||||
SAU_INIT_REGION(2);
|
||||
#else
|
||||
#error("TFM doesn't support SAU_INIT_REGION2")
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U)
|
||||
#if TFM_LVL == 0
|
||||
SAU_INIT_REGION(3);
|
||||
#else
|
||||
SAU_INIT_REGION(3, TFM_NS_REGION_VENEER);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U)
|
||||
#if TFM_LVL == 0
|
||||
SAU_INIT_REGION(4);
|
||||
#else
|
||||
SAU_INIT_REGION(4, TFM_NS_REGION_CODE);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U)
|
||||
#if TFM_LVL == 0
|
||||
SAU_INIT_REGION(5);
|
||||
#else
|
||||
#warning("TFM doesn't support SAU_INIT_REGION5")
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U)
|
||||
#if TFM_LVL == 0
|
||||
SAU_INIT_REGION(6);
|
||||
#else
|
||||
SAU_INIT_REGION(6, TFM_NS_REGION_DATA);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U)
|
||||
#if TFM_LVL == 0
|
||||
SAU_INIT_REGION(7);
|
||||
#else
|
||||
SAU_INIT_REGION(7, TFM_NS_REGION_PERIPH_1);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* repeat this for all possible SAU regions */
|
||||
|
||||
#if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U)
|
||||
SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) |
|
||||
((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ;
|
||||
#endif
|
||||
|
||||
#endif /* defined (__SAU_PRESENT) && (__SAU_PRESENT == 1U) */
|
||||
}
|
||||
|
||||
void SCB_Setup(void)
|
||||
{
|
||||
#if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U)
|
||||
SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk)) |
|
||||
((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk);
|
||||
|
||||
// SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_SYSRESETREQS_Msk | SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk)) |
|
||||
// ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) |
|
||||
// ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk) |
|
||||
// ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk);
|
||||
|
||||
SCB->AIRCR = (0x05FA << 16) |
|
||||
((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) |
|
||||
((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk) |
|
||||
((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk);
|
||||
|
||||
|
||||
|
||||
#endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */
|
||||
|
||||
#if defined (SCB_ICSR_INIT) && (SCB_ICSR_INIT == 1U)
|
||||
SCB->ICSR = (SCB->ICSR & ~(SCB_ICSR_STTNS_Msk)) |
|
||||
((SCB_ICSR_STTNS_VAL << SCB_ICSR_STTNS_Pos) & SCB_ICSR_STTNS_Msk);
|
||||
#endif /* defined (SCB_ICSR_INIT) && (SCB_ICSR_INIT == 1U) */
|
||||
}
|
||||
|
||||
void TZ_NVIC_Setup(void)
|
||||
{
|
||||
#if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U)
|
||||
NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL;
|
||||
#endif
|
||||
|
||||
#if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U)
|
||||
NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL;
|
||||
#endif
|
||||
|
||||
#if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U)
|
||||
NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL;
|
||||
#endif
|
||||
|
||||
#if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U)
|
||||
NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL;
|
||||
#endif
|
||||
|
||||
/* repeat this for all possible ITNS elements */
|
||||
}
|
||||
|
||||
#endif /* #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2019-2020, Nuvoton Technology Corporation
|
||||
* Copyright (c) 2018-2019, Nuvoton Technology Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
|
|
@ -21,48 +21,31 @@
|
|||
|
||||
#include "partition_M2351_mem.h"
|
||||
|
||||
#define NU_TZ_SECURE_FLASH_SIZE NU_ROM_SIZE_S
|
||||
#define NU_TZ_SECURE_SRAM_SIZE NU_RAM_SIZE_S
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
|
||||
#if defined(__ARMCC_VERSION)
|
||||
|
||||
extern int Load$$LR$$LR_IROM_NSC$$Base;
|
||||
extern int Load$$LR$$LR_IROM_NSC$$Length;
|
||||
|
||||
#define NU_TZ_NSC_REGION_START ((uint32_t) &Load$$LR$$LR_IROM_NSC$$Base)
|
||||
#define NU_TZ_NSC_REGION_SIZE ((uint32_t) &Load$$LR$$LR_IROM_NSC$$Length)
|
||||
extern int Image$$ER_IROM_NSC$$Base;
|
||||
#define NU_TZ_NSC_REGION_START ((uint32_t) &Image$$ER_IROM_NSC$$Base)
|
||||
#define NU_TZ_NSC_REGION_SIZE (NU_TZ_NSC_SIZE)
|
||||
|
||||
#elif defined(__ICCARM__)
|
||||
|
||||
extern int __NU_TZ_NSC_start__;
|
||||
extern int __NU_TZ_NSC_size__;
|
||||
|
||||
#define NU_TZ_NSC_REGION_START ((uint32_t) &__NU_TZ_NSC_start__)
|
||||
#define NU_TZ_NSC_REGION_SIZE ((uint32_t) &__NU_TZ_NSC_size__)
|
||||
extern int Image$$ER_IROM_NSC$$Base;
|
||||
#define NU_TZ_NSC_REGION_START ((uint32_t) &Image$$ER_IROM_NSC$$Base)
|
||||
#define NU_TZ_NSC_REGION_SIZE (NU_TZ_NSC_SIZE)
|
||||
|
||||
#elif defined(__GNUC__)
|
||||
|
||||
extern int __nu_tz_nsc_start;
|
||||
extern int __nu_tz_nsc_size;
|
||||
|
||||
#define NU_TZ_NSC_REGION_START ((uint32_t) &__nu_tz_nsc_start)
|
||||
#define NU_TZ_NSC_REGION_SIZE ((uint32_t) &__nu_tz_nsc_size)
|
||||
extern int Image$$ER_IROM_NSC$$Base;
|
||||
#define NU_TZ_NSC_REGION_START ((uint32_t) &Image$$ER_IROM_NSC$$Base)
|
||||
#define NU_TZ_NSC_REGION_SIZE (NU_TZ_NSC_SIZE)
|
||||
|
||||
#endif
|
||||
|
||||
/* Check relevant macros have been defined */
|
||||
#if (! defined(NU_TZ_SECURE_FLASH_SIZE))
|
||||
#error("NU_TZ_SECURE_FLASH_SIZE not defined")
|
||||
#endif
|
||||
#if (! defined(NU_TZ_SECURE_SRAM_SIZE))
|
||||
#error("NU_TZ_SECURE_SRAM_SIZE not defined")
|
||||
#endif
|
||||
#if (! defined(NU_TZ_NSC_REGION_START))
|
||||
#error("NU_TZ_NSC_REGION_START not defined")
|
||||
#endif
|
||||
#if (! defined(NU_TZ_NSC_REGION_SIZE))
|
||||
#error("NU_TZ_NSC_REGION_SIZE not defined")
|
||||
#endif
|
||||
|
||||
/*
|
||||
//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------
|
||||
|
|
@ -88,7 +71,7 @@ extern int __nu_tz_nsc_size;
|
|||
// <0x16000=> 88KB
|
||||
// <0x18000=> 96KB
|
||||
*/
|
||||
#define SCU_SECURE_SRAM_SIZE NU_TZ_SECURE_SRAM_SIZE
|
||||
#define SCU_SECURE_SRAM_SIZE NU_RAM_SIZE_S
|
||||
#define NON_SECURE_SRAM_BASE (0x30000000 + SCU_SECURE_SRAM_SIZE)
|
||||
|
||||
|
||||
|
|
@ -103,58 +86,10 @@ extern int __nu_tz_nsc_size;
|
|||
// <o>Secure Flash ROM Size <0x800-0x7FFFF:0x800>
|
||||
*/
|
||||
|
||||
#define FMC_SECURE_ROM_SIZE NU_TZ_SECURE_FLASH_SIZE
|
||||
#define FMC_SECURE_ROM_SIZE NU_ROM_SIZE_S
|
||||
|
||||
#define FMC_NON_SECURE_BASE (0x10000000 + FMC_SECURE_ROM_SIZE)
|
||||
|
||||
__STATIC_INLINE void FMC_NSBA_Setup(void)
|
||||
{
|
||||
/* Skip NSBA Setupt according config */
|
||||
if(FMC_INIT_NSBA == 0)
|
||||
return;
|
||||
|
||||
/* Check if NSBA value with current active NSBA */
|
||||
if(SCU->FNSADDR != FMC_SECURE_ROM_SIZE)
|
||||
{
|
||||
/* Unlock Protected Register */
|
||||
SYS_UnlockReg();
|
||||
|
||||
/* Enable ISP and config update */
|
||||
FMC->ISPCTL = FMC_ISPCTL_ISPEN_Msk | FMC_ISPCTL_CFGUEN_Msk;
|
||||
|
||||
/* Config Base of NSBA */
|
||||
FMC->ISPADDR = 0x200800;
|
||||
|
||||
/* Read Non-secure base address config */
|
||||
FMC->ISPCMD = FMC_ISPCMD_READ;
|
||||
FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
|
||||
while(FMC->ISPTRG);
|
||||
|
||||
/* Setting NSBA when it is empty */
|
||||
if(FMC->ISPDAT == 0xfffffffful)
|
||||
{
|
||||
FMC->ISPDAT = FMC_SECURE_ROM_SIZE;
|
||||
FMC->ISPCMD = FMC_ISPCMD_PROGRAM;
|
||||
FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
|
||||
while(FMC->ISPTRG);
|
||||
|
||||
/* Force Chip Reset to valid new setting */
|
||||
SYS->IPRST0 = SYS_IPRST0_CHIPRST_Msk;
|
||||
}
|
||||
|
||||
/* Fatal Error:
|
||||
FMC NSBA setting is different to FMC_INIT_NSBA_VAL.
|
||||
User must double confirm which one is wrong.
|
||||
|
||||
If user need to change NSBA config of FMC, user must do Mess-erase by
|
||||
ISP or ICP.
|
||||
*/
|
||||
while(1);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
||||
/*--------------------------------------------------------------------------------------------------------*/
|
||||
|
||||
|
||||
|
|
@ -300,37 +235,6 @@ __STATIC_INLINE void FMC_NSBA_Setup(void)
|
|||
// </h>
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/**
|
||||
\brief Setup SCU Configuration Unit
|
||||
\details
|
||||
|
||||
*/
|
||||
__STATIC_INLINE void SCU_Setup(void)
|
||||
{
|
||||
int32_t i;
|
||||
|
||||
SCU->PNSSET[0] = SCU_INIT_PNSSET0_VAL;
|
||||
SCU->PNSSET[1] = SCU_INIT_PNSSET1_VAL;
|
||||
SCU->PNSSET[2] = SCU_INIT_PNSSET2_VAL;
|
||||
SCU->PNSSET[3] = SCU_INIT_PNSSET3_VAL;
|
||||
SCU->PNSSET[4] = SCU_INIT_PNSSET4_VAL;
|
||||
SCU->PNSSET[5] = SCU_INIT_PNSSET5_VAL;
|
||||
SCU->PNSSET[6] = SCU_INIT_PNSSET6_VAL;
|
||||
|
||||
SCU->IONSSET = SCU_INIT_IONSSET_VAL;
|
||||
|
||||
/* Set Non-secure SRAM */
|
||||
for(i = 11; i >= SCU_SECURE_SRAM_SIZE / 8192; i--)
|
||||
{
|
||||
SCU->SRAMNSSET |= (1U << i);
|
||||
}
|
||||
|
||||
|
||||
}
|
||||
|
||||
|
||||
/* ---------------------------------------------------------------------------------------------------- */
|
||||
|
||||
/*
|
||||
|
|
@ -763,109 +667,58 @@ __STATIC_INLINE void SCU_Setup(void)
|
|||
SAU regions are defined in partition.h
|
||||
*/
|
||||
|
||||
#if TFM_LVL == 0
|
||||
#define SAU_INIT_REGION(n) \
|
||||
SAU->RNR = (n & SAU_RNR_REGION_Msk); \
|
||||
SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \
|
||||
SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \
|
||||
((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U
|
||||
#else
|
||||
#define SAU_INIT_REGION(n, tfm_n) \
|
||||
SAU->RNR = (tfm_n & SAU_RNR_REGION_Msk); \
|
||||
SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \
|
||||
SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \
|
||||
((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U
|
||||
#endif
|
||||
|
||||
|
||||
#if SCB_AIRCR_SYSRESETREQS_VAL == 1
|
||||
#warning ("Debugger (and other) resets fail when SCB_AIRCR_SYSRESETREQS_VAL == 1!!!")
|
||||
#endif
|
||||
|
||||
/**
|
||||
\brief Setup a SAU Region
|
||||
\details Writes the region information contained in SAU_Region to the
|
||||
registers SAU_RNR, SAU_RBAR, and SAU_RLAR
|
||||
* \brief Setup SAU regions
|
||||
* \details Writes the region information contained in SAU_Region to the
|
||||
* registers SAU_RNR, SAU_RBAR, and SAU_RLAR
|
||||
*/
|
||||
void TZ_SAU_Setup(void);
|
||||
|
||||
/**
|
||||
* \brief Setup System Control Block
|
||||
*/
|
||||
void SCB_Setup(void);
|
||||
|
||||
/**
|
||||
* \brief Setup NVIC interrupt target state
|
||||
*/
|
||||
__STATIC_INLINE void TZ_SAU_Setup(void)
|
||||
{
|
||||
void TZ_NVIC_Setup(void);
|
||||
|
||||
#if defined (__SAU_PRESENT) && (__SAU_PRESENT == 1U)
|
||||
/**
|
||||
*\brief Setup SCU Configuration Unit
|
||||
*/
|
||||
void SCU_Setup(void);
|
||||
|
||||
#if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U)
|
||||
SAU_INIT_REGION(0);
|
||||
#endif
|
||||
|
||||
#if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U)
|
||||
SAU_INIT_REGION(1);
|
||||
#endif
|
||||
|
||||
#if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U)
|
||||
SAU_INIT_REGION(2);
|
||||
#endif
|
||||
|
||||
#if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U)
|
||||
SAU_INIT_REGION(3);
|
||||
#endif
|
||||
|
||||
#if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U)
|
||||
SAU_INIT_REGION(4);
|
||||
#endif
|
||||
|
||||
#if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U)
|
||||
SAU_INIT_REGION(5);
|
||||
#endif
|
||||
|
||||
#if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U)
|
||||
SAU_INIT_REGION(6);
|
||||
#endif
|
||||
|
||||
#if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U)
|
||||
SAU_INIT_REGION(7);
|
||||
#endif
|
||||
|
||||
/* repeat this for all possible SAU regions */
|
||||
|
||||
|
||||
#if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U)
|
||||
SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) |
|
||||
((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ;
|
||||
#endif
|
||||
|
||||
#endif /* defined (__SAU_PRESENT) && (__SAU_PRESENT == 1U) */
|
||||
|
||||
#if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U)
|
||||
SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk)) |
|
||||
((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk);
|
||||
|
||||
// SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_SYSRESETREQS_Msk | SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk)) |
|
||||
// ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) |
|
||||
// ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk) |
|
||||
// ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk);
|
||||
|
||||
SCB->AIRCR = (0x05FA << 16) |
|
||||
((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) |
|
||||
((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk) |
|
||||
((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk);
|
||||
|
||||
|
||||
|
||||
#endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */
|
||||
|
||||
#if defined (SCB_ICSR_INIT) && (SCB_ICSR_INIT == 1U)
|
||||
SCB->ICSR = (SCB->ICSR & ~(SCB_ICSR_STTNS_Msk)) |
|
||||
((SCB_ICSR_STTNS_VAL << SCB_ICSR_STTNS_Pos) & SCB_ICSR_STTNS_Msk);
|
||||
#endif /* defined (SCB_ICSR_INIT) && (SCB_ICSR_INIT == 1U) */
|
||||
|
||||
#if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U)
|
||||
NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL;
|
||||
#endif
|
||||
|
||||
#if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U)
|
||||
NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL;
|
||||
#endif
|
||||
|
||||
#if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U)
|
||||
NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL;
|
||||
#endif
|
||||
|
||||
#if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U)
|
||||
NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL;
|
||||
#endif
|
||||
|
||||
|
||||
/* repeat this for all possible ITNS elements */
|
||||
|
||||
}
|
||||
/**
|
||||
* \brief Configure Non-secure flash boundary for the first time after Mass Erase or
|
||||
* check if flash partition matches SCU.FNSADDR which has already configured
|
||||
* and fixed until next Mass Erase.
|
||||
*/
|
||||
void FMC_NSBA_Setup(void);
|
||||
|
||||
#endif /* #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
|
||||
|
||||
#endif /* PARTITION_M2351 */
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* PARTITION_M2351 */
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2019-2020, Nuvoton Technology Corporation
|
||||
* Copyright (c) 2018-2019, Nuvoton Technology Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
|
|
@ -39,37 +39,79 @@
|
|||
*/
|
||||
#if defined(DOMAIN_NS) && DOMAIN_NS
|
||||
|
||||
/* Default non-secure ROM layout */
|
||||
/* Resolve non-secure ROM start */
|
||||
#ifndef MBED_ROM_START
|
||||
#ifdef PSA_NON_SECURE_ROM_START
|
||||
#define MBED_ROM_START (PSA_NON_SECURE_ROM_START)
|
||||
#else
|
||||
#define MBED_ROM_START (0x10040000)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* Resolve non-secure ROM size */
|
||||
#ifndef MBED_ROM_SIZE
|
||||
#ifdef PSA_NON_SECURE_ROM_SIZE
|
||||
#define MBED_ROM_SIZE (PSA_NON_SECURE_ROM_SIZE)
|
||||
#else
|
||||
#define MBED_ROM_SIZE (0x40000)
|
||||
#endif
|
||||
/* Default non-secure RAM layout */
|
||||
#endif
|
||||
|
||||
/* Resolve non-secure RAM start */
|
||||
#ifndef MBED_RAM_START
|
||||
#ifdef PSA_NON_SECURE_RAM_START
|
||||
#define MBED_RAM_START (PSA_NON_SECURE_RAM_START)
|
||||
#else
|
||||
#define MBED_RAM_START (0x30008000)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* Resolve non-secure RAM size */
|
||||
#ifndef MBED_RAM_SIZE
|
||||
#ifdef PSA_NON_SECURE_RAM_SIZE
|
||||
#define MBED_RAM_SIZE (PSA_NON_SECURE_RAM_SIZE)
|
||||
#else
|
||||
#define MBED_RAM_SIZE (0x10000)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#else
|
||||
|
||||
/* Default secure ROM layout */
|
||||
/* Resolve secure ROM start */
|
||||
#ifndef MBED_ROM_START
|
||||
#ifdef PSA_SECURE_ROM_START
|
||||
#define MBED_ROM_START (PSA_SECURE_ROM_START)
|
||||
#else
|
||||
#define MBED_ROM_START (0x0)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* Resolve secure ROM size */
|
||||
#ifndef MBED_ROM_SIZE
|
||||
#ifdef PSA_SECURE_ROM_SIZE
|
||||
#define MBED_ROM_SIZE (PSA_SECURE_ROM_SIZE)
|
||||
#else
|
||||
#define MBED_ROM_SIZE (0x40000)
|
||||
#endif
|
||||
/* Default secure RAM layout */
|
||||
#endif
|
||||
|
||||
/* Resolve secure RAM start */
|
||||
#ifndef MBED_RAM_START
|
||||
#ifdef PSA_SECURE_RAM_START
|
||||
#define MBED_RAM_START (PSA_SECURE_RAM_START)
|
||||
#else
|
||||
#define MBED_RAM_START (0x20000000)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* Resolve secure RAM size */
|
||||
#ifndef MBED_RAM_SIZE
|
||||
#ifdef PSA_SECURE_RAM_SIZE
|
||||
#define MBED_RAM_SIZE (PSA_SECURE_RAM_SIZE)
|
||||
#else
|
||||
#define MBED_RAM_SIZE (0x8000)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
|
|
@ -108,4 +150,124 @@
|
|||
|
||||
#endif
|
||||
|
||||
/* Mbed build tool passes just APPLICATION_xxx macros to C/C++ files and just
|
||||
* MBED_APP_xxx macros to linker files even though they mean the same thing.
|
||||
* Because this file is to include by both C/C++ files and linker files, we add
|
||||
* these macros according to the others for consistency when they are missing
|
||||
* in compile or link stage. */
|
||||
|
||||
#ifndef APPLICATION_ADDR
|
||||
#ifdef MBED_APP_START
|
||||
#define APPLICATION_ADDR MBED_APP_START
|
||||
#else
|
||||
#define APPLICATION_ADDR MBED_ROM_START
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef APPLICATION_SIZE
|
||||
#ifdef MBED_APP_SIZE
|
||||
#define APPLICATION_SIZE MBED_APP_SIZE
|
||||
#else
|
||||
#define APPLICATION_SIZE MBED_ROM_SIZE
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef APPLICATION_RAM_ADDR
|
||||
#ifdef MBED_RAM_APP_START
|
||||
#define APPLICATION_RAM_ADDR MBED_RAM_APP_START
|
||||
#else
|
||||
#define APPLICATION_RAM_ADDR MBED_RAM_START
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef APPLICATION_RAM_SIZE
|
||||
#ifdef MBED_RAM_APP_SIZE
|
||||
#define APPLICATION_RAM_SIZE MBED_RAM_APP_SIZE
|
||||
#else
|
||||
#define APPLICATION_RAM_SIZE MBED_RAM_SIZE
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef MBED_APP_START
|
||||
#define MBED_APP_START APPLICATION_ADDR
|
||||
#endif
|
||||
|
||||
#ifndef MBED_APP_SIZE
|
||||
#define MBED_APP_SIZE APPLICATION_SIZE
|
||||
#endif
|
||||
|
||||
#ifndef MBED_RAM_APP_START
|
||||
#define MBED_RAM_APP_START APPLICATION_RAM_ADDR
|
||||
#endif
|
||||
|
||||
#ifndef MBED_RAM_APP_SIZE
|
||||
#define MBED_RAM_APP_SIZE APPLICATION_RAM_SIZE
|
||||
#endif
|
||||
|
||||
#if (APPLICATION_ADDR != MBED_APP_START)
|
||||
#error("APPLICATION_ADDR and MBED_APP_START are not the same!!!")
|
||||
#endif
|
||||
|
||||
#if (APPLICATION_SIZE != MBED_APP_SIZE)
|
||||
#error("APPLICATION_SIZE and MBED_APP_SIZE are not the same!!!")
|
||||
#endif
|
||||
|
||||
#if (APPLICATION_RAM_ADDR != MBED_RAM_APP_START)
|
||||
#error("APPLICATION_RAM_ADDR and MBED_RAM_APP_START are not the same!!!")
|
||||
#endif
|
||||
|
||||
#if (APPLICATION_RAM_SIZE != MBED_RAM_APP_SIZE)
|
||||
#error("APPLICATION_RAM_SIZE and MBED_RAM_APP_SIZE are not the same!!!")
|
||||
#endif
|
||||
|
||||
/* Determine NSC area
|
||||
*
|
||||
* Requirements for NSC area:
|
||||
* 1. Requested by SAU, NSC area must start at 32 byte-aligned boundary.
|
||||
* 2. By IDAU, 0~0x4000 is secure. NSC can only locate in 0x4000~0x10000000.
|
||||
* 3. Greentea flash IAP uses last 2 sectors for its test. Avoid this range.
|
||||
* 4. Greentea NVSTORE uses last 2 sectors or 4 KiB x 2 for its test. Avoid this range.
|
||||
* 5. KVStore uses last a few KiB. Avoid this range.
|
||||
* 6. Due to TFM build process, TFM and its tests must generate the same cmse_lib.o.
|
||||
* To this end, TZ NSC location must fix at a well-known location and cannot place
|
||||
* arbitrarily.
|
||||
*
|
||||
* Configurable for NSC area:
|
||||
* We cannot configure NSC location via configuration parameter because the generated
|
||||
* configuration macros are just passed to C/C++ files but not to linker files. So
|
||||
* we can only hardcode NSC location here as constants (to be included by linker file).
|
||||
*
|
||||
* Locate NSC area at end of secure flash:
|
||||
* We decide to locate NSC area at end of secure flash. To avoid this area
|
||||
* accidentally erased by flash IAP operation, flash IAP must configure to exclude
|
||||
* this area.
|
||||
*/
|
||||
/* TZ NSC area defaults to from secure ROM end */
|
||||
#define NU_TZ_NSC_START (NU_ROM_START_S + NU_ROM_SIZE_S - NU_TZ_NSC_SIZE)
|
||||
/* TZ NSC area defaults to 4KiB. */
|
||||
#define NU_TZ_NSC_SIZE 0x1000
|
||||
|
||||
/* Configuration of TDB internal storage area
|
||||
*
|
||||
* 1. Must match "tdb_internal/mbed_lib.json"
|
||||
* 2. Can pass to linker files for memory layout check
|
||||
*
|
||||
* With this approach, we can pass this configuration from "tdb_internal/mbed_lib.json"
|
||||
* to linker file for detecting memory layout error before run-time.
|
||||
*/
|
||||
#if !defined(DOMAIN_NS) || (DOMAIN_NS == 0)
|
||||
#if (TFM_LVL > 0)
|
||||
/* TDB internal storage area defaults to 32KiB at end of flash. */
|
||||
#define NU_TDB_INTERNAL_STORAGE_START (NU_ROM_START_S + NU_ROM_SIZE_S - NU_TZ_NSC_SIZE - NU_TDB_INTERNAL_STORAGE_SIZE)
|
||||
#define NU_TDB_INTERNAL_STORAGE_SIZE 0x8000
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* Configuration of flash IAP area */
|
||||
#define NU_FLASHIAP_SECURE_START NU_ROM_START_S
|
||||
/* Exclude NSC area to avoid accidentally erased */
|
||||
#define NU_FLASHIAP_SECURE_SIZE (NU_ROM_SIZE_S - NU_TZ_NSC_SIZE)
|
||||
#define NU_FLASHIAP_NONSECURE_START NU_ROM_START_NS
|
||||
#define NU_FLASHIAP_NONSECURE_SIZE NU_ROM_SIZE_NS
|
||||
|
||||
#endif /* __PARTITION_M2351_MEM_H__ */
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2019-2020, Nuvoton Technology Corporation
|
||||
* Copyright (c) 2018-2019, Nuvoton Technology Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
|
|
@ -30,36 +30,78 @@
|
|||
*/
|
||||
#if defined(DOMAIN_NS) && DOMAIN_NS
|
||||
|
||||
/* Default non-secure ROM layout */
|
||||
/* Resolve non-secure ROM start */
|
||||
if (! isdefinedsymbol(MBED_ROM_START)) {
|
||||
define symbol MBED_ROM_START = 0x10040000;
|
||||
if (isdefinedsymbol(PSA_NON_SECURE_ROM_START)) {
|
||||
define symbol MBED_ROM_START = PSA_NON_SECURE_ROM_START;
|
||||
} else {
|
||||
define symbol MBED_ROM_START = 0x10040000;
|
||||
}
|
||||
}
|
||||
|
||||
/* Resolve non-secure ROM size */
|
||||
if (! isdefinedsymbol(MBED_ROM_SIZE)) {
|
||||
define symbol MBED_ROM_SIZE = 0x40000;
|
||||
if (isdefinedsymbol(PSA_NON_SECURE_ROM_SIZE)) {
|
||||
define symbol MBED_ROM_SIZE = PSA_NON_SECURE_ROM_SIZE;
|
||||
} else {
|
||||
define symbol MBED_ROM_SIZE = 0x40000;
|
||||
}
|
||||
}
|
||||
/* Default non-secure RAM layout */
|
||||
|
||||
/* Resolve non-secure RAM start */
|
||||
if (! isdefinedsymbol(MBED_RAM_START)) {
|
||||
define symbol MBED_RAM_START = 0x30008000;
|
||||
if (isdefinedsymbol(PSA_NON_SECURE_RAM_START)) {
|
||||
define symbol MBED_RAM_START = PSA_NON_SECURE_RAM_START;
|
||||
} else {
|
||||
define symbol MBED_RAM_START = 0x30008000;
|
||||
}
|
||||
}
|
||||
|
||||
/* Resolve non-secure RAM size */
|
||||
if (! isdefinedsymbol(MBED_RAM_SIZE)) {
|
||||
define symbol MBED_RAM_SIZE = 0x10000;
|
||||
if (isdefinedsymbol(PSA_NON_SECURE_RAM_SIZE)) {
|
||||
define symbol MBED_RAM_SIZE = PSA_NON_SECURE_RAM_SIZE;
|
||||
} else {
|
||||
define symbol MBED_RAM_SIZE = 0x10000;
|
||||
}
|
||||
}
|
||||
|
||||
#else
|
||||
|
||||
/* Default secure ROM layout */
|
||||
/* Resolve secure ROM start */
|
||||
if (! isdefinedsymbol(MBED_ROM_START)) {
|
||||
define symbol MBED_ROM_START = 0x0;
|
||||
if (isdefinedsymbol(PSA_SECURE_ROM_START)) {
|
||||
define symbol MBED_ROM_START = PSA_SECURE_ROM_START;
|
||||
} else {
|
||||
define symbol MBED_ROM_START = 0x0;
|
||||
}
|
||||
}
|
||||
|
||||
/* Resolve secure ROM size */
|
||||
if (! isdefinedsymbol(MBED_ROM_SIZE)) {
|
||||
define symbol MBED_ROM_SIZE = 0x40000;
|
||||
if (isdefinedsymbol(PSA_SECURE_ROM_SIZE)) {
|
||||
define symbol MBED_ROM_SIZE = PSA_SECURE_ROM_SIZE;
|
||||
} else {
|
||||
define symbol MBED_ROM_SIZE = 0x40000;
|
||||
}
|
||||
}
|
||||
/* Default secure RAM layout */
|
||||
|
||||
/* Resolve secure RAM start */
|
||||
if (! isdefinedsymbol(MBED_RAM_START)) {
|
||||
define symbol MBED_RAM_START = 0x20000000;
|
||||
if (isdefinedsymbol(PSA_SECURE_RAM_START)) {
|
||||
define symbol MBED_RAM_START = PSA_SECURE_RAM_START;
|
||||
} else {
|
||||
define symbol MBED_RAM_START = 0x20000000;
|
||||
}
|
||||
}
|
||||
|
||||
/* Resolve secure RAM size */
|
||||
if (! isdefinedsymbol(MBED_RAM_SIZE)) {
|
||||
define symbol MBED_RAM_SIZE = 0x8000;
|
||||
if (isdefinedsymbol(PSA_SECURE_RAM_SIZE)) {
|
||||
define symbol MBED_RAM_SIZE = PSA_SECURE_RAM_SIZE;
|
||||
} else {
|
||||
define symbol MBED_RAM_SIZE = 0x8000;
|
||||
}
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
@ -98,3 +140,41 @@ define symbol NU_RAM_START_NS = (0x30000000 + MBED_RAM_SIZE);
|
|||
define symbol NU_RAM_SIZE_NS = (0x18000 - MBED_RAM_SIZE);
|
||||
|
||||
#endif
|
||||
|
||||
if (isdefinedsymbol(DOMAIN_NS)) {
|
||||
|
||||
if (! isdefinedsymbol(MBED_APP_START)) {
|
||||
define symbol MBED_APP_START = NU_ROM_START_NS;
|
||||
}
|
||||
|
||||
if (! isdefinedsymbol(MBED_APP_SIZE)) {
|
||||
define symbol MBED_APP_SIZE = NU_ROM_SIZE_NS;
|
||||
}
|
||||
|
||||
if (! isdefinedsymbol(MBED_RAM_APP_START)) {
|
||||
define symbol MBED_RAM_APP_START = NU_RAM_START_NS;
|
||||
}
|
||||
|
||||
if (! isdefinedsymbol(MBED_RAM_APP_SIZE)) {
|
||||
define symbol MBED_RAM_APP_SIZE = NU_RAM_SIZE_NS;
|
||||
}
|
||||
|
||||
} else {
|
||||
|
||||
if (! isdefinedsymbol(MBED_APP_START)) {
|
||||
define symbol MBED_APP_START = NU_ROM_START_S;
|
||||
}
|
||||
|
||||
if (! isdefinedsymbol(MBED_APP_SIZE)) {
|
||||
define symbol MBED_APP_SIZE = NU_ROM_SIZE_S;
|
||||
}
|
||||
|
||||
if (! isdefinedsymbol(MBED_RAM_APP_START)) {
|
||||
define symbol MBED_RAM_APP_START = NU_RAM_START_S;
|
||||
}
|
||||
|
||||
if (! isdefinedsymbol(MBED_RAM_APP_SIZE)) {
|
||||
define symbol MBED_RAM_APP_SIZE = NU_RAM_SIZE_S;
|
||||
}
|
||||
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,20 +1,26 @@
|
|||
/**************************************************************************//**
|
||||
* @file startup_M2351.c
|
||||
* @version V2.00
|
||||
* $Revision: 9 $
|
||||
* $Date: 16/08/27 12:33p $
|
||||
* @brief Startup Source File
|
||||
/*
|
||||
* Copyright (c) 2018-2019, Nuvoton Technology Corporation
|
||||
*
|
||||
* @note
|
||||
* Copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
******************************************************************************/
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#include "M2351.h"
|
||||
|
||||
/* Suppress warning messages */
|
||||
#if defined(__CC_ARM)
|
||||
// Suppress warning message: extended constant initialiser used
|
||||
// Suppress warning message: extended constant initializer used
|
||||
#pragma diag_suppress 1296
|
||||
#elif defined(__ICCARM__)
|
||||
#elif defined(__GNUC__)
|
||||
|
|
@ -49,19 +55,21 @@ void FUN(void) __attribute__ ((weak, alias(#FUN_ALIAS)));
|
|||
|
||||
/* Initialize segments */
|
||||
#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
|
||||
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) && (TFM_LVL > 0)
|
||||
extern uint32_t Image$$ARM_LIB_STACK_MSP$$ZI$$Limit;
|
||||
#else
|
||||
extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit;
|
||||
#endif
|
||||
extern void __main(void);
|
||||
#elif defined(__ICCARM__)
|
||||
void __iar_program_start(void);
|
||||
#elif defined(__GNUC__)
|
||||
extern uint32_t __StackTop;
|
||||
extern uint32_t __etext;
|
||||
extern uint32_t __data_start__;
|
||||
extern uint32_t __data_end__;
|
||||
extern uint32_t __bss_start__;
|
||||
extern uint32_t __bss_end__;
|
||||
extern uint32_t __copy_table_start__;
|
||||
extern uint32_t __copy_table_end__;
|
||||
extern uint32_t __zero_table_start__;
|
||||
extern uint32_t __zero_table_end__;
|
||||
|
||||
extern void uvisor_init(void);
|
||||
#if defined(TOOLCHAIN_GCC_ARM)
|
||||
extern void _start(void);
|
||||
#else
|
||||
|
|
@ -87,7 +95,7 @@ WEAK_ALIAS_FUNC(SysTick_Handler, Default_Handler)
|
|||
WEAK_ALIAS_FUNC(BOD_IRQHandler, Default_Handler) // 0: Brown Out detection
|
||||
WEAK_ALIAS_FUNC(IRC_IRQHandler, Default_Handler) // 1: Internal RC
|
||||
WEAK_ALIAS_FUNC(PWRWU_IRQHandler, Default_Handler) // 2: Power down wake up
|
||||
WEAK_ALIAS_FUNC(SRAM_IRQHandler, Default_Handler) // 3: SRAM
|
||||
WEAK_ALIAS_FUNC(SRAM_IRQHandler, Default_Handler) // 3: SRAM
|
||||
WEAK_ALIAS_FUNC(CLKFAIL_IRQHandler, Default_Handler) // 4: Clock detection fail
|
||||
// 5: Reserved
|
||||
WEAK_ALIAS_FUNC(RTC_IRQHandler, Default_Handler) // 6: Real Time Clock
|
||||
|
|
@ -106,16 +114,16 @@ WEAK_ALIAS_FUNC(GPC_IRQHandler, Default_Handler) // 18: GPIO Port C
|
|||
WEAK_ALIAS_FUNC(GPD_IRQHandler, Default_Handler) // 19: GPIO Port D
|
||||
WEAK_ALIAS_FUNC(GPE_IRQHandler, Default_Handler) // 20: GPIO Port E
|
||||
WEAK_ALIAS_FUNC(GPF_IRQHandler, Default_Handler) // 21: GPIO Port F
|
||||
WEAK_ALIAS_FUNC(QSPI0_IRQHandler, Default_Handler) // 22: SPI0
|
||||
WEAK_ALIAS_FUNC(QSPI0_IRQHandler, Default_Handler) // 22: SPI0
|
||||
WEAK_ALIAS_FUNC(SPI0_IRQHandler, Default_Handler) // 23: SPI1
|
||||
WEAK_ALIAS_FUNC(BRAKE0_IRQHandler, Default_Handler) // 24:
|
||||
WEAK_ALIAS_FUNC(EPWM0_P0_IRQHandler, Default_Handler) // 25:
|
||||
WEAK_ALIAS_FUNC(EPWM0_P1_IRQHandler, Default_Handler) // 26:
|
||||
WEAK_ALIAS_FUNC(EPWM0_P2_IRQHandler, Default_Handler) // 27:
|
||||
WEAK_ALIAS_FUNC(EPWM0_P0_IRQHandler, Default_Handler) // 25:
|
||||
WEAK_ALIAS_FUNC(EPWM0_P1_IRQHandler, Default_Handler) // 26:
|
||||
WEAK_ALIAS_FUNC(EPWM0_P2_IRQHandler, Default_Handler) // 27:
|
||||
WEAK_ALIAS_FUNC(BRAKE1_IRQHandler, Default_Handler) // 28:
|
||||
WEAK_ALIAS_FUNC(EPWM1_P0_IRQHandler, Default_Handler) // 29:
|
||||
WEAK_ALIAS_FUNC(EPWM1_P1_IRQHandler, Default_Handler) // 30:
|
||||
WEAK_ALIAS_FUNC(EPWM1_P2_IRQHandler, Default_Handler) // 31:
|
||||
WEAK_ALIAS_FUNC(EPWM1_P0_IRQHandler, Default_Handler) // 29:
|
||||
WEAK_ALIAS_FUNC(EPWM1_P1_IRQHandler, Default_Handler) // 30:
|
||||
WEAK_ALIAS_FUNC(EPWM1_P2_IRQHandler, Default_Handler) // 31:
|
||||
WEAK_ALIAS_FUNC(TMR0_IRQHandler, Default_Handler) // 32: Timer 0
|
||||
WEAK_ALIAS_FUNC(TMR1_IRQHandler, Default_Handler) // 33: Timer 1
|
||||
WEAK_ALIAS_FUNC(TMR2_IRQHandler, Default_Handler) // 34: Timer 2
|
||||
|
|
@ -124,7 +132,7 @@ WEAK_ALIAS_FUNC(UART0_IRQHandler, Default_Handler) // 36: UART0
|
|||
WEAK_ALIAS_FUNC(UART1_IRQHandler, Default_Handler) // 37: UART1
|
||||
WEAK_ALIAS_FUNC(I2C0_IRQHandler, Default_Handler) // 38: I2C0
|
||||
WEAK_ALIAS_FUNC(I2C1_IRQHandler, Default_Handler) // 39: I2C1
|
||||
WEAK_ALIAS_FUNC(PDMA0_IRQHandler, Default_Handler) // 40: Peripheral DMA
|
||||
WEAK_ALIAS_FUNC(PDMA0_IRQHandler, Default_Handler) // 40: Peripheral DMA
|
||||
WEAK_ALIAS_FUNC(DAC_IRQHandler, Default_Handler) // 41: DAC
|
||||
WEAK_ALIAS_FUNC(EADC0_IRQHandler, Default_Handler) // 42: ADC0 interrupt source 0
|
||||
WEAK_ALIAS_FUNC(EADC1_IRQHandler, Default_Handler) // 43: ADC0 interrupt source 1
|
||||
|
|
@ -177,7 +185,7 @@ WEAK_ALIAS_FUNC(DSRC_IRQHandler, Default_Handler) // 97:
|
|||
WEAK_ALIAS_FUNC(PDMA1_IRQHandler, Default_Handler) // 98:
|
||||
WEAK_ALIAS_FUNC(SCU_IRQHandler, Default_Handler) // 99:
|
||||
// 100: Reserved
|
||||
WEAK_ALIAS_FUNC(TRNG_IRQHandler, Default_Handler) // 101:
|
||||
WEAK_ALIAS_FUNC(TRNG_IRQHandler, Default_Handler) // 101:
|
||||
|
||||
|
||||
/* Vector table */
|
||||
|
|
@ -194,7 +202,12 @@ const uint32_t __vector_handlers[] = {
|
|||
|
||||
/* Configure Initial Stack Pointer, using linker-generated symbols */
|
||||
#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
|
||||
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) && (TFM_LVL > 0)
|
||||
(uint32_t) &Image$$ARM_LIB_STACK_MSP$$ZI$$Limit,
|
||||
#else
|
||||
(uint32_t) &Image$$ARM_LIB_STACK$$ZI$$Limit,
|
||||
#endif
|
||||
|
||||
#elif defined(__ICCARM__)
|
||||
//(uint32_t) __sfe("CSTACK"),
|
||||
(uint32_t) &CSTACK$$Limit,
|
||||
|
|
@ -323,12 +336,56 @@ const uint32_t __vector_handlers[] = {
|
|||
(uint32_t) TRNG_IRQHandler, // 101:
|
||||
};
|
||||
|
||||
/**
|
||||
* \brief This is the code that gets called on processor reset.
|
||||
*/
|
||||
void Reset_Handler(void)
|
||||
{
|
||||
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
|
||||
|
||||
/* Some reset handler code cannot implement in pure C. Implement it in inline/embedded assembly.
|
||||
*
|
||||
* Reset_Handler:
|
||||
* For non-secure PSA/non-secure non-PSA/secure non-PSA, do as usual
|
||||
* For secure PSA, switch from MSP to PSP, then jump to Reset_Handler_1 for usual work
|
||||
*
|
||||
* Reset_Handler_1
|
||||
* C/C++ runtime initialization
|
||||
*/
|
||||
|
||||
void Reset_Handler_1(void);
|
||||
|
||||
/* Add '__attribute__((naked))' here to make sure compiler does not generate prologue and
|
||||
* epilogue sequences for Reset_Handler. We don't want MSP is updated by compiler-generated
|
||||
* code during stack switch. */
|
||||
__attribute__((naked)) void Reset_Handler(void)
|
||||
{
|
||||
__asm(".syntax unified \n");
|
||||
__asm(".globl Reset_Handler_1 \n");
|
||||
|
||||
/* Secure TFM requires PSP as boot stack */
|
||||
#if TFM_LVL != 0
|
||||
__asm(".globl Image$$ARM_LIB_STACK$$ZI$$Limit \n");
|
||||
__asm("movw r0, #:lower16:Image$$ARM_LIB_STACK$$ZI$$Limit \n"); // Initialize PSP
|
||||
__asm("movt r0, #:upper16:Image$$ARM_LIB_STACK$$ZI$$Limit \n");
|
||||
__asm("msr psp, r0 \n");
|
||||
__asm("mrs r0, control \n"); // Switch SP to PSP
|
||||
__asm("movs r1, #2 \n");
|
||||
__asm("orrs r0, r1 \n");
|
||||
__asm("msr control, r0 \n");
|
||||
#endif
|
||||
|
||||
__asm("movw r0, #:lower16:Reset_Handler_1 \n");
|
||||
__asm("movt r0, #:upper16:Reset_Handler_1 \n");
|
||||
__asm("bx r0 \n");
|
||||
}
|
||||
|
||||
void Reset_Handler_1(void)
|
||||
|
||||
#else
|
||||
|
||||
void Reset_Handler(void)
|
||||
|
||||
#endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
|
||||
|
||||
|
||||
{
|
||||
#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
|
||||
/* Disable register write-protection function */
|
||||
SYS_UnlockReg();
|
||||
|
||||
|
|
@ -339,9 +396,7 @@ void Reset_Handler(void)
|
|||
SYS_LockReg();
|
||||
#endif
|
||||
|
||||
/**
|
||||
* SystemInit() must be called at the very start.
|
||||
*/
|
||||
/* SystemInit() must be called at the very start. */
|
||||
SystemInit();
|
||||
|
||||
#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
|
||||
|
|
@ -351,26 +406,51 @@ void Reset_Handler(void)
|
|||
__iar_program_start();
|
||||
|
||||
#elif defined(__GNUC__)
|
||||
uint32_t *src_ind = (uint32_t *) &__etext;
|
||||
uint32_t *dst_ind = (uint32_t *) &__data_start__;
|
||||
uint32_t *dst_end = (uint32_t *) &__data_end__;
|
||||
/* Move (multiple) .data section(s) from ROM to RAM */
|
||||
{
|
||||
/* Struct of copy table entry which must match linker script */
|
||||
typedef struct copy_table_entry_ {
|
||||
uint32_t src; // Address to copy from
|
||||
uint32_t dst; // Address to copy to
|
||||
uint32_t size; // Copy size in bytes
|
||||
} copy_table_entry;
|
||||
|
||||
/* Move .data section from ROM to RAM */
|
||||
if (src_ind != dst_ind) {
|
||||
for (; dst_ind < dst_end;) {
|
||||
*dst_ind ++ = *src_ind ++;
|
||||
copy_table_entry *copy_table_ind = (copy_table_entry *) &__copy_table_start__;
|
||||
copy_table_entry *copy_table_end = (copy_table_entry *) &__copy_table_end__;
|
||||
|
||||
for (; copy_table_ind != copy_table_end; copy_table_ind ++) {
|
||||
uint32_t *src_ind = (uint32_t *) copy_table_ind->src;
|
||||
uint32_t *src_end = (uint32_t *) (copy_table_ind->src + copy_table_ind->size);
|
||||
uint32_t *dst_ind = (uint32_t *) copy_table_ind->dst;
|
||||
if (src_ind != dst_ind) {
|
||||
for (; src_ind < src_end;) {
|
||||
*dst_ind ++ = *src_ind ++;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Initialize .bss section to zero */
|
||||
dst_ind = (uint32_t *) &__bss_start__;
|
||||
dst_end = (uint32_t *) &__bss_end__;
|
||||
if (dst_ind != dst_end) {
|
||||
for (; dst_ind < dst_end;) {
|
||||
*dst_ind ++ = 0;
|
||||
|
||||
/* Initialize (multiple) .bss sections to zero */
|
||||
{
|
||||
/* Struct of zero table entry which must match linker script */
|
||||
typedef struct zero_table_entry_ {
|
||||
uint32_t start; // Address to start zero'ing
|
||||
uint32_t size; // Zero size in bytes
|
||||
} zero_table_entry;
|
||||
|
||||
zero_table_entry *zero_table_ind = (zero_table_entry *) &__zero_table_start__;
|
||||
zero_table_entry *zero_table_end = (zero_table_entry *) &__zero_table_end__;
|
||||
|
||||
for (; zero_table_ind != zero_table_end; zero_table_ind ++) {
|
||||
uint32_t *dst_ind = (uint32_t *) zero_table_ind->start;
|
||||
uint32_t *dst_end = (uint32_t *) (zero_table_ind->start + zero_table_ind->size);
|
||||
|
||||
for (; dst_ind < dst_end; ) {
|
||||
*dst_ind ++ = 0;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
_start();
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -20,6 +20,9 @@
|
|||
#include "partition_M2351.h"
|
||||
#include "stddriver_secure.h"
|
||||
#include "mbed_error.h"
|
||||
#if defined(DOMAIN_NS) && (DOMAIN_NS == 1L) && (TFM_LVL > 0)
|
||||
#include "tfm_ns_lock.h"
|
||||
#endif
|
||||
|
||||
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
|
||||
|
||||
|
|
@ -133,11 +136,10 @@ static const nu_modidx_ns_t modidx_ns_tab[] = {
|
|||
*/
|
||||
static bool check_mod_ns(int modclass, uint32_t modidx);
|
||||
|
||||
__NONSECURE_ENTRY
|
||||
void SYS_ResetModule_S(uint32_t u32ModuleIndex)
|
||||
static void SYS_ResetModule_Impl(uint32_t u32ModuleIndex, bool nonsecure_caller)
|
||||
{
|
||||
/* Guard access to secure module from non-secure domain */
|
||||
if (cmse_nonsecure_caller() &&
|
||||
if (nonsecure_caller &&
|
||||
(! check_mod_ns(NU_MODCLASS_SYS, u32ModuleIndex))) {
|
||||
error("Non-secure domain tries to control secure or undefined module.");
|
||||
}
|
||||
|
|
@ -145,11 +147,10 @@ void SYS_ResetModule_S(uint32_t u32ModuleIndex)
|
|||
SYS_ResetModule(u32ModuleIndex);
|
||||
}
|
||||
|
||||
__NONSECURE_ENTRY
|
||||
void CLK_SetModuleClock_S(uint32_t u32ModuleIndex, uint32_t u32ClkSrc, uint32_t u32ClkDiv)
|
||||
static void CLK_SetModuleClock_Impl(uint32_t u32ModuleIndex, uint32_t u32ClkSrc, uint32_t u32ClkDiv, bool nonsecure_caller)
|
||||
{
|
||||
/* Guard access to secure module from non-secure domain */
|
||||
if (cmse_nonsecure_caller() &&
|
||||
if (nonsecure_caller &&
|
||||
(! check_mod_ns(NU_MODCLASS_CLK, u32ModuleIndex))) {
|
||||
error("Non-secure domain tries to control secure or undefined module.");
|
||||
}
|
||||
|
|
@ -157,11 +158,10 @@ void CLK_SetModuleClock_S(uint32_t u32ModuleIndex, uint32_t u32ClkSrc, uint32_t
|
|||
CLK_SetModuleClock(u32ModuleIndex, u32ClkSrc, u32ClkDiv);
|
||||
}
|
||||
|
||||
__NONSECURE_ENTRY
|
||||
void CLK_EnableModuleClock_S(uint32_t u32ModuleIndex)
|
||||
static void CLK_EnableModuleClock_Impl(uint32_t u32ModuleIndex, bool nonsecure_caller)
|
||||
{
|
||||
/* Guard access to secure module from non-secure domain */
|
||||
if (cmse_nonsecure_caller() &&
|
||||
if (nonsecure_caller &&
|
||||
(! check_mod_ns(NU_MODCLASS_CLK, u32ModuleIndex))) {
|
||||
error("Non-secure domain tries to control secure or undefined module.");
|
||||
}
|
||||
|
|
@ -169,11 +169,10 @@ void CLK_EnableModuleClock_S(uint32_t u32ModuleIndex)
|
|||
CLK_EnableModuleClock(u32ModuleIndex);
|
||||
}
|
||||
|
||||
__NONSECURE_ENTRY
|
||||
void CLK_DisableModuleClock_S(uint32_t u32ModuleIndex)
|
||||
static void CLK_DisableModuleClock_Impl(uint32_t u32ModuleIndex, bool nonsecure_caller)
|
||||
{
|
||||
/* Guard access to secure module from non-secure domain */
|
||||
if (cmse_nonsecure_caller() &&
|
||||
if (nonsecure_caller &&
|
||||
(! check_mod_ns(NU_MODCLASS_CLK, u32ModuleIndex))) {
|
||||
error("Non-secure domain tries to control secure or undefined module.");
|
||||
}
|
||||
|
|
@ -181,30 +180,26 @@ void CLK_DisableModuleClock_S(uint32_t u32ModuleIndex)
|
|||
CLK_DisableModuleClock(u32ModuleIndex);
|
||||
}
|
||||
|
||||
__NONSECURE_ENTRY
|
||||
void SYS_LockReg_S(void)
|
||||
static void SYS_LockReg_Impl(void)
|
||||
{
|
||||
/* Allow non-secure domain to lock/unlock locked registers without check.
|
||||
* Guard access to locked registers is done through other related secure functions. */
|
||||
SYS_LockReg();
|
||||
}
|
||||
|
||||
__NONSECURE_ENTRY
|
||||
void SYS_UnlockReg_S(void)
|
||||
static void SYS_UnlockReg_Impl(void)
|
||||
{
|
||||
/* Allow non-secure domain to lock/unlock locked registers without check.
|
||||
* Guard access to locked registers is done through other related secure functions. */
|
||||
SYS_UnlockReg();
|
||||
}
|
||||
|
||||
__NONSECURE_ENTRY
|
||||
void CLK_Idle_S(void)
|
||||
static void CLK_Idle_Impl(void)
|
||||
{
|
||||
CLK_Idle();
|
||||
}
|
||||
|
||||
__NONSECURE_ENTRY
|
||||
void CLK_PowerDown_S(void)
|
||||
static void CLK_PowerDown_Impl(void)
|
||||
{
|
||||
CLK_PowerDown();
|
||||
}
|
||||
|
|
@ -251,4 +246,227 @@ static bool check_mod_ns(int modclass, uint32_t modidx)
|
|||
return false;
|
||||
}
|
||||
|
||||
#if (TFM_LVL > 0)
|
||||
|
||||
__NONSECURE_ENTRY
|
||||
int32_t SYS_ResetModule_Veneer(uint32_t arg0, uint32_t arg1, uint32_t arg2, uint32_t arg3)
|
||||
{
|
||||
uint32_t u32ModuleIndex = (uint32_t) arg0;
|
||||
SYS_ResetModule_Impl(u32ModuleIndex, cmse_nonsecure_caller());
|
||||
return 0;
|
||||
}
|
||||
|
||||
__NONSECURE_ENTRY
|
||||
int32_t CLK_SetModuleClock_Veneer(uint32_t arg0, uint32_t arg1, uint32_t arg2, uint32_t arg3)
|
||||
{
|
||||
uint32_t u32ModuleIndex = (uint32_t) arg0;
|
||||
uint32_t u32ClkSrc = (uint32_t) arg1;
|
||||
uint32_t u32ClkDiv = (uint32_t) arg2;
|
||||
CLK_SetModuleClock_Impl(u32ModuleIndex, u32ClkSrc, u32ClkDiv, cmse_nonsecure_caller());
|
||||
return 0;
|
||||
}
|
||||
|
||||
__NONSECURE_ENTRY
|
||||
int32_t CLK_EnableModuleClock_Veneer(uint32_t arg0, uint32_t arg1, uint32_t arg2, uint32_t arg3)
|
||||
{
|
||||
uint32_t u32ModuleIndex = (uint32_t) arg0;
|
||||
CLK_EnableModuleClock_Impl(u32ModuleIndex, cmse_nonsecure_caller());
|
||||
return 0;
|
||||
}
|
||||
|
||||
__NONSECURE_ENTRY
|
||||
int32_t CLK_DisableModuleClock_Veneer(uint32_t arg0, uint32_t arg1, uint32_t arg2, uint32_t arg3)
|
||||
{
|
||||
uint32_t u32ModuleIndex = (uint32_t) arg0;
|
||||
CLK_DisableModuleClock_Impl(u32ModuleIndex, cmse_nonsecure_caller());
|
||||
return 0;
|
||||
}
|
||||
|
||||
__NONSECURE_ENTRY
|
||||
int32_t SYS_LockReg_Veneer(uint32_t arg0, uint32_t arg1, uint32_t arg2, uint32_t arg3)
|
||||
{
|
||||
SYS_LockReg_Impl();
|
||||
return 0;
|
||||
}
|
||||
|
||||
__NONSECURE_ENTRY
|
||||
int32_t SYS_UnlockReg_Veneer(uint32_t arg0, uint32_t arg1, uint32_t arg2, uint32_t arg3)
|
||||
{
|
||||
SYS_UnlockReg_Impl();
|
||||
return 0;
|
||||
}
|
||||
|
||||
__NONSECURE_ENTRY
|
||||
int32_t CLK_Idle_Veneer(uint32_t arg0, uint32_t arg1, uint32_t arg2, uint32_t arg3)
|
||||
{
|
||||
CLK_Idle_Impl();
|
||||
return 0;
|
||||
}
|
||||
|
||||
__NONSECURE_ENTRY
|
||||
int32_t CLK_PowerDown_Veneer(uint32_t arg0, uint32_t arg1, uint32_t arg2, uint32_t arg3)
|
||||
{
|
||||
CLK_PowerDown_Impl();
|
||||
return 0;
|
||||
}
|
||||
|
||||
__NONSECURE_ENTRY
|
||||
int32_t nu_idle_veneer(uint32_t arg0, uint32_t arg1, uint32_t arg2, uint32_t arg3)
|
||||
{
|
||||
SYS_UnlockReg_Impl();
|
||||
CLK_Idle_Impl();
|
||||
SYS_LockReg_Impl();
|
||||
return 0;
|
||||
}
|
||||
|
||||
__NONSECURE_ENTRY
|
||||
int32_t nu_powerdown_veneer(uint32_t arg0, uint32_t arg1, uint32_t arg2, uint32_t arg3)
|
||||
{
|
||||
SYS_UnlockReg_Impl();
|
||||
CLK_PowerDown_Impl();
|
||||
SYS_LockReg_Impl();
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if defined(DOMAIN_NS) && (DOMAIN_NS == 1) && (TFM_LVL > 0)
|
||||
|
||||
void SYS_ResetModule_S(uint32_t u32ModuleIndex)
|
||||
{
|
||||
tfm_ns_lock_dispatch(SYS_ResetModule_Veneer, u32ModuleIndex, 0, 0, 0);
|
||||
}
|
||||
|
||||
void CLK_SetModuleClock_S(uint32_t u32ModuleIndex, uint32_t u32ClkSrc, uint32_t u32ClkDiv)
|
||||
{
|
||||
tfm_ns_lock_dispatch(CLK_SetModuleClock_Veneer, u32ModuleIndex, u32ClkSrc, u32ClkDiv, 0);
|
||||
}
|
||||
|
||||
void CLK_EnableModuleClock_S(uint32_t u32ModuleIndex)
|
||||
{
|
||||
tfm_ns_lock_dispatch(CLK_EnableModuleClock_Veneer, u32ModuleIndex, 0, 0, 0);
|
||||
}
|
||||
|
||||
void CLK_DisableModuleClock_S(uint32_t u32ModuleIndex)
|
||||
{
|
||||
tfm_ns_lock_dispatch(CLK_DisableModuleClock_Veneer, u32ModuleIndex, 0, 0, 0);
|
||||
}
|
||||
|
||||
void SYS_LockReg_S(void)
|
||||
{
|
||||
tfm_ns_lock_dispatch(SYS_LockReg_Veneer, 0, 0, 0, 0);
|
||||
}
|
||||
|
||||
void SYS_UnlockReg_S(void)
|
||||
{
|
||||
tfm_ns_lock_dispatch(SYS_UnlockReg_Veneer, 0, 0, 0, 0);
|
||||
}
|
||||
|
||||
void CLK_Idle_S(void)
|
||||
{
|
||||
tfm_ns_lock_dispatch(CLK_Idle_Veneer, 0, 0, 0, 0);
|
||||
}
|
||||
|
||||
void CLK_PowerDown_S(void)
|
||||
{
|
||||
tfm_ns_lock_dispatch(CLK_PowerDown_Veneer, 0, 0, 0, 0);
|
||||
}
|
||||
|
||||
void nu_idle_s(void)
|
||||
{
|
||||
tfm_ns_lock_dispatch(nu_idle_veneer, 0, 0, 0, 0);
|
||||
}
|
||||
|
||||
void nu_powerdown_s(void)
|
||||
{
|
||||
tfm_ns_lock_dispatch(nu_powerdown_veneer, 0, 0, 0, 0);
|
||||
}
|
||||
|
||||
#elif defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
|
||||
|
||||
#if (TFM_LVL == 0)
|
||||
__NONSECURE_ENTRY
|
||||
#endif
|
||||
void SYS_ResetModule_S(uint32_t u32ModuleIndex)
|
||||
{
|
||||
SYS_ResetModule_Impl(u32ModuleIndex, cmse_nonsecure_caller());
|
||||
}
|
||||
|
||||
#if (TFM_LVL == 0)
|
||||
__NONSECURE_ENTRY
|
||||
#endif
|
||||
void CLK_SetModuleClock_S(uint32_t u32ModuleIndex, uint32_t u32ClkSrc, uint32_t u32ClkDiv)
|
||||
{
|
||||
CLK_SetModuleClock_Impl(u32ModuleIndex, u32ClkSrc, u32ClkDiv, cmse_nonsecure_caller());
|
||||
}
|
||||
|
||||
#if (TFM_LVL == 0)
|
||||
__NONSECURE_ENTRY
|
||||
#endif
|
||||
void CLK_EnableModuleClock_S(uint32_t u32ModuleIndex)
|
||||
{
|
||||
CLK_EnableModuleClock_Impl(u32ModuleIndex, cmse_nonsecure_caller());
|
||||
}
|
||||
|
||||
#if (TFM_LVL == 0)
|
||||
__NONSECURE_ENTRY
|
||||
#endif
|
||||
void CLK_DisableModuleClock_S(uint32_t u32ModuleIndex)
|
||||
{
|
||||
CLK_DisableModuleClock_Impl(u32ModuleIndex, cmse_nonsecure_caller());
|
||||
}
|
||||
|
||||
#if (TFM_LVL == 0)
|
||||
__NONSECURE_ENTRY
|
||||
#endif
|
||||
void SYS_LockReg_S(void)
|
||||
{
|
||||
SYS_LockReg_Impl();
|
||||
}
|
||||
|
||||
#if (TFM_LVL == 0)
|
||||
__NONSECURE_ENTRY
|
||||
#endif
|
||||
void SYS_UnlockReg_S(void)
|
||||
{
|
||||
SYS_UnlockReg_Impl();
|
||||
}
|
||||
|
||||
#if (TFM_LVL == 0)
|
||||
__NONSECURE_ENTRY
|
||||
#endif
|
||||
void CLK_Idle_S(void)
|
||||
{
|
||||
CLK_Idle_Impl();
|
||||
}
|
||||
|
||||
#if (TFM_LVL == 0)
|
||||
__NONSECURE_ENTRY
|
||||
#endif
|
||||
void CLK_PowerDown_S(void)
|
||||
{
|
||||
CLK_PowerDown_Impl();
|
||||
}
|
||||
|
||||
#if (TFM_LVL == 0)
|
||||
__NONSECURE_ENTRY
|
||||
#endif
|
||||
void nu_idle_s(void)
|
||||
{
|
||||
SYS_UnlockReg_Impl();
|
||||
CLK_Idle_Impl();
|
||||
SYS_LockReg_Impl();
|
||||
}
|
||||
|
||||
#if (TFM_LVL == 0)
|
||||
__NONSECURE_ENTRY
|
||||
#endif
|
||||
void nu_powerdown_s(void)
|
||||
{
|
||||
SYS_UnlockReg_Impl();
|
||||
CLK_PowerDown_Impl();
|
||||
SYS_LockReg_Impl();
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -28,56 +28,124 @@ extern "C" {
|
|||
* Guard access to secure module from non-secure domain before SYS_ResetModule.
|
||||
* Its synopsis is the same as SYS_ResetModule.
|
||||
*/
|
||||
#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) && (TFM_LVL == 0)
|
||||
__NONSECURE_ENTRY
|
||||
#endif
|
||||
void SYS_ResetModule_S(uint32_t u32ModuleIndex);
|
||||
#if (TFM_LVL > 0)
|
||||
__NONSECURE_ENTRY
|
||||
int32_t SYS_ResetModule_Veneer(uint32_t arg0, uint32_t arg1, uint32_t arg2, uint32_t arg3);
|
||||
#endif
|
||||
|
||||
/* Secure CLK_SetModuleClock
|
||||
*
|
||||
* Guard access to secure module from non-secure domain before CLK_SetModuleClock.
|
||||
* Its synopsis is the same as CLK_SetModuleClock.
|
||||
*/
|
||||
#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) && (TFM_LVL == 0)
|
||||
__NONSECURE_ENTRY
|
||||
#endif
|
||||
void CLK_SetModuleClock_S(uint32_t u32ModuleIndex, uint32_t u32ClkSrc, uint32_t u32ClkDiv);
|
||||
#if (TFM_LVL > 0)
|
||||
__NONSECURE_ENTRY
|
||||
int32_t CLK_SetModuleClock_Veneer(uint32_t arg0, uint32_t arg1, uint32_t arg2, uint32_t arg3);
|
||||
#endif
|
||||
|
||||
/* Secure CLK_EnableModuleClock
|
||||
*
|
||||
* Guard access to secure module from non-secure domain before CLK_EnableModuleClock.
|
||||
* Its synopsis is the same as CLK_EnableModuleClock.
|
||||
*/
|
||||
#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) && (TFM_LVL == 0)
|
||||
__NONSECURE_ENTRY
|
||||
#endif
|
||||
void CLK_EnableModuleClock_S(uint32_t u32ModuleIndex);
|
||||
#if (TFM_LVL > 0)
|
||||
__NONSECURE_ENTRY
|
||||
int32_t CLK_EnableModuleClock_Veneer(uint32_t arg0, uint32_t arg1, uint32_t arg2, uint32_t arg3);
|
||||
#endif
|
||||
|
||||
/* Secure CLK_DisableModuleClock
|
||||
*
|
||||
* Guard access to secure module from non-secure domain before CLK_DisableModuleClock.
|
||||
* Its synopsis is the same as CLK_DisableModuleClock.
|
||||
*/
|
||||
#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) && (TFM_LVL == 0)
|
||||
__NONSECURE_ENTRY
|
||||
#endif
|
||||
void CLK_DisableModuleClock_S(uint32_t u32ModuleIndex);
|
||||
#if (TFM_LVL > 0)
|
||||
__NONSECURE_ENTRY
|
||||
int32_t CLK_DisableModuleClock_Veneer(uint32_t arg0, uint32_t arg1, uint32_t arg2, uint32_t arg3);
|
||||
#endif
|
||||
|
||||
/* Secure SYS_LockReg
|
||||
*
|
||||
* Guard access to secure module from non-secure domain before SYS_LockReg.
|
||||
* Its synopsis is the same as SYS_LockReg.
|
||||
*/
|
||||
#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) && (TFM_LVL == 0)
|
||||
__NONSECURE_ENTRY
|
||||
#endif
|
||||
void SYS_LockReg_S(void);
|
||||
#if (TFM_LVL > 0)
|
||||
__NONSECURE_ENTRY
|
||||
int32_t SYS_LockReg_Veneer(uint32_t arg0, uint32_t arg1, uint32_t arg2, uint32_t arg3);
|
||||
#endif
|
||||
|
||||
/* Secure SYS_UnlockReg
|
||||
*
|
||||
* Guard access to secure module from non-secure domain before SYS_UnlockReg.
|
||||
* Its synopsis is the same as SYS_UnlockReg.
|
||||
*/
|
||||
#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) && (TFM_LVL == 0)
|
||||
__NONSECURE_ENTRY
|
||||
#endif
|
||||
void SYS_UnlockReg_S(void);
|
||||
|
||||
/* Secure CLK_Idle */
|
||||
#if (TFM_LVL > 0)
|
||||
__NONSECURE_ENTRY
|
||||
int32_t SYS_UnlockReg_Veneer(uint32_t arg0, uint32_t arg1, uint32_t arg2, uint32_t arg3);
|
||||
#endif
|
||||
|
||||
/* Secure CLK_Idle */
|
||||
#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) && (TFM_LVL == 0)
|
||||
__NONSECURE_ENTRY
|
||||
#endif
|
||||
void CLK_Idle_S(void);
|
||||
|
||||
/* Secure CLK_PowerDown */
|
||||
#if (TFM_LVL > 0)
|
||||
__NONSECURE_ENTRY
|
||||
int32_t CLK_Idle_Veneer(uint32_t arg0, uint32_t arg1, uint32_t arg2, uint32_t arg3);
|
||||
#endif
|
||||
|
||||
/* Secure CLK_PowerDown */
|
||||
#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) && (TFM_LVL == 0)
|
||||
__NONSECURE_ENTRY
|
||||
#endif
|
||||
void CLK_PowerDown_S(void);
|
||||
#if (TFM_LVL > 0)
|
||||
__NONSECURE_ENTRY
|
||||
int32_t CLK_PowerDown_Veneer(uint32_t arg0, uint32_t arg1, uint32_t arg2, uint32_t arg3);
|
||||
#endif
|
||||
|
||||
/* Secure SYS_UnlockReg > CLK_Idle > SYS_LockReg */
|
||||
#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) && (TFM_LVL == 0)
|
||||
__NONSECURE_ENTRY
|
||||
#endif
|
||||
void nu_idle_s(void);
|
||||
#if (TFM_LVL > 0)
|
||||
__NONSECURE_ENTRY
|
||||
int32_t nu_idle_veneer(uint32_t arg0, uint32_t arg1, uint32_t arg2, uint32_t arg3);
|
||||
#endif
|
||||
|
||||
/* Secure SYS_UnlockReg > CLK_PowerDown > SYS_LockReg */
|
||||
#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) && (TFM_LVL == 0)
|
||||
__NONSECURE_ENTRY
|
||||
#endif
|
||||
void nu_powerdown_s(void);
|
||||
#if (TFM_LVL > 0)
|
||||
__NONSECURE_ENTRY
|
||||
int32_t nu_powerdown_veneer(uint32_t arg0, uint32_t arg1, uint32_t arg2, uint32_t arg3);
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
|
|
|
|||
|
|
@ -80,10 +80,14 @@ void SystemInit(void)
|
|||
#endif
|
||||
|
||||
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
|
||||
#if TFM_LVL == 0
|
||||
TZ_SAU_Setup();
|
||||
SCB_Setup();
|
||||
TZ_NVIC_Setup();
|
||||
SCU_Setup();
|
||||
FMC_NSBA_Setup();
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef INIT_SYSCLK_AT_BOOTING
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,32 @@
|
|||
/*
|
||||
* Copyright (c) 2018-2019, Nuvoton Technology Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef __SYSTEM_CORE_M2351_H__
|
||||
#define __SYSTEM_CORE_M2351_H__
|
||||
|
||||
/* -------- Configuration of the Cortex-ARMv8MBL Processor and Core Peripherals ------- */
|
||||
#define __ARMv8MBL_REV 0x0000U /* Core revision r0p0 */
|
||||
#define __SAU_PRESENT 1U /* SAU present */
|
||||
#define __SAUREGION_PRESENT 1U /* SAU present */
|
||||
#define __MPU_PRESENT 1U /* MPU present */
|
||||
#define __VTOR_PRESENT 1U /* VTOR present */
|
||||
#define __NVIC_PRIO_BITS 2U /* Number of Bits used for Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */
|
||||
#define USE_ASSERT 0U /* Define to use Assert function or not */
|
||||
|
||||
#endif /* __SYSTEM_CORE_M2351_H__ */
|
||||
|
|
@ -87,7 +87,7 @@ static const flash_algo_t flash_algo_config = {
|
|||
|
||||
/* Secure flash */
|
||||
static const sector_info_t sectors_info[] = {
|
||||
{NU_ROM_START_S, 0x800}, // (start, sector size)
|
||||
{NU_FLASHIAP_SECURE_START, 0x800}, // (start, sector size)
|
||||
};
|
||||
|
||||
/* Secure flash */
|
||||
|
|
@ -95,15 +95,15 @@ static const flash_target_config_t flash_target_config = {
|
|||
.page_size = 4, // 4 bytes
|
||||
// Here page_size is program unit, which is different
|
||||
// than FMC definition.
|
||||
.flash_start = NU_ROM_START_S,
|
||||
.flash_size = NU_ROM_SIZE_S,
|
||||
.flash_start = NU_FLASHIAP_SECURE_START,
|
||||
.flash_size = NU_FLASHIAP_SECURE_SIZE,
|
||||
.sectors = sectors_info,
|
||||
.sector_info_count = sizeof(sectors_info) / sizeof(sector_info_t)
|
||||
};
|
||||
|
||||
/* Non-secure flash */
|
||||
static const sector_info_t sectors_info_ns[] = {
|
||||
{NU_ROM_START_NS, 0x800}, // (start, sector size)
|
||||
{NU_FLASHIAP_NONSECURE_START, 0x800}, // (start, sector size)
|
||||
};
|
||||
|
||||
/* Non-secure flash */
|
||||
|
|
@ -111,8 +111,8 @@ static const flash_target_config_t flash_target_config_ns = {
|
|||
.page_size = 4, // 4 bytes
|
||||
// Here page_size is program unit, which is different
|
||||
// than FMC definition.
|
||||
.flash_start = NU_ROM_START_NS,
|
||||
.flash_size = NU_ROM_SIZE_NS,
|
||||
.flash_start = NU_FLASHIAP_NONSECURE_START,
|
||||
.flash_size = NU_FLASHIAP_NONSECURE_SIZE,
|
||||
.sectors = sectors_info_ns,
|
||||
.sector_info_count = sizeof(sectors_info_ns) / sizeof(sector_info_t)
|
||||
};
|
||||
|
|
|
|||
|
|
@ -30,8 +30,14 @@ extern "C" {
|
|||
* Its synopsis is the same as normal version except change of return/argument type for
|
||||
* binary-compatible across compilers.
|
||||
*/
|
||||
#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) && (TFM_LVL == 0)
|
||||
__NONSECURE_ENTRY
|
||||
#endif
|
||||
void pin_function_s(int32_t pin, int32_t data);
|
||||
#if (TFM_LVL > 0)
|
||||
__NONSECURE_ENTRY
|
||||
int32_t pin_function_veneer(uint32_t arg0, uint32_t arg1, uint32_t arg2, uint32_t arg3);
|
||||
#endif
|
||||
|
||||
/* NOTE: time_t
|
||||
*
|
||||
|
|
@ -41,60 +47,109 @@ void pin_function_s(int32_t pin, int32_t data);
|
|||
*/
|
||||
|
||||
/* rtc_init (secure version) */
|
||||
#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) && (TFM_LVL == 0)
|
||||
__NONSECURE_ENTRY
|
||||
#endif
|
||||
void rtc_init_s(void);
|
||||
#if (TFM_LVL > 0)
|
||||
__NONSECURE_ENTRY
|
||||
int32_t rtc_init_veneer(uint32_t arg0, uint32_t arg1, uint32_t arg2, uint32_t arg3);
|
||||
#endif
|
||||
|
||||
|
||||
/* rtc_free (secure version) */
|
||||
#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) && (TFM_LVL == 0)
|
||||
__NONSECURE_ENTRY
|
||||
#endif
|
||||
void rtc_free_s(void);
|
||||
#if (TFM_LVL > 0)
|
||||
__NONSECURE_ENTRY
|
||||
int32_t rtc_free_veneer(uint32_t arg0, uint32_t arg1, uint32_t arg2, uint32_t arg3);
|
||||
#endif
|
||||
|
||||
/* rtc_isenabled (secure version)
|
||||
*
|
||||
* Its synopsis is the same as normal version except change of return/argument type for
|
||||
* binary-compatible across compilers.
|
||||
*/
|
||||
#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) && (TFM_LVL == 0)
|
||||
__NONSECURE_ENTRY
|
||||
#endif
|
||||
int32_t rtc_isenabled_s(void);
|
||||
#if (TFM_LVL > 0)
|
||||
__NONSECURE_ENTRY
|
||||
int32_t rtc_isenabled_veneer(uint32_t arg0, uint32_t arg1, uint32_t arg2, uint32_t arg3);
|
||||
#endif
|
||||
|
||||
/* rtc_read (secure version)
|
||||
*
|
||||
* Its synopsis is the same as normal version except change of return/argument type for
|
||||
* binary-compatible across compilers.
|
||||
*/
|
||||
#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) && (TFM_LVL == 0)
|
||||
__NONSECURE_ENTRY
|
||||
#endif
|
||||
int64_t rtc_read_s(void);
|
||||
#if (TFM_LVL > 0)
|
||||
__NONSECURE_ENTRY
|
||||
int32_t rtc_read_veneer(uint32_t arg0, uint32_t arg1, uint32_t arg2, uint32_t arg3);
|
||||
#endif
|
||||
|
||||
/* rtc_write (secure version)
|
||||
*
|
||||
* Its synopsis is the same as normal version except change of return/argument type for
|
||||
* binary-compatible across compilers.
|
||||
*/
|
||||
#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) && (TFM_LVL == 0)
|
||||
__NONSECURE_ENTRY
|
||||
#endif
|
||||
void rtc_write_s(int64_t t);
|
||||
#if (TFM_LVL > 0)
|
||||
__NONSECURE_ENTRY
|
||||
int32_t rtc_write_veneer(uint32_t arg0, uint32_t arg1, uint32_t arg2, uint32_t arg3);
|
||||
#endif
|
||||
|
||||
/* trng_init (secure version)
|
||||
*
|
||||
* Its synopsis is the same as normal version except change of return/argument type for
|
||||
* binary-compatible across compilers.
|
||||
*/
|
||||
#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) && (TFM_LVL == 0)
|
||||
__NONSECURE_ENTRY
|
||||
#endif
|
||||
void trng_init_s(void *obj);
|
||||
#if (TFM_LVL > 0)
|
||||
__NONSECURE_ENTRY
|
||||
int32_t trng_init_veneer(uint32_t arg0, uint32_t arg1, uint32_t arg2, uint32_t arg3);
|
||||
#endif
|
||||
|
||||
/* trng_free (secure version)
|
||||
*
|
||||
* Its synopsis is the same as normal version except change of return/argument type for
|
||||
* binary-compatible across compilers.
|
||||
*/
|
||||
#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) && (TFM_LVL == 0)
|
||||
__NONSECURE_ENTRY
|
||||
#endif
|
||||
void trng_free_s(void *obj);
|
||||
#if (TFM_LVL > 0)
|
||||
__NONSECURE_ENTRY
|
||||
int32_t trng_free_veneer(uint32_t arg0, uint32_t arg1, uint32_t arg2, uint32_t arg3);
|
||||
#endif
|
||||
|
||||
/* trng_get_bytes (secure version)
|
||||
*
|
||||
* Its synopsis is the same as normal version except change of return/argument type for
|
||||
* binary-compatible across compilers.
|
||||
*/
|
||||
#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) && (TFM_LVL == 0)
|
||||
__NONSECURE_ENTRY
|
||||
#endif
|
||||
int32_t trng_get_bytes_s(void *obj, uint8_t *output, uint32_t length, uint32_t *output_length);
|
||||
#if (TFM_LVL > 0)
|
||||
__NONSECURE_ENTRY
|
||||
int32_t trng_get_bytes_veneer(uint32_t arg0, uint32_t arg1, uint32_t arg2, uint32_t arg3);
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
|
|
|
|||
|
|
@ -22,6 +22,9 @@
|
|||
#include "mbed_error.h"
|
||||
#include "partition_M2351.h"
|
||||
#include "hal_secure.h"
|
||||
#if defined(DOMAIN_NS) && (DOMAIN_NS == 1L) && (TFM_LVL > 0)
|
||||
#include "tfm_ns_lock.h"
|
||||
#endif
|
||||
|
||||
/**
|
||||
* Configure pin multi-function
|
||||
|
|
@ -93,16 +96,16 @@ const PeripheralList *pinmap_restricted_peripherals()
|
|||
return &peripheral_list;
|
||||
}
|
||||
|
||||
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
|
||||
__NONSECURE_ENTRY
|
||||
void pin_function_s(int32_t pin, int32_t data)
|
||||
#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
|
||||
|
||||
static void pin_function_impl(int32_t pin, int32_t data, bool nonsecure_caller)
|
||||
{
|
||||
MBED_ASSERT(pin != (PinName)NC);
|
||||
uint32_t pin_index = NU_PINNAME_TO_PIN(pin);
|
||||
uint32_t port_index = NU_PINNAME_TO_PORT(pin);
|
||||
|
||||
/* Guard access to secure GPIO from non-secure domain */
|
||||
if (cmse_nonsecure_caller() &&
|
||||
if (nonsecure_caller &&
|
||||
(! (SCU_INIT_IONSSET_VAL & (1 << (port_index + 0))))) {
|
||||
error("Non-secure domain tries to control secure or undefined GPIO.");
|
||||
}
|
||||
|
|
@ -113,4 +116,35 @@ void pin_function_s(int32_t pin, int32_t data)
|
|||
// E.g.: SYS->GPA_MFPL = (SYS->GPA_MFPL & (~SYS_GPA_MFPL_PA0MFP_Msk) ) | SYS_GPA_MFPL_PA0MFP_SC0_CD ;
|
||||
*GPx_MFPx = (*GPx_MFPx & (~MFP_Msk)) | data;
|
||||
}
|
||||
|
||||
#if (TFM_LVL > 0)
|
||||
__NONSECURE_ENTRY
|
||||
int32_t pin_function_veneer(uint32_t arg0, uint32_t arg1, uint32_t arg2, uint32_t arg3)
|
||||
{
|
||||
int32_t pin = (int32_t) arg0;
|
||||
int32_t data = (int32_t) arg1;
|
||||
pin_function_impl(pin, data, cmse_nonsecure_caller());
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
#if defined(DOMAIN_NS) && (DOMAIN_NS == 1) && (TFM_LVL > 0)
|
||||
|
||||
void pin_function_s(int32_t pin, int32_t data)
|
||||
{
|
||||
tfm_ns_lock_dispatch(pin_function_veneer, pin, data, 0, 0);
|
||||
}
|
||||
|
||||
#elif defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
|
||||
|
||||
#if (TFM_LVL == 0)
|
||||
__NONSECURE_ENTRY
|
||||
#endif
|
||||
void pin_function_s(int32_t pin, int32_t data)
|
||||
{
|
||||
pin_function_impl(pin, data, cmse_nonsecure_caller());
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -25,6 +25,9 @@
|
|||
#include "mbed_mktime.h"
|
||||
#include "partition_M2351.h"
|
||||
#include "hal_secure.h"
|
||||
#if defined(DOMAIN_NS) && (DOMAIN_NS == 1L) && (TFM_LVL > 0)
|
||||
#include "tfm_ns_lock.h"
|
||||
#endif
|
||||
|
||||
/* NOTE: BSP RTC driver judges secure/non-secure RTC by PC. This implementation cannot support non-secure RTC
|
||||
* controlled by secure executable. A better way would be that secure/non-secure RTC base is passed
|
||||
|
|
@ -123,27 +126,30 @@ static void rtc_convert_datetime_hwrtc_to_tm(struct tm *datetime_tm, const S_RTC
|
|||
|
||||
static const struct nu_modinit_s rtc_modinit = {RTC_0, RTC_MODULE, 0, 0, 0, RTC_IRQn, NULL};
|
||||
|
||||
__NONSECURE_ENTRY
|
||||
void rtc_init_s(void)
|
||||
static void rtc_init_impl(void);
|
||||
static void rtc_free_impl(void);
|
||||
static int32_t rtc_isenabled_impl(void);
|
||||
static int64_t rtc_read_impl(void);
|
||||
static void rtc_write_impl(int64_t t);
|
||||
|
||||
static void rtc_init_impl(void)
|
||||
{
|
||||
if (rtc_isenabled()) {
|
||||
if (rtc_isenabled_impl()) {
|
||||
return;
|
||||
}
|
||||
|
||||
RTC_Open(NULL);
|
||||
|
||||
/* POSIX time origin (00:00:00 UTC, Thursday, 1 January 1970) */
|
||||
rtc_write(0);
|
||||
rtc_write_impl(0);
|
||||
}
|
||||
|
||||
__NONSECURE_ENTRY
|
||||
void rtc_free_s(void)
|
||||
static void rtc_free_impl(void)
|
||||
{
|
||||
CLK_DisableModuleClock_S(rtc_modinit.clkidx);
|
||||
}
|
||||
|
||||
__NONSECURE_ENTRY
|
||||
int32_t rtc_isenabled_s(void)
|
||||
static int32_t rtc_isenabled_impl(void)
|
||||
{
|
||||
// NOTE: To access (RTC) registers, clock must be enabled first.
|
||||
if (! (CLK->APBCLK0 & CLK_APBCLK0_RTCCKEN_Msk)) {
|
||||
|
|
@ -157,16 +163,15 @@ int32_t rtc_isenabled_s(void)
|
|||
return !! (rtc_base->INIT & RTC_INIT_ACTIVE_Msk);
|
||||
}
|
||||
|
||||
__NONSECURE_ENTRY
|
||||
int64_t rtc_read_s(void)
|
||||
static int64_t rtc_read_impl(void)
|
||||
{
|
||||
/* NOTE: After boot, RTC time registers are not synced immediately, about 1 sec latency.
|
||||
* RTC time got (through RTC_GetDateAndTime()) in this sec would be last-synced and incorrect.
|
||||
* NUC472/M453: Known issue
|
||||
* M487: Fixed
|
||||
*/
|
||||
if (! rtc_isenabled()) {
|
||||
rtc_init();
|
||||
if (! rtc_isenabled_impl()) {
|
||||
rtc_init_impl();
|
||||
}
|
||||
|
||||
/* Used for intermediary between date time of H/W RTC and POSIX time */
|
||||
|
|
@ -206,11 +211,10 @@ int64_t rtc_read_s(void)
|
|||
return t_present;
|
||||
}
|
||||
|
||||
__NONSECURE_ENTRY
|
||||
void rtc_write_s(int64_t t)
|
||||
static void rtc_write_impl(int64_t t)
|
||||
{
|
||||
if (! rtc_isenabled()) {
|
||||
rtc_init();
|
||||
if (! rtc_isenabled_impl()) {
|
||||
rtc_init_impl();
|
||||
}
|
||||
|
||||
t_write = t;
|
||||
|
|
@ -254,5 +258,124 @@ static void rtc_convert_datetime_hwrtc_to_tm(struct tm *datetime_tm, const S_RTC
|
|||
datetime_tm->tm_sec = datetime_hwrtc->u32Second;
|
||||
}
|
||||
|
||||
|
||||
#if (TFM_LVL > 0)
|
||||
|
||||
__NONSECURE_ENTRY
|
||||
int32_t rtc_init_veneer(uint32_t arg0, uint32_t arg1, uint32_t arg2, uint32_t arg3)
|
||||
{
|
||||
rtc_init_impl();
|
||||
return 0;
|
||||
}
|
||||
|
||||
__NONSECURE_ENTRY
|
||||
int32_t rtc_free_veneer(uint32_t arg0, uint32_t arg1, uint32_t arg2, uint32_t arg3)
|
||||
{
|
||||
rtc_free_impl();
|
||||
return 0;
|
||||
}
|
||||
|
||||
__NONSECURE_ENTRY
|
||||
int32_t rtc_isenabled_veneer(uint32_t arg0, uint32_t arg1, uint32_t arg2, uint32_t arg3)
|
||||
{
|
||||
int32_t *enabled = (int32_t *) arg0;
|
||||
*enabled = rtc_isenabled_impl();
|
||||
return 0;
|
||||
}
|
||||
|
||||
__NONSECURE_ENTRY
|
||||
int32_t rtc_read_veneer(uint32_t arg0, uint32_t arg1, uint32_t arg2, uint32_t arg3)
|
||||
{
|
||||
int64_t *t = (int64_t *) arg0;
|
||||
*t = rtc_read_impl();
|
||||
return 0;
|
||||
}
|
||||
|
||||
__NONSECURE_ENTRY
|
||||
int32_t rtc_write_veneer(uint32_t arg0, uint32_t arg1, uint32_t arg2, uint32_t arg3)
|
||||
{
|
||||
int64_t *t = (int64_t *) arg0;
|
||||
rtc_write_impl(*t);
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
#if defined(DOMAIN_NS) && (DOMAIN_NS == 1) && (TFM_LVL > 0)
|
||||
|
||||
void rtc_init_s(void)
|
||||
{
|
||||
tfm_ns_lock_dispatch(rtc_init_veneer, 0, 0, 0, 0);
|
||||
}
|
||||
|
||||
void rtc_free_s(void)
|
||||
{
|
||||
tfm_ns_lock_dispatch(rtc_free_veneer, 0, 0, 0, 0);
|
||||
}
|
||||
|
||||
int32_t rtc_isenabled_s(void)
|
||||
{
|
||||
int32_t enabled = 0;
|
||||
tfm_ns_lock_dispatch(rtc_isenabled_veneer, &enabled, 0, 0, 0);
|
||||
return enabled;
|
||||
}
|
||||
|
||||
int64_t rtc_read_s(void)
|
||||
{
|
||||
int64_t t = 0;
|
||||
tfm_ns_lock_dispatch(rtc_read_veneer, &t, 0, 0, 0);
|
||||
return t;
|
||||
}
|
||||
|
||||
void rtc_write_s(int64_t t)
|
||||
{
|
||||
tfm_ns_lock_dispatch(rtc_write_veneer, &t, 0, 0, 0);
|
||||
}
|
||||
|
||||
#elif defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
|
||||
|
||||
#if (TFM_LVL == 0)
|
||||
__NONSECURE_ENTRY
|
||||
#endif
|
||||
void rtc_init_s(void)
|
||||
{
|
||||
rtc_init_impl();
|
||||
}
|
||||
|
||||
#if (TFM_LVL == 0)
|
||||
__NONSECURE_ENTRY
|
||||
#endif
|
||||
void rtc_free_s(void)
|
||||
{
|
||||
rtc_free_impl();
|
||||
}
|
||||
|
||||
#if (TFM_LVL == 0)
|
||||
__NONSECURE_ENTRY
|
||||
#endif
|
||||
int32_t rtc_isenabled_s(void)
|
||||
{
|
||||
return rtc_isenabled_impl();
|
||||
}
|
||||
|
||||
#if (TFM_LVL == 0)
|
||||
__NONSECURE_ENTRY
|
||||
#endif
|
||||
int64_t rtc_read_s(void)
|
||||
{
|
||||
return rtc_read_impl();
|
||||
}
|
||||
|
||||
#if (TFM_LVL == 0)
|
||||
__NONSECURE_ENTRY
|
||||
#endif
|
||||
void rtc_write_s(int64_t t)
|
||||
{
|
||||
rtc_write_impl(t);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -22,8 +22,18 @@
|
|||
#include "device.h"
|
||||
#include "objects.h"
|
||||
#include "PeripheralPins.h"
|
||||
#include "platform/mbed_toolchain.h"
|
||||
#include <stdbool.h>
|
||||
|
||||
/* Merge SYS_UnlockReg_S()/CLK_Idle_S() or CLK_PowerDown_S()/SYS_LockReg_S()
|
||||
* into nu_idle_s() or nu_powerdown_s()
|
||||
*
|
||||
* These APIs are secure calls. For performance, merge them into one when
|
||||
* nu_idle_s() and nu_powerdown_s() are available.
|
||||
*/
|
||||
MBED_WEAK void nu_idle_s(void);
|
||||
MBED_WEAK void nu_powerdown_s(void);
|
||||
|
||||
#if DEVICE_SERIAL
|
||||
bool serial_can_deep_sleep(void);
|
||||
#endif
|
||||
|
|
@ -38,9 +48,13 @@ void hal_sleep(void)
|
|||
CLK_Idle();
|
||||
SYS_LockReg();
|
||||
#else
|
||||
SYS_UnlockReg_S();
|
||||
CLK_Idle_S();
|
||||
SYS_LockReg_S();
|
||||
if (nu_idle_s) {
|
||||
nu_idle_s();
|
||||
} else {
|
||||
SYS_UnlockReg_S();
|
||||
CLK_Idle_S();
|
||||
SYS_LockReg_S();
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
|
|
@ -60,9 +74,13 @@ void hal_deepsleep(void)
|
|||
CLK_PowerDown();
|
||||
SYS_LockReg();
|
||||
#else
|
||||
SYS_UnlockReg_S();
|
||||
CLK_PowerDown_S();
|
||||
SYS_LockReg_S();
|
||||
if (nu_powerdown_s) {
|
||||
nu_powerdown_s();
|
||||
} else {
|
||||
SYS_UnlockReg_S();
|
||||
CLK_PowerDown_S();
|
||||
SYS_LockReg_S();
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -25,6 +25,9 @@
|
|||
#include "platform/mbed_error.h"
|
||||
#include "nu_modutil.h"
|
||||
#include "hal_secure.h"
|
||||
#if defined(DOMAIN_NS) && (DOMAIN_NS == 1L) && (TFM_LVL > 0)
|
||||
#include "tfm_ns_lock.h"
|
||||
#endif
|
||||
#include "partition_M2351.h"
|
||||
|
||||
#if defined(SCU_INIT_PNSSET5_VAL) && (SCU_INIT_PNSSET5_VAL & (1 << 25))
|
||||
|
|
@ -63,9 +66,11 @@ int trng_get_bytes(trng_t *obj, uint8_t *output, size_t length, size_t *output_l
|
|||
|
||||
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
|
||||
|
||||
extern "C"
|
||||
__NONSECURE_ENTRY
|
||||
void trng_init_s(MBED_UNUSED void *obj)
|
||||
static void trng_init_impl(void *obj);
|
||||
static void trng_free_impl(void *obj);
|
||||
static int32_t trng_get_bytes_impl(void *obj, uint8_t *output, uint32_t length, uint32_t *output_length);
|
||||
|
||||
static void trng_init_impl(MBED_UNUSED void *obj)
|
||||
{
|
||||
core_util_critical_section_enter();
|
||||
if (trng_init_counter == USHRT_MAX) {
|
||||
|
|
@ -89,9 +94,7 @@ void trng_init_s(MBED_UNUSED void *obj)
|
|||
core_util_critical_section_exit();
|
||||
}
|
||||
|
||||
extern "C"
|
||||
__NONSECURE_ENTRY
|
||||
void trng_free_s(MBED_UNUSED void *obj)
|
||||
static void trng_free_impl(MBED_UNUSED void *obj)
|
||||
{
|
||||
core_util_critical_section_enter();
|
||||
if (trng_init_counter == 0) {
|
||||
|
|
@ -111,9 +114,7 @@ void trng_free_s(MBED_UNUSED void *obj)
|
|||
core_util_critical_section_exit();
|
||||
}
|
||||
|
||||
extern "C"
|
||||
__NONSECURE_ENTRY
|
||||
int32_t trng_get_bytes_s(MBED_UNUSED void *obj, uint8_t *output, uint32_t length, uint32_t *output_length)
|
||||
static int32_t trng_get_bytes_impl(MBED_UNUSED void *obj, uint8_t *output, uint32_t length, uint32_t *output_length)
|
||||
{
|
||||
/* Check augument validity */
|
||||
if (!output && length) {
|
||||
|
|
@ -138,5 +139,102 @@ int32_t trng_get_bytes_s(MBED_UNUSED void *obj, uint8_t *output, uint32_t length
|
|||
return 0;
|
||||
}
|
||||
|
||||
#if (TFM_LVL > 0)
|
||||
|
||||
/* Add 'extern "C"' here to get around compile error on ARMC6 */
|
||||
|
||||
extern "C"
|
||||
__NONSECURE_ENTRY
|
||||
int32_t trng_init_veneer(uint32_t arg0, uint32_t arg1, uint32_t arg2, uint32_t arg3)
|
||||
{
|
||||
void *obj = (void *) arg0;
|
||||
trng_init_impl(obj);
|
||||
return 0;
|
||||
}
|
||||
|
||||
extern "C"
|
||||
__NONSECURE_ENTRY
|
||||
int32_t trng_free_veneer(uint32_t arg0, uint32_t arg1, uint32_t arg2, uint32_t arg3)
|
||||
{
|
||||
void *obj = (void *) arg0;
|
||||
trng_free_impl(obj);
|
||||
return 0;
|
||||
}
|
||||
|
||||
extern "C"
|
||||
__NONSECURE_ENTRY
|
||||
int32_t trng_get_bytes_veneer(uint32_t arg0, uint32_t arg1, uint32_t arg2, uint32_t arg3)
|
||||
{
|
||||
void *obj = (void *) arg0;
|
||||
uint8_t *output = (uint8_t *) arg1;
|
||||
uint32_t *length_bidi = (uint32_t *) arg2;
|
||||
int32_t *status = (int32_t *) arg3;
|
||||
*status = trng_get_bytes_impl(obj, output, *length_bidi, length_bidi);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
#if defined(DOMAIN_NS) && (DOMAIN_NS == 1) && (TFM_LVL > 0)
|
||||
|
||||
void trng_init_s(void *obj)
|
||||
{
|
||||
tfm_ns_lock_dispatch(trng_init_veneer, (uint32_t) obj, 0, 0, 0);
|
||||
}
|
||||
|
||||
void trng_free_s(void *obj)
|
||||
{
|
||||
tfm_ns_lock_dispatch(trng_free_veneer, (uint32_t) obj, 0, 0, 0);
|
||||
}
|
||||
|
||||
int32_t trng_get_bytes_s(void *obj, uint8_t *output, uint32_t length, uint32_t *output_length)
|
||||
{
|
||||
uint32_t length_bidi = length;
|
||||
int32_t status;
|
||||
|
||||
tfm_ns_lock_dispatch(trng_get_bytes_veneer, (uint32_t) obj, (uint32_t) output, (uint32_t) &length_bidi, (uint32_t) &status);
|
||||
|
||||
if (output_length) {
|
||||
*output_length = length_bidi;
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
#elif defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
|
||||
|
||||
/* Add 'extern "C"' here to get around compile error on ARMC6 */
|
||||
|
||||
#if (TFM_LVL == 0)
|
||||
extern "C"
|
||||
__NONSECURE_ENTRY
|
||||
#endif
|
||||
void trng_init_s(void *obj)
|
||||
{
|
||||
trng_init_impl(obj);
|
||||
}
|
||||
|
||||
#if (TFM_LVL == 0)
|
||||
extern "C"
|
||||
__NONSECURE_ENTRY
|
||||
#endif
|
||||
void trng_free_s(void *obj)
|
||||
{
|
||||
trng_free_impl(obj);
|
||||
}
|
||||
|
||||
#if (TFM_LVL == 0)
|
||||
extern "C"
|
||||
__NONSECURE_ENTRY
|
||||
#endif
|
||||
int32_t trng_get_bytes_s(void *obj, uint8_t *output, uint32_t length, uint32_t *output_length)
|
||||
{
|
||||
return trng_get_bytes_impl(obj, output, length, output_length);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -8856,6 +8856,64 @@
|
|||
"mbed_ram_start" : "0x20000000",
|
||||
"mbed_ram_size" : "0x2000"
|
||||
},
|
||||
"NU_PFM_M2351_NS": {
|
||||
"inherits": ["NSPE_Target", "NU_PFM_M2351"],
|
||||
"core": "Cortex-M23-NS",
|
||||
"tfm.level": 1,
|
||||
"extra_labels_add": [
|
||||
"M23_NS",
|
||||
"PSA",
|
||||
"TFM",
|
||||
"NU_PREBUILD_SECURE"
|
||||
],
|
||||
"macros_add": [
|
||||
"MBED_TZ_DEFAULT_ACCESS=1",
|
||||
"CMSIS_NVIC_VIRTUAL",
|
||||
"MBEDTLS_PSA_CRYPTO_C"
|
||||
],
|
||||
"components_add": ["FLASHIAP"],
|
||||
"post_binary_hook": {"function": "M2351Code.merge_secure"},
|
||||
"secure_image_filename": "tfm.hex",
|
||||
"overrides": {
|
||||
"secure-rom-start" : "0x0",
|
||||
"secure-rom-size" : "0x3C000",
|
||||
"secure-ram-start" : "0x20000000",
|
||||
"secure-ram-size" : "0x10000",
|
||||
"non-secure-rom-start" : "0x1003C000",
|
||||
"non-secure-rom-size" : "0x44000",
|
||||
"non-secure-ram-start" : "0x30010000",
|
||||
"non-secure-ram-size" : "0x8000"
|
||||
}
|
||||
},
|
||||
"NU_PFM_M2351_S": {
|
||||
"inherits": ["SPE_Target", "NU_PFM_M2351"],
|
||||
"core": "Cortex-M23",
|
||||
"tfm.level": 1,
|
||||
"extra_labels_add": [
|
||||
"M23_S",
|
||||
"PSA",
|
||||
"TFM"
|
||||
],
|
||||
"device_has_remove": ["SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "STDIO_MESSAGES"],
|
||||
"macros_add": [
|
||||
"DAUTH_CHIP_DEFAULT",
|
||||
"MBEDTLS_PSA_CRYPTO_C",
|
||||
"MBEDTLS_PSA_CRYPTO_SPM"
|
||||
],
|
||||
"components_add": ["FLASHIAP"],
|
||||
"deliver_to_target": "NU_PFM_M2351_NS",
|
||||
"delivery_dir": "TARGET_NUVOTON/TARGET_M2351/TARGET_M23_NS/TARGET_NU_PFM_M2351_NS/TARGET_NU_PREBUILD_SECURE",
|
||||
"overrides": {
|
||||
"secure-rom-start" : "0x0",
|
||||
"secure-rom-size" : "0x3C000",
|
||||
"secure-ram-start" : "0x20000000",
|
||||
"secure-ram-size" : "0x10000",
|
||||
"non-secure-rom-start" : "0x1003C000",
|
||||
"non-secure-rom-size" : "0x44000",
|
||||
"non-secure-ram-start" : "0x30010000",
|
||||
"non-secure-ram-size" : "0x8000"
|
||||
}
|
||||
},
|
||||
"NUMAKER_M252KG": {
|
||||
"core": "Cortex-M23",
|
||||
"trustzone": false,
|
||||
|
|
|
|||
Loading…
Reference in New Issue