6 Commits (920133e8edab4e77be2dacf414bd193fdba758c7)

Author	SHA1	Message	Date
Alexandre Bourdiol	315220832f	TARGET_STM: L0 CUBE SPI async mode send next byte after previous one read ... In STM32 Cube HAL, in interrupt mode (async), 2 bytes can be prepared in hardware registers without any read (1 in regular register, the other in shift register), but Only 1 RX byte can stored in hardware register, specially when there is no hardware FIFO. If interrupt handling is fast enough, each read is made in parralele of the write. But if interrupt handling is too long or is interrupted for too long, it can happen that one read byte is lost (overrun). For STM32F4, Tickless has been deactivated to avoid such issue. For STM32L0, we don't want to deactivate tickless, because those chips are specially design for lowpower. So instead of removing SPI async mode, we propose to change the HAL behavior specially for L0: each byte is send only when previous read is performed. Thus only 1 RX byte at a time which is saved in hardware register. This prevent overrun, but it introduceS some latency between each byte send, this is why it is not applied to all STM32 families.	2020-02-04 13:26:49 +01:00
bcostm	61576f8131	L0 ST CUBE V1.10.0: spi and i2c corrections	2018-04-18 14:06:20 +02:00
bcostm	8191487a4d	L0 ST CUBE V1.10.0	2018-04-18 14:06:20 +02:00
Laurent MEUNIER	64a037cc8d	STM32L0 - update spi HAL driver ... This is a temporary update waiting for the next official release	2016-11-18 09:59:53 +01:00
Laurent MEUNIER	ab0a8ad508	STM32L0: Cube update V1.5.0 to v1.7.0 ... Including HAL and CMSIS udpate	2016-11-10 11:03:46 +01:00
Christopher Haster	26ced98734	restructure - Restructured cmsis directory ... targets/cmsis -> cmsis targets/cmsis/TARGET_* -> targets/TARGET_*/device targets/cmsis/TARGET_*/mbed_rtx.h -> targets/TARGET_*/mbed_rtx.h	2016-10-04 17:51:44 -05:00