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STM32L0: Cube update V1.5.0 to v1.7.0 

Including HAL and CMSIS udpate
pull/3251/head
Laurent MEUNIER 2016-11-09 23:16:49 +01:00
parent 7963e8e7c1
commit ab0a8ad508
122 changed files with 30737 additions and 16194 deletions
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7837
targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/device/stm32l053xx.h
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30
targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/device/stm32l0xx.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx.h
* @author MCD Application Team
* @version V1.4.0
* @date 01-October-2015
* @version V1.7.0
* @date 31-May-2016
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
* This file contains all the peripheral register's definitions, bits
* definitions and memory mapping for STM32L0xx devices.
@ -12,8 +12,8 @@
* is using in the C source code, usually in main.c. This file contains:
* - Configuration section that allows to select:
* - The device used in the target application
* - To use or not the peripheral’s drivers in application code(i.e.
* code will be based on direct access to peripheral’s registers
* - To use or not the peripheral's drivers in application code(i.e.
* code will be based on direct access to peripheral's registers
* rather than drivers API), this option is controlled by
* "#define USE_HAL_DRIVER"
*
@ -89,7 +89,7 @@
/* #define STM32L041xx */ /*!< STM32L041C6, STM32L041E6, STM32L041F6, STM32L041G6, STM32L041K6 Devices */
/* #define STM32L051xx */ /*!< STM32L051K8, STM32L051C6, STM32L051C8, STM32L051R6, STM32L051R8 Devices */
/* #define STM32L052xx */ /*!< STM32L052K6, STM32L052K8, STM32L052C6, STM32L052C8, STM32L052R6, STM32L052R8 Devices */
#define STM32L053xx /*!< STM32L053C6, STM32L053C8, STM32L053R6, STM32L053R8 Devices */
#define STM32L053xx /*!< STM32L053C6, STM32L053C8, STM32L053R6, STM32L053R8 Devices */
/* #define STM32L061xx */ /*!< */
/* #define STM32L062xx */ /*!< STM32L062K8 */
/* #define STM32L063xx */ /*!< STM32L063C8, STM32L063R8 */
@ -114,16 +114,16 @@
#endif /* USE_HAL_DRIVER */
/**
* @brief CMSIS Device version number V1.2.0RC1
* @brief CMSIS Device version number V1.7.0
*/
#define __STM32L0xx_CMSIS_DEVICE_VERSION_MAIN (0x01) /*!< [31:24] main version */
#define __STM32L0xx_CMSIS_DEVICE_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
#define __STM32L0xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32L0xx_CMSIS_DEVICE_VERSION_RC (0x01) /*!< [7:0] release candidate */
#define __STM32L0xx_CMSIS_DEVICE_VERSION ((__CMSIS_DEVICE_VERSION_MAIN << 24)\
|(__CMSIS_DEVICE_HAL_VERSION_SUB1 << 16)\
|(__CMSIS_DEVICE_HAL_VERSION_SUB2 << 8 )\
|(__CMSIS_DEVICE_HAL_VERSION_RC))
#define __STM32L0xx_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */
#define __STM32L0xx_CMSIS_VERSION_SUB1 (0x07) /*!< [23:16] sub1 version */
#define __STM32L0xx_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32L0xx_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32L0xx_CMSIS_VERSION ((__STM32L0xx_CMSIS_VERSION_MAIN << 24)\
|(__STM32L0xx_CMSIS_VERSION_SUB1 << 16)\
|(__STM32L0xx_CMSIS_VERSION_SUB2 << 8 )\
|(__STM32L0xx_CMSIS_VERSION_RC))
/**
* @}
@ -216,8 +216,6 @@ typedef enum
#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
/**
* @}
*/

34
targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/device/stm32l0xx_hal_conf.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx_hal_conf.h
* @author MCD Application Team
* @version V1.5.0
* @date 8-January-2016
* @version V1.7.0
* @date 31-May-2016
* @brief HAL configuration template file.
* This file should be copied to the application folder and renamed
* to stm32l0xx_hal_conf.h.
@ -90,7 +90,7 @@
* (when HSE is used as system clock source, directly or through the PLL).
*/
#if !defined (HSE_VALUE)
#define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
#define HSE_VALUE ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */
#endif /* HSE_VALUE */
#if !defined (HSE_STARTUP_TIMEOUT)
@ -102,7 +102,7 @@
* This value is the default MSI range value after Reset.
*/
#if !defined (MSI_VALUE)
#define MSI_VALUE ((uint32_t)2000000) /*!< Value of the Internal oscillator in Hz*/
#define MSI_VALUE ((uint32_t)2000000U) /*!< Value of the Internal oscillator in Hz*/
#endif /* MSI_VALUE */
/**
* @brief Internal High Speed oscillator (HSI) value.
@ -110,14 +110,14 @@
* (when HSI is used as system clock source, directly or through the PLL).
*/
#if !defined (HSI_VALUE)
#define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
#define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */
/**
* @brief Internal High Speed oscillator for USB (HSI48) value.
*/
#if !defined (HSI48_VALUE)
#define HSI48_VALUE ((uint32_t)48000000) /*!< Value of the Internal High Speed oscillator for USB in Hz.
#define HSI48_VALUE ((uint32_t)48000000U) /*!< Value of the Internal High Speed oscillator for USB in Hz.
The real value may vary depending on the variations
in voltage and temperature. */
#endif /* HSI48_VALUE */
@ -126,7 +126,7 @@
* @brief Internal Low Speed oscillator (LSI) value.
*/
#if !defined (LSI_VALUE)
#define LSI_VALUE ((uint32_t)37000) /*!< LSI Typical Value in Hz*/
#define LSI_VALUE ((uint32_t)37000U) /*!< LSI Typical Value in Hz*/
#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
The real value may vary depending on the variations
in voltage and temperature.*/
@ -135,12 +135,12 @@
* This value is used by the UART, RTC HAL module to compute the system frequency
*/
#if !defined (LSE_VALUE)
#define LSE_VALUE ((uint32_t)32768) /*!< Value of the External oscillator in Hz*/
#define LSE_VALUE ((uint32_t)32768U) /*!< Value of the External oscillator in Hz*/
#endif /* LSE_VALUE */
#if !defined (LSE_STARTUP_TIMEOUT)
#define LSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for LSE start up, in ms */
#define LSE_STARTUP_TIMEOUT ((uint32_t)5000U) /*!< Time out for LSE start up, in ms */
#endif /* HSE_STARTUP_TIMEOUT */
@ -151,12 +151,12 @@
/**
* @brief This is the HAL system configuration section
*/
#define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */
#define TICK_INT_PRIORITY (((uint32_t)1<<__NVIC_PRIO_BITS) - 1) /*!< tick interrupt priority */
#define USE_RTOS 0
#define PREFETCH_ENABLE 1
#define PREREAD_ENABLE 0
#define BUFFER_CACHE_DISABLE 0
#define VDD_VALUE ((uint32_t)3300U) /*!< Value of VDD in mv */
#define TICK_INT_PRIORITY (((uint32_t)1U<<__NVIC_PRIO_BITS) - 1U) /*!< tick interrupt priority */
#define USE_RTOS 0U
#define PREFETCH_ENABLE 1U
#define PREREAD_ENABLE 0U
#define BUFFER_CACHE_DISABLE 0U
/* ########################## Assert Selection ############################## */
/**
@ -296,11 +296,11 @@
* If expr is true, it returns no value.
* @retval None
*/
#define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
/* Exported functions ------------------------------------------------------- */
void assert_failed(uint8_t* file, uint32_t line);
#else
#define assert_param(expr) ((void)0)
#define assert_param(expr) ((void)0U)
#endif /* USE_FULL_ASSERT */
#ifdef __cplusplus

61
targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/device/system_stm32l0xx.c
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@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32l0xx.c
* @author MCD Application Team
* @version V1.5.0
* @date 8-January-2016
* @version V1.7.0
* @date 31-May-2016
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Source File.
*
* This file provides two functions and one global variable to be called from
@ -40,7 +40,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -83,15 +83,15 @@
#include "hal_tick.h"
#if !defined (HSE_VALUE)
#define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
#define HSE_VALUE ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */
#endif /* HSE_VALUE */
#if !defined (MSI_VALUE)
#define MSI_VALUE ((uint32_t)2000000) /*!< Value of the Internal oscillator in Hz*/
#define MSI_VALUE ((uint32_t)2000000U) /*!< Value of the Internal oscillator in Hz*/
#endif /* MSI_VALUE */
#if !defined (HSI_VALUE)
#define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
#define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */
@ -115,8 +115,8 @@
/*!< Uncomment the following line if you need to relocate your vector Table in
Internal SRAM. */
/* #define VECT_TAB_SRAM */
#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
This value must be a multiple of 0x200. */
#define VECT_TAB_OFFSET 0x00U /*!< Vector Table base offset field.
This value must be a multiple of 0x100. */
/******************************************************************************/
/**
* @}
@ -146,8 +146,9 @@
variable is updated automatically.
*/
uint32_t SystemCoreClock = 32000000;
const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
const uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48};
const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U};
const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U};
const uint8_t PLLMulTable[9] = {3U, 4U, 6U, 8U, 12U, 16U, 24U, 32U, 48U};
/**
* @}
@ -179,25 +180,25 @@ uint8_t SetSysClock_PLL_HSI(void);
void SystemInit (void)
{
/*!< Set MSION bit */
RCC->CR |= (uint32_t)0x00000100;
RCC->CR |= (uint32_t)0x00000100U;
/*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */
RCC->CFGR &= (uint32_t) 0x88FF400C;
RCC->CFGR &= (uint32_t) 0x88FF400CU;
/*!< Reset HSION, HSIDIVEN, HSEON, CSSON and PLLON bits */
RCC->CR &= (uint32_t)0xFEF6FFF6;
RCC->CR &= (uint32_t)0xFEF6FFF6U;
/*!< Reset HSI48ON bit */
RCC->CRRCR &= (uint32_t)0xFFFFFFFE;
RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
/*!< Reset HSEBYP bit */
RCC->CR &= (uint32_t)0xFFFBFFFF;
RCC->CR &= (uint32_t)0xFFFBFFFFU;
/*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */
RCC->CFGR &= (uint32_t)0xFF02FFFF;
RCC->CFGR &= (uint32_t)0xFF02FFFFU;
/*!< Disable all interrupts */
RCC->CIER = 0x00000000;
RCC->CIER = 0x00000000U;
/* Configure the Vector Table location add offset address ------------------*/
#ifdef VECT_TAB_SRAM
@ -259,33 +260,33 @@ void SystemInit (void)
*/
void SystemCoreClockUpdate (void)
{
uint32_t tmp = 0, pllmul = 0, plldiv = 0, pllsource = 0, msirange = 0;
uint32_t tmp = 0U, pllmul = 0U, plldiv = 0U, pllsource = 0U, msirange = 0U;
/* Get SYSCLK source -------------------------------------------------------*/
tmp = RCC->CFGR & RCC_CFGR_SWS;
switch (tmp)
{
case 0x00: /* MSI used as system clock */
msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;
SystemCoreClock = (32768 * (1 << (msirange + 1)));
case 0x00U: /* MSI used as system clock */
msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13U;
SystemCoreClock = (32768U * (1U << (msirange + 1U)));
break;
case 0x04: /* HSI used as system clock */
case 0x04U: /* HSI used as system clock */
SystemCoreClock = HSI_VALUE;
break;
case 0x08: /* HSE used as system clock */
case 0x08U: /* HSE used as system clock */
SystemCoreClock = HSE_VALUE;
break;
case 0x0C: /* PLL used as system clock */
case 0x0CU: /* PLL used as system clock */
/* Get PLL clock source and multiplication factor ----------------------*/
pllmul = RCC->CFGR & RCC_CFGR_PLLMUL;
plldiv = RCC->CFGR & RCC_CFGR_PLLDIV;
pllmul = PLLMulTable[(pllmul >> 18)];
plldiv = (plldiv >> 22) + 1;
pllmul = PLLMulTable[(pllmul >> 18U)];
plldiv = (plldiv >> 22U) + 1U;
pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
if (pllsource == 0x00)
if (pllsource == 0x00U)
{
/* HSI oscillator clock selected as PLL clock entry */
SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv);
@ -297,13 +298,13 @@ void SystemCoreClockUpdate (void)
}
break;
default: /* MSI used as system clock */
msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;
SystemCoreClock = (32768 * (1 << (msirange + 1)));
msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13U;
SystemCoreClock = (32768U * (1U << (msirange + 1U)));
break;
}
/* Compute HCLK clock frequency --------------------------------------------*/
/* Get HCLK prescaler */
tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)];
/* HCLK clock frequency */
SystemCoreClock >>= tmp;
}

11
targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/device/system_stm32l0xx.h
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@ -2,13 +2,13 @@
******************************************************************************
* @file system_stm32l0xx.h
* @author MCD Application Team
* @version V1.5.0
* @date 8-January-2016
* @version V1.7.0
* @date 31-May-2016
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Header File.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -74,6 +74,11 @@
variable is updated automatically.
*/
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
/*
*/
extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */
extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */
extern const uint8_t PLLMulTable[9]; /*!< PLL multipiers table values */
/**
* @}

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targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L011K4/device/stm32l011xx.h
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targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L011K4/device/stm32l0xx.h
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@ -2,21 +2,21 @@
******************************************************************************
* @file stm32l0xx.h
* @author MCD Application Team
* @version V1.4.0
* @date 01-October-2015
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
* This file contains all the peripheral register's definitions, bits
* definitions and memory mapping for STM32L0xx devices.
*
* @version V1.7.0
* @date 31-May-2016
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
* This file contains all the peripheral register's definitions, bits
* definitions and memory mapping for STM32L0xx devices.
*
* The file is the unique include file that the application programmer
* is using in the C source code, usually in main.c. This file contains:
* - Configuration section that allows to select:
* - The device used in the target application
* - To use or not the peripheral’s drivers in application code(i.e.
* code will be based on direct access to peripheral’s registers
* rather than drivers API), this option is controlled by
* - To use or not the peripheral's drivers in application code(i.e.
* code will be based on direct access to peripheral's registers
* rather than drivers API), this option is controlled by
* "#define USE_HAL_DRIVER"
*
*
******************************************************************************
* @attention
*
@ -44,8 +44,8 @@
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
******************************************************************************
*/
/** @addtogroup CMSIS
* @{
@ -54,14 +54,14 @@
/** @addtogroup stm32l0xx
* @{
*/
#ifndef __STM32L0xx_H
#define __STM32L0xx_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/** @addtogroup Library_configuration_section
* @{
*/
@ -74,7 +74,7 @@
#endif /* STM32L0 */
/* Uncomment the line below according to the target STM32 device used in your
application
application
*/
#if !defined (STM32L011xx) && !defined (STM32L021xx) && \
@ -92,39 +92,39 @@
/* #define STM32L053xx */ /*!< STM32L053C6, STM32L053C8, STM32L053R6, STM32L053R8 Devices */
/* #define STM32L061xx */ /*!< */
/* #define STM32L062xx */ /*!< STM32L062K8 */
/* #define STM32L063xx */ /*!< STM32L063C8, STM32L063R8 */
/* #define STM32L063xx */ /*!< STM32L063C8, STM32L063R8 */
/* #define STM32L071xx */ /*!< */
/* #define STM32L072xx */ /*!< */
/* #define STM32L073xx */ /*!< STM32L073V8, STM32L073VB, STM32L073RB, STM32L073VZ, STM32L073RZ Devices */
/* #define STM32L081xx */ /*!< */
/* #define STM32L082xx */ /*!< */
/* #define STM32L083xx */ /*!< */
/* #define STM32L083xx */ /*!< */
#endif
/* Tip: To avoid modifying this file each time you need to switch between these
devices, you can define the device in your toolchain compiler preprocessor.
*/
#if !defined (USE_HAL_DRIVER)
/**
* @brief Comment the line below if you will not use the peripherals drivers.
In this case, these drivers will not be included and the application code will
be based on direct access to peripherals registers
In this case, these drivers will not be included and the application code will
be based on direct access to peripherals registers
*/
#define USE_HAL_DRIVER
#endif /* USE_HAL_DRIVER */
/**
* @brief CMSIS Device version number V1.2.0RC1
* @brief CMSIS Device version number V1.7.0
*/
#define __STM32L0xx_CMSIS_DEVICE_VERSION_MAIN (0x01) /*!< [31:24] main version */
#define __STM32L0xx_CMSIS_DEVICE_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
#define __STM32L0xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32L0xx_CMSIS_DEVICE_VERSION_RC (0x01) /*!< [7:0] release candidate */
#define __STM32L0xx_CMSIS_DEVICE_VERSION ((__CMSIS_DEVICE_VERSION_MAIN << 24)\
|(__CMSIS_DEVICE_HAL_VERSION_SUB1 << 16)\
|(__CMSIS_DEVICE_HAL_VERSION_SUB2 << 8 )\
|(__CMSIS_DEVICE_HAL_VERSION_RC))
#define __STM32L0xx_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */
#define __STM32L0xx_CMSIS_VERSION_SUB1 (0x07) /*!< [23:16] sub1 version */
#define __STM32L0xx_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32L0xx_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32L0xx_CMSIS_VERSION ((__STM32L0xx_CMSIS_VERSION_MAIN << 24)\
|(__STM32L0xx_CMSIS_VERSION_SUB1 << 16)\
|(__STM32L0xx_CMSIS_VERSION_SUB2 << 8 )\
|(__STM32L0xx_CMSIS_VERSION_RC))
/**
* @}
*/
@ -174,23 +174,23 @@
/** @addtogroup Exported_types
* @{
*/
typedef enum
*/
typedef enum
{
RESET = 0,
RESET = 0,
SET = !RESET
} FlagStatus, ITStatus;
typedef enum
typedef enum
{
DISABLE = 0,
DISABLE = 0,
ENABLE = !DISABLE
} FunctionalState;
#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
typedef enum
typedef enum
{
ERROR = 0,
ERROR = 0,
SUCCESS = !ERROR
} ErrorStatus;
@ -216,8 +216,6 @@ typedef enum
#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
/**
* @}
*/
@ -238,7 +236,7 @@ typedef enum
/**
* @}
*/

34
targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L011K4/device/stm32l0xx_hal_conf.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx_hal_conf.h
* @author MCD Application Team
* @version V1.5.0
* @date 8-January-2016
* @version V1.7.0
* @date 31-May-2016
* @brief HAL configuration template file.
* This file should be copied to the application folder and renamed
* to stm32l0xx_hal_conf.h.
@ -90,7 +90,7 @@
* (when HSE is used as system clock source, directly or through the PLL).
*/
#if !defined (HSE_VALUE)
#define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
#define HSE_VALUE ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */
#endif /* HSE_VALUE */
#if !defined (HSE_STARTUP_TIMEOUT)
@ -102,7 +102,7 @@
* This value is the default MSI range value after Reset.
*/
#if !defined (MSI_VALUE)
#define MSI_VALUE ((uint32_t)2000000) /*!< Value of the Internal oscillator in Hz*/
#define MSI_VALUE ((uint32_t)2000000U) /*!< Value of the Internal oscillator in Hz*/
#endif /* MSI_VALUE */
/**
* @brief Internal High Speed oscillator (HSI) value.
@ -110,14 +110,14 @@
* (when HSI is used as system clock source, directly or through the PLL).
*/
#if !defined (HSI_VALUE)
#define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
#define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */
/**
* @brief Internal High Speed oscillator for USB (HSI48) value.
*/
#if !defined (HSI48_VALUE)
#define HSI48_VALUE ((uint32_t)48000000) /*!< Value of the Internal High Speed oscillator for USB in Hz.
#define HSI48_VALUE ((uint32_t)48000000U) /*!< Value of the Internal High Speed oscillator for USB in Hz.
The real value may vary depending on the variations
in voltage and temperature. */
#endif /* HSI48_VALUE */
@ -126,7 +126,7 @@
* @brief Internal Low Speed oscillator (LSI) value.
*/
#if !defined (LSI_VALUE)
#define LSI_VALUE ((uint32_t)37000) /*!< LSI Typical Value in Hz*/
#define LSI_VALUE ((uint32_t)37000U) /*!< LSI Typical Value in Hz*/
#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
The real value may vary depending on the variations
in voltage and temperature.*/
@ -135,12 +135,12 @@
* This value is used by the UART, RTC HAL module to compute the system frequency
*/
#if !defined (LSE_VALUE)
#define LSE_VALUE ((uint32_t)32768) /*!< Value of the External oscillator in Hz*/
#define LSE_VALUE ((uint32_t)32768U) /*!< Value of the External oscillator in Hz*/
#endif /* LSE_VALUE */
#if !defined (LSE_STARTUP_TIMEOUT)
#define LSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for LSE start up, in ms */
#define LSE_STARTUP_TIMEOUT ((uint32_t)5000U) /*!< Time out for LSE start up, in ms */
#endif /* HSE_STARTUP_TIMEOUT */
@ -151,12 +151,12 @@
/**
* @brief This is the HAL system configuration section
*/
#define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */
#define TICK_INT_PRIORITY (((uint32_t)1<<__NVIC_PRIO_BITS) - 1) /*!< tick interrupt priority */
#define USE_RTOS 0
#define PREFETCH_ENABLE 1
#define PREREAD_ENABLE 0
#define BUFFER_CACHE_DISABLE 0
#define VDD_VALUE ((uint32_t)3300U) /*!< Value of VDD in mv */
#define TICK_INT_PRIORITY (((uint32_t)1U<<__NVIC_PRIO_BITS) - 1U) /*!< tick interrupt priority */
#define USE_RTOS 0U
#define PREFETCH_ENABLE 1U
#define PREREAD_ENABLE 0U
#define BUFFER_CACHE_DISABLE 0U
/* ########################## Assert Selection ############################## */
/**
@ -296,11 +296,11 @@
* If expr is true, it returns no value.
* @retval None
*/
#define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
/* Exported functions ------------------------------------------------------- */
void assert_failed(uint8_t* file, uint32_t line);
#else
#define assert_param(expr) ((void)0)
#define assert_param(expr) ((void)0U)
#endif /* USE_FULL_ASSERT */
#ifdef __cplusplus

61
targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L011K4/device/system_stm32l0xx.c
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@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32l0xx.c
* @author MCD Application Team
* @version V1.5.0
* @date 8-January-2016
* @version V1.7.0
* @date 31-May-2016
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Source File.
*
* This file provides two functions and one global variable to be called from
@ -40,7 +40,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -83,15 +83,15 @@
#include "hal_tick.h"
#if !defined (HSE_VALUE)
#define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
#define HSE_VALUE ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */
#endif /* HSE_VALUE */
#if !defined (MSI_VALUE)
#define MSI_VALUE ((uint32_t)2000000) /*!< Value of the Internal oscillator in Hz*/
#define MSI_VALUE ((uint32_t)2000000U) /*!< Value of the Internal oscillator in Hz*/
#endif /* MSI_VALUE */
#if !defined (HSI_VALUE)
#define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
#define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */
@ -115,8 +115,8 @@
/*!< Uncomment the following line if you need to relocate your vector Table in
Internal SRAM. */
/* #define VECT_TAB_SRAM */
#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
This value must be a multiple of 0x200. */
#define VECT_TAB_OFFSET 0x00U /*!< Vector Table base offset field.
This value must be a multiple of 0x100. */
/******************************************************************************/
/**
* @}
@ -146,8 +146,9 @@
variable is updated automatically.
*/
uint32_t SystemCoreClock = 32000000;
const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
const uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48};
const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U};
const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U};
const uint8_t PLLMulTable[9] = {3U, 4U, 6U, 8U, 12U, 16U, 24U, 32U, 48U};
/**
* @}
@ -179,25 +180,25 @@ uint8_t SetSysClock_PLL_HSI(void);
void SystemInit (void)
{
/*!< Set MSION bit */
RCC->CR |= (uint32_t)0x00000100;
RCC->CR |= (uint32_t)0x00000100U;
/*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */
RCC->CFGR &= (uint32_t) 0x88FF400C;
RCC->CFGR &= (uint32_t) 0x88FF400CU;
/*!< Reset HSION, HSIDIVEN, HSEON, CSSON and PLLON bits */
RCC->CR &= (uint32_t)0xFEF6FFF6;
RCC->CR &= (uint32_t)0xFEF6FFF6U;
/*!< Reset HSI48ON bit */
RCC->CRRCR &= (uint32_t)0xFFFFFFFE;
RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
/*!< Reset HSEBYP bit */
RCC->CR &= (uint32_t)0xFFFBFFFF;
RCC->CR &= (uint32_t)0xFFFBFFFFU;
/*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */
RCC->CFGR &= (uint32_t)0xFF02FFFF;
RCC->CFGR &= (uint32_t)0xFF02FFFFU;
/*!< Disable all interrupts */
RCC->CIER = 0x00000000;
RCC->CIER = 0x00000000U;
/* Configure the Vector Table location add offset address ------------------*/
#ifdef VECT_TAB_SRAM
@ -259,33 +260,33 @@ void SystemInit (void)
*/
void SystemCoreClockUpdate (void)
{
uint32_t tmp = 0, pllmul = 0, plldiv = 0, pllsource = 0, msirange = 0;
uint32_t tmp = 0U, pllmul = 0U, plldiv = 0U, pllsource = 0U, msirange = 0U;
/* Get SYSCLK source -------------------------------------------------------*/
tmp = RCC->CFGR & RCC_CFGR_SWS;
switch (tmp)
{
case 0x00: /* MSI used as system clock */
msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;
SystemCoreClock = (32768 * (1 << (msirange + 1)));
case 0x00U: /* MSI used as system clock */
msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13U;
SystemCoreClock = (32768U * (1U << (msirange + 1U)));
break;
case 0x04: /* HSI used as system clock */
case 0x04U: /* HSI used as system clock */
SystemCoreClock = HSI_VALUE;
break;
case 0x08: /* HSE used as system clock */
case 0x08U: /* HSE used as system clock */
SystemCoreClock = HSE_VALUE;
break;
case 0x0C: /* PLL used as system clock */
case 0x0CU: /* PLL used as system clock */
/* Get PLL clock source and multiplication factor ----------------------*/
pllmul = RCC->CFGR & RCC_CFGR_PLLMUL;
plldiv = RCC->CFGR & RCC_CFGR_PLLDIV;
pllmul = PLLMulTable[(pllmul >> 18)];
plldiv = (plldiv >> 22) + 1;
pllmul = PLLMulTable[(pllmul >> 18U)];
plldiv = (plldiv >> 22U) + 1U;
pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
if (pllsource == 0x00)
if (pllsource == 0x00U)
{
/* HSI oscillator clock selected as PLL clock entry */
SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv);
@ -297,13 +298,13 @@ void SystemCoreClockUpdate (void)
}
break;
default: /* MSI used as system clock */
msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;
SystemCoreClock = (32768 * (1 << (msirange + 1)));
msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13U;
SystemCoreClock = (32768U * (1U << (msirange + 1U)));
break;
}
/* Compute HCLK clock frequency --------------------------------------------*/
/* Get HCLK prescaler */
tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)];
/* HCLK clock frequency */
SystemCoreClock >>= tmp;
}

11
targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L011K4/device/system_stm32l0xx.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file system_stm32l0xx.h
* @author MCD Application Team
* @version V1.5.0
* @date 8-January-2016
* @version V1.7.0
* @date 31-May-2016
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Header File.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -74,6 +74,11 @@
variable is updated automatically.
*/
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
/*
*/
extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */
extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */
extern const uint8_t PLLMulTable[9]; /*!< PLL multipiers table values */
/**
* @}

6349
targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/device/stm32l031xx.h
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80
targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/device/stm32l0xx.h
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@ -2,21 +2,21 @@
******************************************************************************
* @file stm32l0xx.h
* @author MCD Application Team
* @version V1.4.0
* @date 01-October-2015
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
* This file contains all the peripheral register's definitions, bits
* definitions and memory mapping for STM32L0xx devices.
*
* @version V1.7.0
* @date 31-May-2016
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
* This file contains all the peripheral register's definitions, bits
* definitions and memory mapping for STM32L0xx devices.
*
* The file is the unique include file that the application programmer
* is using in the C source code, usually in main.c. This file contains:
* - Configuration section that allows to select:
* - The device used in the target application
* - To use or not the peripheral’s drivers in application code(i.e.
* code will be based on direct access to peripheral’s registers
* rather than drivers API), this option is controlled by
* - To use or not the peripheral's drivers in application code(i.e.
* code will be based on direct access to peripheral's registers
* rather than drivers API), this option is controlled by
* "#define USE_HAL_DRIVER"
*
*
******************************************************************************
* @attention
*
@ -44,8 +44,8 @@
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
******************************************************************************
*/
/** @addtogroup CMSIS
* @{
@ -54,14 +54,14 @@
/** @addtogroup stm32l0xx
* @{
*/
#ifndef __STM32L0xx_H
#define __STM32L0xx_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/** @addtogroup Library_configuration_section
* @{
*/
@ -74,7 +74,7 @@
#endif /* STM32L0 */
/* Uncomment the line below according to the target STM32 device used in your
application
application
*/
#if !defined (STM32L011xx) && !defined (STM32L021xx) && \
@ -85,46 +85,46 @@
!defined (STM32L081xx) && !defined (STM32L082xx) && !defined (STM32L083xx) \
/* #define STM32L011xx */
/* #define STM32L021xx */
#define STM32L031xx /*!< STM32L031C6, STM32L031E6, STM32L031F6, STM32L031G6, STM32L031K6 Devices */
#define STM32L031xx /*!< STM32L031C6, STM32L031E6, STM32L031F6, STM32L031G6, STM32L031K6 Devices */
/* #define STM32L041xx */ /*!< STM32L041C6, STM32L041E6, STM32L041F6, STM32L041G6, STM32L041K6 Devices */
/* #define STM32L051xx */ /*!< STM32L051K8, STM32L051C6, STM32L051C8, STM32L051R6, STM32L051R8 Devices */
/* #define STM32L052xx */ /*!< STM32L052K6, STM32L052K8, STM32L052C6, STM32L052C8, STM32L052R6, STM32L052R8 Devices */
/* #define STM32L053xx */ /*!< STM32L053C6, STM32L053C8, STM32L053R6, STM32L053R8 Devices */
/* #define STM32L061xx */ /*!< */
/* #define STM32L062xx */ /*!< STM32L062K8 */
/* #define STM32L063xx */ /*!< STM32L063C8, STM32L063R8 */
/* #define STM32L063xx */ /*!< STM32L063C8, STM32L063R8 */
/* #define STM32L071xx */ /*!< */
/* #define STM32L072xx */ /*!< */
/* #define STM32L073xx */ /*!< STM32L073V8, STM32L073VB, STM32L073RB, STM32L073VZ, STM32L073RZ Devices */
/* #define STM32L081xx */ /*!< */
/* #define STM32L082xx */ /*!< */
/* #define STM32L083xx */ /*!< */
/* #define STM32L083xx */ /*!< */
#endif
/* Tip: To avoid modifying this file each time you need to switch between these
devices, you can define the device in your toolchain compiler preprocessor.
*/
#if !defined (USE_HAL_DRIVER)
/**
* @brief Comment the line below if you will not use the peripherals drivers.
In this case, these drivers will not be included and the application code will
be based on direct access to peripherals registers
In this case, these drivers will not be included and the application code will
be based on direct access to peripherals registers
*/
#define USE_HAL_DRIVER
#endif /* USE_HAL_DRIVER */
/**
* @brief CMSIS Device version number V1.2.0RC1
* @brief CMSIS Device version number V1.7.0
*/
#define __STM32L0xx_CMSIS_DEVICE_VERSION_MAIN (0x01) /*!< [31:24] main version */
#define __STM32L0xx_CMSIS_DEVICE_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
#define __STM32L0xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32L0xx_CMSIS_DEVICE_VERSION_RC (0x01) /*!< [7:0] release candidate */
#define __STM32L0xx_CMSIS_DEVICE_VERSION ((__CMSIS_DEVICE_VERSION_MAIN << 24)\
|(__CMSIS_DEVICE_HAL_VERSION_SUB1 << 16)\
|(__CMSIS_DEVICE_HAL_VERSION_SUB2 << 8 )\
|(__CMSIS_DEVICE_HAL_VERSION_RC))
#define __STM32L0xx_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */
#define __STM32L0xx_CMSIS_VERSION_SUB1 (0x07) /*!< [23:16] sub1 version */
#define __STM32L0xx_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32L0xx_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32L0xx_CMSIS_VERSION ((__STM32L0xx_CMSIS_VERSION_MAIN << 24)\
|(__STM32L0xx_CMSIS_VERSION_SUB1 << 16)\
|(__STM32L0xx_CMSIS_VERSION_SUB2 << 8 )\
|(__STM32L0xx_CMSIS_VERSION_RC))
/**
* @}
*/
@ -174,23 +174,23 @@
/** @addtogroup Exported_types
* @{
*/
typedef enum
*/
typedef enum
{
RESET = 0,
RESET = 0,
SET = !RESET
} FlagStatus, ITStatus;
typedef enum
typedef enum
{
DISABLE = 0,
DISABLE = 0,
ENABLE = !DISABLE
} FunctionalState;
#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
typedef enum
typedef enum
{
ERROR = 0,
ERROR = 0,
SUCCESS = !ERROR
} ErrorStatus;
@ -216,8 +216,6 @@ typedef enum
#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
/**
* @}
*/
@ -238,7 +236,7 @@ typedef enum
/**
* @}
*/

34
targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/device/stm32l0xx_hal_conf.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx_hal_conf.h
* @author MCD Application Team
* @version V1.5.0
* @date 8-January-2016
* @version V1.7.0
* @date 31-May-2016
* @brief HAL configuration template file.
* This file should be copied to the application folder and renamed
* to stm32l0xx_hal_conf.h.
@ -90,7 +90,7 @@
* (when HSE is used as system clock source, directly or through the PLL).
*/
#if !defined (HSE_VALUE)
#define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
#define HSE_VALUE ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */
#endif /* HSE_VALUE */
#if !defined (HSE_STARTUP_TIMEOUT)
@ -102,7 +102,7 @@
* This value is the default MSI range value after Reset.
*/
#if !defined (MSI_VALUE)
#define MSI_VALUE ((uint32_t)2000000) /*!< Value of the Internal oscillator in Hz*/
#define MSI_VALUE ((uint32_t)2000000U) /*!< Value of the Internal oscillator in Hz*/
#endif /* MSI_VALUE */
/**
* @brief Internal High Speed oscillator (HSI) value.
@ -110,14 +110,14 @@
* (when HSI is used as system clock source, directly or through the PLL).
*/
#if !defined (HSI_VALUE)
#define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
#define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */
/**
* @brief Internal High Speed oscillator for USB (HSI48) value.
*/
#if !defined (HSI48_VALUE)
#define HSI48_VALUE ((uint32_t)48000000) /*!< Value of the Internal High Speed oscillator for USB in Hz.
#define HSI48_VALUE ((uint32_t)48000000U) /*!< Value of the Internal High Speed oscillator for USB in Hz.
The real value may vary depending on the variations
in voltage and temperature. */
#endif /* HSI48_VALUE */
@ -126,7 +126,7 @@
* @brief Internal Low Speed oscillator (LSI) value.
*/
#if !defined (LSI_VALUE)
#define LSI_VALUE ((uint32_t)37000) /*!< LSI Typical Value in Hz*/
#define LSI_VALUE ((uint32_t)37000U) /*!< LSI Typical Value in Hz*/
#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
The real value may vary depending on the variations
in voltage and temperature.*/
@ -135,12 +135,12 @@
* This value is used by the UART, RTC HAL module to compute the system frequency
*/
#if !defined (LSE_VALUE)
#define LSE_VALUE ((uint32_t)32768) /*!< Value of the External oscillator in Hz*/
#define LSE_VALUE ((uint32_t)32768U) /*!< Value of the External oscillator in Hz*/
#endif /* LSE_VALUE */
#if !defined (LSE_STARTUP_TIMEOUT)
#define LSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for LSE start up, in ms */
#define LSE_STARTUP_TIMEOUT ((uint32_t)5000U) /*!< Time out for LSE start up, in ms */
#endif /* HSE_STARTUP_TIMEOUT */
@ -151,12 +151,12 @@
/**
* @brief This is the HAL system configuration section
*/
#define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */
#define TICK_INT_PRIORITY (((uint32_t)1<<__NVIC_PRIO_BITS) - 1) /*!< tick interrupt priority */
#define USE_RTOS 0
#define PREFETCH_ENABLE 1
#define PREREAD_ENABLE 0
#define BUFFER_CACHE_DISABLE 0
#define VDD_VALUE ((uint32_t)3300U) /*!< Value of VDD in mv */
#define TICK_INT_PRIORITY (((uint32_t)1U<<__NVIC_PRIO_BITS) - 1U) /*!< tick interrupt priority */
#define USE_RTOS 0U
#define PREFETCH_ENABLE 1U
#define PREREAD_ENABLE 0U
#define BUFFER_CACHE_DISABLE 0U
/* ########################## Assert Selection ############################## */
/**
@ -296,11 +296,11 @@
* If expr is true, it returns no value.
* @retval None
*/
#define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
/* Exported functions ------------------------------------------------------- */
void assert_failed(uint8_t* file, uint32_t line);
#else
#define assert_param(expr) ((void)0)
#define assert_param(expr) ((void)0U)
#endif /* USE_FULL_ASSERT */
#ifdef __cplusplus

61
targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/device/system_stm32l0xx.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32l0xx.c
* @author MCD Application Team
* @version V1.5.0
* @date 8-January-2016
* @version V1.7.0
* @date 31-May-2016
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Source File.
*
* This file provides two functions and one global variable to be called from
@ -40,7 +40,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -83,15 +83,15 @@
#include "hal_tick.h"
#if !defined (HSE_VALUE)
#define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
#define HSE_VALUE ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */
#endif /* HSE_VALUE */
#if !defined (MSI_VALUE)
#define MSI_VALUE ((uint32_t)2000000) /*!< Value of the Internal oscillator in Hz*/
#define MSI_VALUE ((uint32_t)2000000U) /*!< Value of the Internal oscillator in Hz*/
#endif /* MSI_VALUE */
#if !defined (HSI_VALUE)
#define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
#define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */
@ -115,8 +115,8 @@
/*!< Uncomment the following line if you need to relocate your vector Table in
Internal SRAM. */
/* #define VECT_TAB_SRAM */
#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
This value must be a multiple of 0x200. */
#define VECT_TAB_OFFSET 0x00U /*!< Vector Table base offset field.
This value must be a multiple of 0x100. */
/******************************************************************************/
/**
* @}
@ -147,8 +147,9 @@
variable is updated automatically.
*/
uint32_t SystemCoreClock = 32000000;
const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
const uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48};
const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U};
const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U};
const uint8_t PLLMulTable[9] = {3U, 4U, 6U, 8U, 12U, 16U, 24U, 32U, 48U};
/**
* @}
@ -181,25 +182,25 @@ uint8_t SetSysClock_MSI(void);
void SystemInit (void)
{
/*!< Set MSION bit */
RCC->CR |= (uint32_t)0x00000100;
RCC->CR |= (uint32_t)0x00000100U;
/*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */
RCC->CFGR &= (uint32_t) 0x88FF400C;
RCC->CFGR &= (uint32_t) 0x88FF400CU;
/*!< Reset HSION, HSIDIVEN, HSEON, CSSON and PLLON bits */
RCC->CR &= (uint32_t)0xFEF6FFF6;
RCC->CR &= (uint32_t)0xFEF6FFF6U;
/*!< Reset HSI48ON bit */
RCC->CRRCR &= (uint32_t)0xFFFFFFFE;
RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
/*!< Reset HSEBYP bit */
RCC->CR &= (uint32_t)0xFFFBFFFF;
RCC->CR &= (uint32_t)0xFFFBFFFFU;
/*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */
RCC->CFGR &= (uint32_t)0xFF02FFFF;
RCC->CFGR &= (uint32_t)0xFF02FFFFU;
/*!< Disable all interrupts */
RCC->CIER = 0x00000000;
RCC->CIER = 0x00000000U;
/* Configure the Vector Table location add offset address ------------------*/
#ifdef VECT_TAB_SRAM
@ -261,33 +262,33 @@ void SystemInit (void)
*/
void SystemCoreClockUpdate (void)
{
uint32_t tmp = 0, pllmul = 0, plldiv = 0, pllsource = 0, msirange = 0;
uint32_t tmp = 0U, pllmul = 0U, plldiv = 0U, pllsource = 0U, msirange = 0U;
/* Get SYSCLK source -------------------------------------------------------*/
tmp = RCC->CFGR & RCC_CFGR_SWS;
switch (tmp)
{
case 0x00: /* MSI used as system clock */
msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;
SystemCoreClock = (32768 * (1 << (msirange + 1)));
case 0x00U: /* MSI used as system clock */
msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13U;
SystemCoreClock = (32768U * (1U << (msirange + 1U)));
break;
case 0x04: /* HSI used as system clock */
case 0x04U: /* HSI used as system clock */
SystemCoreClock = HSI_VALUE;
break;
case 0x08: /* HSE used as system clock */
case 0x08U: /* HSE used as system clock */
SystemCoreClock = HSE_VALUE;
break;
case 0x0C: /* PLL used as system clock */
case 0x0CU: /* PLL used as system clock */
/* Get PLL clock source and multiplication factor ----------------------*/
pllmul = RCC->CFGR & RCC_CFGR_PLLMUL;
plldiv = RCC->CFGR & RCC_CFGR_PLLDIV;
pllmul = PLLMulTable[(pllmul >> 18)];
plldiv = (plldiv >> 22) + 1;
pllmul = PLLMulTable[(pllmul >> 18U)];
plldiv = (plldiv >> 22U) + 1U;
pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
if (pllsource == 0x00)
if (pllsource == 0x00U)
{
/* HSI oscillator clock selected as PLL clock entry */
SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv);
@ -299,13 +300,13 @@ void SystemCoreClockUpdate (void)
}
break;
default: /* MSI used as system clock */
msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;
SystemCoreClock = (32768 * (1 << (msirange + 1)));
msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13U;
SystemCoreClock = (32768U * (1U << (msirange + 1U)));
break;
}
/* Compute HCLK clock frequency --------------------------------------------*/
/* Get HCLK prescaler */
tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)];
/* HCLK clock frequency */
SystemCoreClock >>= tmp;
}

11
targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/device/system_stm32l0xx.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file system_stm32l0xx.h
* @author MCD Application Team
* @version V1.5.0
* @date 8-January-2016
* @version V1.7.0
* @date 31-May-2016
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Header File.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -74,6 +74,11 @@
variable is updated automatically.
*/
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
/*
*/
extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */
extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */
extern const uint8_t PLLMulTable[9]; /*!< PLL multipiers table values */
/**
* @}

7837
targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/device/stm32l053xx.h
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30
targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/device/stm32l0xx.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx.h
* @author MCD Application Team
* @version V1.4.0
* @date 01-October-2015
* @version V1.7.0
* @date 31-May-2016
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
* This file contains all the peripheral register's definitions, bits
* definitions and memory mapping for STM32L0xx devices.
@ -12,8 +12,8 @@
* is using in the C source code, usually in main.c. This file contains:
* - Configuration section that allows to select:
* - The device used in the target application
* - To use or not the peripheral’s drivers in application code(i.e.
* code will be based on direct access to peripheral’s registers
* - To use or not the peripheral's drivers in application code(i.e.
* code will be based on direct access to peripheral's registers
* rather than drivers API), this option is controlled by
* "#define USE_HAL_DRIVER"
*
@ -89,7 +89,7 @@
/* #define STM32L041xx */ /*!< STM32L041C6, STM32L041E6, STM32L041F6, STM32L041G6, STM32L041K6 Devices */
/* #define STM32L051xx */ /*!< STM32L051K8, STM32L051C6, STM32L051C8, STM32L051R6, STM32L051R8 Devices */
/* #define STM32L052xx */ /*!< STM32L052K6, STM32L052K8, STM32L052C6, STM32L052C8, STM32L052R6, STM32L052R8 Devices */
#define STM32L053xx /*!< STM32L053C6, STM32L053C8, STM32L053R6, STM32L053R8 Devices */
#define STM32L053xx /*!< STM32L053C6, STM32L053C8, STM32L053R6, STM32L053R8 Devices */
/* #define STM32L061xx */ /*!< */
/* #define STM32L062xx */ /*!< STM32L062K8 */
/* #define STM32L063xx */ /*!< STM32L063C8, STM32L063R8 */
@ -114,16 +114,16 @@
#endif /* USE_HAL_DRIVER */
/**
* @brief CMSIS Device version number V1.2.0RC1
* @brief CMSIS Device version number V1.7.0
*/
#define __STM32L0xx_CMSIS_DEVICE_VERSION_MAIN (0x01) /*!< [31:24] main version */
#define __STM32L0xx_CMSIS_DEVICE_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
#define __STM32L0xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32L0xx_CMSIS_DEVICE_VERSION_RC (0x01) /*!< [7:0] release candidate */
#define __STM32L0xx_CMSIS_DEVICE_VERSION ((__CMSIS_DEVICE_VERSION_MAIN << 24)\
|(__CMSIS_DEVICE_HAL_VERSION_SUB1 << 16)\
|(__CMSIS_DEVICE_HAL_VERSION_SUB2 << 8 )\
|(__CMSIS_DEVICE_HAL_VERSION_RC))
#define __STM32L0xx_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */
#define __STM32L0xx_CMSIS_VERSION_SUB1 (0x07) /*!< [23:16] sub1 version */
#define __STM32L0xx_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32L0xx_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32L0xx_CMSIS_VERSION ((__STM32L0xx_CMSIS_VERSION_MAIN << 24)\
|(__STM32L0xx_CMSIS_VERSION_SUB1 << 16)\
|(__STM32L0xx_CMSIS_VERSION_SUB2 << 8 )\
|(__STM32L0xx_CMSIS_VERSION_RC))
/**
* @}
@ -216,8 +216,6 @@ typedef enum
#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
/**
* @}
*/

34
targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/device/stm32l0xx_hal_conf.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx_hal_conf.h
* @author MCD Application Team
* @version V1.5.0
* @date 8-January-2016
* @version V1.7.0
* @date 31-May-2016
* @brief HAL configuration template file.
* This file should be copied to the application folder and renamed
* to stm32l0xx_hal_conf.h.
@ -90,7 +90,7 @@
* (when HSE is used as system clock source, directly or through the PLL).
*/
#if !defined (HSE_VALUE)
#define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
#define HSE_VALUE ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */
#endif /* HSE_VALUE */
#if !defined (HSE_STARTUP_TIMEOUT)
@ -102,7 +102,7 @@
* This value is the default MSI range value after Reset.
*/
#if !defined (MSI_VALUE)
#define MSI_VALUE ((uint32_t)2000000) /*!< Value of the Internal oscillator in Hz*/
#define MSI_VALUE ((uint32_t)2000000U) /*!< Value of the Internal oscillator in Hz*/
#endif /* MSI_VALUE */
/**
* @brief Internal High Speed oscillator (HSI) value.
@ -110,14 +110,14 @@
* (when HSI is used as system clock source, directly or through the PLL).
*/
#if !defined (HSI_VALUE)
#define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
#define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */
/**
* @brief Internal High Speed oscillator for USB (HSI48) value.
*/
#if !defined (HSI48_VALUE)
#define HSI48_VALUE ((uint32_t)48000000) /*!< Value of the Internal High Speed oscillator for USB in Hz.
#define HSI48_VALUE ((uint32_t)48000000U) /*!< Value of the Internal High Speed oscillator for USB in Hz.
The real value may vary depending on the variations
in voltage and temperature. */
#endif /* HSI48_VALUE */
@ -126,7 +126,7 @@
* @brief Internal Low Speed oscillator (LSI) value.
*/
#if !defined (LSI_VALUE)
#define LSI_VALUE ((uint32_t)37000) /*!< LSI Typical Value in Hz*/
#define LSI_VALUE ((uint32_t)37000U) /*!< LSI Typical Value in Hz*/
#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
The real value may vary depending on the variations
in voltage and temperature.*/
@ -135,12 +135,12 @@
* This value is used by the UART, RTC HAL module to compute the system frequency
*/
#if !defined (LSE_VALUE)
#define LSE_VALUE ((uint32_t)32768) /*!< Value of the External oscillator in Hz*/
#define LSE_VALUE ((uint32_t)32768U) /*!< Value of the External oscillator in Hz*/
#endif /* LSE_VALUE */
#if !defined (LSE_STARTUP_TIMEOUT)
#define LSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for LSE start up, in ms */
#define LSE_STARTUP_TIMEOUT ((uint32_t)5000U) /*!< Time out for LSE start up, in ms */
#endif /* HSE_STARTUP_TIMEOUT */
@ -151,12 +151,12 @@
/**
* @brief This is the HAL system configuration section
*/
#define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */
#define TICK_INT_PRIORITY (((uint32_t)1<<__NVIC_PRIO_BITS) - 1) /*!< tick interrupt priority */
#define USE_RTOS 0
#define PREFETCH_ENABLE 1
#define PREREAD_ENABLE 0
#define BUFFER_CACHE_DISABLE 0
#define VDD_VALUE ((uint32_t)3300U) /*!< Value of VDD in mv */
#define TICK_INT_PRIORITY (((uint32_t)1U<<__NVIC_PRIO_BITS) - 1U) /*!< tick interrupt priority */
#define USE_RTOS 0U
#define PREFETCH_ENABLE 1U
#define PREREAD_ENABLE 0U
#define BUFFER_CACHE_DISABLE 0U
/* ########################## Assert Selection ############################## */
/**
@ -296,11 +296,11 @@
* If expr is true, it returns no value.
* @retval None
*/
#define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
/* Exported functions ------------------------------------------------------- */
void assert_failed(uint8_t* file, uint32_t line);
#else
#define assert_param(expr) ((void)0)
#define assert_param(expr) ((void)0U)
#endif /* USE_FULL_ASSERT */
#ifdef __cplusplus

61
targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/device/system_stm32l0xx.c
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@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32l0xx.c
* @author MCD Application Team
* @version V1.5.0
* @date 8-January-2016
* @version V1.7.0
* @date 31-May-2016
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Source File.
*
* This file provides two functions and one global variable to be called from
@ -40,7 +40,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -83,15 +83,15 @@
#include "hal_tick.h"
#if !defined (HSE_VALUE)
#define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
#define HSE_VALUE ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */
#endif /* HSE_VALUE */
#if !defined (MSI_VALUE)
#define MSI_VALUE ((uint32_t)2000000) /*!< Value of the Internal oscillator in Hz*/
#define MSI_VALUE ((uint32_t)2000000U) /*!< Value of the Internal oscillator in Hz*/
#endif /* MSI_VALUE */
#if !defined (HSI_VALUE)
#define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
#define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */
@ -115,8 +115,8 @@
/*!< Uncomment the following line if you need to relocate your vector Table in
Internal SRAM. */
/* #define VECT_TAB_SRAM */
#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
This value must be a multiple of 0x200. */
#define VECT_TAB_OFFSET 0x00U /*!< Vector Table base offset field.
This value must be a multiple of 0x100. */
/******************************************************************************/
/**
* @}
@ -146,8 +146,9 @@
variable is updated automatically.
*/
uint32_t SystemCoreClock = 32000000;
const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
const uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48};
const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U};
const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U};
const uint8_t PLLMulTable[9] = {3U, 4U, 6U, 8U, 12U, 16U, 24U, 32U, 48U};
/**
* @}
@ -179,25 +180,25 @@ uint8_t SetSysClock_PLL_HSI(void);
void SystemInit (void)
{
/*!< Set MSION bit */
RCC->CR |= (uint32_t)0x00000100;
RCC->CR |= (uint32_t)0x00000100U;
/*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */
RCC->CFGR &= (uint32_t) 0x88FF400C;
RCC->CFGR &= (uint32_t) 0x88FF400CU;
/*!< Reset HSION, HSIDIVEN, HSEON, CSSON and PLLON bits */
RCC->CR &= (uint32_t)0xFEF6FFF6;
RCC->CR &= (uint32_t)0xFEF6FFF6U;
/*!< Reset HSI48ON bit */
RCC->CRRCR &= (uint32_t)0xFFFFFFFE;
RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
/*!< Reset HSEBYP bit */
RCC->CR &= (uint32_t)0xFFFBFFFF;
RCC->CR &= (uint32_t)0xFFFBFFFFU;
/*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */
RCC->CFGR &= (uint32_t)0xFF02FFFF;
RCC->CFGR &= (uint32_t)0xFF02FFFFU;
/*!< Disable all interrupts */
RCC->CIER = 0x00000000;
RCC->CIER = 0x00000000U;
/* Configure the Vector Table location add offset address ------------------*/
#ifdef VECT_TAB_SRAM
@ -259,33 +260,33 @@ void SystemInit (void)
*/
void SystemCoreClockUpdate (void)
{
uint32_t tmp = 0, pllmul = 0, plldiv = 0, pllsource = 0, msirange = 0;
uint32_t tmp = 0U, pllmul = 0U, plldiv = 0U, pllsource = 0U, msirange = 0U;
/* Get SYSCLK source -------------------------------------------------------*/
tmp = RCC->CFGR & RCC_CFGR_SWS;
switch (tmp)
{
case 0x00: /* MSI used as system clock */
msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;
SystemCoreClock = (32768 * (1 << (msirange + 1)));
case 0x00U: /* MSI used as system clock */
msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13U;
SystemCoreClock = (32768U * (1U << (msirange + 1U)));
break;
case 0x04: /* HSI used as system clock */
case 0x04U: /* HSI used as system clock */
SystemCoreClock = HSI_VALUE;
break;
case 0x08: /* HSE used as system clock */
case 0x08U: /* HSE used as system clock */
SystemCoreClock = HSE_VALUE;
break;
case 0x0C: /* PLL used as system clock */
case 0x0CU: /* PLL used as system clock */
/* Get PLL clock source and multiplication factor ----------------------*/
pllmul = RCC->CFGR & RCC_CFGR_PLLMUL;
plldiv = RCC->CFGR & RCC_CFGR_PLLDIV;
pllmul = PLLMulTable[(pllmul >> 18)];
plldiv = (plldiv >> 22) + 1;
pllmul = PLLMulTable[(pllmul >> 18U)];
plldiv = (plldiv >> 22U) + 1U;
pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
if (pllsource == 0x00)
if (pllsource == 0x00U)
{
/* HSI oscillator clock selected as PLL clock entry */
SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv);
@ -297,13 +298,13 @@ void SystemCoreClockUpdate (void)
}
break;
default: /* MSI used as system clock */
msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;
SystemCoreClock = (32768 * (1 << (msirange + 1)));
msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13U;
SystemCoreClock = (32768U * (1U << (msirange + 1U)));
break;
}
/* Compute HCLK clock frequency --------------------------------------------*/
/* Get HCLK prescaler */
tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)];
/* HCLK clock frequency */
SystemCoreClock >>= tmp;
}

11
targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/device/system_stm32l0xx.h
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@ -2,13 +2,13 @@
******************************************************************************
* @file system_stm32l0xx.h
* @author MCD Application Team
* @version V1.5.0
* @date 8-January-2016
* @version V1.7.0
* @date 31-May-2016
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Header File.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -74,6 +74,11 @@
variable is updated automatically.
*/
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
/*
*/
extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */
extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */
extern const uint8_t PLLMulTable[9]; /*!< PLL multipiers table values */
/**
* @}

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targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/device/stm32l073xx.h
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30
targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/device/stm32l0xx.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx.h
* @author MCD Application Team
* @version V1.4.0
* @date 01-October-2015
* @version V1.7.0
* @date 31-May-2016
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
* This file contains all the peripheral register's definitions, bits
* definitions and memory mapping for STM32L0xx devices.
@ -12,8 +12,8 @@
* is using in the C source code, usually in main.c. This file contains:
* - Configuration section that allows to select:
* - The device used in the target application
* - To use or not the peripheral’s drivers in application code(i.e.
* code will be based on direct access to peripheral’s registers
* - To use or not the peripheral's drivers in application code(i.e.
* code will be based on direct access to peripheral's registers
* rather than drivers API), this option is controlled by
* "#define USE_HAL_DRIVER"
*
@ -95,7 +95,7 @@
/* #define STM32L063xx */ /*!< STM32L063C8, STM32L063R8 */
/* #define STM32L071xx */ /*!< */
/* #define STM32L072xx */ /*!< */
#define STM32L073xx /*!< STM32L073V8, STM32L073VB, STM32L073RB, STM32L073VZ, STM32L073RZ Devices */
#define STM32L073xx /*!< STM32L073V8, STM32L073VB, STM32L073RB, STM32L073VZ, STM32L073RZ Devices */
/* #define STM32L081xx */ /*!< */
/* #define STM32L082xx */ /*!< */
/* #define STM32L083xx */ /*!< */
@ -114,16 +114,16 @@
#endif /* USE_HAL_DRIVER */
/**
* @brief CMSIS Device version number V1.2.0RC1
* @brief CMSIS Device version number V1.7.0
*/
#define __STM32L0xx_CMSIS_DEVICE_VERSION_MAIN (0x01) /*!< [31:24] main version */
#define __STM32L0xx_CMSIS_DEVICE_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
#define __STM32L0xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32L0xx_CMSIS_DEVICE_VERSION_RC (0x01) /*!< [7:0] release candidate */
#define __STM32L0xx_CMSIS_DEVICE_VERSION ((__CMSIS_DEVICE_VERSION_MAIN << 24)\
|(__CMSIS_DEVICE_HAL_VERSION_SUB1 << 16)\
|(__CMSIS_DEVICE_HAL_VERSION_SUB2 << 8 )\
|(__CMSIS_DEVICE_HAL_VERSION_RC))
#define __STM32L0xx_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */
#define __STM32L0xx_CMSIS_VERSION_SUB1 (0x07) /*!< [23:16] sub1 version */
#define __STM32L0xx_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32L0xx_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32L0xx_CMSIS_VERSION ((__STM32L0xx_CMSIS_VERSION_MAIN << 24)\
|(__STM32L0xx_CMSIS_VERSION_SUB1 << 16)\
|(__STM32L0xx_CMSIS_VERSION_SUB2 << 8 )\
|(__STM32L0xx_CMSIS_VERSION_RC))
/**
* @}
@ -216,8 +216,6 @@ typedef enum
#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
/**
* @}
*/

34
targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/device/stm32l0xx_hal_conf.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx_hal_conf.h
* @author MCD Application Team
* @version V1.5.0
* @date 8-January-2016
* @version V1.7.0
* @date 31-May-2016
* @brief HAL configuration template file.
* This file should be copied to the application folder and renamed
* to stm32l0xx_hal_conf.h.
@ -90,7 +90,7 @@
* (when HSE is used as system clock source, directly or through the PLL).
*/
#if !defined (HSE_VALUE)
#define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
#define HSE_VALUE ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */
#endif /* HSE_VALUE */
#if !defined (HSE_STARTUP_TIMEOUT)
@ -102,7 +102,7 @@
* This value is the default MSI range value after Reset.
*/
#if !defined (MSI_VALUE)
#define MSI_VALUE ((uint32_t)2000000) /*!< Value of the Internal oscillator in Hz*/
#define MSI_VALUE ((uint32_t)2000000U) /*!< Value of the Internal oscillator in Hz*/
#endif /* MSI_VALUE */
/**
* @brief Internal High Speed oscillator (HSI) value.
@ -110,14 +110,14 @@
* (when HSI is used as system clock source, directly or through the PLL).
*/
#if !defined (HSI_VALUE)
#define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
#define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */
/**
* @brief Internal High Speed oscillator for USB (HSI48) value.
*/
#if !defined (HSI48_VALUE)
#define HSI48_VALUE ((uint32_t)48000000) /*!< Value of the Internal High Speed oscillator for USB in Hz.
#define HSI48_VALUE ((uint32_t)48000000U) /*!< Value of the Internal High Speed oscillator for USB in Hz.
The real value may vary depending on the variations
in voltage and temperature. */
#endif /* HSI48_VALUE */
@ -126,7 +126,7 @@
* @brief Internal Low Speed oscillator (LSI) value.
*/
#if !defined (LSI_VALUE)
#define LSI_VALUE ((uint32_t)37000) /*!< LSI Typical Value in Hz*/
#define LSI_VALUE ((uint32_t)37000U) /*!< LSI Typical Value in Hz*/
#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
The real value may vary depending on the variations
in voltage and temperature.*/
@ -135,12 +135,12 @@
* This value is used by the UART, RTC HAL module to compute the system frequency
*/
#if !defined (LSE_VALUE)
#define LSE_VALUE ((uint32_t)32768) /*!< Value of the External oscillator in Hz*/
#define LSE_VALUE ((uint32_t)32768U) /*!< Value of the External oscillator in Hz*/
#endif /* LSE_VALUE */
#if !defined (LSE_STARTUP_TIMEOUT)
#define LSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for LSE start up, in ms */
#define LSE_STARTUP_TIMEOUT ((uint32_t)5000U) /*!< Time out for LSE start up, in ms */
#endif /* HSE_STARTUP_TIMEOUT */
@ -151,12 +151,12 @@
/**
* @brief This is the HAL system configuration section
*/
#define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */
#define TICK_INT_PRIORITY (((uint32_t)1<<__NVIC_PRIO_BITS) - 1) /*!< tick interrupt priority */
#define USE_RTOS 0
#define PREFETCH_ENABLE 1
#define PREREAD_ENABLE 0
#define BUFFER_CACHE_DISABLE 0
#define VDD_VALUE ((uint32_t)3300U) /*!< Value of VDD in mv */
#define TICK_INT_PRIORITY (((uint32_t)1U<<__NVIC_PRIO_BITS) - 1U) /*!< tick interrupt priority */
#define USE_RTOS 0U
#define PREFETCH_ENABLE 1U
#define PREREAD_ENABLE 0U
#define BUFFER_CACHE_DISABLE 0U
/* ########################## Assert Selection ############################## */
/**
@ -296,11 +296,11 @@
* If expr is true, it returns no value.
* @retval None
*/
#define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
/* Exported functions ------------------------------------------------------- */
void assert_failed(uint8_t* file, uint32_t line);
#else
#define assert_param(expr) ((void)0)
#define assert_param(expr) ((void)0U)
#endif /* USE_FULL_ASSERT */
#ifdef __cplusplus

61
targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/device/system_stm32l0xx.c
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@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32l0xx.c
* @author MCD Application Team
* @version V1.5.0
* @date 8-January-2016
* @version V1.7.0
* @date 31-May-2016
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Source File.
*
* This file provides two functions and one global variable to be called from
@ -40,7 +40,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -83,15 +83,15 @@
#include "hal_tick.h"
#if !defined (HSE_VALUE)
#define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
#define HSE_VALUE ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */
#endif /* HSE_VALUE */
#if !defined (MSI_VALUE)
#define MSI_VALUE ((uint32_t)2000000) /*!< Value of the Internal oscillator in Hz*/
#define MSI_VALUE ((uint32_t)2000000U) /*!< Value of the Internal oscillator in Hz*/
#endif /* MSI_VALUE */
#if !defined (HSI_VALUE)
#define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
#define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */
@ -115,8 +115,8 @@
/*!< Uncomment the following line if you need to relocate your vector Table in
Internal SRAM. */
/* #define VECT_TAB_SRAM */
#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
This value must be a multiple of 0x200. */
#define VECT_TAB_OFFSET 0x00U /*!< Vector Table base offset field.
This value must be a multiple of 0x100. */
/******************************************************************************/
/**
* @}
@ -146,8 +146,9 @@
variable is updated automatically.
*/
uint32_t SystemCoreClock = 32000000;
const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
const uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48};
const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U};
const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U};
const uint8_t PLLMulTable[9] = {3U, 4U, 6U, 8U, 12U, 16U, 24U, 32U, 48U};
/**
* @}
@ -179,25 +180,25 @@ uint8_t SetSysClock_PLL_HSI(void);
void SystemInit (void)
{
/*!< Set MSION bit */
RCC->CR |= (uint32_t)0x00000100;
RCC->CR |= (uint32_t)0x00000100U;
/*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */
RCC->CFGR &= (uint32_t) 0x88FF400C;
RCC->CFGR &= (uint32_t) 0x88FF400CU;
/*!< Reset HSION, HSIDIVEN, HSEON, CSSON and PLLON bits */
RCC->CR &= (uint32_t)0xFEF6FFF6;
RCC->CR &= (uint32_t)0xFEF6FFF6U;
/*!< Reset HSI48ON bit */
RCC->CRRCR &= (uint32_t)0xFFFFFFFE;
RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
/*!< Reset HSEBYP bit */
RCC->CR &= (uint32_t)0xFFFBFFFF;
RCC->CR &= (uint32_t)0xFFFBFFFFU;
/*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */
RCC->CFGR &= (uint32_t)0xFF02FFFF;
RCC->CFGR &= (uint32_t)0xFF02FFFFU;
/*!< Disable all interrupts */
RCC->CIER = 0x00000000;
RCC->CIER = 0x00000000U;
/* Configure the Vector Table location add offset address ------------------*/
#ifdef VECT_TAB_SRAM
@ -259,33 +260,33 @@ void SystemInit (void)
*/
void SystemCoreClockUpdate (void)
{
uint32_t tmp = 0, pllmul = 0, plldiv = 0, pllsource = 0, msirange = 0;
uint32_t tmp = 0U, pllmul = 0U, plldiv = 0U, pllsource = 0U, msirange = 0U;
/* Get SYSCLK source -------------------------------------------------------*/
tmp = RCC->CFGR & RCC_CFGR_SWS;
switch (tmp)
{
case 0x00: /* MSI used as system clock */
msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;
SystemCoreClock = (32768 * (1 << (msirange + 1)));
case 0x00U: /* MSI used as system clock */
msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13U;
SystemCoreClock = (32768U * (1U << (msirange + 1U)));
break;
case 0x04: /* HSI used as system clock */
case 0x04U: /* HSI used as system clock */
SystemCoreClock = HSI_VALUE;
break;
case 0x08: /* HSE used as system clock */
case 0x08U: /* HSE used as system clock */
SystemCoreClock = HSE_VALUE;
break;
case 0x0C: /* PLL used as system clock */
case 0x0CU: /* PLL used as system clock */
/* Get PLL clock source and multiplication factor ----------------------*/
pllmul = RCC->CFGR & RCC_CFGR_PLLMUL;
plldiv = RCC->CFGR & RCC_CFGR_PLLDIV;
pllmul = PLLMulTable[(pllmul >> 18)];
plldiv = (plldiv >> 22) + 1;
pllmul = PLLMulTable[(pllmul >> 18U)];
plldiv = (plldiv >> 22U) + 1U;
pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
if (pllsource == 0x00)
if (pllsource == 0x00U)
{
/* HSI oscillator clock selected as PLL clock entry */
SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv);
@ -297,13 +298,13 @@ void SystemCoreClockUpdate (void)
}
break;
default: /* MSI used as system clock */
msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;
SystemCoreClock = (32768 * (1 << (msirange + 1)));
msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13U;
SystemCoreClock = (32768U * (1U << (msirange + 1U)));
break;
}
/* Compute HCLK clock frequency --------------------------------------------*/
/* Get HCLK prescaler */
tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)];
/* HCLK clock frequency */
SystemCoreClock >>= tmp;
}

11
targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/device/system_stm32l0xx.h
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@ -2,13 +2,13 @@
******************************************************************************
* @file system_stm32l0xx.h
* @author MCD Application Team
* @version V1.5.0
* @date 8-January-2016
* @version V1.7.0
* @date 31-May-2016
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Header File.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -74,6 +74,11 @@
variable is updated automatically.
*/
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
/*
*/
extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */
extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */
extern const uint8_t PLLMulTable[9]; /*!< PLL multipiers table values */
/**
* @}

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237
targets/TARGET_STM/TARGET_STM32L0/device/stm32_hal_legacy.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32_hal_legacy.h
* @author MCD Application Team
* @version V1.5.0
* @date 8-January-2016
* @version V1.7.0
* @date 31-May-2016
* @brief This file contains aliases definition for the STM32Cube HAL constants
* macros and functions maintained for legacy purpose.
******************************************************************************
@ -129,7 +129,6 @@
/** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose
* @{
*/
#define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE
#define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE
#define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1
@ -144,6 +143,72 @@
#define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1
#define COMP_OUTPUT_TIM3OCREFCLR COMP_OUTPUT_COMP1_TIM3OCREFCLR
#endif /* STM32F373xC || STM32F378xx */
#if defined(STM32L0) || defined(STM32L4)
#define COMP_WINDOWMODE_ENABLE COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON
#define COMP_NONINVERTINGINPUT_IO1 COMP_INPUT_PLUS_IO1
#define COMP_NONINVERTINGINPUT_IO2 COMP_INPUT_PLUS_IO2
#define COMP_NONINVERTINGINPUT_IO3 COMP_INPUT_PLUS_IO3
#define COMP_NONINVERTINGINPUT_IO4 COMP_INPUT_PLUS_IO4
#define COMP_NONINVERTINGINPUT_IO5 COMP_INPUT_PLUS_IO5
#define COMP_NONINVERTINGINPUT_IO6 COMP_INPUT_PLUS_IO6
#define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT
#define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT
#define COMP_INVERTINGINPUT_3_4VREFINT COMP_INPUT_MINUS_3_4VREFINT
#define COMP_INVERTINGINPUT_VREFINT COMP_INPUT_MINUS_VREFINT
#define COMP_INVERTINGINPUT_DAC1_CH1 COMP_INPUT_MINUS_DAC1_CH1
#define COMP_INVERTINGINPUT_DAC1_CH2 COMP_INPUT_MINUS_DAC1_CH2
#define COMP_INVERTINGINPUT_DAC1 COMP_INPUT_MINUS_DAC1_CH1
#define COMP_INVERTINGINPUT_DAC2 COMP_INPUT_MINUS_DAC1_CH2
#define COMP_INVERTINGINPUT_IO1 COMP_INPUT_MINUS_IO1
#if defined(STM32L0)
/* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2), */
/* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding */
/* to the second dedicated IO (only for COMP2). */
#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_DAC1_CH2
#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO2
#else
#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_IO2
#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO3
#endif
#define COMP_INVERTINGINPUT_IO4 COMP_INPUT_MINUS_IO4
#define COMP_INVERTINGINPUT_IO5 COMP_INPUT_MINUS_IO5
#define COMP_OUTPUTLEVEL_LOW COMP_OUTPUT_LEVEL_LOW
#define COMP_OUTPUTLEVEL_HIGH COMP_OUTPUT_LEVEL_HIGH
/* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose. */
/* To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()". */
#if defined(COMP_CSR_LOCK)
#define COMP_FLAG_LOCK COMP_CSR_LOCK
#elif defined(COMP_CSR_COMP1LOCK)
#define COMP_FLAG_LOCK COMP_CSR_COMP1LOCK
#elif defined(COMP_CSR_COMPxLOCK)
#define COMP_FLAG_LOCK COMP_CSR_COMPxLOCK
#endif
#if defined(STM32L4)
#define COMP_BLANKINGSRCE_TIM1OC5 COMP_BLANKINGSRC_TIM1_OC5_COMP1
#define COMP_BLANKINGSRCE_TIM2OC3 COMP_BLANKINGSRC_TIM2_OC3_COMP1
#define COMP_BLANKINGSRCE_TIM3OC3 COMP_BLANKINGSRC_TIM3_OC3_COMP1
#define COMP_BLANKINGSRCE_TIM3OC4 COMP_BLANKINGSRC_TIM3_OC4_COMP2
#define COMP_BLANKINGSRCE_TIM8OC5 COMP_BLANKINGSRC_TIM8_OC5_COMP2
#define COMP_BLANKINGSRCE_TIM15OC1 COMP_BLANKINGSRC_TIM15_OC1_COMP2
#endif
#if defined(STM32L0)
#define COMP_MODE_HIGHSPEED COMP_POWERMODE_MEDIUMSPEED
#define COMP_MODE_LOWSPEED COMP_POWERMODE_ULTRALOWPOWER
#else
#define COMP_MODE_HIGHSPEED COMP_POWERMODE_HIGHSPEED
#define COMP_MODE_MEDIUMSPEED COMP_POWERMODE_MEDIUMSPEED
#define COMP_MODE_LOWPOWER COMP_POWERMODE_LOWPOWER
#define COMP_MODE_ULTRALOWPOWER COMP_POWERMODE_ULTRALOWPOWER
#endif
#endif
/**
* @}
*/
@ -384,6 +449,7 @@
#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH
#endif /* STM32F0 || STM32F3 || STM32F1 */
#define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1
/**
* @}
*/
@ -424,7 +490,7 @@
#define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE
#define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE
#define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE
#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0)
#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7)
#define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX
#define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX
#define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX
@ -488,6 +554,11 @@
/** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose
* @{
*/
#define HAL_NAND_Read_Page HAL_NAND_Read_Page_8b
#define HAL_NAND_Write_Page HAL_NAND_Write_Page_8b
#define HAL_NAND_Read_SpareArea HAL_NAND_Read_SpareArea_8b
#define HAL_NAND_Write_SpareArea HAL_NAND_Write_SpareArea_8b
#define NAND_AddressTypedef NAND_AddressTypeDef
#define __ARRAY_ADDRESS ARRAY_ADDRESS
@ -551,6 +622,9 @@
* @{
*/
#define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS
#if defined(STM32F7)
#define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL
#endif
/**
* @}
*/
@ -646,7 +720,7 @@
*/
/** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose
/** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose
* @{
*/
#define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE
@ -664,7 +738,7 @@
* @}
*/
/** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose
/** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose
* @{
*/
#define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE
@ -848,11 +922,82 @@
#define ETH_MMCTGFCR ((uint32_t)0x00000168U)
#define ETH_MMCRFCECR ((uint32_t)0x00000194U)
#define ETH_MMCRFAECR ((uint32_t)0x00000198U)
#define ETH_MMCRGUFCR ((uint32_t)0x000001C4U)
#define ETH_MMCRGUFCR ((uint32_t)0x000001C4U)
#define ETH_MAC_TXFIFO_FULL ((uint32_t)0x02000000) /* Tx FIFO full */
#define ETH_MAC_TXFIFONOT_EMPTY ((uint32_t)0x01000000) /* Tx FIFO not empty */
#define ETH_MAC_TXFIFO_WRITE_ACTIVE ((uint32_t)0x00400000) /* Tx FIFO write active */
#define ETH_MAC_TXFIFO_IDLE ((uint32_t)0x00000000) /* Tx FIFO read status: Idle */
#define ETH_MAC_TXFIFO_READ ((uint32_t)0x00100000) /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
#define ETH_MAC_TXFIFO_WAITING ((uint32_t)0x00200000) /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
#define ETH_MAC_TXFIFO_WRITING ((uint32_t)0x00300000) /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
#define ETH_MAC_TRANSMISSION_PAUSE ((uint32_t)0x00080000) /* MAC transmitter in pause */
#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE ((uint32_t)0x00000000) /* MAC transmit frame controller: Idle */
#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING ((uint32_t)0x00020000) /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF ((uint32_t)0x00040000) /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING ((uint32_t)0x00060000) /* MAC transmit frame controller: Transferring input frame for transmission */
#define ETH_MAC_MII_TRANSMIT_ACTIVE ((uint32_t)0x00010000) /* MAC MII transmit engine active */
#define ETH_MAC_RXFIFO_EMPTY ((uint32_t)0x00000000) /* Rx FIFO fill level: empty */
#define ETH_MAC_RXFIFO_BELOW_THRESHOLD ((uint32_t)0x00000100) /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD ((uint32_t)0x00000200) /* Rx FIFO fill level: fill-level above flow-control activate threshold */
#define ETH_MAC_RXFIFO_FULL ((uint32_t)0x00000300) /* Rx FIFO fill level: full */
#define ETH_MAC_READCONTROLLER_IDLE ((uint32_t)0x00000000) /* Rx FIFO read controller IDLE state */
#define ETH_MAC_READCONTROLLER_READING_DATA ((uint32_t)0x00000020) /* Rx FIFO read controller Reading frame data */
#define ETH_MAC_READCONTROLLER_READING_STATUS ((uint32_t)0x00000040) /* Rx FIFO read controller Reading frame status (or time-stamp) */
#define ETH_MAC_READCONTROLLER_FLUSHING ((uint32_t)0x00000060) /* Rx FIFO read controller Flushing the frame data and status */
#define ETH_MAC_RXFIFO_WRITE_ACTIVE ((uint32_t)0x00000010) /* Rx FIFO write controller active */
#define ETH_MAC_SMALL_FIFO_NOTACTIVE ((uint32_t)0x00000000) /* MAC small FIFO read / write controllers not active */
#define ETH_MAC_SMALL_FIFO_READ_ACTIVE ((uint32_t)0x00000002) /* MAC small FIFO read controller active */
#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE ((uint32_t)0x00000004) /* MAC small FIFO write controller active */
#define ETH_MAC_SMALL_FIFO_RW_ACTIVE ((uint32_t)0x00000006) /* MAC small FIFO read / write controllers active */
#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE ((uint32_t)0x00000001) /* MAC MII receive protocol engine active */
/**
* @}
*/
/** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose
* @{
*/
#define HAL_DCMI_ERROR_OVF HAL_DCMI_ERROR_OVR
#define DCMI_IT_OVF DCMI_IT_OVR
#define DCMI_FLAG_OVFRI DCMI_FLAG_OVRRI
#define DCMI_FLAG_OVFMI DCMI_FLAG_OVRMI
#define HAL_DCMI_ConfigCROP HAL_DCMI_ConfigCrop
#define HAL_DCMI_EnableCROP HAL_DCMI_EnableCrop
#define HAL_DCMI_DisableCROP HAL_DCMI_DisableCrop
/**
* @}
*/
#if defined(STM32L4xx) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) ||\
defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
/** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose
* @{
*/
#define DMA2D_ARGB8888 DMA2D_OUTPUT_ARGB8888
#define DMA2D_RGB888 DMA2D_OUTPUT_RGB888
#define DMA2D_RGB565 DMA2D_OUTPUT_RGB565
#define DMA2D_ARGB1555 DMA2D_OUTPUT_ARGB1555
#define DMA2D_ARGB4444 DMA2D_OUTPUT_ARGB4444
#define CM_ARGB8888 DMA2D_INPUT_ARGB8888
#define CM_RGB888 DMA2D_INPUT_RGB888
#define CM_RGB565 DMA2D_INPUT_RGB565
#define CM_ARGB1555 DMA2D_INPUT_ARGB1555
#define CM_ARGB4444 DMA2D_INPUT_ARGB4444
#define CM_L8 DMA2D_INPUT_L8
#define CM_AL44 DMA2D_INPUT_AL44
#define CM_AL88 DMA2D_INPUT_AL88
#define CM_L4 DMA2D_INPUT_L4
#define CM_A8 DMA2D_INPUT_A8
#define CM_A4 DMA2D_INPUT_A4
/**
* @}
*/
#endif /* STM32L4xx || STM32F7*/
/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose
* @{
@ -910,7 +1055,10 @@
#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
#define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect
#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())
#if defined(STM32L0)
#else
#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT())
#endif
#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
/**
@ -935,8 +1083,10 @@
/** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose
* @{
*/
#define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter
#define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter
#define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter
#define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter
#define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter
#define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter
#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
/**
@ -1037,7 +1187,7 @@
*/
/** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose
/** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose
* @{
*/
@ -1412,10 +1562,28 @@
#define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE
#if defined(STM32L0) || defined(STM32L4)
/* Note: On these STM32 families, the only argument of this macro */
/* is COMP_FLAG_LOCK. */
/* This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle */
/* argument. */
#define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_COMP_IS_LOCKED(__HANDLE__))
#endif
/**
* @}
*/
#if defined(STM32L0) || defined(STM32L4)
/** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose
* @{
*/
#define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
#define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
/**
* @}
*/
#endif
/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
* @{
*/
@ -2459,7 +2627,7 @@
#endif
#if defined(STM32F7)
#define RCC_SDIOCLKSOURCE_CK48 RCC_SDMMC1CLKSOURCE_CLK48
#define RCC_SDIOCLKSOURCE_CLK48 RCC_SDMMC1CLKSOURCE_CLK48
#define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK
#endif
@ -2573,6 +2741,34 @@
#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE __HAL_RCC_CRS_RELOADVALUE_CALCULATE
#define __HAL_RCC_GET_IT_SOURCE __HAL_RCC_GET_IT
#define RCC_CRS_SYNCWARM RCC_CRS_SYNCWARN
#define RCC_CRS_TRIMOV RCC_CRS_TRIMOVF
#define RCC_PERIPHCLK_CK48 RCC_PERIPHCLK_CLK48
#define RCC_CK48CLKSOURCE_PLLQ RCC_CLK48CLKSOURCE_PLLQ
#define RCC_CK48CLKSOURCE_PLLSAIP RCC_CLK48CLKSOURCE_PLLSAIP
#define RCC_CK48CLKSOURCE_PLLI2SQ RCC_CLK48CLKSOURCE_PLLI2SQ
#define IS_RCC_CK48CLKSOURCE IS_RCC_CLK48CLKSOURCE
#define RCC_SDIOCLKSOURCE_CK48 RCC_SDIOCLKSOURCE_CLK48
#define __HAL_RCC_DFSDM_CLK_ENABLE __HAL_RCC_DFSDM1_CLK_ENABLE
#define __HAL_RCC_DFSDM_CLK_DISABLE __HAL_RCC_DFSDM1_CLK_DISABLE
#define __HAL_RCC_DFSDM_IS_CLK_ENABLED __HAL_RCC_DFSDM1_IS_CLK_ENABLED
#define __HAL_RCC_DFSDM_IS_CLK_DISABLED __HAL_RCC_DFSDM1_IS_CLK_DISABLED
#define __HAL_RCC_DFSDM_FORCE_RESET __HAL_RCC_DFSDM1_FORCE_RESET
#define __HAL_RCC_DFSDM_RELEASE_RESET __HAL_RCC_DFSDM1_RELEASE_RESET
#define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE
#define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE
#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED
#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED
#define DfsdmClockSelection Dfsdm1ClockSelection
#define RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1
#define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK
#define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK
#define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG
#define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE
/**
* @}
*/
@ -2861,6 +3057,8 @@
#define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER
#define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE
#define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE
#define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1
/**
* @}
*/
@ -2900,14 +3098,15 @@
#define SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE
#define SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE
#define SAI_STREOMODE SAI_STEREOMODE
#define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY
#define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL
#define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL
#define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL
#define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL
#define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL
#define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE
#define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY
#define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL
#define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL
#define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL
#define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL
#define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL
#define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE
#define SAI_SYNCHRONOUS_EXT SAI_SYNCHRONOUS_EXT_SAI1
#define SAI_SYNCEXT_IN_ENABLE SAI_SYNCEXT_OUTBLOCKA_ENABLE
/**
* @}
*/

64
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx_hal.c
* @author MCD Application Team
* @version V1.5.0
* @date 8-January-2016
* @version V1.7.0
* @date 31-May-2016
* @brief HAL module driver.
* This is the common part of the HAL initialization
*
@ -68,23 +68,36 @@
* @{
*/
/** @defgroup SysTick System Tick
* @{
*/
/**
* @brief uwTick_variable uwTick variable
*/
__IO uint32_t uwTick;
/**
* @}
*/
/** @defgroup HAL_Version HAL Version
* @{
*/
/**
* @brief STM32L0xx HAL Driver version number V1.5.0
* @brief STM32L0xx HAL Driver version number V1.7.0
*/
#define __STM32L0xx_HAL_VERSION_MAIN (0x01) /*!< [31:24] main version */
#define __STM32L0xx_HAL_VERSION_SUB1 (0x05) /*!< [23:16] sub1 version */
#define __STM32L0xx_HAL_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32L0xx_HAL_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32L0xx_HAL_VERSION ((__STM32L0xx_HAL_VERSION_MAIN << 24)\
|(__STM32L0xx_HAL_VERSION_SUB1 << 16)\
|(__STM32L0xx_HAL_VERSION_SUB2 << 8 )\
#define __STM32L0xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */
#define __STM32L0xx_HAL_VERSION_SUB1 (0x07U) /*!< [23:16] sub1 version */
#define __STM32L0xx_HAL_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */
#define __STM32L0xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __STM32L0xx_HAL_VERSION ((__STM32L0xx_HAL_VERSION_MAIN << 24U)\
|(__STM32L0xx_HAL_VERSION_SUB1 << 16U)\
|(__STM32L0xx_HAL_VERSION_SUB2 << 8U )\
|(__STM32L0xx_HAL_VERSION_RC))
#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF)
#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFFU)
/**
* @}
@ -96,7 +109,7 @@
/** @defgroup HAL_Private HAL Private
* @{
*/
static __IO uint32_t uwTick;
/**
* @}
@ -247,10 +260,10 @@ __weak void HAL_MspDeInit(void)
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
/*Configure the SysTick to have interrupt in 1ms time basis*/
HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq()/1000);
HAL_SYSTICK_Config(SystemCoreClock/1000U);
/*Configure the SysTick IRQ priority */
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority ,0);
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority ,0U);
/* Return function status */
return HAL_OK;
@ -319,7 +332,7 @@ __weak uint32_t HAL_GetTick(void)
*/
__weak void HAL_Delay(__IO uint32_t Delay)
{
uint32_t tickstart = 0;
uint32_t tickstart = 0U;
tickstart = HAL_GetTick();
while((HAL_GetTick() - tickstart) < Delay)
{
@ -373,7 +386,7 @@ uint32_t HAL_GetHalVersion(void)
*/
uint32_t HAL_GetREVID(void)
{
return((DBGMCU->IDCODE) >> 16);
return((DBGMCU->IDCODE) >> 16U);
}
/**
@ -487,25 +500,6 @@ uint32_t HAL_SYSCFG_GetBootMode(void)
return (SYSCFG->CFGR1 & SYSCFG_CFGR1_BOOT_MODE);
}
/**
* @brief Enables the VREFINT.
* @retval None
*/
void HAL_SYSCFG_EnableVREFINT(void)
{
/* Enable the VREFINT by setting EN_VREFINT bit in the CFGR3 register */
SET_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_EN_VREFINT);
}
/**
* @brief Disables the VREFINT.
* @retval None
*/
void HAL_SYSCFG_DisableVREFINT(void)
{
/* Disable the VREFINT by setting EN_VREFINT bit in the CFGR3 register */
CLEAR_BIT(SYSCFG->CFGR3,SYSCFG_CFGR3_EN_VREFINT);
}
/**
* @brief Selects the output of internal reference voltage (VREFINT).
* The VREFINT output can be routed to(PB0) or

46
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx_hal.h
* @author MCD Application Team
* @version V1.5.0
* @date 8-January-2016
* @version V1.7.0
* @date 31-May-2016
* @brief This file contains all the functions prototypes for the HAL
* module driver.
******************************************************************************
@ -61,7 +61,7 @@
/** @defgroup SYSCFG_BootMode Boot Mode
* @{
*/
#define SYSCFG_BOOT_MAINFLASH ((uint32_t)0x00000000)
#define SYSCFG_BOOT_MAINFLASH ((uint32_t)0x00000000U)
#define SYSCFG_BOOT_SYSTEMFLASH ((uint32_t)SYSCFG_CFGR1_BOOT_MODE_0)
#define SYSCFG_BOOT_SRAM ((uint32_t)SYSCFG_CFGR1_BOOT_MODE)
@ -75,7 +75,7 @@
#define DBGMCU_SLEEP DBGMCU_CR_DBG_SLEEP
#define DBGMCU_STOP DBGMCU_CR_DBG_STOP
#define DBGMCU_STANDBY DBGMCU_CR_DBG_STANDBY
#define IS_DBGMCU_PERIPH(__PERIPH__) ((((__PERIPH__) & (~(DBGMCU_CR_DBG))) == 0x00) && ((__PERIPH__) != 0x00))
#define IS_DBGMCU_PERIPH(__PERIPH__) ((((__PERIPH__) & (~(DBGMCU_CR_DBG))) == 0x00U) && ((__PERIPH__) != 0x00U))
/**
@ -89,9 +89,9 @@
#define SYSCFG_LCD_EXT_CAPA SYSCFG_CFGR2_CAPA /*!< Connection of internal Vlcd rail to external capacitors */
#define SYSCFG_VLCD_PB2_EXT_CAPA_ON SYSCFG_CFGR2_CAPA_0 /*!< Connection on PB2 */
#define SYSCFG_VLCD_PB12_EXT_CAPA_ON SYSCFG_CFGR2_CAPA_1 /*!< Connection on PB12 */
#define SYSCFG_VLCD_PE11_EXT_CAPA_ON SYSCFG_CFGR2_CAPA_2 /*!< Connection on PB0 */
#define SYSCFG_VLCD_PB0_EXT_CAPA_ON SYSCFG_CFGR2_CAPA_2 /*!< Connection on PB0 */
#if defined (SYSCFG_CFGR2_CAPA_3)
#define SYSCFG_VLCD_PB0_EXT_CAPA_ON SYSCFG_CFGR2_CAPA_3 /*!< Connection on PE11 */
#define SYSCFG_VLCD_PE11_EXT_CAPA_ON SYSCFG_CFGR2_CAPA_3 /*!< Connection on PE11 */
#endif
#if defined (SYSCFG_CFGR2_CAPA_4)
#define SYSCFG_VLCD_PE12_EXT_CAPA_ON SYSCFG_CFGR2_CAPA_4 /*!< Connection on PE12 */
@ -105,7 +105,7 @@
/** @defgroup SYSCFG_VREFINT_OUT_SELECT SYSCFG VREFINT Out Selection
* @{
*/
#define SYSCFG_VREFINT_OUT_NONE ((uint32_t)0x00000000) /* no pad connected */
#define SYSCFG_VREFINT_OUT_NONE ((uint32_t)0x00000000U) /* no pad connected */
#define SYSCFG_VREFINT_OUT_PB0 SYSCFG_CFGR3_VREF_OUT_0 /* Selects PBO as output for the Vrefint */
#define SYSCFG_VREFINT_OUT_PB1 SYSCFG_CFGR3_VREF_OUT_1 /* Selects PB1 as output for the Vrefint */
#define SYSCFG_VREFINT_OUT_PB0_PB1 SYSCFG_CFGR3_VREF_OUT /* Selects PBO and PB1 as output for the Vrefint */
@ -291,6 +291,36 @@
#define __HAL_SYSCFG_DBG_LP_CONFIG(__DBGLPMODE__) do {assert_param(IS_DBGMCU_PERIPH(__DBGLPMODE__)); \
MODIFY_REG(DBGMCU->CR, DBGMCU_CR_DBG, (__DBGLPMODE__)); \
} while (0)
#if defined (LCD_BASE) /* STM32L0x3xx only */
/** @brief Macro to configure the VLCD Decoupling capacitance connection.
*
* @param __SYSCFG_VLCD_CAPA__: specifies the decoupling of LCD capacitance for rails connection on GPIO.
* This parameter can be a combination of following values (when available):
* @arg SYSCFG_VLCD_PB2_EXT_CAPA_ON: Connection on PB2
* @arg SYSCFG_VLCD_PB12_EXT_CAPA_ON: Connection on PB12
* @arg SYSCFG_VLCD_PB0_EXT_CAPA_ON: Connection on PB0
* @arg SYSCFG_VLCD_PE11_EXT_CAPA_ON: Connection on PE11
* @arg SYSCFG_VLCD_PE12_EXT_CAPA_ON: Connection on PE12
* @retval None
*/
#define __HAL_SYSCFG_VLCD_CAPA_CONFIG(__SYSCFG_VLCD_CAPA__) \
MODIFY_REG(SYSCFG->CFGR2, SYSCFG_LCD_EXT_CAPA, (uint32_t)(__SYSCFG_VLCD_CAPA__))
/**
* @brief Returns the decoupling of LCD capacitance configured by user.
* @retval The LCD capacitance connection as configured by user. The returned can be a combination of :
* SYSCFG_VLCD_PB2_EXT_CAPA_ON: Connection on PB2
* SYSCFG_VLCD_PB12_EXT_CAPA_ON: Connection on PB12
* SYSCFG_VLCD_PB0_EXT_CAPA_ON: Connection on PB0
* SYSCFG_VLCD_PE11_EXT_CAPA_ON: Connection on PE11
* SYSCFG_VLCD_PE12_EXT_CAPA_ON: Connection on PE12
*/
#define __HAL_SYSCFG_GET_VLCD_CAPA_CONFIG() READ_BIT(SYSCFG->CFGR2, SYSCFG_LCD_EXT_CAPA)
#endif
/**
* @brief Returns the boot mode as configured by user.
* @retval The boot mode as configured by user. The returned can be a value of :
@ -372,8 +402,6 @@ void HAL_DBGMCU_DisableDBGStandbyMode(void);
void HAL_DBGMCU_DBG_EnableLowPowerConfig(uint32_t Periph);
void HAL_DBGMCU_DBG_DisableLowPowerConfig(uint32_t Periph);
uint32_t HAL_SYSCFG_GetBootMode(void);
void HAL_SYSCFG_EnableVREFINT(void);
void HAL_SYSCFG_DisableVREFINT(void);
void HAL_SYSCFG_Enable_Lock_VREFINT(void);
void HAL_SYSCFG_Disable_Lock_VREFINT(void);
void HAL_SYSCFG_VREFINT_OutputSelect(uint32_t SYSCFG_Vrefint_OUTPUT);

36
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_adc.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx_hal_adc.c
* @author MCD Application Team
* @version V1.5.0
* @date 8-January-2016
* @version V1.7.0
* @date 31-May-2016
* @brief This file provides firmware functions to manage the following
* functionalities of the Analog to Digital Convertor (ADC)
* peripheral:
@ -283,12 +283,12 @@
/* Delay for ADC stabilization time. */
/* Maximum delay is 1us (refer to device datasheet, parameter tSTART). */
/* Unit: us */
#define ADC_STAB_DELAY_US ((uint32_t) 1)
#define ADC_STAB_DELAY_US ((uint32_t) 1U)
/* Delay for temperature sensor stabilization time. */
/* Maximum delay is 10us (refer to device datasheet, parameter tSTART). */
/* Unit: us */
#define ADC_TEMPSENSOR_DELAY_US ((uint32_t) 10)
#define ADC_TEMPSENSOR_DELAY_US ((uint32_t) 10U)
/**
* @}
*/
@ -374,12 +374,12 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
assert_param(IS_ADC_SAMPLE_TIME(hadc->Init.SamplingTime));
assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode));
assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign));
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode));
assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv));
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));
assert_param(IS_ADC_OVERRUN(hadc->Init.Overrun));
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));
assert_param(IS_ADC_OVERRUN(hadc->Init.Overrun));
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoWait));
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerFrequencyMode));
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoPowerOff));
@ -581,7 +581,7 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
* @note For devices with several ADCs: reset of ADC common registers is done
* only if all ADCs sharing the same common group are disabled.
* If this is not the case, reset of these common parameters reset is
* bypassed without error reporting: it can be the intended behaviour in
* bypassed without error reporting: it can be the intended behavior in
* case of reset of a single ADC while the other ADCs sharing the same
* common group is still running.
* @param hadc: ADC handle
@ -934,7 +934,7 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Ti
/* Check if timeout is disabled (set to infinite wait) */
if(Timeout != HAL_MAX_DELAY)
{
if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
{
/* Update ADC state machine to timeout */
SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
@ -1009,7 +1009,7 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Ti
*/
HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout)
{
uint32_t tickstart = 0;
uint32_t tickstart = 0U;
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
@ -1024,7 +1024,7 @@ HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventTy
/* Check if timeout is disabled (set to infinite wait) */
if(Timeout != HAL_MAX_DELAY)
{
if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
{
/* Update ADC state machine to timeout */
SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
@ -1578,7 +1578,7 @@ __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
*/
/** @addtogroup ADC_Exported_Functions_Group3
* @brief Peripheral Control functions
* @brief Peripheral Control functions
*
@verbatim
===============================================================================
@ -1722,7 +1722,7 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf
* "ADC_AnalogWDGConfTypeDef".
* @param hadc: ADC handle
* @param AnalogWDGConfig: Structure of ADC analog watchdog configuration
* @retval HAL status
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig)
{
@ -1882,7 +1882,7 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc)
*/
static HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc)
{
uint32_t tickstart = 0;
uint32_t tickstart = 0U;
/* ADC enable and wait for ADC ready (in case of ADC is disabled or */
/* enabling phase not yet completed: flag ADC ready not yet set). */
@ -1941,7 +1941,7 @@ static HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc)
*/
static HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc)
{
uint32_t tickstart = 0;
uint32_t tickstart = 0U;
/* Verification if ADC is not already disabled: */
/* Note: forbidden to disable ADC (set bit ADC_CR_ADDIS) if ADC is already */
@ -1997,7 +1997,7 @@ static HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc)
*/
static HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc)
{
uint32_t tickstart = 0;
uint32_t tickstart = 0U;
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
@ -2143,9 +2143,9 @@ static void ADC_DMAError(DMA_HandleTypeDef *hdma)
static void ADC_DelayMicroSecond(uint32_t microSecond)
{
/* Compute number of CPU cycles to wait for */
__IO uint32_t waitLoopIndex = (microSecond * (SystemCoreClock / 1000000));
__IO uint32_t waitLoopIndex = (microSecond * (SystemCoreClock / 1000000U));
while(waitLoopIndex != 0)
while(waitLoopIndex != 0U)
{
waitLoopIndex--;
}

154
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_adc.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx_hal_adc.h
* @author MCD Application Team
* @version V1.5.0
* @date 8-January-2016
* @version V1.7.0
* @date 31-May-2016
* @brief This file contains all the functions prototypes for the ADC firmware
* library.
******************************************************************************
@ -64,36 +64,36 @@
* @brief HAL ADC state machine: ADC states definition (bitfields)
*/
/* States of ADC global scope */
#define HAL_ADC_STATE_RESET ((uint32_t)0x00000000) /*!< ADC not yet initialized or disabled */
#define HAL_ADC_STATE_READY ((uint32_t)0x00000001) /*!< ADC peripheral ready for use */
#define HAL_ADC_STATE_BUSY_INTERNAL ((uint32_t)0x00000002) /*!< ADC is busy to internal process (initialization, calibration) */
#define HAL_ADC_STATE_TIMEOUT ((uint32_t)0x00000004) /*!< TimeOut occurrence */
#define HAL_ADC_STATE_RESET ((uint32_t)0x00000000U) /*!< ADC not yet initialized or disabled */
#define HAL_ADC_STATE_READY ((uint32_t)0x00000001U) /*!< ADC peripheral ready for use */
#define HAL_ADC_STATE_BUSY_INTERNAL ((uint32_t)0x00000002U) /*!< ADC is busy to internal process (initialization, calibration) */
#define HAL_ADC_STATE_TIMEOUT ((uint32_t)0x00000004U) /*!< TimeOut occurrence */
/* States of ADC errors */
#define HAL_ADC_STATE_ERROR_INTERNAL ((uint32_t)0x00000010) /*!< Internal error occurrence */
#define HAL_ADC_STATE_ERROR_CONFIG ((uint32_t)0x00000020) /*!< Configuration error occurrence */
#define HAL_ADC_STATE_ERROR_DMA ((uint32_t)0x00000040) /*!< DMA error occurrence */
#define HAL_ADC_STATE_ERROR_INTERNAL ((uint32_t)0x00000010U) /*!< Internal error occurrence */
#define HAL_ADC_STATE_ERROR_CONFIG ((uint32_t)0x00000020U) /*!< Configuration error occurrence */
#define HAL_ADC_STATE_ERROR_DMA ((uint32_t)0x00000040U) /*!< DMA error occurrence */
/* States of ADC group regular */
#define HAL_ADC_STATE_REG_BUSY ((uint32_t)0x00000100) /*!< A conversion on group regular is ongoing or can occur (either by continuous mode,
#define HAL_ADC_STATE_REG_BUSY ((uint32_t)0x00000100U) /*!< A conversion on group regular is ongoing or can occur (either by continuous mode,
external trigger, low power auto power-on, multimode ADC master control) */
#define HAL_ADC_STATE_REG_EOC ((uint32_t)0x00000200) /*!< Conversion data available on group regular */
#define HAL_ADC_STATE_REG_OVR ((uint32_t)0x00000400) /*!< Overrun occurrence */
#define HAL_ADC_STATE_REG_EOSMP ((uint32_t)0x00000800) /*!< Not available on STM32F0 device: End Of Sampling flag raised */
#define HAL_ADC_STATE_REG_EOC ((uint32_t)0x00000200U) /*!< Conversion data available on group regular */
#define HAL_ADC_STATE_REG_OVR ((uint32_t)0x00000400U) /*!< Overrun occurrence */
#define HAL_ADC_STATE_REG_EOSMP ((uint32_t)0x00000800U) /*!< Not available on STM32F0 device: End Of Sampling flag raised */
/* States of ADC group injected */
#define HAL_ADC_STATE_INJ_BUSY ((uint32_t)0x00001000) /*!< Not available on STM32F0 device: A conversion on group injected is ongoing or can occur (either by auto-injection mode,
#define HAL_ADC_STATE_INJ_BUSY ((uint32_t)0x00001000U) /*!< Not available on STM32F0 device: A conversion on group injected is ongoing or can occur (either by auto-injection mode,
external trigger, low power auto power-on, multimode ADC master control) */
#define HAL_ADC_STATE_INJ_EOC ((uint32_t)0x00002000) /*!< Not available on STM32F0 device: Conversion data available on group injected */
#define HAL_ADC_STATE_INJ_JQOVF ((uint32_t)0x00004000) /*!< Not available on STM32F0 device: Not available on STM32F0 device: Injected queue overflow occurrence */
#define HAL_ADC_STATE_INJ_EOC ((uint32_t)0x00002000U) /*!< Not available on STM32F0 device: Conversion data available on group injected */
#define HAL_ADC_STATE_INJ_JQOVF ((uint32_t)0x00004000U) /*!< Not available on STM32F0 device: Not available on STM32F0 device: Injected queue overflow occurrence */
/* States of ADC analog watchdogs */
#define HAL_ADC_STATE_AWD1 ((uint32_t)0x00010000) /*!< Out-of-window occurrence of analog watchdog 1 */
#define HAL_ADC_STATE_AWD2 ((uint32_t)0x00020000) /*!< Not available on STM32F0 device: Out-of-window occurrence of analog watchdog 2 */
#define HAL_ADC_STATE_AWD3 ((uint32_t)0x00040000) /*!< Not available on STM32F0 device: Out-of-window occurrence of analog watchdog 3 */
#define HAL_ADC_STATE_AWD1 ((uint32_t)0x00010000U) /*!< Out-of-window occurrence of analog watchdog 1 */
#define HAL_ADC_STATE_AWD2 ((uint32_t)0x00020000U) /*!< Not available on STM32F0 device: Out-of-window occurrence of analog watchdog 2 */
#define HAL_ADC_STATE_AWD3 ((uint32_t)0x00040000U) /*!< Not available on STM32F0 device: Out-of-window occurrence of analog watchdog 3 */
/* States of ADC multi-mode */
#define HAL_ADC_STATE_MULTIMODE_SLAVE ((uint32_t)0x00100000) /*!< Not available on STM32F0 device: ADC in multimode slave state, controlled by another ADC master ( */
#define HAL_ADC_STATE_MULTIMODE_SLAVE ((uint32_t)0x00100000U) /*!< Not available on STM32F0 device: ADC in multimode slave state, controlled by another ADC master ( */
/**
@ -114,7 +114,7 @@ typedef struct
* @brief ADC Init structure definition
* @note The setting of these parameters with function HAL_ADC_Init() is conditioned by the ADC state.
* If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
* without error reporting (as it can be the expected behaviour in case of intended action to update antother parameter (which fullfills the ADC state condition) on the fly).
* without error reporting (as it can be the expected behavior in case of intended action to update antother parameter (which fullfills the ADC state condition) on the fly).
*/
typedef struct
{
@ -255,11 +255,11 @@ typedef struct
/** @defgroup ADC_Error_Code ADC Error Code
* @{
*/
#define HAL_ADC_ERROR_NONE ((uint32_t)0x00) /*!< No error */
#define HAL_ADC_ERROR_INTERNAL ((uint32_t)0x01) /*!< ADC IP internal error: if problem of clocking,
enable/disable, erroneous state */
#define HAL_ADC_ERROR_OVR ((uint32_t)0x02) /*!< OVR error */
#define HAL_ADC_ERROR_DMA ((uint32_t)0x04) /*!< DMA transfer error */
#define HAL_ADC_ERROR_NONE ((uint32_t)0x00U) /*!< No error */
#define HAL_ADC_ERROR_INTERNAL ((uint32_t)0x01U) /*!< ADC IP internal error: if problem of clocking,
enable/disable, erroneous state */
#define HAL_ADC_ERROR_OVR ((uint32_t)0x02U) /*!< OVR error */
#define HAL_ADC_ERROR_DMA ((uint32_t)0x04U) /*!< DMA transfer error */
/**
* @}
*/
@ -273,13 +273,13 @@ typedef struct
/* Values defined to be higher than worst cases: low clocks freq, */
/* maximum prescalers. */
/* Unit: ms */
#define ADC_ENABLE_TIMEOUT 10
#define ADC_DISABLE_TIMEOUT 10
#define ADC_STOP_CONVERSION_TIMEOUT 10
#define ADC_ENABLE_TIMEOUT 10U
#define ADC_DISABLE_TIMEOUT 10U
#define ADC_STOP_CONVERSION_TIMEOUT 10U
/* Delay of 10us fixed to worst case: maximum CPU frequency 180MHz to have */
/* the minimum number of CPU cycles to fulfill this delay */
#define ADC_DELAY_10US_MIN_CPU_CYCLES 1800
#define ADC_DELAY_10US_MIN_CPU_CYCLES 1800U
/**
* @}
*/
@ -287,7 +287,7 @@ typedef struct
/** @defgroup ADC_ClockPrescaler ADC Clock Prescaler
* @{
*/
#define ADC_CLOCK_ASYNC_DIV1 ((uint32_t)0x00000000) /*!< ADC Asynchronous clock mode divided by 1 */
#define ADC_CLOCK_ASYNC_DIV1 ((uint32_t)0x00000000U) /*!< ADC Asynchronous clock mode divided by 1 */
#define ADC_CLOCK_ASYNC_DIV2 (ADC_CCR_PRESC_0) /*!< ADC Asynchronous clock mode divided by 2 */
#define ADC_CLOCK_ASYNC_DIV4 (ADC_CCR_PRESC_1) /*!< ADC Asynchronous clock mode divided by 2 */
#define ADC_CLOCK_ASYNC_DIV6 (ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC Asynchronous clock mode divided by 2 */
@ -314,7 +314,7 @@ typedef struct
/** @defgroup ADC_Resolution ADC Resolution
* @{
*/
#define ADC_RESOLUTION_12B ((uint32_t)0x00000000) /*!< ADC 12-bit resolution */
#define ADC_RESOLUTION_12B ((uint32_t)0x00000000U) /*!< ADC 12-bit resolution */
#define ADC_RESOLUTION_10B ((uint32_t)ADC_CFGR1_RES_0) /*!< ADC 10-bit resolution */
#define ADC_RESOLUTION_8B ((uint32_t)ADC_CFGR1_RES_1) /*!< ADC 8-bit resolution */
#define ADC_RESOLUTION_6B ((uint32_t)ADC_CFGR1_RES) /*!< ADC 6-bit resolution */
@ -325,7 +325,7 @@ typedef struct
/** @defgroup ADC_data_align ADC Data Align
* @{
*/
#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000)
#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000U)
#define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CFGR1_ALIGN)
/**
@ -335,7 +335,7 @@ typedef struct
/** @defgroup ADC_Regular_External_Trigger_Source_Edge ADC External Trigger Source Edge for Regular Group
* @{
*/
#define ADC_EXTERNALTRIGCONVEDGE_NONE ((uint32_t)0x00000000)
#define ADC_EXTERNALTRIGCONVEDGE_NONE ((uint32_t)0x00000000U)
#define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CFGR1_EXTEN_0)
#define ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CFGR1_EXTEN_1)
#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ((uint32_t)ADC_CFGR1_EXTEN)
@ -356,7 +356,7 @@ typedef struct
/** @defgroup ADC_Overrun ADC Overrun
* @{
*/
#define ADC_OVR_DATA_PRESERVED ((uint32_t)0x00000000)
#define ADC_OVR_DATA_PRESERVED ((uint32_t)0x00000000U)
#define ADC_OVR_DATA_OVERWRITTEN ((uint32_t)ADC_CFGR1_OVRMOD)
/**
* @}
@ -366,8 +366,8 @@ typedef struct
/** @defgroup ADC_rank ADC rank
* @{
*/
#define ADC_RANK_CHANNEL_NUMBER ((uint32_t)0x00001000) /*!< Enable the rank of the selected channels. Number of ranks in the sequence is defined by number of channels enabled, rank of each channel is defined by channel number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...) */
#define ADC_RANK_NONE ((uint32_t)0x00001001) /*!< Disable the selected rank (selected channel) from sequencer */
#define ADC_RANK_CHANNEL_NUMBER ((uint32_t)0x00001000U) /*!< Enable the rank of the selected channels. Number of ranks in the sequence is defined by number of channels enabled, rank of each channel is defined by channel number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...) */
#define ADC_RANK_NONE ((uint32_t)0x00001001U) /*!< Disable the selected rank (selected channel) from sequencer */
/**
* @}
*/
@ -411,8 +411,8 @@ typedef struct
/** @defgroup ADC_Channel_AWD_Masks ADC Channel Masks
* @{
*/
#define ADC_CHANNEL_MASK ((uint32_t)0x0007FFFF)
#define ADC_CHANNEL_AWD_MASK ((uint32_t)0x7C000000)
#define ADC_CHANNEL_MASK ((uint32_t)0x0007FFFFU)
#define ADC_CHANNEL_AWD_MASK ((uint32_t)0x7C000000U)
/**
* @}
*/
@ -422,7 +422,7 @@ typedef struct
* @{
*/
#define ADC_SAMPLETIME_1CYCLE_5 ((uint32_t)0x00000000) /*!< ADC sampling time 1.5 cycle */
#define ADC_SAMPLETIME_1CYCLE_5 ((uint32_t)0x00000000U) /*!< ADC sampling time 1.5 cycle */
#define ADC_SAMPLETIME_7CYCLES_5 ((uint32_t)ADC_SMPR_SMPR_0) /*!< ADC sampling time 7.5 CYCLES */
#define ADC_SAMPLETIME_13CYCLES_5 ((uint32_t)ADC_SMPR_SMPR_1) /*!< ADC sampling time 13.5 CYCLES */
#define ADC_SAMPLETIME_28CYCLES_5 ((uint32_t)(ADC_SMPR_SMPR_1 | ADC_SMPR_SMPR_0)) /*!< ADC sampling time 28.5 CYCLES */
@ -449,8 +449,8 @@ typedef struct
/* Scan direction backward is considered as additional setting. */
/* In case of migration from another STM32 device, the user will be */
/* warned of change of setting choices with assert check. */
#define ADC_SCAN_DIRECTION_FORWARD ((uint32_t)0x00000001) /*!< Scan direction forward: from channel 0 to channel 18 */
#define ADC_SCAN_DIRECTION_BACKWARD ((uint32_t)0x00000002) /*!< Scan direction backward: from channel 18 to channel 0 */
#define ADC_SCAN_DIRECTION_FORWARD ((uint32_t)0x00000001U) /*!< Scan direction forward: from channel 0 to channel 18 */
#define ADC_SCAN_DIRECTION_BACKWARD ((uint32_t)0x00000002U) /*!< Scan direction backward: from channel 18 to channel 0 */
#define ADC_SCAN_ENABLE ADC_SCAN_DIRECTION_FORWARD /* For compatibility with other STM32 devices */
/**
@ -461,14 +461,14 @@ typedef struct
* @{
*/
#define ADC_OVERSAMPLING_RATIO_2 ((uint32_t)0x00000000) /*!< ADC Oversampling ratio 2x */
#define ADC_OVERSAMPLING_RATIO_4 ((uint32_t)0x00000004) /*!< ADC Oversampling ratio 4x */
#define ADC_OVERSAMPLING_RATIO_8 ((uint32_t)0x00000008) /*!< ADC Oversampling ratio 8x */
#define ADC_OVERSAMPLING_RATIO_16 ((uint32_t)0x0000000C) /*!< ADC Oversampling ratio 16x */
#define ADC_OVERSAMPLING_RATIO_32 ((uint32_t)0x00000010) /*!< ADC Oversampling ratio 32x */
#define ADC_OVERSAMPLING_RATIO_64 ((uint32_t)0x00000014) /*!< ADC Oversampling ratio 64x */
#define ADC_OVERSAMPLING_RATIO_128 ((uint32_t)0x00000018) /*!< ADC Oversampling ratio 128x */
#define ADC_OVERSAMPLING_RATIO_256 ((uint32_t)0x0000001C) /*!< ADC Oversampling ratio 256x */
#define ADC_OVERSAMPLING_RATIO_2 ((uint32_t)0x00000000U) /*!< ADC Oversampling ratio 2x */
#define ADC_OVERSAMPLING_RATIO_4 ((uint32_t)0x00000004U) /*!< ADC Oversampling ratio 4x */
#define ADC_OVERSAMPLING_RATIO_8 ((uint32_t)0x00000008U) /*!< ADC Oversampling ratio 8x */
#define ADC_OVERSAMPLING_RATIO_16 ((uint32_t)0x0000000CU) /*!< ADC Oversampling ratio 16x */
#define ADC_OVERSAMPLING_RATIO_32 ((uint32_t)0x00000010U) /*!< ADC Oversampling ratio 32x */
#define ADC_OVERSAMPLING_RATIO_64 ((uint32_t)0x00000014U) /*!< ADC Oversampling ratio 64x */
#define ADC_OVERSAMPLING_RATIO_128 ((uint32_t)0x00000018U) /*!< ADC Oversampling ratio 128x */
#define ADC_OVERSAMPLING_RATIO_256 ((uint32_t)0x0000001CU) /*!< ADC Oversampling ratio 256x */
/**
* @}
*/
@ -476,15 +476,15 @@ typedef struct
/** @defgroup ADC_Right_Bit_Shift ADC Right Bit Shift
* @{
*/
#define ADC_RIGHTBITSHIFT_NONE ((uint32_t)0x00000000) /*!< ADC No bit shift for oversampling */
#define ADC_RIGHTBITSHIFT_1 ((uint32_t)0x00000020) /*!< ADC 1 bit shift for oversampling */
#define ADC_RIGHTBITSHIFT_2 ((uint32_t)0x00000040) /*!< ADC 2 bits shift for oversampling */
#define ADC_RIGHTBITSHIFT_3 ((uint32_t)0x00000060) /*!< ADC 3 bits shift for oversampling */
#define ADC_RIGHTBITSHIFT_4 ((uint32_t)0x00000080) /*!< ADC 4 bits shift for oversampling */
#define ADC_RIGHTBITSHIFT_5 ((uint32_t)0x000000A0) /*!< ADC 5 bits shift for oversampling */
#define ADC_RIGHTBITSHIFT_6 ((uint32_t)0x000000C0) /*!< ADC 6 bits shift for oversampling */
#define ADC_RIGHTBITSHIFT_7 ((uint32_t)0x000000E0) /*!< ADC 7 bits shift for oversampling */
#define ADC_RIGHTBITSHIFT_8 ((uint32_t)0x00000100) /*!< ADC 8 bits shift for oversampling */
#define ADC_RIGHTBITSHIFT_NONE ((uint32_t)0x00000000U) /*!< ADC No bit shift for oversampling */
#define ADC_RIGHTBITSHIFT_1 ((uint32_t)0x00000020U) /*!< ADC 1 bit shift for oversampling */
#define ADC_RIGHTBITSHIFT_2 ((uint32_t)0x00000040U) /*!< ADC 2 bits shift for oversampling */
#define ADC_RIGHTBITSHIFT_3 ((uint32_t)0x00000060U) /*!< ADC 3 bits shift for oversampling */
#define ADC_RIGHTBITSHIFT_4 ((uint32_t)0x00000080U) /*!< ADC 4 bits shift for oversampling */
#define ADC_RIGHTBITSHIFT_5 ((uint32_t)0x000000A0U) /*!< ADC 5 bits shift for oversampling */
#define ADC_RIGHTBITSHIFT_6 ((uint32_t)0x000000C0U) /*!< ADC 6 bits shift for oversampling */
#define ADC_RIGHTBITSHIFT_7 ((uint32_t)0x000000E0U) /*!< ADC 7 bits shift for oversampling */
#define ADC_RIGHTBITSHIFT_8 ((uint32_t)0x00000100U) /*!< ADC 8 bits shift for oversampling */
/**
* @}
*/
@ -492,8 +492,8 @@ typedef struct
/** @defgroup ADC_Triggered_Oversampling_Mode ADC Triggered Oversampling Mode
* @{
*/
#define ADC_TRIGGEREDMODE_SINGLE_TRIGGER ((uint32_t)0x00000000) /*!< ADC No bit shift for oversampling */
#define ADC_TRIGGEREDMODE_MULTI_TRIGGER ((uint32_t)0x00000200) /*!< ADC No bit shift for oversampling */
#define ADC_TRIGGEREDMODE_SINGLE_TRIGGER ((uint32_t)0x00000000U) /*!< ADC No bit shift for oversampling */
#define ADC_TRIGGEREDMODE_MULTI_TRIGGER ((uint32_t)0x00000200U) /*!< ADC No bit shift for oversampling */
/**
* @}
*/
@ -501,7 +501,7 @@ typedef struct
/** @defgroup ADC_analog_watchdog_mode ADC Analog Watchdog Mode
* @{
*/
#define ADC_ANALOGWATCHDOG_NONE ((uint32_t) 0x00000000)
#define ADC_ANALOGWATCHDOG_NONE ((uint32_t) 0x00000000U)
#define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CFGR1_AWDSGL | ADC_CFGR1_AWDEN))
#define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t) ADC_CFGR1_AWDEN)
/**
@ -654,7 +654,7 @@ typedef struct
* @param _CONTINUOUS_MODE_: Continuous mode.
* @retval None
*/
#define ADC_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << 13)
#define ADC_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << 13U)
/**
* @brief Enable ADC scan mode to convert multiple ranks with sequencer.
@ -663,7 +663,7 @@ typedef struct
*/
#define ADC_SCANDIR(_SCAN_MODE_) \
( ( (_SCAN_MODE_) == (ADC_SCAN_DIRECTION_BACKWARD) \
)? (ADC_CFGR1_SCANDIR) : (0x00000000) \
)? (ADC_CFGR1_SCANDIR) : (0x00000000U) \
)
/**
@ -671,42 +671,42 @@ typedef struct
* @param _NBR_DISCONTINUOUS_CONV_: Number of discontinuous conversions.
* @retval None
*/
#define __HAL_ADC_CFGR1_DISCONTINUOUS_NUM(_NBR_DISCONTINUOUS_CONV_) (((_NBR_DISCONTINUOUS_CONV_) - 1) << 17)
#define __HAL_ADC_CFGR1_DISCONTINUOUS_NUM(_NBR_DISCONTINUOUS_CONV_) (((_NBR_DISCONTINUOUS_CONV_) - 1U) << 17U)
/**
* @brief Enable the ADC DMA continuous request.
* @param _DMAContReq_MODE_: DMA continuous request mode.
* @retval None
*/
#define ADC_DMACONTREQ(_DMAContReq_MODE_) ((_DMAContReq_MODE_) << 1)
#define ADC_DMACONTREQ(_DMAContReq_MODE_) ((_DMAContReq_MODE_) << 1U)
/**
* @brief Enable the ADC Auto Delay.
* @param _AutoDelay_: Auto delay bit enable or disable.
* @retval None
*/
#define __HAL_ADC_CFGR1_AutoDelay(_AutoDelay_) ((_AutoDelay_) << 14)
#define __HAL_ADC_CFGR1_AutoDelay(_AutoDelay_) ((_AutoDelay_) << 14U)
/**
* @brief Enable the ADC LowPowerAutoPowerOff.
* @param _AUTOFF_: AutoOff bit enable or disable.
* @retval None
*/
#define __HAL_ADC_CFGR1_AUTOFF(_AUTOFF_) ((_AUTOFF_) << 15)
#define __HAL_ADC_CFGR1_AUTOFF(_AUTOFF_) ((_AUTOFF_) << 15U)
/**
* @brief Configure the analog watchdog high threshold into registers TR1, TR2 or TR3.
* @param _Threshold_: Threshold value
* @retval None
*/
#define ADC_TRX_HIGHTHRESHOLD(_Threshold_) ((_Threshold_) << 16)
#define ADC_TRX_HIGHTHRESHOLD(_Threshold_) ((_Threshold_) << 16U)
/**
* @brief Enable the ADC Low Frequency mode.
* @param _LOW_FREQUENCY_MODE_: Low Frequency mode.
* @retval None
*/
#define __HAL_ADC_CCR_LOWFREQUENCY(_LOW_FREQUENCY_MODE_) ((_LOW_FREQUENCY_MODE_) << 25)
#define __HAL_ADC_CCR_LOWFREQUENCY(_LOW_FREQUENCY_MODE_) ((_LOW_FREQUENCY_MODE_) << 25U)
/**
* @brief Shift the offset in function of the selected ADC resolution.
@ -721,7 +721,7 @@ typedef struct
* @retval None
*/
#define ADC_OFFSET_SHIFT_RESOLUTION(__HANDLE__, _Offset_) \
((_Offset_) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR1_RES) >> 3)*2))
((_Offset_) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR1_RES) >> 3U)*2U))
/**
* @brief Shift the AWD1 threshold in function of the selected ADC resolution.
@ -736,7 +736,7 @@ typedef struct
* @retval None
*/
#define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, _Threshold_) \
((_Threshold_) << ((((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_RES) >> 3)*2))
((_Threshold_) << ((((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_RES) >> 3U)*2U))
/**
* @brief Shift the value on the left, less significant are set to 0.
@ -973,10 +973,10 @@ typedef struct
* @{
*/
#define IS_ADC_RANGE(RESOLUTION, ADC_VALUE) \
((((RESOLUTION) == ADC_RESOLUTION_12B) && ((ADC_VALUE) <= ((uint32_t)0x0FFF))) || \
(((RESOLUTION) == ADC_RESOLUTION_10B) && ((ADC_VALUE) <= ((uint32_t)0x03FF))) || \
(((RESOLUTION) == ADC_RESOLUTION_8B) && ((ADC_VALUE) <= ((uint32_t)0x00FF))) || \
(((RESOLUTION) == ADC_RESOLUTION_6B) && ((ADC_VALUE) <= ((uint32_t)0x003F))))
((((RESOLUTION) == ADC_RESOLUTION_12B) && ((ADC_VALUE) <= ((uint32_t)0x0FFFU))) || \
(((RESOLUTION) == ADC_RESOLUTION_10B) && ((ADC_VALUE) <= ((uint32_t)0x03FFU))) || \
(((RESOLUTION) == ADC_RESOLUTION_8B) && ((ADC_VALUE) <= ((uint32_t)0x00FFU))) || \
(((RESOLUTION) == ADC_RESOLUTION_6B) && ((ADC_VALUE) <= ((uint32_t)0x003FU))))
/**
* @}
*/
@ -984,7 +984,7 @@ typedef struct
/** @defgroup ADC_regular_nb_conv_verification ADC Regular Nb Conversion Verification
* @{
*/
#define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)16)))
#define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= ((uint32_t)1U)) && ((LENGTH) <= ((uint32_t)16U)))
/**
* @}
*/

42
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_adc_ex.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx_hal_adc_ex.c
* @author MCD Application Team
* @version V1.5.0
* @date 8-January-2016
* @version V1.7.0
* @date 31-May-2016
* @brief This file provides firmware functions to manage the following
* functionalities of the Analog to Digital Convertor (ADC)
* peripheral:
@ -83,17 +83,17 @@
/* Values defined to be higher than worst cases: low clock frequency, */
/* maximum prescaler. */
/* Unit: ms */
#define ADC_CALIBRATION_TIMEOUT 10
#define ADC_CALIBRATION_TIMEOUT 10U
/* Delay for VREFINT stabilization time. */
/* Internal reference startup time max value is 3ms (refer to device datasheet, parameter TVREFINT). */
/* Unit: ms */
#define SYSCFG_BUF_VREFINT_ENABLE_TIMEOUT ((uint32_t) 3)
#define SYSCFG_BUF_VREFINT_ENABLE_TIMEOUT ((uint32_t) 3U)
/* Delay for TEMPSENSOR stabilization time. */
/* Temperature sensor startup time max value is 10µs (refer to device datasheet, parameter tSTART). */
/* Temperature sensor startup time max value is 10us (refer to device datasheet, parameter tSTART). */
/* Unit: ms */
#define SYSCFG_BUF_TEMPSENSOR_ENABLE_TIMEOUT ((uint32_t) 1)
#define SYSCFG_BUF_TEMPSENSOR_ENABLE_TIMEOUT ((uint32_t) 1U)
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
@ -138,7 +138,7 @@ This subsection provides functions allowing to:
HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc, uint32_t SingleDiff)
{
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
uint32_t tickstart=0;
uint32_t tickstart=0U;
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
@ -211,7 +211,7 @@ uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef* hadc, uint32_t Single
assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff));
/* Return the ADC calibration value */
return ((hadc->Instance->CALFACT) & 0x0000007F);
return ((hadc->Instance->CALFACT) & 0x0000007FU);
}
/**
@ -272,16 +272,16 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef* hadc, uint32
*/
HAL_StatusTypeDef HAL_ADCEx_EnableVREFINT(void)
{
uint32_t tickstart = 0;
uint32_t tickstart = 0U;
/* Enable the Buffer for the ADC by setting EN_VREFINT bit and the ENBUF_SENSOR_ADC in the CFGR3 register */
SET_BIT(SYSCFG->CFGR3, (SYSCFG_CFGR3_ENBUF_VREFINT_ADC | SYSCFG_CFGR3_EN_VREFINT));
/* Enable the Buffer for the ADC by setting ENBUF_SENSOR_ADC bit in the CFGR3 register */
SET_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_ENBUF_VREFINT_ADC);
/* Wait for Vrefint buffer effectively enabled */
/* Get tick count */
tickstart = HAL_GetTick();
while(HAL_IS_BIT_CLR(SYSCFG->CFGR3, SYSCFG_CFGR3_VREFINT_ADC_RDYF))
while(HAL_IS_BIT_CLR(SYSCFG->CFGR3, SYSCFG_CFGR3_VREFINT_RDYF))
{
if((HAL_GetTick() - tickstart) > SYSCFG_BUF_VREFINT_ENABLE_TIMEOUT)
{
@ -299,8 +299,8 @@ HAL_StatusTypeDef HAL_ADCEx_EnableVREFINT(void)
*/
void HAL_ADCEx_DisableVREFINT(void)
{
/* Disable the Vrefint by resetting EN_VREFINT bit and the ENBUF_SENSOR_ADC in the CFGR3 register */
CLEAR_BIT(SYSCFG->CFGR3, (SYSCFG_CFGR3_ENBUF_VREFINT_ADC | SYSCFG_CFGR3_EN_VREFINT));
/* Disable the Vrefint by resetting ENBUF_SENSOR_ADC bit in the CFGR3 register */
CLEAR_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_ENBUF_VREFINT_ADC);
}
/**
@ -313,16 +313,16 @@ void HAL_ADCEx_DisableVREFINT(void)
*/
HAL_StatusTypeDef HAL_ADCEx_EnableVREFINTTempSensor(void)
{
uint32_t tickstart = 0;
uint32_t tickstart = 0U;
/* Enable the Buffer for the ADC by setting EN_VREFINT bit and the ENBUF_SENSOR_ADC in the CFGR3 register */
SET_BIT(SYSCFG->CFGR3, (SYSCFG_CFGR3_ENBUF_SENSOR_ADC | SYSCFG_CFGR3_EN_VREFINT));
/* Enable the Buffer for the ADC by setting ENBUF_SENSOR_ADC bit in the CFGR3 register */
SET_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_ENBUF_SENSOR_ADC);
/* Wait for Vrefint buffer effectively enabled */
/* Get tick count */
tickstart = HAL_GetTick();
while(HAL_IS_BIT_CLR(SYSCFG->CFGR3, SYSCFG_CFGR3_VREFINT_ADC_RDYF))
while(HAL_IS_BIT_CLR(SYSCFG->CFGR3, SYSCFG_CFGR3_VREFINT_RDYF))
{
if((HAL_GetTick() - tickstart) > SYSCFG_BUF_TEMPSENSOR_ENABLE_TIMEOUT)
{
@ -334,14 +334,14 @@ HAL_StatusTypeDef HAL_ADCEx_EnableVREFINTTempSensor(void)
}
/**
* @brief Disables the VEREFINT and Sensor for the ADC.
* @brief Disables the VREFINT and Sensor for the ADC.
* @note This is functional only if the LOCK is not set.
* @retval None
*/
void HAL_ADCEx_DisableVREFINTTempSensor(void)
{
/* Disable the Vrefint by resetting EN_VREFINT bit and the ENBUF_SENSOR_ADC in the CFGR3 register */
CLEAR_BIT(SYSCFG->CFGR3, (SYSCFG_CFGR3_ENBUF_SENSOR_ADC | SYSCFG_CFGR3_EN_VREFINT));
/* Disable the Vrefint by resetting ENBUF_SENSOR_ADC bit in the CFGR3 register */
CLEAR_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_ENBUF_SENSOR_ADC);
}
/**

14
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_adc_ex.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx_hal_adc_ex.h
* @author MCD Application Team
* @version V1.5.0
* @date 8-January-2016
* @version V1.7.0
* @date 31-May-2016
* @brief This file contains all the functions prototypes for the ADC firmware
* library.
******************************************************************************
@ -65,7 +65,7 @@
/** @defgroup ADCEx_Channel_Mode ADC Single Ended
* @{
*/
#define ADC_SINGLE_ENDED (uint32_t)0x00000000 /* dummy value */
#define ADC_SINGLE_ENDED (uint32_t)0x00000000U /* dummy value */
/**
* @}
*/
@ -73,7 +73,7 @@
/** @defgroup ADC_External_trigger_Source ADC External Trigger Source
* @{
*/
#define ADC_EXTERNALTRIGCONV_T6_TRGO ((uint32_t)0x00000000)
#define ADC_EXTERNALTRIGCONV_T6_TRGO ((uint32_t)0x00000000U)
#define ADC_EXTERNALTRIGCONV_T21_CC2 (ADC_CFGR1_EXTSEL_0)
#define ADC_EXTERNALTRIGCONV_T2_TRGO (ADC_CFGR1_EXTSEL_1)
#define ADC_EXTERNALTRIGCONV_T2_CC4 (ADC_CFGR1_EXTSEL_1 | ADC_CFGR1_EXTSEL_0)
@ -108,7 +108,7 @@
/** @defgroup ADC_SYSCFG_internal_paths_flags_definition ADC SYSCFG internal paths Flags Definition
* @{
*/
#define ADC_FLAG_SENSOR SYSCFG_CFGR3_SENSOR_ADC_RDYF
#define ADC_FLAG_SENSOR SYSCFG_CFGR3_VREFINT_RDYF
#define ADC_FLAG_VREFINT SYSCFG_VREFINT_ADC_RDYF
/**
* @}
@ -130,11 +130,11 @@
* @{
*/
/**
* @brief Calibration factor lenght verification (7 bits maximum)
* @brief Calibration factor length verification (7 bits maximum)
* @param _Calibration_Factor_: Calibration factor value
* @retval None
*/
#define IS_ADC_CALFACT(_Calibration_Factor_) ((_Calibration_Factor_) <= ((uint32_t)0x7F))
#define IS_ADC_CALFACT(_Calibration_Factor_) ((_Calibration_Factor_) <= ((uint32_t)0x7FU))
/**
* @}
*/

877
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_comp.c
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File diff suppressed because it is too large Load Diff

896
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_comp.h
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File diff suppressed because it is too large Load Diff

32
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_comp_ex.c
View File

@ -2,11 +2,12 @@
******************************************************************************
* @file stm32l0xx_hal_comp_ex.c
* @author MCD Application Team
* @version V1.5.0
* @date 8-January-2016
* @version V1.7.0
* @date 31-May-2016
* @brief Extended COMP HAL module driver.
* @brief This file provides firmware functions to manage the VREFINT
* which can act as input to the comparator.
* @brief This file provides firmware functions to manage voltage reference
* VrefInt that must be specifically controled for comparator
* instance COMP2.
@verbatim
==============================================================================
##### COMP peripheral Extended features #####
@ -75,28 +76,29 @@
*/
/**
* @brief Enables the Buffer Vrefint for the COMP.
* @note This is functional only if the LOCK bit is not set
* @brief Enable Vrefint and path to comparator, used by comparator
* instance COMP2 input based on VrefInt or subdivision of VrefInt.
* @note The equivalent of this function is managed automatically when
* using function "HAL_COMP_Init()".
* @note VrefInt requires a startup time
* (refer to device datasheet, parameter "TVREFINT").
* @retval None
*/
void HAL_COMPEx_EnableVREFINT(void)
{
/* Enable the Buffer for the COMP by setting EN_VREFINT bit and the ENBUFLP_VREFINT_COMP in the CFGR3 register */
SYSCFG->CFGR3 |= (SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP | SYSCFG_CFGR3_EN_VREFINT);
/* Enable the Buffer for the COMP by setting ENBUFLP_VREFINT_COMP bit in the CFGR3 register */
SYSCFG->CFGR3 |= (SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP);
}
/**
* @brief Disables the Buffer Vrefint for the COMP.
* @note This is functional only if the LOCK bit is not set
* @brief Disable Vrefint and path to comparator, used by comparator
* instance COMP2 input based on VrefInt or subdivision of VrefInt.
* @retval None
*/
void HAL_COMPEx_DisableVREFINT(void)
{
/* Disable the Vrefint by resetting ENBUFLP_BGAP_COMP bit and the EN_VREFINT bit in the CFGR3 register */
SYSCFG->CFGR3 &= (uint32_t)~((uint32_t)(SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP | SYSCFG_CFGR3_EN_VREFINT));
/* Disable the Vrefint by resetting ENBUFLP_VREFINT_COMP bit in the CFGR3 register */
SYSCFG->CFGR3 &= (uint32_t)~((uint32_t)(SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP));
}
/**

4
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_comp_ex.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx_hal_comp_ex.h
* @author MCD Application Team
* @version V1.5.0
* @date 8-January-2016
* @version V1.7.0
* @date 31-May-2016
* @brief Header file of COMP HAL Extended module.
******************************************************************************
* @attention

12
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_cortex.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx_hal_cortex.c
* @author MCD Application Team
* @version V1.5.0
* @date 8-January-2016
* @version V1.7.0
* @date 31-May-2016
* @brief CORTEX HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the CORTEX:
@ -47,7 +47,7 @@
(++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
(++) Enables the SysTick Interrupt.
(++) Starts the SysTick Counter.
(+) You can change the SysTick Clock source to be HCLK_Div8 by calling the function
HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
HAL_SYSTICK_Config() function call. The HAL_SYSTICK_CLKSourceConfig() function is defined
@ -356,7 +356,7 @@ void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
/* Set the base adsress and set the 4 LSB to 0 */
MPU->RBAR = (MPU_Init->BaseAddress) & 0xfffffff0;
MPU->RBAR = (MPU_Init->BaseAddress) & 0xfffffff0U;
/* Fill the field RASR */
MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) |
@ -370,8 +370,8 @@ void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
}
else
{
MPU->RBAR = 0x00;
MPU->RASR = 0x00;
MPU->RBAR = 0x00U;
MPU->RASR = 0x00U;
}
}
#endif /* __MPU_PRESENT */

126
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_cortex.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx_hal_cortex.h
* @author MCD Application Team
* @version V1.5.0
* @date 8-January-2016
* @version V1.7.0
* @date 31-May-2016
* @brief Header file of CORTEX HAL module.
******************************************************************************
* @attention
@ -106,15 +106,15 @@ typedef struct
*/
#define IS_NVIC_PREEMPTION_PRIORITY(__PRIORITY__) ((__PRIORITY__) < 0x4)
#define IS_NVIC_PREEMPTION_PRIORITY(__PRIORITY__) ((__PRIORITY__) < 0x4U)
#define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= 0x00)
#define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= 0x0)
/** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick Clock Source
* @{
*/
#define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000)
#define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004)
#define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000U)
#define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004U)
#define IS_SYSTICK_CLK_SOURCE(__SOURCE__) (((__SOURCE__) == SYSTICK_CLKSOURCE_HCLK) || \
((__SOURCE__) == SYSTICK_CLKSOURCE_HCLK_DIV8))
/**
@ -125,10 +125,10 @@ typedef struct
/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control CORTEX MPU HFNMI and PRIVILEGED Access control
* @{
*/
#define MPU_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000)
#define MPU_HARDFAULT_NMI ((uint32_t)0x00000002)
#define MPU_PRIVILEGED_DEFAULT ((uint32_t)0x00000004)
#define MPU_HFNMI_PRIVDEF ((uint32_t)0x00000006)
#define MPU_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000U)
#define MPU_HARDFAULT_NMI ((uint32_t)0x00000002U)
#define MPU_PRIVILEGED_DEFAULT ((uint32_t)0x00000004U)
#define MPU_HFNMI_PRIVDEF ((uint32_t)0x00000006U)
/**
* @}
*/
@ -136,8 +136,8 @@ typedef struct
/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
* @{
*/
#define MPU_REGION_ENABLE ((uint8_t)0x01)
#define MPU_REGION_DISABLE ((uint8_t)0x00)
#define MPU_REGION_ENABLE ((uint8_t)0x01U)
#define MPU_REGION_DISABLE ((uint8_t)0x00U)
/**
* @}
*/
@ -145,8 +145,8 @@ typedef struct
/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
* @{
*/
#define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00)
#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01)
#define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00U)
#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01U)
/**
* @}
*/
@ -154,8 +154,8 @@ typedef struct
/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
* @{
*/
#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01)
#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00)
#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01U)
#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00U)
/**
* @}
*/
@ -163,8 +163,8 @@ typedef struct
/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable
* @{
*/
#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01)
#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00)
#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01U)
#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00U)
/**
* @}
*/
@ -172,8 +172,8 @@ typedef struct
/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable
* @{
*/
#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01)
#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00)
#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01U)
#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00U)
/**
* @}
*/
@ -181,34 +181,34 @@ typedef struct
/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size
* @{
*/
#define MPU_REGION_SIZE_32B ((uint8_t)0x04)
#define MPU_REGION_SIZE_64B ((uint8_t)0x05)
#define MPU_REGION_SIZE_128B ((uint8_t)0x06)
#define MPU_REGION_SIZE_256B ((uint8_t)0x07)
#define MPU_REGION_SIZE_512B ((uint8_t)0x08)
#define MPU_REGION_SIZE_1KB ((uint8_t)0x09)
#define MPU_REGION_SIZE_2KB ((uint8_t)0x0A)
#define MPU_REGION_SIZE_4KB ((uint8_t)0x0B)
#define MPU_REGION_SIZE_8KB ((uint8_t)0x0C)
#define MPU_REGION_SIZE_16KB ((uint8_t)0x0D)
#define MPU_REGION_SIZE_32KB ((uint8_t)0x0E)
#define MPU_REGION_SIZE_64KB ((uint8_t)0x0F)
#define MPU_REGION_SIZE_128KB ((uint8_t)0x10)
#define MPU_REGION_SIZE_256KB ((uint8_t)0x11)
#define MPU_REGION_SIZE_512KB ((uint8_t)0x12)
#define MPU_REGION_SIZE_1MB ((uint8_t)0x13)
#define MPU_REGION_SIZE_2MB ((uint8_t)0x14)
#define MPU_REGION_SIZE_4MB ((uint8_t)0x15)
#define MPU_REGION_SIZE_8MB ((uint8_t)0x16)
#define MPU_REGION_SIZE_16MB ((uint8_t)0x17)
#define MPU_REGION_SIZE_32MB ((uint8_t)0x18)
#define MPU_REGION_SIZE_64MB ((uint8_t)0x19)
#define MPU_REGION_SIZE_128MB ((uint8_t)0x1A)
#define MPU_REGION_SIZE_256MB ((uint8_t)0x1B)
#define MPU_REGION_SIZE_512MB ((uint8_t)0x1C)
#define MPU_REGION_SIZE_1GB ((uint8_t)0x1D)
#define MPU_REGION_SIZE_2GB ((uint8_t)0x1E)
#define MPU_REGION_SIZE_4GB ((uint8_t)0x1F)
#define MPU_REGION_SIZE_32B ((uint8_t)0x04U)
#define MPU_REGION_SIZE_64B ((uint8_t)0x05U)
#define MPU_REGION_SIZE_128B ((uint8_t)0x06U)
#define MPU_REGION_SIZE_256B ((uint8_t)0x07U)
#define MPU_REGION_SIZE_512B ((uint8_t)0x08U)
#define MPU_REGION_SIZE_1KB ((uint8_t)0x09U)
#define MPU_REGION_SIZE_2KB ((uint8_t)0x0AU)
#define MPU_REGION_SIZE_4KB ((uint8_t)0x0BU)
#define MPU_REGION_SIZE_8KB ((uint8_t)0x0CU)
#define MPU_REGION_SIZE_16KB ((uint8_t)0x0DU)
#define MPU_REGION_SIZE_32KB ((uint8_t)0x0EU)
#define MPU_REGION_SIZE_64KB ((uint8_t)0x0FU)
#define MPU_REGION_SIZE_128KB ((uint8_t)0x10U)
#define MPU_REGION_SIZE_256KB ((uint8_t)0x11U)
#define MPU_REGION_SIZE_512KB ((uint8_t)0x12U)
#define MPU_REGION_SIZE_1MB ((uint8_t)0x13U)
#define MPU_REGION_SIZE_2MB ((uint8_t)0x14U)
#define MPU_REGION_SIZE_4MB ((uint8_t)0x15U)
#define MPU_REGION_SIZE_8MB ((uint8_t)0x16U)
#define MPU_REGION_SIZE_16MB ((uint8_t)0x17U)
#define MPU_REGION_SIZE_32MB ((uint8_t)0x18U)
#define MPU_REGION_SIZE_64MB ((uint8_t)0x19U)
#define MPU_REGION_SIZE_128MB ((uint8_t)0x1AU)
#define MPU_REGION_SIZE_256MB ((uint8_t)0x1BU)
#define MPU_REGION_SIZE_512MB ((uint8_t)0x1CU)
#define MPU_REGION_SIZE_1GB ((uint8_t)0x1DU)
#define MPU_REGION_SIZE_2GB ((uint8_t)0x1EU)
#define MPU_REGION_SIZE_4GB ((uint8_t)0x1FU)
/**
* @}
*/
@ -216,12 +216,12 @@ typedef struct
/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes
* @{
*/
#define MPU_REGION_NO_ACCESS ((uint8_t)0x00)
#define MPU_REGION_PRIV_RW ((uint8_t)0x01)
#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02)
#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03)
#define MPU_REGION_PRIV_RO ((uint8_t)0x05)
#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06)
#define MPU_REGION_NO_ACCESS ((uint8_t)0x00U)
#define MPU_REGION_PRIV_RW ((uint8_t)0x01U)
#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02U)
#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03U)
#define MPU_REGION_PRIV_RO ((uint8_t)0x05U)
#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06U)
/**
* @}
*/
@ -229,14 +229,14 @@ typedef struct
/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
* @{
*/
#define MPU_REGION_NUMBER0 ((uint8_t)0x00)
#define MPU_REGION_NUMBER1 ((uint8_t)0x01)
#define MPU_REGION_NUMBER2 ((uint8_t)0x02)
#define MPU_REGION_NUMBER3 ((uint8_t)0x03)
#define MPU_REGION_NUMBER4 ((uint8_t)0x04)
#define MPU_REGION_NUMBER5 ((uint8_t)0x05)
#define MPU_REGION_NUMBER6 ((uint8_t)0x06)
#define MPU_REGION_NUMBER7 ((uint8_t)0x07)
#define MPU_REGION_NUMBER0 ((uint8_t)0x00U)
#define MPU_REGION_NUMBER1 ((uint8_t)0x01U)
#define MPU_REGION_NUMBER2 ((uint8_t)0x02U)
#define MPU_REGION_NUMBER3 ((uint8_t)0x03U)
#define MPU_REGION_NUMBER4 ((uint8_t)0x04U)
#define MPU_REGION_NUMBER5 ((uint8_t)0x05U)
#define MPU_REGION_NUMBER6 ((uint8_t)0x06U)
#define MPU_REGION_NUMBER7 ((uint8_t)0x07U)
/**
* @}
*/
@ -391,7 +391,7 @@ void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
((SIZE) == MPU_REGION_SIZE_2GB) || \
((SIZE) == MPU_REGION_SIZE_4GB))
#define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF)
#define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FFU)
#endif /* __MPU_PRESENT */

48
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_crc.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx_hal_crc.c
* @author MCD Application Team
* @version V1.5.0
* @date 8-January-2016
* @version V1.7.0
* @date 31-May-2016
* @brief CRC HAL module driver.
*
* This file provides firmware functions to manage the following
@ -315,8 +315,8 @@ __weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc)
*/
uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
{
uint32_t index = 0; /* CRC input data buffer index */
uint32_t temp = 0; /* CRC output (read from hcrc->Instance->DR register) */
uint32_t index = 0U; /* CRC input data buffer index */
uint32_t temp = 0U; /* CRC output (read from hcrc->Instance->DR register) */
/* Process locked */
__HAL_LOCK(hcrc);
@ -328,7 +328,7 @@ uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_
{
case CRC_INPUTDATA_FORMAT_WORDS:
/* Enter Data to the CRC calculator */
for(index = 0; index < BufferLength; index++)
for(index = 0U; index < BufferLength; index++)
{
hcrc->Instance->DR = pBuffer[index];
}
@ -374,8 +374,8 @@ uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_
*/
uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
{
uint32_t index = 0; /* CRC input data buffer index */
uint32_t temp = 0; /* CRC output (read from hcrc->Instance->DR register) */
uint32_t index = 0U; /* CRC input data buffer index */
uint32_t temp = 0U; /* CRC output (read from hcrc->Instance->DR register) */
/* Process locked */
__HAL_LOCK(hcrc);
@ -391,7 +391,7 @@ uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t
{
case CRC_INPUTDATA_FORMAT_WORDS:
/* Enter 32-bit input data to the CRC calculator */
for(index = 0; index < BufferLength; index++)
for(index = 0U; index < BufferLength; index++)
{
hcrc->Instance->DR = pBuffer[index];
}
@ -472,30 +472,30 @@ HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc)
*/
static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength)
{
uint32_t i = 0; /* input data buffer index */
uint32_t i = 0U; /* input data buffer index */
/* Processing time optimization: 4 bytes are entered in a row with a single word write,
* last bytes must be carefully fed to the CRC calculator to ensure a correct type
* handling by the IP */
for(i = 0; i < (BufferLength/4); i++)
for(i = 0U; i < (BufferLength/4U); i++)
{
hcrc->Instance->DR = ((uint32_t)pBuffer[4*i]<<24) | ((uint32_t)pBuffer[4*i+1]<<16) | ((uint32_t)pBuffer[4*i+2]<<8) | (uint32_t)pBuffer[4*i+3];
hcrc->Instance->DR = ((uint32_t)pBuffer[4U*i]<<24U) | ((uint32_t)pBuffer[4U*i+1U]<<16U) | ((uint32_t)pBuffer[4U*i+2U]<<8U) | (uint32_t)pBuffer[4U*i+3U];
}
/* last bytes specific handling */
if ((BufferLength%4) != 0)
if ((BufferLength%4U) != 0U)
{
if (BufferLength%4 == 1)
if (BufferLength%4U == 1U)
{
*(uint8_t volatile*) (&hcrc->Instance->DR) = pBuffer[4*i];
*(uint8_t volatile*) (&hcrc->Instance->DR) = pBuffer[4U*i];
}
if (BufferLength%4 == 2)
if (BufferLength%4U == 2U)
{
*(uint16_t volatile*) (&hcrc->Instance->DR) = ((uint32_t)pBuffer[4*i]<<8) | (uint32_t)pBuffer[4*i+1];
*(uint16_t volatile*) (&hcrc->Instance->DR) = ((uint32_t)pBuffer[4U*i]<<8U) | (uint32_t)pBuffer[4U*i+1U];
}
if (BufferLength%4 == 3)
if (BufferLength%4U == 3U)
{
*(uint16_t volatile*) (&hcrc->Instance->DR) = ((uint32_t)pBuffer[4*i]<<8) | (uint32_t)pBuffer[4*i+1];
*(uint8_t volatile*) (&hcrc->Instance->DR) = pBuffer[4*i+2];
*(uint16_t volatile*) (&hcrc->Instance->DR) = ((uint32_t)pBuffer[4U*i]<<8U) | (uint32_t)pBuffer[4U*i+1U];
*(uint8_t volatile*) (&hcrc->Instance->DR) = pBuffer[4U*i+2U];
}
}
@ -513,18 +513,18 @@ static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_
*/
static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength)
{
uint32_t i = 0; /* input data buffer index */
uint32_t i = 0U; /* input data buffer index */
/* Processing time optimization: 2 HalfWords are entered in a row with a single word write,
* in case of odd length, last HalfWord must be carefully fed to the CRC calculator to ensure
* a correct type handling by the IP */
for(i = 0; i < (BufferLength/2); i++)
for(i = 0U; i < (BufferLength/2U); i++)
{
hcrc->Instance->DR = ((uint32_t)pBuffer[2*i]<<16) | (uint32_t)pBuffer[2*i+1];
hcrc->Instance->DR = ((uint32_t)pBuffer[2U*i]<<16U) | (uint32_t)pBuffer[2U*i+1U];
}
if ((BufferLength%2) != 0)
if ((BufferLength%2U) != 0U)
{
*(uint16_t volatile*) (&hcrc->Instance->DR) = pBuffer[2*i];
*(uint16_t volatile*) (&hcrc->Instance->DR) = pBuffer[2U*i];
}
/* Return the CRC computed value */

44
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_crc.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx_hal_crc.h
* @author MCD Application Team
* @version V1.5.0
* @date 8-January-2016
* @version V1.7.0
* @date 31-May-2016
* @brief Header file of CRC HAL module.
******************************************************************************
* @attention
@ -64,11 +64,11 @@
*/
typedef enum
{
HAL_CRC_STATE_RESET = 0x00, /*!< CRC not yet initialized or disabled */
HAL_CRC_STATE_READY = 0x01, /*!< CRC initialized and ready for use */
HAL_CRC_STATE_BUSY = 0x02, /*!< CRC internal process is ongoing */
HAL_CRC_STATE_TIMEOUT = 0x03, /*!< CRC timeout state */
HAL_CRC_STATE_ERROR = 0x04 /*!< CRC error state */
HAL_CRC_STATE_RESET = 0x00U, /*!< CRC not yet initialized or disabled */
HAL_CRC_STATE_READY = 0x01U, /*!< CRC initialized and ready for use */
HAL_CRC_STATE_BUSY = 0x02U, /*!< CRC internal process is ongoing */
HAL_CRC_STATE_TIMEOUT = 0x03U, /*!< CRC timeout state */
HAL_CRC_STATE_ERROR = 0x04U /*!< CRC error state */
}HAL_CRC_StateTypeDef;
@ -151,7 +151,7 @@ typedef struct
/** @defgroup CRC_Default_Polynomial_Value Default CRC generating polynomial
* @{
*/
#define DEFAULT_CRC32_POLY 0x04C11DB7
#define DEFAULT_CRC32_POLY 0x04C11DB7U
/**
* @}
@ -160,7 +160,7 @@ typedef struct
/** @defgroup CRC_Default_InitValue Default CRC computation initialization value
* @{
*/
#define DEFAULT_CRC_INITVALUE 0xFFFFFFFF
#define DEFAULT_CRC_INITVALUE 0xFFFFFFFFU
/**
* @}
@ -169,8 +169,8 @@ typedef struct
/** @defgroup CRC_Default_Polynomial Indicates whether or not default polynomial is used
* @{
*/
#define DEFAULT_POLYNOMIAL_ENABLE ((uint8_t)0x00)
#define DEFAULT_POLYNOMIAL_DISABLE ((uint8_t)0x01)
#define DEFAULT_POLYNOMIAL_ENABLE ((uint8_t)0x00U)
#define DEFAULT_POLYNOMIAL_DISABLE ((uint8_t)0x01U)
/**
* @}
@ -179,8 +179,8 @@ typedef struct
/** @defgroup CRC_Default_InitValue_Use Indicates whether or not default init value is used
* @{
*/
#define DEFAULT_INIT_VALUE_ENABLE ((uint8_t)0x00)
#define DEFAULT_INIT_VALUE_DISABLE ((uint8_t)0x01)
#define DEFAULT_INIT_VALUE_ENABLE ((uint8_t)0x00U)
#define DEFAULT_INIT_VALUE_DISABLE ((uint8_t)0x01U)
/**
@ -190,7 +190,7 @@ typedef struct
/** @defgroup CRC_Polynomial_Sizes Polynomial sizes to configure the IP
* @{
*/
#define CRC_POLYLENGTH_32B ((uint32_t)0x00000000)
#define CRC_POLYLENGTH_32B ((uint32_t)0x00000000U)
#define CRC_POLYLENGTH_16B ((uint32_t)CRC_CR_POLYSIZE_0)
#define CRC_POLYLENGTH_8B ((uint32_t)CRC_CR_POLYSIZE_1)
#define CRC_POLYLENGTH_7B ((uint32_t)CRC_CR_POLYSIZE)
@ -201,10 +201,10 @@ typedef struct
/** @defgroup CRC_Polynomial_Size_Definitions CRC polynomial possible sizes actual definitions
* @{
*/
#define HAL_CRC_LENGTH_32B 32
#define HAL_CRC_LENGTH_16B 16
#define HAL_CRC_LENGTH_8B 8
#define HAL_CRC_LENGTH_7B 7
#define HAL_CRC_LENGTH_32B 32U
#define HAL_CRC_LENGTH_16B 16U
#define HAL_CRC_LENGTH_8B 8U
#define HAL_CRC_LENGTH_7B 7U
/**
* @}
@ -217,10 +217,10 @@ typedef struct
* an error is triggered in HAL_CRC_Init() if InputDataFormat field is set
* to CRC_INPUT_FORMAT_UNDEFINED: the format MUST be defined by the user for
* the CRC APIs to provide a correct result */
#define CRC_INPUTDATA_FORMAT_UNDEFINED ((uint32_t)0x00000000)
#define CRC_INPUTDATA_FORMAT_BYTES ((uint32_t)0x00000001)
#define CRC_INPUTDATA_FORMAT_HALFWORDS ((uint32_t)0x00000002)
#define CRC_INPUTDATA_FORMAT_WORDS ((uint32_t)0x00000003)
#define CRC_INPUTDATA_FORMAT_UNDEFINED ((uint32_t)0x00000000U)
#define CRC_INPUTDATA_FORMAT_BYTES ((uint32_t)0x00000001U)
#define CRC_INPUTDATA_FORMAT_HALFWORDS ((uint32_t)0x00000002U)
#define CRC_INPUTDATA_FORMAT_WORDS ((uint32_t)0x00000003U)
/**
* @}

8
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_crc_ex.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx_hal_crc_ex.c
* @author MCD Application Team
* @version V1.5.0
* @date 8-January-2016
* @version V1.7.0
* @date 31-May-2016
* @brief Extended CRC HAL module driver.
*
* This file provides firmware functions to manage the following
@ -108,7 +108,7 @@ This subsection provides function allowing to:
*/
HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength)
{
uint32_t msb = 31; /* polynomial degree is 32 at most, so msb is initialized to max value */
uint32_t msb = 31U; /* polynomial degree is 32 at most, so msb is initialized to max value */
/* Check the parameters */
assert_param(IS_CRC_POL_LENGTH(PolyLength));
@ -120,7 +120,7 @@ HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol
* Look for MSB position: msb will contain the degree of
* the second to the largest polynomial member. E.g., for
* X^7 + X^6 + X^5 + X^2 + 1, msb = 6. */
while (((Pol & ((uint32_t)(0x1) << msb)) == 0) && (msb-- > 0));
while (((Pol & ((uint32_t)(0x1U) << msb)) == 0U) && (msb-- > 0U));
switch (PolyLength)
{

8
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_crc_ex.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx_hal_crc_ex.h
* @author MCD Application Team
* @version V1.5.0
* @date 8-January-2016
* @version V1.7.0
* @date 31-May-2016
* @brief Header file of CRC HAL extension module.
******************************************************************************
* @attention
@ -64,7 +64,7 @@
/** @defgroup CRCEx_Input_Data_Inversion CRC Extended input data inversion modes
* @{
*/
#define CRC_INPUTDATA_INVERSION_NONE ((uint32_t)0x00000000)
#define CRC_INPUTDATA_INVERSION_NONE ((uint32_t)0x00000000U)
#define CRC_INPUTDATA_INVERSION_BYTE ((uint32_t)CRC_CR_REV_IN_0)
#define CRC_INPUTDATA_INVERSION_HALFWORD ((uint32_t)CRC_CR_REV_IN_1)
#define CRC_INPUTDATA_INVERSION_WORD ((uint32_t)CRC_CR_REV_IN)
@ -76,7 +76,7 @@
/** @defgroup CRCEx_Output_Data_Inversion CRC Extended output data inversion modes
* @{
*/
#define CRC_OUTPUTDATA_INVERSION_DISABLE ((uint32_t)0x00000000)
#define CRC_OUTPUTDATA_INVERSION_DISABLE ((uint32_t)0x00000000U)
#define CRC_OUTPUTDATA_INVERSION_ENABLE ((uint32_t)CRC_CR_REV_OUT)
/**
* @}

194
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_cryp.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx_hal_cryp.c
* @author MCD Application Team
* @version V1.5.0
* @date 8-January-2016
* @version V1.7.0
* @date 31-May-2016
* @brief CRYP HAL module driver.
*
* This file provides firmware functions to manage the following
@ -97,7 +97,7 @@
******************************************************************************
*/
#if defined (STM32L021xx) || defined (STM32L041xx) || defined (STM32L061xx) || defined (STM32L062xx) || defined (STM32L063xx) || (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
#if defined (STM32L021xx) || defined (STM32L041xx) || defined (STM32L061xx) || defined (STM32L062xx) || defined (STM32L063xx) || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
/* Includes ------------------------------------------------------------------*/
#include "stm32l0xx_hal.h"
@ -208,8 +208,8 @@ HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp)
MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, hcryp->Init.DataType);
/* Reset CrypInCount and CrypOutCount */
hcryp->CrypInCount = 0;
hcryp->CrypOutCount = 0;
hcryp->CrypInCount = 0U;
hcryp->CrypOutCount = 0U;
/* Change the CRYP state */
hcryp->State = HAL_CRYP_STATE_READY;
@ -252,8 +252,8 @@ HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp)
hcryp->Phase = HAL_CRYP_PHASE_READY;
/* Reset CrypInCount and CrypOutCount */
hcryp->CrypInCount = 0;
hcryp->CrypOutCount = 0;
hcryp->CrypInCount = 0U;
hcryp->CrypOutCount = 0U;
/* Disable the CRYP Peripheral Clock */
__HAL_CRYP_DISABLE(hcryp);
@ -341,7 +341,7 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pP
__HAL_LOCK(hcryp);
/* Check that data aligned on u32 and Size multiple of 16*/
if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0))
if((((uint32_t)pPlainData & (uint32_t)0x00000003U) != 0U) || (((uint32_t)pCypherData & (uint32_t)0x00000003U) != 0U) || ((Size & (uint16_t)0x000FU) != 0U))
{
/* Process Locked */
__HAL_UNLOCK(hcryp);
@ -417,7 +417,7 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pP
__HAL_LOCK(hcryp);
/* Check that data aligned on u32 */
if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0))
if((((uint32_t)pPlainData & (uint32_t)0x00000003U) != 0U) || (((uint32_t)pCypherData & (uint32_t)0x00000003U) != 0U) || ((Size & (uint16_t)0x000FU) != 0U))
{
/* Process Locked */
__HAL_UNLOCK(hcryp);
@ -496,7 +496,7 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pP
__HAL_LOCK(hcryp);
/* Check that data aligned on u32 */
if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0))
if((((uint32_t)pPlainData & (uint32_t)0x00000003U) != 0U) || (((uint32_t)pCypherData & (uint32_t)0x00000003U) != 0U) || ((Size & (uint16_t)0x000FU) != 0U))
{
/* Process Locked */
__HAL_UNLOCK(hcryp);
@ -575,7 +575,7 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pC
__HAL_LOCK(hcryp);
/* Check that data aligned on u32 */
if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0))
if((((uint32_t)pPlainData & (uint32_t)0x00000003U) != 0U) || (((uint32_t)pCypherData & (uint32_t)0x00000003U) != 0U) || ((Size & (uint16_t)0x000FU) != 0U))
{
/* Process Locked */
__HAL_UNLOCK(hcryp);
@ -651,7 +651,7 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pC
__HAL_LOCK(hcryp);
/* Check that data aligned on u32 */
if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0))
if((((uint32_t)pPlainData & (uint32_t)0x00000003U) != 0U) || (((uint32_t)pCypherData & (uint32_t)0x00000003U) != 0U) || ((Size & (uint16_t)0x000FU) != 0U))
{
/* Process Locked */
__HAL_UNLOCK(hcryp);
@ -730,7 +730,7 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pC
__HAL_LOCK(hcryp);
/* Check that data aligned on u32 */
if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0))
if((((uint32_t)pPlainData & (uint32_t)0x00000003U) != 0U) || (((uint32_t)pCypherData & (uint32_t)0x00000003U) != 0U) || ((Size & (uint16_t)0x000FU) != 0U))
{
/* Process Locked */
__HAL_UNLOCK(hcryp);
@ -791,10 +791,10 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pC
*/
HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
{
uint32_t inputaddr = 0;
uint32_t inputaddr = 0U;
/* Check that data aligned on u32 */
if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0))
if((((uint32_t)pPlainData & (uint32_t)0x00000003U) != 0U) || (((uint32_t)pCypherData & (uint32_t)0x00000003U) != 0U) || ((Size & (uint16_t)0x000FU) != 0U))
{
/* Process Locked */
__HAL_UNLOCK(hcryp);
@ -844,14 +844,14 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t
/* Write the Input block in the Data Input register */
hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
inputaddr+=4;
inputaddr+=4U;
hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
inputaddr+=4;
inputaddr+=4U;
hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
inputaddr+=4;
inputaddr+=4U;
hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
hcryp->pCrypInBuffPtr += 16;
hcryp->CrypInCount -= 16;
hcryp->pCrypInBuffPtr += 16U;
hcryp->CrypInCount -= 16U;
/* Return function status */
return HAL_OK;
@ -877,10 +877,10 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t
*/
HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
{
uint32_t inputaddr = 0;
uint32_t inputaddr = 0U;
/* Check that data aligned on u32 */
if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0))
if((((uint32_t)pPlainData & (uint32_t)0x00000003U) != 0U) || (((uint32_t)pCypherData & (uint32_t)0x00000003U) != 0U) || ((Size & (uint16_t)0x000FU) != 0U))
{
/* Process Locked */
__HAL_UNLOCK(hcryp);
@ -933,14 +933,14 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t
/* Write the Input block in the Data Input register */
hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
inputaddr+=4;
inputaddr+=4U;
hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
inputaddr+=4;
inputaddr+=4U;
hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
inputaddr+=4;
inputaddr+=4U;
hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
hcryp->pCrypInBuffPtr += 16;
hcryp->CrypInCount -= 16;
hcryp->pCrypInBuffPtr += 16U;
hcryp->CrypInCount -= 16U;
/* Return function status */
return HAL_OK;
@ -966,10 +966,10 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t
*/
HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
{
uint32_t inputaddr = 0;
uint32_t inputaddr = 0U;
/* Check that data aligned on u32 */
if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0))
if((((uint32_t)pPlainData & (uint32_t)0x00000003U) != 0U) || (((uint32_t)pCypherData & (uint32_t)0x00000003U) != 0U) || ((Size & (uint16_t)0x000FU) != 0U))
{
/* Process Locked */
__HAL_UNLOCK(hcryp);
@ -1022,14 +1022,14 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t
/* Write the Input block in the Data Input register */
hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
inputaddr+=4;
inputaddr+=4U;
hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
inputaddr+=4;
inputaddr+=4U;
hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
inputaddr+=4;
inputaddr+=4U;
hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
hcryp->pCrypInBuffPtr += 16;
hcryp->CrypInCount -= 16;
hcryp->pCrypInBuffPtr += 16U;
hcryp->CrypInCount -= 16U;
/* Return function status */
return HAL_OK;
@ -1055,10 +1055,10 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t
*/
HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
{
uint32_t inputaddr = 0;
uint32_t inputaddr = 0U;
/* Check that data aligned on u32 */
if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0))
if((((uint32_t)pPlainData & (uint32_t)0x00000003U) != 0U) || (((uint32_t)pCypherData & (uint32_t)0x00000003U) != 0U) || ((Size & (uint16_t)0x000FU) != 0U))
{
/* Process Locked */
__HAL_UNLOCK(hcryp);
@ -1108,14 +1108,14 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t
/* Write the Input block in the Data Input register */
hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
inputaddr+=4;
inputaddr+=4U;
hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
inputaddr+=4;
inputaddr+=4U;
hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
inputaddr+=4;
inputaddr+=4U;
hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
hcryp->pCrypInBuffPtr += 16;
hcryp->CrypInCount -= 16;
hcryp->pCrypInBuffPtr += 16U;
hcryp->CrypInCount -= 16U;
/* Return function status */
return HAL_OK;
@ -1141,10 +1141,10 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t
*/
HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
{
uint32_t inputaddr = 0;
uint32_t inputaddr = 0U;
/* Check that data aligned on u32 */
if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0))
if((((uint32_t)pPlainData & (uint32_t)0x00000003U) != 0U) || (((uint32_t)pCypherData & (uint32_t)0x00000003U) != 0U) || ((Size & (uint16_t)0x000FU) != 0U))
{
/* Process Locked */
__HAL_UNLOCK(hcryp);
@ -1197,14 +1197,14 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t
/* Write the Input block in the Data Input register */
hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
inputaddr+=4;
inputaddr+=4U;
hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
inputaddr+=4;
inputaddr+=4U;
hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
inputaddr+=4;
inputaddr+=4U;
hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
hcryp->pCrypInBuffPtr += 16;
hcryp->CrypInCount -= 16;
hcryp->pCrypInBuffPtr += 16U;
hcryp->CrypInCount -= 16U;
/* Return function status */
return HAL_OK;
@ -1230,10 +1230,10 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t
*/
HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
{
uint32_t inputaddr = 0;
uint32_t inputaddr = 0U;
/* Check that data aligned on u32 */
if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0))
if((((uint32_t)pPlainData & (uint32_t)0x00000003U) != 0U) || (((uint32_t)pCypherData & (uint32_t)0x00000003U) != 0U) || ((Size & (uint16_t)0x000FU) != 0U))
{
/* Process Locked */
__HAL_UNLOCK(hcryp);
@ -1286,14 +1286,14 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t
/* Write the Input block in the Data Input register */
hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
inputaddr+=4;
inputaddr+=4U;
hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
inputaddr+=4;
inputaddr+=4U;
hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
inputaddr+=4;
inputaddr+=4U;
hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
hcryp->pCrypInBuffPtr += 16;
hcryp->CrypInCount -= 16;
hcryp->pCrypInBuffPtr += 16U;
hcryp->CrypInCount -= 16U;
/* Return function status */
return HAL_OK;
@ -1319,10 +1319,10 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t
*/
HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
{
uint32_t inputaddr = 0, outputaddr = 0;
uint32_t inputaddr = 0U, outputaddr = 0U;
/* Check that data aligned on u32 */
if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0))
if((((uint32_t)pPlainData & (uint32_t)0x00000003U) != 0U) || (((uint32_t)pCypherData & (uint32_t)0x00000003U) != 0U) || ((Size & (uint16_t)0x000FU) != 0U))
{
/* Process Locked */
__HAL_UNLOCK(hcryp);
@ -1384,10 +1384,10 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t
*/
HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
{
uint32_t inputaddr = 0, outputaddr = 0;
uint32_t inputaddr = 0U, outputaddr = 0U;
/* Check that data aligned on u32 */
if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0))
if((((uint32_t)pPlainData & (uint32_t)0x00000003U) != 0U) || (((uint32_t)pCypherData & (uint32_t)0x00000003U) != 0U) || ((Size & (uint16_t)0x000FU) != 0U))
{
/* Process Locked */
__HAL_UNLOCK(hcryp);
@ -1452,10 +1452,10 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t
*/
HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
{
uint32_t inputaddr = 0, outputaddr = 0;
uint32_t inputaddr = 0U, outputaddr = 0U;
/* Check that data aligned on u32 */
if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0))
if((((uint32_t)pPlainData & (uint32_t)0x00000003U) != 0U) || (((uint32_t)pCypherData & (uint32_t)0x00000003U) != 0U) || ((Size & (uint16_t)0x000FU) != 0U))
{
/* Process Locked */
__HAL_UNLOCK(hcryp);
@ -1521,10 +1521,10 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t
*/
HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
{
uint32_t inputaddr = 0, outputaddr = 0;
uint32_t inputaddr = 0U, outputaddr = 0U;
/* Check that data aligned on u32 */
if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0))
if((((uint32_t)pPlainData & (uint32_t)0x00000003U) != 0U) || (((uint32_t)pCypherData & (uint32_t)0x00000003U) != 0U) || ((Size & (uint16_t)0x000FU) != 0U))
{
/* Process Locked */
__HAL_UNLOCK(hcryp);
@ -1590,10 +1590,10 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t
*/
HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
{
uint32_t inputaddr = 0, outputaddr = 0;
uint32_t inputaddr = 0U, outputaddr = 0U;
/* Check that data aligned on u32 */
if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0))
if((((uint32_t)pPlainData & (uint32_t)0x00000003U) != 0U) || (((uint32_t)pCypherData & (uint32_t)0x00000003U) != 0U) || ((Size & (uint16_t)0x000FU) != 0U))
{
/* Process Locked */
__HAL_UNLOCK(hcryp);
@ -1662,10 +1662,10 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t
*/
HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
{
uint32_t inputaddr = 0, outputaddr = 0;
uint32_t inputaddr = 0U, outputaddr = 0U;
/* Check that data aligned on u32 */
if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0))
if((((uint32_t)pPlainData & (uint32_t)0x00000003U) != 0U) || (((uint32_t)pCypherData & (uint32_t)0x00000003U) != 0U) || ((Size & (uint16_t)0x000FU) != 0U))
{
/* Process Locked */
__HAL_UNLOCK(hcryp);
@ -1903,25 +1903,25 @@ HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp)
*/
static HAL_StatusTypeDef CRYP_EncryptDecrypt_IT(CRYP_HandleTypeDef *hcryp)
{
uint32_t inputaddr = 0, outputaddr = 0;
uint32_t inputaddr = 0U, outputaddr = 0U;
/* Get the last Output data adress */
outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
/* Read the Output block from the Output Register */
*(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
outputaddr+=4;
outputaddr+=4U;
*(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
outputaddr+=4;
outputaddr+=4U;
*(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
outputaddr+=4;
outputaddr+=4U;
*(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
hcryp->pCrypOutBuffPtr += 16;
hcryp->CrypOutCount -= 16;
hcryp->pCrypOutBuffPtr += 16U;
hcryp->CrypOutCount -= 16U;
/* Check if all input text is encrypted or decrypted */
if(hcryp->CrypOutCount == 0)
if(hcryp->CrypOutCount == 0U)
{
/* Disable Computation Complete Interrupt */
__HAL_CRYP_DISABLE_IT(hcryp,CRYP_IT_CC);
@ -1943,14 +1943,14 @@ static HAL_StatusTypeDef CRYP_EncryptDecrypt_IT(CRYP_HandleTypeDef *hcryp)
/* Write the Input block in the Data Input register */
hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
inputaddr+=4;
inputaddr+=4U;
hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
inputaddr+=4;
inputaddr+=4U;
hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
inputaddr+=4;
inputaddr+=4U;
hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
hcryp->pCrypInBuffPtr += 16;
hcryp->CrypInCount -= 16;
hcryp->pCrypInBuffPtr += 16U;
hcryp->CrypInCount -= 16U;
}
return HAL_OK;
}
@ -2026,11 +2026,11 @@ static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint8_t *Key)
uint32_t keyaddr = (uint32_t)Key;
hcryp->Instance->KEYR3 = __REV(*(uint32_t*)(keyaddr));
keyaddr+=4;
keyaddr+=4U;
hcryp->Instance->KEYR2 = __REV(*(uint32_t*)(keyaddr));
keyaddr+=4;
keyaddr+=4U;
hcryp->Instance->KEYR1 = __REV(*(uint32_t*)(keyaddr));
keyaddr+=4;
keyaddr+=4U;
hcryp->Instance->KEYR0 = __REV(*(uint32_t*)(keyaddr));
}
@ -2052,11 +2052,11 @@ static void CRYP_SetInitVector(CRYP_HandleTypeDef *hcryp, uint8_t *InitVector)
uint32_t ivaddr = (uint32_t)InitVector;
hcryp->Instance->IVR3 = __REV(*(uint32_t*)(ivaddr));
ivaddr+=4;
ivaddr+=4U;
hcryp->Instance->IVR2 = __REV(*(uint32_t*)(ivaddr));
ivaddr+=4;
ivaddr+=4U;
hcryp->Instance->IVR1 = __REV(*(uint32_t*)(ivaddr));
ivaddr+=4;
ivaddr+=4U;
hcryp->Instance->IVR0 = __REV(*(uint32_t*)(ivaddr));
}
@ -2072,23 +2072,23 @@ static void CRYP_SetInitVector(CRYP_HandleTypeDef *hcryp, uint8_t *InitVector)
*/
static HAL_StatusTypeDef CRYP_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout)
{
uint32_t tickstart = 0;
uint32_t tickstart = 0U;
uint32_t index = 0;
uint32_t index = 0U;
uint32_t inputaddr = (uint32_t)Input;
uint32_t outputaddr = (uint32_t)Output;
for(index=0; (index < Ilength); index += 16)
for(index=0U; (index < Ilength); index += 16U)
{
/* Write the Input block in the Data Input register */
hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
inputaddr+=4;
inputaddr+=4U;
hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
inputaddr+=4;
inputaddr+=4U;
hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
inputaddr+=4;
inputaddr+=4U;
hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
inputaddr+=4;
inputaddr+=4U;
/* Get timeout */
tickstart = HAL_GetTick();
@ -2098,7 +2098,7 @@ static HAL_StatusTypeDef CRYP_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t* In
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
{
if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
{
/* Change state */
hcryp->State = HAL_CRYP_STATE_TIMEOUT;
@ -2115,13 +2115,13 @@ static HAL_StatusTypeDef CRYP_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t* In
/* Read the Output block from the Data Output Register */
*(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
outputaddr+=4;
outputaddr+=4U;
*(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
outputaddr+=4;
outputaddr+=4U;
*(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
outputaddr+=4;
outputaddr+=4U;
*(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
outputaddr+=4;
outputaddr+=4U;
}
/* Return function status */
return HAL_OK;

22
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_cryp.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx_hal_cryp.h
* @author MCD Application Team
* @version V1.5.0
* @date 8-January-2016
* @version V1.7.0
* @date 31-May-2016
* @brief Header file of CRYP HAL module.
******************************************************************************
* @attention
@ -82,11 +82,11 @@ typedef struct
*/
typedef enum
{
HAL_CRYP_STATE_RESET = 0x00, /*!< CRYP not yet initialized or disabled */
HAL_CRYP_STATE_READY = 0x01, /*!< CRYP initialized and ready for use */
HAL_CRYP_STATE_BUSY = 0x02, /*!< CRYP internal processing is ongoing */
HAL_CRYP_STATE_TIMEOUT = 0x03, /*!< CRYP timeout state */
HAL_CRYP_STATE_ERROR = 0x04 /*!< CRYP error state */
HAL_CRYP_STATE_RESET = 0x00U, /*!< CRYP not yet initialized or disabled */
HAL_CRYP_STATE_READY = 0x01U, /*!< CRYP initialized and ready for use */
HAL_CRYP_STATE_BUSY = 0x02U, /*!< CRYP internal processing is ongoing */
HAL_CRYP_STATE_TIMEOUT = 0x03U, /*!< CRYP timeout state */
HAL_CRYP_STATE_ERROR = 0x04U /*!< CRYP error state */
}HAL_CRYP_STATETypeDef;
@ -95,8 +95,8 @@ typedef enum
*/
typedef enum
{
HAL_CRYP_PHASE_READY = 0x01, /*!< CRYP peripheral is ready for initialization. */
HAL_CRYP_PHASE_PROCESS = 0x02, /*!< CRYP peripheral is in processing phase */
HAL_CRYP_PHASE_READY = 0x01U, /*!< CRYP peripheral is ready for initialization. */
HAL_CRYP_PHASE_PROCESS = 0x02U, /*!< CRYP peripheral is in processing phase */
}HAL_PhaseTypeDef;
/**
@ -143,7 +143,7 @@ typedef struct
/** @defgroup CRYP_Data_Type CRYP Data Type
* @{
*/
#define CRYP_DATATYPE_32B ((uint32_t)0x00000000)
#define CRYP_DATATYPE_32B ((uint32_t)0x00000000U)
#define CRYP_DATATYPE_16B AES_CR_DATATYPE_0
#define CRYP_DATATYPE_8B AES_CR_DATATYPE_1
#define CRYP_DATATYPE_1B AES_CR_DATATYPE
@ -161,7 +161,7 @@ typedef struct
*/
#define CRYP_CR_ALGOMODE_DIRECTION (uint32_t)(AES_CR_MODE|AES_CR_CHMOD)
#define CRYP_CR_ALGOMODE_AES_ECB_ENCRYPT ((uint32_t)0x00000000)
#define CRYP_CR_ALGOMODE_AES_ECB_ENCRYPT ((uint32_t)0x00000000U)
#define CRYP_CR_ALGOMODE_AES_ECB_KEYDERDECRYPT (AES_CR_MODE)
#define CRYP_CR_ALGOMODE_AES_CBC_ENCRYPT (AES_CR_CHMOD_0)
#define CRYP_CR_ALGOMODE_AES_CBC_KEYDERDECRYPT ((uint32_t)(AES_CR_CHMOD_0|AES_CR_MODE))

6
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_cryp_ex.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx_hal_cryp_ex.c
* @author MCD Application Team
* @version V1.5.0
* @date 8-January-2016
* @version V1.7.0
* @date 31-May-2016
* @brief CRYPEx HAL module driver.
*
* This file provides firmware functions to manage the following
@ -40,7 +40,7 @@
******************************************************************************
*/
#if defined (STM32L021xx) ||defined (STM32L041xx) || defined (STM32L061xx) || defined (STM32L062xx) || defined (STM32L063xx) || (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
#if defined (STM32L021xx) ||defined (STM32L041xx) || defined (STM32L061xx) || defined (STM32L062xx) || defined (STM32L063xx) || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
/* Includes ------------------------------------------------------------------*/
#include "stm32l0xx_hal.h"

4
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_cryp_ex.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx_hal_cryp_ex.h
* @author MCD Application Team
* @version V1.5.0
* @date 8-January-2016
* @version V1.7.0
* @date 31-May-2016
* @brief Header file of CRYPEx HAL module.
******************************************************************************
* @attention

8
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_dac.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx_hal_dac.c
* @author MCD Application Team
* @version V1.5.0
* @date 8-January-2016
* @version V1.7.0
* @date 31-May-2016
* @brief DAC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Digital to Analog Converter (DAC) peripheral:
@ -481,7 +481,7 @@ __weak uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel)
/* Function content is located into file stm32l0xx_hal_dac_ex.c */
/* Return function status */
return 0;
return 0U;
}
/**
@ -596,7 +596,7 @@ __weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac)
*/
HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel)
{
uint32_t tmpreg1 = 0, tmpreg2 = 0;
uint32_t tmpreg1 = 0U, tmpreg2 = 0U;
/* Check the DAC parameters */
assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger));

44
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_dac.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx_hal_dac.h
* @author MCD Application Team
* @version V1.5.0
* @date 8-January-2016
* @version V1.7.0
* @date 31-May-2016
* @brief Header file of DAC HAL module.
******************************************************************************
* @attention
@ -67,11 +67,11 @@
*/
typedef enum
{
HAL_DAC_STATE_RESET = 0x00, /*!< DAC not yet initialized or disabled */
HAL_DAC_STATE_READY = 0x01, /*!< DAC initialized and ready for use */
HAL_DAC_STATE_BUSY = 0x02, /*!< DAC internal processing is ongoing */
HAL_DAC_STATE_TIMEOUT = 0x03, /*!< DAC timeout state */
HAL_DAC_STATE_ERROR = 0x04 /*!< DAC error state */
HAL_DAC_STATE_RESET = 0x00U, /*!< DAC not yet initialized or disabled */
HAL_DAC_STATE_READY = 0x01U, /*!< DAC initialized and ready for use */
HAL_DAC_STATE_BUSY = 0x02U, /*!< DAC internal processing is ongoing */
HAL_DAC_STATE_TIMEOUT = 0x03U, /*!< DAC timeout state */
HAL_DAC_STATE_ERROR = 0x04U /*!< DAC error state */
}HAL_DAC_StateTypeDef;
@ -122,12 +122,12 @@ typedef struct
/** @defgroup DAC_Error_Code DAC Error Code
* @{
*/
#define HAL_DAC_ERROR_NONE 0x00 /*!< No error */
#define HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01 /*!< DAC channel1 DAM underrun error */
#define HAL_DAC_ERROR_NONE 0x00U /*!< No error */
#define HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01U /*!< DAC channel1 DAM underrun error */
#if defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L082xx) || defined (STM32L083xx)
#define HAL_DAC_ERROR_DMAUNDERRUNCH2 0x02 /*!< DAC channel2 DAM underrun error */
#define HAL_DAC_ERROR_DMAUNDERRUNCH2 0x02U /*!< DAC channel2 DAM underrun error */
#endif
#define HAL_DAC_ERROR_DMA 0x04 /*!< DMA error */
#define HAL_DAC_ERROR_DMA 0x04U /*!< DMA error */
/**
* @}
*/
@ -135,7 +135,7 @@ typedef struct
/** @defgroup DAC_trigger_selection DAC trigger selection
* @{
*/
#define DAC_TRIGGER_NONE ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register has been loaded, and not by external trigger */
#define DAC_TRIGGER_NONE ((uint32_t)0x00000000U) /*!< Conversion is automatic once the DAC1_DHRxxxx register has been loaded, and not by external trigger */
#define DAC_TRIGGER_T6_TRGO ((uint32_t) DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_T21_TRGO ((uint32_t)( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM21 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
@ -173,7 +173,7 @@ typedef struct
/** @defgroup DAC_output_buffer DAC output buffer
* @{
*/
#define DAC_OUTPUTBUFFER_ENABLE ((uint32_t)0x00000000)
#define DAC_OUTPUTBUFFER_ENABLE ((uint32_t)0x00000000U)
#define DAC_OUTPUTBUFFER_DISABLE ((uint32_t)DAC_CR_BOFF1)
#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \
@ -185,9 +185,9 @@ typedef struct
/** @defgroup DAC_Channel_selection DAC Channel selection
* @{
*/
#define DAC_CHANNEL_1 ((uint32_t)0x00000000)
#define DAC_CHANNEL_1 ((uint32_t)0x00000000U)
#if defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L082xx) || defined (STM32L083xx)
#define DAC_CHANNEL_2 ((uint32_t)0x00000010)
#define DAC_CHANNEL_2 ((uint32_t)0x00000010U)
#endif
#if defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L082xx) || defined (STM32L083xx)
@ -203,9 +203,9 @@ typedef struct
/** @defgroup DAC_data_alignement DAC data alignement
* @{
*/
#define DAC_ALIGN_12B_R ((uint32_t)0x00000000)
#define DAC_ALIGN_12B_L ((uint32_t)0x00000004)
#define DAC_ALIGN_8B_R ((uint32_t)0x00000008)
#define DAC_ALIGN_12B_R ((uint32_t)0x00000000U)
#define DAC_ALIGN_12B_L ((uint32_t)0x00000004U)
#define DAC_ALIGN_8B_R ((uint32_t)0x00000008U)
#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \
((ALIGN) == DAC_ALIGN_12B_L) || \
@ -217,7 +217,7 @@ typedef struct
/** @defgroup DAC_data DAC data
* @{
*/
#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0)
#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0U)
/**
* @}
*/
@ -332,19 +332,19 @@ CLEAR_BIT((__HANDLE__)->Instance->CR, __INTERRUPT__)
* @param __ALIGNEMENT__: specifies the DAC alignement
* @retval None
*/
#define DAC_DHR12R1_ALIGNEMENT(__ALIGNEMENT__) (((uint32_t)0x00000008) + (__ALIGNEMENT__))
#define DAC_DHR12R1_ALIGNEMENT(__ALIGNEMENT__) (((uint32_t)0x00000008U) + (__ALIGNEMENT__))
/** @brief Set DHR12R2 alignment
* @param __ALIGNEMENT__: specifies the DAC alignement
* @retval None
*/
#define DAC_DHR12R2_ALIGNEMENT(__ALIGNEMENT__) (((uint32_t)0x00000014) + (__ALIGNEMENT__))
#define DAC_DHR12R2_ALIGNEMENT(__ALIGNEMENT__) (((uint32_t)0x00000014U) + (__ALIGNEMENT__))
/** @brief Set DHR12RD alignment
* @param __ALIGNEMENT__: specifies the DAC alignement
* @retval None
*/
#define DAC_DHR12RD_ALIGNEMENT(__ALIGNEMENT__) (((uint32_t)0x00000020) + (__ALIGNEMENT__))
#define DAC_DHR12RD_ALIGNEMENT(__ALIGNEMENT__) (((uint32_t)0x00000020U) + (__ALIGNEMENT__))
/** @brief Enable the DAC interrupt
* @param __HANDLE__: specifies the DAC handle

26
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_dac_ex.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx_hal_dac_ex.c
* @author MCD Application Team
* @version V1.5.0
* @date 8-January-2016
* @version V1.7.0
* @date 31-May-2016
* @brief Extended DAC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of DAC extension peripheral:
@ -110,11 +110,11 @@ static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma);
*/
uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac)
{
uint32_t tmp = 0;
uint32_t tmp = 0U;
tmp |= hdac->Instance->DOR1;
tmp |= hdac->Instance->DOR2 << 16;
tmp |= hdac->Instance->DOR2 << 16U;
/* Returns the DAC channel data output register value */
return tmp;
@ -238,7 +238,7 @@ HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t
*/
HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2)
{
uint32_t data = 0, tmp = 0;
uint32_t data = 0U, tmp = 0U;
/* Check the parameters */
assert_param(IS_DAC_ALIGN(Alignment));
@ -248,11 +248,11 @@ HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Align
/* Calculate and set dual DAC data holding register value */
if (Alignment == DAC_ALIGN_8B_R)
{
data = ((uint32_t)Data2 << 8) | Data1;
data = ((uint32_t)Data2 << 8U) | Data1;
}
else
{
data = ((uint32_t)Data2 << 16) | Data1;
data = ((uint32_t)Data2 << 16U) | Data1;
}
tmp = (uint32_t)hdac->Instance;
@ -342,7 +342,7 @@ __weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac)
*/
HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel)
{
uint32_t tmp1 = 0, tmp2 = 0;
uint32_t tmp1 = 0U, tmp2 = 0U;
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(Channel));
@ -408,7 +408,7 @@ HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel)
*/
HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment)
{
uint32_t tmpreg = 0;
uint32_t tmpreg = 0U;
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(Channel));
@ -658,7 +658,7 @@ void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac)
*/
HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data)
{
__IO uint32_t tmp = 0;
__IO uint32_t tmp = 0U;
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(Channel));
@ -694,7 +694,7 @@ HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, ui
*/
HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel)
{
uint32_t tmp1 = 0, tmp2 = 0;
uint32_t tmp1 = 0U, tmp2 = 0U;
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(Channel));
@ -745,7 +745,7 @@ HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel)
*/
HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment)
{
uint32_t tmpreg = 0;
uint32_t tmpreg = 0U;
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(Channel));
@ -910,7 +910,7 @@ void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac)
*/
HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data)
{
__IO uint32_t tmp = 0;
__IO uint32_t tmp = 0U;
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(Channel));

8
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_dac_ex.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx_hal_dac_ex.h
* @author MCD Application Team
* @version V1.5.0
* @date 8-January-2016
* @version V1.7.0
* @date 31-May-2016
* @brief Header file of DAC HAL Extension module.
******************************************************************************
* @attention
@ -67,7 +67,7 @@
/** @defgroup DACEx_lfsrunmask_triangleamplitude DACEx lfsrunmask triangleamplitude
* @{
*/
#define DAC_LFSRUNMASK_BIT0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
#define DAC_LFSRUNMASK_BIT0 ((uint32_t)0x00000000U) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
#define DAC_LFSRUNMASK_BITS1_0 ((uint32_t)DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
#define DAC_LFSRUNMASK_BITS2_0 ((uint32_t)DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
#define DAC_LFSRUNMASK_BITS3_0 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)/*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
@ -79,7 +79,7 @@
#define DAC_LFSRUNMASK_BITS9_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
#define DAC_LFSRUNMASK_BITS10_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
#define DAC_LFSRUNMASK_BITS11_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
#define DAC_TRIANGLEAMPLITUDE_1 ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */
#define DAC_TRIANGLEAMPLITUDE_1 ((uint32_t)0x00000000U) /*!< Select max triangle amplitude of 1 */
#define DAC_TRIANGLEAMPLITUDE_3 ((uint32_t)DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 3 */
#define DAC_TRIANGLEAMPLITUDE_7 ((uint32_t)DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 7 */
#define DAC_TRIANGLEAMPLITUDE_15 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 15 */

20
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_def.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx_hal_def.h
* @author MCD Application Team
* @version V1.5.0
* @date 8-January-2016
* @version V1.7.0
* @date 31-May-2016
* @brief This file contains HAL common defines, enumeration, macros and
* structures definitions.
******************************************************************************
@ -56,10 +56,10 @@
*/
typedef enum
{
HAL_OK = 0x00,
HAL_ERROR = 0x01,
HAL_BUSY = 0x02,
HAL_TIMEOUT = 0x03
HAL_OK = 0x00U,
HAL_ERROR = 0x01U,
HAL_BUSY = 0x02U,
HAL_TIMEOUT = 0x03U
} HAL_StatusTypeDef;
/**
@ -67,15 +67,15 @@ typedef enum
*/
typedef enum
{
HAL_UNLOCKED = 0x00,
HAL_LOCKED = 0x01
HAL_UNLOCKED = 0x00U,
HAL_LOCKED = 0x01U
} HAL_LockTypeDef;
/* Exported macro ------------------------------------------------------------*/
#define UNUSED(x) ((void)(x))
#define HAL_MAX_DELAY 0xFFFFFFFF
#define HAL_MAX_DELAY 0xFFFFFFFFU
#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) != RESET)
#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == RESET)
@ -101,7 +101,7 @@ typedef enum
* HAL_PPP_MspInit() which will reconfigure the low level hardware.
* @retval None
*/
#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0)
#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0U)
#if (USE_RTOS == 1)

40
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_dma.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx_hal_dma.c
* @author MCD Application Team
* @version V1.5.0
* @date 8-January-2016
* @version V1.7.0
* @date 31-May-2016
* @brief DMA HAL module driver.
*
* This file provides firmware functions to manage the following
@ -104,7 +104,7 @@
*
* @{
*/
#define HAL_TIMEOUT_DMA_ABORT ((uint32_t)1000) /* 1s */
#define HAL_TIMEOUT_DMA_ABORT ((uint32_t)1000U) /* 1s */
static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
@ -140,7 +140,7 @@ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t
*/
HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
{
uint32_t tmp = 0;
uint32_t tmp = 0U;
/* Check the DMA peripheral state */
if(hdma == NULL)
@ -200,7 +200,7 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
DMA1_CSELR->CSELR &= ~DMA_CSELR_C2S;
/* Configure request selection for DMA1 Channel2 */
DMA1_CSELR->CSELR |= (uint32_t)(hdma->Init.Request << 4);
DMA1_CSELR->CSELR |= (uint32_t)(hdma->Init.Request << 4U);
}
else if (hdma->Instance == DMA1_Channel3)
{
@ -208,7 +208,7 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
DMA1_CSELR->CSELR &= ~DMA_CSELR_C3S;
/* Configure request selection for DMA1 Channel3 */
DMA1_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << 8);
DMA1_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << 8U);
}
else if (hdma->Instance == DMA1_Channel4)
{
@ -216,7 +216,7 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
DMA1_CSELR->CSELR &= ~DMA_CSELR_C4S;
/* Configure request selection for DMA1 Channel4 */
DMA1_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << 12);
DMA1_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << 12U);
}
else if (hdma->Instance == DMA1_Channel5)
{
@ -224,7 +224,7 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
DMA1_CSELR->CSELR &= ~DMA_CSELR_C5S;
/* Configure request selection for DMA1 Channel5 */
DMA1_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << 16);
DMA1_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << 16U);
}
#if !defined (STM32L011xx) && !defined (STM32L021xx)
else if (hdma->Instance == DMA1_Channel6)
@ -233,7 +233,7 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
DMA1_CSELR->CSELR &= ~DMA_CSELR_C6S;
/* Configure request selection for DMA1 Channel6 */
DMA1_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << 20);
DMA1_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << 20U);
}
else if (hdma->Instance == DMA1_Channel7)
{
@ -241,7 +241,7 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
DMA1_CSELR->CSELR &= ~DMA_CSELR_C7S;
/* Configure request selection for DMA1 Channel7 */
DMA1_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << 24);
DMA1_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << 24U);
}
#endif
/* Initialize the DMA state*/
@ -274,16 +274,16 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
__HAL_DMA_DISABLE(hdma);
/* Reset DMA Channel control register */
hdma->Instance->CCR = 0;
hdma->Instance->CCR = 0U;
/* Reset DMA Channel Number of Data to Transfer register */
hdma->Instance->CNDTR = 0;
hdma->Instance->CNDTR = 0U;
/* Reset DMA Channel peripheral address register */
hdma->Instance->CPAR = 0;
hdma->Instance->CPAR = 0U;
/* Reset DMA Channel memory address register */
hdma->Instance->CMAR = 0;
hdma->Instance->CMAR = 0U;
/* Clear all flags */
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_GI_FLAG_INDEX(hdma));
@ -445,7 +445,7 @@ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress,
*/
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
{
uint32_t tickstart = 0;
uint32_t tickstart = 0U;
/* Disable the channel */
__HAL_DMA_DISABLE(hdma);
@ -454,7 +454,7 @@ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
tickstart = HAL_GetTick();
/* Check if the DMA Channel is effectively disabled */
while((hdma->Instance->CCR & DMA_CCR_EN) != 0)
while((hdma->Instance->CCR & DMA_CCR_EN) != 0U)
{
/* Check for the Timeout */
if( (HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT)
@ -491,7 +491,7 @@ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout)
{
uint32_t temp;
uint32_t tickstart = 0;
uint32_t tickstart = 0U;
/* Get the level transfer complete flag */
if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
@ -529,7 +529,7 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t Comp
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
{
if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
{
/* Update error code */
SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TIMEOUT);
@ -614,7 +614,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != RESET)
{
/* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0)
if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
{
/* Disable the half transfer interrupt */
__HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
@ -638,7 +638,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
{
if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != RESET)
{
if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0)
if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
{
/* Disable the transfer complete interrupt */
__HAL_DMA_DISABLE_IT(hdma, DMA_IT_TC);

162
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_dma.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx_hal_dma.h
* @author MCD Application Team
* @version V1.5.0
* @date 8-January-2016
* @version V1.7.0
* @date 31-May-2016
* @brief Header file of DMA HAL module.
******************************************************************************
* @attention
@ -101,8 +101,8 @@ typedef struct
*/
typedef enum
{
DMA_MODE = 0, /*!< Control related DMA mode Parameter in DMA_InitTypeDef */
DMA_PRIORITY = 1, /*!< Control related priority level Parameter in DMA_InitTypeDef */
DMA_MODE = 0U, /*!< Control related DMA mode Parameter in DMA_InitTypeDef */
DMA_PRIORITY = 1U, /*!< Control related priority level Parameter in DMA_InitTypeDef */
} DMA_ControlTypeDef;
@ -111,12 +111,12 @@ typedef enum
*/
typedef enum
{
HAL_DMA_STATE_RESET = 0x00, /*!< DMA not yet initialized or disabled */
HAL_DMA_STATE_READY = 0x01, /*!< DMA process success and ready for use */
HAL_DMA_STATE_BUSY = 0x02, /*!< DMA process is ongoing */
HAL_DMA_STATE_TIMEOUT = 0x03, /*!< DMA timeout state */
HAL_DMA_STATE_ERROR = 0x04, /*!< DMA error state */
HAL_DMA_STATE_READY_HALF = 0x05, /*!< DMA Half process success */
HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */
HAL_DMA_STATE_READY = 0x01U, /*!< DMA process success and ready for use */
HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */
HAL_DMA_STATE_TIMEOUT = 0x03U, /*!< DMA timeout state */
HAL_DMA_STATE_ERROR = 0x04U, /*!< DMA error state */
HAL_DMA_STATE_READY_HALF = 0x05U, /*!< DMA Half process success */
}HAL_DMA_StateTypeDef;
/**
@ -124,8 +124,8 @@ typedef enum
*/
typedef enum
{
HAL_DMA_FULL_TRANSFER = 0x00, /*!< Full transfer */
HAL_DMA_HALF_TRANSFER = 0x01, /*!< Half Transfer */
HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */
HAL_DMA_HALF_TRANSFER = 0x01U, /*!< Half Transfer */
}HAL_DMA_LevelCompleteTypeDef;
@ -168,9 +168,9 @@ typedef struct __DMA_HandleTypeDef
/** @defgroup DMA_Error_Code DMA Error Codes
* @{
*/
#define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
#define HAL_DMA_ERROR_TE ((uint32_t)0x00000001) /*!< Transfer error */
#define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */
#define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
#define HAL_DMA_ERROR_TE ((uint32_t)0x00000001U) /*!< Transfer error */
#define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020U) /*!< Timeout error */
#if defined (STM32L011xx) || defined (STM32L021xx)
#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
@ -200,22 +200,22 @@ typedef struct __DMA_HandleTypeDef
#if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
#define DMA_REQUEST_0 ((uint32_t)0x00000000)
#define DMA_REQUEST_1 ((uint32_t)0x00000001)
#define DMA_REQUEST_2 ((uint32_t)0x00000002)
#define DMA_REQUEST_3 ((uint32_t)0x00000003)
#define DMA_REQUEST_4 ((uint32_t)0x00000004)
#define DMA_REQUEST_5 ((uint32_t)0x00000005)
#define DMA_REQUEST_6 ((uint32_t)0x00000006)
#define DMA_REQUEST_7 ((uint32_t)0x00000007)
#define DMA_REQUEST_8 ((uint32_t)0x00000008)
#define DMA_REQUEST_9 ((uint32_t)0x00000009)
#define DMA_REQUEST_10 ((uint32_t)0x0000000A)
#define DMA_REQUEST_11 ((uint32_t)0x0000000B)
#define DMA_REQUEST_12 ((uint32_t)0x0000000C)
#define DMA_REQUEST_13 ((uint32_t)0x0000000D)
#define DMA_REQUEST_14 ((uint32_t)0x0000000E)
#define DMA_REQUEST_15 ((uint32_t)0x0000000F)
#define DMA_REQUEST_0 ((uint32_t)0x00000000U)
#define DMA_REQUEST_1 ((uint32_t)0x00000001U)
#define DMA_REQUEST_2 ((uint32_t)0x00000002U)
#define DMA_REQUEST_3 ((uint32_t)0x00000003U)
#define DMA_REQUEST_4 ((uint32_t)0x00000004U)
#define DMA_REQUEST_5 ((uint32_t)0x00000005U)
#define DMA_REQUEST_6 ((uint32_t)0x00000006U)
#define DMA_REQUEST_7 ((uint32_t)0x00000007U)
#define DMA_REQUEST_8 ((uint32_t)0x00000008U)
#define DMA_REQUEST_9 ((uint32_t)0x00000009U)
#define DMA_REQUEST_10 ((uint32_t)0x0000000AU)
#define DMA_REQUEST_11 ((uint32_t)0x0000000BU)
#define DMA_REQUEST_12 ((uint32_t)0x0000000CU)
#define DMA_REQUEST_13 ((uint32_t)0x0000000DU)
#define DMA_REQUEST_14 ((uint32_t)0x0000000EU)
#define DMA_REQUEST_15 ((uint32_t)0x0000000FU)
#define IS_DMA_ALL_REQUEST(REQUEST) (((REQUEST) == DMA_REQUEST_0) || \
((REQUEST) == DMA_REQUEST_1) || \
@ -236,17 +236,17 @@ typedef struct __DMA_HandleTypeDef
#else /* #if STM32L071xx || STM32L072xx || STM32L073xx || STM32L081xx || STM32L082xx || STM32L083xx */
#define DMA_REQUEST_0 ((uint32_t)0x00000000)
#define DMA_REQUEST_1 ((uint32_t)0x00000001)
#define DMA_REQUEST_2 ((uint32_t)0x00000002)
#define DMA_REQUEST_3 ((uint32_t)0x00000003)
#define DMA_REQUEST_4 ((uint32_t)0x00000004)
#define DMA_REQUEST_5 ((uint32_t)0x00000005)
#define DMA_REQUEST_6 ((uint32_t)0x00000006)
#define DMA_REQUEST_7 ((uint32_t)0x00000007)
#define DMA_REQUEST_8 ((uint32_t)0x00000008)
#define DMA_REQUEST_9 ((uint32_t)0x00000009)
#define DMA_REQUEST_11 ((uint32_t)0x0000000B)
#define DMA_REQUEST_0 ((uint32_t)0x00000000U)
#define DMA_REQUEST_1 ((uint32_t)0x00000001U)
#define DMA_REQUEST_2 ((uint32_t)0x00000002U)
#define DMA_REQUEST_3 ((uint32_t)0x00000003U)
#define DMA_REQUEST_4 ((uint32_t)0x00000004U)
#define DMA_REQUEST_5 ((uint32_t)0x00000005U)
#define DMA_REQUEST_6 ((uint32_t)0x00000006U)
#define DMA_REQUEST_7 ((uint32_t)0x00000007U)
#define DMA_REQUEST_8 ((uint32_t)0x00000008U)
#define DMA_REQUEST_9 ((uint32_t)0x00000009U)
#define DMA_REQUEST_11 ((uint32_t)0x0000000BU)
#define IS_DMA_ALL_REQUEST(REQUEST) (((REQUEST) == DMA_REQUEST_0) || \
((REQUEST) == DMA_REQUEST_1) || \
@ -268,7 +268,7 @@ typedef struct __DMA_HandleTypeDef
/** @defgroup DMA_Data_transfer_direction DMA Data Transfer directions
* @{
*/
#define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000) /*!< Peripheral to memory direction */
#define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000U) /*!< Peripheral to memory direction */
#define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR) /*!< Memory to peripheral direction */
#define DMA_MEMORY_TO_MEMORY ((uint32_t)(DMA_CCR_MEM2MEM)) /*!< Memory to memory direction */
@ -291,7 +291,7 @@ typedef struct __DMA_HandleTypeDef
* @{
*/
#define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */
#define DMA_PINC_DISABLE ((uint32_t)0x00000000) /*!< Peripheral increment mode Disable */
#define DMA_PINC_DISABLE ((uint32_t)0x00000000U) /*!< Peripheral increment mode Disable */
#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
((STATE) == DMA_PINC_DISABLE))
@ -303,7 +303,7 @@ typedef struct __DMA_HandleTypeDef
* @{
*/
#define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable */
#define DMA_MINC_DISABLE ((uint32_t)0x00000000) /*!< Memory increment mode Disable */
#define DMA_MINC_DISABLE ((uint32_t)0x00000000U) /*!< Memory increment mode Disable */
#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \
((STATE) == DMA_MINC_DISABLE))
@ -314,7 +314,7 @@ typedef struct __DMA_HandleTypeDef
/** @defgroup DMA_Peripheral_data_size DMA Peripheral Data Size Alignment
* @{
*/
#define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Peripheral data alignment : Byte */
#define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000U) /*!< Peripheral data alignment : Byte */
#define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment : HalfWord */
#define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment : Word */
@ -329,7 +329,7 @@ typedef struct __DMA_HandleTypeDef
/** @defgroup DMA_Memory_data_size DMA Memory Data Size Alignment
* @{
*/
#define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Memory data alignment : Byte */
#define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000U) /*!< Memory data alignment : Byte */
#define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment : HalfWord */
#define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1) /*!< Memory data alignment : Word */
@ -343,7 +343,7 @@ typedef struct __DMA_HandleTypeDef
/** @defgroup DMA_mode DMA Mode
* @{
*/
#define DMA_NORMAL ((uint32_t)0x00000000) /*!< Normal Mode */
#define DMA_NORMAL ((uint32_t)0x00000000U) /*!< Normal Mode */
#define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular Mode */
#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \
@ -355,7 +355,7 @@ typedef struct __DMA_HandleTypeDef
/** @defgroup DMA_Priority_level DMA Priority Level
* @{
*/
#define DMA_PRIORITY_LOW ((uint32_t)0x00000000) /*!< Priority level : Low */
#define DMA_PRIORITY_LOW ((uint32_t)0x00000000U) /*!< Priority level : Low */
#define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0) /*!< Priority level : Medium */
#define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1) /*!< Priority level : High */
#define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) /*!< Priority level : Very_High */
@ -385,34 +385,34 @@ typedef struct __DMA_HandleTypeDef
* @{
*/
#define DMA_FLAG_GL1 ((uint32_t)0x00000001)
#define DMA_FLAG_TC1 ((uint32_t)0x00000002)
#define DMA_FLAG_HT1 ((uint32_t)0x00000004)
#define DMA_FLAG_TE1 ((uint32_t)0x00000008)
#define DMA_FLAG_GL2 ((uint32_t)0x00000010)
#define DMA_FLAG_TC2 ((uint32_t)0x00000020)
#define DMA_FLAG_HT2 ((uint32_t)0x00000040)
#define DMA_FLAG_TE2 ((uint32_t)0x00000080)
#define DMA_FLAG_GL3 ((uint32_t)0x00000100)
#define DMA_FLAG_TC3 ((uint32_t)0x00000200)
#define DMA_FLAG_HT3 ((uint32_t)0x00000400)
#define DMA_FLAG_TE3 ((uint32_t)0x00000800)
#define DMA_FLAG_GL4 ((uint32_t)0x00001000)
#define DMA_FLAG_TC4 ((uint32_t)0x00002000)
#define DMA_FLAG_HT4 ((uint32_t)0x00004000)
#define DMA_FLAG_TE4 ((uint32_t)0x00008000)
#define DMA_FLAG_GL5 ((uint32_t)0x00010000)
#define DMA_FLAG_TC5 ((uint32_t)0x00020000)
#define DMA_FLAG_HT5 ((uint32_t)0x00040000)
#define DMA_FLAG_TE5 ((uint32_t)0x00080000)
#define DMA_FLAG_GL6 ((uint32_t)0x00100000)
#define DMA_FLAG_TC6 ((uint32_t)0x00200000)
#define DMA_FLAG_HT6 ((uint32_t)0x00400000)
#define DMA_FLAG_TE6 ((uint32_t)0x00800000)
#define DMA_FLAG_GL7 ((uint32_t)0x01000000)
#define DMA_FLAG_TC7 ((uint32_t)0x02000000)
#define DMA_FLAG_HT7 ((uint32_t)0x04000000)
#define DMA_FLAG_TE7 ((uint32_t)0x08000000)
#define DMA_FLAG_GL1 ((uint32_t)0x00000001U)
#define DMA_FLAG_TC1 ((uint32_t)0x00000002U)
#define DMA_FLAG_HT1 ((uint32_t)0x00000004U)
#define DMA_FLAG_TE1 ((uint32_t)0x00000008U)
#define DMA_FLAG_GL2 ((uint32_t)0x00000010U)
#define DMA_FLAG_TC2 ((uint32_t)0x00000020U)
#define DMA_FLAG_HT2 ((uint32_t)0x00000040U)
#define DMA_FLAG_TE2 ((uint32_t)0x00000080U)
#define DMA_FLAG_GL3 ((uint32_t)0x00000100U)
#define DMA_FLAG_TC3 ((uint32_t)0x00000200U)
#define DMA_FLAG_HT3 ((uint32_t)0x00000400U)
#define DMA_FLAG_TE3 ((uint32_t)0x00000800U)
#define DMA_FLAG_GL4 ((uint32_t)0x00001000U)
#define DMA_FLAG_TC4 ((uint32_t)0x00002000U)
#define DMA_FLAG_HT4 ((uint32_t)0x00004000U)
#define DMA_FLAG_TE4 ((uint32_t)0x00008000U)
#define DMA_FLAG_GL5 ((uint32_t)0x00010000U)
#define DMA_FLAG_TC5 ((uint32_t)0x00020000U)
#define DMA_FLAG_HT5 ((uint32_t)0x00040000U)
#define DMA_FLAG_TE5 ((uint32_t)0x00080000U)
#define DMA_FLAG_GL6 ((uint32_t)0x00100000U)
#define DMA_FLAG_TC6 ((uint32_t)0x00200000U)
#define DMA_FLAG_HT6 ((uint32_t)0x00400000U)
#define DMA_FLAG_TE6 ((uint32_t)0x00800000U)
#define DMA_FLAG_GL7 ((uint32_t)0x01000000U)
#define DMA_FLAG_TC7 ((uint32_t)0x02000000U)
#define DMA_FLAG_HT7 ((uint32_t)0x04000000U)
#define DMA_FLAG_TE7 ((uint32_t)0x08000000U)
/**
@ -605,6 +605,14 @@ typedef struct __DMA_HandleTypeDef
*/
#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__)))
/**
* @brief Returns the number of remaining data units in the current DMAy Channelx transfer.
* @param __HANDLE__: DMA handle
*
* @retval The number of remaining data units in the current DMA Channel transfer.
*/
#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR)
/**
* @}
*/

10
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_firewall.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx_hal_firewall.c
* @author MCD Application Team
* @version V1.5.0
* @date 8-January-2016
* @version V1.7.0
* @date 31-May-2016
* @brief FIREWALL HAL module driver.
* This file provides firmware functions to manage the Firewall
* Peripheral initialization and enabling.
@ -133,19 +133,19 @@ HAL_StatusTypeDef HAL_FIREWALL_Config(FIREWALL_InitTypeDef * fw_init)
/* Check Firewall configuration addresses and lengths when segment is protected */
/* Code segment */
if (fw_init->CodeSegmentLength != 0)
if (fw_init->CodeSegmentLength != 0U)
{
assert_param(IS_FIREWALL_CODE_SEGMENT_ADDRESS(fw_init->CodeSegmentStartAddress));
assert_param(IS_FIREWALL_CODE_SEGMENT_LENGTH(fw_init->CodeSegmentStartAddress, fw_init->CodeSegmentLength));
}
/* Non volatile data segment */
if (fw_init->NonVDataSegmentLength != 0)
if (fw_init->NonVDataSegmentLength != 0U)
{
assert_param(IS_FIREWALL_NONVOLATILEDATA_SEGMENT_ADDRESS(fw_init->NonVDataSegmentStartAddress));
assert_param(IS_FIREWALL_NONVOLATILEDATA_SEGMENT_LENGTH(fw_init->NonVDataSegmentStartAddress, fw_init->NonVDataSegmentLength));
}
/* Volatile data segment */
if (fw_init->VDataSegmentLength != 0)
if (fw_init->VDataSegmentLength != 0U)
{
assert_param(IS_FIREWALL_VOLATILEDATA_SEGMENT_ADDRESS(fw_init->VDataSegmentStartAddress));
assert_param(IS_FIREWALL_VOLATILEDATA_SEGMENT_LENGTH(fw_init->VDataSegmentStartAddress, fw_init->VDataSegmentLength));

12
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_firewall.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx_hal_firewall.h
* @author MCD Application Team
* @version V1.5.0
* @date 8-January-2016
* @version V1.7.0
* @date 31-May-2016
* @brief Header file of FIREWALL HAL module.
******************************************************************************
* @attention
@ -108,7 +108,7 @@ typedef struct
/** @defgroup FIREWALL_VolatileData_Executable FIREWALL volatile data segment execution status
* @{
*/
#define FIREWALL_VOLATILEDATA_NOT_EXECUTABLE ((uint32_t)0x0000)
#define FIREWALL_VOLATILEDATA_NOT_EXECUTABLE ((uint32_t)0x0000U)
#define FIREWALL_VOLATILEDATA_EXECUTABLE ((uint32_t)FW_CR_VDE)
/**
* @}
@ -117,7 +117,7 @@ typedef struct
/** @defgroup FIREWALL_VolatileData_Shared FIREWALL volatile data segment share status
* @{
*/
#define FIREWALL_VOLATILEDATA_NOT_SHARED ((uint32_t)0x0000)
#define FIREWALL_VOLATILEDATA_NOT_SHARED ((uint32_t)0x0000U)
#define FIREWALL_VOLATILEDATA_SHARED ((uint32_t)FW_CR_VDS)
/**
* @}
@ -126,7 +126,7 @@ typedef struct
/** @defgroup FIREWALL_Pre_Arm FIREWALL pre arm status
* @{
*/
#define FIREWALL_PRE_ARM_RESET ((uint32_t)0x0000)
#define FIREWALL_PRE_ARM_RESET ((uint32_t)0x0000U)
#define FIREWALL_PRE_ARM_SET ((uint32_t)FW_CR_FPA)
/**
@ -147,7 +147,7 @@ typedef struct
#define IS_FIREWALL_NONVOLATILEDATA_SEGMENT_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) < (FLASH_BASE + FLASH_SIZE)))
#define IS_FIREWALL_NONVOLATILEDATA_SEGMENT_LENGTH(ADDRESS, LENGTH) (((ADDRESS) + (LENGTH)) <= (FLASH_BASE + FLASH_SIZE))
#define IS_FIREWALL_VOLATILEDATA_SEGMENT_ADDRESS(ADDRESS) (((ADDRESS) >= SRAM_BASE) && ((ADDRESS) < (SRAM_BASE + SRAM1_SIZE_MAX)))
#define IS_FIREWALL_VOLATILEDATA_SEGMENT_ADDRESS(ADDRESS) (((ADDRESS) >= SRAM_BASE) && ((ADDRESS) < (SRAM_BASE + SRAM_SIZE_MAX)))
#define IS_FIREWALL_VOLATILEDATA_SEGMENT_LENGTH(ADDRESS, LENGTH) (((ADDRESS) + (LENGTH)) <= (SRAM_BASE + SRAM_SIZE_MAX))

18
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_flash.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx_hal_flash.c
* @author MCD Application Team
* @version V1.5.0
* @date 8-January-2016
* @version V1.7.0
* @date 31-May-2016
* @brief FLASH HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the internal FLASH memory:
@ -315,12 +315,12 @@ void HAL_FLASH_IRQHandler(void)
/* Check FLASH operation error flags */
/* WARNING : On the first cut of STM32L031xx and STM32L041xx devices,
* (RevID = 0x1000) the FLASH_FLAG_OPTVERR bit was not behaving
* (RefID = 0x1000) the FLASH_FLAG_OPTVERR bit was not behaving
* as expected. If the user run an application using the first
* cut of the STM32L031xx device or the first cut of the STM32L041xx
* device, the check on the FLASH_FLAG_OPTVERR bit should be ignored.
*
* Note :The RevID of the device can be retrieved via the HAL_GetREVID()
* Note :The revId of the device can be retrieved via the HAL_GetREVID()
* function.
*
*/
@ -332,7 +332,7 @@ void HAL_FLASH_IRQHandler(void)
{
/* Return the faulty sector */
temp = ProcFlash.Page;
ProcFlash.Page = 0xFFFFFFFF;
ProcFlash.Page = 0xFFFFFFFFU;
}
else
{
@ -365,7 +365,7 @@ void HAL_FLASH_IRQHandler(void)
ProcFlash.NbPagesToErase--;
/* Check if there are still sectors to erase */
if(ProcFlash.NbPagesToErase != 0)
if(ProcFlash.NbPagesToErase != 0U)
{
temp = ProcFlash.Page;
/* Indicate user which sector has been erased */
@ -384,7 +384,7 @@ void HAL_FLASH_IRQHandler(void)
{
/* No more sectors to Erase, user callback can be called */
/* Reset Sector and stop Erase sectors procedure */
ProcFlash.Page = temp = 0xFFFFFFFF;
ProcFlash.Page = temp = 0xFFFFFFFFU;
ProcFlash.ProcedureOnGoing = FLASH_PROC_NONE;
/* FLASH EOP interrupt user callback */
HAL_FLASH_EndOfOperationCallback(temp);
@ -634,7 +634,7 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)
{
if(Timeout != HAL_MAX_DELAY)
{
if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
{
return HAL_TIMEOUT;
}
@ -745,7 +745,7 @@ void FLASH_ErasePage(uint32_t Page_Address)
SET_BIT(FLASH->PECR, FLASH_PECR_PROG);
/* Write 00000000h to the first word of the program page to erase */
*(__IO uint32_t *)Page_Address = 0x00000000;
*(__IO uint32_t *)Page_Address = 0x00000000U;
}
/**

60
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_flash.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx_hal_flash.h
* @author MCD Application Team
* @version V1.5.0
* @date 8-January-2016
* @version V1.7.0
* @date 31-May-2016
* @brief Header file of Flash HAL module.
******************************************************************************
* @attention
@ -63,7 +63,7 @@
*/
typedef enum
{
FLASH_PROC_NONE = 0,
FLASH_PROC_NONE = 0U,
FLASH_PROC_PAGEERASE,
FLASH_PROC_PROGRAM
} FLASH_ProcedureTypeDef;
@ -117,8 +117,8 @@ typedef struct
extern FLASH_ProcessTypeDef ProcFlash;
#define FLASH_TIMEOUT_VALUE ((uint32_t)50000) /* 50 s */
#define FLASH_SIZE_DATA_REGISTER ((uint32_t)0x1FF8007C)
#define FLASH_TIMEOUT_VALUE ((uint32_t)50000U) /* 50 s */
#define FLASH_SIZE_DATA_REGISTER ((uint32_t)0x1FF8007CU)
/**
* @}
*/
@ -131,13 +131,13 @@ extern FLASH_ProcessTypeDef ProcFlash;
/**
* @brief FLASH size information
*/
#define FLASH_SIZE (uint32_t)(*((uint16_t *)FLASH_SIZE_DATA_REGISTER) * 1024)
#define FLASH_PAGE_SIZE ((uint32_t)128)
#define FLASH_SIZE (uint32_t)(*((uint16_t *)FLASH_SIZE_DATA_REGISTER) * 1024U)
#define FLASH_PAGE_SIZE ((uint32_t)128U)
/** @defgroup FLASH_Type_Program FLASH Type Program
* @{
*/
#define FLASH_TYPEPROGRAM_WORD ((uint32_t)0x02) /*!<Program a word (32-bit) at a specified address.*/
#define FLASH_TYPEPROGRAM_WORD ((uint32_t)0x02U) /*!<Program a word (32-bit) at a specified address.*/
/**
* @}
*/
@ -145,8 +145,8 @@ extern FLASH_ProcessTypeDef ProcFlash;
/** @defgroup FLASH_Latency FLASH Latency
* @{
*/
#define FLASH_LATENCY_0 ((uint8_t)0x00) /*!< FLASH Zero Latency cycle */
#define FLASH_LATENCY_1 ((uint8_t)0x01) /*!< FLASH One Latency cycle */
#define FLASH_LATENCY_0 ((uint8_t)0x00U) /*!< FLASH Zero Latency cycle */
#define FLASH_LATENCY_1 ((uint8_t)0x01U) /*!< FLASH One Latency cycle */
/**
* @}
*/
@ -181,14 +181,14 @@ extern FLASH_ProcessTypeDef ProcFlash;
/** @defgroup FLASH_Error_Code Flash Error Code
* @{
*/
#define HAL_FLASH_ERROR_NONE 0x00
#define HAL_FLASH_ERROR_RD 0x01
#define HAL_FLASH_ERROR_SIZE 0x02
#define HAL_FLASH_ERROR_PGA 0x04
#define HAL_FLASH_ERROR_WRP 0x08
#define HAL_FLASH_ERROR_OPTV 0x10
#define HAL_FLASH_ERROR_FWWERR 0x20
#define HAL_FLASH_ERROR_NOTZERO 0x40
#define HAL_FLASH_ERROR_NONE 0x00U
#define HAL_FLASH_ERROR_RD 0x01U
#define HAL_FLASH_ERROR_SIZE 0x02U
#define HAL_FLASH_ERROR_PGA 0x04U
#define HAL_FLASH_ERROR_WRP 0x08U
#define HAL_FLASH_ERROR_OPTV 0x10U
#define HAL_FLASH_ERROR_FWWERR 0x20U
#define HAL_FLASH_ERROR_NOTZERO 0x40U
/**
* @}
*/
@ -196,22 +196,22 @@ extern FLASH_ProcessTypeDef ProcFlash;
/** @defgroup FLASH_Keys FLASH Keys
* @{
*/
#define FLASH_PDKEY1 ((uint32_t)0x04152637) /*!< Flash power down key1 */
#define FLASH_PDKEY2 ((uint32_t)0xFAFBFCFD) /*!< Flash power down key2: used with FLASH_PDKEY1
#define FLASH_PDKEY1 ((uint32_t)0x04152637U) /*!< Flash power down key1 */
#define FLASH_PDKEY2 ((uint32_t)0xFAFBFCFDU) /*!< Flash power down key2: used with FLASH_PDKEY1
to unlock the RUN_PD bit in FLASH_ACR */
#define FLASH_PEKEY1 ((uint32_t)0x89ABCDEF) /*!< Flash program erase key1 */
#define FLASH_PEKEY2 ((uint32_t)0x02030405) /*!< Flash program erase key: used with FLASH_PEKEY2
to unlock the write access to the FLASH_PECR register and
data EEPROM */
#define FLASH_PEKEY1 ((uint32_t)0x89ABCDEFU) /*!< Flash program erase key1 */
#define FLASH_PEKEY2 ((uint32_t)0x02030405U) /*!< Flash program erase key: used with FLASH_PEKEY2
to unlock the write access to the FLASH_PECR register and
data EEPROM */
#define FLASH_PRGKEY1 ((uint32_t)0x8C9DAEBF) /*!< Flash program memory key1 */
#define FLASH_PRGKEY2 ((uint32_t)0x13141516) /*!< Flash program memory key2: used with FLASH_PRGKEY2
to unlock the program memory */
#define FLASH_PRGKEY1 ((uint32_t)0x8C9DAEBFU) /*!< Flash program memory key1 */
#define FLASH_PRGKEY2 ((uint32_t)0x13141516u) /*!< Flash program memory key2: used with FLASH_PRGKEY2
to unlock the program memory */
#define FLASH_OPTKEY1 ((uint32_t)0xFBEAD9C8) /*!< Flash option key1 */
#define FLASH_OPTKEY2 ((uint32_t)0x24252627) /*!< Flash option key2: used with FLASH_OPTKEY1 to
unlock the write access to the option byte block */
#define FLASH_OPTKEY1 ((uint32_t)0xFBEAD9C8U) /*!< Flash option key1 */
#define FLASH_OPTKEY2 ((uint32_t)0x24252627U) /*!< Flash option key2: used with FLASH_OPTKEY1 to
unlock the write access to the option byte block */
/**
* @}
*/

90
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_flash_ex.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx_hal_flash_ex.c
* @author MCD Application Team
* @version V1.5.0
* @date 8-January-2016
* @version V1.7.0
* @date 31-May-2016
* @brief FLASH HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the internal FLASH memory:
@ -103,7 +103,7 @@ static uint32_t FLASH_OB_GetWRP(void);
static uint32_t FLASH_OB_GetWRP2(void);
#endif
static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY);
static HAL_StatusTypeDef FLASH_OB_BOOTBit1Config(uint8_t OB_BOOT_Bit1);
static HAL_StatusTypeDef FLASH_OB_BOOTBit1Config(uint8_t OB_BOOT_BIT1);
#if defined(STM32L071xx) || defined(STM32L072xx) || defined(STM32L073xx) || defined(STM32L081xx) || defined(STM32L082xx) || defined(STM32L083xx)
static HAL_StatusTypeDef FLASH_OB_BFB2Config(uint8_t OB_BFB2);
#endif
@ -159,7 +159,7 @@ static HAL_StatusTypeDef FLASH_OB_BFB2Config(uint8_t OB_BFB2);
HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError)
{
HAL_StatusTypeDef status = HAL_ERROR;
uint32_t index = 0;
uint32_t index = 0U;
/* Process Locked */
__HAL_LOCK(&ProcFlash);
@ -173,13 +173,13 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t
ProcFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
/*Initialization of PageError variable*/
*PageError = 0xFFFFFFFF;
*PageError = 0xFFFFFFFFU;
/* Check the parameters */
assert_param(IS_NBPAGES(pEraseInit->NbPages));
assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress));
assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress + pEraseInit->NbPages * FLASH_PAGE_SIZE - 1));
assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress + pEraseInit->NbPages * FLASH_PAGE_SIZE - 1U));
/* Erase by sector by sector to be done*/
for(index = pEraseInit->PageAddress; index < ((pEraseInit->NbPages * FLASH_PAGE_SIZE)+ pEraseInit->PageAddress); index += FLASH_PAGE_SIZE)
@ -243,7 +243,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)
assert_param(IS_NBPAGES(pEraseInit->NbPages));
assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress));
assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress + pEraseInit->NbPages * FLASH_PAGE_SIZE - 1));
assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress + pEraseInit->NbPages * FLASH_PAGE_SIZE - 1U));
/* Clean the error context */
ProcFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
@ -458,7 +458,7 @@ void HAL_FLASHEx_AdvOBGetConfig(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit)
pAdvOBInit->OptionType = OPTIONBYTE_PCROP;
#endif
/* Get PCROP state */
pAdvOBInit->PCROPState = (FLASH->OPTR & FLASH_OPTR_WPRMOD) >> 8;
pAdvOBInit->PCROPState = (FLASH->OPTR & FLASH_OPTR_WPRMOD) >> 8U;
/* Get PCROP protected sector */
pAdvOBInit->PCROPSector = FLASH->WRPR;
@ -467,7 +467,7 @@ void HAL_FLASHEx_AdvOBGetConfig(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit)
pAdvOBInit->PCROPSector2 = FLASH->WRPR2;
/* Get boot bank config */
pAdvOBInit->BootConfig = (FLASH->OPTR & FLASH_OPTR_BFB2) >> 23;
pAdvOBInit->BootConfig = (FLASH->OPTR & FLASH_OPTR_BFB2) >> 23U;
#endif
}
@ -479,7 +479,7 @@ void HAL_FLASHEx_AdvOBGetConfig(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit)
*/
HAL_StatusTypeDef HAL_FLASHEx_OB_SelectPCROP(void)
{
return (FLASH_OB_PCROPSelectionConfig(1));
return (FLASH_OB_PCROPSelectionConfig(1U));
}
/**
@ -490,7 +490,7 @@ HAL_StatusTypeDef HAL_FLASHEx_OB_SelectPCROP(void)
*/
HAL_StatusTypeDef HAL_FLASHEx_OB_DeSelectPCROP(void)
{
return (FLASH_OB_PCROPSelectionConfig(0));
return (FLASH_OB_PCROPSelectionConfig(0U));
}
/**
@ -578,7 +578,7 @@ HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Erase(uint32_t Address)
ProcFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
/* Write "00000000h" to valid address in the data memory" */
*(__IO uint32_t *) Address = 0x00000000;
*(__IO uint32_t *) Address = 0x00000000U;
status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
}
@ -680,7 +680,7 @@ void HAL_FLASHEx_DATAEEPROM_DisableFixedTimeProgram(void)
static uint8_t FLASH_OB_GetUser(void)
{
/* Return the User Option Byte */
return (uint8_t)((FLASH->OPTR & FLASH_OPTR_USER) >> 16);
return (uint8_t)((FLASH->OPTR & FLASH_OPTR_USER) >> 16U);
}
/**
@ -699,7 +699,7 @@ static uint8_t FLASH_OB_GetRDP(void)
static uint8_t FLASH_OB_GetBOR(void)
{
/* Return the BOR level */
return (uint8_t)((FLASH->OPTR & (uint32_t)FLASH_OPTR_BOR_LEV) >> 16);
return (uint8_t)((FLASH->OPTR & (uint32_t)FLASH_OPTR_BOR_LEV) >> 16U);
}
/**
@ -709,7 +709,7 @@ static uint8_t FLASH_OB_GetBOR(void)
static uint8_t FLASH_OB_GetBOOTBit1(void)
{
/* Return the BOR level */
return (FLASH->OPTR & FLASH_OPTR_BOOT1) >> 31;
return (FLASH->OPTR & FLASH_OPTR_BOOT1) >> 31U;
}
@ -754,7 +754,7 @@ static uint32_t FLASH_OB_GetWRP2(void)
static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY)
{
HAL_StatusTypeDef status = HAL_OK;
uint32_t tmp = 0, tmp1 = 0, OB_Bits = (uint32_t) (OB_IWDG | OB_STOP | OB_STDBY);
uint32_t tmp = 0U, tmp1 = 0U, OB_Bits = (uint32_t) (OB_IWDG | OB_STOP | OB_STDBY);
/* Check the parameters */
assert_param(IS_OB_IWDG_SOURCE(OB_IWDG));
@ -765,10 +765,10 @@ static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, u
ProcFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
/* Get the User Option byte register */
tmp1 = OB->USER & ((~FLASH_OPTR_USER) >> 16);
tmp1 = OB->USER & ((~FLASH_OPTR_USER) >> 16U);
/* Calculate the user option byte to write */
tmp = (~(OB_Bits | tmp1)) << 16;
tmp = (~(OB_Bits | tmp1)) << 16U;
tmp |= OB_Bits | tmp1;
/* Wait for last operation to be completed */
@ -803,14 +803,14 @@ static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, u
static HAL_StatusTypeDef FLASH_OB_RDPConfig(uint8_t OB_RDP)
{
HAL_StatusTypeDef status;
uint32_t tmp = 0, tmp1 = 0, OB_Bits = (uint32_t) OB_RDP;
uint32_t tmp = 0U, tmp1 = 0U, OB_Bits = (uint32_t) OB_RDP;
/* Check the parameters */
assert_param(IS_OB_RDP(OB_RDP));
/* Calculate the option byte to write */
tmp = (OB->RDP & ((~FLASH_OPTR_RDPROT) & 0x0000FFFF)) | OB_Bits;
tmp1 = (~tmp << 16) | tmp;
tmp = (OB->RDP & ((~FLASH_OPTR_RDPROT) & 0x0000FFFFU)) | OB_Bits;
tmp1 = (~tmp << 16U) | tmp;
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
@ -843,16 +843,16 @@ static HAL_StatusTypeDef FLASH_OB_RDPConfig(uint8_t OB_RDP)
static HAL_StatusTypeDef FLASH_OB_BORConfig(uint8_t OB_BOR)
{
HAL_StatusTypeDef status = HAL_OK;
uint32_t tmp = 0, tmp1 = 0, OB_Bits = (uint32_t) OB_BOR;
uint32_t tmp = 0U, tmp1 = 0U, OB_Bits = (uint32_t) OB_BOR;
/* Check the parameters */
assert_param(IS_OB_BOR_LEVEL(OB_BOR));
/* Get the User Option byte register */
tmp1 = OB->USER & ((~FLASH_OPTR_BOR_LEV) >> 16);
tmp1 = OB->USER & ((~FLASH_OPTR_BOR_LEV) >> 16U);
/* Calculate the user option byte to write */
tmp = (~(OB_Bits | tmp1)) << 16;
tmp = (~(OB_Bits | tmp1)) << 16U;
tmp |= OB_Bits | tmp1;
/* Wait for last operation to be completed */
@ -882,16 +882,16 @@ static HAL_StatusTypeDef FLASH_OB_BORConfig(uint8_t OB_BOR)
static HAL_StatusTypeDef FLASH_OB_BOOTBit1Config(uint8_t OB_BOOT_BIT1)
{
HAL_StatusTypeDef status = HAL_OK;
uint32_t tmp = 0, tmp1 = 0, OB_Bits = ((uint32_t) OB_BOOT_BIT1) << 15;
uint32_t tmp = 0U, tmp1 = 0U, OB_Bits = ((uint32_t) OB_BOOT_BIT1) << 15U;
/* Check the parameters */
assert_param(IS_OB_BOOT1(OB_BOOT_BIT1));
/* Get the User Option byte register */
tmp1 = OB->USER & ((~FLASH_OPTR_BOOT1) >> 16);
tmp1 = OB->USER & ((~FLASH_OPTR_BOOT1) >> 16U);
/* Calculate the user option byte to write */
tmp = (~(OB_Bits | tmp1)) << 16;
tmp = (~(OB_Bits | tmp1)) << 16U;
tmp |= OB_Bits | tmp1;
/* Wait for last operation to be completed */
@ -923,13 +923,13 @@ static HAL_StatusTypeDef FLASH_OB_BOOTBit1Config(uint8_t OB_BOOT_BIT1)
static HAL_StatusTypeDef FLASH_OB_PCROPSelectionConfig(uint32_t WPRMOD)
{
HAL_StatusTypeDef status;
uint32_t tmp = 0, tmp1 = 0, OB_Bits = ((uint32_t) WPRMOD) << 8;
uint32_t tmp = 0U, tmp1 = 0U, OB_Bits = ((uint32_t) WPRMOD) << 8U;
/* Get the User Option byte register */
tmp1 = OB->USER & ((~FLASH_OPTR_WPRMOD) >> 16);
tmp1 = OB->USER & ((~FLASH_OPTR_WPRMOD) >> 16U);
/* Calculate the user option byte to write */
tmp = (~(OB_Bits | tmp1)) << 16;
tmp = (~(OB_Bits | tmp1)) << 16U;
tmp |= OB_Bits | tmp1;
/* Wait for last operation to be completed */
@ -960,16 +960,16 @@ static HAL_StatusTypeDef FLASH_OB_PCROPSelectionConfig(uint32_t WPRMOD)
static HAL_StatusTypeDef FLASH_OB_BFB2Config(uint8_t OB_BFB2)
{
HAL_StatusTypeDef status = HAL_OK;
uint32_t tmp = 0, tmp1 = 0, OB_Bits = ((uint32_t) OB_BFB2) << 7;
uint32_t tmp = 0U, tmp1 = 0U, OB_Bits = ((uint32_t) OB_BFB2) << 7U;
/* Check the parameters */
assert_param(IS_OB_BOOT_BANK(OB_BFB2));
/* Get the User Option byte register */
tmp1 = OB->USER & ((~FLASH_OPTR_BFB2) >> 16);
tmp1 = OB->USER & ((~FLASH_OPTR_BFB2) >> 16U);
/* Calculate the user option byte to write */
tmp = (~(OB_Bits | tmp1)) << 16;
tmp = (~(OB_Bits | tmp1)) << 16U;
tmp |= OB_Bits | tmp1;
/* Wait for last operation to be completed */
@ -1013,7 +1013,7 @@ static HAL_StatusTypeDef FLASH_OB_ProtectedSectorsConfig(uint32_t Sector, uint32
#endif
{
HAL_StatusTypeDef status = HAL_OK;
uint32_t WRP_Data = 0;
uint32_t WRP_Data = 0U;
uint32_t OB_WRP = Sector;
/* Check the parameters */
@ -1027,46 +1027,46 @@ static HAL_StatusTypeDef FLASH_OB_ProtectedSectorsConfig(uint32_t Sector, uint32
/* Clean the error context */
ProcFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
if (OB_WRP & 0x0000FFFF)
if (OB_WRP & 0x0000FFFFU)
{
if (NewState != OB_WRPSTATE_DISABLE)
{
WRP_Data = (uint16_t)(((OB_WRP & WRP_MASK_LOW) | OB->WRP01));
OB->WRP01 = (uint32_t)(~(WRP_Data) << 16) | (WRP_Data);
OB->WRP01 = (uint32_t)(~(WRP_Data) << 16U) | (WRP_Data);
}
else
{
WRP_Data = (uint16_t)(~OB_WRP & (WRP_MASK_LOW & OB->WRP01));
OB->WRP01 = (uint32_t)((~WRP_Data) << 16) | (WRP_Data);
OB->WRP01 = (uint32_t)((~WRP_Data) << 16U) | (WRP_Data);
}
}
#if defined(STM32L071xx) || defined(STM32L072xx) || defined(STM32L073xx) || defined(STM32L081xx) || defined(STM32L082xx) || defined(STM32L083xx)
if (OB_WRP & 0xFFFF0000)
if (OB_WRP & 0xFFFF0000U)
{
if (NewState != OB_WRPSTATE_DISABLE)
{
WRP_Data = (uint16_t)((((OB_WRP & WRP_MASK_HIGH) >> 16 | OB->WRP23)));
OB->WRP23 = (uint32_t)(~(WRP_Data) << 16) | (WRP_Data);
WRP_Data = (uint16_t)((((OB_WRP & WRP_MASK_HIGH) >> 16U | OB->WRP23)));
OB->WRP23 = (uint32_t)(~(WRP_Data) << 16U) | (WRP_Data);
}
else
{
WRP_Data = (uint16_t)((((~OB_WRP & WRP_MASK_HIGH) >> 16 & OB->WRP23)));
OB->WRP23 = (uint32_t)((~WRP_Data) << 16) | (WRP_Data);
WRP_Data = (uint16_t)((((~OB_WRP & WRP_MASK_HIGH) >> 16U & OB->WRP23)));
OB->WRP23 = (uint32_t)((~WRP_Data) << 16U) | (WRP_Data);
}
}
OB_WRP = Sector2;
if (OB_WRP & 0x0000FFFF)
if (OB_WRP & 0x0000FFFFU)
{
if (NewState != OB_WRPSTATE_DISABLE)
{
WRP_Data = (uint16_t)(((OB_WRP & WRP_MASK_LOW) | OB->WRP45));
OB->WRP45 =(uint32_t)(~(WRP_Data) << 16) | (WRP_Data);
OB->WRP45 =(uint32_t)(~(WRP_Data) << 16U) | (WRP_Data);
}
else
{
WRP_Data = (uint16_t)(~OB_WRP & (WRP_MASK_LOW & OB->WRP45));
OB->WRP45 = (uint32_t)((~WRP_Data) << 16) | (WRP_Data);
OB->WRP45 = (uint32_t)((~WRP_Data) << 16U) | (WRP_Data);
}
}
#endif /* STM32L071xx || STM32L072xx || STM32L073xx || STM32L081xx || STM32L082xx || STM32L083xx */

390
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_flash_ex.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx_hal_flash_ex.h
* @author MCD Application Team
* @version V1.5.0
* @date 8-January-2016
* @version V1.7.0
* @date 31-May-2016
* @brief Header file of FLash HAL Extension module.
******************************************************************************
* @attention
@ -126,7 +126,7 @@ typedef struct
/** @defgroup FLASHEx_Type_Erase FLASH Type Erase
* @{
*/
#define FLASH_TYPEERASE_PAGES ((uint32_t)0x00) /*!< Page erase only */
#define FLASH_TYPEERASE_PAGES ((uint32_t)0x00U) /*!< Page erase only */
/**
* @}
*/
@ -134,11 +134,11 @@ typedef struct
/** @defgroup FLASHEx_Option_Type FLASH Option Type
* @{
*/
#define OPTIONBYTE_WRP ((uint32_t)0x01) /*!< WRP option byte configuration */
#define OPTIONBYTE_RDP ((uint32_t)0x02) /*!< RDP option byte configuration */
#define OPTIONBYTE_USER ((uint32_t)0x04) /*!< USER option byte configuration */
#define OPTIONBYTE_BOR ((uint32_t)0x08) /*!< BOR option byte configuration */
#define OPTIONBYTE_BOOT_BIT1 ((uint32_t)0x10) /*!< BOOT PIN1 option byte configuration*/
#define OPTIONBYTE_WRP ((uint32_t)0x01U) /*!< WRP option byte configuration */
#define OPTIONBYTE_RDP ((uint32_t)0x02U) /*!< RDP option byte configuration */
#define OPTIONBYTE_USER ((uint32_t)0x04U) /*!< USER option byte configuration */
#define OPTIONBYTE_BOR ((uint32_t)0x08U) /*!< BOR option byte configuration */
#define OPTIONBYTE_BOOT_BIT1 ((uint32_t)0x10U) /*!< BOOT PIN1 option byte configuration*/
/**
* @}
*/
@ -146,8 +146,8 @@ typedef struct
/** @defgroup FLASHEx_WRP_State FLASH WRP State
* @{
*/
#define OB_WRPSTATE_DISABLE ((uint32_t)0x00) /*!< Disable the write protection of the desired sectors */
#define OB_WRPSTATE_ENABLE ((uint32_t)0x01) /*!< Enable the write protection of the desired sectors */
#define OB_WRPSTATE_DISABLE ((uint32_t)0x00U) /*!< Disable the write protection of the desired sectors */
#define OB_WRPSTATE_ENABLE ((uint32_t)0x01U) /*!< Enable the write protection of the desired sectors */
/**
* @}
*/
@ -155,8 +155,8 @@ typedef struct
/** @defgroup FLASHEx_Option_Bytes_ReadWrite_Mask FLASH Option Bytes Write Mask
* @{
*/
#define WRP_MASK_LOW ((uint32_t)0x0000FFFF)
#define WRP_MASK_HIGH ((uint32_t)0xFFFF0000)
#define WRP_MASK_LOW ((uint32_t)0x0000FFFFU)
#define WRP_MASK_HIGH ((uint32_t)0xFFFF0000U)
/**
* @}
*/
@ -165,15 +165,15 @@ typedef struct
/** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection
* @{
*/
#define OB_WRP_Pages0to31 ((uint32_t)0x00000001) /* Write protection of Sector0 */
#define OB_WRP_Pages32to63 ((uint32_t)0x00000002) /* Write protection of Sector1 */
#define OB_WRP_Pages64to95 ((uint32_t)0x00000004) /* Write protection of Sector2 */
#define OB_WRP_Pages96to127 ((uint32_t)0x00000008) /* Write protection of Sector3 */
#define OB_WRP_Pages128to159 ((uint32_t)0x00000010) /* Write protection of Sector4 */
#define OB_WRP_Pages160to191 ((uint32_t)0x00000020) /* Write protection of Sector5 */
#define OB_WRP_Pages192to223 ((uint32_t)0x00000040) /* Write protection of Sector6 */
#define OB_WRP_Pages224to255 ((uint32_t)0x00000080) /* Write protection of Sector7 */
#define OB_WRP_AllPages ((uint32_t)0x000000FF) /*!< Write protection of all Sectors */
#define OB_WRP_Pages0to31 ((uint32_t)0x00000001U) /* Write protection of Sector0 */
#define OB_WRP_Pages32to63 ((uint32_t)0x00000002U) /* Write protection of Sector1 */
#define OB_WRP_Pages64to95 ((uint32_t)0x00000004U) /* Write protection of Sector2 */
#define OB_WRP_Pages96to127 ((uint32_t)0x00000008U) /* Write protection of Sector3 */
#define OB_WRP_Pages128to159 ((uint32_t)0x00000010U) /* Write protection of Sector4 */
#define OB_WRP_Pages160to191 ((uint32_t)0x00000020U) /* Write protection of Sector5 */
#define OB_WRP_Pages192to223 ((uint32_t)0x00000040U) /* Write protection of Sector6 */
#define OB_WRP_Pages224to255 ((uint32_t)0x00000080U) /* Write protection of Sector7 */
#define OB_WRP_AllPages ((uint32_t)0x000000FFU) /*!< Write protection of all Sectors */
/**
* @}
*/
@ -181,23 +181,23 @@ typedef struct
/** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection
* @{
*/
#define OB_WRP_Pages0to31 ((uint32_t)0x00000001) /* Write protection of Sector0 */
#define OB_WRP_Pages32to63 ((uint32_t)0x00000002) /* Write protection of Sector1 */
#define OB_WRP_Pages64to95 ((uint32_t)0x00000004) /* Write protection of Sector2 */
#define OB_WRP_Pages96to127 ((uint32_t)0x00000008) /* Write protection of Sector3 */
#define OB_WRP_Pages128to159 ((uint32_t)0x00000010) /* Write protection of Sector4 */
#define OB_WRP_Pages160to191 ((uint32_t)0x00000020) /* Write protection of Sector5 */
#define OB_WRP_Pages192to223 ((uint32_t)0x00000040) /* Write protection of Sector6 */
#define OB_WRP_Pages224to255 ((uint32_t)0x00000080) /* Write protection of Sector7 */
#define OB_WRP_Pages256to287 ((uint32_t)0x00000100) /* Write protection of Sector8 */
#define OB_WRP_Pages288to319 ((uint32_t)0x00000200) /* Write protection of Sector9 */
#define OB_WRP_Pages320to351 ((uint32_t)0x00000400) /* Write protection of Sector10 */
#define OB_WRP_Pages352to383 ((uint32_t)0x00000800) /* Write protection of Sector11 */
#define OB_WRP_Pages384to415 ((uint32_t)0x00001000) /* Write protection of Sector12 */
#define OB_WRP_Pages416to447 ((uint32_t)0x00002000) /* Write protection of Sector13 */
#define OB_WRP_Pages448to479 ((uint32_t)0x00004000) /* Write protection of Sector14 */
#define OB_WRP_Pages480to511 ((uint32_t)0x00008000) /* Write protection of Sector15 */
#define OB_WRP_AllPages ((uint32_t)0x0000FFFF) /*!< Write protection of all Sectors */
#define OB_WRP_Pages0to31 ((uint32_t)0x00000001U) /* Write protection of Sector0 */
#define OB_WRP_Pages32to63 ((uint32_t)0x00000002U) /* Write protection of Sector1 */
#define OB_WRP_Pages64to95 ((uint32_t)0x00000004U) /* Write protection of Sector2 */
#define OB_WRP_Pages96to127 ((uint32_t)0x00000008U) /* Write protection of Sector3 */
#define OB_WRP_Pages128to159 ((uint32_t)0x00000010U) /* Write protection of Sector4 */
#define OB_WRP_Pages160to191 ((uint32_t)0x00000020U) /* Write protection of Sector5 */
#define OB_WRP_Pages192to223 ((uint32_t)0x00000040U) /* Write protection of Sector6 */
#define OB_WRP_Pages224to255 ((uint32_t)0x00000080U) /* Write protection of Sector7 */
#define OB_WRP_Pages256to287 ((uint32_t)0x00000100U) /* Write protection of Sector8 */
#define OB_WRP_Pages288to319 ((uint32_t)0x00000200U) /* Write protection of Sector9 */
#define OB_WRP_Pages320to351 ((uint32_t)0x00000400U) /* Write protection of Sector10 */
#define OB_WRP_Pages352to383 ((uint32_t)0x00000800U) /* Write protection of Sector11 */
#define OB_WRP_Pages384to415 ((uint32_t)0x00001000U) /* Write protection of Sector12 */
#define OB_WRP_Pages416to447 ((uint32_t)0x00002000U) /* Write protection of Sector13 */
#define OB_WRP_Pages448to479 ((uint32_t)0x00004000U) /* Write protection of Sector14 */
#define OB_WRP_Pages480to511 ((uint32_t)0x00008000U) /* Write protection of Sector15 */
#define OB_WRP_AllPages ((uint32_t)0x0000FFFFU) /*!< Write protection of all Sectors */
/**
* @}
*/
@ -206,39 +206,39 @@ typedef struct
/** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write ProtectionP
* @{
*/
#define OB_WRP_Pages0to31 ((uint32_t)0x00000001) /* Write protection of Sector0 */
#define OB_WRP_Pages32to63 ((uint32_t)0x00000002) /* Write protection of Sector1 */
#define OB_WRP_Pages64to95 ((uint32_t)0x00000004) /* Write protection of Sector2 */
#define OB_WRP_Pages96to127 ((uint32_t)0x00000008) /* Write protection of Sector3 */
#define OB_WRP_Pages128to159 ((uint32_t)0x00000010) /* Write protection of Sector4 */
#define OB_WRP_Pages160to191 ((uint32_t)0x00000020) /* Write protection of Sector5 */
#define OB_WRP_Pages192to223 ((uint32_t)0x00000040) /* Write protection of Sector6 */
#define OB_WRP_Pages224to255 ((uint32_t)0x00000080) /* Write protection of Sector7 */
#define OB_WRP_Pages256to287 ((uint32_t)0x00000100) /* Write protection of Sector8 */
#define OB_WRP_Pages288to319 ((uint32_t)0x00000200) /* Write protection of Sector9 */
#define OB_WRP_Pages320to351 ((uint32_t)0x00000400) /* Write protection of Sector10 */
#define OB_WRP_Pages352to383 ((uint32_t)0x00000800) /* Write protection of Sector11 */
#define OB_WRP_Pages384to415 ((uint32_t)0x00001000) /* Write protection of Sector12 */
#define OB_WRP_Pages416to447 ((uint32_t)0x00002000) /* Write protection of Sector13 */
#define OB_WRP_Pages448to479 ((uint32_t)0x00004000) /* Write protection of Sector14 */
#define OB_WRP_Pages480to511 ((uint32_t)0x00008000) /* Write protection of Sector15 */
#define OB_WRP_Pages512to543 ((uint32_t)0x00010000) /* Write protection of Sector16 */
#define OB_WRP_Pages544to575 ((uint32_t)0x00020000) /* Write protection of Sector17 */
#define OB_WRP_Pages576to607 ((uint32_t)0x00040000) /* Write protection of Sector18 */
#define OB_WRP_Pages608to639 ((uint32_t)0x00080000) /* Write protection of Sector19 */
#define OB_WRP_Pages640to671 ((uint32_t)0x00100000) /* Write protection of Sector20 */
#define OB_WRP_Pages672to703 ((uint32_t)0x00200000) /* Write protection of Sector21 */
#define OB_WRP_Pages704to735 ((uint32_t)0x00400000) /* Write protection of Sector22 */
#define OB_WRP_Pages736to767 ((uint32_t)0x00800000) /* Write protection of Sector23 */
#define OB_WRP_Pages768to799 ((uint32_t)0x01000000) /* Write protection of Sector24 */
#define OB_WRP_Pages800to831 ((uint32_t)0x02000000) /* Write protection of Sector25 */
#define OB_WRP_Pages832to863 ((uint32_t)0x04000000) /* Write protection of Sector26 */
#define OB_WRP_Pages864to895 ((uint32_t)0x08000000) /* Write protection of Sector27 */
#define OB_WRP_Pages896to927 ((uint32_t)0x10000000) /* Write protection of Sector28 */
#define OB_WRP_Pages928to959 ((uint32_t)0x20000000) /* Write protection of Sector29 */
#define OB_WRP_Pages960to991 ((uint32_t)0x40000000) /* Write protection of Sector30 */
#define OB_WRP_Pages992to1023 ((uint32_t)0x80000000) /* Write protection of Sector31 */
#define OB_WRP_AllPages ((uint32_t)0xFFFFFFFF) /*!<Write protection of all Sectors */
#define OB_WRP_Pages0to31 ((uint32_t)0x00000001U) /* Write protection of Sector0 */
#define OB_WRP_Pages32to63 ((uint32_t)0x00000002U) /* Write protection of Sector1 */
#define OB_WRP_Pages64to95 ((uint32_t)0x00000004U) /* Write protection of Sector2 */
#define OB_WRP_Pages96to127 ((uint32_t)0x00000008U) /* Write protection of Sector3 */
#define OB_WRP_Pages128to159 ((uint32_t)0x00000010U) /* Write protection of Sector4 */
#define OB_WRP_Pages160to191 ((uint32_t)0x00000020U) /* Write protection of Sector5 */
#define OB_WRP_Pages192to223 ((uint32_t)0x00000040U) /* Write protection of Sector6 */
#define OB_WRP_Pages224to255 ((uint32_t)0x00000080U) /* Write protection of Sector7 */
#define OB_WRP_Pages256to287 ((uint32_t)0x00000100U) /* Write protection of Sector8 */
#define OB_WRP_Pages288to319 ((uint32_t)0x00000200U) /* Write protection of Sector9 */
#define OB_WRP_Pages320to351 ((uint32_t)0x00000400U) /* Write protection of Sector10 */
#define OB_WRP_Pages352to383 ((uint32_t)0x00000800U) /* Write protection of Sector11 */
#define OB_WRP_Pages384to415 ((uint32_t)0x00001000U) /* Write protection of Sector12 */
#define OB_WRP_Pages416to447 ((uint32_t)0x00002000U) /* Write protection of Sector13 */
#define OB_WRP_Pages448to479 ((uint32_t)0x00004000U) /* Write protection of Sector14 */
#define OB_WRP_Pages480to511 ((uint32_t)0x00008000U) /* Write protection of Sector15 */
#define OB_WRP_Pages512to543 ((uint32_t)0x00010000U) /* Write protection of Sector16 */
#define OB_WRP_Pages544to575 ((uint32_t)0x00020000U) /* Write protection of Sector17 */
#define OB_WRP_Pages576to607 ((uint32_t)0x00040000U) /* Write protection of Sector18 */
#define OB_WRP_Pages608to639 ((uint32_t)0x00080000U) /* Write protection of Sector19 */
#define OB_WRP_Pages640to671 ((uint32_t)0x00100000U) /* Write protection of Sector20 */
#define OB_WRP_Pages672to703 ((uint32_t)0x00200000U) /* Write protection of Sector21 */
#define OB_WRP_Pages704to735 ((uint32_t)0x00400000U) /* Write protection of Sector22 */
#define OB_WRP_Pages736to767 ((uint32_t)0x00800000U) /* Write protection of Sector23 */
#define OB_WRP_Pages768to799 ((uint32_t)0x01000000U) /* Write protection of Sector24 */
#define OB_WRP_Pages800to831 ((uint32_t)0x02000000U) /* Write protection of Sector25 */
#define OB_WRP_Pages832to863 ((uint32_t)0x04000000U) /* Write protection of Sector26 */
#define OB_WRP_Pages864to895 ((uint32_t)0x08000000U) /* Write protection of Sector27 */
#define OB_WRP_Pages896to927 ((uint32_t)0x10000000U) /* Write protection of Sector28 */
#define OB_WRP_Pages928to959 ((uint32_t)0x20000000U) /* Write protection of Sector29 */
#define OB_WRP_Pages960to991 ((uint32_t)0x40000000U) /* Write protection of Sector30 */
#define OB_WRP_Pages992to1023 ((uint32_t)0x80000000U) /* Write protection of Sector31 */
#define OB_WRP_AllPages ((uint32_t)0xFFFFFFFFU) /*!<Write protection of all Sectors */
/**
* @}
*/
@ -246,23 +246,23 @@ typedef struct
/** @defgroup FLASHEx_Option_Bytes_Write_Protection2 FLASH Option Bytes Write Protection
* @{
*/
#define OB_WRP2_Pages1024to1055 ((uint32_t)0x00000001) /* Write protection of Sector32 */
#define OB_WRP2_Pages1056to1087 ((uint32_t)0x00000002) /* Write protection of Sector33 */
#define OB_WRP2_Pages1088to1119 ((uint32_t)0x00000004) /* Write protection of Sector34 */
#define OB_WRP2_Pages1120to1151 ((uint32_t)0x00000008) /* Write protection of Sector35 */
#define OB_WRP2_Pages1152to1183 ((uint32_t)0x00000010) /* Write protection of Sector36 */
#define OB_WRP2_Pages1184to1215 ((uint32_t)0x00000020) /* Write protection of Sector37 */
#define OB_WRP2_Pages1216to1247 ((uint32_t)0x00000040) /* Write protection of Sector38 */
#define OB_WRP2_Pages1248to1279 ((uint32_t)0x00000080) /* Write protection of Sector39 */
#define OB_WRP2_Pages1280to1311 ((uint32_t)0x00000100) /* Write protection of Sector40 */
#define OB_WRP2_Pages1312to1343 ((uint32_t)0x00000200) /* Write protection of Sector41 */
#define OB_WRP2_Pages1344to1375 ((uint32_t)0x00000400) /* Write protection of Sector42 */
#define OB_WRP2_Pages1376to1407 ((uint32_t)0x00000800) /* Write protection of Sector43 */
#define OB_WRP2_Pages1408to1439 ((uint32_t)0x00001000) /* Write protection of Sector44 */
#define OB_WRP2_Pages1440to1471 ((uint32_t)0x00002000) /* Write protection of Sector45 */
#define OB_WRP2_Pages1472to1503 ((uint32_t)0x00004000) /* Write protection of Sector46 */
#define OB_WRP2_Pages1504to1535 ((uint32_t)0x00008000) /* Write protection of Sector47 */
#define OB_WRP2_AllPages ((uint32_t)0x0000FFFF) /*!< Write protection of all Sectors WRP2 */
#define OB_WRP2_Pages1024to1055 ((uint32_t)0x00000001U) /* Write protection of Sector32 */
#define OB_WRP2_Pages1056to1087 ((uint32_t)0x00000002U) /* Write protection of Sector33 */
#define OB_WRP2_Pages1088to1119 ((uint32_t)0x00000004U) /* Write protection of Sector34 */
#define OB_WRP2_Pages1120to1151 ((uint32_t)0x00000008U) /* Write protection of Sector35 */
#define OB_WRP2_Pages1152to1183 ((uint32_t)0x00000010U) /* Write protection of Sector36 */
#define OB_WRP2_Pages1184to1215 ((uint32_t)0x00000020U) /* Write protection of Sector37 */
#define OB_WRP2_Pages1216to1247 ((uint32_t)0x00000040U) /* Write protection of Sector38 */
#define OB_WRP2_Pages1248to1279 ((uint32_t)0x00000080U) /* Write protection of Sector39 */
#define OB_WRP2_Pages1280to1311 ((uint32_t)0x00000100U) /* Write protection of Sector40 */
#define OB_WRP2_Pages1312to1343 ((uint32_t)0x00000200U) /* Write protection of Sector41 */
#define OB_WRP2_Pages1344to1375 ((uint32_t)0x00000400U) /* Write protection of Sector42 */
#define OB_WRP2_Pages1376to1407 ((uint32_t)0x00000800U) /* Write protection of Sector43 */
#define OB_WRP2_Pages1408to1439 ((uint32_t)0x00001000U) /* Write protection of Sector44 */
#define OB_WRP2_Pages1440to1471 ((uint32_t)0x00002000U) /* Write protection of Sector45 */
#define OB_WRP2_Pages1472to1503 ((uint32_t)0x00004000U) /* Write protection of Sector46 */
#define OB_WRP2_Pages1504to1535 ((uint32_t)0x00008000U) /* Write protection of Sector47 */
#define OB_WRP2_AllPages ((uint32_t)0x0000FFFFU) /*!< Write protection of all Sectors WRP2 */
/**
* @}
*/
@ -271,9 +271,9 @@ typedef struct
/** @defgroup FLASHEx_Option_Bytes_Read_Protection FLASH Option Bytes Read Protection
* @{
*/
#define OB_RDP_LEVEL_0 ((uint8_t)0xAA)
#define OB_RDP_LEVEL_1 ((uint8_t)0xBB)
#define OB_RDP_LEVEL_2 ((uint8_t)0xCC) /* Warning: When enabling read protection level 2
#define OB_RDP_LEVEL_0 ((uint8_t)0xAAU)
#define OB_RDP_LEVEL_1 ((uint8_t)0xBBU)
#define OB_RDP_LEVEL_2 ((uint8_t)0xCCU) /* Warning: When enabling read protection level 2
it is no more possible to go back to level 1 or 0 */
/**
* @}
@ -282,13 +282,13 @@ typedef struct
/** @defgroup FLASHEx_Option_Bytes_BOR_Level FLASH Option Bytes BOR Level
* @{
*/
#define OB_BOR_OFF ((uint8_t)0x00) /*!< BOR is disabled at power down, the reset is asserted when the VDD
#define OB_BOR_OFF ((uint8_t)0x00U) /*!< BOR is disabled at power down, the reset is asserted when the VDD
power supply reaches the PDR(Power Down Reset) threshold (1.5V) */
#define OB_BOR_LEVEL1 ((uint8_t)0x08) /*!< BOR Reset threshold levels for 1.7V - 1.8V VDD power supply */
#define OB_BOR_LEVEL2 ((uint8_t)0x09) /*!< BOR Reset threshold levels for 1.9V - 2.0V VDD power supply */
#define OB_BOR_LEVEL3 ((uint8_t)0x0A) /*!< BOR Reset threshold levels for 2.3V - 2.4V VDD power supply */
#define OB_BOR_LEVEL4 ((uint8_t)0x0B) /*!< BOR Reset threshold levels for 2.55V - 2.65V VDD power supply */
#define OB_BOR_LEVEL5 ((uint8_t)0x0C) /*!< BOR Reset threshold levels for 2.8V - 2.9V VDD power supply */
#define OB_BOR_LEVEL1 ((uint8_t)0x08U) /*!< BOR Reset threshold levels for 1.7V - 1.8V VDD power supply */
#define OB_BOR_LEVEL2 ((uint8_t)0x09U) /*!< BOR Reset threshold levels for 1.9V - 2.0V VDD power supply */
#define OB_BOR_LEVEL3 ((uint8_t)0x0AU) /*!< BOR Reset threshold levels for 2.3V - 2.4V VDD power supply */
#define OB_BOR_LEVEL4 ((uint8_t)0x0BU) /*!< BOR Reset threshold levels for 2.55V - 2.65V VDD power supply */
#define OB_BOR_LEVEL5 ((uint8_t)0x0CU) /*!< BOR Reset threshold levels for 2.8V - 2.9V VDD power supply */
/**
* @}
*/
@ -296,8 +296,8 @@ typedef struct
/** @defgroup FLASHEx_Option_Bytes_IWatchdog FLASH Option Bytes IWatchdog
* @{
*/
#define OB_IWDG_SW ((uint8_t)0x10) /*!< Software WDG selected */
#define OB_IWDG_HW ((uint8_t)0x00) /*!< Hardware WDG selected */
#define OB_IWDG_SW ((uint8_t)0x10U) /*!< Software WDG selected */
#define OB_IWDG_HW ((uint8_t)0x00U) /*!< Hardware WDG selected */
/**
* @}
*/
@ -305,8 +305,8 @@ typedef struct
/** @defgroup FLASHEx_Option_Bytes_nRST_STOP FLASHEx Option Bytes nRST_STOP
* @{
*/
#define OB_STOP_NORST ((uint8_t)0x20) /*!< No reset generated when entering in STOP */
#define OB_STOP_RST ((uint8_t)0x00) /*!< Reset generated when entering in STOP */
#define OB_STOP_NORST ((uint8_t)0x20U) /*!< No reset generated when entering in STOP */
#define OB_STOP_RST ((uint8_t)0x00U) /*!< Reset generated when entering in STOP */
/**
* @}
*/
@ -314,8 +314,8 @@ typedef struct
/** @defgroup FLASHEx_Option_Bytes_nRST_STDBY FLASH Option Bytes nRST_STDBY
* @{
*/
#define OB_STDBY_NORST ((uint8_t)0x40) /*!< No reset generated when entering in STANDBY */
#define OB_STDBY_RST ((uint8_t)0x00) /*!< Reset generated when entering in STANDBY */
#define OB_STDBY_NORST ((uint8_t)0x40U) /*!< No reset generated when entering in STANDBY */
#define OB_STDBY_RST ((uint8_t)0x00U) /*!< Reset generated when entering in STANDBY */
/**
* @}
*/
@ -324,8 +324,8 @@ typedef struct
/** @defgroup FLASHEx_PCROP_State FLASH PCROP State
* @{
*/
#define OB_PCROP_STATE_DISABLE ((uint8_t)0x00) /*!< Disable PCROP */
#define OB_PCROP_STATE_ENABLE ((uint8_t)0x01) /*!< Enable PCROP */
#define OB_PCROP_STATE_DISABLE ((uint8_t)0x00U) /*!< Disable PCROP */
#define OB_PCROP_STATE_ENABLE ((uint8_t)0x01U) /*!< Enable PCROP */
/**
* @}
*/
@ -335,10 +335,10 @@ typedef struct
* @{
*/
#if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
#define OPTIONBYTE_PCROP ((uint32_t)0x01) /*!< PCROP option byte configuration*/
#define OPTIONBYTE_BOOTCONFIG ((uint32_t)0x02) /*!< BOOTConfig option byte configuration, boot from bank 2*/
#define OPTIONBYTE_PCROP ((uint32_t)0x01U) /*!< PCROP option byte configuration*/
#define OPTIONBYTE_BOOTCONFIG ((uint32_t)0x02U) /*!< BOOTConfig option byte configuration, boot from bank 2*/
#else /* if STM32L071xx || STM32L072xx || STM32L073xx || STM32L081xx || STM32L082xx || STM32L083xx */
#define OPTIONBYTE_PCROP ((uint32_t)0x01) /*!< PCROP option byte configuration*/
#define OPTIONBYTE_PCROP ((uint32_t)0x01U) /*!< PCROP option byte configuration*/
#endif /* if STM32L071xx || STM32L072xx || STM32L073xx || STM32L081xx || STM32L082xx || STM32L083xx */
/**
* @}
@ -348,15 +348,15 @@ typedef struct
/** @defgroup FLASHEx_Option_Bytes_PC_ReadWrite_Protection FLASHEx Option Bytes PC Read/Write Protection
* @{
*/
#define OB_PCROP_Pages0to31 ((uint32_t)0x00000001) /* PC Read/Write protection of Sector0 */
#define OB_PCROP_Pages32to63 ((uint32_t)0x00000002) /* PC Read/Write protection of Sector1 */
#define OB_PCROP_Pages64to95 ((uint32_t)0x00000004) /* PC Read/Write protection of Sector2 */
#define OB_PCROP_Pages96to127 ((uint32_t)0x00000008) /* PC Read/Write protection of Sector3 */
#define OB_PCROP_Pages128to159 ((uint32_t)0x00000010) /* PC Read/Write protection of Sector4 */
#define OB_PCROP_Pages160to191 ((uint32_t)0x00000020) /* PC Read/Write protection of Sector5 */
#define OB_PCROP_Pages192to223 ((uint32_t)0x00000040) /* PC Read/Write protection of Sector6 */
#define OB_PCROP_Pages224to255 ((uint32_t)0x00000080) /* PC Read/Write protection of Sector7 */
#define OB_PCROP_AllPages ((uint32_t)0x000000FF) /*!< PC Read/Write protection of all Sectors */
#define OB_PCROP_Pages0to31 ((uint32_t)0x00000001U) /* PC Read/Write protection of Sector0 */
#define OB_PCROP_Pages32to63 ((uint32_t)0x00000002U) /* PC Read/Write protection of Sector1 */
#define OB_PCROP_Pages64to95 ((uint32_t)0x00000004U) /* PC Read/Write protection of Sector2 */
#define OB_PCROP_Pages96to127 ((uint32_t)0x00000008U) /* PC Read/Write protection of Sector3 */
#define OB_PCROP_Pages128to159 ((uint32_t)0x00000010U) /* PC Read/Write protection of Sector4 */
#define OB_PCROP_Pages160to191 ((uint32_t)0x00000020U) /* PC Read/Write protection of Sector5 */
#define OB_PCROP_Pages192to223 ((uint32_t)0x00000040U) /* PC Read/Write protection of Sector6 */
#define OB_PCROP_Pages224to255 ((uint32_t)0x00000080U) /* PC Read/Write protection of Sector7 */
#define OB_PCROP_AllPages ((uint32_t)0x000000FFU) /*!< PC Read/Write protection of all Sectors */
/**
* @}
*/
@ -364,23 +364,23 @@ typedef struct
/** @defgroup FLASHEx_Option_Bytes_PC_ReadWrite_Protection FLASHEx Option Bytes PC Read/Write Protection
* @{
*/
#define OB_PCROP_Pages0to31 ((uint32_t)0x00000001) /* PC Read/Write protection of Sector0 */
#define OB_PCROP_Pages32to63 ((uint32_t)0x00000002) /* PC Read/Write protection of Sector1 */
#define OB_PCROP_Pages64to95 ((uint32_t)0x00000004) /* PC Read/Write protection of Sector2 */
#define OB_PCROP_Pages96to127 ((uint32_t)0x00000008) /* PC Read/Write protection of Sector3 */
#define OB_PCROP_Pages128to159 ((uint32_t)0x00000010) /* PC Read/Write protection of Sector4 */
#define OB_PCROP_Pages160to191 ((uint32_t)0x00000020) /* PC Read/Write protection of Sector5 */
#define OB_PCROP_Pages192to223 ((uint32_t)0x00000040) /* PC Read/Write protection of Sector6 */
#define OB_PCROP_Pages224to255 ((uint32_t)0x00000080) /* PC Read/Write protection of Sector7 */
#define OB_PCROP_Pages256to287 ((uint32_t)0x00000100) /* PC Read/Write protection of Sector8 */
#define OB_PCROP_Pages288to319 ((uint32_t)0x00000200) /* PC Read/Write protection of Sector9 */
#define OB_PCROP_Pages320to351 ((uint32_t)0x00000400) /* PC Read/Write protection of Sector10 */
#define OB_PCROP_Pages352to383 ((uint32_t)0x00000800) /* PC Read/Write protection of Sector11 */
#define OB_PCROP_Pages384to415 ((uint32_t)0x00001000) /* PC Read/Write protection of Sector12 */
#define OB_PCROP_Pages416to447 ((uint32_t)0x00002000) /* PC Read/Write protection of Sector13 */
#define OB_PCROP_Pages448to479 ((uint32_t)0x00004000) /* PC Read/Write protection of Sector14 */
#define OB_PCROP_Pages480to511 ((uint32_t)0x00008000) /* PC Read/Write protection of Sector15 */
#define OB_PCROP_AllPages ((uint32_t)0x0000FFFF) /*!< PC Read/Write protection of all Sectors */
#define OB_PCROP_Pages0to31 ((uint32_t)0x00000001U) /* PC Read/Write protection of Sector0 */
#define OB_PCROP_Pages32to63 ((uint32_t)0x00000002U) /* PC Read/Write protection of Sector1 */
#define OB_PCROP_Pages64to95 ((uint32_t)0x00000004U) /* PC Read/Write protection of Sector2 */
#define OB_PCROP_Pages96to127 ((uint32_t)0x00000008U) /* PC Read/Write protection of Sector3 */
#define OB_PCROP_Pages128to159 ((uint32_t)0x00000010U) /* PC Read/Write protection of Sector4 */
#define OB_PCROP_Pages160to191 ((uint32_t)0x00000020U) /* PC Read/Write protection of Sector5 */
#define OB_PCROP_Pages192to223 ((uint32_t)0x00000040U) /* PC Read/Write protection of Sector6 */
#define OB_PCROP_Pages224to255 ((uint32_t)0x00000080U) /* PC Read/Write protection of Sector7 */
#define OB_PCROP_Pages256to287 ((uint32_t)0x00000100U) /* PC Read/Write protection of Sector8 */
#define OB_PCROP_Pages288to319 ((uint32_t)0x00000200U) /* PC Read/Write protection of Sector9 */
#define OB_PCROP_Pages320to351 ((uint32_t)0x00000400U) /* PC Read/Write protection of Sector10 */
#define OB_PCROP_Pages352to383 ((uint32_t)0x00000800U) /* PC Read/Write protection of Sector11 */
#define OB_PCROP_Pages384to415 ((uint32_t)0x00001000U) /* PC Read/Write protection of Sector12 */
#define OB_PCROP_Pages416to447 ((uint32_t)0x00002000U) /* PC Read/Write protection of Sector13 */
#define OB_PCROP_Pages448to479 ((uint32_t)0x00004000U) /* PC Read/Write protection of Sector14 */
#define OB_PCROP_Pages480to511 ((uint32_t)0x00008000U) /* PC Read/Write protection of Sector15 */
#define OB_PCROP_AllPages ((uint32_t)0x0000FFFFU) /*!< PC Read/Write protection of all Sectors */
/**
* @}
*/
@ -390,39 +390,39 @@ typedef struct
/** @defgroup FLASHEx_Option_Bytes_PC_ReadWrite_Protection FLASH Option Bytes PC Read/Write Protection
* @{
*/
#define OB_PCROP_Pages0to31 ((uint32_t)0x00000001) /* PC Read/Write protection of Sector0 */
#define OB_PCROP_Pages32to63 ((uint32_t)0x00000002) /* PC Read/Write protection of Sector1 */
#define OB_PCROP_Pages64to95 ((uint32_t)0x00000004) /* PC Read/Write protection of Sector2 */
#define OB_PCROP_Pages96to127 ((uint32_t)0x00000008) /* PC Read/Write protection of Sector3 */
#define OB_PCROP_Pages128to159 ((uint32_t)0x00000010) /* PC Read/Write protection of Sector4 */
#define OB_PCROP_Pages160to191 ((uint32_t)0x00000020) /* PC Read/Write protection of Sector5 */
#define OB_PCROP_Pages192to223 ((uint32_t)0x00000040) /* PC Read/Write protection of Sector6 */
#define OB_PCROP_Pages224to255 ((uint32_t)0x00000080) /* PC Read/Write protection of Sector7 */
#define OB_PCROP_Pages256to287 ((uint32_t)0x00000100) /* PC Read/Write protection of Sector8 */
#define OB_PCROP_Pages288to319 ((uint32_t)0x00000200) /* PC Read/Write protection of Sector9 */
#define OB_PCROP_Pages320to351 ((uint32_t)0x00000400) /* PC Read/Write protection of Sector10 */
#define OB_PCROP_Pages352to383 ((uint32_t)0x00000800) /* PC Read/Write protection of Sector11 */
#define OB_PCROP_Pages384to415 ((uint32_t)0x00001000) /* PC Read/Write protection of Sector12 */
#define OB_PCROP_Pages416to447 ((uint32_t)0x00002000) /* PC Read/Write protection of Sector13 */
#define OB_PCROP_Pages448to479 ((uint32_t)0x00004000) /* PC Read/Write protection of Sector14 */
#define OB_PCROP_Pages480to511 ((uint32_t)0x00008000) /* PC Read/Write protection of Sector15 */
#define OB_PCROP_Pages512to543 ((uint32_t)0x00010000) /* PC Read/Write protection of Sector16 */
#define OB_PCROP_Pages544to575 ((uint32_t)0x00020000) /* PC Read/Write protection of Sector17 */
#define OB_PCROP_Pages576to607 ((uint32_t)0x00040000) /* PC Read/Write protection of Sector18 */
#define OB_PCROP_Pages608to639 ((uint32_t)0x00080000) /* PC Read/Write protection of Sector19 */
#define OB_PCROP_Pages640to671 ((uint32_t)0x00100000) /* PC Read/Write protection of Sector20 */
#define OB_PCROP_Pages672to703 ((uint32_t)0x00200000) /* PC Read/Write protection of Sector21 */
#define OB_PCROP_Pages704to735 ((uint32_t)0x00400000) /* PC Read/Write protection of Sector22 */
#define OB_PCROP_Pages736to767 ((uint32_t)0x00800000) /* PC Read/Write protection of Sector23 */
#define OB_PCROP_Pages768to799 ((uint32_t)0x01000000) /* PC Read/Write protection of Sector24 */
#define OB_PCROP_Pages800to831 ((uint32_t)0x02000000) /* PC Read/Write protection of Sector25 */
#define OB_PCROP_Pages832to863 ((uint32_t)0x04000000) /* PC Read/Write protection of Sector26 */
#define OB_PCROP_Pages864to895 ((uint32_t)0x08000000) /* PC Read/Write protection of Sector27 */
#define OB_PCROP_Pages896to927 ((uint32_t)0x10000000) /* PC Read/Write protection of Sector28 */
#define OB_PCROP_Pages928to959 ((uint32_t)0x20000000) /* PC Read/Write protection of Sector29 */
#define OB_PCROP_Pages960to991 ((uint32_t)0x40000000) /* PC Read/Write protection of Sector30 */
#define OB_PCROP_Pages992to1023 ((uint32_t)0x80000000) /* PC Read/Write protection of Sector31 */
#define OB_PCROP_AllPages ((uint32_t)0xFFFFFFFF) /*!<PC Read/Write protection of all Sectors */
#define OB_PCROP_Pages0to31 ((uint32_t)0x00000001U) /* PC Read/Write protection of Sector0 */
#define OB_PCROP_Pages32to63 ((uint32_t)0x00000002U) /* PC Read/Write protection of Sector1 */
#define OB_PCROP_Pages64to95 ((uint32_t)0x00000004U) /* PC Read/Write protection of Sector2 */
#define OB_PCROP_Pages96to127 ((uint32_t)0x00000008U) /* PC Read/Write protection of Sector3 */
#define OB_PCROP_Pages128to159 ((uint32_t)0x00000010U) /* PC Read/Write protection of Sector4 */
#define OB_PCROP_Pages160to191 ((uint32_t)0x00000020U) /* PC Read/Write protection of Sector5 */
#define OB_PCROP_Pages192to223 ((uint32_t)0x00000040U) /* PC Read/Write protection of Sector6 */
#define OB_PCROP_Pages224to255 ((uint32_t)0x00000080U) /* PC Read/Write protection of Sector7 */
#define OB_PCROP_Pages256to287 ((uint32_t)0x00000100U) /* PC Read/Write protection of Sector8 */
#define OB_PCROP_Pages288to319 ((uint32_t)0x00000200U) /* PC Read/Write protection of Sector9 */
#define OB_PCROP_Pages320to351 ((uint32_t)0x00000400U) /* PC Read/Write protection of Sector10 */
#define OB_PCROP_Pages352to383 ((uint32_t)0x00000800U) /* PC Read/Write protection of Sector11 */
#define OB_PCROP_Pages384to415 ((uint32_t)0x00001000U) /* PC Read/Write protection of Sector12 */
#define OB_PCROP_Pages416to447 ((uint32_t)0x00002000U) /* PC Read/Write protection of Sector13 */
#define OB_PCROP_Pages448to479 ((uint32_t)0x00004000U) /* PC Read/Write protection of Sector14 */
#define OB_PCROP_Pages480to511 ((uint32_t)0x00008000U) /* PC Read/Write protection of Sector15 */
#define OB_PCROP_Pages512to543 ((uint32_t)0x00010000U) /* PC Read/Write protection of Sector16 */
#define OB_PCROP_Pages544to575 ((uint32_t)0x00020000U) /* PC Read/Write protection of Sector17 */
#define OB_PCROP_Pages576to607 ((uint32_t)0x00040000U) /* PC Read/Write protection of Sector18 */
#define OB_PCROP_Pages608to639 ((uint32_t)0x00080000U) /* PC Read/Write protection of Sector19 */
#define OB_PCROP_Pages640to671 ((uint32_t)0x00100000U) /* PC Read/Write protection of Sector20 */
#define OB_PCROP_Pages672to703 ((uint32_t)0x00200000U) /* PC Read/Write protection of Sector21 */
#define OB_PCROP_Pages704to735 ((uint32_t)0x00400000U) /* PC Read/Write protection of Sector22 */
#define OB_PCROP_Pages736to767 ((uint32_t)0x00800000U) /* PC Read/Write protection of Sector23 */
#define OB_PCROP_Pages768to799 ((uint32_t)0x01000000U) /* PC Read/Write protection of Sector24 */
#define OB_PCROP_Pages800to831 ((uint32_t)0x02000000U) /* PC Read/Write protection of Sector25 */
#define OB_PCROP_Pages832to863 ((uint32_t)0x04000000U) /* PC Read/Write protection of Sector26 */
#define OB_PCROP_Pages864to895 ((uint32_t)0x08000000U) /* PC Read/Write protection of Sector27 */
#define OB_PCROP_Pages896to927 ((uint32_t)0x10000000U) /* PC Read/Write protection of Sector28 */
#define OB_PCROP_Pages928to959 ((uint32_t)0x20000000U) /* PC Read/Write protection of Sector29 */
#define OB_PCROP_Pages960to991 ((uint32_t)0x40000000U) /* PC Read/Write protection of Sector30 */
#define OB_PCROP_Pages992to1023 ((uint32_t)0x80000000U) /* PC Read/Write protection of Sector31 */
#define OB_PCROP_AllPages ((uint32_t)0xFFFFFFFFU) /*!<PC Read/Write protection of all Sectors */
/**
* @}
*/
@ -430,23 +430,23 @@ typedef struct
/** @defgroup FLASHEx_Option_Bytes_PC_ReadWrite_Protection2 FLASH Option Bytes PC Read/Write Protection (Sector 2)
* @{
*/
#define OB_PCROP2_Pages1024to1055 ((uint32_t)0x00000001) /* PC Read/Write protection of Sector32 */
#define OB_PCROP2_Pages1056to1087 ((uint32_t)0x00000002) /* PC Read/Write protection of Sector33 */
#define OB_PCROP2_Pages1088to1119 ((uint32_t)0x00000004) /* PC Read/Write protection of Sector34 */
#define OB_PCROP2_Pages1120to1151 ((uint32_t)0x00000008) /* PC Read/Write protection of Sector35 */
#define OB_PCROP2_Pages1152to1183 ((uint32_t)0x00000010) /* PC Read/Write protection of Sector36 */
#define OB_PCROP2_Pages1184to1215 ((uint32_t)0x00000020) /* PC Read/Write protection of Sector37 */
#define OB_PCROP2_Pages1216to1247 ((uint32_t)0x00000040) /* PC Read/Write protection of Sector38 */
#define OB_PCROP2_Pages1248to1279 ((uint32_t)0x00000080) /* PC Read/Write protection of Sector39 */
#define OB_PCROP2_Pages1280to1311 ((uint32_t)0x00000100) /* PC Read/Write protection of Sector40 */
#define OB_PCROP2_Pages1312to1343 ((uint32_t)0x00000200) /* PC Read/Write protection of Sector41 */
#define OB_PCROP2_Pages1344to1375 ((uint32_t)0x00000400) /* PC Read/Write protection of Sector42 */
#define OB_PCROP2_Pages1376to1407 ((uint32_t)0x00000800) /* PC Read/Write protection of Sector43 */
#define OB_PCROP2_Pages1408to1439 ((uint32_t)0x00001000) /* PC Read/Write protection of Sector44 */
#define OB_PCROP2_Pages1440to1471 ((uint32_t)0x00002000) /* PC Read/Write protection of Sector45 */
#define OB_PCROP2_Pages1472to1503 ((uint32_t)0x00004000) /* PC Read/Write protection of Sector46 */
#define OB_PCROP2_Pages1504to1535 ((uint32_t)0x00008000) /* PC Read/Write protection of Sector47 */
#define OB_PCROP2_AllPages ((uint32_t)0x0000FFFF) /*!< PC Read/Write protection of all Sectors PCROP2 */
#define OB_PCROP2_Pages1024to1055 ((uint32_t)0x00000001U) /* PC Read/Write protection of Sector32 */
#define OB_PCROP2_Pages1056to1087 ((uint32_t)0x00000002U) /* PC Read/Write protection of Sector33 */
#define OB_PCROP2_Pages1088to1119 ((uint32_t)0x00000004U) /* PC Read/Write protection of Sector34 */
#define OB_PCROP2_Pages1120to1151 ((uint32_t)0x00000008U) /* PC Read/Write protection of Sector35 */
#define OB_PCROP2_Pages1152to1183 ((uint32_t)0x00000010U) /* PC Read/Write protection of Sector36 */
#define OB_PCROP2_Pages1184to1215 ((uint32_t)0x00000020U) /* PC Read/Write protection of Sector37 */
#define OB_PCROP2_Pages1216to1247 ((uint32_t)0x00000040U) /* PC Read/Write protection of Sector38 */
#define OB_PCROP2_Pages1248to1279 ((uint32_t)0x00000080U) /* PC Read/Write protection of Sector39 */
#define OB_PCROP2_Pages1280to1311 ((uint32_t)0x00000100U) /* PC Read/Write protection of Sector40 */
#define OB_PCROP2_Pages1312to1343 ((uint32_t)0x00000200U) /* PC Read/Write protection of Sector41 */
#define OB_PCROP2_Pages1344to1375 ((uint32_t)0x00000400U) /* PC Read/Write protection of Sector42 */
#define OB_PCROP2_Pages1376to1407 ((uint32_t)0x00000800U) /* PC Read/Write protection of Sector43 */
#define OB_PCROP2_Pages1408to1439 ((uint32_t)0x00001000U) /* PC Read/Write protection of Sector44 */
#define OB_PCROP2_Pages1440to1471 ((uint32_t)0x00002000U) /* PC Read/Write protection of Sector45 */
#define OB_PCROP2_Pages1472to1503 ((uint32_t)0x00004000U) /* PC Read/Write protection of Sector46 */
#define OB_PCROP2_Pages1504to1535 ((uint32_t)0x00008000U) /* PC Read/Write protection of Sector47 */
#define OB_PCROP2_AllPages ((uint32_t)0x0000FFFFU) /*!< PC Read/Write protection of all Sectors PCROP2 */
/**
* @}
*/
@ -455,8 +455,8 @@ typedef struct
/** @defgroup FLASHEx_Option_Bytes_BOOTBit1 FLASH Option Bytes BOOT Bit1 Setup
* @{
*/
#define OB_BOOT_BIT1_RESET (uint8_t)(0x00) /*!< BOOT Bit 1 Reset */
#define OB_BOOT_BIT1_SET (uint8_t)(0x01) /*!< BOOT Bit 1 Set */
#define OB_BOOT_BIT1_RESET (uint8_t)(0x00U) /*!< BOOT Bit 1 Reset */
#define OB_BOOT_BIT1_SET (uint8_t)(0x01U) /*!< BOOT Bit 1 Set */
/**
* @}
*/
@ -465,9 +465,9 @@ typedef struct
/** @defgroup FLASHEx_Option_Bytes_BOOT_BANK FLASH Option Bytes BOOT BANK
* @{
*/
#define OB_BOOT_BANK1 ((uint8_t)0x00) /*!< At startup, if boot pin 0 and BOOT1 bit are set in boot from user Flash position
#define OB_BOOT_BANK1 ((uint8_t)0x00U) /*!< At startup, if boot pin 0 and BOOT1 bit are set in boot from user Flash position
and this parameter is selected the device will boot from Bank 1 (Default)*/
#define OB_BOOT_BANK2 (uint8_t)(0x01) /*!< At startup, if boot pin 0 and BOOT1 bit are set in boot from user Flash position
#define OB_BOOT_BANK2 (uint8_t)(0x01U) /*!< At startup, if boot pin 0 and BOOT1 bit are set in boot from user Flash position
and this parameter is selected the device will boot from Bank 2 */
/**
* @}
@ -477,9 +477,9 @@ typedef struct
/** @defgroup FLASHEx_Type_Program_Data FLASH Type Program Data
* @{
*/
#define FLASH_TYPEPROGRAMDATA_BYTE ((uint32_t)0x00) /*!< Program byte (8-bit) at a specified address.*/
#define FLASH_TYPEPROGRAMDATA_HALFWORD ((uint32_t)0x01) /*!< Program a half-word (16-bit) at a specified address.*/
#define FLASH_TYPEPROGRAMDATA_WORD ((uint32_t)0x02) /*!< Program a word (32-bit) at a specified address.*/
#define FLASH_TYPEPROGRAMDATA_BYTE ((uint32_t)0x00U) /*!< Program byte (8-bit) at a specified address.*/
#define FLASH_TYPEPROGRAMDATA_HALFWORD ((uint32_t)0x01U) /*!< Program a half-word (16-bit) at a specified address.*/
#define FLASH_TYPEPROGRAMDATA_WORD ((uint32_t)0x02U) /*!< Program a word (32-bit) at a specified address.*/
/* Aliases for compatibility with the V1.0.0 package */
#define FLASH_TYPEPROGRAM_BYTE FLASH_TYPEPROGRAMDATA_BYTE
@ -529,8 +529,8 @@ typedef struct
* @brief Enable/Disable the FLASH prefetch buffer.
* @retval none
*/
#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() CLEAR_BIT((FLASH->ACR), FLASH_ACR_PRFTEN)
#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() SET_BIT((FLASH->ACR), FLASH_ACR_PRFTEN)
#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() SET_BIT((FLASH->ACR), FLASH_ACR_PRFTEN)
#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() CLEAR_BIT((FLASH->ACR), FLASH_ACR_PRFTEN)
/**
* @brief Enable/Disable the FLASH Buffer cache.
@ -632,7 +632,7 @@ void HAL_FLASHEx_DATAEEPROM_DisableFixedTimeProgram(void);
#define IS_WRPSTATE(__VALUE__) (((__VALUE__) == OB_WRPSTATE_DISABLE) || \
((__VALUE__) == OB_WRPSTATE_ENABLE))
#define IS_OB_WRP(PAGE) (((PAGE) != 0x0000000))
#define IS_OB_WRP(PAGE) (((PAGE) != 0x0000000U))
#define IS_OB_RDP(__LEVEL__) (((__LEVEL__) == OB_RDP_LEVEL_0)||\
((__LEVEL__) == OB_RDP_LEVEL_1)||\
@ -654,7 +654,7 @@ void HAL_FLASHEx_DATAEEPROM_DisableFixedTimeProgram(void);
#define IS_PCROPSTATE(VALUE)(((VALUE) == OB_PCROP_STATE_DISABLE) || \
((VALUE) == OB_PCROP_STATE_ENABLE))
#define IS_OB_PCROP(__PAGE__) (((__PAGE__) != 0x0000000))
#define IS_OB_PCROP(__PAGE__) (((__PAGE__) != 0x0000000U))
#define IS_OB_BOOT1(__BOOT_BIT1__) (((__BOOT_BIT1__) == OB_BOOT_BIT1_RESET) || ((__BOOT_BIT1__) == OB_BOOT_BIT1_SET))

28
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_flash_ramfunc.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx_hal_flash_ramfunc.c
* @author MCD Application Team
* @version V1.5.0
* @date 8-January-2016
* @version V1.7.0
* @date 31-May-2016
* @brief FLASH RAMFUNC driver.
* This file provides a Flash firmware functions which should be
* executed from internal SRAM
@ -177,9 +177,9 @@ __RAM_FUNC HAL_FLASHEx_EraseParallelPage(uint32_t Page_Address1, uint32_t Page_A
SET_BIT(FLASH->PECR, FLASH_PECR_PROG);
/* Write 00000000h to the first word of the first program page to erase */
*(__IO uint32_t *)Page_Address1 = 0x00000000;
*(__IO uint32_t *)Page_Address1 = 0x00000000U;
/* Write 00000000h to the first word of the second program page to erase */
*(__IO uint32_t *)Page_Address2 = 0x00000000;
*(__IO uint32_t *)Page_Address2 = 0x00000000U;
/* Wait for last operation to be completed */
status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
@ -245,12 +245,12 @@ __RAM_FUNC HAL_FLASHEx_ProgramParallelHalfPage(uint32_t Address1, uint32_t* pBuf
{
/* Write one half page,
Address1 doesn't need to be increased */
count = 0;
count = 0U;
/* Disable all IRQs */
__disable_irq();
while(count < 16)
while(count < 16U)
{
*(__IO uint32_t*) Address1 = *pBuffer1;
pBuffer1++;
@ -259,8 +259,8 @@ __RAM_FUNC HAL_FLASHEx_ProgramParallelHalfPage(uint32_t Address1, uint32_t* pBuf
/* Write the second half page,
Address2 doesn't need to be increased */
count = 0;
while(count < 16)
count = 0U;
while(count < 16U)
{
*(__IO uint32_t*) Address2 = *pBuffer2;
pBuffer2++;
@ -328,14 +328,14 @@ __RAM_FUNC HAL_FLASHEx_HalfPageProgram(uint32_t Address, uint32_t *pBuffer)
SET_BIT(FLASH->PECR, FLASH_PECR_PROG);
count = 0;
count = 0U;
/* Write one half page,
Address doesn't need to be increased */
/* Disable all IRQs */
__disable_irq();
while(count < 16)
while(count < 16U)
{
*(__IO uint32_t*) Address = *pBuffer;
pBuffer++;
@ -407,10 +407,10 @@ static __RAM_FUNC FLASHRAM_SetErrorCode(void)
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR))
{
/* WARNING : On the first cut of STM32L031xx and STM32L041xx devices,
* (RevID = 0x1000) the FLASH_FLAG_OPTVERR bit was not behaving
* (RefID = 0x1000) the FLASH_FLAG_OPTVERR bit was not behaving
* as expected. If the user run an application using the first
* cut of the STM32L031xx device or the first cut of the STM32L041xx
* device, this error should be ignored. The RevID of the device
* device, this error should be ignored. The revId of the device
* can be retrieved via the HAL_GetREVID() function.
*
*/
@ -449,12 +449,12 @@ static __RAM_FUNC FLASHRAM_WaitForLastOperation(uint32_t Timeout)
Even if the FLASH operation fails, the BUSY flag will be reset and an error
flag will be set */
while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY) && (Timeout != 0x00))
while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY) && (Timeout != 0x00U))
{
Timeout--;
}
if(Timeout == 0x00 )
if(Timeout == 0x00U )
{
return HAL_TIMEOUT;
}

4
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_flash_ramfunc.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx_hal_flash_ramfunc.h
* @author MCD Application Team
* @version V1.5.0
* @date 8-January-2016
* @version V1.7.0
* @date 31-May-2016
* @brief Header file of FLASH RAMFUNC driver.
******************************************************************************
* @attention

84
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_gpio.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx_hal_gpio.c
* @author MCD Application Team
* @version V1.5.0
* @date 8-January-2016
* @version V1.7.0
* @date 31-May-2016
* @brief GPIO HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the General Purpose Input/Output (GPIO) peripheral:
@ -145,15 +145,15 @@
/* Private define ------------------------------------------------------------*/
#define GPIO_MODE ((uint32_t)0x00000003)
#define EXTI_MODE ((uint32_t)0x10000000)
#define GPIO_MODE_IT ((uint32_t)0x00010000)
#define GPIO_MODE_EVT ((uint32_t)0x00020000)
#define RISING_EDGE ((uint32_t)0x00100000)
#define FALLING_EDGE ((uint32_t)0x00200000)
#define GPIO_OUTPUT_TYPE ((uint32_t)0x00000010)
#define GPIO_MODE ((uint32_t)0x00000003U)
#define EXTI_MODE ((uint32_t)0x10000000U)
#define GPIO_MODE_IT ((uint32_t)0x00010000U)
#define GPIO_MODE_EVT ((uint32_t)0x00020000U)
#define RISING_EDGE ((uint32_t)0x00100000U)
#define FALLING_EDGE ((uint32_t)0x00200000U)
#define GPIO_OUTPUT_TYPE ((uint32_t)0x00000010U)
#define GPIO_NUMBER ((uint32_t)16)
#define GPIO_NUMBER ((uint32_t)16U)
/**
* @}
@ -184,9 +184,9 @@
*/
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
uint32_t position = 0x00;
uint32_t iocurrent = 0x00;
uint32_t temp = 0x00;
uint32_t position = 0x00U;
uint32_t iocurrent = 0x00U;
uint32_t temp = 0x00U;
/* Check the parameters */
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
@ -197,7 +197,7 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
while ((GPIO_Init->Pin) >> position)
{
/* Get the IO position */
iocurrent = (GPIO_Init->Pin) & (1 << position);
iocurrent = (GPIO_Init->Pin) & (1U << position);
if(iocurrent)
{
@ -208,10 +208,10 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
/* Check if the Alternate function is compliant with the GPIO in use */
assert_param(IS_GPIO_AF_AVAILABLE(GPIOx,(GPIO_Init->Alternate)));
/* Configure Alternate function mapped with the current IO */
temp = GPIOx->AFR[position >> 3];
temp &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ;
temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & (uint32_t)0x07) * 4)) ;
GPIOx->AFR[position >> 3] = temp;
temp = GPIOx->AFR[position >> 3U];
temp &= ~((uint32_t)0xFU << ((uint32_t)(position & (uint32_t)0x07U) * 4U)) ;
temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & (uint32_t)0x07U) * 4U)) ;
GPIOx->AFR[position >> 3U] = temp;
}
/* In case of Output or Alternate function mode selection */
@ -222,27 +222,27 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
/* Configure the IO Speed */
temp = GPIOx->OSPEEDR;
temp &= ~(GPIO_OSPEEDER_OSPEED0 << (position * 2));
temp |= (GPIO_Init->Speed << (position * 2));
temp &= ~(GPIO_OSPEEDER_OSPEED0 << (position * 2U));
temp |= (GPIO_Init->Speed << (position * 2U));
GPIOx->OSPEEDR = temp;
/* Configure the IO Output Type */
temp= GPIOx->OTYPER;
temp &= ~(GPIO_OTYPER_OT_0 << position) ;
temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4) << position);
temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4U) << position);
GPIOx->OTYPER = temp;
}
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
temp = GPIOx->MODER;
temp &= ~(GPIO_MODER_MODE0 << (position * 2));
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2));
temp &= ~(GPIO_MODER_MODE0 << (position * 2U));
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
GPIOx->MODER = temp;
/* Activate the Pull-up or Pull down resistor for the current IO */
temp = GPIOx->PUPDR;
temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2));
temp |= ((GPIO_Init->Pull) << (position * 2));
temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U));
temp |= ((GPIO_Init->Pull) << (position * 2U));
GPIOx->PUPDR = temp;
/*--------------------- EXTI Mode Configuration ------------------------*/
@ -252,10 +252,10 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
/* Enable SYSCFG Clock */
__HAL_RCC_SYSCFG_CLK_ENABLE();
temp = SYSCFG->EXTICR[position >> 2];
temp &= ~(((uint32_t)0x0F) << (4 * (position & 0x03)));
temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03)));
SYSCFG->EXTICR[position >> 2] = temp;
temp = SYSCFG->EXTICR[position >> 2U];
temp &= ~(((uint32_t)0x0FU) << (4U * (position & 0x03U)));
temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U)));
SYSCFG->EXTICR[position >> 2U] = temp;
/* Clear EXTI line configuration */
temp = EXTI->IMR;
@ -307,9 +307,9 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
*/
void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
{
uint32_t position = 0x00;
uint32_t iocurrent = 0x00;
uint32_t tmp = 0x00;
uint32_t position = 0x00U;
uint32_t iocurrent = 0x00U;
uint32_t tmp = 0x00U;
/* Check the parameters */
assert_param(IS_GPIO_PIN_AVAILABLE(GPIOx,GPIO_Pin));
@ -318,35 +318,35 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
while (GPIO_Pin >> position)
{
/* Get the IO position */
iocurrent = (GPIO_Pin) & (1 << position);
iocurrent = (GPIO_Pin) & (1U << position);
if(iocurrent)
{
/*------------------------- GPIO Mode Configuration --------------------*/
/* Configure IO Direction in Input Floting Mode */
GPIOx->MODER &= ~(GPIO_MODER_MODE0 << (position * 2));
GPIOx->MODER &= ~(GPIO_MODER_MODE0 << (position * 2U));
/* Configure the default Alternate Function in current IO */
GPIOx->AFR[position >> 3] &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ;
GPIOx->AFR[position >> 3U] &= ~((uint32_t)0xFU << ((uint32_t)(position & (uint32_t)0x07U) * 4U)) ;
/* Configure the default value for IO Speed */
GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEED0 << (position * 2));
GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEED0 << (position * 2U));
/* Configure the default value IO Output Type */
GPIOx->OTYPER &= ~(GPIO_OTYPER_OT_0 << position) ;
/* Deactivate the Pull-up oand Pull-down resistor for the current IO */
GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPD0 << (position * 2));
GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPD0 << (position * 2U));
/*------------------------- EXTI Mode Configuration --------------------*/
/* Clear the External Interrupt or Event for the current IO */
tmp = SYSCFG->EXTICR[position >> 2];
tmp &= (((uint32_t)0x0F) << (4 * (position & 0x03)));
if(tmp == (GPIO_GET_INDEX(GPIOx) << (4 * (position & 0x03))))
tmp = SYSCFG->EXTICR[position >> 2U];
tmp &= (((uint32_t)0x0FU) << (4U * (position & 0x03U)));
if(tmp == (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U))))
{
tmp = ((uint32_t)0x0F) << (4 * (position & 0x03));
SYSCFG->EXTICR[position >> 2] &= ~tmp;
tmp = ((uint32_t)0x0FU) << (4U * (position & 0x03U));
SYSCFG->EXTICR[position >> 2U] &= ~tmp;
/* Clear EXTI line configuration */
EXTI->IMR &= ~((uint32_t)iocurrent);

82
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_gpio.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx_hal_gpio.h
* @author MCD Application Team
* @version V1.5.0
* @date 8-January-2016
* @version V1.7.0
* @date 31-May-2016
* @brief Header file of GPIO HAL module.
******************************************************************************
* @attention
@ -96,7 +96,7 @@ typedef struct
*/
typedef enum
{
GPIO_PIN_RESET = 0,
GPIO_PIN_RESET = 0U,
GPIO_PIN_SET
}GPIO_PinState;
/**
@ -120,29 +120,29 @@ typedef enum
/** @defgroup GPIO_pins_define Pin definition
* @{
*/
#define GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */
#define GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */
#define GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */
#define GPIO_PIN_3 ((uint16_t)0x0008) /* Pin 3 selected */
#define GPIO_PIN_4 ((uint16_t)0x0010) /* Pin 4 selected */
#define GPIO_PIN_5 ((uint16_t)0x0020) /* Pin 5 selected */
#define GPIO_PIN_6 ((uint16_t)0x0040) /* Pin 6 selected */
#define GPIO_PIN_7 ((uint16_t)0x0080) /* Pin 7 selected */
#define GPIO_PIN_8 ((uint16_t)0x0100) /* Pin 8 selected */
#define GPIO_PIN_9 ((uint16_t)0x0200) /* Pin 9 selected */
#define GPIO_PIN_10 ((uint16_t)0x0400) /* Pin 10 selected */
#define GPIO_PIN_11 ((uint16_t)0x0800) /* Pin 11 selected */
#define GPIO_PIN_12 ((uint16_t)0x1000) /* Pin 12 selected */
#define GPIO_PIN_13 ((uint16_t)0x2000) /* Pin 13 selected */
#define GPIO_PIN_14 ((uint16_t)0x4000) /* Pin 14 selected */
#define GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */
#define GPIO_PIN_All ((uint16_t)0xFFFF) /* All pins selected */
#define GPIO_PIN_0 ((uint16_t)0x0001U) /* Pin 0 selected */
#define GPIO_PIN_1 ((uint16_t)0x0002U) /* Pin 1 selected */
#define GPIO_PIN_2 ((uint16_t)0x0004U) /* Pin 2 selected */
#define GPIO_PIN_3 ((uint16_t)0x0008U) /* Pin 3 selected */
#define GPIO_PIN_4 ((uint16_t)0x0010U) /* Pin 4 selected */
#define GPIO_PIN_5 ((uint16_t)0x0020U) /* Pin 5 selected */
#define GPIO_PIN_6 ((uint16_t)0x0040U) /* Pin 6 selected */
#define GPIO_PIN_7 ((uint16_t)0x0080U) /* Pin 7 selected */
#define GPIO_PIN_8 ((uint16_t)0x0100U) /* Pin 8 selected */
#define GPIO_PIN_9 ((uint16_t)0x0200U) /* Pin 9 selected */
#define GPIO_PIN_10 ((uint16_t)0x0400U) /* Pin 10 selected */
#define GPIO_PIN_11 ((uint16_t)0x0800U) /* Pin 11 selected */
#define GPIO_PIN_12 ((uint16_t)0x1000U) /* Pin 12 selected */
#define GPIO_PIN_13 ((uint16_t)0x2000U) /* Pin 13 selected */
#define GPIO_PIN_14 ((uint16_t)0x4000U) /* Pin 14 selected */
#define GPIO_PIN_15 ((uint16_t)0x8000U) /* Pin 15 selected */
#define GPIO_PIN_All ((uint16_t)0xFFFFU) /* All pins selected */
/**
* @}
*/
#define GPIO_PIN_MASK ((uint32_t)0x0000FFFF) /* PIN mask for assert test */
#define IS_GPIO_PIN(__PIN__) (((__PIN__) & GPIO_PIN_MASK ) != (uint32_t)0x00)
#define GPIO_PIN_MASK ((uint32_t)0x0000FFFFU) /* PIN mask for assert test */
#define IS_GPIO_PIN(__PIN__) (((__PIN__) & GPIO_PIN_MASK ) != (uint32_t)0x00U)
/** @defgroup GPIO_mode_define Mode definition
* @brief GPIO Configuration Mode
@ -154,21 +154,21 @@ typedef enum
* - Z : IO Direction mode (Input, Output, Alternate or Analog)
* @{
*/
#define GPIO_MODE_INPUT ((uint32_t)0x00000000) /*!< Input Floating Mode */
#define GPIO_MODE_OUTPUT_PP ((uint32_t)0x00000001) /*!< Output Push Pull Mode */
#define GPIO_MODE_OUTPUT_OD ((uint32_t)0x00000011) /*!< Output Open Drain Mode */
#define GPIO_MODE_AF_PP ((uint32_t)0x00000002) /*!< Alternate Function Push Pull Mode */
#define GPIO_MODE_AF_OD ((uint32_t)0x00000012) /*!< Alternate Function Open Drain Mode */
#define GPIO_MODE_INPUT ((uint32_t)0x00000000U) /*!< Input Floating Mode */
#define GPIO_MODE_OUTPUT_PP ((uint32_t)0x00000001U) /*!< Output Push Pull Mode */
#define GPIO_MODE_OUTPUT_OD ((uint32_t)0x00000011U) /*!< Output Open Drain Mode */
#define GPIO_MODE_AF_PP ((uint32_t)0x00000002U) /*!< Alternate Function Push Pull Mode */
#define GPIO_MODE_AF_OD ((uint32_t)0x00000012U) /*!< Alternate Function Open Drain Mode */
#define GPIO_MODE_ANALOG ((uint32_t)0x00000003) /*!< Analog Mode */
#define GPIO_MODE_ANALOG ((uint32_t)0x00000003U) /*!< Analog Mode */
#define GPIO_MODE_IT_RISING ((uint32_t)0x10110000) /*!< External Interrupt Mode with Rising edge trigger detection */
#define GPIO_MODE_IT_FALLING ((uint32_t)0x10210000) /*!< External Interrupt Mode with Falling edge trigger detection */
#define GPIO_MODE_IT_RISING_FALLING ((uint32_t)0x10310000) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
#define GPIO_MODE_IT_RISING ((uint32_t)0x10110000U) /*!< External Interrupt Mode with Rising edge trigger detection */
#define GPIO_MODE_IT_FALLING ((uint32_t)0x10210000U) /*!< External Interrupt Mode with Falling edge trigger detection */
#define GPIO_MODE_IT_RISING_FALLING ((uint32_t)0x10310000U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
#define GPIO_MODE_EVT_RISING ((uint32_t)0x10120000) /*!< External Event Mode with Rising edge trigger detection */
#define GPIO_MODE_EVT_FALLING ((uint32_t)0x10220000) /*!< External Event Mode with Falling edge trigger detection */
#define GPIO_MODE_EVT_RISING_FALLING ((uint32_t)0x10320000) /*!< External Event Mode with Rising/Falling edge trigger detection */
#define GPIO_MODE_EVT_RISING ((uint32_t)0x10120000U) /*!< External Event Mode with Rising edge trigger detection */
#define GPIO_MODE_EVT_FALLING ((uint32_t)0x10220000U) /*!< External Event Mode with Falling edge trigger detection */
#define GPIO_MODE_EVT_RISING_FALLING ((uint32_t)0x10320000U) /*!< External Event Mode with Rising/Falling edge trigger detection */
/**
* @}
@ -192,10 +192,10 @@ typedef enum
* @brief GPIO Output Maximum frequency
* @{
*/
#define GPIO_SPEED_FREQ_LOW ((uint32_t)0x00000000) /*!< range up to 0.4 MHz, please refer to the product datasheet */
#define GPIO_SPEED_FREQ_MEDIUM ((uint32_t)0x00000001) /*!< range 0.4 MHz to 2 MHz, please refer to the product datasheet */
#define GPIO_SPEED_FREQ_HIGH ((uint32_t)0x00000002) /*!< range 2 MHz to 10 MHz, please refer to the product datasheet */
#define GPIO_SPEED_FREQ_VERY_HIGH ((uint32_t)0x00000003) /*!< range 10 MHz to 35 MHz, please refer to the product datasheet */
#define GPIO_SPEED_FREQ_LOW ((uint32_t)0x00000000U) /*!< range up to 0.4 MHz, please refer to the product datasheet */
#define GPIO_SPEED_FREQ_MEDIUM ((uint32_t)0x00000001U) /*!< range 0.4 MHz to 2 MHz, please refer to the product datasheet */
#define GPIO_SPEED_FREQ_HIGH ((uint32_t)0x00000002U) /*!< range 2 MHz to 10 MHz, please refer to the product datasheet */
#define GPIO_SPEED_FREQ_VERY_HIGH ((uint32_t)0x00000003U) /*!< range 10 MHz to 35 MHz, please refer to the product datasheet */
/**
* @}
@ -209,9 +209,9 @@ typedef enum
* @brief GPIO Pull-Up or Pull-Down Activation
* @{
*/
#define GPIO_NOPULL ((uint32_t)0x00000000) /*!< No Pull-up or Pull-down activation */
#define GPIO_PULLUP ((uint32_t)0x00000001) /*!< Pull-up activation */
#define GPIO_PULLDOWN ((uint32_t)0x00000002) /*!< Pull-down activation */
#define GPIO_NOPULL ((uint32_t)0x00000000U) /*!< No Pull-up or Pull-down activation */
#define GPIO_PULLUP ((uint32_t)0x00000001U) /*!< Pull-up activation */
#define GPIO_PULLDOWN ((uint32_t)0x00000002U) /*!< Pull-down activation */
/**
* @}

740
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_gpio_ex.h
View File

File diff suppressed because it is too large Load Diff

309
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_i2c.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx_hal_i2c.c
* @author MCD Application Team
* @version V1.5.0
* @date 8-January-2016
* @version V1.7.0
* @date 31-May-2016
* @brief I2C HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Inter Integrated Circuit (I2C) peripheral:
@ -197,16 +197,16 @@
/** @addtogroup I2C_Private
* @{
*/
#define TIMING_CLEAR_MASK ((uint32_t)0xF0FFFFFF) /*<! I2C TIMING clear register Mask */
#define I2C_TIMEOUT_ADDR ((uint32_t)10000) /* 10 s */
#define I2C_TIMEOUT_BUSY ((uint32_t)25) /* 25 ms */
#define I2C_TIMEOUT_DIR ((uint32_t)25) /* 25 ms */
#define I2C_TIMEOUT_RXNE ((uint32_t)25) /* 25 ms */
#define I2C_TIMEOUT_STOPF ((uint32_t)25) /* 25 ms */
#define I2C_TIMEOUT_TC ((uint32_t)25) /* 25 ms */
#define I2C_TIMEOUT_TCR ((uint32_t)25) /* 25 ms */
#define I2C_TIMEOUT_TXIS ((uint32_t)25) /* 25 ms */
#define I2C_TIMEOUT_FLAG ((uint32_t)25) /* 25 ms */
#define TIMING_CLEAR_MASK ((uint32_t)0xF0FFFFFFU) /*<! I2C TIMING clear register Mask */
#define I2C_TIMEOUT_ADDR ((uint32_t)10000U) /* 10 s */
#define I2C_TIMEOUT_BUSY ((uint32_t)25U) /* 25 ms */
#define I2C_TIMEOUT_DIR ((uint32_t)25U) /* 25 ms */
#define I2C_TIMEOUT_RXNE ((uint32_t)25U) /* 25 ms */
#define I2C_TIMEOUT_STOPF ((uint32_t)25U) /* 25 ms */
#define I2C_TIMEOUT_TC ((uint32_t)25U) /* 25 ms */
#define I2C_TIMEOUT_TCR ((uint32_t)25U) /* 25 ms */
#define I2C_TIMEOUT_TXIS ((uint32_t)25U) /* 25 ms */
#define I2C_TIMEOUT_FLAG ((uint32_t)25U) /* 25 ms */
/**
* @}
*/
@ -327,7 +327,7 @@ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
/*---------------------------- I2Cx OAR1 Configuration ---------------------*/
/* Configure I2Cx: Own Address1 and ack own address1 mode */
hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
if(hi2c->Init.OwnAddress1 != 0)
if(hi2c->Init.OwnAddress1 != 0U)
{
if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
{
@ -507,15 +507,11 @@ HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
*/
HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
uint32_t sizetmp = 0;
uint32_t sizetmp = 0U;
if(hi2c->State == HAL_I2C_STATE_READY)
{
if((pData == NULL ) || (Size == 0))
{
return HAL_ERROR;
}
if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
{
return HAL_BUSY;
@ -530,10 +526,10 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA
/* Send Slave Address */
/* Set NBYTES to write and reload if size > 255 and generate RESTART */
/* Size > 255, need to set RELOAD bit */
if(Size > 255)
if(Size > 255U)
{
I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
sizetmp = 255;
I2C_TransferConfig(hi2c,DevAddress,255U, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
sizetmp = 255U;
}
else
{
@ -560,7 +556,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA
sizetmp--;
Size--;
if((sizetmp == 0)&&(Size!=0))
if((sizetmp == 0U)&&(Size!=0U))
{
/* Wait until TCR flag is set */
if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout) != HAL_OK)
@ -568,10 +564,10 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA
return HAL_TIMEOUT;
}
if(Size > 255)
if(Size > 255U)
{
I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
sizetmp = 255;
I2C_TransferConfig(hi2c,DevAddress,255U, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
sizetmp = 255U;
}
else
{
@ -580,7 +576,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA
}
}
}while(Size > 0);
}while(Size > 0U);
/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
/* Wait until STOPF flag is set */
@ -627,15 +623,10 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA
*/
HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
uint32_t sizetmp = 0;
uint32_t sizetmp = 0U;
if(hi2c->State == HAL_I2C_STATE_READY)
{
if((pData == NULL ) || (Size == 0))
{
return HAL_ERROR;
}
{
if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
{
return HAL_BUSY;
@ -650,10 +641,10 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd
/* Send Slave Address */
/* Set NBYTES to write and reload if size > 255 and generate RESTART */
/* Size > 255, need to set RELOAD bit */
if(Size > 255)
if(Size > 255U)
{
I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
sizetmp = 255;
I2C_TransferConfig(hi2c,DevAddress,255U, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
sizetmp = 255U;
}
else
{
@ -681,7 +672,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd
sizetmp--;
Size--;
if((sizetmp == 0)&&(Size!=0))
if((sizetmp == 0U)&&(Size!=0U))
{
/* Wait until TCR flag is set */
if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout) != HAL_OK)
@ -689,10 +680,10 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd
return HAL_TIMEOUT;
}
if(Size > 255)
if(Size > 255U)
{
I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
sizetmp = 255;
I2C_TransferConfig(hi2c,DevAddress,255U, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
sizetmp = 255U;
}
else
{
@ -701,7 +692,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd
}
}
}while(Size > 0);
}while(Size > 0U);
/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
/* Wait until STOPF flag is set */
@ -749,7 +740,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData
{
if(hi2c->State == HAL_I2C_STATE_READY)
{
if((pData == NULL ) || (Size == 0))
if((pData == NULL ) || (Size == 0U))
{
return HAL_ERROR;
}
@ -818,7 +809,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData
/* Read data from TXDR */
hi2c->Instance->TXDR = (*pData++);
Size--;
}while(Size > 0);
}while(Size > 0U);
/* Wait until STOP flag is set */
if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)
@ -878,7 +869,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData,
{
if(hi2c->State == HAL_I2C_STATE_READY)
{
if((pData == NULL ) || (Size == 0))
if((pData == NULL ) || (Size == 0U))
{
return HAL_ERROR;
}
@ -911,7 +902,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData,
return HAL_TIMEOUT;
}
while(Size > 0)
while(Size > 0U)
{
/* Wait until RXNE flag is set */
if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout) != HAL_OK)
@ -998,7 +989,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t D
{
if(hi2c->State == HAL_I2C_STATE_READY)
{
if((pData == NULL) || (Size == 0))
if((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@ -1016,9 +1007,9 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t D
hi2c->pBuffPtr = pData;
hi2c->XferCount = Size;
if(Size > 255)
if(Size > 255U)
{
hi2c->XferSize = 255;
hi2c->XferSize = 255U;
}
else
{
@ -1027,7 +1018,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t D
/* Send Slave Address */
/* Set NBYTES to write and reload if size > 255 and generate RESTART */
if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
if( (hi2c->XferSize == 255U) && (hi2c->XferSize < hi2c->XferCount) )
{
I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
}
@ -1070,7 +1061,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t De
{
if(hi2c->State == HAL_I2C_STATE_READY)
{
if((pData == NULL) || (Size == 0))
if((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@ -1088,9 +1079,9 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t De
hi2c->pBuffPtr = pData;
hi2c->XferCount = Size;
if(Size > 255)
if(Size > 255U)
{
hi2c->XferSize = 255;
hi2c->XferSize = 255U;
}
else
{
@ -1099,7 +1090,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t De
/* Send Slave Address */
/* Set NBYTES to write and reload if size > 255 and generate RESTART */
if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
if( (hi2c->XferSize == 255U) && (hi2c->XferSize < hi2c->XferCount) )
{
I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
}
@ -1140,7 +1131,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pD
{
if(hi2c->State == HAL_I2C_STATE_READY)
{
if((pData == NULL) || (Size == 0))
if((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@ -1190,7 +1181,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pDa
{
if(hi2c->State == HAL_I2C_STATE_READY)
{
if((pData == NULL) || (Size == 0))
if((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@ -1241,7 +1232,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t
{
if(hi2c->State == HAL_I2C_STATE_READY)
{
if((pData == NULL) || (Size == 0))
if((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@ -1259,9 +1250,9 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t
hi2c->pBuffPtr = pData;
hi2c->XferCount = Size;
if(Size > 255)
if(Size > 255U)
{
hi2c->XferSize = 255;
hi2c->XferSize = 255U;
}
else
{
@ -1279,7 +1270,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t
/* Send Slave Address */
/* Set NBYTES to write and reload if size > 255 and generate RESTART */
if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
if( (hi2c->XferSize == 255U) && (hi2c->XferSize < hi2c->XferCount) )
{
I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
}
@ -1335,7 +1326,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D
{
if(hi2c->State == HAL_I2C_STATE_READY)
{
if((pData == NULL) || (Size == 0))
if((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@ -1353,9 +1344,9 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D
hi2c->pBuffPtr = pData;
hi2c->XferCount = Size;
if(Size > 255)
if(Size > 255U)
{
hi2c->XferSize = 255;
hi2c->XferSize = 255U;
}
else
{
@ -1373,7 +1364,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D
/* Send Slave Address */
/* Set NBYTES to write and reload if size > 255 and generate RESTART */
if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
if( (hi2c->XferSize == 255U) && (hi2c->XferSize < hi2c->XferCount) )
{
I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
}
@ -1424,7 +1415,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *p
{
if(hi2c->State == HAL_I2C_STATE_READY)
{
if((pData == NULL) || (Size == 0))
if((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@ -1510,7 +1501,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pD
{
if(hi2c->State == HAL_I2C_STATE_READY)
{
if((pData == NULL) || (Size == 0))
if((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@ -1583,14 +1574,14 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pD
*/
HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
uint32_t Sizetmp = 0;
uint32_t Sizetmp = 0U;
/* Check the parameters */
assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
if(hi2c->State == HAL_I2C_STATE_READY)
{
if((pData == NULL) || (Size == 0))
if((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@ -1625,10 +1616,10 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress
/* Set NBYTES to write and reload if size > 255 */
/* Size > 255, need to set RELOAD bit */
if(Size > 255)
if(Size > 255U)
{
I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
Sizetmp = 255;
I2C_TransferConfig(hi2c,DevAddress,255U, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
Sizetmp = 255U;
}
else
{
@ -1656,7 +1647,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress
Sizetmp--;
Size--;
if((Sizetmp == 0)&&(Size!=0))
if((Sizetmp == 0U)&&(Size!=0U))
{
/* Wait until TCR flag is set */
if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout) != HAL_OK)
@ -1665,10 +1656,10 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress
}
if(Size > 255)
if(Size > 255U)
{
I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
Sizetmp = 255;
I2C_TransferConfig(hi2c,DevAddress,255U, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
Sizetmp = 255U;
}
else
{
@ -1677,7 +1668,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress
}
}
}while(Size > 0);
}while(Size > 0U);
/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
/* Wait until STOPF flag is reset */
@ -1726,14 +1717,14 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress
*/
HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
uint32_t Sizetmp = 0;
uint32_t Sizetmp = 0U;
/* Check the parameters */
assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
if(hi2c->State == HAL_I2C_STATE_READY)
{
if((pData == NULL) || (Size == 0))
if((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@ -1769,10 +1760,10 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
/* Send Slave Address */
/* Set NBYTES to write and reload if size > 255 and generate RESTART */
/* Size > 255, need to set RELOAD bit */
if(Size > 255)
if(Size > 255U)
{
I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
Sizetmp = 255;
I2C_TransferConfig(hi2c,DevAddress,255U, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
Sizetmp = 255U;
}
else
{
@ -1795,7 +1786,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
Sizetmp--;
Size--;
if((Sizetmp == 0)&&(Size!=0))
if((Sizetmp == 0U)&&(Size!=0U))
{
/* Wait until TCR flag is set */
if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout) != HAL_OK)
@ -1803,10 +1794,10 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
return HAL_TIMEOUT;
}
if(Size > 255)
if(Size > 255U)
{
I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
Sizetmp = 255;
I2C_TransferConfig(hi2c,DevAddress,255U, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
Sizetmp = 255U;
}
else
{
@ -1815,7 +1806,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
}
}
}while(Size > 0);
}while(Size > 0U);
/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
/* Wait until STOPF flag is reset */
@ -1868,7 +1859,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr
if(hi2c->State == HAL_I2C_STATE_READY)
{
if((pData == NULL) || (Size == 0))
if((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@ -1886,9 +1877,9 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr
hi2c->pBuffPtr = pData;
hi2c->XferCount = Size;
if(Size > 255)
if(Size > 255U)
{
hi2c->XferSize = 255;
hi2c->XferSize = 255U;
}
else
{
@ -1914,7 +1905,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr
/* Set NBYTES to write and reload if size > 255 */
/* Size > 255, need to set RELOAD bit */
if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
if( (hi2c->XferSize == 255U) && (hi2c->XferSize < hi2c->XferCount) )
{
I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
}
@ -1961,7 +1952,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre
if(hi2c->State == HAL_I2C_STATE_READY)
{
if((pData == NULL) || (Size == 0))
if((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@ -1978,9 +1969,9 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre
hi2c->pBuffPtr = pData;
hi2c->XferCount = Size;
if(Size > 255)
if(Size > 255U)
{
hi2c->XferSize = 255;
hi2c->XferSize = 255U;
}
else
{
@ -2006,7 +1997,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre
/* Set NBYTES to write and reload if size > 255 and generate RESTART */
/* Size > 255, need to set RELOAD bit */
if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
if( (hi2c->XferSize == 255U) && (hi2c->XferSize < hi2c->XferCount) )
{
I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
}
@ -2053,7 +2044,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd
if(hi2c->State == HAL_I2C_STATE_READY)
{
if((pData == NULL) || (Size == 0))
if((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@ -2071,9 +2062,9 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd
hi2c->pBuffPtr = pData;
hi2c->XferCount = Size;
if(Size > 255)
if(Size > 255U)
{
hi2c->XferSize = 255;
hi2c->XferSize = 255U;
}
else
{
@ -2108,7 +2099,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd
/* Send Slave Address */
/* Set NBYTES to write and reload if size > 255 */
if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
if( (hi2c->XferSize == 255U) && (hi2c->XferSize < hi2c->XferCount) )
{
I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
}
@ -2162,7 +2153,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr
if(hi2c->State == HAL_I2C_STATE_READY)
{
if((pData == NULL) || (Size == 0))
if((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@ -2179,9 +2170,9 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr
hi2c->pBuffPtr = pData;
hi2c->XferCount = Size;
if(Size > 255)
if(Size > 255U)
{
hi2c->XferSize = 255;
hi2c->XferSize = 255U;
}
else
{
@ -2215,7 +2206,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr
}
/* Set NBYTES to write and reload if size > 255 and generate RESTART */
if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
if( (hi2c->XferSize == 255U) && (hi2c->XferSize < hi2c->XferCount) )
{
I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
}
@ -2256,9 +2247,9 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr
*/
HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
{
uint32_t tickstart = 0;
uint32_t tickstart = 0U;
__IO uint32_t I2C_Trials = 0;
__IO uint32_t I2C_Trials = 0U;
if(hi2c->State == HAL_I2C_STATE_READY)
{
@ -2285,7 +2276,7 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd
{
if(Timeout != HAL_MAX_DELAY)
{
if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
{
/* Device is ready */
hi2c->State = HAL_I2C_STATE_READY;
@ -2645,14 +2636,14 @@ static HAL_StatusTypeDef I2C_MasterTransmit_ISR(I2C_HandleTypeDef *hi2c)
}
else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TCR) == SET)
{
if((hi2c->XferSize == 0)&&(hi2c->XferCount!=0))
if((hi2c->XferSize == 0U)&&(hi2c->XferCount!=0U))
{
DevAddress = (hi2c->Instance->CR2 & I2C_CR2_SADD);
if(hi2c->XferCount > 255)
if(hi2c->XferCount > 255U)
{
I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
hi2c->XferSize = 255;
I2C_TransferConfig(hi2c,DevAddress,255U, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
hi2c->XferSize = 255U;
}
else
{
@ -2672,7 +2663,7 @@ static HAL_StatusTypeDef I2C_MasterTransmit_ISR(I2C_HandleTypeDef *hi2c)
}
else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TC) == SET)
{
if(hi2c->XferCount == 0)
if(hi2c->XferCount == 0U)
{
/* Generate Stop */
hi2c->Instance->CR2 |= I2C_CR2_STOP;
@ -2783,14 +2774,14 @@ static HAL_StatusTypeDef I2C_MasterReceive_ISR(I2C_HandleTypeDef *hi2c)
}
else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TCR) == SET)
{
if((hi2c->XferSize == 0)&&(hi2c->XferCount!=0))
if((hi2c->XferSize == 0U)&&(hi2c->XferCount!=0U))
{
DevAddress = (hi2c->Instance->CR2 & I2C_CR2_SADD);
if(hi2c->XferCount > 255)
if(hi2c->XferCount > 255U)
{
I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
hi2c->XferSize = 255;
I2C_TransferConfig(hi2c,DevAddress,255U, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
hi2c->XferSize = 255U;
}
else
{
@ -2810,7 +2801,7 @@ static HAL_StatusTypeDef I2C_MasterReceive_ISR(I2C_HandleTypeDef *hi2c)
}
else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TC) == SET)
{
if(hi2c->XferCount == 0)
if(hi2c->XferCount == 0U)
{
/* Generate Stop */
hi2c->Instance->CR2 |= I2C_CR2_STOP;
@ -2911,7 +2902,7 @@ static HAL_StatusTypeDef I2C_SlaveTransmit_ISR(I2C_HandleTypeDef *hi2c)
/* if yes, normal usecase, a NACK is sent by the MASTER when Transfer is finished */
/* Mean XferCount == 0*/
/* So clear Flag NACKF only */
if(hi2c->XferCount == 0)
if(hi2c->XferCount == 0U)
{
/* Clear NACK Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
@ -2966,7 +2957,7 @@ static HAL_StatusTypeDef I2C_SlaveTransmit_ISR(I2C_HandleTypeDef *hi2c)
{
/* Write data to TXDR only if XferCount not reach "0" */
/* A TXIS flag can be set, during STOP treatment */
if(hi2c->XferCount > 0)
if(hi2c->XferCount > 0U)
{
/* Write data to TXDR */
hi2c->Instance->TXDR = (*hi2c->pBuffPtr++);
@ -3181,7 +3172,7 @@ static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma)
/* Check if last DMA request was done with RELOAD */
/* Set NBYTES to write and reload if size > 255 */
if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
if( (hi2c->XferSize == 255U) && (hi2c->XferSize < hi2c->XferCount) )
{
/* Wait until TCR flag is set */
if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, I2C_TIMEOUT_TCR) != HAL_OK)
@ -3215,7 +3206,7 @@ static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma)
/* Clear Configuration Register 2 */
__I2C_RESET_CR2(hi2c);
hi2c->XferCount = 0;
hi2c->XferCount = 0U;
hi2c->State = HAL_I2C_STATE_READY;
HAL_I2C_ErrorCallback(hi2c);
@ -3224,9 +3215,9 @@ static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma)
{
hi2c->pBuffPtr += hi2c->XferSize;
hi2c->XferCount -= hi2c->XferSize;
if(hi2c->XferCount > 255)
if(hi2c->XferCount > 255U)
{
hi2c->XferSize = 255;
hi2c->XferSize = 255U;
}
else
{
@ -3240,7 +3231,7 @@ static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma)
/* Send Slave Address */
/* Set NBYTES to write and reload if size > 255 */
if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
if( (hi2c->XferSize == 255U) && (hi2c->XferSize < hi2c->XferCount) )
{
I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
}
@ -3272,7 +3263,7 @@ static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma)
/* Clear Configuration Register 2 */
__I2C_RESET_CR2(hi2c);
hi2c->XferCount = 0;
hi2c->XferCount = 0U;
hi2c->State = HAL_I2C_STATE_READY;
HAL_I2C_ErrorCallback(hi2c);
@ -3309,7 +3300,7 @@ static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma)
/* Disable DMA Request */
hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
hi2c->XferCount = 0;
hi2c->XferCount = 0U;
hi2c->State = HAL_I2C_STATE_READY;
@ -3361,7 +3352,7 @@ static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma)
/* Disable DMA Request */
hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
hi2c->XferCount = 0;
hi2c->XferCount = 0U;
hi2c->State = HAL_I2C_STATE_READY;
@ -3388,7 +3379,7 @@ static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma)
/* Check if last DMA request was done with RELOAD */
/* Set NBYTES to write and reload if size > 255 */
if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
if( (hi2c->XferSize == 255U) && (hi2c->XferSize < hi2c->XferCount) )
{
/* Wait until TCR flag is set */
if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, I2C_TIMEOUT_TCR) != HAL_OK)
@ -3422,7 +3413,7 @@ static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma)
/* Clear Configuration Register 2 */
__I2C_RESET_CR2(hi2c);
hi2c->XferCount = 0;
hi2c->XferCount = 0U;
hi2c->State = HAL_I2C_STATE_READY;
HAL_I2C_ErrorCallback(hi2c);
@ -3431,9 +3422,9 @@ static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma)
{
hi2c->pBuffPtr += hi2c->XferSize;
hi2c->XferCount -= hi2c->XferSize;
if(hi2c->XferCount > 255)
if(hi2c->XferCount > 255U)
{
hi2c->XferSize = 255;
hi2c->XferSize = 255U;
}
else
{
@ -3447,7 +3438,7 @@ static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma)
/* Send Slave Address */
/* Set NBYTES to write and reload if size > 255 */
if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
if( (hi2c->XferSize == 255U) && (hi2c->XferSize < hi2c->XferCount) )
{
I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
}
@ -3485,7 +3476,7 @@ static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma)
/* Clear Configuration Register 2 */
__I2C_RESET_CR2(hi2c);
hi2c->XferCount = 0;
hi2c->XferCount = 0U;
hi2c->State = HAL_I2C_STATE_READY;
@ -3523,7 +3514,7 @@ static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma)
/* Disable DMA Request */
hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
hi2c->XferCount = 0;
hi2c->XferCount = 0U;
hi2c->State = HAL_I2C_STATE_READY;
@ -3576,7 +3567,7 @@ static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma)
/* Disable Address Acknowledge */
hi2c->Instance->CR2 |= I2C_CR2_NACK;
hi2c->XferCount = 0;
hi2c->XferCount = 0U;
hi2c->State = HAL_I2C_STATE_READY;
@ -3603,7 +3594,7 @@ static void I2C_DMAMemTransmitCplt(DMA_HandleTypeDef *hdma)
/* Check if last DMA request was done with RELOAD */
/* Set NBYTES to write and reload if size > 255 */
if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
if( (hi2c->XferSize == 255U) && (hi2c->XferSize < hi2c->XferCount) )
{
/* Wait until TCR flag is set */
if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, I2C_TIMEOUT_TCR) != HAL_OK)
@ -3637,7 +3628,7 @@ static void I2C_DMAMemTransmitCplt(DMA_HandleTypeDef *hdma)
/* Clear Configuration Register 2 */
__I2C_RESET_CR2(hi2c);
hi2c->XferCount = 0;
hi2c->XferCount = 0U;
hi2c->State = HAL_I2C_STATE_READY;
HAL_I2C_ErrorCallback(hi2c);
@ -3646,9 +3637,9 @@ static void I2C_DMAMemTransmitCplt(DMA_HandleTypeDef *hdma)
{
hi2c->pBuffPtr += hi2c->XferSize;
hi2c->XferCount -= hi2c->XferSize;
if(hi2c->XferCount > 255)
if(hi2c->XferCount > 255U)
{
hi2c->XferSize = 255;
hi2c->XferSize = 255U;
}
else
{
@ -3662,7 +3653,7 @@ static void I2C_DMAMemTransmitCplt(DMA_HandleTypeDef *hdma)
/* Send Slave Address */
/* Set NBYTES to write and reload if size > 255 */
if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
if( (hi2c->XferSize == 255U) && (hi2c->XferSize < hi2c->XferCount) )
{
I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
}
@ -3694,7 +3685,7 @@ static void I2C_DMAMemTransmitCplt(DMA_HandleTypeDef *hdma)
/* Clear Configuration Register 2 */
__I2C_RESET_CR2(hi2c);
hi2c->XferCount = 0;
hi2c->XferCount = 0U;
hi2c->State = HAL_I2C_STATE_READY;
HAL_I2C_ErrorCallback(hi2c);
@ -3731,7 +3722,7 @@ static void I2C_DMAMemTransmitCplt(DMA_HandleTypeDef *hdma)
/* Disable DMA Request */
hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
hi2c->XferCount = 0;
hi2c->XferCount = 0U;
hi2c->State = HAL_I2C_STATE_READY;
@ -3759,7 +3750,7 @@ static void I2C_DMAMemReceiveCplt(DMA_HandleTypeDef *hdma)
/* Check if last DMA request was done with RELOAD */
/* Set NBYTES to write and reload if size > 255 */
if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
if( (hi2c->XferSize == 255U) && (hi2c->XferSize < hi2c->XferCount) )
{
/* Wait until TCR flag is set */
if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, I2C_TIMEOUT_TCR) != HAL_OK)
@ -3793,7 +3784,7 @@ static void I2C_DMAMemReceiveCplt(DMA_HandleTypeDef *hdma)
/* Clear Configuration Register 2 */
__I2C_RESET_CR2(hi2c);
hi2c->XferCount = 0;
hi2c->XferCount = 0U;
hi2c->State = HAL_I2C_STATE_READY;
HAL_I2C_ErrorCallback(hi2c);
@ -3802,9 +3793,9 @@ static void I2C_DMAMemReceiveCplt(DMA_HandleTypeDef *hdma)
{
hi2c->pBuffPtr += hi2c->XferSize;
hi2c->XferCount -= hi2c->XferSize;
if(hi2c->XferCount > 255)
if(hi2c->XferCount > 255U)
{
hi2c->XferSize = 255;
hi2c->XferSize = 255U;
}
else
{
@ -3818,7 +3809,7 @@ static void I2C_DMAMemReceiveCplt(DMA_HandleTypeDef *hdma)
/* Send Slave Address */
/* Set NBYTES to write and reload if size > 255 */
if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
if( (hi2c->XferSize == 255U) && (hi2c->XferSize < hi2c->XferCount) )
{
I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
}
@ -3856,7 +3847,7 @@ static void I2C_DMAMemReceiveCplt(DMA_HandleTypeDef *hdma)
/* Clear Configuration Register 2 */
__I2C_RESET_CR2(hi2c);
hi2c->XferCount = 0;
hi2c->XferCount = 0U;
hi2c->State = HAL_I2C_STATE_READY;
HAL_I2C_ErrorCallback(hi2c);
@ -3893,7 +3884,7 @@ static void I2C_DMAMemReceiveCplt(DMA_HandleTypeDef *hdma)
/* Disable DMA Request */
hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
hi2c->XferCount = 0;
hi2c->XferCount = 0U;
hi2c->State = HAL_I2C_STATE_READY;
@ -3921,7 +3912,7 @@ static void I2C_DMAError(DMA_HandleTypeDef *hdma)
/* Disable Acknowledge */
hi2c->Instance->CR2 |= I2C_CR2_NACK;
hi2c->XferCount = 0;
hi2c->XferCount = 0U;
hi2c->State = HAL_I2C_STATE_READY;
@ -3951,7 +3942,7 @@ static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uin
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
{
if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
{
hi2c->State= HAL_I2C_STATE_READY;
/* Process Unlocked */
@ -3968,7 +3959,7 @@ static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uin
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
{
if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
{
hi2c->State= HAL_I2C_STATE_READY;
/* Process Unlocked */
@ -4003,7 +3994,7 @@ static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c,
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
{
if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
{
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
hi2c->State= HAL_I2C_STATE_READY;
@ -4027,7 +4018,7 @@ static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c,
*/
static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout)
{
uint32_t tickstart = 0x00;
uint32_t tickstart = 0x00U;
tickstart = HAL_GetTick();
while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
@ -4039,7 +4030,7 @@ static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c,
}
/* Check for the Timeout */
if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
{
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
hi2c->State= HAL_I2C_STATE_READY;
@ -4062,7 +4053,7 @@ static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c,
*/
static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout)
{
uint32_t tickstart = 0x00;
uint32_t tickstart = 0x00U;
tickstart = HAL_GetTick();
while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)
@ -4091,7 +4082,7 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c,
}
/* Check for the Timeout */
if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
{
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
hi2c->State= HAL_I2C_STATE_READY;
@ -4114,7 +4105,7 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c,
*/
static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout)
{
uint32_t tickstart = 0x00;
uint32_t tickstart = 0x00U;
tickstart = HAL_GetTick();
if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
@ -4139,7 +4130,7 @@ static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
{
if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
{
hi2c->State= HAL_I2C_STATE_READY;
/* Process Unlocked */
@ -4195,7 +4186,7 @@ static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32
*/
static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
{
uint32_t tmpreg = 0;
uint32_t tmpreg = 0U;
/* Check the parameters */
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
@ -4209,7 +4200,7 @@ static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, ui
tmpreg &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP));
/* update tmpreg */
tmpreg |= (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << 16 ) & I2C_CR2_NBYTES) | \
tmpreg |= (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << 16U ) & I2C_CR2_NBYTES) | \
(uint32_t)Mode | (uint32_t)Request);
/* update CR2 register */

84
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_i2c.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx_hal_i2c.h
* @author MCD Application Team
* @version V1.5.0
* @date 8-January-2016
* @version V1.7.0
* @date 31-May-2016
* @brief Header file of I2C HAL module.
******************************************************************************
* @attention
@ -103,17 +103,17 @@ typedef struct
typedef enum
{
HAL_I2C_STATE_RESET = 0x00, /*!< I2C not yet initialized or disabled */
HAL_I2C_STATE_READY = 0x01, /*!< I2C initialized and ready for use */
HAL_I2C_STATE_BUSY = 0x02, /*!< I2C internal process is ongoing */
HAL_I2C_STATE_MASTER_BUSY_TX = 0x12, /*!< Master Data Transmission process is ongoing */
HAL_I2C_STATE_MASTER_BUSY_RX = 0x22, /*!< Master Data Reception process is ongoing */
HAL_I2C_STATE_SLAVE_BUSY_TX = 0x32, /*!< Slave Data Transmission process is ongoing */
HAL_I2C_STATE_SLAVE_BUSY_RX = 0x42, /*!< Slave Data Reception process is ongoing */
HAL_I2C_STATE_MEM_BUSY_TX = 0x52, /*!< Memory Data Transmission process is ongoing */
HAL_I2C_STATE_MEM_BUSY_RX = 0x62, /*!< Memory Data Reception process is ongoing */
HAL_I2C_STATE_TIMEOUT = 0x03, /*!< Timeout state */
HAL_I2C_STATE_ERROR = 0x04 /*!< Reception process is ongoing */
HAL_I2C_STATE_RESET = 0x00U, /*!< I2C not yet initialized or disabled */
HAL_I2C_STATE_READY = 0x01U, /*!< I2C initialized and ready for use */
HAL_I2C_STATE_BUSY = 0x02U, /*!< I2C internal process is ongoing */
HAL_I2C_STATE_MASTER_BUSY_TX = 0x12U, /*!< Master Data Transmission process is ongoing */
HAL_I2C_STATE_MASTER_BUSY_RX = 0x22U, /*!< Master Data Reception process is ongoing */
HAL_I2C_STATE_SLAVE_BUSY_TX = 0x32U, /*!< Slave Data Transmission process is ongoing */
HAL_I2C_STATE_SLAVE_BUSY_RX = 0x42U, /*!< Slave Data Reception process is ongoing */
HAL_I2C_STATE_MEM_BUSY_TX = 0x52U, /*!< Memory Data Transmission process is ongoing */
HAL_I2C_STATE_MEM_BUSY_RX = 0x62U, /*!< Memory Data Reception process is ongoing */
HAL_I2C_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
HAL_I2C_STATE_ERROR = 0x04U /*!< Reception process is ongoing */
}HAL_I2C_StateTypeDef;
/**
@ -124,14 +124,14 @@ typedef enum
* @brief I2C Error Code
* @{
*/
#define HAL_I2C_ERROR_NONE 0x00 /*!< No error */
#define HAL_I2C_ERROR_BERR 0x01 /*!< BERR error */
#define HAL_I2C_ERROR_ARLO 0x02 /*!< ARLO error */
#define HAL_I2C_ERROR_AF 0x04 /*!< ACKF error */
#define HAL_I2C_ERROR_OVR 0x08 /*!< OVR error */
#define HAL_I2C_ERROR_DMA 0x10 /*!< DMA transfer error */
#define HAL_I2C_ERROR_TIMEOUT 0x20 /*!< Timeout error */
#define HAL_I2C_ERROR_SIZE 0x40 /*!< Size Management error */
#define HAL_I2C_ERROR_NONE 0x00U /*!< No error */
#define HAL_I2C_ERROR_BERR 0x01U /*!< BERR error */
#define HAL_I2C_ERROR_ARLO 0x02U /*!< ARLO error */
#define HAL_I2C_ERROR_AF 0x04U /*!< ACKF error */
#define HAL_I2C_ERROR_OVR 0x08U /*!< OVR error */
#define HAL_I2C_ERROR_DMA 0x10U /*!< DMA transfer error */
#define HAL_I2C_ERROR_TIMEOUT 0x20U /*!< Timeout error */
#define HAL_I2C_ERROR_SIZE 0x40U /*!< Size Management error */
/**
* @}
*/
@ -179,8 +179,8 @@ typedef struct
/** @defgroup I2C_addressing_mode I2C addressing mode
* @{
*/
#define I2C_ADDRESSINGMODE_7BIT ((uint32_t)0x00000001)
#define I2C_ADDRESSINGMODE_10BIT ((uint32_t)0x00000002)
#define I2C_ADDRESSINGMODE_7BIT ((uint32_t)0x00000001U)
#define I2C_ADDRESSINGMODE_10BIT ((uint32_t)0x00000002U)
/**
* @}
*/
@ -188,7 +188,7 @@ typedef struct
/** @defgroup I2C_dual_addressing_mode I2C dual addressing mode
* @{
*/
#define I2C_DUALADDRESS_DISABLE ((uint32_t)0x00000000)
#define I2C_DUALADDRESS_DISABLE ((uint32_t)0x00000000U)
#define I2C_DUALADDRESS_ENABLE I2C_OAR2_OA2EN
/**
* @}
@ -197,14 +197,14 @@ typedef struct
/** @defgroup I2C_own_address2_masks I2C own address2 masks
* @{
*/
#define I2C_OA2_NOMASK ((uint8_t)0x00)
#define I2C_OA2_MASK01 ((uint8_t)0x01)
#define I2C_OA2_MASK02 ((uint8_t)0x02)
#define I2C_OA2_MASK03 ((uint8_t)0x03)
#define I2C_OA2_MASK04 ((uint8_t)0x04)
#define I2C_OA2_MASK05 ((uint8_t)0x05)
#define I2C_OA2_MASK06 ((uint8_t)0x06)
#define I2C_OA2_MASK07 ((uint8_t)0x07)
#define I2C_OA2_NOMASK ((uint8_t)0x00U)
#define I2C_OA2_MASK01 ((uint8_t)0x01U)
#define I2C_OA2_MASK02 ((uint8_t)0x02U)
#define I2C_OA2_MASK03 ((uint8_t)0x03U)
#define I2C_OA2_MASK04 ((uint8_t)0x04U)
#define I2C_OA2_MASK05 ((uint8_t)0x05U)
#define I2C_OA2_MASK06 ((uint8_t)0x06U)
#define I2C_OA2_MASK07 ((uint8_t)0x07U)
/**
* @}
*/
@ -212,7 +212,7 @@ typedef struct
/** @defgroup I2C_general_call_addressing_mode I2C general call addressing mode
* @{
*/
#define I2C_GENERALCALL_DISABLE ((uint32_t)0x00000000)
#define I2C_GENERALCALL_DISABLE ((uint32_t)0x00000000U)
#define I2C_GENERALCALL_ENABLE I2C_CR1_GCEN
/**
* @}
@ -221,7 +221,7 @@ typedef struct
/** @defgroup I2C_nostretch_mode I2C nostretch mode
* @{
*/
#define I2C_NOSTRETCH_DISABLE ((uint32_t)0x00000000)
#define I2C_NOSTRETCH_DISABLE ((uint32_t)0x00000000U)
#define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH
/**
* @}
@ -230,8 +230,8 @@ typedef struct
/** @defgroup I2C_Memory_Address_Size I2C Memory Address Size
* @{
*/
#define I2C_MEMADD_SIZE_8BIT ((uint32_t)0x00000001)
#define I2C_MEMADD_SIZE_16BIT ((uint32_t)0x00000002)
#define I2C_MEMADD_SIZE_8BIT ((uint32_t)0x00000001U)
#define I2C_MEMADD_SIZE_16BIT ((uint32_t)0x00000002U)
/**
* @}
*/
@ -241,7 +241,7 @@ typedef struct
*/
#define I2C_RELOAD_MODE I2C_CR2_RELOAD
#define I2C_AUTOEND_MODE I2C_CR2_AUTOEND
#define I2C_SOFTEND_MODE ((uint32_t)0x00000000)
#define I2C_SOFTEND_MODE ((uint32_t)0x00000000U)
/**
* @}
*/
@ -249,7 +249,7 @@ typedef struct
/** @defgroup I2C_StartStopMode_definition I2C StartStopMode definition
* @{
*/
#define I2C_NO_STARTSTOP ((uint32_t)0x00000000)
#define I2C_NO_STARTSTOP ((uint32_t)0x00000000U)
#define I2C_GENERATE_STOP I2C_CR2_STOP
#define I2C_GENERATE_START_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN)
#define I2C_GENERATE_START_WRITE I2C_CR2_START
@ -469,11 +469,11 @@ typedef struct
#define __I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= (uint32_t)0x000003FF)
#define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FF)
#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= (uint32_t)0x000003FFU)
#define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU)
#define __I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00))) >> 8)))
#define __I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF))))
#define __I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00U))) >> 8)))
#define __I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
#define __I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \
(uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))

12
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_i2c_ex.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx_hal_i2c_ex.c
* @author MCD Application Team
* @version V1.5.0
* @date 8-January-2016
* @version V1.7.0
* @date 31-May-2016
* @brief I2C Extended HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of I2C Extended peripheral:
@ -153,7 +153,7 @@ HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t
*/
HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
{
uint32_t tmpreg = 0;
uint32_t tmpreg = 0U;
/* Check the parameters */
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
@ -180,7 +180,7 @@ HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_
tmpreg &= ~(I2C_CR1_DNF);
/* Set I2Cx DNF coefficient */
tmpreg |= DigitalFilter << 8;
tmpreg |= DigitalFilter << 8U;
/* Store the new register value */
hi2c->Instance->CR1 = tmpreg;
@ -204,7 +204,7 @@ HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_
HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp (I2C_HandleTypeDef *hi2c)
{
/* Check the parameters */
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance));
if((hi2c->State == HAL_I2C_STATE_BUSY) || (hi2c->State == HAL_I2C_STATE_MASTER_BUSY_TX) || (hi2c->State == HAL_I2C_STATE_MASTER_BUSY_RX)
|| (hi2c->State == HAL_I2C_STATE_SLAVE_BUSY_TX) || (hi2c->State == HAL_I2C_STATE_SLAVE_BUSY_RX))
@ -243,7 +243,7 @@ HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp (I2C_HandleTypeDef *hi2c)
HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp (I2C_HandleTypeDef *hi2c)
{
/* Check the parameters */
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance));
if((hi2c->State == HAL_I2C_STATE_BUSY) || (hi2c->State == HAL_I2C_STATE_MASTER_BUSY_TX) || (hi2c->State == HAL_I2C_STATE_MASTER_BUSY_RX)
|| (hi2c->State == HAL_I2C_STATE_SLAVE_BUSY_TX) || (hi2c->State == HAL_I2C_STATE_SLAVE_BUSY_RX))

8
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_i2c_ex.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx_hal_i2c_ex.h
* @author MCD Application Team
* @version V1.5.0
* @date 8-January-2016
* @version V1.7.0
* @date 31-May-2016
* @brief Header file of I2C HAL Extension module.
******************************************************************************
* @attention
@ -64,7 +64,7 @@
/** @defgroup I2CEx_Analog_Filter I2C Analog Filter Enabling
* @{
*/
#define I2C_ANALOGFILTER_ENABLE ((uint32_t)0x00000000)
#define I2C_ANALOGFILTER_ENABLE ((uint32_t)0x00000000U)
#define I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF
/**
* @}
@ -124,7 +124,7 @@ void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
#define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \
((FILTER) == I2C_ANALOGFILTER_DISABLE))
#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000F)
#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU)
#if defined(STM32L031xx) || defined(STM32L041xx) || defined(STM32L011xx) || defined(STM32L021xx)
#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & (I2C_FASTMODEPLUS_PB6)) == I2C_FASTMODEPLUS_PB6) || \

92
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_i2s.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx_hal_i2s.c
* @author MCD Application Team
* @version V1.5.0
* @date 8-January-2016
* @version V1.7.0
* @date 31-May-2016
* @brief I2S HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Integrated Interchip Sound (I2S) peripheral:
@ -214,8 +214,8 @@ static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s,
*/
HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
{
uint32_t i2sdiv = 2, i2sodd = 0, packetlength = 1;
uint32_t tmp = 0, i2sclk = 0, tmpreg = 0;
uint32_t i2sdiv = 2U, i2sodd = 0U, packetlength = 1U;
uint32_t tmp = 0U, i2sclk = 0U, tmpreg = 0U;
/* Check the I2S handle allocation */
if(hi2s == NULL)
@ -246,8 +246,8 @@ HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
/* If the default value has to be written, reinitialize i2sdiv and i2sodd*/
if(hi2s->Init.AudioFreq == I2S_AUDIOFREQ_DEFAULT)
{
i2sodd = (uint32_t)0;
i2sdiv = (uint32_t)2;
i2sodd = (uint32_t)0U;
i2sdiv = (uint32_t)2U;
}
/* If the requested audio frequency is not the default, compute the prescaler */
else
@ -256,12 +256,12 @@ HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
if(hi2s->Init.DataFormat == I2S_DATAFORMAT_16B)
{
/* Packet length is 16 bits */
packetlength = 1;
packetlength = 1U;
}
else
{
/* Packet length is 32 bits */
packetlength = 2;
packetlength = 2U;
}
/* Get the source clock value: based on System Clock value */
@ -271,33 +271,33 @@ HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
if(hi2s->Init.MCLKOutput == I2S_MCLKOUTPUT_ENABLE)
{
/* MCLK output is enabled */
tmp = (uint32_t)(((((i2sclk / 256) * 10) / hi2s->Init.AudioFreq)) + 5);
tmp = (uint32_t)(((((i2sclk / 256U) * 10U) / hi2s->Init.AudioFreq)) + 5U);
}
else
{
/* MCLK output is disabled */
tmp = (uint32_t)(((((i2sclk / (32 * packetlength)) *10 ) / hi2s->Init.AudioFreq)) + 5);
tmp = (uint32_t)(((((i2sclk / (32U * packetlength)) *10U ) / hi2s->Init.AudioFreq)) + 5U);
}
/* Remove the flatting point */
tmp = tmp / 10;
tmp = tmp / 10U;
/* Check the parity of the divider */
i2sodd = (uint32_t)(tmp & (uint32_t)1);
i2sodd = (uint32_t)(tmp & (uint32_t)1U);
/* Compute the i2sdiv prescaler */
i2sdiv = (uint32_t)((tmp - i2sodd) / 2);
i2sdiv = (uint32_t)((tmp - i2sodd) / 2U);
/* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
i2sodd = (uint32_t) (i2sodd << 8);
i2sodd = (uint32_t) (i2sodd << 8U);
}
/* Test if the divider is 1 or 0 or greater than 0xFF */
if((i2sdiv < 2) || (i2sdiv > 0xFF))
if((i2sdiv < 2U) || (i2sdiv > 0xFFU))
{
/* Set the default values */
i2sdiv = 2;
i2sodd = 0;
i2sdiv = 2U;
i2sodd = 0U;
}
/*----------------------- SPIx I2SCFGR & I2SPR Configuration ----------------*/
@ -467,7 +467,7 @@ HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s)
*/
HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
{
if((pData == NULL ) || (Size == 0))
if((pData == NULL ) || (Size == 0U))
{
return HAL_ERROR;
}
@ -480,8 +480,8 @@ HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uin
if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
{
hi2s->TxXferSize = (Size << 1);
hi2s->TxXferCount = (Size << 1);
hi2s->TxXferSize = (Size << 1U);
hi2s->TxXferCount = (Size << 1U);
}
else
{
@ -501,7 +501,7 @@ HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uin
__HAL_I2S_ENABLE(hi2s);
}
while(hi2s->TxXferCount > 0)
while(hi2s->TxXferCount > 0U)
{
/* Wait until TXE flag is set */
if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, RESET, Timeout) != HAL_OK)
@ -562,7 +562,7 @@ HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uin
*/
HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
{
if((pData == NULL ) || (Size == 0))
if((pData == NULL ) || (Size == 0U))
{
return HAL_ERROR;
}
@ -575,8 +575,8 @@ HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint
if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
{
hi2s->RxXferSize = (Size << 1);
hi2s->RxXferCount = (Size << 1);
hi2s->RxXferSize = (Size << 1U);
hi2s->RxXferCount = (Size << 1U);
}
else
{
@ -605,7 +605,7 @@ HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint
}
/* Receive data */
while(hi2s->RxXferCount > 0)
while(hi2s->RxXferCount > 0U)
{
/* Wait until RXNE flag is set */
if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, RESET, Timeout) != HAL_OK)
@ -649,7 +649,7 @@ HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint
*/
HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
{
if((pData == NULL) || (Size == 0))
if((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@ -666,8 +666,8 @@ HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData,
if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
{
hi2s->TxXferSize = (Size << 1);
hi2s->TxXferCount = (Size << 1);
hi2s->TxXferSize = (Size << 1U);
hi2s->TxXferCount = (Size << 1U);
}
else
{
@ -717,7 +717,7 @@ HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData,
*/
HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
{
if((pData == NULL) || (Size == 0))
if((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@ -734,8 +734,8 @@ HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, u
if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
{
hi2s->RxXferSize = (Size << 1);
hi2s->RxXferCount = (Size << 1);
hi2s->RxXferSize = (Size << 1U);
hi2s->RxXferCount = (Size << 1U);
}
else
{
@ -782,7 +782,7 @@ HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, u
*/
HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
{
if((pData == NULL) || (Size == 0))
if((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@ -799,8 +799,8 @@ HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData,
if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
{
hi2s->TxXferSize = (Size << 1);
hi2s->TxXferCount = (Size << 1);
hi2s->TxXferSize = (Size << 1U);
hi2s->TxXferCount = (Size << 1U);
}
else
{
@ -863,7 +863,7 @@ HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData,
*/
HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
{
if((pData == NULL) || (Size == 0))
if((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@ -880,8 +880,8 @@ HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData,
if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
{
hi2s->RxXferSize = (Size << 1);
hi2s->RxXferCount = (Size << 1);
hi2s->RxXferSize = (Size << 1U);
hi2s->RxXferCount = (Size << 1U);
}
else
{
@ -1243,7 +1243,7 @@ static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma)
/* Disable Tx DMA Request */
CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
hi2s->TxXferCount = 0;
hi2s->TxXferCount = 0U;
hi2s->State = HAL_I2S_STATE_READY;
}
HAL_I2S_TxCpltCallback(hi2s);
@ -1276,7 +1276,7 @@ static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma)
{
/* Disable Rx DMA Request */
CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
hi2s->RxXferCount = 0;
hi2s->RxXferCount = 0U;
hi2s->State = HAL_I2S_STATE_READY;
}
HAL_I2S_RxCpltCallback(hi2s);
@ -1307,8 +1307,8 @@ static void I2S_DMAError(DMA_HandleTypeDef *hdma)
/* Disable Rx and Tx DMA Request */
CLEAR_BIT(hi2s->Instance->CR2, (SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN));
hi2s->TxXferCount = 0;
hi2s->RxXferCount = 0;
hi2s->TxXferCount = 0U;
hi2s->RxXferCount = 0U;
hi2s->State= HAL_I2S_STATE_READY;
@ -1329,7 +1329,7 @@ static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s)
hi2s->Instance->DR = (*hi2s->pTxBuffPtr++);
hi2s->TxXferCount--;
if(hi2s->TxXferCount == 0)
if(hi2s->TxXferCount == 0U)
{
/* Disable TXE and ERR interrupt */
__HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
@ -1350,7 +1350,7 @@ static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s)
(*hi2s->pRxBuffPtr++) = hi2s->Instance->DR;
hi2s->RxXferCount--;
if(hi2s->RxXferCount == 0)
if(hi2s->RxXferCount == 0U)
{
/* Disable RXNE and ERR interrupt */
__HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
@ -1372,7 +1372,7 @@ static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s)
*/
static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t Status, uint32_t Timeout)
{
uint32_t tickstart = 0;
uint32_t tickstart = 0U;
/* Get tick */
tickstart = HAL_GetTick();
@ -1384,7 +1384,7 @@ static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s,
{
if(Timeout != HAL_MAX_DELAY)
{
if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
{
/* Set the I2S State ready */
hi2s->State= HAL_I2S_STATE_READY;
@ -1403,7 +1403,7 @@ static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s,
{
if(Timeout != HAL_MAX_DELAY)
{
if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
{
/* Set the I2S State ready */
hi2s->State= HAL_I2S_STATE_READY;

58
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_i2s.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx_hal_i2s.h
* @author MCD Application Team
* @version V1.5.0
* @date 8-January-2016
* @version V1.7.0
* @date 31-May-2016
* @brief Header file of I2S HAL module.
******************************************************************************
* @attention
@ -90,13 +90,13 @@ typedef struct
*/
typedef enum
{
HAL_I2S_STATE_RESET = 0x00, /*!< I2S not yet initialized or disabled */
HAL_I2S_STATE_READY = 0x01, /*!< I2S initialized and ready for use */
HAL_I2S_STATE_BUSY = 0x02, /*!< I2S internal process is ongoing */
HAL_I2S_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */
HAL_I2S_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */
HAL_I2S_STATE_TIMEOUT = 0x03, /*!< I2S timeout state */
HAL_I2S_STATE_ERROR = 0x04 /*!< I2S error state */
HAL_I2S_STATE_RESET = 0x00U, /*!< I2S not yet initialized or disabled */
HAL_I2S_STATE_READY = 0x01U, /*!< I2S initialized and ready for use */
HAL_I2S_STATE_BUSY = 0x02U, /*!< I2S internal process is ongoing */
HAL_I2S_STATE_BUSY_TX = 0x12U, /*!< Data Transmission process is ongoing */
HAL_I2S_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */
HAL_I2S_STATE_TIMEOUT = 0x03U, /*!< I2S timeout state */
HAL_I2S_STATE_ERROR = 0x04U /*!< I2S error state */
}HAL_I2S_StateTypeDef;
/**
@ -149,11 +149,11 @@ typedef struct
* @defgroup I2S_ErrorCode I2S Error Code
* @{
*/
#define HAL_I2S_ERROR_NONE ((uint32_t)0x00) /*!< No error */
#define HAL_I2S_ERROR_UDR ((uint32_t)0x01) /*!< I2S Underrun error */
#define HAL_I2S_ERROR_OVR ((uint32_t)0x02) /*!< I2S Overrun error */
#define HAL_I2S_ERROR_FRE ((uint32_t)0x04) /*!< I2S Frame format error */
#define HAL_I2S_ERROR_DMA ((uint32_t)0x08) /*!< DMA transfer error */
#define HAL_I2S_ERROR_NONE ((uint32_t)0x00U) /*!< No error */
#define HAL_I2S_ERROR_UDR ((uint32_t)0x01U) /*!< I2S Underrun error */
#define HAL_I2S_ERROR_OVR ((uint32_t)0x02U) /*!< I2S Overrun error */
#define HAL_I2S_ERROR_FRE ((uint32_t)0x04U) /*!< I2S Frame format error */
#define HAL_I2S_ERROR_DMA ((uint32_t)0x08U) /*!< DMA transfer error */
/**
* @}
*/
@ -161,7 +161,7 @@ typedef struct
/** @defgroup I2S_Mode I2S Mode
* @{
*/
#define I2S_MODE_SLAVE_TX ((uint32_t) 0x00000000)
#define I2S_MODE_SLAVE_TX ((uint32_t) 0x00000000U)
#define I2S_MODE_SLAVE_RX ((uint32_t) SPI_I2SCFGR_I2SCFG_0)
#define I2S_MODE_MASTER_TX ((uint32_t) SPI_I2SCFGR_I2SCFG_1)
#define I2S_MODE_MASTER_RX ((uint32_t)(SPI_I2SCFGR_I2SCFG_0 |\
@ -173,7 +173,7 @@ typedef struct
/** @defgroup I2S_Standard I2S Standard
* @{
*/
#define I2S_STANDARD_PHILIPS ((uint32_t) 0x00000000)
#define I2S_STANDARD_PHILIPS ((uint32_t) 0x00000000U)
#define I2S_STANDARD_MSB ((uint32_t) SPI_I2SCFGR_I2SSTD_0)
#define I2S_STANDARD_LSB ((uint32_t) SPI_I2SCFGR_I2SSTD_1)
#define I2S_STANDARD_PCM_SHORT ((uint32_t)(SPI_I2SCFGR_I2SSTD_0 |\
@ -196,7 +196,7 @@ typedef struct
/** @defgroup I2S_Data_Format I2S Data Format
* @{
*/
#define I2S_DATAFORMAT_16B ((uint32_t) 0x00000000)
#define I2S_DATAFORMAT_16B ((uint32_t) 0x00000000U)
#define I2S_DATAFORMAT_16B_EXTENDED ((uint32_t) SPI_I2SCFGR_CHLEN)
#define I2S_DATAFORMAT_24B ((uint32_t)(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0))
#define I2S_DATAFORMAT_32B ((uint32_t)(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1))
@ -208,7 +208,7 @@ typedef struct
* @{
*/
#define I2S_MCLKOUTPUT_ENABLE ((uint32_t)SPI_I2SPR_MCKOE)
#define I2S_MCLKOUTPUT_DISABLE ((uint32_t)0x00000000)
#define I2S_MCLKOUTPUT_DISABLE ((uint32_t)0x00000000U)
/**
* @}
*/
@ -216,16 +216,16 @@ typedef struct
/** @defgroup I2S_Audio_Frequency I2S Audio Frequency
* @{
*/
#define I2S_AUDIOFREQ_192K ((uint32_t)192000)
#define I2S_AUDIOFREQ_96K ((uint32_t)96000)
#define I2S_AUDIOFREQ_48K ((uint32_t)48000)
#define I2S_AUDIOFREQ_44K ((uint32_t)44100)
#define I2S_AUDIOFREQ_32K ((uint32_t)32000)
#define I2S_AUDIOFREQ_22K ((uint32_t)22050)
#define I2S_AUDIOFREQ_16K ((uint32_t)16000)
#define I2S_AUDIOFREQ_11K ((uint32_t)11025)
#define I2S_AUDIOFREQ_8K ((uint32_t)8000)
#define I2S_AUDIOFREQ_DEFAULT ((uint32_t)2)
#define I2S_AUDIOFREQ_192K ((uint32_t)192000U)
#define I2S_AUDIOFREQ_96K ((uint32_t)96000U)
#define I2S_AUDIOFREQ_48K ((uint32_t)48000U)
#define I2S_AUDIOFREQ_44K ((uint32_t)44100U)
#define I2S_AUDIOFREQ_32K ((uint32_t)32000U)
#define I2S_AUDIOFREQ_22K ((uint32_t)22050U)
#define I2S_AUDIOFREQ_16K ((uint32_t)16000U)
#define I2S_AUDIOFREQ_11K ((uint32_t)11025U)
#define I2S_AUDIOFREQ_8K ((uint32_t)8000U)
#define I2S_AUDIOFREQ_DEFAULT ((uint32_t)2U)
/**
* @}
*/
@ -233,7 +233,7 @@ typedef struct
/** @defgroup I2S_Clock_Polarity I2S Clock Polarity
* @{
*/
#define I2S_CPOL_LOW ((uint32_t)0x00000000)
#define I2S_CPOL_LOW ((uint32_t)0x00000000U)
#define I2S_CPOL_HIGH ((uint32_t)SPI_I2SCFGR_CKPOL)
/**
* @}

114
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_irda.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx_hal_irda.c
* @author MCD Application Team
* @version V1.5.0
* @date 8-January-2016
* @version V1.7.0
* @date 31-May-2016
* @brief IRDA HAL module driver.
*
* This file provides firmware functions to manage the following
@ -147,8 +147,8 @@
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
#define TEACK_REACK_TIMEOUT 1000
#define HAL_IRDA_TXDMA_TIMEOUTVALUE 22000
#define TEACK_REACK_TIMEOUT 1000U
#define HAL_IRDA_TXDMA_TIMEOUTVALUE 22000U
#define IRDA_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE \
| USART_CR1_PS | USART_CR1_TE | USART_CR1_RE))
/* Private macro -------------------------------------------------------------*/
@ -187,9 +187,21 @@ static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda);
(++) Word Length
(++) Parity: If the parity is enabled, then the MSB bit of the data written
in the data register is transmitted but is changed by the parity bit.
Depending on the frame length defined by the M bit (8-bits or 9-bits)
or by the M1 and M0 bits (7-bit, 8-bit or 9-bit),
the possible IRDA frame formats are as listed in the following table:
(++) Power mode
(++) Prescaler setting
(++) Receiver/transmitter modes
[..]
The HAL_IRDA_Init() API follows the USART asynchronous configuration procedures
(details for the procedures are available in reference manual).
@endverbatim
Depending on the frame length defined by the M bit (8-bits or 9-bits)
or by the M1 and M0 bits (7-bit, 8-bit or 9-bit),
the possible IRDA frame formats are as listed in the following table:
Table 1. IRDA frame format.
+---------------------------------------------------------------+
| M1M0 bits | PCE bit | IRDA frame |
|-----------|-----------|---------------------------------------|
@ -205,16 +217,7 @@ static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda);
|-----------|-----------|---------------------------------------|
| 10 | 1 | | SB | 6-bit data | PB | STB | |
+---------------------------------------------------------------+
(++) Power mode
(++) Prescaler setting
(++) Receiver/transmitter modes
[..]
The HAL_IRDA_Init() API follows the USART asynchronous configuration procedures
(details for the procedures are available in reference manual).
@endverbatim
* @{
*/
@ -396,7 +399,7 @@ HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, u
if ((hirda->State == HAL_IRDA_STATE_READY) || (hirda->State == HAL_IRDA_STATE_BUSY_RX))
{
if((pData == NULL) || (Size == 0))
if((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@ -416,7 +419,7 @@ HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, u
hirda->TxXferSize = Size;
hirda->TxXferCount = Size;
while(hirda->TxXferCount > 0)
while(hirda->TxXferCount > 0U)
{
hirda->TxXferCount--;
@ -427,12 +430,12 @@ HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, u
if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
{
tmp = (uint16_t*) pData;
hirda->Instance->TDR = (*tmp & (uint16_t)0x01FF);
hirda->Instance->TDR = (*tmp & (uint16_t)0x01FFU);
pData +=2;
}
else
{
hirda->Instance->TDR = (*pData++ & (uint8_t)0xFF);
hirda->Instance->TDR = (*pData++ & (uint8_t)0xFFU);
}
}
@ -476,7 +479,7 @@ HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, ui
if ((hirda->State == HAL_IRDA_STATE_READY) || (hirda->State == HAL_IRDA_STATE_BUSY_TX))
{
if((pData == NULL) || (Size == 0))
if((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@ -503,7 +506,7 @@ HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, ui
uhMask = hirda->Mask;
/* Check data remaining to be received */
while(hirda->RxXferCount > 0)
while(hirda->RxXferCount > 0U)
{
hirda->RxXferCount--;
@ -515,7 +518,7 @@ HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, ui
{
tmp = (uint16_t*) pData ;
*tmp = (uint16_t)(hirda->Instance->RDR & uhMask);
pData +=2;
pData +=2U;
}
else
{
@ -554,7 +557,7 @@ HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData
{
if ((hirda->State == HAL_IRDA_STATE_READY) || (hirda->State == HAL_IRDA_STATE_BUSY_RX))
{
if((pData == NULL) || (Size == 0))
if((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@ -576,9 +579,6 @@ HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData
hirda->State = HAL_IRDA_STATE_BUSY_TX;
}
/* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
__HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_ERR);
/* Process Unlocked */
__HAL_UNLOCK(hirda);
@ -604,7 +604,7 @@ HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData,
{
if ((hirda->State == HAL_IRDA_STATE_READY) || (hirda->State == HAL_IRDA_STATE_BUSY_TX))
{
if((pData == NULL) || (Size == 0))
if((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@ -663,7 +663,7 @@ HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pDat
if ((hirda->State == HAL_IRDA_STATE_READY) || (hirda->State == HAL_IRDA_STATE_BUSY_RX))
{
if((pData == NULL) || (Size == 0))
if((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@ -732,7 +732,7 @@ HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData
if ((hirda->State == HAL_IRDA_STATE_READY) || (hirda->State == HAL_IRDA_STATE_BUSY_TX))
{
if((pData == NULL) || (Size == 0))
if((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@ -1097,8 +1097,8 @@ uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda)
*/
static void IRDA_SetConfig(IRDA_HandleTypeDef *hirda)
{
uint32_t tmpreg = 0x00000000;
uint32_t clocksource = 0x00000000;
uint32_t tmpreg = 0x00000000U;
uint32_t clocksource = 0x00000000U;
/* Check the communication parameters */
assert_param(IS_IRDA_BAUDRATE(hirda->Init.BaudRate));
@ -1127,19 +1127,19 @@ static void IRDA_SetConfig(IRDA_HandleTypeDef *hirda)
switch (clocksource)
{
case IRDA_CLOCKSOURCE_PCLK1:
hirda->Instance->BRR = (uint16_t)(HAL_RCC_GetPCLK1Freq() / hirda->Init.BaudRate);
hirda->Instance->BRR = (uint16_t)((HAL_RCC_GetPCLK1Freq() + (hirda->Init.BaudRate/2U)) / hirda->Init.BaudRate);
break;
case IRDA_CLOCKSOURCE_PCLK2:
hirda->Instance->BRR = (uint16_t)(HAL_RCC_GetPCLK2Freq() / hirda->Init.BaudRate);
hirda->Instance->BRR = (uint16_t)((HAL_RCC_GetPCLK2Freq() + (hirda->Init.BaudRate/2U)) / hirda->Init.BaudRate);
break;
case IRDA_CLOCKSOURCE_HSI:
hirda->Instance->BRR = (uint16_t)(HSI_VALUE / hirda->Init.BaudRate);
hirda->Instance->BRR = (uint16_t)((HSI_VALUE + (hirda->Init.BaudRate/2U)) / hirda->Init.BaudRate);
break;
case IRDA_CLOCKSOURCE_SYSCLK:
hirda->Instance->BRR = (uint16_t)(HAL_RCC_GetSysClockFreq() / hirda->Init.BaudRate);
hirda->Instance->BRR = (uint16_t)((HAL_RCC_GetSysClockFreq() + (hirda->Init.BaudRate/2U)) / hirda->Init.BaudRate);
break;
case IRDA_CLOCKSOURCE_LSE:
hirda->Instance->BRR = (uint16_t)(LSE_VALUE / hirda->Init.BaudRate);
hirda->Instance->BRR = (uint16_t)((LSE_VALUE + (hirda->Init.BaudRate/2U)) / hirda->Init.BaudRate);
break;
default:
break;
@ -1194,7 +1194,7 @@ static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda)
*/
static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
{
uint32_t tickstart = 0x00;
uint32_t tickstart = 0x00U;
tickstart = HAL_GetTick();
/* Wait until flag is set */
@ -1205,7 +1205,7 @@ static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda,
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
{
if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
{
/* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
__HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TXE);
@ -1230,7 +1230,7 @@ static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda,
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
{
if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
{
/* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
__HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TXE);
@ -1265,7 +1265,7 @@ static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda)
if((hirda->State == HAL_IRDA_STATE_BUSY_TX) || (hirda->State == HAL_IRDA_STATE_BUSY_TX_RX))
{
if(hirda->TxXferCount == 0)
if(hirda->TxXferCount == 0U)
{
/* Disable the IRDA Transmit Data Register Empty Interrupt */
__HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TXE);
@ -1280,12 +1280,12 @@ static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda)
if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
{
tmp = (uint16_t*) hirda->pTxBuffPtr;
hirda->Instance->TDR = (*tmp & (uint16_t)0x01FF);
hirda->pTxBuffPtr += 2;
hirda->Instance->TDR = (*tmp & (uint16_t)0x01FFU);
hirda->pTxBuffPtr += 2U;
}
else
{
hirda->Instance->TDR = (uint8_t)(*hirda->pTxBuffPtr++ & (uint8_t)0xFF);
hirda->Instance->TDR = (uint8_t)(*hirda->pTxBuffPtr++ & (uint8_t)0xFFU);
}
hirda->TxXferCount--;
return HAL_OK;
@ -1343,32 +1343,32 @@ static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda)
{
tmp = (uint16_t*) hirda->pRxBuffPtr ;
*tmp = (uint16_t)(hirda->Instance->RDR & uhMask);
hirda->pRxBuffPtr +=2;
hirda->pRxBuffPtr +=2U;
}
else
{
*hirda->pRxBuffPtr++ = (uint8_t)(hirda->Instance->RDR & (uint8_t)uhMask);
}
if(--hirda->RxXferCount == 0)
if(--hirda->RxXferCount == 0U)
{
while(HAL_IS_BIT_SET(hirda->Instance->ISR, IRDA_FLAG_RXNE))
{
}
__HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_RXNE);
/* Disable the IRDA Parity Error Interrupt */
__HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_PE);
/* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
__HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR);
if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX)
{
hirda->State = HAL_IRDA_STATE_BUSY_TX;
}
else
{
/* Disable the IRDA Parity Error Interrupt */
__HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_PE);
/* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
__HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR);
hirda->State = HAL_IRDA_STATE_READY;
}
@ -1397,7 +1397,7 @@ static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma)
/* DMA Normal mode */
if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) )
{
hirda->TxXferCount = 0;
hirda->TxXferCount = 0U;
/* Disable the DMA transfer for transmit request by resetting the DMAT bit
in the IRDA CR3 register */
@ -1435,9 +1435,9 @@ static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
{
IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
/* DMA Normal mode */
if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0)
if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
{
hirda->RxXferCount = 0;
hirda->RxXferCount = 0U;
/* Disable the DMA transfer for the receiver request by setting the DMAR bit
in the IRDA CR3 register */
@ -1477,8 +1477,8 @@ static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma)
static void IRDA_DMAError(DMA_HandleTypeDef *hdma)
{
IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
hirda->RxXferCount = 0;
hirda->TxXferCount = 0;
hirda->RxXferCount = 0U;
hirda->TxXferCount = 0U;
hirda->State= HAL_IRDA_STATE_READY;
hirda->ErrorCode |= HAL_IRDA_ERROR_DMA;
HAL_IRDA_ErrorCallback(hirda);

96
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_irda.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx_hal_irda.h
* @author MCD Application Team
* @version V1.5.0
* @date 8-January-2016
* @version V1.7.0
* @date 31-May-2016
* @brief Header file of IRDA HAL module.
******************************************************************************
* @attention
@ -94,14 +94,14 @@ typedef struct
*/
typedef enum
{
HAL_IRDA_STATE_RESET = 0x00, /*!< Peripheral is not yet Initialized */
HAL_IRDA_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
HAL_IRDA_STATE_BUSY = 0x02, /*!< an internal process is ongoing */
HAL_IRDA_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */
HAL_IRDA_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */
HAL_IRDA_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */
HAL_IRDA_STATE_TIMEOUT = 0x03, /*!< Timeout state */
HAL_IRDA_STATE_ERROR = 0x04 /*!< Error */
HAL_IRDA_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */
HAL_IRDA_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
HAL_IRDA_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */
HAL_IRDA_STATE_BUSY_TX = 0x12U, /*!< Data Transmission process is ongoing */
HAL_IRDA_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */
HAL_IRDA_STATE_BUSY_TX_RX = 0x32U, /*!< Data Transmission and Reception process is ongoing */
HAL_IRDA_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
HAL_IRDA_STATE_ERROR = 0x04U /*!< Error */
}HAL_IRDA_StateTypeDef;
@ -159,29 +159,29 @@ typedef struct
* @brief HAL IRDA Error Code definition
*/
#define HAL_IRDA_ERROR_NONE ((uint32_t)0x00) /*!< No error */
#define HAL_IRDA_ERROR_PE ((uint32_t)0x01) /*!< Parity error */
#define HAL_IRDA_ERROR_NE ((uint32_t)0x02) /*!< Noise error */
#define HAL_IRDA_ERROR_FE ((uint32_t)0x04) /*!< frame error */
#define HAL_IRDA_ERROR_ORE ((uint32_t)0x08) /*!< Overrun error */
#define HAL_IRDA_ERROR_DMA ((uint32_t)0x10) /*!< DMA transfer error */
#define HAL_IRDA_ERROR_NONE ((uint32_t)0x00U) /*!< No error */
#define HAL_IRDA_ERROR_PE ((uint32_t)0x01U) /*!< Parity error */
#define HAL_IRDA_ERROR_NE ((uint32_t)0x02U) /*!< Noise error */
#define HAL_IRDA_ERROR_FE ((uint32_t)0x04U) /*!< frame error */
#define HAL_IRDA_ERROR_ORE ((uint32_t)0x08U) /*!< Overrun error */
#define HAL_IRDA_ERROR_DMA ((uint32_t)0x10U) /*!< DMA transfer error */
/**
* @brief IRDA clock sources definition
*/
typedef enum
{
IRDA_CLOCKSOURCE_PCLK1 = 0x00, /*!< PCLK1 clock source */
IRDA_CLOCKSOURCE_PCLK2 = 0x01, /*!< PCLK2 clock source */
IRDA_CLOCKSOURCE_HSI = 0x02, /*!< HSI clock source */
IRDA_CLOCKSOURCE_SYSCLK = 0x04, /*!< SYSCLK clock source */
IRDA_CLOCKSOURCE_LSE = 0x08 /*!< LSE clock source */
IRDA_CLOCKSOURCE_PCLK1 = 0x00U, /*!< PCLK1 clock source */
IRDA_CLOCKSOURCE_PCLK2 = 0x01U, /*!< PCLK2 clock source */
IRDA_CLOCKSOURCE_HSI = 0x02U, /*!< HSI clock source */
IRDA_CLOCKSOURCE_SYSCLK = 0x04U, /*!< SYSCLK clock source */
IRDA_CLOCKSOURCE_LSE = 0x08U /*!< LSE clock source */
}IRDA_ClockSourceTypeDef;
/** @defgroup IRDA_Parity IRDA Parity
* @{
*/
#define IRDA_PARITY_NONE ((uint32_t)0x0000)
#define IRDA_PARITY_NONE ((uint32_t)0x0000U)
#define IRDA_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
#define IRDA_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
#define IS_IRDA_PARITY(PARITY) (((PARITY) == IRDA_PARITY_NONE) || \
@ -206,7 +206,7 @@ typedef enum
/** @defgroup IRDA_Low_Power IRDA low power
* @{
*/
#define IRDA_POWERMODE_NORMAL ((uint32_t)0x0000)
#define IRDA_POWERMODE_NORMAL ((uint32_t)0x0000U)
#define IRDA_POWERMODE_LOWPOWER ((uint32_t)USART_CR3_IRLP)
#define IS_IRDA_POWERMODE(MODE) (((MODE) == IRDA_POWERMODE_LOWPOWER) || \
((MODE) == IRDA_POWERMODE_NORMAL))
@ -217,7 +217,7 @@ typedef enum
/** @defgroup IRDA_State IRDA State
* @{
*/
#define IRDA_STATE_DISABLE ((uint32_t)0x0000)
#define IRDA_STATE_DISABLE ((uint32_t)0x0000U)
#define IRDA_STATE_ENABLE ((uint32_t)USART_CR1_UE)
#define IS_IRDA_STATE(STATE) (((STATE) == IRDA_STATE_DISABLE) || \
((STATE) == IRDA_STATE_ENABLE))
@ -228,7 +228,7 @@ typedef enum
/** @defgroup IRDA_Mode IRDA Mode
* @{
*/
#define IRDA_MODE_DISABLE ((uint32_t)0x0000)
#define IRDA_MODE_DISABLE ((uint32_t)0x0000U)
#define IRDA_MODE_ENABLE ((uint32_t)USART_CR3_IREN)
#define IS_IRDA_MODE(STATE) (((STATE) == IRDA_MODE_DISABLE) || \
((STATE) == IRDA_MODE_ENABLE))
@ -239,7 +239,7 @@ typedef enum
/** @defgroup IRDA_One_Bit IRDA One bit
* @{
*/
#define IRDA_ONE_BIT_SAMPLE_DISABLE ((uint32_t)0x00000000)
#define IRDA_ONE_BIT_SAMPLE_DISABLE ((uint32_t)0x00000000U)
#define IRDA_ONE_BIT_SAMPLE_ENABLE ((uint32_t)USART_CR3_ONEBIT)
#define IS_IRDA_ONE_BIT_SAMPLE(ONEBIT) (((ONEBIT) == IRDA_ONE_BIT_SAMPLE_DISABLE) || \
((ONEBIT) == IRDA_ONE_BIT_SAMPLE_ENABLE))
@ -250,7 +250,7 @@ typedef enum
/** @defgroup IRDA_DMA_Tx IRDA DMA TX
* @{
*/
#define IRDA_DMA_TX_DISABLE ((uint32_t)0x00000000)
#define IRDA_DMA_TX_DISABLE ((uint32_t)0x00000000U)
#define IRDA_DMA_TX_ENABLE ((uint32_t)USART_CR3_DMAT)
#define IS_IRDA_DMA_TX(DMATX) (((DMATX) == IRDA_DMA_TX_DISABLE) || \
((DMATX) == IRDA_DMA_TX_ENABLE))
@ -261,7 +261,7 @@ typedef enum
/** @defgroup IRDA_DMA_Rx IRDA DMA RX
* @{
*/
#define IRDA_DMA_RX_DISABLE ((uint32_t)0x0000)
#define IRDA_DMA_RX_DISABLE ((uint32_t)0x0000U)
#define IRDA_DMA_RX_ENABLE ((uint32_t)USART_CR3_DMAR)
#define IS_IRDA_DMA_RX(DMARX) (((DMARX) == IRDA_DMA_RX_DISABLE) || \
((DMARX) == IRDA_DMA_RX_ENABLE))
@ -300,11 +300,11 @@ typedef enum
* - ZZZZ : Flag position in the ISR register(4bits)
* @{
*/
#define IRDA_IT_PE ((uint16_t)0x0028)
#define IRDA_IT_TXE ((uint16_t)0x0727)
#define IRDA_IT_TC ((uint16_t)0x0626)
#define IRDA_IT_RXNE ((uint16_t)0x0525)
#define IRDA_IT_IDLE ((uint16_t)0x0424)
#define IRDA_IT_PE ((uint16_t)0x0028U)
#define IRDA_IT_TXE ((uint16_t)0x0727U)
#define IRDA_IT_TC ((uint16_t)0x0626U)
#define IRDA_IT_RXNE ((uint16_t)0x0525U)
#define IRDA_IT_IDLE ((uint16_t)0x0424U)
@ -315,14 +315,14 @@ typedef enum
* - 10: CR2 register
* - 11: CR3 register
*/
#define IRDA_IT_ERR ((uint16_t)0x0060)
#define IRDA_IT_ERR ((uint16_t)0x0060U)
/** Elements values convention: 0000ZZZZ00000000b
* - ZZZZ : Flag position in the ISR register(4bits)
*/
#define IRDA_IT_ORE ((uint16_t)0x0300)
#define IRDA_IT_NE ((uint16_t)0x0200)
#define IRDA_IT_FE ((uint16_t)0x0100)
#define IRDA_IT_ORE ((uint16_t)0x0300U)
#define IRDA_IT_NE ((uint16_t)0x0200U)
#define IRDA_IT_FE ((uint16_t)0x0100U)
/**
* @}
*/
@ -360,7 +360,7 @@ typedef enum
/** @defgroup IRDA_Interruption_Mask IRDA Interruption mask
* @{
*/
#define IRDA_IT_MASK ((uint16_t)0x001F)
#define IRDA_IT_MASK ((uint16_t)0x001FU)
/**
* @}
*/
@ -477,9 +477,9 @@ typedef enum
* @arg IRDA_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
* @retval None
*/
#define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5) == 1)? ((__HANDLE__)->Instance->CR1 |= (1 << ((__INTERRUPT__) & IRDA_IT_MASK))): \
((((uint8_t)(__INTERRUPT__)) >> 5) == 2)? ((__HANDLE__)->Instance->CR2 |= (1 << ((__INTERRUPT__) & IRDA_IT_MASK))): \
((__HANDLE__)->Instance->CR3 |= (1 << ((__INTERRUPT__) & IRDA_IT_MASK))))
#define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & IRDA_IT_MASK))))
/** @brief Disable the specified IRDA interrupt.
* @param __HANDLE__: specifies the IRDA Handle.
@ -494,8 +494,8 @@ typedef enum
* @arg IRDA_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
* @retval None
*/
#define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ ((uint32_t)1 << ((__INTERRUPT__) & IRDA_IT_MASK))): \
((((uint8_t)(__INTERRUPT__)) >> 5) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ ((uint32_t)1 << ((__INTERRUPT__) & IRDA_IT_MASK))): \
#define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
((__HANDLE__)->Instance->CR3 &= ~ ((uint32_t)1 << ((__INTERRUPT__) & IRDA_IT_MASK))))
/** @brief Check whether the specified IRDA interrupt has occurred or not.
@ -513,7 +513,7 @@ typedef enum
* @arg IRDA_IT_PE: Parity Error interrupt
* @retval The new state of __IT__ (TRUE or FALSE).
*/
#define __HAL_IRDA_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08)))
#define __HAL_IRDA_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1U << ((__IT__)>> 0x08U)))
/** @brief Check whether the specified IRDA interrupt source is enabled.
* @param __HANDLE__: specifies the IRDA Handle.
@ -530,8 +530,8 @@ typedef enum
* @arg IRDA_IT_PE: Parity Error interrupt
* @retval The new state of __IT__ (TRUE or FALSE).
*/
#define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5) == 1)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5) == 2)? \
(__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & ((uint32_t)1 << (((uint16_t)(__IT__)) & IRDA_IT_MASK)))
#define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5U) == 1U)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5U) == 2U)? \
(__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & ((uint32_t)1U << (((uint16_t)(__IT__)) & IRDA_IT_MASK)))
/** @brief Clear the specified IRDA ISR flag, in setting the proper ICR register flag.
* @param __HANDLE__: specifies the IRDA Handle.
@ -591,13 +591,13 @@ typedef enum
* @param __BAUDRATE__: specifies the IRDA Baudrate set by the user.
* @retval True or False
*/
#define IS_IRDA_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 115201)
#define IS_IRDA_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 115201U)
/** @brief Ensure that IRDA prescaler value is strictly larger than 0
* @param __PRESCALER__: specifies the IRDA prescaler value set by the user.
* @retval True or False
*/
#define IS_IRDA_PRESCALER(__PRESCALER__) ((__PRESCALER__) > 0)
#define IS_IRDA_PRESCALER(__PRESCALER__) ((__PRESCALER__) > 0U)
/**
* @}

18
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_irda_ex.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx_hal_irda_ex.h
* @author MCD Application Team
* @version V1.5.0
* @date 8-January-2016
* @version V1.7.0
* @date 31-May-2016
* @brief Header file of IRDA HAL Extension module.
******************************************************************************
* @attention
@ -64,7 +64,7 @@
* @{
*/
#define IRDA_WORDLENGTH_7B ((uint32_t)USART_CR1_M1)
#define IRDA_WORDLENGTH_8B ((uint32_t)0x00000000)
#define IRDA_WORDLENGTH_8B ((uint32_t)0x00000000U)
#define IRDA_WORDLENGTH_9B ((uint32_t)USART_CR1_M0)
#define IS_IRDA_WORD_LENGTH(LENGTH) (((LENGTH) == IRDA_WORDLENGTH_7B) || \
((LENGTH) == IRDA_WORDLENGTH_8B) || \
@ -211,33 +211,33 @@
{ \
if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
{ \
(__HANDLE__)->Mask = 0x01FF ; \
(__HANDLE__)->Mask = 0x01FFU ; \
} \
else \
{ \
(__HANDLE__)->Mask = 0x00FF ; \
(__HANDLE__)->Mask = 0x00FFU ; \
} \
} \
else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_8B) \
{ \
if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
{ \
(__HANDLE__)->Mask = 0x00FF ; \
(__HANDLE__)->Mask = 0x00FFU ; \
} \
else \
{ \
(__HANDLE__)->Mask = 0x007F ; \
(__HANDLE__)->Mask = 0x007FU ; \
} \
} \
else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_7B) \
{ \
if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
{ \
(__HANDLE__)->Mask = 0x007F ; \
(__HANDLE__)->Mask = 0x007FU ; \
} \
else \
{ \
(__HANDLE__)->Mask = 0x003F ; \
(__HANDLE__)->Mask = 0x003FU ; \
} \
} \
} while(0)

18
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_iwdg.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx_hal_iwdg.c
* @author MCD Application Team
* @version V1.5.0
* @date 8-January-2016
* @version V1.7.0
* @date 31-May-2016
* @brief IWDG HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Independent Watchdog (IWDG) peripheral:
@ -129,7 +129,7 @@
* @{
*/
/* TimeOut value */
#define HAL_IWDG_DEFAULT_TIMEOUT (uint32_t)1000
#define HAL_IWDG_DEFAULT_TIMEOUT (uint32_t)1000U
/* Local define used to check the SR status register */
#define IWDG_SR_FLAGS (IWDG_FLAG_PVU | IWDG_FLAG_RVU | IWDG_FLAG_WVU)
@ -172,7 +172,7 @@
HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
{
uint32_t tickstart = 0;
uint32_t tickstart = 0U;
/* Check the IWDG handle allocation */
if(hiwdg == NULL)
@ -186,7 +186,7 @@ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
assert_param(IS_IWDG_WINDOW(hiwdg->Init.Window));
/* Check pending flag, if previous update not done, return error */
if(((hiwdg->Instance->SR) & IWDG_SR_FLAGS) != 0)
if(((hiwdg->Instance->SR) & IWDG_SR_FLAGS) != 0U)
{
return HAL_ERROR;
}
@ -217,7 +217,7 @@ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
tickstart = HAL_GetTick();
/* Wait for register to be updated */
while (((hiwdg->Instance->SR) & IWDG_SR_FLAGS) != 0)
while (((hiwdg->Instance->SR) & IWDG_SR_FLAGS) != 0U)
{
if((HAL_GetTick()-tickstart) > HAL_IWDG_DEFAULT_TIMEOUT)
{
@ -281,7 +281,7 @@ __weak void HAL_IWDG_MspInit(IWDG_HandleTypeDef *hiwdg)
*/
HAL_StatusTypeDef HAL_IWDG_Start(IWDG_HandleTypeDef *hiwdg)
{
uint32_t tickstart = 0;
uint32_t tickstart = 0U;
/* Process locked */
__HAL_LOCK(hiwdg);
@ -301,7 +301,7 @@ HAL_StatusTypeDef HAL_IWDG_Start(IWDG_HandleTypeDef *hiwdg)
tickstart = HAL_GetTick();
/* Wait until PVU, RVU, WVU flag are RESET */
while (((hiwdg->Instance->SR) & IWDG_SR_FLAGS) != 0)
while (((hiwdg->Instance->SR) & IWDG_SR_FLAGS) != 0U)
{
if((HAL_GetTick()-tickstart) > HAL_IWDG_DEFAULT_TIMEOUT)
{
@ -332,7 +332,7 @@ HAL_StatusTypeDef HAL_IWDG_Start(IWDG_HandleTypeDef *hiwdg)
*/
HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg)
{
uint32_t tickstart = 0;
uint32_t tickstart = 0U;
/* Process Locked */
__HAL_LOCK(hiwdg);

30
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_iwdg.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx_hal_iwdg.h
* @author MCD Application Team
* @version V1.5.0
* @date 8-January-2016
* @version V1.7.0
* @date 31-May-2016
* @brief Header file of IWDG HAL module.
******************************************************************************
* @attention
@ -68,11 +68,11 @@
*/
typedef enum
{
HAL_IWDG_STATE_RESET = 0x00, /*!< IWDG not yet initialized or disabled */
HAL_IWDG_STATE_READY = 0x01, /*!< IWDG initialized and ready for use */
HAL_IWDG_STATE_BUSY = 0x02, /*!< IWDG internal process is ongoing */
HAL_IWDG_STATE_TIMEOUT = 0x03, /*!< IWDG timeout state */
HAL_IWDG_STATE_ERROR = 0x04 /*!< IWDG error state */
HAL_IWDG_STATE_RESET = 0x00U, /*!< IWDG not yet initialized or disabled */
HAL_IWDG_STATE_READY = 0x01U, /*!< IWDG initialized and ready for use */
HAL_IWDG_STATE_BUSY = 0x02U, /*!< IWDG internal process is ongoing */
HAL_IWDG_STATE_TIMEOUT = 0x03U, /*!< IWDG timeout state */
HAL_IWDG_STATE_ERROR = 0x04U /*!< IWDG error state */
}HAL_IWDG_StateTypeDef;
/**
@ -138,10 +138,10 @@ typedef struct
*/
/* --- KR Register ---*/
/* KR register bit mask */
#define IWDG_KEY_RELOAD ((uint32_t)0xAAAA) /*!< IWDG Reload Counter Enable */
#define IWDG_KEY_ENABLE ((uint32_t)0xCCCC) /*!< IWDG Peripheral Enable */
#define IWDG_KEY_WRITE_ACCESS_ENABLE ((uint32_t)0x5555) /*!< IWDG KR Write Access Enable */
#define IWDG_KEY_WRITE_ACCESS_DISABLE ((uint32_t)0x0000) /*!< IWDG KR Write Access Disable */
#define IWDG_KEY_RELOAD ((uint32_t)0xAAAAU) /*!< IWDG Reload Counter Enable */
#define IWDG_KEY_ENABLE ((uint32_t)0xCCCCU) /*!< IWDG Peripheral Enable */
#define IWDG_KEY_WRITE_ACCESS_ENABLE ((uint32_t)0x5555U) /*!< IWDG KR Write Access Enable */
#define IWDG_KEY_WRITE_ACCESS_DISABLE ((uint32_t)0x0000U) /*!< IWDG KR Write Access Disable */
/**
* @}
*/
@ -165,7 +165,7 @@ typedef struct
/** @defgroup IWDG_Prescaler IWDG Prescaler
* @{
*/
#define IWDG_PRESCALER_4 ((uint8_t)0x00) /*!< IWDG prescaler set to 4 */
#define IWDG_PRESCALER_4 ((uint8_t)0x00U) /*!< IWDG prescaler set to 4 */
#define IWDG_PRESCALER_8 ((uint8_t)(IWDG_PR_PR_0)) /*!< IWDG prescaler set to 8 */
#define IWDG_PRESCALER_16 ((uint8_t)(IWDG_PR_PR_1)) /*!< IWDG prescaler set to 16 */
#define IWDG_PRESCALER_32 ((uint8_t)(IWDG_PR_PR_1 | IWDG_PR_PR_0)) /*!< IWDG prescaler set to 32 */
@ -184,16 +184,16 @@ typedef struct
((__PRESCALER__) == IWDG_PRESCALER_256))
/* Check for reload value */
#define IS_IWDG_RELOAD(__RELOAD__) ((__RELOAD__) <= 0xFFF)
#define IS_IWDG_RELOAD(__RELOAD__) ((__RELOAD__) <= 0xFFFU)
/* Check for window value */
#define IS_IWDG_WINDOW(__VALUE__) ((__VALUE__) <= 0xFFF)
#define IS_IWDG_WINDOW(__VALUE__) ((__VALUE__) <= 0xFFFU)
/** @defgroup IWDG_Disable IWDG Disable
* @{
*/
#define IWDG_WINDOW_DISABLE 0xFFF
#define IWDG_WINDOW_DISABLE 0xFFFU
/**
* @}
*/

24
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_lcd.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx_hal_lcd.c
* @author MCD Application Team
* @version V1.5.0
* @date 8-January-2016
* @version V1.7.0
* @date 31-May-2016
* @brief LCD Controller HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the LCD Controller (LCD) peripheral:
@ -108,7 +108,7 @@
/** @addtogroup LCD_Private
* @{
*/
#define LCD_TIMEOUT_VALUE 1000
#define LCD_TIMEOUT_VALUE 1000U
/**
* @}
*/
@ -186,8 +186,8 @@ HAL_StatusTypeDef HAL_LCD_DeInit(LCD_HandleTypeDef *hlcd)
*/
HAL_StatusTypeDef HAL_LCD_Init(LCD_HandleTypeDef *hlcd)
{
uint32_t tickstart = 0x00;
uint8_t counter = 0;
uint32_t tickstart = 0x00U;
uint8_t counter = 0U;
/* Check the LCD handle allocation */
if(hlcd == NULL)
@ -228,7 +228,7 @@ HAL_StatusTypeDef HAL_LCD_Init(LCD_HandleTypeDef *hlcd)
in the LCD_SR register */
for(counter = LCD_RAM_REGISTER0; counter <= LCD_RAM_REGISTER15; counter++)
{
hlcd->Instance->RAM[counter] = 0;
hlcd->Instance->RAM[counter] = 0U;
}
/* Enable the display request */
SET_BIT(hlcd->Instance->SR, LCD_SR_UDR);
@ -394,7 +394,7 @@ HAL_StatusTypeDef HAL_LCD_Init(LCD_HandleTypeDef *hlcd)
*/
HAL_StatusTypeDef HAL_LCD_Write(LCD_HandleTypeDef *hlcd, uint32_t RAMRegisterIndex, uint32_t RAMRegisterMask, uint32_t Data)
{
uint32_t tickstart = 0x00;
uint32_t tickstart = 0x00U;
if((hlcd->State == HAL_LCD_STATE_READY) || (hlcd->State == HAL_LCD_STATE_BUSY))
{
@ -440,8 +440,8 @@ HAL_StatusTypeDef HAL_LCD_Write(LCD_HandleTypeDef *hlcd, uint32_t RAMRegisterInd
*/
HAL_StatusTypeDef HAL_LCD_Clear(LCD_HandleTypeDef *hlcd)
{
uint32_t tickstart = 0x00;
uint32_t counter = 0;
uint32_t tickstart = 0x00U;
uint32_t counter = 0U;
if((hlcd->State == HAL_LCD_STATE_READY) || (hlcd->State == HAL_LCD_STATE_BUSY))
{
@ -469,7 +469,7 @@ HAL_StatusTypeDef HAL_LCD_Clear(LCD_HandleTypeDef *hlcd)
/* Clear the LCD_RAM registers */
for(counter = LCD_RAM_REGISTER0; counter <= LCD_RAM_REGISTER15; counter++)
{
hlcd->Instance->RAM[counter] = 0;
hlcd->Instance->RAM[counter] = 0U;
}
/* Update the LCD display */
@ -499,7 +499,7 @@ HAL_StatusTypeDef HAL_LCD_Clear(LCD_HandleTypeDef *hlcd)
*/
HAL_StatusTypeDef HAL_LCD_UpdateDisplayRequest(LCD_HandleTypeDef *hlcd)
{
uint32_t tickstart = 0x00;
uint32_t tickstart = 0x00U;
/* Clear the Update Display Done flag before starting the update display request */
__HAL_LCD_CLEAR_FLAG(hlcd, LCD_FLAG_UDD);
@ -591,7 +591,7 @@ uint32_t HAL_LCD_GetError(LCD_HandleTypeDef *hlcd)
*/
HAL_StatusTypeDef LCD_WaitForSynchro(LCD_HandleTypeDef *hlcd)
{
uint32_t tickstart = 0x00;
uint32_t tickstart = 0x00U;
/* Get timeout */
tickstart = HAL_GetTick();

158
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_lcd.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx_hal_lcd.h
* @author MCD Application Team
* @version V1.5.0
* @date 8-January-2016
* @version V1.7.0
* @date 31-May-2016
* @brief Header file of LCD Controller HAL module.
******************************************************************************
* @attention
@ -99,11 +99,11 @@ typedef struct
*/
typedef enum
{
HAL_LCD_STATE_RESET = 0x00, /*!< Peripheral is not yet Initialized */
HAL_LCD_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
HAL_LCD_STATE_BUSY = 0x02, /*!< an internal process is ongoing */
HAL_LCD_STATE_TIMEOUT = 0x03, /*!< Timeout state */
HAL_LCD_STATE_ERROR = 0x04 /*!< Error */
HAL_LCD_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */
HAL_LCD_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
HAL_LCD_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */
HAL_LCD_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
HAL_LCD_STATE_ERROR = 0x04U /*!< Error */
}HAL_LCD_StateTypeDef;
/**
@ -136,12 +136,12 @@ typedef struct
/** @defgroup LCD_ErrorCode LCD Error Code
* @{
*/
#define HAL_LCD_ERROR_NONE ((uint32_t)0x00) /*!< No error */
#define HAL_LCD_ERROR_FCRSF ((uint32_t)0x01) /*!< Synchro flag timeout error */
#define HAL_LCD_ERROR_UDR ((uint32_t)0x02) /*!< Update display request flag timeout error */
#define HAL_LCD_ERROR_UDD ((uint32_t)0x04) /*!< Update display done flag timeout error */
#define HAL_LCD_ERROR_ENS ((uint32_t)0x08) /*!< LCD enabled status flag timeout error */
#define HAL_LCD_ERROR_RDY ((uint32_t)0x10) /*!< LCD Booster ready timeout error */
#define HAL_LCD_ERROR_NONE ((uint32_t)0x00U) /*!< No error */
#define HAL_LCD_ERROR_FCRSF ((uint32_t)0x01U) /*!< Synchro flag timeout error */
#define HAL_LCD_ERROR_UDR ((uint32_t)0x02U) /*!< Update display request flag timeout error */
#define HAL_LCD_ERROR_UDD ((uint32_t)0x04U) /*!< Update display done flag timeout error */
#define HAL_LCD_ERROR_ENS ((uint32_t)0x08U) /*!< LCD enabled status flag timeout error */
#define HAL_LCD_ERROR_RDY ((uint32_t)0x10U) /*!< LCD Booster ready timeout error */
/**
* @}
*/
@ -150,21 +150,21 @@ typedef struct
* @{
*/
#define LCD_PRESCALER_1 ((uint32_t)0x00000000) /*!< CLKPS = LCDCLK */
#define LCD_PRESCALER_2 ((uint32_t)0x00400000) /*!< CLKPS = LCDCLK/2 */
#define LCD_PRESCALER_4 ((uint32_t)0x00800000) /*!< CLKPS = LCDCLK/4 */
#define LCD_PRESCALER_8 ((uint32_t)0x00C00000) /*!< CLKPS = LCDCLK/8 */
#define LCD_PRESCALER_16 ((uint32_t)0x01000000) /*!< CLKPS = LCDCLK/16 */
#define LCD_PRESCALER_32 ((uint32_t)0x01400000) /*!< CLKPS = LCDCLK/32 */
#define LCD_PRESCALER_64 ((uint32_t)0x01800000) /*!< CLKPS = LCDCLK/64 */
#define LCD_PRESCALER_128 ((uint32_t)0x01C00000) /*!< CLKPS = LCDCLK/128 */
#define LCD_PRESCALER_256 ((uint32_t)0x02000000) /*!< CLKPS = LCDCLK/256 */
#define LCD_PRESCALER_512 ((uint32_t)0x02400000) /*!< CLKPS = LCDCLK/512 */
#define LCD_PRESCALER_1024 ((uint32_t)0x02800000) /*!< CLKPS = LCDCLK/1024 */
#define LCD_PRESCALER_2048 ((uint32_t)0x02C00000) /*!< CLKPS = LCDCLK/2048 */
#define LCD_PRESCALER_4096 ((uint32_t)0x03000000) /*!< CLKPS = LCDCLK/4096 */
#define LCD_PRESCALER_8192 ((uint32_t)0x03400000) /*!< CLKPS = LCDCLK/8192 */
#define LCD_PRESCALER_16384 ((uint32_t)0x03800000) /*!< CLKPS = LCDCLK/16384 */
#define LCD_PRESCALER_1 ((uint32_t)0x00000000U) /*!< CLKPS = LCDCLK */
#define LCD_PRESCALER_2 ((uint32_t)0x00400000U) /*!< CLKPS = LCDCLK/2 */
#define LCD_PRESCALER_4 ((uint32_t)0x00800000U) /*!< CLKPS = LCDCLK/4 */
#define LCD_PRESCALER_8 ((uint32_t)0x00C00000U) /*!< CLKPS = LCDCLK/8 */
#define LCD_PRESCALER_16 ((uint32_t)0x01000000U) /*!< CLKPS = LCDCLK/16 */
#define LCD_PRESCALER_32 ((uint32_t)0x01400000U) /*!< CLKPS = LCDCLK/32 */
#define LCD_PRESCALER_64 ((uint32_t)0x01800000U) /*!< CLKPS = LCDCLK/64 */
#define LCD_PRESCALER_128 ((uint32_t)0x01C00000U) /*!< CLKPS = LCDCLK/128 */
#define LCD_PRESCALER_256 ((uint32_t)0x02000000U) /*!< CLKPS = LCDCLK/256 */
#define LCD_PRESCALER_512 ((uint32_t)0x02400000U) /*!< CLKPS = LCDCLK/512 */
#define LCD_PRESCALER_1024 ((uint32_t)0x02800000U) /*!< CLKPS = LCDCLK/1024 */
#define LCD_PRESCALER_2048 ((uint32_t)0x02C00000U) /*!< CLKPS = LCDCLK/2048 */
#define LCD_PRESCALER_4096 ((uint32_t)0x03000000U) /*!< CLKPS = LCDCLK/4096 */
#define LCD_PRESCALER_8192 ((uint32_t)0x03400000U) /*!< CLKPS = LCDCLK/8192 */
#define LCD_PRESCALER_16384 ((uint32_t)0x03800000U) /*!< CLKPS = LCDCLK/16384 */
#define LCD_PRESCALER_32768 ((uint32_t)LCD_FCR_PS) /*!< CLKPS = LCDCLK/32768 */
#define IS_LCD_PRESCALER(__PRESCALER__) (((__PRESCALER__) == LCD_PRESCALER_1) || \
@ -192,21 +192,21 @@ typedef struct
* @{
*/
#define LCD_DIVIDER_16 ((uint32_t)0x00000000) /*!< LCD frequency = CLKPS/16 */
#define LCD_DIVIDER_17 ((uint32_t)0x00040000) /*!< LCD frequency = CLKPS/17 */
#define LCD_DIVIDER_18 ((uint32_t)0x00080000) /*!< LCD frequency = CLKPS/18 */
#define LCD_DIVIDER_19 ((uint32_t)0x000C0000) /*!< LCD frequency = CLKPS/19 */
#define LCD_DIVIDER_20 ((uint32_t)0x00100000) /*!< LCD frequency = CLKPS/20 */
#define LCD_DIVIDER_21 ((uint32_t)0x00140000) /*!< LCD frequency = CLKPS/21 */
#define LCD_DIVIDER_22 ((uint32_t)0x00180000) /*!< LCD frequency = CLKPS/22 */
#define LCD_DIVIDER_23 ((uint32_t)0x001C0000) /*!< LCD frequency = CLKPS/23 */
#define LCD_DIVIDER_24 ((uint32_t)0x00200000) /*!< LCD frequency = CLKPS/24 */
#define LCD_DIVIDER_25 ((uint32_t)0x00240000) /*!< LCD frequency = CLKPS/25 */
#define LCD_DIVIDER_26 ((uint32_t)0x00280000) /*!< LCD frequency = CLKPS/26 */
#define LCD_DIVIDER_27 ((uint32_t)0x002C0000) /*!< LCD frequency = CLKPS/27 */
#define LCD_DIVIDER_28 ((uint32_t)0x00300000) /*!< LCD frequency = CLKPS/28 */
#define LCD_DIVIDER_29 ((uint32_t)0x00340000) /*!< LCD frequency = CLKPS/29 */
#define LCD_DIVIDER_30 ((uint32_t)0x00380000) /*!< LCD frequency = CLKPS/30 */
#define LCD_DIVIDER_16 ((uint32_t)0x00000000U) /*!< LCD frequency = CLKPS/16 */
#define LCD_DIVIDER_17 ((uint32_t)0x00040000U) /*!< LCD frequency = CLKPS/17 */
#define LCD_DIVIDER_18 ((uint32_t)0x00080000U) /*!< LCD frequency = CLKPS/18 */
#define LCD_DIVIDER_19 ((uint32_t)0x000C0000U) /*!< LCD frequency = CLKPS/19 */
#define LCD_DIVIDER_20 ((uint32_t)0x00100000U) /*!< LCD frequency = CLKPS/20 */
#define LCD_DIVIDER_21 ((uint32_t)0x00140000U) /*!< LCD frequency = CLKPS/21 */
#define LCD_DIVIDER_22 ((uint32_t)0x00180000U) /*!< LCD frequency = CLKPS/22 */
#define LCD_DIVIDER_23 ((uint32_t)0x001C0000U) /*!< LCD frequency = CLKPS/23 */
#define LCD_DIVIDER_24 ((uint32_t)0x00200000U) /*!< LCD frequency = CLKPS/24 */
#define LCD_DIVIDER_25 ((uint32_t)0x00240000U) /*!< LCD frequency = CLKPS/25 */
#define LCD_DIVIDER_26 ((uint32_t)0x00280000U) /*!< LCD frequency = CLKPS/26 */
#define LCD_DIVIDER_27 ((uint32_t)0x002C0000U) /*!< LCD frequency = CLKPS/27 */
#define LCD_DIVIDER_28 ((uint32_t)0x00300000U) /*!< LCD frequency = CLKPS/28 */
#define LCD_DIVIDER_29 ((uint32_t)0x00340000U) /*!< LCD frequency = CLKPS/29 */
#define LCD_DIVIDER_30 ((uint32_t)0x00380000U) /*!< LCD frequency = CLKPS/30 */
#define LCD_DIVIDER_31 ((uint32_t)LCD_FCR_DIV) /*!< LCD frequency = CLKPS/31 */
#define IS_LCD_DIVIDER(__DIVIDER__) (((__DIVIDER__) == LCD_DIVIDER_16) || \
@ -235,7 +235,7 @@ typedef struct
* @{
*/
#define LCD_DUTY_STATIC ((uint32_t)0x00000000) /*!< Static duty */
#define LCD_DUTY_STATIC ((uint32_t)0x00000000U) /*!< Static duty */
#define LCD_DUTY_1_2 (LCD_CR_DUTY_0) /*!< 1/2 duty */
#define LCD_DUTY_1_3 (LCD_CR_DUTY_1) /*!< 1/3 duty */
#define LCD_DUTY_1_4 ((LCD_CR_DUTY_1 | LCD_CR_DUTY_0)) /*!< 1/4 duty */
@ -256,7 +256,7 @@ typedef struct
* @{
*/
#define LCD_BIAS_1_4 ((uint32_t)0x00000000) /*!< 1/4 Bias */
#define LCD_BIAS_1_4 ((uint32_t)0x00000000U) /*!< 1/4 Bias */
#define LCD_BIAS_1_2 LCD_CR_BIAS_0 /*!< 1/2 Bias */
#define LCD_BIAS_1_3 LCD_CR_BIAS_1 /*!< 1/3 Bias */
@ -271,7 +271,7 @@ typedef struct
* @{
*/
#define LCD_VOLTAGESOURCE_INTERNAL ((uint32_t)0x00000000) /*!< Internal voltage source for the LCD */
#define LCD_VOLTAGESOURCE_INTERNAL ((uint32_t)0x00000000U) /*!< Internal voltage source for the LCD */
#define LCD_VOLTAGESOURCE_EXTERNAL LCD_CR_VSEL /*!< External voltage source for the LCD */
#define IS_LCD_VOLTAGE_SOURCE(SOURCE) (((SOURCE) == LCD_VOLTAGESOURCE_INTERNAL) || \
@ -295,7 +295,7 @@ typedef struct
* @{
*/
#define LCD_PULSEONDURATION_0 ((uint32_t)0x00000000) /*!< Pulse ON duration = 0 pulse */
#define LCD_PULSEONDURATION_0 ((uint32_t)0x00000000U) /*!< Pulse ON duration = 0 pulse */
#define LCD_PULSEONDURATION_1 (LCD_FCR_PON_0) /*!< Pulse ON duration = 1/CK_PS */
#define LCD_PULSEONDURATION_2 (LCD_FCR_PON_1) /*!< Pulse ON duration = 2/CK_PS */
#define LCD_PULSEONDURATION_3 (LCD_FCR_PON_1 | LCD_FCR_PON_0) /*!< Pulse ON duration = 3/CK_PS */
@ -320,7 +320,7 @@ typedef struct
* @{
*/
#define LCD_HIGHDRIVE_0 ((uint32_t)0x00000000) /*!< Low resistance Drive */
#define LCD_HIGHDRIVE_0 ((uint32_t)0x00000000U) /*!< Low resistance Drive */
#define LCD_HIGHDRIVE_1 (LCD_FCR_HD) /*!< High resistance Drive */
#define IS_LCD_HIGHDRIVE(__HIGHDRIVE__) (((__HIGHDRIVE__) == LCD_HIGHDRIVE_0) || \
@ -333,7 +333,7 @@ typedef struct
* @{
*/
#define LCD_DEADTIME_0 ((uint32_t)0x00000000) /*!< No dead Time */
#define LCD_DEADTIME_0 ((uint32_t)0x00000000U) /*!< No dead Time */
#define LCD_DEADTIME_1 (LCD_FCR_DEAD_0) /*!< One Phase between different couple of Frame */
#define LCD_DEADTIME_2 (LCD_FCR_DEAD_1) /*!< Two Phase between different couple of Frame */
#define LCD_DEADTIME_3 (LCD_FCR_DEAD_1 | LCD_FCR_DEAD_0) /*!< Three Phase between different couple of Frame */
@ -358,7 +358,7 @@ typedef struct
* @{
*/
#define LCD_BLINKMODE_OFF ((uint32_t)0x00000000) /*!< Blink disabled */
#define LCD_BLINKMODE_OFF ((uint32_t)0x00000000U) /*!< Blink disabled */
#define LCD_BLINKMODE_SEG0_COM0 (LCD_FCR_BLINK_0) /*!< Blink enabled on SEG[0], COM[0] (1 pixel) */
#define LCD_BLINKMODE_SEG0_ALLCOM (LCD_FCR_BLINK_1) /*!< Blink enabled on SEG[0], all COM (up to
8 pixels according to the programmed duty) */
@ -376,7 +376,7 @@ typedef struct
* @{
*/
#define LCD_BLINKFREQUENCY_DIV8 ((uint32_t)0x00000000) /*!< The Blink frequency = fLCD/8 */
#define LCD_BLINKFREQUENCY_DIV8 ((uint32_t)0x00000000U) /*!< The Blink frequency = fLCD/8 */
#define LCD_BLINKFREQUENCY_DIV16 (LCD_FCR_BLINKF_0) /*!< The Blink frequency = fLCD/16 */
#define LCD_BLINKFREQUENCY_DIV32 (LCD_FCR_BLINKF_1) /*!< The Blink frequency = fLCD/32 */
#define LCD_BLINKFREQUENCY_DIV64 (LCD_FCR_BLINKF_1 | LCD_FCR_BLINKF_0) /*!< The Blink frequency = fLCD/64 */
@ -401,7 +401,7 @@ typedef struct
* @{
*/
#define LCD_CONTRASTLEVEL_0 ((uint32_t)0x00000000) /*!< Maximum Voltage = 2.60V */
#define LCD_CONTRASTLEVEL_0 ((uint32_t)0x00000000U) /*!< Maximum Voltage = 2.60V */
#define LCD_CONTRASTLEVEL_1 (LCD_FCR_CC_0) /*!< Maximum Voltage = 2.73V */
#define LCD_CONTRASTLEVEL_2 (LCD_FCR_CC_1) /*!< Maximum Voltage = 2.86V */
#define LCD_CONTRASTLEVEL_3 (LCD_FCR_CC_1 | LCD_FCR_CC_0) /*!< Maximum Voltage = 2.99V */
@ -426,7 +426,7 @@ typedef struct
* @{
*/
#define LCD_MUXSEGMENT_DISABLE ((uint32_t)0x00000000) /*!< SEG pin multiplexing disabled */
#define LCD_MUXSEGMENT_DISABLE ((uint32_t)0x00000000U) /*!< SEG pin multiplexing disabled */
#define LCD_MUXSEGMENT_ENABLE (LCD_CR_MUX_SEG) /*!< SEG[31:28] are multiplexed with SEG[43:40] */
#define IS_LCD_MUXSEGMENT(__VALUE__) (((__VALUE__) == LCD_MUXSEGMENT_ENABLE) || \
@ -435,6 +435,19 @@ typedef struct
* @}
*/
/** @defgroup LCD_BUFEN LCD Voltage output buffer enable
* @{
*/
#define LCD_VOLTBUFOUT_DISABLE ((uint32_t)0x00000000U) /*!< Voltage output buffer disabled */
#define LCD_VOLTBUFOUT_ENABLE (LCD_CR_BUFEN) /*!< BUFEN[1] Voltage output buffer enabled */
#define IS_LCD_VOLTBUFOUT(__VALUE__) (((__VALUE__) == LCD_VOLTBUFOUT_ENABLE) || \
((__VALUE__) == LCD_VOLTBUFOUT_DISABLE))
/**
* @}
*/
/** @defgroup LCD_Flag LCD Flag
* @{
*/
@ -454,22 +467,22 @@ typedef struct
* @{
*/
#define LCD_RAM_REGISTER0 ((uint32_t)0x00000000) /*!< LCD RAM Register 0 */
#define LCD_RAM_REGISTER1 ((uint32_t)0x00000001) /*!< LCD RAM Register 1 */
#define LCD_RAM_REGISTER2 ((uint32_t)0x00000002) /*!< LCD RAM Register 2 */
#define LCD_RAM_REGISTER3 ((uint32_t)0x00000003) /*!< LCD RAM Register 3 */
#define LCD_RAM_REGISTER4 ((uint32_t)0x00000004) /*!< LCD RAM Register 4 */
#define LCD_RAM_REGISTER5 ((uint32_t)0x00000005) /*!< LCD RAM Register 5 */
#define LCD_RAM_REGISTER6 ((uint32_t)0x00000006) /*!< LCD RAM Register 6 */
#define LCD_RAM_REGISTER7 ((uint32_t)0x00000007) /*!< LCD RAM Register 7 */
#define LCD_RAM_REGISTER8 ((uint32_t)0x00000008) /*!< LCD RAM Register 8 */
#define LCD_RAM_REGISTER9 ((uint32_t)0x00000009) /*!< LCD RAM Register 9 */
#define LCD_RAM_REGISTER10 ((uint32_t)0x0000000A) /*!< LCD RAM Register 10 */
#define LCD_RAM_REGISTER11 ((uint32_t)0x0000000B) /*!< LCD RAM Register 11 */
#define LCD_RAM_REGISTER12 ((uint32_t)0x0000000C) /*!< LCD RAM Register 12 */
#define LCD_RAM_REGISTER13 ((uint32_t)0x0000000D) /*!< LCD RAM Register 13 */
#define LCD_RAM_REGISTER14 ((uint32_t)0x0000000E) /*!< LCD RAM Register 14 */
#define LCD_RAM_REGISTER15 ((uint32_t)0x0000000F) /*!< LCD RAM Register 15 */
#define LCD_RAM_REGISTER0 ((uint32_t)0x00000000U) /*!< LCD RAM Register 0 */
#define LCD_RAM_REGISTER1 ((uint32_t)0x00000001U) /*!< LCD RAM Register 1 */
#define LCD_RAM_REGISTER2 ((uint32_t)0x00000002U) /*!< LCD RAM Register 2 */
#define LCD_RAM_REGISTER3 ((uint32_t)0x00000003U) /*!< LCD RAM Register 3 */
#define LCD_RAM_REGISTER4 ((uint32_t)0x00000004U) /*!< LCD RAM Register 4 */
#define LCD_RAM_REGISTER5 ((uint32_t)0x00000005U) /*!< LCD RAM Register 5 */
#define LCD_RAM_REGISTER6 ((uint32_t)0x00000006U) /*!< LCD RAM Register 6 */
#define LCD_RAM_REGISTER7 ((uint32_t)0x00000007U) /*!< LCD RAM Register 7 */
#define LCD_RAM_REGISTER8 ((uint32_t)0x00000008U) /*!< LCD RAM Register 8 */
#define LCD_RAM_REGISTER9 ((uint32_t)0x00000009U) /*!< LCD RAM Register 9 */
#define LCD_RAM_REGISTER10 ((uint32_t)0x0000000AU) /*!< LCD RAM Register 10 */
#define LCD_RAM_REGISTER11 ((uint32_t)0x0000000BU) /*!< LCD RAM Register 11 */
#define LCD_RAM_REGISTER12 ((uint32_t)0x0000000CU) /*!< LCD RAM Register 12 */
#define LCD_RAM_REGISTER13 ((uint32_t)0x0000000DU) /*!< LCD RAM Register 13 */
#define LCD_RAM_REGISTER14 ((uint32_t)0x0000000EU) /*!< LCD RAM Register 14 */
#define LCD_RAM_REGISTER15 ((uint32_t)0x0000000FU) /*!< LCD RAM Register 15 */
#define IS_LCD_RAM_REGISTER(__REGISTER__) (((__REGISTER__) == LCD_RAM_REGISTER0) || \
((__REGISTER__) == LCD_RAM_REGISTER1) || \
@ -515,6 +528,13 @@ typedef struct
#define __HAL_LCD_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR, LCD_CR_LCDEN))
#define __HAL_LCD_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR, LCD_CR_LCDEN))
/** @brief macros to enables or disables the Voltage output buffer
* @param __HANDLE__: specifies the LCD Handle.
* @retval None
*/
#define __HAL_LCD_VOLTOUTBUFFER_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR, LCD_CR_BUFEN))
#define __HAL_LCD_VOLTOUTBUFFER_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR, LCD_CR_BUFEN))
/** @brief Macros to enable or disable the low resistance divider. Displays with high
* internal resistance may need a longer drive time to achieve
* satisfactory contrast. This function is useful in this case if some

36
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_lptim.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx_hal_lptim.c
* @author MCD Application Team
* @version V1.5.0
* @date 8-January-2016
* @version V1.7.0
* @date 31-May-2016
* @brief LPTIM HAL module driver.
*
* This file provides firmware functions to manage the following
@ -165,7 +165,7 @@
*/
HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim)
{
uint32_t tmpcfgr = 0;
uint32_t tmpcfgr = 0U;
/* Check the LPTIM handle allocation */
if(hlptim == NULL)
@ -851,7 +851,7 @@ HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT(LPTIM_HandleTypeDef *hlptim)
*/
HAL_StatusTypeDef HAL_LPTIM_Encoder_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period)
{
uint32_t tmpcfgr = 0;
uint32_t tmpcfgr = 0U;
/* Check the parameters */
assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
@ -930,7 +930,7 @@ HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop(LPTIM_HandleTypeDef *hlptim)
*/
HAL_StatusTypeDef HAL_LPTIM_Encoder_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period)
{
uint32_t tmpcfgr = 0;
uint32_t tmpcfgr = 0U;
/* Check the parameters */
assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
@ -1102,6 +1102,12 @@ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32
/* Set the LPTIM state */
hlptim->State= HAL_LPTIM_STATE_BUSY;
/* Enable EXTI Line interrupt on the LPTIM Wake-up Timer */
__HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT();
/* Enable rising edge trigger on the LPTIM Wake-up Timer Exti line */
__HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();
/* Set TIMOUT bit to enable the timeout function */
hlptim->Instance->CFGR |= LPTIM_CFGR_TIMOUT;
@ -1140,6 +1146,12 @@ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim)
/* Set the LPTIM state */
hlptim->State= HAL_LPTIM_STATE_BUSY;
/* Disable rising edge trigger on the LPTIM Wake-up Timer Exti line */
__HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE();
/* Disable EXTI Line interrupt on the LPTIM Wake-up Timer */
__HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT();
/* Disable the Peripheral */
__HAL_LPTIM_DISABLE(hlptim);
@ -1236,6 +1248,12 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32
/* Set the LPTIM state */
hlptim->State= HAL_LPTIM_STATE_BUSY;
/* Enable EXTI Line interrupt on the LPTIM Wake-up Timer */
__HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT();
/* Enable rising edge trigger on the LPTIM Wake-up Timer Exti line */
__HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();
/* If clock source is not ULPTIM clock and counter source is external, then it must not be prescaled */
if((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM) && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
{
@ -1280,6 +1298,12 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim)
/* Set the LPTIM state */
hlptim->State= HAL_LPTIM_STATE_BUSY;
/* Disable rising edge trigger on the LPTIM Wake-up Timer Exti line */
__HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE();
/* Disable EXTI Line interrupt on the LPTIM Wake-up Timer */
__HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT();
/* Disable the Peripheral */
__HAL_LPTIM_DISABLE(hlptim);
@ -1470,6 +1494,8 @@ void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim)
HAL_LPTIM_DirectionDownCallback(hlptim);
}
}
__HAL_LPTIM_WAKEUPTIMER_EXTI_CLEAR_FLAG();
}
/**

124
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_lptim.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx_hal_lptim.h
* @author MCD Application Team
* @version V1.5.0
* @date 8-January-2016
* @version V1.7.0
* @date 31-May-2016
* @brief Header file of LPTIM HAL module.
******************************************************************************
* @attention
@ -62,6 +62,8 @@
/** @defgroup LPTIM_Clock_Configuration LPTIM Clock configuration structure
* @{
*/
#define LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT ((uint32_t)EXTI_IMR_IM29) /*!< External interrupt line 29 Connected to the LPTIM EXTI Line */
/**
* @brief LPTIM Clock configuration definition
*/
@ -111,7 +113,7 @@ typedef struct
typedef struct
{
uint32_t Source; /*!< Selects the Trigger source.
This parameter can be a value of @ref LPTIM_Trigger_Source */
This parameter can be a value of @ref LPTIMEx_Trigger_Source */
uint32_t ActiveEdge; /*!< Selects the Trigger active edge.
Note: This parameter is used only when an external trigger is used.
@ -162,11 +164,11 @@ typedef struct
*/
typedef enum __HAL_LPTIM_StateTypeDef
{
HAL_LPTIM_STATE_RESET = 0x00, /*!< Peripheral not yet initialized or disabled */
HAL_LPTIM_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
HAL_LPTIM_STATE_BUSY = 0x02, /*!< An internal process is ongoing */
HAL_LPTIM_STATE_TIMEOUT = 0x03, /*!< Timeout state */
HAL_LPTIM_STATE_ERROR = 0x04 /*!< Internal Process is ongoing */
HAL_LPTIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */
HAL_LPTIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
HAL_LPTIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */
HAL_LPTIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
HAL_LPTIM_STATE_ERROR = 0x04U /*!< Internal Process is ongoing */
}HAL_LPTIM_StateTypeDef;
/**
* @}
@ -206,15 +208,15 @@ typedef struct
*/
/* Check autoreload value */
#define IS_LPTIM_AUTORELOAD(__AUTORELOAD__) ((__AUTORELOAD__) <= 0x0000FFFF)
#define IS_LPTIM_AUTORELOAD(__AUTORELOAD__) ((__AUTORELOAD__) <= 0x0000FFFFU)
/* Check compare value */
#define IS_LPTIM_COMPARE(__COMPARE__) ((__COMPARE__) <= 0x0000FFFF)
#define IS_LPTIM_COMPARE(__COMPARE__) ((__COMPARE__) <= 0x0000FFFFU)
/** @defgroup LPTIM_Clock_Source Clock source
* @{
*/
#define LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC ((uint32_t)0x00)
#define LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC ((uint32_t)0x00U)
#define LPTIM_CLOCKSOURCE_ULPTIM LPTIM_CFGR_CKSEL
/**
* @}
@ -226,7 +228,7 @@ typedef struct
/** @defgroup LPTIM_Clock_Prescaler Prescaler
* @{
*/
#define LPTIM_PRESCALER_DIV1 ((uint32_t)0x000000)
#define LPTIM_PRESCALER_DIV1 ((uint32_t)0x000000U)
#define LPTIM_PRESCALER_DIV2 LPTIM_CFGR_PRESC_0
#define LPTIM_PRESCALER_DIV4 LPTIM_CFGR_PRESC_1
#define LPTIM_PRESCALER_DIV8 ((uint32_t)(LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_1))
@ -253,7 +255,7 @@ typedef struct
/** @defgroup LPTIM_Output_Polarity Output polarity
* @{
*/
#define LPTIM_OUTPUTPOLARITY_HIGH ((uint32_t)0x00000000)
#define LPTIM_OUTPUTPOLARITY_HIGH ((uint32_t)0x00000000U)
#define LPTIM_OUTPUTPOLARITY_LOW (LPTIM_CFGR_WAVPOL)
/**
* @}
@ -264,7 +266,7 @@ typedef struct
/** @defgroup LPTIM_Clock_Sample_Time Clock sample time
* @{
*/
#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION ((uint32_t)0x00000000)
#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION ((uint32_t)0x00000000U)
#define LPTIM_CLOCKSAMPLETIME_2TRANSITIONS LPTIM_CFGR_CKFLT_0
#define LPTIM_CLOCKSAMPLETIME_4TRANSITIONS LPTIM_CFGR_CKFLT_1
#define LPTIM_CLOCKSAMPLETIME_8TRANSITIONS LPTIM_CFGR_CKFLT
@ -279,7 +281,7 @@ typedef struct
/** @defgroup LPTIM_Clock_Polarity Clock polarity
* @{
*/
#define LPTIM_CLOCKPOLARITY_RISING ((uint32_t)0x00000000)
#define LPTIM_CLOCKPOLARITY_RISING ((uint32_t)0x00000000U)
#define LPTIM_CLOCKPOLARITY_FALLING LPTIM_CFGR_CKPOL_0
#define LPTIM_CLOCKPOLARITY_RISING_FALLING LPTIM_CFGR_CKPOL_1
/**
@ -306,7 +308,7 @@ typedef struct
/** @defgroup LPTIM_Trigger_Sample_Time Trigger sample time
* @{
*/
#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION ((uint32_t)0x00000000)
#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION ((uint32_t)0x00000000U)
#define LPTIM_TRIGSAMPLETIME_2TRANSITIONS LPTIM_CFGR_TRGFLT_0
#define LPTIM_TRIGSAMPLETIME_4TRANSITIONS LPTIM_CFGR_TRGFLT_1
#define LPTIM_TRIGSAMPLETIME_8TRANSITIONS LPTIM_CFGR_TRGFLT
@ -323,7 +325,7 @@ typedef struct
* @{
*/
#define LPTIM_UPDATE_IMMEDIATE ((uint32_t)0x00000000)
#define LPTIM_UPDATE_IMMEDIATE ((uint32_t)0x00000000U)
#define LPTIM_UPDATE_ENDOFPERIOD LPTIM_CFGR_PRELOAD
/**
* @}
@ -336,7 +338,7 @@ typedef struct
/** @defgroup LPTIM_Counter_Source Counter source
* @{
*/
#define LPTIM_COUNTERSOURCE_INTERNAL ((uint32_t)0x00000000)
#define LPTIM_COUNTERSOURCE_INTERNAL ((uint32_t)0x00000000U)
#define LPTIM_COUNTERSOURCE_EXTERNAL LPTIM_CFGR_COUNTMODE
/**
* @}
@ -347,10 +349,10 @@ typedef struct
/* Check for period value */
#define IS_LPTIM_PERIOD(__PERIOD__) ((__PERIOD__) <= 0x0000FFFF)
#define IS_LPTIM_PERIOD(__PERIOD__) ((__PERIOD__) <= 0x0000FFFFU)
/* Check for pulse value */
#define IS_LPTIM_PULSE(__PULSE__) ((__PULSE__) <= 0x0000FFFF)
#define IS_LPTIM_PULSE(__PULSE__) ((__PULSE__) <= 0x0000FFFFU)
/** @defgroup LPTIM_Flag_Definition Flag definition
* @{
@ -510,6 +512,88 @@ typedef struct
#define __HAL_LPTIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
/**
* @brief Enable interrupt on the LPTIM Wake-up Timer associated Exti line.
* @retval None
*/
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT() (EXTI->IMR |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
/**
* @brief Disable interrupt on the LPTIM Wake-up Timer associated Exti line.
* @retval None
*/
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT() (EXTI->IMR &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT))
/**
* @brief Enable event on the LPTIM Wake-up Timer associated Exti line.
* @retval None.
*/
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_EVENT() (EXTI->EMR |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
/**
* @brief Disable event on the LPTIM Wake-up Timer associated Exti line.
* @retval None.
*/
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT))
/**
* @brief Enable falling edge trigger on the LPTIM Wake-up Timer associated Exti line.
* @retval None.
*/
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
/**
* @brief Disable falling edge trigger on the LPTIM Wake-up Timer associated Exti line.
* @retval None.
*/
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT))
/**
* @brief Enable rising edge trigger on the LPTIM Wake-up Timer associated Exti line.
* @retval None.
*/
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
/**
* @brief Disable rising edge trigger on the LPTIM Wake-up Timer associated Exti line.
* @retval None.
*/
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT))
/**
* @brief Enable rising & falling edge trigger on the LPTIM Wake-up Timer associated Exti line.
* @retval None.
*/
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE() do{__HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();\
__HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE();\
}while(0)
/**
* @brief Disable rising & falling edge trigger on the LPTIM Wake-up Timer associated Exti line.
* @retval None.
*/
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE() do{__HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE();\
__HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE();\
}while(0)
/**
* @brief Check whether the LPTIM Wake-up Timer associated Exti line interrupt flag is set or not.
* @retval Line Status.
*/
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_GET_FLAG() (EXTI->PR & LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
/**
* @brief Clear the LPTIM Wake-up Timer associated Exti line flag.
* @retval None.
*/
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_CLEAR_FLAG() (EXTI->PR = LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
/**
* @brief Generate a Software interrupt on the LPTIM Wake-up Timer associated Exti line.
* @retval None.
*/
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_GENERATE_SWIT() (EXTI->SWIER |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
/**
* @}
*/

10
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_lptim_ex.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx_hal_lptim_ex.h
* @author MCD Application Team
* @version V1.5.0
* @date 8-January-2016
* @version V1.7.0
* @date 31-May-2016
* @brief Header file of LPTIM Extended HAL module.
******************************************************************************
* @attention
@ -61,11 +61,11 @@
*/
/** @defgroup LPTIM_Trigger_Source Trigger source
/** @defgroup LPTIMEx_Trigger_Source Trigger source
* @{
*/
#define LPTIM_TRIGSOURCE_SOFTWARE ((uint32_t)0x0000FFFF)
#define LPTIM_TRIGSOURCE_0 ((uint32_t)0x00000000)
#define LPTIM_TRIGSOURCE_SOFTWARE ((uint32_t)0x0000FFFFU)
#define LPTIM_TRIGSOURCE_0 ((uint32_t)0x00000000U)
#define LPTIM_TRIGSOURCE_1 ((uint32_t)LPTIM_CFGR_TRIGSEL_0)
#define LPTIM_TRIGSOURCE_2 LPTIM_CFGR_TRIGSEL_1
#define LPTIM_TRIGSOURCE_3 ((uint32_t)LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_1)

186
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_pcd.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx_hal_pcd.c
* @author MCD Application Team
* @version V1.5.0
* @date 8-January-2016
* @version V1.7.0
* @date 31-May-2016
* @brief PCD HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the USB Peripheral Controller:
@ -91,7 +91,7 @@
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
#define BTABLE_ADDRESS (0x000)
#define BTABLE_ADDRESS (0x000U)
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
@ -130,9 +130,9 @@ void PCD_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, ui
*/
HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
{
uint32_t i = 0;
uint32_t i = 0U;
uint32_t wInterrupt_Mask = 0;
uint32_t wInterrupt_Mask = 0U;
/* Check the PCD handle allocation */
if(hpcd == NULL)
@ -155,27 +155,27 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
hpcd->State = HAL_PCD_STATE_BUSY;
/* Init endpoints structures */
for (i = 0; i < hpcd->Init.dev_endpoints ; i++)
for (i = 0U; i < hpcd->Init.dev_endpoints ; i++)
{
/* Init ep structure */
hpcd->IN_ep[i].is_in = 1;
hpcd->IN_ep[i].is_in = 1U;
hpcd->IN_ep[i].num = i;
/* Control until ep is actvated */
hpcd->IN_ep[i].type = PCD_EP_TYPE_CTRL;
hpcd->IN_ep[i].maxpacket = 0;
hpcd->IN_ep[i].xfer_buff = 0;
hpcd->IN_ep[i].xfer_len = 0;
hpcd->IN_ep[i].maxpacket = 0U;
hpcd->IN_ep[i].xfer_buff = 0U;
hpcd->IN_ep[i].xfer_len = 0U;
}
for (i = 0; i < hpcd->Init.dev_endpoints ; i++)
for (i = 0U; i < hpcd->Init.dev_endpoints ; i++)
{
hpcd->OUT_ep[i].is_in = 0;
hpcd->OUT_ep[i].is_in = 0U;
hpcd->OUT_ep[i].num = i;
/* Control until ep is activated */
hpcd->OUT_ep[i].type = PCD_EP_TYPE_CTRL;
hpcd->OUT_ep[i].maxpacket = 0;
hpcd->OUT_ep[i].xfer_buff = 0;
hpcd->OUT_ep[i].xfer_len = 0;
hpcd->OUT_ep[i].maxpacket = 0U;
hpcd->OUT_ep[i].xfer_buff = 0U;
hpcd->OUT_ep[i].xfer_len = 0U;
}
/* Init Device */
@ -183,10 +183,10 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
hpcd->Instance->CNTR = USB_CNTR_FRES;
/*CNTR_FRES = 0*/
hpcd->Instance->CNTR = 0;
hpcd->Instance->CNTR = 0U;
/*Clear pending interrupts*/
hpcd->Instance->ISTR = 0;
hpcd->Instance->ISTR = 0U;
/*Set Btable Adress*/
hpcd->Instance->BTABLE = BTABLE_ADDRESS;
@ -198,7 +198,7 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
/*Set interrupt mask*/
hpcd->Instance->CNTR = wInterrupt_Mask;
hpcd->USB_Address = 0;
hpcd->USB_Address = 0U;
hpcd->State= HAL_PCD_STATE_READY;
return HAL_OK;
@ -305,7 +305,7 @@ HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd)
hpcd->Instance->CNTR = USB_CNTR_FRES;
/* clear interrupt status register */
hpcd->Instance->ISTR = 0;
hpcd->Instance->ISTR = 0U;
/* switch-off device */
hpcd->Instance->CNTR = (USB_CNTR_FRES | USB_CNTR_PDWN);
@ -321,7 +321,7 @@ HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd)
*/
void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
{
uint32_t wInterrupt_Mask = 0;
uint32_t wInterrupt_Mask = 0U;
if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_CTR))
{
@ -334,7 +334,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
{
__HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_RESET);
HAL_PCD_ResetCallback(hpcd);
HAL_PCD_SetAddress(hpcd, 0);
HAL_PCD_SetAddress(hpcd, 0U);
}
if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_PMAOVR))
@ -373,7 +373,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
hpcd->Instance->CNTR |= USB_CNTR_FSUSP;
hpcd->Instance->CNTR |= USB_CNTR_LPMODE;
if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_WKUP) == 0)
if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_WKUP) == 0U)
{
HAL_PCD_SuspendCallback(hpcd);
}
@ -626,7 +626,7 @@ HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address)
{
__HAL_LOCK(hpcd);
if(address == 0)
if(address == 0U)
{
/* set device address and enable function */
hpcd->Instance->DADDR = USB_DADDR_EF;
@ -652,17 +652,17 @@ HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint
HAL_StatusTypeDef ret = HAL_OK;
PCD_EPTypeDef *ep;
if ((ep_addr & 0x80) == 0x80)
if ((ep_addr & 0x80U) == 0x80U)
{
ep = &hpcd->IN_ep[ep_addr & 0x7F];
ep = &hpcd->IN_ep[ep_addr & 0x7FU];
}
else
{
ep = &hpcd->OUT_ep[ep_addr & 0x7F];
ep = &hpcd->OUT_ep[ep_addr & 0x7FU];
}
ep->num = ep_addr & 0x7F;
ep->num = ep_addr & 0x7FU;
ep->is_in = (0x80 & ep_addr) != 0;
ep->is_in = (0x80U & ep_addr) != 0U;
ep->maxpacket = ep_mps;
ep->type = ep_type;
@ -687,7 +687,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint
PCD_SET_EP_ADDRESS(hpcd->Instance, ep->num, ep->num);
if (ep->doublebuffer == 0)
if (ep->doublebuffer == 0U)
{
if (ep->is_in)
{
@ -716,7 +716,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint
/*Set buffer address for double buffered mode*/
PCD_SET_EP_DBUF_ADDR(hpcd->Instance, ep->num,ep->pmaaddr0, ep->pmaaddr1);
if (ep->is_in==0)
if (ep->is_in==0U)
{
/* Clear the data toggle bits for the endpoint IN/OUT*/
PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num);
@ -755,21 +755,21 @@ HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
{
PCD_EPTypeDef *ep;
if ((ep_addr & 0x80) == 0x80)
if ((ep_addr & 0x80U) == 0x80U)
{
ep = &hpcd->IN_ep[ep_addr & 0x7F];
ep = &hpcd->IN_ep[ep_addr & 0x7FU];
}
else
{
ep = &hpcd->OUT_ep[ep_addr & 0x7F];
ep = &hpcd->OUT_ep[ep_addr & 0x7FU];
}
ep->num = ep_addr & 0x7F;
ep->num = ep_addr & 0x7FU;
ep->is_in = (0x80 & ep_addr) != 0;
ep->is_in = (0x80U & ep_addr) != 0U;
__HAL_LOCK(hpcd);
if (ep->doublebuffer == 0)
if (ep->doublebuffer == 0U)
{
if (ep->is_in)
{
@ -787,7 +787,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
/*Double Buffer*/
else
{
if (ep->is_in==0)
if (ep->is_in==0U)
{
/* Clear the data toggle bits for the endpoint IN/OUT*/
PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num);
@ -829,14 +829,14 @@ HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, u
PCD_EPTypeDef *ep;
ep = &hpcd->OUT_ep[ep_addr & 0x7F];
ep = &hpcd->OUT_ep[ep_addr & 0x7FU];
/*setup and start the Xfer */
ep->xfer_buff = pBuf;
ep->xfer_len = len;
ep->xfer_count = 0;
ep->is_in = 0;
ep->num = ep_addr & 0x7F;
ep->xfer_count = 0U;
ep->is_in = 0U;
ep->num = ep_addr & 0x7FU;
__HAL_LOCK(hpcd);
@ -849,11 +849,11 @@ HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, u
else
{
len=ep->xfer_len;
ep->xfer_len =0;
ep->xfer_len =0U;
}
/* configure and validate Rx endpoint */
if (ep->doublebuffer == 0)
if (ep->doublebuffer == 0U)
{
/*Set RX buffer count*/
PCD_SET_EP_RX_CNT(hpcd->Instance, ep->num, len);
@ -879,7 +879,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, u
*/
uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
{
return hpcd->OUT_ep[ep_addr & 0x7F].xfer_count;
return hpcd->OUT_ep[ep_addr & 0x7FU].xfer_count;
}
/**
* @brief Send an amount of data
@ -892,16 +892,16 @@ uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
{
PCD_EPTypeDef *ep;
uint16_t pmabuffer = 0;
uint16_t pmabuffer = 0U;
ep = &hpcd->IN_ep[ep_addr & 0x7F];
ep = &hpcd->IN_ep[ep_addr & 0x7FU];
/*setup and start the Xfer */
ep->xfer_buff = pBuf;
ep->xfer_len = len;
ep->xfer_count = 0;
ep->is_in = 1;
ep->num = ep_addr & 0x7F;
ep->xfer_count = 0U;
ep->is_in = 1U;
ep->num = ep_addr & 0x7FU;
__HAL_LOCK(hpcd);
@ -914,11 +914,11 @@ HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
else
{
len=ep->xfer_len;
ep->xfer_len =0;
ep->xfer_len =0U;
}
/* configure and validate Tx endpoint */
if (ep->doublebuffer == 0)
if (ep->doublebuffer == 0U)
{
PCD_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, len);
PCD_SET_EP_TX_CNT(hpcd->Instance, ep->num, len);
@ -961,20 +961,20 @@ HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
__HAL_LOCK(hpcd);
if ((0x80 & ep_addr) == 0x80)
if ((0x80U & ep_addr) == 0x80U)
{
ep = &hpcd->IN_ep[ep_addr & 0x7F];
ep = &hpcd->IN_ep[ep_addr & 0x7FU];
}
else
{
ep = &hpcd->OUT_ep[ep_addr];
}
ep->is_stall = 1;
ep->num = ep_addr & 0x7F;
ep->is_in = ((ep_addr & 0x80) == 0x80);
ep->is_stall = 1U;
ep->num = ep_addr & 0x7FU;
ep->is_in = ((ep_addr & 0x80U) == 0x80U);
if (ep->num == 0)
if (ep->num == 0U)
{
/* This macro sets STALL status for RX & TX*/
PCD_SET_EP_TXRX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_STALL, USB_EP_TX_STALL);
@ -1005,18 +1005,18 @@ HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
{
PCD_EPTypeDef *ep;
if ((0x80 & ep_addr) == 0x80)
if ((0x80U & ep_addr) == 0x80U)
{
ep = &hpcd->IN_ep[ep_addr & 0x7F];
ep = &hpcd->IN_ep[ep_addr & 0x7FU];
}
else
{
ep = &hpcd->OUT_ep[ep_addr];
}
ep->is_stall = 0;
ep->num = ep_addr & 0x7F;
ep->is_in = ((ep_addr & 0x80) == 0x80);
ep->is_stall = 0U;
ep->num = ep_addr & 0x7FU;
ep->is_in = ((ep_addr & 0x80U) == 0x80U);
__HAL_LOCK(hpcd);
@ -1120,17 +1120,17 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd)
*/
void PCD_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
{
uint32_t n = (wNBytes + 1) >> 1;
uint32_t n = (wNBytes + 1U) >> 1U;
uint32_t i;
uint16_t temp1, temp2;
uint16_t *pdwVal;
pdwVal = (uint16_t *)(wPMABufAddr + (uint32_t)USBx + 0x400);
pdwVal = (uint16_t *)(wPMABufAddr + (uint32_t)USBx + 0x400U);
for (i = n; i != 0; i--)
for (i = n; i != 0U; i--)
{
temp1 = (uint16_t) * pbUsrBuf;
pbUsrBuf++;
temp2 = temp1 | (uint16_t) * pbUsrBuf << 8;
temp2 = temp1 | (uint16_t) * pbUsrBuf << 8U;
*pdwVal++ = temp2;
pbUsrBuf++;
}
@ -1146,11 +1146,11 @@ void PCD_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, u
*/
void PCD_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
{
uint32_t n = (wNBytes + 1) >> 1;
uint32_t n = (wNBytes + 1U) >> 1U;
uint32_t i;
uint16_t *pdwVal;
pdwVal = (uint16_t *)(wPMABufAddr + (uint32_t)USBx + 0x400);
for (i = n; i != 0; i--)
pdwVal = (uint16_t *)(wPMABufAddr + (uint32_t)USBx + 0x400U);
for (i = n; i != 0U; i--)
{
*(uint16_t*)pbUsrBuf++ = *pdwVal++;
pbUsrBuf++;
@ -1164,23 +1164,23 @@ void PCD_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, ui
static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd)
{
PCD_EPTypeDef *ep;
uint16_t count=0;
uint16_t count=0U;
uint8_t EPindex;
__IO uint16_t wIstr;
__IO uint16_t wEPVal = 0;
__IO uint16_t wEPVal = 0U;
/* stay in loop while pending interrupts */
while (((wIstr = hpcd->Instance->ISTR) & USB_ISTR_CTR) != 0)
while (((wIstr = hpcd->Instance->ISTR) & USB_ISTR_CTR) != 0U)
{
/* extract highest priority endpoint number */
EPindex = (uint8_t)(wIstr & USB_ISTR_EP_ID);
if (EPindex == 0)
if (EPindex == 0U)
{
/* Decode and service control endpoint interrupt */
/* DIR bit = origin of the interrupt */
if ((wIstr & USB_ISTR_DIR) == 0)
if ((wIstr & USB_ISTR_DIR) == 0U)
{
/* DIR = 0 */
@ -1193,13 +1193,13 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd)
ep->xfer_buff += ep->xfer_count;
/* TX COMPLETE */
HAL_PCD_DataInStageCallback(hpcd, 0);
HAL_PCD_DataInStageCallback(hpcd, 0U);
if((hpcd->USB_Address > 0)&& ( ep->xfer_len == 0))
if((hpcd->USB_Address > 0U)&& ( ep->xfer_len == 0U))
{
hpcd->Instance->DADDR = (hpcd->USB_Address | USB_DADDR_EF);
hpcd->USB_Address = 0;
hpcd->USB_Address = 0U;
}
}
@ -1212,7 +1212,7 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd)
ep = &hpcd->OUT_ep[0];
wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, PCD_ENDP0);
if ((wEPVal & USB_EP_SETUP) != 0)
if ((wEPVal & USB_EP_SETUP) != 0U)
{
/* Get SETUP Packet*/
ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
@ -1224,20 +1224,20 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd)
HAL_PCD_SetupStageCallback(hpcd);
}
else if ((wEPVal & USB_EP_CTR_RX) != 0)
else if ((wEPVal & USB_EP_CTR_RX) != 0U)
{
PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0);
/* Get Control Data OUT Packet*/
ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
if (ep->xfer_count != 0)
if (ep->xfer_count != 0U)
{
PCD_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, ep->xfer_count);
ep->xfer_buff+=ep->xfer_count;
}
/* Process Control Data OUT Packet*/
HAL_PCD_DataOutStageCallback(hpcd, 0);
HAL_PCD_DataOutStageCallback(hpcd, 0U);
PCD_SET_EP_RX_CNT(hpcd->Instance, PCD_ENDP0, ep->maxpacket);
PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID);
@ -1251,17 +1251,17 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd)
/* process related endpoint register */
wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, EPindex);
if ((wEPVal & USB_EP_CTR_RX) != 0)
if ((wEPVal & USB_EP_CTR_RX) != 0U)
{
/* clear int flag */
PCD_CLEAR_RX_EP_CTR(hpcd->Instance, EPindex);
ep = &hpcd->OUT_ep[EPindex];
/* OUT double Buffering*/
if (ep->doublebuffer == 0)
if (ep->doublebuffer == 0U)
{
count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
if (count != 0)
if (count != 0U)
{
PCD_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, count);
}
@ -1272,7 +1272,7 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd)
{
/*read from endpoint BUF0Addr buffer*/
count = PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num);
if (count != 0)
if (count != 0U)
{
PCD_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, count);
}
@ -1281,7 +1281,7 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd)
{
/*read from endpoint BUF1Addr buffer*/
count = PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num);
if (count != 0)
if (count != 0U)
{
PCD_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, count);
}
@ -1292,7 +1292,7 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd)
ep->xfer_count+=count;
ep->xfer_buff+=count;
if ((ep->xfer_len == 0) || (count < ep->maxpacket))
if ((ep->xfer_len == 0U) || (count < ep->maxpacket))
{
/* RX COMPLETE */
HAL_PCD_DataOutStageCallback(hpcd, ep->num);
@ -1304,7 +1304,7 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd)
} /* if((wEPVal & EP_CTR_RX) */
if ((wEPVal & USB_EP_CTR_TX) != 0)
if ((wEPVal & USB_EP_CTR_TX) != 0U)
{
ep = &hpcd->IN_ep[EPindex];
@ -1312,10 +1312,10 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd)
PCD_CLEAR_TX_EP_CTR(hpcd->Instance, EPindex);
/* IN double Buffering*/
if (ep->doublebuffer == 0)
if (ep->doublebuffer == 0U)
{
ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num);
if (ep->xfer_count != 0)
if (ep->xfer_count != 0U)
{
PCD_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, ep->xfer_count);
}
@ -1326,7 +1326,7 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd)
{
/*read from endpoint BUF0Addr buffer*/
ep->xfer_count = PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num);
if (ep->xfer_count != 0)
if (ep->xfer_count != 0U)
{
PCD_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, ep->xfer_count);
}
@ -1335,7 +1335,7 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd)
{
/*read from endpoint BUF1Addr buffer*/
ep->xfer_count = PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num);
if (ep->xfer_count != 0)
if (ep->xfer_count != 0U)
{
PCD_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, ep->xfer_count);
}
@ -1347,7 +1347,7 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd)
ep->xfer_buff+=ep->xfer_count;
/* Zero Length Packet? */
if (ep->xfer_len == 0)
if (ep->xfer_len == 0U)
{
/* TX COMPLETE */
HAL_PCD_DataInStageCallback(hpcd, ep->num);

104
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_pcd.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx_hal_pcd.h
* @author MCD Application Team
* @version V1.5.0
* @date 8-January-2016
* @version V1.7.0
* @date 31-May-2016
* @brief Header file of PCD HAL module.
******************************************************************************
* @attention
@ -67,11 +67,11 @@
*/
typedef enum
{
HAL_PCD_STATE_RESET = 0x00,
HAL_PCD_STATE_READY = 0x01,
HAL_PCD_STATE_ERROR = 0x02,
HAL_PCD_STATE_BUSY = 0x03,
HAL_PCD_STATE_TIMEOUT = 0x04
HAL_PCD_STATE_RESET = 0x00U,
HAL_PCD_STATE_READY = 0x01U,
HAL_PCD_STATE_ERROR = 0x02U,
HAL_PCD_STATE_BUSY = 0x03U,
HAL_PCD_STATE_TIMEOUT = 0x04U
} PCD_StateTypeDef;
typedef enum
@ -199,18 +199,18 @@ typedef struct
*/
#define PCD_ENDP0 ((uint8_t)0)
#define PCD_ENDP1 ((uint8_t)1)
#define PCD_ENDP2 ((uint8_t)2)
#define PCD_ENDP3 ((uint8_t)3)
#define PCD_ENDP4 ((uint8_t)4)
#define PCD_ENDP5 ((uint8_t)5)
#define PCD_ENDP6 ((uint8_t)6)
#define PCD_ENDP7 ((uint8_t)7)
#define PCD_ENDP0 ((uint8_t)0U)
#define PCD_ENDP1 ((uint8_t)1U)
#define PCD_ENDP2 ((uint8_t)2U)
#define PCD_ENDP3 ((uint8_t)3U)
#define PCD_ENDP4 ((uint8_t)4U)
#define PCD_ENDP5 ((uint8_t)5U)
#define PCD_ENDP6 ((uint8_t)6U)
#define PCD_ENDP7 ((uint8_t)7U)
/* Endpoint Kind */
#define PCD_SNG_BUF 0
#define PCD_DBL_BUF 1
#define PCD_SNG_BUF 0U
#define PCD_DBL_BUF 1U
#define IS_PCD_ALL_INSTANCE IS_USB_ALL_INSTANCE
@ -222,8 +222,8 @@ typedef struct
/** @defgroup PCD_Speed PCD Speed
* @{
*/
#define PCD_SPEED_HIGH 0 /* Not Supported */
#define PCD_SPEED_FULL 2
#define PCD_SPEED_HIGH 0U /* Not Supported */
#define PCD_SPEED_FULL 2U
/**
* @}
*/
@ -231,7 +231,7 @@ typedef struct
/** @defgroup PCD_USB_Core_PHY PCD USB Core PHY
* @{
*/
#define PCD_PHY_EMBEDDED 2
#define PCD_PHY_EMBEDDED 2U
/**
* @}
*/
@ -239,10 +239,10 @@ typedef struct
/** @defgroup PCD_USB_EP0_MPS PCD USB EP0 MPS
* @{
*/
#define DEP0CTL_MPS_64 0
#define DEP0CTL_MPS_32 1
#define DEP0CTL_MPS_16 2
#define DEP0CTL_MPS_8 3
#define DEP0CTL_MPS_64 0U
#define DEP0CTL_MPS_32 1U
#define DEP0CTL_MPS_16 2U
#define DEP0CTL_MPS_8 3U
#define PCD_EP0MPS_64 DEP0CTL_MPS_64
#define PCD_EP0MPS_32 DEP0CTL_MPS_32
@ -255,10 +255,10 @@ typedef struct
/** @defgroup PCD_USB_EP_Type PCD USB EP Type
* @{
*/
#define PCD_EP_TYPE_CTRL 0
#define PCD_EP_TYPE_ISOC 1
#define PCD_EP_TYPE_BULK 2
#define PCD_EP_TYPE_INTR 3
#define PCD_EP_TYPE_CTRL 0U
#define PCD_EP_TYPE_ISOC 1U
#define PCD_EP_TYPE_BULK 2U
#define PCD_EP_TYPE_INTR 3U
/**
* @}
*/
@ -282,10 +282,10 @@ typedef struct
/* Internal macros -----------------------------------------------------------*/
/* SetENDPOINT */
#define PCD_SET_ENDPOINT(USBx, bEpNum,wRegValue) (*(&USBx->EP0R + bEpNum * 2)= (uint16_t)wRegValue)
#define PCD_SET_ENDPOINT(USBx, bEpNum,wRegValue) (*(&USBx->EP0R + bEpNum * 2U)= (uint16_t)wRegValue)
/* GetENDPOINT */
#define PCD_GET_ENDPOINT(USBx, bEpNum) (*(&USBx->EP0R + bEpNum * 2))
#define PCD_GET_ENDPOINT(USBx, bEpNum) (*(&USBx->EP0R + bEpNum * 2U))
@ -336,9 +336,9 @@ do {\
*/
#define PCD_GET_DB_DIR(USBx, bEpNum)\
do {\
if ((uint16_t)(*PCD_EP_RX_CNT(USBx, bEpNum) & 0xFC00) != 0)\
if ((uint16_t)(*PCD_EP_RX_CNT(USBx, bEpNum) & 0xFC00U) != 0U)\
return(PCD_EP_DBUF_OUT);\
else if (((uint16_t)(*PCD_EP_TX_CNT(USBx, bEpNum)) & 0x03FF) != 0)\
else if (((uint16_t)(*PCD_EP_TX_CNT(USBx, bEpNum)) & 0x03FFU) != 0U)\
return(PCD_EP_DBUF_IN);\
else\
return(PCD_EP_DBUF_ERR);\
@ -356,10 +356,10 @@ do {\
\
_wRegVal = PCD_GET_ENDPOINT(USBx, bEpNum) & USB_EPTX_DTOGMASK;\
/* toggle first bit ? */ \
if((USB_EPTX_DTOG1 & wState)!= 0) \
if((USB_EPTX_DTOG1 & wState)!= 0U) \
_wRegVal ^= USB_EPTX_DTOG1; \
/* toggle second bit ? */ \
if((USB_EPTX_DTOG2 & wState)!= 0) \
if((USB_EPTX_DTOG2 & wState)!= 0U) \
_wRegVal ^= USB_EPTX_DTOG2; \
PCD_SET_ENDPOINT(USBx, bEpNum, (_wRegVal | USB_EP_CTR_RX|USB_EP_CTR_TX)); \
} while(0) /* PCD_SET_EP_TX_STATUS */
@ -376,10 +376,10 @@ do {\
\
_wRegVal = PCD_GET_ENDPOINT(USBx, bEpNum) & USB_EPRX_DTOGMASK;\
/* toggle first bit ? */ \
if((USB_EPRX_DTOG1 & wState)!= 0) \
if((USB_EPRX_DTOG1 & wState)!= 0U) \
_wRegVal ^= USB_EPRX_DTOG1; \
/* toggle second bit ? */ \
if((USB_EPRX_DTOG2 & wState)!= 0) \
if((USB_EPRX_DTOG2 & wState)!= 0U) \
_wRegVal ^= USB_EPRX_DTOG2; \
PCD_SET_ENDPOINT(USBx, bEpNum, (_wRegVal | USB_EP_CTR_RX|USB_EP_CTR_TX)); \
} while(0) /* PCD_SET_EP_RX_STATUS */
@ -397,16 +397,16 @@ do {\
\
_wRegVal = PCD_GET_ENDPOINT(USBx, bEpNum) & (USB_EPRX_DTOGMASK |USB_EPTX_STAT) ;\
/* toggle first bit ? */ \
if((USB_EPRX_DTOG1 & wStaterx)!= 0) \
if((USB_EPRX_DTOG1 & wStaterx)!= 0U) \
_wRegVal ^= USB_EPRX_DTOG1; \
/* toggle second bit ? */ \
if((USB_EPRX_DTOG2 & wStaterx)!= 0) \
if((USB_EPRX_DTOG2 & wStaterx)!= 0U) \
_wRegVal ^= USB_EPRX_DTOG2; \
/* toggle first bit ? */ \
if((USB_EPTX_DTOG1 & wStatetx)!= 0) \
if((USB_EPTX_DTOG1 & wStatetx)!= 0U) \
_wRegVal ^= USB_EPTX_DTOG1; \
/* toggle second bit ? */ \
if((USB_EPTX_DTOG2 & wStatetx)!= 0) \
if((USB_EPTX_DTOG2 & wStatetx)!= 0U) \
_wRegVal ^= USB_EPTX_DTOG2; \
PCD_SET_ENDPOINT(USBx, bEpNum, _wRegVal | USB_EP_CTR_RX|USB_EP_CTR_TX); \
} while(0) /* PCD_SET_EP_TXRX_STATUS */
@ -479,9 +479,9 @@ do {\
* @retval None
*/
#define PCD_CLEAR_RX_EP_CTR(USBx, bEpNum) (PCD_SET_ENDPOINT(USBx, bEpNum,\
PCD_GET_ENDPOINT(USBx, bEpNum) & 0x7FFF & USB_EPREG_MASK))
PCD_GET_ENDPOINT(USBx, bEpNum) & 0x7FFFU & USB_EPREG_MASK))
#define PCD_CLEAR_TX_EP_CTR(USBx, bEpNum) (PCD_SET_ENDPOINT(USBx, bEpNum,\
PCD_GET_ENDPOINT(USBx, bEpNum) & 0xFF7F & USB_EPREG_MASK))
PCD_GET_ENDPOINT(USBx, bEpNum) & 0xFF7FU & USB_EPREG_MASK))
/**
* @brief Toggles DTOG_RX / DTOG_TX bit in the endpoint register.
@ -522,10 +522,10 @@ do {\
* @retval None
*/
#define PCD_GET_EP_ADDRESS(USBx, bEpNum) ((uint8_t)(PCD_GET_ENDPOINT(USBx, bEpNum) & USB_EPADDR_FIELD))
#define PCD_EP_TX_ADDRESS(USBx, bEpNum) ((uint16_t *)((USBx->BTABLE+bEpNum*8)+ ((uint32_t)USBx + 0x400)))
#define PCD_EP_TX_CNT(USBx, bEpNum) ((uint16_t *)((USBx->BTABLE+bEpNum*8+2)+ ((uint32_t)USBx + 0x400)))
#define PCD_EP_RX_ADDRESS(USBx, bEpNum) ((uint16_t *)((USBx->BTABLE+bEpNum*8+4)+ ((uint32_t)USBx + 0x400)))
#define PCD_EP_RX_CNT(USBx, bEpNum) ((uint16_t *)((USBx->BTABLE+bEpNum*8+6)+ ((uint32_t)USBx + 0x400)))
#define PCD_EP_TX_ADDRESS(USBx, bEpNum) ((uint16_t *)((USBx->BTABLE+bEpNum*8U)+ ((uint32_t)USBx + 0x400U)))
#define PCD_EP_TX_CNT(USBx, bEpNum) ((uint16_t *)((USBx->BTABLE+bEpNum*8U+2U)+ ((uint32_t)USBx + 0x400U)))
#define PCD_EP_RX_ADDRESS(USBx, bEpNum) ((uint16_t *)((USBx->BTABLE+bEpNum*8U+4U)+ ((uint32_t)USBx + 0x400U)))
#define PCD_EP_RX_CNT(USBx, bEpNum) ((uint16_t *)((USBx->BTABLE+bEpNum*8U+6U)+ ((uint32_t)USBx + 0x400U)))
/**
* @brief sets address of the tx/rx buffer.
@ -534,8 +534,8 @@ do {\
* @param wAddr: address to be set (must be word aligned).
* @retval None
*/
#define PCD_SET_EP_TX_ADDRESS(USBx, bEpNum,wAddr) (*PCD_EP_TX_ADDRESS(USBx, bEpNum) = ((wAddr >> 1) << 1))
#define PCD_SET_EP_RX_ADDRESS(USBx, bEpNum,wAddr) (*PCD_EP_RX_ADDRESS(USBx, bEpNum) = ((wAddr >> 1) << 1))
#define PCD_SET_EP_TX_ADDRESS(USBx, bEpNum,wAddr) (*PCD_EP_TX_ADDRESS(USBx, bEpNum) = ((wAddr >> 1U) << 1U))
#define PCD_SET_EP_RX_ADDRESS(USBx, bEpNum,wAddr) (*PCD_EP_RX_ADDRESS(USBx, bEpNum) = ((wAddr >> 1U) << 1U))
/**
* @brief Gets address of the tx/rx buffer.
@ -557,14 +557,14 @@ do {\
wNBlocks = wCount >> 5;\
if((wCount & 0x1f) == 0)\
wNBlocks--;\
*pdwReg = (uint16_t)((wNBlocks << 10) | 0x8000);\
*pdwReg = (uint16_t)((wNBlocks << 10U) | 0x8000U);\
} while(0) /* PCD_CALC_BLK32 */
#define PCD_CALC_BLK2(dwReg,wCount,wNBlocks) do {\
wNBlocks = wCount >> 1;\
if((wCount & 0x1) != 0)\
wNBlocks++;\
*pdwReg = (uint16_t)(wNBlocks << 10);\
*pdwReg = (uint16_t)(wNBlocks << 10U);\
} while(0) /* PCD_CALC_BLK2 */
#define PCD_SET_EP_CNT_RX_REG(dwReg,wCount) do {\
@ -596,8 +596,8 @@ do {\
* @param bEpNum: Endpoint Number.
* @retval Counter value
*/
#define PCD_GET_EP_TX_CNT(USBx, bEpNum)((uint16_t)(*PCD_EP_TX_CNT(USBx, bEpNum)) & 0x3ff)
#define PCD_GET_EP_RX_CNT(USBx, bEpNum)((uint16_t)(*PCD_EP_RX_CNT(USBx, bEpNum)) & 0x3ff)
#define PCD_GET_EP_TX_CNT(USBx, bEpNum)((uint16_t)(*PCD_EP_TX_CNT(USBx, bEpNum)) & 0x3ffU)
#define PCD_GET_EP_RX_CNT(USBx, bEpNum)((uint16_t)(*PCD_EP_RX_CNT(USBx, bEpNum)) & 0x3ffU)
/**
* @brief Sets buffer 0/1 address in a double buffer endpoint.

16
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_pcd_ex.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx_hal_pcd_ex.c
* @author MCD Application Team
* @version V1.5.0
* @date 8-January-2016
* @version V1.7.0
* @date 31-May-2016
* @brief Extended PCD HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the USB Peripheral Controller:
@ -104,9 +104,9 @@ HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd,
PCD_EPTypeDef *ep;
/* initialize ep structure*/
if ((0x80 & ep_addr) == 0x80)
if ((0x80U & ep_addr) == 0x80U)
{
ep = &hpcd->IN_ep[ep_addr & 0x7F];
ep = &hpcd->IN_ep[ep_addr & 0x7FU];
}
else
{
@ -117,17 +117,17 @@ HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd,
if (ep_kind == PCD_SNG_BUF)
{
/*Single Buffer*/
ep->doublebuffer = 0;
ep->doublebuffer = 0U;
/*Configure te PMA*/
ep->pmaadress = (uint16_t)pmaadress;
}
else /*USB_DBL_BUF*/
{
/*Double Buffer Endpoint*/
ep->doublebuffer = 1;
ep->doublebuffer = 1U;
/*Configure the PMA*/
ep->pmaaddr0 = pmaadress & 0xFFFF;
ep->pmaaddr1 = (pmaadress & 0xFFFF0000) >> 16;
ep->pmaaddr0 = pmaadress & 0xFFFFU;
ep->pmaaddr1 = (pmaadress & 0xFFFF0000U) >> 16U;
}
return HAL_OK;

4
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_pcd_ex.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx_hal_pcd.h
* @author MCD Application Team
* @version V1.5.0
* @date 8-January-2016
* @version V1.7.0
* @date 31-May-2016
* @brief Header file of PCD HAL module.
******************************************************************************
* @attention

16
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_pwr.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx_hal_pwr.c
* @author MCD Application Team
* @version V1.5.0
* @date 8-January-2016
* @version V1.7.0
* @date 31-May-2016
* @brief PWR HAL module driver.
*
* This file provides firmware functions to manage the following
@ -60,10 +60,10 @@
/** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask
* @{
*/
#define PVD_MODE_IT ((uint32_t)0x00010000)
#define PVD_MODE_EVT ((uint32_t)0x00020000)
#define PVD_RISING_EDGE ((uint32_t)0x00000001)
#define PVD_FALLING_EDGE ((uint32_t)0x00000002)
#define PVD_MODE_IT ((uint32_t)0x00010000U)
#define PVD_MODE_EVT ((uint32_t)0x00020000U)
#define PVD_RISING_EDGE ((uint32_t)0x00000001U)
#define PVD_FALLING_EDGE ((uint32_t)0x00000002U)
/**
* @}
*/
@ -477,7 +477,7 @@ void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
*/
void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
{
uint32_t tmpreg = 0;
uint32_t tmpreg = 0U;
/* Check the parameters */
assert_param(IS_PWR_REGULATOR(Regulator));
assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
@ -538,7 +538,7 @@ void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
*/
void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
{
uint32_t tmpreg = 0;
uint32_t tmpreg = 0U;
/* Check the parameters */
assert_param(IS_PWR_REGULATOR(Regulator));

30
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_pwr.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx_hal_pwr.h
* @author MCD Application Team
* @version V1.5.0
* @date 8-January-2016
* @version V1.7.0
* @date 31-May-2016
* @brief Header file of PWR HAL module.
******************************************************************************
* @attention
@ -120,13 +120,13 @@ typedef struct
/** @defgroup PWR_PVD_Mode PWR PVD Mode
* @{
*/
#define PWR_PVD_MODE_NORMAL ((uint32_t)0x00000000) /*!< basic mode is used */
#define PWR_PVD_MODE_IT_RISING ((uint32_t)0x00010001) /*!< External Interrupt Mode with Rising edge trigger detection */
#define PWR_PVD_MODE_IT_FALLING ((uint32_t)0x00010002) /*!< External Interrupt Mode with Falling edge trigger detection */
#define PWR_PVD_MODE_IT_RISING_FALLING ((uint32_t)0x00010003) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
#define PWR_PVD_MODE_EVENT_RISING ((uint32_t)0x00020001) /*!< Event Mode with Rising edge trigger detection */
#define PWR_PVD_MODE_EVENT_FALLING ((uint32_t)0x00020002) /*!< Event Mode with Falling edge trigger detection */
#define PWR_PVD_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003) /*!< Event Mode with Rising/Falling edge trigger detection */
#define PWR_PVD_MODE_NORMAL ((uint32_t)0x00000000U) /*!< basic mode is used */
#define PWR_PVD_MODE_IT_RISING ((uint32_t)0x00010001U) /*!< External Interrupt Mode with Rising edge trigger detection */
#define PWR_PVD_MODE_IT_FALLING ((uint32_t)0x00010002U) /*!< External Interrupt Mode with Falling edge trigger detection */
#define PWR_PVD_MODE_IT_RISING_FALLING ((uint32_t)0x00010003U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
#define PWR_PVD_MODE_EVENT_RISING ((uint32_t)0x00020001U) /*!< Event Mode with Rising edge trigger detection */
#define PWR_PVD_MODE_EVENT_FALLING ((uint32_t)0x00020002U) /*!< Event Mode with Falling edge trigger detection */
#define PWR_PVD_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003U) /*!< Event Mode with Rising/Falling edge trigger detection */
/**
* @}
@ -135,7 +135,7 @@ typedef struct
/** @defgroup PWR_Regulator_state_in_SLEEP_STOP_mode PWR Regulator state in SLEEP/STOP mode
* @{
*/
#define PWR_MAINREGULATOR_ON ((uint32_t)0x00000000)
#define PWR_MAINREGULATOR_ON ((uint32_t)0x00000000U)
#define PWR_LOWPOWERREGULATOR_ON PWR_CR_LPSDSR
/**
@ -145,8 +145,8 @@ typedef struct
/** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry
* @{
*/
#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01)
#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02)
#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01U)
#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02U)
/**
* @}
*/
@ -154,8 +154,8 @@ typedef struct
/** @defgroup PWR_STOP_mode_entry PWR STOP mode entry
* @{
*/
#define PWR_STOPENTRY_WFI ((uint8_t)0x01)
#define PWR_STOPENTRY_WFE ((uint8_t)0x02)
#define PWR_STOPENTRY_WFI ((uint8_t)0x01U)
#define PWR_STOPENTRY_WFE ((uint8_t)0x02U)
/**
* @}
*/
@ -251,7 +251,7 @@ typedef struct
* @arg PWR_FLAG_WU: Wake Up flag
* @arg PWR_FLAG_SB: StandBy flag
*/
#define __HAL_PWR_CLEAR_FLAG(__FLAG__) SET_BIT(PWR->CR, (__FLAG__) << 2)
#define __HAL_PWR_CLEAR_FLAG(__FLAG__) SET_BIT(PWR->CR, (__FLAG__) << 2U)
/**
* @brief Enable interrupt on PVD Exti Line 16.

12
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_pwr_ex.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx_hal_pwr_ex.c
* @author MCD Application Team
* @version V1.5.0
* @date 8-January-2016
* @version V1.7.0
* @date 31-May-2016
* @brief Extended PWR HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Power Controller (PWR) peripheral:
@ -59,7 +59,7 @@
/** @defgroup PWR_Extended_TimeOut_Value PWREx Flag Setting Time Out Value
* @{
*/
#define PWR_FLAG_SETTING_DELAY_US 50
#define PWR_FLAG_SETTING_DELAY_US 50U
/**
* @}
*/
@ -153,16 +153,16 @@ void HAL_PWREx_EnableLowPowerRunMode(void)
*/
HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void)
{
uint32_t wait_loop_index = 0;
uint32_t wait_loop_index = 0U;
/* Exit the Low Power Run mode */
CLEAR_BIT(PWR->CR, PWR_CR_LPRUN);
CLEAR_BIT(PWR->CR, PWR_CR_LPSDSR);
/* Wait until REGLPF is reset */
wait_loop_index = (PWR_FLAG_SETTING_DELAY_US * (SystemCoreClock / 1000000));
wait_loop_index = (PWR_FLAG_SETTING_DELAY_US * (SystemCoreClock / 1000000U));
while ((wait_loop_index != 0) && (HAL_IS_BIT_SET(PWR->CSR, PWR_CSR_REGLPF)))
while ((wait_loop_index != 0U) && (HAL_IS_BIT_SET(PWR->CSR, PWR_CSR_REGLPF)))
{
wait_loop_index--;
}

4
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_pwr_ex.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx_hal_pwr_ex.h
* @author MCD Application Team
* @version V1.5.0
* @date 8-January-2016
* @version V1.7.0
* @date 31-May-2016
* @brief Header file of PWR HAL Extension module.
******************************************************************************
* @attention

126
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_rcc.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx_hal_rcc.c
* @author MCD Application Team
* @version V1.5.0
* @date 8-January-2016
* @version V1.4.0
* @date 01-October-2015
* @brief RCC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Reset and Clock Control (RCC) peripheral:
@ -122,8 +122,6 @@
#endif
extern const uint8_t PLLMulTable[]; /* Defined in CMSIS (system_stm32l0xx.c)*/
static const uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
/**
* @}
@ -187,20 +185,23 @@ static const uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4,
(#) For the STM32L0xx devices, the maximum
frequency of the SYSCLK ,HCLK, APB1 and APB2 is 32 MHz.
Depending on the device voltage range, the maximum frequency should
be adapted accordingly:
----------------------------------------------------------------
| Wait states | HCLK clock frequency (MHz) |
| |------------------------------------------------|
| (Latency) | voltage range | voltage range |
| | 1.65 V - 3.6 V | 2.0 V - 3.6 V |
| |----------------|---------------|---------------|
| | VCORE = 1.2 V | VCORE = 1.5 V | VCORE = 1.8 V |
|-------------- |----------------|---------------|---------------|
|0WS(1CPU cycle)|0 < HCLK <= 2 |0 < HCLK <= 8 |0 < HCLK <= 16 |
|---------------|----------------|---------------|---------------|
|1WS(2CPU cycle)|2 < HCLK <= 4 |8 < HCLK <= 16 |16 < HCLK <= 32|
----------------------------------------------------------------
be adapted accordingly. Refer to the Reference Manual for more details.
@endverbatim
Table 1. HCLK clock frequency.
+----------------------------------------------------------------+
| Wait states | HCLK clock frequency (MHz) |
| |------------------------------------------------|
| (Latency) | voltage range | voltage range |
| | 1.65 V - 3.6 V | 2.0 V - 3.6 V |
| |----------------|---------------|---------------|
| | VCORE = 1.2 V | VCORE = 1.5 V | VCORE = 1.8 V |
|-------------- |----------------|---------------|---------------|
|0WS(1CPU cycle)|0 < HCLK <= 2 |0 < HCLK <= 8 |0 < HCLK <= 16 |
|---------------|----------------|---------------|---------------|
|1WS(2CPU cycle)|2 < HCLK <= 4 |8 < HCLK <= 16 |16 < HCLK <= 32|
+----------------------------------------------------------------+
* @{
*/
@ -209,7 +210,7 @@ static const uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4,
* @note The default reset state of the clock configuration is given below:
* - MSI ON and used as system clock source (MSI range is not modified
* - by this function, it keep the value configured by user application)
* - HSI, HSE and PLL OFF
* - HSI, HSI_OUT, HSE and PLL OFF
* - AHB, APB1 and APB2 prescaler set to 1.
* - CSS and MCO OFF
* - All interrupts disabled
@ -218,9 +219,43 @@ static const uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4,
* @note -HSI48, LSI, LSE and RTC clocks
* @retval None
*/
__weak void HAL_RCC_DeInit(void)
void HAL_RCC_DeInit(void)
{
/* This function is now defined in the file stm32L0xx_rcc_ex.c */
__IO uint32_t tmpreg;
/* Set MSION bit */
SET_BIT(RCC->CR, RCC_CR_MSION);
#if defined(STM32L073xx) || defined(STM32L083xx) || \
defined(STM32L072xx) || defined(STM32L082xx) || \
defined(STM32L071xx) || defined(STM32L081xx) || \
defined(STM32L031xx) || defined(STM32L041xx)
/* Reset HSE, HSI, CSS, PLL */
CLEAR_BIT(RCC->CR, RCC_CR_HSION| RCC_CR_HSIKERON| RCC_CR_HSIDIVEN | RCC_CR_HSIOUTEN | \
RCC_CR_HSEON | RCC_CR_CSSHSEON | RCC_CR_PLLON);
#elif defined(STM32L011xx) || defined(STM32L021xx)
CLEAR_BIT(RCC->CR, RCC_CR_HSION| RCC_CR_HSIKERON| RCC_CR_HSIDIVEN | RCC_CR_HSIOUTEN | \
RCC_CR_HSEON | RCC_CR_PLLON);
#else
CLEAR_BIT(RCC->CR, RCC_CR_HSION| RCC_CR_HSIKERON| RCC_CR_HSIDIVEN | \
RCC_CR_HSEON | RCC_CR_CSSHSEON | RCC_CR_PLLON);
#endif
/* Delay after an RCC peripheral clock */ \
tmpreg = READ_BIT(RCC->CR, RCC_CR_HSEON); \
UNUSED(tmpreg);
/* Reset HSEBYP bit */
CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
/* Reset CFGR register */
CLEAR_REG(RCC->CFGR);
/* Disable all interrupts */
CLEAR_REG(RCC->CIER);
/* Update the SystemCoreClock global variable */
SystemCoreClock = MSI_VALUE;
}
/**
@ -240,7 +275,7 @@ __weak void HAL_RCC_DeInit(void)
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
uint32_t tickstart = 0;
uint32_t tickstart = 0U;
/* Check the parameters */
assert_param(RCC_OscInitStruct != NULL);
@ -382,6 +417,9 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
/* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
__HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
/* Update the SystemCoreClock global variable */
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
/* Configure the source of time base considering new system clocks settings*/
HAL_InitTick (TICK_INT_PRIORITY);
}
@ -701,7 +739,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
{
uint32_t tickstart = 0;
uint32_t tickstart = 0U;
/* Check the parameters */
assert_param(RCC_ClkInitStruct != NULL);
@ -850,6 +888,9 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
}
/* Update the SystemCoreClock global variable */
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
/* Configure the source of time base considering new system clocks settings*/
HAL_InitTick (TICK_INT_PRIORITY);
@ -1000,26 +1041,26 @@ void HAL_RCC_EnableCSS(void)
*/
uint32_t HAL_RCC_GetSysClockFreq(void)
{
uint32_t pllmul = 0, plldiv = 0, pllsource = 0, msirange = 0;
uint32_t sysclockfreq = 0;
uint32_t pllmul = 0U, plldiv = 0U, pllsource = 0U, msirange = 0U;
uint32_t sysclockfreq = 0U;
/* Get SYSCLK source -------------------------------------------------------*/
/*MSI frequency range in HZ*/
msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;
msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13U;
switch (RCC->CFGR & RCC_CFGR_SWS)
{
case RCC_CFGR_SWS_MSI: /* MSI used as system clock */
{
sysclockfreq = (32768 * (1 << (msirange + 1)));
sysclockfreq = (32768U * (1U << (msirange + 1U)));
break;
}
case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock */
{
if ((RCC->CR & RCC_CR_HSIDIVF) != 0)
if ((RCC->CR & RCC_CR_HSIDIVF) != 0U)
{
sysclockfreq = (HSI_VALUE >> 2);
sysclockfreq = (HSI_VALUE >> 2U);
}
else
{
@ -1037,17 +1078,17 @@ uint32_t HAL_RCC_GetSysClockFreq(void)
/* Get PLL clock source and multiplication factor ----------------------*/
pllmul = RCC->CFGR & RCC_CFGR_PLLMUL;
plldiv = RCC->CFGR & RCC_CFGR_PLLDIV;
pllmul = PLLMulTable[(pllmul >> 18)];
plldiv = (plldiv >> 22) + 1;
pllmul = PLLMulTable[(pllmul >> 18U)];
plldiv = (plldiv >> 22U) + 1U;
pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
if (pllsource == RCC_CFGR_PLLSRC_HSI)
{
/* HSI oscillator clock selected as PLL clock source */
if ((RCC->CR & RCC_CR_HSIDIVF) != 0)
if ((RCC->CR & RCC_CR_HSIDIVF) != 0U)
{
sysclockfreq = (((HSI_VALUE >> 2) * pllmul) / plldiv);
sysclockfreq = (((HSI_VALUE >> 2U) * pllmul) / plldiv);
}
else
{
@ -1063,7 +1104,7 @@ uint32_t HAL_RCC_GetSysClockFreq(void)
}
default: /* MSI used as system clock */
{
sysclockfreq = (32768 * (1 << (msirange + 1)));
sysclockfreq = (32768U * (1U << (msirange + 1U)));
break;
}
}
@ -1081,10 +1122,7 @@ uint32_t HAL_RCC_GetSysClockFreq(void)
*/
uint32_t HAL_RCC_GetHCLKFreq(void)
{
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> APBAHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
return (SystemCoreClock);
}
/**
@ -1096,7 +1134,7 @@ uint32_t HAL_RCC_GetHCLKFreq(void)
uint32_t HAL_RCC_GetPCLK1Freq(void)
{
return ( HAL_RCC_GetHCLKFreq() >> APBAHBPrescTable[((RCC->CFGR & RCC_CFGR_PPRE1) >> 8)]);
return ( HAL_RCC_GetHCLKFreq() >> APBPrescTable[((RCC->CFGR & RCC_CFGR_PPRE1) >> 8U)]);
}
@ -1109,7 +1147,7 @@ uint32_t HAL_RCC_GetPCLK1Freq(void)
uint32_t HAL_RCC_GetPCLK2Freq(void)
{
return ( HAL_RCC_GetHCLKFreq() >> APBAHBPrescTable[((RCC->CFGR & RCC_CFGR_PPRE2) >> 11)]);
return ( HAL_RCC_GetHCLKFreq() >> APBPrescTable[((RCC->CFGR & RCC_CFGR_PPRE2) >> 11U)]);
}
@ -1153,8 +1191,8 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
RCC_OscInitStruct->MSIState = RCC_MSI_OFF;
}
RCC_OscInitStruct->MSICalibrationValue = (uint32_t)((RCC->CR &RCC_ICSCR_MSITRIM) >> 24);
RCC_OscInitStruct->MSIClockRange = (uint32_t)((RCC->ICSCR &RCC_ICSCR_MSIRANGE) >> 13);
RCC_OscInitStruct->MSICalibrationValue = (uint32_t)((RCC->CR &RCC_ICSCR_MSITRIM) >> 24U);
RCC_OscInitStruct->MSIClockRange = (uint32_t)((RCC->ICSCR &RCC_ICSCR_MSIRANGE) >> 13U);
#if !defined (STM32L011xx) && !defined (STM32L021xx) && !defined (STM32L031xx) && !defined (STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
/* Get the HSI48 configuration -----------------------------------------------*/
@ -1178,7 +1216,7 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
}
RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->ICSCR &RCC_ICSCR_HSITRIM) >> 8);
RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->ICSCR &RCC_ICSCR_HSITRIM) >> 8U);
/* Get the LSE configuration -----------------------------------------------*/
if((RCC->CSR &RCC_CSR_LSEBYP) == RCC_CSR_LSEBYP)
@ -1214,8 +1252,8 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
}
RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLSRC);
RCC_OscInitStruct->PLL.PLLMUL = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLMUL) >> 18;
RCC_OscInitStruct->PLL.PLLDIV = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLDIV) >> 22;
RCC_OscInitStruct->PLL.PLLMUL = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLMUL) >> 18U;
RCC_OscInitStruct->PLL.PLLDIV = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLDIV) >> 22U;
}
@ -1242,7 +1280,7 @@ void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pF
RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1);
/* Get the APB2 configuration ----------------------------------------------*/
RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3);
RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3U);
/* Get the Flash Wait State (Latency) configuration ------------------------*/
*pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);

155
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_rcc.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx_hal_rcc.h
* @author MCD Application Team
* @version V1.5.0
* @date 8-January-2016
* @version V1.7.0
* @date 31-May-2016
* @brief Header file of RCC HAL module.
******************************************************************************
* @attention
@ -153,18 +153,18 @@ typedef struct
#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
/* --- CR Register ---*/
/* Alias word address of HSION bit */
#define RCC_CR_OFFSET (RCC_OFFSET + 0x00)
#define RCC_CR_OFFSET (RCC_OFFSET + 0x00U)
/* --- CFGR Register ---*/
/* Alias word address of I2SSRC bit */
#define RCC_CFGR_OFFSET (RCC_OFFSET + 0x08)
#define RCC_CFGR_OFFSET (RCC_OFFSET + 0x08U)
/* --- CSR Register ---*/
#define RCC_CSR_OFFSET (RCC_OFFSET + 0x74)
#define RCC_CSR_OFFSET (RCC_OFFSET + 0x74U)
/* CR register byte 3 (Bits[23:16]) base address */
#define RCC_CR_BYTE2_ADDRESS ((uint32_t)0x40023802)
#define RCC_CR_BYTE2_ADDRESS ((uint32_t)0x40023802U)
/* CIER register byte 0 (Bits[0:8]) base address */
#define CIER_BYTE0_ADDRESS ((uint32_t)(RCC_BASE + 0x10 + 0x00))
#define CIER_BYTE0_ADDRESS ((uint32_t)(RCC_BASE + 0x10U + 0x00U))
/**
* @}
@ -178,7 +178,7 @@ typedef struct
/** @defgroup RCC_Timeout_Value Timeout Values
* @{
*/
#define RCC_DBP_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
#define RCC_DBP_TIMEOUT_VALUE ((uint32_t)100U) /* 100 ms */
#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
#define RCC_HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
/**
@ -188,14 +188,14 @@ typedef struct
/** @defgroup RCC_Oscillator_Type Oscillator Type
* @{
*/
#define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000) /*!< Oscillator configuration unchanged */
#define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001) /*!< HSE to configure */
#define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002) /*!< HSI to configure */
#define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004) /*!< LSE to configure */
#define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008) /*!< LSI to configure */
#define RCC_OSCILLATORTYPE_MSI ((uint32_t)0x00000010) /*!< MSI to configure */
#define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000U) /*!< Oscillator configuration unchanged */
#define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001U) /*!< HSE to configure */
#define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002U) /*!< HSI to configure */
#define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004U) /*!< LSE to configure */
#define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008U) /*!< LSI to configure */
#define RCC_OSCILLATORTYPE_MSI ((uint32_t)0x00000010U) /*!< MSI to configure */
#if !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
#define RCC_OSCILLATORTYPE_HSI48 ((uint32_t)0x00000020)
#define RCC_OSCILLATORTYPE_HSI48 ((uint32_t)0x00000020U)
#endif /* !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) */
/**
@ -205,7 +205,7 @@ typedef struct
/** @defgroup RCC_HSE_Config RCC HSE Config
* @{
*/
#define RCC_HSE_OFF ((uint32_t)0x00000000)
#define RCC_HSE_OFF ((uint32_t)0x00000000U)
#define RCC_HSE_ON RCC_CR_HSEON
#define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON))
@ -216,7 +216,7 @@ typedef struct
/** @defgroup RCC_LSE_Config RCC LSE Config
* @{
*/
#define RCC_LSE_OFF ((uint32_t)0x00000000)
#define RCC_LSE_OFF ((uint32_t)0x00000000U)
#define RCC_LSE_ON RCC_CSR_LSEON
#define RCC_LSE_BYPASS ((uint32_t)(RCC_CSR_LSEBYP | RCC_CSR_LSEON))
@ -229,8 +229,8 @@ typedef struct
/** @defgroup RCC_LSI_Config RCC LSI Config
* @{
*/
#define RCC_LSI_OFF ((uint8_t)0x00)
#define RCC_LSI_ON ((uint8_t)0x01)
#define RCC_LSI_OFF ((uint8_t)0x00U)
#define RCC_LSI_ON ((uint8_t)0x01U)
#define RCC_MSICALIBRATION_DEFAULT ((uint32_t)0) /* Default MSI calibration trimming value */
@ -242,10 +242,10 @@ typedef struct
/** @defgroup RCC_MSI_Config RCC MSI Config
* @{
*/
#define RCC_MSI_OFF ((uint8_t)0x00)
#define RCC_MSI_ON ((uint8_t)0x01)
#define RCC_MSI_OFF ((uint8_t)0x00U)
#define RCC_MSI_ON ((uint8_t)0x01U)
#define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x10) /* Default HSI calibration trimming value */
#define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x10U) /* Default HSI calibration trimming value */
/**
* @}
@ -255,8 +255,8 @@ typedef struct
/** @defgroup RCC_HSI48_Config RCC HSI48 Configuration
* @{
*/
#define RCC_HSI48_OFF ((uint8_t)0x00)
#define RCC_HSI48_ON ((uint8_t)0x01)
#define RCC_HSI48_OFF ((uint8_t)0x00U)
#define RCC_HSI48_ON ((uint8_t)0x01U)
/**
* @}
@ -266,9 +266,9 @@ typedef struct
/** @defgroup RCC_PLL_Config RCC PLL Config
* @{
*/
#define RCC_PLL_NONE ((uint8_t)0x00)
#define RCC_PLL_OFF ((uint8_t)0x01)
#define RCC_PLL_ON ((uint8_t)0x02)
#define RCC_PLL_NONE ((uint8_t)0x00U)
#define RCC_PLL_OFF ((uint8_t)0x01U)
#define RCC_PLL_ON ((uint8_t)0x02U)
/**
* @}
@ -335,10 +335,10 @@ typedef struct
/** @defgroup RCC_System_Clock_Type RCC System Clock Type
* @{
*/
#define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001) /*!< SYSCLK to configure */
#define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002) /*!< HCLK to configure */
#define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004) /*!< PCLK1 to configure */
#define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008) /*!< PCLK2 to configure */
#define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001U) /*!< SYSCLK to configure */
#define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002U) /*!< HCLK to configure */
#define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004U) /*!< PCLK1 to configure */
#define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008U) /*!< PCLK2 to configure */
/**
* @}
*/
@ -396,7 +396,7 @@ typedef struct
/** @defgroup RCC_RTC_Clock_Source RCC RTC Clock Source
* @{
*/
#define RCC_RTCCLKSOURCE_NO_CLK ((uint32_t)0x00000000)
#define RCC_RTCCLKSOURCE_NO_CLK ((uint32_t)0x00000000U)
#define RCC_RTCCLKSOURCE_LSE RCC_CSR_RTCSEL_LSE
#define RCC_RTCCLKSOURCE_LSI RCC_CSR_RTCSEL_LSI
#define RCC_RTCCLKSOURCE_HSE_DIVX RCC_CSR_RTCSEL_HSE
@ -454,11 +454,11 @@ typedef struct
/** @defgroup RCC_MCO_Index RCC MCO Index
* @{
*/
#define RCC_MCO1 ((uint32_t)0x00000000)
#define RCC_MCO2 ((uint32_t)0x00000001)
#define RCC_MCO1 ((uint32_t)0x00000000U)
#define RCC_MCO2 ((uint32_t)0x00000001U)
#if defined(STM32L031xx) || defined(STM32L041xx) || defined(STM32L073xx) || defined(STM32L083xx) || \
defined(STM32L072xx) || defined(STM32L082xx) || defined(STM32L071xx) || defined(STM32L081xx)
#define RCC_MCO3 ((uint32_t)0x00000002)
#define RCC_MCO3 ((uint32_t)0x00000002U)
#endif
/**
@ -495,28 +495,28 @@ typedef struct
* @{
*/
/* Flags in the CR register */
#define RCC_FLAG_HSIRDY ((uint8_t)0x22)
#define RCC_FLAG_HSIDIV ((uint8_t)0x24)
#define RCC_FLAG_MSIRDY ((uint8_t)0x29)
#define RCC_FLAG_HSERDY ((uint8_t)0x31)
#define RCC_FLAG_PLLRDY ((uint8_t)0x39)
#define RCC_FLAG_HSIRDY ((uint8_t)0x22U)
#define RCC_FLAG_HSIDIV ((uint8_t)0x24U)
#define RCC_FLAG_MSIRDY ((uint8_t)0x29U)
#define RCC_FLAG_HSERDY ((uint8_t)0x31U)
#define RCC_FLAG_PLLRDY ((uint8_t)0x39U)
/* Flags in the CSR register */
#define RCC_FLAG_LSERDY ((uint8_t)0x49)
#define RCC_FLAG_LSECSS ((uint8_t)0x4E)
#define RCC_FLAG_LSIRDY ((uint8_t)0x41)
#define RCC_FLAG_FWRST ((uint8_t)0x58)
#define RCC_FLAG_OBLRST ((uint8_t)0x59)
#define RCC_FLAG_PINRST ((uint8_t)0x5A)
#define RCC_FLAG_PORRST ((uint8_t)0x5B)
#define RCC_FLAG_SFTRST ((uint8_t)0x5C)
#define RCC_FLAG_IWDGRST ((uint8_t)0x5D)
#define RCC_FLAG_WWDGRST ((uint8_t)0x5E)
#define RCC_FLAG_LPWRRST ((uint8_t)0x5F)
#define RCC_FLAG_LSERDY ((uint8_t)0x49U)
#define RCC_FLAG_LSECSS ((uint8_t)0x4EU)
#define RCC_FLAG_LSIRDY ((uint8_t)0x41U)
#define RCC_FLAG_FWRST ((uint8_t)0x58U)
#define RCC_FLAG_OBLRST ((uint8_t)0x59U)
#define RCC_FLAG_PINRST ((uint8_t)0x5AU)
#define RCC_FLAG_PORRST ((uint8_t)0x5BU)
#define RCC_FLAG_SFTRST ((uint8_t)0x5CU)
#define RCC_FLAG_IWDGRST ((uint8_t)0x5DU)
#define RCC_FLAG_WWDGRST ((uint8_t)0x5EU)
#define RCC_FLAG_LPWRRST ((uint8_t)0x5FU)
#if !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
/* Flags in the CRRCR register */
#define RCC_FLAG_HSI48RDY ((uint8_t)0x61)
#define RCC_FLAG_HSI48RDY ((uint8_t)0x61U)
#endif /* !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) */
@ -718,12 +718,12 @@ typedef struct
* @brief Force or release AHB peripheral reset.
* @{
*/
#define __HAL_RCC_AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFF)
#define __HAL_RCC_AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFFU)
#define __HAL_RCC_DMA1_FORCE_RESET() SET_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_DMA1RST))
#define __HAL_RCC_MIF_FORCE_RESET() SET_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_MIFRST))
#define __HAL_RCC_CRC_FORCE_RESET() SET_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_CRCRST))
#define __HAL_RCC_AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00)
#define __HAL_RCC_AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00U)
#define __HAL_RCC_CRC_RELEASE_RESET() CLEAR_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_CRCRST))
#define __HAL_RCC_DMA1_RELEASE_RESET() CLEAR_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_DMA1RST))
#define __HAL_RCC_MIF_RELEASE_RESET() CLEAR_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_MIFRST))
@ -735,13 +735,13 @@ typedef struct
* @brief Force or release IOPORT peripheral reset.
* @{
*/
#define __HAL_RCC_IOP_FORCE_RESET() (RCC->IOPRSTR = 0xFFFFFFFF)
#define __HAL_RCC_IOP_FORCE_RESET() (RCC->IOPRSTR = 0xFFFFFFFFU)
#define __HAL_RCC_GPIOA_FORCE_RESET() SET_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOARST))
#define __HAL_RCC_GPIOB_FORCE_RESET() SET_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOBRST))
#define __HAL_RCC_GPIOC_FORCE_RESET() SET_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOCRST))
#define __HAL_RCC_GPIOH_FORCE_RESET() SET_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOHRST))
#define __HAL_RCC_IOP_RELEASE_RESET() (RCC->IOPRSTR = 0x00)
#define __HAL_RCC_IOP_RELEASE_RESET() (RCC->IOPRSTR = 0x00U)
#define __HAL_RCC_GPIOA_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOARST))
#define __HAL_RCC_GPIOB_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOBRST))
#define __HAL_RCC_GPIOC_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOCRST))
@ -755,11 +755,11 @@ typedef struct
* @brief Force or release APB1 peripheral reset.
* @{
*/
#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFF)
#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU)
#define __HAL_RCC_WWDG_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_WWDGRST))
#define __HAL_RCC_PWR_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_PWRRST))
#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00)
#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00U)
#define __HAL_RCC_WWDG_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_WWDGRST))
#define __HAL_RCC_PWR_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_PWRRST))
@ -771,11 +771,11 @@ typedef struct
* @brief Force or release APB2 peripheral reset.
* @{
*/
#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFF)
#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU)
#define __HAL_RCC_DBGMCU_FORCE_RESET() SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_DBGMCURST))
#define __HAL_RCC_SYSCFG_FORCE_RESET() SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_SYSCFGRST))
#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00)
#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00U)
#define __HAL_RCC_DBGMCU_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_DBGMCURST))
#define __HAL_RCC_SYSCFG_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_SYSCFGRST))
/**
@ -980,7 +980,7 @@ typedef struct
* This parameter must be a number between 0 and 0x1F.
*/
#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) (MODIFY_REG(RCC->ICSCR,\
RCC_ICSCR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << 8))
RCC_ICSCR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << 8U))
/** @brief Macro to enable or disable the Internal High Speed oscillator (HSI).
* @note After enabling the HSI, the application software should wait on
@ -1030,7 +1030,7 @@ typedef struct
* This parameter must be a number between 0 and 0xFF.
*/
#define __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(__MSICalibrationValue__) (MODIFY_REG(RCC->ICSCR,\
RCC_ICSCR_MSITRIM, (uint32_t)(__MSICalibrationValue__) << 24))
RCC_ICSCR_MSITRIM, (uint32_t)(__MSICalibrationValue__) << 24U))
/**
* @brief Macro to configures the Internal Multi Speed oscillator (MSI) clock range.
@ -1064,7 +1064,7 @@ typedef struct
*/
#define __HAL_RCC_GET_MSI_RANGE() \
((uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSIRANGE) >> 12))
((uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSIRANGE) >> 12U))
/** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI).
* @note After enabling the LSI, the application software should wait on
@ -1207,10 +1207,10 @@ typedef struct
* @brief Get the RTC and LCD clock (RTCCLK / LCDCLK).
*
* @retval The clock source can be one of the following values:
* @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock
* @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock
* @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock
* @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX HSE divided by X selected as RTC clock (X can be retrieved thanks to @ref __HAL_RCC_GET_RTC_HSE_PRESCALER()
* @arg RCC_RTCCLKSOURCE_NO_CLK: No clock selected as RTC clock
* @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock
* @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock
* @arg RCC_RTCCLKSOURCE_HSE_DIVX: HSE divided by X selected as RTC clock (X can be retrieved thanks to @ref __HAL_RCC_GET_RTC_HSE_PRESCALER()
*
*/
#define __HAL_RCC_GET_RTC_SOURCE() ((uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_RTCSEL)))
@ -1219,14 +1219,15 @@ typedef struct
* @brief Get the RTC and LCD HSE clock divider (RTCCLK / LCDCLK).
*
* @retval Returned value can be one of the following values:
* @arg @ref RCC_RTC_HSE_DIV_2: HSE divided by 2 selected as RTC clock
* @arg @ref RCC_RTC_HSE_DIV_4: HSE divided by 4 selected as RTC clock
* @arg @ref RCC_RTC_HSE_DIV_8: HSE divided by 8 selected as RTC clock
* @arg @ref RCC_RTC_HSE_DIV_16: HSE divided by 16 selected as RTC clock
* @arg RCC_RTC_HSE_DIV_2: HSE divided by 2 selected as RTC clock
* @arg RCC_RTC_HSE_DIV_4: HSE divided by 4 selected as RTC clock
* @arg RCC_RTC_HSE_DIV_8: HSE divided by 8 selected as RTC clock
* @arg RCC_RTC_HSE_DIV_16: HSE divided by 16 selected as RTC clock
*
*/
#define __HAL_RCC_GET_RTC_HSE_PRESCALER() ((uint32_t)(READ_BIT(RCC->CR, RCC_CR_RTCPRE)))
/** @brief Macros to enable or disable the main PLL.
* @note After enabling the main PLL, the application software should wait on
* PLLRDY flag to be set indicating that PLL clock is stable and can
@ -1428,8 +1429,8 @@ typedef struct
* @arg RCC_FLAG_LPWRRST: Low Power reset
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5) == 1)? RCC->CR :((((__FLAG__) >> 5) == 2) ? RCC->CSR :((((__FLAG__) >> 5) == 3)? \
RCC->CRRCR :RCC->CIFR))) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK))) != 0 ) ? 1 : 0 )
#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U)? RCC->CR :((((__FLAG__) >> 5U) == 2U) ? RCC->CSR :((((__FLAG__) >> 5U) == 3U)? \
RCC->CRRCR :RCC->CIFR))) & ((uint32_t)1U << ((__FLAG__) & RCC_FLAG_MASK))) != 0U ) ? 1U : 0U )
/**
* @}
@ -1445,7 +1446,7 @@ typedef struct
* @{
*/
/* Defines used for Flags */
#define RCC_FLAG_MASK ((uint8_t)0x1F)
#define RCC_FLAG_MASK ((uint8_t)0x1FU)
/**
* @}
@ -1457,9 +1458,9 @@ typedef struct
*/
#if !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) ((__OSCILLATOR__) <= 0x3F)
#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) ((__OSCILLATOR__) <= 0x3FU)
#else
#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) ((__OSCILLATOR__) <= 0x1F)
#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) ((__OSCILLATOR__) <= 0x1FU)
#endif /* !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) */
#define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \
@ -1493,7 +1494,7 @@ typedef struct
#define IS_RCC_PLL_DIV(__DIV__) (((__DIV__) == RCC_PLLDIV_2) || ((__DIV__) == RCC_PLLDIV_3) || \
((__DIV__) == RCC_PLLDIV_4))
#define IS_RCC_CLOCKTYPE(__CLK__) ((1 <= (__CLK__)) && ((__CLK__) <= 15))
#define IS_RCC_CLOCKTYPE(__CLK__) ((1U <= (__CLK__)) && ((__CLK__) <= 15U))
#define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \
((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \

133
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_rcc_ex.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx_hal_rcc_ex.c
* @author MCD Application Team
* @version V1.5.0
* @date 8-January-2016
* @version V1.7.0
* @date 31-May-2016
* @brief Extended RCC HAL module driver.
*
* This file provides firmware functions to manage the following
@ -105,9 +105,9 @@
* @{
*/
/* Bit position in register */
#define CRS_CFGR_FELIM_BITNUMBER 16
#define CRS_CR_TRIM_BITNUMBER 8
#define CRS_ISR_FECAP_BITNUMBER 16
#define CRS_CFGR_FELIM_BITNUMBER 16U
#define CRS_CR_TRIM_BITNUMBER 8U
#define CRS_ISR_FECAP_BITNUMBER 16U
#if defined(USB)
extern const uint8_t PLLMulTable[];
@ -135,56 +135,6 @@ extern const uint8_t PLLMulTable[];
* @{
*/
/**
* @brief Resets the RCC clock configuration to the default reset state.
* @note The default reset state of the clock configuration is given below:
* - MSI ON and used as system clock source (MSI range is not modified
* - by this function, it keep the value configured by user application)
* - HSI, HSI_OUT, HSE and PLL OFF
* - AHB, APB1 and APB2 prescaler set to 1.
* - CSS and MCO OFF
* - All interrupts disabled
* @note This function does not modify the configuration of the
* @note -Peripheral clocks
* @note -HSI48, LSI, LSE and RTC clocks
* @retval None
*/
void HAL_RCC_DeInit(void)
{
__IO uint32_t tmpreg;
/* Set MSION bit */
SET_BIT(RCC->CR, RCC_CR_MSION);
#if defined(STM32L073xx) || defined(STM32L083xx) || \
defined(STM32L072xx) || defined(STM32L082xx) || \
defined(STM32L071xx) || defined(STM32L081xx) || \
defined(STM32L031xx) || defined(STM32L041xx)
/* Reset HSE, HSI, CSS, PLL */
CLEAR_BIT(RCC->CR, RCC_CR_HSION| RCC_CR_HSIKERON| RCC_CR_HSIDIVEN | RCC_CR_HSIOUTEN | \
RCC_CR_HSEON | RCC_CR_CSSHSEON | RCC_CR_PLLON);
#elif defined(STM32L011xx) || defined(STM32L021xx)
CLEAR_BIT(RCC->CR, RCC_CR_HSION| RCC_CR_HSIKERON| RCC_CR_HSIDIVEN | RCC_CR_HSIOUTEN | \
RCC_CR_HSEON | RCC_CR_PLLON);
#else
CLEAR_BIT(RCC->CR, RCC_CR_HSION| RCC_CR_HSIKERON| RCC_CR_HSIDIVEN | \
RCC_CR_HSEON | RCC_CR_CSSHSEON | RCC_CR_PLLON);
#endif
/* Delay after an RCC peripheral clock */ \
tmpreg = READ_BIT(RCC->CR, RCC_CR_HSEON); \
UNUSED(tmpreg);
/* Reset HSEBYP bit */
CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
/* Reset CFGR register */
CLEAR_REG(RCC->CFGR);
/* Disable all interrupts */
CLEAR_REG(RCC->CIER);
}
/**
* @brief Initializes the RCC extended peripherals clocks
* @note Initializes the RCC extended peripherals clocks according to the specified parameters in the
@ -198,8 +148,8 @@ void HAL_RCC_DeInit(void)
*/
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
{
uint32_t tickstart = 0;
uint32_t tmpreg = 0;
uint32_t tickstart = 0U;
uint32_t tmpreg = 0U;
/* Check the parameters */
assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
@ -448,9 +398,9 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
*/
uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
{
uint32_t srcclk = 0, clkprediv = 0, frequency = 0;
uint32_t srcclk = 0U, clkprediv = 0U, frequency = 0U;
#if defined(USB)
uint32_t pllmul = 0, plldiv = 0, pllvco = 0;
uint32_t pllmul = 0U, plldiv = 0U, pllvco = 0U;
#endif /* USB */
/* Check the parameters */
@ -483,22 +433,22 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
{
case RCC_RTC_HSE_DIV_16: /* HSE DIV16 has been selected */
{
frequency = HSE_VALUE / 16;
frequency = HSE_VALUE / 16U;
break;
}
case RCC_RTC_HSE_DIV_8: /* HSE DIV8 has been selected */
{
frequency = HSE_VALUE / 8;
frequency = HSE_VALUE / 8U;
break;
}
case RCC_RTC_HSE_DIV_4: /* HSE DIV4 has been selected */
{
frequency = HSE_VALUE / 4;
frequency = HSE_VALUE / 4U;
break;
}
default:
{
frequency = HSE_VALUE / 2;
frequency = HSE_VALUE / 2U;
break;
}
}
@ -506,7 +456,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
/* Clock not enabled for RTC*/
else
{
frequency = 0;
frequency = 0U;
}
break;
}
@ -538,22 +488,22 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
{
case RCC_RTC_HSE_DIV_16: /* HSE DIV16 has been selected */
{
frequency = HSE_VALUE / 16;
frequency = HSE_VALUE / 16U;
break;
}
case RCC_RTC_HSE_DIV_8: /* HSE DIV8 has been selected */
{
frequency = HSE_VALUE / 8;
frequency = HSE_VALUE / 8U;
break;
}
case RCC_RTC_HSE_DIV_4: /* HSE DIV4 has been selected */
{
frequency = HSE_VALUE / 4;
frequency = HSE_VALUE / 4U;
break;
}
default:
{
frequency = HSE_VALUE / 2;
frequency = HSE_VALUE / 2U;
break;
}
}
@ -561,12 +511,13 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
/* Clock not enabled for LCD*/
else
{
frequency = 0;
frequency = 0U;
}
break;
}
#endif /* LCD */
#if defined(USB)
case RCC_PERIPHCLK_USB:
{
@ -578,15 +529,15 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
/* Get PLL clock source and multiplication factor ----------------------*/
pllmul = RCC->CFGR & RCC_CFGR_PLLMUL;
plldiv = RCC->CFGR & RCC_CFGR_PLLDIV;
pllmul = PLLMulTable[(pllmul >> 18)];
plldiv = (plldiv >> 22) + 1;
pllmul = PLLMulTable[(pllmul >> 18U)];
plldiv = (plldiv >> 22U) + 1U;
/* Compute PLL clock input */
if(__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI)
{
if (READ_BIT(RCC->CR, RCC_CR_HSIDIVF) != 0)
if (READ_BIT(RCC->CR, RCC_CR_HSIDIVF) != 0U)
{
pllvco = (HSI_VALUE >> 2);
pllvco = (HSI_VALUE >> 2U);
}
else
{
@ -608,7 +559,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
}
else /* RCC_USBCLKSOURCE_NONE */
{
frequency = 0;
frequency = 0U;
}
break;
}
@ -642,7 +593,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
/* Clock not enabled for USART1*/
else
{
frequency = 0;
frequency = 0U;
}
break;
}
@ -675,7 +626,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
/* Clock not enabled for USART2*/
else
{
frequency = 0;
frequency = 0U;
}
break;
}
@ -707,7 +658,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
/* Clock not enabled for LPUART1*/
else
{
frequency = 0;
frequency = 0U;
}
break;
}
@ -734,7 +685,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
/* Clock not enabled for I2C1*/
else
{
frequency = 0;
frequency = 0U;
}
break;
}
@ -749,7 +700,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
}
else
{
frequency = 0;
frequency = 0U;
}
break;
}
@ -779,7 +730,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
/* Clock not enabled for I2C3*/
else
{
frequency = 0;
frequency = 0U;
}
break;
}
@ -966,15 +917,15 @@ void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo
* This parameter can be a combination of the following values:
* @arg RCC_CRS_TIMEOUT
* @arg RCC_CRS_SYNCOK
* @arg RCC_CRS_SYNCWARM
* @arg RCC_CRS_SYNCWARN
* @arg RCC_CRS_SYNCERR
* @arg RCC_CRS_SYNCMISS
* @arg RCC_CRS_TRIMOV
* @arg RCC_CRS_TRIMOVF
*/
uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout)
{
uint32_t crsstatus = RCC_CRS_NONE;
uint32_t tickstart = 0;
uint32_t tickstart = 0U;
/* Get timeout */
tickstart = HAL_GetTick();
@ -984,7 +935,7 @@ uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout)
{
if(Timeout != HAL_MAX_DELAY)
{
if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
{
crsstatus = RCC_CRS_TIMEOUT;
}
@ -1003,7 +954,7 @@ uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout)
if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCWARN))
{
/* CRS SYNC warning */
crsstatus |= RCC_CRS_SYNCWARM;
crsstatus |= RCC_CRS_SYNCWARN;
/* Clear CRS SYNCWARN bit */
__HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCWARN);
@ -1013,7 +964,7 @@ uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout)
if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_TRIMOVF))
{
/* CRS SYNC Error */
crsstatus |= RCC_CRS_TRIMOV;
crsstatus |= RCC_CRS_TRIMOVF;
/* Clear CRS Error bit */
__HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_TRIMOVF);
@ -1056,9 +1007,8 @@ uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout)
*/
void HAL_RCCEx_EnableHSI48_VREFINT(void)
{
/* Enable the Buffer for the ADC by setting EN_VREFINT bit */
/* and the SYSCFG_CFGR3_ENREF_HSI48 in the CFGR3 register */
SET_BIT (SYSCFG->CFGR3, (SYSCFG_CFGR3_ENREF_HSI48 | SYSCFG_CFGR3_EN_VREFINT));
/* Enable the Buffer for the ADC by setting SYSCFG_CFGR3_ENREF_HSI48 bit in SYSCFG_CFGR3 register */
SET_BIT (SYSCFG->CFGR3, SYSCFG_CFGR3_ENREF_HSI48);
}
/**
@ -1068,9 +1018,8 @@ void HAL_RCCEx_EnableHSI48_VREFINT(void)
*/
void HAL_RCCEx_DisableHSI48_VREFINT(void)
{
/* Disable the Vrefint by resetting SYSCFG_CFGR3_ENREF_HSI48 bit */
/* and the EN_VREFINT bit in the CFGR3 register */
CLEAR_BIT(SYSCFG->CFGR3, (SYSCFG_CFGR3_ENREF_HSI48 | SYSCFG_CFGR3_EN_VREFINT));
/* Disable the Vrefint by resetting SYSCFG_CFGR3_ENREF_HSI48 bit in SYSCFG_CFGR3 register */
CLEAR_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_ENREF_HSI48);
}
#endif /* !defined (STM32L011xx) && !defined (STM32L021xx) && !defined (STM32L031xx) && !defined (STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) */

122
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_rcc_ex.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx_hal_rcc_ex.h
* @author MCD Application Team
* @version V1.5.0
* @date 8-January-2016
* @version V1.7.0
* @date 31-May-2016
* @brief Header file of RCC HAL Extension module.
******************************************************************************
* @attention
@ -153,13 +153,13 @@ typedef struct
* @brief RCC CRS Status definition
*/
#define RCC_CRS_NONE ((uint32_t) 0x00000000)
#define RCC_CRS_TIMEOUT ((uint32_t) 0x00000001)
#define RCC_CRS_SYNCOK ((uint32_t) 0x00000002)
#define RCC_CRS_SYNCWARM ((uint32_t) 0x00000004)
#define RCC_CRS_SYNCERR ((uint32_t) 0x00000008)
#define RCC_CRS_SYNCMISS ((uint32_t) 0x00000010)
#define RCC_CRS_TRIMOV ((uint32_t) 0x00000020)
#define RCC_CRS_NONE ((uint32_t) 0x00000000U)
#define RCC_CRS_TIMEOUT ((uint32_t) 0x00000001U)
#define RCC_CRS_SYNCOK ((uint32_t) 0x00000002U)
#define RCC_CRS_SYNCWARN ((uint32_t) 0x00000004U)
#define RCC_CRS_SYNCERR ((uint32_t) 0x00000008U)
#define RCC_CRS_SYNCMISS ((uint32_t) 0x00000010U)
#define RCC_CRS_TRIMOVF ((uint32_t) 0x00000020U)
/**
* @}
@ -232,37 +232,37 @@ typedef struct
*/
#if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
#define RCC_PERIPHCLK_LPUART1 ((uint32_t)0x00000004)
#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000008)
#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000010)
#define RCC_PERIPHCLK_RTC ((uint32_t)0x00000020)
#define RCC_PERIPHCLK_USB ((uint32_t)0x00000040)
#define RCC_PERIPHCLK_LPTIM1 ((uint32_t)0x00000080)
#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001U)
#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002U)
#define RCC_PERIPHCLK_LPUART1 ((uint32_t)0x00000004U)
#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000008U)
#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000010U)
#define RCC_PERIPHCLK_RTC ((uint32_t)0x00000020U)
#define RCC_PERIPHCLK_USB ((uint32_t)0x00000040U)
#define RCC_PERIPHCLK_LPTIM1 ((uint32_t)0x00000080U)
#if defined (STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx)
#define RCC_PERIPHCLK_LCD ((uint32_t)0x00000800)
#define RCC_PERIPHCLK_LCD ((uint32_t)0x00000800U)
#endif
#if defined (STM32L072xx) || defined(STM32L073xx) || defined(STM32L082xx) || defined(STM32L083xx)
#define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00000100)
#define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00000100U)
#endif
#else /* !(STM32L011xx) && !(STM32L021xx) && !(STM32L031xx) && !(STM32L041xx) && !(STM32L051xx) && !(STM32L061xx) && !(STM32L071xx) && !(STM32L081xx) */
#if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx)
#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001U)
#endif
#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
#define RCC_PERIPHCLK_LPUART1 ((uint32_t)0x00000004)
#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000008)
#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002U)
#define RCC_PERIPHCLK_LPUART1 ((uint32_t)0x00000004U)
#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000008U)
#if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx)
#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000010)
#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000010U)
#endif
#define RCC_PERIPHCLK_RTC ((uint32_t)0x00000020)
#define RCC_PERIPHCLK_LPTIM1 ((uint32_t)0x00000080)
#define RCC_PERIPHCLK_RTC ((uint32_t)0x00000020U)
#define RCC_PERIPHCLK_LPTIM1 ((uint32_t)0x00000080U)
#if defined(STM32L071xx) || defined(STM32L081xx)
#define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00000100)
#define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00000100U)
#endif
#endif /* !(STM32L011xx) && !(STM32L021xx) && !(STM32L031xx) && !(STM32L041xx) && !(STM32L061xx) && !(STM32L071xx) && !(STM32L081xx) */
@ -273,7 +273,7 @@ typedef struct
/** @defgroup RCCEx_USART1_Clock_Source RCC USART1 Clock Source
* @{
*/
#define RCC_USART1CLKSOURCE_PCLK2 ((uint32_t)0x00000000)
#define RCC_USART1CLKSOURCE_PCLK2 ((uint32_t)0x00000000U)
#define RCC_USART1CLKSOURCE_SYSCLK RCC_CCIPR_USART1SEL_0
#define RCC_USART1CLKSOURCE_HSI RCC_CCIPR_USART1SEL_1
#define RCC_USART1CLKSOURCE_LSE (RCC_CCIPR_USART1SEL_0 | RCC_CCIPR_USART1SEL_1)
@ -285,7 +285,7 @@ typedef struct
/** @defgroup RCCEx_USART2_Clock_Source RCC USART2 Clock Source
* @{
*/
#define RCC_USART2CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
#define RCC_USART2CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
#define RCC_USART2CLKSOURCE_SYSCLK RCC_CCIPR_USART2SEL_0
#define RCC_USART2CLKSOURCE_HSI RCC_CCIPR_USART2SEL_1
#define RCC_USART2CLKSOURCE_LSE (RCC_CCIPR_USART2SEL_0 | RCC_CCIPR_USART2SEL_1)
@ -297,7 +297,7 @@ typedef struct
/** @defgroup RCCEx_LPUART1_Clock_Source RCC LPUART Clock Source
* @{
*/
#define RCC_LPUART1CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
#define RCC_LPUART1CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
#define RCC_LPUART1CLKSOURCE_SYSCLK RCC_CCIPR_LPUART1SEL_0
#define RCC_LPUART1CLKSOURCE_HSI RCC_CCIPR_LPUART1SEL_1
#define RCC_LPUART1CLKSOURCE_LSE (RCC_CCIPR_LPUART1SEL_0 | RCC_CCIPR_LPUART1SEL_1)
@ -309,7 +309,7 @@ typedef struct
/** @defgroup RCCEx_I2C1_Clock_Source RCC I2C1 Clock Source
* @{
*/
#define RCC_I2C1CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
#define RCC_I2C1CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
#define RCC_I2C1CLKSOURCE_SYSCLK RCC_CCIPR_I2C1SEL_0
#define RCC_I2C1CLKSOURCE_HSI RCC_CCIPR_I2C1SEL_1
@ -322,7 +322,7 @@ typedef struct
/** @defgroup RCCEx_I2C3_Clock_Source RCC I2C3 Clock Source
* @{
*/
#define RCC_I2C3CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
#define RCC_I2C3CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
#define RCC_I2C3CLKSOURCE_SYSCLK RCC_CCIPR_I2C3SEL_0
#define RCC_I2C3CLKSOURCE_HSI RCC_CCIPR_I2C3SEL_1
@ -336,8 +336,8 @@ typedef struct
/** @defgroup RCCEx_TIM_PRescaler_Selection RCC TIM Prescaler Selection
* @{
*/
#define RCC_TIMPRES_DESACTIVATED ((uint8_t)0x00)
#define RCC_TIMPRES_ACTIVATED ((uint8_t)0x01)
#define RCC_TIMPRES_DESACTIVATED ((uint8_t)0x00U)
#define RCC_TIMPRES_ACTIVATED ((uint8_t)0x01U)
/**
* @}
*/
@ -347,7 +347,7 @@ typedef struct
* @{
*/
#define RCC_USBCLKSOURCE_HSI48 RCC_CCIPR_HSI48SEL
#define RCC_USBCLKSOURCE_PLL ((uint32_t)0x00000000)
#define RCC_USBCLKSOURCE_PLL ((uint32_t)0x00000000U)
/**
* @}
@ -357,7 +357,7 @@ typedef struct
* @{
*/
#define RCC_RNGCLKSOURCE_HSI48 RCC_CCIPR_HSI48SEL
#define RCC_RNGCLKSOURCE_PLLCLK ((uint32_t)0x00000000)
#define RCC_RNGCLKSOURCE_PLLCLK ((uint32_t)0x00000000U)
/**
* @}
@ -366,9 +366,9 @@ typedef struct
/** @defgroup RCCEx_HSI48M_Clock_Source RCC HSI48M Clock Source
* @{
*/
#define RCC_FLAG_HSI48 SYSCFG_CFGR3_REF_HSI48_RDYF
#define RCC_FLAG_HSI48 SYSCFG_CFGR3_VREFINT_RDYF
#define RCC_HSI48M_PLL ((uint32_t)0x00000000)
#define RCC_HSI48M_PLL ((uint32_t)0x00000000U)
#define RCC_HSI48M_HSI48 RCC_CCIPR_HSI48SEL
@ -380,7 +380,7 @@ typedef struct
/** @defgroup RCC_HSI_Config RCC HSI Configuration
* @{
*/
#define RCC_HSI_OFF ((uint8_t)0x00)
#define RCC_HSI_OFF ((uint8_t)0x00U)
#define RCC_HSI_ON RCC_CR_HSION
#define RCC_HSI_DIV4 (RCC_CR_HSIDIVEN | RCC_CR_HSION)
#if defined(STM32L073xx) || defined(STM32L083xx) || \
@ -396,7 +396,7 @@ typedef struct
/** @defgroup RCCEx_LPTIM1_Clock_Source RCC LPTIM1 Clock Source
* @{
*/
#define RCC_LPTIM1CLKSOURCE_PCLK ((uint32_t)0x00000000)
#define RCC_LPTIM1CLKSOURCE_PCLK ((uint32_t)0x00000000U)
#define RCC_LPTIM1CLKSOURCE_LSI RCC_CCIPR_LPTIM1SEL_0
#define RCC_LPTIM1CLKSOURCE_HSI RCC_CCIPR_LPTIM1SEL_1
#define RCC_LPTIM1CLKSOURCE_LSE RCC_CCIPR_LPTIM1SEL
@ -409,7 +409,7 @@ typedef struct
* @{
*/
#define RCC_STOP_WAKEUPCLOCK_MSI ((uint32_t)0x00)
#define RCC_STOP_WAKEUPCLOCK_MSI ((uint32_t)0x00U)
#define RCC_STOP_WAKEUPCLOCK_HSI RCC_CFGR_STOPWUCK
/**
@ -420,7 +420,7 @@ typedef struct
* @{
*/
#define RCC_LSEDRIVE_LOW ((uint32_t)0x00000000)
#define RCC_LSEDRIVE_LOW ((uint32_t)0x00000000U)
#define RCC_LSEDRIVE_MEDIUMLOW RCC_CSR_LSEDRV_0
#define RCC_LSEDRIVE_MEDIUMHIGH RCC_CSR_LSEDRV_1
#define RCC_LSEDRIVE_HIGH RCC_CSR_LSEDRV
@ -441,7 +441,7 @@ typedef struct
/** @defgroup RCCEx_CRS_SynchroSource RCC CRS Synchro Source
* @{
*/
#define RCC_CRS_SYNC_SOURCE_GPIO ((uint32_t)0x00) /*!< Synchro Signal source GPIO */
#define RCC_CRS_SYNC_SOURCE_GPIO ((uint32_t)0x00U) /*!< Synchro Signal source GPIO */
#define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */
#define RCC_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/
@ -452,7 +452,7 @@ typedef struct
/** @defgroup RCCEx_CRS_SynchroDivider RCC CRS Synchro Divider
* @{
*/
#define RCC_CRS_SYNC_DIV1 ((uint32_t)0x00) /*!< Synchro Signal not divided (default) */
#define RCC_CRS_SYNC_DIV1 ((uint32_t)0x00U) /*!< Synchro Signal not divided (default) */
#define RCC_CRS_SYNC_DIV2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */
#define RCC_CRS_SYNC_DIV4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */
#define RCC_CRS_SYNC_DIV8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */
@ -468,7 +468,7 @@ typedef struct
/** @defgroup RCCEx_CRS_SynchroPolarity RCC CRS Synchro Polarity
* @{
*/
#define RCC_CRS_SYNC_POLARITY_RISING ((uint32_t)0x00) /*!< Synchro Active on rising edge (default) */
#define RCC_CRS_SYNC_POLARITY_RISING ((uint32_t)0x00U) /*!< Synchro Active on rising edge (default) */
#define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */
/**
@ -478,7 +478,7 @@ typedef struct
/** @defgroup RCCEx_CRS_ReloadValueDefault RCC CRS Reload Default Value
* @{
*/
#define RCC_CRS_RELOADVALUE_DEFAULT ((uint32_t)0xBB7F) /*!< The reset value of the RELOAD field corresponds
#define RCC_CRS_RELOADVALUE_DEFAULT ((uint32_t)0xBB7FU) /*!< The reset value of the RELOAD field corresponds
to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */
/**
@ -488,7 +488,7 @@ typedef struct
/** @defgroup RCCEx_CRS_ErrorLimitDefault RCC CRS Error Limit Default
* @{
*/
#define RCC_CRS_ERRORLIMIT_DEFAULT ((uint32_t)0x22) /*!< Default Frequency error limit */
#define RCC_CRS_ERRORLIMIT_DEFAULT ((uint32_t)0x22U) /*!< Default Frequency error limit */
/**
* @}
@ -497,7 +497,7 @@ typedef struct
/** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCC CRS HSI48 Calibration Default
* @{
*/
#define RCC_CRS_HSI48CALIBRATION_DEFAULT ((uint32_t)0x20) /*!< The default value is 32, which corresponds to the middle of the trimming interval.
#define RCC_CRS_HSI48CALIBRATION_DEFAULT ((uint32_t)0x20U) /*!< The default value is 32, which corresponds to the middle of the trimming interval.
The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value
corresponds to a higher output frequency */
@ -508,7 +508,7 @@ typedef struct
/** @defgroup RCCEx_CRS_FreqErrorDirection RCC CRS Frequency Error Direction
* @{
*/
#define RCC_CRS_FREQERRORDIR_UP ((uint32_t)0x00) /*!< Upcounting direction, the actual frequency is above the target */
#define RCC_CRS_FREQERRORDIR_UP ((uint32_t)0x00U) /*!< Upcounting direction, the actual frequency is above the target */
#define RCC_CRS_FREQERRORDIR_DOWN ((uint32_t)CRS_ISR_FEDIR) /*!< Downcounting direction, the actual frequency is below the target */
/**
@ -518,13 +518,13 @@ typedef struct
/** @defgroup RCCEx_CRS_Interrupt_Sources RCC CRS Interrupt Sources
* @{
*/
#define RCC_CRS_IT_SYNCOK CRS_ISR_SYNCOKF /*!< SYNC event OK */
#define RCC_CRS_IT_SYNCWARN CRS_ISR_SYNCWARNF /*!< SYNC warning */
#define RCC_CRS_IT_ERR CRS_ISR_ERRF /*!< error */
#define RCC_CRS_IT_ESYNC CRS_ISR_ESYNCF /*!< Expected SYNC */
#define RCC_CRS_IT_TRIMOVF CRS_ISR_TRIMOVF /*!< Trimming overflow or underflow */
#define RCC_CRS_IT_SYNCERR CRS_ISR_SYNCERR /*!< SYNC error */
#define RCC_CRS_IT_SYNCMISS CRS_ISR_SYNCMISS /*!< SYNC missed*/
#define RCC_CRS_IT_SYNCOK CRS_CR_SYNCOKIE /*!< SYNC event OK */
#define RCC_CRS_IT_SYNCWARN CRS_CR_SYNCWARNIE /*!< SYNC warning */
#define RCC_CRS_IT_ERR CRS_CR_ERRIE /*!< error */
#define RCC_CRS_IT_ESYNC CRS_CR_ESYNCIE /*!< Expected SYNC */
#define RCC_CRS_IT_TRIMOVF CRS_CR_ERRIE /*!< Trimming overflow or underflow */
#define RCC_CRS_IT_SYNCERR CRS_CR_ERRIE /*!< SYNC error */
#define RCC_CRS_IT_SYNCMISS CRS_CR_ERRIE /*!< SYNC missed*/
/**
* @}
@ -1626,10 +1626,10 @@ typedef struct
*/
#define __HAL_RCC_HSI48_ENABLE() do { SET_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON); \
RCC->APB2ENR |= RCC_APB2ENR_SYSCFGEN; \
SYSCFG->CFGR3 |= (SYSCFG_CFGR3_ENREF_HSI48 | SYSCFG_CFGR3_EN_VREFINT); \
SYSCFG->CFGR3 |= (SYSCFG_CFGR3_ENREF_HSI48); \
} while (0)
#define __HAL_RCC_HSI48_DISABLE() do { CLEAR_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON); \
SYSCFG->CFGR3 &= (uint32_t)~((uint32_t)(SYSCFG_CFGR3_ENREF_HSI48 | SYSCFG_CFGR3_EN_VREFINT)); \
SYSCFG->CFGR3 &= (uint32_t)~((uint32_t)(SYSCFG_CFGR3_ENREF_HSI48)); \
} while (0)
/** @brief Enable or disable the HSI48M DIV6 OUT .
* @note After reset, the HSI48Mhz (divided by 6) output is not available
@ -1784,11 +1784,11 @@ void HAL_RCCEx_DisableHSI48_VREFINT(void);
#define IS_RCC_CRS_SYNC_POLARITY(__POLARITY__) (((__POLARITY__) == RCC_CRS_SYNC_POLARITY_RISING) || \
((__POLARITY__) == RCC_CRS_SYNC_POLARITY_FALLING))
#define IS_RCC_CRS_RELOADVALUE(__VALUE__) (((__VALUE__) <= 0xFFFF))
#define IS_RCC_CRS_RELOADVALUE(__VALUE__) (((__VALUE__) <= 0xFFFFU))
#define IS_RCC_CRS_ERRORLIMIT(__VALUE__) (((__VALUE__) <= 0xFF))
#define IS_RCC_CRS_ERRORLIMIT(__VALUE__) (((__VALUE__) <= 0xFFU))
#define IS_RCC_CRS_HSI48CALIBRATION(__VALUE__) (((__VALUE__) <= 0x3F))
#define IS_RCC_CRS_HSI48CALIBRATION(__VALUE__) (((__VALUE__) <= 0x3FU))
#define IS_RCC_CRS_FREQERRORDIR(__DIR__) (((__DIR__) == RCC_CRS_FREQERRORDIR_UP) || \
((__DIR__) == RCC_CRS_FREQERRORDIR_DOWN))

12
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_rng.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx_hal_rng.c
* @author MCD Application Team
* @version V1.5.0
* @date 8-January-2016
* @version V1.7.0
* @date 31-May-2016
* @brief RNG HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Random Number Generator (RNG) peripheral:
@ -78,7 +78,7 @@
/** @addtogroup RNG_Private
* @{
*/
#define RNG_TIMEOUT_VALUE 1000
#define RNG_TIMEOUT_VALUE 1000U
/**
* @}
*/
@ -245,7 +245,7 @@ __weak void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng)
HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t *random32bit)
{
uint32_t tickstart = 0;
uint32_t tickstart = 0U;
HAL_StatusTypeDef status = HAL_OK;
/* Process Locked */
@ -396,7 +396,7 @@ uint32_t HAL_RNG_GetRandomNumber(RNG_HandleTypeDef *hrng)
}
else
{
return 0;
return 0U;
}
}
@ -409,7 +409,7 @@ uint32_t HAL_RNG_GetRandomNumber(RNG_HandleTypeDef *hrng)
*/
uint32_t HAL_RNG_GetRandomNumber_IT(RNG_HandleTypeDef *hrng)
{
uint32_t random32bit = 0;
uint32_t random32bit = 0U;
/* Process locked */
__HAL_LOCK(hrng);

14
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_rng.h
View File

@ -3,8 +3,8 @@
* @file stm32l0xx_hal_rng.h
* @author MCD Application Team
* @version V1.5.0
* @date 8-January-2016
* @version V1.7.0
* @date 31-May-2016
* @brief Header file of RNG HAL module.
******************************************************************************
* @attention
@ -70,11 +70,11 @@
*/
typedef enum
{
HAL_RNG_STATE_RESET = 0x00, /*!< RNG not yet initialized or disabled */
HAL_RNG_STATE_READY = 0x01, /*!< RNG initialized and ready for use */
HAL_RNG_STATE_BUSY = 0x02, /*!< RNG internal process is ongoing */
HAL_RNG_STATE_TIMEOUT = 0x03, /*!< RNG timeout state */
HAL_RNG_STATE_ERROR = 0x04 /*!< RNG error state */
HAL_RNG_STATE_RESET = 0x00U, /*!< RNG not yet initialized or disabled */
HAL_RNG_STATE_READY = 0x01U, /*!< RNG initialized and ready for use */
HAL_RNG_STATE_BUSY = 0x02U, /*!< RNG internal process is ongoing */
HAL_RNG_STATE_TIMEOUT = 0x03U, /*!< RNG timeout state */
HAL_RNG_STATE_ERROR = 0x04U /*!< RNG error state */
}HAL_RNG_StateTypeDef;

172
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_rtc.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx_hal_rtc.c
* @author MCD Application Team
* @version V1.5.0
* @date 8-January-2016
* @version V1.7.0
* @date 31-May-2016
* @brief RTC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Real Time Clock (RTC) peripheral:
@ -228,7 +228,7 @@ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc)
/* Configure the RTC PRER */
hrtc->Instance->PRER = (uint32_t)(hrtc->Init.SynchPrediv);
hrtc->Instance->PRER |= (uint32_t)(hrtc->Init.AsynchPrediv << 16);
hrtc->Instance->PRER |= (uint32_t)(hrtc->Init.AsynchPrediv << 16U);
/* Exit Initialization mode */
hrtc->Instance->ISR &= ((uint32_t)~RTC_ISR_INIT);
@ -254,7 +254,7 @@ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc)
*/
HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc)
{
uint32_t tickstart = 0;
uint32_t tickstart = 0U;
/* Check the parameters */
assert_param(IS_RTC_ALL_INSTANCE(hrtc->Instance));
@ -279,7 +279,7 @@ HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc)
else
{
/* Reset TR, DR and CR registers */
hrtc->Instance->TR = (uint32_t)0x00000000;
hrtc->Instance->TR = (uint32_t)0x00000000U;
hrtc->Instance->DR = ((uint32_t)(RTC_DR_WDU_0 | RTC_DR_MU_0 | RTC_DR_DU_0));
/* Reset All CR bits except CR[2:0] */
hrtc->Instance->CR &= RTC_CR_WUCKSEL;
@ -302,24 +302,24 @@ HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc)
}
/* Reset all RTC CR register bits */
hrtc->Instance->CR &= (uint32_t)0x00000000;
hrtc->Instance->CR &= (uint32_t)0x00000000U;
hrtc->Instance->WUTR = RTC_WUTR_WUT;
hrtc->Instance->PRER = ((uint32_t)(RTC_PRER_PREDIV_A | 0x000000FF));
hrtc->Instance->ALRMAR = (uint32_t)0x00000000;
hrtc->Instance->ALRMBR = (uint32_t)0x00000000;
hrtc->Instance->SHIFTR = (uint32_t)0x00000000;
hrtc->Instance->CALR = (uint32_t)0x00000000;
hrtc->Instance->ALRMASSR = (uint32_t)0x00000000;
hrtc->Instance->ALRMBSSR = (uint32_t)0x00000000;
hrtc->Instance->PRER = ((uint32_t)(RTC_PRER_PREDIV_A | 0x000000FFU));
hrtc->Instance->ALRMAR = (uint32_t)0x00000000U;
hrtc->Instance->ALRMBR = (uint32_t)0x00000000U;
hrtc->Instance->SHIFTR = (uint32_t)0x00000000U;
hrtc->Instance->CALR = (uint32_t)0x00000000U;
hrtc->Instance->ALRMASSR = (uint32_t)0x00000000U;
hrtc->Instance->ALRMBSSR = (uint32_t)0x00000000U;
/* Reset ISR register and exit initialization mode */
hrtc->Instance->ISR = (uint32_t)0x00000000;
hrtc->Instance->ISR = (uint32_t)0x00000000U;
/* Reset Tamper configuration register */
hrtc->Instance->TAMPCR = 0x00000000;
hrtc->Instance->TAMPCR = 0x00000000U;
/* Reset Option register */
hrtc->Instance->OR = 0x00000000;
hrtc->Instance->OR = 0x00000000U;
/* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)
@ -410,7 +410,7 @@ __weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc)
*/
HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
{
uint32_t tmpreg = 0;
uint32_t tmpreg = 0U;
/* Check the parameters */
assert_param(IS_RTC_FORMAT(Format));
@ -431,16 +431,16 @@ HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim
}
else
{
sTime->TimeFormat = 0x00;
sTime->TimeFormat = 0x00U;
assert_param(IS_RTC_HOUR24(sTime->Hours));
}
assert_param(IS_RTC_MINUTES(sTime->Minutes));
assert_param(IS_RTC_SECONDS(sTime->Seconds));
tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(sTime->Hours) << 16) | \
((uint32_t)RTC_ByteToBcd2(sTime->Minutes) << 8) | \
tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(sTime->Hours) << 16U) | \
((uint32_t)RTC_ByteToBcd2(sTime->Minutes) << 8U) | \
((uint32_t)RTC_ByteToBcd2(sTime->Seconds)) | \
(((uint32_t)sTime->TimeFormat) << 16));
(((uint32_t)sTime->TimeFormat) << 16U));
}
else
{
@ -452,15 +452,15 @@ HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim
}
else
{
sTime->TimeFormat = 0x00;
sTime->TimeFormat = 0x00U;
assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sTime->Hours)));
}
assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sTime->Minutes)));
assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sTime->Seconds)));
tmpreg = (((uint32_t)(sTime->Hours) << 16) | \
((uint32_t)(sTime->Minutes) << 8) | \
tmpreg = (((uint32_t)(sTime->Hours) << 16U) | \
((uint32_t)(sTime->Minutes) << 8U) | \
((uint32_t)sTime->Seconds) | \
((uint32_t)(sTime->TimeFormat) << 16));
((uint32_t)(sTime->TimeFormat) << 16U));
}
UNUSED(tmpreg);
/* Disable the write protection for RTC registers */
@ -545,7 +545,7 @@ HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim
*/
HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
{
uint32_t tmpreg = 0;
uint32_t tmpreg = 0U;
/* Check the parameters */
assert_param(IS_RTC_FORMAT(Format));
@ -560,10 +560,10 @@ HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim
tmpreg = (uint32_t)(hrtc->Instance->TR & RTC_TR_RESERVED_MASK);
/* Fill the structure fields with the read parameters */
sTime->Hours = (uint8_t)((tmpreg & (RTC_TR_HT | RTC_TR_HU)) >> 16);
sTime->Minutes = (uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >>8);
sTime->Hours = (uint8_t)((tmpreg & (RTC_TR_HT | RTC_TR_HU)) >> 16U);
sTime->Minutes = (uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >>8U);
sTime->Seconds = (uint8_t)(tmpreg & (RTC_TR_ST | RTC_TR_SU));
sTime->TimeFormat = (uint8_t)((tmpreg & (RTC_TR_PM)) >> 16);
sTime->TimeFormat = (uint8_t)((tmpreg & (RTC_TR_PM)) >> 16U);
/* Check the input parameters format */
if(Format == RTC_FORMAT_BIN)
@ -589,7 +589,7 @@ HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim
*/
HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
{
uint32_t datetmpreg = 0;
uint32_t datetmpreg = 0U;
/* Check the parameters */
assert_param(IS_RTC_FORMAT(Format));
@ -599,9 +599,9 @@ HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDat
hrtc->State = HAL_RTC_STATE_BUSY;
if((Format == RTC_FORMAT_BIN) && ((sDate->Month & 0x10) == 0x10))
if((Format == RTC_FORMAT_BIN) && ((sDate->Month & 0x10U) == 0x10U))
{
sDate->Month = (uint8_t)((sDate->Month & (uint8_t)~(0x10)) + (uint8_t)0x0A);
sDate->Month = (uint8_t)((sDate->Month & (uint8_t)~(0x10U)) + (uint8_t)0x0AU);
}
assert_param(IS_RTC_WEEKDAY(sDate->WeekDay));
@ -612,10 +612,10 @@ HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDat
assert_param(IS_RTC_MONTH(sDate->Month));
assert_param(IS_RTC_DATE(sDate->Date));
datetmpreg = (((uint32_t)RTC_ByteToBcd2(sDate->Year) << 16) | \
((uint32_t)RTC_ByteToBcd2(sDate->Month) << 8) | \
datetmpreg = (((uint32_t)RTC_ByteToBcd2(sDate->Year) << 16U) | \
((uint32_t)RTC_ByteToBcd2(sDate->Month) << 8U) | \
((uint32_t)RTC_ByteToBcd2(sDate->Date)) | \
((uint32_t)sDate->WeekDay << 13));
((uint32_t)sDate->WeekDay << 13U));
}
else
{
@ -625,10 +625,10 @@ HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDat
datetmpreg = RTC_Bcd2ToByte(sDate->Date);
assert_param(IS_RTC_DATE(datetmpreg));
datetmpreg = ((((uint32_t)sDate->Year) << 16) | \
(((uint32_t)sDate->Month) << 8) | \
datetmpreg = ((((uint32_t)sDate->Year) << 16U) | \
(((uint32_t)sDate->Month) << 8U) | \
((uint32_t)sDate->Date) | \
(((uint32_t)sDate->WeekDay) << 13));
(((uint32_t)sDate->WeekDay) << 13U));
}
/* Disable the write protection for RTC registers */
@ -700,7 +700,7 @@ HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDat
*/
HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
{
uint32_t datetmpreg = 0;
uint32_t datetmpreg = 0U;
/* Check the parameters */
assert_param(IS_RTC_FORMAT(Format));
@ -709,10 +709,10 @@ HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDat
datetmpreg = (uint32_t)(hrtc->Instance->DR & RTC_DR_RESERVED_MASK);
/* Fill the structure fields with the read parameters */
sDate->Year = (uint8_t)((datetmpreg & (RTC_DR_YT | RTC_DR_YU)) >> 16);
sDate->Month = (uint8_t)((datetmpreg & (RTC_DR_MT | RTC_DR_MU)) >> 8);
sDate->Year = (uint8_t)((datetmpreg & (RTC_DR_YT | RTC_DR_YU)) >> 16U);
sDate->Month = (uint8_t)((datetmpreg & (RTC_DR_MT | RTC_DR_MU)) >> 8U);
sDate->Date = (uint8_t)(datetmpreg & (RTC_DR_DT | RTC_DR_DU));
sDate->WeekDay = (uint8_t)((datetmpreg & (RTC_DR_WDU)) >> 13);
sDate->WeekDay = (uint8_t)((datetmpreg & (RTC_DR_WDU)) >> 13U);
/* Check the input parameters format */
if(Format == RTC_FORMAT_BIN)
@ -754,8 +754,8 @@ HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDat
*/
HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
{
uint32_t tickstart = 0;
uint32_t tmpreg = 0, subsecondtmpreg = 0;
uint32_t tickstart = 0U;
uint32_t tmpreg = 0U, subsecondtmpreg = 0U;
/* Check the parameters */
assert_param(IS_RTC_FORMAT(Format));
@ -779,7 +779,7 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA
}
else
{
sAlarm->AlarmTime.TimeFormat = 0x00;
sAlarm->AlarmTime.TimeFormat = 0x00U;
assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours));
}
assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes));
@ -794,11 +794,11 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA
assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay));
}
tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16) | \
((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8) | \
tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16U) | \
((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8U) | \
((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \
((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \
((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24) | \
((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16U) | \
((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24U) | \
((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
((uint32_t)sAlarm->AlarmMask));
}
@ -812,7 +812,7 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA
}
else
{
sAlarm->AlarmTime.TimeFormat = 0x00;
sAlarm->AlarmTime.TimeFormat = 0x00U;
assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));
}
@ -830,11 +830,11 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA
assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg));
}
tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16) | \
((uint32_t)(sAlarm->AlarmTime.Minutes) << 8) | \
tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16U) | \
((uint32_t)(sAlarm->AlarmTime.Minutes) << 8U) | \
((uint32_t) sAlarm->AlarmTime.Seconds) | \
((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \
((uint32_t)(sAlarm->AlarmDateWeekDay) << 24) | \
((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16U) | \
((uint32_t)(sAlarm->AlarmDateWeekDay) << 24U) | \
((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
((uint32_t)sAlarm->AlarmMask));
}
@ -938,8 +938,8 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA
*/
HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
{
uint32_t tickstart = 0;
uint32_t tmpreg = 0, subsecondtmpreg = 0;
uint32_t tickstart = 0U;
uint32_t tmpreg = 0U, subsecondtmpreg = 0U;
/* Check the parameters */
assert_param(IS_RTC_FORMAT(Format));
@ -963,7 +963,7 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef
}
else
{
sAlarm->AlarmTime.TimeFormat = 0x00;
sAlarm->AlarmTime.TimeFormat = 0x00U;
assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours));
}
assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes));
@ -977,11 +977,11 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef
{
assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay));
}
tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16) | \
((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8) | \
tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16U) | \
((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8U) | \
((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \
((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \
((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24) | \
((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16U) | \
((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24U) | \
((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
((uint32_t)sAlarm->AlarmMask));
}
@ -995,7 +995,7 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef
}
else
{
sAlarm->AlarmTime.TimeFormat = 0x00;
sAlarm->AlarmTime.TimeFormat = 0x00U;
assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));
}
@ -1012,11 +1012,11 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef
tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg));
}
tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16) | \
((uint32_t)(sAlarm->AlarmTime.Minutes) << 8) | \
tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16U) | \
((uint32_t)(sAlarm->AlarmTime.Minutes) << 8U) | \
((uint32_t) sAlarm->AlarmTime.Seconds) | \
((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \
((uint32_t)(sAlarm->AlarmDateWeekDay) << 24) | \
((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16U) | \
((uint32_t)(sAlarm->AlarmDateWeekDay) << 24U) | \
((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
((uint32_t)sAlarm->AlarmMask));
}
@ -1123,7 +1123,7 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef
*/
HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm)
{
uint32_t tickstart = 0;
uint32_t tickstart = 0U;
/* Check the parameters */
assert_param(IS_RTC_ALARM(Alarm));
@ -1217,7 +1217,7 @@ HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alar
*/
HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format)
{
uint32_t tmpreg = 0, subsecondtmpreg = 0;
uint32_t tmpreg = 0U, subsecondtmpreg = 0U;
/* Check the parameters */
assert_param(IS_RTC_FORMAT(Format));
@ -1232,12 +1232,12 @@ HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA
subsecondtmpreg = (uint32_t)((hrtc->Instance->ALRMASSR ) & RTC_ALRMASSR_SS);
/* Fill the structure with the read parameters */
sAlarm->AlarmTime.Hours = (uint32_t)((tmpreg & (RTC_ALRMAR_HT | RTC_ALRMAR_HU)) >> 16);
sAlarm->AlarmTime.Minutes = (uint32_t)((tmpreg & (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU)) >> 8);
sAlarm->AlarmTime.Hours = (uint32_t)((tmpreg & (RTC_ALRMAR_HT | RTC_ALRMAR_HU)) >> 16U);
sAlarm->AlarmTime.Minutes = (uint32_t)((tmpreg & (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU)) >> 8U);
sAlarm->AlarmTime.Seconds = (uint32_t)(tmpreg & (RTC_ALRMAR_ST | RTC_ALRMAR_SU));
sAlarm->AlarmTime.TimeFormat = (uint32_t)((tmpreg & RTC_ALRMAR_PM) >> 16);
sAlarm->AlarmTime.TimeFormat = (uint32_t)((tmpreg & RTC_ALRMAR_PM) >> 16U);
sAlarm->AlarmTime.SubSeconds = (uint32_t) subsecondtmpreg;
sAlarm->AlarmDateWeekDay = (uint32_t)((tmpreg & (RTC_ALRMAR_DT | RTC_ALRMAR_DU)) >> 24);
sAlarm->AlarmDateWeekDay = (uint32_t)((tmpreg & (RTC_ALRMAR_DT | RTC_ALRMAR_DU)) >> 24U);
sAlarm->AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMAR_WDSEL);
sAlarm->AlarmMask = (uint32_t)(tmpreg & RTC_ALARMMASK_ALL);
}
@ -1249,12 +1249,12 @@ HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA
subsecondtmpreg = (uint32_t)((hrtc->Instance->ALRMBSSR) & RTC_ALRMBSSR_SS);
/* Fill the structure with the read parameters */
sAlarm->AlarmTime.Hours = (uint32_t)((tmpreg & (RTC_ALRMBR_HT | RTC_ALRMBR_HU)) >> 16);
sAlarm->AlarmTime.Minutes = (uint32_t)((tmpreg & (RTC_ALRMBR_MNT | RTC_ALRMBR_MNU)) >> 8);
sAlarm->AlarmTime.Hours = (uint32_t)((tmpreg & (RTC_ALRMBR_HT | RTC_ALRMBR_HU)) >> 16U);
sAlarm->AlarmTime.Minutes = (uint32_t)((tmpreg & (RTC_ALRMBR_MNT | RTC_ALRMBR_MNU)) >> 8U);
sAlarm->AlarmTime.Seconds = (uint32_t)(tmpreg & (RTC_ALRMBR_ST | RTC_ALRMBR_SU));
sAlarm->AlarmTime.TimeFormat = (uint32_t)((tmpreg & RTC_ALRMBR_PM) >> 16);
sAlarm->AlarmTime.TimeFormat = (uint32_t)((tmpreg & RTC_ALRMBR_PM) >> 16U);
sAlarm->AlarmTime.SubSeconds = (uint32_t) subsecondtmpreg;
sAlarm->AlarmDateWeekDay = (uint32_t)((tmpreg & (RTC_ALRMBR_DT | RTC_ALRMBR_DU)) >> 24);
sAlarm->AlarmDateWeekDay = (uint32_t)((tmpreg & (RTC_ALRMBR_DT | RTC_ALRMBR_DU)) >> 24U);
sAlarm->AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMBR_WDSEL);
sAlarm->AlarmMask = (uint32_t)(tmpreg & RTC_ALARMMASK_ALL);
}
@ -1342,7 +1342,7 @@ HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t T
{
if(Timeout != HAL_MAX_DELAY)
{
if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
{
hrtc->State = HAL_RTC_STATE_TIMEOUT;
return HAL_TIMEOUT;
@ -1394,7 +1394,7 @@ HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t T
*/
HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc)
{
uint32_t tickstart = 0;
uint32_t tickstart = 0U;
/* Clear RSF flag */
hrtc->Instance->ISR &= (uint32_t)RTC_RSF_MASK;
@ -1461,7 +1461,7 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef* hrtc)
*/
HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc)
{
uint32_t tickstart = 0;
uint32_t tickstart = 0U;
/* Check if the Initialization mode is set */
if((hrtc->Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET)
@ -1491,15 +1491,15 @@ HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc)
*/
uint8_t RTC_ByteToBcd2(uint8_t Value)
{
uint32_t bcdhigh = 0;
uint32_t bcdhigh = 0U;
while(Value >= 10)
while(Value >= 10U)
{
bcdhigh++;
Value -= 10;
Value -= 10U;
}
return ((uint8_t)(bcdhigh << 4) | Value);
return ((uint8_t)(bcdhigh << 4U) | Value);
}
/**
@ -1509,9 +1509,9 @@ uint8_t RTC_ByteToBcd2(uint8_t Value)
*/
uint8_t RTC_Bcd2ToByte(uint8_t Value)
{
uint32_t tmp = 0;
tmp = ((uint8_t)(Value & (uint8_t)0xF0) >> (uint8_t)0x4) * 10;
return (tmp + (Value & (uint8_t)0x0F));
uint32_t tmp = 0U;
tmp = ((uint8_t)(Value & (uint8_t)0xF0U) >> (uint8_t)0x4U) * 10U;
return (tmp + (Value & (uint8_t)0x0FU));
}
/**

141
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_rtc.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx_hal_rtc.h
* @author MCD Application Team
* @version V1.5.0
* @date 8-January-2016
* @version V1.7.0
* @date 31-May-2016
* @brief Header file of RTC HAL module.
******************************************************************************
* @attention
@ -64,11 +64,11 @@
*/
typedef enum
{
HAL_RTC_STATE_RESET = 0x00, /*!< RTC not yet initialized or disabled */
HAL_RTC_STATE_READY = 0x01, /*!< RTC initialized and ready for use */
HAL_RTC_STATE_BUSY = 0x02, /*!< RTC process is ongoing */
HAL_RTC_STATE_TIMEOUT = 0x03, /*!< RTC timeout state */
HAL_RTC_STATE_ERROR = 0x04 /*!< RTC error state */
HAL_RTC_STATE_RESET = 0x00U, /*!< RTC not yet initialized or disabled */
HAL_RTC_STATE_READY = 0x01U, /*!< RTC initialized and ready for use */
HAL_RTC_STATE_BUSY = 0x02U, /*!< RTC process is ongoing */
HAL_RTC_STATE_TIMEOUT = 0x03U, /*!< RTC timeout state */
HAL_RTC_STATE_ERROR = 0x04U /*!< RTC error state */
}HAL_RTCStateTypeDef;
@ -204,7 +204,7 @@ typedef struct
/** @defgroup RTC_Hour_Formats RTC Hour Formats
* @{
*/
#define RTC_HOURFORMAT_24 ((uint32_t)0x00000000)
#define RTC_HOURFORMAT_24 ((uint32_t)0x00000000U)
#define RTC_HOURFORMAT_12 ((uint32_t)RTC_CR_FMT)
/**
@ -215,7 +215,7 @@ typedef struct
/** @defgroup RTC_Output_Polarity_Definitions RTC Output Polarity Definitions
* @{
*/
#define RTC_OUTPUT_POLARITY_HIGH ((uint32_t)0x00000000)
#define RTC_OUTPUT_POLARITY_HIGH ((uint32_t)0x00000000U)
#define RTC_OUTPUT_POLARITY_LOW ((uint32_t)RTC_CR_POL)
/**
@ -225,7 +225,7 @@ typedef struct
/** @defgroup RTC_Output_Type_ALARM_OUT RTC Output Type ALARM OUT
* @{
*/
#define RTC_OUTPUT_TYPE_OPENDRAIN ((uint32_t)0x00000000)
#define RTC_OUTPUT_TYPE_OPENDRAIN ((uint32_t)0x00000000U)
#define RTC_OUTPUT_TYPE_PUSHPULL ((uint32_t)RTC_OR_ALARMOUTTYPE)
/**
@ -235,7 +235,7 @@ typedef struct
/** @defgroup RTC_Output_ALARM_OUT_Remap RTC Output ALARM OUT Remap
* @{
*/
#define RTC_OUTPUT_REMAP_NONE ((uint32_t)0x00000000)
#define RTC_OUTPUT_REMAP_NONE ((uint32_t)0x00000000U)
#define RTC_OUTPUT_REMAP_POS1 ((uint32_t)RTC_OR_OUT_RMP)
/**
* @}
@ -244,8 +244,8 @@ typedef struct
/** @defgroup RTC_AM_PM_Definitions RTC AM PM Definitions
* @{
*/
#define RTC_HOURFORMAT12_AM ((uint8_t)0x00)
#define RTC_HOURFORMAT12_PM ((uint8_t)0x40)
#define RTC_HOURFORMAT12_AM ((uint8_t)0x00U)
#define RTC_HOURFORMAT12_PM ((uint8_t)0x40U)
/**
* @}
@ -256,7 +256,7 @@ typedef struct
*/
#define RTC_DAYLIGHTSAVING_SUB1H ((uint32_t)RTC_CR_SUB1H)
#define RTC_DAYLIGHTSAVING_ADD1H ((uint32_t)RTC_CR_ADD1H)
#define RTC_DAYLIGHTSAVING_NONE ((uint32_t)0x00000000)
#define RTC_DAYLIGHTSAVING_NONE ((uint32_t)0x00000000U)
/**
* @}
@ -265,19 +265,18 @@ typedef struct
/** @defgroup RTC_StoreOperation_Definitions RTC StoreOperation Definitions
* @{
*/
#define RTC_STOREOPERATION_RESET ((uint32_t)0x00000000)
#define RTC_STOREOPERATION_RESET ((uint32_t)0x00000000U)
#define RTC_STOREOPERATION_SET ((uint32_t)RTC_CR_BCK)
/**
* @}
*/
/** @defgroup RTC_Input_parameter_format_definitions RTC Input parameter format definitions
/** @defgroup RTC_Input_parameter_format_definitions RTC Input Parameter Format Definitions
* @{
*/
#define RTC_FORMAT_BIN ((uint32_t)0x000000000)
#define RTC_FORMAT_BCD ((uint32_t)0x000000001)
#define RTC_FORMAT_BIN ((uint32_t)0x000000000U)
#define RTC_FORMAT_BCD ((uint32_t)0x000000001U)
/**
* @}
@ -288,18 +287,18 @@ typedef struct
*/
/* Coded in BCD format */
#define RTC_MONTH_JANUARY ((uint8_t)0x01)
#define RTC_MONTH_FEBRUARY ((uint8_t)0x02)
#define RTC_MONTH_MARCH ((uint8_t)0x03)
#define RTC_MONTH_APRIL ((uint8_t)0x04)
#define RTC_MONTH_MAY ((uint8_t)0x05)
#define RTC_MONTH_JUNE ((uint8_t)0x06)
#define RTC_MONTH_JULY ((uint8_t)0x07)
#define RTC_MONTH_AUGUST ((uint8_t)0x08)
#define RTC_MONTH_SEPTEMBER ((uint8_t)0x09)
#define RTC_MONTH_OCTOBER ((uint8_t)0x10)
#define RTC_MONTH_NOVEMBER ((uint8_t)0x11)
#define RTC_MONTH_DECEMBER ((uint8_t)0x12)
#define RTC_MONTH_JANUARY ((uint8_t)0x01U)
#define RTC_MONTH_FEBRUARY ((uint8_t)0x02U)
#define RTC_MONTH_MARCH ((uint8_t)0x03U)
#define RTC_MONTH_APRIL ((uint8_t)0x04U)
#define RTC_MONTH_MAY ((uint8_t)0x05U)
#define RTC_MONTH_JUNE ((uint8_t)0x06U)
#define RTC_MONTH_JULY ((uint8_t)0x07U)
#define RTC_MONTH_AUGUST ((uint8_t)0x08U)
#define RTC_MONTH_SEPTEMBER ((uint8_t)0x09U)
#define RTC_MONTH_OCTOBER ((uint8_t)0x10U)
#define RTC_MONTH_NOVEMBER ((uint8_t)0x11U)
#define RTC_MONTH_DECEMBER ((uint8_t)0x12U)
/**
* @}
@ -308,13 +307,13 @@ typedef struct
/** @defgroup RTC_WeekDay_Definitions RTC WeekDay Definitions
* @{
*/
#define RTC_WEEKDAY_MONDAY ((uint8_t)0x01)
#define RTC_WEEKDAY_TUESDAY ((uint8_t)0x02)
#define RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03)
#define RTC_WEEKDAY_THURSDAY ((uint8_t)0x04)
#define RTC_WEEKDAY_FRIDAY ((uint8_t)0x05)
#define RTC_WEEKDAY_SATURDAY ((uint8_t)0x06)
#define RTC_WEEKDAY_SUNDAY ((uint8_t)0x07)
#define RTC_WEEKDAY_MONDAY ((uint8_t)0x01U)
#define RTC_WEEKDAY_TUESDAY ((uint8_t)0x02U)
#define RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03U)
#define RTC_WEEKDAY_THURSDAY ((uint8_t)0x04U)
#define RTC_WEEKDAY_FRIDAY ((uint8_t)0x05U)
#define RTC_WEEKDAY_SATURDAY ((uint8_t)0x06U)
#define RTC_WEEKDAY_SUNDAY ((uint8_t)0x07U)
/**
* @}
@ -323,7 +322,7 @@ typedef struct
/** @defgroup RTC_AlarmDateWeekDay_Definitions RTC AlarmDateWeekDay Definitions
* @{
*/
#define RTC_ALARMDATEWEEKDAYSEL_DATE ((uint32_t)0x00000000)
#define RTC_ALARMDATEWEEKDAYSEL_DATE ((uint32_t)0x00000000U)
#define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY RTC_ALRMAR_WDSEL
/**
@ -333,7 +332,7 @@ typedef struct
/** @defgroup RTC_AlarmMask_Definitions RTC AlarmMask Definitions
* @{
*/
#define RTC_ALARMMASK_NONE ((uint32_t)0x00000000)
#define RTC_ALARMMASK_NONE ((uint32_t)0x00000000U)
#define RTC_ALARMMASK_DATEWEEKDAY RTC_ALRMAR_MSK4
#define RTC_ALARMMASK_HOURS RTC_ALRMAR_MSK3
#define RTC_ALARMMASK_MINUTES RTC_ALRMAR_MSK2
@ -362,7 +361,7 @@ typedef struct
/** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions RTC Alarm Sub Seconds Masks Definitions
* @{
*/
#define RTC_ALARMSUBSECONDMASK_ALL ((uint32_t)0x00000000) /*!< All Alarm SS fields are masked.
#define RTC_ALARMSUBSECONDMASK_ALL ((uint32_t)0x00000000U) /*!< All Alarm SS fields are masked.
There is no comparison on sub seconds
for Alarm */
#define RTC_ALARMSUBSECONDMASK_SS14_1 RTC_ALRMASSR_MASKSS_0 /*!< SS[14:1] are don't care in Alarm
@ -402,11 +401,11 @@ typedef struct
/** @defgroup RTC_Interrupts_Definitions RTC Interrupts Definitions
* @{
*/
#define RTC_IT_TS ((uint32_t)RTC_CR_TSIE)
#define RTC_IT_WUT ((uint32_t)RTC_CR_WUTIE)
#define RTC_IT_ALRB ((uint32_t)RTC_CR_ALRBIE)
#define RTC_IT_ALRA ((uint32_t)RTC_CR_ALRAIE)
#define RTC_IT_TAMP ((uint32_t)RTC_TAMPCR_TAMPIE) /* Used only to Enable the Tamper Interrupt */
#define RTC_IT_TS ((uint32_t)RTC_CR_TSIE) /*!< Enable Timestamp Interrupt */
#define RTC_IT_WUT ((uint32_t)RTC_CR_WUTIE) /*!< Enable Wakeup timer Interrupt */
#define RTC_IT_ALRA ((uint32_t)RTC_CR_ALRAIE) /*!< Enable Alarm A Interrupt */
#define RTC_IT_ALRB ((uint32_t)RTC_CR_ALRBIE) /*!< Enable Alarm B Interrupt */
#define RTC_IT_TAMP ((uint32_t)RTC_TAMPCR_TAMPIE) /*!< Enable all Tamper Interrupt */
#if defined (STM32L063xx) || defined (STM32L062xx) || defined (STM32L061xx) || \
defined (STM32L053xx) || defined (STM32L052xx) || defined (STM32L051xx) ||\
@ -414,14 +413,14 @@ typedef struct
defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx) || \
defined (STM32L031xx) || defined (STM32L041xx)
#define RTC_IT_TAMP1 ((uint32_t)RTC_TAMPCR_TAMP1IE)
#define RTC_IT_TAMP1 ((uint32_t)RTC_TAMPCR_TAMP1IE) /*!< Enable Tamper 1 Interrupt */
#endif /* (STM32L063xx) || (STM32L062xx) || (STM32L061xx) ||
* (STM32L053xx) || (STM32L052xx) || (STM32L051xx) ||
* (STM32L083xx) || (STM32L082xx) || (STM32L081xx) ||
* (STM32L073xx) || (STM32L072xx) || (STM32L071xx) ||
* (STM32L031xx) || (STM32L041xx)
*/
#define RTC_IT_TAMP2 ((uint32_t)RTC_TAMPCR_TAMP2IE)
#define RTC_IT_TAMP2 ((uint32_t)RTC_TAMPCR_TAMP2IE) /*!< Enable Tamper 2 Interrupt */
/**
* @}
*/
@ -483,9 +482,9 @@ typedef struct
*/
#define __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__) \
do{ \
(__HANDLE__)->Instance->WPR = 0xCA; \
(__HANDLE__)->Instance->WPR = 0x53; \
} while(0)
(__HANDLE__)->Instance->WPR = 0xCAU; \
(__HANDLE__)->Instance->WPR = 0x53U; \
} while(0U)
/**
* @brief Enable the write protection for RTC registers.
@ -494,8 +493,8 @@ typedef struct
*/
#define __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__) \
do{ \
(__HANDLE__)->Instance->WPR = 0xFF; \
} while(0)
(__HANDLE__)->Instance->WPR = 0xFFU; \
} while(0U)
/**
* @brief Enable the RTC ALARMA peripheral.
@ -556,7 +555,7 @@ typedef struct
* @arg RTC_IT_ALRB: Alarm B interrupt
* @retval None
*/
#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR)& ((__INTERRUPT__)>> 4)) != RESET)? SET : RESET)
#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR)& ((__INTERRUPT__)>> 4U)) != RESET)? SET : RESET)
/**
* @brief Check whether the specified RTC Alarm interrupt has been enabled or not.
@ -645,13 +644,19 @@ typedef struct
* @brief Enable rising & falling edge trigger on the RTC Alarm associated Exti line.
* @retval None.
*/
#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE() do { __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE();__HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE(); } while(0);
#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE() do { \
__HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE(); \
__HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE(); \
} while(0U)
/**
* @brief Disable rising & falling edge trigger on the RTC Alarm associated Exti line.
* @retval None.
*/
#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE() do { __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE();__HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE(); } while(0);
#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
__HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE(); \
__HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE(); \
} while(0U)
/**
* @brief Check whether the RTC Alarm associated Exti line interrupt flag is set or not.
@ -757,10 +762,10 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc);
#define RTC_DR_RESERVED_MASK ((uint32_t) (RTC_DR_YT | RTC_DR_YU | RTC_DR_WDU | \
RTC_DR_MT | RTC_DR_MU | RTC_DR_DT | \
RTC_DR_DU))
#define RTC_INIT_MASK ((uint32_t)0xFFFFFFFF)
#define RTC_INIT_MASK ((uint32_t)0xFFFFFFFFU)
#define RTC_RSF_MASK ((uint32_t)~(RTC_ISR_INIT | RTC_ISR_RSF))
#define RTC_TIMEOUT_VALUE 1000
#define RTC_TIMEOUT_VALUE 1000U
#define RTC_EXTI_LINE_ALARM_EVENT ((uint32_t)EXTI_IMR_IM17) /*!< External interrupt line 17 Connected to the RTC Alarm event */
@ -801,11 +806,11 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc);
#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_FORMAT_BIN) || ((FORMAT) == RTC_FORMAT_BCD))
#define IS_RTC_YEAR(YEAR) ((YEAR) <= (uint32_t)99)
#define IS_RTC_YEAR(YEAR) ((YEAR) <= (uint32_t)99U)
#define IS_RTC_MONTH(MONTH) (((MONTH) >= (uint32_t)1) && ((MONTH) <= (uint32_t)12))
#define IS_RTC_MONTH(MONTH) (((MONTH) >= (uint32_t)1U) && ((MONTH) <= (uint32_t)12U))
#define IS_RTC_DATE(DATE) (((DATE) >= (uint32_t)1) && ((DATE) <= (uint32_t)31))
#define IS_RTC_DATE(DATE) (((DATE) >= (uint32_t)1U) && ((DATE) <= (uint32_t)31U))
#define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \
((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \
@ -815,7 +820,7 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc);
((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || \
((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) >(uint32_t) 0) && ((DATE) <= (uint32_t)31))
#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) >(uint32_t)0U) && ((DATE) <= (uint32_t)31U))
#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \
((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \
@ -851,17 +856,17 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc);
((MASK) == RTC_ALARMSUBSECONDMASK_SS14) || \
((MASK) == RTC_ALARMSUBSECONDMASK_NONE))
#define IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= (uint32_t)0x7F)
#define IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= (uint32_t)0x7FU)
#define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= (uint32_t)0x7FFF)
#define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= (uint32_t)0x7FFFU)
#define IS_RTC_HOUR12(HOUR) (((HOUR) > (uint32_t)0) && ((HOUR) <= (uint32_t)12))
#define IS_RTC_HOUR12(HOUR) (((HOUR) > (uint32_t)0U) && ((HOUR) <= (uint32_t)12U))
#define IS_RTC_HOUR24(HOUR) ((HOUR) <= (uint32_t)23)
#define IS_RTC_HOUR24(HOUR) ((HOUR) <= (uint32_t)23U)
#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= (uint32_t)59)
#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= (uint32_t)59U)
#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= (uint32_t)59)
#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= (uint32_t)59U)
/**
* @}

117
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_rtc_ex.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx_hal_rtc_ex.c
* @author MCD Application Team
* @version V1.5.0
* @date 8-January-2016
* @version V1.7.0
* @date 31-May-2016
* @brief Extended RTC HAL module driver.
*
* This file provides firmware functions to manage the following
@ -170,7 +170,7 @@
*/
HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
{
uint32_t tmpreg = 0;
uint32_t tmpreg = 0U;
/* Check the parameters */
assert_param(IS_TIMESTAMP_EDGE(TimeStampEdge));
@ -225,7 +225,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeS
*/
HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
{
uint32_t tmpreg = 0;
uint32_t tmpreg = 0U;
/* Check the parameters */
assert_param(IS_TIMESTAMP_EDGE(TimeStampEdge));
@ -275,7 +275,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t Ti
*/
HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc)
{
uint32_t tmpreg = 0;
uint32_t tmpreg = 0U;
/* Process Locked */
__HAL_LOCK(hrtc);
@ -319,7 +319,7 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc)
*/
HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef* sTimeStamp, RTC_DateTypeDef* sTimeStampDate, uint32_t Format)
{
uint32_t tmptime = 0, tmpdate = 0;
uint32_t tmptime = 0U, tmpdate = 0U;
/* Check the parameters */
assert_param(IS_RTC_FORMAT(Format));
@ -329,17 +329,17 @@ HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDe
tmpdate = (uint32_t)(hrtc->Instance->TSDR & RTC_DR_RESERVED_MASK);
/* Fill the Time structure fields with the read parameters */
sTimeStamp->Hours = (uint8_t)((tmptime & (RTC_TR_HT | RTC_TR_HU)) >> 16);
sTimeStamp->Minutes = (uint8_t)((tmptime & (RTC_TR_MNT | RTC_TR_MNU)) >> 8);
sTimeStamp->Hours = (uint8_t)((tmptime & (RTC_TR_HT | RTC_TR_HU)) >> 16U);
sTimeStamp->Minutes = (uint8_t)((tmptime & (RTC_TR_MNT | RTC_TR_MNU)) >> 8U);
sTimeStamp->Seconds = (uint8_t)(tmptime & (RTC_TR_ST | RTC_TR_SU));
sTimeStamp->TimeFormat = (uint8_t)((tmptime & (RTC_TR_PM)) >> 16);
sTimeStamp->TimeFormat = (uint8_t)((tmptime & (RTC_TR_PM)) >> 16U);
sTimeStamp->SubSeconds = (uint32_t) hrtc->Instance->TSSSR;
/* Fill the Date structure fields with the read parameters */
sTimeStampDate->Year = 0;
sTimeStampDate->Month = (uint8_t)((tmpdate & (RTC_DR_MT | RTC_DR_MU)) >> 8);
sTimeStampDate->Year = 0U;
sTimeStampDate->Month = (uint8_t)((tmpdate & (RTC_DR_MT | RTC_DR_MU)) >> 8U);
sTimeStampDate->Date = (uint8_t)(tmpdate & (RTC_DR_DT | RTC_DR_DU));
sTimeStampDate->WeekDay = (uint8_t)((tmpdate & (RTC_DR_WDU)) >> 13);
sTimeStampDate->WeekDay = (uint8_t)((tmpdate & (RTC_DR_WDU)) >> 13U);
/* Check the input parameters format */
if(Format == RTC_FORMAT_BIN)
@ -370,7 +370,7 @@ HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDe
*/
HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper)
{
uint32_t tmpreg = 0;
uint32_t tmpreg = 0U;
/* Check the parameters */
assert_param( IS_RTC_TAMPER(sTamper->Tamper));
@ -391,19 +391,19 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef
/* Configure the tamper trigger */
if(sTamper->Trigger != RTC_TAMPERTRIGGER_RISINGEDGE)
{
sTamper->Trigger = (uint32_t)(sTamper->Tamper << 1);
sTamper->Trigger = (uint32_t)(sTamper->Tamper << 1U);
}
if(sTamper->NoErase != RTC_TAMPER_ERASE_BACKUP_ENABLE)
{
sTamper->NoErase = 0;
sTamper->NoErase = 0U;
#if defined (STM32L063xx) || defined (STM32L062xx) || defined (STM32L061xx) || \
defined (STM32L053xx) || defined (STM32L052xx) || defined (STM32L051xx) ||\
defined (STM32L083xx) || defined (STM32L082xx) || defined (STM32L081xx) || \
defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx) || \
defined (STM32L031xx) || defined (STM32L041xx)
if((sTamper->Tamper & RTC_TAMPER_1) != 0)
if((sTamper->Tamper & RTC_TAMPER_1) != 0U)
{
sTamper->NoErase |= RTC_TAMPCR_TAMP1NOERASE;
}
@ -414,7 +414,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef
* (STM32L031xx) || (STM32L041xx)
*/
if((sTamper->Tamper & RTC_TAMPER_2) != 0)
if((sTamper->Tamper & RTC_TAMPER_2) != 0U)
{
sTamper->NoErase |= RTC_TAMPCR_TAMP2NOERASE;
}
@ -422,7 +422,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef
defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx) || \
defined (STM32L031xx) || defined (STM32L041xx) || defined (STM32L011xx) || defined (STM32L021xx)
if((sTamper->Tamper & RTC_TAMPER_3) != 0)
if((sTamper->Tamper & RTC_TAMPER_3) != 0U)
{
sTamper->NoErase |= RTC_TAMPCR_TAMP3NOERASE;
}
@ -434,7 +434,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef
if(sTamper->MaskFlag != RTC_TAMPERMASK_FLAG_DISABLE)
{
sTamper->MaskFlag = 0;
sTamper->MaskFlag = 0U;
#if defined (STM32L063xx) || defined (STM32L062xx) || defined (STM32L061xx) || \
defined (STM32L053xx) || defined (STM32L052xx) || defined (STM32L051xx) ||\
@ -442,7 +442,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef
defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx) || \
defined (STM32L031xx) || defined (STM32L041xx)
if((sTamper->Tamper & RTC_TAMPER_1) != 0)
if((sTamper->Tamper & RTC_TAMPER_1) != 0U)
{
sTamper->MaskFlag |= RTC_TAMPCR_TAMP1MF;
}
@ -453,7 +453,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef
* (STM32L031xx) || (STM32L041xx)
*/
if((sTamper->Tamper & RTC_TAMPER_2) != 0)
if((sTamper->Tamper & RTC_TAMPER_2) != 0U)
{
sTamper->MaskFlag |= RTC_TAMPCR_TAMP2MF;
}
@ -461,7 +461,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef
defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx) || \
defined (STM32L031xx) || defined (STM32L041xx) || defined (STM32L011xx) || defined (STM32L021xx)
if((sTamper->Tamper & RTC_TAMPER_3) != 0)
if((sTamper->Tamper & RTC_TAMPER_3) != 0U)
{
sTamper->MaskFlag |= RTC_TAMPCR_TAMP3MF;
}
@ -477,7 +477,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef
#if defined (STM32L063xx) || defined (STM32L062xx) || defined (STM32L061xx) || \
defined (STM32L053xx) || defined (STM32L052xx) || defined (STM32L051xx)
hrtc->Instance->TAMPCR &= ((uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1) | RTC_TAMPCR_TAMPTS |\
hrtc->Instance->TAMPCR &= ((uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1U) | RTC_TAMPCR_TAMPTS |\
RTC_TAMPCR_TAMPFREQ | RTC_TAMPCR_TAMPFLT | RTC_TAMPCR_TAMPPRCH |\
RTC_TAMPCR_TAMPPUDIS | RTC_TAMPCR_TAMPIE | RTC_TAMPCR_TAMP1IE |\
RTC_TAMPCR_TAMP2IE | RTC_TAMPCR_TAMP1NOERASE | RTC_TAMPCR_TAMP2NOERASE|\
@ -486,7 +486,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef
#elif defined (STM32L083xx) || defined (STM32L082xx) || defined (STM32L081xx) || \
defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx) || \
defined (STM32L031xx) || defined (STM32L041xx)
hrtc->Instance->TAMPCR &= ((uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1) | RTC_TAMPCR_TAMPTS |\
hrtc->Instance->TAMPCR &= ((uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1U) | RTC_TAMPCR_TAMPTS |\
RTC_TAMPCR_TAMPFREQ | RTC_TAMPCR_TAMPFLT | RTC_TAMPCR_TAMPPRCH |\
RTC_TAMPCR_TAMPPUDIS | RTC_TAMPCR_TAMPIE | RTC_TAMPCR_TAMP1IE |\
RTC_TAMPCR_TAMP2IE | RTC_TAMPCR_TAMP3IE | RTC_TAMPCR_TAMP1NOERASE |\
@ -494,7 +494,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef
RTC_TAMPCR_TAMP2MF | RTC_TAMPCR_TAMP3MF));
#elif defined (STM32L011xx) || defined (STM32L021xx)
hrtc->Instance->TAMPCR &= ((uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1) | RTC_TAMPCR_TAMPTS |\
hrtc->Instance->TAMPCR &= ((uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1U) | RTC_TAMPCR_TAMPTS |\
RTC_TAMPCR_TAMPFREQ | RTC_TAMPCR_TAMPFLT | RTC_TAMPCR_TAMPPRCH |\
RTC_TAMPCR_TAMPPUDIS | RTC_TAMPCR_TAMPIE |\
RTC_TAMPCR_TAMP2IE | RTC_TAMPCR_TAMP3IE |\
@ -523,7 +523,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef
*/
HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper)
{
uint32_t tmpreg = 0;
uint32_t tmpreg = 0U;
/* Check the parameters */
assert_param( IS_RTC_TAMPER(sTamper->Tamper));
@ -545,12 +545,12 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperType
/* Configure the tamper trigger */
if(sTamper->Trigger != RTC_TAMPERTRIGGER_RISINGEDGE)
{
sTamper->Trigger = (uint32_t)(sTamper->Tamper << 1);
sTamper->Trigger = (uint32_t)(sTamper->Tamper << 1U);
}
if(sTamper->NoErase != RTC_TAMPER_ERASE_BACKUP_ENABLE)
{
sTamper->NoErase = 0;
sTamper->NoErase = 0U;
#if defined (STM32L063xx) || defined (STM32L062xx) || defined (STM32L061xx) || \
defined (STM32L053xx) || defined (STM32L052xx) || defined (STM32L051xx) ||\
@ -558,7 +558,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperType
defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx) || \
defined (STM32L031xx) || defined (STM32L041xx)
if((sTamper->Tamper & RTC_TAMPER_1) != 0)
if((sTamper->Tamper & RTC_TAMPER_1) != 0U)
{
sTamper->NoErase |= RTC_TAMPCR_TAMP1NOERASE;
}
@ -570,7 +570,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperType
*/
if((sTamper->Tamper & RTC_TAMPER_2) != 0)
if((sTamper->Tamper & RTC_TAMPER_2) != 0U)
{
sTamper->NoErase |= RTC_TAMPCR_TAMP2NOERASE;
}
@ -578,7 +578,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperType
defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx) || \
defined (STM32L031xx) || defined (STM32L041xx) || defined (STM32L011xx) || defined (STM32L021xx)
if((sTamper->Tamper & RTC_TAMPER_3) != 0)
if((sTamper->Tamper & RTC_TAMPER_3) != 0U)
{
sTamper->NoErase |= RTC_TAMPCR_TAMP3NOERASE;
}
@ -589,14 +589,14 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperType
if(sTamper->MaskFlag != RTC_TAMPERMASK_FLAG_DISABLE)
{
sTamper->MaskFlag = 0;
sTamper->MaskFlag = 0U;
#if defined (STM32L063xx) || defined (STM32L062xx) || defined (STM32L061xx) || \
defined (STM32L053xx) || defined (STM32L052xx) || defined (STM32L051xx) ||\
defined (STM32L083xx) || defined (STM32L082xx) || defined (STM32L081xx) || \
defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx) || \
defined (STM32L031xx) || defined (STM32L041xx)
if((sTamper->Tamper & RTC_TAMPER_1) != 0)
if((sTamper->Tamper & RTC_TAMPER_1) != 0U)
{
sTamper->MaskFlag |= RTC_TAMPCR_TAMP1MF;
}
@ -607,7 +607,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperType
* (STM32L031xx) || (STM32L041xx)
*/
if((sTamper->Tamper & RTC_TAMPER_2) != 0)
if((sTamper->Tamper & RTC_TAMPER_2) != 0U)
{
sTamper->MaskFlag |= RTC_TAMPCR_TAMP2MF;
}
@ -615,7 +615,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperType
defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx) || \
defined (STM32L031xx) || defined (STM32L041xx) || defined (STM32L011xx) || defined (STM32L021xx)
if((sTamper->Tamper & RTC_TAMPER_3) != 0)
if((sTamper->Tamper & RTC_TAMPER_3) != 0U)
{
sTamper->MaskFlag |= RTC_TAMPCR_TAMP3MF;
}
@ -631,7 +631,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperType
#if defined (STM32L063xx) || defined (STM32L062xx) || defined (STM32L061xx) || \
defined (STM32L053xx) || defined (STM32L052xx) || defined (STM32L051xx)
hrtc->Instance->TAMPCR &= (uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1) | RTC_TAMPCR_TAMPTS |\
hrtc->Instance->TAMPCR &= (uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1U) | RTC_TAMPCR_TAMPTS |\
RTC_TAMPCR_TAMPFREQ | RTC_TAMPCR_TAMPFLT | RTC_TAMPCR_TAMPPRCH |\
RTC_TAMPCR_TAMPPUDIS | RTC_TAMPCR_TAMPIE | RTC_TAMPCR_TAMP1IE |\
RTC_TAMPCR_TAMP2IE | RTC_TAMPCR_TAMP1NOERASE | RTC_TAMPCR_TAMP2NOERASE |\
@ -640,7 +640,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperType
#elif defined (STM32L083xx) || defined (STM32L082xx) || defined (STM32L081xx) || \
defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx) || \
defined (STM32L031xx) || defined (STM32L041xx)
hrtc->Instance->TAMPCR &= (uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1) | RTC_TAMPCR_TAMPTS |\
hrtc->Instance->TAMPCR &= (uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1U) | RTC_TAMPCR_TAMPTS |\
RTC_TAMPCR_TAMPFREQ | RTC_TAMPCR_TAMPFLT | RTC_TAMPCR_TAMPPRCH |\
RTC_TAMPCR_TAMPPUDIS | RTC_TAMPCR_TAMPIE | RTC_TAMPCR_TAMP1IE |\
RTC_TAMPCR_TAMP2IE | RTC_TAMPCR_TAMP3IE | RTC_TAMPCR_TAMP1NOERASE |\
@ -648,7 +648,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperType
RTC_TAMPCR_TAMP2MF | RTC_TAMPCR_TAMP3MF);
#elif defined (STM32L011xx) || defined (STM32L021xx)
hrtc->Instance->TAMPCR &= (uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1) | RTC_TAMPCR_TAMPTS |\
hrtc->Instance->TAMPCR &= (uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1U) | RTC_TAMPCR_TAMPTS |\
RTC_TAMPCR_TAMPFREQ | RTC_TAMPCR_TAMPFLT | RTC_TAMPCR_TAMPPRCH |\
RTC_TAMPCR_TAMPPUDIS | RTC_TAMPCR_TAMPIE |\
RTC_TAMPCR_TAMP2IE | RTC_TAMPCR_TAMP3IE |\
@ -698,7 +698,7 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t T
defined (STM32L083xx) || defined (STM32L082xx) || defined (STM32L081xx) || \
defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx) || \
defined (STM32L031xx) || defined (STM32L041xx)
if ((Tamper & RTC_TAMPER_1) != 0)
if ((Tamper & RTC_TAMPER_1) != 0U)
{
/* Disable the Tamper1 interrupt */
hrtc->Instance->TAMPCR &= ((uint32_t)~(RTC_IT_TAMP | RTC_IT_TAMP1));
@ -711,7 +711,7 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t T
* (STM32L031xx) || (STM32L041xx)
*/
if ((Tamper & RTC_TAMPER_2) != 0)
if ((Tamper & RTC_TAMPER_2) != 0U)
{
/* Disable the Tamper2 interrupt */
hrtc->Instance->TAMPCR &= ((uint32_t)~(RTC_IT_TAMP | RTC_IT_TAMP2));
@ -721,7 +721,7 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t T
defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx) || \
defined (STM32L031xx) || defined (STM32L041xx) || defined (STM32L011xx) || defined (STM32L021xx)
if ((Tamper & RTC_TAMPER_3) != 0)
if ((Tamper & RTC_TAMPER_3) != 0U)
{
/* Disable the Tamper3 interrupt */
hrtc->Instance->TAMPCR &= ((uint32_t)~(RTC_IT_TAMP | RTC_IT_TAMP3));
@ -925,7 +925,7 @@ HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint3
if(Timeout != HAL_MAX_DELAY)
{
if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
{
hrtc->State = HAL_RTC_STATE_TIMEOUT;
return HAL_TIMEOUT;
@ -959,7 +959,7 @@ HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_
{
if(Timeout != HAL_MAX_DELAY)
{
if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
{
hrtc->State = HAL_RTC_STATE_TIMEOUT;
return HAL_TIMEOUT;
@ -997,7 +997,7 @@ HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_
{
if(Timeout != HAL_MAX_DELAY)
{
if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
{
hrtc->State = HAL_RTC_STATE_TIMEOUT;
return HAL_TIMEOUT;
@ -1034,7 +1034,7 @@ HAL_StatusTypeDef HAL_RTCEx_PollForTamper3Event(RTC_HandleTypeDef *hrtc, uint32_
{
if(Timeout != HAL_MAX_DELAY)
{
if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
{
hrtc->State = HAL_RTC_STATE_TIMEOUT;
return HAL_TIMEOUT;
@ -1081,7 +1081,7 @@ HAL_StatusTypeDef HAL_RTCEx_PollForTamper3Event(RTC_HandleTypeDef *hrtc, uint32_
*/
HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
{
uint32_t tickstart = 0;
uint32_t tickstart = 0U;
/* Check the parameters */
assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock));
@ -1170,7 +1170,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t Wak
*/
HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
{
uint32_t tickstart = 0;
uint32_t tickstart = 0U;
/* Check the parameters */
assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock));
@ -1205,9 +1205,12 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t
}
}
}
/* Disable the Wake-Up timer */
__HAL_RTC_WAKEUPTIMER_DISABLE(hrtc);
/* Clear flag Wake-Up */
__HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF);
tickstart = HAL_GetTick();
/* Wait till RTC WUTWF flag is set and if Time out is reached exit */
@ -1265,7 +1268,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t
*/
uint32_t HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc)
{
uint32_t tickstart = 0;
uint32_t tickstart = 0U;
/* Process Locked */
__HAL_LOCK(hrtc);
@ -1376,7 +1379,7 @@ HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uin
{
if(Timeout != HAL_MAX_DELAY)
{
if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
{
hrtc->State = HAL_RTC_STATE_TIMEOUT;
@ -1436,13 +1439,13 @@ HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uin
*/
void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data)
{
uint32_t tmp = 0;
uint32_t tmp = 0U;
/* Check the parameters */
assert_param(IS_RTC_BKP(BackupRegister));
tmp = (uint32_t)&(hrtc->Instance->BKP0R);
tmp += (BackupRegister * 4);
tmp += (BackupRegister * 4U);
/* Write the specified register */
*(__IO uint32_t *)tmp = (uint32_t)Data;
@ -1458,13 +1461,13 @@ void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint3
*/
uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister)
{
uint32_t tmp = 0;
uint32_t tmp = 0U;
/* Check the parameters */
assert_param(IS_RTC_BKP(BackupRegister));
tmp = (uint32_t)&(hrtc->Instance->BKP0R);
tmp += (BackupRegister * 4);
tmp += (BackupRegister * 4U);
/* Read the specified register */
return (*(__IO uint32_t *)tmp);
@ -1491,7 +1494,7 @@ uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister)
*/
HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef* hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmoothCalibMinusPulsesValue)
{
uint32_t tickstart = 0;
uint32_t tickstart = 0U;
/* Check the parameters */
assert_param(IS_RTC_SMOOTH_CALIB_PERIOD(SmoothCalibPeriod));
@ -1559,7 +1562,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef* hrtc, uint32_t Smo
*/
HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef* hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS)
{
uint32_t tickstart = 0;
uint32_t tickstart = 0U;
/* Check the parameters */
assert_param(IS_RTC_SHIFT_ADD1S(ShiftAdd1S));
@ -1922,7 +1925,7 @@ HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t
{
if(Timeout != HAL_MAX_DELAY)
{
if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
{
hrtc->State = HAL_RTC_STATE_TIMEOUT;
return HAL_TIMEOUT;

96
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_rtc_ex.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx_hal_rtc_ex.h
* @author MCD Application Team
* @version V1.5.0
* @date 8-January-2016
* @version V1.7.0
* @date 31-May-2016
* @brief Header file of RTC HAL Extended module.
******************************************************************************
* @attention
@ -107,7 +107,7 @@ typedef struct
/** @defgroup RTCEx_Output_selection_Definitions RTCEx Output Selection Definition
* @{
*/
#define RTC_OUTPUT_DISABLE ((uint32_t)0x00000000)
#define RTC_OUTPUT_DISABLE ((uint32_t)0x00000000U)
#define RTC_OUTPUT_ALARMA ((uint32_t)RTC_CR_OSEL_0)
#define RTC_OUTPUT_ALARMB ((uint32_t)RTC_CR_OSEL_1)
#define RTC_OUTPUT_WAKEUP ((uint32_t)RTC_CR_OSEL)
@ -119,11 +119,11 @@ typedef struct
/** @defgroup RTCEx_Backup_Registers_Definitions RTCEx Backup Registers Definition
* @{
*/
#define RTC_BKP_DR0 ((uint32_t)0x00000000)
#define RTC_BKP_DR1 ((uint32_t)0x00000001)
#define RTC_BKP_DR2 ((uint32_t)0x00000002)
#define RTC_BKP_DR3 ((uint32_t)0x00000003)
#define RTC_BKP_DR4 ((uint32_t)0x00000004)
#define RTC_BKP_DR0 ((uint32_t)0x00000000U)
#define RTC_BKP_DR1 ((uint32_t)0x00000001U)
#define RTC_BKP_DR2 ((uint32_t)0x00000002U)
#define RTC_BKP_DR3 ((uint32_t)0x00000003U)
#define RTC_BKP_DR4 ((uint32_t)0x00000004U)
/**
* @}
*/
@ -132,7 +132,7 @@ typedef struct
/** @defgroup RTCEx_Time_Stamp_Edges_definitions RTCEx Time Stamp Edges definition
* @{
*/
#define RTC_TIMESTAMPEDGE_RISING ((uint32_t)0x00000000)
#define RTC_TIMESTAMPEDGE_RISING ((uint32_t)0x00000000U)
#define RTC_TIMESTAMPEDGE_FALLING RTC_CR_TSEDGE
/**
@ -142,7 +142,7 @@ typedef struct
/** @defgroup RTCEx_TimeStamp_Pin_Selections RTCEx TimeStamp Pin Selection
* @{
*/
#define RTC_TIMESTAMPPIN_DEFAULT ((uint32_t)0x00000000)
#define RTC_TIMESTAMPPIN_DEFAULT ((uint32_t)0x00000000U)
/**
* @}
@ -222,8 +222,8 @@ typedef struct
/** @defgroup RTCEx_Tamper_Trigger_Definitions RTCEx Tamper Trigger Definitions
* @{
*/
#define RTC_TAMPERTRIGGER_RISINGEDGE ((uint32_t)0x00000000)
#define RTC_TAMPERTRIGGER_FALLINGEDGE ((uint32_t)0x00000002)
#define RTC_TAMPERTRIGGER_RISINGEDGE ((uint32_t)0x00000000U)
#define RTC_TAMPERTRIGGER_FALLINGEDGE ((uint32_t)0x00000002U)
#define RTC_TAMPERTRIGGER_LOWLEVEL RTC_TAMPERTRIGGER_RISINGEDGE
#define RTC_TAMPERTRIGGER_HIGHLEVEL RTC_TAMPERTRIGGER_FALLINGEDGE
@ -234,8 +234,8 @@ typedef struct
/** @defgroup RTCEx_Tamper_EraseBackUp_Definitions RTCEx Tamper EraseBackUp Definitions
* @{
*/
#define RTC_TAMPER_ERASE_BACKUP_ENABLE ((uint32_t)0x00000000)
#define RTC_TAMPER_ERASE_BACKUP_DISABLE ((uint32_t)0x00020000)
#define RTC_TAMPER_ERASE_BACKUP_ENABLE ((uint32_t)0x00000000U)
#define RTC_TAMPER_ERASE_BACKUP_DISABLE ((uint32_t)0x00020000U)
/**
* @}
*/
@ -243,8 +243,8 @@ typedef struct
/** @defgroup RTCEx_Tamper_MaskFlag_Definitions RTCEx Tamper MaskFlag Definitions
* @{
*/
#define RTC_TAMPERMASK_FLAG_DISABLE ((uint32_t)0x00000000)
#define RTC_TAMPERMASK_FLAG_ENABLE ((uint32_t)0x00040000)
#define RTC_TAMPERMASK_FLAG_DISABLE ((uint32_t)0x00000000U)
#define RTC_TAMPERMASK_FLAG_ENABLE ((uint32_t)0x00040000U)
/**
* @}
@ -253,7 +253,7 @@ typedef struct
/** @defgroup RTCEx_Tamper_Filter_Definitions RTCEx Tamper Filter Definitions
* @{
*/
#define RTC_TAMPERFILTER_DISABLE ((uint32_t)0x00000000) /*!< Tamper filter is disabled */
#define RTC_TAMPERFILTER_DISABLE ((uint32_t)0x00000000U) /*!< Tamper filter is disabled */
#define RTC_TAMPERFILTER_2SAMPLE RTC_TAMPCR_TAMPFLT_0 /*!< Tamper is activated after 2
consecutive samples at the active level */
@ -269,7 +269,7 @@ typedef struct
/** @defgroup RTCEx_Tamper_Sampling_Frequencies_Definitions RTCEx Tamper Sampling Frequencies Definitions
* @{
*/
#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 ((uint32_t)0x00000000) /*!< Each of the tamper inputs are sampled
#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 ((uint32_t)0x00000000U) /*!< Each of the tamper inputs are sampled
with a frequency = RTCCLK / 32768 */
#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384 RTC_TAMPCR_TAMPFREQ_0 /*!< Each of the tamper inputs are sampled
with a frequency = RTCCLK / 16384 */
@ -294,7 +294,7 @@ typedef struct
/** @defgroup RTCEx_Tamper_Pin_Precharge_Duration_Definitions RTCEx Tamper Pin Precharge Duration Definitions
* @{
*/
#define RTC_TAMPERPRECHARGEDURATION_1RTCCLK ((uint32_t)0x00000000) /*!< Tamper pins are pre-charged before
#define RTC_TAMPERPRECHARGEDURATION_1RTCCLK ((uint32_t)0x00000000U) /*!< Tamper pins are pre-charged before
sampling during 1 RTCCLK cycle */
#define RTC_TAMPERPRECHARGEDURATION_2RTCCLK RTC_TAMPCR_TAMPPRCH_0 /*!< Tamper pins are pre-charged before
sampling during 2 RTCCLK cycles */
@ -311,7 +311,7 @@ typedef struct
* @{
*/
#define RTC_TIMESTAMPONTAMPERDETECTION_ENABLE RTC_TAMPCR_TAMPTS /*!< TimeStamp on Tamper Detection event saved */
#define RTC_TIMESTAMPONTAMPERDETECTION_DISABLE ((uint32_t)0x00000000) /*!< TimeStamp on Tamper Detection event is not saved */
#define RTC_TIMESTAMPONTAMPERDETECTION_DISABLE ((uint32_t)0x00000000U) /*!< TimeStamp on Tamper Detection event is not saved */
/**
* @}
@ -320,7 +320,7 @@ typedef struct
/** @defgroup RTCEx_Tamper_Pull_UP_Definitions RTCEx Tamper Pull UP Definitions
* @{
*/
#define RTC_TAMPER_PULLUP_ENABLE ((uint32_t)0x00000000) /*!< Tamper pins are pre-charged before sampling */
#define RTC_TAMPER_PULLUP_ENABLE ((uint32_t)0x00000000U) /*!< Tamper pins are pre-charged before sampling */
#define RTC_TAMPER_PULLUP_DISABLE RTC_TAMPCR_TAMPPUDIS /*!< Tamper pins pre-charge is disabled */
/**
@ -330,7 +330,7 @@ typedef struct
/** @defgroup RTCEx_Wakeup_Timer_Definitions RTCEx Wakeup Timer Definitions
* @{
*/
#define RTC_WAKEUPCLOCK_RTCCLK_DIV16 ((uint32_t)0x00000000)
#define RTC_WAKEUPCLOCK_RTCCLK_DIV16 ((uint32_t)0x00000000U)
#define RTC_WAKEUPCLOCK_RTCCLK_DIV8 RTC_CR_WUCKSEL_0
#define RTC_WAKEUPCLOCK_RTCCLK_DIV4 RTC_CR_WUCKSEL_1
#define RTC_WAKEUPCLOCK_RTCCLK_DIV2 ((uint32_t) (RTC_CR_WUCKSEL_0 | RTC_CR_WUCKSEL_1))
@ -343,7 +343,7 @@ typedef struct
/** @defgroup RTCEx_Smooth_calib_period_Definitions RTCEx Smooth calib period Definitions
* @{
*/
#define RTC_SMOOTHCALIB_PERIOD_32SEC ((uint32_t)0x00000000) /*!< If RTCCLK = 32768 Hz, Smooth calibation
#define RTC_SMOOTHCALIB_PERIOD_32SEC ((uint32_t)0x00000000U) /*!< If RTCCLK = 32768 Hz, Smooth calibation
period is 32s, else 2exp20 RTCCLK pulses */
#define RTC_SMOOTHCALIB_PERIOD_16SEC RTC_CALR_CALW16 /*!< If RTCCLK = 32768 Hz, Smooth calibation
period is 16s, else 2exp19 RTCCLK pulses */
@ -360,7 +360,7 @@ typedef struct
#define RTC_SMOOTHCALIB_PLUSPULSES_SET RTC_CALR_CALP /*!< The number of RTCCLK pulses added
during a X -second window = Y - CALM[8:0]
with Y = 512, 256, 128 when X = 32, 16, 8 */
#define RTC_SMOOTHCALIB_PLUSPULSES_RESET ((uint32_t)0x00000000) /*!< The number of RTCCLK pulses subbstited
#define RTC_SMOOTHCALIB_PLUSPULSES_RESET ((uint32_t)0x00000000U) /*!< The number of RTCCLK pulses subbstited
during a 32-second window = CALM[8:0] */
/**
@ -369,7 +369,7 @@ typedef struct
/** @defgroup RTCEx_Calib_Output_selection_Definitions RTCEx Calib Output selection Definitions
* @{
*/
#define RTC_CALIBOUTPUT_512HZ ((uint32_t)0x00000000)
#define RTC_CALIBOUTPUT_512HZ ((uint32_t)0x00000000U)
#define RTC_CALIBOUTPUT_1HZ RTC_CR_COSEL
/**
@ -380,7 +380,7 @@ typedef struct
/** @defgroup RTCEx_Add_1_Second_Parameter_Definition RTCEx Add 1 Second Parameter Definitions
* @{
*/
#define RTC_SHIFTADD1S_RESET ((uint32_t)0x00000000)
#define RTC_SHIFTADD1S_RESET ((uint32_t)0x00000000U)
#define RTC_SHIFTADD1S_SET RTC_SHIFTR_ADD1S
/**
* @}
@ -475,7 +475,7 @@ typedef struct
* @arg RTC_IT_WUT: WakeUpTimer interrupt
* @retval None
*/
#define __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4)) != RESET) ? SET : RESET)
#define __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4U)) != RESET) ? SET : RESET)
/**
* @brief Check whether the specified RTC Wake Up timer interrupt has been enabled or not.
@ -562,14 +562,20 @@ typedef struct
* @brief Enable rising & falling edge trigger on the RTC WakeUp Timer associated Exti line.
* @retval None.
*/
#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE() do { __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();__HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE(); } while(0);
#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE() do { \
__HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE(); \
__HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE(); \
} while(0U)
/**
* @brief Disable rising & falling edge trigger on the RTC WakeUp Timer associated Exti line.
* This parameter can be:
* @retval None.
*/
#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE() do { __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE();__HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE(); } while(0);
#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
__HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE(); \
__HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE(); \
} while(0U)
/**
* @brief Check whether the RTC WakeUp Timer associated Exti line interrupt flag is set or not.
@ -638,7 +644,7 @@ typedef struct
* @arg RTC_IT_TS: TimeStamp interrupt
* @retval None
*/
#define __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4)) != RESET) ? SET : RESET)
#define __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4U)) != RESET) ? SET : RESET)
/**
* @brief Check whether the specified RTC Time Stamp interrupt has been enabled or not.
@ -847,8 +853,8 @@ typedef struct
* @arg RTC_IT_TAMP2: Tamper2 interrupt
* @retval None
*/
#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) == RTC_IT_TAMP1) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 3)) != RESET) ? SET : RESET) : \
((__INTERRUPT__) == RTC_IT_TAMP2) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 5)) != RESET) ? SET : RESET))
#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) == RTC_IT_TAMP1) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 3U)) != RESET) ? SET : RESET) : \
((__INTERRUPT__) == RTC_IT_TAMP2) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 5U)) != RESET) ? SET : RESET))
#elif defined (STM32L083xx) || defined (STM32L082xx) || defined (STM32L081xx) || \
defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx) || \
@ -864,9 +870,9 @@ typedef struct
* @arg RTC_IT_TAMP3: Tamper3 interrupt
* @retval None
*/
#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) == RTC_IT_TAMP1) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 3)) != RESET) ? SET : RESET) : \
((__INTERRUPT__) == RTC_IT_TAMP2) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 5)) != RESET) ? SET : RESET) : \
((__INTERRUPT__) == RTC_IT_TAMP3) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 7)) != RESET) ? SET : RESET))
#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) == RTC_IT_TAMP1) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 3U)) != RESET) ? SET : RESET) : \
((__INTERRUPT__) == RTC_IT_TAMP2) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 5U)) != RESET) ? SET : RESET) : \
((__INTERRUPT__) == RTC_IT_TAMP3) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 7U)) != RESET) ? SET : RESET))
#elif defined (STM32L011xx) || defined (STM32L021xx)
@ -879,8 +885,8 @@ typedef struct
* @arg RTC_IT_TAMP3: Tamper3 interrupt
* @retval None
*/
#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) == RTC_IT_TAMP2) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 5)) != RESET) ? SET : RESET) : \
((__INTERRUPT__) == RTC_IT_TAMP3) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 7)) != RESET) ? SET : RESET))
#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) == RTC_IT_TAMP2) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 5U)) != RESET) ? SET : RESET) : \
((__INTERRUPT__) == RTC_IT_TAMP3) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 7U)) != RESET) ? SET : RESET))
#endif /* (STM32L011xx) || (STM32L021xx)
@ -1075,14 +1081,20 @@ typedef struct
* @brief Enable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
* @retval None.
*/
#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_FALLING_EDGE() do { __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE();__HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE(); } while(0);
#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_FALLING_EDGE() do { \
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE(); \
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE(); \
} while(0U)
/**
* @brief Disable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
* This parameter can be:
* @retval None.
*/
#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_FALLING_EDGE() do { __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE();__HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE(); } while(0);
#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE(); \
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE(); \
} while(0U)
/**
* @brief Check whether the RTC Tamper and Timestamp associated Exti line interrupt flag is set or not.
@ -1338,9 +1350,9 @@ HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t
#define IS_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TIMESTAMPEDGE_RISING) || \
((EDGE) == RTC_TIMESTAMPEDGE_FALLING))
#define IS_RTC_TAMPER(TAMPER) ((((TAMPER) & ((uint32_t)(0xFFFFFFFF ^ RTC_TAMPCR_TAMPXE))) == 0x00) && ((TAMPER) != (uint32_t)RESET))
#define IS_RTC_TAMPER(TAMPER) ((((TAMPER) & ((uint32_t)(0xFFFFFFFFU ^ RTC_TAMPCR_TAMPXE))) == 0x00U) && ((TAMPER) != (uint32_t)RESET))
#define IS_RTC_TAMPER_INTERRUPT(INTERRUPT) ((((INTERRUPT) & (uint32_t)(0xFFFFFFFF ^ RTC_TAMPCR_TAMPXIE)) == 0x00) && ((INTERRUPT) != (uint32_t)RESET))
#define IS_RTC_TAMPER_INTERRUPT(INTERRUPT) ((((INTERRUPT) & (uint32_t)(0xFFFFFFFFU ^ RTC_TAMPCR_TAMPXIE)) == 0x00U) && ((INTERRUPT) != (uint32_t)RESET))
#define IS_RTC_TIMESTAMP_PIN(PIN) (((PIN) == RTC_TIMESTAMPPIN_DEFAULT))
@ -1380,7 +1392,7 @@ HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t
#define IS_RTC_TAMPER_PULLUP_STATE(STATE) (((STATE) == RTC_TAMPER_PULLUP_ENABLE) || \
((STATE) == RTC_TAMPER_PULLUP_DISABLE))
#define IS_RTC_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV16) || \
#define IS_RTC_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV16) || \
((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV8) || \
((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV4) || \
((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV2) || \

82
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_smartcard.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx_hal_smartcard.c
* @author MCD Application Team
* @version V1.5.0
* @date 8-January-2016
* @version V1.7.0
* @date 31-May-2016
* @brief SMARTCARD HAL module driver.
*
* This file provides firmware functions to manage the following
@ -106,8 +106,8 @@
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
#define TEACK_REACK_TIMEOUT 1000
#define HAL_SMARTCARD_TXDMA_TIMEOUTVALUE 22000
#define TEACK_REACK_TIMEOUT 1000U
#define HAL_SMARTCARD_TXDMA_TIMEOUTVALUE 22000U
#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \
USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8))
#define USART_CR2_CLK_FIELDS ((uint32_t)(USART_CR2_CLKEN|USART_CR2_CPOL|USART_CR2_CPHA|USART_CR2_LBCL))
@ -146,14 +146,7 @@ static void SMARTCARD_AdvFeatureConfig(SMARTCARD_HandleTypeDef *hsc);
associated to the SmartCard.
(+) These parameters can be configured:
(++) Baud Rate
(++) Parity: parity should be enabled,
Frame Length is fixed to 8 bits plus parity:
the USART frame format is given in the following table:
+---------------------------------------------------------------+
| M1M0 bits | PCE bit | USART frame |
|-----------------------|---------------------------------------|
| 01 | 1 | | SB | 8 bit data | PB | STB | |
+---------------------------------------------------------------+
(++) Parity: parity should be enabled,frame Length is fixed to 8 bits plus parity.
(++) Receiver/transmitter modes
(++) Synchronous mode (and if enabled, phase, polarity and last bit parameters)
(++) Prescaler value
@ -176,6 +169,15 @@ static void SMARTCARD_AdvFeatureConfig(SMARTCARD_HandleTypeDef *hsc);
(details for the procedures are available in reference manual).
@endverbatim
The USART frame format is given in the following table:
Table 1. USART frame format.
+---------------------------------------------------------------+
| M1M0 bits | PCE bit | USART frame |
|-----------------------|---------------------------------------|
| 01 | 1 | | SB | 8 bit data | PB | STB | |
+---------------------------------------------------------------+
* @{
*/
@ -356,7 +358,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsc, uint8_t *
{
if((hsc->State == HAL_SMARTCARD_STATE_READY) || (hsc->State == HAL_SMARTCARD_STATE_BUSY_RX))
{
if((pData == NULL) || (Size == 0))
if((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@ -376,14 +378,14 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsc, uint8_t *
hsc->TxXferSize = Size;
hsc->TxXferCount = Size;
while(hsc->TxXferCount > 0)
while(hsc->TxXferCount > 0U)
{
hsc->TxXferCount--;
if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_TXE, RESET, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
hsc->Instance->TDR = (*pData++ & (uint8_t)0xFF);
hsc->Instance->TDR = (*pData++ & (uint8_t)0xFFU);
}
if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_TC, RESET, Timeout) != HAL_OK)
{
@ -422,7 +424,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsc, uint8_t *p
{
if((hsc->State == HAL_SMARTCARD_STATE_READY) || (hsc->State == HAL_SMARTCARD_STATE_BUSY_TX))
{
if((pData == NULL) || (Size == 0))
if((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@ -444,14 +446,14 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsc, uint8_t *p
hsc->RxXferSize = Size;
hsc->RxXferCount = Size;
/* Check the remain data to be received */
while(hsc->RxXferCount > 0)
while(hsc->RxXferCount > 0U)
{
hsc->RxXferCount--;
if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_RXNE, RESET, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
*pData++ = (uint8_t)(hsc->Instance->RDR & (uint8_t)0x00FF);
*pData++ = (uint8_t)(hsc->Instance->RDR & (uint8_t)0x00FFU);
}
/* Check if a non-blocking transmit Process is ongoing or not */
@ -486,7 +488,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc, uint8_
{
if((hsc->State == HAL_SMARTCARD_STATE_READY) || (hsc->State == HAL_SMARTCARD_STATE_BUSY_RX))
{
if((pData == NULL) || (Size == 0))
if((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@ -537,7 +539,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t
{
if((hsc->State == HAL_SMARTCARD_STATE_READY) || (hsc->State == HAL_SMARTCARD_STATE_BUSY_TX))
{
if((pData == NULL) || (Size == 0))
if((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@ -593,7 +595,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsc, uint8
if((hsc->State == HAL_SMARTCARD_STATE_READY) || (hsc->State == HAL_SMARTCARD_STATE_BUSY_RX))
{
if((pData == NULL) || (Size == 0))
if((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@ -659,7 +661,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_
if((hsc->State == HAL_SMARTCARD_STATE_READY) || (hsc->State == HAL_SMARTCARD_STATE_BUSY_TX))
{
if((pData == NULL) || (Size == 0))
if((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@ -892,7 +894,7 @@ static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc)
{
if((hsc->State == HAL_SMARTCARD_STATE_BUSY_TX) || (hsc->State == HAL_SMARTCARD_STATE_BUSY_TX_RX))
{
if(hsc->TxXferCount == 0)
if(hsc->TxXferCount == 0U)
{
/* Disable the SMARTCARD Transmit Complete Interrupt */
__HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_TC);
@ -916,7 +918,7 @@ static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc)
}
else
{
hsc->Instance->TDR = (*hsc->pTxBuffPtr++ & (uint8_t)0xFF);
hsc->Instance->TDR = (*hsc->pTxBuffPtr++ & (uint8_t)0xFFU);
hsc->TxXferCount--;
return HAL_OK;
@ -939,9 +941,9 @@ static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc)
{
if((hsc->State == HAL_SMARTCARD_STATE_BUSY_RX) || (hsc->State == HAL_SMARTCARD_STATE_BUSY_TX_RX))
{
*hsc->pRxBuffPtr++ = (uint8_t)(hsc->Instance->RDR & (uint8_t)0xFF);
*hsc->pRxBuffPtr++ = (uint8_t)(hsc->Instance->RDR & (uint8_t)0xFFU);
if(--hsc->RxXferCount == 0)
if(--hsc->RxXferCount == 0U)
{
while(HAL_IS_BIT_SET(hsc->Instance->ISR, SMARTCARD_FLAG_RXNE))
{
@ -983,8 +985,8 @@ static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc)
*/
static void SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsc)
{
uint32_t tmpreg = 0x00000000;
uint32_t clocksource = 0x00000000;
uint32_t tmpreg = 0x00000000U;
uint32_t clocksource = 0x00000000U;
/* Check the parameters */
assert_param(IS_SMARTCARD_INSTANCE(hsc->Instance));
@ -1056,19 +1058,19 @@ static void SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsc)
switch (clocksource)
{
case SMARTCARD_CLOCKSOURCE_PCLK1:
hsc->Instance->BRR = (uint16_t)(HAL_RCC_GetPCLK1Freq() / hsc->Init.BaudRate);
hsc->Instance->BRR = (uint16_t)((HAL_RCC_GetPCLK1Freq() + (hsc->Init.BaudRate/2U)) / hsc->Init.BaudRate);
break;
case SMARTCARD_CLOCKSOURCE_PCLK2:
hsc->Instance->BRR = (uint16_t)(HAL_RCC_GetPCLK2Freq() / hsc->Init.BaudRate);
hsc->Instance->BRR = (uint16_t)((HAL_RCC_GetPCLK2Freq() + (hsc->Init.BaudRate/2U)) / hsc->Init.BaudRate);
break;
case SMARTCARD_CLOCKSOURCE_HSI:
hsc->Instance->BRR = (uint16_t)(HSI_VALUE / hsc->Init.BaudRate);
hsc->Instance->BRR = (uint16_t)((HSI_VALUE + (hsc->Init.BaudRate/2U)) / hsc->Init.BaudRate);
break;
case SMARTCARD_CLOCKSOURCE_SYSCLK:
hsc->Instance->BRR = (uint16_t)(HAL_RCC_GetSysClockFreq() / hsc->Init.BaudRate);
hsc->Instance->BRR = (uint16_t)((HAL_RCC_GetSysClockFreq() + (hsc->Init.BaudRate/2U)) / hsc->Init.BaudRate);
break;
case SMARTCARD_CLOCKSOURCE_LSE:
hsc->Instance->BRR = (uint16_t)(LSE_VALUE / hsc->Init.BaudRate);
hsc->Instance->BRR = (uint16_t)((LSE_VALUE + (hsc->Init.BaudRate/2U)) / hsc->Init.BaudRate);
break;
default:
break;
@ -1184,7 +1186,7 @@ static void SMARTCARD_AdvFeatureConfig(SMARTCARD_HandleTypeDef *hsc)
*/
static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsc, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
{
uint32_t tickstart = 0x00;
uint32_t tickstart = 0x00U;
tickstart = HAL_GetTick();
/* Wait until flag is set */
@ -1195,7 +1197,7 @@ static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDe
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
{
if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
{
/* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
__HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_TXE);
@ -1220,7 +1222,7 @@ static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDe
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
{
if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
{
/* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
__HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_TXE);
@ -1249,7 +1251,7 @@ static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDe
static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma)
{
SMARTCARD_HandleTypeDef* hsmartcard = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
hsmartcard->TxXferCount = 0;
hsmartcard->TxXferCount = 0U;
/* Disable the DMA transfer for transmit request by resetting the DMAT bit
in the SMARTCARD associated USART CR3 register */
@ -1267,7 +1269,7 @@ static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma)
static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
{
SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
hsc->RxXferCount = 0;
hsc->RxXferCount = 0U;
/* Disable the DMA transfer for the receiver request by setting the DMAR bit
in the SMARTCARD associated USART CR3 register */
@ -1294,8 +1296,8 @@ static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma)
{
SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
hsc->RxXferCount = 0;
hsc->TxXferCount = 0;
hsc->RxXferCount = 0U;
hsc->TxXferCount = 0U;
hsc->State= HAL_SMARTCARD_STATE_READY;
hsc->ErrorCode |= HAL_SMARTCARD_ERROR_DMA;
HAL_SMARTCARD_ErrorCallback(hsc);

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