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L0 ST CUBE V1.10.0

pull/6666/head
bcostm 2018-03-29 14:35:47 +02:00
parent 934101ecf6
commit 8191487a4d
172 changed files with 20248 additions and 15075 deletions
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5
targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L011K4/device/TOOLCHAIN_ARM_MICRO/startup_stm32l011xx.S
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@ -1,8 +1,8 @@
;******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
;* File Name : startup_stm32l011xx.s
;* Author : MCD Application Team
;* Version : V1.5.0
;* Date : 8-January-2016
;* Version : V1.7.1
;* Date : 25-November-2016
;* Description : STM32l011xx Devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
@ -12,7 +12,6 @@
;* calls main()).
;* After Reset the Cortex-M0+ processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
;*
;* Redistribution and use in source and binary forms, with or without modification,

8
targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L011K4/device/stm32l011xx.h
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@ -2,8 +2,6 @@
******************************************************************************
* @file stm32l011xx.h
* @author MCD Application Team
* @version V1.7.0
* @date 31-May-2016
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
* This file contains all the peripheral register's definitions, bits
* definitions and memory mapping for stm32l011xx devices.
@ -16,7 +14,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -752,7 +750,7 @@ typedef struct
/******************* Bits definition for ADC_CFGR2 register *****************/
#define ADC_CFGR2_TOVS_Pos (9U)
#define ADC_CFGR2_TOVS_Msk (0x400001U << ADC_CFGR2_TOVS_Pos) /*!< 0x80000200 */
#define ADC_CFGR2_TOVS_Msk (0x1U << ADC_CFGR2_TOVS_Pos) /*!< 0x80000200 */
#define ADC_CFGR2_TOVS ADC_CFGR2_TOVS_Msk /*!< Triggered Oversampling */
#define ADC_CFGR2_OVSS_Pos (5U)
#define ADC_CFGR2_OVSS_Msk (0xFU << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */
@ -5736,7 +5734,7 @@ typedef struct
#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
((INSTANCE) == COMP2))
#define IS_COMP_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == COMP12_COMMON)
#define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON)
/******************************* CRC Instances ********************************/
#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)

14
targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L011K4/device/stm32l0xx.h
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@ -2,8 +2,6 @@
******************************************************************************
* @file stm32l0xx.h
* @author MCD Application Team
* @version V1.7.0
* @date 31-May-2016
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
* This file contains all the peripheral register's definitions, bits
* definitions and memory mapping for STM32L0xx devices.
@ -20,7 +18,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -114,16 +112,16 @@
#endif /* USE_HAL_DRIVER */
/**
* @brief CMSIS Device version number V1.7.0
* @brief CMSIS Device version number V1.7.1
*/
#define __STM32L0xx_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */
#define __STM32L0xx_CMSIS_VERSION_SUB1 (0x07) /*!< [23:16] sub1 version */
#define __STM32L0xx_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32L0xx_CMSIS_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */
#define __STM32L0xx_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32L0xx_CMSIS_VERSION ((__STM32L0xx_CMSIS_VERSION_MAIN << 24)\
|(__STM32L0xx_CMSIS_VERSION_SUB1 << 16)\
|(__STM32L0xx_CMSIS_VERSION_SUB2 << 8 )\
|(__STM32L0xx_CMSIS_VERSION_RC))
|(__STM32L0xx_CMSIS_VERSION_SUB1 << 16)\
|(__STM32L0xx_CMSIS_VERSION_SUB2 << 8 )\
|(__STM32L0xx_CMSIS_VERSION_RC))
/**
* @}

4
targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L011K4/device/system_stm32l0xx.h
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@ -2,13 +2,11 @@
******************************************************************************
* @file system_stm32l0xx.h
* @author MCD Application Team
* @version V1.7.0
* @date 31-May-2016
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Header File.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:

5
targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/device/TOOLCHAIN_ARM_MICRO/startup_stm32l031xx.S
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@ -1,8 +1,8 @@
;******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
;* File Name : startup_stm32l053xx.s
;* Author : MCD Application Team
;* Version : V1.5.0
;* Date : 8-January-2016
;* Version : V1.7.1
;* Date : 25-November-2016
;* Description : STM32l053xx Devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
@ -12,7 +12,6 @@
;* calls main()).
;* After Reset the Cortex-M0+ processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
;*
;* Redistribution and use in source and binary forms, with or without modification,

5
targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/device/TOOLCHAIN_ARM_STD/startup_stm32l031xx.S
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@ -1,8 +1,8 @@
;******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
;* File Name : startup_stm32l053xx.s
;* Author : MCD Application Team
;* Version : V1.5.0
;* Date : 8-January-2016
;* Version : V1.7.1
;* Date : 25-November-2016
;* Description : STM32l053xx Devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
@ -12,7 +12,6 @@
;* calls main()).
;* After Reset the Cortex-M0+ processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
;*
;* Redistribution and use in source and binary forms, with or without modification,

2
targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/device/TOOLCHAIN_GCC_ARM/startup_stm32l031xx.S
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@ -2,8 +2,6 @@
******************************************************************************
* @file startup_stm32l031xx.s
* @author MCD Application Team
* @version V1.5.0
* @date 8-January-2016
* @brief STM32L031xx Devices vector table for Atollic TrueSTUDIO toolchain.
* This module performs:
* - Set the initial SP

4
targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/device/TOOLCHAIN_IAR/startup_stm32l031xx.S
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@ -1,8 +1,8 @@
;/******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
;* File Name : startup_stm32l031xx.s
;* Author : MCD Application Team
;* Version : V1.5.0
;* Date : 8-January-2016
;* Version : V1.7.1
;* Date : 25-November-2016
;* Description : STM32L031xx Ultra Low Power Devices vector
;* This module performs:
;* - Set the initial SP

8
targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/device/stm32l031xx.h
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@ -2,8 +2,6 @@
******************************************************************************
* @file stm32l031xx.h
* @author MCD Application Team
* @version V1.7.0
* @date 31-May-2016
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
* This file contains all the peripheral register's definitions, bits
* definitions and memory mapping for stm32l031xx devices.
@ -16,7 +14,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -761,7 +759,7 @@ typedef struct
/******************* Bits definition for ADC_CFGR2 register *****************/
#define ADC_CFGR2_TOVS_Pos (9U)
#define ADC_CFGR2_TOVS_Msk (0x400001U << ADC_CFGR2_TOVS_Pos) /*!< 0x80000200 */
#define ADC_CFGR2_TOVS_Msk (0x1U << ADC_CFGR2_TOVS_Pos) /*!< 0x80000200 */
#define ADC_CFGR2_TOVS ADC_CFGR2_TOVS_Msk /*!< Triggered Oversampling */
#define ADC_CFGR2_OVSS_Pos (5U)
#define ADC_CFGR2_OVSS_Msk (0xFU << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */
@ -5857,7 +5855,7 @@ typedef struct
#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
((INSTANCE) == COMP2))
#define IS_COMP_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == COMP12_COMMON)
#define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON)
/******************************* CRC Instances ********************************/
#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)

14
targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/device/stm32l0xx.h
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@ -2,8 +2,6 @@
******************************************************************************
* @file stm32l0xx.h
* @author MCD Application Team
* @version V1.7.0
* @date 31-May-2016
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
* This file contains all the peripheral register's definitions, bits
* definitions and memory mapping for STM32L0xx devices.
@ -20,7 +18,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -114,16 +112,16 @@
#endif /* USE_HAL_DRIVER */
/**
* @brief CMSIS Device version number V1.7.0
* @brief CMSIS Device version number V1.7.1
*/
#define __STM32L0xx_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */
#define __STM32L0xx_CMSIS_VERSION_SUB1 (0x07) /*!< [23:16] sub1 version */
#define __STM32L0xx_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32L0xx_CMSIS_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */
#define __STM32L0xx_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32L0xx_CMSIS_VERSION ((__STM32L0xx_CMSIS_VERSION_MAIN << 24)\
|(__STM32L0xx_CMSIS_VERSION_SUB1 << 16)\
|(__STM32L0xx_CMSIS_VERSION_SUB2 << 8 )\
|(__STM32L0xx_CMSIS_VERSION_RC))
|(__STM32L0xx_CMSIS_VERSION_SUB1 << 16)\
|(__STM32L0xx_CMSIS_VERSION_SUB2 << 8 )\
|(__STM32L0xx_CMSIS_VERSION_RC))
/**
* @}

4
targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/device/system_stm32l0xx.h
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@ -2,13 +2,11 @@
******************************************************************************
* @file system_stm32l0xx.h
* @author MCD Application Team
* @version V1.7.0
* @date 31-May-2016
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Header File.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:

5
targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/device/TOOLCHAIN_ARM_MICRO/startup_stm32l073xx.S
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@ -1,8 +1,8 @@
;******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
;* File Name : startup_stm32l073xx.s
;* Author : MCD Application Team
;* Version : V1.5.0
;* Date : 8-January-2016
;* Version : V1.7.1
;* Date : 25-November-2016
;* Description : STM32l073xx Devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
@ -12,7 +12,6 @@
;* calls main()).
;* After Reset the Cortex-M0+ processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
;*
;* Redistribution and use in source and binary forms, with or without modification,

5
targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/device/TOOLCHAIN_ARM_STD/startup_stm32l073xx.S
View File

@ -1,8 +1,8 @@
;******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
;* File Name : startup_stm32l073xx.s
;* Author : MCD Application Team
;* Version : V1.5.0
;* Date : 8-January-2016
;* Version : V1.7.1
;* Date : 25-November-2016
;* Description : STM32l073xx Devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
@ -12,7 +12,6 @@
;* calls main()).
;* After Reset the Cortex-M0+ processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
;*
;* Redistribution and use in source and binary forms, with or without modification,

2
targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/device/TOOLCHAIN_GCC_ARM/startup_stm32l073xx.S
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@ -2,8 +2,6 @@
******************************************************************************
* @file startup_stm32l073xx.s
* @author MCD Application Team
* @version V1.5.0
* @date 8-January-2016
* @brief STM32L073xx Devices vector table for Atollic TrueSTUDIO toolchain.
* This module performs:
* - Set the initial SP

4
targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/device/TOOLCHAIN_IAR/startup_stm32l073xx.S
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@ -1,8 +1,8 @@
;/******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
;* File Name : startup_stm32l073xx.s
;* Author : MCD Application Team
;* Version : V1.5.0
;* Date : 8-January-2016
;* Version : V1.7.1
;* Date : 25-November-2016
;* Description : STM32L073xx Ultra Low Power Devices vector
;* This module performs:
;* - Set the initial SP

8
targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/device/stm32l073xx.h
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@ -2,8 +2,6 @@
******************************************************************************
* @file stm32l073xx.h
* @author MCD Application Team
* @version V1.7.0
* @date 31-May-2016
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
* This file contains all the peripheral register's definitions, bits
* definitions and memory mapping for stm32l073xx devices.
@ -16,7 +14,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -950,7 +948,7 @@ typedef struct
/******************* Bits definition for ADC_CFGR2 register *****************/
#define ADC_CFGR2_TOVS_Pos (9U)
#define ADC_CFGR2_TOVS_Msk (0x400001U << ADC_CFGR2_TOVS_Pos) /*!< 0x80000200 */
#define ADC_CFGR2_TOVS_Msk (0x1U << ADC_CFGR2_TOVS_Pos) /*!< 0x80000200 */
#define ADC_CFGR2_TOVS ADC_CFGR2_TOVS_Msk /*!< Triggered Oversampling */
#define ADC_CFGR2_OVSS_Pos (5U)
#define ADC_CFGR2_OVSS_Msk (0xFU << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */
@ -7532,7 +7530,7 @@ typedef struct
#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
((INSTANCE) == COMP2))
#define IS_COMP_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == COMP12_COMMON)
#define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON)
/******************************* CRC Instances ********************************/
#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)

14
targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/device/stm32l0xx.h
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@ -2,8 +2,6 @@
******************************************************************************
* @file stm32l0xx.h
* @author MCD Application Team
* @version V1.7.0
* @date 31-May-2016
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
* This file contains all the peripheral register's definitions, bits
* definitions and memory mapping for STM32L0xx devices.
@ -20,7 +18,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -114,16 +112,16 @@
#endif /* USE_HAL_DRIVER */
/**
* @brief CMSIS Device version number V1.7.0
* @brief CMSIS Device version number V1.7.1
*/
#define __STM32L0xx_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */
#define __STM32L0xx_CMSIS_VERSION_SUB1 (0x07) /*!< [23:16] sub1 version */
#define __STM32L0xx_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32L0xx_CMSIS_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */
#define __STM32L0xx_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32L0xx_CMSIS_VERSION ((__STM32L0xx_CMSIS_VERSION_MAIN << 24)\
|(__STM32L0xx_CMSIS_VERSION_SUB1 << 16)\
|(__STM32L0xx_CMSIS_VERSION_SUB2 << 8 )\
|(__STM32L0xx_CMSIS_VERSION_RC))
|(__STM32L0xx_CMSIS_VERSION_SUB1 << 16)\
|(__STM32L0xx_CMSIS_VERSION_SUB2 << 8 )\
|(__STM32L0xx_CMSIS_VERSION_RC))
/**
* @}

4
targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/device/system_stm32l0xx.h
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@ -2,13 +2,11 @@
******************************************************************************
* @file system_stm32l0xx.h
* @author MCD Application Team
* @version V1.7.0
* @date 31-May-2016
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Header File.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:

5
targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/device/TOOLCHAIN_ARM_MICRO/startup_stm32l053xx.S
View File

@ -1,8 +1,8 @@
;******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
;* File Name : startup_stm32l053xx.s
;* Author : MCD Application Team
;* Version : V1.5.0
;* Date : 8-January-2016
;* Version : V1.7.1
;* Date : 25-November-2016
;* Description : STM32l053xx Devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
@ -12,7 +12,6 @@
;* calls main()).
;* After Reset the Cortex-M0+ processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
;*
;* Redistribution and use in source and binary forms, with or without modification,

5
targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/device/TOOLCHAIN_ARM_STD/startup_stm32l053xx.S
View File

@ -1,8 +1,8 @@
;******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
;* File Name : startup_stm32l053xx.s
;* Author : MCD Application Team
;* Version : V1.5.0
;* Date : 8-January-2016
;* Version : V1.7.1
;* Date : 25-November-2016
;* Description : STM32l053xx Devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
@ -12,7 +12,6 @@
;* calls main()).
;* After Reset the Cortex-M0+ processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
;*
;* Redistribution and use in source and binary forms, with or without modification,

2
targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/device/TOOLCHAIN_GCC_ARM/startup_stm32l053xx.S
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file startup_stm32l053xx.s
* @author MCD Application Team
* @version V1.5.0
* @date 8-January-2016
* @brief STM32L053xx Devices vector table for Atollic TrueSTUDIO toolchain.
* This module performs:
* - Set the initial SP

4
targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/device/TOOLCHAIN_IAR/startup_stm32l053xx.S
View File

@ -1,8 +1,8 @@
;/******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
;* File Name : startup_stm32l053xx.s
;* Author : MCD Application Team
;* Version : V1.5.0
;* Date : 8-January-2016
;* Version : V1.7.1
;* Date : 25-November-2016
;* Description : STM32L053xx Ultra Low Power Devices vector
;* This module performs:
;* - Set the initial SP

8
targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/device/stm32l053xx.h
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32l053xx.h
* @author MCD Application Team
* @version V1.7.0
* @date 31-May-2016
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
* This file contains all the peripheral register's definitions, bits
* definitions and memory mapping for stm32l053xx devices.
@ -16,7 +14,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -921,7 +919,7 @@ typedef struct
/******************* Bits definition for ADC_CFGR2 register *****************/
#define ADC_CFGR2_TOVS_Pos (9U)
#define ADC_CFGR2_TOVS_Msk (0x400001U << ADC_CFGR2_TOVS_Pos) /*!< 0x80000200 */
#define ADC_CFGR2_TOVS_Msk (0x1U << ADC_CFGR2_TOVS_Pos) /*!< 0x80000200 */
#define ADC_CFGR2_TOVS ADC_CFGR2_TOVS_Msk /*!< Triggered Oversampling */
#define ADC_CFGR2_OVSS_Pos (5U)
#define ADC_CFGR2_OVSS_Msk (0xFU << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */
@ -7235,7 +7233,7 @@ typedef struct
#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
((INSTANCE) == COMP2))
#define IS_COMP_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == COMP12_COMMON)
#define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON)
/******************************* CRC Instances ********************************/
#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)

14
targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/device/stm32l0xx.h
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32l0xx.h
* @author MCD Application Team
* @version V1.7.0
* @date 31-May-2016
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
* This file contains all the peripheral register's definitions, bits
* definitions and memory mapping for STM32L0xx devices.
@ -20,7 +18,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -114,16 +112,16 @@
#endif /* USE_HAL_DRIVER */
/**
* @brief CMSIS Device version number V1.7.0
* @brief CMSIS Device version number V1.7.1
*/
#define __STM32L0xx_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */
#define __STM32L0xx_CMSIS_VERSION_SUB1 (0x07) /*!< [23:16] sub1 version */
#define __STM32L0xx_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32L0xx_CMSIS_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */
#define __STM32L0xx_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32L0xx_CMSIS_VERSION ((__STM32L0xx_CMSIS_VERSION_MAIN << 24)\
|(__STM32L0xx_CMSIS_VERSION_SUB1 << 16)\
|(__STM32L0xx_CMSIS_VERSION_SUB2 << 8 )\
|(__STM32L0xx_CMSIS_VERSION_RC))
|(__STM32L0xx_CMSIS_VERSION_SUB1 << 16)\
|(__STM32L0xx_CMSIS_VERSION_SUB2 << 8 )\
|(__STM32L0xx_CMSIS_VERSION_RC))
/**
* @}

4
targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/device/system_stm32l0xx.h
View File

@ -2,13 +2,11 @@
******************************************************************************
* @file system_stm32l0xx.h
* @author MCD Application Team
* @version V1.7.0
* @date 31-May-2016
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Header File.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:

2
targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L072xZ/device/TOOLCHAIN_GCC_ARM/startup_stm32l072xx.S
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file startup_stm32l072xx.s
* @author MCD Application Team
* @version V1.7.1
* @date 25-November-2016
* @brief STM32L072xx Devices vector table for Atollic TrueSTUDIO toolchain.
* This module performs:
* - Set the initial SP

2
targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L072xZ/device/stm32l072xx.h
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32l072xx.h
* @author MCD Application Team
* @version V1.7.1
* @date 25-November-2016
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
* This file contains all the peripheral register's definitions, bits
* definitions and memory mapping for stm32l072xx devices.

14
targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L072xZ/device/stm32l0xx.h
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32l0xx.h
* @author MCD Application Team
* @version V1.7.0
* @date 31-May-2016
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
* This file contains all the peripheral register's definitions, bits
* definitions and memory mapping for STM32L0xx devices.
@ -20,7 +18,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -114,16 +112,16 @@
#endif /* USE_HAL_DRIVER */
/**
* @brief CMSIS Device version number V1.7.0
* @brief CMSIS Device version number V1.7.1
*/
#define __STM32L0xx_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */
#define __STM32L0xx_CMSIS_VERSION_SUB1 (0x07) /*!< [23:16] sub1 version */
#define __STM32L0xx_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32L0xx_CMSIS_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */
#define __STM32L0xx_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32L0xx_CMSIS_VERSION ((__STM32L0xx_CMSIS_VERSION_MAIN << 24)\
|(__STM32L0xx_CMSIS_VERSION_SUB1 << 16)\
|(__STM32L0xx_CMSIS_VERSION_SUB2 << 8 )\
|(__STM32L0xx_CMSIS_VERSION_RC))
|(__STM32L0xx_CMSIS_VERSION_SUB1 << 16)\
|(__STM32L0xx_CMSIS_VERSION_SUB2 << 8 )\
|(__STM32L0xx_CMSIS_VERSION_RC))
/**
* @}

4
targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L072xZ/device/system_stm32l0xx.h
View File

@ -2,13 +2,11 @@
******************************************************************************
* @file system_stm32l0xx.h
* @author MCD Application Team
* @version V1.7.0
* @date 31-May-2016
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Header File.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:

14
targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L0x2xZ/device/stm32l0xx.h
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32l0xx.h
* @author MCD Application Team
* @version V1.7.0
* @date 31-May-2016
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
* This file contains all the peripheral register's definitions, bits
* definitions and memory mapping for STM32L0xx devices.
@ -20,7 +18,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -114,16 +112,16 @@
#endif /* USE_HAL_DRIVER */
/**
* @brief CMSIS Device version number V1.7.0
* @brief CMSIS Device version number V1.7.1
*/
#define __STM32L0xx_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */
#define __STM32L0xx_CMSIS_VERSION_SUB1 (0x07) /*!< [23:16] sub1 version */
#define __STM32L0xx_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32L0xx_CMSIS_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */
#define __STM32L0xx_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32L0xx_CMSIS_VERSION ((__STM32L0xx_CMSIS_VERSION_MAIN << 24)\
|(__STM32L0xx_CMSIS_VERSION_SUB1 << 16)\
|(__STM32L0xx_CMSIS_VERSION_SUB2 << 8 )\
|(__STM32L0xx_CMSIS_VERSION_RC))
|(__STM32L0xx_CMSIS_VERSION_SUB1 << 16)\
|(__STM32L0xx_CMSIS_VERSION_SUB2 << 8 )\
|(__STM32L0xx_CMSIS_VERSION_RC))
/**
* @}

4
targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L0x2xZ/device/system_stm32l0xx.h
View File

@ -2,13 +2,11 @@
******************************************************************************
* @file system_stm32l0xx.h
* @author MCD Application Team
* @version V1.7.0
* @date 31-May-2016
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Header File.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:

193
targets/TARGET_STM/TARGET_STM32L0/device/stm32_hal_legacy.h
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32_hal_legacy.h
* @author MCD Application Team
* @version V1.7.0
* @date 31-May-2016
* @brief This file contains aliases definition for the STM32Cube HAL constants
* macros and functions maintained for legacy purpose.
******************************************************************************
@ -138,6 +136,9 @@
#define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5
#define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6
#define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7
#if defined(STM32L0)
#define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM input 1 for COMP1, LPTIM input 2 for COMP2 */
#endif
#define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR
#if defined(STM32F373xC) || defined(STM32F378xx)
#define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1
@ -196,6 +197,7 @@
#define COMP_BLANKINGSRCE_TIM3OC4 COMP_BLANKINGSRC_TIM3_OC4_COMP2
#define COMP_BLANKINGSRCE_TIM8OC5 COMP_BLANKINGSRC_TIM8_OC5_COMP2
#define COMP_BLANKINGSRCE_TIM15OC1 COMP_BLANKINGSRC_TIM15_OC1_COMP2
#define COMP_BLANKINGSRCE_NONE COMP_BLANKINGSRC_NONE
#endif
#if defined(STM32L0)
@ -263,7 +265,6 @@
#define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7
#define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67
#define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67
#define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32
#define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76
#define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6
#define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7
@ -354,6 +355,7 @@
#define OB_RDP_LEVEL0 OB_RDP_LEVEL_0
#define OB_RDP_LEVEL1 OB_RDP_LEVEL_1
#define OB_RDP_LEVEL2 OB_RDP_LEVEL_2
/**
* @}
*/
@ -454,6 +456,78 @@
* @}
*/
/** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose
* @{
*/
#if defined(STM32H7)
#define __HAL_RCC_JPEG_CLK_ENABLE __HAL_RCC_JPGDECEN_CLK_ENABLE
#define __HAL_RCC_JPEG_CLK_DISABLE __HAL_RCC_JPGDECEN_CLK_DISABLE
#define __HAL_RCC_JPEG_FORCE_RESET __HAL_RCC_JPGDECRST_FORCE_RESET
#define __HAL_RCC_JPEG_RELEASE_RESET __HAL_RCC_JPGDECRST_RELEASE_RESET
#define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE
#define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE
#define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1
#define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2
#define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX
#define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX
#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT
#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT
#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT
#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT
#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT
#define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT
#define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0
#define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO HAL_DMAMUX1_REQ_GEN_TIM12_TRGO
#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT
#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT
#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT
#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT
#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT
#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT
#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT
#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP
#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP
#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP
#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT
#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP
#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT
#define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP
#define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP
#define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP HAL_DMAMUX2_REQ_GEN_I2C4_WKUP
#define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP HAL_DMAMUX2_REQ_GEN_SPI6_WKUP
#define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT HAL_DMAMUX2_REQ_GEN_COMP1_OUT
#define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT HAL_DMAMUX2_REQ_GEN_COMP2_OUT
#define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP HAL_DMAMUX2_REQ_GEN_RTC_WKUP
#define HAL_DMAMUX2_REQUEST_GEN_EXTI0 HAL_DMAMUX2_REQ_GEN_EXTI0
#define HAL_DMAMUX2_REQUEST_GEN_EXTI2 HAL_DMAMUX2_REQ_GEN_EXTI2
#define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT
#define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT HAL_DMAMUX2_REQ_GEN_SPI6_IT
#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT
#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT
#define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT HAL_DMAMUX2_REQ_GEN_ADC3_IT
#define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT
#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT
#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT
#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT
#define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING
#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING
#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING
#endif /* STM32H7 */
/**
* @}
*/
/** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose
* @{
*/
@ -667,7 +741,6 @@
#define FORMAT_BCD RTC_FORMAT_BCD
#define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE
#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE
#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE
#define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
#define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
@ -675,9 +748,6 @@
#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE
#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE
#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
#define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
@ -851,6 +921,8 @@
#define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8
#define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8
#define __DIV_LPUART UART_DIV_LPUART
#define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE
#define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK
@ -941,9 +1013,12 @@
#define ETH_MAC_RXFIFO_BELOW_THRESHOLD ((uint32_t)0x00000100) /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD ((uint32_t)0x00000200) /* Rx FIFO fill level: fill-level above flow-control activate threshold */
#define ETH_MAC_RXFIFO_FULL ((uint32_t)0x00000300) /* Rx FIFO fill level: full */
#if defined(STM32F1)
#else
#define ETH_MAC_READCONTROLLER_IDLE ((uint32_t)0x00000000) /* Rx FIFO read controller IDLE state */
#define ETH_MAC_READCONTROLLER_READING_DATA ((uint32_t)0x00000020) /* Rx FIFO read controller Reading frame data */
#define ETH_MAC_READCONTROLLER_READING_STATUS ((uint32_t)0x00000040) /* Rx FIFO read controller Reading frame status (or time-stamp) */
#endif
#define ETH_MAC_READCONTROLLER_FLUSHING ((uint32_t)0x00000060) /* Rx FIFO read controller Flushing the frame data and status */
#define ETH_MAC_RXFIFO_WRITE_ACTIVE ((uint32_t)0x00000010) /* Rx FIFO write controller active */
#define ETH_MAC_SMALL_FIFO_NOTACTIVE ((uint32_t)0x00000000) /* MAC small FIFO read / write controllers not active */
@ -1304,7 +1379,6 @@
#define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV
#define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection
#define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq
#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION
#define __HAL_ADC_JSQR ADC_JSQR
#define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL
@ -1777,20 +1851,20 @@
#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback
#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE
#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE
#define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE
#define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE
#define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET
#define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET
#define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE
#define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE
#define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET
#define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET
#define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE
#define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE
#define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE
#define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE
#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE
#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE
#define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE
#define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE
#define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET
#define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET
#define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE
#define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE
#define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET
#define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET
#define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE
#define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE
#define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE
#define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE
#define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET
#define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET
#define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE
@ -1807,7 +1881,7 @@
#define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE
#define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE
#define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE
#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET
#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET
#define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET
#define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE
#define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE
@ -2223,26 +2297,26 @@
#define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE
#define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET
#define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET
#define __USART4_CLK_DISABLE __HAL_RCC_USART4_CLK_DISABLE
#define __USART4_CLK_ENABLE __HAL_RCC_USART4_CLK_ENABLE
#define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_USART4_CLK_SLEEP_ENABLE
#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_USART4_CLK_SLEEP_DISABLE
#define __USART4_FORCE_RESET __HAL_RCC_USART4_FORCE_RESET
#define __USART4_RELEASE_RESET __HAL_RCC_USART4_RELEASE_RESET
#define __USART5_CLK_DISABLE __HAL_RCC_USART5_CLK_DISABLE
#define __USART5_CLK_ENABLE __HAL_RCC_USART5_CLK_ENABLE
#define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_USART5_CLK_SLEEP_ENABLE
#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_USART5_CLK_SLEEP_DISABLE
#define __USART5_FORCE_RESET __HAL_RCC_USART5_FORCE_RESET
#define __USART5_RELEASE_RESET __HAL_RCC_USART5_RELEASE_RESET
#define __USART7_CLK_DISABLE __HAL_RCC_USART7_CLK_DISABLE
#define __USART7_CLK_ENABLE __HAL_RCC_USART7_CLK_ENABLE
#define __USART7_FORCE_RESET __HAL_RCC_USART7_FORCE_RESET
#define __USART7_RELEASE_RESET __HAL_RCC_USART7_RELEASE_RESET
#define __USART8_CLK_DISABLE __HAL_RCC_USART8_CLK_DISABLE
#define __USART8_CLK_ENABLE __HAL_RCC_USART8_CLK_ENABLE
#define __USART8_FORCE_RESET __HAL_RCC_USART8_FORCE_RESET
#define __USART8_RELEASE_RESET __HAL_RCC_USART8_RELEASE_RESET
#define __USART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE
#define __USART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE
#define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE
#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE
#define __USART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET
#define __USART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET
#define __USART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE
#define __USART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE
#define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE
#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE
#define __USART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET
#define __USART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET
#define __USART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE
#define __USART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE
#define __USART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET
#define __USART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET
#define __USART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE
#define __USART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE
#define __USART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET
#define __USART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET
#define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE
#define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE
#define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET
@ -2402,7 +2476,6 @@
#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED
#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED
#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET
#define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE
#define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE
#define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE
@ -2435,8 +2508,6 @@
#define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
#define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE
#define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE
#define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE
#define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
#define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE
#define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE
#define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE
@ -2458,8 +2529,6 @@
#define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
#define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET
#define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET
#define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
#define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
#define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET
#define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET
#define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET
@ -2644,10 +2713,22 @@
#define RCC_IT_HSI14 RCC_IT_HSI14RDY
#if defined(STM32L0)
#define RCC_IT_LSECSS RCC_IT_CSSLSE
#define RCC_IT_CSS RCC_IT_CSSHSE
#endif
#define RCC_IT_CSSLSE RCC_IT_LSECSS
#define RCC_IT_CSSHSE RCC_IT_CSS
#define RCC_PLLMUL_3 RCC_PLL_MUL3
#define RCC_PLLMUL_4 RCC_PLL_MUL4
#define RCC_PLLMUL_6 RCC_PLL_MUL6
#define RCC_PLLMUL_8 RCC_PLL_MUL8
#define RCC_PLLMUL_12 RCC_PLL_MUL12
#define RCC_PLLMUL_16 RCC_PLL_MUL16
#define RCC_PLLMUL_24 RCC_PLL_MUL24
#define RCC_PLLMUL_32 RCC_PLL_MUL32
#define RCC_PLLMUL_48 RCC_PLL_MUL48
#define RCC_PLLDIV_2 RCC_PLL_DIV2
#define RCC_PLLDIV_3 RCC_PLL_DIV3
#define RCC_PLLDIV_4 RCC_PLL_DIV4
#define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE
#define __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG
@ -2672,7 +2753,10 @@
#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK
#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2
#if defined(STM32WB) || defined(STM32G0)
#else
#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
#endif
#define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1
#define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL
@ -2768,7 +2852,6 @@
#define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK
#define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG
#define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE
/**
* @}
*/
@ -2785,8 +2868,10 @@
/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
* @{
*/
#if defined (STM32G0)
#else
#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
#endif
#define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT
#define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT

8
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal.c
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@ -2,8 +2,6 @@
******************************************************************************
* @file stm32l0xx_hal.c
* @author MCD Application Team
* @version V1.7.0
* @date 31-May-2016
* @brief HAL module driver.
* This is the common part of the HAL initialization
*
@ -86,11 +84,11 @@ __IO uint32_t uwTick;
*/
/**
* @brief STM32L0xx HAL Driver version number V1.7.0
* @brief STM32L0xx HAL Driver version number
*/
#define __STM32L0xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */
#define __STM32L0xx_HAL_VERSION_SUB1 (0x07U) /*!< [23:16] sub1 version */
#define __STM32L0xx_HAL_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */
#define __STM32L0xx_HAL_VERSION_SUB1 (0x08U) /*!< [23:16] sub1 version */
#define __STM32L0xx_HAL_VERSION_SUB2 (0x02U) /*!< [15:8] sub2 version */
#define __STM32L0xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __STM32L0xx_HAL_VERSION ((__STM32L0xx_HAL_VERSION_MAIN << 24U)\
|(__STM32L0xx_HAL_VERSION_SUB1 << 16U)\

6
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal.h
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32l0xx_hal.h
* @author MCD Application Team
* @version V1.7.0
* @date 31-May-2016
* @brief This file contains all the functions prototypes for the HAL
* module driver.
******************************************************************************
@ -346,7 +344,7 @@
* @arg SYSCFG_FASTMODEPLUS_PB9
*/
#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__))); \
SET_BIT(SYSCFG->CFGR2, __FASTMODEPLUS__); \
SET_BIT(SYSCFG->CFGR2, (__FASTMODEPLUS__)); \
}while(0)
/** @brief Fast mode Plus driving capability disable macro
* @param __FASTMODEPLUS__: This parameter can be a value of :
@ -356,7 +354,7 @@
* @arg SYSCFG_FASTMODEPLUS_PB9
*/
#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__))); \
CLEAR_BIT(SYSCFG->CFGR2, __FASTMODEPLUS__); \
CLEAR_BIT(SYSCFG->CFGR2, (__FASTMODEPLUS__)); \
}while(0)

603
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_adc.c
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File diff suppressed because it is too large Load Diff

544
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_adc.h
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@ -2,10 +2,7 @@
******************************************************************************
* @file stm32l0xx_hal_adc.h
* @author MCD Application Team
* @version V1.7.0
* @date 31-May-2016
* @brief This file contains all the functions prototypes for the ADC firmware
* library.
* @brief Header file of ADC HAL module.
******************************************************************************
* @attention
*
@ -37,8 +34,8 @@
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32L0xx_ADC_H
#define __STM32L0xx_ADC_H
#ifndef __STM32L0xx_HAL_ADC_H
#define __STM32L0xx_HAL_ADC_H
#ifdef __cplusplus
extern "C" {
@ -46,150 +43,242 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32l0xx_hal_def.h"
/** @addtogroup STM32L0xx_HAL_Driver
* @{
*/
/** @defgroup ADC ADC
/** @addtogroup ADC
* @{
*/
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup ADC_Exported_Types ADC Exported Types
* @{
*/
/* Exported types ------------------------------------------------------------*/
/**
* @brief HAL ADC state machine: ADC states definition (bitfields)
*/
/* States of ADC global scope */
#define HAL_ADC_STATE_RESET ((uint32_t)0x00000000U) /*!< ADC not yet initialized or disabled */
#define HAL_ADC_STATE_READY ((uint32_t)0x00000001U) /*!< ADC peripheral ready for use */
#define HAL_ADC_STATE_BUSY_INTERNAL ((uint32_t)0x00000002U) /*!< ADC is busy to internal process (initialization, calibration) */
#define HAL_ADC_STATE_TIMEOUT ((uint32_t)0x00000004U) /*!< TimeOut occurrence */
/* States of ADC errors */
#define HAL_ADC_STATE_ERROR_INTERNAL ((uint32_t)0x00000010U) /*!< Internal error occurrence */
#define HAL_ADC_STATE_ERROR_CONFIG ((uint32_t)0x00000020U) /*!< Configuration error occurrence */
#define HAL_ADC_STATE_ERROR_DMA ((uint32_t)0x00000040U) /*!< DMA error occurrence */
/* States of ADC group regular */
#define HAL_ADC_STATE_REG_BUSY ((uint32_t)0x00000100U) /*!< A conversion on group regular is ongoing or can occur (either by continuous mode,
external trigger, low power auto power-on, multimode ADC master control) */
#define HAL_ADC_STATE_REG_EOC ((uint32_t)0x00000200U) /*!< Conversion data available on group regular */
#define HAL_ADC_STATE_REG_OVR ((uint32_t)0x00000400U) /*!< Overrun occurrence */
#define HAL_ADC_STATE_REG_EOSMP ((uint32_t)0x00000800U) /*!< Not available on STM32F0 device: End Of Sampling flag raised */
/* States of ADC group injected */
#define HAL_ADC_STATE_INJ_BUSY ((uint32_t)0x00001000U) /*!< Not available on STM32F0 device: A conversion on group injected is ongoing or can occur (either by auto-injection mode,
external trigger, low power auto power-on, multimode ADC master control) */
#define HAL_ADC_STATE_INJ_EOC ((uint32_t)0x00002000U) /*!< Not available on STM32F0 device: Conversion data available on group injected */
#define HAL_ADC_STATE_INJ_JQOVF ((uint32_t)0x00004000U) /*!< Not available on STM32F0 device: Not available on STM32F0 device: Injected queue overflow occurrence */
/* States of ADC analog watchdogs */
#define HAL_ADC_STATE_AWD1 ((uint32_t)0x00010000U) /*!< Out-of-window occurrence of analog watchdog 1 */
#define HAL_ADC_STATE_AWD2 ((uint32_t)0x00020000U) /*!< Not available on STM32F0 device: Out-of-window occurrence of analog watchdog 2 */
#define HAL_ADC_STATE_AWD3 ((uint32_t)0x00040000U) /*!< Not available on STM32F0 device: Out-of-window occurrence of analog watchdog 3 */
/* States of ADC multi-mode */
#define HAL_ADC_STATE_MULTIMODE_SLAVE ((uint32_t)0x00100000U) /*!< Not available on STM32F0 device: ADC in multimode slave state, controlled by another ADC master ( */
/**
* @brief ADC Oversampler structure definition
* @brief ADC group regular oversampling structure definition
*/
typedef struct
{
uint32_t Ratio; /*!< Configures the oversampling ratio.
This parameter can be a value of @ref ADC_Oversampling_Ratio */
uint32_t RightBitShift; /*!< Configures the division coefficient for the Oversampler.
This parameter can be a value of @ref ADC_Right_Bit_Shift */
uint32_t TriggeredMode; /*!< Selects the regular triggered oversampling mode
uint32_t TriggeredMode; /*!< Selects the regular triggered oversampling mode.
This parameter can be a value of @ref ADC_Triggered_Oversampling_Mode */
}ADC_OversamplingTypeDef;
/**
* @brief ADC Init structure definition
* @note The setting of these parameters with function HAL_ADC_Init() is conditioned by the ADC state.
* @brief Structure definition of ADC instance and ADC group regular.
* @note Parameters of this structure are shared within 2 scopes:
* - Scope entire ADC (differentiation done for compatibility with some other STM32 series featuring ADC groups regular and injected): ClockPrescaler, Resolution, DataAlign,
* ScanConvMode, EOCSelection, LowPowerAutoWait.
* - Scope ADC group regular: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode,
* ExternalTrigConv, ExternalTrigConvEdge, DMAContinuousRequests, Overrun, OversamplingMode, Oversampling.
* @note The setting of these parameters by function HAL_ADC_Init() is conditioned to ADC state.
* ADC state can be either:
* - For all parameters: ADC disabled
* - For all parameters except 'ClockPrescaler' and 'Resolution': ADC enabled without conversion on going on group regular.
* If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
* without error reporting (as it can be the expected behavior in case of intended action to update antother parameter (which fullfills the ADC state condition) on the fly).
* without error reporting (as it can be the expected behavior in case of intended action to update another parameter
* (which fulfills the ADC state condition) on the fly).
*/
typedef struct
{
uint32_t OversamplingMode; /*!< Specifies whether the oversampling feature is enabled or disabled
This parameter can be set to ENABLE or DISABLE.
Note: This parameter can be modified only if there is no conversion is ongoing. */
ADC_OversamplingTypeDef Oversample; /*!< Specifies the Oversampling parameters
Note: This parameter can be modified only if there is no conversion is ongoing. */
uint32_t ClockPrescaler; /*!< Selects the ADC clock frequency.
This parameter can be a value of @ref ADC_ClockPrescaler
Note: This parameter can be modified only if ADC is disabled.
Note: In case of Synchronous clock mode divided by 1, this configuration must be enabled only
if PCLK has a 50% duty clock cycle (APB prescaler configured inside the RCC
must be bypassed and the system clock must by 50% duty cycle). Refer to reference manual for details */
uint32_t Resolution; /*!< Configures the ADC resolution mode.
This parameter can be a value of @ref ADC_Resolution
Note: This parameter can be modified only if ADC is disabled. */
uint32_t SamplingTime; /*!< The sample time value to be set for all channels.
uint32_t ClockPrescaler; /*!< Select ADC clock source (synchronous clock derived from APB clock or asynchronous clock derived from ADC dedicated HSI RC oscillator) and clock prescaler.
This parameter can be a value of @ref ADC_ClockPrescaler.
Note: In case of synchronous clock mode based on HCLK/1, the configuration must be enabled only
if the system clock has a 50% duty clock cycle (APB prescaler configured inside RCC
must be bypassed and PCLK clock must have 50% duty cycle). Refer to reference manual for details.
Note: In case of usage of the ADC dedicated HSI RC oscillator, it must be preliminarily enabled at RCC top level.
Note: This parameter can be modified only if the ADC is disabled. */
uint32_t Resolution; /*!< Configure the ADC resolution.
This parameter can be a value of @ref ADC_Resolution */
uint32_t DataAlign; /*!< Specify ADC data alignment in conversion data register (right or left).
Refer to reference manual for alignments formats versus resolutions.
This parameter can be a value of @ref ADC_Data_align */
uint32_t ScanConvMode; /*!< Configure the sequencer of regular group.
This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts.
Sequencer is automatically enabled if several channels are set (sequencer cannot be disabled, as it can be the case on other STM32 devices):
If only 1 channel is set: Conversion is performed in single mode.
If several channels are set: Conversions are performed in sequence mode (ranks defined by each channel number: channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
Scan direction can be set to forward (from channel 0 to channel 18) or backward (from channel 18 to channel 0).
This parameter can be a value of @ref ADC_Scan_mode */
uint32_t EOCSelection; /*!< Specify which EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of unitary conversion or end of sequence conversions.
This parameter can be a value of @ref ADC_EOCSelection. */
uint32_t LowPowerAutoWait; /*!< Select the dynamic low power Auto Delay: new conversion start only when the previous
conversion (for ADC group regular) has been retrieved by user software,
using function HAL_ADC_GetValue().
This feature automatically adapts the frequency of ADC conversions triggers to the speed of the system that reads the data. Moreover, this avoids risk of overrun
for low frequency applications.
This parameter can be set to ENABLE or DISABLE.
Note: Do not use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since they clear immediately the EOC flag
to free the IRQ vector sequencer.
Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, when ADC conversion data is needed:
use HAL_ADC_PollForConversion() to ensure that conversion is completed and HAL_ADC_GetValue() to retrieve conversion result and trig another conversion start. */
uint32_t LowPowerAutoPowerOff; /*!< Select the auto-off mode: the ADC automatically powers-off after a conversion and automatically wakes-up when a new conversion is triggered (with startup time between trigger and start of sampling).
This feature can be combined with automatic wait mode (parameter 'LowPowerAutoWait').
This parameter can be set to ENABLE or DISABLE.
Note: If enabled, this feature also turns off the ADC dedicated 14 MHz RC oscillator (HSI14) */
uint32_t ContinuousConvMode; /*!< Specify whether the conversion is performed in single mode (one conversion) or continuous mode for ADC group regular,
after the first ADC conversion start trigger occurred (software start or external trigger).
This parameter can be set to ENABLE or DISABLE. */
uint32_t DiscontinuousConvMode; /*!< Specify whether the conversions sequence of ADC group regular is performed in Complete-sequence/Discontinuous-sequence
(main sequence subdivided in successive parts).
Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
This parameter can be set to ENABLE or DISABLE.
Note: On this STM32 serie, ADC group regular number of discontinuous ranks increment is fixed to one-by-one. */
uint32_t ExternalTrigConv; /*!< Select the external event source used to trigger ADC group regular conversion start.
If set to ADC_SOFTWARE_START, external triggers are disabled and software trigger is used instead.
This parameter can be a value of @ref ADC_regular_external_trigger_source.
Caution: external trigger source is common to all ADC instances. */
uint32_t ExternalTrigConvEdge; /*!< Select the external event edge used to trigger ADC group regular conversion start.
If trigger source is set to ADC_SOFTWARE_START, this parameter is discarded.
This parameter can be a value of @ref ADC_regular_external_trigger_edge */
uint32_t DMAContinuousRequests; /*!< Specify whether the DMA requests are performed in one shot mode (DMA transfer stops when number of conversions is reached)
or in continuous mode (DMA transfer unlimited, whatever number of conversions).
This parameter can be set to ENABLE or DISABLE.
Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached. */
uint32_t Overrun; /*!< Select the behavior in case of overrun: data overwritten or preserved (default).
This parameter can be a value of @ref ADC_Overrun.
Note: In case of overrun set to data preserved and usage with programming model with interruption (HAL_Start_IT()): ADC IRQ handler has to clear
end of conversion flags, this induces the release of the preserved data. If needed, this data can be saved in function
HAL_ADC_ConvCpltCallback(), placed in user program code (called before end of conversion flags clear).
Note: Error reporting with respect to the conversion mode:
- Usage with ADC conversion by polling for event or interruption: Error is reported only if overrun is set to data preserved. If overrun is set to data
overwritten, user can willingly not read all the converted data, this is not considered as an erroneous case.
- Usage with ADC conversion by DMA: Error is reported whatever overrun setting (DMA is expected to process all data from data register). */
uint32_t LowPowerFrequencyMode; /*!< When selecting an analog ADC clock frequency lower than 2.8MHz,
it is mandatory to first enable the Low Frequency Mode.
This parameter can be set to ENABLE or DISABLE.
Note: This parameter can be modified only if there is no conversion is ongoing. */
uint32_t SamplingTime; /*!< The sample time common to all channels.
Unit: ADC clock cycles
This parameter can be a value of @ref ADC_sampling_times
Note: This parameter can be modified only if there is no conversion ongoing. */
uint32_t ScanConvMode; /*!< The scan sequence direction.
If several channels are set: Conversions are performed in sequence mode
(ranks defined by each channel number: channel 0 fixed on rank 0,
channel 1 fixed on rank1, ...).
This parameter can be a value of @ref ADC_Scan_mode
Note: This parameter can be modified only if there is no conversion is ongoing. */
uint32_t DataAlign; /*!< Specifies whether the ADC data alignment is left or right.
This parameter can be a value of @ref ADC_data_align
Note: This parameter can be modified only if there is no conversion is ongoing. */
uint32_t ContinuousConvMode; /*!< Specifies whether the conversion is performed in Continuous or Single mode.
This parameter can be set to ENABLE or DISABLE.
Note: This parameter can be modified only if there is no conversion is ongoing. */
uint32_t DiscontinuousConvMode; /*!< Specifies whether the conversion is performed
in Complete-sequence/Discontinuous-sequence.
Discontinuous mode can be enabled only if continuous mode is disabled.
This parameter can be set to ENABLE or DISABLE.
Note: This parameter can be modified only if there is no conversion is ongoing. */
uint32_t ExternalTrigConv; /*!< Select the external event used to trigger the start of conversion.
If set to ADC_SOFTWARE_START, external triggers are disabled.
This parameter can be a value of @ref ADC_External_trigger_Source
Note: This parameter can be modified only if there is no conversion is ongoing. */
uint32_t ExternalTrigConvEdge; /*!< Select the external trigger edge and enable the trigger.
If trigger is set to ADC_SOFTWARE_START, this parameter is discarded.
This parameter can be a value of @ref ADC_Regular_External_Trigger_Source_Edge
Note: This parameter can be modified only if there is no conversion is ongoing. */
uint32_t DMAContinuousRequests; /*!< Specifies whether the DMA requests are performed in one shot mode (DMA transfer stop when number of conversions is reached)
or in Continuous mode (DMA transfer unlimited, whatever number of conversions).
Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer max pointer is reached.
This parameter can be set to ENABLE or DISABLE.
Note: This parameter can be modified only if there is no conversion is ongoing. */
uint32_t EOCSelection; /*!< Specifies what EOC (End Of Conversion) flag is used for conversion polling and interruption:
end of single channel conversion or end of channels conversions sequence.
This parameter can be a value of @ref ADC_EOCSelection */
uint32_t Overrun; /*!< Select the behaviour in case of overrun: data preserved or overwritten
This parameter has an effect on regular channels only, including in DMA mode.
This parameter can be a value of @ref ADC_Overrun
Note: This parameter can be modified only if there is no conversion is ongoing. */
uint32_t LowPowerAutoWait; /*!< Specifies the usage of dynamic low power Auto Delay: new conversion start only
when the previous conversion (for regular channel) is completed.
This avoids risk of overrun for low frequency application.
This parameter can be set to ENABLE or DISABLE.
Note: This parameter can be modified only if there is no conversion is ongoing. */
uint32_t LowPowerFrequencyMode; /*!< When selecting an analog ADC clock frequency lower than 2.8MHz,
it is mandatory to first enable the Low Frequency Mode.
This parameter can be set to ENABLE or DISABLE.
Note: This parameter can be modified only if there is no conversion is ongoing. */
uint32_t LowPowerAutoPowerOff; /*!< When setting the AutoOff feature, the ADC is always powered off when not converting and automatically
wakes-up when a conversion is started (by software or hardware trigger).
This parameter can be set to ENABLE or DISABLE.
Note: This parameter can be modified only if there is no conversion is ongoing. */
uint32_t OversamplingMode; /*!< Specify whether the oversampling feature is enabled or disabled.
This parameter can be set to ENABLE or DISABLE.
Note: This parameter can be modified only if there is no conversion is ongoing on ADC group regular. */
ADC_OversamplingTypeDef Oversample; /*!< Specify the Oversampling parameters
Caution: this setting overwrites the previous oversampling configuration if oversampling is already enabled. */
}ADC_InitTypeDef;
/**
* @brief Structure definition of ADC channel for regular group
* @note The setting of these parameters by function HAL_ADC_ConfigChannel() is conditioned to ADC state.
* ADC state can be either:
* - For all parameters: ADC disabled or enabled without conversion on going on regular group.
* If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
* without error reporting (as it can be the expected behavior in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly).
*/
typedef struct
{
uint32_t Channel; /*!< Specify the channel to configure into ADC regular group.
This parameter can be a value of @ref ADC_channels
Note: Depending on devices, some channels may not be available on device package pins. Refer to device datasheet for channels availability. */
uint32_t Rank; /*!< Add or remove the channel from ADC regular group sequencer.
On STM32L0 devices, number of ranks in the sequence is defined by number of channels enabled, rank of each channel is defined by channel number
(channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
Despite the channel rank is fixed, this parameter allow an additional possibility: to remove the selected rank (selected channel) from sequencer.
This parameter can be a value of @ref ADC_rank */
}ADC_ChannelConfTypeDef;
/**
* @brief Structure definition of ADC analog watchdog
* @note The setting of these parameters by function HAL_ADC_AnalogWDGConfig() is conditioned to ADC state.
* ADC state can be either:
* - For all parameters: ADC disabled or ADC enabled without conversion on going on ADC group regular
* - For parameters 'HighThreshold' and 'LowThreshold': ADC enabled with conversion on going on regular group (AWD thresholds can be modify on the fly while ADC conversion is on going)
*/
typedef struct
{
uint32_t WatchdogMode; /*!< Configure the ADC analog watchdog mode: single/all channels.
This parameter can be a value of @ref ADC_analog_watchdog_mode */
uint32_t Channel; /*!< Select which ADC channel to monitor by analog watchdog.
This parameter has an effect only if watchdog mode is configured on single channel (parameter WatchdogMode)
This parameter can be a value of @ref ADC_channels */
uint32_t ITMode; /*!< Specify whether the analog watchdog is configured in interrupt or polling mode.
This parameter can be set to ENABLE or DISABLE */
uint32_t HighThreshold; /*!< Configures the ADC analog watchdog High threshold value.
Depending of ADC resolution selected (12, 10, 8 or 6 bits),
this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */
uint32_t LowThreshold; /*!< Configures the ADC analog watchdog High threshold value.
Depending of ADC resolution selected (12, 10, 8 or 6 bits),
this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */
}ADC_AnalogWDGConfTypeDef;
/**
* @brief HAL ADC state machine: ADC states definition (bitfields)
* @note ADC state machine is managed by bitfields, state must be compared
* with bit by bit.
* For example:
* " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_REG_BUSY)) "
* " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_AWD1) ) "
*/
/* States of ADC global scope */
#define HAL_ADC_STATE_RESET ((uint32_t)0x00000000) /*!< ADC not yet initialized or disabled */
#define HAL_ADC_STATE_READY ((uint32_t)0x00000001) /*!< ADC peripheral ready for use */
#define HAL_ADC_STATE_BUSY_INTERNAL ((uint32_t)0x00000002) /*!< ADC is busy due to an internal process (initialization, calibration) */
#define HAL_ADC_STATE_TIMEOUT ((uint32_t)0x00000004) /*!< TimeOut occurrence */
/* States of ADC errors */
#define HAL_ADC_STATE_ERROR_INTERNAL ((uint32_t)0x00000010) /*!< Internal error occurrence */
#define HAL_ADC_STATE_ERROR_CONFIG ((uint32_t)0x00000020) /*!< Configuration error occurrence */
#define HAL_ADC_STATE_ERROR_DMA ((uint32_t)0x00000040) /*!< DMA error occurrence */
/* States of ADC group regular */
#define HAL_ADC_STATE_REG_BUSY ((uint32_t)0x00000100) /*!< A conversion on ADC group regular is ongoing or can occur (either by continuous mode,
external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
#define HAL_ADC_STATE_REG_EOC ((uint32_t)0x00000200) /*!< Conversion data available on group regular */
#define HAL_ADC_STATE_REG_OVR ((uint32_t)0x00000400) /*!< Overrun occurrence */
#define HAL_ADC_STATE_REG_EOSMP ((uint32_t)0x00000800) /*!< Not available on this STM32 serie: End Of Sampling flag raised */
/* States of ADC group injected */
#define HAL_ADC_STATE_INJ_BUSY ((uint32_t)0x00001000) /*!< Not available on this STM32 serie: A conversion on group injected is ongoing or can occur (either by auto-injection mode,
external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
#define HAL_ADC_STATE_INJ_EOC ((uint32_t)0x00002000) /*!< Not available on this STM32 serie: Conversion data available on group injected */
#define HAL_ADC_STATE_INJ_JQOVF ((uint32_t)0x00004000) /*!< Not available on this STM32 serie: Injected queue overflow occurrence */
/* States of ADC analog watchdogs */
#define HAL_ADC_STATE_AWD1 ((uint32_t)0x00010000) /*!< Out-of-window occurrence of ADC analog watchdog 1 */
#define HAL_ADC_STATE_AWD2 ((uint32_t)0x00020000) /*!< Not available on this STM32 serie: Out-of-window occurrence of ADC analog watchdog 2 */
#define HAL_ADC_STATE_AWD3 ((uint32_t)0x00040000) /*!< Not available on this STM32 serie: Out-of-window occurrence of ADC analog watchdog 3 */
/* States of ADC multi-mode */
#define HAL_ADC_STATE_MULTIMODE_SLAVE ((uint32_t)0x00100000) /*!< Not available on this STM32 serie: ADC in multimode slave state, controlled by another ADC master (when feature available) */
/**
* @brief ADC handle Structure definition
*/
* @brief ADC handle Structure definition
*/
typedef struct
{
ADC_TypeDef *Instance; /*!< Register base address */
@ -204,43 +293,6 @@ typedef struct
__IO uint32_t ErrorCode; /*!< ADC Error code */
}ADC_HandleTypeDef;
/**
* @brief ADC Configuration regular Channel structure definition
*/
typedef struct
{
uint32_t Channel; /*!< the ADC channel to configure
This parameter can be a value of @ref ADC_channels */
uint32_t Rank; /*!< Add or remove the channel from ADC regular group sequencer.
On STM32L0 devices, number of ranks in the sequence is defined by number of channels enabled, rank of each channel is defined by channel number
(channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
Despite the channel rank is fixed, this parameter allow an additional possibility: to remove the selected rank (selected channel) from sequencer.
This parameter can be a value of @ref ADC_rank */
}ADC_ChannelConfTypeDef;
/**
* @brief ADC Configuration analog watchdog definition
*/
typedef struct
{
uint32_t WatchdogMode; /*!< Configures the ADC analog watchdog mode: single/all channels.
This parameter can be a value of @ref ADC_analog_watchdog_mode */
uint32_t Channel; /*!< Selects which ADC channel to monitor by analog watchdog.
This parameter has an effect only if watchdog mode is configured on single channel (parameter WatchdogMode)
This parameter can be a value of @ref ADC_channels */
uint32_t ITMode; /*!< Specifies whether the analog watchdog is configured in interrupt or polling mode.
This parameter can be set to ENABLE or DISABLE */
uint32_t HighThreshold; /*!< Configures the ADC analog watchdog High threshold value.
Depending of ADC resolution selected (12, 10, 8 or 6 bits),
this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */
uint32_t LowThreshold; /*!< Configures the ADC analog watchdog High threshold value.
Depending of ADC resolution selected (12, 10, 8 or 6 bits),
this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */
}ADC_AnalogWDGConfTypeDef;
/**
* @}
*/
@ -254,19 +306,19 @@ typedef struct
/** @defgroup ADC_Error_Code ADC Error Code
* @{
*/
#define HAL_ADC_ERROR_NONE ((uint32_t)0x00U) /*!< No error */
#define HAL_ADC_ERROR_INTERNAL ((uint32_t)0x01U) /*!< ADC IP internal error: if problem of clocking,
enable/disable, erroneous state */
#define HAL_ADC_ERROR_OVR ((uint32_t)0x02U) /*!< OVR error */
#define HAL_ADC_ERROR_DMA ((uint32_t)0x04U) /*!< DMA transfer error */
*/
#define HAL_ADC_ERROR_NONE ((uint32_t)0x00U) /*!< No error */
#define HAL_ADC_ERROR_INTERNAL ((uint32_t)0x01U) /*!< ADC IP internal error (problem of clocking,
enable/disable, erroneous state, ...) */
#define HAL_ADC_ERROR_OVR ((uint32_t)0x02U) /*!< Overrun error */
#define HAL_ADC_ERROR_DMA ((uint32_t)0x04U) /*!< DMA transfer error */
/**
* @}
*/
*/
/** @defgroup ADC_TimeOut_Values ADC TimeOut Values
* @{
*/
*/
/* Fixed timeout values for ADC calibration, enable settling time, disable */
/* settling time. */
@ -313,28 +365,27 @@ typedef struct
/** @defgroup ADC_Resolution ADC Resolution
* @{
*/
#define ADC_RESOLUTION_12B ((uint32_t)0x00000000U) /*!< ADC 12-bit resolution */
#define ADC_RESOLUTION_10B ((uint32_t)ADC_CFGR1_RES_0) /*!< ADC 10-bit resolution */
#define ADC_RESOLUTION_8B ((uint32_t)ADC_CFGR1_RES_1) /*!< ADC 8-bit resolution */
#define ADC_RESOLUTION_6B ((uint32_t)ADC_CFGR1_RES) /*!< ADC 6-bit resolution */
*/
#define ADC_RESOLUTION_12B ((uint32_t)0x00000000U) /*!< ADC 12-bit resolution */
#define ADC_RESOLUTION_10B ((uint32_t)ADC_CFGR1_RES_0) /*!< ADC 10-bit resolution */
#define ADC_RESOLUTION_8B ((uint32_t)ADC_CFGR1_RES_1) /*!< ADC 8-bit resolution */
#define ADC_RESOLUTION_6B ((uint32_t)ADC_CFGR1_RES) /*!< ADC 6-bit resolution */
/**
* @}
*/
*/
/** @defgroup ADC_data_align ADC Data Align
/** @defgroup ADC_Data_align ADC conversion data alignment
* @{
*/
*/
#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000U)
#define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CFGR1_ALIGN)
/**
* @}
*/
*/
/** @defgroup ADC_Regular_External_Trigger_Source_Edge ADC External Trigger Source Edge for Regular Group
/** @defgroup ADC_regular_external_trigger_edge ADC External Trigger Source Edge for Regular Group
* @{
*/
*/
#define ADC_EXTERNALTRIGCONVEDGE_NONE ((uint32_t)0x00000000U)
#define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CFGR1_EXTEN_0)
#define ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CFGR1_EXTEN_1)
@ -360,12 +411,12 @@ typedef struct
#define ADC_OVR_DATA_OVERWRITTEN ((uint32_t)ADC_CFGR1_OVRMOD)
/**
* @}
*/
*/
/** @defgroup ADC_rank ADC rank
* @{
*/
*/
#define ADC_RANK_CHANNEL_NUMBER ((uint32_t)0x00001000U) /*!< Enable the rank of the selected channels. Number of ranks in the sequence is defined by number of channels enabled, rank of each channel is defined by channel number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...) */
#define ADC_RANK_NONE ((uint32_t)0x00001001U) /*!< Disable the selected rank (selected channel) from sequencer */
/**
@ -417,24 +468,21 @@ typedef struct
* @}
*/
/** @defgroup ADC_sampling_times ADC Sampling Cycles
* @{
*/
#define ADC_SAMPLETIME_1CYCLE_5 ((uint32_t)0x00000000U) /*!< ADC sampling time 1.5 cycle */
#define ADC_SAMPLETIME_7CYCLES_5 ((uint32_t)ADC_SMPR_SMPR_0) /*!< ADC sampling time 7.5 CYCLES */
#define ADC_SAMPLETIME_13CYCLES_5 ((uint32_t)ADC_SMPR_SMPR_1) /*!< ADC sampling time 13.5 CYCLES */
#define ADC_SAMPLETIME_28CYCLES_5 ((uint32_t)(ADC_SMPR_SMPR_1 | ADC_SMPR_SMPR_0)) /*!< ADC sampling time 28.5 CYCLES */
#define ADC_SAMPLETIME_41CYCLES_5 ((uint32_t)ADC_SMPR_SMPR_2) /*!< ADC sampling time 41.5 CYCLES */
#define ADC_SAMPLETIME_55CYCLES_5 ((uint32_t)(ADC_SMPR_SMPR_2 | ADC_SMPR_SMPR_0)) /*!< ADC sampling time 55.5 CYCLES */
#define ADC_SAMPLETIME_71CYCLES_5 ((uint32_t)(ADC_SMPR_SMPR_2 | ADC_SMPR_SMPR_1)) /*!< ADC sampling time 71.5 CYCLES */
#define ADC_SAMPLETIME_239CYCLES_5 ((uint32_t)ADC_SMPR_SMPR) /*!< ADC sampling time 239.5 CYCLES */
#define ADC_SAMPLETIME_3CYCLES_5 ((uint32_t)ADC_SMPR_SMPR_0) /*!< ADC sampling time 3.5 CYCLES */
#define ADC_SAMPLETIME_7CYCLES_5 ((uint32_t)ADC_SMPR_SMPR_1) /*!< ADC sampling time 7.5 CYCLES */
#define ADC_SAMPLETIME_12CYCLES_5 ((uint32_t)(ADC_SMPR_SMPR_1 | ADC_SMPR_SMPR_0)) /*!< ADC sampling time 12.5 CYCLES */
#define ADC_SAMPLETIME_19CYCLES_5 ((uint32_t)ADC_SMPR_SMPR_2) /*!< ADC sampling time 19.5 CYCLES */
#define ADC_SAMPLETIME_39CYCLES_5 ((uint32_t)(ADC_SMPR_SMPR_2 | ADC_SMPR_SMPR_0)) /*!< ADC sampling time 39.5 CYCLES */
#define ADC_SAMPLETIME_79CYCLES_5 ((uint32_t)(ADC_SMPR_SMPR_2 | ADC_SMPR_SMPR_1)) /*!< ADC sampling time 79.5 CYCLES */
#define ADC_SAMPLETIME_160CYCLES_5 ((uint32_t)ADC_SMPR_SMPR) /*!< ADC sampling time 160.5 CYCLES */
/**
* @}
*/
/** @defgroup ADC_Scan_mode ADC Scan mode
* @{
*/
@ -518,7 +566,7 @@ typedef struct
/** @defgroup ADC_Event_type ADC Event
* @{
*/
*/
#define ADC_AWD_EVENT ((uint32_t)ADC_FLAG_AWD)
#define ADC_OVR_EVENT ((uint32_t)ADC_FLAG_OVR)
/**
@ -537,14 +585,12 @@ typedef struct
#define ADC_IT_EOCAL ADC_IER_EOCALIE /*!< ADC End of Calibration interrupt source */
/**
* @}
*/
*/
/** @defgroup ADC_flags_definition ADC Flags Definition
/** @defgroup ADC_flags_definition ADC flags definition
* @{
*/
#define ADC_FLAG_RDY ADC_ISR_ADRDY /*!< ADC Ready (ADRDY) flag */
#define ADC_FLAG_RDY ADC_ISR_ADRDY /*!< ADC Ready flag */
#define ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC End of Sampling flag */
#define ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC End of Regular Conversion flag */
#define ADC_FLAG_EOS ADC_ISR_EOSEQ /*!< ADC End of Regular sequence of Conversions flag */
@ -562,9 +608,11 @@ typedef struct
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup ADC_Exported_Macro ADC Exported Macro
/** @defgroup ADC_Exported_Macros ADC Exported Macros
* @{
*/
/** @brief Reset ADC handle state
@ -648,7 +696,7 @@ typedef struct
#define ADC_IS_CONVERSION_ONGOING_REGULAR(__HANDLE__) \
(( (((__HANDLE__)->Instance->CR) & ADC_CR_ADSTART) == RESET \
) ? RESET : SET)
/**
* @brief Enable ADC continuous conversion mode.
* @param _CONTINUOUS_MODE_: Continuous mode.
@ -693,7 +741,7 @@ typedef struct
* @retval None
*/
#define __HAL_ADC_CFGR1_AUTOFF(_AUTOFF_) ((_AUTOFF_) << 15U)
/**
* @brief Configure the analog watchdog high threshold into registers TR1, TR2 or TR3.
* @param _Threshold_: Threshold value
@ -707,7 +755,7 @@ typedef struct
* @retval None
*/
#define __HAL_ADC_CCR_LOWFREQUENCY(_LOW_FREQUENCY_MODE_) ((_LOW_FREQUENCY_MODE_) << 25U)
/**
* @brief Shift the offset in function of the selected ADC resolution.
* Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0
@ -737,7 +785,7 @@ typedef struct
*/
#define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, _Threshold_) \
((_Threshold_) << ((((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_RES) >> 3U)*2U))
/**
* @brief Shift the value on the left, less significant are set to 0.
* @param _Value_: Value to be shifted
@ -813,8 +861,6 @@ typedef struct
((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
/**
* @brief Configuration of ADC clock & prescaler: clock source PCLK or Asynchronous with selectable prescaler
* @param __HANDLE__: ADC handle
@ -925,13 +971,13 @@ typedef struct
#endif
#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_1CYCLE_5 ) || \
((TIME) == ADC_SAMPLETIME_3CYCLES_5 ) || \
((TIME) == ADC_SAMPLETIME_7CYCLES_5 ) || \
((TIME) == ADC_SAMPLETIME_13CYCLES_5 ) || \
((TIME) == ADC_SAMPLETIME_28CYCLES_5 ) || \
((TIME) == ADC_SAMPLETIME_41CYCLES_5 ) || \
((TIME) == ADC_SAMPLETIME_55CYCLES_5 ) || \
((TIME) == ADC_SAMPLETIME_71CYCLES_5 ) || \
((TIME) == ADC_SAMPLETIME_239CYCLES_5))
((TIME) == ADC_SAMPLETIME_12CYCLES_5 ) || \
((TIME) == ADC_SAMPLETIME_19CYCLES_5 ) || \
((TIME) == ADC_SAMPLETIME_39CYCLES_5 ) || \
((TIME) == ADC_SAMPLETIME_79CYCLES_5 ) || \
((TIME) == ADC_SAMPLETIME_160CYCLES_5))
#define IS_ADC_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC_SCAN_DIRECTION_FORWARD) || \
((SCAN_MODE) == ADC_SCAN_DIRECTION_BACKWARD))
@ -971,7 +1017,7 @@ typedef struct
/** @defgroup ADC_range_verification ADC Range Verification
* in function of ADC resolution selected (12, 10, 8 or 6 bits)
* @{
*/
*/
#define IS_ADC_RANGE(RESOLUTION, ADC_VALUE) \
((((RESOLUTION) == ADC_RESOLUTION_12B) && ((ADC_VALUE) <= ((uint32_t)0x0FFFU))) || \
(((RESOLUTION) == ADC_RESOLUTION_10B) && ((ADC_VALUE) <= ((uint32_t)0x03FFU))) || \
@ -979,61 +1025,64 @@ typedef struct
(((RESOLUTION) == ADC_RESOLUTION_6B) && ((ADC_VALUE) <= ((uint32_t)0x003FU))))
/**
* @}
*/
*/
/** @defgroup ADC_regular_nb_conv_verification ADC Regular Nb Conversion Verification
* @{
*/
*/
#define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= ((uint32_t)1U)) && ((LENGTH) <= ((uint32_t)16U)))
/**
* @}
*/
/**
/**
* @}
*/
/* Include ADC HAL Extension module */
/* Include ADC HAL Extended module */
#include "stm32l0xx_hal_adc_ex.h"
/* Exported functions --------------------------------------------------------*/
/** @defgroup ADC_Exported_Functions ADC Exported Functions
/* Exported functions --------------------------------------------------------*/
/** @addtogroup ADC_Exported_Functions
* @{
*/
/* Initialization and de-initialization functions **********************************/
/** @defgroup ADC_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and de-initialization functions
* @{
*/
/** @addtogroup ADC_Exported_Functions_Group1
* @brief Initialization and Configuration functions
* @{
*/
/* Initialization and de-initialization functions ****************************/
HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc);
HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc);
void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc);
/**
* @}
*/
*/
/* IO operation functions *****************************************************/
/** @defgroup ADC_Exported_Functions_Group2 I/O operation functions
/** @addtogroup ADC_Exported_Functions_Group2
* @brief IO operation functions
* @{
*/
/* IO operation functions *****************************************************/
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc);
HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc);
HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout);
/* Non-blocking mode: Interruption */
HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc);
HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc);
/* Non-blocking mode: DMA */
HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length);
HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc);
/* ADC retrieve conversion value intended to be used with polling or interruption */
uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc);
/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */
void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc);
void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc);
@ -1042,46 +1091,37 @@ void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc);
void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
/**
* @}
*/
/* Peripheral Control functions ***********************************************/
/** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions
* @{
*/
/** @addtogroup ADC_Exported_Functions_Group3 Peripheral Control functions
* @brief Peripheral Control functions
* @{
*/
/* Peripheral Control functions ***********************************************/
HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig);
HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig);
/**
* @}
*/
*/
/* Peripheral State functions *************************************************/
/** @defgroup ADC_Exported_Functions_Group4 Peripheral State functions
/** @addtogroup ADC_Exported_Functions_Group4
* @{
*/
uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc);
uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
/**
* @}
*/
/**
* @}
*/
/* Define the private group ***********************************/
/**************************************************************/
/** @defgroup ADC_Private ADC Private
* @{
*/
/**
* @}
*/
/**************************************************************/
/**
* @}
*/
*/
/**
* @}
@ -1091,7 +1131,7 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
}
#endif
#endif /*__STM32L0xx_ADC_H */
#endif /*__STM32L0xx_HAL_ADC_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

119
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_adc_ex.c
View File

@ -2,34 +2,22 @@
******************************************************************************
* @file stm32l0xx_hal_adc_ex.c
* @author MCD Application Team
* @version V1.7.0
* @date 31-May-2016
* @brief This file provides firmware functions to manage the following
* functionalities of the Analog to Digital Convertor (ADC)
* peripheral:
* + Start calibration.
* + Read the calibration factor.
* + Set a calibration factor.
*
* + Operation functions
* ++ Calibration
* +++ ADC automatic self-calibration
* +++ Calibration factors get or set
* Other functions (generic functions) are available in file
* "stm32l0xx_hal_adc.c".
*
@verbatim
==============================================================================
##### ADC specific features #####
==============================================================================
[..]
(#) Self calibration.
##### How to use this driver #####
==============================================================================
[..]
(#) Call HAL_ADCEx_Calibration_Start() to start calibration
(#) Read the calibration factor using HAL_ADCEx_Calibration_GetValue()
(#) User can set a his calibration factor using HAL_ADCEx_Calibration_SetValue()
@endverbatim
(@) Sections "ADC peripheral features" and "How to use this driver" are
available in file of generic functions "stm32l0xx_hal_adc.c".
[..]
@endverbatim
******************************************************************************
* @attention
*
@ -57,7 +45,7 @@
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@ -67,18 +55,21 @@
* @{
*/
/** @defgroup ADCEx ADCEx
* @brief ADC Extended HAL module driver
* @{
*/
#ifdef HAL_ADC_MODULE_ENABLED
/** @addtogroup ADCEx
* @brief ADC driver modules
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Fixed timeout values for ADC calibration, enable settling time, disable */
/** @defgroup ADCEx_Private_Constants ADC Extended Private Constants
* @{
*/
/* Fixed timeout values for ADC calibration, enable settling time, disable */
/* settling time. */
/* Values defined to be higher than worst cases: low clock frequency, */
/* maximum prescaler. */
@ -98,38 +89,32 @@
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup ADCEx_Exported_Functions ADC Extended Exported Functions
* @{
*/
/** @addtogroup ADCEx_Exported_Functions
* @brief ADC Extended features functions
*
@verbatim
/** @defgroup ADCEx_Exported_Functions_Group1 Extended Input and Output operation functions
* @brief Extended IO operation functions
*
@verbatim
===============================================================================
##### ADC Extended features functions #####
===============================================================================
[..]
This subsection provides functions allowing to:
(+) Start calibration.
(+) Get calibration factor.
(+) Set calibration factor.
(+) Enable VREFInt.
(+) Disable VREFInt.
(+) Enable VREFInt TempSensor.
(+) Disable VREFInt TempSensor.
##### IO operation functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Perform the ADC calibration.
@endverbatim
* @{
*/
/** @addtogroup ADCEx_Exported_Functions_Group3
* @{
*/
/**
* @brief Start an automatic calibration
* @param hadc: pointer to a ADC_HandleTypeDef structure that contains
* the configuration information for the specified ADC.
* @brief Perform an ADC automatic self-calibration
* Calibration prerequisite: ADC must be disabled (execute this
* function before HAL_ADC_Start() or after HAL_ADC_Stop() ).
* @note Calibration factor can be read after calibration, using function
* HAL_ADC_GetValue() (value on 7 bits: from DR[6;0]).
* @param hadc ADC handle
* @param SingleDiff: Selection of single-ended or differential input
* This parameter can be only of the following values:
* @arg ADC_SINGLE_ENDED: Channel in mode input single ended
@ -138,7 +123,8 @@ This subsection provides functions allowing to:
HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc, uint32_t SingleDiff)
{
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
uint32_t tickstart=0U;
uint32_t tickstart = 0U;
uint32_t backup_setting_adc_dma_transfer = 0U; /* Note: Variable not declared as volatile because register read is already declared as volatile */
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
@ -154,11 +140,20 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc, uint32_t
HAL_ADC_STATE_REG_BUSY,
HAL_ADC_STATE_BUSY_INTERNAL);
/* Disable ADC DMA transfer request during calibration */
/* Note: Specificity of this STM32 serie: Calibration factor is */
/* available in data register and also transfered by DMA. */
/* To not insert ADC calibration factor among ADC conversion data */
/* in array variable, DMA transfer must be disabled during */
/* calibration. */
backup_setting_adc_dma_transfer = READ_BIT(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG);
CLEAR_BIT(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG);
/* Start ADC calibration */
hadc->Instance->CR |= ADC_CR_ADCAL;
tickstart = HAL_GetTick();
/* Wait for calibration completion */
while(HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADCAL))
{
@ -176,6 +171,9 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc, uint32_t
}
}
/* Restore ADC DMA transfer request after calibration */
SET_BIT(hadc->Instance->CFGR1, backup_setting_adc_dma_transfer);
/* Set ADC state */
ADC_STATE_CLR_SET(hadc->State,
HAL_ADC_STATE_BUSY_INTERNAL,
@ -196,7 +194,6 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc, uint32_t
return tmp_hal_status;
}
/**
* @brief Get the calibration factor.
* @param hadc: ADC handle.
@ -352,13 +349,13 @@ void HAL_ADCEx_DisableVREFINTTempSensor(void)
* @}
*/
#endif /* HAL_ADC_MODULE_ENABLED */
/**
* @}
*/
#endif /* HAL_ADC_MODULE_ENABLED */
/**
* @}
*/
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

35
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_adc_ex.h
View File

@ -2,10 +2,7 @@
******************************************************************************
* @file stm32l0xx_hal_adc_ex.h
* @author MCD Application Team
* @version V1.7.0
* @date 31-May-2016
* @brief This file contains all the functions prototypes for the ADC firmware
* library.
* @brief Header file of ADC HAL extended module.
******************************************************************************
* @attention
*
@ -37,8 +34,8 @@
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32L0xx_ADC_EX_H
#define __STM32L0xx_ADC_EX_H
#ifndef __STM32L0xx_HAL_ADC_EX_H
#define __STM32L0xx_HAL_ADC_EX_H
#ifdef __cplusplus
extern "C" {
@ -46,19 +43,19 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32l0xx_hal_def.h"
/** @addtogroup STM32L0xx_HAL_Driver
* @{
*/
/** @defgroup ADCEx ADCEx
* @brief ADC driver modules
/** @addtogroup ADCEx
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup ADCEx_Exported_Constants ADCEx Exported Constants
/** @defgroup ADCEx_Exported_Constants ADC Extended Exported Constants
* @{
*/
@ -70,7 +67,7 @@
* @}
*/
/** @defgroup ADC_External_trigger_Source ADC External Trigger Source
/** @defgroup ADC_regular_external_trigger_source ADC External Trigger Source
* @{
*/
#define ADC_EXTERNALTRIGCONV_T6_TRGO ((uint32_t)0x00000000U)
@ -185,18 +182,22 @@
* @}
*/
/** @defgroup ADCEx_Exported_Functions ADCEx Exported Functions
/* Exported functions --------------------------------------------------------*/
/** @addtogroup ADCEx_Exported_Functions
* @{
*/
/** @defgroup ADCEx_Exported_Functions_Group3 Peripheral Control functions
/** @addtogroup ADCEx_Exported_Functions_Group1
* @{
*/
/* Exported functions --------------------------------------------------------*/
/* Peripheral Control functions ***********************************************/
/* IO operation functions *****************************************************/
/* ADC calibration */
HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc, uint32_t SingleDiff);
uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef* hadc, uint32_t SingleDiff);
HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef* hadc, uint32_t SingleDiff, uint32_t CalibrationFactor);
/* ADC VrefInt and Temperature sensor functions specific to this STM32 serie */
HAL_StatusTypeDef HAL_ADCEx_EnableVREFINT(void);
void HAL_ADCEx_DisableVREFINT(void);
HAL_StatusTypeDef HAL_ADCEx_EnableVREFINTTempSensor(void);
@ -209,6 +210,7 @@ void HAL_ADCEx_DisableVREFINTTempSensor(void);
* @}
*/
/**
* @}
*/
@ -221,8 +223,7 @@ void HAL_ADCEx_DisableVREFINTTempSensor(void);
}
#endif
#endif /*__STM32L0xx_ADC_H */
#endif /*__STM32L0xx_HAL_ADC_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

86
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_comp.c
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32l0xx_hal_comp.c
* @author MCD Application Team
* @version V1.7.0
* @date 31-May-2016
* @brief COMP HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the COMP peripheral:
@ -320,45 +318,49 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp)
{
/* Note : COMP1 can be connected to the input 1 of LPTIM if requested */
assert_param(IS_COMP1_LPTIMCONNECTION(hcomp->Init.LPTIMConnection));
if (hcomp->Init.LPTIMConnection == COMP_LPTIMCONNECTION_IN1_ENABLED)
{
/* Note: Compatibility with previous driver version using */
/* generic literal COMP_LPTIMCONNECTION_ENABLED corresponding */
/* to LPTIM input 1 for COMP1. */
tmp_csr |= (COMP_CSR_COMP1LPTIM1IN1);
}
}
else
{
/* Check the MCU_ID in order to allow or not the COMP2 connection to LPTIM-input2 */
if (((HAL_GetDEVID() == C_DEV_ID_L073) && (HAL_GetREVID() == C_REV_ID_A))
||
((HAL_GetDEVID() == C_DEV_ID_L053) && (HAL_GetREVID() == C_REV_ID_A))
||
((HAL_GetDEVID() == C_DEV_ID_L053) && (HAL_GetREVID() == C_REV_ID_Z)))
/* Note : COMP2 can be connected to input 1 or input 2 of LPTIM if requested */
assert_param(IS_COMP2_LPTIMCONNECTION(hcomp->Init.LPTIMConnection));
switch (hcomp->Init.LPTIMConnection)
{
/* Note : COMP2 can be connected only to input 1 of LPTIM if requested */
assert_param(IS_COMP2_LPTIMCONNECTION_RESTRICTED(hcomp->Init.LPTIMConnection));
case COMP_LPTIMCONNECTION_IN1_ENABLED :
tmp_csr |= (COMP_CSR_COMP2LPTIM1IN1);
}
/* LPTIM connexion requested on COMP2 */
else
{
/* Note : COMP2 can be connected to input 1 or input2 of LPTIM if requested */
assert_param(IS_COMP2_LPTIMCONNECTION(hcomp->Init.LPTIMConnection));
switch (hcomp->Init.LPTIMConnection)
break;
case COMP_LPTIMCONNECTION_IN2_ENABLED :
default :
/* Note: Default case for compatibility with previous driver version*/
/* using generic literal COMP_LPTIMCONNECTION_ENABLED corresponding */
/* to LPTIM input 2 for COMP2. */
/* Check the MCU_ID in order to allow or not the COMP2 connection to LPTIM input 2 */
if (((HAL_GetDEVID() == C_DEV_ID_L073) && (HAL_GetREVID() == C_REV_ID_A))
||
((HAL_GetDEVID() == C_DEV_ID_L053) && (HAL_GetREVID() == C_REV_ID_A))
||
((HAL_GetDEVID() == C_DEV_ID_L053) && (HAL_GetREVID() == C_REV_ID_Z)))
{
case COMP_LPTIMCONNECTION_IN1_ENABLED :
tmp_csr |= (COMP_CSR_COMP2LPTIM1IN1);
break;
case COMP_LPTIMCONNECTION_IN2_ENABLED :
tmp_csr |= (COMP_CSR_COMP2LPTIM1IN2);
break;
default :
break;
assert_param(IS_COMP2_LPTIMCONNECTION_RESTRICTED(hcomp->Init.LPTIMConnection));
/* Error: On the selected device, COMP2 cannot be connected to LPTIM input 2 */
status = HAL_ERROR;
}
else
{
tmp_csr |= (COMP_CSR_COMP2LPTIM1IN2);
}
break;
}
}
}
/* Update comparator register */
if ((hcomp->Instance) == COMP1)
{
@ -442,8 +444,11 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp)
}
else
{
/* Disable EXTI event generation */
/* Disable EXTI event mode */
CLEAR_BIT(EXTI->EMR, exti_line);
/* Disable EXTI interrupt mode */
CLEAR_BIT(EXTI->IMR, exti_line);
}
/* Set HAL COMP handle state */
@ -641,8 +646,23 @@ void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp)
/* Check COMP EXTI flag */
if(READ_BIT(EXTI->PR, exti_line) != RESET)
{
/* Clear COMP EXTI pending bit */
WRITE_REG(EXTI->PR, exti_line);
/* Check whether comparator is in independent or window mode */
if(READ_BIT(COMP12_COMMON->CSR, COMP_CSR_WINMODE) != 0)
{
/* Clear COMP EXTI line pending bit of the pair of comparators */
/* in window mode. */
/* Note: Pair of comparators in window mode can both trig IRQ when */
/* input voltage is changing from "out of window" area */
/* (low or high ) to the other "out of window" area (high or low).*/
/* Both flags must be cleared to call comparator trigger */
/* callback is called once. */
WRITE_REG(EXTI->PR, (COMP_EXTI_LINE_COMP1 | COMP_EXTI_LINE_COMP2));
}
else
{
/* Clear COMP EXTI line pending bit */
WRITE_REG(EXTI->PR, exti_line);
}
/* COMP trigger user callback */
HAL_COMP_TriggerCallback(hcomp);

4
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_comp.h
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32l0xx_hal_comp.h
* @author MCD Application Team
* @version V1.7.0
* @date 31-May-2016
* @brief Header file of COMP HAL module.
******************************************************************************
* @attention
@ -586,7 +584,7 @@ typedef struct
((LPTIMCONNECTION) == COMP_LPTIMCONNECTION_IN2_ENABLED))
#define IS_COMP2_LPTIMCONNECTION_RESTRICTED(LPTIMCONNECTION) (((LPTIMCONNECTION) == COMP_LPTIMCONNECTION_DISABLED) || \
((LPTIMCONNECTION) == COMP_LPTIMCONNECTION_IN2_ENABLED))
((LPTIMCONNECTION) == COMP_LPTIMCONNECTION_IN1_ENABLED))
#define IS_COMP_OUTPUTPOL(POL) (((POL) == COMP_OUTPUTPOL_NONINVERTED) || \
((POL) == COMP_OUTPUTPOL_INVERTED))

32
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_comp_ex.c
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32l0xx_hal_comp_ex.c
* @author MCD Application Team
* @version V1.7.0
* @date 31-May-2016
* @brief Extended COMP HAL module driver.
* @brief This file provides firmware functions to manage voltage reference
* VrefInt that must be specifically controled for comparator
@ -65,6 +63,23 @@
* @{
*/
/* Private define ------------------------------------------------------------*/
/** @addtogroup COMP_Private_Constants
* @{
*/
/* Delay for COMP voltage scaler stabilization time (voltage from VrefInt, */
/* delay based on VrefInt startup time). */
/* Literal set to maximum value (refer to device datasheet, */
/* parameter "TVREFINT"). */
/* Unit: us */
#define COMP_DELAY_VOLTAGE_SCALER_STAB_US ((uint32_t)3000U) /*!< Delay for COMP voltage scaler stabilization time */
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup COMPEx_Exported_Functions
* @{
*/
@ -82,12 +97,25 @@
* using function "HAL_COMP_Init()".
* @note VrefInt requires a startup time
* (refer to device datasheet, parameter "TVREFINT").
* This function waits for the startup time
* (alternative solution: poll for bit SYSCFG_CFGR3_VREFINT_RDYF set).
* @retval None
*/
void HAL_COMPEx_EnableVREFINT(void)
{
__IO uint32_t wait_loop_index = 0U;
/* Enable the Buffer for the COMP by setting ENBUFLP_VREFINT_COMP bit in the CFGR3 register */
SYSCFG->CFGR3 |= (SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP);
/* Wait loop initialization and execution */
/* Note: Variable divided by 2 to compensate partially */
/* CPU processing cycles. */
wait_loop_index = (COMP_DELAY_VOLTAGE_SCALER_STAB_US * (SystemCoreClock / (1000000U * 2U)));
while(wait_loop_index != 0U)
{
wait_loop_index--;
}
}
/**

2
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_comp_ex.h
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32l0xx_hal_comp_ex.h
* @author MCD Application Team
* @version V1.7.0
* @date 31-May-2016
* @brief Header file of COMP HAL Extended module.
******************************************************************************
* @attention

8
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_conf.h
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32l0xx_hal_conf.h
* @author MCD Application Team
* @version V1.7.0
* @date 31-May-2016
* @brief HAL configuration file.
******************************************************************************
* @attention
@ -146,10 +144,12 @@
#define LSE_VALUE ((uint32_t)32768U) /*!< Value of the External oscillator in Hz*/
#endif /* LSE_VALUE */
/**
* @brief Time out for LSE start up value in ms.
*/
#if !defined (LSE_STARTUP_TIMEOUT)
#define LSE_STARTUP_TIMEOUT ((uint32_t)5000U) /*!< Time out for LSE start up, in ms */
#endif /* HSE_STARTUP_TIMEOUT */
#endif /* LSE_STARTUP_TIMEOUT */
/* Tip: To avoid modifying this file each time you need to use different HSE,

2
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_cortex.c
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32l0xx_hal_cortex.c
* @author MCD Application Team
* @version V1.7.0
* @date 31-May-2016
* @brief CORTEX HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the CORTEX:

2
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_cortex.h
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32l0xx_hal_cortex.h
* @author MCD Application Team
* @version V1.7.0
* @date 31-May-2016
* @brief Header file of CORTEX HAL module.
******************************************************************************
* @attention

7
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_crc.c
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32l0xx_hal_crc.c
* @author MCD Application Team
* @version V1.7.0
* @date 31-May-2016
* @brief CRC HAL module driver.
*
* This file provides firmware functions to manage the following
@ -228,13 +226,16 @@ HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc)
/* Reset CRC calculation unit */
__HAL_CRC_DR_RESET(hcrc);
/* Reset IDR register content */
CLEAR_BIT(hcrc->Instance->IDR, CRC_IDR_IDR) ;
/* DeInit the low level hardware */
HAL_CRC_MspDeInit(hcrc);
/* Change CRC peripheral state */
hcrc->State = HAL_CRC_STATE_RESET;
/* Process unlocked */
__HAL_UNLOCK(hcrc);

2
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_crc.h
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32l0xx_hal_crc.h
* @author MCD Application Team
* @version V1.7.0
* @date 31-May-2016
* @brief Header file of CRC HAL module.
******************************************************************************
* @attention

25
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_crc_ex.c
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32l0xx_hal_crc_ex.c
* @author MCD Application Team
* @version V1.7.0
* @date 31-May-2016
* @brief Extended CRC HAL module driver.
*
* This file provides firmware functions to manage the following
@ -120,24 +118,33 @@ HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol
* Look for MSB position: msb will contain the degree of
* the second to the largest polynomial member. E.g., for
* X^7 + X^6 + X^5 + X^2 + 1, msb = 6. */
while (((Pol & ((uint32_t)(0x1U) << msb)) == 0U) && (msb-- > 0U));
while (((Pol & (1U << msb)) == 0) && (msb-- > 0)){}
switch (PolyLength)
{
case CRC_POLYLENGTH_7B:
if (msb >= HAL_CRC_LENGTH_7B) return HAL_ERROR;
if (msb >= HAL_CRC_LENGTH_7B)
{
return HAL_ERROR;
}
break;
case CRC_POLYLENGTH_8B:
if (msb >= HAL_CRC_LENGTH_8B) return HAL_ERROR;
if (msb >= HAL_CRC_LENGTH_8B)
{
return HAL_ERROR;
}
break;
case CRC_POLYLENGTH_16B:
if (msb >= HAL_CRC_LENGTH_16B) return HAL_ERROR;
if (msb >= HAL_CRC_LENGTH_16B)
{
return HAL_ERROR;
}
break;
case CRC_POLYLENGTH_32B:
/* no polynomial definition vs. polynomial length issue possible */
break;
default:
break;
break;
default:
break;
}
/* set generating polynomial */

2
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_crc_ex.h
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32l0xx_hal_crc_ex.h
* @author MCD Application Team
* @version V1.7.0
* @date 31-May-2016
* @brief Header file of CRC HAL extension module.
******************************************************************************
* @attention

2
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_cryp.c
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32l0xx_hal_cryp.c
* @author MCD Application Team
* @version V1.7.0
* @date 31-May-2016
* @brief CRYP HAL module driver.
*
* This file provides firmware functions to manage the following

4
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_cryp.h
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32l0xx_hal_cryp.h
* @author MCD Application Team
* @version V1.7.0
* @date 31-May-2016
* @brief Header file of CRYP HAL module.
******************************************************************************
* @attention
@ -43,7 +41,7 @@
extern "C" {
#endif
#if defined (STM32L021xx) || (STM32L041xx) || defined (STM32L061xx) || defined (STM32L062xx) || defined (STM32L063xx) || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
#if defined (STM32L021xx) || defined (STM32L041xx) || defined (STM32L061xx) || defined (STM32L062xx) || defined (STM32L063xx) || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
/* Includes ------------------------------------------------------------------*/
#include "stm32l0xx_hal_def.h"

2
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_cryp_ex.c
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32l0xx_hal_cryp_ex.c
* @author MCD Application Team
* @version V1.7.0
* @date 31-May-2016
* @brief CRYPEx HAL module driver.
*
* This file provides firmware functions to manage the following

2
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_cryp_ex.h
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32l0xx_hal_cryp_ex.h
* @author MCD Application Team
* @version V1.7.0
* @date 31-May-2016
* @brief Header file of CRYPEx HAL module.
******************************************************************************
* @attention

2
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_dac.c
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32l0xx_hal_dac.c
* @author MCD Application Team
* @version V1.7.0
* @date 31-May-2016
* @brief DAC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Digital to Analog Converter (DAC) peripheral:

6
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_dac.h
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32l0xx_hal_dac.h
* @author MCD Application Team
* @version V1.7.0
* @date 31-May-2016
* @brief Header file of DAC HAL module.
******************************************************************************
* @attention
@ -280,7 +278,7 @@ CLEAR_BIT((__HANDLE__)->Instance->CR, (DAC_CR_EN1 << (__DAC_CHANNEL__)))
#define __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
SET_BIT((__HANDLE__)->Instance->CR, __INTERRUPT__)
SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
/** @brief Disable the DAC interrupt
@ -289,7 +287,7 @@ SET_BIT((__HANDLE__)->Instance->CR, __INTERRUPT__)
* @retval None
*/
#define __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \
CLEAR_BIT((__HANDLE__)->Instance->CR, __INTERRUPT__)
CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
/** @brief Check whether the specified DAC interrupt source is enabled or not.
* @param __HANDLE__: DAC handle

2
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_dac_ex.c
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32l0xx_hal_dac_ex.c
* @author MCD Application Team
* @version V1.7.0
* @date 31-May-2016
* @brief Extended DAC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of DAC extension peripheral:

2
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_dac_ex.h
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32l0xx_hal_dac_ex.h
* @author MCD Application Team
* @version V1.7.0
* @date 31-May-2016
* @brief Header file of DAC HAL Extension module.
******************************************************************************
* @attention

2
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_def.h
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32l0xx_hal_def.h
* @author MCD Application Team
* @version V1.7.0
* @date 31-May-2016
* @brief This file contains HAL common defines, enumeration, macros and
* structures definitions.
******************************************************************************

2
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_dma.c
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32l0xx_hal_dma.c
* @author MCD Application Team
* @version $VERSION$
* @date $DATE$
* @brief DMA HAL module driver.
*
* This file provides firmware functions to manage the following

2
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_dma.h
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32l0xx_hal_dma.h
* @author MCD Application Team
* @version $VERSION$
* @date $DATE$
* @brief Header file of DMA HAL module.
******************************************************************************
* @attention

2
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_firewall.c
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@ -2,8 +2,6 @@
******************************************************************************
* @file stm32l0xx_hal_firewall.c
* @author MCD Application Team
* @version V1.7.0
* @date 31-May-2016
* @brief FIREWALL HAL module driver.
* This file provides firmware functions to manage the Firewall
* Peripheral initialization and enabling.

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targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_firewall.h
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@ -2,8 +2,6 @@
******************************************************************************
* @file stm32l0xx_hal_firewall.h
* @author MCD Application Team
* @version V1.7.0
* @date 31-May-2016
* @brief Header file of FIREWALL HAL module.
******************************************************************************
* @attention

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targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_flash.c
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targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_flash.h
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@ -2,8 +2,6 @@
******************************************************************************
* @file stm32l0xx_hal_flash.h
* @author MCD Application Team
* @version V1.7.0
* @date 31-May-2016
* @brief Header file of Flash HAL module.
******************************************************************************
* @attention
@ -32,12 +30,12 @@
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32L0XX_HAL_FLASH_H
#define __STM32L0XX_HAL_FLASH_H
#ifndef __STM32L0xx_HAL_FLASH_H
#define __STM32L0xx_HAL_FLASH_H
#ifdef __cplusplus
extern "C" {
@ -45,15 +43,38 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32l0xx_hal_def.h"
/** @addtogroup STM32L0xx_HAL_Driver
* @{
*/
/** @defgroup FLASH FLASH
/** @addtogroup FLASH
* @{
*/
/** @addtogroup FLASH_Private_Constants
* @{
*/
#define FLASH_TIMEOUT_VALUE (50000U) /* 50 s */
#define FLASH_SIZE_DATA_REGISTER FLASHSIZE_BASE
/**
* @}
*/
/** @addtogroup FLASH_Private_Macros
* @{
*/
#define IS_FLASH_TYPEPROGRAM(_VALUE_) ((_VALUE_) == FLASH_TYPEPROGRAM_WORD)
#define IS_FLASH_LATENCY(__LATENCY__) (((__LATENCY__) == FLASH_LATENCY_0) || \
((__LATENCY__) == FLASH_LATENCY_1))
/**
* @}
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup FLASH_Exported_Types FLASH Exported Types
* @{
*/
@ -63,90 +84,82 @@
*/
typedef enum
{
FLASH_PROC_NONE = 0U,
FLASH_PROC_PAGEERASE,
FLASH_PROC_PROGRAM
FLASH_PROC_NONE = 0,
FLASH_PROC_PAGEERASE = 1,
FLASH_PROC_PROGRAM = 2,
} FLASH_ProcedureTypeDef;
/**
* @brief FLASH Erase structure definition
*/
typedef struct
{
uint32_t TypeErase; /*!< TypeErase: Page Erase only.
This parameter can be a value of @ref FLASHEx_Type_Erase */
uint32_t PageAddress ; /*!< PageAddress : Initial FLASH address to be erased
This parameter must be a value belonging to FLASH Programm address (depending on the devices) */
uint32_t NbPages; /*!< NbPages: Number of pages to be erased.
This parameter must be a value between 1 and (max number of pages - value of Initial page)*/
} FLASH_EraseInitTypeDef;
/**
* @brief FLASH handle Structure definition
*/
typedef struct
{
__IO FLASH_ProcedureTypeDef ProcedureOnGoing; /* Internal variable to indicate which procedure is ongoing or not in IT context */
__IO FLASH_ProcedureTypeDef ProcedureOnGoing; /*!< Internal variable to indicate which procedure is ongoing or not in IT context */
__IO uint32_t NbPagesToErase; /* Internal variable to save the remaining sectors to erase in IT context */
__IO uint32_t Page; /* Internal variable to define the current sector which is erasing */
__IO uint32_t Address; /* Internal variable to save address selected for program */
HAL_LockTypeDef Lock; /* FLASH locking object */
__IO uint32_t NbPagesToErase; /*!< Internal variable to save the remaining sectors to erase in IT context*/
__IO uint32_t ErrorCode; /* FLASH error code */
__IO uint32_t Address; /*!< Internal variable to save address selected for program or erase */
__IO uint32_t Page; /*!< Internal variable to define the current page which is erasing */
HAL_LockTypeDef Lock; /*!< FLASH locking object */
__IO uint32_t ErrorCode; /*!< FLASH error code
This parameter can be a value of @ref FLASH_Error_Codes */
} FLASH_ProcessTypeDef;
}FLASH_ProcessTypeDef;
/**
* @}
*/
*/
/** @addtogroup FLASH_Private
/* Exported constants --------------------------------------------------------*/
/** @defgroup FLASH_Exported_Constants FLASH Exported Constants
* @{
*/
/**
* @brief Variable used for Program/Erase sectors under interruption.
* Put as extern as used also in flash_ex.c.
/** @defgroup FLASH_Error_Codes FLASH Error Codes
* @{
*/
extern FLASH_ProcessTypeDef ProcFlash;
#define HAL_FLASH_ERROR_NONE 0x00U /*!< No error */
#define HAL_FLASH_ERROR_PGA 0x01U /*!< Programming alignment error */
#define HAL_FLASH_ERROR_WRP 0x02U /*!< Write protection error */
#define HAL_FLASH_ERROR_OPTV 0x04U /*!< Option validity error */
#define HAL_FLASH_ERROR_SIZE 0x08U /*!< */
#define HAL_FLASH_ERROR_RD 0x10U /*!< Read protected error */
#define HAL_FLASH_ERROR_FWWERR 0x20U /*!< FLASH Write or Erase operation aborted */
#define HAL_FLASH_ERROR_NOTZERO 0x40U /*!< FLASH Write operation is done in a not-erased region */
#define FLASH_TIMEOUT_VALUE ((uint32_t)50000U) /* 50 s */
#define FLASH_SIZE_DATA_REGISTER ((uint32_t)0x1FF8007CU)
/**
* @}
*/
/** @defgroup FLASH_Exported_Constants FLASH Public Constants
/** @defgroup FLASH_Page_Size FLASH size information
* @{
*/
#define FLASH_SIZE (uint32_t)((*((uint32_t *)FLASHSIZE_BASE)&0xFFFF) * 1024U)
#define FLASH_PAGE_SIZE ((uint32_t)128U) /*!< FLASH Page Size in bytes */
/**
* @}
*/
/**
* @brief FLASH size information
*/
#define FLASH_SIZE (uint32_t)(*((uint16_t *)FLASH_SIZE_DATA_REGISTER) * 1024U)
#define FLASH_PAGE_SIZE ((uint32_t)128U)
/** @defgroup FLASH_Type_Program FLASH Type Program
* @{
*/
#define FLASH_TYPEPROGRAM_WORD ((uint32_t)0x02U) /*!<Program a word (32-bit) at a specified address.*/
*/
#define FLASH_TYPEPROGRAM_WORD ((uint32_t)0x02U) /*!<Program a word (32-bit) at a specified address.*/
/**
* @}
*/
/** @defgroup FLASH_Latency FLASH Latency
/** @defgroup FLASH_Latency FLASH Latency
* @{
*/
#define FLASH_LATENCY_0 ((uint8_t)0x00U) /*!< FLASH Zero Latency cycle */
#define FLASH_LATENCY_1 ((uint8_t)0x01U) /*!< FLASH One Latency cycle */
#define FLASH_LATENCY_0 ((uint32_t)0x00000000U) /*!< FLASH Zero Latency cycle */
#define FLASH_LATENCY_1 FLASH_ACR_LATENCY /*!< FLASH One Latency cycle */
/**
* @}
*/
@ -154,6 +167,7 @@ extern FLASH_ProcessTypeDef ProcFlash;
/** @defgroup FLASH_Interrupts FLASH Interrupts
* @{
*/
#define FLASH_IT_EOP FLASH_PECR_EOPIE /*!< End of programming interrupt source */
#define FLASH_IT_ERR FLASH_PECR_ERRIE /*!< Error interrupt source */
/**
@ -163,55 +177,43 @@ extern FLASH_ProcessTypeDef ProcFlash;
/** @defgroup FLASH_Flags FLASH Flags
* @{
*/
#define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */
#define FLASH_FLAG_EOP FLASH_SR_EOP /*!< FLASH End of Programming flag */
#define FLASH_FLAG_ENDHV FLASH_SR_HVOFF /*!< FLASH End of High Voltage flag */
#define FLASH_FLAG_READY FLASH_SR_READY /*!< FLASH Ready flag after low power mode */
#define FLASH_FLAG_WRPERR FLASH_SR_WRPERR /*!< FLASH Write protected error flag */
#define FLASH_FLAG_PGAERR FLASH_SR_PGAERR /*!< FLASH Programming Alignment error flag */
#define FLASH_FLAG_SIZERR FLASH_SR_SIZERR /*!< FLASH Size error flag */
#define FLASH_FLAG_OPTVERR FLASH_SR_OPTVERR /*!< FLASH Option Validity error flag (not valid with STM32L031xx/STM32L041xx) */
#define FLASH_FLAG_RDERR FLASH_SR_RDERR /*!< FLASH Read protected error flag */
#define FLASH_FLAG_FWWERR FLASH_SR_FWWERR /*!< FLASH Write or Errase operation aborted */
#define FLASH_FLAG_NOTZEROERR FLASH_SR_NOTZEROERR /*!< FLASH Read protected error flag */
#define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */
#define FLASH_FLAG_EOP FLASH_SR_EOP /*!< FLASH End of Programming flag */
#define FLASH_FLAG_ENDHV FLASH_SR_HVOFF /*!< FLASH End of High Voltage flag */
#define FLASH_FLAG_READY FLASH_SR_READY /*!< FLASH Ready flag after low power mode */
#define FLASH_FLAG_WRPERR FLASH_SR_WRPERR /*!< FLASH Write protected error flag */
#define FLASH_FLAG_PGAERR FLASH_SR_PGAERR /*!< FLASH Programming Alignment error flag */
#define FLASH_FLAG_SIZERR FLASH_SR_SIZERR /*!< FLASH Size error flag */
#define FLASH_FLAG_OPTVERR FLASH_SR_OPTVERR /*!< FLASH Option Validity error flag */
#define FLASH_FLAG_RDERR FLASH_SR_RDERR /*!< FLASH Read protected error flag */
#define FLASH_FLAG_FWWERR FLASH_SR_FWWERR /*!< FLASH Write or Errase operation aborted */
#define FLASH_FLAG_NOTZEROERR FLASH_SR_NOTZEROERR /*!< FLASH Read protected error flag */
/**
* @}
*/
/** @defgroup FLASH_Error_Code Flash Error Code
* @{
*/
#define HAL_FLASH_ERROR_NONE 0x00U
#define HAL_FLASH_ERROR_RD 0x01U
#define HAL_FLASH_ERROR_SIZE 0x02U
#define HAL_FLASH_ERROR_PGA 0x04U
#define HAL_FLASH_ERROR_WRP 0x08U
#define HAL_FLASH_ERROR_OPTV 0x10U
#define HAL_FLASH_ERROR_FWWERR 0x20U
#define HAL_FLASH_ERROR_NOTZERO 0x40U
/**
* @}
*/
/** @defgroup FLASH_Keys FLASH Keys
* @{
*/
#define FLASH_PDKEY1 ((uint32_t)0x04152637U) /*!< Flash power down key1 */
#define FLASH_PDKEY2 ((uint32_t)0xFAFBFCFDU) /*!< Flash power down key2: used with FLASH_PDKEY1
to unlock the RUN_PD bit in FLASH_ACR */
to unlock the RUN_PD bit in FLASH_ACR */
#define FLASH_PEKEY1 ((uint32_t)0x89ABCDEFU) /*!< Flash program erase key1 */
#define FLASH_PEKEY2 ((uint32_t)0x02030405U) /*!< Flash program erase key: used with FLASH_PEKEY2
to unlock the write access to the FLASH_PECR register and
data EEPROM */
to unlock the write access to the FLASH_PECR register and
data EEPROM */
#define FLASH_PRGKEY1 ((uint32_t)0x8C9DAEBFU) /*!< Flash program memory key1 */
#define FLASH_PRGKEY2 ((uint32_t)0x13141516u) /*!< Flash program memory key2: used with FLASH_PRGKEY2
to unlock the program memory */
#define FLASH_PRGKEY2 ((uint32_t)0x13141516U) /*!< Flash program memory key2: used with FLASH_PRGKEY2
to unlock the program memory */
#define FLASH_OPTKEY1 ((uint32_t)0xFBEAD9C8U) /*!< Flash option key1 */
#define FLASH_OPTKEY2 ((uint32_t)0x24252627U) /*!< Flash option key2: used with FLASH_OPTKEY1 to
unlock the write access to the option byte block */
unlock the write access to the option byte block */
/**
* @}
*/
@ -224,71 +226,75 @@ extern FLASH_ProcessTypeDef ProcFlash;
/**
* @}
*/
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup FLASH_Exported_Macros FLASH Exported Macros
* @{
*/
* @brief macros to control FLASH features
* @{
*/
/** @defgroup FLASH_Macro_Interrupt Macros to handle FLASH interrupts
* @brief Enable and disable the specified FLASH interrupt.
* @{
*/
/** @defgroup FLASH_Interrupt FLASH Interrupts
* @brief macros to handle FLASH interrupts
* @{
*/
/**
* @brief Enable the specified FLASH interrupt.
* @param __INTERRUPT__ : FLASH interrupt
* This parameter can be any combination of the following values:
* @arg FLASH_IT_EOP: End of FLASH Operation Interrupt
* @arg FLASH_IT_ERR: Error Interrupt
* @param __INTERRUPT__ FLASH interrupt
* This parameter can be any combination of the following values:
* @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt
* @arg @ref FLASH_IT_ERR Error Interrupt
* @retval none
*/
#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) ((FLASH->PECR) |= (__INTERRUPT__))
*/
#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) SET_BIT((FLASH->PECR), (__INTERRUPT__))
/**
* @brief Disable the specified FLASH interrupt.
* @param __INTERRUPT__ : FLASH interrupt
* This parameter can be any combination of the following values:
* @arg FLASH_IT_EOP: End of FLASH Operation Interrupt
* @arg FLASH_IT_ERR: Error Interrupt
* @param __INTERRUPT__ FLASH interrupt
* This parameter can be any combination of the following values:
* @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt
* @arg @ref FLASH_IT_ERR Error Interrupt
* @retval none
*/
#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) ((FLASH->PECR) &= ~(uint32_t)(__INTERRUPT__))
*/
#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) CLEAR_BIT((FLASH->PECR), (uint32_t)(__INTERRUPT__))
/**
* @brief Get the specified FLASH flag status.
* @param __FLAG__: specifies the FLASH flag to check.
* This parameter can be one of the following values:
* @arg FLASH_FLAG_BSY : FLASH Busy flag
* @arg FLASH_FLAG_EOP: FLASH End of Operation flag
* @arg FLASH_FLAG_READY: FLASH Ready flag after low power mode
* @arg FLASH_FLAG_ENDHV: FLASH End of high voltage flag
* @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag
* @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag (not valid with STM32L031xx/STM32L041xx)
* @arg FLASH_FLAG_SIZERR: FLASH Size error flag
* @arg FLASH_FLAG_OPTVERR: FLASH Option validity error flag (not valid with STM32L031xx/STM32L041xx)
* @arg FLASH_FLAG_RDERR: FLASH Read protected error flag
* @arg FLASH_FLAG_FWWERR: FLASH Fetch While Write Error flag
* @arg FLASH_FLAG_NOTZEROERR: Not Zero area error flag
* @param __FLAG__ specifies the FLASH flag to check.
* This parameter can be one of the following values:
* @arg @ref FLASH_FLAG_BSY FLASH Busy flag
* @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag
* @arg @ref FLASH_FLAG_ENDHV FLASH End of High Voltage flag
* @arg @ref FLASH_FLAG_READY FLASH Ready flag after low power mode
* @arg @ref FLASH_FLAG_PGAERR FLASH Programming Alignment error flag
* @arg @ref FLASH_FLAG_SIZERR FLASH Size error flag
* @arg @ref FLASH_FLAG_OPTVERR FLASH Option validity error flag (not valid with STM32L031xx/STM32L041xx)
* @arg @ref FLASH_FLAG_RDERR FLASH Read protected error flag
* @arg @ref FLASH_FLAG_WRPERR FLASH Write protected error flag
* @arg @ref FLASH_FLAG_FWWERR FLASH Fetch While Write Error flag
* @arg @ref FLASH_FLAG_NOTZEROERR Not Zero area error flag
* @retval The new state of __FLAG__ (SET or RESET).
*/
#define __HAL_FLASH_GET_FLAG(__FLAG__) (((FLASH->SR) & (__FLAG__)) == (__FLAG__))
/**
* @brief Clear the specified FLASH flag.
* @param __FLAG__: specifies the FLASH flags to clear.
* This parameter can be any combination of the following values:
* @arg FLASH_FLAG_EOP: FLASH End of Operation flag
* @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag
* @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag (not valid with STM32L031xx/STM32L041xx)
* @arg FLASH_FLAG_SIZERR: FLASH size error flag
* @arg FLASH_FLAG_OPTVERR: FLASH Option validity error flag (not valid with STM32L031xx/STM32L041xx)
* @arg FLASH_FLAG_RDERR: FLASH Read protected error flag
* @arg FLASH_FLAG_FWWERR: FLASH Fetch While Write Error flag
* @arg FLASH_FLAG_NOTZEROERR: Not Zero area error flag
* @retval None
* @param __FLAG__ specifies the FLASH flags to clear.
* This parameter can be any combination of the following values:
* @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag
* @arg @ref FLASH_FLAG_PGAERR FLASH Programming Alignment error flag
* @arg @ref FLASH_FLAG_SIZERR FLASH Size error flag
* @arg @ref FLASH_FLAG_OPTVERR FLASH Option validity error flag (not valid with STM32L031xx/STM32L041xx)
* @arg @ref FLASH_FLAG_RDERR FLASH Read protected error flag
* @arg @ref FLASH_FLAG_WRPERR FLASH Write protected error flag
* @arg @ref FLASH_FLAG_FWWERR FLASH Fetch While Write Error flag
* @arg @ref FLASH_FLAG_NOTZEROERR Not Zero area error flag
* @retval none
*/
#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) (FLASH->SR = (__FLAG__))
#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) ((FLASH->SR) = (__FLAG__))
/**
* @}
@ -298,101 +304,73 @@ extern FLASH_ProcessTypeDef ProcFlash;
* @}
*/
/* Include FLASH HAL Extension module */
#include "stm32l0xx_hal_flash_ex.h"
#include "stm32l0xx_hal_flash_ramfunc.h"
/* Include FLASH HAL Extended module */
#include "stm32l0xx_hal_flash_ex.h"
#include "stm32l0xx_hal_flash_ramfunc.h"
/* Exported functions ------------------------------------------------------- */
/** @defgroup FLASH_Exported_Functions FLASH Exported functions
/* Exported functions --------------------------------------------------------*/
/** @addtogroup FLASH_Exported_Functions
* @{
*/
/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions
/** @addtogroup FLASH_Exported_Functions_Group1
* @{
*/
/**
* @brief FLASH memory functions that can be executed from FLASH.
*/
/* Program operation functions ***********************************************/
/* IO operation functions *****************************************************/
HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint32_t Data);
HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint32_t Data);
/* FLASH IRQ handler function ***********************************************/
void HAL_FLASH_IRQHandler(void);
/* FLASH IRQ handler function */
void HAL_FLASH_IRQHandler(void);
/* Callbacks in non blocking modes */
void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue);
void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue);
/* Callbacks in non blocking modes ******************************************/
void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue);
void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue);
/**
* @}
*/
/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions
* @{
*/
/* FLASH Memory Programming functions *****************************************/
/** @addtogroup FLASH_Exported_Functions_Group2
* @{
*/
/* Peripheral Control functions ***********************************************/
HAL_StatusTypeDef HAL_FLASH_Unlock(void);
HAL_StatusTypeDef HAL_FLASH_Lock(void);
/* Option Bytes Programming functions *****************************************/
HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void);
HAL_StatusTypeDef HAL_FLASH_OB_Lock(void);
HAL_StatusTypeDef HAL_FLASH_OB_Launch(void);
/**
* @}
*/
*/
/** @defgroup FLASH_Exported_Functions_Group3 Peripheral State and Errors functions
/** @addtogroup FLASH_Exported_Functions_Group3
* @{
*/
/* Peripheral State methods **************************************************/
/* Peripheral State and Error functions ***************************************/
uint32_t HAL_FLASH_GetError(void);
/**
* @}
*/
/**
* @}
*/
/** @addtogroup FLASH_Private
* @{
*/
#define IS_FLASH_TYPEPROGRAM(VALUE) ((VALUE) == FLASH_TYPEPROGRAM_WORD)
#define IS_FLASH_LATENCY(__LATENCY__) (((__LATENCY__) == FLASH_LATENCY_0) || \
((__LATENCY__) == FLASH_LATENCY_1))
/**
* @brief Function used internally by HAL FLASH driver.
*/
HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
void FLASH_ErasePage(uint32_t Page_Address);
/**
* @}
*/
/* Define the private group ***********************************/
/**************************************************************/
/** @defgroup FLASH_Private FLASH Private
* @{
*/
/**
* @}
*/
/**************************************************************/
/* Private function -------------------------------------------------*/
/** @addtogroup FLASH_Private_Functions
* @{
*/
HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
/**
* @}
*/
*/
/**
* @}
*/
/**
* @}
@ -402,7 +380,7 @@ void FLASH_ErasePage(uint32_t Page_Address);
}
#endif
#endif /* __STM32L0XX_HAL_FLASH_H */
#endif /* __STM32L0xx_HAL_FLASH_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_flash_ex.c
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targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_flash_ex.h
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@ -2,9 +2,7 @@
******************************************************************************
* @file stm32l0xx_hal_flash_ex.h
* @author MCD Application Team
* @version V1.7.0
* @date 31-May-2016
* @brief Header file of FLash HAL Extension module.
* @brief Header file of Flash HAL Extended module.
******************************************************************************
* @attention
*
@ -50,113 +48,238 @@
* @{
*/
/** @defgroup FLASHEx FLASHEx
/** @addtogroup FLASHEx
* @{
*/
/** @addtogroup FLASHEx_Private_Constants
* @{
*/
#define FLASH_SIZE_DATA_REGISTER FLASHSIZE_BASE
#define FLASH_NBPAGES_MAX (FLASH_SIZE / FLASH_PAGE_SIZE)
#define WRP_MASK_LOW (0x0000FFFFU)
#define WRP_MASK_HIGH (0xFFFF0000U)
/**
* @}
*/
/** @addtogroup FLASHEx_Private_Macros
* @{
*/
#define IS_FLASH_TYPEERASE(__VALUE__) (((__VALUE__) == FLASH_TYPEERASE_PAGES))
#define IS_OPTIONBYTE(__VALUE__) (((__VALUE__) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | \
OPTIONBYTE_USER | OPTIONBYTE_BOR | OPTIONBYTE_BOOT_BIT1)))
#define IS_WRPSTATE(__VALUE__) (((__VALUE__) == OB_WRPSTATE_DISABLE) || \
((__VALUE__) == OB_WRPSTATE_ENABLE))
#define IS_OB_WRP(__PAGE__) (((__PAGE__) != 0x0000000U))
#define IS_OB_RDP(__LEVEL__) (((__LEVEL__) == OB_RDP_LEVEL_0) ||\
((__LEVEL__) == OB_RDP_LEVEL_1) ||\
((__LEVEL__) == OB_RDP_LEVEL_2))
#define IS_OB_BOR_LEVEL(__LEVEL__) (((__LEVEL__) == OB_BOR_OFF) || \
((__LEVEL__) == OB_BOR_LEVEL1) || \
((__LEVEL__) == OB_BOR_LEVEL2) || \
((__LEVEL__) == OB_BOR_LEVEL3) || \
((__LEVEL__) == OB_BOR_LEVEL4) || \
((__LEVEL__) == OB_BOR_LEVEL5))
#define IS_OB_IWDG_SOURCE(__SOURCE__) (((__SOURCE__) == OB_IWDG_SW) || ((__SOURCE__) == OB_IWDG_HW))
#define IS_OB_STOP_SOURCE(__SOURCE__) (((__SOURCE__) == OB_STOP_NORST) || ((__SOURCE__) == OB_STOP_RST))
#define IS_OB_STDBY_SOURCE(__SOURCE__) (((__SOURCE__) == OB_STDBY_NORST) || ((__SOURCE__) == OB_STDBY_RST))
#if defined(FLASH_OPTR_WPRMOD) && defined(FLASH_OPTR_BFB2)
#define IS_OBEX(__VALUE__) (((__VALUE__) == OPTIONBYTE_PCROP) || ((__VALUE__) == OPTIONBYTE_BOOTCONFIG))
#elif defined(FLASH_OPTR_WPRMOD) && !defined(FLASH_OPTR_BFB2)
#define IS_OBEX(__VALUE__) ((__VALUE__) == OPTIONBYTE_PCROP)
#elif !defined(FLASH_OPTR_WPRMOD) && defined(FLASH_OPTR_BFB2)
#define IS_OBEX(__VALUE__) ((__VALUE__) == OPTIONBYTE_BOOTCONFIG)
#endif /* FLASH_OPTR_WPRMOD && FLASH_OPTR_BFB2 */
#if defined(FLASH_OPTR_WPRMOD)
#define IS_PCROPSTATE(__VALUE__) (((__VALUE__) == OB_PCROP_STATE_DISABLE) || \
((__VALUE__) == OB_PCROP_STATE_ENABLE))
#define IS_OB_PCROP(__PAGE__) (((__PAGE__) != 0x0000000U))
#endif /* FLASH_OPTR_WPRMOD */
#if defined(FLASH_OPTR_BFB2)
#define IS_OB_BOOT_BANK(__BANK__) (((__BANK__) == OB_BOOT_BANK2) || ((__BANK__) == OB_BOOT_BANK1))
#endif /* FLASH_OPTR_BFB2 */
#define IS_OB_BOOT1(__BOOT_BIT1__) (((__BOOT_BIT1__) == OB_BOOT_BIT1_RESET) || ((__BOOT_BIT1__) == OB_BOOT_BIT1_SET))
#define IS_TYPEPROGRAMDATA(__VALUE__) (((__VALUE__) == FLASH_TYPEPROGRAMDATA_BYTE) || \
((__VALUE__) == FLASH_TYPEPROGRAMDATA_HALFWORD) || \
((__VALUE__) == FLASH_TYPEPROGRAMDATA_WORD))
/** @defgroup FLASHEx_Address FLASHEx Address
* @{
*/
#if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
#define IS_FLASH_DATA_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= DATA_EEPROM_BASE) && ((__ADDRESS__) <= DATA_EEPROM_BANK2_END))
#define IS_FLASH_DATA_BANK1_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= DATA_EEPROM_BASE) && ((__ADDRESS__) <= DATA_EEPROM_BANK1_END))
#define IS_FLASH_DATA_BANK2_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= DATA_EEPROM_BANK2_BASE) && ((__ADDRESS__) <= DATA_EEPROM_BANK2_END))
#define IS_FLASH_PROGRAM_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= FLASH_BASE) && ((__ADDRESS__) < (FLASH_BASE + FLASH_SIZE)))
#define IS_FLASH_PROGRAM_BANK1_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= FLASH_BASE) && ((__ADDRESS__) < (FLASH_BASE + (FLASH_SIZE >> 1))))
#define IS_FLASH_PROGRAM_BANK2_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= FLASH_BANK2_BASE) && ((__ADDRESS__) < (FLASH_BASE + FLASH_SIZE)))
#else
#define IS_FLASH_DATA_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= DATA_EEPROM_BASE) && ((__ADDRESS__) <= DATA_EEPROM_END))
#define IS_FLASH_PROGRAM_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= FLASH_BASE) && ((__ADDRESS__) < (FLASH_BASE + FLASH_SIZE)))
#endif
#define IS_NBPAGES(__PAGES__) (((__PAGES__) >= 1) && ((__PAGES__) <= FLASH_NBPAGES_MAX))
/**
* @}
*/
/**
* @}
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup FLASHEx_Exported_Types FLASHEx Exported Types
* @{
*/
/**
* @brief FLASH Erase structure definition
*/
typedef struct
{
uint32_t TypeErase; /*!< TypeErase: Page Erase only.
This parameter can be a value of @ref FLASHEx_Type_Erase */
uint32_t PageAddress; /*!< PageAddress: Initial FLASH address to be erased
This parameter must be a value belonging to FLASH Programm address (depending on the devices) */
uint32_t NbPages; /*!< NbPages: Number of pages to be erased.
This parameter must be a value between 1 and (max number of pages - value of Initial page)*/
} FLASH_EraseInitTypeDef;
/**
* @brief FLASH Option Bytes PROGRAM structure definition
*/
typedef struct
{
uint32_t OptionType; /*!< OptionType: Option byte to be configured.
This parameter can be a value of @ref FLASHEx_Option_Type */
uint32_t OptionType; /*!< OptionType: Option byte to be configured.
This parameter can be a value of @ref FLASHEx_Option_Type */
uint32_t WRPState; /*!< WRPState: Write protection activation or deactivation.
This parameter can be a value of @ref FLASHEx_WRP_State */
uint32_t WRPState; /*!< WRPState: Write protection activation or deactivation.
This parameter can be a value of @ref FLASHEx_WRP_State */
uint32_t WRPSector; /*!< WRPSector: This bitfield specifies the sector (s) which are write protected.
This parameter can be a combination of @ref FLASHEx_Option_Bytes_Write_Protection */
uint32_t WRPSector; /*!< WRPSector: This bitfield specifies the sector (s) which are write protected.
This parameter can be a combination of @ref FLASHEx_Option_Bytes_Write_Protection */
#if defined(STM32L071xx) || defined(STM32L072xx) || defined(STM32L073xx) || defined(STM32L081xx) || defined(STM32L082xx) || defined(STM32L083xx)
uint32_t WRPSector2; /*!< WRPSector2 : This bitfield specifies the sector(s) upper Sector31 which are write protected.
This parameter can be a combination of @ref FLASHEx_Option_Bytes_Write_Protection2 */
uint32_t WRPSector2; /*!< WRPSector2 : This bitfield specifies the sector(s) upper Sector31 which are write protected.
This parameter can be a combination of @ref FLASHEx_Option_Bytes_Write_Protection2 */
#endif
uint8_t RDPLevel; /*!< RDPLevel: Set the read protection level.
This parameter can be a value of @ref FLASHEx_Option_Bytes_Read_Protection */
uint8_t RDPLevel; /*!< RDPLevel: Set the read protection level.
This parameter can be a value of @ref FLASHEx_Option_Bytes_Read_Protection */
uint8_t BORLevel; /*!< BORLevel: Set the BOR Level.
This parameter can be a value of @ref FLASHEx_Option_Bytes_BOR_Level */
uint8_t BORLevel; /*!< BORLevel: Set the BOR Level.
This parameter can be a value of @ref FLASHEx_Option_Bytes_BOR_Level */
uint8_t USERConfig; /*!< USERConfig: Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.
This parameter can be a combination of @ref FLASHEx_Option_Bytes_IWatchdog,
@ref FLASHEx_Option_Bytes_nRST_STOP and @ref FLASHEx_Option_Bytes_nRST_STDBY*/
uint8_t USERConfig; /*!< USERConfig: Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.
This parameter can be a combination of @ref FLASHEx_Option_Bytes_IWatchdog,
@ref FLASHEx_Option_Bytes_nRST_STOP and @ref FLASHEx_Option_Bytes_nRST_STDBY */
uint8_t BOOTBit1Config; /*!< BOOT1Config: Together with input pad Boot0, this bit selects the boot source, flash, ram or system memory
This parameter can be a value of @ref FLASHEx_Option_Bytes_BOOTBit1 */
uint8_t BOOTBit1Config; /*!< BOOT1Config: Together with input pad Boot0, this bit selects the boot source, flash, ram or system memory
This parameter can be a value of @ref FLASHEx_Option_Bytes_BOOTBit1 */
} FLASH_OBProgramInitTypeDef;
#if defined(FLASH_OPTR_WPRMOD) || defined(FLASH_OPTR_BFB2)
/**
* @brief FLASH Advanced Option Bytes Program structure definition
*/
typedef struct
{
uint32_t OptionType; /*!< OptionType: Option byte to be configured for extension .
This parameter can be a value of @ref FLASHEx_OptionAdv_Type */
uint8_t PCROPState; /*!< PCROPState: PCROP activation or deactivation.
This parameter can be a value of @ref FLASHEx_PCROP_State */
uint32_t OptionType; /*!< OptionType: Option byte to be configured for extension .
This parameter can be a value of @ref FLASHEx_OptionAdv_Type */
#if defined(FLASH_OPTR_WPRMOD)
uint32_t PCROPState; /*!< PCROPState: PCROP activation or deactivation.
This parameter can be a value of @ref FLASHEx_PCROP_State */
uint32_t PCROPSector; /*!< PCROPSector : This bitfield specifies the sector(s) which are read/write protected.
This parameter can be a combination of @ref FLASHEx_Option_Bytes_PC_ReadWrite_Protection */
#if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
uint32_t PCROPSector2; /*!< PCROPSector : This bitfield specifies the sector(s) upper Sector31 which are read/write protected.
This parameter can be a combination of @ref FLASHEx_Option_Bytes_PC_ReadWrite_Protection2 */
uint8_t BootConfig; /*!< BootConfig: specifies Option bytes for boot config.
This parameter can be a value of @ref FLASHEx_Option_Bytes_BOOT_BANK */
#endif /* if STM32L071xx || STM32L072xx || STM32L073xx || STM32L081xx || STM32L082xx || STM32L083xx */
#endif /* STM32L071xx || STM32L072xx || STM32L073xx || STM32L081xx || STM32L082xx || STM32L083xx */
#endif /* FLASH_OPTR_WPRMOD */
#if defined(FLASH_OPTR_BFB2)
uint16_t BootConfig; /*!< BootConfig: specifies Option bytes for boot config
This parameter can be a value of @ref FLASHEx_Option_Bytes_BOOT */
#endif /* FLASH_OPTR_BFB2*/
} FLASH_AdvOBProgramInitTypeDef;
/**
* @}
*/
*/
#endif /* FLASH_OPTR_WPRMOD || FLASH_OPTR_BFB2 */
/* Exported constants --------------------------------------------------------*/
/** @defgroup FLASHEx_Exported_Constants FLASHEx Exported Constants
* @{
*/
/** @defgroup FLASHEx_Type_Erase FLASH Type Erase
/** @defgroup FLASHEx_Type_Erase FLASHEx_Type_Erase
* @{
*/
#define FLASH_TYPEERASE_PAGES ((uint32_t)0x00U) /*!< Page erase only */
*/
#define FLASH_TYPEERASE_PAGES ((uint32_t)0x00U) /*!<Page erase only*/
/**
* @}
*/
/** @defgroup FLASHEx_Option_Type FLASH Option Type
/** @defgroup FLASHEx_Option_Type FLASHEx Option Type
* @{
*/
#define OPTIONBYTE_WRP ((uint32_t)0x01U) /*!< WRP option byte configuration */
#define OPTIONBYTE_RDP ((uint32_t)0x02U) /*!< RDP option byte configuration */
#define OPTIONBYTE_USER ((uint32_t)0x04U) /*!< USER option byte configuration */
#define OPTIONBYTE_BOR ((uint32_t)0x08U) /*!< BOR option byte configuration */
#define OPTIONBYTE_BOOT_BIT1 ((uint32_t)0x10U) /*!< BOOT PIN1 option byte configuration*/
#define OPTIONBYTE_WRP ((uint32_t)0x01U) /*!<WRP option byte configuration*/
#define OPTIONBYTE_RDP ((uint32_t)0x02U) /*!<RDP option byte configuration*/
#define OPTIONBYTE_USER ((uint32_t)0x04U) /*!<USER option byte configuration*/
#define OPTIONBYTE_BOR ((uint32_t)0x08U) /*!<BOR option byte configuration*/
#define OPTIONBYTE_BOOT_BIT1 ((uint32_t)0x10U) /*!< BOOT PIN1 option byte configuration*/
/**
* @}
*/
/** @defgroup FLASHEx_WRP_State FLASH WRP State
/** @defgroup FLASHEx_WRP_State FLASHEx WRP State
* @{
*/
#define OB_WRPSTATE_DISABLE ((uint32_t)0x00U) /*!< Disable the write protection of the desired sectors */
#define OB_WRPSTATE_ENABLE ((uint32_t)0x01U) /*!< Enable the write protection of the desired sectors */
/**
* @}
*/
#define OB_WRPSTATE_DISABLE ((uint32_t)0x00U) /*!<Disable the write protection of the desired sectors*/
#define OB_WRPSTATE_ENABLE ((uint32_t)0x01U) /*!<Enable the write protection of the desired sectors*/
/** @defgroup FLASHEx_Option_Bytes_ReadWrite_Mask FLASH Option Bytes Write Mask
* @{
*/
#define WRP_MASK_LOW ((uint32_t)0x0000FFFFU)
#define WRP_MASK_HIGH ((uint32_t)0xFFFF0000U)
/**
* @}
*/
@ -266,38 +389,43 @@ typedef struct
/**
* @}
*/
#endif /* STM32L071xx || STM32L072xx || (STM32L073xx) || (STM32L081xx) || (STM32L082xx) || (STM32L083xx) */
#endif /* STM32L071xx || STM32L072xx || (STM32L073xx) || (STM32L081xx) || (STM32L082xx) || (STM32L083xx) */
/** @defgroup FLASHEx_Option_Bytes_Read_Protection FLASH Option Bytes Read Protection
/** @defgroup FLASHEx_Option_Bytes_Read_Protection FLASHEx Option Bytes Read Protection
* @{
*/
#define OB_RDP_LEVEL_0 ((uint8_t)0xAAU)
#define OB_RDP_LEVEL_1 ((uint8_t)0xBBU)
#define OB_RDP_LEVEL_2 ((uint8_t)0xCCU) /* Warning: When enabling read protection level 2
it is no more possible to go back to level 1 or 0 */
/**
* @}
*/
/** @defgroup FLASHEx_Option_Bytes_BOR_Level FLASH Option Bytes BOR Level
/** @defgroup FLASHEx_Option_Bytes_BOR_Level FLASHEx Option Bytes BOR Level
* @{
*/
#define OB_BOR_OFF ((uint8_t)0x00U) /*!< BOR is disabled at power down, the reset is asserted when the VDD
#define OB_BOR_OFF ((uint8_t)0x00U) /*!< BOR is disabled at power down, the reset is asserted when the VDD
power supply reaches the PDR(Power Down Reset) threshold (1.5V) */
#define OB_BOR_LEVEL1 ((uint8_t)0x08U) /*!< BOR Reset threshold levels for 1.7V - 1.8V VDD power supply */
#define OB_BOR_LEVEL2 ((uint8_t)0x09U) /*!< BOR Reset threshold levels for 1.9V - 2.0V VDD power supply */
#define OB_BOR_LEVEL3 ((uint8_t)0x0AU) /*!< BOR Reset threshold levels for 2.3V - 2.4V VDD power supply */
#define OB_BOR_LEVEL4 ((uint8_t)0x0BU) /*!< BOR Reset threshold levels for 2.55V - 2.65V VDD power supply */
#define OB_BOR_LEVEL5 ((uint8_t)0x0CU) /*!< BOR Reset threshold levels for 2.8V - 2.9V VDD power supply */
#define OB_BOR_LEVEL1 ((uint8_t)0x08U) /*!< BOR Reset threshold levels for 1.7V - 1.8V VDD power supply */
#define OB_BOR_LEVEL2 ((uint8_t)0x09U) /*!< BOR Reset threshold levels for 1.9V - 2.0V VDD power supply */
#define OB_BOR_LEVEL3 ((uint8_t)0x0AU) /*!< BOR Reset threshold levels for 2.3V - 2.4V VDD power supply */
#define OB_BOR_LEVEL4 ((uint8_t)0x0BU) /*!< BOR Reset threshold levels for 2.55V - 2.65V VDD power supply */
#define OB_BOR_LEVEL5 ((uint8_t)0x0CU) /*!< BOR Reset threshold levels for 2.8V - 2.9V VDD power supply */
/**
* @}
*/
/** @defgroup FLASHEx_Option_Bytes_IWatchdog FLASH Option Bytes IWatchdog
/** @defgroup FLASHEx_Option_Bytes_IWatchdog FLASHEx Option Bytes IWatchdog
* @{
*/
#define OB_IWDG_SW ((uint8_t)0x10U) /*!< Software WDG selected */
#define OB_IWDG_HW ((uint8_t)0x00U) /*!< Hardware WDG selected */
#define OB_IWDG_SW ((uint8_t)0x10U) /*!< Software WDG selected */
#define OB_IWDG_HW ((uint8_t)0x00U) /*!< Hardware WDG selected */
/**
* @}
*/
@ -305,45 +433,75 @@ typedef struct
/** @defgroup FLASHEx_Option_Bytes_nRST_STOP FLASHEx Option Bytes nRST_STOP
* @{
*/
#define OB_STOP_NORST ((uint8_t)0x20U) /*!< No reset generated when entering in STOP */
#define OB_STOP_RST ((uint8_t)0x00U) /*!< Reset generated when entering in STOP */
#define OB_STOP_NORST ((uint8_t)0x20U) /*!< No reset generated when entering in STOP */
#define OB_STOP_RST ((uint8_t)0x00U) /*!< Reset generated when entering in STOP */
/**
* @}
*/
/** @defgroup FLASHEx_Option_Bytes_nRST_STDBY FLASH Option Bytes nRST_STDBY
/** @defgroup FLASHEx_Option_Bytes_nRST_STDBY FLASHEx Option Bytes nRST_STDBY
* @{
*/
#define OB_STDBY_NORST ((uint8_t)0x40U) /*!< No reset generated when entering in STANDBY */
#define OB_STDBY_RST ((uint8_t)0x00U) /*!< Reset generated when entering in STANDBY */
#define OB_STDBY_NORST ((uint8_t)0x40U) /*!< No reset generated when entering in STANDBY */
#define OB_STDBY_RST ((uint8_t)0x00U) /*!< Reset generated when entering in STANDBY */
/**
* @}
*/
/** @defgroup FLASHEx_PCROP_State FLASH PCROP State
#if defined(FLASH_OPTR_WPRMOD)
/** @defgroup FLASHEx_OptionAdv_Type FLASHEx Option Advanced Type
* @{
*/
#define OB_PCROP_STATE_DISABLE ((uint8_t)0x00U) /*!< Disable PCROP */
#define OB_PCROP_STATE_ENABLE ((uint8_t)0x01U) /*!< Enable PCROP */
#define OPTIONBYTE_PCROP ((uint32_t)0x01U) /*!<PCROP option byte configuration*/
/**
* @}
*/
#endif /* FLASH_OPTR_WPRMOD */
/** @defgroup FLASHEx_OptionAdv_Type FLASH Option Byte
#if defined(FLASH_OPTR_BFB2)
/** @defgroup FLASHEx_OptionAdv_Type FLASHEx Option Advanced Type
* @{
*/
#if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
#define OPTIONBYTE_PCROP ((uint32_t)0x01U) /*!< PCROP option byte configuration*/
#define OPTIONBYTE_BOOTCONFIG ((uint32_t)0x02U) /*!< BOOTConfig option byte configuration, boot from bank 2*/
#else /* if STM32L071xx || STM32L072xx || STM32L073xx || STM32L081xx || STM32L082xx || STM32L083xx */
#define OPTIONBYTE_PCROP ((uint32_t)0x01U) /*!< PCROP option byte configuration*/
#endif /* if STM32L071xx || STM32L072xx || STM32L073xx || STM32L081xx || STM32L082xx || STM32L083xx */
#define OPTIONBYTE_BOOTCONFIG ((uint32_t)0x02U) /*!<BOOTConfig option byte configuration*/
/**
* @}
*/
#endif /* FLASH_OPTR_BFB2 */
#if defined(FLASH_OPTR_WPRMOD)
/** @defgroup FLASHEx_PCROP_State FLASHEx PCROP State
* @{
*/
#define OB_PCROP_STATE_DISABLE ((uint32_t)0x00U) /*!<Disable PCROP for selected sectors */
#define OB_PCROP_STATE_ENABLE ((uint32_t)0x01U) /*!<Enable PCROP for selected sectors */
/**
* @}
*/
/** @defgroup FLASHEx_Selection_Protection_Mode FLASHEx Selection Protection Mode
* @{
*/
#define OB_PCROP_DESELECTED ((uint16_t)0x0000U) /*!< Disabled PCROP, nWPRi bits used for Write Protection on sector i */
#define OB_PCROP_SELECTED ((uint16_t)FLASH_OPTR_WPRMOD) /*!< Enable PCROP, nWPRi bits used for PCRoP Protection on sector i */
/**
* @}
*/
#endif /* FLASH_OPTR_WPRMOD */
#if defined (STM32L011xx) || defined (STM32L021xx) || defined (STM32L031xx) || defined (STM32L041xx)
/** @defgroup FLASHEx_Option_Bytes_PC_ReadWrite_Protection FLASHEx Option Bytes PC Read/Write Protection
* @{
@ -450,8 +608,8 @@ typedef struct
/**
* @}
*/
#endif /* if STM32L071xx || STM32L072xx || STM32L073xx || STM32L081xx || STM32L082xx || STM32L083xx */
#endif /* STM32L071xx || STM32L072xx || STM32L073xx || STM32L081xx || STM32L082xx || STM32L083xx */
/** @defgroup FLASHEx_Option_Bytes_BOOTBit1 FLASH Option Bytes BOOT Bit1 Setup
* @{
*/
@ -461,97 +619,110 @@ typedef struct
* @}
*/
#if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
/** @defgroup FLASHEx_Option_Bytes_BOOT_BANK FLASH Option Bytes BOOT BANK
/** @defgroup FLASHEx_Type_Program_Data FLASHEx Type Program Data
* @{
*/
#define FLASH_TYPEPROGRAMDATA_BYTE ((uint32_t)0x00U) /*!<Program byte (8-bit) at a specified address.*/
#define FLASH_TYPEPROGRAMDATA_HALFWORD ((uint32_t)0x01U) /*!<Program a half-word (16-bit) at a specified address.*/
#define FLASH_TYPEPROGRAMDATA_WORD ((uint32_t)0x02U) /*!<Program a word (32-bit) at a specified address.*/
/**
* @}
*/
#if defined(FLASH_OPTR_BFB2)
/** @defgroup FLASHEx_Option_Bytes_BOOT FLASHEx Option Bytes BOOT
* @{
*/
#define OB_BOOT_BANK1 ((uint8_t)0x00U) /*!< At startup, if boot pin 0 and BOOT1 bit are set in boot from user Flash position
and this parameter is selected the device will boot from Bank 1 (Default)*/
#define OB_BOOT_BANK2 (uint8_t)(0x01U) /*!< At startup, if boot pin 0 and BOOT1 bit are set in boot from user Flash position
#define OB_BOOT_BANK2 ((uint8_t)(FLASH_OPTR_BFB2 >> 16)) /*!< At startup, if boot pin 0 and BOOT1 bit are set in boot from user Flash position
and this parameter is selected the device will boot from Bank 2 */
/**
* @}
*/
#endif /* if STM32L071xx || STM32L072xx || STM32L073xx || STM32L081xx || STM32L082xx || STM32L083xx */
#endif /* FLASH_OPTR_BFB2 */
/** @defgroup FLASHEx_Type_Program_Data FLASH Type Program Data
* @{
*/
#define FLASH_TYPEPROGRAMDATA_BYTE ((uint32_t)0x00U) /*!< Program byte (8-bit) at a specified address.*/
#define FLASH_TYPEPROGRAMDATA_HALFWORD ((uint32_t)0x01U) /*!< Program a half-word (16-bit) at a specified address.*/
#define FLASH_TYPEPROGRAMDATA_WORD ((uint32_t)0x02U) /*!< Program a word (32-bit) at a specified address.*/
/* Aliases for compatibility with the V1.0.0 package */
#define FLASH_TYPEPROGRAM_BYTE FLASH_TYPEPROGRAMDATA_BYTE
#define FLASH_TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORD
/**
* @}
*/
/** @defgroup FLASHEx_Address FLASHEx Address
* @{
*/
#define FLASH_NBPAGES_MAX (FLASH_SIZE / FLASH_PAGE_SIZE)
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup FLASHEx_Exported_Macros FLASHEx Exported Macros
* @brief
/** @defgroup FLASHEx_Exported_Macros FLASHEx Exported Macros
* @{
*/
/**
* @brief Set the FLASH Latency.
* @param __LATENCY__: FLASH Latency
* This parameter can be one of the following values:
* @arg FLASH_LATENCY_0: FLASH Zero Latency cycle
* @arg FLASH_LATENCY_1: FLASH One Latency cycle
* @param __LATENCY__ FLASH Latency
* This parameter can be one of the following values:
* @arg @ref FLASH_LATENCY_0 FLASH Zero Latency cycle
* @arg @ref FLASH_LATENCY_1 FLASH One Latency cycle
* @retval none
*/
#define __HAL_FLASH_SET_LATENCY(__LATENCY__) \
MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(__LATENCY__))
/**
* @brief Get the FLASH Latency.
* @retval FLASH Latency
* This parameter can be one of the following values:
* @arg FLASH_LATENCY_0: FLASH Zero Latency cycle
* @arg FLASH_LATENCY_1: FLASH One Latency cycle
*/
#define __HAL_FLASH_GET_LATENCY() (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))
* @brief Get the FLASH Latency.
* @retval FLASH Latency
* This parameter can be one of the following values:
* @arg @ref FLASH_LATENCY_0 FLASH Zero Latency cycle
* @arg @ref FLASH_LATENCY_1 FLASH One Latency cycle
*/
#define __HAL_FLASH_GET_LATENCY() (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))
/**
* @brief Enable/Disable the FLASH prefetch buffer.
* @brief Enable the FLASH prefetch buffer.
* @retval none
*/
#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() SET_BIT((FLASH->ACR), FLASH_ACR_PRFTEN)
#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() CLEAR_BIT((FLASH->ACR), FLASH_ACR_PRFTEN)
#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() SET_BIT((FLASH->ACR), FLASH_ACR_PRFTEN)
/**
* @brief Enable/Disable the FLASH Buffer cache.
* @brief Disable the FLASH prefetch buffer.
* @retval none
*/
#define __HAL_FLASH_BUFFER_CACHE_ENABLE() SET_BIT((FLASH->ACR), FLASH_ACR_DISAB_BUF)
#define __HAL_FLASH_BUFFER_CACHE_DISABLE() CLEAR_BIT((FLASH->ACR), FLASH_ACR_DISAB_BUF)
#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() CLEAR_BIT((FLASH->ACR), FLASH_ACR_PRFTEN)
/**
* @brief Enable/Disable the FLASH preread buffer.
* @brief Enable the FLASH Buffer cache.
* @retval none
*/
#define __HAL_FLASH_PREREAD_BUFFER_ENABLE() SET_BIT((FLASH->ACR), FLASH_ACR_PRE_READ)
#define __HAL_FLASH_PREREAD_BUFFER_DISABLE() CLEAR_BIT((FLASH->ACR), FLASH_ACR_PRE_READ)
#define __HAL_FLASH_BUFFER_CACHE_ENABLE() SET_BIT((FLASH->ACR), FLASH_ACR_DISAB_BUF)
/**
* @brief Enable/Disable the FLASH power down during Sleep mode.
* @brief Disable the FLASH Buffer cache.
* @retval none
*/
#define __HAL_FLASH_SLEEP_POWERDOWN_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD)
#define __HAL_FLASH_SLEEP_POWERDOWN_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD)
#define __HAL_FLASH_BUFFER_CACHE_DISABLE() CLEAR_BIT((FLASH->ACR), FLASH_ACR_DISAB_BUF)
/**
* @brief Enable the FLASH preread buffer.
* @retval none
*/
#define __HAL_FLASH_PREREAD_BUFFER_ENABLE() SET_BIT((FLASH->ACR), FLASH_ACR_PRE_READ)
/**
* @brief Disable the FLASH preread buffer.
* @retval none
*/
#define __HAL_FLASH_PREREAD_BUFFER_DISABLE() CLEAR_BIT((FLASH->ACR), FLASH_ACR_PRE_READ)
/**
* @brief Enable the FLASH power down during Sleep mode
* @retval none
*/
#define __HAL_FLASH_SLEEP_POWERDOWN_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD)
/**
* @brief Disable the FLASH power down during Sleep mode
* @retval none
*/
#define __HAL_FLASH_SLEEP_POWERDOWN_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD)
/**
* @brief Enable the Flash Run power down mode.
@ -565,49 +736,67 @@ typedef struct
/**
* @brief Disable the Flash Run power down mode.
* @note Writing this bit to 0 this bit, automatically the keys are
* @note Writing this bit to 0 this bit, automatically the keys are
* loss and a new unlock sequence is necessary to re-write it to 1.
*/
#define __HAL_FLASH_POWER_DOWN_DISABLE() do { FLASH->PDKEYR = FLASH_PDKEY1; \
FLASH->PDKEYR = FLASH_PDKEY2; \
CLEAR_BIT((FLASH->ACR), FLASH_ACR_RUN_PD); \
CLEAR_BIT((FLASH->ACR), FLASH_ACR_RUN_PD); \
} while (0)
/**
* @}
*/
/** @defgroup FLASHEx_Exported_Functions FLASHEx Exported Functions
/* Exported functions --------------------------------------------------------*/
/** @addtogroup FLASHEx_Exported_Functions
* @{
*/
/** @defgroup FLASHEx_Exported_Functions_Group1 FLASH Memory Erasing functions
/** @addtogroup FLASHEx_Exported_Functions_Group1
* @{
*/
HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError);
HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit);
/**
* @}
*/
/** @defgroup FLASHEx_Exported_Functions_Group2 Option Bytes Programming functions
/** @addtogroup FLASHEx_Exported_Functions_Group2
* @{
*/
HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);
void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
#if defined(FLASH_OPTR_WPRMOD) || defined(FLASH_OPTR_BFB2)
HAL_StatusTypeDef HAL_FLASHEx_AdvOBProgram (FLASH_AdvOBProgramInitTypeDef *pAdvOBInit);
void HAL_FLASHEx_AdvOBGetConfig(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit);
#endif /* FLASH_OPTR_WPRMOD || FLASH_OPTR_BFB2 */
#if defined(FLASH_OPTR_WPRMOD)
HAL_StatusTypeDef HAL_FLASHEx_OB_SelectPCROP(void);
HAL_StatusTypeDef HAL_FLASHEx_OB_DeSelectPCROP(void);
#endif /* FLASH_OPTR_WPRMOD */
/**
* @}
*/
/** @defgroup FLASHEx_Exported_Functions_Group3 DATA EEPROM Programming functions
/** @addtogroup FLASHEx_Exported_Functions_Group3
* @{
*/
HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Unlock(void);
HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Lock(void);
HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Erase(uint32_t Address);
HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Program(uint32_t TypeProgram, uint32_t Address, uint32_t Data);
void HAL_FLASHEx_DATAEEPROM_EnableFixedTimeProgram(void);
@ -620,77 +809,6 @@ void HAL_FLASHEx_DATAEEPROM_DisableFixedTimeProgram(void);
/**
* @}
*/
/** @addtogroup FLASHEx_Private
* @{
*/
#define IS_FLASH_TYPEERASE(__VALUE__) (((__VALUE__) == FLASH_TYPEERASE_PAGES))
#define IS_OPTIONBYTE(__VALUE__) (((__VALUE__) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | \
OPTIONBYTE_USER | OPTIONBYTE_BOR | OPTIONBYTE_BOOT_BIT1)))
#define IS_WRPSTATE(__VALUE__) (((__VALUE__) == OB_WRPSTATE_DISABLE) || \
((__VALUE__) == OB_WRPSTATE_ENABLE))
#define IS_OB_WRP(PAGE) (((PAGE) != 0x0000000U))
#define IS_OB_RDP(__LEVEL__) (((__LEVEL__) == OB_RDP_LEVEL_0)||\
((__LEVEL__) == OB_RDP_LEVEL_1)||\
((__LEVEL__) == OB_RDP_LEVEL_2))
#define IS_OB_BOR_LEVEL(__LEVEL__) ( ((__LEVEL__) == OB_BOR_OFF) || \
((__LEVEL__) == OB_BOR_LEVEL1) || \
((__LEVEL__) == OB_BOR_LEVEL2) || \
((__LEVEL__) == OB_BOR_LEVEL3) || \
((__LEVEL__) == OB_BOR_LEVEL4) || \
((__LEVEL__) == OB_BOR_LEVEL5))
#define IS_OB_IWDG_SOURCE(__SOURCE__) (((__SOURCE__) == OB_IWDG_SW) || ((__SOURCE__) == OB_IWDG_HW))
#define IS_OB_STOP_SOURCE(__SOURCE__) (((__SOURCE__) == OB_STOP_NORST) || ((__SOURCE__) == OB_STOP_RST))
#define IS_OB_STDBY_SOURCE(__SOURCE__) (((__SOURCE__) == OB_STDBY_NORST) || ((__SOURCE__) == OB_STDBY_RST))
#define IS_PCROPSTATE(VALUE)(((VALUE) == OB_PCROP_STATE_DISABLE) || \
((VALUE) == OB_PCROP_STATE_ENABLE))
#define IS_OB_PCROP(__PAGE__) (((__PAGE__) != 0x0000000U))
#define IS_OB_BOOT1(__BOOT_BIT1__) (((__BOOT_BIT1__) == OB_BOOT_BIT1_RESET) || ((__BOOT_BIT1__) == OB_BOOT_BIT1_SET))
#define IS_TYPEPROGRAMDATA(__VALUE__) (((__VALUE__) == FLASH_TYPEPROGRAMDATA_BYTE) || \
((__VALUE__) == FLASH_TYPEPROGRAMDATA_HALFWORD) || \
((__VALUE__) == FLASH_TYPEPROGRAMDATA_WORD))
#define IS_NBPAGES(__PAGES__) (((__PAGES__) >= 1) && ((__PAGES__) <= FLASH_NBPAGES_MAX))
#if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
#define IS_OBEX(__VALUE__)(((__VALUE__) <= (OPTIONBYTE_PCROP | OPTIONBYTE_BOOTCONFIG)))
#define IS_OB_BOOT_BANK(__BANK__) (((__BANK__) == OB_BOOT_BANK2) || ((__BANK__) == OB_BOOT_BANK1))
#define IS_FLASH_DATA_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= DATA_EEPROM_BASE) && ((__ADDRESS__) <= DATA_EEPROM_BANK2_END))
#define IS_FLASH_DATA_BANK1_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= DATA_EEPROM_BASE) && ((__ADDRESS__) <= DATA_EEPROM_BANK1_END))
#define IS_FLASH_DATA_BANK2_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= DATA_EEPROM_BANK2_BASE) && ((__ADDRESS__) <= DATA_EEPROM_BANK2_END))
#define IS_FLASH_PROGRAM_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= FLASH_BASE) && ((__ADDRESS__) < (FLASH_BASE + FLASH_SIZE)))
#define IS_FLASH_PROGRAM_BANK1_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= FLASH_BASE) && ((__ADDRESS__) < (FLASH_BASE + (FLASH_SIZE >> 1))))
#define IS_FLASH_PROGRAM_BANK2_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= FLASH_BANK2_BASE) && ((__ADDRESS__) < (FLASH_BASE + FLASH_SIZE)))
#else
#define IS_OBEX(VALUE)((VALUE) == OPTIONBYTE_PCROP)
#define IS_FLASH_DATA_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= DATA_EEPROM_BASE) && ((__ADDRESS__) <= DATA_EEPROM_END))
#define IS_FLASH_PROGRAM_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= FLASH_BASE) && ((__ADDRESS__) < (FLASH_BASE + FLASH_SIZE)))
#endif
/**
* @}
*/
/* Define the private group ***********************************/
/**************************************************************/
/** @defgroup FLASHEx_Private FLASHEx Private
* @{
*/
/**
* @}
*/
/**************************************************************/
/**
* @}
@ -707,4 +825,3 @@ void HAL_FLASHEx_DATAEEPROM_DisableFixedTimeProgram(void);
#endif /* __STM32L0xx_HAL_FLASH_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

306
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_flash_ramfunc.c
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32l0xx_hal_flash_ramfunc.c
* @author MCD Application Team
* @version V1.7.0
* @date 31-May-2016
* @brief FLASH RAMFUNC driver.
* This file provides a Flash firmware functions which should be
* executed from internal SRAM
@ -57,7 +55,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32l0xx_hal.h"
@ -68,30 +66,48 @@
#ifdef HAL_FLASH_MODULE_ENABLED
/** @addtogroup FLASH
* @{
*/
/** @addtogroup FLASH_Private_Variables
* @{
*/
extern FLASH_ProcessTypeDef pFlash;
/**
* @}
*/
/** @addtogroup FLASH_RAMFUNC
/**
* @}
*/
/** @defgroup FLASH_RAMFUNC FLASH_RAMFUNC
* @brief FLASH functions executed from RAM
* @{
*/
/** @addtogroup FLASH_RAMFUNC_Private
* @{
*/
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/** @defgroup FLASH_RAMFUNC_Private_Functions FLASH RAM Private Functions
* @{
*/
static __RAM_FUNC FLASHRAM_WaitForLastOperation(uint32_t Timeout);
static __RAM_FUNC FLASHRAM_SetErrorCode(void);
/**
* @}
*/
/** @addtogroup FLASH_RAMFUNC_Exported_Functions
/* Private functions ---------------------------------------------------------*/
/** @defgroup FLASH_RAMFUNC_Exported_Functions FLASH RAM Exported Functions
*
@verbatim
@verbatim
===============================================================================
##### ramfunc functions #####
===============================================================================
@ -101,33 +117,35 @@ static __RAM_FUNC FLASHRAM_SetErrorCode(void);
@endverbatim
* @{
*/
*/
/** @addtogroup FLASH_RAMFUNC_Exported_Functions_Group1
/** @defgroup FLASH_RAMFUNC_Exported_Functions_Group1 Peripheral features functions
* @{
*/
/**
* @brief Enable the power down mode during RUN mode.
* @note This function can be used only when the user code is running from Internal SRAM.
* @retval HAL Status
* @note This function can be used only when the user code is running from Internal SRAM.
* @retval HAL status
*/
__RAM_FUNC HAL_FLASHEx_EnableRunPowerDown(void)
{
/* Enable the Power Down in Run mode*/
__HAL_FLASH_POWER_DOWN_ENABLE();
return HAL_OK;
}
/**
* @brief Disable the power down mode during RUN mode.
* @note This function can be used only when the user code is running from Internal SRAM.
* @retval HAL Status
* @note This function can be used only when the user code is running from Internal SRAM.
* @retval HAL status
*/
__RAM_FUNC HAL_FLASHEx_DisableRunPowerDown(void)
{
/* Disable the Power Down in Run mode*/
__HAL_FLASH_POWER_DOWN_DISABLE();
return HAL_OK;
}
@ -135,22 +153,21 @@ __RAM_FUNC HAL_FLASHEx_DisableRunPowerDown(void)
* @}
*/
#if defined(STM32L071xx) || defined(STM32L072xx) || defined(STM32L073xx) || defined(STM32L081xx) || defined(STM32L082xx) || defined(STM32L083xx)
/** @addtogroup FLASH_RAMFUNC_Exported_Functions_Group2
/** @defgroup FLASH_RAMFUNC_Exported_Functions_Group2 Programming and erasing operation functions
*
@verbatim
@endverbatim
* @{
*/
#if defined(FLASH_PECR_PARALLBANK)
/**
* @brief Erases a specified 2 pages in program memory in parallel.
* @note This function can be used only for STM32L07xxx/STM32L08xxx devices.
* To correctly run this function, the HAL_FLASH_Unlock() function
* To correctly run this function, the @ref HAL_FLASH_Unlock() function
* must be called before.
* Call the HAL_FLASH_Lock() to disable the flash memory access
* (recommended to protect the FLASH memory against possible unwanted operation).
* Call the @ref HAL_FLASH_Lock() to disable the flash memory access
* (recommended to protect the FLASH memory against possible unwanted operation).
* @param Page_Address1: The page address in program memory to be erased in
* the first Bank (BANK1). This parameter should be between FLASH_BASE
* and FLASH_BANK1_END.
@ -158,9 +175,8 @@ __RAM_FUNC HAL_FLASHEx_DisableRunPowerDown(void)
* the second Bank (BANK2). This parameter should be between FLASH_BANK2_BASE
* and FLASH_BANK2_END.
* @note A Page is erased in the Program memory only if the address to load
* is the start address of a page (multiple of 128 bytes).
* @retval HAL Status: The returned value can be:
* HAL_ERROR, HAL_OK or HAL_TIMEOUT.
* is the start address of a page (multiple of @ref FLASH_PAGE_SIZE bytes).
* @retval HAL status
*/
__RAM_FUNC HAL_FLASHEx_EraseParallelPage(uint32_t Page_Address1, uint32_t Page_Address2)
{
@ -179,7 +195,7 @@ __RAM_FUNC HAL_FLASHEx_EraseParallelPage(uint32_t Page_Address1, uint32_t Page_A
/* Write 00000000h to the first word of the first program page to erase */
*(__IO uint32_t *)Page_Address1 = 0x00000000U;
/* Write 00000000h to the first word of the second program page to erase */
*(__IO uint32_t *)Page_Address2 = 0x00000000U;
*(__IO uint32_t *)Page_Address2 = 0x00000000U;
/* Wait for last operation to be completed */
status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
@ -189,24 +205,24 @@ __RAM_FUNC HAL_FLASHEx_EraseParallelPage(uint32_t Page_Address1, uint32_t Page_A
CLEAR_BIT(FLASH->PECR, FLASH_PECR_ERASE);
CLEAR_BIT(FLASH->PECR, FLASH_PECR_PARALLBANK);
}
/* Return the erasesStatus */
/* Return the Erase Status */
return status;
}
/**
* @brief Programs 2 half pages in program memory in parallel. The half page size is 16 Words.
* @note This function can be used only for STM32L07xxx/STM32L08xxx devices.
* @brief Program 2 half pages in program memory in parallel (half page size is 16 Words).
* @note This function can be used only for STM32L07xxx/STM32L08xxx devices.
* @param Address1: specifies the first address to be written in the first bank
* (BANK1). This parameter should be between FLASH_BASE and (FLASH_BANK1_END - FLASH_PAGE_SIZE).
* (BANK1). This parameter should be between FLASH_BASE and (FLASH_BANK1_END - FLASH_PAGE_SIZE).
* @param pBuffer1: pointer to the buffer containing the data to be written
* to the first half page in the first bank.
* @param Address2: specifies the second address to be written in the second bank
* (BANK2). This parameter should be between FLASH_BANK2_BASE and (FLASH_BANK2_END - FLASH_PAGE_SIZE).
* (BANK2). This parameter should be between FLASH_BANK2_BASE and (FLASH_BANK2_END - FLASH_PAGE_SIZE).
* @param pBuffer2: pointer to the buffer containing the data to be written
* to the second half page in the second bank.
* @note To correctly run this function, the HAL_FLASH_Unlock() function
* @note To correctly run this function, the @ref HAL_FLASH_Unlock() function
* must be called before.
* Call the HAL_FLASH_Lock() to disable the flash memory access
* Call the @ref HAL_FLASH_Lock() to disable the flash memory access
* (recommended to protect the FLASH memory against possible unwanted operation).
* @note Half page write is possible only from SRAM.
* @note A half page is written to the program memory only if the first
@ -219,13 +235,12 @@ __RAM_FUNC HAL_FLASHEx_EraseParallelPage(uint32_t Page_Address1, uint32_t Page_A
* complete write operation is aborted. Software should then reset the
* FPRG and PROG/DATA bits and restart the write operation from the
* beginning.
* @retval HAL Status: The returned value can be:
* HAL_ERROR, HAL_OK or HAL_TIMEOUT.
* @retval HAL status
*/
__RAM_FUNC HAL_FLASHEx_ProgramParallelHalfPage(uint32_t Address1, uint32_t* pBuffer1, uint32_t Address2, uint32_t* pBuffer2)
{
uint32_t count;
HAL_StatusTypeDef status;
uint32_t count = 0U;
HAL_StatusTypeDef status = HAL_OK;
/* Wait for last operation to be completed */
status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
@ -237,67 +252,58 @@ __RAM_FUNC HAL_FLASHEx_ProgramParallelHalfPage(uint32_t Address1, uint32_t* pBuf
SET_BIT(FLASH->PECR, FLASH_PECR_FPRG);
SET_BIT(FLASH->PECR, FLASH_PECR_PROG);
/* Wait for last operation to be completed */
status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
if(status == HAL_OK)
{
/* Write one half page,
Address1 doesn't need to be increased */
count = 0U;
/* Disable all IRQs */
__disable_irq();
/* Write the first half page directly with 16 different words */
while(count < 16U)
{
/* Address1 doesn't need to be increased */
*(__IO uint32_t*) Address1 = *pBuffer1;
pBuffer1++;
count++;
count ++;
}
/* Write the second half page,
Address2 doesn't need to be increased */
/* Write the second half page directly with 16 different words */
count = 0U;
while(count < 16U)
{
/* Address2 doesn't need to be increased */
*(__IO uint32_t*) Address2 = *pBuffer2;
pBuffer2++;
count++;
count ++;
}
/* Enable IRQs */
__enable_irq();
/* Wait for last operation to be completed */
status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
}
}
/* if the write operation is completed, disable the PROG, FPRG and PARALLBANK bits */
CLEAR_BIT(FLASH->PECR, FLASH_PECR_PROG);
CLEAR_BIT(FLASH->PECR, FLASH_PECR_FPRG);
CLEAR_BIT(FLASH->PECR, FLASH_PECR_PARALLBANK);
}
/* Return the Write Status */
return status;
}
/**
* @}
*/
#endif /* STM32L071xx || STM32L072xx || STM32L073xx || STM32L081xx || STM32L082xx || STM32L083xx */
#endif /* FLASH_PECR_PARALLBANK */
/** @addtogroup FLASH_RAMFUNC_Exported_Functions_Group1
*
* @{
*/
/**
* @brief Program a half page in program memory.
* @brief Program a half page in program memory.
* @param Address: specifies the address to be written.
* @param pBuffer: pointer to the buffer containing the data to be written to
* the half page.
* @note To correctly run this function, the HAL_FLASH_Unlock() function
* @note To correctly run this function, the @ref HAL_FLASH_Unlock() function
* must be called before.
* Call the HAL_FLASH_Lock() to disable the flash memory access
* Call the @ref HAL_FLASH_Lock() to disable the flash memory access
* (recommended to protect the FLASH memory against possible unwanted operation)
* @note Half page write is possible only from SRAM.
* @note A half page is written to the program memory only if the first
@ -310,67 +316,82 @@ __RAM_FUNC HAL_FLASHEx_ProgramParallelHalfPage(uint32_t Address1, uint32_t* pBuf
* complete write operation is aborted. Software should then reset the
* FPRG and PROG/DATA bits and restart the write operation from the
* beginning.
* @retval HAL Status: The returned value can be:
* HAL_ERROR, HAL_OK or HAL_TIMEOUT.
* @retval HAL status
*/
__RAM_FUNC HAL_FLASHEx_HalfPageProgram(uint32_t Address, uint32_t *pBuffer)
__RAM_FUNC HAL_FLASHEx_HalfPageProgram(uint32_t Address, uint32_t* pBuffer)
{
uint32_t count;
HAL_StatusTypeDef status;
uint32_t count = 0U;
HAL_StatusTypeDef status = HAL_OK;
/* Wait for last operation to be completed */
status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
if(status == HAL_OK)
{
/* Proceed to program the new half page */
SET_BIT(FLASH->PECR, FLASH_PECR_FPRG);
SET_BIT(FLASH->PECR, FLASH_PECR_PROG);
count = 0U;
/* Write one half page,
Address doesn't need to be increased */
/* Disable all IRQs */
__disable_irq();
/* Write one half page directly with 16 different words */
while(count < 16U)
{
/* Address doesn't need to be increased */
*(__IO uint32_t*) Address = *pBuffer;
pBuffer++;
count++;
count ++;
}
/* Enable IRQs */
__enable_irq();
/* Wait for last operation to be completed */
status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
/* If the write operation is completed, disable the PROG and FPRG bits */
CLEAR_BIT(FLASH->PECR, FLASH_PECR_PROG);
CLEAR_BIT(FLASH->PECR, FLASH_PECR_FPRG);
}
/* Return the write status */
/* Return the Write Status */
return status;
}
/**
* @}
*/
/** @defgroup FLASH_RAMFUNC_Exported_Functions_Group3 Peripheral errors functions
* @brief Peripheral errors functions
*
@verbatim
===============================================================================
##### Peripheral errors functions #####
===============================================================================
[..]
This subsection permit to get in run-time errors of the FLASH peripheral.
@endverbatim
* @{
*/
/**
* @brief Get the specific FLASH errors flag.
* @param error pointer is the error value. It can be a mixed of :
* @arg HAL_FLASH_ERROR_RD: FLASH Read Protection error flag (PCROP)
* @arg HAL_FLASH_ERROR_SIZE: FLASH Programming Parallelism error flag
* @arg HAL_FLASH_ERROR_PGA: FLASH Programming Alignment error flag
* @arg HAL_FLASH_ERROR_WRP: FLASH Write protected error flag
* @arg HAL_FLASH_ERROR_OPTV: FLASH Option valid error flag
* @arg HAL_FLASH_ERROR_FWWERR: FLASH Write or Errase operation aborted
* @arg HAL_FLASH_ERROR_NOTZERO: FLASH Write operation is done in a not-erased region
* @param Error pointer is the error value. It can be a mixed of:
* @arg @ref HAL_FLASH_ERROR_RD FLASH Read Protection error flag (PCROP)
* @arg @ref HAL_FLASH_ERROR_SIZE FLASH Programming Parallelism error flag
* @arg @ref HAL_FLASH_ERROR_PGA FLASH Programming Alignment error flag
* @arg @ref HAL_FLASH_ERROR_WRP FLASH Write protected error flag
* @arg @ref HAL_FLASH_ERROR_OPTV FLASH Option valid error flag
* @arg @ref HAL_FLASH_ERROR_FWWERR FLASH Write or Erase operation aborted
* @arg @ref HAL_FLASH_ERROR_NOTZERO FLASH Write operation is done in a not-erased region
* @retval HAL Status
*/
__RAM_FUNC HAL_FLASHRAM_GetError(uint32_t * error)
__RAM_FUNC HAL_FLASHEx_GetError(uint32_t * Error)
{
*error = ProcFlash.ErrorCode;
*Error = pFlash.ErrorCode;
return HAL_OK;
}
@ -382,7 +403,7 @@ __RAM_FUNC HAL_FLASHRAM_GetError(uint32_t * error)
* @}
*/
/** @addtogroup FLASH_RAMFUNC_Private
/** @addtogroup FLASH_RAMFUNC_Private_Functions
* @{
*/
@ -391,21 +412,26 @@ __RAM_FUNC HAL_FLASHRAM_GetError(uint32_t * error)
* @retval HAL Status
*/
static __RAM_FUNC FLASHRAM_SetErrorCode(void)
{
{
uint32_t flags = 0;
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR))
{
ProcFlash.ErrorCode |= HAL_FLASH_ERROR_WRP;
{
pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP;
flags |= FLASH_FLAG_WRPERR;
}
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR))
{
ProcFlash.ErrorCode |= HAL_FLASH_ERROR_PGA;
{
pFlash.ErrorCode |= HAL_FLASH_ERROR_PGA;
flags |= FLASH_FLAG_PGAERR;
}
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_SIZERR))
{
ProcFlash.ErrorCode |= HAL_FLASH_ERROR_SIZE;
pFlash.ErrorCode |= HAL_FLASH_ERROR_SIZE;
flags |= FLASH_FLAG_SIZERR;
}
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR))
{
{
/* WARNING : On the first cut of STM32L031xx and STM32L041xx devices,
* (RefID = 0x1000) the FLASH_FLAG_OPTVERR bit was not behaving
* as expected. If the user run an application using the first
@ -414,36 +440,38 @@ static __RAM_FUNC FLASHRAM_SetErrorCode(void)
* can be retrieved via the HAL_GetREVID() function.
*
*/
ProcFlash.ErrorCode |= HAL_FLASH_ERROR_OPTV;
pFlash.ErrorCode |= HAL_FLASH_ERROR_OPTV;
flags |= FLASH_FLAG_OPTVERR;
}
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR))
{
ProcFlash.ErrorCode |= HAL_FLASH_ERROR_RD;
{
pFlash.ErrorCode |= HAL_FLASH_ERROR_RD;
flags |= FLASH_FLAG_RDERR;
}
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_FWWERR))
{
ProcFlash.ErrorCode |= HAL_FLASH_ERROR_FWWERR;
pFlash.ErrorCode |= HAL_FLASH_ERROR_FWWERR;
flags |= HAL_FLASH_ERROR_FWWERR;
}
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_NOTZEROERR))
{
ProcFlash.ErrorCode |= HAL_FLASH_ERROR_NOTZERO;
pFlash.ErrorCode |= HAL_FLASH_ERROR_NOTZERO;
flags |= FLASH_FLAG_NOTZEROERR;
}
/* Errors are now stored, clear errors flags */
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR |
FLASH_FLAG_OPTVERR | FLASH_FLAG_RDERR | FLASH_FLAG_FWWERR |
FLASH_FLAG_NOTZEROERR);
/* Clear FLASH error pending bits */
__HAL_FLASH_CLEAR_FLAG(flags);
return HAL_OK;
}
}
/**
* @brief Wait for a FLASH operation to complete.
* @param Timeout: maximum flash operationtimeout
* @retval HAL status
*/
static __RAM_FUNC FLASHRAM_WaitForLastOperation(uint32_t Timeout)
static __RAM_FUNC FLASHRAM_WaitForLastOperation(uint32_t Timeout)
{
/* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.
Even if the FLASH operation fails, the BUSY flag will be reset and an error
@ -454,36 +482,42 @@ static __RAM_FUNC FLASHRAM_WaitForLastOperation(uint32_t Timeout)
Timeout--;
}
if(Timeout == 0x00U )
if(Timeout == 0x00U)
{
return HAL_TIMEOUT;
}
if( (__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR) != RESET) ||
(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) != RESET) ||
(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR) != RESET) ||
(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR) != RESET) ||
(__HAL_FLASH_GET_FLAG(FLASH_FLAG_SIZERR) != RESET) ||
(__HAL_FLASH_GET_FLAG(FLASH_FLAG_FWWERR) != RESET) ||
(__HAL_FLASH_GET_FLAG(FLASH_FLAG_NOTZEROERR) != RESET) )
{
/*Save the error code*/
/* WARNING : On the first cut of STM32L031xx and STM32L041xx devices,
* (RefID = 0x1000) the FLASH_FLAG_OPTVERR bit was not behaving
* as expected. If the user run an application using the first
* cut of the STM32L031xx device or the first cut of the STM32L041xx
* device, this error should be ignored. The revId of the device
* can be retrieved via the HAL_GetREVID() function.
*
*/
FLASHRAM_SetErrorCode();
return HAL_ERROR;
}
/* Check FLASH End of Operation flag */
if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP))
{
/* Clear FLASH End of Operation pending bit */
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
}
/* If there is an error flag set */
return HAL_OK;
if( __HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) ||
__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR) ||
__HAL_FLASH_GET_FLAG(FLASH_FLAG_SIZERR) ||
__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR) ||
__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR) ||
__HAL_FLASH_GET_FLAG(FLASH_FLAG_FWWERR) ||
__HAL_FLASH_GET_FLAG(FLASH_FLAG_NOTZEROERR) )
{
/*Save the error code*/
/* WARNING : On the first cut of STM32L031xx and STM32L041xx devices,
* (RefID = 0x1000) the FLASH_FLAG_OPTVERR bit was not behaving
* as expected. If the user run an application using the first
* cut of the STM32L031xx device or the first cut of the STM32L041xx
* device, this error should be ignored. The revId of the device
* can be retrieved via the HAL_GetREVID() function.
*
*/
FLASHRAM_SetErrorCode();
return HAL_ERROR;
}
/* There is no error flag set */
return HAL_OK;
}
/**
@ -495,11 +529,9 @@ static __RAM_FUNC FLASHRAM_WaitForLastOperation(uint32_t Timeout)
*/
#endif /* HAL_FLASH_MODULE_ENABLED */
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

48
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_flash_ramfunc.h
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32l0xx_hal_flash_ramfunc.h
* @author MCD Application Team
* @version V1.7.0
* @date 31-May-2016
* @brief Header file of FLASH RAMFUNC driver.
******************************************************************************
* @attention
@ -50,13 +48,16 @@
* @{
*/
/** @defgroup FLASH_RAMFUNC FLASH Ram Function
/** @addtogroup FLASH_RAMFUNC
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup FLASH_RAMFUNC_Exported_Functions FLASH Ram Exported Functions
/** @addtogroup FLASH_RAMFUNC_Exported_Functions
* @{
*/
@ -66,41 +67,45 @@
* file.
*/
/** @defgroup FLASH_RAMFUNC_Exported_Functions_Group1 FLASH RAM peripheral features functions
/** @addtogroup FLASH_RAMFUNC_Exported_Functions_Group1
* @{
*/
__RAM_FUNC HAL_FLASHEx_HalfPageProgram(uint32_t Address, uint32_t* pBuffer);
__RAM_FUNC HAL_FLASHEx_EnableRunPowerDown(void);
__RAM_FUNC HAL_FLASHEx_DisableRunPowerDown(void);
__RAM_FUNC HAL_FLASHRAM_GetError(uint32_t * error);
__RAM_FUNC HAL_FLASHEx_EnableRunPowerDown(void);
__RAM_FUNC HAL_FLASHEx_DisableRunPowerDown(void);
/**
* @}
*/
#if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
/** @defgroup FLASH_RAMFUNC_Exported_Functions_Group2 FLASH RAM programming and erasing operation functions
/** @addtogroup FLASH_RAMFUNC_Exported_Functions_Group2
* @{
*/
#if defined(FLASH_PECR_PARALLBANK)
__RAM_FUNC HAL_FLASHEx_EraseParallelPage(uint32_t Page_Address1, uint32_t Page_Address2);
__RAM_FUNC HAL_FLASHEx_ProgramParallelHalfPage(uint32_t Address1, uint32_t* pBuffer1, uint32_t Address2, uint32_t* pBuffer2);
#endif /* FLASH_PECR_PARALLBANK */
__RAM_FUNC HAL_FLASHEx_HalfPageProgram(uint32_t Address, uint32_t* pBuffer);
/**
* @}
*/
#endif /* STM32L071xx || STM32L072xx || STM32L073xx || STM32L081xx || STM32L082xx || STM32L083xx */
/**
* @}
*/
/* Define the private group ***********************************/
/**************************************************************/
/** @defgroup FLASH_RAMFUNC_Private FLASH Ram Private
/** @addtogroup FLASH_RAMFUNC_Exported_Functions_Group3
* @{
*/
__RAM_FUNC HAL_FLASHEx_GetError(uint32_t *Error);
/**
* @}
*/
/**************************************************************/
*/
/**
* @}
*/
/**
* @}
@ -117,4 +122,3 @@ __RAM_FUNC HAL_FLASHEx_ProgramParallelHalfPage(uint32_t Address1, uint32_t* pBuf
#endif /* __STM32L0xx_FLASH_RAMFUNC_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

18
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_gpio.c
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32l0xx_hal_gpio.c
* @author MCD Application Team
* @version V1.7.0
* @date 31-May-2016
* @brief GPIO HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the General Purpose Input/Output (GPIO) peripheral:
@ -194,7 +192,7 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
assert_param(IS_GPIO_PIN_AVAILABLE(GPIOx,(GPIO_Init->Pin)));
/* Configure the port pins */
while ((GPIO_Init->Pin) >> position)
while (((GPIO_Init->Pin) >> position) != 0)
{
/* Get the IO position */
iocurrent = (GPIO_Init->Pin) & (1U << position);
@ -251,12 +249,12 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
/* Enable SYSCFG Clock */
__HAL_RCC_SYSCFG_CLK_ENABLE();
temp = SYSCFG->EXTICR[position >> 2U];
temp &= ~(((uint32_t)0x0FU) << (4U * (position & 0x03U)));
temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U)));
CLEAR_BIT(temp, ((uint32_t)0x0FU) << (4U * (position & 0x03U)));
SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03U)));
SYSCFG->EXTICR[position >> 2U] = temp;
/* Clear EXTI line configuration */
temp = EXTI->IMR;
temp &= ~((uint32_t)iocurrent);
@ -315,7 +313,7 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
assert_param(IS_GPIO_PIN_AVAILABLE(GPIOx,GPIO_Pin));
/* Configure the port pins */
while (GPIO_Pin >> position)
while ((GPIO_Pin >> position) != 0)
{
/* Get the IO position */
iocurrent = (GPIO_Pin) & (1U << position);
@ -324,8 +322,8 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
{
/*------------------------- GPIO Mode Configuration --------------------*/
/* Configure IO Direction in Input Floting Mode */
GPIOx->MODER &= ~(GPIO_MODER_MODE0 << (position * 2U));
GPIOx->MODER |= (GPIO_MODER_MODE0 << (position * 2U));
/* Configure the default Alternate Function in current IO */
GPIOx->AFR[position >> 3U] &= ~((uint32_t)0xFU << ((uint32_t)(position & (uint32_t)0x07U) * 4U)) ;

5
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_gpio.h
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32l0xx_hal_gpio.h
* @author MCD Application Team
* @version V1.7.0
* @date 31-May-2016
* @brief Header file of GPIO HAL module.
******************************************************************************
* @attention
@ -142,7 +140,8 @@ typedef enum
*/
#define GPIO_PIN_MASK ((uint32_t)0x0000FFFFU) /* PIN mask for assert test */
#define IS_GPIO_PIN(__PIN__) (((__PIN__) & GPIO_PIN_MASK ) != (uint32_t)0x00U)
#define IS_GPIO_PIN(__PIN__) ((((__PIN__) & GPIO_PIN_MASK) != (uint32_t)0x00) &&\
(((__PIN__) & ~GPIO_PIN_MASK) == (uint32_t)0x00))
/** @defgroup GPIO_mode_define Mode definition
* @brief GPIO Configuration Mode

2
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_gpio_ex.h
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32l0xx_hal_gpio_ex.h
* @author MCD Application Team
* @version V1.7.0
* @date 31-May-2016
* @brief Header file of GPIO HAL Extension module.
******************************************************************************
* @attention

833
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_i2c.c
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File diff suppressed because it is too large Load Diff

127
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_i2c.h
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32l0xx_hal_i2c.h
* @author MCD Application Team
* @version $VERSION$
* @date $DATE$
* @brief Header file of I2C HAL module.
******************************************************************************
* @attention
@ -40,11 +38,11 @@
#define __STM32L0xx_HAL_I2C_H
#ifdef __cplusplus
extern "C" {
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32l0xx_hal_def.h"
#include "stm32l0xx_hal_def.h"
/** @addtogroup STM32L0xx_HAL_Driver
* @{
@ -52,7 +50,7 @@
/** @addtogroup I2C
* @{
*/
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup I2C_Exported_Types I2C Exported Types
@ -60,13 +58,13 @@
*/
/** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition
* @brief I2C Configuration Structure definition
* @brief I2C Configuration Structure definition
* @{
*/
typedef struct
{
uint32_t Timing; /*!< Specifies the I2C_TIMINGR_register value.
This parameter calculated by referring to I2C initialization
This parameter calculated by referring to I2C initialization
section in Reference manual */
uint32_t OwnAddress1; /*!< Specifies the first device own address.
@ -90,9 +88,9 @@ typedef struct
uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected.
This parameter can be a value of @ref I2C_NOSTRETCH_MODE */
}I2C_InitTypeDef;
} I2C_InitTypeDef;
/**
/**
* @}
*/
@ -122,7 +120,7 @@ typedef struct
* 0 : Ready (no Tx operation ongoing)\n
* 1 : Busy (Tx operation ongoing)
* @{
*/
*/
typedef enum
{
HAL_I2C_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */
@ -139,7 +137,7 @@ typedef enum
HAL_I2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */
HAL_I2C_STATE_ERROR = 0xE0U /*!< Error */
}HAL_I2C_StateTypeDef;
} HAL_I2C_StateTypeDef;
/**
* @}
@ -170,9 +168,9 @@ typedef enum
HAL_I2C_MODE_SLAVE = 0x20U, /*!< I2C communication is in Slave Mode */
HAL_I2C_MODE_MEM = 0x40U /*!< I2C communication is in Memory Mode */
}HAL_I2C_ModeTypeDef;
} HAL_I2C_ModeTypeDef;
/**
/**
* @}
*/
@ -213,7 +211,7 @@ typedef struct __I2C_HandleTypeDef
__IO uint32_t PreviousState; /*!< I2C communication Previous state */
HAL_StatusTypeDef (*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); /*!< I2C transfer IRQ handler function pointer */
HAL_StatusTypeDef(*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); /*!< I2C transfer IRQ handler function pointer */
DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */
@ -227,8 +225,10 @@ typedef struct __I2C_HandleTypeDef
__IO uint32_t ErrorCode; /*!< I2C Error code */
__IO uint32_t ErrorCode; /*!< I2C Error code */
__IO uint32_t AddrEventCount; /*!< I2C Address Event counter */
}I2C_HandleTypeDef;
} I2C_HandleTypeDef;
/**
* @}
*/
@ -313,7 +313,7 @@ typedef struct __I2C_HandleTypeDef
/**
* @}
*/
/** @defgroup I2C_XFERDIRECTION I2C Transfer Direction Master Point of View
* @{
*/
@ -337,9 +337,9 @@ typedef struct __I2C_HandleTypeDef
* @{
*/
#define I2C_NO_STARTSTOP (0x00000000U)
#define I2C_GENERATE_STOP I2C_CR2_STOP
#define I2C_GENERATE_START_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN)
#define I2C_GENERATE_START_WRITE I2C_CR2_START
#define I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP)
#define I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
#define I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
/**
* @}
*/
@ -431,7 +431,7 @@ typedef struct __I2C_HandleTypeDef
* @retval None
*/
#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
/** @brief Check whether the specified I2C interrupt source is enabled or not.
* @param __HANDLE__ specifies the I2C Handle.
* @param __INTERRUPT__ specifies the I2C interrupt source to check.
@ -506,7 +506,7 @@ typedef struct __I2C_HandleTypeDef
#define __HAL_I2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
/** @brief Generate a Non-Acknowledge I2C peripheral in Slave mode.
* @param __HANDLE__: specifies the I2C Handle.
* @param __HANDLE__ specifies the I2C Handle.
* @retval None
*/
#define __HAL_I2C_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
@ -527,7 +527,7 @@ typedef struct __I2C_HandleTypeDef
*/
/* Initialization and de-initialization functions******************************/
HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c);
HAL_StatusTypeDef HAL_I2C_DeInit (I2C_HandleTypeDef *hi2c);
HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c);
void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c);
void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c);
/**
@ -538,7 +538,7 @@ void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c);
* @{
*/
/* IO operation functions ****************************************************/
/******* Blocking mode: Polling */
/******* Blocking mode: Polling */
HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
@ -547,7 +547,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress
HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);
/******* Non-Blocking mode: Interrupt */
/******* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
@ -563,7 +563,7 @@ HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c);
HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c);
HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress);
/******* Non-Blocking mode: DMA */
/******* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
@ -604,11 +604,11 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
/**
* @}
*/
*/
/**
* @}
*/
*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup I2C_Private_Constants I2C Private Constants
@ -617,7 +617,10 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
/**
* @}
*/
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup I2C_Private_Macro I2C Private Macros
/* Private macros ------------------------------------------------------------*/
/** @defgroup I2C_Private_Macro I2C Private Macros
@ -683,6 +686,70 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
* @}
*/
/* Private Functions ---------------------------------------------------------*/
/** @defgroup I2C_Private_Functions I2C Private Functions
* @{
*/
#define IS_I2C_ADDRESSING_MODE(MODE) (((MODE) == I2C_ADDRESSINGMODE_7BIT) || \
((MODE) == I2C_ADDRESSINGMODE_10BIT))
#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \
((ADDRESS) == I2C_DUALADDRESS_ENABLE))
#define IS_I2C_OWN_ADDRESS2_MASK(MASK) (((MASK) == I2C_OA2_NOMASK) || \
((MASK) == I2C_OA2_MASK01) || \
((MASK) == I2C_OA2_MASK02) || \
((MASK) == I2C_OA2_MASK03) || \
((MASK) == I2C_OA2_MASK04) || \
((MASK) == I2C_OA2_MASK05) || \
((MASK) == I2C_OA2_MASK06) || \
((MASK) == I2C_OA2_MASK07))
#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || \
((CALL) == I2C_GENERALCALL_ENABLE))
#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \
((STRETCH) == I2C_NOSTRETCH_ENABLE))
#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \
((SIZE) == I2C_MEMADD_SIZE_16BIT))
#define IS_TRANSFER_MODE(MODE) (((MODE) == I2C_RELOAD_MODE) || \
((MODE) == I2C_AUTOEND_MODE) || \
((MODE) == I2C_SOFTEND_MODE))
#define IS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == I2C_GENERATE_STOP) || \
((REQUEST) == I2C_GENERATE_START_READ) || \
((REQUEST) == I2C_GENERATE_START_WRITE) || \
((REQUEST) == I2C_NO_STARTSTOP))
#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_FIRST_FRAME) || \
((REQUEST) == I2C_FIRST_AND_NEXT_FRAME) || \
((REQUEST) == I2C_NEXT_FRAME) || \
((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \
((REQUEST) == I2C_LAST_FRAME))
#define I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
#define I2C_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 16U)
#define I2C_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U)
#define I2C_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
#define I2C_GET_OWN_ADDRESS1(__HANDLE__) ((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1)
#define I2C_GET_OWN_ADDRESS2(__HANDLE__) ((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2)
#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU)
#define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU)
#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00U))) >> 8U)))
#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
#define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \
(uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))
/**
* @}
*/
/* Private Functions ---------------------------------------------------------*/
/** @defgroup I2C_Private_Functions I2C Private Functions
* @{
@ -694,11 +761,11 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
/**
* @}
*/
*/
/**
* @}
*/
*/
#ifdef __cplusplus
}

28
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_i2c_ex.c
View File

@ -2,10 +2,8 @@
******************************************************************************
* @file stm32l0xx_hal_i2c_ex.c
* @author MCD Application Team
* @version $VERSION$
* @date $DATE$
* @brief I2C Extended HAL module driver.
* This file provides firmware functions to manage the following
* This file provides firmware functions to manage the following
* functionalities of I2C Extended peripheral:
* + Extended features functions
*
@ -19,7 +17,8 @@
(+) Possibility to disable or enable Analog Noise Filter
(+) Use of a configured Digital Noise Filter
(+) Disable or enable wakeup from Stop mode
(+) Disable or enable wakeup from Stop mode(s)
(+) Disable or enable Fast Mode Plus
##### How to use this driver #####
==============================================================================
@ -96,8 +95,9 @@
##### Extended features functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Configure Noise Filters
(+) Configure Noise Filters
(+) Configure Wake Up Feature
(+) Configure Fast Mode Plus
@endverbatim
* @{
@ -116,7 +116,7 @@ HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter));
if(hi2c->State == HAL_I2C_STATE_READY)
if (hi2c->State == HAL_I2C_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hi2c);
@ -162,7 +162,7 @@ HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter));
if(hi2c->State == HAL_I2C_STATE_READY)
if (hi2c->State == HAL_I2C_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hi2c);
@ -200,17 +200,17 @@ HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_
}
/**
* @brief Enable I2C wakeup from stop mode.
* @brief Enable I2C wakeup from Stop mode(s).
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2Cx peripheral.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp (I2C_HandleTypeDef *hi2c)
HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c)
{
/* Check the parameters */
assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance));
if(hi2c->State == HAL_I2C_STATE_READY)
if (hi2c->State == HAL_I2C_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hi2c);
@ -239,17 +239,17 @@ HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp (I2C_HandleTypeDef *hi2c)
}
/**
* @brief Disable I2C wakeup from stop mode.
* @brief Disable I2C wakeup from Stop mode(s).
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2Cx peripheral.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp (I2C_HandleTypeDef *hi2c)
HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c)
{
/* Check the parameters */
assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance));
if(hi2c->State == HAL_I2C_STATE_READY)
if (hi2c->State == HAL_I2C_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hi2c);
@ -262,7 +262,7 @@ HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp (I2C_HandleTypeDef *hi2c)
/* Enable wakeup from stop mode */
hi2c->Instance->CR1 &= ~(I2C_CR1_WUPEN);
__HAL_I2C_ENABLE(hi2c);
__HAL_I2C_ENABLE(hi2c);
hi2c->State = HAL_I2C_STATE_READY;

10
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_i2c_ex.h
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32l0xx_hal_i2c_ex.h
* @author MCD Application Team
* @version $VERSION$
* @date $DATE$
* @brief Header file of I2C HAL Extended module.
******************************************************************************
* @attention
@ -40,7 +38,7 @@
#define __STM32L0xx_HAL_I2C_EX_H
#ifdef __cplusplus
extern "C" {
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@ -52,7 +50,7 @@
/** @addtogroup I2CEx
* @{
*/
*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
@ -95,7 +93,7 @@
/**
* @}
*/
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
@ -145,7 +143,7 @@ void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
(((__CONFIG__) & (I2C_FASTMODEPLUS_I2C3)) == I2C_FASTMODEPLUS_I2C3)))
/**
* @}
*/
*/
/* Private Functions ---------------------------------------------------------*/
/** @defgroup I2CEx_Private_Functions I2C Extended Private Functions

2
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_i2s.c
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32l0xx_hal_i2s.c
* @author MCD Application Team
* @version V1.7.0
* @date 31-May-2016
* @brief I2S HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Integrated Interchip Sound (I2S) peripheral:

2
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_i2s.h
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32l0xx_hal_i2s.h
* @author MCD Application Team
* @version V1.7.0
* @date 31-May-2016
* @brief Header file of I2S HAL module.
******************************************************************************
* @attention

2578
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_irda.c
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File diff suppressed because it is too large Load Diff

885
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_irda.h
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File diff suppressed because it is too large Load Diff

112
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_irda_ex.h
View File

@ -2,13 +2,11 @@
******************************************************************************
* @file stm32l0xx_hal_irda_ex.h
* @author MCD Application Team
* @version V1.7.0
* @date 31-May-2016
* @brief Header file of IRDA HAL Extension module.
* @brief Header file of IRDA HAL Extended module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2013 STMicroelectronics</center></h2>
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -32,7 +30,7 @@
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
@ -50,42 +48,24 @@
* @{
*/
/** @defgroup IRDAEx IRDAEx
/** @addtogroup IRDAEx
* @{
*/
*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup IRDAEx_Extended_Exported_Constants IRDAEx Exported Constants
* @{
*/
/** @defgroup IRDAEx_Word_Length IRDAEx Word length
* @{
*/
#define IRDA_WORDLENGTH_7B ((uint32_t)USART_CR1_M1)
#define IRDA_WORDLENGTH_8B ((uint32_t)0x00000000U)
#define IRDA_WORDLENGTH_9B ((uint32_t)USART_CR1_M0)
#define IS_IRDA_WORD_LENGTH(LENGTH) (((LENGTH) == IRDA_WORDLENGTH_7B) || \
((LENGTH) == IRDA_WORDLENGTH_8B) || \
((LENGTH) == IRDA_WORDLENGTH_9B))
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported macros -----------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup IRDAEx_Extended_Exported_Macros IRDAEx Exported Macros
/* Private macros ------------------------------------------------------------*/
/** @defgroup IRDAEx_Private_Macros IRDAEx Private Macros
* @{
*/
/** @brief Reports the IRDA clock source.
* @param __HANDLE__: specifies the UART Handle
* @param __CLOCKSOURCE__ : output variable
/** @brief Report the IRDA clock source.
* @param __HANDLE__: specifies the IRDA Handle.
* @param __CLOCKSOURCE__: output variable.
* @retval IRDA clocking source, written in __CLOCKSOURCE__.
*/
#if defined (STM32L031xx) || defined (STM32L041xx) || defined (STM32L011xx) || defined (STM32L021xx)
@ -108,6 +88,7 @@
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
@ -128,6 +109,7 @@
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
@ -154,10 +136,11 @@
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if((__HANDLE__)->Instance == USART2) \
else if((__HANDLE__)->Instance == USART2) \
{ \
switch(__HAL_RCC_GET_USART2_SOURCE()) \
{ \
@ -174,6 +157,7 @@
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
@ -194,71 +178,27 @@
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
} while(0)
#endif /* (STM32L031xx) || (STM32L041xx) || (STM32L011xx) || (STM32L021xx) */
/** @brief Reports the mask to apply to retrieve the received data
* according to the word length and to the parity bits activation.
* @param __HANDLE__: specifies the IRDA Handle
* @retval mask to apply to USART RDR register value.
*/
#define IRDA_MASK_COMPUTATION(__HANDLE__) \
do { \
if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_9B) \
{ \
if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
{ \
(__HANDLE__)->Mask = 0x01FFU ; \
} \
else \
{ \
(__HANDLE__)->Mask = 0x00FFU ; \
} \
} \
else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_8B) \
{ \
if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
{ \
(__HANDLE__)->Mask = 0x00FFU ; \
} \
else \
{ \
(__HANDLE__)->Mask = 0x007FU ; \
} \
} \
else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_7B) \
{ \
if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
{ \
(__HANDLE__)->Mask = 0x007FU ; \
} \
else \
{ \
(__HANDLE__)->Mask = 0x003FU ; \
} \
} \
} while(0)
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/* Initialization/de-initialization methods **********************************/
/* IO operation methods *******************************************************/
/* Peripheral Control methods ************************************************/
/* Peripheral State methods **************************************************/
/**
* @}
*/
*/
/**
* @}
*/
*/
#ifdef __cplusplus
}
#endif

366
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_iwdg.c
View File

@ -2,37 +2,41 @@
******************************************************************************
* @file stm32l0xx_hal_iwdg.c
* @author MCD Application Team
* @version V1.7.0
* @date 31-May-2016
* @brief IWDG HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Independent Watchdog (IWDG) peripheral:
* + Initialization and de-initialization functions
* + Initialization and Start functions
* + IO operation functions
* + Peripheral State functions
*
*
@verbatim
==============================================================================
##### IWDG Generic features #####
==============================================================================
[..]
[..]
(+) The IWDG can be started by either software or hardware (configurable
through option byte).
through option byte).
(+) The IWDG is clocked by its own dedicated Low-Speed clock (LSI) and
thus stays active even if the main clock fails.
Once the IWDG is started, the LSI is forced ON and cannot be disabled
(LSI cannot be disabled too), and the counter starts counting down from
the reset value of 0xFFF. When it reaches the end of count value (0x000)
a system reset is generated.
(+) The IWDG is clocked by Low-Speed clock (LSI) and thus stays active even
if the main clock fails.
(+) The IWDG counter should be refreshed at regular intervals, otherwise the
watchdog generates an MCU reset when the counter reaches 0.
(+) Once the IWDG is started, the LSI is forced ON and both can not be
disabled. The counter starts counting down from the reset value (0xFFF).
When it reaches the end of count value (0x000) a reset signal is
generated (IWDG reset).
(+) Whenever the key value 0x0000 AAAA is written in the IWDG_KR register,
the IWDG_RLR value is reloaded in the counter and the watchdog reset is
prevented.
(+) The IWDG is implemented in the VDD voltage domain that is still functional
in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY).
IWDGRST flag in RCC_CSR register can be used to inform when an IWDG
reset occurs.
in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY).
IWDGRST flag in RCC_CSR register can be used to inform when an IWDG
reset occurs.
(+) Debug mode : When the microcontroller enters debug mode (core halted),
the IWDG counter either continues to work normally or stops, depending
on DBG_IWDG_STOP configuration bit in DBG module, accessible through
__HAL_DBGMCU_FREEZE_IWDG() and __HAL_DBGMCU_UNFREEZE_IWDG() macros
[..] Min-max timeout value @32KHz (LSI): ~0.512ms / ~32.0s
The IWDG timeout may vary due to LSI frequency dispersion. STM32L0xx
@ -40,46 +44,37 @@
connected internally to TIM5 CH4 input capture). The measured value
can be used to have an IWDG timeout with an acceptable accuracy.
##### How to use this driver #####
==============================================================================
[..]
If Window option is disabled
(+) Use IWDG using HAL_IWDG_Init() function to :
(++) Enable write access to IWDG_PR, IWDG_RLR.
(++) Configure the IWDG prescaler, counter reload value.
This reload value will be loaded in the IWDG counter each time the counter
is reloaded, then the IWDG will start counting down from this value.
(+) Use IWDG using HAL_IWDG_Start() function to :
(++) Reload IWDG counter with value defined in the IWDG_RLR register.
(++) Start the IWDG, when the IWDG is used in software mode (no need
to enable the LSI, it will be enabled by hardware).
(+) Then the application program must refresh the IWDG counter at regular
intervals during normal operation to prevent an MCU reset, using
HAL_IWDG_Refresh() function.
[..]
if Window option is enabled:
(+) Use IWDG using HAL_IWDG_Start() function to enable IWDG downcounter
(+) Use IWDG using HAL_IWDG_Init() function to :
(++) Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
(++) Configure the IWDG prescaler, reload value and window value.
(+) Then the application program must refresh the IWDG counter at regular
intervals during normal operation to prevent an MCU reset, using
HAL_IWDG_Refresh() function.
[..]
(#) Use IWDG using HAL_IWDG_Init() function to :
(++) Enable instance by writing Start keyword in IWDG_KEY register. LSI
clock is forced ON and IWDG counter starts downcounting.
(++) Enable write access to configuration register: IWDG_PR, IWDG_RLR &
IWDG_WINR.
(++) Configure the IWDG prescaler and counter reload value. This reload
value will be loaded in the IWDG counter each time the watchdog is
reloaded, then the IWDG will start counting down from this value.
(++) Wait for status flags to be reset
(++) Depending on window parameter:
(+++) If Window Init parameter is same as Window register value,
nothing more is done but reload counter value in order to exit
function withy exact time base.
(+++) Else modify Window register. This will automatically reload
watchdog counter.
(#) Then the application program must refresh the IWDG counter at regular
intervals during normal operation to prevent an MCU reset, using
HAL_IWDG_Refresh() function.
*** IWDG HAL driver macros list ***
====================================
[..]
Below the list of most used macros in IWDG HAL driver.
Below the list of most used macros in IWDG HAL driver:
(+) __HAL_IWDG_START: Enable the IWDG peripheral
(+) __HAL_IWDG_RELOAD_COUNTER: Reloads IWDG counter with value defined in the reload register
(+) IWDG_ENABLE_WRITE_ACCESS : Enable write access to IWDG_PR and IWDG_RLR registers
(+) __HAL_IWDG_DISABLE_WRITE_ACCESS : Disable write access to IWDG_PR and IWDG_RLR registers
(+) __HAL_IWDG_GET_FLAG: Get the selected IWDG's flag status
(+) __HAL_IWDG_RELOAD_COUNTER: Reloads IWDG counter with value defined in
the reload register
@endverbatim
******************************************************************************
* @attention
@ -119,60 +114,62 @@
*/
#ifdef HAL_IWDG_MODULE_ENABLED
/** @addtogroup IWDG
* @brief IWDG HAL module driver.
* @{
*/
/** @addtogroup IWDG_Private
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/** @defgroup IWDG_Private_Defines IWDG Private Defines
* @{
*/
/* TimeOut value */
#define HAL_IWDG_DEFAULT_TIMEOUT (uint32_t)1000U
/* Local define used to check the SR status register */
#define IWDG_SR_FLAGS (IWDG_FLAG_PVU | IWDG_FLAG_RVU | IWDG_FLAG_WVU)
/* Status register need 5 RC LSI divided by prescaler clock to be updated. With
higher prescaler (256), and according to LSI variation, we need to wait at
least 6 cycles so 48 ms. */
#define HAL_IWDG_DEFAULT_TIMEOUT 48U
/**
* @}
*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup IWDG_Exported_Functions
* @{
*/
/** @addtogroup IWDG_Exported_Functions_Group1
* @brief Initialization and Configuration functions.
* @brief Initialization and Start functions.
*
@verbatim
===============================================================================
##### Initialization and de-initialization functions #####
##### Initialization and Start functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Initialize the IWDG according to the specified parameters
in the IWDG_InitTypeDef and create the associated handle
(+) Manage Window option
(+) Initialize the IWDG MSP
[..] This section provides functions allowing to:
(+) Initialize the IWDG according to the specified parameters in the
IWDG_InitTypeDef of associated handle.
(+) Manage Window option.
(+) Once initialization is performed in HAL_IWDG_Init function, Watchdog
is reloaded in order to exit function with correct time base.
@endverbatim
* @{
*/
/**
* @brief Initializes the IWDG according to the specified
* parameters in the IWDG_InitTypeDef and creates the associated handle.
*
* When using the 'window option', the function HAL_IWDG_Start() must
* be called before calling this function
*
* @param hiwdg : pointer to a IWDG_HandleTypeDef structure that contains
* the configuration information for the specified IWDG module.
* @brief Initialize the IWDG according to the specified parameters in the
* IWDG_InitTypeDef and start watchdog. Before exiting function,
* watchdog is refreshed in order to have correct time base.
* @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains
* the configuration information for the specified IWDG module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
{
uint32_t tickstart = 0U;
uint32_t tickstart;
/* Check the IWDG handle allocation */
if(hiwdg == NULL)
@ -181,229 +178,88 @@ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
}
/* Check the parameters */
assert_param(IS_IWDG_ALL_INSTANCE(hiwdg->Instance));
assert_param(IS_IWDG_PRESCALER(hiwdg->Init.Prescaler));
assert_param(IS_IWDG_RELOAD(hiwdg->Init.Reload));
assert_param(IS_IWDG_WINDOW(hiwdg->Init.Window));
/* Check pending flag, if previous update not done, return error */
if(((hiwdg->Instance->SR) & IWDG_SR_FLAGS) != 0U)
{
return HAL_ERROR;
}
/* Enable IWDG. LSI is turned on automaticaly */
__HAL_IWDG_START(hiwdg);
if(hiwdg->State == HAL_IWDG_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hiwdg->Lock = HAL_UNLOCKED;
/* Init the low level hardware */
HAL_IWDG_MspInit(hiwdg);
}
/* Change IWDG peripheral state */
hiwdg->State = HAL_IWDG_STATE_BUSY;
/* Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers */
/* by writing 0x5555 in KR */
/* Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers by writing
0x5555 in KR */
IWDG_ENABLE_WRITE_ACCESS(hiwdg);
/* Write to IWDG registers the IWDG_Prescaler & IWDG_Reload values to work with */
MODIFY_REG(hiwdg->Instance->PR, (uint32_t)IWDG_PR_PR, hiwdg->Init.Prescaler);
MODIFY_REG(hiwdg->Instance->RLR, (uint32_t)IWDG_RLR_RL, hiwdg->Init.Reload);
/* Write to IWDG registers the Prescaler & Reload values to work with */
hiwdg->Instance->PR = hiwdg->Init.Prescaler;
hiwdg->Instance->RLR = hiwdg->Init.Reload;
/* check if window option is enabled */
if (((hiwdg->Init.Window) != IWDG_WINDOW_DISABLE) || ((hiwdg->Instance->WINR) != IWDG_WINDOW_DISABLE))
/* Check pending flag, if previous update not done, return timeout */
tickstart = HAL_GetTick();
/* Wait for register to be updated */
while(hiwdg->Instance->SR != RESET)
{
tickstart = HAL_GetTick();
/* Wait for register to be updated */
while (((hiwdg->Instance->SR) & IWDG_SR_FLAGS) != 0U)
{
if((HAL_GetTick()-tickstart) > HAL_IWDG_DEFAULT_TIMEOUT)
{
/* Set IWDG state */
hiwdg->State = HAL_IWDG_STATE_TIMEOUT;
return HAL_TIMEOUT;
}
if((HAL_GetTick() - tickstart ) > HAL_IWDG_DEFAULT_TIMEOUT)
{
return HAL_TIMEOUT;
}
/* Write to IWDG WINR the IWDG_Window value to compare with */
MODIFY_REG(hiwdg->Instance->WINR, (uint32_t)IWDG_WINR_WIN, hiwdg->Init.Window);
}
/* Change IWDG peripheral state */
hiwdg->State = HAL_IWDG_STATE_READY;
/* If window parameter is different than current value, modify window
register */
if(hiwdg->Instance->WINR != hiwdg->Init.Window)
{
/* Write to IWDG WINR the IWDG_Window value to compare with. In any case,
even if window feature is disabled, Watchdog will be reloaded by writing
windows register */
hiwdg->Instance->WINR = hiwdg->Init.Window;
}
else
{
/* Reload IWDG counter with value defined in the reload register */
__HAL_IWDG_RELOAD_COUNTER(hiwdg);
}
/* Return function status */
return HAL_OK;
}
/**
* @brief Initializes the IWDG MSP.
* @param hiwdg: pointer to a IWDG_HandleTypeDef structure that contains
* the configuration information for the specified IWDG module.
* @retval None
*/
__weak void HAL_IWDG_MspInit(IWDG_HandleTypeDef *hiwdg)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hiwdg);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_IWDG_MspInit could be implemented in the user file
*/
}
/**
* @}
*/
/** @addtogroup IWDG_Exported_Functions_Group2
* @brief IO operation functions
* @brief IO operation functions
*
@verbatim
===============================================================================
##### IO operation functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Start the IWDG.
[..] This section provides functions allowing to:
(+) Refresh the IWDG.
@endverbatim
* @{
*/
/**
* @brief Starts the IWDG.
* @param hiwdg : pointer to a IWDG_HandleTypeDef structure that contains
* the configuration information for the specified IWDG module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IWDG_Start(IWDG_HandleTypeDef *hiwdg)
{
uint32_t tickstart = 0U;
/* Process locked */
__HAL_LOCK(hiwdg);
/* Change IWDG peripheral state */
hiwdg->State = HAL_IWDG_STATE_BUSY;
/* Enable the IWDG peripheral */
__HAL_IWDG_START(hiwdg);
/* Reload IWDG counter with value defined in the RLR register */
if ((hiwdg->Init.Window) == IWDG_WINDOW_DISABLE)
{
__HAL_IWDG_RELOAD_COUNTER(hiwdg);
}
tickstart = HAL_GetTick();
/* Wait until PVU, RVU, WVU flag are RESET */
while (((hiwdg->Instance->SR) & IWDG_SR_FLAGS) != 0U)
{
if((HAL_GetTick()-tickstart) > HAL_IWDG_DEFAULT_TIMEOUT)
{
/* Set IWDG state */
hiwdg->State = HAL_IWDG_STATE_TIMEOUT;
/* Process unlocked */
__HAL_UNLOCK(hiwdg);
return HAL_TIMEOUT;
}
}
/* Change IWDG peripheral state */
hiwdg->State = HAL_IWDG_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hiwdg);
/* Return function status */
return HAL_OK;
}
/**
* @brief Refreshes the IWDG.
* @param hiwdg : pointer to a IWDG_HandleTypeDef structure that contains
* the configuration information for the specified IWDG module.
* @brief Refresh the IWDG.
* @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains
* the configuration information for the specified IWDG module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg)
{
uint32_t tickstart = 0U;
/* Process Locked */
__HAL_LOCK(hiwdg);
/* Change IWDG peripheral state */
hiwdg->State = HAL_IWDG_STATE_BUSY;
tickstart = HAL_GetTick();
/* Wait until RVU flag is RESET */
while(__HAL_IWDG_GET_FLAG(hiwdg, IWDG_FLAG_RVU) != RESET)
{
if((HAL_GetTick()-tickstart) > HAL_IWDG_DEFAULT_TIMEOUT)
{
/* Set IWDG state */
hiwdg->State = HAL_IWDG_STATE_TIMEOUT;
/* Process unlocked */
__HAL_UNLOCK(hiwdg);
return HAL_TIMEOUT;
}
}
/* Reload IWDG counter with value defined in the reload register */
__HAL_IWDG_RELOAD_COUNTER(hiwdg);
/* Change IWDG peripheral state */
hiwdg->State = HAL_IWDG_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hiwdg);
/* Return function status */
return HAL_OK;
}
/**
* @}
*/
/** @addtogroup IWDG_Exported_Functions_Group3
* @brief Peripheral State functions.
*
@verbatim
===============================================================================
##### Peripheral State functions #####
===============================================================================
[..]
This subsection permits to get in run-time the status of the peripheral
and the data flow.
@endverbatim
* @{
*/
/**
* @brief Returns the IWDG state.
* @param hiwdg : pointer to a IWDG_HandleTypeDef structure that contains
* the configuration information for the specified IWDG module.
* @retval HAL state
*/
HAL_IWDG_StateTypeDef HAL_IWDG_GetState(IWDG_HandleTypeDef *hiwdg)
{
return hiwdg->State;
}
/**
* @}
*/
/**
* @}
*/
@ -413,10 +269,12 @@ HAL_IWDG_StateTypeDef HAL_IWDG_GetState(IWDG_HandleTypeDef *hiwdg)
*/
#endif /* HAL_IWDG_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

231
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_iwdg.h
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32l0xx_hal_iwdg.h
* @author MCD Application Team
* @version V1.7.0
* @date 31-May-2016
* @brief Header file of IWDG HAL module.
******************************************************************************
* @attention
@ -55,32 +53,10 @@
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup IWDG_Exported_Types IWDG Exported Types
* @{
*/
/** @defgroup IWDG_State IWDG state definition
* @{
*/
/**
* @brief IWDG HAL State Structure definition
*/
typedef enum
{
HAL_IWDG_STATE_RESET = 0x00U, /*!< IWDG not yet initialized or disabled */
HAL_IWDG_STATE_READY = 0x01U, /*!< IWDG initialized and ready for use */
HAL_IWDG_STATE_BUSY = 0x02U, /*!< IWDG internal process is ongoing */
HAL_IWDG_STATE_TIMEOUT = 0x03U, /*!< IWDG timeout state */
HAL_IWDG_STATE_ERROR = 0x04U /*!< IWDG error state */
}HAL_IWDG_StateTypeDef;
/**
* @}
*/
/** @defgroup IWDG_Init IWDG init configuration structure
* @{
*/
/**
* @brief IWDG Init structure definition
*/
@ -96,13 +72,7 @@ typedef struct
This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */
} IWDG_InitTypeDef;
/**
* @}
*/
/** @defgroup IWDG_handle IWDG handler
* @{
*/
/**
* @brief IWDG Handle Structure definition
*/
@ -112,88 +82,35 @@ typedef struct
IWDG_InitTypeDef Init; /*!< IWDG required parameters */
HAL_LockTypeDef Lock; /*!< IWDG Locking object */
__IO HAL_IWDG_StateTypeDef State; /*!< IWDG communication state */
}IWDG_HandleTypeDef;
/**
* @}
*/
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup IWDG_Exported_Constants IWDG Exported Constants
* @{
*/
/** @defgroup IWDG_Registers_Key IWDG key
* @brief IWDG registers bit mask
* @{
*/
/* --- KR Register ---*/
/* KR register bit mask */
#define IWDG_KEY_RELOAD ((uint32_t)0xAAAAU) /*!< IWDG Reload Counter Enable */
#define IWDG_KEY_ENABLE ((uint32_t)0xCCCCU) /*!< IWDG Peripheral Enable */
#define IWDG_KEY_WRITE_ACCESS_ENABLE ((uint32_t)0x5555U) /*!< IWDG KR Write Access Enable */
#define IWDG_KEY_WRITE_ACCESS_DISABLE ((uint32_t)0x0000U) /*!< IWDG KR Write Access Disable */
/**
* @}
*/
#define IS_IWDG_KR(__KR__) (((__KR__) == IWDG_KEY_RELOAD) || \
((__KR__) == IWDG_KEY_ENABLE))|| \
((__KR__) == IWDG_KEY_WRITE_ACCESS_ENABLE)) || \
((__KR__) == IWDG_KEY_WRITE_ACCESS_DISABLE))
/** @defgroup IWDG_Flag_definition IWDG Flag definition
* @{
*/
#define IWDG_FLAG_PVU ((uint32_t)IWDG_SR_PVU) /*!< Watchdog counter prescaler value update flag */
#define IWDG_FLAG_RVU ((uint32_t)IWDG_SR_RVU) /*!< Watchdog counter reload value update flag */
#define IWDG_FLAG_WVU ((uint32_t)IWDG_SR_WVU) /*!< Watchdog counter window value update Flag */
/**
* @}
*/
/** @defgroup IWDG_Prescaler IWDG Prescaler
* @{
*/
#define IWDG_PRESCALER_4 ((uint8_t)0x00U) /*!< IWDG prescaler set to 4 */
#define IWDG_PRESCALER_8 ((uint8_t)(IWDG_PR_PR_0)) /*!< IWDG prescaler set to 8 */
#define IWDG_PRESCALER_16 ((uint8_t)(IWDG_PR_PR_1)) /*!< IWDG prescaler set to 16 */
#define IWDG_PRESCALER_32 ((uint8_t)(IWDG_PR_PR_1 | IWDG_PR_PR_0)) /*!< IWDG prescaler set to 32 */
#define IWDG_PRESCALER_64 ((uint8_t)(IWDG_PR_PR_2)) /*!< IWDG prescaler set to 64 */
#define IWDG_PRESCALER_128 ((uint8_t)(IWDG_PR_PR_2 | IWDG_PR_PR_0)) /*!< IWDG prescaler set to 128 */
#define IWDG_PRESCALER_256 ((uint8_t)(IWDG_PR_PR_2 | IWDG_PR_PR_1)) /*!< IWDG prescaler set to 256 */
#define IWDG_PRESCALER_4 0x00000000U /*!< IWDG prescaler set to 4 */
#define IWDG_PRESCALER_8 IWDG_PR_PR_0 /*!< IWDG prescaler set to 8 */
#define IWDG_PRESCALER_16 IWDG_PR_PR_1 /*!< IWDG prescaler set to 16 */
#define IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 32 */
#define IWDG_PRESCALER_64 IWDG_PR_PR_2 /*!< IWDG prescaler set to 64 */
#define IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 128 */
#define IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1) /*!< IWDG prescaler set to 256 */
/**
* @}
*/
#define IS_IWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == IWDG_PRESCALER_4) || \
((__PRESCALER__) == IWDG_PRESCALER_8) || \
((__PRESCALER__) == IWDG_PRESCALER_16) || \
((__PRESCALER__) == IWDG_PRESCALER_32) || \
((__PRESCALER__) == IWDG_PRESCALER_64) || \
((__PRESCALER__) == IWDG_PRESCALER_128)|| \
((__PRESCALER__) == IWDG_PRESCALER_256))
/* Check for reload value */
#define IS_IWDG_RELOAD(__RELOAD__) ((__RELOAD__) <= 0xFFFU)
/* Check for window value */
#define IS_IWDG_WINDOW(__VALUE__) ((__VALUE__) <= 0xFFFU)
/** @defgroup IWDG_Disable IWDG Disable
/** @defgroup IWDG_Window_option IWDG Window option
* @{
*/
#define IWDG_WINDOW_DISABLE 0xFFFU
#define IWDG_WINDOW_DISABLE IWDG_WINR_WIN
/**
* @}
*/
@ -201,106 +118,120 @@ typedef struct
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup IWDG_Exported_Macro IWDG Exported Macros
/* Exported macros -----------------------------------------------------------*/
/** @defgroup IWDG_Exported_Macros IWDG Exported Macros
* @{
*/
/** @brief Reset IWDG handle state
* @param __HANDLE__ : IWDG handle
/**
* @brief Enable the IWDG peripheral.
* @param __HANDLE__ IWDG handle
* @retval None
*/
#define __HAL_IWDG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_IWDG_STATE_RESET)
#define __HAL_IWDG_START(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE)
/**
* @brief Enables the IWDG peripheral.
* @param __HANDLE__ : IWDG handle
* @brief Reload IWDG counter with value defined in the reload register
* (write access to IWDG_PR, IWDG_RLR & IWDG_WINR registers disabled).
* @param __HANDLE__ IWDG handle
* @retval None
*/
#define __HAL_IWDG_START(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE)
/**
* @brief Reloads IWDG counter with value defined in the reload register
* (write access to IWDG_PR and IWDG_RLR registers disabled).
* @param __HANDLE__ : IWDG handle
* @retval None
*/
#define __HAL_IWDG_RELOAD_COUNTER(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD)
/**
* @brief Enables write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
* @param __HANDLE__ : IWDG handle
* @retval None
*/
#define IWDG_ENABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE)
/**
* @brief Disables write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
* @param __HANDLE__ : IWDG handle
* @retval None
*/
#define IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_DISABLE)
/**
* @brief Gets the selected IWDG's flag status.
* @param __HANDLE__ : IWDG handle
* @param __FLAG__ : specifies the flag to check.
* This parameter can be one of the following values:
* @arg IWDG_FLAG_PVU: Watchdog counter reload value update flag
* @arg IWDG_FLAG_RVU: Watchdog counter prescaler value flag
* @arg IWDG_FLAG_WVU: Watchdog counter window value flag
* @retval The new state of __FLAG__ (TRUE or FALSE) .
*/
#define __HAL_IWDG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
#define __HAL_IWDG_RELOAD_COUNTER(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD)
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup IWDG_Exported_Functions IWDG Exported Functions
/** @defgroup IWDG_Exported_Functions IWDG Exported Functions
* @{
*/
/** @defgroup IWDG_Exported_Functions_Group1 Initialization/de-initialization functions
/** @defgroup IWDG_Exported_Functions_Group1 Initialization and Start functions
* @{
*/
/* Initialization/Start functions ********************************************/
HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg);
void HAL_IWDG_MspInit(IWDG_HandleTypeDef *hiwdg);
/**
* @}
*/
/** @defgroup IWDG_Exported_Functions_Group2 I/O operation functions
/** @defgroup IWDG_Exported_Functions_Group2 IO operation functions
* @{
*/
HAL_StatusTypeDef HAL_IWDG_Start(IWDG_HandleTypeDef *hiwdg);
/* I/O operation functions ****************************************************/
HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg);
/**
* @}
*/
/** @defgroup IWDG_Exported_Functions_Group3 Peripheral State functions
/**
* @}
*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup IWDG_Private_Constants IWDG Private Constants
* @{
*/
HAL_IWDG_StateTypeDef HAL_IWDG_GetState(IWDG_HandleTypeDef *hiwdg);
/**
* @}
* @brief IWDG Key Register BitMask
*/
#define IWDG_KEY_RELOAD 0x0000AAAAU /*!< IWDG Reload Counter Enable */
#define IWDG_KEY_ENABLE 0x0000CCCCU /*!< IWDG Peripheral Enable */
#define IWDG_KEY_WRITE_ACCESS_ENABLE 0x00005555U /*!< IWDG KR Write Access Enable */
#define IWDG_KEY_WRITE_ACCESS_DISABLE 0x00000000U /*!< IWDG KR Write Access Disable */
/**
* @}
*/
/* Define the private group ***********************************/
/**************************************************************/
/** @defgroup IWDG_Private IWDG Private
/* Private macros ------------------------------------------------------------*/
/** @defgroup IWDG_Private_Macros IWDG Private Macros
* @{
*/
/**
* @}
* @brief Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
* @param __HANDLE__ IWDG handle
* @retval None
*/
/**************************************************************/
#define IWDG_ENABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE)
/**
* @brief Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
* @param __HANDLE__ IWDG handle
* @retval None
*/
#define IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_DISABLE)
/**
* @brief Check IWDG prescaler value.
* @param __PRESCALER__ IWDG prescaler value
* @retval None
*/
#define IS_IWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == IWDG_PRESCALER_4) || \
((__PRESCALER__) == IWDG_PRESCALER_8) || \
((__PRESCALER__) == IWDG_PRESCALER_16) || \
((__PRESCALER__) == IWDG_PRESCALER_32) || \
((__PRESCALER__) == IWDG_PRESCALER_64) || \
((__PRESCALER__) == IWDG_PRESCALER_128)|| \
((__PRESCALER__) == IWDG_PRESCALER_256))
/**
* @brief Check IWDG reload value.
* @param __RELOAD__ IWDG reload value
* @retval None
*/
#define IS_IWDG_RELOAD(__RELOAD__) ((__RELOAD__) <= IWDG_RLR_RL)
/**
* @brief Check IWDG window value.
* @param __WINDOW__ IWDG window value
* @retval None
*/
#define IS_IWDG_WINDOW(__WINDOW__) ((__WINDOW__) <= IWDG_WINR_WIN)
/**
* @}
@ -310,6 +241,11 @@ HAL_IWDG_StateTypeDef HAL_IWDG_GetState(IWDG_HandleTypeDef *hiwdg);
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
@ -317,4 +253,3 @@ HAL_IWDG_StateTypeDef HAL_IWDG_GetState(IWDG_HandleTypeDef *hiwdg);
#endif /* __STM32L0xx_HAL_IWDG_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

2
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_lcd.c
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32l0xx_hal_lcd.c
* @author MCD Application Team
* @version V1.7.0
* @date 31-May-2016
* @brief LCD Controller HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the LCD Controller (LCD) peripheral:

11
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_lcd.h
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32l0xx_hal_lcd.h
* @author MCD Application Team
* @version V1.7.0
* @date 31-May-2016
* @brief Header file of LCD Controller HAL module.
******************************************************************************
* @attention
@ -35,7 +33,6 @@
******************************************************************************
*/
#if defined (STM32L053xx) || defined (STM32L063xx) || defined (STM32L073xx) || defined (STM32L083xx)
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32L0xx_HAL_LCD_H
@ -45,6 +42,7 @@
extern "C" {
#endif
#if defined (STM32L053xx) || defined (STM32L063xx) || defined (STM32L073xx) || defined (STM32L083xx)
/* Includes ------------------------------------------------------------------*/
#include "stm32l0xx_hal_def.h"
@ -434,7 +432,7 @@ typedef struct
/**
* @}
*/
/** @defgroup LCD_BUFEN LCD Voltage output buffer enable
* @{
*/
@ -794,14 +792,13 @@ HAL_StatusTypeDef LCD_WaitForSynchro(LCD_HandleTypeDef *hlcd);
* @}
*/
#endif /* STM32L053xx || STM32L063xx || STM32L073xx || STM32L083xx */
#ifdef __cplusplus
}
#endif
#endif /* __STM32L0xx_HAL_LCD_H */
#endif /* STM32L053xx || STM32L063xx || STM32L073xx || STM32L083xx */
/******************* (C) COPYRIGHT 2016 STMicroelectronics *****END OF FILE****/

2
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_lptim.c
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32l0xx_hal_lptim.c
* @author MCD Application Team
* @version V1.7.0
* @date 31-May-2016
* @brief LPTIM HAL module driver.
*
* This file provides firmware functions to manage the following

4
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_lptim.h
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32l0xx_hal_lptim.h
* @author MCD Application Team
* @version V1.7.0
* @date 31-May-2016
* @brief Header file of LPTIM HAL module.
******************************************************************************
* @attention
@ -113,7 +111,7 @@ typedef struct
typedef struct
{
uint32_t Source; /*!< Selects the Trigger source.
This parameter can be a value of @ref LPTIMEx_Trigger_Source */
This parameter can be a value of @ref LPTIM_Trigger_Source */
uint32_t ActiveEdge; /*!< Selects the Trigger active edge.
Note: This parameter is used only when an external trigger is used.

4
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_lptim_ex.h
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32l0xx_hal_lptim_ex.h
* @author MCD Application Team
* @version V1.7.0
* @date 31-May-2016
* @brief Header file of LPTIM Extended HAL module.
******************************************************************************
* @attention
@ -61,7 +59,7 @@
*/
/** @defgroup LPTIMEx_Trigger_Source Trigger source
/** @defgroup LPTIM_Trigger_Source Trigger source
* @{
*/
#define LPTIM_TRIGSOURCE_SOFTWARE ((uint32_t)0x0000FFFFU)

114
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_pcd.c
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32l0xx_hal_pcd.c
* @author MCD Application Team
* @version V1.7.0
* @date 31-May-2016
* @brief PCD HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the USB Peripheral Controller:
@ -190,17 +188,28 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
/*Set Btable Adress*/
hpcd->Instance->BTABLE = BTABLE_ADDRESS;
/*set wInterrupt_Mask global variable*/
wInterrupt_Mask = USB_CNTR_CTRM | USB_CNTR_WKUPM | USB_CNTR_SUSPM | USB_CNTR_ERRM \
| USB_CNTR_ESOFM | USB_CNTR_RESETM;
/*set wInterrupt_Mask global variable*/
wInterrupt_Mask = USB_CNTR_CTRM | USB_CNTR_WKUPM | USB_CNTR_SUSPM | USB_CNTR_ERRM \
| USB_CNTR_SOFM | USB_CNTR_ESOFM | USB_CNTR_RESETM;
/*Set interrupt mask*/
hpcd->Instance->CNTR = wInterrupt_Mask;
hpcd->Instance->CNTR = wInterrupt_Mask;
hpcd->USB_Address = 0U;
hpcd->State= HAL_PCD_STATE_READY;
hpcd->USB_Address = 0U;
hpcd->State= HAL_PCD_STATE_READY;
/* Activate LPM */
if (hpcd->Init.lpm_enable ==1)
{
HAL_PCDEx_ActivateLPM(hpcd);
}
/* Activate Battery charging */
if (hpcd->Init.battery_charging_enable ==1)
{
HAL_PCDEx_ActivateBCD(hpcd);
}
return HAL_OK;
}
@ -354,16 +363,30 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
/*set wInterrupt_Mask global variable*/
wInterrupt_Mask = USB_CNTR_CTRM | USB_CNTR_WKUPM | USB_CNTR_SUSPM | USB_CNTR_ERRM \
| USB_CNTR_ESOFM | USB_CNTR_RESETM;
| USB_CNTR_SOFM | USB_CNTR_ESOFM | USB_CNTR_RESETM;
/*Set interrupt mask*/
hpcd->Instance->CNTR = wInterrupt_Mask;
/* enable L1REQ interrupt */
if (hpcd->Init.lpm_enable ==1)
{
wInterrupt_Mask |= USB_CNTR_L1REQM;
/* Enable LPM support and enable ACK answer to LPM request*/
USB_TypeDef *USBx = hpcd->Instance;
hpcd->lpm_active = ENABLE;
hpcd->LPM_State = LPM_L0;
USBx->LPMCSR |= (USB_LPMCSR_LMPEN);
USBx->LPMCSR |= (USB_LPMCSR_LPMACK);
}
HAL_PCD_ResumeCallback(hpcd);
__HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_WKUP);
}
if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_SUSP))
{
/* clear of the ISTR bit must be done after setting of CNTR_FSUSP */
@ -378,6 +401,26 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
HAL_PCD_SuspendCallback(hpcd);
}
}
/* Handle LPM Interrupt */
if(__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_L1REQ))
{
__HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_L1REQ);
if( hpcd->LPM_State == LPM_L0)
{
/* Force suspend and low-power mode before going to L1 state*/
hpcd->Instance->CNTR |= USB_CNTR_LPMODE;
hpcd->Instance->CNTR |= USB_CNTR_FSUSP;
hpcd->LPM_State = LPM_L1;
hpcd->BESL = (hpcd->Instance->LPMCSR & USB_LPMCSR_BESL) >>2 ;
HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L1_ACTIVE);
}
else
{
HAL_PCD_SuspendCallback(hpcd);
}
}
if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_SOF))
{
@ -837,9 +880,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, u
ep->xfer_count = 0U;
ep->is_in = 0U;
ep->num = ep_addr & 0x7FU;
__HAL_LOCK(hpcd);
/* Multi packet transfer*/
if (ep->xfer_len > ep->maxpacket)
{
@ -865,9 +906,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, u
}
PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_VALID);
__HAL_UNLOCK(hpcd);
return HAL_OK;
}
@ -902,9 +941,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
ep->xfer_count = 0U;
ep->is_in = 1U;
ep->num = ep_addr & 0x7FU;
__HAL_LOCK(hpcd);
/*Multi packet transfer*/
if (ep->xfer_len > ep->maxpacket)
{
@ -944,8 +981,6 @@ HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_VALID);
__HAL_UNLOCK(hpcd);
return HAL_OK;
}
@ -1050,11 +1085,20 @@ HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
* @brief HAL_PCD_ActivateRemoteWakeup : active remote wakeup signalling
* @param hpcd: PCD handle
* @retval status
*/
*/
HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)
{
hpcd->Instance->CNTR |= USB_CNTR_RESUME;
return HAL_OK;
if (hpcd->Init.lpm_enable ==1)
{
/* Apply L1 Resume */
hpcd->Instance->CNTR |= USB_CNTR_L1RESUME;
}
else
{
/* Apply L2 Resume */
hpcd->Instance->CNTR |= USB_CNTR_RESUME;
}
return (HAL_OK);
}
/**
@ -1064,11 +1108,19 @@ HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)
*/
HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)
{
hpcd->Instance->CNTR &= ((uint16_t) ~(USB_CNTR_RESUME));
return HAL_OK;
if (hpcd->Init.lpm_enable ==1)
{
/* Release L1 Resume */
hpcd->Instance->CNTR &= ~ USB_CNTR_L1RESUME;
}
else
{
/* Release L2 Resume */
hpcd->Instance->CNTR &= ~ USB_CNTR_RESUME;
}
return (HAL_OK);
}
/**
* @}
*/

20
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_pcd.h
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32l0xx_hal_pcd.h
* @author MCD Application Team
* @version V1.7.0
* @date 31-May-2016
* @brief Header file of PCD HAL module.
******************************************************************************
* @attention
@ -74,6 +72,15 @@ typedef enum
HAL_PCD_STATE_TIMEOUT = 0x04U
} PCD_StateTypeDef;
/* Device LPM suspend state */
typedef enum
{
LPM_L0 = 0x00, /* on */
LPM_L1 = 0x01, /* LPM L1 sleep */
LPM_L2 = 0x02, /* suspend */
LPM_L3 = 0x03, /* off */
}PCD_LPM_StateTypeDef;
typedef enum
{
/* double buffered endpoint direction */
@ -179,6 +186,15 @@ typedef struct
HAL_LockTypeDef Lock; /*!< PCD peripheral status */
__IO PCD_StateTypeDef State; /*!< PCD communication state */
uint32_t Setup[12]; /*!< Setup packet buffer */
PCD_LPM_StateTypeDef LPM_State; /*!< LPM State */
uint32_t BESL;
uint32_t lpm_active; /*!< Enable or disable the Link Power Management .
This parameter can be set to ENABLE or DISABLE */
uint32_t battery_charging_active; /*!< Enable or disable Battery charging.
This parameter can be set to ENABLE or DISABLE */
void *pData; /*!< Pointer to upper stack Handler */
} PCD_HandleTypeDef;

169
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_pcd_ex.c
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32l0xx_hal_pcd_ex.c
* @author MCD Application Team
* @version V1.7.0
* @date 31-May-2016
* @brief Extended PCD HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the USB Peripheral Controller:
@ -132,6 +130,173 @@ HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd,
return HAL_OK;
}
/**
* @brief Activate BatteryCharging feature.
* @param hpcd: PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd)
{
USB_TypeDef *USBx = hpcd->Instance;
hpcd->battery_charging_active = ENABLE;
USBx->BCDR |= (USB_BCDR_BCDEN);
/* Enable DCD : Data Contact Detect */
USBx->BCDR |= (USB_BCDR_DCDEN);
return HAL_OK;
}
/**
* @brief Deactivate BatteryCharging feature.
* @param hpcd: PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd)
{
USB_TypeDef *USBx = hpcd->Instance;
hpcd->battery_charging_active = DISABLE;
USBx->BCDR &= ~(USB_BCDR_BCDEN);
return HAL_OK;
}
/**
* @brief Handle BatteryCharging Process.
* @param hpcd: PCD handle
* @retval HAL status
*/
void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd)
{
USB_TypeDef *USBx = hpcd->Instance;
uint32_t tickstart = HAL_GetTick();
/* Wait Detect flag or a timeout is happen*/
while ((USBx->BCDR & USB_BCDR_DCDET) == 0)
{
/* Check for the Timeout */
if((HAL_GetTick() - tickstart ) > 1000)
{
HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_ERROR);
return;
}
}
HAL_Delay(300);
/* Data Pin Contact ? Check Detect flag */
if (USBx->BCDR & USB_BCDR_DCDET)
{
HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CONTACT_DETECTION);
}
/* Primary detection: checks if connected to Standard Downstream Port
(without charging capability) */
USBx->BCDR &= ~(USB_BCDR_DCDEN);
USBx->BCDR |= (USB_BCDR_PDEN);
HAL_Delay(300);
/* If Charger detect ? */
if (USBx->BCDR & USB_BCDR_PDET)
{
/* Start secondary detection to check connection to Charging Downstream
Port or Dedicated Charging Port */
USBx->BCDR &= ~(USB_BCDR_PDEN);
USBx->BCDR |= (USB_BCDR_SDEN);
HAL_Delay(300);
/* If CDP ? */
if (USBx->BCDR & USB_BCDR_SDET)
{
/* Dedicated Downstream Port DCP */
HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DEDICATED_CHARGING_PORT);
}
else
{
/* Charging Downstream Port CDP */
HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT);
}
}
else
{
/* Standard Downstream Port */
HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_STD_DOWNSTREAM_PORT);
}
/* Battery Charging capability discovery finished
Start Enumeration*/
HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DISCOVERY_COMPLETED);
}
/**
* @brief Activate LPM feature.
* @param hpcd: PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd)
{
USB_TypeDef *USBx = hpcd->Instance;
hpcd->lpm_active = ENABLE;
hpcd->LPM_State = LPM_L0;
USBx->LPMCSR |= (USB_LPMCSR_LMPEN);
USBx->LPMCSR |= (USB_LPMCSR_LPMACK);
return HAL_OK;
}
/**
* @brief Deactivate LPM feature.
* @param hpcd: PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd)
{
USB_TypeDef *USBx = hpcd->Instance;
hpcd->lpm_active = DISABLE;
USBx->LPMCSR &= ~ (USB_LPMCSR_LMPEN);
USBx->LPMCSR &= ~ (USB_LPMCSR_LPMACK);
return HAL_OK;
}
/**
* @brief Send LPM message to user layer callback.
* @param hpcd: PCD handle
* @param msg: LPM message
* @retval HAL status
*/
__weak void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hpcd);
UNUSED(msg);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_PCDEx_LPM_Callback could be implemented in the user file
*/
}
/**
* @brief Send BatteryCharging message to user layer callback.
* @param hpcd: PCD handle
* @param msg: LPM message
* @retval HAL status
*/
__weak void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hpcd);
UNUSED(msg);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_PCDEx_BCD_Callback could be implemented in the user file
*/
}
/**
* @}
*/

31
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_pcd_ex.h
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32l0xx_hal_pcd.h
* @author MCD Application Team
* @version V1.7.0
* @date 31-May-2016
* @brief Header file of PCD HAL module.
******************************************************************************
* @attention
@ -52,8 +50,27 @@
/** @defgroup PCDEx PCDEx
* @{
*/
*/
/* Exported types ------------------------------------------------------------*/
typedef enum
{
PCD_LPM_L0_ACTIVE = 0x00, /* on */
PCD_LPM_L1_ACTIVE = 0x01, /* LPM L1 sleep */
}PCD_LPM_MsgTypeDef;
typedef enum
{
PCD_BCD_ERROR = 0xFF,
PCD_BCD_CONTACT_DETECTION = 0xFE,
PCD_BCD_STD_DOWNSTREAM_PORT = 0xFD,
PCD_BCD_CHARGING_DOWNSTREAM_PORT = 0xFC,
PCD_BCD_DEDICATED_CHARGING_PORT = 0xFB,
PCD_BCD_DISCOVERY_COMPLETED = 0x00,
}PCD_BCD_MsgTypeDef;
/* Exported constants --------------------------------------------------------*/
/* Exported macros -----------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup PCDEx_Exported_Functions PCDEx Exported Functions
@ -67,6 +84,14 @@ HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd,
uint16_t ep_addr,
uint16_t ep_kind,
uint32_t pmaadress);
HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd);
void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd);
void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg);
void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg);
/**
* @}
*/

2
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_pwr.c
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@ -2,8 +2,6 @@
******************************************************************************
* @file stm32l0xx_hal_pwr.c
* @author MCD Application Team
* @version V1.7.0
* @date 31-May-2016
* @brief PWR HAL module driver.
*
* This file provides firmware functions to manage the following

2
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_pwr.h
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32l0xx_hal_pwr.h
* @author MCD Application Team
* @version V1.7.0
* @date 31-May-2016
* @brief Header file of PWR HAL module.
******************************************************************************
* @attention

12
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_pwr_ex.c
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32l0xx_hal_pwr_ex.c
* @author MCD Application Team
* @version V1.7.0
* @date 31-May-2016
* @brief Extended PWR HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Power Controller (PWR) peripheral:
@ -81,6 +79,16 @@
* @{
*/
/**
* @brief Return Voltage Scaling Range.
* @retval VOS bit field (PWR_REGULATOR_VOLTAGE_SCALE1, PWR_REGULATOR_VOLTAGE_SCALE2 or PWR_REGULATOR_VOLTAGE_SCALE3)
*/
uint32_t HAL_PWREx_GetVoltageRange(void)
{
return (PWR->CR & PWR_CR_VOS);
}
/**
* @brief Enables the Fast WakeUp from Ultra Low Power mode.
* @note This bit works in conjunction with ULP bit.

3
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_pwr_ex.h
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32l0xx_hal_pwr_ex.h
* @author MCD Application Team
* @version V1.7.0
* @date 31-May-2016
* @brief Header file of PWR HAL Extension module.
******************************************************************************
* @attention
@ -78,6 +76,7 @@
/** @defgroup PWREx_Exported_Functions PWREx Exported Functions
* @{
*/
uint32_t HAL_PWREx_GetVoltageRange(void);
void HAL_PWREx_EnableFastWakeUp(void);
void HAL_PWREx_DisableFastWakeUp(void);
void HAL_PWREx_EnableUltraLowPower(void);

1234
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_rcc.c
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1821
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_rcc.h
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830
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_rcc_ex.c
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2669
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_rcc_ex.h
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2
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_rng.c
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@ -2,8 +2,6 @@
******************************************************************************
* @file stm32l0xx_hal_rng.c
* @author MCD Application Team
* @version V1.7.0
* @date 31-May-2016
* @brief RNG HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Random Number Generator (RNG) peripheral:

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