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12389 Commits (908a05b2313e6d2113f02d0f574fefd06ed02cfd)

Author SHA1 Message Date
Jarno Komula 6289596f04 Fixed sw4stm32 exporter 2017-09-13 12:05:27 +03:00
Shrikant Tudavekar fec2346627 add ARMC6 in supported compiler 2017-09-12 15:31:50 -05:00
adbridge 32bd25e8df Fix include file for ARMCC 6, should use cmsis_armclang.h 2017-09-12 16:41:11 +01:00
Andres Amaya Garcia f928e7a707 mbedtls: Disable MD5, SHA1, SHA256 HW ACC for STM32F439xI 
STM32F439xI-family MD5, SHA1 and SHA256 hardware acceleration
occasionally produces incorrect output (#5079).

Don't enable MD5, SHA1 and SHA256 HW acceleration on STM32F439xI-family
targets by default until issue #5079 is fixed.
 2017-09-12 13:39:04 +01:00
Anna Bridge 5e437fe5ea Merge pull request #5073 from studavekar/fix-buuld-error-armc6 
use gcc assembly for arm 6
 2017-09-12 11:01:16 +01:00
Shrikant Tudavekar 1cb41e9715 use default macro for armcc 2017-09-12 01:00:45 -05:00
Martin Kojtal de6d2918b8 Merge pull request #4987 from andresag01/release-mbedtls-2.6.0 
Update mbed TLS to version 2.6.0
 2017-09-12 06:18:46 +01:00
Shrikant Tudavekar 45202df55e gaurd thumb instruction for amrc6 2017-09-11 20:09:43 -05:00
Jimmy Brisson 4b9856604d Merge pull request #4875 from deepikabhavnani/cm_23_support 
Initial support for Cortex M-23/M-33 devices.
 2017-09-11 18:37:55 -05:00
Anna Bridge 2955a0adc6 Merge pull request #5063 from 0xc0170/fix_lpticker_test 
Fixing lp ticker and sleep manager tests
 2017-09-11 22:28:52 +01:00
Jimmy Brisson 23aafbfe6c Optimize space usage on builds 
by not creating gigantic exception nonsense
 2017-09-11 14:45:21 -05:00
Jimmy Brisson 33113ae207 Correct unity math for ARMC6 
The assumed that isnan and isinf would be macros, but they are functions
in ARMC6.
 2017-09-11 13:20:33 -05:00
Jimmy Brisson 8a9d79bcbd Add ARMC6 to supported matrix 2017-09-11 13:20:33 -05:00
Jimmy Brisson d56c19f253 Detect test skips with armc6 2017-09-11 13:20:33 -05:00
Jimmy Brisson 41a6197208 Update mbed 2 discriminator 2017-09-11 13:20:33 -05:00
Jimmy Brisson 887d29372b Check for support in ARMC6 2017-09-11 13:20:33 -05:00
Jimmy Brisson d72f6dbfe4 Disable MULADDC assembly 
It's not supported in ARMC6
 2017-09-11 13:20:33 -05:00
Jimmy Brisson d3b33d75a4 Correct NRF SDK11 assembly 2017-09-11 13:20:33 -05:00
Jimmy Brisson 4f3f0cc9cc Make Realtek link 
There was some interesting stuff here.
 * ARMC6 treats assembly the same as GNU, but has a different startup
   function, so we branch the asm there
 * Incorrect discriminant, probably copied from other ports
 2017-09-11 13:20:33 -05:00
Jimmy Brisson 91afbce18a Correct Nuvoton compiler detection logic 2017-09-11 13:20:33 -05:00
Jimmy Brisson 75549754bc Compile source code for Maxim targets 
They don't link because of differences in the precompiled libraries
 2017-09-11 13:20:32 -05:00
Jimmy Brisson fb53eb65d4 Correct Silabs NVIC selection 
Again, the culprit was that the discriminant did not include armc6
 2017-09-11 13:20:32 -05:00
Jimmy Brisson 0b7a9033b5 Enable many STM devices with ARMC6 
Yet another incorrect arm vs gcc discriminant
 2017-09-11 13:20:32 -05:00
Jimmy Brisson b22a174c39 Correct semihosting check for ARMC6 2017-09-11 13:20:32 -05:00
Jimmy Brisson 4da4c1f5ce Correct compiler switching in Nordic code 2017-09-11 13:20:32 -05:00
Jimmy Brisson cd4fd86f1f Correct Freescale + NXP compiler detection macros 
Also removes duplication of common files
 2017-09-11 13:20:32 -05:00
Jimmy Brisson f4b7d8ba77 Avoid forcing preprocessing 
We avoid forcing preprocessing by not replacing the first line when it's
not a shebang (#!). Should work pretty darn well.
 2017-09-11 13:20:32 -05:00
Jimmy Brisson 06b00683c3 Genericify arm compiler exporter to versions 5 + 6 2017-09-11 13:20:32 -05:00
Jimmy Brisson e9d3166a5e Expose present get_compile_options API in Toolcahins 2017-09-11 13:20:32 -05:00
Jimmy Brisson 15a9a0382b Enable Compiling with ARMC6 across all targets 
remove duplicate sys.cpp
 2017-09-11 13:20:32 -05:00
Jimmy Brisson 922bf1b619 Update mbed OS to handle ARMC6 requirements 2017-09-11 13:20:32 -05:00
Jimmy Brisson 1fef5553b4 Parse deps the same for GCC_ARM and ARMC6 2017-09-11 13:17:54 -05:00
Jimmy Brisson 98b4768434 Initial toolchain class for ARMC6 
While ARMC6 does use the same linker (armlink) as ARM Compiler 5, it
is not compatible.

The reason for this incompatibility are twofold:
 * armlink may invoke the C preprocessor by adding a shebang
   (`#!`) to the top of their input files.
 * ARMC6 and ARMC5 differ in how you invoke the preprocessor:
   * ARMC5: `#! armcc -E`
   * ARMC6: `#! armclang -E`

This forces the tools to rewrite the shebang if it's wrong.

This does not yet handle dependencies properly
 2017-09-11 13:17:54 -05:00
Deepika ca1f24cc0e Add -mcmse flag for GCC and improved logic for cpu core 2017-09-11 11:49:28 -05:00
Deepika 9422c351e4 Initial RTX and tools support for Cortex M-23/M-33 devices 2017-09-11 11:43:26 -05:00
Deepika 65150b62b9 Added assert for malloc 2017-09-11 11:41:34 -05:00
Anna Bridge cab660d980 Merge pull request #4938 from deepikabhavnani/IAR_fixes 
Update IAR to version 8
 2017-09-11 17:28:38 +01:00
adbridge 6bd28ecb68 Remove string literal values and revert back to using CTX macro . 
The previous fix to replace CTX with string literals was the wrong
solution. All that was actually required was to insert a space before
the macro.
 2017-09-11 11:13:54 +01:00
Russ Butler cf8d6c49a7 Fix errors on NCS36510 after deep sleep 
Add NOPs after deep sleep to prevent unexpected behavior. It appears
that the first one or two instructions after deep sleep do not get
executed properly.

Note - This is a temporary workaround. For a more robust solution
the NCS36510 needs to investigate the root cause of this issue.
 2017-09-10 22:25:12 -05:00
Russ Butler f746fc5bac Allow lp_ticker test to coexist with TimerEvents 
The lp_ticker test overrides the default ticker handler for the
low power ticker. This stops all other low power TimerEvents in the
system, including the ones for tickless, from getting called. Because
of this devices with tickless enabled malfunction during this test.

This patch fixes this problem by passing all lp ticker events it did
not trigger on to the TimerEvent irq handler.
 2017-09-10 17:06:46 -05:00
Deepika 0132d31124 Fix IAR8 : user-defined literal operator not found 
Cellular example had build issues with IAR8, combination of define and string
as argument to send function resulted in above error. Typecasting to const char *
didn't help, hence replacing the define explicitly.
 2017-09-10 09:58:34 -05:00
Russ Butler acf428200f Turn off tickless for the NCS36510 
The NCS36510 is not suitable for tickless, since its LP ticker cannot
be scheduled fast enough. This is because it takes four 32KHz clock
cycles before these writes take effect - ~120us.
 2017-09-09 20:43:37 -05:00
Russ Butler 30450d40d6 Decrease error in Timeout test due to ISR latency 
Increase the Timeout period from 1ms to 10ms so interrupt latency has
1/10th the effect on the measurement. This prevents failures due to
interrupt latency causing a drift.
 2017-09-09 20:43:36 -05:00
Russ Butler d9aff6f0dd Prevent deeps sleep in regular sleep test case 
Lock deep sleep before calling sleep to prevent the device from
entering deep sleep mode.
 2017-09-09 20:43:35 -05:00
Martin Kojtal 78718910d3 Ticker: invoke _function only if attached 2017-09-09 20:42:57 -05:00
Martin Kojtal deb1febb8b sleep manager test: fix Thread stack size 
Decrease the default stack size as it's not needed for purposes of testing.
 2017-09-09 20:42:55 -05:00
Jimmy Brisson 3f2e986256 Merge pull request #5012 from LMESTM/issue5004_ticker_16b 
STM32_us_ticker_16b: keep code to cope with past event
 2017-09-09 12:09:25 -05:00
Jimmy Brisson e0bc631a0a Merge pull request #4991 from c1728p9/tickless 
Add tickless to some mbed-os devices
 2017-09-08 14:30:39 -05:00
Jimmy Brisson e5638b7272 Merge pull request #5055 from 0xc0170/fix_ssltravis 
Travis: fix the latest breakage - use group:
 2017-09-08 13:40:33 -05:00
Jimmy Brisson a108adf396 Merge pull request #4916 from JojoS62/add_MCUXpresso_exporter 
Add mcuxpresso exporter
 2017-09-08 09:44:25 -05:00