ohagendorf
883b2bc0ce
[STM32xxx] CoIDE exporter and gcc_arm
...
- CoIDE options: wrap main and linker option DiscradUnusedSection=1 was
missing in some targets
- CoIDE options: corrected flash loader config for Nucleo_F030 and
Nucleo_F072
- CoIDE options: corrected memory layout (not used per default but now
it is the same as in linker script)
- gcc linker script: changed the memory size from hex number e.g. 0x2000
to decimal 8K
2014-12-07 20:07:56 +01:00
Bogdan Marinescu
e1d38422ed
Merge branch 'newbuild_lib_rev92'
2014-11-27 13:56:11 +00:00
Martin Kojtal
8a3087825b
Merge pull request #744 from masaohamanaka/master
...
Targets: RZ_A1H - Fix RTOS build error (Cortex A)
2014-11-27 03:35:29 -08:00
Martin Kojtal
84b6398edd
Merge pull request #742 from GustavWi/iar_mbed
...
Targets: IAR Fixed NVIC table in ram for stm targets
2014-11-27 03:33:50 -08:00
Masao Hamanaka
cf9fc3c4ac
Add SD function
...
Add SD function and tests for RZ_A1H.
2014-11-27 17:12:57 +09:00
Martin Kojtal
1401e677dd
Merge pull request #743 from ohagendorf/linker_scripts
...
Targets: STM32F0, F3, F4, L053, L152 - GCC ARM linker script reorganisation
2014-11-26 23:42:34 -08:00
GustavWi
0f65920536
IAR Fixed NVIC table in ram for nucleo targets
2014-11-27 08:24:08 +01:00
Olaf Hagendorf
e0d3730a55
[STM_Targets] linker file naming principle
2014-11-26 16:13:37 +01:00
GustavWi
939471cdbd
IAR Fixed NVIC table in ram for stm targets
2014-11-26 16:09:03 +01:00
Olaf Hagendorf
2e3c02f121
[STM32L1xx] linker script reorganisation
2014-11-26 15:07:38 +01:00
Olaf Hagendorf
80ddc6661d
[DISCO_F4xx][NUCLEO_F4xx] linker and startup script reorganisation
2014-11-26 14:29:52 +01:00
Olaf Hagendorf
dda84e6c32
[STM32F03X][STM3207X] linker script reorganizatin
2014-11-26 13:48:58 +01:00
GustavWi
60a7d3755f
IAR Fixed NVIC RAM Vector space for NXP targets
2014-11-26 13:30:49 +01:00
Olaf Hagendorf
087a8eab34
[STM32L053xx] linker script reorganisation
2014-11-26 13:15:09 +01:00
Olaf Hagendorf
0737130e57
[STM32F3xx] linker script reorganisation
2014-11-26 12:31:02 +01:00
Martin Kojtal
c3208fe6f4
Merge pull request #736 from GustavWi/iar_mbed
...
RTOS: IAR Export for CORTEX M3
2014-11-26 08:57:24 +01:00
Martin Kojtal
d9a231862a
Merge pull request #733 from masaohamanaka/master
...
Targets: RZ_A1H - Modified Terminal setting for New GR-PEACH.
2014-11-26 08:53:06 +01:00
Masao Hamanaka
0d99a7d7ad
Delete old version terminal setting code.
...
We confirmed that user never use the old version GR-PEACH.
So, we deleted old version terminal setting code.
2014-11-26 13:44:01 +09:00
Bogdan Marinescu
d8f6c47dde
Bumped build number
2014-11-25 13:48:38 +00:00
Martin Kojtal
4e89d3c771
Merge pull request #739 from xiongyihui/master
...
Targets: ARCH_MAX & DISCO_F407VG - Add SystemCoreClockUpdate and HAL_Init to mbed_sdk_init
2014-11-25 12:30:32 +01:00
Yihui Xiong
9bf1247ff9
[ARCH_MAX & DISCO_F407VG] add SystemCoreClockUpdate and HAL_Init to
...
mbed_sdk_init
HAL_Init is needed by Arch MAX to setup RTC with internal clock
2014-11-25 16:48:14 +08:00
Martin Kojtal
d5afb47760
Merge pull request #711 from ohagendorf/_exit-or-exit
...
mbed: Name of exit function in exit.c for GCC ARM (_exit)
2014-11-25 08:21:11 +01:00
bcostm
ea50eb3512
[NUCLEO_L053R8] Correct issue with Travis build
2014-11-24 16:20:26 +01:00
GustavWi
d03da0cd30
removed comments and fixed USB_RAM section
2014-11-24 14:28:08 +01:00
GustavWi
c2de05e882
Fixed LPC1768 NVIC placement space in RAM
2014-11-24 14:16:32 +01:00
bcostm
53f92133dc
[NUCLEO_L0/L1] Add PeripheralPins files
2014-11-24 12:36:39 +01:00
bcostm
afd167f734
[NUCLEO_F4] Add note on optional pins
2014-11-24 12:35:46 +01:00
bcostm
04dc0c7a24
[NUCLEO_F3] Add PeripheralPins files
2014-11-24 12:34:35 +01:00
bcostm
f62073e179
[NUCLEO_F103RB] Add PeripheralPins files
2014-11-24 12:33:15 +01:00
bcostm
60e0d1431e
[NUCLEO_F0] Add PeripheralPins files
2014-11-24 12:32:02 +01:00
GustavWi
092828ce33
Added IAR Export RTOS CORTEX M3
2014-11-24 10:58:08 +01:00
Martin Kojtal
814740f86e
Merge pull request #720 from bcostm/master
...
Targets: NUCLEOs - Improvement of gpio_irq hal
2014-11-24 08:15:36 +01:00
ohagendorf
4d04aba235
[NUCLEO_F072RB] exporter for gcc and coide
2014-11-22 14:56:30 +01:00
ohagendorf
caf42f946c
[NUCLEO_F030R8] exporter for gcc and coide
2014-11-22 12:18:31 +01:00
Masao Hamanaka
59f686bbc1
Modified Terminal setting for New GR-PEACH.
...
Modified Terminal setting of Ethernet and LED PIN for New GR-PEACH.
2014-11-21 13:47:46 +09:00
Yihui Xiong
c6f0c3b14b
Revert "[NUCLEO_F103RB] update SystemCoreClock after changing clock settings"
2014-11-20 19:19:47 +08:00
Michael Brudevold
3e1aac36e1
Correct pin names for serial rx/tx
2014-11-19 14:52:49 -06:00
Martin Kojtal
f364b76d2f
Merge pull request #703 from masaohamanaka/master
...
Targets: RZ_A1H - Fixed a bug of serial interrupt
2014-11-19 00:59:43 -08:00
0xc0170
dcfa675e50
Merge branch 'NUCLEO_L152RE_exporter' of github.com:ohagendorf/mbed into ohagendorf-NUCLEO_L152RE_exporter
...
Conflicts:
workspace_tools/build_travis.py
workspace_tools/export/coide.py
2014-11-19 08:43:14 +00:00
Martin Kojtal
7ff3e68a96
Merge pull request #714 from ohagendorf/NUCLEO_F302R8_exporter_2
...
Tools: NUCLEO_F302R8 - exporters for gcc_arm and coide
2014-11-19 00:28:37 -08:00
Martin Kojtal
5ad32eaa60
Merge pull request #715 from kshoji/nRF51822_serial_31250
...
Targets: nRF51822 - Add support for Serial 31250 baud (for legacy MIDI)
2014-11-19 00:26:52 -08:00
Martin Kojtal
12b3c601ea
Merge pull request #721 from GustavWi/iar_mbed
...
Tools: IAR export for some NXP Platforms
2014-11-19 00:23:12 -08:00
Yihui Xiong
72e2d393a6
[NUCLEO_F103RB] update SystemCoreClock after changing clock settings
2014-11-19 13:51:12 +08:00
kshoji
d05c1d4950
nrf51_bitfields.h reverted.
2014-11-19 14:47:01 +09:00
GustavWi
849c8742f0
IAR export LPC4088
2014-11-18 16:19:26 +01:00
GustavWi
299749f143
IAR export LPC810 + 812
2014-11-18 16:09:38 +01:00
GustavWi
82523de2c6
IAR export LPC1549
2014-11-18 16:01:34 +01:00
GustavWi
d13714fb07
IAR export for LPC11XX and 11CXX
2014-11-18 15:49:23 +01:00
GustavWi
b3656be310
Added IAR export for LPC11UXX
2014-11-18 14:54:40 +01:00
bcostm
20177c912b
[NUCLEOs] Improvement of gpio_irq hal
...
Now it is possible to have multiple interrupt pins on EXTI vectors.
Example:
EXTI0 -> PA_0 or PB_0 or PC_0, ... only 1 pin
EXTI5_9 -> PA_5 and PA_6 and PB_7 and PC_8 and PC_9: up to 5 pins
EXTI10_15: PA_10 and PB_11 and PB_12, ... : up to 6 pins
2014-11-18 12:28:30 +01:00