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Added IAR Export RTOS CORTEX M3

pull/736/head
GustavWi 2014-11-21 12:56:20 +01:00
parent ab15b6b123
commit 092828ce33
6 changed files with 371 additions and 86 deletions
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65
libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC176X/TOOLCHAIN_IAR/LPC17xx.icf
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@ -1,40 +1,39 @@
/* [ROM] */
define symbol __intvec_start__ = 0x00000000;
define symbol __region_ROM_start__ = 0x00000000;
define symbol __CRP_start__ = 0x000002FC;
define symbol __CRP_end__ = 0x000002FF;
define symbol __region_ROM_end__ = 0x0007FFFF;
/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x00000000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
define symbol __ICFEDIT_region_ROM_end__ = 0x0007FFFF;
define symbol __ICFEDIT_region_RAM_start__ = 0x10000000;
define symbol __ICFEDIT_region_RAM_end__ = 0x10007FDF;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x800;
define symbol __ICFEDIT_size_heap__ = 0x1000;
/**** End of ICF editor section. ###ICF###*/
/* [RAM] Vector table dynamic copy: 8_byte_aligned(49 vect * 4 bytes) = 8_byte_aligned(0xC4) = 0xC8*/
define symbol __NVIC_start__ = 0x10000000;
define symbol __NVIC_end__ = 0x100000C7;
define symbol __region_RAM_start__ = 0x100000C8;
define symbol __region_RAM_end__ = 0x10007FDF;
define symbol _AHB_RAM_start__ = 0x2007C000;
define symbol _AHB_RAM_end__ = 0x20083FFF;
define symbol __CRP_start__ = 0x000002FC;
define symbol __CRP_end__ = 0x000002FF;
define symbol __RAM1_start__ = 0x2007C000;
define symbol __RAM1_end__ = 0x20083FFF;
/* Memory regions */
define memory mem with size = 4G;
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__] - mem:[from __CRP_start__ to __CRP_end__];
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
define region CRP_region = mem:[from __CRP_start__ to __CRP_end__];
define region RAM1_region = mem:[from __RAM1_start__ to __RAM1_end__];
define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__] - mem:[from __CRP_start__ to __CRP_end__];
define region CRP_region = mem:[from __CRP_start__ to __CRP_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__];
define region AHB_RAM_region = mem:[from _AHB_RAM_start__ to _AHB_RAM_end__];
/* Stack and Heap */
define symbol __size_cstack__ = 0x800;
define symbol __size_heap__ = 0x800;
define block CSTACK with alignment = 8, size = __size_cstack__ { };
define block HEAP with alignment = 8, size = __size_heap__ { };
define block STACKHEAP with fixed order { block HEAP, block CSTACK };
initialize by copy with packing = zeros { readwrite };
initialize by copy { readwrite };
do not initialize { section .noinit };
place at address mem:__intvec_start__ { section .intvec };
place at address mem:0x2FC { section CRPKEY };
place in ROM_region { readonly };
place in RAM_region { readwrite, block STACKHEAP };
place in AHB_RAM_region { section USB_RAM };
place in CRP_region { section .crp };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, block HEAP };
place in CRP_region { section .crp };
place in RAM1_region { section .sram };

4
libraries/rtos/rtx/TARGET_CORTEX_M/RTX_CM_lib.h
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@ -291,6 +291,9 @@ extern unsigned char Image$$RW_IRAM1$$ZI$$Limit[];
#elif defined(__GNUC__)
extern unsigned char __end__[];
#define HEAP_START (__end__)
#elif defined(__ICCARM__)
#pragma section="HEAP"
#define HEAP_START (void *)__section_begin("HEAP")
#endif
void set_main_stack(void) {
@ -441,6 +444,7 @@ __noreturn __stackless void __cmain(void) {
__iar_data_init3();
}
osKernelInitialize();
set_main_stack();
osThreadCreate(&os_thread_def_main, NULL);
a = osKernelStart();
exit(a);

265
libraries/rtos/rtx/TARGET_CORTEX_M/TARGET_M3/TOOLCHAIN_IAR/HAL_CM3.s Normal file
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@ -0,0 +1,265 @@
/*----------------------------------------------------------------------------
* RL-ARM - RTX
*----------------------------------------------------------------------------
* Name: HAL_CM3.S
* Purpose: Hardware Abstraction Layer for Cortex-M3
* Rev.: V4.70
*----------------------------------------------------------------------------
*
* Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH
* All rights reserved.
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*---------------------------------------------------------------------------*/
NAME HAL_CM3.S
#define TCB_TSTACK 36
EXTERN os_flags
EXTERN os_tsk
EXTERN rt_alloc_box
EXTERN rt_free_box
EXTERN rt_stk_check
EXTERN rt_pop_req
EXTERN rt_systick
EXTERN os_tick_irqack
EXTERN SVC_Table
EXTERN SVC_Count
/*----------------------------------------------------------------------------
* Functions
*---------------------------------------------------------------------------*/
SECTION .text:CODE:NOROOT(2)
THUMB
/*--------------------------- rt_set_PSP ------------------------------------*/
; void rt_set_PSP (U32 stack);
PUBLIC rt_set_PSP
rt_set_PSP:
MSR PSP,R0
BX LR
/*--------------------------- rt_get_PSP ------------------------------------*/
; U32 rt_get_PSP (void);
PUBLIC rt_get_PSP
rt_get_PSP:
MRS R0,PSP
BX LR
/*--------------------------- os_set_env ------------------------------------*/
; void os_set_env (void);
/* Switch to Unprivileged/Privileged Thread mode, use PSP. */
PUBLIC os_set_env
os_set_env:
MOV R0,SP /* PSP = MSP */
MSR PSP,R0
LDR R0,=os_flags
LDRB R0,[R0]
LSLS R0,#31
ITE NE
MOVNE R0,#0x02 /* Privileged Thread mode, use PSP */
MOVEQ R0,#0x03 /* Unprivileged Thread mode, use PSP */
MSR CONTROL,R0
BX LR
/*--------------------------- _alloc_box ------------------------------------*/
; void *_alloc_box (void *box_mem);
/* Function wrapper for Unprivileged/Privileged mode. */
PUBLIC _alloc_box
_alloc_box:
LDR R12,=rt_alloc_box
MRS R3,IPSR
LSLS R3,#24
IT NE
BXNE R12
MRS R3,CONTROL
LSLS R3,#31
IT EQ
BXEQ R12
SVC 0
BX LR
/*--------------------------- _free_box -------------------------------------*/
; int _free_box (void *box_mem, void *box);
/* Function wrapper for Unprivileged/Privileged mode. */
PUBLIC _free_box
_free_box:
LDR R12,=rt_free_box
MRS R3,IPSR
LSLS R3,#24
IT NE
BXNE R12
MRS R3,CONTROL
LSLS R3,#31
IT EQ
BXEQ R12
SVC 0
BX LR
/*-------------------------- SVC_Handler ------------------------------------*/
; void SVC_Handler (void);
PUBLIC SVC_Handler
SVC_Handler:
MRS R0,PSP /* Read PSP */
LDR R1,[R0,#24] /* Read Saved PC from Stack */
LDRB R1,[R1,#-2] /* Load SVC Number */
CBNZ R1,SVC_User
LDM R0,{R0-R3,R12} /* Read R0-R3,R12 from stack */
BLX R12 /* Call SVC Function */
MRS R12,PSP /* Read PSP */
STM R12,{R0-R2} /* Store return values */
LDR R3,=os_tsk
LDM R3,{R1,R2} /* os_tsk.run, os_tsk.new */
CMP R1,R2
BEQ SVC_Exit /* no task switch */
CBZ R1,SVC_Next /* Runtask deleted? */
STMDB R12!,{R4-R11} /* Save Old context */
STR R12,[R1,#TCB_TSTACK] /* Update os_tsk.run->tsk_stack */
PUSH {R2,R3}
BL rt_stk_check /* Check for Stack overflow */
POP {R2,R3}
SVC_Next:
STR R2,[R3] /* os_tsk.run = os_tsk.new */
LDR R12,[R2,#TCB_TSTACK] /* os_tsk.new->tsk_stack */
LDMIA R12!,{R4-R11} /* Restore New Context */
MSR PSP,R12 /* Write PSP */
SVC_Exit:
MVN LR,#~0xFFFFFFFD /* set EXC_RETURN value */
BX LR
/*------------------- User SVC ------------------------------*/
SVC_User:
PUSH {R4,LR} /* Save Registers */
LDR R2,=SVC_Count
LDR R2,[R2]
CMP R1,R2
BHI SVC_Done /* Overflow */
LDR R4,=SVC_Table-4
LDR R4,[R4,R1,LSL #2] /* Load SVC Function Address */
LDM R0,{R0-R3,R12} /* Read R0-R3,R12 from stack */
BLX R4 /* Call SVC Function */
MRS R12,PSP
STM R12,{R0-R3} /* Function return values */
SVC_Done:
POP {R4,PC} /* RETI */
/*-------------------------- PendSV_Handler ---------------------------------*/
; void PendSV_Handler (void);
PUBLIC PendSV_Handler
PendSV_Handler:
BL rt_pop_req
Sys_Switch:
LDR R3,=os_tsk
LDM R3,{R1,R2} /* os_tsk.run, os_tsk.new */
CMP R1,R2
BEQ Sys_Exit
MRS R12,PSP /* Read PSP */
STMDB R12!,{R4-R11} /* Save Old context */
STR R12,[R1,#TCB_TSTACK] /* Update os_tsk.run->tsk_stack */
PUSH {R2,R3}
BL rt_stk_check /* Check for Stack overflow */
POP {R2,R3}
STR R2,[R3] /* os_tsk.run = os_tsk.new */
LDR R12,[R2,#TCB_TSTACK] /* os_tsk.new->tsk_stack */
LDMIA R12!,{R4-R11} /* Restore New Context */
MSR PSP,R12 /* Write PSP */
Sys_Exit:
MVN LR,#~0xFFFFFFFD /* set EXC_RETURN value */
BX LR /* Return to Thread Mode */
/*-------------------------- SysTick_Handler --------------------------------*/
; void SysTick_Handler (void);
PUBLIC SysTick_Handler
SysTick_Handler:
BL rt_systick
B Sys_Switch
/*-------------------------- OS_Tick_Handler --------------------------------*/
; void OS_Tick_Handler (void);
PUBLIC OS_Tick_Handler
OS_Tick_Handler:
BL os_tick_irqack
BL rt_systick
B Sys_Switch
END
/*----------------------------------------------------------------------------
* end of file
*---------------------------------------------------------------------------*/

58
libraries/rtos/rtx/TARGET_CORTEX_M/TARGET_M3/TOOLCHAIN_IAR/SVC_Table.s Normal file
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@ -0,0 +1,58 @@
;/*----------------------------------------------------------------------------
; * CMSIS-RTOS - RTX
; *----------------------------------------------------------------------------
; * Name: SVC_TABLE.S
; * Purpose: Pre-defined SVC Table for Cortex-M
; * Rev.: V4.70
; *----------------------------------------------------------------------------
; *
; * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH
; * All rights reserved.
; * Redistribution and use in source and binary forms, with or without
; * modification, are permitted provided that the following conditions are met:
; * - Redistributions of source code must retain the above copyright
; * notice, this list of conditions and the following disclaimer.
; * - Redistributions in binary form must reproduce the above copyright
; * notice, this list of conditions and the following disclaimer in the
; * documentation and/or other materials provided with the distribution.
; * - Neither the name of ARM nor the names of its contributors may be used
; * to endorse or promote products derived from this software without
; * specific prior written permission.
; *
; * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
; * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
; * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
; * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
; * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
; * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
; * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
; * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
; * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
; * POSSIBILITY OF SUCH DAMAGE.
; *---------------------------------------------------------------------------*/
NAME SVC_TABLE
SECTION .text:CONST (2)
PUBLIC SVC_Count
SVC_Cnt EQU (SVC_End-SVC_Table)/4
SVC_Count DCD SVC_Cnt
; Import user SVC functions here.
; IMPORT __SVC_1
PUBLIC SVC_Table
SVC_Table
; Insert user SVC functions here. SVC 0 used by RTL Kernel.
; DCD __SVC_1 ; user SVC function
SVC_End
END
/*----------------------------------------------------------------------------
* end of file
*---------------------------------------------------------------------------*/

4
libraries/rtos/rtx/TARGET_CORTEX_M/cmsis_os.h
View File

@ -115,7 +115,7 @@ used throughout the whole project.
#define CMSIS_OS_RTX
// The stack space occupied is mainly dependent on the underling C standard library
#if defined(TOOLCHAIN_GCC) || defined(TOOLCHAIN_ARM_STD)
#if defined(TOOLCHAIN_GCC) || defined(TOOLCHAIN_ARM_STD) || defined(TOOLCHAIN_IAR)
# define WORDS_STACK_SIZE 512
#elif defined(TOOLCHAIN_ARM_MICRO)
# define WORDS_STACK_SIZE 128
@ -135,6 +135,8 @@ used throughout the whole project.
#if defined (__CC_ARM)
#define os_InRegs __value_in_regs // Compiler specific: force struct in registers
#elif defined (__ICCARM__)
#define os_InRegs __value_in_regs // Compiler specific: force struct in registers
#else
#define os_InRegs
#endif

61
libraries/rtos/rtx/TARGET_CORTEX_M/rt_CMSIS.c
View File

@ -265,30 +265,24 @@ static inline t __##f (t1 a1, t2 a2, t3 a3, t4 a4) { \
#define __NO_RETURN __noreturn
#define RET_osEvent "=r"(ret.status), "=r"(ret.value), "=r"(ret.def)
#define RET_osCallback "=r"(ret.fp), "=r"(ret.arg)
#define osEvent_type osEvent
#define osEvent_ret_status ret
#define osEvent_ret_value ret
#define osEvent_ret_msg ret
#define osEvent_ret_mail ret
#define osCallback_type uint64_t
#define osCallback_ret ((uint64_t)ret.fp | ((uint64_t)ret.arg)<<32)
#define osCallback_type osCallback
#define osCallback_ret ret
#define RET_osEvent osEvent
#define RET_osCallback osCallback
#define SVC_Setup(f) \
__asm( \
__asm( \
"mov r12,%0\n" \
:: "r"(&f): "r12" \
);
#define SVC_Ret3() \
__asm( \
"ldr r0,[sp,#0]\n" \
"ldr r1,[sp,#4]\n" \
"ldr r2,[sp,#8]\n" \
);
#define SVC_0_1(f,t,...) \
t f (void); \
@ -330,46 +324,9 @@ static inline t __##f (t1 a1, t2 a2, t3 a3, t4 a4) { \
return _##f(a1,a2,a3,a4); \
}
#define SVC_1_2(f,t,t1,rr) \
uint64_t f (t1 a1); \
_Pragma("swi_number=0") __swi uint64_t _##f (t1 a1); \
static inline t __##f (t1 a1) { \
t ret; \
SVC_Setup(f); \
_##f(a1); \
__asm("" : rr : :); \
return ret; \
}
#define SVC_1_3(f,t,t1,rr) \
t f (t1 a1); \
void f##_ (t1 a1) { \
f(a1); \
SVC_Ret3(); \
} \
_Pragma("swi_number=0") __swi void _##f (t1 a1); \
static inline t __##f (t1 a1) { \
t ret; \
SVC_Setup(f##_); \
_##f(a1); \
__asm("" : rr : :); \
return ret; \
}
#define SVC_2_3(f,t,t1,t2,rr) \
t f (t1 a1, t2 a2); \
void f##_ (t1 a1, t2 a2) { \
f(a1,a2); \
SVC_Ret3(); \
} \
_Pragma("swi_number=0") __swi void _##f (t1 a1, t2 a2); \
static inline t __##f (t1 a1, t2 a2) { \
t ret; \
SVC_Setup(f##_); \
_##f(a1,a2); \
__asm("" : rr : :); \
return ret; \
}
#define SVC_1_2 SVC_1_1
#define SVC_1_3 SVC_1_1
#define SVC_2_3 SVC_2_1
#endif