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17,107 Commits
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17107 Commits (822bf98c11c5b45ec9089eaab04503411d9e37c5)

Author SHA1 Message Date
ccli8 5839431812 Remove dead code with '#if 0' in SPI 2018-07-27 13:30:06 -05:00
ccli8 d611a3c9b0 Add GPIO debounce configuration in targets.json 2018-07-27 13:30:06 -05:00
ccli8 b1b57d24af Support PWM out 2018-07-27 13:30:06 -05:00
ccli8 6b811afb73 Support analog-in 2018-07-27 13:30:06 -05:00
ccli8 bce2b6460d Support TRNG 
To change TRNG security state, we need to:
1. Change CRPT/CRYPTO bit in NVIC/SCU in partition_M2351.h
2. Add/remove TRNG in device_has list in targets.json to match partition_M2351.h
 2018-07-27 13:30:06 -05:00
ccli8 b86c957c0d Centralize size configuration for secure flash, secure SRAM, NSC, and bootloader 2018-07-27 13:30:06 -05:00
ccli8 3950b12a82 Change NSC location 
NSC location has the following requirements:
1. By IDAU, 0~0x4000 is secure. NSC can only locate in 0x4000~0x10000000.
2. Greentea flash IAP uses last 4 sectors for its test. Avoid this range.
3. Greentea NVSTORE uses last 2 sectors or 4KB x 2 for its test. Avoid this range.
 2018-07-27 13:30:06 -05:00
ccli8 1e7b6eec89 Upgrade partition format 
Following BSP, this upgrade makes partitioning flash/SRAM clear.
flash_api.c relies on flash partition, so it is updated accordingly.
 2018-07-27 13:30:06 -05:00
ccli8 d2f5548269 Fix page size in flash IAP 
In Mbed OS, page size is program unit, which is different than FMC definition.
After fixing page size, we can pass NVSTORE test (mbed-os-features-nvstore-tests-nvstore-functionality).
 2018-07-27 13:30:06 -05:00
ccli8 3ac5e48d40 Support flash IAP 2018-07-27 13:30:06 -05:00
ccli8 68b8db1a1e Add missing delay in lp_ticker 2018-07-27 13:30:06 -05:00
ccli8 c34d8aeab2 Trim HIRC48 to 48M against LXT 2018-07-27 13:30:06 -05:00
ccli8 c7ed684285 Support I2C 2018-07-27 13:30:06 -05:00
ccli8 ffe1e23ba0 Support SPI 2018-07-27 13:30:06 -05:00
ccli8 a8ed3ff5cd Refine UART code 
1. Replace SYS_ResetModule/CLK_SetModuleClock/CLK_EnableModuleClock/CLK_DisableModuleClock with TrustZone-aware versions.
2. Configure all UART to secure
3. Support asynchronous transfer
4. Remove sleep management code, which has been replaced with Sleep Manager.
 2018-07-27 13:30:06 -05:00
ccli8 61a021ca9a Support PDMA 2018-07-27 13:30:06 -05:00
cyliangtw 2cd825d463 Rework us_ticker and lp_ticker 
The rework includes the following:
1. Remove ticker overflow handling because upper layer (mbed_ticker_api.c) has done with it.
   This makes us_ticker/lp_ticker implementation more succinct and avoids potential error.
2. Refine timer register access with low-power clock source
 2018-07-27 13:30:06 -05:00
ccli8 7cf3501935 Remove peripheral sleep management from hal_sleep/hal_deepsleep 
The upper layer has introduced Sleep Manager to handle the task.
 2018-07-27 13:30:06 -05:00
ccli8 a1c8803c7d Rework RTC 
The rework includes the following:
1. Support year range beyond H/W RTC 2000~2099.
2. Refine RTC register access with low-power clock source
 2018-07-27 13:30:06 -05:00
ccli8 3f4da6166d Fix GPIO to be TrustZone-aware 
1. Revise NU_PORT_BASE to be TrustZone-aware
2. Add TrustZone-aware NU_GET_GPIO_PIN_DATA/NU_SET_GPIO_PIN_DATA to replace GPIO_PIN_DATA
3. Revise pin_function to be TrustZone-aware
 2018-07-27 13:30:06 -05:00
ccli8 160c26847a Fix SystemCoreClockUpdate isn't called in non-secure domain 2018-07-27 13:30:06 -05:00
ccli8 7f0e35f5ad Fix HCLK clock source 
There is a reset halt issue with PLL in A version.
Work around it by using HIRC48 instead of PLL as HCLK clock source.
 2018-07-27 13:30:06 -05:00
ccli8 001aa01a6d Add secure BSP driver function 
SYS_ResetModule_S
CLK_SetModuleClock_S
CLK_EnableModuleClock_S
CLK_DisableModuleClock_S
 2018-07-27 13:30:06 -05:00
ccli8 07548bdc07 Unify secure/non-secure peripheral base based on partition file 2018-07-27 13:30:06 -05:00
ccli8 e51be32292 Configure most modules to non-secure 
All modules are configured to non-secure except:
1. TIMER0/1 hard-wired to secure and TIMER2/3 reserved for non-secure.
2. PDMA0 hard-wired to secure and PDMA1 reserved for non-secure.
3. RTC configured to secure and shared to non-secure through NSC.
4. CRYPTO configured to secure and shared to non-secure through NSC.
 2018-07-27 13:30:06 -05:00
ccli8 dbaf7ea0dd Fix STDIO UART 2018-07-27 13:30:06 -05:00
ccli8 f5029ff739 Fix target configuration 
1. NUMAKER_PFM_M2351 defaults to non-secure
2. Add NUMAKER_PFM_M2351_S/NUMAKER_PFM_M2351_NS which are for secure/non-secure build respectively.
3. Change output format to Intel HEX
4. Fix device name to M2351KIAAEES from M2351K1AAEES
5. Add detect_code
 2018-07-27 13:30:06 -05:00
cyliangtw f861923709 To fulfill _rtc_localtime one more argument 2018-07-27 13:30:05 -05:00
deepikabhavnani d710ee0d4e Disabled fault handler support 2018-07-27 13:30:05 -05:00
cyliangtw db4048d199 Add gpio_is_connected 2018-07-27 13:30:05 -05:00
cyliangtw 4561c86a4e Set secure SRAM size as 24KB in SAU & SCU 2018-07-27 13:30:05 -05:00
cyliangtw 6e799ec9e4 Set 48KB SRAM and UART0 as non-secure 2018-07-27 13:30:05 -05:00
cyliangtw 1f891fc2d6 Resolve reset halt issue in MP chip A version 2018-07-27 13:30:05 -05:00
cyliangtw 602aac8813 Sync IRQ arrangement to fulfill MP version 2018-07-27 13:30:05 -05:00
cyliangtw 2bd15eac69 Remove redundant GetPC 2018-07-27 13:30:05 -05:00
cyliangtw f3afbf2e00 Migrate for MP chip version, build sucessfully 2018-07-27 13:30:05 -05:00
Deepika 7a48a74967 Support TrustZone in port_read/port_write 2018-07-27 13:30:05 -05:00
Deepika ea72d5e734 Add non-secure reset handler address 2018-07-27 13:30:05 -05:00
deepikabhavnani a70e6f51a4 Corrected Vector table address in scatter file 2018-07-27 13:30:05 -05:00
cyliangtw 625bfa8c0b Link register base with partition file & correct heap size in linker file 2018-07-27 13:30:05 -05:00
cyliangtw e674eda1dc Support secure loader invoke non-secure Mbed OS 2018-07-27 13:30:05 -05:00
deepikabhavnani d7964f4e8a Corrected preprocess define usage in toolchain specific linker files 2018-07-27 13:30:05 -05:00
cyliangtw 2bf79ca1c2 Fix GCC linker file 'cannot move location counter backwards' issue 2018-07-27 13:30:05 -05:00
cyliangtw 16a6012d97 IAR linker file support both of secure & non-secure domain 2018-07-27 13:30:05 -05:00
cyliangtw cee23da446 Linker files support both of secure & non-secure domain 2018-07-27 13:30:05 -05:00
cyliangtw bcfe934734 Update GCC linker for NSC Veneer 2018-07-27 13:30:05 -05:00
Deepika 0be7de013e ARMC6 compiler related changes 2018-07-27 13:30:05 -05:00
Deepika 42b713cab2 Removed device name, till device patch is added to IAR/Keil 2018-07-27 13:30:05 -05:00
Deepika f1336c9f85 Set SAU Region present flag for M2351 device and include security header file. 
As per SAU documents, SAU is always present if the security extension is
available. The functionality differs if the SAU contains SAU regions.
If SAU regions are available it is configured with the macro __SAUREGION_PRESENT
 2018-07-27 13:30:05 -05:00
Deepika 0468bf2b6b Added xx_ticker_fire_interrupt function for M2351 device 2018-07-27 13:30:05 -05:00