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Trim HIRC48 to 48M against LXT

pull/7631/head
ccli8 2018-03-19 18:09:07 +08:00 committed by Cruz Monrreal II
parent c7ed684285
commit c34d8aeab2
2 changed files with 27 additions and 2 deletions
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27
targets/TARGET_NUVOTON/TARGET_M2351/TARGET_NUMAKER_PFM_M2351/mbed_overrides.c
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@ -15,7 +15,7 @@
*/
#include "cmsis.h"
#include "mbed_error.h"
void mbed_sdk_init(void)
{
@ -64,6 +64,31 @@ void mbed_sdk_init(void)
/* Set core clock as 48M from PLL */
CLK_SetCoreClock(FREQ_48MHZ);
#else
/* Trim HIRC48 to 48M against LXT */
/* Reset TISTS48M status flags */
SYS->TISTS48M |= (SYS_TISTS48M_FREQLOCK_Msk | SYS_TISTS48M_TFAILIF_Msk | SYS_TISTS48M_CLKERRIF_Msk);
/* With reference clock from LXT, start trimming HIRC48 to 48M */
SYS->TCTL48M = (SYS->TCTL48M & ~(SYS_TCTL48M_FREQSEL_Msk | SYS_TCTL48M_REFCKSEL_Msk)) | (0x01 << SYS_TCTL48M_FREQSEL_Pos) | (0x00 << SYS_TCTL48M_REFCKSEL_Pos);
/* Wait for HIRC48 clock locked */
while (1)
{
if (SYS->TISTS48M & SYS_TISTS48M_FREQLOCK_Msk)
{
break;
}
else if (SYS->TISTS48M & SYS_TISTS48M_TFAILIF_Msk)
{
error("HIRC48 auto-trim error: SYS_TISTS48M_TFAILIF_Msk");
}
else if (SYS->TISTS48M & SYS_TISTS48M_CLKERRIF_Msk)
{
error("HIRC48 auto-trim error: SYS_TISTS48M_CLKERRIF_Msk");
}
}
CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_HIRC48, CLK_CLKDIV0_HCLK(1UL));
#endif

2
targets/TARGET_NUVOTON/TARGET_M2351/device/Reg/sys_reg.h
View File

@ -1064,7 +1064,7 @@ typedef struct
__IO uint32_t SRAMPPCT; /*!< [0x00E0] Peripheral SRAM Power Mode Control Register */
__IO uint32_t TCTL48M; /*!< [0x00E4] HIRC 48M Trim Control Register */
__IO uint32_t TIEN48M; /*!< [0x00E8] HIRC 48M Trim Interrupt Enable Register */
__IO uint32_t TOSTS48M; /*!< [0x00EC] HIRC 48M Trim Interrupt Status Register */
__IO uint32_t TISTS48M; /*!< [0x00EC] HIRC 48M Trim Interrupt Status Register */
__IO uint32_t TCTL12M; /*!< [0x00F0] HIRC 12M Trim Control Register */
__IO uint32_t TIEN12M; /*!< [0x00F4] HIRC 12M Trim Interrupt Enable Register */
__IO uint32_t TISTS12M; /*!< [0x00F8] HIRC 12M Trim Interrupt Status Register */