Commit Graph

180 Commits (6867499da373e64dda87e269c81b551a7ee4501a)

Author SHA1 Message Date
svastm 3c684e13f2 [NUCLEO_L432KC] Fix peripheral definitions 2016-06-30 15:05:06 +02:00
svastm b91c65ee2d [NUCLEO_L432KC] Update HAL API 2016-06-30 15:04:45 +02:00
svastm 9cfc3bf2aa [NUCLEO_L432KC] Add HAL target 2016-06-30 14:48:06 +02:00
svastm 26251314c5 [NUCLEO_L432KC] Add CMSIS target 2016-06-30 14:48:06 +02:00
Sam Grove 07958da38b Merge pull request #2065 from NXPmicro/K22_KL27_Updates
K22 kl27 updates
2016-06-29 22:24:35 -05:00
Sam Grove 737a7809f9 Merge pull request #2063 from geky/fix-heap
Removed heap region from ARM sct file on K devices
2016-06-28 20:54:33 -05:00
Christopher Haster 1bf641d6b3 Removed heap region from ARM sct file on K devices
- __heap_size__ was used to allocate a fixed size region for the heap in
  RW_IRAM1
- __user_setup_stackheap in sys.cpp uses Image$$RW_IRAM1$$ZI$$Limit as the
  start of the heap, which leaves the fixed size region unused
2016-06-28 20:16:19 -05:00
Sam Grove c6db458ff6 Merge pull request #2014 from TomoYamanaka/master
RTX - init sequence (C++ array init) for Cortex-A version
2016-06-28 17:45:57 -05:00
Sam Grove a773b639d6 Merge pull request #2013 from egostm/spi_freq_selection
Spi freq selection
2016-06-28 17:43:43 -05:00
Sam Grove a6f640c3f8 Merge pull request #2009 from MultiTechSystems/mdot-leds-fix
[MTS_MDOT_F411RE] add LED2-LED4 definitions
2016-06-28 17:40:42 -05:00
Mahadevan Mahesh f15a178be0 Set the clock source in KL27 PWMOUT driver
By default the TPM clock source is disabled

Signed-off-by: Mahadevan Mahesh <Mahesh.Mahadevan@nxp.com>
2016-06-28 15:14:58 -05:00
tomoyuki yamanaka d6624c078a RTX - init sequence (C++ array init) for Cortex-A version
This is an update to RTX kernel for Cortex-A version to allow c++ libc array init to be called after kernel start.
Ref: https://github.com/mbedmicro/mbed/pull/1730
2016-06-27 19:40:22 +09:00
Erwan GOURIOU bc08631931 [STM32L4xx] Change SPI clock selection
Update of STM32L4 family CPI clock selection algo.
Maximum SPI clock is obtained from APB domain clock (based on HAL API).
Then algo sets maximum frequency available below requested frequency
2016-06-27 10:03:57 +02:00
Erwan GOURIOU 67e6f729c7 [STM32L1xx] Change SPI clock selection
Update of STM32L1 family CPI clock selection algo.
Maximum SPI clock is obtained from APB domain clock (based on HAL API).
Then algo sets maximum frequency available below requested frequency
2016-06-27 10:03:57 +02:00
Erwan GOURIOU b126d345d1 [STM32L0xx] Change SPI clock selection
Update of STM32L0 family CPI clock selection algo.
Maximum SPI clock is obtained from APB domain clock (based on HAL API).
Then algo sets maximum frequency available below requested frequency
2016-06-27 10:03:57 +02:00
Erwan GOURIOU e8103fbb94 [STM32F7xx] Change SPI clock selection
Update of STM32F7 family CPI clock selection algo.
Maximum SPI clock is obtained from APB domain clock (based on HAL API).
Then algo sets maximum frequency available below requested frequency
2016-06-27 10:03:57 +02:00
Erwan GOURIOU c87ff7872a [STM32F3xx] Change SPI clock selection
Update of STM32F3 family CPI clock selection algo.
Maximum SPI clock is obtained from APB domain clock (based on HAL API).
Then algo sets maximum frequency available below requested frequency

Signed-off-by: Erwan GOURIOU <frq07517@st.com>
2016-06-27 10:03:57 +02:00
Erwan GOURIOU 837cb78b39 [STM32F1xx] Change SPI clock selection
Update of STM32F1 family CPI clock selection algo.
Maximum SPI clock is obtained from APB domain clock (based on HAL API).
Then algo sets maximum frequency available below requested frequency
2016-06-27 10:03:57 +02:00
Erwan GOURIOU 0739d31235 [STM32F0xx] Change SPI clock selection
Update of STM32F0 family CPI clock selection algo.
Maximum SPI clock is obtained from APB domain clock (based on HAL API).
Then algo sets maximum frequency available below requested frequency
2016-06-27 10:03:57 +02:00
Erwan GOURIOU b574bb5048 [STM32F4xx] Change SPI clock selection
Update of STM32F4 family CPI clock selection algo.
Maximum SPI clock is obtained from APB domain clock (based on HAL API).
Then algo sets maximum frequency available below requested frequency
2016-06-27 10:03:57 +02:00
Sam Grove 245d4b8deb Merge pull request #2003 from rgrover/PR
minor fix for a warning when compiling with ARMCC
2016-06-26 00:48:49 -05:00
Mike Fiore e10feb7724 [MTS_MDOT_F411RE] add LED2-LED4 definitions 2016-06-24 16:38:32 -05:00
Sam Grove e508525bd4 Merge pull request #2000 from egostm/STM32F4xx_ADC2_support
[STM32F4] Add ADC2 support to F4 family
2016-06-24 16:15:30 -05:00
Rohit Grover b12f0c2ad2 take care of a compiler warning 2016-06-24 15:21:04 +01:00
Rohit Grover 7b110f077e make use of symbol BLOCK1_SIZE to replace a naked constant 2016-06-24 15:21:04 +01:00
Rohit Grover 0c5a7beb20 white space diffs 2016-06-24 15:21:03 +01:00
Rohit Grover 717651eb3f add better comments to the #if blocks guarding KSDK2 support 2016-06-24 15:21:03 +01:00
Laurent MEUNIER db7628c4b6 [STM32] Add SPI defaults pins to DISCO_F429ZI 2016-06-24 15:06:59 +02:00
Laurent MEUNIER 0f49396a0a [STM32F4] Add ADC2 support to F4 family
Introducing ADC2 support for NUCLEO_F446ZE implies to have the support
in the core part for all F4 chipsets that possibly support it (even if
not supported on all boards).
2016-06-23 17:08:22 +02:00
Sam Grove 3f5ab2fbb1 Revert "cfstore flash-journal integration with config_system (Resubmitted)" 2016-06-21 17:32:57 -05:00
Simon Hughes 8f6957e195 cfstore flash-journal integration sync mode test fixes. 2016-06-17 17:16:19 +01:00
Martin Kojtal abf9850559 Merge pull request #1796 from BartSX/lptickerF0
[STM32F0xx] LowPowerTicker implementation
2016-06-17 09:51:09 +01:00
Bartosz Szczepanski c094dcd960 [STM32F0xx] LowPowerTicker implementation
Change-Id: I3eb37aa7e35df901b7d3cd00069638425fb3fdc6
2016-06-17 08:18:37 +02:00
Martin Kojtal 42bc1a43ee Merge pull request #1890 from bcostm/fix_f0_force_serial_reset
[STM32F0] Add USART force/release Reset at Init phase
2016-06-16 17:10:30 +02:00
Martin Kojtal b79e95ab7e Merge pull request #1894 from bcostm/fix_f3_force_serial_reset
[STM32F3] Add USART force/release Reset at Init phase
2016-06-16 17:07:31 +02:00
Martin Kojtal 39acdd66a0 Merge pull request #1945 from jeromecoutant/PR_UpdateF0_driver_v1_6_0
STM32Cube_FW_F0_V1.6.0
2016-06-16 17:06:10 +02:00
Martin Kojtal b4bb088876 Merge pull request #1960 from AlessandroA/fix_volatile_missing
K64F KSDK2: Re-add missing volatile in CLOCK functions
2016-06-16 15:52:21 +02:00
Martin Kojtal 9836fedd33 Merge pull request #1915 from anpilog/master
Fix pin mode for STM32F1 target.
2016-06-16 15:22:16 +02:00
Alessandro Angelino 75fa7af17c K64F KSDK2: Re-add missing volatile in CLOCK functions
A previous patch removed two `volatile` keywords by mistake, which are
here re-introduced.

Fixes:

* 23904e7 "Access MCG and SIM through secure access"
2016-06-16 13:18:24 +01:00
Martin Kojtal 9b5adb8cd1 Merge pull request #1752 from svastm/add_nucleo_l011k4
Add NUCLEO_L011K4
2016-06-14 22:00:28 +02:00
Martin Kojtal 53d7115b49 Merge pull request #1895 from bcostm/fix_l0_force_serial_reset
[STM32L0] Add USART force/release Reset at Init phase
2016-06-14 21:53:45 +02:00
Martin Kojtal 4dcefa604a Merge pull request #1913 from BartSX/816f0xx
[STM32F0xx] Fix for #816 issue
2016-06-14 21:53:26 +02:00
Niklas Hauser 516c7cdb80 Rename NVIC_Set/GetVector for K64F
This allows FEATURE_UVISOR to virtualize the NVIC calls.
2016-06-14 14:06:45 +00:00
Niklas Hauser e4c217e21d Backport virtual NVIC mechanism from CMSIS 5 2016-06-14 14:06:45 +00:00
Niklas Hauser 23904e74be Access MCG and SIM through secure access 2016-06-14 14:06:45 +00:00
Niklas Hauser 37238fb9be Add secure access header to CMSIS 2016-06-14 14:06:44 +00:00
Alessandro Angelino 8db93cf0d9 K64F: Explicitly set the start of .uvisor.bss 2016-06-14 14:06:44 +00:00
Alessandro Angelino abd24ae4f1 K64F: Explicitly set the start of .text
If you don't specify the start address of a section explicitly, that
section can end up at different addresses depending on its alignment. If
the alignment of a section is not explicitly set, it inherits it from
the element with the highest alignment inside that section.

Since the uVisor code is in the .text section, and it *must* end up at a
known location, we set the start address of .text to 0x410, which is the
value that the uVisor binary expects.
2016-06-14 14:06:44 +00:00
Martin Kojtal e9b56018d2 Merge pull request #1848 from TomoYamanaka/master
Implement SystemcoreClock
2016-06-14 01:53:10 +02:00
Martin Kojtal 9a06a7509b Merge pull request #1921 from akselsm/efm32-license-update
[EFM32] Update license texts.
2016-06-14 00:30:26 +02:00