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Merge pull request #1945 from jeromecoutant/PR_UpdateF0_driver_v1_6_0 

STM32Cube_FW_F0_V1.6.0
pull/1816/merge
Martin Kojtal 2016-06-16 17:06:10 +02:00 committed by GitHub
parent b4bb088876 6c31f3c110
commit 39acdd66a0
116 changed files with 49361 additions and 23023 deletions
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1743
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/Release_Notes_stm32f0xx_hal.html
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6818
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/stm32f051x8.h
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hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/stm32f0xx.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx.h
* @author MCD Application Team
* @version V2.2.3
* @date 29-January-2016
* @version V2.3.0
* @date 27-May-2016
* @brief CMSIS STM32F0xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
@ -112,11 +112,11 @@
#endif /* USE_HAL_DRIVER */
/**
* @brief CMSIS Device version number V2.2.3
* @brief CMSIS Device version number V2.3.0
*/
#define __STM32F0_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */
#define __STM32F0_DEVICE_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */
#define __STM32F0_DEVICE_VERSION_SUB2 (0x03) /*!< [15:8] sub2 version */
#define __STM32F0_DEVICE_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
#define __STM32F0_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32F0_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F0_DEVICE_VERSION ((__STM32F0_DEVICE_VERSION_MAIN << 24)\
|(__STM32F0_DEVICE_VERSION_SUB1 << 16)\

5
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/system_stm32f0xx.c
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@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32f0xx.c
* @author MCD Application Team
* @version V2.2.3
* @date 29-January-2016
* @version V2.3.0
* @date 27-May-2016
* @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Source File.
*
* 1. This file provides two functions and one global variable to be called from
@ -142,6 +142,7 @@
uint32_t SystemCoreClock = 48000000;
const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
/**
* @}

9
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/system_stm32f0xx.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32f0xx.h
* @author MCD Application Team
* @version V2.2.3
* @date 29-January-2016
* @version V2.3.0
* @date 27-May-2016
* @brief CMSIS Cortex-M0 Device System Source File for STM32F0xx devices.
******************************************************************************
* @attention
@ -73,8 +73,9 @@
is no need to call the 2 first functions listed above, since SystemCoreClock
variable is updated automatically.
*/
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */
extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */
/**
* @}

5399
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/stm32f030x8.h
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10
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/stm32f0xx.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx.h
* @author MCD Application Team
* @version V2.2.3
* @date 29-January-2016
* @version V2.3.0
* @date 27-May-2016
* @brief CMSIS STM32F0xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
@ -112,11 +112,11 @@
#endif /* USE_HAL_DRIVER */
/**
* @brief CMSIS Device version number V2.2.3
* @brief CMSIS Device version number V2.3.0
*/
#define __STM32F0_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */
#define __STM32F0_DEVICE_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */
#define __STM32F0_DEVICE_VERSION_SUB2 (0x03) /*!< [15:8] sub2 version */
#define __STM32F0_DEVICE_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
#define __STM32F0_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32F0_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F0_DEVICE_VERSION ((__STM32F0_DEVICE_VERSION_MAIN << 24)\
|(__STM32F0_DEVICE_VERSION_SUB1 << 16)\

5
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/system_stm32f0xx.c
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@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32f0xx.c
* @author MCD Application Team
* @version V2.2.3
* @date 29-January-2016
* @version V2.3.0
* @date 27-May-2016
* @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Source File.
*
* 1. This file provides two functions and one global variable to be called from
@ -142,6 +142,7 @@
uint32_t SystemCoreClock = 48000000;
const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
/**
* @}

9
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/system_stm32f0xx.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32f0xx.h
* @author MCD Application Team
* @version V2.2.3
* @date 29-January-2016
* @version V2.3.0
* @date 27-May-2016
* @brief CMSIS Cortex-M0 Device System Source File for STM32F0xx devices.
******************************************************************************
* @attention
@ -73,8 +73,9 @@
is no need to call the 2 first functions listed above, since SystemCoreClock
variable is updated automatically.
*/
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */
extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */
/**
* @}

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hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/stm32f031x6.h
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hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/stm32f0xx.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx.h
* @author MCD Application Team
* @version V2.2.3
* @date 29-January-2016
* @version V2.3.0
* @date 27-May-2016
* @brief CMSIS STM32F0xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
@ -112,11 +112,11 @@
#endif /* USE_HAL_DRIVER */
/**
* @brief CMSIS Device version number V2.2.3
* @brief CMSIS Device version number V2.3.0
*/
#define __STM32F0_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */
#define __STM32F0_DEVICE_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */
#define __STM32F0_DEVICE_VERSION_SUB2 (0x03) /*!< [15:8] sub2 version */
#define __STM32F0_DEVICE_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
#define __STM32F0_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32F0_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F0_DEVICE_VERSION ((__STM32F0_DEVICE_VERSION_MAIN << 24)\
|(__STM32F0_DEVICE_VERSION_SUB1 << 16)\

5
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/system_stm32f0xx.c
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@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32f0xx.c
* @author MCD Application Team
* @version V2.2.3
* @date 29-January-2016
* @version V2.3.0
* @date 27-May-2016
* @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Source File.
*
* 1. This file provides two functions and one global variable to be called from
@ -142,6 +142,7 @@
uint32_t SystemCoreClock = 48000000;
const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
/**
* @}

9
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/system_stm32f0xx.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32f0xx.h
* @author MCD Application Team
* @version V2.2.3
* @date 29-January-2016
* @version V2.3.0
* @date 27-May-2016
* @brief CMSIS Cortex-M0 Device System Source File for STM32F0xx devices.
******************************************************************************
* @attention
@ -73,8 +73,9 @@
is no need to call the 2 first functions listed above, since SystemCoreClock
variable is updated automatically.
*/
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */
extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */
/**
* @}

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hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/stm32f042x6.h
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hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/stm32f0xx.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx.h
* @author MCD Application Team
* @version V2.2.3
* @date 29-January-2016
* @version V2.3.0
* @date 27-May-2016
* @brief CMSIS STM32F0xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
@ -112,11 +112,11 @@
#endif /* USE_HAL_DRIVER */
/**
* @brief CMSIS Device version number V2.2.3
* @brief CMSIS Device version number V2.3.0
*/
#define __STM32F0_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */
#define __STM32F0_DEVICE_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */
#define __STM32F0_DEVICE_VERSION_SUB2 (0x03) /*!< [15:8] sub2 version */
#define __STM32F0_DEVICE_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
#define __STM32F0_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32F0_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F0_DEVICE_VERSION ((__STM32F0_DEVICE_VERSION_MAIN << 24)\
|(__STM32F0_DEVICE_VERSION_SUB1 << 16)\

5
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/system_stm32f0xx.c
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@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32f0xx.c
* @author MCD Application Team
* @version V2.2.3
* @date 29-January-2016
* @version V2.3.0
* @date 27-May-2016
* @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Source File.
*
* 1. This file provides two functions and one global variable to be called from
@ -142,6 +142,7 @@
uint32_t SystemCoreClock = 48000000;
const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
/**
* @}

9
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/system_stm32f0xx.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32f0xx.h
* @author MCD Application Team
* @version V2.2.3
* @date 29-January-2016
* @version V2.3.0
* @date 27-May-2016
* @brief CMSIS Cortex-M0 Device System Source File for STM32F0xx devices.
******************************************************************************
* @attention
@ -73,8 +73,9 @@
is no need to call the 2 first functions listed above, since SystemCoreClock
variable is updated automatically.
*/
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */
extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */
/**
* @}

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hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/stm32f070xb.h
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hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/stm32f0xx.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx.h
* @author MCD Application Team
* @version V2.2.3
* @date 29-January-2016
* @version V2.3.0
* @date 27-May-2016
* @brief CMSIS STM32F0xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
@ -112,11 +112,11 @@
#endif /* USE_HAL_DRIVER */
/**
* @brief CMSIS Device version number V2.2.3
* @brief CMSIS Device version number V2.3.0
*/
#define __STM32F0_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */
#define __STM32F0_DEVICE_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */
#define __STM32F0_DEVICE_VERSION_SUB2 (0x03) /*!< [15:8] sub2 version */
#define __STM32F0_DEVICE_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
#define __STM32F0_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32F0_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F0_DEVICE_VERSION ((__STM32F0_DEVICE_VERSION_MAIN << 24)\
|(__STM32F0_DEVICE_VERSION_SUB1 << 16)\

5
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/system_stm32f0xx.c
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@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32f0xx.c
* @author MCD Application Team
* @version V2.2.3
* @date 29-January-2016
* @version V2.3.0
* @date 27-May-2016
* @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Source File.
*
* 1. This file provides two functions and one global variable to be called from
@ -142,6 +142,7 @@
uint32_t SystemCoreClock = 48000000;
const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
/**
* @}

9
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/system_stm32f0xx.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32f0xx.h
* @author MCD Application Team
* @version V2.2.3
* @date 29-January-2016
* @version V2.3.0
* @date 27-May-2016
* @brief CMSIS Cortex-M0 Device System Source File for STM32F0xx devices.
******************************************************************************
* @attention
@ -73,8 +73,9 @@
is no need to call the 2 first functions listed above, since SystemCoreClock
variable is updated automatically.
*/
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */
extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */
/**
* @}

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hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/stm32f072xb.h
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hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/stm32f0xx.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx.h
* @author MCD Application Team
* @version V2.2.3
* @date 29-January-2016
* @version V2.3.0
* @date 27-May-2016
* @brief CMSIS STM32F0xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
@ -112,11 +112,11 @@
#endif /* USE_HAL_DRIVER */
/**
* @brief CMSIS Device version number V2.2.3
* @brief CMSIS Device version number V2.3.0
*/
#define __STM32F0_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */
#define __STM32F0_DEVICE_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */
#define __STM32F0_DEVICE_VERSION_SUB2 (0x03) /*!< [15:8] sub2 version */
#define __STM32F0_DEVICE_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
#define __STM32F0_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32F0_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F0_DEVICE_VERSION ((__STM32F0_DEVICE_VERSION_MAIN << 24)\
|(__STM32F0_DEVICE_VERSION_SUB1 << 16)\

5
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/system_stm32f0xx.c
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@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32f0xx.c
* @author MCD Application Team
* @version V2.2.3
* @date 29-January-2016
* @version V2.3.0
* @date 27-May-2016
* @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Source File.
*
* 1. This file provides two functions and one global variable to be called from
@ -142,6 +142,7 @@
uint32_t SystemCoreClock = 48000000;
const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
/**
* @}

9
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/system_stm32f0xx.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32f0xx.h
* @author MCD Application Team
* @version V2.2.3
* @date 29-January-2016
* @version V2.3.0
* @date 27-May-2016
* @brief CMSIS Cortex-M0 Device System Source File for STM32F0xx devices.
******************************************************************************
* @attention
@ -73,8 +73,9 @@
is no need to call the 2 first functions listed above, since SystemCoreClock
variable is updated automatically.
*/
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */
extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */
/**
* @}

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hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/stm32f091xc.h
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hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/stm32f0xx.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx.h
* @author MCD Application Team
* @version V2.2.3
* @date 29-January-2016
* @version V2.3.0
* @date 27-May-2016
* @brief CMSIS STM32F0xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
@ -112,11 +112,11 @@
#endif /* USE_HAL_DRIVER */
/**
* @brief CMSIS Device version number V2.2.3
* @brief CMSIS Device version number V2.3.0
*/
#define __STM32F0_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */
#define __STM32F0_DEVICE_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */
#define __STM32F0_DEVICE_VERSION_SUB2 (0x03) /*!< [15:8] sub2 version */
#define __STM32F0_DEVICE_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
#define __STM32F0_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32F0_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F0_DEVICE_VERSION ((__STM32F0_DEVICE_VERSION_MAIN << 24)\
|(__STM32F0_DEVICE_VERSION_SUB1 << 16)\

5
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/system_stm32f0xx.c
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@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32f0xx.c
* @author MCD Application Team
* @version V2.2.3
* @date 29-January-2016
* @version V2.3.0
* @date 27-May-2016
* @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Source File.
*
* 1. This file provides two functions and one global variable to be called from
@ -142,6 +142,7 @@
uint32_t SystemCoreClock = 48000000;
const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
/**
* @}

9
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/system_stm32f0xx.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32f0xx.h
* @author MCD Application Team
* @version V2.2.3
* @date 29-January-2016
* @version V2.3.0
* @date 27-May-2016
* @brief CMSIS Cortex-M0 Device System Source File for STM32F0xx devices.
******************************************************************************
* @attention
@ -73,8 +73,9 @@
is no need to call the 2 first functions listed above, since SystemCoreClock
variable is updated automatically.
*/
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */
extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */
/**
* @}

188
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32_hal_legacy.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32_hal_legacy.h
* @author MCD Application Team
* @version V1.3.1
* @date 29-January-2016
* @version V1.4.0
* @date 27-May-2016
* @brief This file contains aliases definition for the STM32Cube HAL constants
* macros and functions maintained for legacy purpose.
******************************************************************************
@ -129,7 +129,6 @@
/** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose
* @{
*/
#define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE
#define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE
#define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1
@ -144,6 +143,73 @@
#define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1
#define COMP_OUTPUT_TIM3OCREFCLR COMP_OUTPUT_COMP1_TIM3OCREFCLR
#endif /* STM32F373xC || STM32F378xx */
#if defined(STM32L0) || defined(STM32L4)
#define COMP_WINDOWMODE_ENABLE COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON
#define COMP_NONINVERTINGINPUT_IO1 COMP_INPUT_PLUS_IO1
#define COMP_NONINVERTINGINPUT_IO2 COMP_INPUT_PLUS_IO2
#define COMP_NONINVERTINGINPUT_IO3 COMP_INPUT_PLUS_IO3
#define COMP_NONINVERTINGINPUT_IO4 COMP_INPUT_PLUS_IO4
#define COMP_NONINVERTINGINPUT_IO5 COMP_INPUT_PLUS_IO5
#define COMP_NONINVERTINGINPUT_IO6 COMP_INPUT_PLUS_IO6
#define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT
#define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT
#define COMP_INVERTINGINPUT_3_4VREFINT COMP_INPUT_MINUS_3_4VREFINT
#define COMP_INVERTINGINPUT_VREFINT COMP_INPUT_MINUS_VREFINT
#define COMP_INVERTINGINPUT_DAC1_CH1 COMP_INPUT_MINUS_DAC1_CH1
#define COMP_INVERTINGINPUT_DAC1_CH2 COMP_INPUT_MINUS_DAC1_CH2
#define COMP_INVERTINGINPUT_DAC1 COMP_INPUT_MINUS_DAC1_CH1
#define COMP_INVERTINGINPUT_DAC2 COMP_INPUT_MINUS_DAC1_CH2
#define COMP_INVERTINGINPUT_IO1 COMP_INPUT_MINUS_IO1
#if defined(STM32L0)
/* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2), */
/* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding */
/* to the second dedicated IO (only for COMP2). */
#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_DAC1_CH2
#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO2
#else
#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_IO2
#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO3
#endif
#define COMP_INVERTINGINPUT_IO4 COMP_INPUT_MINUS_IO4
#define COMP_INVERTINGINPUT_IO5 COMP_INPUT_MINUS_IO5
#define COMP_OUTPUTLEVEL_LOW COMP_OUTPUT_LEVEL_LOW
#define COMP_OUTPUTLEVEL_HIGH COMP_OUTPUT_LEVEL_HIGH
/* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose. */
/* To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()". */
#if defined(COMP_CSR_LOCK)
#define COMP_FLAG_LOCK COMP_CSR_LOCK
#elif defined(COMP_CSR_COMP1LOCK)
#define COMP_FLAG_LOCK COMP_CSR_COMP1LOCK
#elif defined(COMP_CSR_COMPxLOCK)
#define COMP_FLAG_LOCK COMP_CSR_COMPxLOCK
#endif
#if defined(STM32L4)
#define COMP_BLANKINGSRCE_TIM1OC5 COMP_BLANKINGSRC_TIM1_OC5_COMP1
#define COMP_BLANKINGSRCE_TIM2OC3 COMP_BLANKINGSRC_TIM2_OC3_COMP1
#define COMP_BLANKINGSRCE_TIM3OC3 COMP_BLANKINGSRC_TIM3_OC3_COMP1
#define COMP_BLANKINGSRCE_TIM3OC4 COMP_BLANKINGSRC_TIM3_OC4_COMP2
#define COMP_BLANKINGSRCE_TIM8OC5 COMP_BLANKINGSRC_TIM8_OC5_COMP2
#define COMP_BLANKINGSRCE_TIM15OC1 COMP_BLANKINGSRC_TIM15_OC1_COMP2
#define COMP_BLANKINGSRCE_NONE COMP_BLANKINGSRC_NONE
#endif
#if defined(STM32L0)
#define COMP_MODE_HIGHSPEED COMP_POWERMODE_MEDIUMSPEED
#define COMP_MODE_LOWSPEED COMP_POWERMODE_ULTRALOWPOWER
#else
#define COMP_MODE_HIGHSPEED COMP_POWERMODE_HIGHSPEED
#define COMP_MODE_MEDIUMSPEED COMP_POWERMODE_MEDIUMSPEED
#define COMP_MODE_LOWPOWER COMP_POWERMODE_LOWPOWER
#define COMP_MODE_ULTRALOWPOWER COMP_POWERMODE_ULTRALOWPOWER
#endif
#endif
/**
* @}
*/
@ -384,6 +450,7 @@
#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH
#endif /* STM32F0 || STM32F3 || STM32F1 */
#define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1
/**
* @}
*/
@ -424,7 +491,7 @@
#define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE
#define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE
#define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE
#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4)
#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7)
#define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX
#define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX
#define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX
@ -488,6 +555,11 @@
/** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose
* @{
*/
#define HAL_NAND_Read_Page HAL_NAND_Read_Page_8b
#define HAL_NAND_Write_Page HAL_NAND_Write_Page_8b
#define HAL_NAND_Read_SpareArea HAL_NAND_Read_SpareArea_8b
#define HAL_NAND_Write_SpareArea HAL_NAND_Write_SpareArea_8b
#define NAND_AddressTypedef NAND_AddressTypeDef
#define __ARRAY_ADDRESS ARRAY_ADDRESS
@ -551,6 +623,9 @@
* @{
*/
#define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS
#if defined(STM32F7)
#define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL
#endif
/**
* @}
*/
@ -646,7 +721,7 @@
*/
/** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose
/** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose
* @{
*/
#define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE
@ -664,7 +739,7 @@
* @}
*/
/** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose
/** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose
* @{
*/
#define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE
@ -867,9 +942,12 @@
#define ETH_MAC_RXFIFO_BELOW_THRESHOLD ((uint32_t)0x00000100) /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD ((uint32_t)0x00000200) /* Rx FIFO fill level: fill-level above flow-control activate threshold */
#define ETH_MAC_RXFIFO_FULL ((uint32_t)0x00000300) /* Rx FIFO fill level: full */
#if defined(STM32F1)
#else
#define ETH_MAC_READCONTROLLER_IDLE ((uint32_t)0x00000000) /* Rx FIFO read controller IDLE state */
#define ETH_MAC_READCONTROLLER_READING_DATA ((uint32_t)0x00000020) /* Rx FIFO read controller Reading frame data */
#define ETH_MAC_READCONTROLLER_READING_STATUS ((uint32_t)0x00000040) /* Rx FIFO read controller Reading frame status (or time-stamp) */
#endif
#define ETH_MAC_READCONTROLLER_FLUSHING ((uint32_t)0x00000060) /* Rx FIFO read controller Flushing the frame data and status */
#define ETH_MAC_RXFIFO_WRITE_ACTIVE ((uint32_t)0x00000010) /* Rx FIFO write controller active */
#define ETH_MAC_SMALL_FIFO_NOTACTIVE ((uint32_t)0x00000000) /* MAC small FIFO read / write controllers not active */
@ -881,6 +959,49 @@
/**
* @}
*/
/** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose
* @{
*/
#define HAL_DCMI_ERROR_OVF HAL_DCMI_ERROR_OVR
#define DCMI_IT_OVF DCMI_IT_OVR
#define DCMI_FLAG_OVFRI DCMI_FLAG_OVRRI
#define DCMI_FLAG_OVFMI DCMI_FLAG_OVRMI
#define HAL_DCMI_ConfigCROP HAL_DCMI_ConfigCrop
#define HAL_DCMI_EnableCROP HAL_DCMI_EnableCrop
#define HAL_DCMI_DisableCROP HAL_DCMI_DisableCrop
/**
* @}
*/
#if defined(STM32L4xx) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) ||\
defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
/** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose
* @{
*/
#define DMA2D_ARGB8888 DMA2D_OUTPUT_ARGB8888
#define DMA2D_RGB888 DMA2D_OUTPUT_RGB888
#define DMA2D_RGB565 DMA2D_OUTPUT_RGB565
#define DMA2D_ARGB1555 DMA2D_OUTPUT_ARGB1555
#define DMA2D_ARGB4444 DMA2D_OUTPUT_ARGB4444
#define CM_ARGB8888 DMA2D_INPUT_ARGB8888
#define CM_RGB888 DMA2D_INPUT_RGB888
#define CM_RGB565 DMA2D_INPUT_RGB565
#define CM_ARGB1555 DMA2D_INPUT_ARGB1555
#define CM_ARGB4444 DMA2D_INPUT_ARGB4444
#define CM_L8 DMA2D_INPUT_L8
#define CM_AL44 DMA2D_INPUT_AL44
#define CM_AL88 DMA2D_INPUT_AL88
#define CM_L4 DMA2D_INPUT_L4
#define CM_A8 DMA2D_INPUT_A8
#define CM_A4 DMA2D_INPUT_A4
/**
* @}
*/
#endif /* STM32L4xx || STM32F7*/
/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose
* @{
@ -938,7 +1059,10 @@
#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
#define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect
#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())
#if defined(STM32L0)
#else
#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT())
#endif
#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
/**
@ -1067,7 +1191,7 @@
*/
/** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose
/** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose
* @{
*/
@ -1442,10 +1566,28 @@
#define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE
#if defined(STM32L0) || defined(STM32L4)
/* Note: On these STM32 families, the only argument of this macro */
/* is COMP_FLAG_LOCK. */
/* This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle */
/* argument. */
#define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_COMP_IS_LOCKED(__HANDLE__))
#endif
/**
* @}
*/
#if defined(STM32L0) || defined(STM32L4)
/** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose
* @{
*/
#define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
#define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
/**
* @}
*/
#endif
/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
* @{
*/
@ -2489,7 +2631,7 @@
#endif
#if defined(STM32F7)
#define RCC_SDIOCLKSOURCE_CK48 RCC_SDMMC1CLKSOURCE_CLK48
#define RCC_SDIOCLKSOURCE_CLK48 RCC_SDMMC1CLKSOURCE_CLK48
#define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK
#endif
@ -2603,6 +2745,34 @@
#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE __HAL_RCC_CRS_RELOADVALUE_CALCULATE
#define __HAL_RCC_GET_IT_SOURCE __HAL_RCC_GET_IT
#define RCC_CRS_SYNCWARM RCC_CRS_SYNCWARN
#define RCC_CRS_TRIMOV RCC_CRS_TRIMOVF
#define RCC_PERIPHCLK_CK48 RCC_PERIPHCLK_CLK48
#define RCC_CK48CLKSOURCE_PLLQ RCC_CLK48CLKSOURCE_PLLQ
#define RCC_CK48CLKSOURCE_PLLSAIP RCC_CLK48CLKSOURCE_PLLSAIP
#define RCC_CK48CLKSOURCE_PLLI2SQ RCC_CLK48CLKSOURCE_PLLI2SQ
#define IS_RCC_CK48CLKSOURCE IS_RCC_CLK48CLKSOURCE
#define RCC_SDIOCLKSOURCE_CK48 RCC_SDIOCLKSOURCE_CLK48
#define __HAL_RCC_DFSDM_CLK_ENABLE __HAL_RCC_DFSDM1_CLK_ENABLE
#define __HAL_RCC_DFSDM_CLK_DISABLE __HAL_RCC_DFSDM1_CLK_DISABLE
#define __HAL_RCC_DFSDM_IS_CLK_ENABLED __HAL_RCC_DFSDM1_IS_CLK_ENABLED
#define __HAL_RCC_DFSDM_IS_CLK_DISABLED __HAL_RCC_DFSDM1_IS_CLK_DISABLED
#define __HAL_RCC_DFSDM_FORCE_RESET __HAL_RCC_DFSDM1_FORCE_RESET
#define __HAL_RCC_DFSDM_RELEASE_RESET __HAL_RCC_DFSDM1_RELEASE_RESET
#define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE
#define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE
#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED
#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED
#define DfsdmClockSelection Dfsdm1ClockSelection
#define RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1
#define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK
#define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK
#define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG
#define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE
/**
* @}
*/
@ -2891,6 +3061,8 @@
#define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER
#define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE
#define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE
#define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1
/**
* @}
*/

12
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal.c
* @author MCD Application Team
* @version V1.3.1
* @date 29-January-2016
* @version V1.4.0
* @date 27-May-2016
* @brief HAL module driver.
* This is the common part of the HAL initialization
*
@ -70,11 +70,11 @@
* @{
*/
/**
* @brief STM32F0xx HAL Driver version number V1.3.1
* @brief STM32F0xx HAL Driver version number V1.4.0
*/
#define __STM32F0xx_HAL_VERSION_MAIN (0x01) /*!< [31:24] main version */
#define __STM32F0xx_HAL_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
#define __STM32F0xx_HAL_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */
#define __STM32F0xx_HAL_VERSION_SUB1 (0x04) /*!< [23:16] sub1 version */
#define __STM32F0xx_HAL_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32F0xx_HAL_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F0xx_HAL_VERSION ((__STM32F0xx_HAL_VERSION_MAIN << 24)\
|(__STM32F0xx_HAL_VERSION_SUB1 << 16)\
@ -98,7 +98,7 @@
/** @defgroup HAL_Private_Variables HAL Private Variables
* @{
*/
static __IO uint32_t uwTick;
__IO uint32_t uwTick;
/**
* @}
*/

4
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal.h
* @author MCD Application Team
* @version V1.3.1
* @date 29-January-2016
* @version V1.4.0
* @date 27-May-2016
* @brief This file contains all the functions prototypes for the HAL
* module driver.
******************************************************************************

4
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_adc.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_adc.c
* @author MCD Application Team
* @version V1.3.1
* @date 29-January-2016
* @version V1.4.0
* @date 27-May-2016
* @brief This file provides firmware functions to manage the following
* functionalities of the Analog to Digital Convertor (ADC)
* peripheral:

4
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_adc.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_adc.h
* @author MCD Application Team
* @version V1.3.1
* @date 29-January-2016
* @version V1.4.0
* @date 27-May-2016
* @brief Header file containing functions prototypes of ADC HAL library.
******************************************************************************
* @attention

4
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_adc_ex.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_adc_ex.c
* @author MCD Application Team
* @version V1.3.1
* @date 29-January-2016
* @version V1.4.0
* @date 27-May-2016
* @brief This file provides firmware functions to manage the following
* functionalities of the Analog to Digital Convertor (ADC)
* peripheral:

4
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_adc_ex.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_adc_ex.h
* @author MCD Application Team
* @version V1.3.1
* @date 29-January-2016
* @version V1.4.0
* @date 27-May-2016
* @brief Header file of ADC HAL Extension module.
******************************************************************************
* @attention

4
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_can.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_can.c
* @author MCD Application Team
* @version V1.3.1
* @date 29-January-2016
* @version V1.4.0
* @date 27-May-2016
* @brief CAN HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Controller Area Network (CAN) peripheral:

8
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_can.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_can.h
* @author MCD Application Team
* @version V1.3.1
* @date 29-January-2016
* @version V1.4.0
* @date 27-May-2016
* @brief Header file of CAN HAL module.
******************************************************************************
* @attention
@ -234,7 +234,7 @@ typedef struct
__IO HAL_CAN_StateTypeDef State; /*!< CAN communication state */
__IO uint32_t ErrorCode; /*!< CAN Error code
This parameter can be a value of @ref HAL_CAN_Error_Code */
This parameter can be a value of @ref CAN_Error_Code */
}CAN_HandleTypeDef;
/**
@ -247,7 +247,7 @@ typedef struct
* @{
*/
/** @defgroup HAL_CAN_Error_Code CAN Error Code
/** @defgroup CAN_Error_Code CAN Error Code
* @{
*/
#define HAL_CAN_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */

4
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_cec.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_cec.c
* @author MCD Application Team
* @version V1.3.1
* @date 29-January-2016
* @version V1.4.0
* @date 27-May-2016
* @brief CEC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the High Definition Multimedia Interface

4
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_cec.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_cec.h
* @author MCD Application Team
* @version V1.3.1
* @date 29-January-2016
* @version V1.4.0
* @date 27-May-2016
* @brief Header file of CEC HAL module.
******************************************************************************
* @attention

133
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_comp.c
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_comp.c
* @author MCD Application Team
* @version V1.3.1
* @date 29-January-2016
* @version V1.4.0
* @date 27-May-2016
* @brief COMP HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the COMP peripheral:
@ -19,14 +19,12 @@
[..]
The STM32F0xx device family integrates up to 2 analog comparators COMP1 and COMP2:
(+) The non inverting input and inverting input can be set to GPIO pins
as shown in table1. COMP Inputs below.
(+) The non inverting input and inverting input can be set to GPIO pins.
(+) The COMP output is available using HAL_COMP_GetOutputLevel()
and can be set on GPIO pins. Refer to table 2. COMP Outputs below.
(+) The COMP output is available using HAL_COMP_GetOutputLevel()
and can be set on GPIO pins.
(+) The COMP output can be redirected to embedded timers (TIM1, TIM2 and TIM3)
Refer to table 3. COMP Outputs redirection to embedded timers below.
(+) The COMP output can be redirected to embedded timers (TIM1, TIM2 and TIM3).
(+) The comparators COMP1 and COMP2 can be combined in window mode.
@ -39,50 +37,6 @@
macros __HAL_COMP_COMP1_EXTI_GET_FLAG() and __HAL_COMP_COMP2_EXTI_GET_FLAG().
[..] Table 1. COMP Inputs for the STM32F05x, STM32F07x and STM32F09x devices
+--------------------------------------------------+
| | | COMP1 | COMP2 |
|-----------------|----------------|---------------|
| | 1/4 VREFINT | OK | OK |
| | 1/2 VREFINT | OK | OK |
| | 3/4 VREFINT | OK | OK |
| Inverting Input | VREFINT | OK | OK |
| | DAC1 OUT (PA4) | OK | OK |
| | DAC2 OUT (PA5) | OK | OK |
| | IO1 | PA0 | PA2 |
|-----------------|----------------|-------|-------|
| Non Inverting | | PA1 | PA3 |
| Input | | | |
+--------------------------------------------------+
[..] Table 2. COMP Outputs for the STM32F05x, STM32F07x and STM32F09x devices
+---------------+
| COMP1 | COMP2 |
|-------|-------|
| PA0 | PA2 |
| PA6 | PA7 |
| PA11 | PA12 |
+---------------+
[..] Table 3. COMP Outputs redirection to embedded timers for the STM32F05x, STM32F07x and STM32F09x devices
+---------------------------------+
| COMP1 | COMP2 |
|----------------|----------------|
| TIM1 BKIN | TIM1 BKIN |
| | |
| TIM1 OCREFCLR | TIM1 OCREFCLR |
| | |
| TIM1 IC1 | TIM1 IC1 |
| | |
| TIM2 IC4 | TIM2 IC4 |
| | |
| TIM2 OCREFCLR | TIM2 OCREFCLR |
| | |
| TIM3 IC1 | TIM3 IC1 |
| | |
| TIM3 OCREFCLR | TIM3 OCREFCLR |
+---------------------------------+
##### How to use this driver #####
================================================================================
[..]
@ -155,6 +109,55 @@
******************************************************************************
*/
/*
Additional Tables:
Table 1. COMP Inputs for the STM32F05x, STM32F07x and STM32F09x devices
+--------------------------------------------------+
| | | COMP1 | COMP2 |
|-----------------|----------------|---------------|
| | 1/4 VREFINT | OK | OK |
| | 1/2 VREFINT | OK | OK |
| | 3/4 VREFINT | OK | OK |
| Inverting Input | VREFINT | OK | OK |
| | DAC1 OUT (PA4) | OK | OK |
| | DAC2 OUT (PA5) | OK | OK |
| | IO1 | PA0 | PA2 |
|-----------------|----------------|-------|-------|
| Non Inverting | | PA1 | PA3 |
| Input | | | |
+--------------------------------------------------+
Table 2. COMP Outputs for the STM32F05x, STM32F07x and STM32F09x devices
+---------------+
| COMP1 | COMP2 |
|-------|-------|
| PA0 | PA2 |
| PA6 | PA7 |
| PA11 | PA12 |
+---------------+
Table 3. COMP Outputs redirection to embedded timers for the STM32F05x, STM32F07x and STM32F09x devices
+---------------------------------+
| COMP1 | COMP2 |
|----------------|----------------|
| TIM1 BKIN | TIM1 BKIN |
| | |
| TIM1 OCREFCLR | TIM1 OCREFCLR |
| | |
| TIM1 IC1 | TIM1 IC1 |
| | |
| TIM2 IC4 | TIM2 IC4 |
| | |
| TIM2 OCREFCLR | TIM2 OCREFCLR |
| | |
| TIM3 IC1 | TIM3 IC1 |
| | |
| TIM3 OCREFCLR | TIM3 OCREFCLR |
+---------------------------------+
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f0xx_hal.h"
@ -175,9 +178,18 @@
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/** @defgroup COMP_Private_Constants COMP Private Constants
* @{
*/
/* Delay for COMP startup time. */
/* Note: Delay required to reach propagation delay specification. */
/* Literal set to maximum value (refer to device datasheet, */
/* parameter "tSTART"). */
/* Unit: us */
#define LL_COMP_DELAY_STARTUP_US ((uint32_t) 60U) /*!< Delay for COMP startup time */
/* CSR register reset value */
#define COMP_CSR_RESET_VALUE ((uint32_t)0x00000000)
/* CSR register masks */
@ -222,7 +234,7 @@
* @retval HAL status
*/
HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp)
{
{
HAL_StatusTypeDef status = HAL_OK;
uint32_t regshift = COMP_CSR_COMP1_SHIFT;
@ -399,6 +411,7 @@ __weak void HAL_COMP_MspDeInit(COMP_HandleTypeDef *hcomp)
*/
HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp)
{
uint32_t wait_loop_index = 0;
HAL_StatusTypeDef status = HAL_OK;
uint32_t regshift = COMP_CSR_COMP1_SHIFT;
@ -420,8 +433,16 @@ HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp)
regshift = COMP_CSR_COMP2_SHIFT;
}
SET_BIT(COMP->CSR, COMP_CSR_COMPxEN << regshift);
hcomp->State = HAL_COMP_STATE_BUSY;
/* Set HAL COMP handle state */
hcomp->State = HAL_COMP_STATE_BUSY;
/* Delay for COMP startup time */
wait_loop_index = (LL_COMP_DELAY_STARTUP_US * (SystemCoreClock / 1000000));
while(wait_loop_index != 0)
{
wait_loop_index--;
}
}
else
{
@ -478,7 +499,7 @@ HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp)
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_COMP_Start_IT(COMP_HandleTypeDef *hcomp)
{
{
HAL_StatusTypeDef status = HAL_OK;
uint32_t extiline = 0;

4
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_comp.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_comp.h
* @author MCD Application Team
* @version V1.3.1
* @date 29-January-2016
* @version V1.4.0
* @date 27-May-2016
* @brief Header file of COMP HAL module.
******************************************************************************
* @attention

8
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_conf.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_conf.h
* @author MCD Application Team
* @version V1.3.1
* @date 29-January-2016
* @version V1.4.0
* @date 27-May-2016
* @brief HAL configuration file.
******************************************************************************
* @attention
@ -296,11 +296,11 @@
* If expr is true, it returns no value.
* @retval None
*/
#define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
/* Exported functions ------------------------------------------------------- */
void assert_failed(uint8_t* file, uint32_t line);
#else
#define assert_param(expr) ((void)0)
#define assert_param(expr) ((void)0U)
#endif /* USE_FULL_ASSERT */
#ifdef __cplusplus

4
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_cortex.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_cortex.c
* @author MCD Application Team
* @version V1.3.1
* @date 29-January-2016
* @version V1.4.0
* @date 27-May-2016
* @brief CORTEX HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the CORTEX:

4
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_cortex.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_cortex.h
* @author MCD Application Team
* @version V1.3.1
* @date 29-January-2016
* @version V1.4.0
* @date 27-May-2016
* @brief Header file of CORTEX HAL module.
******************************************************************************
* @attention

7
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_crc.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_crc.c
* @author MCD Application Team
* @version V1.3.1
* @date 29-January-2016
* @version V1.4.0
* @date 27-May-2016
* @brief CRC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Cyclic Redundancy Check (CRC) peripheral:
@ -204,6 +204,9 @@ HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc)
/* Change CRC peripheral state */
hcrc->State = HAL_CRC_STATE_BUSY;
/* Reset IDR register content */
CLEAR_BIT(hcrc->Instance->IDR, CRC_IDR_IDR) ;
/* DeInit the low level hardware */
HAL_CRC_MspDeInit(hcrc);

10
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_crc.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_crc.h
* @author MCD Application Team
* @version V1.3.1
* @date 29-January-2016
* @version V1.4.0
* @date 27-May-2016
* @brief Header file of CRC HAL module.
******************************************************************************
* @attention
@ -166,11 +166,17 @@ typedef struct
/** @defgroup CRC_Default_Polynomial Indicates whether or not default polynomial is used
* @{
*/
#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx)
#define DEFAULT_POLYNOMIAL_ENABLE ((uint8_t)0x00)
#define DEFAULT_POLYNOMIAL_DISABLE ((uint8_t)0x01)
#define IS_DEFAULT_POLYNOMIAL(DEFAULT) (((DEFAULT) == DEFAULT_POLYNOMIAL_ENABLE) || \
((DEFAULT) == DEFAULT_POLYNOMIAL_DISABLE))
#else
#define DEFAULT_POLYNOMIAL_ENABLE ((uint8_t)0x00)
#define IS_DEFAULT_POLYNOMIAL(DEFAULT) ((DEFAULT) == DEFAULT_POLYNOMIAL_ENABLE)
#endif /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) */
/**
* @}

4
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_crc_ex.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_crc_ex.c
* @author MCD Application Team
* @version V1.3.1
* @date 29-January-2016
* @version V1.4.0
* @date 27-May-2016
* @brief Extended CRC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the CRC peripheral:

14
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_crc_ex.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_crc_ex.h
* @author MCD Application Team
* @version V1.3.1
* @date 29-January-2016
* @version V1.4.0
* @date 27-May-2016
* @brief Header file of CRC HAL extension module.
******************************************************************************
* @attention
@ -117,7 +117,7 @@
#define HAL_CRC_LENGTH_7B 7
#else
#define HAL_CRC_LENGTH_32B 32
#endif /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) */
#endif /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) */
/**
* @}
*/
@ -145,7 +145,7 @@
*/
#define __HAL_CRC_OUTPUTREVERSAL_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(CRC_CR_REV_OUT))
#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC)
#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx)
/**
* @brief Set CRC non-default polynomial
* @param __HANDLE__ : CRC handle
@ -153,7 +153,7 @@
* @retval None.
*/
#define __HAL_CRC_POLYNOMIAL_CONFIG(__HANDLE__, __POLYNOMIAL__) ((__HANDLE__)->Instance->POL = (__POLYNOMIAL__))
#endif /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC) */
#endif /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) */
/**
* @}
*/
@ -173,9 +173,9 @@ HAL_StatusTypeDef HAL_CRCEx_Init(CRC_HandleTypeDef *hcrc);
HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode);
HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode);
#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC)
#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx)
HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength);
#endif /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC) */
#endif /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) */
/**
* @}
*/

4
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dac.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_dac.c
* @author MCD Application Team
* @version V1.3.1
* @date 29-January-2016
* @version V1.4.0
* @date 27-May-2016
* @brief DAC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Digital to Analog Converter (DAC) peripheral:

4
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dac.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_dac.h
* @author MCD Application Team
* @version V1.3.1
* @date 29-January-2016
* @version V1.4.0
* @date 27-May-2016
* @brief Header file of DAC HAL module.
******************************************************************************
* @attention

4
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dac_ex.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_dac_ex.c
* @author MCD Application Team
* @version V1.3.1
* @date 29-January-2016
* @version V1.4.0
* @date 27-May-2016
* @brief DAC HAL module driver.
* This file provides firmware functions to manage the extended
* functionalities of the DAC peripheral.

4
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dac_ex.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_dac_ex.h
* @author MCD Application Team
* @version V1.3.1
* @date 29-January-2016
* @version V1.4.0
* @date 27-May-2016
* @brief Header file of DAC HAL Extension module.
******************************************************************************
* @attention

4
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_def.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_def.h
* @author MCD Application Team
* @version V1.3.1
* @date 29-January-2016
* @version V1.4.0
* @date 27-May-2016
* @brief This file contains HAL common defines, enumeration, macros and
* structures definitions.
******************************************************************************

67
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dma.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_dma.c
* @author MCD Application Team
* @version V1.3.1
* @date 29-January-2016
* @version V1.4.0
* @date 27-May-2016
* @brief DMA HAL module driver.
*
* This file provides firmware functions to manage the following
@ -247,21 +247,15 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
/* Check the parameters */
assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
/* Check the DMA peripheral state */
if(hdma->State == HAL_DMA_STATE_BUSY)
{
return HAL_ERROR;
}
/* Disable the selected DMA Channelx */
__HAL_DMA_DISABLE(hdma);
/* Reset DMA Channel control register */
hdma->Instance->CCR = 0;
/* Reset DMA Channel Number of Data to Transfer register */
hdma->Instance->CNDTR = 0;
/* Reset DMA Channel peripheral address register */
hdma->Instance->CPAR = 0;
@ -272,7 +266,7 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
/* Initialize the error code */
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
@ -430,6 +424,49 @@ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
return HAL_OK;
}
/**
* @brief Aborts the DMA Transfer in Interrupt mode.
* @param hdma : pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
{
HAL_StatusTypeDef status = HAL_OK;
if(HAL_DMA_STATE_BUSY != hdma->State)
{
/* no transfer ongoing */
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
status = HAL_ERROR;
}
else
{
/* Disable DMA IT */
__HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
/* Disable the channel */
__HAL_DMA_DISABLE(hdma);
/* Clear all flags */
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_GI_FLAG_INDEX(hdma));
/* Change the DMA state */
hdma->State = HAL_DMA_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hdma);
/* Call User Abort callback */
if(hdma->XferAbortCallback != NULL)
{
hdma->XferAbortCallback(hdma);
}
}
return status;
}
/**
* @brief Polling for transfer complete.
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
@ -549,7 +586,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
/* Process Unlocked */
__HAL_UNLOCK(hdma);
if (hdma->XferErrorCallback != (void (*)(DMA_HandleTypeDef *))NULL)
if(hdma->XferErrorCallback != NULL)
{
/* Transfer error callback */
hdma->XferErrorCallback(hdma);
@ -574,7 +611,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
/* Change DMA peripheral state */
hdma->State = HAL_DMA_STATE_READY_HALF;
if(hdma->XferHalfCpltCallback != (void (*)(DMA_HandleTypeDef *))NULL)
if(hdma->XferHalfCpltCallback != NULL)
{
/* Half transfer callback */
hdma->XferHalfCpltCallback(hdma);
@ -604,7 +641,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
/* Process Unlocked */
__HAL_UNLOCK(hdma);
if(hdma->XferCpltCallback != (void (*)(DMA_HandleTypeDef *))NULL)
if(hdma->XferCpltCallback != NULL)
{
/* Transfer complete callback */
hdma->XferCpltCallback(hdma);

22
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dma.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_dma.h
* @author MCD Application Team
* @version V1.3.1
* @date 29-January-2016
* @version V1.4.0
* @date 27-May-2016
* @brief Header file of DMA HAL module.
******************************************************************************
* @attention
@ -143,6 +143,8 @@ typedef struct __DMA_HandleTypeDef
void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */
void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer abort callback */
__IO uint32_t ErrorCode; /*!< DMA Error code */
} DMA_HandleTypeDef;
@ -159,9 +161,10 @@ typedef struct __DMA_HandleTypeDef
/** @defgroup DMA_Error_Code DMA Error Code
* @{
*/
#define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
#define HAL_DMA_ERROR_TE ((uint32_t)0x00000001) /*!< Transfer error */
#define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */
#define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
#define HAL_DMA_ERROR_TE ((uint32_t)0x00000001) /*!< Transfer error */
#define HAL_DMA_ERROR_NO_XFER ((uint32_t)0x00000004) /*!< no ongoin transfer */
#define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */
/**
* @}
*/
@ -414,6 +417,14 @@ typedef struct __DMA_HandleTypeDef
*/
#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CCR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
/**
* @brief Returns the number of remaining data units in the current DMAy Channelx transfer.
* @param __HANDLE__: DMA handle
*
* @retval The number of remaining data units in the current DMA Channel transfer.
*/
#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR)
#if defined(SYSCFG_CFGR1_DMA_RMP)
/** @brief DMA remapping enable/disable macros
* @param __DMA_REMAP__: This parameter can be a value of @ref HAL_DMA_remapping
@ -455,6 +466,7 @@ HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma);
HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout);
void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
/**

49
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dma_ex.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_dma_ex.h
* @author MCD Application Team
* @version V1.3.1
* @date 29-January-2016
* @version V1.4.0
* @date 27-May-2016
* @brief Header file of DMA HAL Extension module.
******************************************************************************
* @attention
@ -563,6 +563,20 @@
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
DMA_FLAG_TE7)
/**
* @brief Return the current DMA Channel Global interrupt flag.
* @param __HANDLE__: DMA handle
* @retval The specified transfer error flag index.
*/
#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GL1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GL2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GL3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GL4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_GL5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_GL6 :\
DMA_FLAG_GL7)
/**
* @brief Get the DMA Channel pending flags.
* @param __HANDLE__: DMA handle
@ -648,6 +662,25 @@
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\
DMA_FLAG_TE5)
/**
* @brief Return the current DMA Channel Global interrupt flag.
* @param __HANDLE__: DMA handle
* @retval The specified transfer error flag index.
*/
#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GL1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GL2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GL3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GL4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_GL5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_GL6 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_GL7 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_GL1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_GL2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_GL3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_GL4 :\
DMA_FLAG_GL5)
/**
* @brief Get the DMA Channel pending flags.
* @param __HANDLE__: DMA handle
@ -716,6 +749,18 @@
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
DMA_FLAG_TE5)
/**
* @brief Return the current DMA Channel Global interrupt flag.
* @param __HANDLE__: DMA handle
* @retval The specified transfer error flag index.
*/
#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GL1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GL2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GL3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GL4 :\
DMA_FLAG_GL5)
/**
* @brief Get the DMA Channel pending flags.
* @param __HANDLE__: DMA handle

83
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_flash.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_flash.c
* @author MCD Application Team
* @version V1.3.1
* @date 29-January-2016
* @version V1.4.0
* @date 27-May-2016
* @brief FLASH HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the internal FLASH memory:
@ -41,7 +41,6 @@
(++) Lock and Unlock the FLASH interface
(++) Erase function: Erase page, erase all pages
(++) Program functions: half word, word and doubleword
(#) FLASH Option Bytes Programming functions: this group includes all needed
functions to manage the Option Bytes:
(++) Lock and Unlock the Option Bytes
@ -58,7 +57,7 @@
includes all needed functions to:
(++) Handle FLASH interrupts
(++) Wait for last FLASH operation according to its status
(++) Get error flag status
(++) Get error flag status
[..] In addition to these function, this driver includes a set of macros allowing
to handle the following operations:
@ -147,6 +146,7 @@ FLASH_ProcessTypeDef pFlash;
*/
static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data);
static void FLASH_SetErrorCode(void);
extern void FLASH_PageErase(uint32_t PageAddress);
/**
* @}
*/
@ -196,7 +196,7 @@ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint
assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
if(status == HAL_OK)
{
@ -221,7 +221,7 @@ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint
FLASH_Program_HalfWord((Address + (2*index)), (uint16_t)(Data >> (16*index)));
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
/* If the program operation is completed, disable the PG Bit */
CLEAR_BIT(FLASH->CR, FLASH_CR_PG);
@ -274,23 +274,23 @@ HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, u
if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD)
{
pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMHALFWORD;
/*Program halfword (16-bit) at a specified address.*/
/* Program halfword (16-bit) at a specified address. */
pFlash.DataRemaining = 1;
}
else if(TypeProgram == FLASH_TYPEPROGRAM_WORD)
{
pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMWORD;
/*Program word (32-bit : 2*16-bit) at a specified address.*/
/* Program word (32-bit : 2*16-bit) at a specified address. */
pFlash.DataRemaining = 2;
}
else
{
pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMDOUBLEWORD;
/*Program double word (64-bit : 4*16-bit) at a specified address.*/
/* Program double word (64-bit : 4*16-bit) at a specified address. */
pFlash.DataRemaining = 4;
}
/*Program halfword (16-bit) at a specified address.*/
/* Program halfword (16-bit) at a specified address. */
FLASH_Program_HalfWord(Address, (uint16_t)Data);
return status;
@ -307,18 +307,18 @@ void HAL_FLASH_IRQHandler(void)
/* Check FLASH operation error flags */
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) ||__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR))
{
/*return the faulty address*/
/* Return the faulty address */
addresstmp = pFlash.Address;
/* Reset address */
pFlash.Address = 0xFFFFFFFFU;
/*Save the Error code*/
/* Save the Error code */
FLASH_SetErrorCode();
/* FLASH error interrupt user callback */
HAL_FLASH_OperationErrorCallback(addresstmp);
/* Stop the procedure ongoing*/
/* Stop the procedure ongoing */
pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
}
@ -336,11 +336,11 @@ void HAL_FLASH_IRQHandler(void)
/* Nb of pages to erased can be decreased */
pFlash.DataRemaining--;
/* Check if there are still pages to erase*/
/* Check if there are still pages to erase */
if(pFlash.DataRemaining != 0)
{
addresstmp = pFlash.Address;
/*Indicate user which sector has been erased*/
/*Indicate user which sector has been erased */
HAL_FLASH_EndOfOperationCallback(addresstmp);
/*Increment sector number*/
@ -354,8 +354,8 @@ void HAL_FLASH_IRQHandler(void)
}
else
{
/*No more pages to Erase, user callback can be called.*/
/*Reset Sector and stop Erase pages procedure*/
/* No more pages to Erase, user callback can be called. */
/* Reset Sector and stop Erase pages procedure */
pFlash.Address = addresstmp = 0xFFFFFFFFU;
pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
/* FLASH EOP interrupt user callback */
@ -367,7 +367,7 @@ void HAL_FLASH_IRQHandler(void)
/* Operation is completed, disable the MER Bit */
CLEAR_BIT(FLASH->CR, FLASH_CR_MER);
/* MassErase ended. Return the selected bank*/
/* MassErase ended. Return the selected bank */
/* FLASH EOP interrupt user callback */
HAL_FLASH_EndOfOperationCallback(0);
@ -397,7 +397,7 @@ void HAL_FLASH_IRQHandler(void)
}
else
{
/*Program ended. Return the selected address*/
/* Program ended. Return the selected address */
/* FLASH EOP interrupt user callback */
if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMHALFWORD)
{
@ -412,7 +412,7 @@ void HAL_FLASH_IRQHandler(void)
HAL_FLASH_EndOfOperationCallback(pFlash.Address - 6);
}
/* Reset Address and stop Program procedure*/
/* Reset Address and stop Program procedure */
pFlash.Address = 0xFFFFFFFFU;
pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
}
@ -434,7 +434,6 @@ void HAL_FLASH_IRQHandler(void)
}
}
/**
* @brief FLASH end of operation interrupt callback
* @param ReturnValue: The value saved in this parameter depends on the ongoing procedure
@ -520,11 +519,9 @@ HAL_StatusTypeDef HAL_FLASH_Lock(void)
/* Set the LOCK Bit to lock the FLASH Registers access */
SET_BIT(FLASH->CR, FLASH_CR_LOCK);
return HAL_OK;
}
/**
* @brief Unlock the FLASH Option Control Registers access.
* @retval HAL Status
@ -560,7 +557,7 @@ HAL_StatusTypeDef HAL_FLASH_OB_Lock(void)
/**
* @brief Launch the option byte loading.
* @note This function will reset automatically the MCU.
* @retval HAL_StatusTypeDef HAL Status
* @retval HAL Status
*/
HAL_StatusTypeDef HAL_FLASH_OB_Launch(void)
{
@ -568,22 +565,22 @@ HAL_StatusTypeDef HAL_FLASH_OB_Launch(void)
SET_BIT(FLASH->CR, FLASH_CR_OBL_LAUNCH);
/* Wait for last operation to be completed */
return(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE));
return(FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE));
}
/**
* @}
*/
/** @defgroup FLASH_Exported_Functions_Group3 Peripheral State functions
* @brief Peripheral State functions
/** @defgroup FLASH_Exported_Functions_Group3 Peripheral errors functions
* @brief Peripheral errors functions
*
@verbatim
===============================================================================
##### Peripheral State functions #####
##### Peripheral Errors functions #####
===============================================================================
[..]
This subsection permit to get in run-time the status of the FLASH peripheral.
This subsection permit to get in run-time errors of the FLASH peripheral.
@endverbatim
* @{
@ -591,13 +588,14 @@ HAL_StatusTypeDef HAL_FLASH_OB_Launch(void)
/**
* @brief Get the specific FLASH error flag.
* @retval FLASH_ErrorCode: The returned value can be:
* @retval FLASH_ErrorCode The returned value can be:
* @ref FLASH_Error_Codes
*/
uint32_t HAL_FLASH_GetError(void)
{
{
return pFlash.ErrorCode;
}
}
/**
* @}
*/
@ -612,8 +610,8 @@ uint32_t HAL_FLASH_GetError(void)
/**
* @brief Program a half-word (16-bit) at a specified address.
* @param Address: specifies the address to be programmed.
* @param Data: specifies the data to be programmed.
* @param Address specify the address to be programmed.
* @param Data specify the data to be programmed.
* @retval None
*/
static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data)
@ -630,8 +628,8 @@ static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data)
/**
* @brief Wait for a FLASH operation to complete.
* @param Timeout: maximum flash operation timeout
* @retval HAL_StatusTypeDef HAL Status
* @param Timeout maximum flash operation timeout
* @retval HAL Status
*/
HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)
{
@ -667,7 +665,7 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)
return HAL_ERROR;
}
/* If there is no error flag set */
/* There is no error flag set */
return HAL_OK;
}
@ -677,18 +675,21 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)
* @retval None
*/
static void FLASH_SetErrorCode(void)
{
{
uint32_t flags = 0;
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR))
{
pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP;
flags |= FLASH_FLAG_WRPERR;
}
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR))
{
pFlash.ErrorCode |= HAL_FLASH_ERROR_PROG;
pFlash.ErrorCode |= HAL_FLASH_ERROR_PROG;
flags |= FLASH_FLAG_PGERR;
}
/* Clear FLASH error pending bits */
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_WRPERR | FLASH_FLAG_PGERR);
__HAL_FLASH_CLEAR_FLAG(flags);
}
/**
* @}

22
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_flash.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_flash.h
* @author MCD Application Team
* @version V1.3.1
* @date 29-January-2016
* @version V1.4.0
* @date 27-May-2016
* @brief Header file of Flash HAL module.
******************************************************************************
* @attention
@ -57,7 +57,7 @@
/** @addtogroup FLASH_Private_Constants
* @{
*/
#define FLASH_TIMEOUT_VALUE ((uint32_t)50000)/* 50 s */
#define FLASH_TIMEOUT_VALUE ((uint32_t)50000U) /* 50 s */
/**
* @}
*/
@ -82,7 +82,6 @@
* @{
*/
/**
* @brief FLASH Procedure structure definition
*/
@ -128,9 +127,9 @@ typedef struct
* @{
*/
#define HAL_FLASH_ERROR_NONE ((uint32_t)0x00) /*!< No error */
#define HAL_FLASH_ERROR_PROG ((uint32_t)0x01) /*!< Programming error */
#define HAL_FLASH_ERROR_WRP ((uint32_t)0x02) /*!< Write protection error */
#define HAL_FLASH_ERROR_NONE 0x00U /*!< No error */
#define HAL_FLASH_ERROR_PROG 0x01U /*!< Programming error */
#define HAL_FLASH_ERROR_WRP 0x02U /*!< Write protection error */
/**
* @}
@ -139,9 +138,9 @@ typedef struct
/** @defgroup FLASH_Type_Program FLASH Type Program
* @{
*/
#define FLASH_TYPEPROGRAM_HALFWORD ((uint32_t)0x01) /*!<Program a half-word (16-bit) at a specified address.*/
#define FLASH_TYPEPROGRAM_WORD ((uint32_t)0x02) /*!<Program a word (32-bit) at a specified address.*/
#define FLASH_TYPEPROGRAM_DOUBLEWORD ((uint32_t)0x03) /*!<Program a double word (64-bit) at a specified address*/
#define FLASH_TYPEPROGRAM_HALFWORD ((uint32_t)0x01U) /*!<Program a half-word (16-bit) at a specified address.*/
#define FLASH_TYPEPROGRAM_WORD ((uint32_t)0x02U) /*!<Program a word (32-bit) at a specified address.*/
#define FLASH_TYPEPROGRAM_DOUBLEWORD ((uint32_t)0x03U) /*!<Program a double word (64-bit) at a specified address*/
/**
* @}
@ -150,7 +149,7 @@ typedef struct
/** @defgroup FLASH_Latency FLASH Latency
* @{
*/
#define FLASH_LATENCY_0 ((uint32_t)0x00000000) /*!< FLASH Zero Latency cycle */
#define FLASH_LATENCY_0 ((uint32_t)0x00000000U) /*!< FLASH Zero Latency cycle */
#define FLASH_LATENCY_1 FLASH_ACR_LATENCY /*!< FLASH One Latency cycle */
/**
@ -348,7 +347,6 @@ uint32_t HAL_FLASH_GetError(void);
/** @addtogroup FLASH_Private_Functions
* @{
*/
void FLASH_PageErase(uint32_t PageAddress);
HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
/**

7
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_flash_ex.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_flash_ex.c
* @author MCD Application Team
* @version V1.3.1
* @date 29-January-2016
* @version V1.4.0
* @date 27-May-2016
* @brief Extended FLASH HAL module driver.
*
* This file provides firmware functions to manage the following
@ -113,6 +113,7 @@ extern FLASH_ProcessTypeDef pFlash;
*/
/* Erase operations */
static void FLASH_MassErase(void);
void FLASH_PageErase(uint32_t PageAddress);
/* Option bytes control */
static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage);
@ -912,7 +913,7 @@ static uint32_t FLASH_OB_GetWRP(void)
/**
* @brief Returns the FLASH Read Protection level.
* @retval FLASH ReadOut Protection Status:
* @retval FLASH RDP level
* This parameter can be one of the following values:
* @arg @ref OB_RDP_LEVEL_0 No protection
* @arg @ref OB_RDP_LEVEL_1 Read protection of the memory

10
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_flash_ex.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_flash_ex.h
* @author MCD Application Team
* @version V1.3.1
* @date 29-January-2016
* @version V1.4.0
* @date 27-May-2016
* @brief Header file of Flash HAL Extended module.
******************************************************************************
* @attention
@ -235,15 +235,15 @@ typedef struct
#if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx) \
|| defined(STM32F051x8) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F058xx) || defined(STM32F070x6)
#define OB_WRP_PAGES0TO31MASK ((uint32_t)0x000000FF)
#define OB_WRP_PAGES0TO31MASK ((uint32_t)0x000000FFU)
#endif /* STM32F030x6 || STM32F030x8 || STM32F031x6 || STM32F051x8 || STM32F042x6 || STM32F048xx || STM32F038xx || STM32F058xx || STM32F070x6 */
#if defined(STM32F030x8) || defined(STM32F051x8) || defined(STM32F058xx)
#define OB_WRP_PAGES32TO63MASK ((uint32_t)0x0000FF00)
#define OB_WRP_PAGES32TO63MASK ((uint32_t)0x0000FF00U)
#endif /* STM32F030x8 || STM32F051x8 || STM32F058xx */
#if defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F038xx)|| defined(STM32F070x6)
#define OB_WRP_ALLPAGES ((uint32_t)0x000000FF) /*!< Write protection of all pages */
#define OB_WRP_ALLPAGES ((uint32_t)0x000000FFU) /*!< Write protection of all pages */
#endif /* STM32F030x6 || STM32F031x6 || STM32F042x6 || STM32F048xx || STM32F038xx || STM32F070x6 */
#if defined(STM32F030x8) || defined(STM32F051x8) || defined(STM32F058xx)

12
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_gpio.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_gpio.c
* @author MCD Application Team
* @version V1.3.1
* @date 29-January-2016
* @version V1.4.0
* @date 27-May-2016
* @brief GPIO HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the General Purpose Input/Output (GPIO) peripheral:
@ -198,10 +198,10 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
/* Configure the port pins */
while ((GPIO_Init->Pin) >> position)
while (((GPIO_Init->Pin) >> position) != RESET)
{
/* Get current io position */
iocurrent = (GPIO_Init->Pin) & (1 << position);
iocurrent = (GPIO_Init->Pin) & (1U << position);
if(iocurrent)
{
@ -321,10 +321,10 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
assert_param(IS_GPIO_PIN(GPIO_Pin));
/* Configure the port pins */
while (GPIO_Pin >> position)
while ((GPIO_Pin >> position) != RESET)
{
/* Get current io position */
iocurrent = (GPIO_Pin) & (1 << position);
iocurrent = GPIO_Pin & (1U << position);
if (iocurrent)
{

7
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_gpio.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_gpio.h
* @author MCD Application Team
* @version V1.3.1
* @date 29-January-2016
* @version V1.4.0
* @date 27-May-2016
* @brief Header file of GPIO HAL module.
******************************************************************************
* @attention
@ -229,7 +229,8 @@ typedef enum
*/
#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
#define IS_GPIO_PIN(__PIN__) (((__PIN__) & GPIO_PIN_MASK) != (uint32_t)0x00)
#define IS_GPIO_PIN(__PIN__) ((((__PIN__) & GPIO_PIN_MASK) != (uint32_t)0x00) &&\
(((__PIN__) & ~GPIO_PIN_MASK) == (uint32_t)0x00))
#define IS_GPIO_MODE(__MODE__) (((__MODE__) == GPIO_MODE_INPUT) ||\
((__MODE__) == GPIO_MODE_OUTPUT_PP) ||\

4
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_gpio_ex.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_gpio_ex.h
* @author MCD Application Team
* @version V1.3.1
* @date 29-January-2016
* @version V1.4.0
* @date 27-May-2016
* @brief Header file of GPIO HAL Extension module.
******************************************************************************
* @attention

4267
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_i2c.c
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File diff suppressed because it is too large Load Diff

472
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_i2c.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_i2c.h
* @author MCD Application Team
* @version V1.3.1
* @date 29-January-2016
* @version V1.4.0
* @date 27-May-2016
* @brief Header file of I2C HAL module.
******************************************************************************
* @attention
@ -33,7 +33,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F0xx_HAL_I2C_H
@ -54,13 +54,13 @@
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup I2C_Exported_Types I2C Exported Types
* @{
*/
/** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition
* @brief I2C Configuration Structure definition
* @brief I2C Configuration Structure definition
* @{
*/
typedef struct
@ -73,43 +73,71 @@ typedef struct
This parameter can be a 7-bit or 10-bit address. */
uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected.
This parameter can be a value of @ref I2C_addressing_mode */
This parameter can be a value of @ref I2C_ADDRESSING_MODE */
uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected.
This parameter can be a value of @ref I2C_dual_addressing_mode */
This parameter can be a value of @ref I2C_DUAL_ADDRESSING_MODE */
uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected
This parameter can be a 7-bit address. */
uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address if dual addressing mode is selected
This parameter can be a value of @ref I2C_own_address2_masks */
This parameter can be a value of @ref I2C_OWN_ADDRESS2_MASKS */
uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected.
This parameter can be a value of @ref I2C_general_call_addressing_mode */
This parameter can be a value of @ref I2C_GENERAL_CALL_ADDRESSING_MODE */
uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected.
This parameter can be a value of @ref I2C_nostretch_mode */
This parameter can be a value of @ref I2C_NOSTRETCH_MODE */
}I2C_InitTypeDef;
/**
/**
* @}
*/
/** @defgroup HAL_state_structure_definition HAL state structure definition
* @brief HAL State structure definition
* @brief HAL State structure definition
* @note HAL I2C State value coding follow below described bitmap :\n
* b7-b6 Error information\n
* 00 : No Error\n
* 01 : Abort (Abort user request on going)\n
* 10 : Timeout\n
* 11 : Error\n
* b5 IP initilisation status\n
* 0 : Reset (IP not initialized)\n
* 1 : Init done (IP initialized and ready to use. HAL I2C Init function called)\n
* b4 (not used)\n
* x : Should be set to 0\n
* b3\n
* 0 : Ready or Busy (No Listen mode ongoing)\n
* 1 : Listen (IP in Address Listen Mode)\n
* b2 Intrinsic process state\n
* 0 : Ready\n
* 1 : Busy (IP busy with some configuration or internal operations)\n
* b1 Rx state\n
* 0 : Ready (no Rx operation ongoing)\n
* 1 : Busy (Rx operation ongoing)\n
* b0 Tx state\n
* 0 : Ready (no Tx operation ongoing)\n
* 1 : Busy (Tx operation ongoing)
* @{
*/
*/
typedef enum
{
HAL_I2C_STATE_RESET = 0x00, /*!< Peripheral is not yet Initialized */
HAL_I2C_STATE_READY = 0x20, /*!< Peripheral Initialized and ready for use */
HAL_I2C_STATE_BUSY = 0x24, /*!< An internal process is ongoing */
HAL_I2C_STATE_BUSY_TX = 0x21, /*!< Data Transmission process is ongoing */
HAL_I2C_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */
HAL_I2C_STATE_TIMEOUT = 0xA0, /*!< Timeout state */
HAL_I2C_STATE_ERROR = 0xE0 /*!< Error */
HAL_I2C_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */
HAL_I2C_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use */
HAL_I2C_STATE_BUSY = 0x24U, /*!< An internal process is ongoing */
HAL_I2C_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing */
HAL_I2C_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */
HAL_I2C_STATE_LISTEN = 0x28U, /*!< Address Listen Mode is ongoing */
HAL_I2C_STATE_BUSY_TX_LISTEN = 0x29U, /*!< Address Listen Mode and Data Transmission
process is ongoing */
HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception
process is ongoing */
HAL_I2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */
HAL_I2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */
HAL_I2C_STATE_ERROR = 0xE0U /*!< Error */
}HAL_I2C_StateTypeDef;
@ -119,61 +147,87 @@ typedef enum
/** @defgroup HAL_mode_structure_definition HAL mode structure definition
* @brief HAL Mode structure definition
* @note HAL I2C Mode value coding follow below described bitmap :\n
* b7 (not used)\n
* x : Should be set to 0\n
* b6\n
* 0 : None\n
* 1 : Memory (HAL I2C communication is in Memory Mode)\n
* b5\n
* 0 : None\n
* 1 : Slave (HAL I2C communication is in Slave Mode)\n
* b4\n
* 0 : None\n
* 1 : Master (HAL I2C communication is in Master Mode)\n
* b3-b2-b1-b0 (not used)\n
* xxxx : Should be set to 0000
* @{
*/
typedef enum
{
HAL_I2C_MODE_NONE = 0x00, /*!< No I2C communication on going */
HAL_I2C_MODE_MASTER = 0x10, /*!< I2C communication is in Master Mode */
HAL_I2C_MODE_SLAVE = 0x20, /*!< I2C communication is in Slave Mode */
HAL_I2C_MODE_MEM = 0x40 /*!< I2C communication is in Memory Mode */
HAL_I2C_MODE_NONE = 0x00U, /*!< No I2C communication on going */
HAL_I2C_MODE_MASTER = 0x10U, /*!< I2C communication is in Master Mode */
HAL_I2C_MODE_SLAVE = 0x20U, /*!< I2C communication is in Slave Mode */
HAL_I2C_MODE_MEM = 0x40U /*!< I2C communication is in Memory Mode */
}HAL_I2C_ModeTypeDef;
/**
* @}
*/
/** @defgroup I2C_Error_Code_definition I2C Error Code definition
* @brief I2C Error Code definition
* @brief I2C Error Code definition
* @{
*/
#define HAL_I2C_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
#define HAL_I2C_ERROR_BERR ((uint32_t)0x00000001) /*!< BERR error */
#define HAL_I2C_ERROR_ARLO ((uint32_t)0x00000002) /*!< ARLO error */
#define HAL_I2C_ERROR_AF ((uint32_t)0x00000004) /*!< ACKF error */
#define HAL_I2C_ERROR_OVR ((uint32_t)0x00000008) /*!< OVR error */
#define HAL_I2C_ERROR_DMA ((uint32_t)0x00000010) /*!< DMA transfer error */
#define HAL_I2C_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */
#define HAL_I2C_ERROR_SIZE ((uint32_t)0x00000040) /*!< Size Management error */
*/
#define HAL_I2C_ERROR_NONE (0x00000000U) /*!< No error */
#define HAL_I2C_ERROR_BERR (0x00000001U) /*!< BERR error */
#define HAL_I2C_ERROR_ARLO (0x00000002U) /*!< ARLO error */
#define HAL_I2C_ERROR_AF (0x00000004U) /*!< ACKF error */
#define HAL_I2C_ERROR_OVR (0x00000008U) /*!< OVR error */
#define HAL_I2C_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
#define HAL_I2C_ERROR_TIMEOUT (0x00000020U) /*!< Timeout error */
#define HAL_I2C_ERROR_SIZE (0x00000040U) /*!< Size Management error */
/**
* @}
*/
/** @defgroup I2C_handle_Structure_definition I2C handle Structure definition
* @brief I2C handle Structure definition
/** @defgroup I2C_handle_Structure_definition I2C handle Structure definition
* @brief I2C handle Structure definition
* @{
*/
typedef struct
*/
typedef struct __I2C_HandleTypeDef
{
I2C_TypeDef *Instance; /*!< I2C registers base address */
I2C_TypeDef *Instance; /*!< I2C registers base address */
I2C_InitTypeDef Init; /*!< I2C communication parameters */
I2C_InitTypeDef Init; /*!< I2C communication parameters */
uint8_t *pBuffPtr; /*!< Pointer to I2C transfer buffer */
uint8_t *pBuffPtr; /*!< Pointer to I2C transfer buffer */
uint16_t XferSize; /*!< I2C transfer size */
uint16_t XferSize; /*!< I2C transfer size */
__IO uint16_t XferCount; /*!< I2C transfer counter */
__IO uint16_t XferCount; /*!< I2C transfer counter */
DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */
__IO uint32_t XferOptions; /*!< I2C sequantial transfer options, this parameter can
be a value of @ref I2C_XFEROPTIONS */
DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */
__IO uint32_t PreviousState; /*!< I2C communication Previous state */
HAL_LockTypeDef Lock; /*!< I2C locking object */
HAL_StatusTypeDef (*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); /*!< I2C transfer IRQ handler function pointer */
__IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */
DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */
__IO HAL_I2C_ModeTypeDef Mode; /*!< I2C communication mode */
DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */
__IO uint32_t ErrorCode; /*!< I2C Error code */
HAL_LockTypeDef Lock; /*!< I2C locking object */
__IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */
__IO HAL_I2C_ModeTypeDef Mode; /*!< I2C communication mode */
__IO uint32_t ErrorCode; /*!< I2C Error code */
__IO uint32_t AddrEventCount; /*!< I2C Address Event counter */
}I2C_HandleTypeDef;
/**
* @}
@ -181,90 +235,111 @@ typedef struct
/**
* @}
*/
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup I2C_Exported_Constants I2C Exported Constants
* @{
*/
/** @defgroup I2C_addressing_mode I2C addressing mode
/** @defgroup I2C_XFEROPTIONS I2C Sequential Transfer Options
* @{
*/
#define I2C_ADDRESSINGMODE_7BIT ((uint32_t)0x00000001)
#define I2C_ADDRESSINGMODE_10BIT ((uint32_t)0x00000002)
#define I2C_NO_OPTION_FRAME (0xFFFF0000U)
#define I2C_FIRST_FRAME ((uint32_t)I2C_SOFTEND_MODE)
#define I2C_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
#define I2C_FIRST_AND_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)
#define I2C_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)
/**
* @}
*/
/** @defgroup I2C_dual_addressing_mode I2C dual addressing mode
/** @defgroup I2C_ADDRESSING_MODE I2C Addressing Mode
* @{
*/
#define I2C_DUALADDRESS_DISABLE ((uint32_t)0x00000000)
#define I2C_DUALADDRESS_ENABLE I2C_OAR2_OA2EN
#define I2C_ADDRESSINGMODE_7BIT (0x00000001U)
#define I2C_ADDRESSINGMODE_10BIT (0x00000002U)
/**
* @}
*/
/** @defgroup I2C_own_address2_masks I2C own address2 masks
/** @defgroup I2C_DUAL_ADDRESSING_MODE I2C Dual Addressing Mode
* @{
*/
#define I2C_OA2_NOMASK ((uint8_t)0x00)
#define I2C_OA2_MASK01 ((uint8_t)0x01)
#define I2C_OA2_MASK02 ((uint8_t)0x02)
#define I2C_OA2_MASK03 ((uint8_t)0x03)
#define I2C_OA2_MASK04 ((uint8_t)0x04)
#define I2C_OA2_MASK05 ((uint8_t)0x05)
#define I2C_OA2_MASK06 ((uint8_t)0x06)
#define I2C_OA2_MASK07 ((uint8_t)0x07)
#define I2C_DUALADDRESS_DISABLE (0x00000000U)
#define I2C_DUALADDRESS_ENABLE I2C_OAR2_OA2EN
/**
* @}
*/
/** @defgroup I2C_general_call_addressing_mode I2C general call addressing mode
/** @defgroup I2C_OWN_ADDRESS2_MASKS I2C Own Address2 Masks
* @{
*/
#define I2C_GENERALCALL_DISABLE ((uint32_t)0x00000000)
#define I2C_GENERALCALL_ENABLE I2C_CR1_GCEN
#define I2C_OA2_NOMASK ((uint8_t)0x00U)
#define I2C_OA2_MASK01 ((uint8_t)0x01U)
#define I2C_OA2_MASK02 ((uint8_t)0x02U)
#define I2C_OA2_MASK03 ((uint8_t)0x03U)
#define I2C_OA2_MASK04 ((uint8_t)0x04U)
#define I2C_OA2_MASK05 ((uint8_t)0x05U)
#define I2C_OA2_MASK06 ((uint8_t)0x06U)
#define I2C_OA2_MASK07 ((uint8_t)0x07U)
/**
* @}
*/
/** @defgroup I2C_nostretch_mode I2C nostretch mode
/** @defgroup I2C_GENERAL_CALL_ADDRESSING_MODE I2C General Call Addressing Mode
* @{
*/
#define I2C_NOSTRETCH_DISABLE ((uint32_t)0x00000000)
#define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH
#define I2C_GENERALCALL_DISABLE (0x00000000U)
#define I2C_GENERALCALL_ENABLE I2C_CR1_GCEN
/**
* @}
*/
/** @defgroup I2C_Memory_Address_Size I2C Memory Address Size
/** @defgroup I2C_NOSTRETCH_MODE I2C No-Stretch Mode
* @{
*/
#define I2C_MEMADD_SIZE_8BIT ((uint32_t)0x00000001)
#define I2C_MEMADD_SIZE_16BIT ((uint32_t)0x00000002)
#define I2C_NOSTRETCH_DISABLE (0x00000000U)
#define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH
/**
* @}
*/
*/
/** @defgroup I2C_MEMORY_ADDRESS_SIZE I2C Memory Address Size
* @{
*/
#define I2C_MEMADD_SIZE_8BIT (0x00000001U)
#define I2C_MEMADD_SIZE_16BIT (0x00000002U)
/**
* @}
*/
/** @defgroup I2C_ReloadEndMode_definition I2C ReloadEndMode definition
/** @defgroup I2C_XFERDIRECTION I2C Transfer Direction Master Point of View
* @{
*/
#define I2C_DIRECTION_TRANSMIT (0x00000000U)
#define I2C_DIRECTION_RECEIVE (0x00000001U)
/**
* @}
*/
/** @defgroup I2C_RELOAD_END_MODE I2C Reload End Mode
* @{
*/
#define I2C_RELOAD_MODE I2C_CR2_RELOAD
#define I2C_AUTOEND_MODE I2C_CR2_AUTOEND
#define I2C_SOFTEND_MODE ((uint32_t)0x00000000)
#define I2C_SOFTEND_MODE (0x00000000U)
/**
* @}
*/
/** @defgroup I2C_StartStopMode_definition I2C StartStopMode definition
/** @defgroup I2C_START_STOP_MODE I2C Start or Stop Mode
* @{
*/
#define I2C_NO_STARTSTOP ((uint32_t)0x00000000)
#define I2C_GENERATE_STOP I2C_CR2_STOP
#define I2C_GENERATE_START_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN)
#define I2C_GENERATE_START_WRITE I2C_CR2_START
#define I2C_NO_STARTSTOP (0x00000000U)
#define I2C_GENERATE_STOP I2C_CR2_STOP
#define I2C_GENERATE_START_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN)
#define I2C_GENERATE_START_WRITE I2C_CR2_START
/**
* @}
*/
@ -275,46 +350,44 @@ typedef struct
* - XXXXXXXX : Interrupt control mask
* @{
*/
#define I2C_IT_ERRI I2C_CR1_ERRIE
#define I2C_IT_TCI I2C_CR1_TCIE
#define I2C_IT_STOPI I2C_CR1_STOPIE
#define I2C_IT_NACKI I2C_CR1_NACKIE
#define I2C_IT_ADDRI I2C_CR1_ADDRIE
#define I2C_IT_RXI I2C_CR1_RXIE
#define I2C_IT_TXI I2C_CR1_TXIE
#define I2C_IT_ERRI I2C_CR1_ERRIE
#define I2C_IT_TCI I2C_CR1_TCIE
#define I2C_IT_STOPI I2C_CR1_STOPIE
#define I2C_IT_NACKI I2C_CR1_NACKIE
#define I2C_IT_ADDRI I2C_CR1_ADDRIE
#define I2C_IT_RXI I2C_CR1_RXIE
#define I2C_IT_TXI I2C_CR1_TXIE
/**
* @}
*/
/** @defgroup I2C_Flag_definition I2C Flag definition
* @{
*/
#define I2C_FLAG_TXE I2C_ISR_TXE
#define I2C_FLAG_TXIS I2C_ISR_TXIS
#define I2C_FLAG_RXNE I2C_ISR_RXNE
#define I2C_FLAG_ADDR I2C_ISR_ADDR
#define I2C_FLAG_AF I2C_ISR_NACKF
#define I2C_FLAG_STOPF I2C_ISR_STOPF
#define I2C_FLAG_TC I2C_ISR_TC
#define I2C_FLAG_TCR I2C_ISR_TCR
#define I2C_FLAG_BERR I2C_ISR_BERR
#define I2C_FLAG_ARLO I2C_ISR_ARLO
#define I2C_FLAG_OVR I2C_ISR_OVR
#define I2C_FLAG_PECERR I2C_ISR_PECERR
#define I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT
#define I2C_FLAG_ALERT I2C_ISR_ALERT
#define I2C_FLAG_BUSY I2C_ISR_BUSY
#define I2C_FLAG_DIR I2C_ISR_DIR
*/
#define I2C_FLAG_TXE I2C_ISR_TXE
#define I2C_FLAG_TXIS I2C_ISR_TXIS
#define I2C_FLAG_RXNE I2C_ISR_RXNE
#define I2C_FLAG_ADDR I2C_ISR_ADDR
#define I2C_FLAG_AF I2C_ISR_NACKF
#define I2C_FLAG_STOPF I2C_ISR_STOPF
#define I2C_FLAG_TC I2C_ISR_TC
#define I2C_FLAG_TCR I2C_ISR_TCR
#define I2C_FLAG_BERR I2C_ISR_BERR
#define I2C_FLAG_ARLO I2C_ISR_ARLO
#define I2C_FLAG_OVR I2C_ISR_OVR
#define I2C_FLAG_PECERR I2C_ISR_PECERR
#define I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT
#define I2C_FLAG_ALERT I2C_ISR_ALERT
#define I2C_FLAG_BUSY I2C_ISR_BUSY
#define I2C_FLAG_DIR I2C_ISR_DIR
/**
* @}
*/
/**
* @}
*/
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup I2C_Exported_Macros I2C Exported Macros
@ -325,28 +398,11 @@ typedef struct
* @param __HANDLE__ specifies the I2C Handle.
* @retval None
*/
#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET)
#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET)
/** @brief Enable the specified I2C interrupt.
* @param __HANDLE__ specifies the I2C Handle.
* @param __INTERRUPT__: specifies the interrupt source to enable.
* This parameter can be one of the following values:
* @arg @ref I2C_IT_ERRI Errors interrupt enable
* @arg @ref I2C_IT_TCI Transfer complete interrupt enable
* @arg @ref I2C_IT_STOPI STOP detection interrupt enable
* @arg @ref I2C_IT_NACKI NACK received interrupt enable
* @arg @ref I2C_IT_ADDRI Address match interrupt enable
* @arg @ref I2C_IT_RXI RX interrupt enable
* @arg @ref I2C_IT_TXI TX interrupt enable
*
* @retval None
*/
#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
/** @brief Disable the specified I2C interrupt.
* @param __HANDLE__ specifies the I2C Handle.
* @param __INTERRUPT__: specifies the interrupt source to disable.
* @param __INTERRUPT__ specifies the interrupt source to enable.
* This parameter can be one of the following values:
* @arg @ref I2C_IT_ERRI Errors interrupt enable
* @arg @ref I2C_IT_TCI Transfer complete interrupt enable
@ -355,15 +411,15 @@ typedef struct
* @arg @ref I2C_IT_ADDRI Address match interrupt enable
* @arg @ref I2C_IT_RXI RX interrupt enable
* @arg @ref I2C_IT_TXI TX interrupt enable
*
*
* @retval None
*/
#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
/** @brief Check whether the specified I2C interrupt source is enabled or not.
#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
/** @brief Disable the specified I2C interrupt.
* @param __HANDLE__ specifies the I2C Handle.
* @param __INTERRUPT__: specifies the I2C interrupt source to check.
* This parameter can be one of the following values:
* @param __INTERRUPT__ specifies the interrupt source to disable.
* This parameter can be one of the following values:
* @arg @ref I2C_IT_ERRI Errors interrupt enable
* @arg @ref I2C_IT_TCI Transfer complete interrupt enable
* @arg @ref I2C_IT_STOPI STOP detection interrupt enable
@ -371,15 +427,31 @@ typedef struct
* @arg @ref I2C_IT_ADDRI Address match interrupt enable
* @arg @ref I2C_IT_RXI RX interrupt enable
* @arg @ref I2C_IT_TXI TX interrupt enable
*
* @retval The new state of __INTERRUPT__ (TRUE or FALSE).
*
* @retval None
*/
#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
/** @brief Check whether the specified I2C interrupt source is enabled or not.
* @param __HANDLE__ specifies the I2C Handle.
* @param __INTERRUPT__ specifies the I2C interrupt source to check.
* This parameter can be one of the following values:
* @arg @ref I2C_IT_ERRI Errors interrupt enable
* @arg @ref I2C_IT_TCI Transfer complete interrupt enable
* @arg @ref I2C_IT_STOPI STOP detection interrupt enable
* @arg @ref I2C_IT_NACKI NACK received interrupt enable
* @arg @ref I2C_IT_ADDRI Address match interrupt enable
* @arg @ref I2C_IT_RXI RX interrupt enable
* @arg @ref I2C_IT_TXI TX interrupt enable
*
* @retval The new state of __INTERRUPT__ (SET or RESET).
*/
#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
/** @brief Check whether the specified I2C flag is set or not.
* @param __HANDLE__ specifies the I2C Handle.
* @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* This parameter can be one of the following values:
* @arg @ref I2C_FLAG_TXE Transmit data register empty
* @arg @ref I2C_FLAG_TXIS Transmit interrupt status
* @arg @ref I2C_FLAG_RXNE Receive data register not empty
@ -390,54 +462,58 @@ typedef struct
* @arg @ref I2C_FLAG_TCR Transfer complete reload
* @arg @ref I2C_FLAG_BERR Bus error
* @arg @ref I2C_FLAG_ARLO Arbitration lost
* @arg @ref I2C_FLAG_OVR Overrun/Underrun
* @arg @ref I2C_FLAG_OVR Overrun/Underrun
* @arg @ref I2C_FLAG_PECERR PEC error in reception
* @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
* @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
* @arg @ref I2C_FLAG_ALERT SMBus alert
* @arg @ref I2C_FLAG_BUSY Bus busy
* @arg @ref I2C_FLAG_DIR Transfer direction (slave mode)
*
* @retval The new state of __FLAG__ (TRUE or FALSE).
*
* @retval The new state of __FLAG__ (SET or RESET).
*/
#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__))
#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) ? SET : RESET)
/** @brief Clear the I2C pending flags which are cleared by writing 1 in a specific bit.
* @param __HANDLE__ specifies the I2C Handle.
* @param __FLAG__ specifies the flag to clear.
* This parameter can be any combination of the following values:
* This parameter can be any combination of the following values:
* @arg @ref I2C_FLAG_TXE Transmit data register empty
* @arg @ref I2C_FLAG_ADDR Address matched (slave mode)
* @arg @ref I2C_FLAG_AF Acknowledge failure received flag
* @arg @ref I2C_FLAG_STOPF STOP detection flag
* @arg @ref I2C_FLAG_BERR Bus error
* @arg @ref I2C_FLAG_ARLO Arbitration lost
* @arg @ref I2C_FLAG_OVR Overrun/Underrun
* @arg @ref I2C_FLAG_OVR Overrun/Underrun
* @arg @ref I2C_FLAG_PECERR PEC error in reception
* @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
* @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
* @arg @ref I2C_FLAG_ALERT SMBus alert
*
*
* @retval None
*/
#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == I2C_FLAG_TXE) ? ((__HANDLE__)->Instance->ISR |= (__FLAG__)) \
: ((__HANDLE__)->Instance->ICR = (__FLAG__)))
/** @brief Enable the specified I2C peripheral.
* @param __HANDLE__ specifies the I2C Handle.
* @param __HANDLE__ specifies the I2C Handle.
* @retval None
*/
#define __HAL_I2C_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
/** @brief Disable the specified I2C peripheral.
* @param __HANDLE__ specifies the I2C Handle.
* @param __HANDLE__ specifies the I2C Handle.
* @retval None
*/
#define __HAL_I2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
/** @brief Generate a Non-Acknowledge I2C peripheral in Slave mode.
* @param __HANDLE__: specifies the I2C Handle.
* @retval None
*/
#define __HAL_I2C_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
/**
* @}
*/
*/
/* Include I2C HAL Extended module */
#include "stm32f0xx_hal_i2c_ex.h"
@ -456,7 +532,7 @@ void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c);
void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c);
/**
* @}
*/
*/
/** @addtogroup I2C_Exported_Functions_Group2 Input and Output operation functions
* @{
@ -479,6 +555,14 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pDa
HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c);
HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c);
HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress);
/******* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
@ -488,24 +572,27 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd
HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
/**
* @}
*/
*/
/** @addtogroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
* @{
*/
/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
*/
/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c);
void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c);
void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);
void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c);
/**
* @}
*/
*/
/** @addtogroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
* @{
@ -538,47 +625,58 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
*/
#define IS_I2C_ADDRESSING_MODE(MODE) (((MODE) == I2C_ADDRESSINGMODE_7BIT) || \
((MODE) == I2C_ADDRESSINGMODE_10BIT))
((MODE) == I2C_ADDRESSINGMODE_10BIT))
#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \
((ADDRESS) == I2C_DUALADDRESS_ENABLE))
((ADDRESS) == I2C_DUALADDRESS_ENABLE))
#define IS_I2C_OWN_ADDRESS2_MASK(MASK) (((MASK) == I2C_OA2_NOMASK) || \
((MASK) == I2C_OA2_MASK01) || \
((MASK) == I2C_OA2_MASK02) || \
((MASK) == I2C_OA2_MASK03) || \
((MASK) == I2C_OA2_MASK04) || \
((MASK) == I2C_OA2_MASK05) || \
((MASK) == I2C_OA2_MASK06) || \
((MASK) == I2C_OA2_MASK07))
((MASK) == I2C_OA2_MASK01) || \
((MASK) == I2C_OA2_MASK02) || \
((MASK) == I2C_OA2_MASK03) || \
((MASK) == I2C_OA2_MASK04) || \
((MASK) == I2C_OA2_MASK05) || \
((MASK) == I2C_OA2_MASK06) || \
((MASK) == I2C_OA2_MASK07))
#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || \
((CALL) == I2C_GENERALCALL_ENABLE))
((CALL) == I2C_GENERALCALL_ENABLE))
#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \
((STRETCH) == I2C_NOSTRETCH_ENABLE))
((STRETCH) == I2C_NOSTRETCH_ENABLE))
#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \
((SIZE) == I2C_MEMADD_SIZE_16BIT))
((SIZE) == I2C_MEMADD_SIZE_16BIT))
#define IS_TRANSFER_MODE(MODE) (((MODE) == I2C_RELOAD_MODE) || \
((MODE) == I2C_AUTOEND_MODE) || \
((MODE) == I2C_SOFTEND_MODE))
((MODE) == I2C_AUTOEND_MODE) || \
((MODE) == I2C_SOFTEND_MODE))
#define IS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == I2C_GENERATE_STOP) || \
((REQUEST) == I2C_GENERATE_START_READ) || \
((REQUEST) == I2C_GENERATE_START_WRITE) || \
((REQUEST) == I2C_NO_STARTSTOP))
#define IS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == I2C_GENERATE_STOP) || \
((REQUEST) == I2C_GENERATE_START_READ) || \
((REQUEST) == I2C_GENERATE_START_WRITE) || \
((REQUEST) == I2C_NO_STARTSTOP))
#define I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_FIRST_FRAME) || \
((REQUEST) == I2C_NEXT_FRAME) || \
((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \
((REQUEST) == I2C_LAST_FRAME))
#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= (uint32_t)0x000003FF)
#define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FF)
#define I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00))) >> 8)))
#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF))))
#define I2C_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 16U)
#define I2C_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U)
#define I2C_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
#define I2C_GET_OWN_ADDRESS1(__HANDLE__) ((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1)
#define I2C_GET_OWN_ADDRESS2(__HANDLE__) ((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2)
#define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \
#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU)
#define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU)
#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00U))) >> 8U)))
#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
#define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \
(uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))
/**
* @}
@ -601,11 +699,6 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
@ -614,4 +707,3 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
#endif /* __STM32F0xx_HAL_I2C_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

31
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_i2c_ex.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_i2c_ex.c
* @author MCD Application Team
* @version V1.3.1
* @date 29-January-2016
* @version V1.4.0
* @date 27-May-2016
* @brief I2C Extended HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of I2C Extended peripheral:
@ -97,6 +97,7 @@
===============================================================================
[..] This section provides functions allowing to:
(+) Configure Noise Filters
(+) Configure Wake Up Feature
@endverbatim
* @{
@ -104,9 +105,9 @@
/**
* @brief Configure I2C Analog noise filter.
* @param hi2c : pointer to a I2C_HandleTypeDef structure that contains
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2Cx peripheral.
* @param AnalogFilter : new state of the Analog filter.
* @param AnalogFilter New state of the Analog filter.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)
@ -148,14 +149,14 @@ HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t
/**
* @brief Configure I2C Digital noise filter.
* @param hi2c : pointer to a I2C_HandleTypeDef structure that contains
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2Cx peripheral.
* @param DigitalFilter : Coefficient of digital noise filter between 0x00 and 0x0F.
* @param DigitalFilter Coefficient of digital noise filter between 0x00 and 0x0F.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
{
uint32_t tmpreg = 0;
uint32_t tmpreg = 0U;
/* Check the parameters */
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
@ -178,7 +179,7 @@ HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_
tmpreg &= ~(I2C_CR1_DNF);
/* Set I2Cx DNF coefficient */
tmpreg |= DigitalFilter << 8;
tmpreg |= DigitalFilter << 8U;
/* Store the new register value */
hi2c->Instance->CR1 = tmpreg;
@ -198,17 +199,17 @@ HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_
}
}
#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
/**
* @brief Enable I2C wakeup from stop mode.
* @param hi2c : pointer to a I2C_HandleTypeDef structure that contains
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2Cx peripheral.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp (I2C_HandleTypeDef *hi2c)
{
/* Check the parameters */
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance));
if(hi2c->State == HAL_I2C_STATE_READY)
{
@ -241,14 +242,14 @@ HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp (I2C_HandleTypeDef *hi2c)
/**
* @brief Disable I2C wakeup from stop mode.
* @param hi2c : pointer to a I2C_HandleTypeDef structure that contains
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2Cx peripheral.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp (I2C_HandleTypeDef *hi2c)
{
/* Check the parameters */
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance));
if(hi2c->State == HAL_I2C_STATE_READY)
{
@ -281,7 +282,7 @@ HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp (I2C_HandleTypeDef *hi2c)
/**
* @brief Enable the I2C fast mode plus driving capability.
* @param ConfigFastModePlus: selects the pin.
* @param ConfigFastModePlus Selects the pin.
* This parameter can be one of the @ref I2CEx_FastModePlus values
* @retval None
*/
@ -299,7 +300,7 @@ void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus)
/**
* @brief Disable the I2C fast mode plus driving capability.
* @param ConfigFastModePlus: selects the pin.
* @param ConfigFastModePlus Selects the pin.
* This parameter can be one of the @ref I2CEx_FastModePlus values
* @retval None
*/

8
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_i2c_ex.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_i2c_ex.h
* @author MCD Application Team
* @version V1.3.1
* @date 29-January-2016
* @version V1.4.0
* @date 27-May-2016
* @brief Header file of I2C HAL Extended module.
******************************************************************************
* @attention
@ -64,7 +64,7 @@
/** @defgroup I2CEx_Analog_Filter I2C Extended Analog Filter
* @{
*/
#define I2C_ANALOGFILTER_ENABLE ((uint32_t)0x00000000)
#define I2C_ANALOGFILTER_ENABLE (0x00000000U)
#define I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF
/**
* @}
@ -155,7 +155,7 @@ void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
#define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \
((FILTER) == I2C_ANALOGFILTER_DISABLE))
#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000F)
#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU)
#if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F042x6) || defined(STM32F048xx)
#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & (I2C_FASTMODEPLUS_PA9)) == I2C_FASTMODEPLUS_PA9) || \

4
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_i2s.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_i2s.c
* @author MCD Application Team
* @version V1.3.1
* @date 29-January-2016
* @version V1.4.0
* @date 27-May-2016
* @brief I2S HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Integrated Interchip Sound (I2S) peripheral:

4
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_i2s.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_i2s.h
* @author MCD Application Team
* @version V1.3.1
* @date 29-January-2016
* @version V1.4.0
* @date 27-May-2016
* @brief Header file of I2S HAL module.
******************************************************************************
* @attention

442
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_irda.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_irda.c
* @author MCD Application Team
* @version V1.3.1
* @date 29-January-2016
* @version V1.4.0
* @date 27-May-2016
* @brief IRDA HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the IrDA (Infrared Data Association) Peripheral
@ -208,43 +208,10 @@ static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda,
(+) For the asynchronous mode only these parameters can be configured:
(++) Baud Rate
(++) Word Length
(++) Parity: If the parity is enabled, then the MSB bit of the data written
in the data register is transmitted but is changed by the parity bit.
According to device capability (support or not of 7-bit word length),
frame length is either defined by the M bit (8-bits or 9-bits)
or by the M1 and M0 bits (7-bit, 8-bit or 9-bit).
Possible IRDA frame formats are as listed in the following table:
(+++) Table 1. IRDA frame format.
(+++) +-----------------------------------------------------------------------+
(+++) | M bit | PCE bit | IRDA frame |
(+++) |-------------------|-----------|---------------------------------------|
(+++) | 0 | 0 | | SB | 8-bit data | STB | |
(+++) |-------------------|-----------|---------------------------------------|
(+++) | 0 | 1 | | SB | 7-bit data | PB | STB | |
(+++) |-------------------|-----------|---------------------------------------|
(+++) | 1 | 0 | | SB | 9-bit data | STB | |
(+++) |-------------------|-----------|---------------------------------------|
(+++) | 1 | 1 | | SB | 8-bit data | PB | STB | |
(+++) +-----------------------------------------------------------------------+
(+++) | M1 bit | M0 bit | PCE bit | IRDA frame |
(+++) |---------|---------|-----------|---------------------------------------|
(+++) | 0 | 0 | 0 | | SB | 8 bit data | STB | |
(+++) |---------|---------|-----------|---------------------------------------|
(+++) | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | |
(+++) |---------|---------|-----------|---------------------------------------|
(+++) | 0 | 1 | 0 | | SB | 9 bit data | STB | |
(+++) |---------|---------|-----------|---------------------------------------|
(+++) | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | |
(+++) |---------|---------|-----------|---------------------------------------|
(+++) | 1 | 0 | 0 | | SB | 7 bit data | STB | |
(+++) |---------|---------|-----------|---------------------------------------|
(+++) | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | |
(+++) +-----------------------------------------------------------------------+
(++) Power mode
(++) Prescaler setting
(++) Receiver/transmitter modes
(++) Parity
(++) Power mode
(++) Prescaler setting
(++) Receiver/transmitter modes
[..]
The HAL_IRDA_Init() API follows the USART asynchronous configuration procedures
@ -254,6 +221,43 @@ static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda,
* @{
*/
/*
Additional Table: If the parity is enabled, then the MSB bit of the data written
in the data register is transmitted but is changed by the parity bit.
According to device capability (support or not of 7-bit word length),
frame length is either defined by the M bit (8-bits or 9-bits)
or by the M1 and M0 bits (7-bit, 8-bit or 9-bit).
Possible IRDA frame formats are as listed in the following table:
Table 1. IRDA frame format.
+-----------------------------------------------------------------------+
| M bit | PCE bit | IRDA frame |
|-------------------|-----------|---------------------------------------|
| 0 | 0 | | SB | 8-bit data | STB | |
|-------------------|-----------|---------------------------------------|
| 0 | 1 | | SB | 7-bit data | PB | STB | |
|-------------------|-----------|---------------------------------------|
| 1 | 0 | | SB | 9-bit data | STB | |
|-------------------|-----------|---------------------------------------|
| 1 | 1 | | SB | 8-bit data | PB | STB | |
+-----------------------------------------------------------------------+
| M1 bit | M0 bit | PCE bit | IRDA frame |
|---------|---------|-----------|---------------------------------------|
| 0 | 0 | 0 | | SB | 8 bit data | STB | |
|---------|---------|-----------|---------------------------------------|
| 0 | 0 | 1 | | SB | 7 bit data | PB | STB | |
|---------|---------|-----------|---------------------------------------|
| 0 | 1 | 0 | | SB | 9 bit data | STB | |
|---------|---------|-----------|---------------------------------------|
| 0 | 1 | 1 | | SB | 8 bit data | PB | STB | |
|---------|---------|-----------|---------------------------------------|
| 1 | 0 | 0 | | SB | 7 bit data | STB | |
|---------|---------|-----------|---------------------------------------|
| 1 | 0 | 1 | | SB | 6 bit data | PB | STB | |
+-----------------------------------------------------------------------+
*/
/**
* @brief Initialize the IRDA mode according to the specified
* parameters in the IRDA_InitTypeDef and initialize the associated handle.
@ -272,7 +276,7 @@ HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda)
/* Check the USART/UART associated to the IRDA handle */
assert_param(IS_IRDA_INSTANCE(hirda->Instance));
if(hirda->State == HAL_IRDA_STATE_RESET)
if(hirda->gState == HAL_IRDA_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hirda->Lock = HAL_UNLOCKED;
@ -281,7 +285,7 @@ HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda)
HAL_IRDA_MspInit(hirda);
}
hirda->State = HAL_IRDA_STATE_BUSY;
hirda->gState = HAL_IRDA_STATE_BUSY;
/* Disable the Peripheral to update the configuration registers */
__HAL_IRDA_DISABLE(hirda);
@ -304,7 +308,7 @@ HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda)
/* Enable the Peripheral */
__HAL_IRDA_ENABLE(hirda);
/* TEACK and/or REACK to check before moving hirda->State to Ready */
/* TEACK and/or REACK to check before moving hirda->gState and hirda->RxState to Ready */
return (IRDA_CheckIdleState(hirda));
}
@ -325,15 +329,15 @@ HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda)
/* Check the USART/UART associated to the IRDA handle */
assert_param(IS_IRDA_INSTANCE(hirda->Instance));
hirda->State = HAL_IRDA_STATE_BUSY;
hirda->gState = HAL_IRDA_STATE_BUSY;
/* DeInit the low level hardware */
HAL_IRDA_MspDeInit(hirda);
/* Disable the Peripheral */
__HAL_IRDA_DISABLE(hirda);
hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
hirda->State = HAL_IRDA_STATE_RESET;
hirda->gState = HAL_IRDA_STATE_RESET;
hirda->RxState = HAL_IRDA_STATE_RESET;
/* Process Unlock */
__HAL_UNLOCK(hirda);
@ -440,33 +444,42 @@ HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda)
* the configuration information for the specified IRDA module.
* @param pData: Pointer to data buffer.
* @param Size: Amount of data to be sent.
* @param Timeout: Specify timeout value.
* @param Timeout: Timeout duration.
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits)
* (as sent data will be handled using u16 pointer cast). Depending on compilation chain,
* use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
uint16_t* tmp;
if((hirda->State == HAL_IRDA_STATE_READY) || (hirda->State == HAL_IRDA_STATE_BUSY_RX))
/* Check that a Tx process is not already ongoing */
if(hirda->gState == HAL_IRDA_STATE_READY)
{
if((pData == NULL) || (Size == 0))
{
return HAL_ERROR;
}
/* In case of 9bits/No Parity transfer, pData buffer provided as input paramter
should be aligned on a u16 frontier, as data to be filled into TDR will be
handled through a u16 cast. */
if ((hirda->Init.WordLength == UART_WORDLENGTH_9B) && (hirda->Init.Parity == UART_PARITY_NONE))
{
if((((uint32_t)pData)&1) != 0)
{
return HAL_ERROR;
}
}
/* Process Locked */
__HAL_LOCK(hirda);
hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
if(hirda->State == HAL_IRDA_STATE_BUSY_RX)
{
hirda->State = HAL_IRDA_STATE_BUSY_TX_RX;
}
else
{
hirda->State = HAL_IRDA_STATE_BUSY_TX;
}
hirda->gState = HAL_IRDA_STATE_BUSY_TX;
hirda->TxXferSize = Size;
hirda->TxXferCount = Size;
@ -495,14 +508,8 @@ HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, u
return HAL_TIMEOUT;
}
if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX)
{
hirda->State = HAL_IRDA_STATE_BUSY_RX;
}
else
{
hirda->State = HAL_IRDA_STATE_READY;
}
/* At end of Tx process, restore hirda->gState to Ready */
hirda->gState = HAL_IRDA_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hirda);
@ -521,7 +528,11 @@ HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, u
* the configuration information for the specified IRDA module.
* @param pData: Pointer to data buffer.
* @param Size: Amount of data to be received.
* @param Timeout: Specify timeout value.
* @param Timeout: Timeout duration.
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits)
* (as received data will be handled using u16 pointer cast). Depending on compilation chain,
* use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
@ -529,26 +540,31 @@ HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, ui
uint16_t* tmp;
uint16_t uhMask;
if((hirda->State == HAL_IRDA_STATE_READY) || (hirda->State == HAL_IRDA_STATE_BUSY_TX))
/* Check that a Rx process is not already ongoing */
if(hirda->RxState == HAL_IRDA_STATE_READY)
{
if((pData == NULL) || (Size == 0))
{
return HAL_ERROR;
}
/* In case of 9bits/No Parity transfer, pData buffer provided as input paramter
should be aligned on a u16 frontier, as data to be received from RDR will be
handled through a u16 cast. */
if ((hirda->Init.WordLength == UART_WORDLENGTH_9B) && (hirda->Init.Parity == UART_PARITY_NONE))
{
if((((uint32_t)pData)&1) != 0)
{
return HAL_ERROR;
}
}
/* Process Locked */
__HAL_LOCK(hirda);
hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
if(hirda->State == HAL_IRDA_STATE_BUSY_TX)
{
hirda->State = HAL_IRDA_STATE_BUSY_TX_RX;
}
else
{
hirda->State = HAL_IRDA_STATE_BUSY_RX;
}
hirda->RxState = HAL_IRDA_STATE_BUSY_RX;
hirda->RxXferSize = Size;
hirda->RxXferCount = Size;
@ -579,14 +595,8 @@ HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, ui
}
}
if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX)
{
hirda->State = HAL_IRDA_STATE_BUSY_TX;
}
else
{
hirda->State = HAL_IRDA_STATE_READY;
}
/* At end of Rx process, restore hirda->RxState to Ready */
hirda->RxState = HAL_IRDA_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hirda);
@ -605,17 +615,33 @@ HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, ui
* the configuration information for the specified IRDA module.
* @param pData: Pointer to data buffer.
* @param Size: Amount of data to be sent.
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits)
* (as sent data will be handled using u16 pointer cast). Depending on compilation chain,
* use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
{
if((hirda->State == HAL_IRDA_STATE_READY) || (hirda->State == HAL_IRDA_STATE_BUSY_RX))
/* Check that a Tx process is not already ongoing */
if(hirda->gState == HAL_IRDA_STATE_READY)
{
if((pData == NULL) || (Size == 0))
{
return HAL_ERROR;
}
/* In case of 9bits/No Parity transfer, pData buffer provided as input paramter
should be aligned on a u16 frontier, as data to be filled into TDR will be
handled through a u16 cast. */
if ((hirda->Init.WordLength == UART_WORDLENGTH_9B) && (hirda->Init.Parity == UART_PARITY_NONE))
{
if((((uint32_t)pData)&1) != 0)
{
return HAL_ERROR;
}
}
/* Process Locked */
__HAL_LOCK(hirda);
@ -625,20 +651,11 @@ HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData
hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
if(hirda->State == HAL_IRDA_STATE_BUSY_RX)
{
hirda->State = HAL_IRDA_STATE_BUSY_TX_RX;
}
else
{
hirda->State = HAL_IRDA_STATE_BUSY_TX;
}
hirda->gState = HAL_IRDA_STATE_BUSY_TX;
/* Process Unlocked */
__HAL_UNLOCK(hirda);
/* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
__HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_ERR);
/* Enable the IRDA Transmit Data Register Empty Interrupt */
__HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_TXE);
@ -656,17 +673,33 @@ HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData
* the configuration information for the specified IRDA module.
* @param pData: Pointer to data buffer.
* @param Size: Amount of data to be received.
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits)
* (as received data will be handled using u16 pointer cast). Depending on compilation chain,
* use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
{
if((hirda->State == HAL_IRDA_STATE_READY) || (hirda->State == HAL_IRDA_STATE_BUSY_TX))
/* Check that a Rx process is not already ongoing */
if(hirda->RxState == HAL_IRDA_STATE_READY)
{
if((pData == NULL) || (Size == 0))
{
return HAL_ERROR;
}
/* In case of 9bits/No Parity transfer, pData buffer provided as input paramter
should be aligned on a u16 frontier, as data to be received from RDR will be
handled through a u16 cast. */
if ((hirda->Init.WordLength == UART_WORDLENGTH_9B) && (hirda->Init.Parity == UART_PARITY_NONE))
{
if((((uint32_t)pData)&1) != 0)
{
return HAL_ERROR;
}
}
/* Process Locked */
__HAL_LOCK(hirda);
@ -680,14 +713,7 @@ HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData,
hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
if(hirda->State == HAL_IRDA_STATE_BUSY_TX)
{
hirda->State = HAL_IRDA_STATE_BUSY_TX_RX;
}
else
{
hirda->State = HAL_IRDA_STATE_BUSY_RX;
}
hirda->RxState = HAL_IRDA_STATE_BUSY_RX;
/* Process Unlocked */
__HAL_UNLOCK(hirda);
@ -715,19 +741,35 @@ HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData,
* the configuration information for the specified IRDA module.
* @param pData: pointer to data buffer.
* @param Size: amount of data to be sent.
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits)
* (as sent data will be handled by DMA from halfword frontier). Depending on compilation chain,
* use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
{
uint32_t *tmp;
if((hirda->State == HAL_IRDA_STATE_READY) || (hirda->State == HAL_IRDA_STATE_BUSY_RX))
/* Check that a Tx process is not already ongoing */
if(hirda->gState == HAL_IRDA_STATE_READY)
{
if((pData == NULL) || (Size == 0))
{
return HAL_ERROR;
}
/* In case of 9bits/No Parity transfer, pData buffer provided as input paramter
should be aligned on a u16 frontier, as data copy into TDR will be
handled by DMA from a u16 frontier. */
if ((hirda->Init.WordLength == UART_WORDLENGTH_9B) && (hirda->Init.Parity == UART_PARITY_NONE))
{
if((((uint32_t)pData)&1) != 0)
{
return HAL_ERROR;
}
}
/* Process Locked */
__HAL_LOCK(hirda);
@ -737,14 +779,7 @@ HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pDat
hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
if(hirda->State == HAL_IRDA_STATE_BUSY_RX)
{
hirda->State = HAL_IRDA_STATE_BUSY_TX_RX;
}
else
{
hirda->State = HAL_IRDA_STATE_BUSY_TX;
}
hirda->gState = HAL_IRDA_STATE_BUSY_TX;
/* Set the IRDA DMA transfer complete callback */
hirda->hdmatx->XferCpltCallback = IRDA_DMATransmitCplt;
@ -783,21 +818,35 @@ HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pDat
* the configuration information for the specified IRDA module.
* @param pData: Pointer to data buffer.
* @param Size: Amount of data to be received.
* @note When the IRDA parity is enabled (PCE = 1) the received data contains
* the parity bit (MSB position).
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits)
* (as received data will be handled by DMA from halfword frontier). Depending on compilation chain,
* use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
{
uint32_t *tmp;
if((hirda->State == HAL_IRDA_STATE_READY) || (hirda->State == HAL_IRDA_STATE_BUSY_TX))
/* Check that a Rx process is not already ongoing */
if(hirda->RxState == HAL_IRDA_STATE_READY)
{
if((pData == NULL) || (Size == 0))
{
return HAL_ERROR;
}
/* In case of 9bits/No Parity transfer, pData buffer provided as input paramter
should be aligned on a u16 frontier, as data copy from RDR will be
handled by DMA from a u16 frontier. */
if ((hirda->Init.WordLength == UART_WORDLENGTH_9B) && (hirda->Init.Parity == UART_PARITY_NONE))
{
if((((uint32_t)pData)&1) != 0)
{
return HAL_ERROR;
}
}
/* Process Locked */
__HAL_LOCK(hirda);
@ -806,14 +855,7 @@ HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData
hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
if(hirda->State == HAL_IRDA_STATE_BUSY_TX)
{
hirda->State = HAL_IRDA_STATE_BUSY_TX_RX;
}
else
{
hirda->State = HAL_IRDA_STATE_BUSY_RX;
}
hirda->RxState = HAL_IRDA_STATE_BUSY_RX;
/* Set the IRDA DMA transfer complete callback */
hirda->hdmarx->XferCpltCallback = IRDA_DMAReceiveCplt;
@ -855,28 +897,16 @@ HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda)
/* Process Locked */
__HAL_LOCK(hirda);
if(hirda->State == HAL_IRDA_STATE_BUSY_TX)
if(hirda->gState == HAL_IRDA_STATE_BUSY_TX)
{
/* Disable the IRDA DMA Tx request */
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
}
else if(hirda->State == HAL_IRDA_STATE_BUSY_RX)
if(hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
{
/* Disable the IRDA DMA Rx request */
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
}
else if (hirda->State == HAL_IRDA_STATE_BUSY_TX_RX)
{
/* Disable the IRDA DMA Tx & Rx requests */
CLEAR_BIT(hirda->Instance->CR3, (USART_CR3_DMAT | USART_CR3_DMAR));
}
else
{
/* Process Unlocked */
__HAL_UNLOCK(hirda);
return HAL_ERROR;
}
/* Process Unlocked */
__HAL_UNLOCK(hirda);
@ -895,32 +925,18 @@ HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda)
/* Process Locked */
__HAL_LOCK(hirda);
if(hirda->State == HAL_IRDA_STATE_BUSY_TX)
if(hirda->gState == HAL_IRDA_STATE_BUSY_TX)
{
/* Enable the IRDA DMA Tx request */
SET_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
}
else if(hirda->State == HAL_IRDA_STATE_BUSY_RX)
if(hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
{
/* Clear the Overrun flag before resuming the Rx transfer*/
__HAL_IRDA_CLEAR_OREFLAG(hirda);
/* Enable the IRDA DMA Rx request */
SET_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
}
else if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX)
{
/* Clear the Overrun flag before resuming the Rx transfer*/
__HAL_IRDA_CLEAR_OREFLAG(hirda);
/* Enable the IRDA DMA Tx & Rx request */
SET_BIT(hirda->Instance->CR3, (USART_CR3_DMAT | USART_CR3_DMAR));
}
else
{
/* Process Unlocked */
__HAL_UNLOCK(hirda);
return HAL_ERROR;
}
/* Process Unlocked */
__HAL_UNLOCK(hirda);
@ -959,7 +975,8 @@ HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda)
HAL_DMA_Abort(hirda->hdmarx);
}
hirda->State = HAL_IRDA_STATE_READY;
hirda->gState = HAL_IRDA_STATE_READY;
hirda->RxState = HAL_IRDA_STATE_READY;
return HAL_OK;
}
@ -979,8 +996,8 @@ void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda)
__HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_PEF);
hirda->ErrorCode |= HAL_IRDA_ERROR_PE;
/* Set the IRDA state ready to be able to start again the process */
hirda->State = HAL_IRDA_STATE_READY;
/* Set the IRDA Rx state ready to be able to start again the process */
hirda->RxState = HAL_IRDA_STATE_READY;
}
/* IRDA frame error interrupt occurred --------------------------------------*/
@ -989,8 +1006,8 @@ void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda)
__HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_FEF);
hirda->ErrorCode |= HAL_IRDA_ERROR_FE;
/* Set the IRDA state ready to be able to start again the process */
hirda->State = HAL_IRDA_STATE_READY;
/* Set the IRDA Rx state ready to be able to start again the process */
hirda->RxState = HAL_IRDA_STATE_READY;
}
/* IRDA noise error interrupt occurred --------------------------------------*/
@ -999,8 +1016,8 @@ void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda)
__HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_NEF);
hirda->ErrorCode |= HAL_IRDA_ERROR_NE;
/* Set the IRDA state ready to be able to start again the process */
hirda->State = HAL_IRDA_STATE_READY;
/* Set the IRDA Rx state ready to be able to start again the process */
hirda->RxState = HAL_IRDA_STATE_READY;
}
/* IRDA Over-Run interrupt occurred -----------------------------------------*/
@ -1009,8 +1026,8 @@ void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda)
__HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_OREF);
hirda->ErrorCode |= HAL_IRDA_ERROR_ORE;
/* Set the IRDA state ready to be able to start again the process */
hirda->State = HAL_IRDA_STATE_READY;
/* Set the IRDA Rx state ready to be able to start again the process */
hirda->RxState = HAL_IRDA_STATE_READY;
}
/* Call IRDA Error Call back function if need be --------------------------*/
@ -1023,19 +1040,17 @@ void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda)
if((__HAL_IRDA_GET_IT(hirda, IRDA_IT_RXNE) != RESET) && (__HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_RXNE) != RESET))
{
IRDA_Receive_IT(hirda);
/* Clear RXNE interrupt flag */
__HAL_IRDA_SEND_REQ(hirda, IRDA_RXDATA_FLUSH_REQUEST);
}
/* IRDA in mode Transmitter ------------------------------------------------*/
if((__HAL_IRDA_GET_IT(hirda, IRDA_IT_TXE) != RESET) &&(__HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_TXE) != RESET))
if((__HAL_IRDA_GET_IT(hirda, IRDA_IT_TXE) != RESET) &&(__HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_TXE) != RESET))
{
IRDA_Transmit_IT(hirda);
}
/* IRDA in mode Transmitter (transmission end) -----------------------------*/
if((__HAL_IRDA_GET_IT(hirda, IRDA_IT_TC) != RESET) &&(__HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_TC) != RESET))
if((__HAL_IRDA_GET_IT(hirda, IRDA_IT_TC) != RESET) &&(__HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_TC) != RESET))
{
IRDA_EndTransmit_IT(hirda);
}
@ -1146,20 +1161,24 @@ __weak void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda)
*/
/**
* @brief Return the IRDA handle state.
* @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @brief Return the IRDA handle state.
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @retval HAL state
*/
HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda)
{
/* Return IRDA handle state */
return hirda->State;
uint32_t temp1= 0x00, temp2 = 0x00;
temp1 = hirda->gState;
temp2 = hirda->RxState;
return (HAL_IRDA_StateTypeDef)(temp1 | temp2);
}
/**
* @brief Return the IRDA handle error code.
* @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
* @brief Return the IRDA handle error code.
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @retval IRDA Error Code
*/
@ -1221,16 +1240,16 @@ static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda)
switch (clocksource)
{
case IRDA_CLOCKSOURCE_PCLK1:
hirda->Instance->BRR = (uint16_t)(HAL_RCC_GetPCLK1Freq() / hirda->Init.BaudRate);
hirda->Instance->BRR = (uint16_t)((HAL_RCC_GetPCLK1Freq() + (hirda->Init.BaudRate/2)) / hirda->Init.BaudRate);
break;
case IRDA_CLOCKSOURCE_HSI:
hirda->Instance->BRR = (uint16_t)(HSI_VALUE / hirda->Init.BaudRate);
hirda->Instance->BRR = (uint16_t)((HSI_VALUE + (hirda->Init.BaudRate/2)) / hirda->Init.BaudRate);
break;
case IRDA_CLOCKSOURCE_SYSCLK:
hirda->Instance->BRR = (uint16_t)(HAL_RCC_GetSysClockFreq() / hirda->Init.BaudRate);
hirda->Instance->BRR = (uint16_t)((HAL_RCC_GetSysClockFreq() + (hirda->Init.BaudRate/2)) / hirda->Init.BaudRate);
break;
case IRDA_CLOCKSOURCE_LSE:
hirda->Instance->BRR = (uint16_t)(LSE_VALUE / hirda->Init.BaudRate);
hirda->Instance->BRR = (uint16_t)((LSE_VALUE + (hirda->Init.BaudRate/2)) / hirda->Init.BaudRate);
break;
case IRDA_CLOCKSOURCE_UNDEFINED:
default:
@ -1257,7 +1276,7 @@ static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda)
Bits are defined for some specific devices, and are available only for UART instances supporting WakeUp from Stop Mode feature.
*/
#if !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC)
if (IS_UART_WAKEUP_INSTANCE(hirda->Instance))
if (IS_UART_WAKEUP_FROMSTOP_INSTANCE(hirda->Instance))
{
/* Check if the Transmitter is enabled */
if((hirda->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
@ -1284,7 +1303,8 @@ static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda)
#endif /* !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC) */
/* Initialize the IRDA state*/
hirda->State= HAL_IRDA_STATE_READY;
hirda->gState= HAL_IRDA_STATE_READY;
hirda->RxState= HAL_IRDA_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hirda);
@ -1321,7 +1341,8 @@ static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda,
__HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_PE);
__HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR);
hirda->State= HAL_IRDA_STATE_READY;
hirda->gState= HAL_IRDA_STATE_READY;
hirda->RxState= HAL_IRDA_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hirda);
@ -1346,7 +1367,8 @@ static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda,
__HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_PE);
__HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR);
hirda->State= HAL_IRDA_STATE_READY;
hirda->gState= HAL_IRDA_STATE_READY;
hirda->RxState= HAL_IRDA_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hirda);
@ -1420,14 +1442,8 @@ static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
in the IRDA CR3 register */
hirda->Instance->CR3 &= ~(USART_CR3_DMAR);
if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX)
{
hirda->State = HAL_IRDA_STATE_BUSY_TX;
}
else
{
hirda->State = HAL_IRDA_STATE_READY;
}
/* At end of Rx process, restore hirda->RxState to Ready */
hirda->RxState = HAL_IRDA_STATE_READY;
}
HAL_IRDA_RxCpltCallback(hirda);
@ -1459,7 +1475,8 @@ static void IRDA_DMAError(DMA_HandleTypeDef *hdma)
hirda->RxXferCount = 0;
hirda->TxXferCount = 0;
hirda->ErrorCode |= HAL_IRDA_ERROR_DMA;
hirda->State= HAL_IRDA_STATE_READY;
hirda->gState= HAL_IRDA_STATE_READY;
hirda->RxState= HAL_IRDA_STATE_READY;
HAL_IRDA_ErrorCallback(hirda);
}
@ -1477,7 +1494,8 @@ static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda)
{
uint16_t* tmp;
if((hirda->State == HAL_IRDA_STATE_BUSY_TX) || (hirda->State == HAL_IRDA_STATE_BUSY_TX_RX))
/* Check that a Tx process is ongoing */
if(hirda->gState == HAL_IRDA_STATE_BUSY_TX)
{
if(hirda->TxXferCount == 0)
{
@ -1514,8 +1532,8 @@ static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda)
/**
* @brief Wrap up transmission in non-blocking mode.
* @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @param hirda pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @retval HAL status
*/
static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda)
@ -1523,18 +1541,8 @@ static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda)
/* Disable the IRDA Transmit Complete Interrupt */
__HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TC);
/* Check if a receive process is ongoing or not */
if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX)
{
hirda->State = HAL_IRDA_STATE_BUSY_RX;
}
else
{
/* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
__HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR);
hirda->State = HAL_IRDA_STATE_READY;
}
/* Tx process is ended, restore hirda->gState to Ready */
hirda->gState = HAL_IRDA_STATE_READY;
HAL_IRDA_TxCpltCallback(hirda);
@ -1543,11 +1551,11 @@ static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda)
/**
* @brief Receive an amount of data in non-blocking mode.
* @brief Receive an amount of data in non-blocking mode.
* Function is called under interruption only, once
* interruptions have been enabled by HAL_IRDA_Receive_IT().
* @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @retval HAL status
*/
static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda)
@ -1555,7 +1563,8 @@ static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda)
uint16_t* tmp;
uint16_t uhMask = hirda->Mask;
if ((hirda->State == HAL_IRDA_STATE_BUSY_RX) || (hirda->State == HAL_IRDA_STATE_BUSY_TX_RX))
/* Check that a Rx process is ongoing */
if (hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
{
if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
@ -1573,20 +1582,14 @@ static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda)
{
__HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_RXNE);
if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX)
{
hirda->State = HAL_IRDA_STATE_BUSY_TX;
}
else
{
/* Disable the IRDA Parity Error Interrupt */
__HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_PE);
/* Disable the IRDA Parity Error Interrupt */
__HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_PE);
/* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
__HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR);
/* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
__HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR);
hirda->State = HAL_IRDA_STATE_READY;
}
/* Rx process is completed, restore hirda->RxState to Ready */
hirda->RxState = HAL_IRDA_STATE_READY;
HAL_IRDA_RxCpltCallback(hirda);
@ -1597,6 +1600,9 @@ static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda)
}
else
{
/* Clear RXNE interrupt flag */
__HAL_IRDA_SEND_REQ(hirda, IRDA_RXDATA_FLUSH_REQUEST);
return HAL_BUSY;
}
}

83
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_irda.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_irda.h
* @author MCD Application Team
* @version V1.3.1
* @date 29-January-2016
* @version V1.4.0
* @date 27-May-2016
* @brief This file contains all the functions prototypes for the IRDA
* firmware library.
******************************************************************************
@ -94,17 +94,62 @@ typedef struct
/**
* @brief HAL IRDA State structures definition
* @note HAL IRDA State value is a combination of 2 different substates: gState and RxState.
* - gState contains IRDA state information related to global Handle management
* and also information related to Tx operations.
* gState value coding follow below described bitmap :
* b7-b6 Error information
* 00 : No Error
* 01 : (Not Used)
* 10 : Timeout
* 11 : Error
* b5 IP initilisation status
* 0 : Reset (IP not initialized)
* 1 : Init done (IP not initialized. HAL IRDA Init function already called)
* b4-b3 (not used)
* xx : Should be set to 00
* b2 Intrinsic process state
* 0 : Ready
* 1 : Busy (IP busy with some configuration or internal operations)
* b1 (not used)
* x : Should be set to 0
* b0 Tx state
* 0 : Ready (no Tx operation ongoing)
* 1 : Busy (Tx operation ongoing)
* - RxState contains information related to Rx operations.
* RxState value coding follow below described bitmap :
* b7-b6 (not used)
* xx : Should be set to 00
* b5 IP initilisation status
* 0 : Reset (IP not initialized)
* 1 : Init done (IP not initialized)
* b4-b2 (not used)
* xxx : Should be set to 000
* b1 Rx state
* 0 : Ready (no Rx operation ongoing)
* 1 : Busy (Rx operation ongoing)
* b0 (not used)
* x : Should be set to 0.
*/
typedef enum
{
HAL_IRDA_STATE_RESET = 0x00, /*!< Peripheral is not initialized */
HAL_IRDA_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
HAL_IRDA_STATE_BUSY = 0x02, /*!< an internal process is ongoing */
HAL_IRDA_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */
HAL_IRDA_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */
HAL_IRDA_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */
HAL_IRDA_STATE_TIMEOUT = 0x03, /*!< Timeout state */
HAL_IRDA_STATE_ERROR = 0x04 /*!< Error */
HAL_IRDA_STATE_RESET = 0x00U, /*!< Peripheral is not initialized
Value is allowed for gState and RxState */
HAL_IRDA_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use
Value is allowed for gState and RxState */
HAL_IRDA_STATE_BUSY = 0x24U, /*!< an internal process is ongoing
Value is allowed for gState only */
HAL_IRDA_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing
Value is allowed for gState only */
HAL_IRDA_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing
Value is allowed for RxState only */
HAL_IRDA_STATE_BUSY_TX_RX = 0x23U, /*!< Data Transmission and Reception process is ongoing
Not to be used for neither gState nor RxState.
Value is result of combination (Or) between gState and RxState values */
HAL_IRDA_STATE_TIMEOUT = 0xA0U, /*!< Timeout state
Value is allowed for gState only */
HAL_IRDA_STATE_ERROR = 0xE0U /*!< Error
Value is allowed for gState only */
}HAL_IRDA_StateTypeDef;
/**
@ -148,7 +193,13 @@ typedef struct
HAL_LockTypeDef Lock; /*!< Locking object */
__IO HAL_IRDA_StateTypeDef State; /*!< IRDA communication state */
__IO HAL_IRDA_StateTypeDef gState; /*!< IRDA state information related to global Handle management
and also related to Tx operations.
This parameter can be a value of @ref HAL_IRDA_StateTypeDef */
__IO HAL_IRDA_StateTypeDef RxState; /*!< IRDA state information related to Rx operations.
This parameter can be a value of @ref HAL_IRDA_StateTypeDef */
__IO uint32_t ErrorCode; /*!< IRDA Error code
This parameter can be a value of @ref IRDA_Error */
@ -219,7 +270,7 @@ typedef enum
* @}
*/
/** @defgroup IRDA_State IRDA State
/** @defgroup IRDA_State IRDA State
* @{
*/
#define IRDA_STATE_DISABLE ((uint32_t)0x00000000) /*!< IRDA disabled */
@ -228,7 +279,7 @@ typedef enum
* @}
*/
/** @defgroup IRDA_Mode IRDA Mode
/** @defgroup IRDA_Mode IRDA Mode
* @{
*/
#define IRDA_MODE_DISABLE ((uint32_t)0x00000000) /*!< Associated UART disabled in IRDA mode */
@ -364,7 +415,10 @@ typedef enum
* @param __HANDLE__: IRDA handle.
* @retval None
*/
#define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_IRDA_STATE_RESET)
#define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->gState = HAL_IRDA_STATE_RESET; \
(__HANDLE__)->RxState = HAL_IRDA_STATE_RESET; \
} while(0)
/** @brief Flush the IRDA DR register.
* @param __HANDLE__: specifies the IRDA Handle.
@ -376,7 +430,6 @@ typedef enum
SET_BIT((__HANDLE__)->Instance->RQR, IRDA_TXDATA_FLUSH_REQUEST); \
} while(0)
/** @brief Clear the specified IRDA pending flag.
* @param __HANDLE__: specifies the IRDA Handle.
* @param __FLAG__: specifies the flag to check.

4
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_irda_ex.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_irda_ex.h
* @author MCD Application Team
* @version V1.3.1
* @date 29-January-2016
* @version V1.4.0
* @date 27-May-2016
* @brief Header file of IRDA HAL Extension module.
******************************************************************************
* @attention

4
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_iwdg.c
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_iwdg.c
* @author MCD Application Team
* @version V1.3.1
* @date 29-January-2016
* @version V1.4.0
* @date 27-May-2016
* @brief IWDG HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Independent Watchdog (IWDG) peripheral:

4
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_iwdg.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_iwdg.h
* @author MCD Application Team
* @version V1.3.1
* @date 29-January-2016
* @version V1.4.0
* @date 27-May-2016
* @brief Header file of IWDG HAL module.
******************************************************************************
* @attention

123
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pcd.c
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_pcd.c
* @author MCD Application Team
* @version V1.3.1
* @date 29-January-2016
* @version V1.4.0
* @date 27-May-2016
* @brief PCD HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the USB Peripheral Controller:
@ -199,8 +199,8 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
hpcd->Instance->BTABLE = BTABLE_ADDRESS;
/*set wInterrupt_Mask global variable*/
wInterrupt_Mask = USB_CNTR_CTRM | USB_CNTR_WKUPM | USB_CNTR_SUSPM | USB_CNTR_ERRM \
| USB_CNTR_ESOFM | USB_CNTR_RESETM;
wInterrupt_Mask = USB_CNTR_CTRM | USB_CNTR_WKUPM | USB_CNTR_SUSPM | USB_CNTR_ERRM \
| USB_CNTR_SOFM | USB_CNTR_ESOFM | USB_CNTR_RESETM;
/*Set interrupt mask*/
hpcd->Instance->CNTR = wInterrupt_Mask;
@ -357,7 +357,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_WKUP))
{
hpcd->Instance->CNTR &= ~(USB_CNTR_LPMODE);
hpcd->Instance->CNTR &= (uint16_t)(~(USB_CNTR_LPMODE));
/*set wInterrupt_Mask global variable*/
wInterrupt_Mask = USB_CNTR_CTRM | USB_CNTR_WKUPM | USB_CNTR_SUSPM | USB_CNTR_ERRM \
@ -615,7 +615,7 @@ HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd)
__HAL_LOCK(hpcd);
/* Disable DP Pull-Down bit*/
hpcd->Instance->BCDR &= ~(USB_BCDR_DPPU);
hpcd->Instance->BCDR &= (uint16_t)(~(USB_BCDR_DPPU));
__HAL_UNLOCK(hpcd);
return HAL_OK;
@ -688,6 +688,8 @@ HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint
case PCD_EP_TYPE_ISOC:
PCD_SET_EPTYPE(hpcd->Instance, ep->num, USB_EP_ISOCHRONOUS);
break;
default:
break;
}
PCD_SET_EP_ADDRESS(hpcd->Instance, ep->num, ep->num);
@ -698,19 +700,19 @@ HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint
{
/*Set the endpoint Transmit buffer address */
PCD_SET_EP_TX_ADDRESS(hpcd->Instance, ep->num, ep->pmaadress);
PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num);
PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num)
/* Configure NAK status for the Endpoint*/
PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_NAK);
PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_NAK)
}
else
{
/*Set the endpoint Receive buffer address */
PCD_SET_EP_RX_ADDRESS(hpcd->Instance, ep->num, ep->pmaadress);
/*Set the endpoint Receive buffer counter*/
PCD_SET_EP_RX_CNT(hpcd->Instance, ep->num, ep->maxpacket);
PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num);
PCD_SET_EP_RX_CNT(hpcd->Instance, ep->num, ep->maxpacket)
PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num)
/* Configure VALID status for the Endpoint*/
PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_VALID);
PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_VALID)
}
}
/*Double Buffer*/
@ -719,29 +721,29 @@ HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint
/*Set the endpoint as double buffered*/
PCD_SET_EP_DBUF(hpcd->Instance, ep->num);
/*Set buffer address for double buffered mode*/
PCD_SET_EP_DBUF_ADDR(hpcd->Instance, ep->num,ep->pmaaddr0, ep->pmaaddr1);
PCD_SET_EP_DBUF_ADDR(hpcd->Instance, ep->num,ep->pmaaddr0, ep->pmaaddr1)
if (ep->is_in==0)
{
/* Clear the data toggle bits for the endpoint IN/OUT*/
PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num);
PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num);
PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num)
PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num)
/* Reset value of the data toggle bits for the endpoint out*/
PCD_TX_DTOG(hpcd->Instance, ep->num);
PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_VALID);
PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS);
PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_VALID)
PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS)
}
else
{
/* Clear the data toggle bits for the endpoint IN/OUT*/
PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num);
PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num);
PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num)
PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num)
PCD_RX_DTOG(hpcd->Instance, ep->num);
/* Configure DISABLE status for the Endpoint*/
PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS);
PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_DIS);
PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS)
PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_DIS)
}
}
@ -778,15 +780,15 @@ HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
{
if (ep->is_in)
{
PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num);
PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num)
/* Configure DISABLE status for the Endpoint*/
PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS);
PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS)
}
else
{
PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num);
PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num)
/* Configure DISABLE status for the Endpoint*/
PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_DIS);
PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_DIS)
}
}
/*Double Buffer*/
@ -795,24 +797,24 @@ HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
if (ep->is_in==0)
{
/* Clear the data toggle bits for the endpoint IN/OUT*/
PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num);
PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num);
PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num)
PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num)
/* Reset value of the data toggle bits for the endpoint out*/
PCD_TX_DTOG(hpcd->Instance, ep->num);
PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_DIS);
PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS);
PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_DIS)
PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS)
}
else
{
/* Clear the data toggle bits for the endpoint IN/OUT*/
PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num);
PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num);
PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num)
PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num)
PCD_RX_DTOG(hpcd->Instance, ep->num);
/* Configure DISABLE status for the Endpoint*/
PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS);
PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_DIS);
PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS)
PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_DIS)
}
}
@ -861,15 +863,15 @@ HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, u
if (ep->doublebuffer == 0)
{
/*Set RX buffer count*/
PCD_SET_EP_RX_CNT(hpcd->Instance, ep->num, len);
PCD_SET_EP_RX_CNT(hpcd->Instance, ep->num, len)
}
else
{
/*Set the Double buffer counter*/
PCD_SET_EP_DBUF_CNT(hpcd->Instance, ep->num, ep->is_in, len);
PCD_SET_EP_DBUF_CNT(hpcd->Instance, ep->num, ep->is_in, len)
}
PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_VALID);
PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_VALID)
__HAL_UNLOCK(hpcd);
@ -931,24 +933,24 @@ HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
else
{
/*Write the data to the USB endpoint*/
if (PCD_GET_ENDPOINT(hpcd->Instance, ep->num)& USB_EP_DTOG_TX)
if ((PCD_GET_ENDPOINT(hpcd->Instance, ep->num)& USB_EP_DTOG_TX) == USB_EP_DTOG_TX)
{
/*Set the Double buffer counter for pmabuffer1*/
PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, len);
PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, len)
pmabuffer = ep->pmaaddr1;
}
else
{
/*Set the Double buffer counter for pmabuffer0*/
PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, len);
PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, len)
pmabuffer = ep->pmaaddr0;
}
PCD_WritePMA(hpcd->Instance, ep->xfer_buff, pmabuffer, len);
PCD_FreeUserBuffer(hpcd->Instance, ep->num, ep->is_in);
PCD_FreeUserBuffer(hpcd->Instance, ep->num, ep->is_in)
}
PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_VALID);
PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_VALID)
__HAL_UNLOCK(hpcd);
@ -983,17 +985,17 @@ HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
if (ep->num == 0)
{
/* This macro sets STALL status for RX & TX*/
PCD_SET_EP_TXRX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_STALL, USB_EP_TX_STALL);
PCD_SET_EP_TXRX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_STALL, USB_EP_TX_STALL)
}
else
{
if (ep->is_in)
{
PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num , USB_EP_TX_STALL);
PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num , USB_EP_TX_STALL)
}
else
{
PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num , USB_EP_RX_STALL);
PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num , USB_EP_RX_STALL)
}
}
__HAL_UNLOCK(hpcd);
@ -1028,13 +1030,13 @@ HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
if (ep->is_in)
{
PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num);
PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_VALID);
PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num)
PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_VALID)
}
else
{
PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num);
PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_VALID);
PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num)
PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_VALID)
}
__HAL_UNLOCK(hpcd);
@ -1070,7 +1072,7 @@ HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)
*/
HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)
{
hpcd->Instance->CNTR &= ~(USB_CNTR_RESUME);
hpcd->Instance->CNTR &= (uint16_t)(~(USB_CNTR_RESUME));
return HAL_OK;
}
/**
@ -1122,17 +1124,17 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd)
*/
void PCD_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
{
uint32_t n = (wNBytes + 1) >> 1;
uint32_t n = ((uint32_t)((uint32_t)wNBytes + 1)) >> 1;
uint32_t i;
uint16_t temp1, temp2;
uint16_t *pdwVal;
pdwVal = (uint16_t *)(wPMABufAddr + (uint32_t)USBx + 0x400);
pdwVal = (uint16_t *)((uint32_t)(wPMABufAddr + (uint32_t)USBx + 0x400));
for (i = n; i != 0; i--)
{
temp1 = (uint16_t) * pbUsrBuf;
pbUsrBuf++;
temp2 = temp1 | (uint16_t) * pbUsrBuf << 8;
temp2 = temp1 | ((uint16_t)((uint16_t) * pbUsrBuf << 8)) ;
*pdwVal++ = temp2;
pbUsrBuf++;
}
@ -1148,13 +1150,13 @@ void PCD_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, u
*/
void PCD_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
{
uint32_t n = (wNBytes + 1) >> 1;
uint32_t n = ((uint32_t)((uint32_t)wNBytes + 1)) >> 1;
uint32_t i;
uint16_t *pdwVal;
pdwVal = (uint16_t *)(wPMABufAddr + (uint32_t)USBx + 0x400);
pdwVal = (uint16_t *)((uint32_t)(wPMABufAddr + (uint32_t)USBx + 0x400));
for (i = n; i != 0; i--)
{
*(uint16_t*)pbUsrBuf++ = *pdwVal++;
*(uint16_t*)((uint32_t)pbUsrBuf++) = *pdwVal++;
pbUsrBuf++;
}
}
@ -1242,8 +1244,8 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd)
/* Process Control Data OUT Packet*/
HAL_PCD_DataOutStageCallback(hpcd, 0);
PCD_SET_EP_RX_CNT(hpcd->Instance, PCD_ENDP0, ep->maxpacket);
PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID);
PCD_SET_EP_RX_CNT(hpcd->Instance, PCD_ENDP0, ep->maxpacket)
PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID)
}
}
}
@ -1271,7 +1273,8 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd)
}
else
{
if (PCD_GET_ENDPOINT(hpcd->Instance, ep->num) & USB_EP_DTOG_RX)
if ((PCD_GET_ENDPOINT(hpcd->Instance, ep->num)& USB_EP_DTOG_RX) == USB_EP_DTOG_RX)
{
/*read from endpoint BUF0Addr buffer*/
count = PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num);
@ -1289,7 +1292,7 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd)
PCD_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, count);
}
}
PCD_FreeUserBuffer(hpcd->Instance, ep->num, PCD_EP_DBUF_OUT);
PCD_FreeUserBuffer(hpcd->Instance, ep->num, PCD_EP_DBUF_OUT)
}
/*multi-packet on the NON control OUT endpoint*/
ep->xfer_count+=count;
@ -1325,7 +1328,7 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd)
}
else
{
if (PCD_GET_ENDPOINT(hpcd->Instance, ep->num) & USB_EP_DTOG_TX)
if ((PCD_GET_ENDPOINT(hpcd->Instance, ep->num)& USB_EP_DTOG_TX) == USB_EP_DTOG_TX)
{
/*read from endpoint BUF0Addr buffer*/
ep->xfer_count = PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num);
@ -1343,7 +1346,7 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd)
PCD_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, ep->xfer_count);
}
}
PCD_FreeUserBuffer(hpcd->Instance, ep->num, PCD_EP_DBUF_IN);
PCD_FreeUserBuffer(hpcd->Instance, ep->num, PCD_EP_DBUF_IN)
}
/*multi-packet on the NON control IN endpoint*/
ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num);

149
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pcd.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_pcd.h
* @author MCD Application Team
* @version V1.3.1
* @date 29-January-2016
* @version V1.4.0
* @date 27-May-2016
* @brief Header file of PCD HAL module.
******************************************************************************
* @attention
@ -219,7 +219,7 @@ typedef struct
* @{
*/
#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISTR) & (__INTERRUPT__)) == (__INTERRUPT__))
#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->ISTR) &= ~(__INTERRUPT__))
#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISTR) &= (uint16_t)(~(__INTERRUPT__))))
#define __HAL_USB_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= USB_WAKEUP_EXTI_LINE
#define __HAL_USB_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_WAKEUP_EXTI_LINE)
@ -377,10 +377,10 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
*/
/* SetENDPOINT */
#define PCD_SET_ENDPOINT(USBx, bEpNum,wRegValue) (*(&(USBx)->EP0R + (bEpNum) * 2)= (uint16_t)(wRegValue))
#define PCD_SET_ENDPOINT(USBx, bEpNum,wRegValue) (*((uint16_t *)(((uint32_t)(&(USBx)->EP0R + (bEpNum) * 2))))= (uint16_t)(wRegValue))
/* GetENDPOINT */
#define PCD_GET_ENDPOINT(USBx, bEpNum) (*(&(USBx)->EP0R + (bEpNum) * 2))
#define PCD_GET_ENDPOINT(USBx, bEpNum) (*((uint16_t *)(((uint32_t)(&(USBx)->EP0R + (bEpNum) * 2)))))
@ -392,7 +392,7 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
* @retval None
*/
#define PCD_SET_EPTYPE(USBx, bEpNum,wType) (PCD_SET_ENDPOINT((USBx), (bEpNum),\
((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_MASK) | (wType) )))
((((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & ((uint32_t)(USB_EP_T_MASK))) | ((uint32_t)(wType)) )))
/**
* @brief gets the type in the endpoint register(bits EP_TYPE[1:0])
@ -400,7 +400,7 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
* @param bEpNum: Endpoint Number.
* @retval Endpoint Type
*/
#define PCD_GET_EPTYPE(USBx, bEpNum) (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_FIELD)
#define PCD_GET_EPTYPE(USBx, bEpNum) (((uint16_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EP_T_FIELD)
/**
@ -432,9 +432,9 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
*/
#define PCD_GET_DB_DIR(USBx, bEpNum)\
{\
if ((uint16_t)(*PCD_EP_RX_CNT((USBx), (bEpNum)) & 0xFC00) != 0)\
if ((uint16_t)(*PCD_EP_RX_CNT((USBx), (bEpNum)) & 0xFC00U) != 0)\
return(PCD_EP_DBUF_OUT);\
else if (((uint16_t)(*PCD_EP_TX_CNT((USBx), (bEpNum))) & 0x03FF) != 0)\
else if (((uint16_t)(*PCD_EP_TX_CNT((USBx), (bEpNum))) & 0x03FFU) != 0)\
return(PCD_EP_DBUF_IN);\
else\
return(PCD_EP_DBUF_ERR);\
@ -447,17 +447,20 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
* @param wState: new state
* @retval None
*/
#define PCD_SET_EP_TX_STATUS(USBx, bEpNum, wState) {\
register uint16_t _wRegVal; \
#define PCD_SET_EP_TX_STATUS(USBx, bEpNum, wState) { register uint16_t _wRegVal;\
\
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_DTOGMASK;\
_wRegVal = (uint32_t) (((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPTX_DTOGMASK);\
/* toggle first bit ? */ \
if((USB_EPTX_DTOG1 & (wState))!= 0) \
_wRegVal ^= USB_EPTX_DTOG1; \
if((USB_EPTX_DTOG1 & (wState))!= 0)\
{ \
_wRegVal ^=(uint16_t) USB_EPTX_DTOG1; \
} \
/* toggle second bit ? */ \
if((USB_EPTX_DTOG2 & (wState))!= 0) \
_wRegVal ^= USB_EPTX_DTOG2; \
PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX|USB_EP_CTR_TX)); \
if((USB_EPTX_DTOG2 & ((uint32_t)(wState)))!= 0) \
{ \
_wRegVal ^=(uint16_t) USB_EPTX_DTOG2; \
} \
PCD_SET_ENDPOINT((USBx), (bEpNum), (((uint32_t)(_wRegVal)) | USB_EP_CTR_RX|USB_EP_CTR_TX));\
} /* PCD_SET_EP_TX_STATUS */
/**
@ -470,14 +473,18 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
#define PCD_SET_EP_RX_STATUS(USBx, bEpNum,wState) {\
register uint16_t _wRegVal; \
\
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_DTOGMASK;\
_wRegVal = (uint32_t) (((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPRX_DTOGMASK);\
/* toggle first bit ? */ \
if((USB_EPRX_DTOG1 & (wState))!= 0) \
_wRegVal ^= USB_EPRX_DTOG1; \
{ \
_wRegVal ^= (uint16_t) USB_EPRX_DTOG1; \
} \
/* toggle second bit ? */ \
if((USB_EPRX_DTOG2 & (wState))!= 0) \
_wRegVal ^= USB_EPRX_DTOG2; \
PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX|USB_EP_CTR_TX)); \
if((USB_EPRX_DTOG2 & ((uint32_t)(wState)))!= 0) \
{ \
_wRegVal ^= (uint16_t) USB_EPRX_DTOG2; \
} \
PCD_SET_ENDPOINT((USBx), (bEpNum), (((uint32_t)(_wRegVal)) | USB_EP_CTR_RX|USB_EP_CTR_TX)); \
} /* PCD_SET_EP_RX_STATUS */
/**
@ -494,16 +501,24 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (USB_EPRX_DTOGMASK |USB_EPTX_STAT) ;\
/* toggle first bit ? */ \
if((USB_EPRX_DTOG1 & ((wStaterx)))!= 0) \
{ \
_wRegVal ^= USB_EPRX_DTOG1; \
} \
/* toggle second bit ? */ \
if((USB_EPRX_DTOG2 & (wStaterx))!= 0) \
{ \
_wRegVal ^= USB_EPRX_DTOG2; \
} \
/* toggle first bit ? */ \
if((USB_EPTX_DTOG1 & (wStatetx))!= 0) \
{ \
_wRegVal ^= USB_EPTX_DTOG1; \
} \
/* toggle second bit ? */ \
if((USB_EPTX_DTOG2 & (wStatetx))!= 0) \
{ \
_wRegVal ^= USB_EPTX_DTOG2; \
} \
PCD_SET_ENDPOINT((USBx), (bEpNum), _wRegVal | USB_EP_CTR_RX|USB_EP_CTR_TX); \
} /* PCD_SET_EP_TXRX_STATUS */
@ -514,9 +529,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
* @param bEpNum: Endpoint Number.
* @retval status
*/
#define PCD_GET_EP_TX_STATUS(USBx, bEpNum) ((uint16_t)PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_STAT)
#define PCD_GET_EP_RX_STATUS(USBx, bEpNum) ((uint16_t)PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_STAT)
#define PCD_GET_EP_TX_STATUS(USBx, bEpNum) (((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPTX_STAT)
#define PCD_GET_EP_RX_STATUS(USBx, bEpNum) (((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPRX_STAT)
/**
* @brief sets directly the VALID tx/rx-status into the endpoint register
@ -525,7 +539,6 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
* @retval None
*/
#define PCD_SET_EP_TX_VALID(USBx, bEpNum) (PCD_SET_EP_TX_STATUS((USBx), (bEpNum), USB_EP_TX_VALID))
#define PCD_SET_EP_RX_VALID(USBx, bEpNum) (PCD_SET_EP_RX_STATUS((USBx), (bEpNum), USB_EP_RX_VALID))
/**
@ -546,9 +559,9 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
* @retval None
*/
#define PCD_SET_EP_KIND(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum), \
(USB_EP_CTR_RX|USB_EP_CTR_TX|((PCD_GET_ENDPOINT((USBx), (bEpNum)) | USB_EP_KIND) & USB_EPREG_MASK))))
(USB_EP_CTR_RX|USB_EP_CTR_TX|((((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) | USB_EP_KIND) & USB_EPREG_MASK))))
#define PCD_CLEAR_EP_KIND(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum), \
(USB_EP_CTR_RX|USB_EP_CTR_TX|(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPKIND_MASK))))
(USB_EP_CTR_RX|USB_EP_CTR_TX|((((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPKIND_MASK))))
/**
* @brief Sets/clears directly STATUS_OUT bit in the endpoint register.
@ -575,9 +588,9 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
* @retval None
*/
#define PCD_CLEAR_RX_EP_CTR(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum),\
PCD_GET_ENDPOINT((USBx), (bEpNum)) & 0x7FFF & USB_EPREG_MASK))
PCD_GET_ENDPOINT((USBx), (bEpNum)) & 0x7FFFU & USB_EPREG_MASK))
#define PCD_CLEAR_TX_EP_CTR(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum),\
PCD_GET_ENDPOINT((USBx), (bEpNum)) & 0xFF7F & USB_EPREG_MASK))
PCD_GET_ENDPOINT((USBx), (bEpNum)) & 0xFF7FU & USB_EPREG_MASK))
/**
* @brief Toggles DTOG_RX / DTOG_TX bit in the endpoint register.
@ -586,9 +599,9 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
* @retval None
*/
#define PCD_RX_DTOG(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum), \
USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_RX | (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK)))
USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_RX | (((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPREG_MASK)))
#define PCD_TX_DTOG(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum), \
USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_TX | (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK)))
USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_TX | (((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPREG_MASK)))
/**
* @brief Clears DTOG_RX / DTOG_TX bit in the endpoint register.
@ -596,10 +609,14 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
* @param bEpNum: Endpoint Number.
* @retval None
*/
#define PCD_CLEAR_RX_DTOG(USBx, bEpNum) if((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_DTOG_RX) != 0)\
PCD_RX_DTOG((USBx), (bEpNum))
#define PCD_CLEAR_TX_DTOG(USBx, bEpNum) if((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_DTOG_TX) != 0)\
PCD_TX_DTOG((USBx), (bEpNum))
#define PCD_CLEAR_RX_DTOG(USBx, bEpNum) if((((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EP_DTOG_RX) != 0)\
{ \
PCD_RX_DTOG((USBx),(bEpNum));\
}
#define PCD_CLEAR_TX_DTOG(USBx, bEpNum) if((((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EP_DTOG_TX) != 0)\
{\
PCD_TX_DTOG((USBx),(bEpNum));\
}
/**
* @brief Sets address in an endpoint register.
@ -609,7 +626,7 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
* @retval None
*/
#define PCD_SET_EP_ADDRESS(USBx, bEpNum,bAddr) PCD_SET_ENDPOINT((USBx), (bEpNum),\
USB_EP_CTR_RX|USB_EP_CTR_TX|(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK) | (bAddr))
USB_EP_CTR_RX|USB_EP_CTR_TX|(((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPREG_MASK) | (bAddr))
/**
* @brief Gets address in an endpoint register.
@ -619,10 +636,11 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
*/
#define PCD_GET_EP_ADDRESS(USBx, bEpNum) ((uint8_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPADDR_FIELD))
#define PCD_EP_TX_ADDRESS(USBx, bEpNum) ((uint16_t *)(((USBx)->BTABLE+(bEpNum)*8)+ ((uint32_t)(USBx) + 0x400)))
#define PCD_EP_TX_CNT(USBx, bEpNum) ((uint16_t *)(((USBx)->BTABLE+(bEpNum)*8+2)+ ((uint32_t)(USBx) + 0x400)))
#define PCD_EP_RX_ADDRESS(USBx, bEpNum) ((uint16_t *)(((USBx)->BTABLE+(bEpNum)*8+4)+ ((uint32_t)(USBx) + 0x400)))
#define PCD_EP_RX_CNT(USBx, bEpNum) ((uint16_t *)(((USBx)->BTABLE+(bEpNum)*8+6)+ ((uint32_t)(USBx) + 0x400)))
#define PCD_EP_TX_ADDRESS(USBx, bEpNum) ((uint16_t *)((uint32_t)((((USBx)->BTABLE+(bEpNum)*8)+ ((uint32_t)(USBx) + 0x400)))))
#define PCD_EP_TX_CNT(USBx, bEpNum) ((uint16_t *)((uint32_t)((((USBx)->BTABLE+(bEpNum)*8+2)+ ((uint32_t)(USBx) + 0x400)))))
#define PCD_EP_RX_ADDRESS(USBx, bEpNum) ((uint16_t *)((uint32_t)((((USBx)->BTABLE+(bEpNum)*8+4)+ ((uint32_t)(USBx) + 0x400)))))
#define PCD_EP_RX_CNT(USBx, bEpNum) ((uint16_t *)((uint32_t)((((USBx)->BTABLE+(bEpNum)*8+6)+ ((uint32_t)(USBx) + 0x400)))))
/**
* @brief sets address of the tx/rx buffer.
@ -653,27 +671,41 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
#define PCD_CALC_BLK32(dwReg,wCount,wNBlocks) {\
(wNBlocks) = (wCount) >> 5;\
if(((wCount) & 0x1f) == 0)\
{ \
(wNBlocks)--;\
*pdwReg = (uint16_t)(((wNBlocks) << 10) | 0x8000);\
} \
*pdwReg = (uint16_t)((uint16_t)((wNBlocks) << 10) | (uint16_t)0x8000); \
}/* PCD_CALC_BLK32 */
#define PCD_CALC_BLK2(dwReg,wCount,wNBlocks) {\
(wNBlocks) = (wCount) >> 1;\
if(((wCount) & 0x1) != 0)\
{ \
(wNBlocks)++;\
} \
*pdwReg = (uint16_t)((wNBlocks) << 10);\
}/* PCD_CALC_BLK2 */
#define PCD_SET_EP_CNT_RX_REG(dwReg,wCount) {\
uint16_t wNBlocks;\
if((wCount) > 62){PCD_CALC_BLK32((dwReg),(wCount),wNBlocks);}\
else {PCD_CALC_BLK2((dwReg),(wCount),wNBlocks);}\
if((wCount) > 62) \
{ \
PCD_CALC_BLK32((dwReg),(wCount),wNBlocks) \
} \
else \
{ \
PCD_CALC_BLK2((dwReg),(wCount),wNBlocks) \
} \
}/* PCD_SET_EP_CNT_RX_REG */
#define PCD_SET_EP_RX_DBUF0_CNT(USBx, bEpNum,wCount) {\
uint16_t *pdwReg = PCD_EP_TX_CNT((USBx), (bEpNum)); \
PCD_SET_EP_CNT_RX_REG(pdwReg, (wCount));\
PCD_SET_EP_CNT_RX_REG(pdwReg, (wCount))\
}
/**
* @brief sets counter for the tx/rx buffer.
* @param USBx: USB peripheral instance register address.
@ -683,8 +715,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
*/
#define PCD_SET_EP_TX_CNT(USBx, bEpNum,wCount) (*PCD_EP_TX_CNT((USBx), (bEpNum)) = (wCount))
#define PCD_SET_EP_RX_CNT(USBx, bEpNum,wCount) {\
uint16_t *pdwReg = PCD_EP_RX_CNT(USBx, bEpNum); \
PCD_SET_EP_CNT_RX_REG(pdwReg, wCount);\
uint16_t *pdwReg =PCD_EP_RX_CNT((USBx),(bEpNum)); \
PCD_SET_EP_CNT_RX_REG((pdwReg), (wCount))\
}
/**
@ -703,8 +735,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
* @param wBuf0Addr: buffer 0 address.
* @retval Counter value
*/
#define PCD_SET_EP_DBUF0_ADDR(USBx, bEpNum,wBuf0Addr) {PCD_SET_EP_TX_ADDRESS((USBx), (bEpNum), (wBuf0Addr));}
#define PCD_SET_EP_DBUF1_ADDR(USBx, bEpNum,wBuf1Addr) {PCD_SET_EP_RX_ADDRESS((USBx), (bEpNum), (wBuf1Addr));}
#define PCD_SET_EP_DBUF0_ADDR(USBx, bEpNum,wBuf0Addr) (PCD_SET_EP_TX_ADDRESS((USBx), (bEpNum), (wBuf0Addr)))
#define PCD_SET_EP_DBUF1_ADDR(USBx, bEpNum,wBuf1Addr) (PCD_SET_EP_RX_ADDRESS((USBx), (bEpNum), (wBuf1Addr)))
/**
* @brief Sets addresses in a double buffer endpoint.
@ -740,24 +772,27 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
#define PCD_SET_EP_DBUF0_CNT(USBx, bEpNum, bDir, wCount) { \
if((bDir) == PCD_EP_DBUF_OUT)\
/* OUT endpoint */ \
{PCD_SET_EP_RX_DBUF0_CNT((USBx), (bEpNum),(wCount));} \
{PCD_SET_EP_RX_DBUF0_CNT((USBx), (bEpNum),(wCount))} \
else if((bDir) == PCD_EP_DBUF_IN)\
/* IN endpoint */ \
{ \
*PCD_EP_TX_CNT((USBx), (bEpNum)) = (uint32_t)(wCount); \
} \
} /* SetEPDblBuf0Count*/
#define PCD_SET_EP_DBUF1_CNT(USBx, bEpNum, bDir, wCount) { \
if((bDir) == PCD_EP_DBUF_OUT)\
/* OUT endpoint */ \
{PCD_SET_EP_RX_CNT((USBx), (bEpNum),(wCount));}\
{/* OUT endpoint */ \
PCD_SET_EP_RX_CNT((USBx), (bEpNum),(wCount)) \
} \
else if((bDir) == PCD_EP_DBUF_IN)\
/* IN endpoint */\
{/* IN endpoint */ \
*PCD_EP_TX_CNT((USBx), (bEpNum)) = (uint32_t)(wCount); \
} /* SetEPDblBuf1Count */
} \
} /* SetEPDblBuf1Count */
#define PCD_SET_EP_DBUF_CNT(USBx, bEpNum, bDir, wCount) {\
PCD_SET_EP_DBUF0_CNT((USBx), (bEpNum), (bDir), (wCount)); \
PCD_SET_EP_DBUF1_CNT((USBx), (bEpNum), (bDir), (wCount)); \
PCD_SET_EP_DBUF0_CNT((USBx), (bEpNum), (bDir), (wCount)) \
PCD_SET_EP_DBUF1_CNT((USBx), (bEpNum), (bDir), (wCount)) \
} /* PCD_SET_EP_DBUF_CNT */
/**

12
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pcd_ex.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_pcd_ex.c
* @author MCD Application Team
* @version V1.3.1
* @date 29-January-2016
* @version V1.4.0
* @date 27-May-2016
* @brief Extended PCD HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the USB Peripheral Controller:
@ -42,14 +42,14 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32f0xx_hal.h"
/** @addtogroup STM32F0xx_HAL_Driver
* @{
*/
#ifdef HAL_PCD_MODULE_ENABLED
#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)|| defined(STM32F070x6)
/** @addtogroup STM32F0xx_HAL_Driver
* @{
*/
/** @defgroup PCDEx PCDEx
* @brief PCD Extended HAL module driver
* @{

4
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pcd_ex.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_pcd_ex.h
* @author MCD Application Team
* @version V1.3.1
* @date 29-January-2016
* @version V1.4.0
* @date 27-May-2016
* @brief Header file of PCD HAL Extension module.
******************************************************************************
* @attention

10
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pwr.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_pwr.c
* @author MCD Application Team
* @version V1.3.1
* @date 29-January-2016
* @version V1.4.0
* @date 27-May-2016
* @brief PWR HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Power Controller (PWR) peripheral:
@ -250,7 +250,8 @@ void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx)
{
/* Check the parameters */
assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
PWR->CSR |= (PWR_CSR_EWUP1 << (uint8_t)WakeUpPinx);
/* Enable the EWUPx pin */
SET_BIT(PWR->CSR, WakeUpPinx);
}
/**
@ -264,7 +265,8 @@ void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
{
/* Check the parameters */
assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
PWR->CSR &= ~(PWR_CSR_EWUP1 << (uint8_t)WakeUpPinx);
/* Disable the EWUPx pin */
CLEAR_BIT(PWR->CSR, WakeUpPinx);
}
/**

4
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pwr.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_pwr.h
* @author MCD Application Team
* @version V1.3.1
* @date 29-January-2016
* @version V1.4.0
* @date 27-May-2016
* @brief Header file of PWR HAL module.
******************************************************************************
* @attention

4
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pwr_ex.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_pwr_ex.c
* @author MCD Application Team
* @version V1.3.1
* @date 29-January-2016
* @version V1.4.0
* @date 27-May-2016
* @brief Extended PWR HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Power Controller (PWR) peripheral:

65
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pwr_ex.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_pwr_ex.h
* @author MCD Application Team
* @version V1.3.1
* @date 29-January-2016
* @version V1.4.0
* @date 27-May-2016
* @brief Header file of PWR HAL Extension module.
******************************************************************************
* @attention
@ -92,16 +92,16 @@ typedef struct
/** @defgroup PWREx_WakeUp_Pins PWREx Wakeup Pins
* @{
*/
#if defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || defined (STM32F070xB) || \
defined (STM32F091xC) || defined (STM32F098xx) || defined (STM32F030xC)
#define PWR_WAKEUP_PIN1 ((uint32_t)0x00)
#define PWR_WAKEUP_PIN2 ((uint32_t)0x01)
#define PWR_WAKEUP_PIN3 ((uint32_t)0x02)
#define PWR_WAKEUP_PIN4 ((uint32_t)0x03)
#define PWR_WAKEUP_PIN5 ((uint32_t)0x04)
#define PWR_WAKEUP_PIN6 ((uint32_t)0x05)
#define PWR_WAKEUP_PIN7 ((uint32_t)0x06)
#define PWR_WAKEUP_PIN8 ((uint32_t)0x07)
#if defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
defined (STM32F091xC) || defined (STM32F098xx)
#define PWR_WAKEUP_PIN1 ((uint32_t)PWR_CSR_EWUP1)
#define PWR_WAKEUP_PIN2 ((uint32_t)PWR_CSR_EWUP2)
#define PWR_WAKEUP_PIN3 ((uint32_t)PWR_CSR_EWUP3)
#define PWR_WAKEUP_PIN4 ((uint32_t)PWR_CSR_EWUP4)
#define PWR_WAKEUP_PIN5 ((uint32_t)PWR_CSR_EWUP5)
#define PWR_WAKEUP_PIN6 ((uint32_t)PWR_CSR_EWUP6)
#define PWR_WAKEUP_PIN7 ((uint32_t)PWR_CSR_EWUP7)
#define PWR_WAKEUP_PIN8 ((uint32_t)PWR_CSR_EWUP8)
#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \
((PIN) == PWR_WAKEUP_PIN2) || \
@ -111,14 +111,45 @@ typedef struct
((PIN) == PWR_WAKEUP_PIN6) || \
((PIN) == PWR_WAKEUP_PIN7) || \
((PIN) == PWR_WAKEUP_PIN8))
#else
#define PWR_WAKEUP_PIN1 ((uint32_t)0x00)
#define PWR_WAKEUP_PIN2 ((uint32_t)0x01)
#elif defined(STM32F030xC) || defined (STM32F070xB)
#define PWR_WAKEUP_PIN1 ((uint32_t)PWR_CSR_EWUP1)
#define PWR_WAKEUP_PIN2 ((uint32_t)PWR_CSR_EWUP2)
#define PWR_WAKEUP_PIN4 ((uint32_t)PWR_CSR_EWUP4)
#define PWR_WAKEUP_PIN5 ((uint32_t)PWR_CSR_EWUP5)
#define PWR_WAKEUP_PIN6 ((uint32_t)PWR_CSR_EWUP6)
#define PWR_WAKEUP_PIN7 ((uint32_t)PWR_CSR_EWUP7)
#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \
((PIN) == PWR_WAKEUP_PIN2) || \
((PIN) == PWR_WAKEUP_PIN4) || \
((PIN) == PWR_WAKEUP_PIN5) || \
((PIN) == PWR_WAKEUP_PIN6) || \
((PIN) == PWR_WAKEUP_PIN7))
#elif defined(STM32F042x6) || defined (STM32F048xx)
#define PWR_WAKEUP_PIN1 ((uint32_t)PWR_CSR_EWUP1)
#define PWR_WAKEUP_PIN2 ((uint32_t)PWR_CSR_EWUP2)
#define PWR_WAKEUP_PIN4 ((uint32_t)PWR_CSR_EWUP4)
#define PWR_WAKEUP_PIN6 ((uint32_t)PWR_CSR_EWUP6)
#define PWR_WAKEUP_PIN7 ((uint32_t)PWR_CSR_EWUP7)
#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \
((PIN) == PWR_WAKEUP_PIN2) || \
((PIN) == PWR_WAKEUP_PIN4) || \
((PIN) == PWR_WAKEUP_PIN6) || \
((PIN) == PWR_WAKEUP_PIN7))
#else
#define PWR_WAKEUP_PIN1 ((uint32_t)PWR_CSR_EWUP1)
#define PWR_WAKEUP_PIN2 ((uint32_t)PWR_CSR_EWUP2)
#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \
((PIN) == PWR_WAKEUP_PIN2))
#endif /* defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || defined (STM32F070xB) || */
/* defined (STM32F091xC) || defined (STM32F098xx) || defined (STM32F030xC) */
#endif
/**
* @}
*/

210
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rcc.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_rcc.c
* @author MCD Application Team
* @version V1.3.1
* @date 29-January-2016
* @version V1.4.0
* @date 27-May-2016
* @brief RCC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Reset and Clock Control (RCC) peripheral:
@ -75,7 +75,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f0xx_hal.h"
@ -116,7 +116,6 @@
/** @defgroup RCC_Private_Variables RCC Private Variables
* @{
*/
const uint8_t aAPBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
/**
* @}
*/
@ -193,7 +192,16 @@ const uint8_t aAPBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4,
(++) IWDG clock which is always the LSI clock.
(#) For the STM32F0xx devices, the maximum frequency of the SYSCLK, HCLK and PCLK1 is 48 MHz,
Depending on the SYSCLK frequency, the flash latency should be adapted accordingly:
Depending on the SYSCLK frequency, the flash latency should be adapted accordingly.
(#) After reset, the System clock source is the HSI (8 MHz) with 0 WS and
prefetch is disabled.
@endverbatim
* @{
*/
/*
Additional consideration on the SYSCLK based on Latency settings:
+-----------------------------------------------+
| Latency | SYSCLK clock frequency (MHz) |
|---------------|-------------------------------|
@ -201,11 +209,6 @@ const uint8_t aAPBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4,
|---------------|-------------------------------|
|1WS(2CPU cycle)| 24 < SYSCLK <= 48 |
+-----------------------------------------------+
(#) After reset, the System clock source is the HSI (8 MHz) with 0 WS and
prefetch is disabled.
@endverbatim
* @{
*/
/**
@ -216,9 +219,9 @@ const uint8_t aAPBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4,
* - AHB, APB1 prescaler set to 1.
* - CSS and MCO1 OFF
* - All interrupts disabled
* @note This function doesn't modify the configuration of the
* - Peripheral clocks
* - LSI, LSE and RTC clocks
* @note This function does not modify the configuration of the
* - Peripheral clocks
* - LSI, LSE and RTC clocks
* @retval None
*/
void HAL_RCC_DeInit(void)
@ -246,6 +249,9 @@ void HAL_RCC_DeInit(void)
/* Disable all interrupts */
CLEAR_REG(RCC->CIR);
/* Update the SystemCoreClock global variable */
SystemCoreClock = HSI_VALUE;
}
/**
@ -254,6 +260,12 @@ void HAL_RCC_DeInit(void)
* @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that
* contains the configuration information for the RCC Oscillators.
* @note The PLL is not disabled when used as system clock.
* @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
* supported by this macro. User should request a transition to LSE Off
* first and then LSE On or LSE Bypass.
* @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
* supported by this macro. User should request a transition to HSE Off
* first and then HSE On or HSE Bypass.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
@ -281,21 +293,6 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
}
else
{
/* Reset HSEON and HSEBYP bits before configuring the HSE --------------*/
__HAL_RCC_HSE_CONFIG(RCC_HSE_OFF);
/* Get Start Tick */
tickstart = HAL_GetTick();
/* Wait till HSE is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
{
if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
/* Set the new HSE configuration ---------------------------------------*/
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
@ -320,7 +317,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
/* Get Start Tick */
tickstart = HAL_GetTick();
/* Wait till HSE is bypassed or disabled */
/* Wait till HSE is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
{
if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
@ -441,41 +438,36 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
/*------------------------------ LSE Configuration -------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
{
FlagStatus pwrclkchanged = RESET;
/* Check the parameters */
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
/* Enable Power Clock*/
__HAL_RCC_PWR_CLK_ENABLE();
/* Enable write access to Backup domain */
SET_BIT(PWR->CR, PWR_CR_DBP);
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
while((PWR->CR & PWR_CR_DBP) == RESET)
/* Update LSE configuration in Backup Domain control register */
/* Requires to enable write access to Backup Domain of necessary */
if(__HAL_RCC_PWR_IS_CLK_DISABLED())
{
if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
__HAL_RCC_PWR_CLK_ENABLE();
pwrclkchanged = SET;
}
/* Reset LSEON and LSEBYP bits before configuring the LSE ----------------*/
__HAL_RCC_LSE_CONFIG(RCC_LSE_OFF);
/* Get Start Tick */
tickstart = HAL_GetTick();
/* Wait till LSE is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
/* Enable write access to Backup domain */
SET_BIT(PWR->CR, PWR_CR_DBP);
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
{
return HAL_TIMEOUT;
if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
}
/* Set the new LSE configuration -----------------------------------------*/
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
/* Check the LSE State */
@ -507,6 +499,12 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
}
}
}
/* Require to disable power clock if necessary */
if(pwrclkchanged == SET)
{
__HAL_RCC_PWR_CLK_DISABLE();
}
}
/*----------------------------- HSI14 Configuration --------------------------*/
@ -570,7 +568,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
}
}
#if defined(RCC_CR2_HSI48ON)
#if defined(RCC_HSI48_SUPPORT)
/*----------------------------- HSI48 Configuration --------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48)
{
@ -588,7 +586,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
}
else
{
/* Check the HSI State */
/* Check the HSI48 State */
if(RCC_OscInitStruct->HSI48State != RCC_HSI48_OFF)
{
/* Enable the Internal High Speed oscillator (HSI48). */
@ -597,7 +595,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
/* Get Start Tick */
tickstart = HAL_GetTick();
/* Wait till HSI is ready */
/* Wait till HSI48 is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == RESET)
{
if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE)
@ -614,7 +612,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
/* Get Start Tick */
tickstart = HAL_GetTick();
/* Wait till HSI is ready */
/* Wait till HSI48 is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != RESET)
{
if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE)
@ -625,7 +623,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
}
}
}
#endif /* RCC_CR2_HSI48ON */
#endif /* RCC_HSI48_SUPPORT */
/*-------------------------------- PLL Configuration -----------------------*/
/* Check the parameters */
@ -783,7 +781,7 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui
return HAL_ERROR;
}
}
#if defined(RCC_CR2_HSI48ON)
#if defined(RCC_CFGR_SWS_HSI48)
/* HSI48 is selected as System Clock Source */
else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI48)
{
@ -793,7 +791,7 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui
return HAL_ERROR;
}
}
#endif /* RCC_CR2_HSI48ON */
#endif /* RCC_CFGR_SWS_HSI48 */
/* HSI is selected as System Clock Source */
else
{
@ -828,7 +826,7 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui
}
}
}
#if defined(RCC_CR2_HSI48ON)
#if defined(RCC_CFGR_SWS_HSI48)
else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI48)
{
while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI48)
@ -839,7 +837,7 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui
}
}
}
#endif /* RCC_CR2_HSI48ON */
#endif /* RCC_CFGR_SWS_HSI48 */
else
{
while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
@ -865,7 +863,6 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui
}
}
/*-------------------------- PCLK1 Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
{
@ -873,6 +870,9 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_ClkInitStruct->APB1CLKDivider);
}
/* Update the SystemCoreClock global variable */
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_BITNUMBER];
/* Configure the source of time base considering new system clocks settings*/
HAL_InitTick (TICK_INT_PRIORITY);
@ -883,8 +883,8 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui
* @}
*/
/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions
* @brief RCC clocks control functions
/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions
* @brief RCC clocks control functions
*
@verbatim
===============================================================================
@ -904,7 +904,7 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui
* @note MCO pin should be configured in alternate function mode.
* @param RCC_MCOx specifies the output direction for the clock source.
* This parameter can be one of the following values:
* @arg @ref RCC_MCO Clock source to output on MCO1 pin(PA8).
* @arg @ref RCC_MCO1 Clock source to output on MCO1 pin(PA8).
* @param RCC_MCOSource specifies the clock source to output.
* This parameter can be one of the following values:
* @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected
@ -916,20 +916,38 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui
* @arg @ref RCC_MCO1SOURCE_HSI14 HSI14 selected as MCO clock
@if STM32F042x6
* @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock
* @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock
@elseif STM32F048xx
* @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock
* @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock
@elseif STM32F071xB
* @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock
* @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock
@elseif STM32F072xB
* @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock
* @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock
@elseif STM32F078xx
* @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock
* @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock
@elseif STM32F091xC
* @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock
* @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock
@elseif STM32F098xx
* @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock
* @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock
@elif STM32F030x6
* @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock
@elif STM32F030xC
* @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock
@elif STM32F031x6
* @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock
@elif STM32F038xx
* @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock
@elif STM32F070x6
* @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock
@elif STM32F070xB
* @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock
@endif
* @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock (not applicable to STM32F05x devices)
* @arg @ref RCC_MCO1SOURCE_PLLCLK_DIV2 PLLCLK Divided by 2 selected as MCO clock
* @param RCC_MCODiv specifies the MCO DIV.
* This parameter can be one of the following values:
@ -949,7 +967,7 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui
* @note MCO pin should be configured in alternate function mode.
* @param RCC_MCOx specifies the output direction for the clock source.
* This parameter can be one of the following values:
* @arg @ref RCC_MCO Clock source to output on MCO1 pin(PA8).
* @arg @ref RCC_MCO1 Clock source to output on MCO1 pin(PA8).
* @param RCC_MCOSource specifies the clock source to output.
* This parameter can be one of the following values:
* @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock
@ -975,15 +993,16 @@ void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_M
assert_param(IS_RCC_MCODIV(RCC_MCODiv));
assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));
/* MCO Clock Enable */
MCO1_CLK_ENABLE();
/* Configure the MCO1 pin in alternate function mode */
gpio.Pin = MCO1_PIN;
gpio.Mode = GPIO_MODE_AF_PP;
gpio.Speed = GPIO_SPEED_FREQ_HIGH;
gpio.Pull = GPIO_NOPULL;
gpio.Pin = MCO1_PIN;
gpio.Alternate = GPIO_AF0_MCO;
/* MCO1 Clock Enable */
MCO1_CLK_ENABLE();
HAL_GPIO_Init(MCO1_GPIO_PORT, &gpio);
/* Configure the MCO clock source */
@ -1073,13 +1092,13 @@ uint32_t HAL_RCC_GetSysClockFreq(void)
/* HSE used as PLL clock source : PLLCLK = HSE/PREDIV * PLLMUL */
pllclk = (HSE_VALUE / prediv) * pllmul;
}
#if defined(RCC_CR2_HSI48ON)
#if defined(RCC_CFGR_PLLSRC_HSI48_PREDIV)
else if ((tmpreg & RCC_CFGR_PLLSRC) == RCC_PLLSOURCE_HSI48)
{
/* HSI48 used as PLL clock source : PLLCLK = HSI48/PREDIV * PLLMUL */
pllclk = (HSI48_VALUE / prediv) * pllmul;
}
#endif /* RCC_CR2_HSI48ON */
#endif /* RCC_CFGR_PLLSRC_HSI48_PREDIV */
else
{
#if (defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC))
@ -1093,13 +1112,13 @@ uint32_t HAL_RCC_GetSysClockFreq(void)
sysclockfreq = pllclk;
break;
}
#if defined(RCC_CR2_HSI48ON)
#if defined(RCC_CFGR_SWS_HSI48)
case RCC_SYSCLKSOURCE_STATUS_HSI48: /* HSI48 used as system clock source */
{
sysclockfreq = HSI48_VALUE;
break;
}
#endif /* RCC_CR2_HSI48ON */
#endif /* RCC_CFGR_SWS_HSI48 */
case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
default: /* HSI used as system clock */
{
@ -1121,7 +1140,6 @@ uint32_t HAL_RCC_GetSysClockFreq(void)
*/
uint32_t HAL_RCC_GetHCLKFreq(void)
{
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> aAPBAHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_BITNUMBER];
return SystemCoreClock;
}
@ -1134,7 +1152,7 @@ uint32_t HAL_RCC_GetHCLKFreq(void)
uint32_t HAL_RCC_GetPCLK1Freq(void)
{
/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
return (HAL_RCC_GetHCLKFreq() >> aAPBAHBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE)>> RCC_CFGR_PPRE_BITNUMBER]);
return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE) >> RCC_CFGR_PPRE_BITNUMBER]);
}
/**
@ -1152,9 +1170,9 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
/* Set all possible values for the Oscillator type parameter ---------------*/
RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI \
| RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_HSI14;
#if defined(RCC_CR2_HSI48ON)
#if defined(RCC_HSI48_SUPPORT)
RCC_OscInitStruct->OscillatorType |= RCC_OSCILLATORTYPE_HSI48;
#endif /* RCC_CR2_HSI48ON */
#endif /* RCC_HSI48_SUPPORT */
/* Get the HSE configuration -----------------------------------------------*/
@ -1207,19 +1225,6 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
}
/* Get the PLL configuration -----------------------------------------------*/
if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON)
{
RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
}
else
{
RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
}
RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLSRC);
RCC_OscInitStruct->PLL.PLLMUL = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLMUL);
RCC_OscInitStruct->PLL.PREDIV = (uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV);
/* Get the HSI14 configuration -----------------------------------------------*/
if((RCC->CR2 & RCC_CR2_HSI14ON) == RCC_CR2_HSI14ON)
{
@ -1232,10 +1237,23 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
RCC_OscInitStruct->HSI14CalibrationValue = (uint32_t)((RCC->CR2 & RCC_CR2_HSI14TRIM) >> RCC_HSI14TRIM_BIT_NUMBER);
#if defined(RCC_CR2_HSI48ON)
#if defined(RCC_HSI48_SUPPORT)
/* Get the HSI48 configuration if any-----------------------------------------*/
RCC_OscInitStruct->HSI48State = __HAL_RCC_GET_HSI48_STATE();
#endif /* RCC_CR2_HSI48ON */
#endif /* RCC_HSI48_SUPPORT */
/* Get the PLL configuration -----------------------------------------------*/
if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON)
{
RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
}
else
{
RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
}
RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLSRC);
RCC_OscInitStruct->PLL.PLLMUL = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLMUL);
RCC_OscInitStruct->PLL.PREDIV = (uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV);
}
/**

113
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rcc.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_rcc.h
* @author MCD Application Team
* @version V1.3.1
* @date 29-January-2016
* @version V1.4.0
* @date 27-May-2016
* @brief Header file of RCC HAL module.
******************************************************************************
* @attention
@ -68,12 +68,13 @@
#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
#define CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */
#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
#define HSI_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */
#define LSI_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */
#define PLL_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */
#define HSI14_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */
#define HSI48_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */
#define HSI_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms (minimum Tick + 1) */
#define LSI_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms (minimum Tick + 1) */
#define PLL_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms (minimum Tick + 1) */
#define HSI14_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms (minimum Tick + 1) */
#if defined(RCC_HSI48_SUPPORT)
#define HSI48_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms (minimum Tick + 1) */
#endif /* RCC_HSI48_SUPPORT */
/**
* @}
*/
@ -108,10 +109,10 @@
#define BDCR_REG_INDEX ((uint8_t)3)
#define CSR_REG_INDEX ((uint8_t)4)
/* Flags in the CFGR register */
#define RCC_CFGR_PLLMUL_BITNUMBER 18
#define RCC_CFGR_HPRE_BITNUMBER 4
#define RCC_CFGR_PPRE_BITNUMBER 8
/* Bits position in in the CFGR register */
#define RCC_CFGR_PLLMUL_BITNUMBER 18U
#define RCC_CFGR_HPRE_BITNUMBER 4U
#define RCC_CFGR_PPRE_BITNUMBER 8U
/* Flags in the CFGR2 register */
#define RCC_CFGR2_PREDIV_BITNUMBER 0
/* Flags in the CR register */
@ -225,7 +226,7 @@ typedef struct
} RCC_PLLInitTypeDef;
/**
/**
* @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
*/
typedef struct
@ -235,49 +236,49 @@ typedef struct
uint32_t HSEState; /*!< The new state of the HSE.
This parameter can be a value of @ref RCC_HSE_Config */
uint32_t LSEState; /*!< The new state of the LSE.
This parameter can be a value of @ref RCC_LSE_Config */
uint32_t HSIState; /*!< The new state of the HSI.
This parameter can be a value of @ref RCC_HSI_Config */
uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
uint32_t HSI14State; /*!< The new state of the HSI14.
This parameter can be a value of @ref RCC_HSI14_Config */
uint32_t HSI14CalibrationValue; /*!< The HSI14 calibration trimming value (default is RCC_HSI14CALIBRATION_DEFAULT).
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
uint32_t HSI48State; /*!< The new state of the HSI48 (only applicable to STM32F07x, STM32F0x2 and STM32F09x devices).
This parameter can be a value of @ref RCCEx_HSI48_Config */
uint32_t LSIState; /*!< The new state of the LSI.
This parameter can be a value of @ref RCC_LSI_Config */
uint32_t HSI48State; /*!< The new state of the HSI48.
This parameter can be a value of @ref RCC_HSI48_Config */
RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */
} RCC_OscInitTypeDef;
/**
/**
* @brief RCC System, AHB and APB busses clock configuration structure definition
*/
typedef struct
{
uint32_t ClockType; /*!< The clock to be configured.
This parameter can be a value of @ref RCC_System_Clock_Type */
uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.
This parameter can be a value of @ref RCC_System_Clock_Source */
uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
This parameter can be a value of @ref RCC_AHB_Clock_Source */
uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
This parameter can be a value of @ref RCC_APB1_Clock_Source */
} RCC_ClkInitTypeDef;
/**
@ -308,6 +309,9 @@ typedef struct
#define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004)
#define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008)
#define RCC_OSCILLATORTYPE_HSI14 ((uint32_t)0x00000010)
#if defined(RCC_HSI48_SUPPORT)
#define RCC_OSCILLATORTYPE_HSI48 ((uint32_t)0x00000020)
#endif /* RCC_HSI48_SUPPORT */
/**
* @}
*/
@ -336,8 +340,8 @@ typedef struct
/** @defgroup RCC_HSI_Config HSI Config
* @{
*/
#define RCC_HSI_OFF ((uint32_t)0x00000000) /*!< HSI clock deactivation */
#define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */
#define RCC_HSI_OFF ((uint32_t)0x00000000) /*!< HSI clock deactivation */
#define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */
#define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x10) /* Default HSI calibration trimming value */
@ -367,6 +371,18 @@ typedef struct
* @}
*/
#if defined(RCC_HSI48_SUPPORT)
/** @defgroup RCC_HSI48_Config HSI48 Config
* @{
*/
#define RCC_HSI48_OFF ((uint8_t)0x00)
#define RCC_HSI48_ON ((uint8_t)0x01)
/**
* @}
*/
#endif /* RCC_HSI48_SUPPORT */
/** @defgroup RCC_PLL_Config PLL Config
* @{
*/
@ -445,8 +461,8 @@ typedef struct
* @{
*/
#define RCC_RTCCLKSOURCE_NO_CLK ((uint32_t)0x00000000) /*!< No clock */
#define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_LSE /*!< LSE oscillator clock used as RTC clock */
#define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_LSI /*!< LSI oscillator clock used as RTC clock */
#define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_LSE /*!< LSE oscillator clock used as RTC clock */
#define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_LSI /*!< LSI oscillator clock used as RTC clock */
#define RCC_RTCCLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL_HSE /*!< HSE oscillator clock divided by 32 used as RTC clock */
/**
* @}
@ -587,7 +603,6 @@ typedef struct
#if defined(RCC_CSR_V18PWRRSTF)
#define RCC_FLAG_V18PWRRST ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_V18PWRRSTF_BitNumber))
#endif
#define RCC_FLAG_RMV ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_RMVF_BitNumber))
#define RCC_FLAG_OBLRST ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_OBLRSTF_BitNumber))
#define RCC_FLAG_PINRST ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_PINRSTF_BitNumber)) /*!< PIN reset flag */
#define RCC_FLAG_PORRST ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_PORRSTF_BitNumber)) /*!< POR/PDR reset flag */
@ -1028,7 +1043,7 @@ typedef struct
* PLL as system clock. In this case, you have to select another source
* of the system clock then change the HSE state (ex. disable it).
* @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
* @note This function reset the CSSON bit, so if the Clock security system(CSS)
* @note This function reset the CSSON bit, so if the clock security system(CSS)
* was previously enabled you have to enable it again after calling this
* function.
* @param __STATE__ specifies the new state of the HSE.
@ -1272,14 +1287,14 @@ typedef struct
/**
* @brief Macro to configure the system clock source.
* @param __RCC_SYSCLKSOURCE__ specifies the system clock source.
* @param __SYSCLKSOURCE__ specifies the system clock source.
* This parameter can be one of the following values:
* @arg @ref RCC_SYSCLKSOURCE_HSI HSI oscillator is used as system clock source.
* @arg @ref RCC_SYSCLKSOURCE_HSE HSE oscillator is used as system clock source.
* @arg @ref RCC_SYSCLKSOURCE_PLLCLK PLL output is used as system clock source.
*/
#define __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) \
MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__))
#define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \
MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__))
/** @brief Macro to get the clock source used as system clock.
* @retval The clock source used as system clock. The returned value can be one
@ -1310,21 +1325,39 @@ typedef struct
* @arg @ref RCC_MCO1SOURCE_LSE LSE selected as MCO clock
* @arg @ref RCC_MCO1SOURCE_HSI14 HSI14 selected as MCO clock
@if STM32F042x6
* @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock
* @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock
* @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock
@elseif STM32F048xx
* @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock
* @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock
* @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock
@elseif STM32F071xB
* @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock
* @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock
* @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock
@elseif STM32F072xB
* @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock
* @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock
* @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock
@elseif STM32F078xx
* @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock
* @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock
* @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock
@elseif STM32F091xC
* @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock
* @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock
* @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock
@elseif STM32F098xx
* @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock
* @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock
* @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock
@elseif STM32F030x6
* @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock
@elseif STM32F030xC
* @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock
@elseif STM32F031x6
* @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock
@elseif STM32F038xx
* @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock
@elseif STM32F070x6
* @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock
@elseif STM32F070xB
* @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock
@endif
* @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock
* @arg @ref RCC_MCO1SOURCE_PLLCLK_DIV2 PLLCLK Divided by 2 selected as MCO clock
* @param __MCODIV__ specifies the MCO clock prescaler.
* This parameter can be one of the following values:

394
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rcc_ex.c
View File

@ -2,61 +2,14 @@
******************************************************************************
* @file stm32f0xx_hal_rcc_ex.c
* @author MCD Application Team
* @version V1.3.1
* @date 29-January-2016
* @brief Extended RCC HAL module driver
* @version V1.4.0
* @date 27-May-2016
* @brief Extended RCC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities RCC extension peripheral:
* + Extended Peripheral Control functions
*
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
For CRS, RCC Extention HAL driver can be used as follows:
(#) In System clock config, HSI48 need to be enabled
(#] Enable CRS clock in IP MSP init which will use CRS functions
(#) Call CRS functions like this
(##) Prepare synchronization configuration necessary for HSI48 calibration
(+++) Default values can be set for frequency Error Measurement (reload and error limit)
and also HSI48 oscillator smooth trimming.
(+++) Macro @ref __HAL_RCC_CRS_RELOADVALUE_CALCULATE can be also used to calculate
directly reload value with target and synchronization frequencies values
(##) Call function @ref HAL_RCCEx_CRSConfig which
(+++) Reset CRS registers to their default values.
(+++) Configure CRS registers with synchronization configuration
(+++) Enable automatic calibration and frequency error counter feature
(##) A polling function is provided to wait for complete Synchronization
(+++) Call function @ref HAL_RCCEx_CRSWaitSynchronization()
(+++) According to CRS status, user can decide to adjust again the calibration or continue
application if synchronization is OK
(#) User can retrieve information related to synchronization in calling function
@ref HAL_RCCEx_CRSGetSynchronizationInfo()
(#) Regarding synchronization status and synchronization information, user can try a new calibration
in changing synchronization configuration and call again HAL_RCCEx_CRSConfig.
Note: When the SYNC event is detected during the downcounting phase (before reaching the zero value),
it means that the actual frequency is lower than the target (and so, that the TRIM value should be
incremented), while when it is detected during the upcounting phase it means that the actual frequency
is higher (and that the TRIM value should be decremented).
(#) To use IT mode, user needs to handle it in calling different macros available to do it
(__HAL_RCC_CRS_XXX_IT). Interuptions will go through RCC Handler (RCC_IRQn/RCC_CRS_IRQHandler)
(++) Call function @ref HAL_RCCEx_CRSConfig()
(++) Enable RCC_IRQn (thnaks to NVIC functions)
(++) Enable CRS IT (@ref __HAL_RCC_CRS_ENABLE_IT)
(++) Implement CRS status management in @ref RCC_CRS_IRQHandler
(#) To force a SYNC EVENT, user can use function @ref HAL_RCCEx_CRSSoftwareSynchronizationGenerate(). Function can be
called before calling @ref HAL_RCCEx_CRSConfig (for instance in Systick handler)
@endverbatim
* + Extended Clock Recovery System Control functions
*
******************************************************************************
* @attention
*
@ -135,7 +88,7 @@
/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions
* @brief Extended Peripheral Control functions
*
@verbatim
@verbatim
===============================================================================
##### Extended Peripheral Control functions #####
===============================================================================
@ -146,7 +99,7 @@
(@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
select the RTC clock source; in this case the Backup domain will be reset in
order to modify the RTC Clock source, as consequence RTC registers (including
the backup registers) and RCC_BDCR register are set to their reset values.
the backup registers) are set to their reset values.
@endverbatim
* @{
@ -180,25 +133,37 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
/* check for RTC Parameters used to output RTCCLK */
assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
/* Enable Power Clock*/
__HAL_RCC_PWR_CLK_ENABLE();
/* Enable write access to Backup domain */
SET_BIT(PWR->CR, PWR_CR_DBP);
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
while((PWR->CR & PWR_CR_DBP) == RESET)
FlagStatus pwrclkchanged = RESET;
/* As soon as function is called to change RTC clock source, activation of the
power domain is done. */
/* Requires to enable write access to Backup Domain of necessary */
if(__HAL_RCC_PWR_IS_CLK_DISABLED())
{
if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
__HAL_RCC_PWR_CLK_ENABLE();
pwrclkchanged = SET;
}
if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
{
/* Enable write access to Backup domain */
SET_BIT(PWR->CR, PWR_CR_DBP);
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
{
return HAL_TIMEOUT;
if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
}
/* Reset the Backup domain only if the RTC Clock source selection is modified */
if((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))
/* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
temp_reg = (RCC->BDCR & RCC_BDCR_RTCSEL);
if((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
{
/* Store the content of BDCR register before the reset of Backup Domain */
temp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
@ -209,7 +174,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
RCC->BDCR = temp_reg;
/* Wait for LSERDY if LSE was enabled */
if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSERDY))
if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSEON))
{
/* Get Start Tick */
tickstart = HAL_GetTick();
@ -223,10 +188,16 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
}
}
}
__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
}
__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
/* Require to disable power clock if necessary */
if(pwrclkchanged == SET)
{
__HAL_RCC_PWR_CLK_DISABLE();
}
}
/*------------------------------- USART1 Configuration ------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
{
@ -661,14 +632,85 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
return(frequency);
}
#if defined(CRS)
/**
* @brief Start automatic synchronization using polling mode
* @}
*/
#if defined(CRS)
/** @defgroup RCCEx_Exported_Functions_Group3 Extended Clock Recovery System Control functions
* @brief Extended Clock Recovery System Control functions
*
@verbatim
===============================================================================
##### Extended Clock Recovery System Control functions #####
===============================================================================
[..]
For devices with Clock Recovery System feature (CRS), RCC Extention HAL driver can be used as follows:
(#) In System clock config, HSI48 needs to be enabled
(#) Enable CRS clock in IP MSP init which will use CRS functions
(#) Call CRS functions as follows:
(##) Prepare synchronization configuration necessary for HSI48 calibration
(+++) Default values can be set for frequency Error Measurement (reload and error limit)
and also HSI48 oscillator smooth trimming.
(+++) Macro @ref __HAL_RCC_CRS_RELOADVALUE_CALCULATE can be also used to calculate
directly reload value with target and synchronization frequencies values
(##) Call function @ref HAL_RCCEx_CRSConfig which
(+++) Reset CRS registers to their default values.
(+++) Configure CRS registers with synchronization configuration
(+++) Enable automatic calibration and frequency error counter feature
Note: When using USB LPM (Link Power Management) and the device is in Sleep mode, the
periodic USB SOF will not be generated by the host. No SYNC signal will therefore be
provided to the CRS to calibrate the HSI48 on the run. To guarantee the required clock
precision after waking up from Sleep mode, the LSE or reference clock on the GPIOs
should be used as SYNC signal.
(##) A polling function is provided to wait for complete synchronization
(+++) Call function @ref HAL_RCCEx_CRSWaitSynchronization()
(+++) According to CRS status, user can decide to adjust again the calibration or continue
application if synchronization is OK
(#) User can retrieve information related to synchronization in calling function
@ref HAL_RCCEx_CRSGetSynchronizationInfo()
(#) Regarding synchronization status and synchronization information, user can try a new calibration
in changing synchronization configuration and call again HAL_RCCEx_CRSConfig.
Note: When the SYNC event is detected during the downcounting phase (before reaching the zero value),
it means that the actual frequency is lower than the target (and so, that the TRIM value should be
incremented), while when it is detected during the upcounting phase it means that the actual frequency
is higher (and that the TRIM value should be decremented).
(#) In interrupt mode, user can resort to the available macros (__HAL_RCC_CRS_XXX_IT). Interrupts will go
through CRS Handler (RCC_IRQn/RCC_IRQHandler)
(++) Call function @ref HAL_RCCEx_CRSConfig()
(++) Enable RCC_IRQn (thanks to NVIC functions)
(++) Enable CRS interrupt (@ref __HAL_RCC_CRS_ENABLE_IT)
(++) Implement CRS status management in the following user callbacks called from
HAL_RCCEx_CRS_IRQHandler():
(+++) @ref HAL_RCCEx_CRS_SyncOkCallback()
(+++) @ref HAL_RCCEx_CRS_SyncWarnCallback()
(+++) @ref HAL_RCCEx_CRS_ExpectedSyncCallback()
(+++) @ref HAL_RCCEx_CRS_ErrorCallback()
(#) To force a SYNC EVENT, user can use the function @ref HAL_RCCEx_CRSSoftwareSynchronizationGenerate().
This function can be called before calling @ref HAL_RCCEx_CRSConfig (for instance in Systick handler)
@endverbatim
* @{
*/
/**
* @brief Start automatic synchronization for polling mode
* @param pInit Pointer on RCC_CRSInitTypeDef structure
* @retval None
*/
void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit)
{
uint32_t value = 0;
/* Check the parameters */
assert_param(IS_RCC_CRS_SYNC_DIV(pInit->Prescaler));
assert_param(IS_RCC_CRS_SYNC_SOURCE(pInit->Source));
@ -677,52 +719,30 @@ void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit)
assert_param(IS_RCC_CRS_ERRORLIMIT(pInit->ErrorLimitValue));
assert_param(IS_RCC_CRS_HSI48CALIBRATION(pInit->HSI48CalibrationValue));
/* CONFIGURATION */
/* Before configuration, reset CRS registers to their default values*/
__HAL_RCC_CRS_FORCE_RESET();
__HAL_RCC_CRS_RELEASE_RESET();
/* Configure Synchronization input */
/* Clear SYNCDIV[2:0], SYNCSRC[1:0] & SYNCSPOL bits */
CRS->CFGR &= ~(CRS_CFGR_SYNCDIV | CRS_CFGR_SYNCSRC | CRS_CFGR_SYNCPOL);
/* Set the CRS_CFGR_SYNCDIV[2:0] bits according to Prescaler value */
CRS->CFGR |= pInit->Prescaler;
/* Set the SYNCDIV[2:0] bits according to Prescaler value */
/* Set the SYNCSRC[1:0] bits according to Source value */
CRS->CFGR |= pInit->Source;
/* Set the SYNCSPOL bits according to Polarity value */
CRS->CFGR |= pInit->Polarity;
/* Configure Frequency Error Measurement */
/* Clear RELOAD[15:0] & FELIM[7:0] bits*/
CRS->CFGR &= ~(CRS_CFGR_RELOAD | CRS_CFGR_FELIM);
/* Set the SYNCSPOL bit according to Polarity value */
value = (pInit->Prescaler | pInit->Source | pInit->Polarity);
/* Set the RELOAD[15:0] bits according to ReloadValue value */
CRS->CFGR |= pInit->ReloadValue;
value |= pInit->ReloadValue;
/* Set the FELIM[7:0] bits according to ErrorLimitValue value */
CRS->CFGR |= (pInit->ErrorLimitValue << CRS_CFGR_FELIM_BITNUMBER);
value |= (pInit->ErrorLimitValue << CRS_CFGR_FELIM_BITNUMBER);
WRITE_REG(CRS->CFGR, value);
/* Adjust HSI48 oscillator smooth trimming */
/* Clear TRIM[5:0] bits */
CRS->CR &= ~CRS_CR_TRIM;
/* Set the TRIM[5:0] bits according to RCC_CRS_HSI48CalibrationValue value */
CRS->CR |= (pInit->HSI48CalibrationValue << CRS_CR_TRIM_BITNUMBER);
MODIFY_REG(CRS->CR, CRS_CR_TRIM, (pInit->HSI48CalibrationValue << CRS_CR_TRIM_BITNUMBER));
/* START AUTOMATIC SYNCHRONIZATION*/
/* Enable Automatic trimming */
__HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE();
/* Enable Frequency error counter */
__HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE();
/* Enable Automatic trimming & Frequency error counter */
SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN | CRS_CR_CEN);
}
/**
@ -731,12 +751,11 @@ void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit)
*/
void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void)
{
CRS->CR |= CRS_CR_SWSYNC;
SET_BIT(CRS->CR, CRS_CR_SWSYNC);
}
/**
* @brief Function to return synchronization info
* @brief Return synchronization info
* @param pSynchroInfo Pointer on RCC_CRSSynchroInfoTypeDef structure
* @retval None
*/
@ -746,23 +765,21 @@ void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo
assert_param(pSynchroInfo != NULL);
/* Get the reload value */
pSynchroInfo->ReloadValue = (uint32_t)(CRS->CFGR & CRS_CFGR_RELOAD);
pSynchroInfo->ReloadValue = (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD));
/* Get HSI48 oscillator smooth trimming */
pSynchroInfo->HSI48CalibrationValue = (uint32_t)((CRS->CR & CRS_CR_TRIM) >> CRS_CR_TRIM_BITNUMBER);
pSynchroInfo->HSI48CalibrationValue = (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_BITNUMBER);
/* Get Frequency error capture */
pSynchroInfo->FreqErrorCapture = (uint32_t)((CRS->ISR & CRS_ISR_FECAP) >> CRS_ISR_FECAP_BITNUMBER);
pSynchroInfo->FreqErrorCapture = (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_ISR_FECAP_BITNUMBER);
/* Get FFrequency error direction */
pSynchroInfo->FreqErrorDirection = (uint32_t)(CRS->ISR & CRS_ISR_FEDIR);
/* Get Frequency error direction */
pSynchroInfo->FreqErrorDirection = (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FEDIR));
}
/**
* @brief This function handles CRS Synchronization Timeout.
* @param Timeout Duration of the timeout
* @brief Wait for CRS Synchronization status.
* @param Timeout Duration of the timeout
* @note Timeout is based on the maximum time to receive a SYNC event based on synchronization
* frequency.
* @note If Timeout set to HAL_MAX_DELAY, HAL_TIMEOUT will be never returned.
@ -770,25 +787,25 @@ void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo
* This parameter can be a combination of the following values:
* @arg @ref RCC_CRS_TIMEOUT
* @arg @ref RCC_CRS_SYNCOK
* @arg @ref RCC_CRS_SYNCWARM
* @arg @ref RCC_CRS_SYNCWARN
* @arg @ref RCC_CRS_SYNCERR
* @arg @ref RCC_CRS_SYNCMISS
* @arg @ref RCC_CRS_TRIMOV
* @arg @ref RCC_CRS_TRIMOVF
*/
uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout)
{
uint32_t crsstatus = RCC_CRS_NONE;
uint32_t tickstart = 0;
uint32_t tickstart = 0U;
/* Get timeout */
tickstart = HAL_GetTick();
/* Check that if one of CRS flags have been set */
while(RCC_CRS_NONE == crsstatus)
/* Wait for CRS flag or timeout detection */
do
{
if(Timeout != HAL_MAX_DELAY)
{
if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
{
crsstatus = RCC_CRS_TIMEOUT;
}
@ -807,7 +824,7 @@ uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout)
if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCWARN))
{
/* CRS SYNC warning */
crsstatus |= RCC_CRS_SYNCWARM;
crsstatus |= RCC_CRS_SYNCWARN;
/* Clear CRS SYNCWARN bit */
__HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCWARN);
@ -817,7 +834,7 @@ uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout)
if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_TRIMOVF))
{
/* CRS SYNC Error */
crsstatus |= RCC_CRS_TRIMOV;
crsstatus |= RCC_CRS_TRIMOVF;
/* Clear CRS Error bit */
__HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_TRIMOVF);
@ -849,11 +866,132 @@ uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout)
/* frequency error counter reached a zero value */
__HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_ESYNC);
}
}
} while(RCC_CRS_NONE == crsstatus);
return crsstatus;
}
/**
* @brief Handle the Clock Recovery System interrupt request.
* @retval None
*/
void HAL_RCCEx_CRS_IRQHandler(void)
{
uint32_t crserror = RCC_CRS_NONE;
/* Get current IT flags and IT sources values */
uint32_t itflags = READ_REG(CRS->ISR);
uint32_t itsources = READ_REG(CRS->CR);
/* Check CRS SYNCOK flag */
if(((itflags & RCC_CRS_FLAG_SYNCOK) != RESET) && ((itsources & RCC_CRS_IT_SYNCOK) != RESET))
{
/* Clear CRS SYNC event OK flag */
WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC);
/* user callback */
HAL_RCCEx_CRS_SyncOkCallback();
}
/* Check CRS SYNCWARN flag */
else if(((itflags & RCC_CRS_FLAG_SYNCWARN) != RESET) && ((itsources & RCC_CRS_IT_SYNCWARN) != RESET))
{
/* Clear CRS SYNCWARN flag */
WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC);
/* user callback */
HAL_RCCEx_CRS_SyncWarnCallback();
}
/* Check CRS Expected SYNC flag */
else if(((itflags & RCC_CRS_FLAG_ESYNC) != RESET) && ((itsources & RCC_CRS_IT_ESYNC) != RESET))
{
/* frequency error counter reached a zero value */
WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC);
/* user callback */
HAL_RCCEx_CRS_ExpectedSyncCallback();
}
/* Check CRS Error flags */
else
{
if(((itflags & RCC_CRS_FLAG_ERR) != RESET) && ((itsources & RCC_CRS_IT_ERR) != RESET))
{
if((itflags & RCC_CRS_FLAG_SYNCERR) != RESET)
{
crserror |= RCC_CRS_SYNCERR;
}
if((itflags & RCC_CRS_FLAG_SYNCMISS) != RESET)
{
crserror |= RCC_CRS_SYNCMISS;
}
if((itflags & RCC_CRS_FLAG_TRIMOVF) != RESET)
{
crserror |= RCC_CRS_TRIMOVF;
}
/* Clear CRS Error flags */
WRITE_REG(CRS->ICR, CRS_ICR_ERRC);
/* user error callback */
HAL_RCCEx_CRS_ErrorCallback(crserror);
}
}
}
/**
* @brief RCCEx Clock Recovery System SYNCOK interrupt callback.
* @retval none
*/
__weak void HAL_RCCEx_CRS_SyncOkCallback(void)
{
/* NOTE : This function should not be modified, when the callback is needed,
the @ref HAL_RCCEx_CRS_SyncOkCallback should be implemented in the user file
*/
}
/**
* @brief RCCEx Clock Recovery System SYNCWARN interrupt callback.
* @retval none
*/
__weak void HAL_RCCEx_CRS_SyncWarnCallback(void)
{
/* NOTE : This function should not be modified, when the callback is needed,
the @ref HAL_RCCEx_CRS_SyncWarnCallback should be implemented in the user file
*/
}
/**
* @brief RCCEx Clock Recovery System Expected SYNC interrupt callback.
* @retval none
*/
__weak void HAL_RCCEx_CRS_ExpectedSyncCallback(void)
{
/* NOTE : This function should not be modified, when the callback is needed,
the @ref HAL_RCCEx_CRS_ExpectedSyncCallback should be implemented in the user file
*/
}
/**
* @brief RCCEx Clock Recovery System Error interrupt callback.
* @param Error Combination of Error status.
* This parameter can be a combination of the following values:
* @arg @ref RCC_CRS_SYNCERR
* @arg @ref RCC_CRS_SYNCMISS
* @arg @ref RCC_CRS_TRIMOVF
* @retval none
*/
__weak void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(Error);
/* NOTE : This function should not be modified, when the callback is needed,
the @ref HAL_RCCEx_CRS_ErrorCallback should be implemented in the user file
*/
}
/**
* @}
*/
#endif /* CRS */
/**

428
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rcc_ex.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_rcc_ex.h
* @author MCD Application Team
* @version V1.3.1
* @date 29-January-2016
* @version V1.4.0
* @date 27-May-2016
* @brief Header file of RCC HAL Extension module.
******************************************************************************
* @attention
@ -57,9 +57,7 @@
/** @addtogroup RCC_Private_Macros
* @{
*/
#if defined(STM32F042x6) || defined(STM32F048xx)\
|| defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
|| defined(STM32F091xC) || defined(STM32F098xx)
#if defined(RCC_HSI48_SUPPORT)
#define IS_RCC_OSCILLATORTYPE(OSCILLATOR) (((OSCILLATOR) == RCC_OSCILLATORTYPE_NONE) || \
(((OSCILLATOR) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \
(((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \
@ -67,6 +65,7 @@
(((OSCILLATOR) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) || \
(((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI14) == RCC_OSCILLATORTYPE_HSI14) || \
(((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48))
#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \
((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \
((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK) || \
@ -76,11 +75,15 @@
((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSE) || \
((SOURCE) == RCC_SYSCLKSOURCE_STATUS_PLLCLK) || \
((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI48))
#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \
((SOURCE) == RCC_PLLSOURCE_HSI48) || \
((SOURCE) == RCC_PLLSOURCE_HSE))
#define IS_RCC_HSI48(HSI48) (((HSI48) == RCC_HSI48_OFF) || ((HSI48) == RCC_HSI48_ON))
#else
#define IS_RCC_OSCILLATORTYPE(OSCILLATOR) (((OSCILLATOR) == RCC_OSCILLATORTYPE_NONE) || \
(((OSCILLATOR) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \
(((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \
@ -97,12 +100,9 @@
#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \
((SOURCE) == RCC_PLLSOURCE_HSE))
#endif /* STM32F042x6 || STM32F048xx || */
/* STM32F071xB || STM32F072xB || STM32F078xx || */
/* STM32F091xC || STM32F098xx */
#endif /* RCC_HSI48_SUPPORT */
#if defined(STM32F031x6) || defined(STM32F038xx) || defined(STM32F070x6) || defined(STM32F070xB) \
|| defined(STM32F030xC)
#if defined(RCC_CFGR_PLLNODIV) && !defined(RCC_CFGR_MCO_HSI48)
#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_NOCLOCK) || \
((SOURCE) == RCC_MCO1SOURCE_LSI) || \
@ -114,24 +114,7 @@
((SOURCE) == RCC_MCO1SOURCE_PLLCLK_DIV2) || \
((SOURCE) == RCC_MCO1SOURCE_HSI14))
#endif /* STM32F030x6 || STM32F031x6 || STM32F038xx || STM32F070x6 || STM32F070xB || STM32F030xC */
#if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F051x8) || defined(STM32F058xx)
#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_NOCLOCK) || \
((SOURCE) == RCC_MCO1SOURCE_LSI) || \
((SOURCE) == RCC_MCO1SOURCE_LSE) || \
((SOURCE) == RCC_MCO1SOURCE_SYSCLK) || \
((SOURCE) == RCC_MCO1SOURCE_HSI) || \
((SOURCE) == RCC_MCO1SOURCE_HSE) || \
((SOURCE) == RCC_MCO1SOURCE_PLLCLK_DIV2) || \
((SOURCE) == RCC_MCO1SOURCE_HSI14))
#endif /* STM32F030x8 || STM32F051x8 || STM32F058xx */
#if defined(STM32F042x6) || defined(STM32F048xx)\
|| defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
|| defined(STM32F091xC) || defined(STM32F098xx)
#elif defined(RCC_CFGR_PLLNODIV) && defined(RCC_CFGR_MCO_HSI48)
#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_NOCLOCK) || \
((SOURCE) == RCC_MCO1SOURCE_LSI) || \
@ -144,9 +127,18 @@
((SOURCE) == RCC_MCO1SOURCE_HSI14) || \
((SOURCE) == RCC_MCO1SOURCE_HSI48))
#endif /* STM32F042x6 || STM32F048xx || */
/* STM32F071xB || STM32F072xB || STM32F078xx || */
/* STM32F091xC || STM32F098xx */
#elif !defined(RCC_CFGR_PLLNODIV) && !defined(RCC_CFGR_MCO_HSI48)
#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_NOCLOCK) || \
((SOURCE) == RCC_MCO1SOURCE_LSI) || \
((SOURCE) == RCC_MCO1SOURCE_LSE) || \
((SOURCE) == RCC_MCO1SOURCE_SYSCLK) || \
((SOURCE) == RCC_MCO1SOURCE_HSI) || \
((SOURCE) == RCC_MCO1SOURCE_HSE) || \
((SOURCE) == RCC_MCO1SOURCE_PLLCLK_DIV2) || \
((SOURCE) == RCC_MCO1SOURCE_HSI14))
#endif /* RCC_CFGR_PLLNODIV && !RCC_CFGR_MCO_HSI48 */
/**
* @}
@ -155,9 +147,7 @@
/** @addtogroup RCC_Exported_Constants
* @{
*/
#if defined(STM32F042x6) || defined(STM32F048xx)\
|| defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
|| defined(STM32F091xC) || defined(STM32F098xx)
#if defined(RCC_HSI48_SUPPORT)
/** @addtogroup RCC_PLL_Clock_Source
* @{
@ -169,14 +159,6 @@
* @}
*/
/** @addtogroup RCC_Oscillator_Type
* @{
*/
#define RCC_OSCILLATORTYPE_HSI48 ((uint32_t)0x00000020)
/**
* @}
*/
/** @addtogroup RCC_Interrupt
* @{
*/
@ -224,31 +206,23 @@
* @}
*/
#endif /* STM32F042x6 || STM32F048xx || */
/* STM32F071xB || STM32F072xB || STM32F078xx || */
/* STM32F091xC || STM32F098xx */
#endif /* RCC_HSI48_SUPPORT */
/** @addtogroup RCC_MCO_Clock_Source
* @{
*/
#if defined(STM32F031x6) || defined(STM32F038xx) || defined(STM32F070x6) || defined(STM32F070xB) \
|| defined(STM32F030xC)
#if defined(RCC_CFGR_PLLNODIV)
#define RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCO_PLL | RCC_CFGR_PLLNODIV)
#endif /* STM32F030x6 || STM32F031x6 || STM32F038xx || STM32F070x6 || STM32F070xB || STM32F030xC */
#endif /* RCC_CFGR_PLLNODIV */
#if defined(STM32F042x6) || defined(STM32F048xx)\
|| defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
|| defined(STM32F091xC) || defined(STM32F098xx)
#if defined(RCC_CFGR_MCO_HSI48)
#define RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCO_HSI48
#define RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCO_PLL | RCC_CFGR_PLLNODIV)
#endif /* STM32F042x6 || STM32F048xx || */
/* STM32F071xB || STM32F072xB || STM32F078xx || */
/* STM32F091xC || STM32F098xx */
#endif /* SRCC_CFGR_MCO_HSI48 */
/**
* @}
*/
@ -609,7 +583,7 @@ typedef struct
This parameter can be a value of @ref RCCEx_CRS_SynchroPolarity */
uint32_t ReloadValue; /*!< Specifies the value to be loaded in the frequency error counter with each SYNC event.
It can be calculated in using macro @ref __HAL_RCC_CRS_RELOADVALUE_CALCULATE(_FTARGET_, _FSYNC_)
It can be calculated in using macro @ref __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__)
This parameter must be a number between 0 and 0xFFFF or a value of @ref RCCEx_CRS_ReloadValueDefault .*/
uint32_t ErrorLimitValue; /*!< Specifies the value to be used to evaluate the captured frequency error value.
@ -617,7 +591,7 @@ typedef struct
uint32_t HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value to the HSI48 oscillator.
This parameter must be a number between 0 and 0x3F or a value of @ref RCCEx_CRS_HSI48CalibrationDefault */
}RCC_CRSInitTypeDef;
/**
@ -626,15 +600,15 @@ typedef struct
typedef struct
{
uint32_t ReloadValue; /*!< Specifies the value loaded in the Counter reload value.
This parameter must be a number between 0 and 0xFFFF*/
This parameter must be a number between 0 and 0xFFFF */
uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48 oscillator smooth trimming.
This parameter must be a number between 0 and 0x3F */
uint32_t FreqErrorCapture; /*!< Specifies the value loaded in the .FECAP, the frequency error counter
value latched in the time of the last SYNC event.
This parameter must be a number between 0 and 0xFFFF */
uint32_t FreqErrorDirection; /*!< Specifies the value loaded in the .FEDIR, the counting direction of the
frequency error counter latched in the time of the last SYNC event.
It shows whether the actual frequency is below or above the target.
@ -654,48 +628,6 @@ typedef struct
* @{
*/
#if defined(STM32F042x6) || defined(STM32F048xx)\
|| defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
|| defined(STM32F091xC) || defined(STM32F098xx)
/** @defgroup RCCEx_HSI48_Config RCCEx HSI48 Config
* @{
*/
#define RCC_HSI48_OFF ((uint8_t)0x00)
#define RCC_HSI48_ON ((uint8_t)0x01)
/**
* @}
*/
/** @defgroup RCCEx_CRS_Status RCCEx CRS Status
* @{
*/
#define RCC_CRS_NONE ((uint32_t)0x00000000)
#define RCC_CRS_TIMEOUT ((uint32_t)0x00000001)
#define RCC_CRS_SYNCOK ((uint32_t)0x00000002)
#define RCC_CRS_SYNCWARM ((uint32_t)0x00000004)
#define RCC_CRS_SYNCERR ((uint32_t)0x00000008)
#define RCC_CRS_SYNCMISS ((uint32_t)0x00000010)
#define RCC_CRS_TRIMOV ((uint32_t)0x00000020)
/**
* @}
*/
#else
/** @defgroup RCCEx_HSI48_Config RCCEx HSI48 Config
* @{
*/
#define RCC_HSI48_OFF ((uint8_t)0x00)
/**
* @}
*/
#endif /* STM32F042x6 || STM32F048xx */
/* STM32F071xB || STM32F072xB || STM32F078xx || */
/* STM32F091xC || STM32F098xx */
/** @defgroup RCCEx_Periph_Clock_Selection RCCEx Periph Clock Selection
* @{
*/
@ -889,21 +821,35 @@ typedef struct
#if defined(CRS)
/** @defgroup RCCEx_CRS_SynchroSource RCCEx CRS SynchroSource
/** @defgroup RCCEx_CRS_Status RCCEx CRS Status
* @{
*/
#define RCC_CRS_SYNC_SOURCE_GPIO ((uint32_t)0x00) /*!< Synchro Signal soucre GPIO */
#define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */
#define RCC_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/
#define RCC_CRS_NONE ((uint32_t)0x00000000)
#define RCC_CRS_TIMEOUT ((uint32_t)0x00000001)
#define RCC_CRS_SYNCOK ((uint32_t)0x00000002)
#define RCC_CRS_SYNCWARN ((uint32_t)0x00000004)
#define RCC_CRS_SYNCERR ((uint32_t)0x00000008)
#define RCC_CRS_SYNCMISS ((uint32_t)0x00000010)
#define RCC_CRS_TRIMOVF ((uint32_t)0x00000020)
/**
* @}
*/
/** @defgroup RCCEx_CRS_SynchroDivider RCCEx CRS SynchroDivider
/** @defgroup RCCEx_CRS_SynchroSource RCCEx CRS Synchronization Source
* @{
*/
#define RCC_CRS_SYNC_DIV1 ((uint32_t)0x00) /*!< Synchro Signal not divided (default) */
#define RCC_CRS_SYNC_SOURCE_GPIO ((uint32_t)0x00000000U) /*!< Synchro Signal source GPIO */
#define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */
#define RCC_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/
/**
* @}
*/
/** @defgroup RCCEx_CRS_SynchroDivider RCCEx CRS Synchronization Divider
* @{
*/
#define RCC_CRS_SYNC_DIV1 ((uint32_t)0x00000000U) /*!< Synchro Signal not divided (default) */
#define RCC_CRS_SYNC_DIV2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */
#define RCC_CRS_SYNC_DIV4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */
#define RCC_CRS_SYNC_DIV8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */
@ -911,57 +857,51 @@ typedef struct
#define RCC_CRS_SYNC_DIV32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */
#define RCC_CRS_SYNC_DIV64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */
#define RCC_CRS_SYNC_DIV128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */
/**
* @}
*/
/** @defgroup RCCEx_CRS_SynchroPolarity RCCEx CRS SynchroPolarity
/** @defgroup RCCEx_CRS_SynchroPolarity RCCEx CRS Synchronization Polarity
* @{
*/
#define RCC_CRS_SYNC_POLARITY_RISING ((uint32_t)0x00) /*!< Synchro Active on rising edge (default) */
#define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */
/**
* @}
*/
/** @defgroup RCCEx_CRS_ReloadValueDefault RCCEx CRS ReloadValueDefault
* @{
*/
#define RCC_CRS_RELOADVALUE_DEFAULT ((uint32_t)0xBB7F) /*!< The reset value of the RELOAD field corresponds
to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */
/**
* @}
*/
/** @defgroup RCCEx_CRS_ErrorLimitDefault RCCEx CRS ErrorLimitDefault
* @{
*/
#define RCC_CRS_ERRORLIMIT_DEFAULT ((uint32_t)0x22) /*!< Default Frequency error limit */
#define RCC_CRS_SYNC_POLARITY_RISING ((uint32_t)0x00000000U) /*!< Synchro Active on rising edge (default) */
#define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */
/**
* @}
*/
/** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCCEx CRS HSI48CalibrationDefault
/** @defgroup RCCEx_CRS_ReloadValueDefault RCCEx CRS Default Reload Value
* @{
*/
#define RCC_CRS_HSI48CALIBRATION_DEFAULT ((uint32_t)0x20) /*!< The default value is 32, which corresponds to the middle of the trimming interval.
The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value
corresponds to a higher output frequency */
#define RCC_CRS_RELOADVALUE_DEFAULT ((uint32_t)0x0000BB7FU) /*!< The reset value of the RELOAD field corresponds
to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */
/**
* @}
*/
/** @defgroup RCCEx_CRS_ErrorLimitDefault RCCEx CRS Default Error Limit Value
* @{
*/
#define RCC_CRS_ERRORLIMIT_DEFAULT ((uint32_t)0x00000022U) /*!< Default Frequency error limit */
/**
* @}
*/
/** @defgroup RCCEx_CRS_FreqErrorDirection RCCEx CRS FreqErrorDirection
/** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCCEx CRS Default HSI48 Calibration vakye
* @{
*/
#define RCC_CRS_FREQERRORDIR_UP ((uint32_t)0x00) /*!< Upcounting direction, the actual frequency is above the target */
#define RCC_CRS_FREQERRORDIR_DOWN ((uint32_t)CRS_ISR_FEDIR) /*!< Downcounting direction, the actual frequency is below the target */
#define RCC_CRS_HSI48CALIBRATION_DEFAULT ((uint32_t)0x00000020U) /*!< The default value is 32, which corresponds to the middle of the trimming interval.
The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value
corresponds to a higher output frequency */
/**
* @}
*/
/** @defgroup RCCEx_CRS_FreqErrorDirection RCCEx CRS Frequency Error Direction
* @{
*/
#define RCC_CRS_FREQERRORDIR_UP ((uint32_t)0x00000000U) /*!< Upcounting direction, the actual frequency is above the target */
#define RCC_CRS_FREQERRORDIR_DOWN ((uint32_t)CRS_ISR_FEDIR) /*!< Downcounting direction, the actual frequency is below the target */
/**
* @}
*/
@ -969,13 +909,13 @@ typedef struct
/** @defgroup RCCEx_CRS_Interrupt_Sources RCCEx CRS Interrupt Sources
* @{
*/
#define RCC_CRS_IT_SYNCOK CRS_ISR_SYNCOKF /*!< SYNC event OK */
#define RCC_CRS_IT_SYNCWARN CRS_ISR_SYNCWARNF /*!< SYNC warning */
#define RCC_CRS_IT_ERR CRS_ISR_ERRF /*!< error */
#define RCC_CRS_IT_ESYNC CRS_ISR_ESYNCF /*!< Expected SYNC */
#define RCC_CRS_IT_TRIMOVF CRS_ISR_TRIMOVF /*!< Trimming overflow or underflow */
#define RCC_CRS_IT_SYNCERR CRS_ISR_SYNCERR /*!< SYNC error */
#define RCC_CRS_IT_SYNCMISS CRS_ISR_SYNCMISS /*!< SYNC missed*/
#define RCC_CRS_IT_SYNCOK CRS_CR_SYNCOKIE /*!< SYNC event OK */
#define RCC_CRS_IT_SYNCWARN CRS_CR_SYNCWARNIE /*!< SYNC warning */
#define RCC_CRS_IT_ERR CRS_CR_ERRIE /*!< Error */
#define RCC_CRS_IT_ESYNC CRS_CR_ESYNCIE /*!< Expected SYNC */
#define RCC_CRS_IT_SYNCERR CRS_CR_ERRIE /*!< SYNC error */
#define RCC_CRS_IT_SYNCMISS CRS_CR_ERRIE /*!< SYNC missed */
#define RCC_CRS_IT_TRIMOVF CRS_CR_ERRIE /*!< Trimming overflow or underflow */
/**
* @}
@ -984,13 +924,13 @@ typedef struct
/** @defgroup RCCEx_CRS_Flags RCCEx CRS Flags
* @{
*/
#define RCC_CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF /* SYNC event OK flag */
#define RCC_CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF /* SYNC warning flag */
#define RCC_CRS_FLAG_ERR CRS_ISR_ERRF /* Error flag */
#define RCC_CRS_FLAG_ESYNC CRS_ISR_ESYNCF /* Expected SYNC flag */
#define RCC_CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF /*!< Trimming overflow or underflow */
#define RCC_CRS_FLAG_SYNCERR CRS_ISR_SYNCERR /*!< SYNC error */
#define RCC_CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS /*!< SYNC missed*/
#define RCC_CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF /*!< SYNC event OK flag */
#define RCC_CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF /*!< SYNC warning flag */
#define RCC_CRS_FLAG_ERR CRS_ISR_ERRF /*!< Error flag */
#define RCC_CRS_FLAG_ESYNC CRS_ISR_ESYNCF /*!< Expected SYNC flag */
#define RCC_CRS_FLAG_SYNCERR CRS_ISR_SYNCERR /*!< SYNC error */
#define RCC_CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS /*!< SYNC missed*/
#define RCC_CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF /*!< Trimming overflow or underflow */
/**
* @}
@ -1790,9 +1730,7 @@ typedef struct
* clock cycles.
* @{
*/
#if defined(STM32F042x6) || defined(STM32F048xx)\
|| defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
|| defined(STM32F091xC) || defined(STM32F098xx)
#if defined(RCC_HSI48_SUPPORT)
#define __HAL_RCC_HSI48_ENABLE() SET_BIT(RCC->CR2, RCC_CR2_HSI48ON)
#define __HAL_RCC_HSI48_DISABLE() CLEAR_BIT(RCC->CR2, RCC_CR2_HSI48ON)
@ -1803,19 +1741,9 @@ typedef struct
* @arg @ref RCC_HSI48_OFF HSI48 disabled
*/
#define __HAL_RCC_GET_HSI48_STATE() \
(((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CR2_HSI48ON)) != RESET) ? RCC_HSI48_ON : RCC_HSI48_OFF)
(((uint32_t)(READ_BIT(RCC->CR2, RCC_CR2_HSI48ON)) != RESET) ? RCC_HSI48_ON : RCC_HSI48_OFF)
#else
/** @brief Macro to get the Internal 48Mhz High Speed oscillator (HSI48) state.
* @retval The clock source can be one of the following values:
* @arg @ref RCC_HSI_OFF HSI48 disabled
*/
#define __HAL_RCC_GET_HSI48_STATE() RCC_HSI_OFF
#endif /* STM32F042x6 || STM32F048xx || */
/* STM32F071xB || STM32F072xB || STM32F078xx || */
/* STM32F091xC || STM32F098xx */
#endif /* RCC_HSI48_SUPPORT */
/**
* @}
@ -1831,7 +1759,11 @@ typedef struct
/** @brief Macro to configure the USB clock (USBCLK).
* @param __USBCLKSOURCE__ specifies the USB clock source.
* This parameter can be one of the following values:
* @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 selected as USB clock (not available for STM32F070x6 & STM32F070xB)
@if STM32F070xB
@elseif STM32F070x6
@else
* @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 selected as USB clock
@endif
* @arg @ref RCC_USBCLKSOURCE_PLL PLL Clock selected as USB clock
*/
#define __HAL_RCC_USB_CONFIG(__USBCLKSOURCE__) \
@ -1839,7 +1771,11 @@ typedef struct
/** @brief Macro to get the USB clock source.
* @retval The clock source can be one of the following values:
@if STM32F070xB
@elseif STM32F070x6
@else
* @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 selected as USB clock
@endif
* @arg @ref RCC_USBCLKSOURCE_PLL PLL Clock selected as USB clock
*/
#define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USBSW)))
@ -1952,51 +1888,50 @@ typedef struct
/* Interrupt & Flag management */
/**
* @brief Enables the specified CRS interrupts.
* @brief Enable the specified CRS interrupts.
* @param __INTERRUPT__ specifies the CRS interrupt sources to be enabled.
* This parameter can be any combination of the following values:
* @arg @ref RCC_CRS_IT_SYNCOK
* @arg @ref RCC_CRS_IT_SYNCWARN
* @arg @ref RCC_CRS_IT_ERR
* @arg @ref RCC_CRS_IT_ESYNC
* @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt
* @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt
* @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt
* @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt
* @retval None
*/
#define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) (CRS->CR |= (__INTERRUPT__))
#define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) SET_BIT(CRS->CR, (__INTERRUPT__))
/**
* @brief Disables the specified CRS interrupts.
* @brief Disable the specified CRS interrupts.
* @param __INTERRUPT__ specifies the CRS interrupt sources to be disabled.
* This parameter can be any combination of the following values:
* @arg @ref RCC_CRS_IT_SYNCOK
* @arg @ref RCC_CRS_IT_SYNCWARN
* @arg @ref RCC_CRS_IT_ERR
* @arg @ref RCC_CRS_IT_ESYNC
* @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt
* @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt
* @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt
* @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt
* @retval None
*/
#define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) (CRS->CR &= ~(__INTERRUPT__))
#define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(CRS->CR, (__INTERRUPT__))
/** @brief Check the CRS's interrupt has occurred or not.
/** @brief Check whether the CRS interrupt has occurred or not.
* @param __INTERRUPT__ specifies the CRS interrupt source to check.
* This parameter can be one of the following values:
* @arg @ref RCC_CRS_IT_SYNCOK
* @arg @ref RCC_CRS_IT_SYNCWARN
* @arg @ref RCC_CRS_IT_ERR
* @arg @ref RCC_CRS_IT_ESYNC
* @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt
* @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt
* @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt
* @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt
* @retval The new state of __INTERRUPT__ (SET or RESET).
*/
#define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((CRS->CR & (__INTERRUPT__))? SET : RESET)
#define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((READ_BIT(CRS->CR, (__INTERRUPT__)) != RESET) ? SET : RESET)
/** @brief Clear the CRS's interrupt pending bits
* bits to clear the selected interrupt pending bits.
/** @brief Clear the CRS interrupt pending bits
* @param __INTERRUPT__ specifies the interrupt pending bit to clear.
* This parameter can be any combination of the following values:
* @arg @ref RCC_CRS_IT_SYNCOK
* @arg @ref RCC_CRS_IT_SYNCWARN
* @arg @ref RCC_CRS_IT_ERR
* @arg @ref RCC_CRS_IT_ESYNC
* @arg @ref RCC_CRS_IT_TRIMOVF
* @arg @ref RCC_CRS_IT_SYNCERR
* @arg @ref RCC_CRS_IT_SYNCMISS
* @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt
* @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt
* @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt
* @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt
* @arg @ref RCC_CRS_IT_TRIMOVF Trimming overflow or underflow interrupt
* @arg @ref RCC_CRS_IT_SYNCERR SYNC error interrupt
* @arg @ref RCC_CRS_IT_SYNCMISS SYNC missed interrupt
*/
#define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) do { \
if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != RESET) \
@ -2010,31 +1945,32 @@ typedef struct
} while(0)
/**
* @brief Checks whether the specified CRS flag is set or not.
* @brief Check whether the specified CRS flag is set or not.
* @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg @ref RCC_CRS_FLAG_SYNCOK
* @arg @ref RCC_CRS_FLAG_SYNCWARN
* @arg @ref RCC_CRS_FLAG_ERR
* @arg @ref RCC_CRS_FLAG_ESYNC
* @arg @ref RCC_CRS_FLAG_TRIMOVF
* @arg @ref RCC_CRS_FLAG_SYNCERR
* @arg @ref RCC_CRS_FLAG_SYNCMISS
* @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK
* @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning
* @arg @ref RCC_CRS_FLAG_ERR Error
* @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC
* @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow
* @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error
* @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed
* @retval The new state of _FLAG_ (TRUE or FALSE).
*/
#define __HAL_RCC_CRS_GET_FLAG(__FLAG__) ((CRS->ISR & (__FLAG__)) == (__FLAG__))
#define __HAL_RCC_CRS_GET_FLAG(__FLAG__) (READ_BIT(CRS->ISR, (__FLAG__)) == (__FLAG__))
/**
* @brief Clears the CRS specified FLAG.
* @brief Clear the CRS specified FLAG.
* @param __FLAG__ specifies the flag to clear.
* This parameter can be one of the following values:
* @arg @ref RCC_CRS_FLAG_SYNCOK
* @arg @ref RCC_CRS_FLAG_SYNCWARN
* @arg @ref RCC_CRS_FLAG_ERR
* @arg @ref RCC_CRS_FLAG_ESYNC
* @arg @ref RCC_CRS_FLAG_TRIMOVF
* @arg @ref RCC_CRS_FLAG_SYNCERR
* @arg @ref RCC_CRS_FLAG_SYNCMISS
* @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK
* @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning
* @arg @ref RCC_CRS_FLAG_ERR Error
* @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC
* @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow
* @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error
* @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed
* @note RCC_CRS_FLAG_ERR clears RCC_CRS_FLAG_TRIMOVF, RCC_CRS_FLAG_SYNCERR, RCC_CRS_FLAG_SYNCMISS and consequently RCC_CRS_FLAG_ERR
* @retval None
*/
#define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) do { \
@ -2056,30 +1992,30 @@ typedef struct
* @{
*/
/**
* @brief Enables the oscillator clock for frequency error counter.
* @brief Enable the oscillator clock for frequency error counter.
* @note when the CEN bit is set the CRS_CFGR register becomes write-protected.
* @retval None
*/
#define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE() (CRS->CR |= CRS_CR_CEN)
#define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE() SET_BIT(CRS->CR, CRS_CR_CEN)
/**
* @brief Disables the oscillator clock for frequency error counter.
* @brief Disable the oscillator clock for frequency error counter.
* @retval None
*/
#define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE() (CRS->CR &= ~CRS_CR_CEN)
#define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_CEN)
/**
* @brief Enables the automatic hardware adjustement of TRIM bits.
* @brief Enable the automatic hardware adjustement of TRIM bits.
* @note When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected.
* @retval None
*/
#define __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE() (CRS->CR |= CRS_CR_AUTOTRIMEN)
#define __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE() SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)
/**
* @brief Enables or disables the automatic hardware adjustement of TRIM bits.
* @brief Disable the automatic hardware adjustement of TRIM bits.
* @retval None
*/
#define __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE() (CRS->CR &= ~CRS_CR_AUTOTRIMEN)
#define __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)
/**
* @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies
@ -2087,28 +2023,28 @@ typedef struct
* of the synchronization source after prescaling. It is then decreased by one in order to
* reach the expected synchronization on the zero value. The formula is the following:
* RELOAD = (fTARGET / fSYNC) -1
* @param _FTARGET_ Target frequency (value in Hz)
* @param _FSYNC_ Synchronization signal frequency (value in Hz)
* @param __FTARGET__ Target frequency (value in Hz)
* @param __FSYNC__ Synchronization signal frequency (value in Hz)
* @retval None
*/
#define __HAL_RCC_CRS_RELOADVALUE_CALCULATE(_FTARGET_, _FSYNC_) (((_FTARGET_) / (_FSYNC_)) - 1)
#define __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U)
/**
* @}
*/
#endif /* CRS */
/**
* @}
*/
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup RCCEx_Exported_Functions
* @{
*/
/** @addtogroup RCCEx_Exported_Functions_Group1
/** @addtogroup RCCEx_Exported_Functions_Group1
* @{
*/
@ -2116,13 +2052,31 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *Perip
void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
#if defined(CRS)
void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit);
void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void);
void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo);
uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout);
#endif /* CRS */
/**
* @}
*/
#if defined(CRS)
/** @addtogroup RCCEx_Exported_Functions_Group3
* @{
*/
void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit);
void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void);
void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo);
uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout);
void HAL_RCCEx_CRS_IRQHandler(void);
void HAL_RCCEx_CRS_SyncOkCallback(void);
void HAL_RCCEx_CRS_SyncWarnCallback(void);
void HAL_RCCEx_CRS_ExpectedSyncCallback(void);
void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error);
/**
* @}
*/
#endif /* CRS */
/**
* @}

4
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rtc.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_rtc.c
* @author MCD Application Team
* @version V1.3.1
* @date 29-January-2016
* @version V1.4.0
* @date 27-May-2016
* @brief RTC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Real Time Clock (RTC) peripheral:

4
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rtc.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_rtc.h
* @author MCD Application Team
* @version V1.3.1
* @date 29-January-2016
* @version V1.4.0
* @date 27-May-2016
* @brief Header file of RTC HAL module.
******************************************************************************
* @attention

4
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rtc_ex.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_rtc_ex.c
* @author MCD Application Team
* @version V1.3.1
* @date 29-January-2016
* @version V1.4.0
* @date 27-May-2016
* @brief Extended RTC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Real Time Clock (RTC) Extended peripheral:

4
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rtc_ex.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_rtc_ex.h
* @author MCD Application Team
* @version V1.3.1
* @date 29-January-2016
* @version V1.4.0
* @date 27-May-2016
* @brief Header file of RTC HAL Extended module.
******************************************************************************
* @attention

288
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_smartcard.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_smartcard.c
* @author MCD Application Team
* @version V1.3.1
* @date 29-January-2016
* @version V1.4.0
* @date 27-May-2016
* @brief SMARTCARD HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the SMARTCARD peripheral:
@ -213,21 +213,7 @@ static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcar
[..]
(+) These parameters can be configured:
(++) Baud Rate
(++) Parity: parity should be enabled,
Frame Length is fixed to 8 bits plus parity:
the SMARTCARD frame format is given in the following table:
(+++) +---------------------------------------------------------------+
(+++) | M bit | PCE bit | SMARTCARD frame |
(+++) |---------------------|-----------------------------------------|
(+++) | 1 | 1 | | SB | 8 bit data | PB | STB | |
(+++) +---------------------------------------------------------------+
(+++) or
(+++) +---------------------------------------------------------------+
(+++) | M1M0 bits | PCE bit | SMARTCARD frame |
(+++) |-----------------------|---------------------------------------|
(+++) | 01 | 1 | | SB | 8 bit data | PB | STB | |
(+++) +---------------------------------------------------------------+
(++) Parity: should be enabled
(++) Receiver/transmitter modes
(++) Synchronous mode (and if enabled, phase, polarity and last bit parameters)
(++) Prescaler value
@ -252,10 +238,28 @@ static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcar
* @{
*/
/*
Additional Table:
Frame Length is fixed to 8 bits plus parity:
SMARTCARD frame format is given in the following table
+---------------------------------------------------------------+
| M bit | PCE bit | SMARTCARD frame |
|---------------------|-----------------------------------------|
| 1 | 1 | | SB | 8 bit data | PB | STB | |
+---------------------------------------------------------------+
or
+---------------------------------------------------------------+
| M1M0 bits | PCE bit | SMARTCARD frame |
|-----------------------|---------------------------------------|
| 01 | 1 | | SB | 8 bit data | PB | STB | |
+---------------------------------------------------------------+
*/
/**
* @brief Initialize the SMARTCARD mode according to the specified
* @brief Initialize the SMARTCARD mode according to the specified
* parameters in the SMARTCARD_HandleTypeDef and initialize the associated handle.
* @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
* @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
* the configuration information for the specified SMARTCARD module.
* @retval HAL status
*/
@ -270,7 +274,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsmartcard)
/* Check the USART associated to the SmartCard */
assert_param(IS_SMARTCARD_INSTANCE(hsmartcard->Instance));
if(hsmartcard->State == HAL_SMARTCARD_STATE_RESET)
if(hsmartcard->gState == HAL_SMARTCARD_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hsmartcard->Lock = HAL_UNLOCKED;
@ -279,7 +283,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsmartcard)
HAL_SMARTCARD_MspInit(hsmartcard);
}
hsmartcard->State = HAL_SMARTCARD_STATE_BUSY;
hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
/* Disable the Peripheral */
__HAL_SMARTCARD_DISABLE(hsmartcard);
@ -307,14 +311,14 @@ HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsmartcard)
/* Enable the Peripheral */
__HAL_SMARTCARD_ENABLE(hsmartcard);
/* TEACK and/or REACK to check before moving hsmartcard->State to Ready */
/* TEACK and/or REACK to check before moving hsmartcard->gState and hsmartcard->RxState to Ready */
return (SMARTCARD_CheckIdleState(hsmartcard));
}
/**
* @brief DeInitialize the SMARTCARD peripheral.
* @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
* @brief DeInitialize the SMARTCARD peripheral.
* @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
* the configuration information for the specified SMARTCARD module.
* @retval HAL status
*/
@ -329,7 +333,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsmartcard)
/* Check the parameters */
assert_param(IS_SMARTCARD_INSTANCE(hsmartcard->Instance));
hsmartcard->State = HAL_SMARTCARD_STATE_BUSY;
hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
/* Disable the Peripheral */
__HAL_SMARTCARD_DISABLE(hsmartcard);
@ -344,7 +348,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsmartcard)
HAL_SMARTCARD_MspDeInit(hsmartcard);
hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
hsmartcard->State = HAL_SMARTCARD_STATE_RESET;
hsmartcard->gState = HAL_SMARTCARD_STATE_RESET;
hsmartcard->RxState = HAL_SMARTCARD_STATE_RESET;
/* Process Unlock */
__HAL_UNLOCK(hsmartcard);
@ -389,7 +394,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsmartcard)
*/
/** @defgroup SMARTCARD_Exported_Functions_Group2 IO operation functions
* @brief SMARTCARD Transmit and Receive functions
* @brief SMARTCARD Transmit and Receive functions
*
@verbatim
==============================================================================
@ -453,7 +458,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsmartcard)
*/
HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
if ((hsmartcard->State == HAL_SMARTCARD_STATE_READY) || (hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_RX))
/* Check that a Tx process is not already ongoing */
if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
{
if((pData == NULL) || (Size == 0))
{
@ -463,15 +469,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, ui
/* Process Locked */
__HAL_LOCK(hsmartcard);
hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
/* Check if a non-blocking receive process is ongoing or not */
if(hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_RX)
{
hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_TX_RX;
}
else
{
hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_TX;
}
hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY_TX;
hsmartcard->TxXferSize = Size;
hsmartcard->TxXferCount = Size;
@ -488,15 +486,9 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, ui
{
return HAL_TIMEOUT;
}
/* Check if a non-blocking receive Process is ongoing or not */
if(hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX_RX)
{
hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_RX;
}
else
{
hsmartcard->State = HAL_SMARTCARD_STATE_READY;
}
/* At end of Tx process, restore hsmartcard->gState to Ready */
hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hsmartcard);
@ -520,7 +512,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, ui
*/
HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
if ((hsmartcard->State == HAL_SMARTCARD_STATE_READY) || (hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX))
/* Check that a Rx process is not already ongoing */
if(hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
{
if((pData == NULL) || (Size == 0))
{
@ -531,15 +524,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uin
__HAL_LOCK(hsmartcard);
hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
/* Check if a non-blocking transmit process is ongoing or not */
if(hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX)
{
hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_TX_RX;
}
else
{
hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_RX;
}
hsmartcard->RxState = HAL_SMARTCARD_STATE_BUSY_RX;
hsmartcard->RxXferSize = Size;
hsmartcard->RxXferCount = Size;
@ -554,15 +539,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uin
*pData++ = (uint8_t)(hsmartcard->Instance->RDR & (uint8_t)0x00FF);
}
/* Check if a non-blocking transmit Process is ongoing or not */
if(hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX_RX)
{
hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_TX;
}
else
{
hsmartcard->State = HAL_SMARTCARD_STATE_READY;
}
/* At end of Rx process, restore hsmartcard->RxState to Ready */
hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hsmartcard);
@ -585,7 +563,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uin
*/
HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
{
if ((hsmartcard->State == HAL_SMARTCARD_STATE_READY) || (hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_RX))
/* Check that a Tx process is not already ongoing */
if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
{
if((pData == NULL) || (Size == 0))
{
@ -600,15 +579,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard,
hsmartcard->TxXferCount = Size;
hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
/* Check if a receive process is ongoing or not */
if(hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_RX)
{
hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_TX_RX;
}
else
{
hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_TX;
}
hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY_TX;
/* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
__HAL_SMARTCARD_ENABLE_IT(hsmartcard, SMARTCARD_IT_ERR);
@ -637,7 +608,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard,
*/
HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
{
if ((hsmartcard->State == HAL_SMARTCARD_STATE_READY) || (hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX))
/* Check that a Rx process is not already ongoing */
if(hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
{
if((pData == NULL) || (Size == 0))
{
@ -652,15 +624,10 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard,
hsmartcard->RxXferCount = Size;
hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
/* Check if a transmit process is ongoing or not */
if(hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX)
{
hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_TX_RX;
}
else
{
hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_RX;
}
hsmartcard->RxState = HAL_SMARTCARD_STATE_BUSY_RX;
/* Process Unlocked */
__HAL_UNLOCK(hsmartcard);
/* Enable the SMARTCARD Parity Error Interrupt */
__HAL_SMARTCARD_ENABLE_IT(hsmartcard, SMARTCARD_IT_PE);
@ -668,9 +635,6 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard,
/* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
__HAL_SMARTCARD_ENABLE_IT(hsmartcard, SMARTCARD_IT_ERR);
/* Process Unlocked */
__HAL_UNLOCK(hsmartcard);
/* Enable the SMARTCARD Data Register not empty Interrupt */
__HAL_SMARTCARD_ENABLE_IT(hsmartcard, SMARTCARD_IT_RXNE);
@ -694,7 +658,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard
{
uint32_t *tmp;
if ((hsmartcard->State == HAL_SMARTCARD_STATE_READY) || (hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_RX))
/* Check that a Tx process is not already ongoing */
if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
{
if((pData == NULL) || (Size == 0))
{
@ -709,15 +674,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard
hsmartcard->TxXferCount = Size;
hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
/* Check if a receive process is ongoing or not */
if(hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_RX)
{
hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_TX_RX;
}
else
{
hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_TX;
}
hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY_TX;
/* Set the SMARTCARD DMA transfer complete callback */
hsmartcard->hdmatx->XferCpltCallback = SMARTCARD_DMATransmitCplt;
@ -761,7 +718,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsmartcard,
{
uint32_t *tmp;
if ((hsmartcard->State == HAL_SMARTCARD_STATE_READY) || (hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX))
/* Check that a Rx process is not already ongoing */
if(hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
{
if((pData == NULL) || (Size == 0))
{
@ -775,15 +733,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsmartcard,
hsmartcard->RxXferSize = Size;
hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
/* Check if a transmit process is ongoing or not */
if(hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX)
{
hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_TX_RX;
}
else
{
hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_RX;
}
hsmartcard->RxState = HAL_SMARTCARD_STATE_BUSY_RX;
/* Set the SMARTCARD DMA transfer complete callback */
hsmartcard->hdmarx->XferCpltCallback = SMARTCARD_DMAReceiveCplt;
@ -823,8 +773,9 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard)
{
__HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_PEF);
hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_PE;
/* Set the SMARTCARD state ready to be able to start again the process */
hsmartcard->State = HAL_SMARTCARD_STATE_READY;
/* Set the SMARTCARD states ready to be able to start again the process */
hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
}
/* SMARTCARD frame error interrupt occurred --------------------------------------*/
@ -832,8 +783,9 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard)
{
__HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_FEF);
hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_FE;
/* Set the SMARTCARD state ready to be able to start again the process */
hsmartcard->State = HAL_SMARTCARD_STATE_READY;
/* Set the SMARTCARD states ready to be able to start again the process */
hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
}
/* SMARTCARD noise error interrupt occurred --------------------------------------*/
@ -841,8 +793,9 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard)
{
__HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_NEF);
hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_NE;
/* Set the SMARTCARD state ready to be able to start again the process */
hsmartcard->State = HAL_SMARTCARD_STATE_READY;
/* Set the SMARTCARD states ready to be able to start again the process */
hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
}
/* SMARTCARD Over-Run interrupt occurred -----------------------------------------*/
@ -850,8 +803,9 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard)
{
__HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_OREF);
hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_ORE;
/* Set the SMARTCARD state ready to be able to start again the process */
hsmartcard->State = HAL_SMARTCARD_STATE_READY;
/* Set the SMARTCARD states ready to be able to start again the process */
hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
}
/* SMARTCARD receiver timeout interrupt occurred -----------------------------------------*/
@ -859,8 +813,9 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard)
{
__HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_RTOF);
hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_RTO;
/* Set the SMARTCARD state ready to be able to start again the process */
hsmartcard->State = HAL_SMARTCARD_STATE_READY;
/* Set the SMARTCARD states ready to be able to start again the process */
hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
}
/* Call SMARTCARD Error Call back function if need be --------------------------*/
@ -873,14 +828,12 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard)
if((__HAL_SMARTCARD_GET_IT(hsmartcard, SMARTCARD_IT_RXNE) != RESET) && (__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, SMARTCARD_IT_RXNE) != RESET))
{
SMARTCARD_Receive_IT(hsmartcard);
/* Clear RXNE interrupt flag */
__HAL_SMARTCARD_SEND_REQ(hsmartcard, SMARTCARD_RXDATA_FLUSH_REQUEST);
}
/* SMARTCARD in mode Receiver, end of block interruption ------------------------*/
if((__HAL_SMARTCARD_GET_IT(hsmartcard, SMARTCARD_IT_EOB) != RESET) && (__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, SMARTCARD_IT_EOB) != RESET))
{
hsmartcard->State = HAL_SMARTCARD_STATE_READY;
hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
__HAL_UNLOCK(hsmartcard);
HAL_SMARTCARD_RxCpltCallback(hsmartcard);
/* Clear EOBF interrupt after HAL_SMARTCARD_RxCpltCallback() call for the End of Block information
@ -889,13 +842,13 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard)
}
/* SMARTCARD in mode Transmitter ------------------------------------------------*/
if((__HAL_SMARTCARD_GET_IT(hsmartcard, SMARTCARD_IT_TXE) != RESET) &&(__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, SMARTCARD_IT_TXE) != RESET))
if((__HAL_SMARTCARD_GET_IT(hsmartcard, SMARTCARD_IT_TXE) != RESET) &&(__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, SMARTCARD_IT_TXE) != RESET))
{
SMARTCARD_Transmit_IT(hsmartcard);
}
/* SMARTCARD in mode Transmitter (transmission end) ------------------------*/
if((__HAL_SMARTCARD_GET_IT(hsmartcard, SMARTCARD_IT_TC) != RESET) &&(__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, SMARTCARD_IT_TC) != RESET))
if((__HAL_SMARTCARD_GET_IT(hsmartcard, SMARTCARD_IT_TC) != RESET) &&(__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, SMARTCARD_IT_TC) != RESET))
{
SMARTCARD_EndTransmit_IT(hsmartcard);
}
@ -975,20 +928,24 @@ __weak void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsmartcard)
/**
* @brief Return the SMARTCARD handle state.
* @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
* @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
* the configuration information for the specified SMARTCARD module.
* @retval SMARTCARD handle state
*/
HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsmartcard)
{
return hsmartcard->State;
uint32_t temp1= 0x00, temp2 = 0x00;
temp1 = hsmartcard->gState;
temp2 = hsmartcard->RxState;
return (HAL_SMARTCARD_StateTypeDef)(temp1 | temp2);
}
/**
* @brief Return the SMARTCARD handle error code.
* @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
* @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
* the configuration information for the specified SMARTCARD module.
* @retval SMARTCARD handle Error Code
* @retval SMARTCARD handle Error Code
*/
uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsmartcard)
{
@ -1017,9 +974,9 @@ uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsmartcard)
*/
static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard)
{
if ((hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX) || (hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX_RX))
/* Check that a Tx process is ongoing */
if (hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX)
{
if(hsmartcard->TxXferCount == 0)
{
/* Disable the SMARTCARD Transmit Data Register Empty Interrupt */
@ -1055,19 +1012,16 @@ static HAL_StatusTypeDef SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmar
/* Disable the SMARTCARD Transmit Complete Interrupt */
__HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_TC);
/* Check if a receive process is ongoing or not */
if(hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX_RX)
{
hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_RX;
}
else
/* Check if a receive process is ongoing or not. If not disable ERR IT */
if(hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
{
/* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
__HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_ERR);
hsmartcard->State = HAL_SMARTCARD_STATE_READY;
}
/* Tx process is ended, restore hsmartcard->gState to Ready */
hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
HAL_SMARTCARD_TxCpltCallback(hsmartcard);
return HAL_OK;
@ -1084,31 +1038,27 @@ static HAL_StatusTypeDef SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmar
*/
static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard)
{
if ((hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_RX) || (hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX_RX))
/* Check that a Rx process is ongoing */
if (hsmartcard->RxState == HAL_SMARTCARD_STATE_BUSY_RX)
{
*hsmartcard->pRxBuffPtr++ = (uint8_t)(hsmartcard->Instance->RDR & (uint8_t)0xFF);
if(--hsmartcard->RxXferCount == 0)
{
__HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_RXNE);
/* Check if a transmit Process is ongoing or not */
if(hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX_RX)
/* Check if a transmit process is ongoing or not. If not disable ERR IT */
if(hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
{
hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_TX;
}
else
{
/* Disable the SMARTCARD Parity Error Interrupt */
__HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_PE);
/* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
__HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_ERR);
hsmartcard->State = HAL_SMARTCARD_STATE_READY;
}
/* Disable the SMARTCARD Parity Error Interrupt */
__HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_PE);
hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
HAL_SMARTCARD_RxCpltCallback(hsmartcard);
return HAL_OK;
@ -1118,6 +1068,9 @@ static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcar
}
else
{
/* Clear RXNE interrupt flag */
__HAL_SMARTCARD_SEND_REQ(hsmartcard, SMARTCARD_RXDATA_FLUSH_REQUEST);
return HAL_BUSY;
}
}
@ -1151,7 +1104,8 @@ static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDe
__HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_PE);
__HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_ERR);
hsmartcard->State= HAL_SMARTCARD_STATE_READY;
hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hsmartcard);
@ -1176,7 +1130,8 @@ static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDe
__HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_PE);
__HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_ERR);
hsmartcard->State= HAL_SMARTCARD_STATE_READY;
hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hsmartcard);
@ -1223,15 +1178,8 @@ static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
in the SMARTCARD associated USART CR3 register */
hsmartcard->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_DMAR);
/* Check if a transmit Process is ongoing or not */
if(hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX_RX)
{
hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_TX;
}
else
{
hsmartcard->State = HAL_SMARTCARD_STATE_READY;
}
/* At end of Rx process, restore hsmartcard->RxState to Ready */
hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
HAL_SMARTCARD_RxCpltCallback(hsmartcard);
}
@ -1247,7 +1195,8 @@ static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma)
SMARTCARD_HandleTypeDef* hsmartcard = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
hsmartcard->RxXferCount = 0;
hsmartcard->TxXferCount = 0;
hsmartcard->State= HAL_SMARTCARD_STATE_READY;
hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_DMA;
HAL_SMARTCARD_ErrorCallback(hsmartcard);
}
@ -1335,16 +1284,16 @@ static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard
switch (clocksource)
{
case SMARTCARD_CLOCKSOURCE_PCLK1:
hsmartcard->Instance->BRR = (uint16_t)(HAL_RCC_GetPCLK1Freq() / hsmartcard->Init.BaudRate);
hsmartcard->Instance->BRR = (uint16_t)((HAL_RCC_GetPCLK1Freq() + (hsmartcard->Init.BaudRate/2)) / hsmartcard->Init.BaudRate);
break;
case SMARTCARD_CLOCKSOURCE_HSI:
hsmartcard->Instance->BRR = (uint16_t)(HSI_VALUE / hsmartcard->Init.BaudRate);
hsmartcard->Instance->BRR = (uint16_t)((HSI_VALUE + (hsmartcard->Init.BaudRate/2)) / hsmartcard->Init.BaudRate);
break;
case SMARTCARD_CLOCKSOURCE_SYSCLK:
hsmartcard->Instance->BRR = (uint16_t)(HAL_RCC_GetSysClockFreq() / hsmartcard->Init.BaudRate);
hsmartcard->Instance->BRR = (uint16_t)((HAL_RCC_GetSysClockFreq() + (hsmartcard->Init.BaudRate/2)) / hsmartcard->Init.BaudRate);
break;
case SMARTCARD_CLOCKSOURCE_LSE:
hsmartcard->Instance->BRR = (uint16_t)(LSE_VALUE / hsmartcard->Init.BaudRate);
hsmartcard->Instance->BRR = (uint16_t)((LSE_VALUE + (hsmartcard->Init.BaudRate/2)) / hsmartcard->Init.BaudRate);
break;
case SMARTCARD_CLOCKSOURCE_UNDEFINED:
default:
@ -1434,7 +1383,7 @@ static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsmar
Bits are defined for some specific devices, and are available only for UART instances supporting WakeUp from Stop Mode feature.
*/
#if !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC)
if (IS_UART_WAKEUP_INSTANCE(hsmartcard->Instance))
if (IS_UART_WAKEUP_FROMSTOP_INSTANCE(hsmartcard->Instance))
{
/* Check if the Transmitter is enabled */
if((hsmartcard->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
@ -1458,8 +1407,9 @@ static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsmar
}
#endif /* !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC) */
/* Initialize the SMARTCARD state*/
hsmartcard->State= HAL_SMARTCARD_STATE_READY;
/* Initialize the SMARTCARD states */
hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hsmartcard);

89
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_smartcard.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_smartcard.h
* @author MCD Application Team
* @version V1.3.1
* @date 29-January-2016
* @version V1.4.0
* @date 27-May-2016
* @brief Header file of SMARTCARD HAL module.
******************************************************************************
* @attention
@ -157,18 +157,63 @@ typedef struct
}SMARTCARD_AdvFeatureInitTypeDef;
/**
* @brief HAL State structures definition
* @brief HAL SMARTCARD State structures definition
* @note HAL SMARTCARD State value is a combination of 2 different substates: gState and RxState.
* - gState contains SMARTCARD state information related to global Handle management
* and also information related to Tx operations.
* gState value coding follow below described bitmap :
* b7-b6 Error information
* 00 : No Error
* 01 : (Not Used)
* 10 : Timeout
* 11 : Error
* b5 IP initilisation status
* 0 : Reset (IP not initialized)
* 1 : Init done (IP not initialized. HAL SMARTCARD Init function already called)
* b4-b3 (not used)
* xx : Should be set to 00
* b2 Intrinsic process state
* 0 : Ready
* 1 : Busy (IP busy with some configuration or internal operations)
* b1 (not used)
* x : Should be set to 0
* b0 Tx state
* 0 : Ready (no Tx operation ongoing)
* 1 : Busy (Tx operation ongoing)
* - RxState contains information related to Rx operations.
* RxState value coding follow below described bitmap :
* b7-b6 (not used)
* xx : Should be set to 00
* b5 IP initilisation status
* 0 : Reset (IP not initialized)
* 1 : Init done (IP not initialized)
* b4-b2 (not used)
* xxx : Should be set to 000
* b1 Rx state
* 0 : Ready (no Rx operation ongoing)
* 1 : Busy (Rx operation ongoing)
* b0 (not used)
* x : Should be set to 0.
*/
typedef enum
{
HAL_SMARTCARD_STATE_RESET = 0x00, /*!< Peripheral is not initialized */
HAL_SMARTCARD_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
HAL_SMARTCARD_STATE_BUSY = 0x02, /*!< an internal process is ongoing */
HAL_SMARTCARD_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */
HAL_SMARTCARD_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */
HAL_SMARTCARD_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */
HAL_SMARTCARD_STATE_TIMEOUT = 0x03, /*!< Timeout state */
HAL_SMARTCARD_STATE_ERROR = 0x04 /*!< Error */
HAL_SMARTCARD_STATE_RESET = 0x00U, /*!< Peripheral is not initialized
Value is allowed for gState and RxState */
HAL_SMARTCARD_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use
Value is allowed for gState and RxState */
HAL_SMARTCARD_STATE_BUSY = 0x24U, /*!< an internal process is ongoing
Value is allowed for gState only */
HAL_SMARTCARD_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing
Value is allowed for gState only */
HAL_SMARTCARD_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing
Value is allowed for RxState only */
HAL_SMARTCARD_STATE_BUSY_TX_RX = 0x23U, /*!< Data Transmission and Reception process is ongoing
Not to be used for neither gState nor RxState.
Value is result of combination (Or) between gState and RxState values */
HAL_SMARTCARD_STATE_TIMEOUT = 0xA0U, /*!< Timeout state
Value is allowed for gState only */
HAL_SMARTCARD_STATE_ERROR = 0xE0U /*!< Error
Value is allowed for gState only */
}HAL_SMARTCARD_StateTypeDef;
/**
@ -212,7 +257,12 @@ typedef struct
HAL_LockTypeDef Lock; /*!< Locking object */
__IO HAL_SMARTCARD_StateTypeDef State; /*!< SmartCard communication state */
__IO HAL_SMARTCARD_StateTypeDef gState; /*!< SmartCard state information related to global Handle management
and also related to Tx operations.
This parameter can be a value of @ref HAL_SMARTCARD_StateTypeDef */
__IO HAL_SMARTCARD_StateTypeDef RxState; /*!< SmartCard state information related to Rx operations.
This parameter can be a value of @ref HAL_SMARTCARD_StateTypeDef */
__IO uint32_t ErrorCode; /*!< SmartCard Error code
This parameter can be a value of @ref SMARTCARD_Error */
@ -254,10 +304,11 @@ typedef struct
* @}
*/
/** @defgroup SMARTCARD_Stop_Bits SMARTCARD Stop Bits
/** @defgroup SMARTCARD_Stop_Bits SMARTCARD Number of Stop Bits
* @{
*/
#define SMARTCARD_STOPBITS_1_5 USART_CR2_STOP /*!< SMARTCARD frame with 1.5 stop bits */
#define SMARTCARD_STOPBITS_0_5 ((uint32_t)USART_CR2_STOP_0) /*!< SMARTCARD frame with 0.5 stop bit */
#define SMARTCARD_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1)) /*!< SMARTCARD frame with 1.5 stop bits */
/**
* @}
*/
@ -529,11 +580,14 @@ typedef struct
* @{
*/
/** @brief Reset SMARTCARD handle state.
/** @brief Reset SMARTCARD handle states.
* @param __HANDLE__: SMARTCARD handle.
* @retval None
*/
#define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SMARTCARD_STATE_RESET)
#define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET; \
(__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET; \
} while(0)
/** @brief Flush the Smartcard Data registers.
* @param __HANDLE__: specifies the SMARTCARD Handle.
@ -801,7 +855,8 @@ typedef struct
* @param __STOPBITS__: SMARTCARD frame number of stop bits.
* @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)
*/
#define IS_SMARTCARD_STOPBITS(__STOPBITS__) ((__STOPBITS__) == SMARTCARD_STOPBITS_1_5)
#define IS_SMARTCARD_STOPBITS(__STOPBITS__) (((__STOPBITS__) == SMARTCARD_STOPBITS_0_5) ||\
((__STOPBITS__) == SMARTCARD_STOPBITS_1_5))
/**
* @brief Ensure that SMARTCARD frame parity is valid.

12
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_smartcard_ex.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_smartcard_ex.c
* @author MCD Application Team
* @version V1.3.1
* @date 29-January-2016
* @version V1.4.0
* @date 27-May-2016
* @brief SMARTCARD HAL module driver.
*
* This file provides extended firmware functions to manage the following
@ -139,12 +139,12 @@ HAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut(SMARTCARD_HandleTypeDef
/* Process Locked */
__HAL_LOCK(hsmartcard);
hsmartcard->State = HAL_SMARTCARD_STATE_BUSY;
hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
/* Set the USART RTOEN bit */
hsmartcard->Instance->CR2 |= USART_CR2_RTOEN;
hsmartcard->State = HAL_SMARTCARD_STATE_READY;
hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hsmartcard);
@ -164,12 +164,12 @@ HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef
/* Process Locked */
__HAL_LOCK(hsmartcard);
hsmartcard->State = HAL_SMARTCARD_STATE_BUSY;
hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
/* Clear the USART RTOEN bit */
hsmartcard->Instance->CR2 &= ~(USART_CR2_RTOEN);
hsmartcard->State = HAL_SMARTCARD_STATE_READY;
hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hsmartcard);

4
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_smartcard_ex.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_smartcard_ex.h
* @author MCD Application Team
* @version V1.3.1
* @date 29-January-2016
* @version V1.4.0
* @date 27-May-2016
* @brief Header file of SMARTCARD HAL Extended module.
******************************************************************************
* @attention

16
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_smbus.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_smbus.c
* @author MCD Application Team
* @version V1.3.1
* @date 29-January-2016
* @version V1.4.0
* @date 27-May-2016
* @brief SMBUS HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the System Management Bus (SMBus) peripheral,
@ -438,7 +438,8 @@ HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus)
* @brief Transmit in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.
* @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
* the configuration information for the specified SMBUS.
* @param DevAddress Target device address
* @param DevAddress Target device address: The device 7 bits address value
* in datasheet must be shift at right before call interface
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
* @param XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition
@ -526,7 +527,8 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint
* @brief Receive in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.
* @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
* the configuration information for the specified SMBUS.
* @param DevAddress Target device address
* @param DevAddress Target device address: The device 7 bits address value
* in datasheet must be shift at right before call interface
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
* @param XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition
@ -608,7 +610,8 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint1
* @note This abort can be called only if state is ready
* @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
* the configuration information for the specified SMBUS.
* @param DevAddress Target device address
* @param DevAddress Target device address: The device 7 bits address value
* in datasheet must be shift at right before call interface
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress)
@ -911,7 +914,8 @@ HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus)
* @brief Check if target device is ready for communication.
* @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
* the configuration information for the specified SMBUS.
* @param DevAddress Target device address
* @param DevAddress Target device address: The device 7 bits address value
* in datasheet must be shift at right before call interface
* @param Trials Number of trials
* @param Timeout Timeout duration
* @retval HAL status

4
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_smbus.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_smbus.h
* @author MCD Application Team
* @version V1.3.1
* @date 29-January-2016
* @version V1.4.0
* @date 27-May-2016
* @brief Header file of SMBUS HAL module.
******************************************************************************
* @attention

95
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_spi.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_spi.c
* @author MCD Application Team
* @version V1.3.1
* @date 29-January-2016
* @version V1.4.0
* @date 27-May-2016
* @brief SPI HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Serial Peripheral Interface (SPI) peripheral:
@ -52,37 +52,9 @@
(#) The CRC feature is not managed when the DMA circular mode is enabled
(#) When the SPI DMA Pause/Stop features are used, we must use the following APIs
the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks
[..]
Using the HAL it is not possible to reach all supported SPI frequency with the differents
the following table resume the max SPI frequency reached with data size 8bits/16bits,
according to frequency used on APBx Peripheral Clock (fPCLK) used by the SPI instance :
+-----------------------------------------------------------------------------------------
| | | 2Lines Fullduplex | 2Lines RxOnly | 1Line
| Process | Tranfert mode |---------------------|---------------------|------------------
| | | Master | Slave | Master | Slave | Master | Slave
|=========================================================================================
| T | Polling | fPCLK/32 | fPCLK/32 | NA | NA | NA | NA
| X |----------------|----------|----------|----------|----------|----------|-------
| / | Interrupt | fPCLK/32 | fPCLK/32 | NA | NA | NA | NA
| R |----------------|----------|----------|----------|----------|----------|-------
| X | DMA | fPCLK/32 | fPCLK/16 | NA | NA | NA | NA
|=========|================|==========|==========|==========|==========|==========|=======
| | Polling | fPCLK/32 | fPCLK/16 | fPCLK/16 | fPCLK/16 | fPCLK/16 | fPCLK/
| |----------------|----------|----------|----------|----------|----------|-------
| R | Interrupt | fPCLK/16 | fPCLK/16 | fPCLK/16 | fPCLK/16 | fPCLK/16 | fPCLK/
| X |----------------|----------|----------|----------|----------|----------|-------
| | DMA | fPCLK/4 | fPCLK/8 | fPCLK/4 | fPCLK/4 | fPCLK/8 | fPCLK/
|=========|================|==========|==========|==========|==========|==========|=======
| | Polling | fPCLK/16 | fPCLK/16 | NA | NA | fPCLK/16 | fPCLK/
| |----------------|----------|----------|----------|----------|----------|-------
| T | Interrupt | fPCLK/32 | fPCLK/16 | NA | NA | fPCLK/16 | fPCLK/
| X |----------------|----------|----------|----------|----------|----------|-------
| | DMA | fPCLK/2 | fPCLK/16 | NA | NA | fPCLK/8 | fPCLK/
+-----------------------------------------------------------------------------------------
@note The max SPI frequency depend on SPI data size (4bits, 5bits,..., 8bits,...15bits, 16
SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling
@note
(#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_S
(#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA()
(#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA()
(#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA()
@ -117,6 +89,39 @@
******************************************************************************
*/
/*
Additional Table:
Using the HAL it is not possible to reach all supported SPI frequency with the differents
the following table resume the max SPI frequency reached with data size 8bits/16bits,
according to frequency used on APBx Peripheral Clock (fPCLK) used by the SPI instance :
+-----------------------------------------------------------------------------------------
| | | 2Lines Fullduplex | 2Lines RxOnly | 1Line
| Process | Tranfert mode |---------------------|---------------------|------------------
| | | Master | Slave | Master | Slave | Master | Slave
|=========================================================================================
| T | Polling | fPCLK/32 | fPCLK/32 | NA | NA | NA | NA
| X |----------------|----------|----------|----------|----------|----------|-------
| / | Interrupt | fPCLK/32 | fPCLK/32 | NA | NA | NA | NA
| R |----------------|----------|----------|----------|----------|----------|-------
| X | DMA | fPCLK/32 | fPCLK/16 | NA | NA | NA | NA
|=========|================|==========|==========|==========|==========|==========|=======
| | Polling | fPCLK/32 | fPCLK/16 | fPCLK/16 | fPCLK/16 | fPCLK/16 | fPCLK/
| |----------------|----------|----------|----------|----------|----------|-------
| R | Interrupt | fPCLK/16 | fPCLK/16 | fPCLK/16 | fPCLK/16 | fPCLK/16 | fPCLK/
| X |----------------|----------|----------|----------|----------|----------|-------
| | DMA | fPCLK/4 | fPCLK/8 | fPCLK/4 | fPCLK/4 | fPCLK/8 | fPCLK/
|=========|================|==========|==========|==========|==========|==========|=======
| | Polling | fPCLK/16 | fPCLK/16 | NA | NA | fPCLK/16 | fPCLK/
| |----------------|----------|----------|----------|----------|----------|-------
| T | Interrupt | fPCLK/32 | fPCLK/16 | NA | NA | fPCLK/16 | fPCLK/
| X |----------------|----------|----------|----------|----------|----------|-------
| | DMA | fPCLK/2 | fPCLK/16 | NA | NA | fPCLK/8 | fPCLK/
+-----------------------------------------------------------------------------------------
@note The max SPI frequency depend on SPI data size (4bits, 5bits,..., 8bits,...15bits, 16
SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f0xx_hal.h"
@ -868,6 +873,11 @@ __IO uint16_t tmpreg;
/* Enable CRC Transmission */
if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
{
/* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */
if(((hspi->Instance->CR1 & SPI_CR1_MSTR) == 0) && ((hspi->Instance->CR2 & SPI_CR2_NSSP) == SPI_CR2_NSSP))
{
SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM);
}
hspi->Instance->CR1|= SPI_CR1_CRCNEXT;
}
}
@ -909,6 +919,11 @@ __IO uint16_t tmpreg;
/* Enable CRC Transmission */
if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
{
/* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */
if(((hspi->Instance->CR1 & SPI_CR1_MSTR) == 0) && ((hspi->Instance->CR2 & SPI_CR2_NSSP) == SPI_CR2_NSSP))
{
SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM);
}
hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
}
}
@ -2282,7 +2297,9 @@ static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
{
if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
__HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
return;
}
/* Disable TXE interrupt */
__HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
@ -2362,7 +2379,9 @@ static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
{
if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
__HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
return;
}
/* Disable TXE interrupt */
__HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
@ -2596,8 +2615,8 @@ static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi,
if((Timeout == 0) || ((HAL_GetTick()-tickstart) >= Timeout))
{
/* Disable the SPI and reset the CRC: the CRC value should be cleared
on both master and slave sides in order to resynchronize the master
and slave for their respective CRC calculation */
on both master and slave sides in order to resynchronize the master
and slave for their respective CRC calculation */
/* Disable TXE, RXNE and ERR interrupts for the interrupt process */
__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
@ -2714,12 +2733,12 @@ static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)
{
if(hspi->State == HAL_SPI_STATE_BUSY_RX)
{
hspi->State = HAL_SPI_STATE_READY;
hspi->State = HAL_SPI_STATE_READY;
HAL_SPI_RxCpltCallback(hspi);
}
else
{
hspi->State = HAL_SPI_STATE_READY;
hspi->State = HAL_SPI_STATE_READY;
HAL_SPI_TxRxCpltCallback(hspi);
}
}

171
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_spi.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_spi.h
* @author MCD Application Team
* @version V1.3.1
* @date 29-January-2016
* @version V1.4.0
* @date 27-May-2016
* @brief Header file of SPI HAL module.
******************************************************************************
* @attention
@ -99,7 +99,7 @@ typedef struct
This parameter can be a value of @ref SPI_CRC_Calculation */
uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation.
This parameter must be a number between Min_Data = 0 and Max_Data = 65535 */
This parameter must be an odd number between Min_Data = 0 and Max_Data = 65535 */
uint32_t CRCLength; /*!< Specifies the CRC Length used for the CRC calculation.
CRC Length is only used with Data8 and Data16, not other data size
@ -132,37 +132,37 @@ typedef enum
*/
typedef struct __SPI_HandleTypeDef
{
SPI_TypeDef *Instance; /* SPI registers base address */
SPI_TypeDef *Instance; /*!< SPI registers base address */
SPI_InitTypeDef Init; /* SPI communication parameters */
SPI_InitTypeDef Init; /*!< SPI communication parameters */
uint8_t *pTxBuffPtr; /* Pointer to SPI Tx transfer Buffer */
uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */
uint16_t TxXferSize; /* SPI Tx Transfer size */
uint16_t TxXferSize; /*!< SPI Tx Transfer size */
uint16_t TxXferCount; /* SPI Tx Transfer Counter */
__IO uint16_t TxXferCount; /*!< SPI Tx Transfer Counter */
uint8_t *pRxBuffPtr; /* Pointer to SPI Rx transfer Buffer */
uint8_t *pRxBuffPtr; /*!< Pointer to SPI Rx transfer Buffer */
uint16_t RxXferSize; /* SPI Rx Transfer size */
uint16_t RxXferSize; /*!< SPI Rx Transfer size */
uint16_t RxXferCount; /* SPI Rx Transfer Counter */
__IO uint16_t RxXferCount; /*!< SPI Rx Transfer Counter */
uint32_t CRCSize; /* SPI CRC size used for the transfer */
uint32_t CRCSize; /*!< SPI CRC size used for the transfer */
void (*RxISR)(struct __SPI_HandleTypeDef *hspi); /* function pointer on Rx IRQ handler */
void (*RxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Rx IRQ handler */
void (*TxISR)(struct __SPI_HandleTypeDef *hspi); /* function pointer on Tx IRQ handler */
void (*TxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Tx IRQ handler */
DMA_HandleTypeDef *hdmatx; /* SPI Tx DMA Handle parameters */
DMA_HandleTypeDef *hdmatx; /*!< SPI Tx DMA Handle parameters */
DMA_HandleTypeDef *hdmarx; /* SPI Rx DMA Handle parameters */
DMA_HandleTypeDef *hdmarx; /*!< SPI Rx DMA Handle parameters */
HAL_LockTypeDef Lock; /* Locking object */
HAL_LockTypeDef Lock; /*!< Locking object */
__IO HAL_SPI_StateTypeDef State; /* SPI communication state */
__IO HAL_SPI_StateTypeDef State; /*!< SPI communication state */
uint32_t ErrorCode; /* SPI Error code */
__IO uint32_t ErrorCode; /*!< SPI Error code */
}SPI_HandleTypeDef;
@ -197,8 +197,6 @@ typedef struct __SPI_HandleTypeDef
*/
#define SPI_MODE_SLAVE ((uint32_t)0x00000000)
#define SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI)
#define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \
((MODE) == SPI_MODE_MASTER))
/**
* @}
*/
@ -209,15 +207,6 @@ typedef struct __SPI_HandleTypeDef
#define SPI_DIRECTION_2LINES ((uint32_t)0x00000000)
#define SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY
#define SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE
#define IS_SPI_DIRECTION(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \
((MODE) == SPI_DIRECTION_2LINES_RXONLY) ||\
((MODE) == SPI_DIRECTION_1LINE))
#define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES)
#define IS_SPI_DIRECTION_2LINES_OR_1LINE(MODE) (((MODE) == SPI_DIRECTION_2LINES)|| \
((MODE) == SPI_DIRECTION_1LINE))
/**
* @}
*/
@ -238,19 +227,6 @@ typedef struct __SPI_HandleTypeDef
#define SPI_DATASIZE_14BIT ((uint32_t)0x0D00) /*!< SPI Datasize = 14bits */
#define SPI_DATASIZE_15BIT ((uint32_t)0x0E00) /*!< SPI Datasize = 15bits */
#define SPI_DATASIZE_16BIT ((uint32_t)0x0F00) /*!< SPI Datasize = 16bits */
#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_16BIT) || \
((DATASIZE) == SPI_DATASIZE_15BIT) || \
((DATASIZE) == SPI_DATASIZE_14BIT) || \
((DATASIZE) == SPI_DATASIZE_13BIT) || \
((DATASIZE) == SPI_DATASIZE_12BIT) || \
((DATASIZE) == SPI_DATASIZE_11BIT) || \
((DATASIZE) == SPI_DATASIZE_10BIT) || \
((DATASIZE) == SPI_DATASIZE_9BIT) || \
((DATASIZE) == SPI_DATASIZE_8BIT) || \
((DATASIZE) == SPI_DATASIZE_7BIT) || \
((DATASIZE) == SPI_DATASIZE_6BIT) || \
((DATASIZE) == SPI_DATASIZE_5BIT) || \
((DATASIZE) == SPI_DATASIZE_4BIT))
/**
* @}
*/
@ -260,8 +236,6 @@ typedef struct __SPI_HandleTypeDef
*/
#define SPI_POLARITY_LOW ((uint32_t)0x00000000) /*!< SPI polarity Low */
#define SPI_POLARITY_HIGH SPI_CR1_CPOL /*!< SPI polarity High */
#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_POLARITY_LOW) || \
((CPOL) == SPI_POLARITY_HIGH))
/**
* @}
*/
@ -271,8 +245,6 @@ typedef struct __SPI_HandleTypeDef
*/
#define SPI_PHASE_1EDGE ((uint32_t)0x00000000) /*!< SPI Phase 1EDGE */
#define SPI_PHASE_2EDGE SPI_CR1_CPHA /*!< SPI Phase 2EDGE */
#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_PHASE_1EDGE) || \
((CPHA) == SPI_PHASE_2EDGE))
/**
* @}
*/
@ -283,9 +255,6 @@ typedef struct __SPI_HandleTypeDef
#define SPI_NSS_SOFT SPI_CR1_SSM
#define SPI_NSS_HARD_INPUT ((uint32_t)0x00000000)
#define SPI_NSS_HARD_OUTPUT ((uint32_t)0x00040000)
#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT) || \
((NSS) == SPI_NSS_HARD_INPUT) || \
((NSS) == SPI_NSS_HARD_OUTPUT))
/**
* @}
*/
@ -295,9 +264,6 @@ typedef struct __SPI_HandleTypeDef
*/
#define SPI_NSS_PULSE_ENABLE SPI_CR2_NSSP
#define SPI_NSS_PULSE_DISABLE ((uint32_t)0x00000000)
#define IS_SPI_NSSP(NSSP) (((NSSP) == SPI_NSS_PULSE_ENABLE) || \
((NSSP) == SPI_NSS_PULSE_DISABLE))
/**
* @}
*/
@ -313,14 +279,6 @@ typedef struct __SPI_HandleTypeDef
#define SPI_BAUDRATEPRESCALER_64 ((uint32_t)0x00000028)
#define SPI_BAUDRATEPRESCALER_128 ((uint32_t)0x00000030)
#define SPI_BAUDRATEPRESCALER_256 ((uint32_t)0x00000038)
#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_2) || \
((PRESCALER) == SPI_BAUDRATEPRESCALER_4) || \
((PRESCALER) == SPI_BAUDRATEPRESCALER_8) || \
((PRESCALER) == SPI_BAUDRATEPRESCALER_16) || \
((PRESCALER) == SPI_BAUDRATEPRESCALER_32) || \
((PRESCALER) == SPI_BAUDRATEPRESCALER_64) || \
((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \
((PRESCALER) == SPI_BAUDRATEPRESCALER_256))
/**
* @}
*/
@ -330,8 +288,6 @@ typedef struct __SPI_HandleTypeDef
*/
#define SPI_FIRSTBIT_MSB ((uint32_t)0x00000000)
#define SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST
#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FIRSTBIT_MSB) || \
((BIT) == SPI_FIRSTBIT_LSB))
/**
* @}
*/
@ -341,8 +297,6 @@ typedef struct __SPI_HandleTypeDef
*/
#define SPI_TIMODE_DISABLE ((uint32_t)0x00000000)
#define SPI_TIMODE_ENABLE SPI_CR2_FRF
#define IS_SPI_TIMODE(MODE) (((MODE) == SPI_TIMODE_DISABLE) || \
((MODE) == SPI_TIMODE_ENABLE))
/**
* @}
*/
@ -352,8 +306,6 @@ typedef struct __SPI_HandleTypeDef
*/
#define SPI_CRCCALCULATION_DISABLE ((uint32_t)0x00000000)
#define SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN
#define IS_SPI_CRC_CALCULATION(CALCULATION) (((CALCULATION) == SPI_CRCCALCULATION_DISABLE) || \
((CALCULATION) == SPI_CRCCALCULATION_ENABLE))
/**
* @}
*/
@ -368,9 +320,6 @@ typedef struct __SPI_HandleTypeDef
#define SPI_CRC_LENGTH_DATASIZE ((uint32_t)0x00000000)
#define SPI_CRC_LENGTH_8BIT ((uint32_t)0x00000001)
#define SPI_CRC_LENGTH_16BIT ((uint32_t)0x00000002)
#define IS_SPI_CRC_LENGTH(LENGTH) (((LENGTH) == SPI_CRC_LENGTH_DATASIZE) ||\
((LENGTH) == SPI_CRC_LENGTH_8BIT) || \
((LENGTH) == SPI_CRC_LENGTH_16BIT))
/**
* @}
*/
@ -521,10 +470,10 @@ typedef struct __SPI_HandleTypeDef
*/
#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) \
do{ \
__IO uint32_t tmpreg; \
tmpreg = (__HANDLE__)->Instance->SR; \
__IO uint32_t tmpreg_modf; \
tmpreg_modf = (__HANDLE__)->Instance->SR; \
(__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE); \
UNUSED(tmpreg); \
UNUSED(tmpreg_modf); \
} while(0)
/** @brief Clear the SPI OVR pending flag.
@ -535,10 +484,10 @@ typedef struct __SPI_HandleTypeDef
*/
#define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) \
do{ \
__IO uint32_t tmpreg; \
tmpreg = (__HANDLE__)->Instance->DR; \
tmpreg = (__HANDLE__)->Instance->SR; \
UNUSED(tmpreg); \
__IO uint32_t tmpreg_ovr; \
tmpreg_ovr = (__HANDLE__)->Instance->DR; \
tmpreg_ovr = (__HANDLE__)->Instance->SR; \
UNUSED(tmpreg_ovr); \
} while(0)
/** @brief Clear the SPI FRE pending flag.
@ -549,9 +498,9 @@ typedef struct __SPI_HandleTypeDef
*/
#define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) \
do{ \
__IO uint32_t tmpreg; \
tmpreg = (__HANDLE__)->Instance->SR; \
UNUSED(tmpreg); \
__IO uint32_t tmpreg_fre; \
tmpreg_fre = (__HANDLE__)->Instance->SR; \
UNUSED(tmpreg_fre); \
} while(0)
/** @brief Enable the SPI peripheral.
@ -599,8 +548,68 @@ typedef struct __SPI_HandleTypeDef
#define SPI_RESET_CRC(__HANDLE__) do{(__HANDLE__)->Instance->CR1 &= (uint16_t)(~SPI_CR1_CRCEN);\
(__HANDLE__)->Instance->CR1 |= SPI_CR1_CRCEN;}while(0)
#define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \
((MODE) == SPI_MODE_MASTER))
#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x1) && ((POLYNOMIAL) <= 0xFFFF))
#define IS_SPI_DIRECTION(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \
((MODE) == SPI_DIRECTION_2LINES_RXONLY) ||\
((MODE) == SPI_DIRECTION_1LINE))
#define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES)
#define IS_SPI_DIRECTION_2LINES_OR_1LINE(MODE) (((MODE) == SPI_DIRECTION_2LINES)|| \
((MODE) == SPI_DIRECTION_1LINE))
#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_16BIT) || \
((DATASIZE) == SPI_DATASIZE_15BIT) || \
((DATASIZE) == SPI_DATASIZE_14BIT) || \
((DATASIZE) == SPI_DATASIZE_13BIT) || \
((DATASIZE) == SPI_DATASIZE_12BIT) || \
((DATASIZE) == SPI_DATASIZE_11BIT) || \
((DATASIZE) == SPI_DATASIZE_10BIT) || \
((DATASIZE) == SPI_DATASIZE_9BIT) || \
((DATASIZE) == SPI_DATASIZE_8BIT) || \
((DATASIZE) == SPI_DATASIZE_7BIT) || \
((DATASIZE) == SPI_DATASIZE_6BIT) || \
((DATASIZE) == SPI_DATASIZE_5BIT) || \
((DATASIZE) == SPI_DATASIZE_4BIT))
#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_POLARITY_LOW) || \
((CPOL) == SPI_POLARITY_HIGH))
#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_PHASE_1EDGE) || \
((CPHA) == SPI_PHASE_2EDGE))
#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT) || \
((NSS) == SPI_NSS_HARD_INPUT) || \
((NSS) == SPI_NSS_HARD_OUTPUT))
#define IS_SPI_NSSP(NSSP) (((NSSP) == SPI_NSS_PULSE_ENABLE) || \
((NSSP) == SPI_NSS_PULSE_DISABLE))
#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_2) || \
((PRESCALER) == SPI_BAUDRATEPRESCALER_4) || \
((PRESCALER) == SPI_BAUDRATEPRESCALER_8) || \
((PRESCALER) == SPI_BAUDRATEPRESCALER_16) || \
((PRESCALER) == SPI_BAUDRATEPRESCALER_32) || \
((PRESCALER) == SPI_BAUDRATEPRESCALER_64) || \
((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \
((PRESCALER) == SPI_BAUDRATEPRESCALER_256))
#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FIRSTBIT_MSB) || \
((BIT) == SPI_FIRSTBIT_LSB))
#define IS_SPI_TIMODE(MODE) (((MODE) == SPI_TIMODE_DISABLE) || \
((MODE) == SPI_TIMODE_ENABLE))
#define IS_SPI_CRC_CALCULATION(CALCULATION) (((CALCULATION) == SPI_CRCCALCULATION_DISABLE) || \
((CALCULATION) == SPI_CRCCALCULATION_ENABLE))
#define IS_SPI_CRC_LENGTH(LENGTH) (((LENGTH) == SPI_CRC_LENGTH_DATASIZE) ||\
((LENGTH) == SPI_CRC_LENGTH_8BIT) || \
((LENGTH) == SPI_CRC_LENGTH_16BIT))
#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x1) && ((POLYNOMIAL) <= 0xFFFF) && (((POLYNOMIAL)&0x1) != 0))
/**

4
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_spi_ex.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_spi_ex.c
* @author MCD Application Team
* @version V1.3.1
* @date 29-January-2016
* @version V1.4.0
* @date 27-May-2016
* @brief Extended SPI HAL module driver.
* This file provides firmware functions to manage the following
* SPI peripheral extended functionalities :

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