diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/Release_Notes_stm32f0xx_hal.html b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/Release_Notes_stm32f0xx_hal.html index 185f5d2c67..5b99b9514a 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/Release_Notes_stm32f0xx_hal.html +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/Release_Notes_stm32f0xx_hal.html @@ -1,877 +1,870 @@ -Release Notes for STM32F0xx HAL Drivers - -
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Release -Notes for STM32F0xx HAL Drivers

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Copyright -2015 STMicroelectronics

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Update History

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V1.3.0 -/ 26-June-2015

Main -Changes

  • Maintenance release to fix known defects and -enhancements implementation
  • Complete HAL API alignment (macro/function renaming)
  • HAL Generic
    • Update HAL drivers to be MISRA/C++ compliant.
    • Initialized handle lock in HAL_PPP_Init().
    • Add SYSCFG define macros to manage FM+ on GPIOs.
    • Use uint32_t instead of uint8_t/uint_16.
  • HAL ADC
    • Update ADC state machine. Missing state in function "HAL_ADCEx_Calibration_Start().
    • Align ADC_SOFTWARE_START literal on STM32L0xx.
    • HAL_ADC_PollForConversion(): update to return error status in case of ADC-DMA mode.
    • HAL_ADC_Init(): ADC resolution must be changed only when ADC is disabled.
    • ADC_ConversionStop(): correct wrong timeout value.
    • HAL_ADC_AnalogWDGConfig(): Add missing assert param.
    • Remove channel for monitoring VBAT power supply pin on F0 Value line devices.
    • Move -sampling time setting into ADC init stucture (keep setting into ADC -channel init stucture with comments of obsolete setting).
    • Move -__HAL_UNLOCK() before peripheral activation because if an interruption -occurs between ADC enable & __HAL_UNLOCK(), IRQ handler will be -executed while HAL still locked.
    • ADC_DMAConvCplt(): Add call to ADC error callback in case of error.
    • Rename local variables for compliancy with coding rules (tmpHALstatus ==> tmp_hal_status).
    • Simplify __HAL_ADC_GET_IT_SOURCE().
    • Add use of POSITION_VAL.
    • Add optimization of ADC stabilization delays.
  • HAL CAN 
    • Add management of CAN Slave start bank in HAL_CAN_ConfigFilter().
    • Unlock the CAN process when communication error occurred.
    • Replace “uint32_t Data[8]” by “uint8_t Data[8]” in structures  CanTxMsgTypeDef and CanRxMsgTypeDef.
  • HAL CEC 
    • Add new API HAL_CEC_GetReceivedFrameSize() to get size of received frame
  • HAL CORTEX 
    • Add new macro IS_NVIC_DEVICE_IRQ() to -check on negative values of IRQn parameter
  • HAL CRC 
    • Add new macros __HAL_CRC_GET_IDR() and __HAL_CRC_SET_IDR().
    • Update __HAL_CRC_SET_IDR macro in resorting to WRITE_REG instead of MODIFY_REG (cycles gain at execution).
  • HAL DAC 
    • HAL_DAC_IRQHandler(): update to check on both DAC_FLAG_DMAUDR1 and -DAC_FLAG_DMAUDR2.
  • HAL DMA
    • Correct __HAL_DMA_GET_IT_SOURCE brief comments.
  • HAL FLASH
    • FLASH_OB_GetRDP(): update function to return the FLASH Read Protection level (OB_RDP_LEVEL_x).
    • FLASH_OB_RDP_LevelConfig(): update function to set the FLASH Read Protection level (OB_RDP_LEVEL_x).
    • Add missing macro __HAL_FLASH_GET_LATENCY.
    • Disable WRP not compliant with other family.
    • Add FLASH_BANK1_END defines.
    • Remove WRP defines for few defines under devices swicthes.
    • Add switch to handle option bits BOOT_SEL & nBOOT1 not present on STM32F030xC & STM32F070x6.
  • HAL GPIO 
    • stm32f0xx_hal_gpio_ex.h: add IR as possible GPIO alternate function 1 for STM32F030x6.
  • HAL I2C
    • HAL_I2C_ER_IRQHandler(): handle NACK test during wait on flag treatment.
  • HAL I2S
    • HAL_I2S_DMAStop(): Correctt DMA Stop function which stops both Rx and Tx channels regardless which one was set-up.
  • HAL IRDA
    • HAL_IRDA_DMAStop(): update comments regarding deletion of LOCK/UNLOCK mechanism.
  • HAL PWR
    • Add macros __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() and __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE.
    • Update HAL_PWR_EnableBkUpAccess() and HAL_PWR_DisableBkUpAccess() comments.
  • HAL RCC
    • Implement workaround to cover RCC limitation regarding Peripheral enable delay.
    • HAL_RCC_OscConfig(): correct test on LSEState.
    • Rework __HAL_RCC_LSE_CONFIG macro to manage correctly LSE_Bypass.
    • Add defines for RCC_System_Clock_Source_Status.
    • Follow specific procedure to enable HSE.
    • Add macros to get the enable or disable status of peripheral clock.
    • HAL_RCCEx_PeriphCLKConfig(): reset backup domain only if RTC clock source has been changed.
    • Add interface HAL_RCCEx_GetPeriphCLKFreq.
  • HAL RTC
    • Add missing RTC_FLAG_INIT in flag list.
    • HAL_RTC_DeInit(): add switch products condition around WakeUp timer registers (WUTWF,WUTR).
    • Remove RTC_FLAG_INIT as currently unused.
  • HAL SMARTCARD
    • Add missing IDLE flag management.
    • Align SMARTCARD_Last_Bit defines.
  • HAL SPI 
    • Fix issue related to missing reset of the Dma Tx callback inside the function HAL_SPI_TransmitReceive_DMA().
      In -that case only RX callback are used and the call of TX callback can -close the communication before the end of the RX processing.
    • SPI_2linesRxISR_8BIT(): -correct issue on RX 2lines with DataSize8bit, even buffer size and CRC -8bit (SPI_RXFIFO_THRESHOLD is not set).
    • Fit bit update add BSY flag check for all the process.
    • Add -__IO (volatile) to the "State" member of the SPI_HandleTypeDef -struct. to missing reset of the Dma Tx callback inside the -function -HAL_SPI_TransmitReceive_DMA().
  • HAL TIM
    • Add __HAL_TIM_SET_CAPTUREPOLARITY, TIM_SET_CAPTUREPOLARITY, TIM_RESET_CAPTUREPOLARITY macros.
  • HAL UART
    • Add macro to control CTS and RTS from the customer applications.
    • UART_DMATransmitCplt(): change implementation to remove WaitOnFlag in ISR.
    • Change DMA TX management to remove WaitOnFlag in ISR.
    • Add DMA circular mode support for the communication peripherals.
    • Add UART NVIC configuration in the HAL_UART_MspInit().
    • Add the UARTx_IRQHandler() in the stm32fxxx_it.c and the prototype in the stm32fxxx_it.h.
    • Modify UART DMA implementation issue (missed clear the TC bit in the SR).
    • Add a OVR flag clear prior resuming DMA RX transfer.
    • HAL_UART_DMAResume(): Remove UART_CheckIdleState() call and replace it by unlock + return(HAL_OK).
    • HAL_UART_DMAStop(): remove LOCK/UNLOCK calls.
    • HAL_UART_DMAStop(): update comments regarding deletion of LOCK/UNLOCK mechanism.
  • HAL USART
    • HAL_USART_IRQHandler(): Correct parameters values of __HAL_USART_CLEAR_IT().
    • Replace xxxITxxx defines by xxxCLEARxxxF defines in __HAL_USART_CLEAR_IT calls.
    • HAL_USART_Init(): update to reach max frequencies (enable oversampling by 8).
    • HAL_USART_DMAPause()/HAL_USART_DMAResume(): add of a OVR flag clear prior resuming DMA RX transfer.
    • HAL_USART_DMAResume(): Remove UART_CheckIdleState() call and replace it by just an Unlock + ret(HAL_OK).
    • HAL_USART_DMAStop(): update comments regarding deletion of LOCK/UNLOCK mechanism.

V1.2.1 -/ 09-January-2015

  • HAL 
    • stm32f0xx_hal.h: add missing define for USART3_RX/TX DMA remap on channel3 & channel2 for STM32F070xB only
  • HAL GPIO
    • stm32f0xx_hal_gpio_ex.h: add I2C1 as possible GPIO alternate function 3 for STM32F070xB
  • HAL RCC
    • stm32f0xx_hal_rcc_ex.h: add missing USART2_CLK_ENABLE/DISABLE() macros for STM32F070x6
  • HAL RTC -
    • stm32f0xx_hal_rtc_ex.h/.c: -Enable RTC periodic Wakeup timer feature on STM32F070xB -& STM32F030xC -
    • stm32f0xx_hal_rtc_ex.c: -remove HAL_RTCEx_Tamper3EventCallback() -API for STM32F070xB -& STM32F030xC, since -there is no TAMPER3 on those products.
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  • HAL UART -
    • stm32f0xx_hal_uart_ex.c/.h: -add HAL_RS485Ex_Init() API for STM32F0xx Value -Line devices

V1.2.0 -/ 05-December-2014

Main -Changes

-
  • HAL generic 
    • Add support of new STM32F0 value line devices STM32F070xB/x6 and STM32F030xC.
    • HandleTypeDef.ErrorCode must be typed uint32_t
    • Update HAL drivers to ensure compliancy w/ C++
    • Add some generic defines (__NOINLINE) in stm32f0xx_hal_def.h
    • Case mismatch between #include typo and effective file name generating compiler errors under Linux
    • Correct various issues for documentation generation (group name, doxygen tags, etc..)
    • Missing support of I2C_PAx_FMP of F04xx devices
  • HAL ADC 

    • Improve HAL ADC comments
    • Correct issue observed with ADC start simultaneous commands
    • Remove macro __HAL_ADC_OFR_CHANNEL() since OFRx register is not available on F0 devices.
  • HAL CAN 
    • ErrorCode field is now declared as __IO uint32 instead of enum HAL_CAN_ErrorTypeDef to fix C++ compilation issue
  • HAL CEC 

    • change ErrorCode field declaration from uint32_t  to __IO uint32_t
    • correct CEC state: Ready to Receive state lost upon Transmission end

  • HAL COMP 
    • State field is now declared as uint32_t instead of enum HAL_COMP_StateTypeDef to fix C++ compilation issue
    • change HAL_COMP_GetState() type declaration from HAL_COMP_StateTypeDef to uint32_t to fix C++ compilation issue
  • HAL CRC 

    • Wrong @ref in CRCLength field description for documentation generation 

    • Add support of new STM32F0 value line devices STM32F070xB/x6 and STM32F030xC.
  • HAL DAC 

    • HAL_DAC_Stop_DMA() code clean up

    • Use of internal macro MODIFY_REG() to update CR register
  • HAL DMA 

    • Add support of new STM32F0 value line devices STM32F070xB/x6 and STM32F030xC.
    • DMA channel remap register renamed for compatibility with other STM32 devices.
    • Correct wrong comments in __HAL_DMA_GET_FLAG and __HAL_DMA_CLEAR_FLAG macros description
  • HAL FLASH 
    • Fix in macro IS_OPTIONBYTE(VALUE) when all option_OB are selected
    • ErrorCode field is now declared as uint32 instead of enum FLASH_ErrorTypeDef to fix C++ compilation issue
    • change HAL_FLASH_GetError() type declaration from FLASH_ErrorTypeDef to uint32_t to fix C++ compilation issue
    • Clean the error context to FLASH_ERROR_NONE before starting new Flash operation
    • Put all the clear flags in the FLASH_SetSerrorCode()
    • Stop the programming procedure in case of error detected in HAL_FLASH_Program()
    • Check error before doing new procedure in HAL_FLASH_IRQhandler()
  • HAL GPIO 

    • Add support of new STM32F0 value line devices STM32F070xB/x6 and STM32F030xC.
    • correct Typo in 'How to use this driver' section & update comments
    • Add assert on GPIO PIN in HAL_GPIO_DeInit()
    • Add assert on GPIO AF instance to protect HAL_GPIO_Init() from impossible AF configuration
    • Rename internal macro GET_GPIO_INDEX() into GPIO_GET_INDEX()
    • Reset Interrupt mode registers only in HAL_GPIO_DeInit()
  • HAL I2C
    • Add support of new STM32F0 value line devices STM32F070xB/x6 and STM32F030xC.
    • ErrorCode field is now declared as uint32 instead of enum HAL_I2C_ErrorTypeDef to fix C++ compilation issue
  • HAL I2S 

    • ErrorCode field is now declared as uint32 instead of enum HAL_I2S_ErrorTypeDef to fix C++ compilation issue.
    • Change HAL_I2S_GetError() type declaration from HAL_I2S_ErrorTypeDef to uint32_t to fix C++ compilation issue.
    • Add use of UNUSED(tmpreg) in __HAL_I2S_CLEAR_OVRFLAG() & __HAL_I2S_CLEAR_UDRFLAG to fix Unused variable" warning w/ TrueSTUDIO.
    • Typo in 'I2S HAL driver macros list' section of stm32f0xx_hal_i2s.c
    • Missing doxygen tags for I2S_HandleTypeDef fields description (documentation generation)
  • HAL IRDA 

    • ErrorCode field is now declared as uint32 instead of enum HAL_IRDA_ErrorTypeDef to fix C++ compilation issue
    • Missing doxygen tags for IRDA_HandleTypeDef fields description
  • HAL PWR 

    • Add support of new STM32F0 value line devices STM32F070xB/x6 and STM32F030xC.
    • Add new API to manage SLEEPONEXIT and SEVONPEND bits of SCR register:
  • HAL_PWR_DisableSleepOnExit()
  • HAL_PWR_EnableSleepOnExit()
  • HAL_PWR_EnableSEVOnPend()
  • HAL_PWR_DisableSEVOnPend()
    • Removed useless regulator parameter setting for F0 family in core of HAL_PWR_EnterSLEEPMode()
  • HAL RCC 

    • Add support of new STM32F0 value line devices STM32F070xB/x6 and STM32F030xC.
    • Add a comment in the 'How to use this driver' section to mention the Peripheral enable delay
    • Move __HAL_RCC_USART2_CONFIG() & __HAL_RCC_GET_USART2_SOURCE() from stm32f0xx_hal_rcc.h to stm32f0xx_hal_rcc_ex.h since this feature is not supported on all F0 devices
    • Change HAL_RCCEx_CRSWaitSynchronization() type declaration from RCC_CRSStatusTypeDef to uint32_t to fix C++ compilation issue
  • HAL RTC 

    • Add support of new STM32F0 value line devices STM32F070xB/x6 and STM32F030xC.
    • Enhance @note describing the use of HAL RTC APIs 
  • HAL SMARTCARD
    • ErrorCode field is now declared as uint32 instead of enum HAL_SMARTCARD_ErrorTypeDef to fix C++ compilation issue
  • HAL SMBUS
    • ErrorCode & PreviousState fields are now declared as uint32 instead of enum HAL_SMBUS_ErrorTypeDef & HAL_SMBUS_StateTypeDef to fix C++ compilation issue
    • Change HAL_SMBUS_GetState() type declaration from HAL_SMBUS_StateTypeDef to uint32_t to fix C++ compilation issue
  • HAL SPI 

    • ErrorCode field is now declared as uint32 instead of enum HAL_SPI_ErrorTypeDef to fix C++ compilation issue
    • Add use of UNUSED(tmpreg) in __HAL_SPI_CLEAR_MODFFLAG(), __HAL_SPI_CLEAR_OVRFLAG(), __HAL_SPI_CLEAR_FREFLAG() to fix "Unused variable" warning w/ TrueSTUDIO.
    • Add DMA circular mode support on SPI HAL driver.
    • Internal -fucntion renaming: HAL_SPI_DMATransmitCplt(), -HAL_SPI_DMAReceiveCplt(), HAL_SPI_DMATransmitReceiveCplt() & -HAL_SPI_DMAError() renamed respectively into SPI_DMATransmitCplt(), SPI_DMAReceiveCplt(), SPI_DMATransmitReceiveCplt() & SPI_DMAError().
    • Remove unused HAL_StatusTypeDef SPI_EndRxTxTransaction() prototype
    • uint32_t driver alignment for compatibility with other STM32 devices
    • Add new API HAL_SPI_GetError(), which was missing on STM32F0xx family
  • HAL UART/USART 

    • Add support of new STM32F0 value line devices STM32F070xB/x6 and STM32F030xC.
    • structure UART_WakeUpTypeDef moved to stm32f0xx_hal_uart_ex.h since wakeup feature is not available on all F0 devices.
    • ErrorCode field is now declared as uint32 instead of enum HAL_U(S)ART_ErrorTypeDef to fix C++ compilation issue
    • unused HAL_USART_SetConfig() prototype to be removed from stm32f0xx_hal_usart.h
    • Add missing API HAL_StatusTypeDef HAL_LIN_SendBreak()
    • correct wrong USART_IT_CM value
    • correct issue with Lin mode data length
    • Add new value for Stop bit definition: UART_STOPBITS_1_5
  • HAL USB 

    • Add support of new STM32F0 value line devices STM32F070xB/x6.
    • Wrong comment in HAL_PCD_Dev(Connect/Disconnect) functions description
    • Correct _HAL_PCD_CLEAR_FLAG() macros definition
  • HAL WWDG 

    • Add new macro to manage WWDG IT & correction:

      • __HAL_WWDG_DISABLE_IT()
      • __HAL_WWDG_GET_IT()
      • __HAL_WWDG_GET_IT_SOURCE()

V1.1.0 -/ 03-October-2014

Main -Changes

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  • HAL generic 
    • general improvement of Doxygen Tags for CHM UM generation
    • Add support of new devices STM32F091xCSTM32F098xx in STM32F0xx HAL drivers
    • minor corrections for Pdf/Chm UM generation
    • Correction for MISRA 
    • [F098xx] Remove PVD IT line wrapper
    • FLAG&IT assert macros to be removed
    • Bad macro name in stm32F0xx_hal.c/.h files
    • uint32_t Alignement in HAL driver
  • HAL update (for STM32F091xC/STM32F098xx)
    • Add new define for HAL IRDA Enveloppe source Selection
    • Add new macro IS_HAL_SYSCFG_IRDA_ENV_SEL()
    • Add new defines for ISR Wrapper (HAL_SYSCFG_ITLINE0, etc..)
    • Add new macro __HAL_GET_PENDING_IT()
    • Add new macro __HAL_SYSCFG_IRDA_ENV_SELECTION()
    • Add new macro __HAL_SYSCFG_GET_IRDA_ENV_SELECTION()
  • HAL COMP 

    • Missing assert param IS_COMP_TRIGGERMODE
  • HAL Cortex 

    • remove Macro not supported by cortex-M0 in stm32f0xx.h

  • HAL DMA 

    • Add new defines for DMAx Channel remapping (DMAx_CHANNELx_RMP)
    • Add new defines for DMAx channels remap bit field definition
    • Add new macros: IS_HAL_DMA1_REMAP(), IS_HAL_DMA2_REMAP()
    • Add new macro: __HAL_DMA_GET_TC_FLAG_INDEX(), that returns specified transfer complete flag index
    • Add new macro: __HAL_DMA_GET_HT_FLAG_INDEX(), that returns specified half transfer complete flag index
    • Add new macro: __HAL_DMA_GET_TE_FLAG_INDEX(), that returns specified transfer error flag index
    • Add new macro: __HAL_DMA_GET_FLAG()
    • Add new macro: __HAL_DMA_CLEAR_FLAG()
    • Add new macro: __HAL_DMA1_REMAP(), __HAL_DMA2_REMAP()
    • Bit definition name error for HAL_DMA1_CH2 remap on STM32F091xC
    • HAL_DMA_PollForTransfer updated
  • HAL GPIO 

    • BSRR regsiter should not be split in BSRRH/BSRRL
    • rework GPIO_GET_SOURCE
    • Add new defines for AF functions selection
  • HAL I2S 

    • Supp ClockSource in Init

  • HAL IRDA 

    • Incorrect definition for IS_IRDA_REQUEST_PARAMETER macro

  • HAL IWDG 

    • Use WRITE_REG instead of SET_BIT

  • HAL PWR 

    • Functions for VDDIO2 management missing in all F09xx, F07xx, F04xx

    • PVD feature need falling/rising Event modes
      • Update defines name PWR_MODE_EVT/PWR_MODE_IT_RISING/PWR_MODE_IT_FALLING/PWR_MODE_IT_RISING_FALLING to PWR_PVD_MODE_NORMAL/PWR_PVD_MODE_IT_RISING/PWR_PVD_MODE_IT_FALLING/PWR_PVD_MODE_IT_RISING_FALLING
      • Add new defines PWR_PVD_MODE_EVENT_RISING, PWR_PVD_MODE_EVENT_FALLING, PWR_PVD_MODE_EVENT_RISING_FALLING
      • Update macro IS_PWR_PVD_MODE()
      • change macro name: __HAL_PWR_PVD_EXTI_ENABLE_IT(), __HAL_PWR_PVD_EXTI_DISABLE_IT(), __HAL_PWR_PVD_EXTI_GENERATE_SWIT(), __HAL_PWR_PVD_EXTI_GET_FLAG(),  __HAL_PWR_PVD_EXTI_CLEAR_FLAG()
      • Add -new macro __HAL_PWR_PVD_EXTI_ENABLE_EVENT(), -__HAL_PWR_PVD_EXTI_DISABLE_EVENT(), -__HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER(), -__HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER()
  • HAL RCC 
    • Defect correction:
      • HAL_RCC_OscConfig: HSERDY has to be checked also in by pass mode
      • STM32F091xC/STM32F098xx
        • New structure RCC_PeriphCLKInitTypeDef
        • Add -defines for RCC new peripheral clock selection: RCC_PERIPHCLK_USART1, -RCC_PERIPHCLK_USART2, RCC_PERIPHCLK_I2C1, RCC_PERIPHCLK_CEC, -RCC_PERIPHCLK_RTC, RCC_PERIPHCLK_USART3
        • Add macro IS_RCC_PERIPHCLK()
        • Add -defines for USART3 clock source selection (RCC_USART3CLKSOURCE_PCLK1, -RCC_USART3CLKSOURCE_SYSCLK, CC_USART3CLKSOURCE_LSE, -CC_USART3CLKSOURCE_HSI
        • Add macro IS_RCC_USART3CLKSOURCE()
        • Add macro __HAL_RCC_GET_USART3_SOURCE()
        • Add macro __HAL_RCC_USART3_CONFIG()
        • add clock enable macros for new UART: __USART5_CLK_ENABLE,  __USART6_CLK_ENABLE, __USART7_CLK_ENABLE, __USART8_CLK_ENABLE
        • add clock disable macros for new UART: __USART5_CLK_DISABLE,  __USART6_CLK_DISABLE, __USART7_CLK_DISABLE, __USART8_CLK_DISABLE
        • add Force reset macros for new UART: __USART5_FORCE_RESET, __USART6_FORCE_RESET, __USART7_FORCE_RESET, __USART8_FORCE_RESET
        • add Release reset macros for new UART: __USART5_RELEASE_RESET, __USART6_RELEASE_RESET, __USART7_RELEASE_RESET, __USART8_RELEASE_RESET 
  • HAL SMARTCARD 

    • change SMARTCARD_AdvFeatureConfig() from exported to static private function
    • STM32F091xC/STM32F098xx:
      • Add new macro __HAL_SMARTCARD_GETCLOCKSOURCE() for USART1, USART2, USART3, USAR
  • HAL SMBUS  

    • change SMARTCARD_AdvFeatureConfig() from exported to static private function
  • HAL SPI 

    • Function HAL_SPI_TransmitReceive muse use SPI_FLAG_RXNE to read CRC

    • Function HAL_SPI_IRQHandler, in case of error the state must be reset to ready
  • HAL TIM 

    • Missed/Unused assert param to be added/removed
    • Trigger interrupt should be activated when working with a slave mode
    • Break interrupt should be activated in HAL_TIMEx_OCN_Start_IT
    • Wrong CCMR register cleared in HAL_TIM_IRQHandler for Input Capture event Channel 3 and 4
    • missing assert in HAL_TIMEx_ConfigBreakDeadTime
    • Add URS_ENABLE/ URS_DISABLE macros
  • HAL UART/USART 

    • Change UART TX-IT implementation to remove WaitOnFlag in ISR
    • STM32F091xC/STM32F098xx:
      • Add new macro __HAL_UART_GETCLOCKSOURCE() for USART1, USART2, USART3, USART4
      • Add new macro __HAL_USART_GETCLOCKSOURCE() for USART1, USART2, USART3, USART4
  • HAL USB 

    • Bad IN/OUT EndPoint parameter array size

  • HAL WWDG 

    • improvements from other families

Defect Correction

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STM32F0xx_HAL_Driver

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Defect

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PWR

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PVD feature need falling/rising Event modes

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STM32F0xx_HAL_Driver

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Defect

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COMP

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Missing assert param IS_COMP_TRIGGERMODE 

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STM32F0xx_HAL_Driver

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Defect

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RCC

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HAL_RCC_OscConfig: HSERDY has to be checked also in by - pass mode

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V1.0.1 -/ 18-June-2014

Main -Changes

-
  • - - - - - - - -

    HAL generic update

    • Fix flag clear procedure: use atomic write operation "=" instead of ready-modify-write operation "|=" or "&="
    • Fix -on Timeout management, Timeout value set to 0 passed to API -automatically exits the function after checking the flag without any -wait.
    • Add -new macro __HAL_RESET_HANDLE_STATE to reset a given handle state.
  • HAL CEC update

    • Process no more locked during the transmission in interrupt mode. 
  • HAL COMP update

    • Add NonInvertingInput field in the COMP_InitTypeDef structure.
    • Add new defines COMP_NONINVERTINGINPUT_IO1 and COMP_NONINVERTINGINPUT_DAC1SWITCHCLOSED
  • HAL DMA update

    • Fix in HAL_DMA_PollForTransfer() to set error code HAL_DMA_ERROR_TE in case of HAL_ERROR status
  • - - - - - - - -

    HAL I2C update

    • Add -management of NACK event in Master transmitter mode and Slave -transmitter/receiver modes (only in polling mode), in that case the -current transfer is stopped.
  • HAL I2S update

    • I2S clock source change: new define I2S_CLOCK_SYSCLK, remove I2S_CLOCK_PLL
    • Improvement done in I2S transfer/receive processes
  • HAL IRDA update

    • Add new enum typedef IRDA_ClockSourceTypeDef
    • Add new macro __HAL_IRDA_GETCLOCKSOURCE
    • Change in HAL_IRDA_Transmit_IT() to enable IRDA_IT_TXE instead of IRDA_IT_TC.
    • Process no more locked during the transmission in interrupt mode.
  • -

    HAL PCD update

    -
    • -

      Add new macro __HAL_USB_EXTI_GENERATE_SWIT

      -
  • HAL PWR update

    • Fix in HAL_PWR_EnterSTANDBYMode() to not clear Wakeup flag (WUF), which need to be cleared at application level before to call this function
  • HAL RCC update

    • Add USB peripheral and clocking macros for STM32F078xx device.
    • Fix HSI Calibration issue when selected as SYSCLK
  • - - - - - - - -

    HAL SMARTCARD update

    • Change in HAL_SMARTCARD_Transmit_IT() to enable SMARTCARD_IT_TXE instead of SMARTCARD_IT_TC.
    • Process no more locked during the transmission in interrupt mode.
  • HAL SMBUS update

    • Fix Slave acknowledge issue: Slave should ack each bit and so stretch the line till the bit is not ack
  • HAL TIM update

    • Fix macro __HAL_TIM_PRESCALER
  • HAL TSC update

    • Fix define TSC_ACQ_MODE_SYNCHRO
  • - - - - - - - -

    HAL UART update

    • Change in HAL_LIN_Init() parameter BreakDetectLength to uint32_t
    • Change in HAL_UART_Transmit_IT() to enable UART_IT_TXE instead of UART_IT_TC.
    • Process no more locked during the transmission in interrupt mode.
  • HAL USART update

    • Change USART_InitTypeDef fields to uint32_t type
    • Rename __USART_ENABLE and __USART_DISABLE macros to respectively __HAL_USART_ENABLE and __HAL_USART_DISABLE
    • Change in HAL_USART_Transmit_IT() to enable USART_IT_TXE instead of USART_IT_TC.
    • Process no more locked during the transmission in interrupt mode.
    • Change in HAL_USART_TransmitReceive_DMA() to manage DMA half transfer mode

V1.0.0 -/ 20-May-2014

-

Main -Changes

-
  • First official -release of STM32F0xx HAL drivers for STM32F030x4/x6, STM32F030x8, STM32F031x4/x6,  STM32F051x4/x6/x8 STM32F071x8/xB,  STM32F042x4/x6, -STM32F072x8/xB,  STM32F038xx, - STM32F048xxSTM32F058xx and STM32F078xx -devices.

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+Release Notes for STM32F0xx HAL Drivers + +
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Release +Notes for STM32F0xx HAL Drivers

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Update History

+

V1.4.0 +/ 27-May-2016

  • First official release supporting the Low Level drivers for the STM32F0xx family:
    • Low Layer drivers APIs provide register level programming:
      they require deep knowledge of peripherals described in STM32F0xx Reference Manual.
    • Low Layer drivers are available for ADC, COMP, Cortex, CRC, CRS, DAC, DMA, EXTI, +GPIO, I2C, IWDG, PWR,
      RCC, RTC, SPI, TIM, USART and WWDG peripherals
      and additional Low Level Bus, System and Utilities APIs.
    • Low Layer drivers APIs are implemented as static inline function in new Inc/stm32f0xx_ll_ppp.h files for PPP peripherals,
      there is no configuration file and each stm32f0xx_ll_ppp.h file must be included in user code.
  • Maintenance release to fix known defects and enhancements implementation.
  • HAL generic
    • Updated HAL Driver compliancy with MISRA C 2004 rules:
      • MISRA C 2004 rule 5.2 (tmpreg" variable shall not be used inside MACRO)
      • MISRA C 2004 rule 10.3 (illegal explicit conversion from type "unsigned int" to "uint16_t *).
      • MISRA C 2004 rule 10.5 (bitwise operators ~ and <<).
      • MISRA C 2004 rule 10.6 ('U' suffix applied to all constants of 'unsigned' type).
      • MISRA C 2004 rule 11.5 (no cast that removes any const or volatile qualification from the type addressed by a pointer).
      • MISRA C 2004 rule 12.6 (logical operators should not be confused with bitwise operators).
      • MISRA C 2004 rule 12.7 (bitwise operations not performed on signed integer types).
      • MISRA C 2004 rule 14.3 (a null statement shall only occur on a line by itself).
      • MISRA C 2004 rule 14.9 ('if {expression}' / 'else' construct shall be followed by a compound statement).
      • MISRA C 2004 rule 15.3 (all switch statements shall contain a final default clause).
      • MISRA C 2004 rule 16.3 (identifiers shall be given for all of the parameters in a function prototype declaration).
      • MISRA C 2004 rule 16.4 (identifiers used in the declaration and definition shall be identical).
      • MISRA C 2004 rule 19.10 (in function-like macro definition, each instance of a parameter shall be enclosed in parenthesis).
  • HAL
    • Changed uwTick to global to allow overwrite of HAL_IncTick().
  • HAL COMP
    • Added delay in COMP startup time required to reach propagation delay specification.
  • HAL CRC
    • Updated devices supporting Programmable Polynomial features: defines and functions prototypes are available only for
      STM32F071xB, STM32F072xB, STM32F078xx, STM32F091xC, STM32F098x devices.
    • Updated HAL_CRC_DeInit() function (restored IDR Register to Reset value).
  • HAL DMA
    • Added __HAL_DMA_GET_COUNTER() macro returning the number of remaining data units in the current DMA Channel transfer.
    • Provided +new function HAL_DMA_Abort_IT() to abort current DMA transfer +under interrupt mode without polling for DMA enable bit.
  • HAL GPIO
    • Updated IS_GPIO_PIN() macro to cover full u32 bits.
  • HAL I2C
    • Used macro definition for I2C instances supporting Wakeup from Stop mode.
    • Updated polling flags management within I2C slave DMA drivers.
    • Added support of repeated start feature in case of multimaster mode (allow master to keep I2C communication with slave).
    • Updated WaitOnFlag management (timeout measurement should be always cumulative).
    • Optimized HAL_I2C_XX_IRQHandler() functions (read status registers only once).
    • Reworked DMA end process and I2C error management during DMA transfer.
  • HAL PWR
    • Aligned EWUPx pins and PWR functions with CMSIS definitions.
  • HAL IRDA
    • Modified IRDA_Receive_IT() to execute the RX flush request only in case no data is read from RDR.
    • Modified EIE bit setting in Tx and Rx transfers (Interrupt mode).
    • Updated IRDA_SetConfig() function following UART Baudrate calculation update.
    • Reviewed IRDA state machine to avoid cases where IRDA state is overwritten by IRDA IRQ.
    • Ensure proper alignment of data pointer in Transmit and Receive functions to avoid toolchain compilation hardfault.
  • HAL RCC
    • Performed optimizations for HAL_RCC_ClockConfig(), HAL_RCCEx_PeriphCLKConfig functions.
    • Updated HAL_RCC_OscConfig() function (Reset HSEON/LSEON and HSEBYP/LSEBYP bits before configuring the HSE/LSE).
    • Updated HAL_RCC_OscConfig() function to enable PWR only if necessary for LSE configuration.
    • Corrected CRS interrupt sources.
    • Modified reset of Backup domain only if the RTC Clock source selection is modified from reset value.
    • Added missing HAL IRQHandler and callbacks API for CRS management.
    • Added missing RCC_CFGR_PLLNODIV definition for STM32F030x4/6 devices.
    • Removed HSI48State from structure RCC_OscInitTypeDef when device does not support HSI48.
    • Removed RCC_HSI48_OFF.
    • Removed flag RCC_FLAG_RMV which is write only.
    • Modified AHBPrescTable and APBPrescTable in HAL.
    • Renamed RCC_CRS_SYNCWARM to RCC_CRS_SYNCWARN.
    • Renamed RCC_CRS_TRIMOV to RCC_CRS_TRIMOVF.
  • HAL SPI
    • Updated HAL_SPI_TransmitReceive() function in slave mode to receive correctly the CRC when NSS pulse activated.
    • Added missing __IO in SPI_HandleTypeDef definition.
    • Updated IS_SPI_CRC_POLYNOMIAL macro definition as polynomial value should be odd only.
    • Updated +SPI_2linesTxISR_8BIT() and SPI_2linesTxISR_16BIT() functions: added +return so that SPI_2linesTxISR_8BITCRC() or SPI_2linesTxISR_16BITCRC() +function is called from HAL_SPI_TransmitReceive_IT() when CRC is +activated.
  • HAL TIM
    • Used IS_TIM_HALL_INTERFACE_INSTANCE macro instead of IS_TIM_XOR_INSTANCE macro in
      HAL_TIMEx_HallSensor_xxx() functions.
    • Updated HAL_TIM_ConfigOCrefClear() function to allow TIM_CLEARINPUTSOURCE_OCREFCLR as new ClearInputSource.
  • HAL UART-USART
    • Updated UART Baudrate calculation (UART_DIV_SAMPLING8() and UART_DIV_SAMPLING16() macros).
    • Updated USART_SetConfig() function following UART Baudrate calculation update.
    • Aligned UART-USART Stop Bits with others STM32 series.
    • Renamed IS_UART_WAKEUP_INSTANCE to IS_UART_WAKEUP_FROMSTOP_INSTANCE.
    • Modified UART_Receive_IT() to execute the RX flush request only in case no data is read from RDR.
    • Reviewed UART state machine to avoid cases where UART state is overwritten by UART IRQ.
    • Ensure proper alignment of data pointer in Transmit and Receive functions to avoid toolchain compilation hardfault.
  • HAL USB
    • Corrected double buffer implementation in PCD_SET_EP_DBUF1_CNT() macro.
    • Added missing USB_CNTR_SOFM when setting wInterrupt_Mask global variable used in HAL_PCD_Init.
  • HAL SMARTCARD
    • Aligned SMARTCARD Stop Bits with others STM32 series.
    • Modified SMARTCARD_Receive_IT() to execute the RX flush request only in case no data is read from RDR.
    • Updated SMARTCARD_SetConfig() function following UART Baudrate calculation update.
    • Reviewed SMARTCARD state machine to avoid cases where SMARTCARD state is overwritten by SMARTCARD IRQ.

V1.3.1 +/ 29-January-2016

Main +Changes

  • Maintenance release to fix known defects and +enhancements implementation
  • HAL Generic
    • Updated HAL Driver compliancy with:
      • MISRA C 2004 rule 10.6 ('U' suffix applied to all constants of 'unsigned' type).
      • MISRA C 2004 rule 10.5 (bitwise operators ~ and <<).
      • MISRA C 2004 rule 12.7 (bitwise operations not performed on signed integer types).
    • Updated HAL weak empty callbacks to prevent unused argument compilation warnings.
    • Updated stm32f3xx_hal_msp.c files:
      • Removed reference to MicroXplorer.
    • Updated stm32f3xx_hal_conf.h files:
      • Set HSE_STARTUP_TIMEOUT value to 100ms instead of 5000ms
  • HAL ADC
    • Corrected ADC_CHANNEL_VREFINT enabling in the CCR register.
    • Corrected assert param of nb of discontinuous conversions when discontinuous mode is enabled.
    • Removed Flag EOS in HAL_ADC_GetValue().
  • HAL CAN
    • Corrected missing __HAL_UNLOCK when all Mailboxes are busy.
    • Added ERRI bit clear besides to clearing LEC bits in CAN_ESR register, in case of Error interrupt.
  • HAL CORTEX
    • Removed __HAL_CORTEX_SYSTICKCLK_CONFIG macro, replaced by HAL_SYSTICK_CLKSourceConfig() function.
  • HAL CRC
    • Updated CRC HAL_CRC_Calculate() and HAL_CRC_Accumulate() comments, handling input data pointers that are not * uint32_t.
  • HAL FLASH
    • Added FLASH API HAL_FLASHEx_OBGetUserData() to get the value saved in User data option byte.
    • Aligned Return value of HAL_FLASH_EndOfOperationCallback function (0xFFFFFFF) when process is finished.
  • HAL GPIO
    • Updated GPIO Output Speed literals naming to ensure HAL full compatibility.
    • Added GPIOD support for STM32070x6 devices.
    • Modified ADC poll for event to return timeout instead of error.
  • HAL I2C
    • Corrected wrong management of AF after NACK.
    • Aligned I2C driver with new state machine definition.
    • Corrected interrupt disabling in I2C_SlaveReceive_ISR() function.
    • Modified HAL_I2C_Master_Transmit to handle sending data of size 0.
    • Renamed I2C_CR1_DFN to I2C_CR1_DNF.
  • HAL PCD
    • Updated call to Double Buffering Counter Function.
  • HAL PWR
    • Added do { } while(0) in __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE() multi statement macro.
  • HAL RCC
    • Performed optimizations for HAL_RCC_ClockConfig() function.
    • Corrected invertion in LSE drive capability Bit definition.
    • Performed optimizations for internal oscillators and PLL startup time.
    • Added GPIOD support for STM32070x6 devices.
    • Removed GPIOE support for STM32F030xC devices.
    • Add RCC_USBCLKSOURCE_NONE when HSI48 is not present.
    • Corrected definition for flag RCC_FLAG_V18PWRRST.
    • Added missing macro __HAL_RCC_LSEDRIVE_CONFIG.
    • Aligned naming of macros related to CRS_CFGR register.
    • Corrected __HAL_RCC_CRS_CLEAR_IT()/__HAL_RCC_CRS_CLEAR_FLAG() macros.
    • Removed Bit PLLNODIV for STM32F030x6 devices.
    • Review implementation to automatically enable backup domain.
    • Added RCC_IT_HSI48RDY definition.
    • Renamed __HAL_RCC_MCO_CONFIG() to __HAL_RCC_MCO1_CONFIG().
  • HAL RTC
    • Aligned different HAL_RTC_XXIRQHandler() implementations.
    • Check the behavior of flag WUTWF and corrected update of wakeup counter registers.
    • Added subsecond fration formula in HAL_RTC_GetTime() function.
    • Updated Bits mask literals used in macros definition.
  • HAL TIM
    • Corrected __HAL_TIM_SET_PRESCALER timer prescaler definition.
    • Protected SMCR register of possible overwrite in HAL_TIM_ConfigOCrefClear().
    • Corrected assert checks in HAL_TIM_ConfigClockSource().
  • HAL TSC
    • Updated IO default state management.
  • HAL UART-USART
    • Corrected behavior of HAL_UART_IRQ_Handler() (removed enabling/disabling of ERR IT source).
    • Corrected UART_FLAG_SBKF definition.
    • Corrected values used for max allowed baudrates constant definitions.
    • Removed +USART_CR2_LINEN/USART_CR3_IREN/USART_CR3_SCEN/USART_CR1_UESM bits +definitions for STM32F030x6, STM32F030x8, STM32F070xB, STM32F070x6, +STM32F030xC.
  • HAL WWDG
    • Aligned WWDG registers Bits naming between all families.

V1.3.0 +/ 26-June-2015

Main +Changes

  • Maintenance release to fix known defects and +enhancements implementation
  • Complete HAL API alignment (macro/function renaming)
  • HAL Generic
    • Update HAL drivers to be MISRA/C++ compliant.
    • Initialized handle lock in HAL_PPP_Init().
    • Add SYSCFG define macros to manage FM+ on GPIOs.
    • Use uint32_t instead of uint8_t/uint_16.
  • HAL ADC
    • Update ADC state machine. Missing state in function "HAL_ADCEx_Calibration_Start().
    • Align ADC_SOFTWARE_START literal on STM32L0xx.
    • HAL_ADC_PollForConversion(): update to return error status in case of ADC-DMA mode.
    • HAL_ADC_Init(): ADC resolution must be changed only when ADC is disabled.
    • ADC_ConversionStop(): correct wrong timeout value.
    • HAL_ADC_AnalogWDGConfig(): Add missing assert param.
    • Remove channel for monitoring VBAT power supply pin on F0 Value line devices.
    • Move +sampling time setting into ADC init stucture (keep setting into ADC +channel init stucture with comments of obsolete setting).
    • Move +__HAL_UNLOCK() before peripheral activation because if an interruption +occurs between ADC enable & __HAL_UNLOCK(), IRQ handler will be +executed while HAL still locked.
    • ADC_DMAConvCplt(): Add call to ADC error callback in case of error.
    • Rename local variables for compliancy with coding rules (tmpHALstatus ==> tmp_hal_status).
    • Simplify __HAL_ADC_GET_IT_SOURCE().
    • Add use of POSITION_VAL.
    • Add optimization of ADC stabilization delays.
  • HAL CAN 
    • Add management of CAN Slave start bank in HAL_CAN_ConfigFilter().
    • Unlock the CAN process when communication error occurred.
    • Replace “uint32_t Data[8]” by “uint8_t Data[8]” in structures  CanTxMsgTypeDef and CanRxMsgTypeDef.
  • HAL CEC 
    • Add new API HAL_CEC_GetReceivedFrameSize() to get size of received frame
  • HAL CORTEX 
    • Add new macro IS_NVIC_DEVICE_IRQ() to +check on negative values of IRQn parameter
  • HAL CRC 
    • Add new macros __HAL_CRC_GET_IDR() and __HAL_CRC_SET_IDR().
    • Update __HAL_CRC_SET_IDR macro in resorting to WRITE_REG instead of MODIFY_REG (cycles gain at execution).
  • HAL DAC 
    • HAL_DAC_IRQHandler(): update to check on both DAC_FLAG_DMAUDR1 and +DAC_FLAG_DMAUDR2.
  • HAL DMA
    • Correct __HAL_DMA_GET_IT_SOURCE brief comments.
  • HAL FLASH
    • FLASH_OB_GetRDP(): update function to return the FLASH Read Protection level (OB_RDP_LEVEL_x).
    • FLASH_OB_RDP_LevelConfig(): update function to set the FLASH Read Protection level (OB_RDP_LEVEL_x).
    • Add missing macro __HAL_FLASH_GET_LATENCY.
    • Disable WRP not compliant with other family.
    • Add FLASH_BANK1_END defines.
    • Remove WRP defines for few defines under devices swicthes.
    • Add switch to handle option bits BOOT_SEL & nBOOT1 not present on STM32F030xC & STM32F070x6.
  • HAL GPIO 
    • stm32f0xx_hal_gpio_ex.h: add IR as possible GPIO alternate function 1 for STM32F030x6.
  • HAL I2C
    • HAL_I2C_ER_IRQHandler(): handle NACK test during wait on flag treatment.
  • HAL I2S
    • HAL_I2S_DMAStop(): Correctt DMA Stop function which stops both Rx and Tx channels regardless which one was set-up.
  • HAL IRDA
    • HAL_IRDA_DMAStop(): update comments regarding deletion of LOCK/UNLOCK mechanism.
  • HAL PWR
    • Add macros __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() and __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE.
    • Update HAL_PWR_EnableBkUpAccess() and HAL_PWR_DisableBkUpAccess() comments.
  • HAL RCC
    • Implement workaround to cover RCC limitation regarding Peripheral enable delay.
    • HAL_RCC_OscConfig(): correct test on LSEState.
    • Rework __HAL_RCC_LSE_CONFIG macro to manage correctly LSE_Bypass.
    • Add defines for RCC_System_Clock_Source_Status.
    • Follow specific procedure to enable HSE.
    • Add macros to get the enable or disable status of peripheral clock.
    • HAL_RCCEx_PeriphCLKConfig(): reset backup domain only if RTC clock source has been changed.
    • Add interface HAL_RCCEx_GetPeriphCLKFreq.
  • HAL RTC
    • Add missing RTC_FLAG_INIT in flag list.
    • HAL_RTC_DeInit(): add switch products condition around WakeUp timer registers (WUTWF,WUTR).
    • Remove RTC_FLAG_INIT as currently unused.
  • HAL SMARTCARD
    • Add missing IDLE flag management.
    • Align SMARTCARD_Last_Bit defines.
  • HAL SPI 
    • Fix issue related to missing reset of the Dma Tx callback inside the function HAL_SPI_TransmitReceive_DMA().
      In +that case only RX callback are used and the call of TX callback can +close the communication before the end of the RX processing.
    • SPI_2linesRxISR_8BIT(): +correct issue on RX 2lines with DataSize8bit, even buffer size and CRC +8bit (SPI_RXFIFO_THRESHOLD is not set).
    • Fit bit update add BSY flag check for all the process.
    • Add +__IO (volatile) to the "State" member of the SPI_HandleTypeDef +struct. to missing reset of the Dma Tx callback inside the +function +HAL_SPI_TransmitReceive_DMA().
  • HAL TIM
    • Add __HAL_TIM_SET_CAPTUREPOLARITY, TIM_SET_CAPTUREPOLARITY, TIM_RESET_CAPTUREPOLARITY macros.
  • HAL UART
    • Add macro to control CTS and RTS from the customer applications.
    • UART_DMATransmitCplt(): change implementation to remove WaitOnFlag in ISR.
    • Change DMA TX management to remove WaitOnFlag in ISR.
    • Add DMA circular mode support for the communication peripherals.
    • Add UART NVIC configuration in the HAL_UART_MspInit().
    • Add the UARTx_IRQHandler() in the stm32fxxx_it.c and the prototype in the stm32fxxx_it.h.
    • Modify UART DMA implementation issue (missed clear the TC bit in the SR).
    • Add a OVR flag clear prior resuming DMA RX transfer.
    • HAL_UART_DMAResume(): Remove UART_CheckIdleState() call and replace it by unlock + return(HAL_OK).
    • HAL_UART_DMAStop(): remove LOCK/UNLOCK calls.
    • HAL_UART_DMAStop(): update comments regarding deletion of LOCK/UNLOCK mechanism.
  • HAL USART
    • HAL_USART_IRQHandler(): Correct parameters values of __HAL_USART_CLEAR_IT().
    • Replace xxxITxxx defines by xxxCLEARxxxF defines in __HAL_USART_CLEAR_IT calls.
    • HAL_USART_Init(): update to reach max frequencies (enable oversampling by 8).
    • HAL_USART_DMAPause()/HAL_USART_DMAResume(): add of a OVR flag clear prior resuming DMA RX transfer.
    • HAL_USART_DMAResume(): Remove UART_CheckIdleState() call and replace it by just an Unlock + ret(HAL_OK).
    • HAL_USART_DMAStop(): update comments regarding deletion of LOCK/UNLOCK mechanism.

V1.2.1 +/ 09-January-2015

  • HAL 
    • stm32f0xx_hal.h: add missing define for USART3_RX/TX DMA remap on channel3 & channel2 for STM32F070xB only
  • HAL GPIO
    • stm32f0xx_hal_gpio_ex.h: add I2C1 as possible GPIO alternate function 3 for STM32F070xB
  • HAL RCC
    • stm32f0xx_hal_rcc_ex.h: add missing USART2_CLK_ENABLE/DISABLE() macros for STM32F070x6
  • HAL RTC +
    • stm32f0xx_hal_rtc_ex.h/.c: +Enable RTC periodic Wakeup timer feature on STM32F070xB +& STM32F030xC +
    • stm32f0xx_hal_rtc_ex.c: +remove HAL_RTCEx_Tamper3EventCallback() +API for STM32F070xB +& STM32F030xC, since +there is no TAMPER3 on those products.
    +
  • HAL UART +
    • stm32f0xx_hal_uart_ex.c/.h: +add HAL_RS485Ex_Init() API for STM32F0xx Value +Line devices

V1.2.0 +/ 05-December-2014

Main +Changes

+
  • HAL generic 
    • Add support of new STM32F0 value line devices STM32F070xB/x6 and STM32F030xC.
    • HandleTypeDef.ErrorCode must be typed uint32_t
    • Update HAL drivers to ensure compliancy w/ C++
    • Add some generic defines (__NOINLINE) in stm32f0xx_hal_def.h
    • Case mismatch between #include typo and effective file name generating compiler errors under Linux
    • Correct various issues for documentation generation (group name, doxygen tags, etc..)
    • Missing support of I2C_PAx_FMP of F04xx devices
  • HAL ADC 

    • Improve HAL ADC comments
    • Correct issue observed with ADC start simultaneous commands
    • Remove macro __HAL_ADC_OFR_CHANNEL() since OFRx register is not available on F0 devices.
  • HAL CAN 
    • ErrorCode field is now declared as __IO uint32 instead of enum HAL_CAN_ErrorTypeDef to fix C++ compilation issue
  • HAL CEC 

    • change ErrorCode field declaration from uint32_t  to __IO uint32_t
    • correct CEC state: Ready to Receive state lost upon Transmission end

  • HAL COMP 
    • State field is now declared as uint32_t instead of enum HAL_COMP_StateTypeDef to fix C++ compilation issue
    • change HAL_COMP_GetState() type declaration from HAL_COMP_StateTypeDef to uint32_t to fix C++ compilation issue
  • HAL CRC 

    • Wrong @ref in CRCLength field description for documentation generation 

    • Add support of new STM32F0 value line devices STM32F070xB/x6 and STM32F030xC.
  • HAL DAC 

    • HAL_DAC_Stop_DMA() code clean up

    • Use of internal macro MODIFY_REG() to update CR register
  • HAL DMA 

    • Add support of new STM32F0 value line devices STM32F070xB/x6 and STM32F030xC.
    • DMA channel remap register renamed for compatibility with other STM32 devices.
    • Correct wrong comments in __HAL_DMA_GET_FLAG and __HAL_DMA_CLEAR_FLAG macros description
  • HAL FLASH 
    • Fix in macro IS_OPTIONBYTE(VALUE) when all option_OB are selected
    • ErrorCode field is now declared as uint32 instead of enum FLASH_ErrorTypeDef to fix C++ compilation issue
    • change HAL_FLASH_GetError() type declaration from FLASH_ErrorTypeDef to uint32_t to fix C++ compilation issue
    • Clean the error context to FLASH_ERROR_NONE before starting new Flash operation
    • Put all the clear flags in the FLASH_SetSerrorCode()
    • Stop the programming procedure in case of error detected in HAL_FLASH_Program()
    • Check error before doing new procedure in HAL_FLASH_IRQhandler()
  • HAL GPIO 

    • Add support of new STM32F0 value line devices STM32F070xB/x6 and STM32F030xC.
    • correct Typo in 'How to use this driver' section & update comments
    • Add assert on GPIO PIN in HAL_GPIO_DeInit()
    • Add assert on GPIO AF instance to protect HAL_GPIO_Init() from impossible AF configuration
    • Rename internal macro GET_GPIO_INDEX() into GPIO_GET_INDEX()
    • Reset Interrupt mode registers only in HAL_GPIO_DeInit()
  • HAL I2C
    • Add support of new STM32F0 value line devices STM32F070xB/x6 and STM32F030xC.
    • ErrorCode field is now declared as uint32 instead of enum HAL_I2C_ErrorTypeDef to fix C++ compilation issue
  • HAL I2S 

    • ErrorCode field is now declared as uint32 instead of enum HAL_I2S_ErrorTypeDef to fix C++ compilation issue.
    • Change HAL_I2S_GetError() type declaration from HAL_I2S_ErrorTypeDef to uint32_t to fix C++ compilation issue.
    • Add use of UNUSED(tmpreg) in __HAL_I2S_CLEAR_OVRFLAG() & __HAL_I2S_CLEAR_UDRFLAG to fix Unused variable" warning w/ TrueSTUDIO.
    • Typo in 'I2S HAL driver macros list' section of stm32f0xx_hal_i2s.c
    • Missing doxygen tags for I2S_HandleTypeDef fields description (documentation generation)
  • HAL IRDA 

    • ErrorCode field is now declared as uint32 instead of enum HAL_IRDA_ErrorTypeDef to fix C++ compilation issue
    • Missing doxygen tags for IRDA_HandleTypeDef fields description
  • HAL PWR 

    • Add support of new STM32F0 value line devices STM32F070xB/x6 and STM32F030xC.
    • Add new API to manage SLEEPONEXIT and SEVONPEND bits of SCR register:
  • HAL_PWR_DisableSleepOnExit()
  • HAL_PWR_EnableSleepOnExit()
  • HAL_PWR_EnableSEVOnPend()
  • HAL_PWR_DisableSEVOnPend()
    • Removed useless regulator parameter setting for F0 family in core of HAL_PWR_EnterSLEEPMode()
  • HAL RCC 

    • Add support of new STM32F0 value line devices STM32F070xB/x6 and STM32F030xC.
    • Add a comment in the 'How to use this driver' section to mention the Peripheral enable delay
    • Move __HAL_RCC_USART2_CONFIG() & __HAL_RCC_GET_USART2_SOURCE() from stm32f0xx_hal_rcc.h to stm32f0xx_hal_rcc_ex.h since this feature is not supported on all F0 devices
    • Change HAL_RCCEx_CRSWaitSynchronization() type declaration from RCC_CRSStatusTypeDef to uint32_t to fix C++ compilation issue
  • HAL RTC 

    • Add support of new STM32F0 value line devices STM32F070xB/x6 and STM32F030xC.
    • Enhance @note describing the use of HAL RTC APIs 
  • HAL SMARTCARD
    • ErrorCode field is now declared as uint32 instead of enum HAL_SMARTCARD_ErrorTypeDef to fix C++ compilation issue
  • HAL SMBUS
    • ErrorCode & PreviousState fields are now declared as uint32 instead of enum HAL_SMBUS_ErrorTypeDef & HAL_SMBUS_StateTypeDef to fix C++ compilation issue
    • Change HAL_SMBUS_GetState() type declaration from HAL_SMBUS_StateTypeDef to uint32_t to fix C++ compilation issue
  • HAL SPI 

    • ErrorCode field is now declared as uint32 instead of enum HAL_SPI_ErrorTypeDef to fix C++ compilation issue
    • Add use of UNUSED(tmpreg) in __HAL_SPI_CLEAR_MODFFLAG(), __HAL_SPI_CLEAR_OVRFLAG(), __HAL_SPI_CLEAR_FREFLAG() to fix "Unused variable" warning w/ TrueSTUDIO.
    • Add DMA circular mode support on SPI HAL driver.
    • Internal +fucntion renaming: HAL_SPI_DMATransmitCplt(), +HAL_SPI_DMAReceiveCplt(), HAL_SPI_DMATransmitReceiveCplt() & +HAL_SPI_DMAError() renamed respectively into SPI_DMATransmitCplt(), SPI_DMAReceiveCplt(), SPI_DMATransmitReceiveCplt() & SPI_DMAError().
    • Remove unused HAL_StatusTypeDef SPI_EndRxTxTransaction() prototype
    • uint32_t driver alignment for compatibility with other STM32 devices
    • Add new API HAL_SPI_GetError(), which was missing on STM32F0xx family
  • HAL UART/USART 

    • Add support of new STM32F0 value line devices STM32F070xB/x6 and STM32F030xC.
    • structure UART_WakeUpTypeDef moved to stm32f0xx_hal_uart_ex.h since wakeup feature is not available on all F0 devices.
    • ErrorCode field is now declared as uint32 instead of enum HAL_U(S)ART_ErrorTypeDef to fix C++ compilation issue
    • unused HAL_USART_SetConfig() prototype to be removed from stm32f0xx_hal_usart.h
    • Add missing API HAL_StatusTypeDef HAL_LIN_SendBreak()
    • correct wrong USART_IT_CM value
    • correct issue with Lin mode data length
    • Add new value for Stop bit definition: UART_STOPBITS_1_5
  • HAL USB 

    • Add support of new STM32F0 value line devices STM32F070xB/x6.
    • Wrong comment in HAL_PCD_Dev(Connect/Disconnect) functions description
    • Correct _HAL_PCD_CLEAR_FLAG() macros definition
  • HAL WWDG 

    • Add new macro to manage WWDG IT & correction:

      • __HAL_WWDG_DISABLE_IT()
      • __HAL_WWDG_GET_IT()
      • __HAL_WWDG_GET_IT_SOURCE()

V1.1.0 +/ 03-October-2014

Main +Changes

+
  • HAL generic 
    • general improvement of Doxygen Tags for CHM UM generation
    • Add support of new devices STM32F091xCSTM32F098xx in STM32F0xx HAL drivers
    • minor corrections for Pdf/Chm UM generation
    • Correction for MISRA 
    • [F098xx] Remove PVD IT line wrapper
    • FLAG&IT assert macros to be removed
    • Bad macro name in stm32F0xx_hal.c/.h files
    • uint32_t Alignement in HAL driver
  • HAL update (for STM32F091xC/STM32F098xx)
    • Add new define for HAL IRDA Enveloppe source Selection
    • Add new macro IS_HAL_SYSCFG_IRDA_ENV_SEL()
    • Add new defines for ISR Wrapper (HAL_SYSCFG_ITLINE0, etc..)
    • Add new macro __HAL_GET_PENDING_IT()
    • Add new macro __HAL_SYSCFG_IRDA_ENV_SELECTION()
    • Add new macro __HAL_SYSCFG_GET_IRDA_ENV_SELECTION()
  • HAL COMP 

    • Missing assert param IS_COMP_TRIGGERMODE
  • HAL Cortex 

    • remove Macro not supported by cortex-M0 in stm32f0xx.h

  • HAL DMA 

    • Add new defines for DMAx Channel remapping (DMAx_CHANNELx_RMP)
    • Add new defines for DMAx channels remap bit field definition
    • Add new macros: IS_HAL_DMA1_REMAP(), IS_HAL_DMA2_REMAP()
    • Add new macro: __HAL_DMA_GET_TC_FLAG_INDEX(), that returns specified transfer complete flag index
    • Add new macro: __HAL_DMA_GET_HT_FLAG_INDEX(), that returns specified half transfer complete flag index
    • Add new macro: __HAL_DMA_GET_TE_FLAG_INDEX(), that returns specified transfer error flag index
    • Add new macro: __HAL_DMA_GET_FLAG()
    • Add new macro: __HAL_DMA_CLEAR_FLAG()
    • Add new macro: __HAL_DMA1_REMAP(), __HAL_DMA2_REMAP()
    • Bit definition name error for HAL_DMA1_CH2 remap on STM32F091xC
    • HAL_DMA_PollForTransfer updated
  • HAL GPIO 

    • BSRR regsiter should not be split in BSRRH/BSRRL
    • rework GPIO_GET_SOURCE
    • Add new defines for AF functions selection
  • HAL I2S 

    • Supp ClockSource in Init

  • HAL IRDA 

    • Incorrect definition for IS_IRDA_REQUEST_PARAMETER macro

  • HAL IWDG 

    • Use WRITE_REG instead of SET_BIT

  • HAL PWR 

    • Functions for VDDIO2 management missing in all F09xx, F07xx, F04xx

    • PVD feature need falling/rising Event modes
      • Update defines name PWR_MODE_EVT/PWR_MODE_IT_RISING/PWR_MODE_IT_FALLING/PWR_MODE_IT_RISING_FALLING to PWR_PVD_MODE_NORMAL/PWR_PVD_MODE_IT_RISING/PWR_PVD_MODE_IT_FALLING/PWR_PVD_MODE_IT_RISING_FALLING
      • Add new defines PWR_PVD_MODE_EVENT_RISING, PWR_PVD_MODE_EVENT_FALLING, PWR_PVD_MODE_EVENT_RISING_FALLING
      • Update macro IS_PWR_PVD_MODE()
      • change macro name: __HAL_PWR_PVD_EXTI_ENABLE_IT(), __HAL_PWR_PVD_EXTI_DISABLE_IT(), __HAL_PWR_PVD_EXTI_GENERATE_SWIT(), __HAL_PWR_PVD_EXTI_GET_FLAG(),  __HAL_PWR_PVD_EXTI_CLEAR_FLAG()
      • Add +new macro __HAL_PWR_PVD_EXTI_ENABLE_EVENT(), +__HAL_PWR_PVD_EXTI_DISABLE_EVENT(), +__HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER(), +__HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER()
  • HAL RCC 
    • Defect correction:
      • HAL_RCC_OscConfig: HSERDY has to be checked also in by pass mode
      • STM32F091xC/STM32F098xx
        • New structure RCC_PeriphCLKInitTypeDef
        • Add +defines for RCC new peripheral clock selection: RCC_PERIPHCLK_USART1, +RCC_PERIPHCLK_USART2, RCC_PERIPHCLK_I2C1, RCC_PERIPHCLK_CEC, +RCC_PERIPHCLK_RTC, RCC_PERIPHCLK_USART3
        • Add macro IS_RCC_PERIPHCLK()
        • Add +defines for USART3 clock source selection (RCC_USART3CLKSOURCE_PCLK1, +RCC_USART3CLKSOURCE_SYSCLK, CC_USART3CLKSOURCE_LSE, +CC_USART3CLKSOURCE_HSI
        • Add macro IS_RCC_USART3CLKSOURCE()
        • Add macro __HAL_RCC_GET_USART3_SOURCE()
        • Add macro __HAL_RCC_USART3_CONFIG()
        • add clock enable macros for new UART: __USART5_CLK_ENABLE,  __USART6_CLK_ENABLE, __USART7_CLK_ENABLE, __USART8_CLK_ENABLE
        • add clock disable macros for new UART: __USART5_CLK_DISABLE,  __USART6_CLK_DISABLE, __USART7_CLK_DISABLE, __USART8_CLK_DISABLE
        • add Force reset macros for new UART: __USART5_FORCE_RESET, __USART6_FORCE_RESET, __USART7_FORCE_RESET, __USART8_FORCE_RESET
        • add Release reset macros for new UART: __USART5_RELEASE_RESET, __USART6_RELEASE_RESET, __USART7_RELEASE_RESET, __USART8_RELEASE_RESET 
  • HAL SMARTCARD 

    • change SMARTCARD_AdvFeatureConfig() from exported to static private function
    • STM32F091xC/STM32F098xx:
      • Add new macro __HAL_SMARTCARD_GETCLOCKSOURCE() for USART1, USART2, USART3, USAR
  • HAL SMBUS  

    • change SMARTCARD_AdvFeatureConfig() from exported to static private function
  • HAL SPI 

    • Function HAL_SPI_TransmitReceive muse use SPI_FLAG_RXNE to read CRC

    • Function HAL_SPI_IRQHandler, in case of error the state must be reset to ready
  • HAL TIM 

    • Missed/Unused assert param to be added/removed
    • Trigger interrupt should be activated when working with a slave mode
    • Break interrupt should be activated in HAL_TIMEx_OCN_Start_IT
    • Wrong CCMR register cleared in HAL_TIM_IRQHandler for Input Capture event Channel 3 and 4
    • missing assert in HAL_TIMEx_ConfigBreakDeadTime
    • Add URS_ENABLE/ URS_DISABLE macros
  • HAL UART/USART 

    • Change UART TX-IT implementation to remove WaitOnFlag in ISR
    • STM32F091xC/STM32F098xx:
      • Add new macro __HAL_UART_GETCLOCKSOURCE() for USART1, USART2, USART3, USART4
      • Add new macro __HAL_USART_GETCLOCKSOURCE() for USART1, USART2, USART3, USART4
  • HAL USB 

    • Bad IN/OUT EndPoint parameter array size

  • HAL WWDG 

    • improvements from other families

Defect Correction

+ + + + + + + + + + + + + + + + + + + + + + + + +
+

STM32F0xx_HAL_Driver

+
+

Defect

+
+

PWR

+
+

PVD feature need falling/rising Event modes

+
+

STM32F0xx_HAL_Driver

+
+

Defect

+
+

COMP

+
+

Missing assert param IS_COMP_TRIGGERMODE 

+
+

STM32F0xx_HAL_Driver

+
+

Defect

+
+

RCC

+
+

HAL_RCC_OscConfig: HSERDY has to be checked also in by + pass mode

+
+

V1.0.1 +/ 18-June-2014

Main +Changes

+
  • + + + + + + + +

    HAL generic update

    • Fix flag clear procedure: use atomic write operation "=" instead of ready-modify-write operation "|=" or "&="
    • Fix +on Timeout management, Timeout value set to 0 passed to API +automatically exits the function after checking the flag without any +wait.
    • Add +new macro __HAL_RESET_HANDLE_STATE to reset a given handle state.
  • HAL CEC update

    • Process no more locked during the transmission in interrupt mode. 
  • HAL COMP update

    • Add NonInvertingInput field in the COMP_InitTypeDef structure.
    • Add new defines COMP_NONINVERTINGINPUT_IO1 and COMP_NONINVERTINGINPUT_DAC1SWITCHCLOSED
  • HAL DMA update

    • Fix in HAL_DMA_PollForTransfer() to set error code HAL_DMA_ERROR_TE in case of HAL_ERROR status
  • + + + + + + + +

    HAL I2C update

    • Add +management of NACK event in Master transmitter mode and Slave +transmitter/receiver modes (only in polling mode), in that case the +current transfer is stopped.
  • HAL I2S update

    • I2S clock source change: new define I2S_CLOCK_SYSCLK, remove I2S_CLOCK_PLL
    • Improvement done in I2S transfer/receive processes
  • HAL IRDA update

    • Add new enum typedef IRDA_ClockSourceTypeDef
    • Add new macro __HAL_IRDA_GETCLOCKSOURCE
    • Change in HAL_IRDA_Transmit_IT() to enable IRDA_IT_TXE instead of IRDA_IT_TC.
    • Process no more locked during the transmission in interrupt mode.
  • +

    HAL PCD update

    +
    • +

      Add new macro __HAL_USB_EXTI_GENERATE_SWIT

      +
  • HAL PWR update

    • Fix in HAL_PWR_EnterSTANDBYMode() to not clear Wakeup flag (WUF), which need to be cleared at application level before to call this function
  • HAL RCC update

    • Add USB peripheral and clocking macros for STM32F078xx device.
    • Fix HSI Calibration issue when selected as SYSCLK
  • + + + + + + + +

    HAL SMARTCARD update

    • Change in HAL_SMARTCARD_Transmit_IT() to enable SMARTCARD_IT_TXE instead of SMARTCARD_IT_TC.
    • Process no more locked during the transmission in interrupt mode.
  • HAL SMBUS update

    • Fix Slave acknowledge issue: Slave should ack each bit and so stretch the line till the bit is not ack
  • HAL TIM update

    • Fix macro __HAL_TIM_PRESCALER
  • HAL TSC update

    • Fix define TSC_ACQ_MODE_SYNCHRO
  • + + + + + + + +

    HAL UART update

    • Change in HAL_LIN_Init() parameter BreakDetectLength to uint32_t
    • Change in HAL_UART_Transmit_IT() to enable UART_IT_TXE instead of UART_IT_TC.
    • Process no more locked during the transmission in interrupt mode.
  • HAL USART update

    • Change USART_InitTypeDef fields to uint32_t type
    • Rename __USART_ENABLE and __USART_DISABLE macros to respectively __HAL_USART_ENABLE and __HAL_USART_DISABLE
    • Change in HAL_USART_Transmit_IT() to enable USART_IT_TXE instead of USART_IT_TC.
    • Process no more locked during the transmission in interrupt mode.
    • Change in HAL_USART_TransmitReceive_DMA() to manage DMA half transfer mode

V1.0.0 +/ 20-May-2014

+

Main +Changes

+
  • First official +release of STM32F0xx HAL drivers for STM32F030x4/x6, STM32F030x8, STM32F031x4/x6,  STM32F051x4/x6/x8 STM32F071x8/xB,  STM32F042x4/x6, +STM32F072x8/xB,  STM32F038xx, + STM32F048xxSTM32F058xx and STM32F078xx +devices.

License

+
Redistribution +and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are +met:
+
+
  1. Redistributions +of source code must retain the above copyright notice, this list of +conditions and the following disclaimer.
  2. Redistributions +in binary form must reproduce the above copyright notice, this list of +conditions and the following disclaimer in the +documentation and/or other materials provided with the distribution.
  3. Neither the +name of STMicroelectronics nor the names of its contributors may be +used to endorse or promote products derived from this software without specific prior written permission.
+
+
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ +
+
+

For +complete documentation on STM32 Microcontrollers visit www.st.com/STM32

+
+

+
+
+

 

+
\ No newline at end of file diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/stm32f051x8.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/stm32f051x8.h index a1e1025c14..28ba09660c 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/stm32f051x8.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/stm32f051x8.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f051x8.h * @author MCD Application Team - * @version V2.2.3 - * @date 29-January-2016 + * @version V2.3.0 + * @date 27-May-2016 * @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File. * This file contains all the peripheral register's definitions, bits * definitions and memory mapping for STM32F0xx devices. @@ -674,76 +674,140 @@ typedef struct /******************************************************************************/ /* - * @brief Specific device feature definitions (not present on all devices in the STM32F0 family) + * @brief Specific device feature definitions (not present on all devices in the STM32F0 serie) */ #define ADC_CHANNEL_VBAT_SUPPORT /*!< ADC feature available only on specific devices: ADC internal channel Vbat */ /******************** Bits definition for ADC_ISR register ******************/ -#define ADC_ISR_ADRDY ((uint32_t)0x00000001U) /*!< ADC ready flag */ -#define ADC_ISR_EOSMP ((uint32_t)0x00000002U) /*!< ADC group regular end of sampling flag */ -#define ADC_ISR_EOC ((uint32_t)0x00000004U) /*!< ADC group regular end of unitary conversion flag */ -#define ADC_ISR_EOS ((uint32_t)0x00000008U) /*!< ADC group regular end of sequence conversions flag */ -#define ADC_ISR_OVR ((uint32_t)0x00000010U) /*!< ADC group regular overrun flag */ -#define ADC_ISR_AWD1 ((uint32_t)0x00000080U) /*!< ADC analog watchdog 1 flag */ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1U << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ +#define ADC_ISR_EOSMP_Pos (1U) +#define ADC_ISR_EOSMP_Msk (0x1U << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ +#define ADC_ISR_EOC_Pos (2U) +#define ADC_ISR_EOC_Msk (0x1U << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ +#define ADC_ISR_EOS_Pos (3U) +#define ADC_ISR_EOS_Msk (0x1U << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ +#define ADC_ISR_OVR_Pos (4U) +#define ADC_ISR_OVR_Msk (0x1U << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ +#define ADC_ISR_AWD1_Pos (7U) +#define ADC_ISR_AWD1_Msk (0x1U << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ /* Legacy defines */ #define ADC_ISR_AWD (ADC_ISR_AWD1) #define ADC_ISR_EOSEQ (ADC_ISR_EOS) /******************** Bits definition for ADC_IER register ******************/ -#define ADC_IER_ADRDYIE ((uint32_t)0x00000001U) /*!< ADC ready interrupt */ -#define ADC_IER_EOSMPIE ((uint32_t)0x00000002U) /*!< ADC group regular end of sampling interrupt */ -#define ADC_IER_EOCIE ((uint32_t)0x00000004U) /*!< ADC group regular end of unitary conversion interrupt */ -#define ADC_IER_EOSIE ((uint32_t)0x00000008U) /*!< ADC group regular end of sequence conversions interrupt */ -#define ADC_IER_OVRIE ((uint32_t)0x00000010U) /*!< ADC group regular overrun interrupt */ -#define ADC_IER_AWD1IE ((uint32_t)0x00000080U) /*!< ADC analog watchdog 1 interrupt */ +#define ADC_IER_ADRDYIE_Pos (0U) +#define ADC_IER_ADRDYIE_Msk (0x1U << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ +#define ADC_IER_EOSMPIE_Pos (1U) +#define ADC_IER_EOSMPIE_Msk (0x1U << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ +#define ADC_IER_EOCIE_Pos (2U) +#define ADC_IER_EOCIE_Msk (0x1U << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ +#define ADC_IER_EOSIE_Pos (3U) +#define ADC_IER_EOSIE_Msk (0x1U << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ +#define ADC_IER_OVRIE_Pos (4U) +#define ADC_IER_OVRIE_Msk (0x1U << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ +#define ADC_IER_AWD1IE_Pos (7U) +#define ADC_IER_AWD1IE_Msk (0x1U << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ /* Legacy defines */ #define ADC_IER_AWDIE (ADC_IER_AWD1IE) #define ADC_IER_EOSEQIE (ADC_IER_EOSIE) /******************** Bits definition for ADC_CR register *******************/ -#define ADC_CR_ADEN ((uint32_t)0x00000001U) /*!< ADC enable */ -#define ADC_CR_ADDIS ((uint32_t)0x00000002U) /*!< ADC disable */ -#define ADC_CR_ADSTART ((uint32_t)0x00000004U) /*!< ADC group regular conversion start */ -#define ADC_CR_ADSTP ((uint32_t)0x00000010U) /*!< ADC group regular conversion stop */ -#define ADC_CR_ADCAL ((uint32_t)0x80000000U) /*!< ADC calibration */ +#define ADC_CR_ADEN_Pos (0U) +#define ADC_CR_ADEN_Msk (0x1U << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ +#define ADC_CR_ADDIS_Pos (1U) +#define ADC_CR_ADDIS_Msk (0x1U << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ +#define ADC_CR_ADSTART_Pos (2U) +#define ADC_CR_ADSTART_Msk (0x1U << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ +#define ADC_CR_ADSTP_Pos (4U) +#define ADC_CR_ADSTP_Msk (0x1U << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ +#define ADC_CR_ADCAL_Pos (31U) +#define ADC_CR_ADCAL_Msk (0x1U << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ /******************* Bits definition for ADC_CFGR1 register *****************/ -#define ADC_CFGR1_DMAEN ((uint32_t)0x00000001U) /*!< ADC DMA transfer enable */ -#define ADC_CFGR1_DMACFG ((uint32_t)0x00000002U) /*!< ADC DMA transfer configuration */ -#define ADC_CFGR1_SCANDIR ((uint32_t)0x00000004U) /*!< ADC group regular sequencer scan direction */ +#define ADC_CFGR1_DMAEN_Pos (0U) +#define ADC_CFGR1_DMAEN_Msk (0x1U << ADC_CFGR1_DMAEN_Pos) /*!< 0x00000001 */ +#define ADC_CFGR1_DMAEN ADC_CFGR1_DMAEN_Msk /*!< ADC DMA transfer enable */ +#define ADC_CFGR1_DMACFG_Pos (1U) +#define ADC_CFGR1_DMACFG_Msk (0x1U << ADC_CFGR1_DMACFG_Pos) /*!< 0x00000002 */ +#define ADC_CFGR1_DMACFG ADC_CFGR1_DMACFG_Msk /*!< ADC DMA transfer configuration */ +#define ADC_CFGR1_SCANDIR_Pos (2U) +#define ADC_CFGR1_SCANDIR_Msk (0x1U << ADC_CFGR1_SCANDIR_Pos) /*!< 0x00000004 */ +#define ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR_Msk /*!< ADC group regular sequencer scan direction */ -#define ADC_CFGR1_RES ((uint32_t)0x00000018U) /*!< ADC data resolution */ -#define ADC_CFGR1_RES_0 ((uint32_t)0x00000008U) /*!< bit 0 */ -#define ADC_CFGR1_RES_1 ((uint32_t)0x00000010U) /*!< bit 1 */ +#define ADC_CFGR1_RES_Pos (3U) +#define ADC_CFGR1_RES_Msk (0x3U << ADC_CFGR1_RES_Pos) /*!< 0x00000018 */ +#define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< ADC data resolution */ +#define ADC_CFGR1_RES_0 (0x1U << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */ +#define ADC_CFGR1_RES_1 (0x2U << ADC_CFGR1_RES_Pos) /*!< 0x00000010 */ -#define ADC_CFGR1_ALIGN ((uint32_t)0x00000020U) /*!< ADC data alignement */ +#define ADC_CFGR1_ALIGN_Pos (5U) +#define ADC_CFGR1_ALIGN_Msk (0x1U << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */ +#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignement */ -#define ADC_CFGR1_EXTSEL ((uint32_t)0x000001C0U) /*!< ADC group regular external trigger source */ -#define ADC_CFGR1_EXTSEL_0 ((uint32_t)0x00000040U) /*!< bit 0 */ -#define ADC_CFGR1_EXTSEL_1 ((uint32_t)0x00000080U) /*!< bit 1 */ -#define ADC_CFGR1_EXTSEL_2 ((uint32_t)0x00000100U) /*!< bit 2 */ +#define ADC_CFGR1_EXTSEL_Pos (6U) +#define ADC_CFGR1_EXTSEL_Msk (0x7U << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */ +#define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< ADC group regular external trigger source */ +#define ADC_CFGR1_EXTSEL_0 (0x1U << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR1_EXTSEL_1 (0x2U << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR1_EXTSEL_2 (0x4U << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */ -#define ADC_CFGR1_EXTEN ((uint32_t)0x00000C00U) /*!< ADC group regular external trigger polarity */ -#define ADC_CFGR1_EXTEN_0 ((uint32_t)0x00000400U) /*!< bit 0 */ -#define ADC_CFGR1_EXTEN_1 ((uint32_t)0x00000800U) /*!< bit 1 */ +#define ADC_CFGR1_EXTEN_Pos (10U) +#define ADC_CFGR1_EXTEN_Msk (0x3U << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< ADC group regular external trigger polarity */ +#define ADC_CFGR1_EXTEN_0 (0x1U << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR1_EXTEN_1 (0x2U << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */ -#define ADC_CFGR1_OVRMOD ((uint32_t)0x00001000U) /*!< ADC group regular overrun configuration */ -#define ADC_CFGR1_CONT ((uint32_t)0x00002000U) /*!< ADC group regular continuous conversion mode */ -#define ADC_CFGR1_WAIT ((uint32_t)0x00004000U) /*!< ADC low power auto wait */ -#define ADC_CFGR1_AUTOFF ((uint32_t)0x00008000U) /*!< ADC low power auto power off */ -#define ADC_CFGR1_DISCEN ((uint32_t)0x00010000U) /*!< ADC group regular sequencer discontinuous mode */ +#define ADC_CFGR1_OVRMOD_Pos (12U) +#define ADC_CFGR1_OVRMOD_Msk (0x1U << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< ADC group regular overrun configuration */ +#define ADC_CFGR1_CONT_Pos (13U) +#define ADC_CFGR1_CONT_Msk (0x1U << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< ADC group regular continuous conversion mode */ +#define ADC_CFGR1_WAIT_Pos (14U) +#define ADC_CFGR1_WAIT_Msk (0x1U << ADC_CFGR1_WAIT_Pos) /*!< 0x00004000 */ +#define ADC_CFGR1_WAIT ADC_CFGR1_WAIT_Msk /*!< ADC low power auto wait */ +#define ADC_CFGR1_AUTOFF_Pos (15U) +#define ADC_CFGR1_AUTOFF_Msk (0x1U << ADC_CFGR1_AUTOFF_Pos) /*!< 0x00008000 */ +#define ADC_CFGR1_AUTOFF ADC_CFGR1_AUTOFF_Msk /*!< ADC low power auto power off */ +#define ADC_CFGR1_DISCEN_Pos (16U) +#define ADC_CFGR1_DISCEN_Msk (0x1U << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ -#define ADC_CFGR1_AWD1SGL ((uint32_t)0x00400000U) /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ -#define ADC_CFGR1_AWD1EN ((uint32_t)0x00800000U) /*!< ADC analog watchdog 1 enable on scope ADC group regular */ +#define ADC_CFGR1_AWD1SGL_Pos (22U) +#define ADC_CFGR1_AWD1SGL_Msk (0x1U << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR1_AWD1SGL ADC_CFGR1_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ +#define ADC_CFGR1_AWD1EN_Pos (23U) +#define ADC_CFGR1_AWD1EN_Msk (0x1U << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR1_AWD1EN ADC_CFGR1_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ -#define ADC_CFGR1_AWD1CH ((uint32_t)0x7C000000U) /*!< ADC analog watchdog 1 monitored channel selection */ -#define ADC_CFGR1_AWD1CH_0 ((uint32_t)0x04000000U) /*!< bit 0 */ -#define ADC_CFGR1_AWD1CH_1 ((uint32_t)0x08000000U) /*!< bit 1 */ -#define ADC_CFGR1_AWD1CH_2 ((uint32_t)0x10000000U) /*!< bit 2 */ -#define ADC_CFGR1_AWD1CH_3 ((uint32_t)0x20000000U) /*!< bit 3 */ -#define ADC_CFGR1_AWD1CH_4 ((uint32_t)0x40000000U) /*!< bit 4 */ +#define ADC_CFGR1_AWD1CH_Pos (26U) +#define ADC_CFGR1_AWD1CH_Msk (0x1FU << ADC_CFGR1_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR1_AWD1CH ADC_CFGR1_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ +#define ADC_CFGR1_AWD1CH_0 (0x01U << ADC_CFGR1_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR1_AWD1CH_1 (0x02U << ADC_CFGR1_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR1_AWD1CH_2 (0x04U << ADC_CFGR1_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR1_AWD1CH_3 (0x08U << ADC_CFGR1_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR1_AWD1CH_4 (0x10U << ADC_CFGR1_AWD1CH_Pos) /*!< 0x40000000 */ /* Legacy defines */ #define ADC_CFGR1_AUTDLY (ADC_CFGR1_WAIT) @@ -757,19 +821,23 @@ typedef struct #define ADC_CFGR1_AWDCH_4 (ADC_CFGR1_AWD1CH_4) /******************* Bits definition for ADC_CFGR2 register *****************/ -#define ADC_CFGR2_CKMODE ((uint32_t)0xC0000000U) /*!< ADC clock source and prescaler (prescaler only for clock source synchronous) */ -#define ADC_CFGR2_CKMODE_1 ((uint32_t)0x80000000U) /*!< bit 1 */ -#define ADC_CFGR2_CKMODE_0 ((uint32_t)0x40000000U) /*!< bit 0 */ +#define ADC_CFGR2_CKMODE_Pos (30U) +#define ADC_CFGR2_CKMODE_Msk (0x3U << ADC_CFGR2_CKMODE_Pos) /*!< 0xC0000000 */ +#define ADC_CFGR2_CKMODE ADC_CFGR2_CKMODE_Msk /*!< ADC clock source and prescaler (prescaler only for clock source synchronous) */ +#define ADC_CFGR2_CKMODE_1 (0x2U << ADC_CFGR2_CKMODE_Pos) /*!< 0x80000000 */ +#define ADC_CFGR2_CKMODE_0 (0x1U << ADC_CFGR2_CKMODE_Pos) /*!< 0x40000000 */ /* Legacy defines */ #define ADC_CFGR2_JITOFFDIV4 (ADC_CFGR2_CKMODE_1) /*!< ADC clocked by PCLK div4 */ #define ADC_CFGR2_JITOFFDIV2 (ADC_CFGR2_CKMODE_0) /*!< ADC clocked by PCLK div2 */ /****************** Bit definition for ADC_SMPR register ********************/ -#define ADC_SMPR_SMP ((uint32_t)0x00000007U) /*!< ADC group of channels sampling time 2 */ -#define ADC_SMPR_SMP_0 ((uint32_t)0x00000001U) /*!< bit 0 */ -#define ADC_SMPR_SMP_1 ((uint32_t)0x00000002U) /*!< bit 1 */ -#define ADC_SMPR_SMP_2 ((uint32_t)0x00000004U) /*!< bit 2 */ +#define ADC_SMPR_SMP_Pos (0U) +#define ADC_SMPR_SMP_Msk (0x7U << ADC_SMPR_SMP_Pos) /*!< 0x00000007 */ +#define ADC_SMPR_SMP ADC_SMPR_SMP_Msk /*!< ADC group of channels sampling time 2 */ +#define ADC_SMPR_SMP_0 (0x1U << ADC_SMPR_SMP_Pos) /*!< 0x00000001 */ +#define ADC_SMPR_SMP_1 (0x2U << ADC_SMPR_SMP_Pos) /*!< 0x00000002 */ +#define ADC_SMPR_SMP_2 (0x4U << ADC_SMPR_SMP_Pos) /*!< 0x00000004 */ /* Legacy defines */ #define ADC_SMPR1_SMPR (ADC_SMPR_SMP) /*!< SMP[2:0] bits (Sampling time selection) */ @@ -778,33 +846,37 @@ typedef struct #define ADC_SMPR1_SMPR_2 (ADC_SMPR_SMP_2) /*!< bit 2 */ /******************* Bit definition for ADC_TR register ********************/ -#define ADC_TR1_LT1 ((uint32_t)0x00000FFFU) /*!< ADC analog watchdog 1 threshold low */ -#define ADC_TR1_LT1_0 ((uint32_t)0x00000001U) /*!< bit 0 */ -#define ADC_TR1_LT1_1 ((uint32_t)0x00000002U) /*!< bit 1 */ -#define ADC_TR1_LT1_2 ((uint32_t)0x00000004U) /*!< bit 2 */ -#define ADC_TR1_LT1_3 ((uint32_t)0x00000008U) /*!< bit 3 */ -#define ADC_TR1_LT1_4 ((uint32_t)0x00000010U) /*!< bit 4 */ -#define ADC_TR1_LT1_5 ((uint32_t)0x00000020U) /*!< bit 5 */ -#define ADC_TR1_LT1_6 ((uint32_t)0x00000040U) /*!< bit 6 */ -#define ADC_TR1_LT1_7 ((uint32_t)0x00000080U) /*!< bit 7 */ -#define ADC_TR1_LT1_8 ((uint32_t)0x00000100U) /*!< bit 8 */ -#define ADC_TR1_LT1_9 ((uint32_t)0x00000200U) /*!< bit 9 */ -#define ADC_TR1_LT1_10 ((uint32_t)0x00000400U) /*!< bit 10 */ -#define ADC_TR1_LT1_11 ((uint32_t)0x00000800U) /*!< bit 11 */ +#define ADC_TR1_LT1_Pos (0U) +#define ADC_TR1_LT1_Msk (0xFFFU << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */ +#define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ +#define ADC_TR1_LT1_0 (0x001U << ADC_TR1_LT1_Pos) /*!< 0x00000001 */ +#define ADC_TR1_LT1_1 (0x002U << ADC_TR1_LT1_Pos) /*!< 0x00000002 */ +#define ADC_TR1_LT1_2 (0x004U << ADC_TR1_LT1_Pos) /*!< 0x00000004 */ +#define ADC_TR1_LT1_3 (0x008U << ADC_TR1_LT1_Pos) /*!< 0x00000008 */ +#define ADC_TR1_LT1_4 (0x010U << ADC_TR1_LT1_Pos) /*!< 0x00000010 */ +#define ADC_TR1_LT1_5 (0x020U << ADC_TR1_LT1_Pos) /*!< 0x00000020 */ +#define ADC_TR1_LT1_6 (0x040U << ADC_TR1_LT1_Pos) /*!< 0x00000040 */ +#define ADC_TR1_LT1_7 (0x080U << ADC_TR1_LT1_Pos) /*!< 0x00000080 */ +#define ADC_TR1_LT1_8 (0x100U << ADC_TR1_LT1_Pos) /*!< 0x00000100 */ +#define ADC_TR1_LT1_9 (0x200U << ADC_TR1_LT1_Pos) /*!< 0x00000200 */ +#define ADC_TR1_LT1_10 (0x400U << ADC_TR1_LT1_Pos) /*!< 0x00000400 */ +#define ADC_TR1_LT1_11 (0x800U << ADC_TR1_LT1_Pos) /*!< 0x00000800 */ -#define ADC_TR1_HT1 ((uint32_t)0x0FFF0000U) /*!< ADC Analog watchdog 1 threshold high */ -#define ADC_TR1_HT1_0 ((uint32_t)0x00010000U) /*!< bit 0 */ -#define ADC_TR1_HT1_1 ((uint32_t)0x00020000U) /*!< bit 1 */ -#define ADC_TR1_HT1_2 ((uint32_t)0x00040000U) /*!< bit 2 */ -#define ADC_TR1_HT1_3 ((uint32_t)0x00080000U) /*!< bit 3 */ -#define ADC_TR1_HT1_4 ((uint32_t)0x00100000U) /*!< bit 4 */ -#define ADC_TR1_HT1_5 ((uint32_t)0x00200000U) /*!< bit 5 */ -#define ADC_TR1_HT1_6 ((uint32_t)0x00400000U) /*!< bit 6 */ -#define ADC_TR1_HT1_7 ((uint32_t)0x00800000U) /*!< bit 7 */ -#define ADC_TR1_HT1_8 ((uint32_t)0x01000000U) /*!< bit 8 */ -#define ADC_TR1_HT1_9 ((uint32_t)0x02000000U) /*!< bit 9 */ -#define ADC_TR1_HT1_10 ((uint32_t)0x04000000U) /*!< bit 10 */ -#define ADC_TR1_HT1_11 ((uint32_t)0x08000000U) /*!< bit 11 */ +#define ADC_TR1_HT1_Pos (16U) +#define ADC_TR1_HT1_Msk (0xFFFU << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */ +#define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */ +#define ADC_TR1_HT1_0 (0x001U << ADC_TR1_HT1_Pos) /*!< 0x00010000 */ +#define ADC_TR1_HT1_1 (0x002U << ADC_TR1_HT1_Pos) /*!< 0x00020000 */ +#define ADC_TR1_HT1_2 (0x004U << ADC_TR1_HT1_Pos) /*!< 0x00040000 */ +#define ADC_TR1_HT1_3 (0x008U << ADC_TR1_HT1_Pos) /*!< 0x00080000 */ +#define ADC_TR1_HT1_4 (0x010U << ADC_TR1_HT1_Pos) /*!< 0x00100000 */ +#define ADC_TR1_HT1_5 (0x020U << ADC_TR1_HT1_Pos) /*!< 0x00200000 */ +#define ADC_TR1_HT1_6 (0x040U << ADC_TR1_HT1_Pos) /*!< 0x00400000 */ +#define ADC_TR1_HT1_7 (0x080U << ADC_TR1_HT1_Pos) /*!< 0x00800000 */ +#define ADC_TR1_HT1_8 (0x100U << ADC_TR1_HT1_Pos) /*!< 0x01000000 */ +#define ADC_TR1_HT1_9 (0x200U << ADC_TR1_HT1_Pos) /*!< 0x02000000 */ +#define ADC_TR1_HT1_10 (0x400U << ADC_TR1_HT1_Pos) /*!< 0x04000000 */ +#define ADC_TR1_HT1_11 (0x800U << ADC_TR1_HT1_Pos) /*!< 0x08000000 */ /* Legacy defines */ #define ADC_TR_HT (ADC_TR1_HT1) @@ -813,52 +885,100 @@ typedef struct #define ADC_LTR_LT (ADC_TR1_LT1) /****************** Bit definition for ADC_CHSELR register ******************/ -#define ADC_CHSELR_CHSEL ((uint32_t)0x0007FFFFU) /*!< ADC group regular sequencer channels, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL18 ((uint32_t)0x00040000U) /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL17 ((uint32_t)0x00020000U) /*!< ADC group regular sequencer channel 17, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL16 ((uint32_t)0x00010000U) /*!< ADC group regular sequencer channel 16, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL15 ((uint32_t)0x00008000U) /*!< ADC group regular sequencer channel 15, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL14 ((uint32_t)0x00004000U) /*!< ADC group regular sequencer channel 14, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL13 ((uint32_t)0x00002000U) /*!< ADC group regular sequencer channel 13, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL12 ((uint32_t)0x00001000U) /*!< ADC group regular sequencer channel 12, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL11 ((uint32_t)0x00000800U) /*!< ADC group regular sequencer channel 11, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL10 ((uint32_t)0x00000400U) /*!< ADC group regular sequencer channel 10, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL9 ((uint32_t)0x00000200U) /*!< ADC group regular sequencer channel 9, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL8 ((uint32_t)0x00000100U) /*!< ADC group regular sequencer channel 8, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL7 ((uint32_t)0x00000080U) /*!< ADC group regular sequencer channel 7, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL6 ((uint32_t)0x00000040U) /*!< ADC group regular sequencer channel 6, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL5 ((uint32_t)0x00000020U) /*!< ADC group regular sequencer channel 5, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL4 ((uint32_t)0x00000010U) /*!< ADC group regular sequencer channel 4, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL3 ((uint32_t)0x00000008U) /*!< ADC group regular sequencer channel 3, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL2 ((uint32_t)0x00000004U) /*!< ADC group regular sequencer channel 2, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL1 ((uint32_t)0x00000002U) /*!< ADC group regular sequencer channel 1, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL0 ((uint32_t)0x00000001U) /*!< ADC group regular sequencer channel 0, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL_Pos (0U) +#define ADC_CHSELR_CHSEL_Msk (0x7FFFFU << ADC_CHSELR_CHSEL_Pos) /*!< 0x0007FFFF */ +#define ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk /*!< ADC group regular sequencer channels, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL18_Pos (18U) +#define ADC_CHSELR_CHSEL18_Msk (0x1U << ADC_CHSELR_CHSEL18_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL18 ADC_CHSELR_CHSEL18_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL17_Pos (17U) +#define ADC_CHSELR_CHSEL17_Msk (0x1U << ADC_CHSELR_CHSEL17_Pos) /*!< 0x00020000 */ +#define ADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk /*!< ADC group regular sequencer channel 17, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL16_Pos (16U) +#define ADC_CHSELR_CHSEL16_Msk (0x1U << ADC_CHSELR_CHSEL16_Pos) /*!< 0x00010000 */ +#define ADC_CHSELR_CHSEL16 ADC_CHSELR_CHSEL16_Msk /*!< ADC group regular sequencer channel 16, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL15_Pos (15U) +#define ADC_CHSELR_CHSEL15_Msk (0x1U << ADC_CHSELR_CHSEL15_Pos) /*!< 0x00008000 */ +#define ADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk /*!< ADC group regular sequencer channel 15, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL14_Pos (14U) +#define ADC_CHSELR_CHSEL14_Msk (0x1U << ADC_CHSELR_CHSEL14_Pos) /*!< 0x00004000 */ +#define ADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk /*!< ADC group regular sequencer channel 14, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL13_Pos (13U) +#define ADC_CHSELR_CHSEL13_Msk (0x1U << ADC_CHSELR_CHSEL13_Pos) /*!< 0x00002000 */ +#define ADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk /*!< ADC group regular sequencer channel 13, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL12_Pos (12U) +#define ADC_CHSELR_CHSEL12_Msk (0x1U << ADC_CHSELR_CHSEL12_Pos) /*!< 0x00001000 */ +#define ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk /*!< ADC group regular sequencer channel 12, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL11_Pos (11U) +#define ADC_CHSELR_CHSEL11_Msk (0x1U << ADC_CHSELR_CHSEL11_Pos) /*!< 0x00000800 */ +#define ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk /*!< ADC group regular sequencer channel 11, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL10_Pos (10U) +#define ADC_CHSELR_CHSEL10_Msk (0x1U << ADC_CHSELR_CHSEL10_Pos) /*!< 0x00000400 */ +#define ADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk /*!< ADC group regular sequencer channel 10, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL9_Pos (9U) +#define ADC_CHSELR_CHSEL9_Msk (0x1U << ADC_CHSELR_CHSEL9_Pos) /*!< 0x00000200 */ +#define ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk /*!< ADC group regular sequencer channel 9, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL8_Pos (8U) +#define ADC_CHSELR_CHSEL8_Msk (0x1U << ADC_CHSELR_CHSEL8_Pos) /*!< 0x00000100 */ +#define ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk /*!< ADC group regular sequencer channel 8, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL7_Pos (7U) +#define ADC_CHSELR_CHSEL7_Msk (0x1U << ADC_CHSELR_CHSEL7_Pos) /*!< 0x00000080 */ +#define ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk /*!< ADC group regular sequencer channel 7, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL6_Pos (6U) +#define ADC_CHSELR_CHSEL6_Msk (0x1U << ADC_CHSELR_CHSEL6_Pos) /*!< 0x00000040 */ +#define ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk /*!< ADC group regular sequencer channel 6, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL5_Pos (5U) +#define ADC_CHSELR_CHSEL5_Msk (0x1U << ADC_CHSELR_CHSEL5_Pos) /*!< 0x00000020 */ +#define ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk /*!< ADC group regular sequencer channel 5, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL4_Pos (4U) +#define ADC_CHSELR_CHSEL4_Msk (0x1U << ADC_CHSELR_CHSEL4_Pos) /*!< 0x00000010 */ +#define ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk /*!< ADC group regular sequencer channel 4, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL3_Pos (3U) +#define ADC_CHSELR_CHSEL3_Msk (0x1U << ADC_CHSELR_CHSEL3_Pos) /*!< 0x00000008 */ +#define ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk /*!< ADC group regular sequencer channel 3, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL2_Pos (2U) +#define ADC_CHSELR_CHSEL2_Msk (0x1U << ADC_CHSELR_CHSEL2_Pos) /*!< 0x00000004 */ +#define ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk /*!< ADC group regular sequencer channel 2, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL1_Pos (1U) +#define ADC_CHSELR_CHSEL1_Msk (0x1U << ADC_CHSELR_CHSEL1_Pos) /*!< 0x00000002 */ +#define ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk /*!< ADC group regular sequencer channel 1, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL0_Pos (0U) +#define ADC_CHSELR_CHSEL0_Msk (0x1U << ADC_CHSELR_CHSEL0_Pos) /*!< 0x00000001 */ +#define ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk /*!< ADC group regular sequencer channel 0, available when ADC_CFGR1_CHSELRMOD is reset */ /******************** Bit definition for ADC_DR register ********************/ -#define ADC_DR_DATA ((uint32_t)0x0000FFFFU) /*!< ADC group regular conversion data */ -#define ADC_DR_DATA_0 ((uint32_t)0x00000001U) /*!< bit 0 */ -#define ADC_DR_DATA_1 ((uint32_t)0x00000002U) /*!< bit 1 */ -#define ADC_DR_DATA_2 ((uint32_t)0x00000004U) /*!< bit 2 */ -#define ADC_DR_DATA_3 ((uint32_t)0x00000008U) /*!< bit 3 */ -#define ADC_DR_DATA_4 ((uint32_t)0x00000010U) /*!< bit 4 */ -#define ADC_DR_DATA_5 ((uint32_t)0x00000020U) /*!< bit 5 */ -#define ADC_DR_DATA_6 ((uint32_t)0x00000040U) /*!< bit 6 */ -#define ADC_DR_DATA_7 ((uint32_t)0x00000080U) /*!< bit 7 */ -#define ADC_DR_DATA_8 ((uint32_t)0x00000100U) /*!< bit 8 */ -#define ADC_DR_DATA_9 ((uint32_t)0x00000200U) /*!< bit 9 */ -#define ADC_DR_DATA_10 ((uint32_t)0x00000400U) /*!< bit 10 */ -#define ADC_DR_DATA_11 ((uint32_t)0x00000800U) /*!< bit 11 */ -#define ADC_DR_DATA_12 ((uint32_t)0x00001000U) /*!< bit 12 */ -#define ADC_DR_DATA_13 ((uint32_t)0x00002000U) /*!< bit 13 */ -#define ADC_DR_DATA_14 ((uint32_t)0x00004000U) /*!< bit 14 */ -#define ADC_DR_DATA_15 ((uint32_t)0x00008000U) /*!< bit 15 */ +#define ADC_DR_DATA_Pos (0U) +#define ADC_DR_DATA_Msk (0xFFFFU << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */ +#define ADC_DR_DATA ADC_DR_DATA_Msk /*!< ADC group regular conversion data */ +#define ADC_DR_DATA_0 (0x0001U << ADC_DR_DATA_Pos) /*!< 0x00000001 */ +#define ADC_DR_DATA_1 (0x0002U << ADC_DR_DATA_Pos) /*!< 0x00000002 */ +#define ADC_DR_DATA_2 (0x0004U << ADC_DR_DATA_Pos) /*!< 0x00000004 */ +#define ADC_DR_DATA_3 (0x0008U << ADC_DR_DATA_Pos) /*!< 0x00000008 */ +#define ADC_DR_DATA_4 (0x0010U << ADC_DR_DATA_Pos) /*!< 0x00000010 */ +#define ADC_DR_DATA_5 (0x0020U << ADC_DR_DATA_Pos) /*!< 0x00000020 */ +#define ADC_DR_DATA_6 (0x0040U << ADC_DR_DATA_Pos) /*!< 0x00000040 */ +#define ADC_DR_DATA_7 (0x0080U << ADC_DR_DATA_Pos) /*!< 0x00000080 */ +#define ADC_DR_DATA_8 (0x0100U << ADC_DR_DATA_Pos) /*!< 0x00000100 */ +#define ADC_DR_DATA_9 (0x0200U << ADC_DR_DATA_Pos) /*!< 0x00000200 */ +#define ADC_DR_DATA_10 (0x0400U << ADC_DR_DATA_Pos) /*!< 0x00000400 */ +#define ADC_DR_DATA_11 (0x0800U << ADC_DR_DATA_Pos) /*!< 0x00000800 */ +#define ADC_DR_DATA_12 (0x1000U << ADC_DR_DATA_Pos) /*!< 0x00001000 */ +#define ADC_DR_DATA_13 (0x2000U << ADC_DR_DATA_Pos) /*!< 0x00002000 */ +#define ADC_DR_DATA_14 (0x4000U << ADC_DR_DATA_Pos) /*!< 0x00004000 */ +#define ADC_DR_DATA_15 (0x8000U << ADC_DR_DATA_Pos) /*!< 0x00008000 */ /************************* ADC Common registers *****************************/ /******************* Bit definition for ADC_CCR register ********************/ -#define ADC_CCR_VREFEN ((uint32_t)0x00400000U) /*!< ADC internal path to VrefInt enable */ -#define ADC_CCR_TSEN ((uint32_t)0x00800000U) /*!< ADC internal path to temperature sensor enable */ +#define ADC_CCR_VREFEN_Pos (22U) +#define ADC_CCR_VREFEN_Msk (0x1U << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ +#define ADC_CCR_TSEN_Pos (23U) +#define ADC_CCR_TSEN_Msk (0x1U << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */ -#define ADC_CCR_VBATEN ((uint32_t)0x01000000U) /*!< ADC internal path to battery voltage enable */ +#define ADC_CCR_VBATEN_Pos (24U) +#define ADC_CCR_VBATEN_Msk (0x1U << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ +#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */ /******************************************************************************/ /* */ @@ -867,56 +987,136 @@ typedef struct /******************************************************************************/ /******************* Bit definition for CEC_CR register *********************/ -#define CEC_CR_CECEN ((uint32_t)0x00000001U) /*!< CEC Enable */ -#define CEC_CR_TXSOM ((uint32_t)0x00000002U) /*!< CEC Tx Start Of Message */ -#define CEC_CR_TXEOM ((uint32_t)0x00000004U) /*!< CEC Tx End Of Message */ +#define CEC_CR_CECEN_Pos (0U) +#define CEC_CR_CECEN_Msk (0x1U << CEC_CR_CECEN_Pos) /*!< 0x00000001 */ +#define CEC_CR_CECEN CEC_CR_CECEN_Msk /*!< CEC Enable */ +#define CEC_CR_TXSOM_Pos (1U) +#define CEC_CR_TXSOM_Msk (0x1U << CEC_CR_TXSOM_Pos) /*!< 0x00000002 */ +#define CEC_CR_TXSOM CEC_CR_TXSOM_Msk /*!< CEC Tx Start Of Message */ +#define CEC_CR_TXEOM_Pos (2U) +#define CEC_CR_TXEOM_Msk (0x1U << CEC_CR_TXEOM_Pos) /*!< 0x00000004 */ +#define CEC_CR_TXEOM CEC_CR_TXEOM_Msk /*!< CEC Tx End Of Message */ /******************* Bit definition for CEC_CFGR register *******************/ -#define CEC_CFGR_SFT ((uint32_t)0x00000007U) /*!< CEC Signal Free Time */ -#define CEC_CFGR_RXTOL ((uint32_t)0x00000008U) /*!< CEC Tolerance */ -#define CEC_CFGR_BRESTP ((uint32_t)0x00000010U) /*!< CEC Rx Stop */ -#define CEC_CFGR_BREGEN ((uint32_t)0x00000020U) /*!< CEC Bit Rising Error generation */ -#define CEC_CFGR_LBPEGEN ((uint32_t)0x00000040U) /*!< CEC Long Bit Period Error gener. */ -#define CEC_CFGR_BRDNOGEN ((uint32_t)0x00000080U) /*!< CEC Broadcast No Error generation */ -#define CEC_CFGR_SFTOPT ((uint32_t)0x00000100U) /*!< CEC Signal Free Time optional */ -#define CEC_CFGR_OAR ((uint32_t)0x7FFF0000U) /*!< CEC Own Address */ -#define CEC_CFGR_LSTN ((uint32_t)0x80000000U) /*!< CEC Listen mode */ +#define CEC_CFGR_SFT_Pos (0U) +#define CEC_CFGR_SFT_Msk (0x7U << CEC_CFGR_SFT_Pos) /*!< 0x00000007 */ +#define CEC_CFGR_SFT CEC_CFGR_SFT_Msk /*!< CEC Signal Free Time */ +#define CEC_CFGR_RXTOL_Pos (3U) +#define CEC_CFGR_RXTOL_Msk (0x1U << CEC_CFGR_RXTOL_Pos) /*!< 0x00000008 */ +#define CEC_CFGR_RXTOL CEC_CFGR_RXTOL_Msk /*!< CEC Tolerance */ +#define CEC_CFGR_BRESTP_Pos (4U) +#define CEC_CFGR_BRESTP_Msk (0x1U << CEC_CFGR_BRESTP_Pos) /*!< 0x00000010 */ +#define CEC_CFGR_BRESTP CEC_CFGR_BRESTP_Msk /*!< CEC Rx Stop */ +#define CEC_CFGR_BREGEN_Pos (5U) +#define CEC_CFGR_BREGEN_Msk (0x1U << CEC_CFGR_BREGEN_Pos) /*!< 0x00000020 */ +#define CEC_CFGR_BREGEN CEC_CFGR_BREGEN_Msk /*!< CEC Bit Rising Error generation */ +#define CEC_CFGR_LBPEGEN_Pos (6U) +#define CEC_CFGR_LBPEGEN_Msk (0x1U << CEC_CFGR_LBPEGEN_Pos) /*!< 0x00000040 */ +#define CEC_CFGR_LBPEGEN CEC_CFGR_LBPEGEN_Msk /*!< CEC Long Bit Period Error gener. */ +#define CEC_CFGR_BRDNOGEN_Pos (7U) +#define CEC_CFGR_BRDNOGEN_Msk (0x1U << CEC_CFGR_BRDNOGEN_Pos) /*!< 0x00000080 */ +#define CEC_CFGR_BRDNOGEN CEC_CFGR_BRDNOGEN_Msk /*!< CEC Broadcast No Error generation */ +#define CEC_CFGR_SFTOPT_Pos (8U) +#define CEC_CFGR_SFTOPT_Msk (0x1U << CEC_CFGR_SFTOPT_Pos) /*!< 0x00000100 */ +#define CEC_CFGR_SFTOPT CEC_CFGR_SFTOPT_Msk /*!< CEC Signal Free Time optional */ +#define CEC_CFGR_OAR_Pos (16U) +#define CEC_CFGR_OAR_Msk (0x7FFFU << CEC_CFGR_OAR_Pos) /*!< 0x7FFF0000 */ +#define CEC_CFGR_OAR CEC_CFGR_OAR_Msk /*!< CEC Own Address */ +#define CEC_CFGR_LSTN_Pos (31U) +#define CEC_CFGR_LSTN_Msk (0x1U << CEC_CFGR_LSTN_Pos) /*!< 0x80000000 */ +#define CEC_CFGR_LSTN CEC_CFGR_LSTN_Msk /*!< CEC Listen mode */ /******************* Bit definition for CEC_TXDR register *******************/ -#define CEC_TXDR_TXD ((uint32_t)0x000000FFU) /*!< CEC Tx Data */ +#define CEC_TXDR_TXD_Pos (0U) +#define CEC_TXDR_TXD_Msk (0xFFU << CEC_TXDR_TXD_Pos) /*!< 0x000000FF */ +#define CEC_TXDR_TXD CEC_TXDR_TXD_Msk /*!< CEC Tx Data */ /******************* Bit definition for CEC_RXDR register *******************/ -#define CEC_TXDR_RXD ((uint32_t)0x000000FFU) /*!< CEC Rx Data */ +#define CEC_TXDR_RXD_Pos (0U) +#define CEC_TXDR_RXD_Msk (0xFFU << CEC_TXDR_RXD_Pos) /*!< 0x000000FF */ +#define CEC_TXDR_RXD CEC_TXDR_RXD_Msk /*!< CEC Rx Data */ /******************* Bit definition for CEC_ISR register ********************/ -#define CEC_ISR_RXBR ((uint32_t)0x00000001U) /*!< CEC Rx-Byte Received */ -#define CEC_ISR_RXEND ((uint32_t)0x00000002U) /*!< CEC End Of Reception */ -#define CEC_ISR_RXOVR ((uint32_t)0x00000004U) /*!< CEC Rx-Overrun */ -#define CEC_ISR_BRE ((uint32_t)0x00000008U) /*!< CEC Rx Bit Rising Error */ -#define CEC_ISR_SBPE ((uint32_t)0x00000010U) /*!< CEC Rx Short Bit period Error */ -#define CEC_ISR_LBPE ((uint32_t)0x00000020U) /*!< CEC Rx Long Bit period Error */ -#define CEC_ISR_RXACKE ((uint32_t)0x00000040U) /*!< CEC Rx Missing Acknowledge */ -#define CEC_ISR_ARBLST ((uint32_t)0x00000080U) /*!< CEC Arbitration Lost */ -#define CEC_ISR_TXBR ((uint32_t)0x00000100U) /*!< CEC Tx Byte Request */ -#define CEC_ISR_TXEND ((uint32_t)0x00000200U) /*!< CEC End of Transmission */ -#define CEC_ISR_TXUDR ((uint32_t)0x00000400U) /*!< CEC Tx-Buffer Underrun */ -#define CEC_ISR_TXERR ((uint32_t)0x00000800U) /*!< CEC Tx-Error */ -#define CEC_ISR_TXACKE ((uint32_t)0x00001000U) /*!< CEC Tx Missing Acknowledge */ +#define CEC_ISR_RXBR_Pos (0U) +#define CEC_ISR_RXBR_Msk (0x1U << CEC_ISR_RXBR_Pos) /*!< 0x00000001 */ +#define CEC_ISR_RXBR CEC_ISR_RXBR_Msk /*!< CEC Rx-Byte Received */ +#define CEC_ISR_RXEND_Pos (1U) +#define CEC_ISR_RXEND_Msk (0x1U << CEC_ISR_RXEND_Pos) /*!< 0x00000002 */ +#define CEC_ISR_RXEND CEC_ISR_RXEND_Msk /*!< CEC End Of Reception */ +#define CEC_ISR_RXOVR_Pos (2U) +#define CEC_ISR_RXOVR_Msk (0x1U << CEC_ISR_RXOVR_Pos) /*!< 0x00000004 */ +#define CEC_ISR_RXOVR CEC_ISR_RXOVR_Msk /*!< CEC Rx-Overrun */ +#define CEC_ISR_BRE_Pos (3U) +#define CEC_ISR_BRE_Msk (0x1U << CEC_ISR_BRE_Pos) /*!< 0x00000008 */ +#define CEC_ISR_BRE CEC_ISR_BRE_Msk /*!< CEC Rx Bit Rising Error */ +#define CEC_ISR_SBPE_Pos (4U) +#define CEC_ISR_SBPE_Msk (0x1U << CEC_ISR_SBPE_Pos) /*!< 0x00000010 */ +#define CEC_ISR_SBPE CEC_ISR_SBPE_Msk /*!< CEC Rx Short Bit period Error */ +#define CEC_ISR_LBPE_Pos (5U) +#define CEC_ISR_LBPE_Msk (0x1U << CEC_ISR_LBPE_Pos) /*!< 0x00000020 */ +#define CEC_ISR_LBPE CEC_ISR_LBPE_Msk /*!< CEC Rx Long Bit period Error */ +#define CEC_ISR_RXACKE_Pos (6U) +#define CEC_ISR_RXACKE_Msk (0x1U << CEC_ISR_RXACKE_Pos) /*!< 0x00000040 */ +#define CEC_ISR_RXACKE CEC_ISR_RXACKE_Msk /*!< CEC Rx Missing Acknowledge */ +#define CEC_ISR_ARBLST_Pos (7U) +#define CEC_ISR_ARBLST_Msk (0x1U << CEC_ISR_ARBLST_Pos) /*!< 0x00000080 */ +#define CEC_ISR_ARBLST CEC_ISR_ARBLST_Msk /*!< CEC Arbitration Lost */ +#define CEC_ISR_TXBR_Pos (8U) +#define CEC_ISR_TXBR_Msk (0x1U << CEC_ISR_TXBR_Pos) /*!< 0x00000100 */ +#define CEC_ISR_TXBR CEC_ISR_TXBR_Msk /*!< CEC Tx Byte Request */ +#define CEC_ISR_TXEND_Pos (9U) +#define CEC_ISR_TXEND_Msk (0x1U << CEC_ISR_TXEND_Pos) /*!< 0x00000200 */ +#define CEC_ISR_TXEND CEC_ISR_TXEND_Msk /*!< CEC End of Transmission */ +#define CEC_ISR_TXUDR_Pos (10U) +#define CEC_ISR_TXUDR_Msk (0x1U << CEC_ISR_TXUDR_Pos) /*!< 0x00000400 */ +#define CEC_ISR_TXUDR CEC_ISR_TXUDR_Msk /*!< CEC Tx-Buffer Underrun */ +#define CEC_ISR_TXERR_Pos (11U) +#define CEC_ISR_TXERR_Msk (0x1U << CEC_ISR_TXERR_Pos) /*!< 0x00000800 */ +#define CEC_ISR_TXERR CEC_ISR_TXERR_Msk /*!< CEC Tx-Error */ +#define CEC_ISR_TXACKE_Pos (12U) +#define CEC_ISR_TXACKE_Msk (0x1U << CEC_ISR_TXACKE_Pos) /*!< 0x00001000 */ +#define CEC_ISR_TXACKE CEC_ISR_TXACKE_Msk /*!< CEC Tx Missing Acknowledge */ /******************* Bit definition for CEC_IER register ********************/ -#define CEC_IER_RXBRIE ((uint32_t)0x00000001U) /*!< CEC Rx-Byte Received IT Enable */ -#define CEC_IER_RXENDIE ((uint32_t)0x00000002U) /*!< CEC End Of Reception IT Enable */ -#define CEC_IER_RXOVRIE ((uint32_t)0x00000004U) /*!< CEC Rx-Overrun IT Enable */ -#define CEC_IER_BREIE ((uint32_t)0x00000008U) /*!< CEC Rx Bit Rising Error IT Enable */ -#define CEC_IER_SBPEIE ((uint32_t)0x00000010U) /*!< CEC Rx Short Bit period Error IT Enable*/ -#define CEC_IER_LBPEIE ((uint32_t)0x00000020U) /*!< CEC Rx Long Bit period Error IT Enable */ -#define CEC_IER_RXACKEIE ((uint32_t)0x00000040U) /*!< CEC Rx Missing Acknowledge IT Enable */ -#define CEC_IER_ARBLSTIE ((uint32_t)0x00000080U) /*!< CEC Arbitration Lost IT Enable */ -#define CEC_IER_TXBRIE ((uint32_t)0x00000100U) /*!< CEC Tx Byte Request IT Enable */ -#define CEC_IER_TXENDIE ((uint32_t)0x00000200U) /*!< CEC End of Transmission IT Enable */ -#define CEC_IER_TXUDRIE ((uint32_t)0x00000400U) /*!< CEC Tx-Buffer Underrun IT Enable */ -#define CEC_IER_TXERRIE ((uint32_t)0x00000800U) /*!< CEC Tx-Error IT Enable */ -#define CEC_IER_TXACKEIE ((uint32_t)0x00001000U) /*!< CEC Tx Missing Acknowledge IT Enable */ +#define CEC_IER_RXBRIE_Pos (0U) +#define CEC_IER_RXBRIE_Msk (0x1U << CEC_IER_RXBRIE_Pos) /*!< 0x00000001 */ +#define CEC_IER_RXBRIE CEC_IER_RXBRIE_Msk /*!< CEC Rx-Byte Received IT Enable */ +#define CEC_IER_RXENDIE_Pos (1U) +#define CEC_IER_RXENDIE_Msk (0x1U << CEC_IER_RXENDIE_Pos) /*!< 0x00000002 */ +#define CEC_IER_RXENDIE CEC_IER_RXENDIE_Msk /*!< CEC End Of Reception IT Enable */ +#define CEC_IER_RXOVRIE_Pos (2U) +#define CEC_IER_RXOVRIE_Msk (0x1U << CEC_IER_RXOVRIE_Pos) /*!< 0x00000004 */ +#define CEC_IER_RXOVRIE CEC_IER_RXOVRIE_Msk /*!< CEC Rx-Overrun IT Enable */ +#define CEC_IER_BREIE_Pos (3U) +#define CEC_IER_BREIE_Msk (0x1U << CEC_IER_BREIE_Pos) /*!< 0x00000008 */ +#define CEC_IER_BREIE CEC_IER_BREIE_Msk /*!< CEC Rx Bit Rising Error IT Enable */ +#define CEC_IER_SBPEIE_Pos (4U) +#define CEC_IER_SBPEIE_Msk (0x1U << CEC_IER_SBPEIE_Pos) /*!< 0x00000010 */ +#define CEC_IER_SBPEIE CEC_IER_SBPEIE_Msk /*!< CEC Rx Short Bit period Error IT Enable*/ +#define CEC_IER_LBPEIE_Pos (5U) +#define CEC_IER_LBPEIE_Msk (0x1U << CEC_IER_LBPEIE_Pos) /*!< 0x00000020 */ +#define CEC_IER_LBPEIE CEC_IER_LBPEIE_Msk /*!< CEC Rx Long Bit period Error IT Enable */ +#define CEC_IER_RXACKEIE_Pos (6U) +#define CEC_IER_RXACKEIE_Msk (0x1U << CEC_IER_RXACKEIE_Pos) /*!< 0x00000040 */ +#define CEC_IER_RXACKEIE CEC_IER_RXACKEIE_Msk /*!< CEC Rx Missing Acknowledge IT Enable */ +#define CEC_IER_ARBLSTIE_Pos (7U) +#define CEC_IER_ARBLSTIE_Msk (0x1U << CEC_IER_ARBLSTIE_Pos) /*!< 0x00000080 */ +#define CEC_IER_ARBLSTIE CEC_IER_ARBLSTIE_Msk /*!< CEC Arbitration Lost IT Enable */ +#define CEC_IER_TXBRIE_Pos (8U) +#define CEC_IER_TXBRIE_Msk (0x1U << CEC_IER_TXBRIE_Pos) /*!< 0x00000100 */ +#define CEC_IER_TXBRIE CEC_IER_TXBRIE_Msk /*!< CEC Tx Byte Request IT Enable */ +#define CEC_IER_TXENDIE_Pos (9U) +#define CEC_IER_TXENDIE_Msk (0x1U << CEC_IER_TXENDIE_Pos) /*!< 0x00000200 */ +#define CEC_IER_TXENDIE CEC_IER_TXENDIE_Msk /*!< CEC End of Transmission IT Enable */ +#define CEC_IER_TXUDRIE_Pos (10U) +#define CEC_IER_TXUDRIE_Msk (0x1U << CEC_IER_TXUDRIE_Pos) /*!< 0x00000400 */ +#define CEC_IER_TXUDRIE CEC_IER_TXUDRIE_Msk /*!< CEC Tx-Buffer Underrun IT Enable */ +#define CEC_IER_TXERRIE_Pos (11U) +#define CEC_IER_TXERRIE_Msk (0x1U << CEC_IER_TXERRIE_Pos) /*!< 0x00000800 */ +#define CEC_IER_TXERRIE CEC_IER_TXERRIE_Msk /*!< CEC Tx-Error IT Enable */ +#define CEC_IER_TXACKEIE_Pos (12U) +#define CEC_IER_TXACKEIE_Msk (0x1U << CEC_IER_TXACKEIE_Pos) /*!< 0x00001000 */ +#define CEC_IER_TXACKEIE CEC_IER_TXACKEIE_Msk /*!< CEC Tx Missing Acknowledge IT Enable */ /******************************************************************************/ /* */ @@ -925,64 +1125,116 @@ typedef struct /******************************************************************************/ /*********************** Bit definition for COMP_CSR register ***************/ /* COMP1 bits definition */ -#define COMP_CSR_COMP1EN ((uint32_t)0x00000001U) /*!< COMP1 enable */ -#define COMP_CSR_COMP1SW1 ((uint32_t)0x00000002U) /*!< COMP1 SW1 switch control */ -#define COMP_CSR_COMP1MODE ((uint32_t)0x0000000CU) /*!< COMP1 power mode */ -#define COMP_CSR_COMP1MODE_0 ((uint32_t)0x00000004U) /*!< COMP1 power mode bit 0 */ -#define COMP_CSR_COMP1MODE_1 ((uint32_t)0x00000008U) /*!< COMP1 power mode bit 1 */ -#define COMP_CSR_COMP1INSEL ((uint32_t)0x00000070U) /*!< COMP1 inverting input select */ -#define COMP_CSR_COMP1INSEL_0 ((uint32_t)0x00000010U) /*!< COMP1 inverting input select bit 0 */ -#define COMP_CSR_COMP1INSEL_1 ((uint32_t)0x00000020U) /*!< COMP1 inverting input select bit 1 */ -#define COMP_CSR_COMP1INSEL_2 ((uint32_t)0x00000040U) /*!< COMP1 inverting input select bit 2 */ -#define COMP_CSR_COMP1OUTSEL ((uint32_t)0x00000700U) /*!< COMP1 output select */ -#define COMP_CSR_COMP1OUTSEL_0 ((uint32_t)0x00000100U) /*!< COMP1 output select bit 0 */ -#define COMP_CSR_COMP1OUTSEL_1 ((uint32_t)0x00000200U) /*!< COMP1 output select bit 1 */ -#define COMP_CSR_COMP1OUTSEL_2 ((uint32_t)0x00000400U) /*!< COMP1 output select bit 2 */ -#define COMP_CSR_COMP1POL ((uint32_t)0x00000800U) /*!< COMP1 output polarity */ -#define COMP_CSR_COMP1HYST ((uint32_t)0x00003000U) /*!< COMP1 hysteresis */ -#define COMP_CSR_COMP1HYST_0 ((uint32_t)0x00001000U) /*!< COMP1 hysteresis bit 0 */ -#define COMP_CSR_COMP1HYST_1 ((uint32_t)0x00002000U) /*!< COMP1 hysteresis bit 1 */ -#define COMP_CSR_COMP1OUT ((uint32_t)0x00004000U) /*!< COMP1 output level */ -#define COMP_CSR_COMP1LOCK ((uint32_t)0x00008000U) /*!< COMP1 lock */ +#define COMP_CSR_COMP1EN_Pos (0U) +#define COMP_CSR_COMP1EN_Msk (0x1U << COMP_CSR_COMP1EN_Pos) /*!< 0x00000001 */ +#define COMP_CSR_COMP1EN COMP_CSR_COMP1EN_Msk /*!< COMP1 enable */ +#define COMP_CSR_COMP1SW1_Pos (1U) +#define COMP_CSR_COMP1SW1_Msk (0x1U << COMP_CSR_COMP1SW1_Pos) /*!< 0x00000002 */ +#define COMP_CSR_COMP1SW1 COMP_CSR_COMP1SW1_Msk /*!< COMP1 SW1 switch control */ +#define COMP_CSR_COMP1MODE_Pos (2U) +#define COMP_CSR_COMP1MODE_Msk (0x3U << COMP_CSR_COMP1MODE_Pos) /*!< 0x0000000C */ +#define COMP_CSR_COMP1MODE COMP_CSR_COMP1MODE_Msk /*!< COMP1 power mode */ +#define COMP_CSR_COMP1MODE_0 (0x1U << COMP_CSR_COMP1MODE_Pos) /*!< 0x00000004 */ +#define COMP_CSR_COMP1MODE_1 (0x2U << COMP_CSR_COMP1MODE_Pos) /*!< 0x00000008 */ +#define COMP_CSR_COMP1INSEL_Pos (4U) +#define COMP_CSR_COMP1INSEL_Msk (0x7U << COMP_CSR_COMP1INSEL_Pos) /*!< 0x00000070 */ +#define COMP_CSR_COMP1INSEL COMP_CSR_COMP1INSEL_Msk /*!< COMP1 inverting input select */ +#define COMP_CSR_COMP1INSEL_0 (0x1U << COMP_CSR_COMP1INSEL_Pos) /*!< 0x00000010 */ +#define COMP_CSR_COMP1INSEL_1 (0x2U << COMP_CSR_COMP1INSEL_Pos) /*!< 0x00000020 */ +#define COMP_CSR_COMP1INSEL_2 (0x4U << COMP_CSR_COMP1INSEL_Pos) /*!< 0x00000040 */ +#define COMP_CSR_COMP1OUTSEL_Pos (8U) +#define COMP_CSR_COMP1OUTSEL_Msk (0x7U << COMP_CSR_COMP1OUTSEL_Pos) /*!< 0x00000700 */ +#define COMP_CSR_COMP1OUTSEL COMP_CSR_COMP1OUTSEL_Msk /*!< COMP1 output select */ +#define COMP_CSR_COMP1OUTSEL_0 (0x1U << COMP_CSR_COMP1OUTSEL_Pos) /*!< 0x00000100 */ +#define COMP_CSR_COMP1OUTSEL_1 (0x2U << COMP_CSR_COMP1OUTSEL_Pos) /*!< 0x00000200 */ +#define COMP_CSR_COMP1OUTSEL_2 (0x4U << COMP_CSR_COMP1OUTSEL_Pos) /*!< 0x00000400 */ +#define COMP_CSR_COMP1POL_Pos (11U) +#define COMP_CSR_COMP1POL_Msk (0x1U << COMP_CSR_COMP1POL_Pos) /*!< 0x00000800 */ +#define COMP_CSR_COMP1POL COMP_CSR_COMP1POL_Msk /*!< COMP1 output polarity */ +#define COMP_CSR_COMP1HYST_Pos (12U) +#define COMP_CSR_COMP1HYST_Msk (0x3U << COMP_CSR_COMP1HYST_Pos) /*!< 0x00003000 */ +#define COMP_CSR_COMP1HYST COMP_CSR_COMP1HYST_Msk /*!< COMP1 hysteresis */ +#define COMP_CSR_COMP1HYST_0 (0x1U << COMP_CSR_COMP1HYST_Pos) /*!< 0x00001000 */ +#define COMP_CSR_COMP1HYST_1 (0x2U << COMP_CSR_COMP1HYST_Pos) /*!< 0x00002000 */ +#define COMP_CSR_COMP1OUT_Pos (14U) +#define COMP_CSR_COMP1OUT_Msk (0x1U << COMP_CSR_COMP1OUT_Pos) /*!< 0x00004000 */ +#define COMP_CSR_COMP1OUT COMP_CSR_COMP1OUT_Msk /*!< COMP1 output level */ +#define COMP_CSR_COMP1LOCK_Pos (15U) +#define COMP_CSR_COMP1LOCK_Msk (0x1U << COMP_CSR_COMP1LOCK_Pos) /*!< 0x00008000 */ +#define COMP_CSR_COMP1LOCK COMP_CSR_COMP1LOCK_Msk /*!< COMP1 lock */ /* COMP2 bits definition */ -#define COMP_CSR_COMP2EN ((uint32_t)0x00010000U) /*!< COMP2 enable */ -#define COMP_CSR_COMP2MODE ((uint32_t)0x000C0000U) /*!< COMP2 power mode */ -#define COMP_CSR_COMP2MODE_0 ((uint32_t)0x00040000U) /*!< COMP2 power mode bit 0 */ -#define COMP_CSR_COMP2MODE_1 ((uint32_t)0x00080000U) /*!< COMP2 power mode bit 1 */ -#define COMP_CSR_COMP2INSEL ((uint32_t)0x00700000U) /*!< COMP2 inverting input select */ -#define COMP_CSR_COMP2INSEL_0 ((uint32_t)0x00100000U) /*!< COMP2 inverting input select bit 0 */ -#define COMP_CSR_COMP2INSEL_1 ((uint32_t)0x00200000U) /*!< COMP2 inverting input select bit 1 */ -#define COMP_CSR_COMP2INSEL_2 ((uint32_t)0x00400000U) /*!< COMP2 inverting input select bit 2 */ -#define COMP_CSR_WNDWEN ((uint32_t)0x00800000U) /*!< COMPx window mode. Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */ -#define COMP_CSR_COMP2OUTSEL ((uint32_t)0x07000000U) /*!< COMP2 output select */ -#define COMP_CSR_COMP2OUTSEL_0 ((uint32_t)0x01000000U) /*!< COMP2 output select bit 0 */ -#define COMP_CSR_COMP2OUTSEL_1 ((uint32_t)0x02000000U) /*!< COMP2 output select bit 1 */ -#define COMP_CSR_COMP2OUTSEL_2 ((uint32_t)0x04000000U) /*!< COMP2 output select bit 2 */ -#define COMP_CSR_COMP2POL ((uint32_t)0x08000000U) /*!< COMP2 output polarity */ -#define COMP_CSR_COMP2HYST ((uint32_t)0x30000000U) /*!< COMP2 hysteresis */ -#define COMP_CSR_COMP2HYST_0 ((uint32_t)0x10000000U) /*!< COMP2 hysteresis bit 0 */ -#define COMP_CSR_COMP2HYST_1 ((uint32_t)0x20000000U) /*!< COMP2 hysteresis bit 1 */ -#define COMP_CSR_COMP2OUT ((uint32_t)0x40000000U) /*!< COMP2 output level */ -#define COMP_CSR_COMP2LOCK ((uint32_t)0x80000000U) /*!< COMP2 lock */ +#define COMP_CSR_COMP2EN_Pos (16U) +#define COMP_CSR_COMP2EN_Msk (0x1U << COMP_CSR_COMP2EN_Pos) /*!< 0x00010000 */ +#define COMP_CSR_COMP2EN COMP_CSR_COMP2EN_Msk /*!< COMP2 enable */ +#define COMP_CSR_COMP2MODE_Pos (18U) +#define COMP_CSR_COMP2MODE_Msk (0x3U << COMP_CSR_COMP2MODE_Pos) /*!< 0x000C0000 */ +#define COMP_CSR_COMP2MODE COMP_CSR_COMP2MODE_Msk /*!< COMP2 power mode */ +#define COMP_CSR_COMP2MODE_0 (0x1U << COMP_CSR_COMP2MODE_Pos) /*!< 0x00040000 */ +#define COMP_CSR_COMP2MODE_1 (0x2U << COMP_CSR_COMP2MODE_Pos) /*!< 0x00080000 */ +#define COMP_CSR_COMP2INSEL_Pos (20U) +#define COMP_CSR_COMP2INSEL_Msk (0x7U << COMP_CSR_COMP2INSEL_Pos) /*!< 0x00700000 */ +#define COMP_CSR_COMP2INSEL COMP_CSR_COMP2INSEL_Msk /*!< COMP2 inverting input select */ +#define COMP_CSR_COMP2INSEL_0 (0x1U << COMP_CSR_COMP2INSEL_Pos) /*!< 0x00100000 */ +#define COMP_CSR_COMP2INSEL_1 (0x2U << COMP_CSR_COMP2INSEL_Pos) /*!< 0x00200000 */ +#define COMP_CSR_COMP2INSEL_2 (0x4U << COMP_CSR_COMP2INSEL_Pos) /*!< 0x00400000 */ +#define COMP_CSR_WNDWEN_Pos (23U) +#define COMP_CSR_WNDWEN_Msk (0x1U << COMP_CSR_WNDWEN_Pos) /*!< 0x00800000 */ +#define COMP_CSR_WNDWEN COMP_CSR_WNDWEN_Msk /*!< COMPx window mode. Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */ +#define COMP_CSR_COMP2OUTSEL_Pos (24U) +#define COMP_CSR_COMP2OUTSEL_Msk (0x7U << COMP_CSR_COMP2OUTSEL_Pos) /*!< 0x07000000 */ +#define COMP_CSR_COMP2OUTSEL COMP_CSR_COMP2OUTSEL_Msk /*!< COMP2 output select */ +#define COMP_CSR_COMP2OUTSEL_0 (0x1U << COMP_CSR_COMP2OUTSEL_Pos) /*!< 0x01000000 */ +#define COMP_CSR_COMP2OUTSEL_1 (0x2U << COMP_CSR_COMP2OUTSEL_Pos) /*!< 0x02000000 */ +#define COMP_CSR_COMP2OUTSEL_2 (0x4U << COMP_CSR_COMP2OUTSEL_Pos) /*!< 0x04000000 */ +#define COMP_CSR_COMP2POL_Pos (27U) +#define COMP_CSR_COMP2POL_Msk (0x1U << COMP_CSR_COMP2POL_Pos) /*!< 0x08000000 */ +#define COMP_CSR_COMP2POL COMP_CSR_COMP2POL_Msk /*!< COMP2 output polarity */ +#define COMP_CSR_COMP2HYST_Pos (28U) +#define COMP_CSR_COMP2HYST_Msk (0x3U << COMP_CSR_COMP2HYST_Pos) /*!< 0x30000000 */ +#define COMP_CSR_COMP2HYST COMP_CSR_COMP2HYST_Msk /*!< COMP2 hysteresis */ +#define COMP_CSR_COMP2HYST_0 (0x1U << COMP_CSR_COMP2HYST_Pos) /*!< 0x10000000 */ +#define COMP_CSR_COMP2HYST_1 (0x2U << COMP_CSR_COMP2HYST_Pos) /*!< 0x20000000 */ +#define COMP_CSR_COMP2OUT_Pos (30U) +#define COMP_CSR_COMP2OUT_Msk (0x1U << COMP_CSR_COMP2OUT_Pos) /*!< 0x40000000 */ +#define COMP_CSR_COMP2OUT COMP_CSR_COMP2OUT_Msk /*!< COMP2 output level */ +#define COMP_CSR_COMP2LOCK_Pos (31U) +#define COMP_CSR_COMP2LOCK_Msk (0x1U << COMP_CSR_COMP2LOCK_Pos) /*!< 0x80000000 */ +#define COMP_CSR_COMP2LOCK COMP_CSR_COMP2LOCK_Msk /*!< COMP2 lock */ /* COMPx bits definition */ -#define COMP_CSR_COMPxEN ((uint32_t)0x00000001U) /*!< COMPx enable */ -#define COMP_CSR_COMPxMODE ((uint32_t)0x0000000CU) /*!< COMPx power mode */ -#define COMP_CSR_COMPxMODE_0 ((uint32_t)0x00000004U) /*!< COMPx power mode bit 0 */ -#define COMP_CSR_COMPxMODE_1 ((uint32_t)0x00000008U) /*!< COMPx power mode bit 1 */ -#define COMP_CSR_COMPxINSEL ((uint32_t)0x00000070U) /*!< COMPx inverting input select */ -#define COMP_CSR_COMPxINSEL_0 ((uint32_t)0x00000010U) /*!< COMPx inverting input select bit 0 */ -#define COMP_CSR_COMPxINSEL_1 ((uint32_t)0x00000020U) /*!< COMPx inverting input select bit 1 */ -#define COMP_CSR_COMPxINSEL_2 ((uint32_t)0x00000040U) /*!< COMPx inverting input select bit 2 */ -#define COMP_CSR_COMPxOUTSEL ((uint32_t)0x00000700U) /*!< COMPx output select */ -#define COMP_CSR_COMPxOUTSEL_0 ((uint32_t)0x00000100U) /*!< COMPx output select bit 0 */ -#define COMP_CSR_COMPxOUTSEL_1 ((uint32_t)0x00000200U) /*!< COMPx output select bit 1 */ -#define COMP_CSR_COMPxOUTSEL_2 ((uint32_t)0x00000400U) /*!< COMPx output select bit 2 */ -#define COMP_CSR_COMPxPOL ((uint32_t)0x00000800U) /*!< COMPx output polarity */ -#define COMP_CSR_COMPxHYST ((uint32_t)0x00003000U) /*!< COMPx hysteresis */ -#define COMP_CSR_COMPxHYST_0 ((uint32_t)0x00001000U) /*!< COMPx hysteresis bit 0 */ -#define COMP_CSR_COMPxHYST_1 ((uint32_t)0x00002000U) /*!< COMPx hysteresis bit 1 */ -#define COMP_CSR_COMPxOUT ((uint32_t)0x00004000U) /*!< COMPx output level */ -#define COMP_CSR_COMPxLOCK ((uint32_t)0x00008000U) /*!< COMPx lock */ +#define COMP_CSR_COMPxEN_Pos (0U) +#define COMP_CSR_COMPxEN_Msk (0x1U << COMP_CSR_COMPxEN_Pos) /*!< 0x00000001 */ +#define COMP_CSR_COMPxEN COMP_CSR_COMPxEN_Msk /*!< COMPx enable */ +#define COMP_CSR_COMPxMODE_Pos (2U) +#define COMP_CSR_COMPxMODE_Msk (0x3U << COMP_CSR_COMPxMODE_Pos) /*!< 0x0000000C */ +#define COMP_CSR_COMPxMODE COMP_CSR_COMPxMODE_Msk /*!< COMPx power mode */ +#define COMP_CSR_COMPxMODE_0 (0x1U << COMP_CSR_COMPxMODE_Pos) /*!< 0x00000004 */ +#define COMP_CSR_COMPxMODE_1 (0x2U << COMP_CSR_COMPxMODE_Pos) /*!< 0x00000008 */ +#define COMP_CSR_COMPxINSEL_Pos (4U) +#define COMP_CSR_COMPxINSEL_Msk (0x7U << COMP_CSR_COMPxINSEL_Pos) /*!< 0x00000070 */ +#define COMP_CSR_COMPxINSEL COMP_CSR_COMPxINSEL_Msk /*!< COMPx inverting input select */ +#define COMP_CSR_COMPxINSEL_0 (0x1U << COMP_CSR_COMPxINSEL_Pos) /*!< 0x00000010 */ +#define COMP_CSR_COMPxINSEL_1 (0x2U << COMP_CSR_COMPxINSEL_Pos) /*!< 0x00000020 */ +#define COMP_CSR_COMPxINSEL_2 (0x4U << COMP_CSR_COMPxINSEL_Pos) /*!< 0x00000040 */ +#define COMP_CSR_COMPxOUTSEL_Pos (8U) +#define COMP_CSR_COMPxOUTSEL_Msk (0x7U << COMP_CSR_COMPxOUTSEL_Pos) /*!< 0x00000700 */ +#define COMP_CSR_COMPxOUTSEL COMP_CSR_COMPxOUTSEL_Msk /*!< COMPx output select */ +#define COMP_CSR_COMPxOUTSEL_0 (0x1U << COMP_CSR_COMPxOUTSEL_Pos) /*!< 0x00000100 */ +#define COMP_CSR_COMPxOUTSEL_1 (0x2U << COMP_CSR_COMPxOUTSEL_Pos) /*!< 0x00000200 */ +#define COMP_CSR_COMPxOUTSEL_2 (0x4U << COMP_CSR_COMPxOUTSEL_Pos) /*!< 0x00000400 */ +#define COMP_CSR_COMPxPOL_Pos (11U) +#define COMP_CSR_COMPxPOL_Msk (0x1U << COMP_CSR_COMPxPOL_Pos) /*!< 0x00000800 */ +#define COMP_CSR_COMPxPOL COMP_CSR_COMPxPOL_Msk /*!< COMPx output polarity */ +#define COMP_CSR_COMPxHYST_Pos (12U) +#define COMP_CSR_COMPxHYST_Msk (0x3U << COMP_CSR_COMPxHYST_Pos) /*!< 0x00003000 */ +#define COMP_CSR_COMPxHYST COMP_CSR_COMPxHYST_Msk /*!< COMPx hysteresis */ +#define COMP_CSR_COMPxHYST_0 (0x1U << COMP_CSR_COMPxHYST_Pos) /*!< 0x00001000 */ +#define COMP_CSR_COMPxHYST_1 (0x2U << COMP_CSR_COMPxHYST_Pos) /*!< 0x00002000 */ +#define COMP_CSR_COMPxOUT_Pos (14U) +#define COMP_CSR_COMPxOUT_Msk (0x1U << COMP_CSR_COMPxOUT_Pos) /*!< 0x00004000 */ +#define COMP_CSR_COMPxOUT COMP_CSR_COMPxOUT_Msk /*!< COMPx output level */ +#define COMP_CSR_COMPxLOCK_Pos (15U) +#define COMP_CSR_COMPxLOCK_Msk (0x1U << COMP_CSR_COMPxLOCK_Pos) /*!< 0x00008000 */ +#define COMP_CSR_COMPxLOCK COMP_CSR_COMPxLOCK_Msk /*!< COMPx lock */ /******************************************************************************/ /* */ @@ -990,20 +1242,30 @@ typedef struct /* */ /******************************************************************************/ /******************* Bit definition for CRC_DR register *********************/ -#define CRC_DR_DR ((uint32_t)0xFFFFFFFFU) /*!< Data register bits */ +#define CRC_DR_DR_Pos (0U) +#define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ /******************* Bit definition for CRC_IDR register ********************/ -#define CRC_IDR_IDR ((uint8_t)0xFFU) /*!< General-purpose 8-bit data register bits */ +#define CRC_IDR_IDR ((uint8_t)0xFFU) /*!< General-purpose 8-bit data register bits */ /******************** Bit definition for CRC_CR register ********************/ -#define CRC_CR_RESET ((uint32_t)0x00000001U) /*!< RESET the CRC computation unit bit */ -#define CRC_CR_REV_IN ((uint32_t)0x00000060U) /*!< REV_IN Reverse Input Data bits */ -#define CRC_CR_REV_IN_0 ((uint32_t)0x00000020U) /*!< REV_IN Bit 0 */ -#define CRC_CR_REV_IN_1 ((uint32_t)0x00000040U) /*!< REV_IN Bit 1 */ -#define CRC_CR_REV_OUT ((uint32_t)0x00000080U) /*!< REV_OUT Reverse Output Data bits */ +#define CRC_CR_RESET_Pos (0U) +#define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */ +#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ +#define CRC_CR_REV_IN_Pos (5U) +#define CRC_CR_REV_IN_Msk (0x3U << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ +#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ +#define CRC_CR_REV_IN_0 (0x1U << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ +#define CRC_CR_REV_IN_1 (0x2U << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ +#define CRC_CR_REV_OUT_Pos (7U) +#define CRC_CR_REV_OUT_Msk (0x1U << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ +#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ /******************* Bit definition for CRC_INIT register *******************/ -#define CRC_INIT_INIT ((uint32_t)0xFFFFFFFFU) /*!< Initial CRC value bits */ +#define CRC_INIT_INIT_Pos (0U) +#define CRC_INIT_INIT_Msk (0xFFFFFFFFU << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ +#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ /******************************************************************************/ /* */ @@ -1012,42 +1274,68 @@ typedef struct /******************************************************************************/ /* - * @brief Specific device feature definitions (not present on all devices in the STM32F0 family) + * @brief Specific device feature definitions (not present on all devices in the STM32F0 serie) */ /* Note: No specific macro feature on this device */ /******************** Bit definition for DAC_CR register ********************/ -#define DAC_CR_EN1 ((uint32_t)0x00000001U) /*!< DAC channel1 enable */ -#define DAC_CR_BOFF1 ((uint32_t)0x00000002U) /*!< DAC channel1 output buffer disable */ -#define DAC_CR_TEN1 ((uint32_t)0x00000004U) /*!< DAC channel1 Trigger enable */ +#define DAC_CR_EN1_Pos (0U) +#define DAC_CR_EN1_Msk (0x1U << DAC_CR_EN1_Pos) /*!< 0x00000001 */ +#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!< DAC channel1 enable */ +#define DAC_CR_BOFF1_Pos (1U) +#define DAC_CR_BOFF1_Msk (0x1U << DAC_CR_BOFF1_Pos) /*!< 0x00000002 */ +#define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk /*!< DAC channel1 output buffer disable */ +#define DAC_CR_TEN1_Pos (2U) +#define DAC_CR_TEN1_Msk (0x1U << DAC_CR_TEN1_Pos) /*!< 0x00000004 */ +#define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!< DAC channel1 Trigger enable */ -#define DAC_CR_TSEL1 ((uint32_t)0x00000038U) /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */ -#define DAC_CR_TSEL1_0 ((uint32_t)0x00000008U) /*!< Bit 0 */ -#define DAC_CR_TSEL1_1 ((uint32_t)0x00000010U) /*!< Bit 1 */ -#define DAC_CR_TSEL1_2 ((uint32_t)0x00000020U) /*!< Bit 2 */ +#define DAC_CR_TSEL1_Pos (3U) +#define DAC_CR_TSEL1_Msk (0x7U << DAC_CR_TSEL1_Pos) /*!< 0x00000038 */ +#define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */ +#define DAC_CR_TSEL1_0 (0x1U << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */ +#define DAC_CR_TSEL1_1 (0x2U << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */ +#define DAC_CR_TSEL1_2 (0x4U << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */ -#define DAC_CR_DMAEN1 ((uint32_t)0x00001000U) /*!< DAC channel1 DMA enable */ -#define DAC_CR_DMAUDRIE1 ((uint32_t)0x00002000U) /*!< DAC channel1 DMA Underrun Interrupt enable */ +#define DAC_CR_DMAEN1_Pos (12U) +#define DAC_CR_DMAEN1_Msk (0x1U << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */ +#define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!< DAC channel1 DMA enable */ +#define DAC_CR_DMAUDRIE1_Pos (13U) +#define DAC_CR_DMAUDRIE1_Msk (0x1U << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */ +#define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!< DAC channel1 DMA Underrun Interrupt enable */ /***************** Bit definition for DAC_SWTRIGR register ******************/ -#define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x00000001U) /*!< DAC channel1 software trigger */ +#define DAC_SWTRIGR_SWTRIG1_Pos (0U) +#define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!< DAC channel1 software trigger */ /***************** Bit definition for DAC_DHR12R1 register ******************/ -#define DAC_DHR12R1_DACC1DHR ((uint32_t)0x00000FFFU) /*!< DAC channel1 12-bit Right aligned data */ +#define DAC_DHR12R1_DACC1DHR_Pos (0U) +#define DAC_DHR12R1_DACC1DHR_Msk (0xFFFU << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */ +#define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!< DAC channel1 12-bit Right aligned data */ /***************** Bit definition for DAC_DHR12L1 register ******************/ -#define DAC_DHR12L1_DACC1DHR ((uint32_t)0x0000FFF0U) /*!< DAC channel1 12-bit Left aligned data */ +#define DAC_DHR12L1_DACC1DHR_Pos (4U) +#define DAC_DHR12L1_DACC1DHR_Msk (0xFFFU << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */ +#define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!< DAC channel1 12-bit Left aligned data */ /****************** Bit definition for DAC_DHR8R1 register ******************/ -#define DAC_DHR8R1_DACC1DHR ((uint32_t)0x000000FFU) /*!< DAC channel1 8-bit Right aligned data */ +#define DAC_DHR8R1_DACC1DHR_Pos (0U) +#define DAC_DHR8R1_DACC1DHR_Msk (0xFFU << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */ +#define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!< DAC channel1 8-bit Right aligned data */ /******************* Bit definition for DAC_DOR1 register *******************/ -#define DAC_DOR1_DACC1DOR ((uint32_t)0x00000FFFU) /*!< DAC channel1 data output */ +#define DAC_DOR1_DACC1DOR_Pos (0U) +#define DAC_DOR1_DACC1DOR_Msk (0xFFFU << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */ +#define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!< DAC channel1 data output */ /******************** Bit definition for DAC_SR register ********************/ -#define DAC_SR_DMAUDR1 ((uint32_t)0x00002000U) /*!< DAC channel1 DMA underrun flag */ -#define DAC_SR_DMAUDR2 ((uint32_t)0x20000000U) /*!< DAC channel2 DMA underrun flag */ +#define DAC_SR_DMAUDR1_Pos (13U) +#define DAC_SR_DMAUDR1_Msk (0x1U << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */ +#define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!< DAC channel1 DMA underrun flag */ +#define DAC_SR_DMAUDR2_Pos (29U) +#define DAC_SR_DMAUDR2_Msk (0x1U << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */ +#define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!< DAC channel2 DMA underrun flag */ /******************************************************************************/ /* */ @@ -1056,45 +1344,77 @@ typedef struct /******************************************************************************/ /**************** Bit definition for DBGMCU_IDCODE register *****************/ -#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFFU) /*!< Device Identifier */ +#define DBGMCU_IDCODE_DEV_ID_Pos (0U) +#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */ +#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk /*!< Device Identifier */ -#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000U) /*!< REV_ID[15:0] bits (Revision Identifier) */ -#define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000U) /*!< Bit 0 */ -#define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000U) /*!< Bit 1 */ -#define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000U) /*!< Bit 2 */ -#define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000U) /*!< Bit 3 */ -#define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000U) /*!< Bit 4 */ -#define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000U) /*!< Bit 5 */ -#define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000U) /*!< Bit 6 */ -#define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000U) /*!< Bit 7 */ -#define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000U) /*!< Bit 8 */ -#define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000U) /*!< Bit 9 */ -#define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000U) /*!< Bit 10 */ -#define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000U) /*!< Bit 11 */ -#define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000U) /*!< Bit 12 */ -#define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000U) /*!< Bit 13 */ -#define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000U) /*!< Bit 14 */ -#define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000U) /*!< Bit 15 */ +#define DBGMCU_IDCODE_REV_ID_Pos (16U) +#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */ +#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /*!< REV_ID[15:0] bits (Revision Identifier) */ +#define DBGMCU_IDCODE_REV_ID_0 (0x0001U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */ +#define DBGMCU_IDCODE_REV_ID_1 (0x0002U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */ +#define DBGMCU_IDCODE_REV_ID_2 (0x0004U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */ +#define DBGMCU_IDCODE_REV_ID_3 (0x0008U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */ +#define DBGMCU_IDCODE_REV_ID_4 (0x0010U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */ +#define DBGMCU_IDCODE_REV_ID_5 (0x0020U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */ +#define DBGMCU_IDCODE_REV_ID_6 (0x0040U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */ +#define DBGMCU_IDCODE_REV_ID_7 (0x0080U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */ +#define DBGMCU_IDCODE_REV_ID_8 (0x0100U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */ +#define DBGMCU_IDCODE_REV_ID_9 (0x0200U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */ +#define DBGMCU_IDCODE_REV_ID_10 (0x0400U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */ +#define DBGMCU_IDCODE_REV_ID_11 (0x0800U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */ +#define DBGMCU_IDCODE_REV_ID_12 (0x1000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */ +#define DBGMCU_IDCODE_REV_ID_13 (0x2000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */ +#define DBGMCU_IDCODE_REV_ID_14 (0x4000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */ +#define DBGMCU_IDCODE_REV_ID_15 (0x8000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */ /****************** Bit definition for DBGMCU_CR register *******************/ -#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002U) /*!< Debug Stop Mode */ -#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004U) /*!< Debug Standby mode */ +#define DBGMCU_CR_DBG_STOP_Pos (1U) +#define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */ +#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk /*!< Debug Stop Mode */ +#define DBGMCU_CR_DBG_STANDBY_Pos (2U) +#define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */ +#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /*!< Debug Standby mode */ /****************** Bit definition for DBGMCU_APB1_FZ register **************/ -#define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001U) /*!< TIM2 counter stopped when core is halted */ -#define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002U) /*!< TIM3 counter stopped when core is halted */ -#define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010U) /*!< TIM6 counter stopped when core is halted */ -#define DBGMCU_APB1_FZ_DBG_TIM14_STOP ((uint32_t)0x00000100U) /*!< TIM14 counter stopped when core is halted */ -#define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400U) /*!< RTC Calendar frozen when core is halted */ -#define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800U) /*!< Debug Window Watchdog stopped when Core is halted */ -#define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000U) /*!< Debug Independent Watchdog stopped when Core is halted */ -#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000U) /*!< I2C1 SMBUS timeout mode stopped when Core is halted */ +#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U) +#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */ +#define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */ +#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U) +#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */ +#define DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk /*!< TIM3 counter stopped when core is halted */ +#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U) +#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */ +#define DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk /*!< TIM6 counter stopped when core is halted */ +#define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos (8U) +#define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos) /*!< 0x00000100 */ +#define DBGMCU_APB1_FZ_DBG_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk /*!< TIM14 counter stopped when core is halted */ +#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U) +#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */ +#define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk /*!< RTC Calendar frozen when core is halted */ +#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U) +#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */ +#define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */ +#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U) +#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */ +#define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */ +#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U) +#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */ +#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk /*!< I2C1 SMBUS timeout mode stopped when Core is halted */ /****************** Bit definition for DBGMCU_APB2_FZ register **************/ -#define DBGMCU_APB2_FZ_DBG_TIM1_STOP ((uint32_t)0x00000800U) /*!< TIM1 counter stopped when core is halted */ -#define DBGMCU_APB2_FZ_DBG_TIM15_STOP ((uint32_t)0x00010000U) /*!< TIM15 counter stopped when core is halted */ -#define DBGMCU_APB2_FZ_DBG_TIM16_STOP ((uint32_t)0x00020000U) /*!< TIM16 counter stopped when core is halted */ -#define DBGMCU_APB2_FZ_DBG_TIM17_STOP ((uint32_t)0x00040000U) /*!< TIM17 counter stopped when core is halted */ +#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos (11U) +#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000800 */ +#define DBGMCU_APB2_FZ_DBG_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk /*!< TIM1 counter stopped when core is halted */ +#define DBGMCU_APB2_FZ_DBG_TIM15_STOP_Pos (16U) +#define DBGMCU_APB2_FZ_DBG_TIM15_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM15_STOP_Pos) /*!< 0x00010000 */ +#define DBGMCU_APB2_FZ_DBG_TIM15_STOP DBGMCU_APB2_FZ_DBG_TIM15_STOP_Msk /*!< TIM15 counter stopped when core is halted */ +#define DBGMCU_APB2_FZ_DBG_TIM16_STOP_Pos (17U) +#define DBGMCU_APB2_FZ_DBG_TIM16_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM16_STOP_Pos) /*!< 0x00020000 */ +#define DBGMCU_APB2_FZ_DBG_TIM16_STOP DBGMCU_APB2_FZ_DBG_TIM16_STOP_Msk /*!< TIM16 counter stopped when core is halted */ +#define DBGMCU_APB2_FZ_DBG_TIM17_STOP_Pos (18U) +#define DBGMCU_APB2_FZ_DBG_TIM17_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM17_STOP_Pos) /*!< 0x00040000 */ +#define DBGMCU_APB2_FZ_DBG_TIM17_STOP DBGMCU_APB2_FZ_DBG_TIM17_STOP_Msk /*!< TIM17 counter stopped when core is halted */ /******************************************************************************/ /* */ @@ -1102,81 +1422,191 @@ typedef struct /* */ /******************************************************************************/ /******************* Bit definition for DMA_ISR register ********************/ -#define DMA_ISR_GIF1 ((uint32_t)0x00000001U) /*!< Channel 1 Global interrupt flag */ -#define DMA_ISR_TCIF1 ((uint32_t)0x00000002U) /*!< Channel 1 Transfer Complete flag */ -#define DMA_ISR_HTIF1 ((uint32_t)0x00000004U) /*!< Channel 1 Half Transfer flag */ -#define DMA_ISR_TEIF1 ((uint32_t)0x00000008U) /*!< Channel 1 Transfer Error flag */ -#define DMA_ISR_GIF2 ((uint32_t)0x00000010U) /*!< Channel 2 Global interrupt flag */ -#define DMA_ISR_TCIF2 ((uint32_t)0x00000020U) /*!< Channel 2 Transfer Complete flag */ -#define DMA_ISR_HTIF2 ((uint32_t)0x00000040U) /*!< Channel 2 Half Transfer flag */ -#define DMA_ISR_TEIF2 ((uint32_t)0x00000080U) /*!< Channel 2 Transfer Error flag */ -#define DMA_ISR_GIF3 ((uint32_t)0x00000100U) /*!< Channel 3 Global interrupt flag */ -#define DMA_ISR_TCIF3 ((uint32_t)0x00000200U) /*!< Channel 3 Transfer Complete flag */ -#define DMA_ISR_HTIF3 ((uint32_t)0x00000400U) /*!< Channel 3 Half Transfer flag */ -#define DMA_ISR_TEIF3 ((uint32_t)0x00000800U) /*!< Channel 3 Transfer Error flag */ -#define DMA_ISR_GIF4 ((uint32_t)0x00001000U) /*!< Channel 4 Global interrupt flag */ -#define DMA_ISR_TCIF4 ((uint32_t)0x00002000U) /*!< Channel 4 Transfer Complete flag */ -#define DMA_ISR_HTIF4 ((uint32_t)0x00004000U) /*!< Channel 4 Half Transfer flag */ -#define DMA_ISR_TEIF4 ((uint32_t)0x00008000U) /*!< Channel 4 Transfer Error flag */ -#define DMA_ISR_GIF5 ((uint32_t)0x00010000U) /*!< Channel 5 Global interrupt flag */ -#define DMA_ISR_TCIF5 ((uint32_t)0x00020000U) /*!< Channel 5 Transfer Complete flag */ -#define DMA_ISR_HTIF5 ((uint32_t)0x00040000U) /*!< Channel 5 Half Transfer flag */ -#define DMA_ISR_TEIF5 ((uint32_t)0x00080000U) /*!< Channel 5 Transfer Error flag */ +#define DMA_ISR_GIF1_Pos (0U) +#define DMA_ISR_GIF1_Msk (0x1U << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */ +#define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */ +#define DMA_ISR_TCIF1_Pos (1U) +#define DMA_ISR_TCIF1_Msk (0x1U << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */ +#define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */ +#define DMA_ISR_HTIF1_Pos (2U) +#define DMA_ISR_HTIF1_Msk (0x1U << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */ +#define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */ +#define DMA_ISR_TEIF1_Pos (3U) +#define DMA_ISR_TEIF1_Msk (0x1U << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */ +#define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */ +#define DMA_ISR_GIF2_Pos (4U) +#define DMA_ISR_GIF2_Msk (0x1U << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */ +#define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */ +#define DMA_ISR_TCIF2_Pos (5U) +#define DMA_ISR_TCIF2_Msk (0x1U << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */ +#define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */ +#define DMA_ISR_HTIF2_Pos (6U) +#define DMA_ISR_HTIF2_Msk (0x1U << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */ +#define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */ +#define DMA_ISR_TEIF2_Pos (7U) +#define DMA_ISR_TEIF2_Msk (0x1U << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */ +#define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */ +#define DMA_ISR_GIF3_Pos (8U) +#define DMA_ISR_GIF3_Msk (0x1U << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */ +#define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */ +#define DMA_ISR_TCIF3_Pos (9U) +#define DMA_ISR_TCIF3_Msk (0x1U << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */ +#define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */ +#define DMA_ISR_HTIF3_Pos (10U) +#define DMA_ISR_HTIF3_Msk (0x1U << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */ +#define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */ +#define DMA_ISR_TEIF3_Pos (11U) +#define DMA_ISR_TEIF3_Msk (0x1U << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */ +#define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */ +#define DMA_ISR_GIF4_Pos (12U) +#define DMA_ISR_GIF4_Msk (0x1U << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */ +#define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */ +#define DMA_ISR_TCIF4_Pos (13U) +#define DMA_ISR_TCIF4_Msk (0x1U << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */ +#define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */ +#define DMA_ISR_HTIF4_Pos (14U) +#define DMA_ISR_HTIF4_Msk (0x1U << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */ +#define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */ +#define DMA_ISR_TEIF4_Pos (15U) +#define DMA_ISR_TEIF4_Msk (0x1U << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */ +#define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */ +#define DMA_ISR_GIF5_Pos (16U) +#define DMA_ISR_GIF5_Msk (0x1U << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */ +#define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */ +#define DMA_ISR_TCIF5_Pos (17U) +#define DMA_ISR_TCIF5_Msk (0x1U << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */ +#define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */ +#define DMA_ISR_HTIF5_Pos (18U) +#define DMA_ISR_HTIF5_Msk (0x1U << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */ +#define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */ +#define DMA_ISR_TEIF5_Pos (19U) +#define DMA_ISR_TEIF5_Msk (0x1U << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */ +#define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */ /******************* Bit definition for DMA_IFCR register *******************/ -#define DMA_IFCR_CGIF1 ((uint32_t)0x00000001U) /*!< Channel 1 Global interrupt clear */ -#define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002U) /*!< Channel 1 Transfer Complete clear */ -#define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004U) /*!< Channel 1 Half Transfer clear */ -#define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008U) /*!< Channel 1 Transfer Error clear */ -#define DMA_IFCR_CGIF2 ((uint32_t)0x00000010U) /*!< Channel 2 Global interrupt clear */ -#define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020U) /*!< Channel 2 Transfer Complete clear */ -#define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040U) /*!< Channel 2 Half Transfer clear */ -#define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080U) /*!< Channel 2 Transfer Error clear */ -#define DMA_IFCR_CGIF3 ((uint32_t)0x00000100U) /*!< Channel 3 Global interrupt clear */ -#define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200U) /*!< Channel 3 Transfer Complete clear */ -#define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400U) /*!< Channel 3 Half Transfer clear */ -#define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800U) /*!< Channel 3 Transfer Error clear */ -#define DMA_IFCR_CGIF4 ((uint32_t)0x00001000U) /*!< Channel 4 Global interrupt clear */ -#define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000U) /*!< Channel 4 Transfer Complete clear */ -#define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000U) /*!< Channel 4 Half Transfer clear */ -#define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000U) /*!< Channel 4 Transfer Error clear */ -#define DMA_IFCR_CGIF5 ((uint32_t)0x00010000U) /*!< Channel 5 Global interrupt clear */ -#define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000U) /*!< Channel 5 Transfer Complete clear */ -#define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000U) /*!< Channel 5 Half Transfer clear */ -#define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000U) /*!< Channel 5 Transfer Error clear */ +#define DMA_IFCR_CGIF1_Pos (0U) +#define DMA_IFCR_CGIF1_Msk (0x1U << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */ +#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */ +#define DMA_IFCR_CTCIF1_Pos (1U) +#define DMA_IFCR_CTCIF1_Msk (0x1U << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */ +#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */ +#define DMA_IFCR_CHTIF1_Pos (2U) +#define DMA_IFCR_CHTIF1_Msk (0x1U << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */ +#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */ +#define DMA_IFCR_CTEIF1_Pos (3U) +#define DMA_IFCR_CTEIF1_Msk (0x1U << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */ +#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */ +#define DMA_IFCR_CGIF2_Pos (4U) +#define DMA_IFCR_CGIF2_Msk (0x1U << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */ +#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */ +#define DMA_IFCR_CTCIF2_Pos (5U) +#define DMA_IFCR_CTCIF2_Msk (0x1U << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */ +#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */ +#define DMA_IFCR_CHTIF2_Pos (6U) +#define DMA_IFCR_CHTIF2_Msk (0x1U << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */ +#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */ +#define DMA_IFCR_CTEIF2_Pos (7U) +#define DMA_IFCR_CTEIF2_Msk (0x1U << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */ +#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */ +#define DMA_IFCR_CGIF3_Pos (8U) +#define DMA_IFCR_CGIF3_Msk (0x1U << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */ +#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */ +#define DMA_IFCR_CTCIF3_Pos (9U) +#define DMA_IFCR_CTCIF3_Msk (0x1U << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */ +#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */ +#define DMA_IFCR_CHTIF3_Pos (10U) +#define DMA_IFCR_CHTIF3_Msk (0x1U << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */ +#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */ +#define DMA_IFCR_CTEIF3_Pos (11U) +#define DMA_IFCR_CTEIF3_Msk (0x1U << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */ +#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */ +#define DMA_IFCR_CGIF4_Pos (12U) +#define DMA_IFCR_CGIF4_Msk (0x1U << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */ +#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */ +#define DMA_IFCR_CTCIF4_Pos (13U) +#define DMA_IFCR_CTCIF4_Msk (0x1U << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */ +#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */ +#define DMA_IFCR_CHTIF4_Pos (14U) +#define DMA_IFCR_CHTIF4_Msk (0x1U << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */ +#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */ +#define DMA_IFCR_CTEIF4_Pos (15U) +#define DMA_IFCR_CTEIF4_Msk (0x1U << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */ +#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */ +#define DMA_IFCR_CGIF5_Pos (16U) +#define DMA_IFCR_CGIF5_Msk (0x1U << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */ +#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */ +#define DMA_IFCR_CTCIF5_Pos (17U) +#define DMA_IFCR_CTCIF5_Msk (0x1U << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */ +#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */ +#define DMA_IFCR_CHTIF5_Pos (18U) +#define DMA_IFCR_CHTIF5_Msk (0x1U << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */ +#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */ +#define DMA_IFCR_CTEIF5_Pos (19U) +#define DMA_IFCR_CTEIF5_Msk (0x1U << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */ +#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */ /******************* Bit definition for DMA_CCR register ********************/ -#define DMA_CCR_EN ((uint32_t)0x00000001U) /*!< Channel enable */ -#define DMA_CCR_TCIE ((uint32_t)0x00000002U) /*!< Transfer complete interrupt enable */ -#define DMA_CCR_HTIE ((uint32_t)0x00000004U) /*!< Half Transfer interrupt enable */ -#define DMA_CCR_TEIE ((uint32_t)0x00000008U) /*!< Transfer error interrupt enable */ -#define DMA_CCR_DIR ((uint32_t)0x00000010U) /*!< Data transfer direction */ -#define DMA_CCR_CIRC ((uint32_t)0x00000020U) /*!< Circular mode */ -#define DMA_CCR_PINC ((uint32_t)0x00000040U) /*!< Peripheral increment mode */ -#define DMA_CCR_MINC ((uint32_t)0x00000080U) /*!< Memory increment mode */ +#define DMA_CCR_EN_Pos (0U) +#define DMA_CCR_EN_Msk (0x1U << DMA_CCR_EN_Pos) /*!< 0x00000001 */ +#define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */ +#define DMA_CCR_TCIE_Pos (1U) +#define DMA_CCR_TCIE_Msk (0x1U << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */ +#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */ +#define DMA_CCR_HTIE_Pos (2U) +#define DMA_CCR_HTIE_Msk (0x1U << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */ +#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */ +#define DMA_CCR_TEIE_Pos (3U) +#define DMA_CCR_TEIE_Msk (0x1U << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */ +#define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */ +#define DMA_CCR_DIR_Pos (4U) +#define DMA_CCR_DIR_Msk (0x1U << DMA_CCR_DIR_Pos) /*!< 0x00000010 */ +#define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */ +#define DMA_CCR_CIRC_Pos (5U) +#define DMA_CCR_CIRC_Msk (0x1U << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */ +#define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */ +#define DMA_CCR_PINC_Pos (6U) +#define DMA_CCR_PINC_Msk (0x1U << DMA_CCR_PINC_Pos) /*!< 0x00000040 */ +#define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */ +#define DMA_CCR_MINC_Pos (7U) +#define DMA_CCR_MINC_Msk (0x1U << DMA_CCR_MINC_Pos) /*!< 0x00000080 */ +#define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */ -#define DMA_CCR_PSIZE ((uint32_t)0x00000300U) /*!< PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CCR_PSIZE_0 ((uint32_t)0x00000100U) /*!< Bit 0 */ -#define DMA_CCR_PSIZE_1 ((uint32_t)0x00000200U) /*!< Bit 1 */ +#define DMA_CCR_PSIZE_Pos (8U) +#define DMA_CCR_PSIZE_Msk (0x3U << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */ +#define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CCR_PSIZE_0 (0x1U << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */ +#define DMA_CCR_PSIZE_1 (0x2U << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */ -#define DMA_CCR_MSIZE ((uint32_t)0x00000C00U) /*!< MSIZE[1:0] bits (Memory size) */ -#define DMA_CCR_MSIZE_0 ((uint32_t)0x00000400U) /*!< Bit 0 */ -#define DMA_CCR_MSIZE_1 ((uint32_t)0x00000800U) /*!< Bit 1 */ +#define DMA_CCR_MSIZE_Pos (10U) +#define DMA_CCR_MSIZE_Msk (0x3U << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */ +#define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */ +#define DMA_CCR_MSIZE_0 (0x1U << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */ +#define DMA_CCR_MSIZE_1 (0x2U << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */ -#define DMA_CCR_PL ((uint32_t)0x00003000U) /*!< PL[1:0] bits(Channel Priority level)*/ -#define DMA_CCR_PL_0 ((uint32_t)0x00001000U) /*!< Bit 0 */ -#define DMA_CCR_PL_1 ((uint32_t)0x00002000U) /*!< Bit 1 */ +#define DMA_CCR_PL_Pos (12U) +#define DMA_CCR_PL_Msk (0x3U << DMA_CCR_PL_Pos) /*!< 0x00003000 */ +#define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/ +#define DMA_CCR_PL_0 (0x1U << DMA_CCR_PL_Pos) /*!< 0x00001000 */ +#define DMA_CCR_PL_1 (0x2U << DMA_CCR_PL_Pos) /*!< 0x00002000 */ -#define DMA_CCR_MEM2MEM ((uint32_t)0x00004000U) /*!< Memory to memory mode */ +#define DMA_CCR_MEM2MEM_Pos (14U) +#define DMA_CCR_MEM2MEM_Msk (0x1U << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */ +#define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */ /****************** Bit definition for DMA_CNDTR register *******************/ -#define DMA_CNDTR_NDT ((uint32_t)0x0000FFFFU) /*!< Number of data to Transfer */ +#define DMA_CNDTR_NDT_Pos (0U) +#define DMA_CNDTR_NDT_Msk (0xFFFFU << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */ +#define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */ /****************** Bit definition for DMA_CPAR register ********************/ -#define DMA_CPAR_PA ((uint32_t)0xFFFFFFFFU) /*!< Peripheral Address */ +#define DMA_CPAR_PA_Pos (0U) +#define DMA_CPAR_PA_Msk (0xFFFFFFFFU << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */ +#define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */ /****************** Bit definition for DMA_CMAR register ********************/ -#define DMA_CMAR_MA ((uint32_t)0xFFFFFFFFU) /*!< Memory Address */ +#define DMA_CMAR_MA_Pos (0U) +#define DMA_CMAR_MA_Msk (0xFFFFFFFFU << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */ +#define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */ /******************************************************************************/ /* */ @@ -1184,31 +1614,81 @@ typedef struct /* */ /******************************************************************************/ /******************* Bit definition for EXTI_IMR register *******************/ -#define EXTI_IMR_MR0 ((uint32_t)0x00000001U) /*!< Interrupt Mask on line 0 */ -#define EXTI_IMR_MR1 ((uint32_t)0x00000002U) /*!< Interrupt Mask on line 1 */ -#define EXTI_IMR_MR2 ((uint32_t)0x00000004U) /*!< Interrupt Mask on line 2 */ -#define EXTI_IMR_MR3 ((uint32_t)0x00000008U) /*!< Interrupt Mask on line 3 */ -#define EXTI_IMR_MR4 ((uint32_t)0x00000010U) /*!< Interrupt Mask on line 4 */ -#define EXTI_IMR_MR5 ((uint32_t)0x00000020U) /*!< Interrupt Mask on line 5 */ -#define EXTI_IMR_MR6 ((uint32_t)0x00000040U) /*!< Interrupt Mask on line 6 */ -#define EXTI_IMR_MR7 ((uint32_t)0x00000080U) /*!< Interrupt Mask on line 7 */ -#define EXTI_IMR_MR8 ((uint32_t)0x00000100U) /*!< Interrupt Mask on line 8 */ -#define EXTI_IMR_MR9 ((uint32_t)0x00000200U) /*!< Interrupt Mask on line 9 */ -#define EXTI_IMR_MR10 ((uint32_t)0x00000400U) /*!< Interrupt Mask on line 10 */ -#define EXTI_IMR_MR11 ((uint32_t)0x00000800U) /*!< Interrupt Mask on line 11 */ -#define EXTI_IMR_MR12 ((uint32_t)0x00001000U) /*!< Interrupt Mask on line 12 */ -#define EXTI_IMR_MR13 ((uint32_t)0x00002000U) /*!< Interrupt Mask on line 13 */ -#define EXTI_IMR_MR14 ((uint32_t)0x00004000U) /*!< Interrupt Mask on line 14 */ -#define EXTI_IMR_MR15 ((uint32_t)0x00008000U) /*!< Interrupt Mask on line 15 */ -#define EXTI_IMR_MR16 ((uint32_t)0x00010000U) /*!< Interrupt Mask on line 16 */ -#define EXTI_IMR_MR17 ((uint32_t)0x00020000U) /*!< Interrupt Mask on line 17 */ -#define EXTI_IMR_MR18 ((uint32_t)0x00040000U) /*!< Interrupt Mask on line 18 */ -#define EXTI_IMR_MR19 ((uint32_t)0x00080000U) /*!< Interrupt Mask on line 19 */ -#define EXTI_IMR_MR21 ((uint32_t)0x00200000U) /*!< Interrupt Mask on line 21 */ -#define EXTI_IMR_MR22 ((uint32_t)0x00400000U) /*!< Interrupt Mask on line 22 */ -#define EXTI_IMR_MR23 ((uint32_t)0x00800000U) /*!< Interrupt Mask on line 23 */ -#define EXTI_IMR_MR25 ((uint32_t)0x02000000U) /*!< Interrupt Mask on line 25 */ -#define EXTI_IMR_MR27 ((uint32_t)0x08000000U) /*!< Interrupt Mask on line 27 */ +#define EXTI_IMR_MR0_Pos (0U) +#define EXTI_IMR_MR0_Msk (0x1U << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */ +#define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */ +#define EXTI_IMR_MR1_Pos (1U) +#define EXTI_IMR_MR1_Msk (0x1U << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */ +#define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */ +#define EXTI_IMR_MR2_Pos (2U) +#define EXTI_IMR_MR2_Msk (0x1U << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */ +#define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */ +#define EXTI_IMR_MR3_Pos (3U) +#define EXTI_IMR_MR3_Msk (0x1U << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */ +#define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */ +#define EXTI_IMR_MR4_Pos (4U) +#define EXTI_IMR_MR4_Msk (0x1U << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */ +#define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */ +#define EXTI_IMR_MR5_Pos (5U) +#define EXTI_IMR_MR5_Msk (0x1U << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */ +#define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */ +#define EXTI_IMR_MR6_Pos (6U) +#define EXTI_IMR_MR6_Msk (0x1U << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */ +#define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */ +#define EXTI_IMR_MR7_Pos (7U) +#define EXTI_IMR_MR7_Msk (0x1U << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */ +#define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */ +#define EXTI_IMR_MR8_Pos (8U) +#define EXTI_IMR_MR8_Msk (0x1U << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */ +#define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */ +#define EXTI_IMR_MR9_Pos (9U) +#define EXTI_IMR_MR9_Msk (0x1U << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */ +#define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */ +#define EXTI_IMR_MR10_Pos (10U) +#define EXTI_IMR_MR10_Msk (0x1U << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */ +#define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */ +#define EXTI_IMR_MR11_Pos (11U) +#define EXTI_IMR_MR11_Msk (0x1U << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */ +#define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */ +#define EXTI_IMR_MR12_Pos (12U) +#define EXTI_IMR_MR12_Msk (0x1U << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */ +#define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */ +#define EXTI_IMR_MR13_Pos (13U) +#define EXTI_IMR_MR13_Msk (0x1U << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */ +#define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */ +#define EXTI_IMR_MR14_Pos (14U) +#define EXTI_IMR_MR14_Msk (0x1U << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */ +#define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */ +#define EXTI_IMR_MR15_Pos (15U) +#define EXTI_IMR_MR15_Msk (0x1U << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */ +#define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */ +#define EXTI_IMR_MR16_Pos (16U) +#define EXTI_IMR_MR16_Msk (0x1U << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */ +#define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */ +#define EXTI_IMR_MR17_Pos (17U) +#define EXTI_IMR_MR17_Msk (0x1U << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */ +#define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */ +#define EXTI_IMR_MR18_Pos (18U) +#define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */ +#define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */ +#define EXTI_IMR_MR19_Pos (19U) +#define EXTI_IMR_MR19_Msk (0x1U << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */ +#define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */ +#define EXTI_IMR_MR21_Pos (21U) +#define EXTI_IMR_MR21_Msk (0x1U << EXTI_IMR_MR21_Pos) /*!< 0x00200000 */ +#define EXTI_IMR_MR21 EXTI_IMR_MR21_Msk /*!< Interrupt Mask on line 21 */ +#define EXTI_IMR_MR22_Pos (22U) +#define EXTI_IMR_MR22_Msk (0x1U << EXTI_IMR_MR22_Pos) /*!< 0x00400000 */ +#define EXTI_IMR_MR22 EXTI_IMR_MR22_Msk /*!< Interrupt Mask on line 22 */ +#define EXTI_IMR_MR23_Pos (23U) +#define EXTI_IMR_MR23_Msk (0x1U << EXTI_IMR_MR23_Pos) /*!< 0x00800000 */ +#define EXTI_IMR_MR23 EXTI_IMR_MR23_Msk /*!< Interrupt Mask on line 23 */ +#define EXTI_IMR_MR25_Pos (25U) +#define EXTI_IMR_MR25_Msk (0x1U << EXTI_IMR_MR25_Pos) /*!< 0x02000000 */ +#define EXTI_IMR_MR25 EXTI_IMR_MR25_Msk /*!< Interrupt Mask on line 25 */ +#define EXTI_IMR_MR27_Pos (27U) +#define EXTI_IMR_MR27_Msk (0x1U << EXTI_IMR_MR27_Pos) /*!< 0x08000000 */ +#define EXTI_IMR_MR27 EXTI_IMR_MR27_Msk /*!< Interrupt Mask on line 27 */ /* References Defines */ #define EXTI_IMR_IM0 EXTI_IMR_MR0 @@ -1237,32 +1717,87 @@ typedef struct #define EXTI_IMR_IM25 EXTI_IMR_MR25 #define EXTI_IMR_IM27 EXTI_IMR_MR27 +#define EXTI_IMR_IM_Pos (0U) +#define EXTI_IMR_IM_Msk (0xAEFFFFFU << EXTI_IMR_IM_Pos) /*!< 0x0AEFFFFF */ +#define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */ + + /****************** Bit definition for EXTI_EMR register ********************/ -#define EXTI_EMR_MR0 ((uint32_t)0x00000001U) /*!< Event Mask on line 0 */ -#define EXTI_EMR_MR1 ((uint32_t)0x00000002U) /*!< Event Mask on line 1 */ -#define EXTI_EMR_MR2 ((uint32_t)0x00000004U) /*!< Event Mask on line 2 */ -#define EXTI_EMR_MR3 ((uint32_t)0x00000008U) /*!< Event Mask on line 3 */ -#define EXTI_EMR_MR4 ((uint32_t)0x00000010U) /*!< Event Mask on line 4 */ -#define EXTI_EMR_MR5 ((uint32_t)0x00000020U) /*!< Event Mask on line 5 */ -#define EXTI_EMR_MR6 ((uint32_t)0x00000040U) /*!< Event Mask on line 6 */ -#define EXTI_EMR_MR7 ((uint32_t)0x00000080U) /*!< Event Mask on line 7 */ -#define EXTI_EMR_MR8 ((uint32_t)0x00000100U) /*!< Event Mask on line 8 */ -#define EXTI_EMR_MR9 ((uint32_t)0x00000200U) /*!< Event Mask on line 9 */ -#define EXTI_EMR_MR10 ((uint32_t)0x00000400U) /*!< Event Mask on line 10 */ -#define EXTI_EMR_MR11 ((uint32_t)0x00000800U) /*!< Event Mask on line 11 */ -#define EXTI_EMR_MR12 ((uint32_t)0x00001000U) /*!< Event Mask on line 12 */ -#define EXTI_EMR_MR13 ((uint32_t)0x00002000U) /*!< Event Mask on line 13 */ -#define EXTI_EMR_MR14 ((uint32_t)0x00004000U) /*!< Event Mask on line 14 */ -#define EXTI_EMR_MR15 ((uint32_t)0x00008000U) /*!< Event Mask on line 15 */ -#define EXTI_EMR_MR16 ((uint32_t)0x00010000U) /*!< Event Mask on line 16 */ -#define EXTI_EMR_MR17 ((uint32_t)0x00020000U) /*!< Event Mask on line 17 */ -#define EXTI_EMR_MR18 ((uint32_t)0x00040000U) /*!< Event Mask on line 18 */ -#define EXTI_EMR_MR19 ((uint32_t)0x00080000U) /*!< Event Mask on line 19 */ -#define EXTI_EMR_MR21 ((uint32_t)0x00200000U) /*!< Event Mask on line 21 */ -#define EXTI_EMR_MR22 ((uint32_t)0x00400000U) /*!< Event Mask on line 22 */ -#define EXTI_EMR_MR23 ((uint32_t)0x00800000U) /*!< Event Mask on line 23 */ -#define EXTI_EMR_MR25 ((uint32_t)0x02000000U) /*!< Event Mask on line 25 */ -#define EXTI_EMR_MR27 ((uint32_t)0x08000000U) /*!< Event Mask on line 27 */ +#define EXTI_EMR_MR0_Pos (0U) +#define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */ +#define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */ +#define EXTI_EMR_MR1_Pos (1U) +#define EXTI_EMR_MR1_Msk (0x1U << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */ +#define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */ +#define EXTI_EMR_MR2_Pos (2U) +#define EXTI_EMR_MR2_Msk (0x1U << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */ +#define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */ +#define EXTI_EMR_MR3_Pos (3U) +#define EXTI_EMR_MR3_Msk (0x1U << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */ +#define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */ +#define EXTI_EMR_MR4_Pos (4U) +#define EXTI_EMR_MR4_Msk (0x1U << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */ +#define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */ +#define EXTI_EMR_MR5_Pos (5U) +#define EXTI_EMR_MR5_Msk (0x1U << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */ +#define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */ +#define EXTI_EMR_MR6_Pos (6U) +#define EXTI_EMR_MR6_Msk (0x1U << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */ +#define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */ +#define EXTI_EMR_MR7_Pos (7U) +#define EXTI_EMR_MR7_Msk (0x1U << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */ +#define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */ +#define EXTI_EMR_MR8_Pos (8U) +#define EXTI_EMR_MR8_Msk (0x1U << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */ +#define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */ +#define EXTI_EMR_MR9_Pos (9U) +#define EXTI_EMR_MR9_Msk (0x1U << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */ +#define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */ +#define EXTI_EMR_MR10_Pos (10U) +#define EXTI_EMR_MR10_Msk (0x1U << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */ +#define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */ +#define EXTI_EMR_MR11_Pos (11U) +#define EXTI_EMR_MR11_Msk (0x1U << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */ +#define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */ +#define EXTI_EMR_MR12_Pos (12U) +#define EXTI_EMR_MR12_Msk (0x1U << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */ +#define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */ +#define EXTI_EMR_MR13_Pos (13U) +#define EXTI_EMR_MR13_Msk (0x1U << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */ +#define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */ +#define EXTI_EMR_MR14_Pos (14U) +#define EXTI_EMR_MR14_Msk (0x1U << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */ +#define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */ +#define EXTI_EMR_MR15_Pos (15U) +#define EXTI_EMR_MR15_Msk (0x1U << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */ +#define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */ +#define EXTI_EMR_MR16_Pos (16U) +#define EXTI_EMR_MR16_Msk (0x1U << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */ +#define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */ +#define EXTI_EMR_MR17_Pos (17U) +#define EXTI_EMR_MR17_Msk (0x1U << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */ +#define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */ +#define EXTI_EMR_MR18_Pos (18U) +#define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */ +#define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */ +#define EXTI_EMR_MR19_Pos (19U) +#define EXTI_EMR_MR19_Msk (0x1U << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */ +#define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */ +#define EXTI_EMR_MR21_Pos (21U) +#define EXTI_EMR_MR21_Msk (0x1U << EXTI_EMR_MR21_Pos) /*!< 0x00200000 */ +#define EXTI_EMR_MR21 EXTI_EMR_MR21_Msk /*!< Event Mask on line 21 */ +#define EXTI_EMR_MR22_Pos (22U) +#define EXTI_EMR_MR22_Msk (0x1U << EXTI_EMR_MR22_Pos) /*!< 0x00400000 */ +#define EXTI_EMR_MR22 EXTI_EMR_MR22_Msk /*!< Event Mask on line 22 */ +#define EXTI_EMR_MR23_Pos (23U) +#define EXTI_EMR_MR23_Msk (0x1U << EXTI_EMR_MR23_Pos) /*!< 0x00800000 */ +#define EXTI_EMR_MR23 EXTI_EMR_MR23_Msk /*!< Event Mask on line 23 */ +#define EXTI_EMR_MR25_Pos (25U) +#define EXTI_EMR_MR25_Msk (0x1U << EXTI_EMR_MR25_Pos) /*!< 0x02000000 */ +#define EXTI_EMR_MR25 EXTI_EMR_MR25_Msk /*!< Event Mask on line 25 */ +#define EXTI_EMR_MR27_Pos (27U) +#define EXTI_EMR_MR27_Msk (0x1U << EXTI_EMR_MR27_Pos) /*!< 0x08000000 */ +#define EXTI_EMR_MR27 EXTI_EMR_MR27_Msk /*!< Event Mask on line 27 */ /* References Defines */ #define EXTI_EMR_EM0 EXTI_EMR_MR0 @@ -1292,27 +1827,69 @@ typedef struct #define EXTI_EMR_EM27 EXTI_EMR_MR27 /******************* Bit definition for EXTI_RTSR register ******************/ -#define EXTI_RTSR_TR0 ((uint32_t)0x00000001U) /*!< Rising trigger event configuration bit of line 0 */ -#define EXTI_RTSR_TR1 ((uint32_t)0x00000002U) /*!< Rising trigger event configuration bit of line 1 */ -#define EXTI_RTSR_TR2 ((uint32_t)0x00000004U) /*!< Rising trigger event configuration bit of line 2 */ -#define EXTI_RTSR_TR3 ((uint32_t)0x00000008U) /*!< Rising trigger event configuration bit of line 3 */ -#define EXTI_RTSR_TR4 ((uint32_t)0x00000010U) /*!< Rising trigger event configuration bit of line 4 */ -#define EXTI_RTSR_TR5 ((uint32_t)0x00000020U) /*!< Rising trigger event configuration bit of line 5 */ -#define EXTI_RTSR_TR6 ((uint32_t)0x00000040U) /*!< Rising trigger event configuration bit of line 6 */ -#define EXTI_RTSR_TR7 ((uint32_t)0x00000080U) /*!< Rising trigger event configuration bit of line 7 */ -#define EXTI_RTSR_TR8 ((uint32_t)0x00000100U) /*!< Rising trigger event configuration bit of line 8 */ -#define EXTI_RTSR_TR9 ((uint32_t)0x00000200U) /*!< Rising trigger event configuration bit of line 9 */ -#define EXTI_RTSR_TR10 ((uint32_t)0x00000400U) /*!< Rising trigger event configuration bit of line 10 */ -#define EXTI_RTSR_TR11 ((uint32_t)0x00000800U) /*!< Rising trigger event configuration bit of line 11 */ -#define EXTI_RTSR_TR12 ((uint32_t)0x00001000U) /*!< Rising trigger event configuration bit of line 12 */ -#define EXTI_RTSR_TR13 ((uint32_t)0x00002000U) /*!< Rising trigger event configuration bit of line 13 */ -#define EXTI_RTSR_TR14 ((uint32_t)0x00004000U) /*!< Rising trigger event configuration bit of line 14 */ -#define EXTI_RTSR_TR15 ((uint32_t)0x00008000U) /*!< Rising trigger event configuration bit of line 15 */ -#define EXTI_RTSR_TR16 ((uint32_t)0x00010000U) /*!< Rising trigger event configuration bit of line 16 */ -#define EXTI_RTSR_TR17 ((uint32_t)0x00020000U) /*!< Rising trigger event configuration bit of line 17 */ -#define EXTI_RTSR_TR19 ((uint32_t)0x00080000U) /*!< Rising trigger event configuration bit of line 19 */ -#define EXTI_RTSR_TR21 ((uint32_t)0x00200000U) /*!< Rising trigger event configuration bit of line 21 */ -#define EXTI_RTSR_TR22 ((uint32_t)0x00400000U) /*!< Rising trigger event configuration bit of line 22 */ +#define EXTI_RTSR_TR0_Pos (0U) +#define EXTI_RTSR_TR0_Msk (0x1U << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */ +#define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */ +#define EXTI_RTSR_TR1_Pos (1U) +#define EXTI_RTSR_TR1_Msk (0x1U << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */ +#define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */ +#define EXTI_RTSR_TR2_Pos (2U) +#define EXTI_RTSR_TR2_Msk (0x1U << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */ +#define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */ +#define EXTI_RTSR_TR3_Pos (3U) +#define EXTI_RTSR_TR3_Msk (0x1U << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */ +#define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */ +#define EXTI_RTSR_TR4_Pos (4U) +#define EXTI_RTSR_TR4_Msk (0x1U << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */ +#define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */ +#define EXTI_RTSR_TR5_Pos (5U) +#define EXTI_RTSR_TR5_Msk (0x1U << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */ +#define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */ +#define EXTI_RTSR_TR6_Pos (6U) +#define EXTI_RTSR_TR6_Msk (0x1U << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */ +#define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */ +#define EXTI_RTSR_TR7_Pos (7U) +#define EXTI_RTSR_TR7_Msk (0x1U << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */ +#define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */ +#define EXTI_RTSR_TR8_Pos (8U) +#define EXTI_RTSR_TR8_Msk (0x1U << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */ +#define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */ +#define EXTI_RTSR_TR9_Pos (9U) +#define EXTI_RTSR_TR9_Msk (0x1U << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */ +#define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */ +#define EXTI_RTSR_TR10_Pos (10U) +#define EXTI_RTSR_TR10_Msk (0x1U << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */ +#define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */ +#define EXTI_RTSR_TR11_Pos (11U) +#define EXTI_RTSR_TR11_Msk (0x1U << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */ +#define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */ +#define EXTI_RTSR_TR12_Pos (12U) +#define EXTI_RTSR_TR12_Msk (0x1U << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */ +#define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */ +#define EXTI_RTSR_TR13_Pos (13U) +#define EXTI_RTSR_TR13_Msk (0x1U << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */ +#define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */ +#define EXTI_RTSR_TR14_Pos (14U) +#define EXTI_RTSR_TR14_Msk (0x1U << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */ +#define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */ +#define EXTI_RTSR_TR15_Pos (15U) +#define EXTI_RTSR_TR15_Msk (0x1U << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */ +#define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */ +#define EXTI_RTSR_TR16_Pos (16U) +#define EXTI_RTSR_TR16_Msk (0x1U << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */ +#define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */ +#define EXTI_RTSR_TR17_Pos (17U) +#define EXTI_RTSR_TR17_Msk (0x1U << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */ +#define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */ +#define EXTI_RTSR_TR19_Pos (19U) +#define EXTI_RTSR_TR19_Msk (0x1U << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */ +#define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */ +#define EXTI_RTSR_TR21_Pos (21U) +#define EXTI_RTSR_TR21_Msk (0x1U << EXTI_RTSR_TR21_Pos) /*!< 0x00200000 */ +#define EXTI_RTSR_TR21 EXTI_RTSR_TR21_Msk /*!< Rising trigger event configuration bit of line 21 */ +#define EXTI_RTSR_TR22_Pos (22U) +#define EXTI_RTSR_TR22_Msk (0x1U << EXTI_RTSR_TR22_Pos) /*!< 0x00400000 */ +#define EXTI_RTSR_TR22 EXTI_RTSR_TR22_Msk /*!< Rising trigger event configuration bit of line 22 */ /* References Defines */ #define EXTI_RTSR_RT0 EXTI_RTSR_TR0 @@ -1338,27 +1915,69 @@ typedef struct #define EXTI_RTSR_RT22 EXTI_RTSR_TR22 /******************* Bit definition for EXTI_FTSR register *******************/ -#define EXTI_FTSR_TR0 ((uint32_t)0x00000001U) /*!< Falling trigger event configuration bit of line 0 */ -#define EXTI_FTSR_TR1 ((uint32_t)0x00000002U) /*!< Falling trigger event configuration bit of line 1 */ -#define EXTI_FTSR_TR2 ((uint32_t)0x00000004U) /*!< Falling trigger event configuration bit of line 2 */ -#define EXTI_FTSR_TR3 ((uint32_t)0x00000008U) /*!< Falling trigger event configuration bit of line 3 */ -#define EXTI_FTSR_TR4 ((uint32_t)0x00000010U) /*!< Falling trigger event configuration bit of line 4 */ -#define EXTI_FTSR_TR5 ((uint32_t)0x00000020U) /*!< Falling trigger event configuration bit of line 5 */ -#define EXTI_FTSR_TR6 ((uint32_t)0x00000040U) /*!< Falling trigger event configuration bit of line 6 */ -#define EXTI_FTSR_TR7 ((uint32_t)0x00000080U) /*!< Falling trigger event configuration bit of line 7 */ -#define EXTI_FTSR_TR8 ((uint32_t)0x00000100U) /*!< Falling trigger event configuration bit of line 8 */ -#define EXTI_FTSR_TR9 ((uint32_t)0x00000200U) /*!< Falling trigger event configuration bit of line 9 */ -#define EXTI_FTSR_TR10 ((uint32_t)0x00000400U) /*!< Falling trigger event configuration bit of line 10 */ -#define EXTI_FTSR_TR11 ((uint32_t)0x00000800U) /*!< Falling trigger event configuration bit of line 11 */ -#define EXTI_FTSR_TR12 ((uint32_t)0x00001000U) /*!< Falling trigger event configuration bit of line 12 */ -#define EXTI_FTSR_TR13 ((uint32_t)0x00002000U) /*!< Falling trigger event configuration bit of line 13 */ -#define EXTI_FTSR_TR14 ((uint32_t)0x00004000U) /*!< Falling trigger event configuration bit of line 14 */ -#define EXTI_FTSR_TR15 ((uint32_t)0x00008000U) /*!< Falling trigger event configuration bit of line 15 */ -#define EXTI_FTSR_TR16 ((uint32_t)0x00010000U) /*!< Falling trigger event configuration bit of line 16 */ -#define EXTI_FTSR_TR17 ((uint32_t)0x00020000U) /*!< Falling trigger event configuration bit of line 17 */ -#define EXTI_FTSR_TR19 ((uint32_t)0x00080000U) /*!< Falling trigger event configuration bit of line 19 */ -#define EXTI_FTSR_TR21 ((uint32_t)0x00200000U) /*!< Falling trigger event configuration bit of line 21 */ -#define EXTI_FTSR_TR22 ((uint32_t)0x00400000U) /*!< Falling trigger event configuration bit of line 22 */ +#define EXTI_FTSR_TR0_Pos (0U) +#define EXTI_FTSR_TR0_Msk (0x1U << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */ +#define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */ +#define EXTI_FTSR_TR1_Pos (1U) +#define EXTI_FTSR_TR1_Msk (0x1U << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */ +#define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */ +#define EXTI_FTSR_TR2_Pos (2U) +#define EXTI_FTSR_TR2_Msk (0x1U << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */ +#define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */ +#define EXTI_FTSR_TR3_Pos (3U) +#define EXTI_FTSR_TR3_Msk (0x1U << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */ +#define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */ +#define EXTI_FTSR_TR4_Pos (4U) +#define EXTI_FTSR_TR4_Msk (0x1U << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */ +#define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */ +#define EXTI_FTSR_TR5_Pos (5U) +#define EXTI_FTSR_TR5_Msk (0x1U << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */ +#define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */ +#define EXTI_FTSR_TR6_Pos (6U) +#define EXTI_FTSR_TR6_Msk (0x1U << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */ +#define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */ +#define EXTI_FTSR_TR7_Pos (7U) +#define EXTI_FTSR_TR7_Msk (0x1U << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */ +#define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */ +#define EXTI_FTSR_TR8_Pos (8U) +#define EXTI_FTSR_TR8_Msk (0x1U << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */ +#define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */ +#define EXTI_FTSR_TR9_Pos (9U) +#define EXTI_FTSR_TR9_Msk (0x1U << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */ +#define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */ +#define EXTI_FTSR_TR10_Pos (10U) +#define EXTI_FTSR_TR10_Msk (0x1U << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */ +#define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */ +#define EXTI_FTSR_TR11_Pos (11U) +#define EXTI_FTSR_TR11_Msk (0x1U << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */ +#define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */ +#define EXTI_FTSR_TR12_Pos (12U) +#define EXTI_FTSR_TR12_Msk (0x1U << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */ +#define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */ +#define EXTI_FTSR_TR13_Pos (13U) +#define EXTI_FTSR_TR13_Msk (0x1U << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */ +#define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */ +#define EXTI_FTSR_TR14_Pos (14U) +#define EXTI_FTSR_TR14_Msk (0x1U << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */ +#define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */ +#define EXTI_FTSR_TR15_Pos (15U) +#define EXTI_FTSR_TR15_Msk (0x1U << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */ +#define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */ +#define EXTI_FTSR_TR16_Pos (16U) +#define EXTI_FTSR_TR16_Msk (0x1U << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */ +#define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */ +#define EXTI_FTSR_TR17_Pos (17U) +#define EXTI_FTSR_TR17_Msk (0x1U << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */ +#define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */ +#define EXTI_FTSR_TR19_Pos (19U) +#define EXTI_FTSR_TR19_Msk (0x1U << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */ +#define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */ +#define EXTI_FTSR_TR21_Pos (21U) +#define EXTI_FTSR_TR21_Msk (0x1U << EXTI_FTSR_TR21_Pos) /*!< 0x00200000 */ +#define EXTI_FTSR_TR21 EXTI_FTSR_TR21_Msk /*!< Falling trigger event configuration bit of line 21 */ +#define EXTI_FTSR_TR22_Pos (22U) +#define EXTI_FTSR_TR22_Msk (0x1U << EXTI_FTSR_TR22_Pos) /*!< 0x00400000 */ +#define EXTI_FTSR_TR22 EXTI_FTSR_TR22_Msk /*!< Falling trigger event configuration bit of line 22 */ /* References Defines */ #define EXTI_FTSR_FT0 EXTI_FTSR_TR0 @@ -1384,27 +2003,69 @@ typedef struct #define EXTI_FTSR_FT22 EXTI_FTSR_TR22 /******************* Bit definition for EXTI_SWIER register *******************/ -#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001U) /*!< Software Interrupt on line 0 */ -#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002U) /*!< Software Interrupt on line 1 */ -#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004U) /*!< Software Interrupt on line 2 */ -#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008U) /*!< Software Interrupt on line 3 */ -#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010U) /*!< Software Interrupt on line 4 */ -#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020U) /*!< Software Interrupt on line 5 */ -#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040U) /*!< Software Interrupt on line 6 */ -#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080U) /*!< Software Interrupt on line 7 */ -#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100U) /*!< Software Interrupt on line 8 */ -#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200U) /*!< Software Interrupt on line 9 */ -#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400U) /*!< Software Interrupt on line 10 */ -#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800U) /*!< Software Interrupt on line 11 */ -#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000U) /*!< Software Interrupt on line 12 */ -#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000U) /*!< Software Interrupt on line 13 */ -#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000U) /*!< Software Interrupt on line 14 */ -#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000U) /*!< Software Interrupt on line 15 */ -#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000U) /*!< Software Interrupt on line 16 */ -#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000U) /*!< Software Interrupt on line 17 */ -#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000U) /*!< Software Interrupt on line 19 */ -#define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000U) /*!< Software Interrupt on line 21 */ -#define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000U) /*!< Software Interrupt on line 22 */ +#define EXTI_SWIER_SWIER0_Pos (0U) +#define EXTI_SWIER_SWIER0_Msk (0x1U << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */ +#define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */ +#define EXTI_SWIER_SWIER1_Pos (1U) +#define EXTI_SWIER_SWIER1_Msk (0x1U << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */ +#define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */ +#define EXTI_SWIER_SWIER2_Pos (2U) +#define EXTI_SWIER_SWIER2_Msk (0x1U << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */ +#define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */ +#define EXTI_SWIER_SWIER3_Pos (3U) +#define EXTI_SWIER_SWIER3_Msk (0x1U << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */ +#define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */ +#define EXTI_SWIER_SWIER4_Pos (4U) +#define EXTI_SWIER_SWIER4_Msk (0x1U << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */ +#define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */ +#define EXTI_SWIER_SWIER5_Pos (5U) +#define EXTI_SWIER_SWIER5_Msk (0x1U << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */ +#define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */ +#define EXTI_SWIER_SWIER6_Pos (6U) +#define EXTI_SWIER_SWIER6_Msk (0x1U << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */ +#define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */ +#define EXTI_SWIER_SWIER7_Pos (7U) +#define EXTI_SWIER_SWIER7_Msk (0x1U << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */ +#define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */ +#define EXTI_SWIER_SWIER8_Pos (8U) +#define EXTI_SWIER_SWIER8_Msk (0x1U << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */ +#define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */ +#define EXTI_SWIER_SWIER9_Pos (9U) +#define EXTI_SWIER_SWIER9_Msk (0x1U << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */ +#define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */ +#define EXTI_SWIER_SWIER10_Pos (10U) +#define EXTI_SWIER_SWIER10_Msk (0x1U << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */ +#define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */ +#define EXTI_SWIER_SWIER11_Pos (11U) +#define EXTI_SWIER_SWIER11_Msk (0x1U << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */ +#define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */ +#define EXTI_SWIER_SWIER12_Pos (12U) +#define EXTI_SWIER_SWIER12_Msk (0x1U << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */ +#define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */ +#define EXTI_SWIER_SWIER13_Pos (13U) +#define EXTI_SWIER_SWIER13_Msk (0x1U << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */ +#define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */ +#define EXTI_SWIER_SWIER14_Pos (14U) +#define EXTI_SWIER_SWIER14_Msk (0x1U << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */ +#define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */ +#define EXTI_SWIER_SWIER15_Pos (15U) +#define EXTI_SWIER_SWIER15_Msk (0x1U << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */ +#define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */ +#define EXTI_SWIER_SWIER16_Pos (16U) +#define EXTI_SWIER_SWIER16_Msk (0x1U << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */ +#define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */ +#define EXTI_SWIER_SWIER17_Pos (17U) +#define EXTI_SWIER_SWIER17_Msk (0x1U << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */ +#define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */ +#define EXTI_SWIER_SWIER19_Pos (19U) +#define EXTI_SWIER_SWIER19_Msk (0x1U << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */ +#define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */ +#define EXTI_SWIER_SWIER21_Pos (21U) +#define EXTI_SWIER_SWIER21_Msk (0x1U << EXTI_SWIER_SWIER21_Pos) /*!< 0x00200000 */ +#define EXTI_SWIER_SWIER21 EXTI_SWIER_SWIER21_Msk /*!< Software Interrupt on line 21 */ +#define EXTI_SWIER_SWIER22_Pos (22U) +#define EXTI_SWIER_SWIER22_Msk (0x1U << EXTI_SWIER_SWIER22_Pos) /*!< 0x00400000 */ +#define EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_Msk /*!< Software Interrupt on line 22 */ /* References Defines */ #define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0 @@ -1430,27 +2091,69 @@ typedef struct #define EXTI_SWIER_SWI22 EXTI_SWIER_SWIER22 /****************** Bit definition for EXTI_PR register *********************/ -#define EXTI_PR_PR0 ((uint32_t)0x00000001U) /*!< Pending bit 0 */ -#define EXTI_PR_PR1 ((uint32_t)0x00000002U) /*!< Pending bit 1 */ -#define EXTI_PR_PR2 ((uint32_t)0x00000004U) /*!< Pending bit 2 */ -#define EXTI_PR_PR3 ((uint32_t)0x00000008U) /*!< Pending bit 3 */ -#define EXTI_PR_PR4 ((uint32_t)0x00000010U) /*!< Pending bit 4 */ -#define EXTI_PR_PR5 ((uint32_t)0x00000020U) /*!< Pending bit 5 */ -#define EXTI_PR_PR6 ((uint32_t)0x00000040U) /*!< Pending bit 6 */ -#define EXTI_PR_PR7 ((uint32_t)0x00000080U) /*!< Pending bit 7 */ -#define EXTI_PR_PR8 ((uint32_t)0x00000100U) /*!< Pending bit 8 */ -#define EXTI_PR_PR9 ((uint32_t)0x00000200U) /*!< Pending bit 9 */ -#define EXTI_PR_PR10 ((uint32_t)0x00000400U) /*!< Pending bit 10 */ -#define EXTI_PR_PR11 ((uint32_t)0x00000800U) /*!< Pending bit 11 */ -#define EXTI_PR_PR12 ((uint32_t)0x00001000U) /*!< Pending bit 12 */ -#define EXTI_PR_PR13 ((uint32_t)0x00002000U) /*!< Pending bit 13 */ -#define EXTI_PR_PR14 ((uint32_t)0x00004000U) /*!< Pending bit 14 */ -#define EXTI_PR_PR15 ((uint32_t)0x00008000U) /*!< Pending bit 15 */ -#define EXTI_PR_PR16 ((uint32_t)0x00010000U) /*!< Pending bit 16 */ -#define EXTI_PR_PR17 ((uint32_t)0x00020000U) /*!< Pending bit 17 */ -#define EXTI_PR_PR19 ((uint32_t)0x00080000U) /*!< Pending bit 19 */ -#define EXTI_PR_PR21 ((uint32_t)0x00200000U) /*!< Pending bit 21 */ -#define EXTI_PR_PR22 ((uint32_t)0x00400000U) /*!< Pending bit 22 */ +#define EXTI_PR_PR0_Pos (0U) +#define EXTI_PR_PR0_Msk (0x1U << EXTI_PR_PR0_Pos) /*!< 0x00000001 */ +#define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit 0 */ +#define EXTI_PR_PR1_Pos (1U) +#define EXTI_PR_PR1_Msk (0x1U << EXTI_PR_PR1_Pos) /*!< 0x00000002 */ +#define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit 1 */ +#define EXTI_PR_PR2_Pos (2U) +#define EXTI_PR_PR2_Msk (0x1U << EXTI_PR_PR2_Pos) /*!< 0x00000004 */ +#define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit 2 */ +#define EXTI_PR_PR3_Pos (3U) +#define EXTI_PR_PR3_Msk (0x1U << EXTI_PR_PR3_Pos) /*!< 0x00000008 */ +#define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit 3 */ +#define EXTI_PR_PR4_Pos (4U) +#define EXTI_PR_PR4_Msk (0x1U << EXTI_PR_PR4_Pos) /*!< 0x00000010 */ +#define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit 4 */ +#define EXTI_PR_PR5_Pos (5U) +#define EXTI_PR_PR5_Msk (0x1U << EXTI_PR_PR5_Pos) /*!< 0x00000020 */ +#define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit 5 */ +#define EXTI_PR_PR6_Pos (6U) +#define EXTI_PR_PR6_Msk (0x1U << EXTI_PR_PR6_Pos) /*!< 0x00000040 */ +#define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit 6 */ +#define EXTI_PR_PR7_Pos (7U) +#define EXTI_PR_PR7_Msk (0x1U << EXTI_PR_PR7_Pos) /*!< 0x00000080 */ +#define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit 7 */ +#define EXTI_PR_PR8_Pos (8U) +#define EXTI_PR_PR8_Msk (0x1U << EXTI_PR_PR8_Pos) /*!< 0x00000100 */ +#define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit 8 */ +#define EXTI_PR_PR9_Pos (9U) +#define EXTI_PR_PR9_Msk (0x1U << EXTI_PR_PR9_Pos) /*!< 0x00000200 */ +#define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit 9 */ +#define EXTI_PR_PR10_Pos (10U) +#define EXTI_PR_PR10_Msk (0x1U << EXTI_PR_PR10_Pos) /*!< 0x00000400 */ +#define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit 10 */ +#define EXTI_PR_PR11_Pos (11U) +#define EXTI_PR_PR11_Msk (0x1U << EXTI_PR_PR11_Pos) /*!< 0x00000800 */ +#define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit 11 */ +#define EXTI_PR_PR12_Pos (12U) +#define EXTI_PR_PR12_Msk (0x1U << EXTI_PR_PR12_Pos) /*!< 0x00001000 */ +#define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit 12 */ +#define EXTI_PR_PR13_Pos (13U) +#define EXTI_PR_PR13_Msk (0x1U << EXTI_PR_PR13_Pos) /*!< 0x00002000 */ +#define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit 13 */ +#define EXTI_PR_PR14_Pos (14U) +#define EXTI_PR_PR14_Msk (0x1U << EXTI_PR_PR14_Pos) /*!< 0x00004000 */ +#define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit 14 */ +#define EXTI_PR_PR15_Pos (15U) +#define EXTI_PR_PR15_Msk (0x1U << EXTI_PR_PR15_Pos) /*!< 0x00008000 */ +#define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit 15 */ +#define EXTI_PR_PR16_Pos (16U) +#define EXTI_PR_PR16_Msk (0x1U << EXTI_PR_PR16_Pos) /*!< 0x00010000 */ +#define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit 16 */ +#define EXTI_PR_PR17_Pos (17U) +#define EXTI_PR_PR17_Msk (0x1U << EXTI_PR_PR17_Pos) /*!< 0x00020000 */ +#define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit 17 */ +#define EXTI_PR_PR19_Pos (19U) +#define EXTI_PR_PR19_Msk (0x1U << EXTI_PR_PR19_Pos) /*!< 0x00080000 */ +#define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit 19 */ +#define EXTI_PR_PR21_Pos (21U) +#define EXTI_PR_PR21_Msk (0x1U << EXTI_PR_PR21_Pos) /*!< 0x00200000 */ +#define EXTI_PR_PR21 EXTI_PR_PR21_Msk /*!< Pending bit 21 */ +#define EXTI_PR_PR22_Pos (22U) +#define EXTI_PR_PR22_Msk (0x1U << EXTI_PR_PR22_Pos) /*!< 0x00400000 */ +#define EXTI_PR_PR22 EXTI_PR_PR22_Msk /*!< Pending bit 22 */ /* References Defines */ #define EXTI_PR_PIF0 EXTI_PR_PR0 @@ -1482,63 +2185,137 @@ typedef struct /******************************************************************************/ /******************* Bit definition for FLASH_ACR register ******************/ -#define FLASH_ACR_LATENCY ((uint32_t)0x00000001U) /*!< LATENCY bit (Latency) */ +#define FLASH_ACR_LATENCY_Pos (0U) +#define FLASH_ACR_LATENCY_Msk (0x1U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */ +#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< LATENCY bit (Latency) */ -#define FLASH_ACR_PRFTBE ((uint32_t)0x00000010U) /*!< Prefetch Buffer Enable */ -#define FLASH_ACR_PRFTBS ((uint32_t)0x00000020U) /*!< Prefetch Buffer Status */ +#define FLASH_ACR_PRFTBE_Pos (4U) +#define FLASH_ACR_PRFTBE_Msk (0x1U << FLASH_ACR_PRFTBE_Pos) /*!< 0x00000010 */ +#define FLASH_ACR_PRFTBE FLASH_ACR_PRFTBE_Msk /*!< Prefetch Buffer Enable */ +#define FLASH_ACR_PRFTBS_Pos (5U) +#define FLASH_ACR_PRFTBS_Msk (0x1U << FLASH_ACR_PRFTBS_Pos) /*!< 0x00000020 */ +#define FLASH_ACR_PRFTBS FLASH_ACR_PRFTBS_Msk /*!< Prefetch Buffer Status */ /****************** Bit definition for FLASH_KEYR register ******************/ -#define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFFU) /*!< FPEC Key */ +#define FLASH_KEYR_FKEYR_Pos (0U) +#define FLASH_KEYR_FKEYR_Msk (0xFFFFFFFFU << FLASH_KEYR_FKEYR_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_KEYR_FKEYR FLASH_KEYR_FKEYR_Msk /*!< FPEC Key */ /***************** Bit definition for FLASH_OPTKEYR register ****************/ -#define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFFU) /*!< Option Byte Key */ +#define FLASH_OPTKEYR_OPTKEYR_Pos (0U) +#define FLASH_OPTKEYR_OPTKEYR_Msk (0xFFFFFFFFU << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk /*!< Option Byte Key */ /****************** FLASH Keys **********************************************/ -#define FLASH_KEY1 ((uint32_t)0x45670123U) /*!< Flash program erase key1 */ -#define FLASH_KEY2 ((uint32_t)0xCDEF89ABU) /*!< Flash program erase key2: used with FLASH_PEKEY1 +#define FLASH_KEY1_Pos (0U) +#define FLASH_KEY1_Msk (0x45670123U << FLASH_KEY1_Pos) /*!< 0x45670123 */ +#define FLASH_KEY1 FLASH_KEY1_Msk /*!< Flash program erase key1 */ +#define FLASH_KEY2_Pos (0U) +#define FLASH_KEY2_Msk (0xCDEF89ABU << FLASH_KEY2_Pos) /*!< 0xCDEF89AB */ +#define FLASH_KEY2 FLASH_KEY2_Msk /*!< Flash program erase key2: used with FLASH_PEKEY1 to unlock the write access to the FPEC. */ -#define FLASH_OPTKEY1 ((uint32_t)0x45670123U) /*!< Flash option key1 */ -#define FLASH_OPTKEY2 ((uint32_t)0xCDEF89ABU) /*!< Flash option key2: used with FLASH_OPTKEY1 to +#define FLASH_OPTKEY1_Pos (0U) +#define FLASH_OPTKEY1_Msk (0x45670123U << FLASH_OPTKEY1_Pos) /*!< 0x45670123 */ +#define FLASH_OPTKEY1 FLASH_OPTKEY1_Msk /*!< Flash option key1 */ +#define FLASH_OPTKEY2_Pos (0U) +#define FLASH_OPTKEY2_Msk (0xCDEF89ABU << FLASH_OPTKEY2_Pos) /*!< 0xCDEF89AB */ +#define FLASH_OPTKEY2 FLASH_OPTKEY2_Msk /*!< Flash option key2: used with FLASH_OPTKEY1 to unlock the write access to the option byte block */ /****************** Bit definition for FLASH_SR register *******************/ -#define FLASH_SR_BSY ((uint32_t)0x00000001U) /*!< Busy */ -#define FLASH_SR_PGERR ((uint32_t)0x00000004U) /*!< Programming Error */ -#define FLASH_SR_WRPRTERR ((uint32_t)0x00000010U) /*!< Write Protection Error */ -#define FLASH_SR_EOP ((uint32_t)0x00000020U) /*!< End of operation */ +#define FLASH_SR_BSY_Pos (0U) +#define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00000001 */ +#define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy */ +#define FLASH_SR_PGERR_Pos (2U) +#define FLASH_SR_PGERR_Msk (0x1U << FLASH_SR_PGERR_Pos) /*!< 0x00000004 */ +#define FLASH_SR_PGERR FLASH_SR_PGERR_Msk /*!< Programming Error */ +#define FLASH_SR_WRPRTERR_Pos (4U) +#define FLASH_SR_WRPRTERR_Msk (0x1U << FLASH_SR_WRPRTERR_Pos) /*!< 0x00000010 */ +#define FLASH_SR_WRPRTERR FLASH_SR_WRPRTERR_Msk /*!< Write Protection Error */ +#define FLASH_SR_EOP_Pos (5U) +#define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /*!< 0x00000020 */ +#define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End of operation */ #define FLASH_SR_WRPERR FLASH_SR_WRPRTERR /*!< Legacy of Write Protection Error */ /******************* Bit definition for FLASH_CR register *******************/ -#define FLASH_CR_PG ((uint32_t)0x00000001U) /*!< Programming */ -#define FLASH_CR_PER ((uint32_t)0x00000002U) /*!< Page Erase */ -#define FLASH_CR_MER ((uint32_t)0x00000004U) /*!< Mass Erase */ -#define FLASH_CR_OPTPG ((uint32_t)0x00000010U) /*!< Option Byte Programming */ -#define FLASH_CR_OPTER ((uint32_t)0x00000020U) /*!< Option Byte Erase */ -#define FLASH_CR_STRT ((uint32_t)0x00000040U) /*!< Start */ -#define FLASH_CR_LOCK ((uint32_t)0x00000080U) /*!< Lock */ -#define FLASH_CR_OPTWRE ((uint32_t)0x00000200U) /*!< Option Bytes Write Enable */ -#define FLASH_CR_ERRIE ((uint32_t)0x00000400U) /*!< Error Interrupt Enable */ -#define FLASH_CR_EOPIE ((uint32_t)0x00001000U) /*!< End of operation interrupt enable */ -#define FLASH_CR_OBL_LAUNCH ((uint32_t)0x00002000U) /*!< Option Bytes Loader Launch */ +#define FLASH_CR_PG_Pos (0U) +#define FLASH_CR_PG_Msk (0x1U << FLASH_CR_PG_Pos) /*!< 0x00000001 */ +#define FLASH_CR_PG FLASH_CR_PG_Msk /*!< Programming */ +#define FLASH_CR_PER_Pos (1U) +#define FLASH_CR_PER_Msk (0x1U << FLASH_CR_PER_Pos) /*!< 0x00000002 */ +#define FLASH_CR_PER FLASH_CR_PER_Msk /*!< Page Erase */ +#define FLASH_CR_MER_Pos (2U) +#define FLASH_CR_MER_Msk (0x1U << FLASH_CR_MER_Pos) /*!< 0x00000004 */ +#define FLASH_CR_MER FLASH_CR_MER_Msk /*!< Mass Erase */ +#define FLASH_CR_OPTPG_Pos (4U) +#define FLASH_CR_OPTPG_Msk (0x1U << FLASH_CR_OPTPG_Pos) /*!< 0x00000010 */ +#define FLASH_CR_OPTPG FLASH_CR_OPTPG_Msk /*!< Option Byte Programming */ +#define FLASH_CR_OPTER_Pos (5U) +#define FLASH_CR_OPTER_Msk (0x1U << FLASH_CR_OPTER_Pos) /*!< 0x00000020 */ +#define FLASH_CR_OPTER FLASH_CR_OPTER_Msk /*!< Option Byte Erase */ +#define FLASH_CR_STRT_Pos (6U) +#define FLASH_CR_STRT_Msk (0x1U << FLASH_CR_STRT_Pos) /*!< 0x00000040 */ +#define FLASH_CR_STRT FLASH_CR_STRT_Msk /*!< Start */ +#define FLASH_CR_LOCK_Pos (7U) +#define FLASH_CR_LOCK_Msk (0x1U << FLASH_CR_LOCK_Pos) /*!< 0x00000080 */ +#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk /*!< Lock */ +#define FLASH_CR_OPTWRE_Pos (9U) +#define FLASH_CR_OPTWRE_Msk (0x1U << FLASH_CR_OPTWRE_Pos) /*!< 0x00000200 */ +#define FLASH_CR_OPTWRE FLASH_CR_OPTWRE_Msk /*!< Option Bytes Write Enable */ +#define FLASH_CR_ERRIE_Pos (10U) +#define FLASH_CR_ERRIE_Msk (0x1U << FLASH_CR_ERRIE_Pos) /*!< 0x00000400 */ +#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk /*!< Error Interrupt Enable */ +#define FLASH_CR_EOPIE_Pos (12U) +#define FLASH_CR_EOPIE_Msk (0x1U << FLASH_CR_EOPIE_Pos) /*!< 0x00001000 */ +#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk /*!< End of operation interrupt enable */ +#define FLASH_CR_OBL_LAUNCH_Pos (13U) +#define FLASH_CR_OBL_LAUNCH_Msk (0x1U << FLASH_CR_OBL_LAUNCH_Pos) /*!< 0x00002000 */ +#define FLASH_CR_OBL_LAUNCH FLASH_CR_OBL_LAUNCH_Msk /*!< Option Bytes Loader Launch */ /******************* Bit definition for FLASH_AR register *******************/ -#define FLASH_AR_FAR ((uint32_t)0xFFFFFFFFU) /*!< Flash Address */ +#define FLASH_AR_FAR_Pos (0U) +#define FLASH_AR_FAR_Msk (0xFFFFFFFFU << FLASH_AR_FAR_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_AR_FAR FLASH_AR_FAR_Msk /*!< Flash Address */ /****************** Bit definition for FLASH_OBR register *******************/ -#define FLASH_OBR_OPTERR ((uint32_t)0x00000001U) /*!< Option Byte Error */ -#define FLASH_OBR_RDPRT1 ((uint32_t)0x00000002U) /*!< Read protection Level 1 */ -#define FLASH_OBR_RDPRT2 ((uint32_t)0x00000004U) /*!< Read protection Level 2 */ +#define FLASH_OBR_OPTERR_Pos (0U) +#define FLASH_OBR_OPTERR_Msk (0x1U << FLASH_OBR_OPTERR_Pos) /*!< 0x00000001 */ +#define FLASH_OBR_OPTERR FLASH_OBR_OPTERR_Msk /*!< Option Byte Error */ +#define FLASH_OBR_RDPRT1_Pos (1U) +#define FLASH_OBR_RDPRT1_Msk (0x1U << FLASH_OBR_RDPRT1_Pos) /*!< 0x00000002 */ +#define FLASH_OBR_RDPRT1 FLASH_OBR_RDPRT1_Msk /*!< Read protection Level 1 */ +#define FLASH_OBR_RDPRT2_Pos (2U) +#define FLASH_OBR_RDPRT2_Msk (0x1U << FLASH_OBR_RDPRT2_Pos) /*!< 0x00000004 */ +#define FLASH_OBR_RDPRT2 FLASH_OBR_RDPRT2_Msk /*!< Read protection Level 2 */ -#define FLASH_OBR_USER ((uint32_t)0x00007700U) /*!< User Option Bytes */ -#define FLASH_OBR_IWDG_SW ((uint32_t)0x00000100U) /*!< IWDG SW */ -#define FLASH_OBR_nRST_STOP ((uint32_t)0x00000200U) /*!< nRST_STOP */ -#define FLASH_OBR_nRST_STDBY ((uint32_t)0x00000400U) /*!< nRST_STDBY */ -#define FLASH_OBR_nBOOT1 ((uint32_t)0x00001000U) /*!< nBOOT1 */ -#define FLASH_OBR_VDDA_MONITOR ((uint32_t)0x00002000U) /*!< VDDA power supply supervisor */ -#define FLASH_OBR_RAM_PARITY_CHECK ((uint32_t)0x00004000U) /*!< RAM parity check */ -#define FLASH_OBR_DATA0 ((uint32_t)0x00FF0000U) /*!< Data0 */ -#define FLASH_OBR_DATA1 ((uint32_t)0xFF000000U) /*!< Data1 */ +#define FLASH_OBR_USER_Pos (8U) +#define FLASH_OBR_USER_Msk (0x77U << FLASH_OBR_USER_Pos) /*!< 0x00007700 */ +#define FLASH_OBR_USER FLASH_OBR_USER_Msk /*!< User Option Bytes */ +#define FLASH_OBR_IWDG_SW_Pos (8U) +#define FLASH_OBR_IWDG_SW_Msk (0x1U << FLASH_OBR_IWDG_SW_Pos) /*!< 0x00000100 */ +#define FLASH_OBR_IWDG_SW FLASH_OBR_IWDG_SW_Msk /*!< IWDG SW */ +#define FLASH_OBR_nRST_STOP_Pos (9U) +#define FLASH_OBR_nRST_STOP_Msk (0x1U << FLASH_OBR_nRST_STOP_Pos) /*!< 0x00000200 */ +#define FLASH_OBR_nRST_STOP FLASH_OBR_nRST_STOP_Msk /*!< nRST_STOP */ +#define FLASH_OBR_nRST_STDBY_Pos (10U) +#define FLASH_OBR_nRST_STDBY_Msk (0x1U << FLASH_OBR_nRST_STDBY_Pos) /*!< 0x00000400 */ +#define FLASH_OBR_nRST_STDBY FLASH_OBR_nRST_STDBY_Msk /*!< nRST_STDBY */ +#define FLASH_OBR_nBOOT1_Pos (12U) +#define FLASH_OBR_nBOOT1_Msk (0x1U << FLASH_OBR_nBOOT1_Pos) /*!< 0x00001000 */ +#define FLASH_OBR_nBOOT1 FLASH_OBR_nBOOT1_Msk /*!< nBOOT1 */ +#define FLASH_OBR_VDDA_MONITOR_Pos (13U) +#define FLASH_OBR_VDDA_MONITOR_Msk (0x1U << FLASH_OBR_VDDA_MONITOR_Pos) /*!< 0x00002000 */ +#define FLASH_OBR_VDDA_MONITOR FLASH_OBR_VDDA_MONITOR_Msk /*!< VDDA power supply supervisor */ +#define FLASH_OBR_RAM_PARITY_CHECK_Pos (14U) +#define FLASH_OBR_RAM_PARITY_CHECK_Msk (0x1U << FLASH_OBR_RAM_PARITY_CHECK_Pos) /*!< 0x00004000 */ +#define FLASH_OBR_RAM_PARITY_CHECK FLASH_OBR_RAM_PARITY_CHECK_Msk /*!< RAM parity check */ +#define FLASH_OBR_DATA0_Pos (16U) +#define FLASH_OBR_DATA0_Msk (0xFFU << FLASH_OBR_DATA0_Pos) /*!< 0x00FF0000 */ +#define FLASH_OBR_DATA0 FLASH_OBR_DATA0_Msk /*!< Data0 */ +#define FLASH_OBR_DATA1_Pos (24U) +#define FLASH_OBR_DATA1_Msk (0xFFU << FLASH_OBR_DATA1_Pos) /*!< 0xFF000000 */ +#define FLASH_OBR_DATA1 FLASH_OBR_DATA1_Msk /*!< Data1 */ /* Old BOOT1 bit definition, maintained for legacy purpose */ #define FLASH_OBR_BOOT1 FLASH_OBR_nBOOT1 @@ -1547,25 +2324,43 @@ typedef struct #define FLASH_OBR_VDDA_ANALOG FLASH_OBR_VDDA_MONITOR /****************** Bit definition for FLASH_WRPR register ******************/ -#define FLASH_WRPR_WRP ((uint32_t)0x0000FFFFU) /*!< Write Protect */ +#define FLASH_WRPR_WRP_Pos (0U) +#define FLASH_WRPR_WRP_Msk (0xFFFFU << FLASH_WRPR_WRP_Pos) /*!< 0x0000FFFF */ +#define FLASH_WRPR_WRP FLASH_WRPR_WRP_Msk /*!< Write Protect */ /*----------------------------------------------------------------------------*/ /****************** Bit definition for OB_RDP register **********************/ -#define OB_RDP_RDP ((uint32_t)0x000000FFU) /*!< Read protection option byte */ -#define OB_RDP_nRDP ((uint32_t)0x0000FF00U) /*!< Read protection complemented option byte */ +#define OB_RDP_RDP_Pos (0U) +#define OB_RDP_RDP_Msk (0xFFU << OB_RDP_RDP_Pos) /*!< 0x000000FF */ +#define OB_RDP_RDP OB_RDP_RDP_Msk /*!< Read protection option byte */ +#define OB_RDP_nRDP_Pos (8U) +#define OB_RDP_nRDP_Msk (0xFFU << OB_RDP_nRDP_Pos) /*!< 0x0000FF00 */ +#define OB_RDP_nRDP OB_RDP_nRDP_Msk /*!< Read protection complemented option byte */ /****************** Bit definition for OB_USER register *********************/ -#define OB_USER_USER ((uint32_t)0x00FF0000U) /*!< User option byte */ -#define OB_USER_nUSER ((uint32_t)0xFF000000U) /*!< User complemented option byte */ +#define OB_USER_USER_Pos (16U) +#define OB_USER_USER_Msk (0xFFU << OB_USER_USER_Pos) /*!< 0x00FF0000 */ +#define OB_USER_USER OB_USER_USER_Msk /*!< User option byte */ +#define OB_USER_nUSER_Pos (24U) +#define OB_USER_nUSER_Msk (0xFFU << OB_USER_nUSER_Pos) /*!< 0xFF000000 */ +#define OB_USER_nUSER OB_USER_nUSER_Msk /*!< User complemented option byte */ /****************** Bit definition for OB_WRP0 register *********************/ -#define OB_WRP0_WRP0 ((uint32_t)0x000000FFU) /*!< Flash memory write protection option bytes */ -#define OB_WRP0_nWRP0 ((uint32_t)0x0000FF00U) /*!< Flash memory write protection complemented option bytes */ +#define OB_WRP0_WRP0_Pos (0U) +#define OB_WRP0_WRP0_Msk (0xFFU << OB_WRP0_WRP0_Pos) /*!< 0x000000FF */ +#define OB_WRP0_WRP0 OB_WRP0_WRP0_Msk /*!< Flash memory write protection option bytes */ +#define OB_WRP0_nWRP0_Pos (8U) +#define OB_WRP0_nWRP0_Msk (0xFFU << OB_WRP0_nWRP0_Pos) /*!< 0x0000FF00 */ +#define OB_WRP0_nWRP0 OB_WRP0_nWRP0_Msk /*!< Flash memory write protection complemented option bytes */ /****************** Bit definition for OB_WRP1 register *********************/ -#define OB_WRP1_WRP1 ((uint32_t)0x00FF0000U) /*!< Flash memory write protection option bytes */ -#define OB_WRP1_nWRP1 ((uint32_t)0xFF000000U) /*!< Flash memory write protection complemented option bytes */ +#define OB_WRP1_WRP1_Pos (16U) +#define OB_WRP1_WRP1_Msk (0xFFU << OB_WRP1_WRP1_Pos) /*!< 0x00FF0000 */ +#define OB_WRP1_WRP1 OB_WRP1_WRP1_Msk /*!< Flash memory write protection option bytes */ +#define OB_WRP1_nWRP1_Pos (24U) +#define OB_WRP1_nWRP1_Msk (0xFFU << OB_WRP1_nWRP1_Pos) /*!< 0xFF000000 */ +#define OB_WRP1_nWRP1 OB_WRP1_nWRP1_Msk /*!< Flash memory write protection complemented option bytes */ /******************************************************************************/ /* */ @@ -1573,122 +2368,186 @@ typedef struct /* */ /******************************************************************************/ /******************* Bit definition for GPIO_MODER register *****************/ -#define GPIO_MODER_MODER0 ((uint32_t)0x00000003U) -#define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001U) -#define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002U) -#define GPIO_MODER_MODER1 ((uint32_t)0x0000000CU) -#define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004U) -#define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008U) -#define GPIO_MODER_MODER2 ((uint32_t)0x00000030U) -#define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010U) -#define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020U) -#define GPIO_MODER_MODER3 ((uint32_t)0x000000C0U) -#define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040U) -#define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080U) -#define GPIO_MODER_MODER4 ((uint32_t)0x00000300U) -#define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100U) -#define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200U) -#define GPIO_MODER_MODER5 ((uint32_t)0x00000C00U) -#define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400U) -#define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800U) -#define GPIO_MODER_MODER6 ((uint32_t)0x00003000U) -#define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000U) -#define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000U) -#define GPIO_MODER_MODER7 ((uint32_t)0x0000C000U) -#define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000U) -#define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000U) -#define GPIO_MODER_MODER8 ((uint32_t)0x00030000U) -#define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000U) -#define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000U) -#define GPIO_MODER_MODER9 ((uint32_t)0x000C0000U) -#define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000U) -#define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000U) -#define GPIO_MODER_MODER10 ((uint32_t)0x00300000U) -#define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000U) -#define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000U) -#define GPIO_MODER_MODER11 ((uint32_t)0x00C00000U) -#define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000U) -#define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000U) -#define GPIO_MODER_MODER12 ((uint32_t)0x03000000U) -#define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000U) -#define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000U) -#define GPIO_MODER_MODER13 ((uint32_t)0x0C000000U) -#define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000U) -#define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000U) -#define GPIO_MODER_MODER14 ((uint32_t)0x30000000U) -#define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000U) -#define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000U) -#define GPIO_MODER_MODER15 ((uint32_t)0xC0000000U) -#define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000U) -#define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000U) +#define GPIO_MODER_MODER0_Pos (0U) +#define GPIO_MODER_MODER0_Msk (0x3U << GPIO_MODER_MODER0_Pos) /*!< 0x00000003 */ +#define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk +#define GPIO_MODER_MODER0_0 (0x1U << GPIO_MODER_MODER0_Pos) /*!< 0x00000001 */ +#define GPIO_MODER_MODER0_1 (0x2U << GPIO_MODER_MODER0_Pos) /*!< 0x00000002 */ +#define GPIO_MODER_MODER1_Pos (2U) +#define GPIO_MODER_MODER1_Msk (0x3U << GPIO_MODER_MODER1_Pos) /*!< 0x0000000C */ +#define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk +#define GPIO_MODER_MODER1_0 (0x1U << GPIO_MODER_MODER1_Pos) /*!< 0x00000004 */ +#define GPIO_MODER_MODER1_1 (0x2U << GPIO_MODER_MODER1_Pos) /*!< 0x00000008 */ +#define GPIO_MODER_MODER2_Pos (4U) +#define GPIO_MODER_MODER2_Msk (0x3U << GPIO_MODER_MODER2_Pos) /*!< 0x00000030 */ +#define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk +#define GPIO_MODER_MODER2_0 (0x1U << GPIO_MODER_MODER2_Pos) /*!< 0x00000010 */ +#define GPIO_MODER_MODER2_1 (0x2U << GPIO_MODER_MODER2_Pos) /*!< 0x00000020 */ +#define GPIO_MODER_MODER3_Pos (6U) +#define GPIO_MODER_MODER3_Msk (0x3U << GPIO_MODER_MODER3_Pos) /*!< 0x000000C0 */ +#define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk +#define GPIO_MODER_MODER3_0 (0x1U << GPIO_MODER_MODER3_Pos) /*!< 0x00000040 */ +#define GPIO_MODER_MODER3_1 (0x2U << GPIO_MODER_MODER3_Pos) /*!< 0x00000080 */ +#define GPIO_MODER_MODER4_Pos (8U) +#define GPIO_MODER_MODER4_Msk (0x3U << GPIO_MODER_MODER4_Pos) /*!< 0x00000300 */ +#define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk +#define GPIO_MODER_MODER4_0 (0x1U << GPIO_MODER_MODER4_Pos) /*!< 0x00000100 */ +#define GPIO_MODER_MODER4_1 (0x2U << GPIO_MODER_MODER4_Pos) /*!< 0x00000200 */ +#define GPIO_MODER_MODER5_Pos (10U) +#define GPIO_MODER_MODER5_Msk (0x3U << GPIO_MODER_MODER5_Pos) /*!< 0x00000C00 */ +#define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk +#define GPIO_MODER_MODER5_0 (0x1U << GPIO_MODER_MODER5_Pos) /*!< 0x00000400 */ +#define GPIO_MODER_MODER5_1 (0x2U << GPIO_MODER_MODER5_Pos) /*!< 0x00000800 */ +#define GPIO_MODER_MODER6_Pos (12U) +#define GPIO_MODER_MODER6_Msk (0x3U << GPIO_MODER_MODER6_Pos) /*!< 0x00003000 */ +#define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk +#define GPIO_MODER_MODER6_0 (0x1U << GPIO_MODER_MODER6_Pos) /*!< 0x00001000 */ +#define GPIO_MODER_MODER6_1 (0x2U << GPIO_MODER_MODER6_Pos) /*!< 0x00002000 */ +#define GPIO_MODER_MODER7_Pos (14U) +#define GPIO_MODER_MODER7_Msk (0x3U << GPIO_MODER_MODER7_Pos) /*!< 0x0000C000 */ +#define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk +#define GPIO_MODER_MODER7_0 (0x1U << GPIO_MODER_MODER7_Pos) /*!< 0x00004000 */ +#define GPIO_MODER_MODER7_1 (0x2U << GPIO_MODER_MODER7_Pos) /*!< 0x00008000 */ +#define GPIO_MODER_MODER8_Pos (16U) +#define GPIO_MODER_MODER8_Msk (0x3U << GPIO_MODER_MODER8_Pos) /*!< 0x00030000 */ +#define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk +#define GPIO_MODER_MODER8_0 (0x1U << GPIO_MODER_MODER8_Pos) /*!< 0x00010000 */ +#define GPIO_MODER_MODER8_1 (0x2U << GPIO_MODER_MODER8_Pos) /*!< 0x00020000 */ +#define GPIO_MODER_MODER9_Pos (18U) +#define GPIO_MODER_MODER9_Msk (0x3U << GPIO_MODER_MODER9_Pos) /*!< 0x000C0000 */ +#define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk +#define GPIO_MODER_MODER9_0 (0x1U << GPIO_MODER_MODER9_Pos) /*!< 0x00040000 */ +#define GPIO_MODER_MODER9_1 (0x2U << GPIO_MODER_MODER9_Pos) /*!< 0x00080000 */ +#define GPIO_MODER_MODER10_Pos (20U) +#define GPIO_MODER_MODER10_Msk (0x3U << GPIO_MODER_MODER10_Pos) /*!< 0x00300000 */ +#define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk +#define GPIO_MODER_MODER10_0 (0x1U << GPIO_MODER_MODER10_Pos) /*!< 0x00100000 */ +#define GPIO_MODER_MODER10_1 (0x2U << GPIO_MODER_MODER10_Pos) /*!< 0x00200000 */ +#define GPIO_MODER_MODER11_Pos (22U) +#define GPIO_MODER_MODER11_Msk (0x3U << GPIO_MODER_MODER11_Pos) /*!< 0x00C00000 */ +#define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk +#define GPIO_MODER_MODER11_0 (0x1U << GPIO_MODER_MODER11_Pos) /*!< 0x00400000 */ +#define GPIO_MODER_MODER11_1 (0x2U << GPIO_MODER_MODER11_Pos) /*!< 0x00800000 */ +#define GPIO_MODER_MODER12_Pos (24U) +#define GPIO_MODER_MODER12_Msk (0x3U << GPIO_MODER_MODER12_Pos) /*!< 0x03000000 */ +#define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk +#define GPIO_MODER_MODER12_0 (0x1U << GPIO_MODER_MODER12_Pos) /*!< 0x01000000 */ +#define GPIO_MODER_MODER12_1 (0x2U << GPIO_MODER_MODER12_Pos) /*!< 0x02000000 */ +#define GPIO_MODER_MODER13_Pos (26U) +#define GPIO_MODER_MODER13_Msk (0x3U << GPIO_MODER_MODER13_Pos) /*!< 0x0C000000 */ +#define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk +#define GPIO_MODER_MODER13_0 (0x1U << GPIO_MODER_MODER13_Pos) /*!< 0x04000000 */ +#define GPIO_MODER_MODER13_1 (0x2U << GPIO_MODER_MODER13_Pos) /*!< 0x08000000 */ +#define GPIO_MODER_MODER14_Pos (28U) +#define GPIO_MODER_MODER14_Msk (0x3U << GPIO_MODER_MODER14_Pos) /*!< 0x30000000 */ +#define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk +#define GPIO_MODER_MODER14_0 (0x1U << GPIO_MODER_MODER14_Pos) /*!< 0x10000000 */ +#define GPIO_MODER_MODER14_1 (0x2U << GPIO_MODER_MODER14_Pos) /*!< 0x20000000 */ +#define GPIO_MODER_MODER15_Pos (30U) +#define GPIO_MODER_MODER15_Msk (0x3U << GPIO_MODER_MODER15_Pos) /*!< 0xC0000000 */ +#define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk +#define GPIO_MODER_MODER15_0 (0x1U << GPIO_MODER_MODER15_Pos) /*!< 0x40000000 */ +#define GPIO_MODER_MODER15_1 (0x2U << GPIO_MODER_MODER15_Pos) /*!< 0x80000000 */ /****************** Bit definition for GPIO_OTYPER register *****************/ -#define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001U) -#define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002U) -#define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004U) -#define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008U) -#define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010U) -#define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020U) -#define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040U) -#define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080U) -#define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100U) -#define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200U) -#define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400U) -#define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800U) -#define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000U) -#define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000U) -#define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000U) -#define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000U) +#define GPIO_OTYPER_OT_0 (0x00000001U) +#define GPIO_OTYPER_OT_1 (0x00000002U) +#define GPIO_OTYPER_OT_2 (0x00000004U) +#define GPIO_OTYPER_OT_3 (0x00000008U) +#define GPIO_OTYPER_OT_4 (0x00000010U) +#define GPIO_OTYPER_OT_5 (0x00000020U) +#define GPIO_OTYPER_OT_6 (0x00000040U) +#define GPIO_OTYPER_OT_7 (0x00000080U) +#define GPIO_OTYPER_OT_8 (0x00000100U) +#define GPIO_OTYPER_OT_9 (0x00000200U) +#define GPIO_OTYPER_OT_10 (0x00000400U) +#define GPIO_OTYPER_OT_11 (0x00000800U) +#define GPIO_OTYPER_OT_12 (0x00001000U) +#define GPIO_OTYPER_OT_13 (0x00002000U) +#define GPIO_OTYPER_OT_14 (0x00004000U) +#define GPIO_OTYPER_OT_15 (0x00008000U) /**************** Bit definition for GPIO_OSPEEDR register ******************/ -#define GPIO_OSPEEDR_OSPEEDR0 ((uint32_t)0x00000003U) -#define GPIO_OSPEEDR_OSPEEDR0_0 ((uint32_t)0x00000001U) -#define GPIO_OSPEEDR_OSPEEDR0_1 ((uint32_t)0x00000002U) -#define GPIO_OSPEEDR_OSPEEDR1 ((uint32_t)0x0000000CU) -#define GPIO_OSPEEDR_OSPEEDR1_0 ((uint32_t)0x00000004U) -#define GPIO_OSPEEDR_OSPEEDR1_1 ((uint32_t)0x00000008U) -#define GPIO_OSPEEDR_OSPEEDR2 ((uint32_t)0x00000030U) -#define GPIO_OSPEEDR_OSPEEDR2_0 ((uint32_t)0x00000010U) -#define GPIO_OSPEEDR_OSPEEDR2_1 ((uint32_t)0x00000020U) -#define GPIO_OSPEEDR_OSPEEDR3 ((uint32_t)0x000000C0U) -#define GPIO_OSPEEDR_OSPEEDR3_0 ((uint32_t)0x00000040U) -#define GPIO_OSPEEDR_OSPEEDR3_1 ((uint32_t)0x00000080U) -#define GPIO_OSPEEDR_OSPEEDR4 ((uint32_t)0x00000300U) -#define GPIO_OSPEEDR_OSPEEDR4_0 ((uint32_t)0x00000100U) -#define GPIO_OSPEEDR_OSPEEDR4_1 ((uint32_t)0x00000200U) -#define GPIO_OSPEEDR_OSPEEDR5 ((uint32_t)0x00000C00U) -#define GPIO_OSPEEDR_OSPEEDR5_0 ((uint32_t)0x00000400U) -#define GPIO_OSPEEDR_OSPEEDR5_1 ((uint32_t)0x00000800U) -#define GPIO_OSPEEDR_OSPEEDR6 ((uint32_t)0x00003000U) -#define GPIO_OSPEEDR_OSPEEDR6_0 ((uint32_t)0x00001000U) -#define GPIO_OSPEEDR_OSPEEDR6_1 ((uint32_t)0x00002000U) -#define GPIO_OSPEEDR_OSPEEDR7 ((uint32_t)0x0000C000U) -#define GPIO_OSPEEDR_OSPEEDR7_0 ((uint32_t)0x00004000U) -#define GPIO_OSPEEDR_OSPEEDR7_1 ((uint32_t)0x00008000U) -#define GPIO_OSPEEDR_OSPEEDR8 ((uint32_t)0x00030000U) -#define GPIO_OSPEEDR_OSPEEDR8_0 ((uint32_t)0x00010000U) -#define GPIO_OSPEEDR_OSPEEDR8_1 ((uint32_t)0x00020000U) -#define GPIO_OSPEEDR_OSPEEDR9 ((uint32_t)0x000C0000U) -#define GPIO_OSPEEDR_OSPEEDR9_0 ((uint32_t)0x00040000U) -#define GPIO_OSPEEDR_OSPEEDR9_1 ((uint32_t)0x00080000U) -#define GPIO_OSPEEDR_OSPEEDR10 ((uint32_t)0x00300000U) -#define GPIO_OSPEEDR_OSPEEDR10_0 ((uint32_t)0x00100000U) -#define GPIO_OSPEEDR_OSPEEDR10_1 ((uint32_t)0x00200000U) -#define GPIO_OSPEEDR_OSPEEDR11 ((uint32_t)0x00C00000U) -#define GPIO_OSPEEDR_OSPEEDR11_0 ((uint32_t)0x00400000U) -#define GPIO_OSPEEDR_OSPEEDR11_1 ((uint32_t)0x00800000U) -#define GPIO_OSPEEDR_OSPEEDR12 ((uint32_t)0x03000000U) -#define GPIO_OSPEEDR_OSPEEDR12_0 ((uint32_t)0x01000000U) -#define GPIO_OSPEEDR_OSPEEDR12_1 ((uint32_t)0x02000000U) -#define GPIO_OSPEEDR_OSPEEDR13 ((uint32_t)0x0C000000U) -#define GPIO_OSPEEDR_OSPEEDR13_0 ((uint32_t)0x04000000U) -#define GPIO_OSPEEDR_OSPEEDR13_1 ((uint32_t)0x08000000U) -#define GPIO_OSPEEDR_OSPEEDR14 ((uint32_t)0x30000000U) -#define GPIO_OSPEEDR_OSPEEDR14_0 ((uint32_t)0x10000000U) -#define GPIO_OSPEEDR_OSPEEDR14_1 ((uint32_t)0x20000000U) -#define GPIO_OSPEEDR_OSPEEDR15 ((uint32_t)0xC0000000U) -#define GPIO_OSPEEDR_OSPEEDR15_0 ((uint32_t)0x40000000U) -#define GPIO_OSPEEDR_OSPEEDR15_1 ((uint32_t)0x80000000U) +#define GPIO_OSPEEDR_OSPEEDR0_Pos (0U) +#define GPIO_OSPEEDR_OSPEEDR0_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR0_Pos) /*!< 0x00000003 */ +#define GPIO_OSPEEDR_OSPEEDR0 GPIO_OSPEEDR_OSPEEDR0_Msk +#define GPIO_OSPEEDR_OSPEEDR0_0 (0x1U << GPIO_OSPEEDR_OSPEEDR0_Pos) /*!< 0x00000001 */ +#define GPIO_OSPEEDR_OSPEEDR0_1 (0x2U << GPIO_OSPEEDR_OSPEEDR0_Pos) /*!< 0x00000002 */ +#define GPIO_OSPEEDR_OSPEEDR1_Pos (2U) +#define GPIO_OSPEEDR_OSPEEDR1_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR1_Pos) /*!< 0x0000000C */ +#define GPIO_OSPEEDR_OSPEEDR1 GPIO_OSPEEDR_OSPEEDR1_Msk +#define GPIO_OSPEEDR_OSPEEDR1_0 (0x1U << GPIO_OSPEEDR_OSPEEDR1_Pos) /*!< 0x00000004 */ +#define GPIO_OSPEEDR_OSPEEDR1_1 (0x2U << GPIO_OSPEEDR_OSPEEDR1_Pos) /*!< 0x00000008 */ +#define GPIO_OSPEEDR_OSPEEDR2_Pos (4U) +#define GPIO_OSPEEDR_OSPEEDR2_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR2_Pos) /*!< 0x00000030 */ +#define GPIO_OSPEEDR_OSPEEDR2 GPIO_OSPEEDR_OSPEEDR2_Msk +#define GPIO_OSPEEDR_OSPEEDR2_0 (0x1U << GPIO_OSPEEDR_OSPEEDR2_Pos) /*!< 0x00000010 */ +#define GPIO_OSPEEDR_OSPEEDR2_1 (0x2U << GPIO_OSPEEDR_OSPEEDR2_Pos) /*!< 0x00000020 */ +#define GPIO_OSPEEDR_OSPEEDR3_Pos (6U) +#define GPIO_OSPEEDR_OSPEEDR3_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR3_Pos) /*!< 0x000000C0 */ +#define GPIO_OSPEEDR_OSPEEDR3 GPIO_OSPEEDR_OSPEEDR3_Msk +#define GPIO_OSPEEDR_OSPEEDR3_0 (0x1U << GPIO_OSPEEDR_OSPEEDR3_Pos) /*!< 0x00000040 */ +#define GPIO_OSPEEDR_OSPEEDR3_1 (0x2U << GPIO_OSPEEDR_OSPEEDR3_Pos) /*!< 0x00000080 */ +#define GPIO_OSPEEDR_OSPEEDR4_Pos (8U) +#define GPIO_OSPEEDR_OSPEEDR4_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR4_Pos) /*!< 0x00000300 */ +#define GPIO_OSPEEDR_OSPEEDR4 GPIO_OSPEEDR_OSPEEDR4_Msk +#define GPIO_OSPEEDR_OSPEEDR4_0 (0x1U << GPIO_OSPEEDR_OSPEEDR4_Pos) /*!< 0x00000100 */ +#define GPIO_OSPEEDR_OSPEEDR4_1 (0x2U << GPIO_OSPEEDR_OSPEEDR4_Pos) /*!< 0x00000200 */ +#define GPIO_OSPEEDR_OSPEEDR5_Pos (10U) +#define GPIO_OSPEEDR_OSPEEDR5_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR5_Pos) /*!< 0x00000C00 */ +#define GPIO_OSPEEDR_OSPEEDR5 GPIO_OSPEEDR_OSPEEDR5_Msk +#define GPIO_OSPEEDR_OSPEEDR5_0 (0x1U << GPIO_OSPEEDR_OSPEEDR5_Pos) /*!< 0x00000400 */ +#define GPIO_OSPEEDR_OSPEEDR5_1 (0x2U << GPIO_OSPEEDR_OSPEEDR5_Pos) /*!< 0x00000800 */ +#define GPIO_OSPEEDR_OSPEEDR6_Pos (12U) +#define GPIO_OSPEEDR_OSPEEDR6_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR6_Pos) /*!< 0x00003000 */ +#define GPIO_OSPEEDR_OSPEEDR6 GPIO_OSPEEDR_OSPEEDR6_Msk +#define GPIO_OSPEEDR_OSPEEDR6_0 (0x1U << GPIO_OSPEEDR_OSPEEDR6_Pos) /*!< 0x00001000 */ +#define GPIO_OSPEEDR_OSPEEDR6_1 (0x2U << GPIO_OSPEEDR_OSPEEDR6_Pos) /*!< 0x00002000 */ +#define GPIO_OSPEEDR_OSPEEDR7_Pos (14U) +#define GPIO_OSPEEDR_OSPEEDR7_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR7_Pos) /*!< 0x0000C000 */ +#define GPIO_OSPEEDR_OSPEEDR7 GPIO_OSPEEDR_OSPEEDR7_Msk +#define GPIO_OSPEEDR_OSPEEDR7_0 (0x1U << GPIO_OSPEEDR_OSPEEDR7_Pos) /*!< 0x00004000 */ +#define GPIO_OSPEEDR_OSPEEDR7_1 (0x2U << GPIO_OSPEEDR_OSPEEDR7_Pos) /*!< 0x00008000 */ +#define GPIO_OSPEEDR_OSPEEDR8_Pos (16U) +#define GPIO_OSPEEDR_OSPEEDR8_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR8_Pos) /*!< 0x00030000 */ +#define GPIO_OSPEEDR_OSPEEDR8 GPIO_OSPEEDR_OSPEEDR8_Msk +#define GPIO_OSPEEDR_OSPEEDR8_0 (0x1U << GPIO_OSPEEDR_OSPEEDR8_Pos) /*!< 0x00010000 */ +#define GPIO_OSPEEDR_OSPEEDR8_1 (0x2U << GPIO_OSPEEDR_OSPEEDR8_Pos) /*!< 0x00020000 */ +#define GPIO_OSPEEDR_OSPEEDR9_Pos (18U) +#define GPIO_OSPEEDR_OSPEEDR9_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR9_Pos) /*!< 0x000C0000 */ +#define GPIO_OSPEEDR_OSPEEDR9 GPIO_OSPEEDR_OSPEEDR9_Msk +#define GPIO_OSPEEDR_OSPEEDR9_0 (0x1U << GPIO_OSPEEDR_OSPEEDR9_Pos) /*!< 0x00040000 */ +#define GPIO_OSPEEDR_OSPEEDR9_1 (0x2U << GPIO_OSPEEDR_OSPEEDR9_Pos) /*!< 0x00080000 */ +#define GPIO_OSPEEDR_OSPEEDR10_Pos (20U) +#define GPIO_OSPEEDR_OSPEEDR10_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR10_Pos) /*!< 0x00300000 */ +#define GPIO_OSPEEDR_OSPEEDR10 GPIO_OSPEEDR_OSPEEDR10_Msk +#define GPIO_OSPEEDR_OSPEEDR10_0 (0x1U << GPIO_OSPEEDR_OSPEEDR10_Pos) /*!< 0x00100000 */ +#define GPIO_OSPEEDR_OSPEEDR10_1 (0x2U << GPIO_OSPEEDR_OSPEEDR10_Pos) /*!< 0x00200000 */ +#define GPIO_OSPEEDR_OSPEEDR11_Pos (22U) +#define GPIO_OSPEEDR_OSPEEDR11_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR11_Pos) /*!< 0x00C00000 */ +#define GPIO_OSPEEDR_OSPEEDR11 GPIO_OSPEEDR_OSPEEDR11_Msk +#define GPIO_OSPEEDR_OSPEEDR11_0 (0x1U << GPIO_OSPEEDR_OSPEEDR11_Pos) /*!< 0x00400000 */ +#define GPIO_OSPEEDR_OSPEEDR11_1 (0x2U << GPIO_OSPEEDR_OSPEEDR11_Pos) /*!< 0x00800000 */ +#define GPIO_OSPEEDR_OSPEEDR12_Pos (24U) +#define GPIO_OSPEEDR_OSPEEDR12_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR12_Pos) /*!< 0x03000000 */ +#define GPIO_OSPEEDR_OSPEEDR12 GPIO_OSPEEDR_OSPEEDR12_Msk +#define GPIO_OSPEEDR_OSPEEDR12_0 (0x1U << GPIO_OSPEEDR_OSPEEDR12_Pos) /*!< 0x01000000 */ +#define GPIO_OSPEEDR_OSPEEDR12_1 (0x2U << GPIO_OSPEEDR_OSPEEDR12_Pos) /*!< 0x02000000 */ +#define GPIO_OSPEEDR_OSPEEDR13_Pos (26U) +#define GPIO_OSPEEDR_OSPEEDR13_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR13_Pos) /*!< 0x0C000000 */ +#define GPIO_OSPEEDR_OSPEEDR13 GPIO_OSPEEDR_OSPEEDR13_Msk +#define GPIO_OSPEEDR_OSPEEDR13_0 (0x1U << GPIO_OSPEEDR_OSPEEDR13_Pos) /*!< 0x04000000 */ +#define GPIO_OSPEEDR_OSPEEDR13_1 (0x2U << GPIO_OSPEEDR_OSPEEDR13_Pos) /*!< 0x08000000 */ +#define GPIO_OSPEEDR_OSPEEDR14_Pos (28U) +#define GPIO_OSPEEDR_OSPEEDR14_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR14_Pos) /*!< 0x30000000 */ +#define GPIO_OSPEEDR_OSPEEDR14 GPIO_OSPEEDR_OSPEEDR14_Msk +#define GPIO_OSPEEDR_OSPEEDR14_0 (0x1U << GPIO_OSPEEDR_OSPEEDR14_Pos) /*!< 0x10000000 */ +#define GPIO_OSPEEDR_OSPEEDR14_1 (0x2U << GPIO_OSPEEDR_OSPEEDR14_Pos) /*!< 0x20000000 */ +#define GPIO_OSPEEDR_OSPEEDR15_Pos (30U) +#define GPIO_OSPEEDR_OSPEEDR15_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR15_Pos) /*!< 0xC0000000 */ +#define GPIO_OSPEEDR_OSPEEDR15 GPIO_OSPEEDR_OSPEEDR15_Msk +#define GPIO_OSPEEDR_OSPEEDR15_0 (0x1U << GPIO_OSPEEDR_OSPEEDR15_Pos) /*!< 0x40000000 */ +#define GPIO_OSPEEDR_OSPEEDR15_1 (0x2U << GPIO_OSPEEDR_OSPEEDR15_Pos) /*!< 0x80000000 */ /* Old Bit definition for GPIO_OSPEEDR register maintained for legacy purpose */ #define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEEDR0 @@ -1741,181 +2600,279 @@ typedef struct #define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEEDR15_1 /******************* Bit definition for GPIO_PUPDR register ******************/ -#define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003U) -#define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001U) -#define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002U) -#define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000CU) -#define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004U) -#define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008U) -#define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030U) -#define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010U) -#define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020U) -#define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0U) -#define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040U) -#define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080U) -#define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300U) -#define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100U) -#define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200U) -#define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00U) -#define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400U) -#define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800U) -#define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000U) -#define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000U) -#define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000U) -#define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000U) -#define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000U) -#define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000U) -#define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000U) -#define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000U) -#define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000U) -#define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000U) -#define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000U) -#define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000U) -#define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000U) -#define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000U) -#define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000U) -#define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000U) -#define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000U) -#define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000U) -#define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000U) -#define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000U) -#define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000U) -#define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000U) -#define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000U) -#define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000U) -#define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000U) -#define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000U) -#define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000U) -#define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000U) -#define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000U) -#define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000U) +#define GPIO_PUPDR_PUPDR0_Pos (0U) +#define GPIO_PUPDR_PUPDR0_Msk (0x3U << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000003 */ +#define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPDR0_Msk +#define GPIO_PUPDR_PUPDR0_0 (0x1U << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000001 */ +#define GPIO_PUPDR_PUPDR0_1 (0x2U << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000002 */ +#define GPIO_PUPDR_PUPDR1_Pos (2U) +#define GPIO_PUPDR_PUPDR1_Msk (0x3U << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x0000000C */ +#define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPDR1_Msk +#define GPIO_PUPDR_PUPDR1_0 (0x1U << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x00000004 */ +#define GPIO_PUPDR_PUPDR1_1 (0x2U << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x00000008 */ +#define GPIO_PUPDR_PUPDR2_Pos (4U) +#define GPIO_PUPDR_PUPDR2_Msk (0x3U << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000030 */ +#define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPDR2_Msk +#define GPIO_PUPDR_PUPDR2_0 (0x1U << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000010 */ +#define GPIO_PUPDR_PUPDR2_1 (0x2U << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000020 */ +#define GPIO_PUPDR_PUPDR3_Pos (6U) +#define GPIO_PUPDR_PUPDR3_Msk (0x3U << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x000000C0 */ +#define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPDR3_Msk +#define GPIO_PUPDR_PUPDR3_0 (0x1U << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x00000040 */ +#define GPIO_PUPDR_PUPDR3_1 (0x2U << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x00000080 */ +#define GPIO_PUPDR_PUPDR4_Pos (8U) +#define GPIO_PUPDR_PUPDR4_Msk (0x3U << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000300 */ +#define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPDR4_Msk +#define GPIO_PUPDR_PUPDR4_0 (0x1U << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000100 */ +#define GPIO_PUPDR_PUPDR4_1 (0x2U << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000200 */ +#define GPIO_PUPDR_PUPDR5_Pos (10U) +#define GPIO_PUPDR_PUPDR5_Msk (0x3U << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000C00 */ +#define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPDR5_Msk +#define GPIO_PUPDR_PUPDR5_0 (0x1U << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000400 */ +#define GPIO_PUPDR_PUPDR5_1 (0x2U << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000800 */ +#define GPIO_PUPDR_PUPDR6_Pos (12U) +#define GPIO_PUPDR_PUPDR6_Msk (0x3U << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00003000 */ +#define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPDR6_Msk +#define GPIO_PUPDR_PUPDR6_0 (0x1U << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00001000 */ +#define GPIO_PUPDR_PUPDR6_1 (0x2U << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00002000 */ +#define GPIO_PUPDR_PUPDR7_Pos (14U) +#define GPIO_PUPDR_PUPDR7_Msk (0x3U << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x0000C000 */ +#define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPDR7_Msk +#define GPIO_PUPDR_PUPDR7_0 (0x1U << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x00004000 */ +#define GPIO_PUPDR_PUPDR7_1 (0x2U << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x00008000 */ +#define GPIO_PUPDR_PUPDR8_Pos (16U) +#define GPIO_PUPDR_PUPDR8_Msk (0x3U << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00030000 */ +#define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPDR8_Msk +#define GPIO_PUPDR_PUPDR8_0 (0x1U << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00010000 */ +#define GPIO_PUPDR_PUPDR8_1 (0x2U << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00020000 */ +#define GPIO_PUPDR_PUPDR9_Pos (18U) +#define GPIO_PUPDR_PUPDR9_Msk (0x3U << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x000C0000 */ +#define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPDR9_Msk +#define GPIO_PUPDR_PUPDR9_0 (0x1U << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x00040000 */ +#define GPIO_PUPDR_PUPDR9_1 (0x2U << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x00080000 */ +#define GPIO_PUPDR_PUPDR10_Pos (20U) +#define GPIO_PUPDR_PUPDR10_Msk (0x3U << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00300000 */ +#define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPDR10_Msk +#define GPIO_PUPDR_PUPDR10_0 (0x1U << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00100000 */ +#define GPIO_PUPDR_PUPDR10_1 (0x2U << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00200000 */ +#define GPIO_PUPDR_PUPDR11_Pos (22U) +#define GPIO_PUPDR_PUPDR11_Msk (0x3U << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00C00000 */ +#define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPDR11_Msk +#define GPIO_PUPDR_PUPDR11_0 (0x1U << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00400000 */ +#define GPIO_PUPDR_PUPDR11_1 (0x2U << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00800000 */ +#define GPIO_PUPDR_PUPDR12_Pos (24U) +#define GPIO_PUPDR_PUPDR12_Msk (0x3U << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x03000000 */ +#define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPDR12_Msk +#define GPIO_PUPDR_PUPDR12_0 (0x1U << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x01000000 */ +#define GPIO_PUPDR_PUPDR12_1 (0x2U << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x02000000 */ +#define GPIO_PUPDR_PUPDR13_Pos (26U) +#define GPIO_PUPDR_PUPDR13_Msk (0x3U << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x0C000000 */ +#define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPDR13_Msk +#define GPIO_PUPDR_PUPDR13_0 (0x1U << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x04000000 */ +#define GPIO_PUPDR_PUPDR13_1 (0x2U << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x08000000 */ +#define GPIO_PUPDR_PUPDR14_Pos (28U) +#define GPIO_PUPDR_PUPDR14_Msk (0x3U << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x30000000 */ +#define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPDR14_Msk +#define GPIO_PUPDR_PUPDR14_0 (0x1U << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x10000000 */ +#define GPIO_PUPDR_PUPDR14_1 (0x2U << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x20000000 */ +#define GPIO_PUPDR_PUPDR15_Pos (30U) +#define GPIO_PUPDR_PUPDR15_Msk (0x3U << GPIO_PUPDR_PUPDR15_Pos) /*!< 0xC0000000 */ +#define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPDR15_Msk +#define GPIO_PUPDR_PUPDR15_0 (0x1U << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x40000000 */ +#define GPIO_PUPDR_PUPDR15_1 (0x2U << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x80000000 */ /******************* Bit definition for GPIO_IDR register *******************/ -#define GPIO_IDR_0 ((uint32_t)0x00000001U) -#define GPIO_IDR_1 ((uint32_t)0x00000002U) -#define GPIO_IDR_2 ((uint32_t)0x00000004U) -#define GPIO_IDR_3 ((uint32_t)0x00000008U) -#define GPIO_IDR_4 ((uint32_t)0x00000010U) -#define GPIO_IDR_5 ((uint32_t)0x00000020U) -#define GPIO_IDR_6 ((uint32_t)0x00000040U) -#define GPIO_IDR_7 ((uint32_t)0x00000080U) -#define GPIO_IDR_8 ((uint32_t)0x00000100U) -#define GPIO_IDR_9 ((uint32_t)0x00000200U) -#define GPIO_IDR_10 ((uint32_t)0x00000400U) -#define GPIO_IDR_11 ((uint32_t)0x00000800U) -#define GPIO_IDR_12 ((uint32_t)0x00001000U) -#define GPIO_IDR_13 ((uint32_t)0x00002000U) -#define GPIO_IDR_14 ((uint32_t)0x00004000U) -#define GPIO_IDR_15 ((uint32_t)0x00008000U) +#define GPIO_IDR_0 (0x00000001U) +#define GPIO_IDR_1 (0x00000002U) +#define GPIO_IDR_2 (0x00000004U) +#define GPIO_IDR_3 (0x00000008U) +#define GPIO_IDR_4 (0x00000010U) +#define GPIO_IDR_5 (0x00000020U) +#define GPIO_IDR_6 (0x00000040U) +#define GPIO_IDR_7 (0x00000080U) +#define GPIO_IDR_8 (0x00000100U) +#define GPIO_IDR_9 (0x00000200U) +#define GPIO_IDR_10 (0x00000400U) +#define GPIO_IDR_11 (0x00000800U) +#define GPIO_IDR_12 (0x00001000U) +#define GPIO_IDR_13 (0x00002000U) +#define GPIO_IDR_14 (0x00004000U) +#define GPIO_IDR_15 (0x00008000U) /****************** Bit definition for GPIO_ODR register ********************/ -#define GPIO_ODR_0 ((uint32_t)0x00000001U) -#define GPIO_ODR_1 ((uint32_t)0x00000002U) -#define GPIO_ODR_2 ((uint32_t)0x00000004U) -#define GPIO_ODR_3 ((uint32_t)0x00000008U) -#define GPIO_ODR_4 ((uint32_t)0x00000010U) -#define GPIO_ODR_5 ((uint32_t)0x00000020U) -#define GPIO_ODR_6 ((uint32_t)0x00000040U) -#define GPIO_ODR_7 ((uint32_t)0x00000080U) -#define GPIO_ODR_8 ((uint32_t)0x00000100U) -#define GPIO_ODR_9 ((uint32_t)0x00000200U) -#define GPIO_ODR_10 ((uint32_t)0x00000400U) -#define GPIO_ODR_11 ((uint32_t)0x00000800U) -#define GPIO_ODR_12 ((uint32_t)0x00001000U) -#define GPIO_ODR_13 ((uint32_t)0x00002000U) -#define GPIO_ODR_14 ((uint32_t)0x00004000U) -#define GPIO_ODR_15 ((uint32_t)0x00008000U) +#define GPIO_ODR_0 (0x00000001U) +#define GPIO_ODR_1 (0x00000002U) +#define GPIO_ODR_2 (0x00000004U) +#define GPIO_ODR_3 (0x00000008U) +#define GPIO_ODR_4 (0x00000010U) +#define GPIO_ODR_5 (0x00000020U) +#define GPIO_ODR_6 (0x00000040U) +#define GPIO_ODR_7 (0x00000080U) +#define GPIO_ODR_8 (0x00000100U) +#define GPIO_ODR_9 (0x00000200U) +#define GPIO_ODR_10 (0x00000400U) +#define GPIO_ODR_11 (0x00000800U) +#define GPIO_ODR_12 (0x00001000U) +#define GPIO_ODR_13 (0x00002000U) +#define GPIO_ODR_14 (0x00004000U) +#define GPIO_ODR_15 (0x00008000U) /****************** Bit definition for GPIO_BSRR register ********************/ -#define GPIO_BSRR_BS_0 ((uint32_t)0x00000001U) -#define GPIO_BSRR_BS_1 ((uint32_t)0x00000002U) -#define GPIO_BSRR_BS_2 ((uint32_t)0x00000004U) -#define GPIO_BSRR_BS_3 ((uint32_t)0x00000008U) -#define GPIO_BSRR_BS_4 ((uint32_t)0x00000010U) -#define GPIO_BSRR_BS_5 ((uint32_t)0x00000020U) -#define GPIO_BSRR_BS_6 ((uint32_t)0x00000040U) -#define GPIO_BSRR_BS_7 ((uint32_t)0x00000080U) -#define GPIO_BSRR_BS_8 ((uint32_t)0x00000100U) -#define GPIO_BSRR_BS_9 ((uint32_t)0x00000200U) -#define GPIO_BSRR_BS_10 ((uint32_t)0x00000400U) -#define GPIO_BSRR_BS_11 ((uint32_t)0x00000800U) -#define GPIO_BSRR_BS_12 ((uint32_t)0x00001000U) -#define GPIO_BSRR_BS_13 ((uint32_t)0x00002000U) -#define GPIO_BSRR_BS_14 ((uint32_t)0x00004000U) -#define GPIO_BSRR_BS_15 ((uint32_t)0x00008000U) -#define GPIO_BSRR_BR_0 ((uint32_t)0x00010000U) -#define GPIO_BSRR_BR_1 ((uint32_t)0x00020000U) -#define GPIO_BSRR_BR_2 ((uint32_t)0x00040000U) -#define GPIO_BSRR_BR_3 ((uint32_t)0x00080000U) -#define GPIO_BSRR_BR_4 ((uint32_t)0x00100000U) -#define GPIO_BSRR_BR_5 ((uint32_t)0x00200000U) -#define GPIO_BSRR_BR_6 ((uint32_t)0x00400000U) -#define GPIO_BSRR_BR_7 ((uint32_t)0x00800000U) -#define GPIO_BSRR_BR_8 ((uint32_t)0x01000000U) -#define GPIO_BSRR_BR_9 ((uint32_t)0x02000000U) -#define GPIO_BSRR_BR_10 ((uint32_t)0x04000000U) -#define GPIO_BSRR_BR_11 ((uint32_t)0x08000000U) -#define GPIO_BSRR_BR_12 ((uint32_t)0x10000000U) -#define GPIO_BSRR_BR_13 ((uint32_t)0x20000000U) -#define GPIO_BSRR_BR_14 ((uint32_t)0x40000000U) -#define GPIO_BSRR_BR_15 ((uint32_t)0x80000000U) +#define GPIO_BSRR_BS_0 (0x00000001U) +#define GPIO_BSRR_BS_1 (0x00000002U) +#define GPIO_BSRR_BS_2 (0x00000004U) +#define GPIO_BSRR_BS_3 (0x00000008U) +#define GPIO_BSRR_BS_4 (0x00000010U) +#define GPIO_BSRR_BS_5 (0x00000020U) +#define GPIO_BSRR_BS_6 (0x00000040U) +#define GPIO_BSRR_BS_7 (0x00000080U) +#define GPIO_BSRR_BS_8 (0x00000100U) +#define GPIO_BSRR_BS_9 (0x00000200U) +#define GPIO_BSRR_BS_10 (0x00000400U) +#define GPIO_BSRR_BS_11 (0x00000800U) +#define GPIO_BSRR_BS_12 (0x00001000U) +#define GPIO_BSRR_BS_13 (0x00002000U) +#define GPIO_BSRR_BS_14 (0x00004000U) +#define GPIO_BSRR_BS_15 (0x00008000U) +#define GPIO_BSRR_BR_0 (0x00010000U) +#define GPIO_BSRR_BR_1 (0x00020000U) +#define GPIO_BSRR_BR_2 (0x00040000U) +#define GPIO_BSRR_BR_3 (0x00080000U) +#define GPIO_BSRR_BR_4 (0x00100000U) +#define GPIO_BSRR_BR_5 (0x00200000U) +#define GPIO_BSRR_BR_6 (0x00400000U) +#define GPIO_BSRR_BR_7 (0x00800000U) +#define GPIO_BSRR_BR_8 (0x01000000U) +#define GPIO_BSRR_BR_9 (0x02000000U) +#define GPIO_BSRR_BR_10 (0x04000000U) +#define GPIO_BSRR_BR_11 (0x08000000U) +#define GPIO_BSRR_BR_12 (0x10000000U) +#define GPIO_BSRR_BR_13 (0x20000000U) +#define GPIO_BSRR_BR_14 (0x40000000U) +#define GPIO_BSRR_BR_15 (0x80000000U) /****************** Bit definition for GPIO_LCKR register ********************/ -#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001U) -#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002U) -#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004U) -#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008U) -#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010U) -#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020U) -#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040U) -#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080U) -#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100U) -#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200U) -#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400U) -#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800U) -#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000U) -#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000U) -#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000U) -#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000U) -#define GPIO_LCKR_LCKK ((uint32_t)0x00010000U) +#define GPIO_LCKR_LCK0_Pos (0U) +#define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */ +#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk +#define GPIO_LCKR_LCK1_Pos (1U) +#define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */ +#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk +#define GPIO_LCKR_LCK2_Pos (2U) +#define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */ +#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk +#define GPIO_LCKR_LCK3_Pos (3U) +#define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */ +#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk +#define GPIO_LCKR_LCK4_Pos (4U) +#define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */ +#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk +#define GPIO_LCKR_LCK5_Pos (5U) +#define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */ +#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk +#define GPIO_LCKR_LCK6_Pos (6U) +#define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */ +#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk +#define GPIO_LCKR_LCK7_Pos (7U) +#define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */ +#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk +#define GPIO_LCKR_LCK8_Pos (8U) +#define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */ +#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk +#define GPIO_LCKR_LCK9_Pos (9U) +#define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */ +#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk +#define GPIO_LCKR_LCK10_Pos (10U) +#define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */ +#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk +#define GPIO_LCKR_LCK11_Pos (11U) +#define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */ +#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk +#define GPIO_LCKR_LCK12_Pos (12U) +#define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */ +#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk +#define GPIO_LCKR_LCK13_Pos (13U) +#define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */ +#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk +#define GPIO_LCKR_LCK14_Pos (14U) +#define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */ +#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk +#define GPIO_LCKR_LCK15_Pos (15U) +#define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */ +#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk +#define GPIO_LCKR_LCKK_Pos (16U) +#define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */ +#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk /****************** Bit definition for GPIO_AFRL register ********************/ -#define GPIO_AFRL_AFRL0 ((uint32_t)0x0000000FU) -#define GPIO_AFRL_AFRL1 ((uint32_t)0x000000F0U) -#define GPIO_AFRL_AFRL2 ((uint32_t)0x00000F00U) -#define GPIO_AFRL_AFRL3 ((uint32_t)0x0000F000U) -#define GPIO_AFRL_AFRL4 ((uint32_t)0x000F0000U) -#define GPIO_AFRL_AFRL5 ((uint32_t)0x00F00000U) -#define GPIO_AFRL_AFRL6 ((uint32_t)0x0F000000U) -#define GPIO_AFRL_AFRL7 ((uint32_t)0xF0000000U) +#define GPIO_AFRL_AFRL0_Pos (0U) +#define GPIO_AFRL_AFRL0_Msk (0xFU << GPIO_AFRL_AFRL0_Pos) /*!< 0x0000000F */ +#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFRL0_Msk +#define GPIO_AFRL_AFRL1_Pos (4U) +#define GPIO_AFRL_AFRL1_Msk (0xFU << GPIO_AFRL_AFRL1_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFRL1_Msk +#define GPIO_AFRL_AFRL2_Pos (8U) +#define GPIO_AFRL_AFRL2_Msk (0xFU << GPIO_AFRL_AFRL2_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFRL2_Msk +#define GPIO_AFRL_AFRL3_Pos (12U) +#define GPIO_AFRL_AFRL3_Msk (0xFU << GPIO_AFRL_AFRL3_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFRL3_Msk +#define GPIO_AFRL_AFRL4_Pos (16U) +#define GPIO_AFRL_AFRL4_Msk (0xFU << GPIO_AFRL_AFRL4_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFRL4_Msk +#define GPIO_AFRL_AFRL5_Pos (20U) +#define GPIO_AFRL_AFRL5_Msk (0xFU << GPIO_AFRL_AFRL5_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFRL5_Msk +#define GPIO_AFRL_AFRL6_Pos (24U) +#define GPIO_AFRL_AFRL6_Msk (0xFU << GPIO_AFRL_AFRL6_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFRL6_Msk +#define GPIO_AFRL_AFRL7_Pos (28U) +#define GPIO_AFRL_AFRL7_Msk (0xFU << GPIO_AFRL_AFRL7_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFRL7_Msk /****************** Bit definition for GPIO_AFRH register ********************/ -#define GPIO_AFRH_AFRH0 ((uint32_t)0x0000000FU) -#define GPIO_AFRH_AFRH1 ((uint32_t)0x000000F0U) -#define GPIO_AFRH_AFRH2 ((uint32_t)0x00000F00U) -#define GPIO_AFRH_AFRH3 ((uint32_t)0x0000F000U) -#define GPIO_AFRH_AFRH4 ((uint32_t)0x000F0000U) -#define GPIO_AFRH_AFRH5 ((uint32_t)0x00F00000U) -#define GPIO_AFRH_AFRH6 ((uint32_t)0x0F000000U) -#define GPIO_AFRH_AFRH7 ((uint32_t)0xF0000000U) +#define GPIO_AFRH_AFRH0_Pos (0U) +#define GPIO_AFRH_AFRH0_Msk (0xFU << GPIO_AFRH_AFRH0_Pos) /*!< 0x0000000F */ +#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFRH0_Msk +#define GPIO_AFRH_AFRH1_Pos (4U) +#define GPIO_AFRH_AFRH1_Msk (0xFU << GPIO_AFRH_AFRH1_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFRH1_Msk +#define GPIO_AFRH_AFRH2_Pos (8U) +#define GPIO_AFRH_AFRH2_Msk (0xFU << GPIO_AFRH_AFRH2_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFRH2_Msk +#define GPIO_AFRH_AFRH3_Pos (12U) +#define GPIO_AFRH_AFRH3_Msk (0xFU << GPIO_AFRH_AFRH3_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFRH3_Msk +#define GPIO_AFRH_AFRH4_Pos (16U) +#define GPIO_AFRH_AFRH4_Msk (0xFU << GPIO_AFRH_AFRH4_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFRH4_Msk +#define GPIO_AFRH_AFRH5_Pos (20U) +#define GPIO_AFRH_AFRH5_Msk (0xFU << GPIO_AFRH_AFRH5_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFRH5_Msk +#define GPIO_AFRH_AFRH6_Pos (24U) +#define GPIO_AFRH_AFRH6_Msk (0xFU << GPIO_AFRH_AFRH6_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFRH6_Msk +#define GPIO_AFRH_AFRH7_Pos (28U) +#define GPIO_AFRH_AFRH7_Msk (0xFU << GPIO_AFRH_AFRH7_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFRH7_Msk /****************** Bit definition for GPIO_BRR register *********************/ -#define GPIO_BRR_BR_0 ((uint32_t)0x00000001U) -#define GPIO_BRR_BR_1 ((uint32_t)0x00000002U) -#define GPIO_BRR_BR_2 ((uint32_t)0x00000004U) -#define GPIO_BRR_BR_3 ((uint32_t)0x00000008U) -#define GPIO_BRR_BR_4 ((uint32_t)0x00000010U) -#define GPIO_BRR_BR_5 ((uint32_t)0x00000020U) -#define GPIO_BRR_BR_6 ((uint32_t)0x00000040U) -#define GPIO_BRR_BR_7 ((uint32_t)0x00000080U) -#define GPIO_BRR_BR_8 ((uint32_t)0x00000100U) -#define GPIO_BRR_BR_9 ((uint32_t)0x00000200U) -#define GPIO_BRR_BR_10 ((uint32_t)0x00000400U) -#define GPIO_BRR_BR_11 ((uint32_t)0x00000800U) -#define GPIO_BRR_BR_12 ((uint32_t)0x00001000U) -#define GPIO_BRR_BR_13 ((uint32_t)0x00002000U) -#define GPIO_BRR_BR_14 ((uint32_t)0x00004000U) -#define GPIO_BRR_BR_15 ((uint32_t)0x00008000U) +#define GPIO_BRR_BR_0 (0x00000001U) +#define GPIO_BRR_BR_1 (0x00000002U) +#define GPIO_BRR_BR_2 (0x00000004U) +#define GPIO_BRR_BR_3 (0x00000008U) +#define GPIO_BRR_BR_4 (0x00000010U) +#define GPIO_BRR_BR_5 (0x00000020U) +#define GPIO_BRR_BR_6 (0x00000040U) +#define GPIO_BRR_BR_7 (0x00000080U) +#define GPIO_BRR_BR_8 (0x00000100U) +#define GPIO_BRR_BR_9 (0x00000200U) +#define GPIO_BRR_BR_10 (0x00000400U) +#define GPIO_BRR_BR_11 (0x00000800U) +#define GPIO_BRR_BR_12 (0x00001000U) +#define GPIO_BRR_BR_13 (0x00002000U) +#define GPIO_BRR_BR_14 (0x00004000U) +#define GPIO_BRR_BR_15 (0x00008000U) /******************************************************************************/ /* */ @@ -1924,111 +2881,279 @@ typedef struct /******************************************************************************/ /******************* Bit definition for I2C_CR1 register *******************/ -#define I2C_CR1_PE ((uint32_t)0x00000001U) /*!< Peripheral enable */ -#define I2C_CR1_TXIE ((uint32_t)0x00000002U) /*!< TX interrupt enable */ -#define I2C_CR1_RXIE ((uint32_t)0x00000004U) /*!< RX interrupt enable */ -#define I2C_CR1_ADDRIE ((uint32_t)0x00000008U) /*!< Address match interrupt enable */ -#define I2C_CR1_NACKIE ((uint32_t)0x00000010U) /*!< NACK received interrupt enable */ -#define I2C_CR1_STOPIE ((uint32_t)0x00000020U) /*!< STOP detection interrupt enable */ -#define I2C_CR1_TCIE ((uint32_t)0x00000040U) /*!< Transfer complete interrupt enable */ -#define I2C_CR1_ERRIE ((uint32_t)0x00000080U) /*!< Errors interrupt enable */ -#define I2C_CR1_DNF ((uint32_t)0x00000F00U) /*!< Digital noise filter */ -#define I2C_CR1_ANFOFF ((uint32_t)0x00001000U) /*!< Analog noise filter OFF */ -#define I2C_CR1_SWRST ((uint32_t)0x00002000U) /*!< Software reset */ -#define I2C_CR1_TXDMAEN ((uint32_t)0x00004000U) /*!< DMA transmission requests enable */ -#define I2C_CR1_RXDMAEN ((uint32_t)0x00008000U) /*!< DMA reception requests enable */ -#define I2C_CR1_SBC ((uint32_t)0x00010000U) /*!< Slave byte control */ -#define I2C_CR1_NOSTRETCH ((uint32_t)0x00020000U) /*!< Clock stretching disable */ -#define I2C_CR1_WUPEN ((uint32_t)0x00040000U) /*!< Wakeup from STOP enable */ -#define I2C_CR1_GCEN ((uint32_t)0x00080000U) /*!< General call enable */ -#define I2C_CR1_SMBHEN ((uint32_t)0x00100000U) /*!< SMBus host address enable */ -#define I2C_CR1_SMBDEN ((uint32_t)0x00200000U) /*!< SMBus device default address enable */ -#define I2C_CR1_ALERTEN ((uint32_t)0x00400000U) /*!< SMBus alert enable */ -#define I2C_CR1_PECEN ((uint32_t)0x00800000U) /*!< PEC enable */ +#define I2C_CR1_PE_Pos (0U) +#define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /*!< 0x00000001 */ +#define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */ +#define I2C_CR1_TXIE_Pos (1U) +#define I2C_CR1_TXIE_Msk (0x1U << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */ +#define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */ +#define I2C_CR1_RXIE_Pos (2U) +#define I2C_CR1_RXIE_Msk (0x1U << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */ +#define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */ +#define I2C_CR1_ADDRIE_Pos (3U) +#define I2C_CR1_ADDRIE_Msk (0x1U << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */ +#define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */ +#define I2C_CR1_NACKIE_Pos (4U) +#define I2C_CR1_NACKIE_Msk (0x1U << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */ +#define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */ +#define I2C_CR1_STOPIE_Pos (5U) +#define I2C_CR1_STOPIE_Msk (0x1U << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */ +#define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */ +#define I2C_CR1_TCIE_Pos (6U) +#define I2C_CR1_TCIE_Msk (0x1U << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */ +#define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */ +#define I2C_CR1_ERRIE_Pos (7U) +#define I2C_CR1_ERRIE_Msk (0x1U << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */ +#define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */ +#define I2C_CR1_DNF_Pos (8U) +#define I2C_CR1_DNF_Msk (0xFU << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */ +#define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */ +#define I2C_CR1_ANFOFF_Pos (12U) +#define I2C_CR1_ANFOFF_Msk (0x1U << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */ +#define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */ +#define I2C_CR1_SWRST_Pos (13U) +#define I2C_CR1_SWRST_Msk (0x1U << I2C_CR1_SWRST_Pos) /*!< 0x00002000 */ +#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software reset */ +#define I2C_CR1_TXDMAEN_Pos (14U) +#define I2C_CR1_TXDMAEN_Msk (0x1U << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */ +#define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */ +#define I2C_CR1_RXDMAEN_Pos (15U) +#define I2C_CR1_RXDMAEN_Msk (0x1U << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */ +#define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */ +#define I2C_CR1_SBC_Pos (16U) +#define I2C_CR1_SBC_Msk (0x1U << I2C_CR1_SBC_Pos) /*!< 0x00010000 */ +#define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */ +#define I2C_CR1_NOSTRETCH_Pos (17U) +#define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */ +#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */ +#define I2C_CR1_WUPEN_Pos (18U) +#define I2C_CR1_WUPEN_Msk (0x1U << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */ +#define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */ +#define I2C_CR1_GCEN_Pos (19U) +#define I2C_CR1_GCEN_Msk (0x1U << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */ +#define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */ +#define I2C_CR1_SMBHEN_Pos (20U) +#define I2C_CR1_SMBHEN_Msk (0x1U << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */ +#define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */ +#define I2C_CR1_SMBDEN_Pos (21U) +#define I2C_CR1_SMBDEN_Msk (0x1U << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */ +#define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */ +#define I2C_CR1_ALERTEN_Pos (22U) +#define I2C_CR1_ALERTEN_Msk (0x1U << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */ +#define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */ +#define I2C_CR1_PECEN_Pos (23U) +#define I2C_CR1_PECEN_Msk (0x1U << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */ +#define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */ /****************** Bit definition for I2C_CR2 register ********************/ -#define I2C_CR2_SADD ((uint32_t)0x000003FFU) /*!< Slave address (master mode) */ -#define I2C_CR2_RD_WRN ((uint32_t)0x00000400U) /*!< Transfer direction (master mode) */ -#define I2C_CR2_ADD10 ((uint32_t)0x00000800U) /*!< 10-bit addressing mode (master mode) */ -#define I2C_CR2_HEAD10R ((uint32_t)0x00001000U) /*!< 10-bit address header only read direction (master mode) */ -#define I2C_CR2_START ((uint32_t)0x00002000U) /*!< START generation */ -#define I2C_CR2_STOP ((uint32_t)0x00004000U) /*!< STOP generation (master mode) */ -#define I2C_CR2_NACK ((uint32_t)0x00008000U) /*!< NACK generation (slave mode) */ -#define I2C_CR2_NBYTES ((uint32_t)0x00FF0000U) /*!< Number of bytes */ -#define I2C_CR2_RELOAD ((uint32_t)0x01000000U) /*!< NBYTES reload mode */ -#define I2C_CR2_AUTOEND ((uint32_t)0x02000000U) /*!< Automatic end mode (master mode) */ -#define I2C_CR2_PECBYTE ((uint32_t)0x04000000U) /*!< Packet error checking byte */ +#define I2C_CR2_SADD_Pos (0U) +#define I2C_CR2_SADD_Msk (0x3FFU << I2C_CR2_SADD_Pos) /*!< 0x000003FF */ +#define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */ +#define I2C_CR2_RD_WRN_Pos (10U) +#define I2C_CR2_RD_WRN_Msk (0x1U << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */ +#define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */ +#define I2C_CR2_ADD10_Pos (11U) +#define I2C_CR2_ADD10_Msk (0x1U << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */ +#define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */ +#define I2C_CR2_HEAD10R_Pos (12U) +#define I2C_CR2_HEAD10R_Msk (0x1U << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */ +#define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */ +#define I2C_CR2_START_Pos (13U) +#define I2C_CR2_START_Msk (0x1U << I2C_CR2_START_Pos) /*!< 0x00002000 */ +#define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */ +#define I2C_CR2_STOP_Pos (14U) +#define I2C_CR2_STOP_Msk (0x1U << I2C_CR2_STOP_Pos) /*!< 0x00004000 */ +#define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */ +#define I2C_CR2_NACK_Pos (15U) +#define I2C_CR2_NACK_Msk (0x1U << I2C_CR2_NACK_Pos) /*!< 0x00008000 */ +#define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */ +#define I2C_CR2_NBYTES_Pos (16U) +#define I2C_CR2_NBYTES_Msk (0xFFU << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */ +#define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */ +#define I2C_CR2_RELOAD_Pos (24U) +#define I2C_CR2_RELOAD_Msk (0x1U << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */ +#define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */ +#define I2C_CR2_AUTOEND_Pos (25U) +#define I2C_CR2_AUTOEND_Msk (0x1U << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */ +#define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */ +#define I2C_CR2_PECBYTE_Pos (26U) +#define I2C_CR2_PECBYTE_Msk (0x1U << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */ +#define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */ /******************* Bit definition for I2C_OAR1 register ******************/ -#define I2C_OAR1_OA1 ((uint32_t)0x000003FFU) /*!< Interface own address 1 */ -#define I2C_OAR1_OA1MODE ((uint32_t)0x00000400U) /*!< Own address 1 10-bit mode */ -#define I2C_OAR1_OA1EN ((uint32_t)0x00008000U) /*!< Own address 1 enable */ +#define I2C_OAR1_OA1_Pos (0U) +#define I2C_OAR1_OA1_Msk (0x3FFU << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */ +#define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */ +#define I2C_OAR1_OA1MODE_Pos (10U) +#define I2C_OAR1_OA1MODE_Msk (0x1U << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */ +#define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */ +#define I2C_OAR1_OA1EN_Pos (15U) +#define I2C_OAR1_OA1EN_Msk (0x1U << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */ +#define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */ /******************* Bit definition for I2C_OAR2 register ******************/ -#define I2C_OAR2_OA2 ((uint32_t)0x000000FEU) /*!< Interface own address 2 */ -#define I2C_OAR2_OA2MSK ((uint32_t)0x00000700U) /*!< Own address 2 masks */ -#define I2C_OAR2_OA2NOMASK ((uint32_t)0x00000000U) /*!< No mask */ -#define I2C_OAR2_OA2MASK01 ((uint32_t)0x00000100U) /*!< OA2[1] is masked, Only OA2[7:2] are compared */ -#define I2C_OAR2_OA2MASK02 ((uint32_t)0x00000200U) /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */ -#define I2C_OAR2_OA2MASK03 ((uint32_t)0x00000300U) /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */ -#define I2C_OAR2_OA2MASK04 ((uint32_t)0x00000400U) /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */ -#define I2C_OAR2_OA2MASK05 ((uint32_t)0x00000500U) /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */ -#define I2C_OAR2_OA2MASK06 ((uint32_t)0x00000600U) /*!< OA2[6:1] is masked, Only OA2[7] are compared */ -#define I2C_OAR2_OA2MASK07 ((uint32_t)0x00000700U) /*!< OA2[7:1] is masked, No comparison is done */ -#define I2C_OAR2_OA2EN ((uint32_t)0x00008000U) /*!< Own address 2 enable */ +#define I2C_OAR2_OA2_Pos (1U) +#define I2C_OAR2_OA2_Msk (0x7FU << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */ +#define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */ +#define I2C_OAR2_OA2MSK_Pos (8U) +#define I2C_OAR2_OA2MSK_Msk (0x7U << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */ +#define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */ +#define I2C_OAR2_OA2NOMASK (0x00000000U) /*!< No mask */ +#define I2C_OAR2_OA2MASK01_Pos (8U) +#define I2C_OAR2_OA2MASK01_Msk (0x1U << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */ +#define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */ +#define I2C_OAR2_OA2MASK02_Pos (9U) +#define I2C_OAR2_OA2MASK02_Msk (0x1U << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */ +#define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */ +#define I2C_OAR2_OA2MASK03_Pos (8U) +#define I2C_OAR2_OA2MASK03_Msk (0x3U << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */ +#define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */ +#define I2C_OAR2_OA2MASK04_Pos (10U) +#define I2C_OAR2_OA2MASK04_Msk (0x1U << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */ +#define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */ +#define I2C_OAR2_OA2MASK05_Pos (8U) +#define I2C_OAR2_OA2MASK05_Msk (0x5U << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */ +#define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */ +#define I2C_OAR2_OA2MASK06_Pos (9U) +#define I2C_OAR2_OA2MASK06_Msk (0x3U << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */ +#define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */ +#define I2C_OAR2_OA2MASK07_Pos (8U) +#define I2C_OAR2_OA2MASK07_Msk (0x7U << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */ +#define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */ +#define I2C_OAR2_OA2EN_Pos (15U) +#define I2C_OAR2_OA2EN_Msk (0x1U << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */ +#define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */ /******************* Bit definition for I2C_TIMINGR register ****************/ -#define I2C_TIMINGR_SCLL ((uint32_t)0x000000FFU) /*!< SCL low period (master mode) */ -#define I2C_TIMINGR_SCLH ((uint32_t)0x0000FF00U) /*!< SCL high period (master mode) */ -#define I2C_TIMINGR_SDADEL ((uint32_t)0x000F0000U) /*!< Data hold time */ -#define I2C_TIMINGR_SCLDEL ((uint32_t)0x00F00000U) /*!< Data setup time */ -#define I2C_TIMINGR_PRESC ((uint32_t)0xF0000000U) /*!< Timings prescaler */ +#define I2C_TIMINGR_SCLL_Pos (0U) +#define I2C_TIMINGR_SCLL_Msk (0xFFU << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */ +#define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */ +#define I2C_TIMINGR_SCLH_Pos (8U) +#define I2C_TIMINGR_SCLH_Msk (0xFFU << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */ +#define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */ +#define I2C_TIMINGR_SDADEL_Pos (16U) +#define I2C_TIMINGR_SDADEL_Msk (0xFU << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */ +#define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */ +#define I2C_TIMINGR_SCLDEL_Pos (20U) +#define I2C_TIMINGR_SCLDEL_Msk (0xFU << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */ +#define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */ +#define I2C_TIMINGR_PRESC_Pos (28U) +#define I2C_TIMINGR_PRESC_Msk (0xFU << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */ +#define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */ /******************* Bit definition for I2C_TIMEOUTR register ****************/ -#define I2C_TIMEOUTR_TIMEOUTA ((uint32_t)0x00000FFFU) /*!< Bus timeout A */ -#define I2C_TIMEOUTR_TIDLE ((uint32_t)0x00001000U) /*!< Idle clock timeout detection */ -#define I2C_TIMEOUTR_TIMOUTEN ((uint32_t)0x00008000U) /*!< Clock timeout enable */ -#define I2C_TIMEOUTR_TIMEOUTB ((uint32_t)0x0FFF0000U) /*!< Bus timeout B*/ -#define I2C_TIMEOUTR_TEXTEN ((uint32_t)0x80000000U) /*!< Extended clock timeout enable */ +#define I2C_TIMEOUTR_TIMEOUTA_Pos (0U) +#define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFU << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */ +#define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */ +#define I2C_TIMEOUTR_TIDLE_Pos (12U) +#define I2C_TIMEOUTR_TIDLE_Msk (0x1U << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */ +#define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */ +#define I2C_TIMEOUTR_TIMOUTEN_Pos (15U) +#define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1U << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */ +#define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */ +#define I2C_TIMEOUTR_TIMEOUTB_Pos (16U) +#define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFU << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */ +#define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B*/ +#define I2C_TIMEOUTR_TEXTEN_Pos (31U) +#define I2C_TIMEOUTR_TEXTEN_Msk (0x1U << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */ +#define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */ /****************** Bit definition for I2C_ISR register ********************/ -#define I2C_ISR_TXE ((uint32_t)0x00000001U) /*!< Transmit data register empty */ -#define I2C_ISR_TXIS ((uint32_t)0x00000002U) /*!< Transmit interrupt status */ -#define I2C_ISR_RXNE ((uint32_t)0x00000004U) /*!< Receive data register not empty */ -#define I2C_ISR_ADDR ((uint32_t)0x00000008U) /*!< Address matched (slave mode)*/ -#define I2C_ISR_NACKF ((uint32_t)0x00000010U) /*!< NACK received flag */ -#define I2C_ISR_STOPF ((uint32_t)0x00000020U) /*!< STOP detection flag */ -#define I2C_ISR_TC ((uint32_t)0x00000040U) /*!< Transfer complete (master mode) */ -#define I2C_ISR_TCR ((uint32_t)0x00000080U) /*!< Transfer complete reload */ -#define I2C_ISR_BERR ((uint32_t)0x00000100U) /*!< Bus error */ -#define I2C_ISR_ARLO ((uint32_t)0x00000200U) /*!< Arbitration lost */ -#define I2C_ISR_OVR ((uint32_t)0x00000400U) /*!< Overrun/Underrun */ -#define I2C_ISR_PECERR ((uint32_t)0x00000800U) /*!< PEC error in reception */ -#define I2C_ISR_TIMEOUT ((uint32_t)0x00001000U) /*!< Timeout or Tlow detection flag */ -#define I2C_ISR_ALERT ((uint32_t)0x00002000U) /*!< SMBus alert */ -#define I2C_ISR_BUSY ((uint32_t)0x00008000U) /*!< Bus busy */ -#define I2C_ISR_DIR ((uint32_t)0x00010000U) /*!< Transfer direction (slave mode) */ -#define I2C_ISR_ADDCODE ((uint32_t)0x00FE0000U) /*!< Address match code (slave mode) */ +#define I2C_ISR_TXE_Pos (0U) +#define I2C_ISR_TXE_Msk (0x1U << I2C_ISR_TXE_Pos) /*!< 0x00000001 */ +#define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */ +#define I2C_ISR_TXIS_Pos (1U) +#define I2C_ISR_TXIS_Msk (0x1U << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */ +#define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */ +#define I2C_ISR_RXNE_Pos (2U) +#define I2C_ISR_RXNE_Msk (0x1U << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */ +#define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */ +#define I2C_ISR_ADDR_Pos (3U) +#define I2C_ISR_ADDR_Msk (0x1U << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */ +#define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode)*/ +#define I2C_ISR_NACKF_Pos (4U) +#define I2C_ISR_NACKF_Msk (0x1U << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */ +#define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */ +#define I2C_ISR_STOPF_Pos (5U) +#define I2C_ISR_STOPF_Msk (0x1U << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */ +#define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */ +#define I2C_ISR_TC_Pos (6U) +#define I2C_ISR_TC_Msk (0x1U << I2C_ISR_TC_Pos) /*!< 0x00000040 */ +#define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */ +#define I2C_ISR_TCR_Pos (7U) +#define I2C_ISR_TCR_Msk (0x1U << I2C_ISR_TCR_Pos) /*!< 0x00000080 */ +#define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */ +#define I2C_ISR_BERR_Pos (8U) +#define I2C_ISR_BERR_Msk (0x1U << I2C_ISR_BERR_Pos) /*!< 0x00000100 */ +#define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */ +#define I2C_ISR_ARLO_Pos (9U) +#define I2C_ISR_ARLO_Msk (0x1U << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */ +#define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */ +#define I2C_ISR_OVR_Pos (10U) +#define I2C_ISR_OVR_Msk (0x1U << I2C_ISR_OVR_Pos) /*!< 0x00000400 */ +#define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */ +#define I2C_ISR_PECERR_Pos (11U) +#define I2C_ISR_PECERR_Msk (0x1U << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */ +#define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */ +#define I2C_ISR_TIMEOUT_Pos (12U) +#define I2C_ISR_TIMEOUT_Msk (0x1U << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */ +#define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */ +#define I2C_ISR_ALERT_Pos (13U) +#define I2C_ISR_ALERT_Msk (0x1U << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */ +#define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */ +#define I2C_ISR_BUSY_Pos (15U) +#define I2C_ISR_BUSY_Msk (0x1U << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */ +#define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */ +#define I2C_ISR_DIR_Pos (16U) +#define I2C_ISR_DIR_Msk (0x1U << I2C_ISR_DIR_Pos) /*!< 0x00010000 */ +#define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */ +#define I2C_ISR_ADDCODE_Pos (17U) +#define I2C_ISR_ADDCODE_Msk (0x7FU << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */ +#define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */ /****************** Bit definition for I2C_ICR register ********************/ -#define I2C_ICR_ADDRCF ((uint32_t)0x00000008U) /*!< Address matched clear flag */ -#define I2C_ICR_NACKCF ((uint32_t)0x00000010U) /*!< NACK clear flag */ -#define I2C_ICR_STOPCF ((uint32_t)0x00000020U) /*!< STOP detection clear flag */ -#define I2C_ICR_BERRCF ((uint32_t)0x00000100U) /*!< Bus error clear flag */ -#define I2C_ICR_ARLOCF ((uint32_t)0x00000200U) /*!< Arbitration lost clear flag */ -#define I2C_ICR_OVRCF ((uint32_t)0x00000400U) /*!< Overrun/Underrun clear flag */ -#define I2C_ICR_PECCF ((uint32_t)0x00000800U) /*!< PAC error clear flag */ -#define I2C_ICR_TIMOUTCF ((uint32_t)0x00001000U) /*!< Timeout clear flag */ -#define I2C_ICR_ALERTCF ((uint32_t)0x00002000U) /*!< Alert clear flag */ +#define I2C_ICR_ADDRCF_Pos (3U) +#define I2C_ICR_ADDRCF_Msk (0x1U << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */ +#define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */ +#define I2C_ICR_NACKCF_Pos (4U) +#define I2C_ICR_NACKCF_Msk (0x1U << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */ +#define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */ +#define I2C_ICR_STOPCF_Pos (5U) +#define I2C_ICR_STOPCF_Msk (0x1U << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */ +#define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */ +#define I2C_ICR_BERRCF_Pos (8U) +#define I2C_ICR_BERRCF_Msk (0x1U << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */ +#define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */ +#define I2C_ICR_ARLOCF_Pos (9U) +#define I2C_ICR_ARLOCF_Msk (0x1U << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */ +#define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */ +#define I2C_ICR_OVRCF_Pos (10U) +#define I2C_ICR_OVRCF_Msk (0x1U << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */ +#define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */ +#define I2C_ICR_PECCF_Pos (11U) +#define I2C_ICR_PECCF_Msk (0x1U << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */ +#define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */ +#define I2C_ICR_TIMOUTCF_Pos (12U) +#define I2C_ICR_TIMOUTCF_Msk (0x1U << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */ +#define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */ +#define I2C_ICR_ALERTCF_Pos (13U) +#define I2C_ICR_ALERTCF_Msk (0x1U << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */ +#define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */ /****************** Bit definition for I2C_PECR register *******************/ -#define I2C_PECR_PEC ((uint32_t)0x000000FFU) /*!< PEC register */ +#define I2C_PECR_PEC_Pos (0U) +#define I2C_PECR_PEC_Msk (0xFFU << I2C_PECR_PEC_Pos) /*!< 0x000000FF */ +#define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */ /****************** Bit definition for I2C_RXDR register *********************/ -#define I2C_RXDR_RXDATA ((uint32_t)0x000000FFU) /*!< 8-bit receive data */ +#define I2C_RXDR_RXDATA_Pos (0U) +#define I2C_RXDR_RXDATA_Msk (0xFFU << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */ +#define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */ /****************** Bit definition for I2C_TXDR register *******************/ -#define I2C_TXDR_TXDATA ((uint32_t)0x000000FFU) /*!< 8-bit transmit data */ +#define I2C_TXDR_TXDATA_Pos (0U) +#define I2C_TXDR_TXDATA_Msk (0xFFU << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */ +#define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */ /*****************************************************************************/ /* */ @@ -2036,24 +3161,38 @@ typedef struct /* */ /*****************************************************************************/ /******************* Bit definition for IWDG_KR register *******************/ -#define IWDG_KR_KEY ((uint32_t)0xFFFF) /*!< Key value (write only, read 0000h) */ +#define IWDG_KR_KEY_Pos (0U) +#define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */ +#define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!< Key value (write only, read 0000h) */ /******************* Bit definition for IWDG_PR register *******************/ -#define IWDG_PR_PR ((uint32_t)0x07) /*!< PR[2:0] (Prescaler divider) */ -#define IWDG_PR_PR_0 ((uint32_t)0x01) /*!< Bit 0 */ -#define IWDG_PR_PR_1 ((uint32_t)0x02) /*!< Bit 1 */ -#define IWDG_PR_PR_2 ((uint32_t)0x04) /*!< Bit 2 */ +#define IWDG_PR_PR_Pos (0U) +#define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /*!< 0x00000007 */ +#define IWDG_PR_PR IWDG_PR_PR_Msk /*!< PR[2:0] (Prescaler divider) */ +#define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x01 */ +#define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x02 */ +#define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x04 */ /******************* Bit definition for IWDG_RLR register ******************/ -#define IWDG_RLR_RL ((uint32_t)0x0FFF) /*!< Watchdog counter reload value */ +#define IWDG_RLR_RL_Pos (0U) +#define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */ +#define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!< Watchdog counter reload value */ /******************* Bit definition for IWDG_SR register *******************/ -#define IWDG_SR_PVU ((uint32_t)0x01) /*!< Watchdog prescaler value update */ -#define IWDG_SR_RVU ((uint32_t)0x02) /*!< Watchdog counter reload value update */ -#define IWDG_SR_WVU ((uint32_t)0x04) /*!< Watchdog counter window value update */ +#define IWDG_SR_PVU_Pos (0U) +#define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */ +#define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */ +#define IWDG_SR_RVU_Pos (1U) +#define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */ +#define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */ +#define IWDG_SR_WVU_Pos (2U) +#define IWDG_SR_WVU_Msk (0x1U << IWDG_SR_WVU_Pos) /*!< 0x00000004 */ +#define IWDG_SR_WVU IWDG_SR_WVU_Msk /*!< Watchdog counter window value update */ /******************* Bit definition for IWDG_KR register *******************/ -#define IWDG_WINR_WIN ((uint32_t)0x0FFF) /*!< Watchdog counter window value */ +#define IWDG_WINR_WIN_Pos (0U) +#define IWDG_WINR_WIN_Msk (0xFFFU << IWDG_WINR_WIN_Pos) /*!< 0x00000FFF */ +#define IWDG_WINR_WIN IWDG_WINR_WIN_Msk /*!< Watchdog counter window value */ /*****************************************************************************/ /* */ @@ -2065,37 +3204,63 @@ typedef struct /******************** Bit definition for PWR_CR register *******************/ -#define PWR_CR_LPDS ((uint32_t)0x00000001U) /*!< Low-power Deepsleep */ -#define PWR_CR_PDDS ((uint32_t)0x00000002U) /*!< Power Down Deepsleep */ -#define PWR_CR_CWUF ((uint32_t)0x00000004U) /*!< Clear Wakeup Flag */ -#define PWR_CR_CSBF ((uint32_t)0x00000008U) /*!< Clear Standby Flag */ -#define PWR_CR_PVDE ((uint32_t)0x00000010U) /*!< Power Voltage Detector Enable */ +#define PWR_CR_LPDS_Pos (0U) +#define PWR_CR_LPDS_Msk (0x1U << PWR_CR_LPDS_Pos) /*!< 0x00000001 */ +#define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< Low-power Deepsleep */ +#define PWR_CR_PDDS_Pos (1U) +#define PWR_CR_PDDS_Msk (0x1U << PWR_CR_PDDS_Pos) /*!< 0x00000002 */ +#define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */ +#define PWR_CR_CWUF_Pos (2U) +#define PWR_CR_CWUF_Msk (0x1U << PWR_CR_CWUF_Pos) /*!< 0x00000004 */ +#define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */ +#define PWR_CR_CSBF_Pos (3U) +#define PWR_CR_CSBF_Msk (0x1U << PWR_CR_CSBF_Pos) /*!< 0x00000008 */ +#define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */ +#define PWR_CR_PVDE_Pos (4U) +#define PWR_CR_PVDE_Msk (0x1U << PWR_CR_PVDE_Pos) /*!< 0x00000010 */ +#define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */ -#define PWR_CR_PLS ((uint32_t)0x000000E0U) /*!< PLS[2:0] bits (PVD Level Selection) */ -#define PWR_CR_PLS_0 ((uint32_t)0x00000020U) /*!< Bit 0 */ -#define PWR_CR_PLS_1 ((uint32_t)0x00000040U) /*!< Bit 1 */ -#define PWR_CR_PLS_2 ((uint32_t)0x00000080U) /*!< Bit 2 */ +#define PWR_CR_PLS_Pos (5U) +#define PWR_CR_PLS_Msk (0x7U << PWR_CR_PLS_Pos) /*!< 0x000000E0 */ +#define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */ +#define PWR_CR_PLS_0 (0x1U << PWR_CR_PLS_Pos) /*!< 0x00000020 */ +#define PWR_CR_PLS_1 (0x2U << PWR_CR_PLS_Pos) /*!< 0x00000040 */ +#define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /*!< 0x00000080 */ /*!< PVD level configuration */ -#define PWR_CR_PLS_LEV0 ((uint32_t)0x00000000U) /*!< PVD level 0 */ -#define PWR_CR_PLS_LEV1 ((uint32_t)0x00000020U) /*!< PVD level 1 */ -#define PWR_CR_PLS_LEV2 ((uint32_t)0x00000040U) /*!< PVD level 2 */ -#define PWR_CR_PLS_LEV3 ((uint32_t)0x00000060U) /*!< PVD level 3 */ -#define PWR_CR_PLS_LEV4 ((uint32_t)0x00000080U) /*!< PVD level 4 */ -#define PWR_CR_PLS_LEV5 ((uint32_t)0x000000A0U) /*!< PVD level 5 */ -#define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0U) /*!< PVD level 6 */ -#define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0U) /*!< PVD level 7 */ +#define PWR_CR_PLS_LEV0 (0x00000000U) /*!< PVD level 0 */ +#define PWR_CR_PLS_LEV1 (0x00000020U) /*!< PVD level 1 */ +#define PWR_CR_PLS_LEV2 (0x00000040U) /*!< PVD level 2 */ +#define PWR_CR_PLS_LEV3 (0x00000060U) /*!< PVD level 3 */ +#define PWR_CR_PLS_LEV4 (0x00000080U) /*!< PVD level 4 */ +#define PWR_CR_PLS_LEV5 (0x000000A0U) /*!< PVD level 5 */ +#define PWR_CR_PLS_LEV6 (0x000000C0U) /*!< PVD level 6 */ +#define PWR_CR_PLS_LEV7 (0x000000E0U) /*!< PVD level 7 */ -#define PWR_CR_DBP ((uint32_t)0x00000100U) /*!< Disable Backup Domain write protection */ +#define PWR_CR_DBP_Pos (8U) +#define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */ +#define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */ /******************* Bit definition for PWR_CSR register *******************/ -#define PWR_CSR_WUF ((uint32_t)0x00000001U) /*!< Wakeup Flag */ -#define PWR_CSR_SBF ((uint32_t)0x00000002U) /*!< Standby Flag */ -#define PWR_CSR_PVDO ((uint32_t)0x00000004U) /*!< PVD Output */ -#define PWR_CSR_VREFINTRDYF ((uint32_t)0x00000008U) /*!< Internal voltage reference (VREFINT) ready flag */ +#define PWR_CSR_WUF_Pos (0U) +#define PWR_CSR_WUF_Msk (0x1U << PWR_CSR_WUF_Pos) /*!< 0x00000001 */ +#define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */ +#define PWR_CSR_SBF_Pos (1U) +#define PWR_CSR_SBF_Msk (0x1U << PWR_CSR_SBF_Pos) /*!< 0x00000002 */ +#define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */ +#define PWR_CSR_PVDO_Pos (2U) +#define PWR_CSR_PVDO_Msk (0x1U << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */ +#define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */ +#define PWR_CSR_VREFINTRDYF_Pos (3U) +#define PWR_CSR_VREFINTRDYF_Msk (0x1U << PWR_CSR_VREFINTRDYF_Pos) /*!< 0x00000008 */ +#define PWR_CSR_VREFINTRDYF PWR_CSR_VREFINTRDYF_Msk /*!< Internal voltage reference (VREFINT) ready flag */ -#define PWR_CSR_EWUP1 ((uint32_t)0x00000100U) /*!< Enable WKUP pin 1 */ -#define PWR_CSR_EWUP2 ((uint32_t)0x00000200U) /*!< Enable WKUP pin 2 */ +#define PWR_CSR_EWUP1_Pos (8U) +#define PWR_CSR_EWUP1_Msk (0x1U << PWR_CSR_EWUP1_Pos) /*!< 0x00000100 */ +#define PWR_CSR_EWUP1 PWR_CSR_EWUP1_Msk /*!< Enable WKUP pin 1 */ +#define PWR_CSR_EWUP2_Pos (9U) +#define PWR_CSR_EWUP2_Msk (0x1U << PWR_CSR_EWUP2_Pos) /*!< 0x00000200 */ +#define PWR_CSR_EWUP2 PWR_CSR_EWUP2_Msk /*!< Enable WKUP pin 2 */ /*****************************************************************************/ /* */ @@ -2103,136 +3268,182 @@ typedef struct /* */ /*****************************************************************************/ /* -* @brief Specific device feature definitions (not present on all devices in the STM32F0 family) +* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie) */ /******************** Bit definition for RCC_CR register *******************/ -#define RCC_CR_HSION ((uint32_t)0x00000001U) /*!< Internal High Speed clock enable */ -#define RCC_CR_HSIRDY ((uint32_t)0x00000002U) /*!< Internal High Speed clock ready flag */ +#define RCC_CR_HSION_Pos (0U) +#define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000001 */ +#define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */ +#define RCC_CR_HSIRDY_Pos (1U) +#define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */ +#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */ -#define RCC_CR_HSITRIM ((uint32_t)0x000000F8U) /*!< Internal High Speed clock trimming */ -#define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008U) /*! exti[31] Interrupt */ -#define SYSCFG_ITLINE1_SR_VDDIO2 ((uint32_t)0x00000002U) /*!< VDDIO2 -> exti[16] Interrupt */ -#define SYSCFG_ITLINE2_SR_RTC_ALRA ((uint32_t)0x00000001U) /*!< RTC Alarm -> exti[17] interrupt .... */ -#define SYSCFG_ITLINE2_SR_RTC_TSTAMP ((uint32_t)0x00000002U) /*!< RTC Time Stamp -> exti[19] interrupt */ -#define SYSCFG_ITLINE2_SR_RTC_WAKEUP ((uint32_t)0x00000004U) /*!< RTC WAKEUP -> exti[20] Interrupt */ -#define SYSCFG_ITLINE3_SR_FLASH_ITF ((uint32_t)0x00000001U) /*!< Flash ITF Interrupt */ -#define SYSCFG_ITLINE4_SR_CRS ((uint32_t)0x00000001U) /*!< CRS interrupt */ -#define SYSCFG_ITLINE4_SR_CLK_CTRL ((uint32_t)0x00000002U) /*!< CLK CTRL interrupt */ -#define SYSCFG_ITLINE5_SR_EXTI0 ((uint32_t)0x00000001U) /*!< External Interrupt 0 */ -#define SYSCFG_ITLINE5_SR_EXTI1 ((uint32_t)0x00000002U) /*!< External Interrupt 1 */ -#define SYSCFG_ITLINE6_SR_EXTI2 ((uint32_t)0x00000001U) /*!< External Interrupt 2 */ -#define SYSCFG_ITLINE6_SR_EXTI3 ((uint32_t)0x00000002U) /*!< External Interrupt 3 */ -#define SYSCFG_ITLINE7_SR_EXTI4 ((uint32_t)0x00000001U) /*!< External Interrupt 15 to 4 */ -#define SYSCFG_ITLINE7_SR_EXTI5 ((uint32_t)0x00000002U) /*!< External Interrupt 15 to 4 */ -#define SYSCFG_ITLINE7_SR_EXTI6 ((uint32_t)0x00000004U) /*!< External Interrupt 15 to 4 */ -#define SYSCFG_ITLINE7_SR_EXTI7 ((uint32_t)0x00000008U) /*!< External Interrupt 15 to 4 */ -#define SYSCFG_ITLINE7_SR_EXTI8 ((uint32_t)0x00000010U) /*!< External Interrupt 15 to 4 */ -#define SYSCFG_ITLINE7_SR_EXTI9 ((uint32_t)0x00000020U) /*!< External Interrupt 15 to 4 */ -#define SYSCFG_ITLINE7_SR_EXTI10 ((uint32_t)0x00000040U) /*!< External Interrupt 15 to 4 */ -#define SYSCFG_ITLINE7_SR_EXTI11 ((uint32_t)0x00000080U) /*!< External Interrupt 15 to 4 */ -#define SYSCFG_ITLINE7_SR_EXTI12 ((uint32_t)0x00000100U) /*!< External Interrupt 15 to 4 */ -#define SYSCFG_ITLINE7_SR_EXTI13 ((uint32_t)0x00000200U) /*!< External Interrupt 15 to 4 */ -#define SYSCFG_ITLINE7_SR_EXTI14 ((uint32_t)0x00000400U) /*!< External Interrupt 15 to 4 */ -#define SYSCFG_ITLINE7_SR_EXTI15 ((uint32_t)0x00000800U) /*!< External Interrupt 15 to 4 */ -#define SYSCFG_ITLINE8_SR_TSC_EOA ((uint32_t)0x00000001U) /*!< Touch control EOA Interrupt */ -#define SYSCFG_ITLINE8_SR_TSC_MCE ((uint32_t)0x00000002U) /*!< Touch control MCE Interrupt */ -#define SYSCFG_ITLINE9_SR_DMA1_CH1 ((uint32_t)0x00000001U) /*!< DMA1 Channel 1 Interrupt */ -#define SYSCFG_ITLINE10_SR_DMA1_CH2 ((uint32_t)0x00000001U) /*!< DMA1 Channel 2 Interrupt */ -#define SYSCFG_ITLINE10_SR_DMA1_CH3 ((uint32_t)0x00000002U) /*!< DMA2 Channel 3 Interrupt */ -#define SYSCFG_ITLINE10_SR_DMA2_CH1 ((uint32_t)0x00000004U) /*!< DMA2 Channel 1 Interrupt */ -#define SYSCFG_ITLINE10_SR_DMA2_CH2 ((uint32_t)0x00000008U) /*!< DMA2 Channel 2 Interrupt */ -#define SYSCFG_ITLINE11_SR_DMA1_CH4 ((uint32_t)0x00000001U) /*!< DMA1 Channel 4 Interrupt */ -#define SYSCFG_ITLINE11_SR_DMA1_CH5 ((uint32_t)0x00000002U) /*!< DMA1 Channel 5 Interrupt */ -#define SYSCFG_ITLINE11_SR_DMA1_CH6 ((uint32_t)0x00000004U) /*!< DMA1 Channel 6 Interrupt */ -#define SYSCFG_ITLINE11_SR_DMA1_CH7 ((uint32_t)0x00000008U) /*!< DMA1 Channel 7 Interrupt */ -#define SYSCFG_ITLINE11_SR_DMA2_CH3 ((uint32_t)0x00000010U) /*!< DMA2 Channel 3 Interrupt */ -#define SYSCFG_ITLINE11_SR_DMA2_CH4 ((uint32_t)0x00000020U) /*!< DMA2 Channel 4 Interrupt */ -#define SYSCFG_ITLINE11_SR_DMA2_CH5 ((uint32_t)0x00000040U) /*!< DMA2 Channel 5 Interrupt */ -#define SYSCFG_ITLINE12_SR_ADC ((uint32_t)0x00000001U) /*!< ADC Interrupt */ -#define SYSCFG_ITLINE12_SR_COMP1 ((uint32_t)0x00000002U) /*!< COMP1 Interrupt -> exti[21] */ -#define SYSCFG_ITLINE12_SR_COMP2 ((uint32_t)0x00000004U) /*!< COMP2 Interrupt -> exti[22] */ -#define SYSCFG_ITLINE13_SR_TIM1_BRK ((uint32_t)0x00000001U) /*!< TIM1 BRK Interrupt */ -#define SYSCFG_ITLINE13_SR_TIM1_UPD ((uint32_t)0x00000002U) /*!< TIM1 UPD Interrupt */ -#define SYSCFG_ITLINE13_SR_TIM1_TRG ((uint32_t)0x00000004U) /*!< TIM1 TRG Interrupt */ -#define SYSCFG_ITLINE13_SR_TIM1_CCU ((uint32_t)0x00000008U) /*!< TIM1 CCU Interrupt */ -#define SYSCFG_ITLINE14_SR_TIM1_CC ((uint32_t)0x00000001U) /*!< TIM1 CC Interrupt */ -#define SYSCFG_ITLINE15_SR_TIM2_GLB ((uint32_t)0x00000001U) /*!< TIM2 GLB Interrupt */ -#define SYSCFG_ITLINE16_SR_TIM3_GLB ((uint32_t)0x00000001U) /*!< TIM3 GLB Interrupt */ -#define SYSCFG_ITLINE17_SR_DAC ((uint32_t)0x00000001U) /*!< DAC Interrupt */ -#define SYSCFG_ITLINE17_SR_TIM6_GLB ((uint32_t)0x00000002U) /*!< TIM6 GLB Interrupt */ -#define SYSCFG_ITLINE18_SR_TIM7_GLB ((uint32_t)0x00000001U) /*!< TIM7 GLB Interrupt */ -#define SYSCFG_ITLINE19_SR_TIM14_GLB ((uint32_t)0x00000001U) /*!< TIM14 GLB Interrupt */ -#define SYSCFG_ITLINE20_SR_TIM15_GLB ((uint32_t)0x00000001U) /*!< TIM15 GLB Interrupt */ -#define SYSCFG_ITLINE21_SR_TIM16_GLB ((uint32_t)0x00000001U) /*!< TIM16 GLB Interrupt */ -#define SYSCFG_ITLINE22_SR_TIM17_GLB ((uint32_t)0x00000001U) /*!< TIM17 GLB Interrupt */ -#define SYSCFG_ITLINE23_SR_I2C1_GLB ((uint32_t)0x00000001U) /*!< I2C1 GLB Interrupt -> exti[23] */ -#define SYSCFG_ITLINE24_SR_I2C2_GLB ((uint32_t)0x00000001U) /*!< I2C2 GLB Interrupt */ -#define SYSCFG_ITLINE25_SR_SPI1 ((uint32_t)0x00000001U) /*!< SPI1 Interrupt */ -#define SYSCFG_ITLINE26_SR_SPI2 ((uint32_t)0x00000001U) /*!< SPI2 Interrupt */ -#define SYSCFG_ITLINE27_SR_USART1_GLB ((uint32_t)0x00000001U) /*!< USART1 GLB Interrupt -> exti[25] */ -#define SYSCFG_ITLINE28_SR_USART2_GLB ((uint32_t)0x00000001U) /*!< USART2 GLB Interrupt -> exti[26] */ -#define SYSCFG_ITLINE29_SR_USART3_GLB ((uint32_t)0x00000001U) /*!< USART3 GLB Interrupt -> exti[28] */ -#define SYSCFG_ITLINE29_SR_USART4_GLB ((uint32_t)0x00000002U) /*!< USART4 GLB Interrupt */ -#define SYSCFG_ITLINE29_SR_USART5_GLB ((uint32_t)0x00000004U) /*!< USART5 GLB Interrupt */ -#define SYSCFG_ITLINE29_SR_USART6_GLB ((uint32_t)0x00000008U) /*!< USART6 GLB Interrupt */ -#define SYSCFG_ITLINE29_SR_USART7_GLB ((uint32_t)0x00000010U) /*!< USART7 GLB Interrupt */ -#define SYSCFG_ITLINE29_SR_USART8_GLB ((uint32_t)0x00000020U) /*!< USART8 GLB Interrupt */ -#define SYSCFG_ITLINE30_SR_CAN ((uint32_t)0x00000001U) /*!< CAN Interrupt */ -#define SYSCFG_ITLINE30_SR_CEC ((uint32_t)0x00000002U) /*!< CEC Interrupt */ +#define SYSCFG_ITLINE0_SR_EWDG_Pos (0U) +#define SYSCFG_ITLINE0_SR_EWDG_Msk (0x1U << SYSCFG_ITLINE0_SR_EWDG_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE0_SR_EWDG SYSCFG_ITLINE0_SR_EWDG_Msk /*!< EWDG interrupt */ +#define SYSCFG_ITLINE1_SR_PVDOUT_Pos (0U) +#define SYSCFG_ITLINE1_SR_PVDOUT_Msk (0x1U << SYSCFG_ITLINE1_SR_PVDOUT_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE1_SR_PVDOUT SYSCFG_ITLINE1_SR_PVDOUT_Msk /*!< Power voltage detection -> exti[31] Interrupt */ +#define SYSCFG_ITLINE1_SR_VDDIO2_Pos (1U) +#define SYSCFG_ITLINE1_SR_VDDIO2_Msk (0x1U << SYSCFG_ITLINE1_SR_VDDIO2_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE1_SR_VDDIO2 SYSCFG_ITLINE1_SR_VDDIO2_Msk /*!< VDDIO2 -> exti[16] Interrupt */ +#define SYSCFG_ITLINE2_SR_RTC_ALRA_Pos (0U) +#define SYSCFG_ITLINE2_SR_RTC_ALRA_Msk (0x1U << SYSCFG_ITLINE2_SR_RTC_ALRA_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE2_SR_RTC_ALRA SYSCFG_ITLINE2_SR_RTC_ALRA_Msk /*!< RTC Alarm -> exti[17] interrupt .... */ +#define SYSCFG_ITLINE2_SR_RTC_TSTAMP_Pos (1U) +#define SYSCFG_ITLINE2_SR_RTC_TSTAMP_Msk (0x1U << SYSCFG_ITLINE2_SR_RTC_TSTAMP_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE2_SR_RTC_TSTAMP SYSCFG_ITLINE2_SR_RTC_TSTAMP_Msk /*!< RTC Time Stamp -> exti[19] interrupt */ +#define SYSCFG_ITLINE2_SR_RTC_WAKEUP_Pos (2U) +#define SYSCFG_ITLINE2_SR_RTC_WAKEUP_Msk (0x1U << SYSCFG_ITLINE2_SR_RTC_WAKEUP_Pos) /*!< 0x00000004 */ +#define SYSCFG_ITLINE2_SR_RTC_WAKEUP SYSCFG_ITLINE2_SR_RTC_WAKEUP_Msk /*!< RTC WAKEUP -> exti[20] Interrupt */ +#define SYSCFG_ITLINE3_SR_FLASH_ITF_Pos (0U) +#define SYSCFG_ITLINE3_SR_FLASH_ITF_Msk (0x1U << SYSCFG_ITLINE3_SR_FLASH_ITF_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE3_SR_FLASH_ITF SYSCFG_ITLINE3_SR_FLASH_ITF_Msk /*!< Flash ITF Interrupt */ +#define SYSCFG_ITLINE4_SR_CRS_Pos (0U) +#define SYSCFG_ITLINE4_SR_CRS_Msk (0x1U << SYSCFG_ITLINE4_SR_CRS_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE4_SR_CRS SYSCFG_ITLINE4_SR_CRS_Msk /*!< CRS interrupt */ +#define SYSCFG_ITLINE4_SR_CLK_CTRL_Pos (1U) +#define SYSCFG_ITLINE4_SR_CLK_CTRL_Msk (0x1U << SYSCFG_ITLINE4_SR_CLK_CTRL_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE4_SR_CLK_CTRL SYSCFG_ITLINE4_SR_CLK_CTRL_Msk /*!< CLK CTRL interrupt */ +#define SYSCFG_ITLINE5_SR_EXTI0_Pos (0U) +#define SYSCFG_ITLINE5_SR_EXTI0_Msk (0x1U << SYSCFG_ITLINE5_SR_EXTI0_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE5_SR_EXTI0 SYSCFG_ITLINE5_SR_EXTI0_Msk /*!< External Interrupt 0 */ +#define SYSCFG_ITLINE5_SR_EXTI1_Pos (1U) +#define SYSCFG_ITLINE5_SR_EXTI1_Msk (0x1U << SYSCFG_ITLINE5_SR_EXTI1_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE5_SR_EXTI1 SYSCFG_ITLINE5_SR_EXTI1_Msk /*!< External Interrupt 1 */ +#define SYSCFG_ITLINE6_SR_EXTI2_Pos (0U) +#define SYSCFG_ITLINE6_SR_EXTI2_Msk (0x1U << SYSCFG_ITLINE6_SR_EXTI2_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE6_SR_EXTI2 SYSCFG_ITLINE6_SR_EXTI2_Msk /*!< External Interrupt 2 */ +#define SYSCFG_ITLINE6_SR_EXTI3_Pos (1U) +#define SYSCFG_ITLINE6_SR_EXTI3_Msk (0x1U << SYSCFG_ITLINE6_SR_EXTI3_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE6_SR_EXTI3 SYSCFG_ITLINE6_SR_EXTI3_Msk /*!< External Interrupt 3 */ +#define SYSCFG_ITLINE7_SR_EXTI4_Pos (0U) +#define SYSCFG_ITLINE7_SR_EXTI4_Msk (0x1U << SYSCFG_ITLINE7_SR_EXTI4_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE7_SR_EXTI4 SYSCFG_ITLINE7_SR_EXTI4_Msk /*!< External Interrupt 15 to 4 */ +#define SYSCFG_ITLINE7_SR_EXTI5_Pos (1U) +#define SYSCFG_ITLINE7_SR_EXTI5_Msk (0x1U << SYSCFG_ITLINE7_SR_EXTI5_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE7_SR_EXTI5 SYSCFG_ITLINE7_SR_EXTI5_Msk /*!< External Interrupt 15 to 4 */ +#define SYSCFG_ITLINE7_SR_EXTI6_Pos (2U) +#define SYSCFG_ITLINE7_SR_EXTI6_Msk (0x1U << SYSCFG_ITLINE7_SR_EXTI6_Pos) /*!< 0x00000004 */ +#define SYSCFG_ITLINE7_SR_EXTI6 SYSCFG_ITLINE7_SR_EXTI6_Msk /*!< External Interrupt 15 to 4 */ +#define SYSCFG_ITLINE7_SR_EXTI7_Pos (3U) +#define SYSCFG_ITLINE7_SR_EXTI7_Msk (0x1U << SYSCFG_ITLINE7_SR_EXTI7_Pos) /*!< 0x00000008 */ +#define SYSCFG_ITLINE7_SR_EXTI7 SYSCFG_ITLINE7_SR_EXTI7_Msk /*!< External Interrupt 15 to 4 */ +#define SYSCFG_ITLINE7_SR_EXTI8_Pos (4U) +#define SYSCFG_ITLINE7_SR_EXTI8_Msk (0x1U << SYSCFG_ITLINE7_SR_EXTI8_Pos) /*!< 0x00000010 */ +#define SYSCFG_ITLINE7_SR_EXTI8 SYSCFG_ITLINE7_SR_EXTI8_Msk /*!< External Interrupt 15 to 4 */ +#define SYSCFG_ITLINE7_SR_EXTI9_Pos (5U) +#define SYSCFG_ITLINE7_SR_EXTI9_Msk (0x1U << SYSCFG_ITLINE7_SR_EXTI9_Pos) /*!< 0x00000020 */ +#define SYSCFG_ITLINE7_SR_EXTI9 SYSCFG_ITLINE7_SR_EXTI9_Msk /*!< External Interrupt 15 to 4 */ +#define SYSCFG_ITLINE7_SR_EXTI10_Pos (6U) +#define SYSCFG_ITLINE7_SR_EXTI10_Msk (0x1U << SYSCFG_ITLINE7_SR_EXTI10_Pos) /*!< 0x00000040 */ +#define SYSCFG_ITLINE7_SR_EXTI10 SYSCFG_ITLINE7_SR_EXTI10_Msk /*!< External Interrupt 15 to 4 */ +#define SYSCFG_ITLINE7_SR_EXTI11_Pos (7U) +#define SYSCFG_ITLINE7_SR_EXTI11_Msk (0x1U << SYSCFG_ITLINE7_SR_EXTI11_Pos) /*!< 0x00000080 */ +#define SYSCFG_ITLINE7_SR_EXTI11 SYSCFG_ITLINE7_SR_EXTI11_Msk /*!< External Interrupt 15 to 4 */ +#define SYSCFG_ITLINE7_SR_EXTI12_Pos (8U) +#define SYSCFG_ITLINE7_SR_EXTI12_Msk (0x1U << SYSCFG_ITLINE7_SR_EXTI12_Pos) /*!< 0x00000100 */ +#define SYSCFG_ITLINE7_SR_EXTI12 SYSCFG_ITLINE7_SR_EXTI12_Msk /*!< External Interrupt 15 to 4 */ +#define SYSCFG_ITLINE7_SR_EXTI13_Pos (9U) +#define SYSCFG_ITLINE7_SR_EXTI13_Msk (0x1U << SYSCFG_ITLINE7_SR_EXTI13_Pos) /*!< 0x00000200 */ +#define SYSCFG_ITLINE7_SR_EXTI13 SYSCFG_ITLINE7_SR_EXTI13_Msk /*!< External Interrupt 15 to 4 */ +#define SYSCFG_ITLINE7_SR_EXTI14_Pos (10U) +#define SYSCFG_ITLINE7_SR_EXTI14_Msk (0x1U << SYSCFG_ITLINE7_SR_EXTI14_Pos) /*!< 0x00000400 */ +#define SYSCFG_ITLINE7_SR_EXTI14 SYSCFG_ITLINE7_SR_EXTI14_Msk /*!< External Interrupt 15 to 4 */ +#define SYSCFG_ITLINE7_SR_EXTI15_Pos (11U) +#define SYSCFG_ITLINE7_SR_EXTI15_Msk (0x1U << SYSCFG_ITLINE7_SR_EXTI15_Pos) /*!< 0x00000800 */ +#define SYSCFG_ITLINE7_SR_EXTI15 SYSCFG_ITLINE7_SR_EXTI15_Msk /*!< External Interrupt 15 to 4 */ +#define SYSCFG_ITLINE8_SR_TSC_EOA_Pos (0U) +#define SYSCFG_ITLINE8_SR_TSC_EOA_Msk (0x1U << SYSCFG_ITLINE8_SR_TSC_EOA_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE8_SR_TSC_EOA SYSCFG_ITLINE8_SR_TSC_EOA_Msk /*!< Touch control EOA Interrupt */ +#define SYSCFG_ITLINE8_SR_TSC_MCE_Pos (1U) +#define SYSCFG_ITLINE8_SR_TSC_MCE_Msk (0x1U << SYSCFG_ITLINE8_SR_TSC_MCE_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE8_SR_TSC_MCE SYSCFG_ITLINE8_SR_TSC_MCE_Msk /*!< Touch control MCE Interrupt */ +#define SYSCFG_ITLINE9_SR_DMA1_CH1_Pos (0U) +#define SYSCFG_ITLINE9_SR_DMA1_CH1_Msk (0x1U << SYSCFG_ITLINE9_SR_DMA1_CH1_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE9_SR_DMA1_CH1 SYSCFG_ITLINE9_SR_DMA1_CH1_Msk /*!< DMA1 Channel 1 Interrupt */ +#define SYSCFG_ITLINE10_SR_DMA1_CH2_Pos (0U) +#define SYSCFG_ITLINE10_SR_DMA1_CH2_Msk (0x1U << SYSCFG_ITLINE10_SR_DMA1_CH2_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE10_SR_DMA1_CH2 SYSCFG_ITLINE10_SR_DMA1_CH2_Msk /*!< DMA1 Channel 2 Interrupt */ +#define SYSCFG_ITLINE10_SR_DMA1_CH3_Pos (1U) +#define SYSCFG_ITLINE10_SR_DMA1_CH3_Msk (0x1U << SYSCFG_ITLINE10_SR_DMA1_CH3_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE10_SR_DMA1_CH3 SYSCFG_ITLINE10_SR_DMA1_CH3_Msk /*!< DMA2 Channel 3 Interrupt */ +#define SYSCFG_ITLINE10_SR_DMA2_CH1_Pos (2U) +#define SYSCFG_ITLINE10_SR_DMA2_CH1_Msk (0x1U << SYSCFG_ITLINE10_SR_DMA2_CH1_Pos) /*!< 0x00000004 */ +#define SYSCFG_ITLINE10_SR_DMA2_CH1 SYSCFG_ITLINE10_SR_DMA2_CH1_Msk /*!< DMA2 Channel 1 Interrupt */ +#define SYSCFG_ITLINE10_SR_DMA2_CH2_Pos (3U) +#define SYSCFG_ITLINE10_SR_DMA2_CH2_Msk (0x1U << SYSCFG_ITLINE10_SR_DMA2_CH2_Pos) /*!< 0x00000008 */ +#define SYSCFG_ITLINE10_SR_DMA2_CH2 SYSCFG_ITLINE10_SR_DMA2_CH2_Msk /*!< DMA2 Channel 2 Interrupt */ +#define SYSCFG_ITLINE11_SR_DMA1_CH4_Pos (0U) +#define SYSCFG_ITLINE11_SR_DMA1_CH4_Msk (0x1U << SYSCFG_ITLINE11_SR_DMA1_CH4_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE11_SR_DMA1_CH4 SYSCFG_ITLINE11_SR_DMA1_CH4_Msk /*!< DMA1 Channel 4 Interrupt */ +#define SYSCFG_ITLINE11_SR_DMA1_CH5_Pos (1U) +#define SYSCFG_ITLINE11_SR_DMA1_CH5_Msk (0x1U << SYSCFG_ITLINE11_SR_DMA1_CH5_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE11_SR_DMA1_CH5 SYSCFG_ITLINE11_SR_DMA1_CH5_Msk /*!< DMA1 Channel 5 Interrupt */ +#define SYSCFG_ITLINE11_SR_DMA1_CH6_Pos (2U) +#define SYSCFG_ITLINE11_SR_DMA1_CH6_Msk (0x1U << SYSCFG_ITLINE11_SR_DMA1_CH6_Pos) /*!< 0x00000004 */ +#define SYSCFG_ITLINE11_SR_DMA1_CH6 SYSCFG_ITLINE11_SR_DMA1_CH6_Msk /*!< DMA1 Channel 6 Interrupt */ +#define SYSCFG_ITLINE11_SR_DMA1_CH7_Pos (3U) +#define SYSCFG_ITLINE11_SR_DMA1_CH7_Msk (0x1U << SYSCFG_ITLINE11_SR_DMA1_CH7_Pos) /*!< 0x00000008 */ +#define SYSCFG_ITLINE11_SR_DMA1_CH7 SYSCFG_ITLINE11_SR_DMA1_CH7_Msk /*!< DMA1 Channel 7 Interrupt */ +#define SYSCFG_ITLINE11_SR_DMA2_CH3_Pos (4U) +#define SYSCFG_ITLINE11_SR_DMA2_CH3_Msk (0x1U << SYSCFG_ITLINE11_SR_DMA2_CH3_Pos) /*!< 0x00000010 */ +#define SYSCFG_ITLINE11_SR_DMA2_CH3 SYSCFG_ITLINE11_SR_DMA2_CH3_Msk /*!< DMA2 Channel 3 Interrupt */ +#define SYSCFG_ITLINE11_SR_DMA2_CH4_Pos (5U) +#define SYSCFG_ITLINE11_SR_DMA2_CH4_Msk (0x1U << SYSCFG_ITLINE11_SR_DMA2_CH4_Pos) /*!< 0x00000020 */ +#define SYSCFG_ITLINE11_SR_DMA2_CH4 SYSCFG_ITLINE11_SR_DMA2_CH4_Msk /*!< DMA2 Channel 4 Interrupt */ +#define SYSCFG_ITLINE11_SR_DMA2_CH5_Pos (6U) +#define SYSCFG_ITLINE11_SR_DMA2_CH5_Msk (0x1U << SYSCFG_ITLINE11_SR_DMA2_CH5_Pos) /*!< 0x00000040 */ +#define SYSCFG_ITLINE11_SR_DMA2_CH5 SYSCFG_ITLINE11_SR_DMA2_CH5_Msk /*!< DMA2 Channel 5 Interrupt */ +#define SYSCFG_ITLINE12_SR_ADC_Pos (0U) +#define SYSCFG_ITLINE12_SR_ADC_Msk (0x1U << SYSCFG_ITLINE12_SR_ADC_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE12_SR_ADC SYSCFG_ITLINE12_SR_ADC_Msk /*!< ADC Interrupt */ +#define SYSCFG_ITLINE12_SR_COMP1_Pos (1U) +#define SYSCFG_ITLINE12_SR_COMP1_Msk (0x1U << SYSCFG_ITLINE12_SR_COMP1_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE12_SR_COMP1 SYSCFG_ITLINE12_SR_COMP1_Msk /*!< COMP1 Interrupt -> exti[21] */ +#define SYSCFG_ITLINE12_SR_COMP2_Pos (2U) +#define SYSCFG_ITLINE12_SR_COMP2_Msk (0x1U << SYSCFG_ITLINE12_SR_COMP2_Pos) /*!< 0x00000004 */ +#define SYSCFG_ITLINE12_SR_COMP2 SYSCFG_ITLINE12_SR_COMP2_Msk /*!< COMP2 Interrupt -> exti[22] */ +#define SYSCFG_ITLINE13_SR_TIM1_BRK_Pos (0U) +#define SYSCFG_ITLINE13_SR_TIM1_BRK_Msk (0x1U << SYSCFG_ITLINE13_SR_TIM1_BRK_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE13_SR_TIM1_BRK SYSCFG_ITLINE13_SR_TIM1_BRK_Msk /*!< TIM1 BRK Interrupt */ +#define SYSCFG_ITLINE13_SR_TIM1_UPD_Pos (1U) +#define SYSCFG_ITLINE13_SR_TIM1_UPD_Msk (0x1U << SYSCFG_ITLINE13_SR_TIM1_UPD_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE13_SR_TIM1_UPD SYSCFG_ITLINE13_SR_TIM1_UPD_Msk /*!< TIM1 UPD Interrupt */ +#define SYSCFG_ITLINE13_SR_TIM1_TRG_Pos (2U) +#define SYSCFG_ITLINE13_SR_TIM1_TRG_Msk (0x1U << SYSCFG_ITLINE13_SR_TIM1_TRG_Pos) /*!< 0x00000004 */ +#define SYSCFG_ITLINE13_SR_TIM1_TRG SYSCFG_ITLINE13_SR_TIM1_TRG_Msk /*!< TIM1 TRG Interrupt */ +#define SYSCFG_ITLINE13_SR_TIM1_CCU_Pos (3U) +#define SYSCFG_ITLINE13_SR_TIM1_CCU_Msk (0x1U << SYSCFG_ITLINE13_SR_TIM1_CCU_Pos) /*!< 0x00000008 */ +#define SYSCFG_ITLINE13_SR_TIM1_CCU SYSCFG_ITLINE13_SR_TIM1_CCU_Msk /*!< TIM1 CCU Interrupt */ +#define SYSCFG_ITLINE14_SR_TIM1_CC_Pos (0U) +#define SYSCFG_ITLINE14_SR_TIM1_CC_Msk (0x1U << SYSCFG_ITLINE14_SR_TIM1_CC_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE14_SR_TIM1_CC SYSCFG_ITLINE14_SR_TIM1_CC_Msk /*!< TIM1 CC Interrupt */ +#define SYSCFG_ITLINE15_SR_TIM2_GLB_Pos (0U) +#define SYSCFG_ITLINE15_SR_TIM2_GLB_Msk (0x1U << SYSCFG_ITLINE15_SR_TIM2_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE15_SR_TIM2_GLB SYSCFG_ITLINE15_SR_TIM2_GLB_Msk /*!< TIM2 GLB Interrupt */ +#define SYSCFG_ITLINE16_SR_TIM3_GLB_Pos (0U) +#define SYSCFG_ITLINE16_SR_TIM3_GLB_Msk (0x1U << SYSCFG_ITLINE16_SR_TIM3_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE16_SR_TIM3_GLB SYSCFG_ITLINE16_SR_TIM3_GLB_Msk /*!< TIM3 GLB Interrupt */ +#define SYSCFG_ITLINE17_SR_DAC_Pos (0U) +#define SYSCFG_ITLINE17_SR_DAC_Msk (0x1U << SYSCFG_ITLINE17_SR_DAC_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE17_SR_DAC SYSCFG_ITLINE17_SR_DAC_Msk /*!< DAC Interrupt */ +#define SYSCFG_ITLINE17_SR_TIM6_GLB_Pos (1U) +#define SYSCFG_ITLINE17_SR_TIM6_GLB_Msk (0x1U << SYSCFG_ITLINE17_SR_TIM6_GLB_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE17_SR_TIM6_GLB SYSCFG_ITLINE17_SR_TIM6_GLB_Msk /*!< TIM6 GLB Interrupt */ +#define SYSCFG_ITLINE18_SR_TIM7_GLB_Pos (0U) +#define SYSCFG_ITLINE18_SR_TIM7_GLB_Msk (0x1U << SYSCFG_ITLINE18_SR_TIM7_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE18_SR_TIM7_GLB SYSCFG_ITLINE18_SR_TIM7_GLB_Msk /*!< TIM7 GLB Interrupt */ +#define SYSCFG_ITLINE19_SR_TIM14_GLB_Pos (0U) +#define SYSCFG_ITLINE19_SR_TIM14_GLB_Msk (0x1U << SYSCFG_ITLINE19_SR_TIM14_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE19_SR_TIM14_GLB SYSCFG_ITLINE19_SR_TIM14_GLB_Msk /*!< TIM14 GLB Interrupt */ +#define SYSCFG_ITLINE20_SR_TIM15_GLB_Pos (0U) +#define SYSCFG_ITLINE20_SR_TIM15_GLB_Msk (0x1U << SYSCFG_ITLINE20_SR_TIM15_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE20_SR_TIM15_GLB SYSCFG_ITLINE20_SR_TIM15_GLB_Msk /*!< TIM15 GLB Interrupt */ +#define SYSCFG_ITLINE21_SR_TIM16_GLB_Pos (0U) +#define SYSCFG_ITLINE21_SR_TIM16_GLB_Msk (0x1U << SYSCFG_ITLINE21_SR_TIM16_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE21_SR_TIM16_GLB SYSCFG_ITLINE21_SR_TIM16_GLB_Msk /*!< TIM16 GLB Interrupt */ +#define SYSCFG_ITLINE22_SR_TIM17_GLB_Pos (0U) +#define SYSCFG_ITLINE22_SR_TIM17_GLB_Msk (0x1U << SYSCFG_ITLINE22_SR_TIM17_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE22_SR_TIM17_GLB SYSCFG_ITLINE22_SR_TIM17_GLB_Msk /*!< TIM17 GLB Interrupt */ +#define SYSCFG_ITLINE23_SR_I2C1_GLB_Pos (0U) +#define SYSCFG_ITLINE23_SR_I2C1_GLB_Msk (0x1U << SYSCFG_ITLINE23_SR_I2C1_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE23_SR_I2C1_GLB SYSCFG_ITLINE23_SR_I2C1_GLB_Msk /*!< I2C1 GLB Interrupt -> exti[23] */ +#define SYSCFG_ITLINE24_SR_I2C2_GLB_Pos (0U) +#define SYSCFG_ITLINE24_SR_I2C2_GLB_Msk (0x1U << SYSCFG_ITLINE24_SR_I2C2_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE24_SR_I2C2_GLB SYSCFG_ITLINE24_SR_I2C2_GLB_Msk /*!< I2C2 GLB Interrupt */ +#define SYSCFG_ITLINE25_SR_SPI1_Pos (0U) +#define SYSCFG_ITLINE25_SR_SPI1_Msk (0x1U << SYSCFG_ITLINE25_SR_SPI1_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE25_SR_SPI1 SYSCFG_ITLINE25_SR_SPI1_Msk /*!< SPI1 Interrupt */ +#define SYSCFG_ITLINE26_SR_SPI2_Pos (0U) +#define SYSCFG_ITLINE26_SR_SPI2_Msk (0x1U << SYSCFG_ITLINE26_SR_SPI2_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE26_SR_SPI2 SYSCFG_ITLINE26_SR_SPI2_Msk /*!< SPI2 Interrupt */ +#define SYSCFG_ITLINE27_SR_USART1_GLB_Pos (0U) +#define SYSCFG_ITLINE27_SR_USART1_GLB_Msk (0x1U << SYSCFG_ITLINE27_SR_USART1_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE27_SR_USART1_GLB SYSCFG_ITLINE27_SR_USART1_GLB_Msk /*!< USART1 GLB Interrupt -> exti[25] */ +#define SYSCFG_ITLINE28_SR_USART2_GLB_Pos (0U) +#define SYSCFG_ITLINE28_SR_USART2_GLB_Msk (0x1U << SYSCFG_ITLINE28_SR_USART2_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE28_SR_USART2_GLB SYSCFG_ITLINE28_SR_USART2_GLB_Msk /*!< USART2 GLB Interrupt -> exti[26] */ +#define SYSCFG_ITLINE29_SR_USART3_GLB_Pos (0U) +#define SYSCFG_ITLINE29_SR_USART3_GLB_Msk (0x1U << SYSCFG_ITLINE29_SR_USART3_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE29_SR_USART3_GLB SYSCFG_ITLINE29_SR_USART3_GLB_Msk /*!< USART3 GLB Interrupt -> exti[28] */ +#define SYSCFG_ITLINE29_SR_USART4_GLB_Pos (1U) +#define SYSCFG_ITLINE29_SR_USART4_GLB_Msk (0x1U << SYSCFG_ITLINE29_SR_USART4_GLB_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE29_SR_USART4_GLB SYSCFG_ITLINE29_SR_USART4_GLB_Msk /*!< USART4 GLB Interrupt */ +#define SYSCFG_ITLINE29_SR_USART5_GLB_Pos (2U) +#define SYSCFG_ITLINE29_SR_USART5_GLB_Msk (0x1U << SYSCFG_ITLINE29_SR_USART5_GLB_Pos) /*!< 0x00000004 */ +#define SYSCFG_ITLINE29_SR_USART5_GLB SYSCFG_ITLINE29_SR_USART5_GLB_Msk /*!< USART5 GLB Interrupt */ +#define SYSCFG_ITLINE29_SR_USART6_GLB_Pos (3U) +#define SYSCFG_ITLINE29_SR_USART6_GLB_Msk (0x1U << SYSCFG_ITLINE29_SR_USART6_GLB_Pos) /*!< 0x00000008 */ +#define SYSCFG_ITLINE29_SR_USART6_GLB SYSCFG_ITLINE29_SR_USART6_GLB_Msk /*!< USART6 GLB Interrupt */ +#define SYSCFG_ITLINE29_SR_USART7_GLB_Pos (4U) +#define SYSCFG_ITLINE29_SR_USART7_GLB_Msk (0x1U << SYSCFG_ITLINE29_SR_USART7_GLB_Pos) /*!< 0x00000010 */ +#define SYSCFG_ITLINE29_SR_USART7_GLB SYSCFG_ITLINE29_SR_USART7_GLB_Msk /*!< USART7 GLB Interrupt */ +#define SYSCFG_ITLINE29_SR_USART8_GLB_Pos (5U) +#define SYSCFG_ITLINE29_SR_USART8_GLB_Msk (0x1U << SYSCFG_ITLINE29_SR_USART8_GLB_Pos) /*!< 0x00000020 */ +#define SYSCFG_ITLINE29_SR_USART8_GLB SYSCFG_ITLINE29_SR_USART8_GLB_Msk /*!< USART8 GLB Interrupt */ +#define SYSCFG_ITLINE30_SR_CAN_Pos (0U) +#define SYSCFG_ITLINE30_SR_CAN_Msk (0x1U << SYSCFG_ITLINE30_SR_CAN_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE30_SR_CAN SYSCFG_ITLINE30_SR_CAN_Msk /*!< CAN Interrupt */ +#define SYSCFG_ITLINE30_SR_CEC_Pos (1U) +#define SYSCFG_ITLINE30_SR_CEC_Msk (0x1U << SYSCFG_ITLINE30_SR_CEC_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE30_SR_CEC SYSCFG_ITLINE30_SR_CEC_Msk /*!< CEC Interrupt */ /*****************************************************************************/ /* */ @@ -4950,297 +9825,549 @@ typedef struct /* */ /*****************************************************************************/ /******************* Bit definition for TIM_CR1 register *******************/ -#define TIM_CR1_CEN ((uint32_t)0x00000001U) /*!CSR, COMP_CSR_COMPxEN << regshift); - - hcomp->State = HAL_COMP_STATE_BUSY; + + /* Set HAL COMP handle state */ + hcomp->State = HAL_COMP_STATE_BUSY; + + /* Delay for COMP startup time */ + wait_loop_index = (LL_COMP_DELAY_STARTUP_US * (SystemCoreClock / 1000000)); + while(wait_loop_index != 0) + { + wait_loop_index--; + } } else { @@ -478,7 +499,7 @@ HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp) * @retval HAL status. */ HAL_StatusTypeDef HAL_COMP_Start_IT(COMP_HandleTypeDef *hcomp) -{ +{ HAL_StatusTypeDef status = HAL_OK; uint32_t extiline = 0; diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_comp.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_comp.h index 06a8352ea9..79b1e964af 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_comp.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_comp.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f0xx_hal_comp.h * @author MCD Application Team - * @version V1.3.1 - * @date 29-January-2016 + * @version V1.4.0 + * @date 27-May-2016 * @brief Header file of COMP HAL module. ****************************************************************************** * @attention diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_conf.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_conf.h index 80996dad42..c3788fb48e 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_conf.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_conf.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f0xx_hal_conf.h * @author MCD Application Team - * @version V1.3.1 - * @date 29-January-2016 + * @version V1.4.0 + * @date 27-May-2016 * @brief HAL configuration file. ****************************************************************************** * @attention @@ -296,11 +296,11 @@ * If expr is true, it returns no value. * @retval None */ - #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) + #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) /* Exported functions ------------------------------------------------------- */ void assert_failed(uint8_t* file, uint32_t line); #else - #define assert_param(expr) ((void)0) + #define assert_param(expr) ((void)0U) #endif /* USE_FULL_ASSERT */ #ifdef __cplusplus diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_cortex.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_cortex.c index cdc9a1537c..d8156aefaf 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_cortex.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_cortex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f0xx_hal_cortex.c * @author MCD Application Team - * @version V1.3.1 - * @date 29-January-2016 + * @version V1.4.0 + * @date 27-May-2016 * @brief CORTEX HAL module driver. * This file provides firmware functions to manage the following * functionalities of the CORTEX: diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_cortex.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_cortex.h index 16ebfc0454..cf25f805d5 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_cortex.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_cortex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f0xx_hal_cortex.h * @author MCD Application Team - * @version V1.3.1 - * @date 29-January-2016 + * @version V1.4.0 + * @date 27-May-2016 * @brief Header file of CORTEX HAL module. ****************************************************************************** * @attention diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_crc.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_crc.c index 0b51ec1c5d..00ada16867 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_crc.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_crc.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f0xx_hal_crc.c * @author MCD Application Team - * @version V1.3.1 - * @date 29-January-2016 + * @version V1.4.0 + * @date 27-May-2016 * @brief CRC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Cyclic Redundancy Check (CRC) peripheral: @@ -204,6 +204,9 @@ HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc) /* Change CRC peripheral state */ hcrc->State = HAL_CRC_STATE_BUSY; + + /* Reset IDR register content */ + CLEAR_BIT(hcrc->Instance->IDR, CRC_IDR_IDR) ; /* DeInit the low level hardware */ HAL_CRC_MspDeInit(hcrc); diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_crc.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_crc.h index 2a26593cda..b6d11151c6 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_crc.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_crc.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f0xx_hal_crc.h * @author MCD Application Team - * @version V1.3.1 - * @date 29-January-2016 + * @version V1.4.0 + * @date 27-May-2016 * @brief Header file of CRC HAL module. ****************************************************************************** * @attention @@ -166,11 +166,17 @@ typedef struct /** @defgroup CRC_Default_Polynomial Indicates whether or not default polynomial is used * @{ */ +#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) #define DEFAULT_POLYNOMIAL_ENABLE ((uint8_t)0x00) #define DEFAULT_POLYNOMIAL_DISABLE ((uint8_t)0x01) #define IS_DEFAULT_POLYNOMIAL(DEFAULT) (((DEFAULT) == DEFAULT_POLYNOMIAL_ENABLE) || \ ((DEFAULT) == DEFAULT_POLYNOMIAL_DISABLE)) +#else +#define DEFAULT_POLYNOMIAL_ENABLE ((uint8_t)0x00) + +#define IS_DEFAULT_POLYNOMIAL(DEFAULT) ((DEFAULT) == DEFAULT_POLYNOMIAL_ENABLE) +#endif /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) */ /** * @} diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_crc_ex.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_crc_ex.c index 6cc0934f62..479ad8e9c7 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_crc_ex.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_crc_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f0xx_hal_crc_ex.c * @author MCD Application Team - * @version V1.3.1 - * @date 29-January-2016 + * @version V1.4.0 + * @date 27-May-2016 * @brief Extended CRC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the CRC peripheral: diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_crc_ex.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_crc_ex.h index 998c91626e..09bc2ad073 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_crc_ex.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_crc_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f0xx_hal_crc_ex.h * @author MCD Application Team - * @version V1.3.1 - * @date 29-January-2016 + * @version V1.4.0 + * @date 27-May-2016 * @brief Header file of CRC HAL extension module. ****************************************************************************** * @attention @@ -117,7 +117,7 @@ #define HAL_CRC_LENGTH_7B 7 #else #define HAL_CRC_LENGTH_32B 32 -#endif /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) */ +#endif /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) */ /** * @} */ @@ -145,7 +145,7 @@ */ #define __HAL_CRC_OUTPUTREVERSAL_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(CRC_CR_REV_OUT)) -#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC) +#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) /** * @brief Set CRC non-default polynomial * @param __HANDLE__ : CRC handle @@ -153,7 +153,7 @@ * @retval None. */ #define __HAL_CRC_POLYNOMIAL_CONFIG(__HANDLE__, __POLYNOMIAL__) ((__HANDLE__)->Instance->POL = (__POLYNOMIAL__)) -#endif /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC) */ +#endif /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) */ /** * @} */ @@ -173,9 +173,9 @@ HAL_StatusTypeDef HAL_CRCEx_Init(CRC_HandleTypeDef *hcrc); HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode); HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode); -#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC) +#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength); -#endif /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC) */ +#endif /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) */ /** * @} */ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dac.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dac.c index 9354658819..9c68dab3bf 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dac.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dac.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f0xx_hal_dac.c * @author MCD Application Team - * @version V1.3.1 - * @date 29-January-2016 + * @version V1.4.0 + * @date 27-May-2016 * @brief DAC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Digital to Analog Converter (DAC) peripheral: diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dac.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dac.h index 1b06918c68..ea82e8b7c7 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dac.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dac.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f0xx_hal_dac.h * @author MCD Application Team - * @version V1.3.1 - * @date 29-January-2016 + * @version V1.4.0 + * @date 27-May-2016 * @brief Header file of DAC HAL module. ****************************************************************************** * @attention diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dac_ex.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dac_ex.c index e535d1aed4..f35b1f3f92 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dac_ex.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dac_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f0xx_hal_dac_ex.c * @author MCD Application Team - * @version V1.3.1 - * @date 29-January-2016 + * @version V1.4.0 + * @date 27-May-2016 * @brief DAC HAL module driver. * This file provides firmware functions to manage the extended * functionalities of the DAC peripheral. diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dac_ex.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dac_ex.h index 28647f263c..ce98b289b3 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dac_ex.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dac_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f0xx_hal_dac_ex.h * @author MCD Application Team - * @version V1.3.1 - * @date 29-January-2016 + * @version V1.4.0 + * @date 27-May-2016 * @brief Header file of DAC HAL Extension module. ****************************************************************************** * @attention diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_def.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_def.h index 167258f2f8..8ca313cb6a 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_def.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_def.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f0xx_hal_def.h * @author MCD Application Team - * @version V1.3.1 - * @date 29-January-2016 + * @version V1.4.0 + * @date 27-May-2016 * @brief This file contains HAL common defines, enumeration, macros and * structures definitions. ****************************************************************************** diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dma.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dma.c index 739a7ffcf6..1bb88ad6d4 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dma.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dma.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f0xx_hal_dma.c * @author MCD Application Team - * @version V1.3.1 - * @date 29-January-2016 + * @version V1.4.0 + * @date 27-May-2016 * @brief DMA HAL module driver. * * This file provides firmware functions to manage the following @@ -247,21 +247,15 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) /* Check the parameters */ assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); - /* Check the DMA peripheral state */ - if(hdma->State == HAL_DMA_STATE_BUSY) - { - return HAL_ERROR; - } - /* Disable the selected DMA Channelx */ __HAL_DMA_DISABLE(hdma); - + /* Reset DMA Channel control register */ hdma->Instance->CCR = 0; - + /* Reset DMA Channel Number of Data to Transfer register */ hdma->Instance->CNDTR = 0; - + /* Reset DMA Channel peripheral address register */ hdma->Instance->CPAR = 0; @@ -272,7 +266,7 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)); __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); - + /* Initialize the error code */ hdma->ErrorCode = HAL_DMA_ERROR_NONE; @@ -430,6 +424,49 @@ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) return HAL_OK; } +/** + * @brief Aborts the DMA Transfer in Interrupt mode. + * @param hdma : pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) +{ + HAL_StatusTypeDef status = HAL_OK; + + if(HAL_DMA_STATE_BUSY != hdma->State) + { + /* no transfer ongoing */ + hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + + status = HAL_ERROR; + } + else + { + /* Disable DMA IT */ + __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); + + /* Disable the channel */ + __HAL_DMA_DISABLE(hdma); + + /* Clear all flags */ + __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_GI_FLAG_INDEX(hdma)); + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + /* Call User Abort callback */ + if(hdma->XferAbortCallback != NULL) + { + hdma->XferAbortCallback(hdma); + } + } + return status; +} + /** * @brief Polling for transfer complete. * @param hdma: pointer to a DMA_HandleTypeDef structure that contains @@ -549,7 +586,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) /* Process Unlocked */ __HAL_UNLOCK(hdma); - if (hdma->XferErrorCallback != (void (*)(DMA_HandleTypeDef *))NULL) + if(hdma->XferErrorCallback != NULL) { /* Transfer error callback */ hdma->XferErrorCallback(hdma); @@ -574,7 +611,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_READY_HALF; - if(hdma->XferHalfCpltCallback != (void (*)(DMA_HandleTypeDef *))NULL) + if(hdma->XferHalfCpltCallback != NULL) { /* Half transfer callback */ hdma->XferHalfCpltCallback(hdma); @@ -604,7 +641,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) /* Process Unlocked */ __HAL_UNLOCK(hdma); - if(hdma->XferCpltCallback != (void (*)(DMA_HandleTypeDef *))NULL) + if(hdma->XferCpltCallback != NULL) { /* Transfer complete callback */ hdma->XferCpltCallback(hdma); diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dma.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dma.h index b488dcaa19..53a0a12712 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dma.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dma.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f0xx_hal_dma.h * @author MCD Application Team - * @version V1.3.1 - * @date 29-January-2016 + * @version V1.4.0 + * @date 27-May-2016 * @brief Header file of DMA HAL module. ****************************************************************************** * @attention @@ -143,6 +143,8 @@ typedef struct __DMA_HandleTypeDef void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */ + void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer abort callback */ + __IO uint32_t ErrorCode; /*!< DMA Error code */ } DMA_HandleTypeDef; @@ -159,9 +161,10 @@ typedef struct __DMA_HandleTypeDef /** @defgroup DMA_Error_Code DMA Error Code * @{ */ -#define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */ -#define HAL_DMA_ERROR_TE ((uint32_t)0x00000001) /*!< Transfer error */ -#define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */ +#define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */ +#define HAL_DMA_ERROR_TE ((uint32_t)0x00000001) /*!< Transfer error */ +#define HAL_DMA_ERROR_NO_XFER ((uint32_t)0x00000004) /*!< no ongoin transfer */ +#define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */ /** * @} */ @@ -414,6 +417,14 @@ typedef struct __DMA_HandleTypeDef */ #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CCR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) +/** + * @brief Returns the number of remaining data units in the current DMAy Channelx transfer. + * @param __HANDLE__: DMA handle + * + * @retval The number of remaining data units in the current DMA Channel transfer. + */ +#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR) + #if defined(SYSCFG_CFGR1_DMA_RMP) /** @brief DMA remapping enable/disable macros * @param __DMA_REMAP__: This parameter can be a value of @ref HAL_DMA_remapping @@ -455,6 +466,7 @@ HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma); HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); +HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma); HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout); void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); /** diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dma_ex.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dma_ex.h index c0f25be733..ef285f5e4a 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dma_ex.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dma_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f0xx_hal_dma_ex.h * @author MCD Application Team - * @version V1.3.1 - * @date 29-January-2016 + * @version V1.4.0 + * @date 27-May-2016 * @brief Header file of DMA HAL Extension module. ****************************************************************************** * @attention @@ -563,6 +563,20 @@ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\ DMA_FLAG_TE7) +/** + * @brief Return the current DMA Channel Global interrupt flag. + * @param __HANDLE__: DMA handle + * @retval The specified transfer error flag index. + */ +#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GL1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GL2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GL3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GL4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_GL5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_GL6 :\ + DMA_FLAG_GL7) + /** * @brief Get the DMA Channel pending flags. * @param __HANDLE__: DMA handle @@ -648,6 +662,25 @@ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\ DMA_FLAG_TE5) +/** + * @brief Return the current DMA Channel Global interrupt flag. + * @param __HANDLE__: DMA handle + * @retval The specified transfer error flag index. + */ +#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GL1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GL2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GL3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GL4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_GL5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_GL6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_GL7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_GL1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_GL2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_GL3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_GL4 :\ + DMA_FLAG_GL5) + /** * @brief Get the DMA Channel pending flags. * @param __HANDLE__: DMA handle @@ -716,6 +749,18 @@ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ DMA_FLAG_TE5) +/** + * @brief Return the current DMA Channel Global interrupt flag. + * @param __HANDLE__: DMA handle + * @retval The specified transfer error flag index. + */ +#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GL1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GL2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GL3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GL4 :\ + DMA_FLAG_GL5) + /** * @brief Get the DMA Channel pending flags. * @param __HANDLE__: DMA handle diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_flash.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_flash.c index c67700314c..876cfc9e1e 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_flash.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_flash.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f0xx_hal_flash.c * @author MCD Application Team - * @version V1.3.1 - * @date 29-January-2016 + * @version V1.4.0 + * @date 27-May-2016 * @brief FLASH HAL module driver. * This file provides firmware functions to manage the following * functionalities of the internal FLASH memory: @@ -41,7 +41,6 @@ (++) Lock and Unlock the FLASH interface (++) Erase function: Erase page, erase all pages (++) Program functions: half word, word and doubleword - (#) FLASH Option Bytes Programming functions: this group includes all needed functions to manage the Option Bytes: (++) Lock and Unlock the Option Bytes @@ -58,7 +57,7 @@ includes all needed functions to: (++) Handle FLASH interrupts (++) Wait for last FLASH operation according to its status - (++) Get error flag status + (++) Get error flag status [..] In addition to these function, this driver includes a set of macros allowing to handle the following operations: @@ -147,6 +146,7 @@ FLASH_ProcessTypeDef pFlash; */ static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data); static void FLASH_SetErrorCode(void); +extern void FLASH_PageErase(uint32_t PageAddress); /** * @} */ @@ -196,7 +196,7 @@ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint assert_param(IS_FLASH_PROGRAM_ADDRESS(Address)); /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); if(status == HAL_OK) { @@ -221,7 +221,7 @@ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint FLASH_Program_HalfWord((Address + (2*index)), (uint16_t)(Data >> (16*index))); /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); /* If the program operation is completed, disable the PG Bit */ CLEAR_BIT(FLASH->CR, FLASH_CR_PG); @@ -274,23 +274,23 @@ HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, u if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD) { pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMHALFWORD; - /*Program halfword (16-bit) at a specified address.*/ + /* Program halfword (16-bit) at a specified address. */ pFlash.DataRemaining = 1; } else if(TypeProgram == FLASH_TYPEPROGRAM_WORD) { pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMWORD; - /*Program word (32-bit : 2*16-bit) at a specified address.*/ + /* Program word (32-bit : 2*16-bit) at a specified address. */ pFlash.DataRemaining = 2; } else { pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMDOUBLEWORD; - /*Program double word (64-bit : 4*16-bit) at a specified address.*/ + /* Program double word (64-bit : 4*16-bit) at a specified address. */ pFlash.DataRemaining = 4; } - /*Program halfword (16-bit) at a specified address.*/ + /* Program halfword (16-bit) at a specified address. */ FLASH_Program_HalfWord(Address, (uint16_t)Data); return status; @@ -307,18 +307,18 @@ void HAL_FLASH_IRQHandler(void) /* Check FLASH operation error flags */ if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) ||__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR)) { - /*return the faulty address*/ + /* Return the faulty address */ addresstmp = pFlash.Address; /* Reset address */ pFlash.Address = 0xFFFFFFFFU; - /*Save the Error code*/ + /* Save the Error code */ FLASH_SetErrorCode(); /* FLASH error interrupt user callback */ HAL_FLASH_OperationErrorCallback(addresstmp); - /* Stop the procedure ongoing*/ + /* Stop the procedure ongoing */ pFlash.ProcedureOnGoing = FLASH_PROC_NONE; } @@ -336,11 +336,11 @@ void HAL_FLASH_IRQHandler(void) /* Nb of pages to erased can be decreased */ pFlash.DataRemaining--; - /* Check if there are still pages to erase*/ + /* Check if there are still pages to erase */ if(pFlash.DataRemaining != 0) { addresstmp = pFlash.Address; - /*Indicate user which sector has been erased*/ + /*Indicate user which sector has been erased */ HAL_FLASH_EndOfOperationCallback(addresstmp); /*Increment sector number*/ @@ -354,8 +354,8 @@ void HAL_FLASH_IRQHandler(void) } else { - /*No more pages to Erase, user callback can be called.*/ - /*Reset Sector and stop Erase pages procedure*/ + /* No more pages to Erase, user callback can be called. */ + /* Reset Sector and stop Erase pages procedure */ pFlash.Address = addresstmp = 0xFFFFFFFFU; pFlash.ProcedureOnGoing = FLASH_PROC_NONE; /* FLASH EOP interrupt user callback */ @@ -367,7 +367,7 @@ void HAL_FLASH_IRQHandler(void) /* Operation is completed, disable the MER Bit */ CLEAR_BIT(FLASH->CR, FLASH_CR_MER); - /* MassErase ended. Return the selected bank*/ + /* MassErase ended. Return the selected bank */ /* FLASH EOP interrupt user callback */ HAL_FLASH_EndOfOperationCallback(0); @@ -397,7 +397,7 @@ void HAL_FLASH_IRQHandler(void) } else { - /*Program ended. Return the selected address*/ + /* Program ended. Return the selected address */ /* FLASH EOP interrupt user callback */ if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMHALFWORD) { @@ -412,7 +412,7 @@ void HAL_FLASH_IRQHandler(void) HAL_FLASH_EndOfOperationCallback(pFlash.Address - 6); } - /* Reset Address and stop Program procedure*/ + /* Reset Address and stop Program procedure */ pFlash.Address = 0xFFFFFFFFU; pFlash.ProcedureOnGoing = FLASH_PROC_NONE; } @@ -434,7 +434,6 @@ void HAL_FLASH_IRQHandler(void) } } - /** * @brief FLASH end of operation interrupt callback * @param ReturnValue: The value saved in this parameter depends on the ongoing procedure @@ -520,11 +519,9 @@ HAL_StatusTypeDef HAL_FLASH_Lock(void) /* Set the LOCK Bit to lock the FLASH Registers access */ SET_BIT(FLASH->CR, FLASH_CR_LOCK); - return HAL_OK; } - /** * @brief Unlock the FLASH Option Control Registers access. * @retval HAL Status @@ -560,7 +557,7 @@ HAL_StatusTypeDef HAL_FLASH_OB_Lock(void) /** * @brief Launch the option byte loading. * @note This function will reset automatically the MCU. - * @retval HAL_StatusTypeDef HAL Status + * @retval HAL Status */ HAL_StatusTypeDef HAL_FLASH_OB_Launch(void) { @@ -568,22 +565,22 @@ HAL_StatusTypeDef HAL_FLASH_OB_Launch(void) SET_BIT(FLASH->CR, FLASH_CR_OBL_LAUNCH); /* Wait for last operation to be completed */ - return(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE)); + return(FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE)); } /** * @} */ -/** @defgroup FLASH_Exported_Functions_Group3 Peripheral State functions - * @brief Peripheral State functions +/** @defgroup FLASH_Exported_Functions_Group3 Peripheral errors functions + * @brief Peripheral errors functions * @verbatim =============================================================================== - ##### Peripheral State functions ##### + ##### Peripheral Errors functions ##### =============================================================================== [..] - This subsection permit to get in run-time the status of the FLASH peripheral. + This subsection permit to get in run-time errors of the FLASH peripheral. @endverbatim * @{ @@ -591,13 +588,14 @@ HAL_StatusTypeDef HAL_FLASH_OB_Launch(void) /** * @brief Get the specific FLASH error flag. - * @retval FLASH_ErrorCode: The returned value can be: + * @retval FLASH_ErrorCode The returned value can be: * @ref FLASH_Error_Codes */ uint32_t HAL_FLASH_GetError(void) -{ +{ return pFlash.ErrorCode; -} +} + /** * @} */ @@ -612,8 +610,8 @@ uint32_t HAL_FLASH_GetError(void) /** * @brief Program a half-word (16-bit) at a specified address. - * @param Address: specifies the address to be programmed. - * @param Data: specifies the data to be programmed. + * @param Address specify the address to be programmed. + * @param Data specify the data to be programmed. * @retval None */ static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data) @@ -630,8 +628,8 @@ static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data) /** * @brief Wait for a FLASH operation to complete. - * @param Timeout: maximum flash operation timeout - * @retval HAL_StatusTypeDef HAL Status + * @param Timeout maximum flash operation timeout + * @retval HAL Status */ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) { @@ -667,7 +665,7 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) return HAL_ERROR; } - /* If there is no error flag set */ + /* There is no error flag set */ return HAL_OK; } @@ -677,18 +675,21 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) * @retval None */ static void FLASH_SetErrorCode(void) -{ +{ + uint32_t flags = 0; + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR)) { pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP; + flags |= FLASH_FLAG_WRPERR; } if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR)) { - pFlash.ErrorCode |= HAL_FLASH_ERROR_PROG; + pFlash.ErrorCode |= HAL_FLASH_ERROR_PROG; + flags |= FLASH_FLAG_PGERR; } - /* Clear FLASH error pending bits */ - __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_WRPERR | FLASH_FLAG_PGERR); + __HAL_FLASH_CLEAR_FLAG(flags); } /** * @} diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_flash.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_flash.h index 21f993c296..7d57c0f078 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_flash.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_flash.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f0xx_hal_flash.h * @author MCD Application Team - * @version V1.3.1 - * @date 29-January-2016 + * @version V1.4.0 + * @date 27-May-2016 * @brief Header file of Flash HAL module. ****************************************************************************** * @attention @@ -57,7 +57,7 @@ /** @addtogroup FLASH_Private_Constants * @{ */ -#define FLASH_TIMEOUT_VALUE ((uint32_t)50000)/* 50 s */ +#define FLASH_TIMEOUT_VALUE ((uint32_t)50000U) /* 50 s */ /** * @} */ @@ -82,7 +82,6 @@ * @{ */ - /** * @brief FLASH Procedure structure definition */ @@ -128,9 +127,9 @@ typedef struct * @{ */ -#define HAL_FLASH_ERROR_NONE ((uint32_t)0x00) /*!< No error */ -#define HAL_FLASH_ERROR_PROG ((uint32_t)0x01) /*!< Programming error */ -#define HAL_FLASH_ERROR_WRP ((uint32_t)0x02) /*!< Write protection error */ +#define HAL_FLASH_ERROR_NONE 0x00U /*!< No error */ +#define HAL_FLASH_ERROR_PROG 0x01U /*!< Programming error */ +#define HAL_FLASH_ERROR_WRP 0x02U /*!< Write protection error */ /** * @} @@ -139,9 +138,9 @@ typedef struct /** @defgroup FLASH_Type_Program FLASH Type Program * @{ */ -#define FLASH_TYPEPROGRAM_HALFWORD ((uint32_t)0x01) /*!Pull)); /* Configure the port pins */ - while ((GPIO_Init->Pin) >> position) + while (((GPIO_Init->Pin) >> position) != RESET) { /* Get current io position */ - iocurrent = (GPIO_Init->Pin) & (1 << position); + iocurrent = (GPIO_Init->Pin) & (1U << position); if(iocurrent) { @@ -321,10 +321,10 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) assert_param(IS_GPIO_PIN(GPIO_Pin)); /* Configure the port pins */ - while (GPIO_Pin >> position) + while ((GPIO_Pin >> position) != RESET) { /* Get current io position */ - iocurrent = (GPIO_Pin) & (1 << position); + iocurrent = GPIO_Pin & (1U << position); if (iocurrent) { diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_gpio.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_gpio.h index 41b697592a..fff17800d8 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_gpio.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_gpio.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f0xx_hal_gpio.h * @author MCD Application Team - * @version V1.3.1 - * @date 29-January-2016 + * @version V1.4.0 + * @date 27-May-2016 * @brief Header file of GPIO HAL module. ****************************************************************************** * @attention @@ -229,7 +229,8 @@ typedef enum */ #define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET)) -#define IS_GPIO_PIN(__PIN__) (((__PIN__) & GPIO_PIN_MASK) != (uint32_t)0x00) +#define IS_GPIO_PIN(__PIN__) ((((__PIN__) & GPIO_PIN_MASK) != (uint32_t)0x00) &&\ + (((__PIN__) & ~GPIO_PIN_MASK) == (uint32_t)0x00)) #define IS_GPIO_MODE(__MODE__) (((__MODE__) == GPIO_MODE_INPUT) ||\ ((__MODE__) == GPIO_MODE_OUTPUT_PP) ||\ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_gpio_ex.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_gpio_ex.h index 77340a9d25..4dd6120d0a 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_gpio_ex.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_gpio_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f0xx_hal_gpio_ex.h * @author MCD Application Team - * @version V1.3.1 - * @date 29-January-2016 + * @version V1.4.0 + * @date 27-May-2016 * @brief Header file of GPIO HAL Extension module. ****************************************************************************** * @attention diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_i2c.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_i2c.c index f6225c800d..a4c07b0421 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_i2c.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_i2c.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f0xx_hal_i2c.c * @author MCD Application Team - * @version V1.3.1 - * @date 29-January-2016 + * @version V1.4.0 + * @date 27-May-2016 * @brief I2C HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Inter Integrated Circuit (I2C) peripheral: @@ -80,6 +80,61 @@ add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can add his own code by customization of function pointer HAL_I2C_ErrorCallback() + (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_AbortCpltCallback() + (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro. + This action will inform Master to generate a Stop condition to discard the communication. + + + *** Interrupt mode IO sequential operation *** + =================================== + [..] + (@) These interfaces allow to manage a sequential transfer with a repeated start condition + when a direction change during transfer + [..] + (+) A specific option field manage the different steps of a sequential transfer + (+) Option field values are defined through I2C_XferOptions_definition and are listed below: + (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functionnal is same as associated interfaces in no sequential mode + (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address + and data to transfer without a final stop condition + (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address + and with new data to transfer if the direction change or manage only the new data to transfer + if no direction change and without a final stop condition in both cases + (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address + and with new data to transfer if the direction change or manage only the new data to transfer + if no direction change and with a final stop condition in both cases + + (+) Differents sequential I2C interfaces are listed below: + (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Transmit_IT() + (+++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() + (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Receive_IT() + (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() + (++) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_AbortCpltCallback() + (+++) mean HAL_I2C_MasterTxCpltCallback() in case of previous state was master transmit + (+++) mean HAL_I2c_MasterRxCpltCallback() in case of previous state was master receive + (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT() HAL_I2C_DisableListen_IT() + (+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and user can + add his own code to check the Address Match Code and the transmission direction request by master (Write/Read). + (+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_ListenCpltCallback() + (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Transmit_IT() + (+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() + (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Receive_IT() + (+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() + (++) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_I2C_ErrorCallback() + (++) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_AbortCpltCallback() + (++) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro. + This action will inform Master to generate a Stop condition to discard the communication. *** Interrupt mode IO MEM operation *** ======================================= @@ -116,6 +171,11 @@ add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can add his own code by customization of function pointer HAL_I2C_ErrorCallback() + (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_AbortCpltCallback() + (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro. + This action will inform Master to generate a Stop condition to discard the communication. *** DMA mode IO MEM operation *** ================================= @@ -139,6 +199,7 @@ (+) __HAL_I2C_ENABLE: Enable the I2C peripheral (+) __HAL_I2C_DISABLE: Disable the I2C peripheral + (+) __HAL_I2C_GENERATE_NACK: Generate a Non-Acknowledge I2C peripheral in Slave mode (+) __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not (+) __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt @@ -198,56 +259,102 @@ /** @defgroup I2C_Private_Define I2C Private Define * @{ */ -#define TIMING_CLEAR_MASK ((uint32_t)0xF0FFFFFFU) /*!< I2C TIMING clear register Mask */ -#define I2C_TIMEOUT_ADDR ((uint32_t)10000) /*!< 10 s */ -#define I2C_TIMEOUT_BUSY ((uint32_t)25) /*!< 25 ms */ -#define I2C_TIMEOUT_DIR ((uint32_t)25) /*!< 25 ms */ -#define I2C_TIMEOUT_RXNE ((uint32_t)25) /*!< 25 ms */ -#define I2C_TIMEOUT_STOPF ((uint32_t)25) /*!< 25 ms */ -#define I2C_TIMEOUT_TC ((uint32_t)25) /*!< 25 ms */ -#define I2C_TIMEOUT_TCR ((uint32_t)25) /*!< 25 ms */ -#define I2C_TIMEOUT_TXIS ((uint32_t)25) /*!< 25 ms */ -#define I2C_TIMEOUT_FLAG ((uint32_t)25) /*!< 25 ms */ +#define TIMING_CLEAR_MASK (0xF0FFFFFFU) /*!< I2C TIMING clear register Mask */ +#define I2C_TIMEOUT_ADDR (10000U) /*!< 10 s */ +#define I2C_TIMEOUT_BUSY (25U) /*!< 25 ms */ +#define I2C_TIMEOUT_DIR (25U) /*!< 25 ms */ +#define I2C_TIMEOUT_RXNE (25U) /*!< 25 ms */ +#define I2C_TIMEOUT_STOPF (25U) /*!< 25 ms */ +#define I2C_TIMEOUT_TC (25U) /*!< 25 ms */ +#define I2C_TIMEOUT_TCR (25U) /*!< 25 ms */ +#define I2C_TIMEOUT_TXIS (25U) /*!< 25 ms */ +#define I2C_TIMEOUT_FLAG (25U) /*!< 25 ms */ -#define MAX_NBYTE_SIZE 255 +#define MAX_NBYTE_SIZE 255U +#define SlaveAddr_SHIFT 7U +#define SlaveAddr_MSK 0x06U + +/* Private define for @ref PreviousState usage */ +#define I2C_STATE_MSK ((uint32_t)((HAL_I2C_STATE_BUSY_TX | HAL_I2C_STATE_BUSY_RX) & (uint32_t)(~HAL_I2C_STATE_READY))) /*!< Mask State define, keep only RX and TX bits */ +#define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE)) /*!< Default Value */ +#define I2C_STATE_MASTER_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER)) /*!< Master Busy TX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_MASTER_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER)) /*!< Master Busy RX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE)) /*!< Slave Busy TX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE)) /*!< Slave Busy RX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_MEM_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_MEM)) /*!< Memory Busy TX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_MEM_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_MEM)) /*!< Memory Busy RX, combinaison of State LSB and Mode enum */ + + +/* Private define to centralize the enable/disable of Interrupts */ +#define I2C_XFER_TX_IT (0x00000001U) +#define I2C_XFER_RX_IT (0x00000002U) +#define I2C_XFER_LISTEN_IT (0x00000004U) + +#define I2C_XFER_ERROR_IT (0x00000011U) +#define I2C_XFER_CPLT_IT (0x00000012U) +#define I2C_XFER_RELOAD_IT (0x00000012U) /** * @} */ - + /* Private macro -------------------------------------------------------------*/ +#define I2C_GET_DMA_REMAIN_DATA(__HANDLE__) ((((__HANDLE__)->State) == HAL_I2C_STATE_BUSY_TX) ? \ + ((uint32_t)((__HANDLE__)->hdmatx->Instance->CNDTR)) : \ + ((uint32_t)((__HANDLE__)->hdmarx->Instance->CNDTR))) + /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /** @defgroup I2C_Private_Functions I2C Private Functions * @{ */ +/* Private functions to handle DMA transfer */ static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma); static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma); static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma); static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma); -static void I2C_DMAMemTransmitCplt(DMA_HandleTypeDef *hdma); -static void I2C_DMAMemReceiveCplt(DMA_HandleTypeDef *hdma); static void I2C_DMAError(DMA_HandleTypeDef *hdma); +static void I2C_DMAAbort(DMA_HandleTypeDef *hdma); -static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout); -static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout); -static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout); -static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout); -static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout); -static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout); -static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout); +/* Private functions to handle IT transfer */ +static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); +static void I2C_ITMasterSequentialCplt(I2C_HandleTypeDef *hi2c); +static void I2C_ITSlaveSequentialCplt(I2C_HandleTypeDef *hi2c); +static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); +static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); +static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); +static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode); -static HAL_StatusTypeDef I2C_MasterTransmit_ISR(I2C_HandleTypeDef *hi2c); -static HAL_StatusTypeDef I2C_MasterReceive_ISR(I2C_HandleTypeDef *hi2c); +/* Private functions to handle IT transfer */ +static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart); -static HAL_StatusTypeDef I2C_SlaveTransmit_ISR(I2C_HandleTypeDef *hi2c); -static HAL_StatusTypeDef I2C_SlaveReceive_ISR(I2C_HandleTypeDef *hi2c); +/* Private functions for I2C transfer IRQ handler */ +static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); +static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); +static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); +static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); +/* Private functions to handle flags during polling transfer */ +static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); + +/* Private functions to centralize the enable/disable of Interrupts */ +static HAL_StatusTypeDef I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest); +static HAL_StatusTypeDef I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest); + +/* Private functions to flush TXDR register */ +static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c); + +/* Private functions to handle start, restart or stop a transfer */ static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request); /** * @} */ - + /* Exported functions --------------------------------------------------------*/ /** @defgroup I2C_Exported_Functions I2C Exported Functions @@ -257,7 +364,7 @@ static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, ui /** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions * @brief Initialization and Configuration functions * -@verbatim +@verbatim =============================================================================== ##### Initialization and de-initialization functions ##### =============================================================================== @@ -293,13 +400,13 @@ static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, ui * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) -{ +{ /* Check the I2C handle allocation */ if(hi2c == NULL) { return HAL_ERROR; } - + /* Check the parameters */ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1)); @@ -320,18 +427,18 @@ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) } hi2c->State = HAL_I2C_STATE_BUSY; - + /* Disable the selected I2C peripheral */ __HAL_I2C_DISABLE(hi2c); - + /*---------------------------- I2Cx TIMINGR Configuration ------------------*/ /* Configure I2Cx: Frequency range */ hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK; - + /*---------------------------- I2Cx OAR1 Configuration ---------------------*/ /* Configure I2Cx: Own Address1 and ack own address1 mode */ hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN; - if(hi2c->Init.OwnAddress1 != 0) + if(hi2c->Init.OwnAddress1 != 0U) { if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) { @@ -351,7 +458,7 @@ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) } /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */ hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK); - + /*---------------------------- I2Cx OAR2 Configuration ---------------------*/ /* Configure I2Cx: Dual mode and Own Address2 */ hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | (hi2c->Init.OwnAddress2Masks << 8)); @@ -359,14 +466,15 @@ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) /*---------------------------- I2Cx CR1 Configuration ----------------------*/ /* Configure I2Cx: Generalcall and NoStretch mode */ hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode); - + /* Enable the selected I2C peripheral */ __HAL_I2C_ENABLE(hi2c); - + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; hi2c->Mode = HAL_I2C_MODE_NONE; - + return HAL_OK; } @@ -383,23 +491,23 @@ HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) { return HAL_ERROR; } - + /* Check the parameters */ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); - + hi2c->State = HAL_I2C_STATE_BUSY; - + /* Disable the I2C Peripheral Clock */ __HAL_I2C_DISABLE(hi2c); - + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ HAL_I2C_MspDeInit(hi2c); - - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; hi2c->State = HAL_I2C_STATE_RESET; + hi2c->PreviousState = I2C_STATE_NONE; hi2c->Mode = HAL_I2C_MODE_NONE; - + /* Release Lock */ __HAL_UNLOCK(hi2c); @@ -505,7 +613,8 @@ HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) * @brief Transmits in master mode an amount of data in blocking mode. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. - * @param DevAddress Target device address + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shift at right before call interface * @param pData Pointer to data buffer * @param Size Amount of data to be sent * @param Timeout Timeout duration @@ -513,40 +622,47 @@ HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) */ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout) { - uint32_t sizetmp = 0; + uint32_t tickstart = 0U; if(hi2c->State == HAL_I2C_STATE_READY) - { - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) - { - return HAL_BUSY; - } - + { /* Process Locked */ __HAL_LOCK(hi2c); - + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) + { + return HAL_TIMEOUT; + } + hi2c->State = HAL_I2C_STATE_BUSY_TX; hi2c->Mode = HAL_I2C_MODE_MASTER; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferISR = NULL; + /* Send Slave Address */ - /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */ - /* Size > MAX_NBYTE_SIZE, need to set RELOAD bit */ - if(Size > MAX_NBYTE_SIZE) + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + if(hi2c->XferCount > MAX_NBYTE_SIZE) { - I2C_TransferConfig(hi2c, DevAddress, MAX_NBYTE_SIZE, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); - sizetmp = MAX_NBYTE_SIZE; + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); } else { - I2C_TransferConfig(hi2c, DevAddress, Size, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE); - sizetmp = Size; + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE); } - while(Size > 0) + while(hi2c->XferCount > 0U) { /* Wait until TXIS flag is set */ - if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout) != HAL_OK) + if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) { @@ -558,34 +674,34 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA } } /* Write data to TXDR */ - hi2c->Instance->TXDR = (*pData++); - sizetmp--; - Size--; + hi2c->Instance->TXDR = (*hi2c->pBuffPtr++); + hi2c->XferCount--; + hi2c->XferSize--; - if((sizetmp == 0)&&(Size!=0)) + if((hi2c->XferSize == 0U) && (hi2c->XferCount!=0U)) { /* Wait until TCR flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout) != HAL_OK) + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) { return HAL_TIMEOUT; } - if(Size > MAX_NBYTE_SIZE) + if(hi2c->XferCount > MAX_NBYTE_SIZE) { - I2C_TransferConfig(hi2c,DevAddress,MAX_NBYTE_SIZE, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); - sizetmp = MAX_NBYTE_SIZE; + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); } else { - I2C_TransferConfig(hi2c,DevAddress,Size, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); - sizetmp = Size; + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); } } } /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ /* Wait until STOPF flag is set */ - if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout) != HAL_OK) + if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) { @@ -596,10 +712,10 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA return HAL_TIMEOUT; } } - + /* Clear STOP Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - + /* Clear Configuration Register 2 */ I2C_RESET_CR2(hi2c); @@ -613,7 +729,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA } else { - return HAL_BUSY; + return HAL_BUSY; } } @@ -621,7 +737,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA * @brief Receives in master mode an amount of data in blocking mode. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. - * @param DevAddress Target device address + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shift at right before call interface * @param pData Pointer to data buffer * @param Size Amount of data to be sent * @param Timeout Timeout duration @@ -629,56 +746,47 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA */ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout) { - uint32_t sizetmp = 0; + uint32_t tickstart = 0U; if(hi2c->State == HAL_I2C_STATE_READY) { - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) - { - return HAL_BUSY; - } - /* Process Locked */ __HAL_LOCK(hi2c); + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) + { + return HAL_TIMEOUT; + } + hi2c->State = HAL_I2C_STATE_BUSY_RX; hi2c->Mode = HAL_I2C_MODE_MASTER; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferISR = NULL; + /* Send Slave Address */ - /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */ - /* Size > MAX_NBYTE_SIZE, need to set RELOAD bit */ - if(Size > MAX_NBYTE_SIZE) + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + if(hi2c->XferCount > MAX_NBYTE_SIZE) { - I2C_TransferConfig(hi2c, DevAddress, MAX_NBYTE_SIZE, I2C_RELOAD_MODE, I2C_GENERATE_START_READ); - sizetmp = MAX_NBYTE_SIZE; - } - else if(Size > 0) - { - I2C_TransferConfig(hi2c, DevAddress, Size, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); - sizetmp = Size; + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ); } else { - I2C_TransferConfig(hi2c, DevAddress, Size, I2C_SOFTEND_MODE, I2C_GENERATE_START_READ); - sizetmp = Size; - - /* Wait until TC flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - else - { - /* Generate a Stop command */ - hi2c->Instance->CR2 |= I2C_CR2_STOP; - } + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); } - - while(Size > 0) + + while(hi2c->XferCount > 0U) { /* Wait until RXNE flag is set */ - if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, I2C_FLAG_RXNE) != HAL_OK) + if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) { @@ -689,36 +797,36 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd return HAL_TIMEOUT; } } - - /* Write data to RXDR */ - (*pData++) =hi2c->Instance->RXDR; - sizetmp--; - Size--; - if((sizetmp == 0)&&(Size!=0)) + /* Read data from RXDR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; + hi2c->XferSize--; + hi2c->XferCount--; + + if((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U)) { /* Wait until TCR flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout) != HAL_OK) + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) { return HAL_TIMEOUT; } - if(Size > MAX_NBYTE_SIZE) + if(hi2c->XferCount > MAX_NBYTE_SIZE) { - I2C_TransferConfig(hi2c, DevAddress, MAX_NBYTE_SIZE, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); - sizetmp = MAX_NBYTE_SIZE; + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); } else { - I2C_TransferConfig(hi2c, DevAddress, Size, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); - sizetmp = Size; + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); } } } - + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ /* Wait until STOPF flag is set */ - if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK) + if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) { @@ -729,16 +837,16 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd return HAL_TIMEOUT; } } - + /* Clear STOP Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - + /* Clear Configuration Register 2 */ I2C_RESET_CR2(hi2c); - + hi2c->State = HAL_I2C_STATE_READY; hi2c->Mode = HAL_I2C_MODE_NONE; - + /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -746,7 +854,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd } else { - return HAL_BUSY; + return HAL_BUSY; } } @@ -761,30 +869,40 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd */ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout) { + uint32_t tickstart = 0U; + if(hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } /* Process Locked */ __HAL_LOCK(hi2c); - + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + hi2c->State = HAL_I2C_STATE_BUSY_TX; hi2c->Mode = HAL_I2C_MODE_SLAVE; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferISR = NULL; + /* Enable Address Acknowledge */ hi2c->Instance->CR2 &= ~I2C_CR2_NACK; /* Wait until ADDR flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout) != HAL_OK) + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; return HAL_TIMEOUT; } - + /* Clear ADDR flag */ __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR); @@ -792,29 +910,29 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) { /* Wait until ADDR flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout) != HAL_OK) + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; return HAL_TIMEOUT; } - + /* Clear ADDR flag */ __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR); } /* Wait until DIR flag is set Transmitter mode */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, Timeout) != HAL_OK) + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; return HAL_TIMEOUT; } - while(Size > 0) + while(hi2c->XferCount > 0U) { /* Wait until TXIS flag is set */ - if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout) != HAL_OK) + if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; @@ -829,13 +947,13 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData } } - /* Read data from TXDR */ - hi2c->Instance->TXDR = (*pData++); - Size--; + /* Write data to TXDR */ + hi2c->Instance->TXDR = (*hi2c->pBuffPtr++); + hi2c->XferCount--; } - + /* Wait until STOP flag is set */ - if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK) + if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; @@ -856,27 +974,27 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_STOPF); /* Wait until BUSY flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout) != HAL_OK) + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; return HAL_TIMEOUT; } - + /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; hi2c->State = HAL_I2C_STATE_READY; hi2c->Mode = HAL_I2C_MODE_NONE; - + /* Process Unlocked */ __HAL_UNLOCK(hi2c); - + return HAL_OK; } else { - return HAL_BUSY; + return HAL_BUSY; } } @@ -891,24 +1009,34 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData */ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout) { + uint32_t tickstart = 0U; + if(hi2c->State == HAL_I2C_STATE_READY) - { - if((pData == NULL) || (Size == 0)) + { + if((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } /* Process Locked */ __HAL_LOCK(hi2c); - + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + hi2c->State = HAL_I2C_STATE_BUSY_RX; hi2c->Mode = HAL_I2C_MODE_SLAVE; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferISR = NULL; + /* Enable Address Acknowledge */ hi2c->Instance->CR2 &= ~I2C_CR2_NACK; /* Wait until ADDR flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout) != HAL_OK) + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; @@ -917,30 +1045,31 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, /* Clear ADDR flag */ __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR); - + /* Wait until DIR flag is reset Receiver mode */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, Timeout) != HAL_OK) + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; return HAL_TIMEOUT; } - while(Size > 0) + while(hi2c->XferCount > 0U) { /* Wait until RXNE flag is set */ - if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout) != HAL_OK) + if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; - + /* Store Last receive data if any */ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) { /* Read data from RXDR */ - (*pData++) = hi2c->Instance->RXDR; + (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; + hi2c->XferCount--; } - + if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT) { return HAL_TIMEOUT; @@ -950,14 +1079,14 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, return HAL_ERROR; } } - + /* Read data from RXDR */ - (*pData++) = hi2c->Instance->RXDR; - Size--; + (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; + hi2c->XferCount--; } - + /* Wait until STOP flag is set */ - if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK) + if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; @@ -974,9 +1103,9 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, /* Clear STOP flag */ __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_STOPF); - + /* Wait until BUSY flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout) != HAL_OK) + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; @@ -985,32 +1114,35 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; - + hi2c->State = HAL_I2C_STATE_READY; hi2c->Mode = HAL_I2C_MODE_NONE; /* Process Unlocked */ __HAL_UNLOCK(hi2c); - + return HAL_OK; } else { - return HAL_BUSY; - } + return HAL_BUSY; + } } /** * @brief Transmit in master mode an amount of data in non-blocking mode with Interrupt * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. - * @param DevAddress Target device address + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shift at right before call interface * @param pData Pointer to data buffer * @param Size Amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) -{ +{ + uint32_t xfermode = 0U; + if(hi2c->State == HAL_I2C_STATE_READY) { if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) @@ -1020,33 +1152,32 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t D /* Process Locked */ __HAL_LOCK(hi2c); - + hi2c->State = HAL_I2C_STATE_BUSY_TX; hi2c->Mode = HAL_I2C_MODE_MASTER; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - + + /* Prepare transfer parameters */ hi2c->pBuffPtr = pData; hi2c->XferCount = Size; - if(Size > MAX_NBYTE_SIZE) + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Master_ISR_IT; + + if(hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; } else { - hi2c->XferSize = Size; + hi2c->XferSize = hi2c->XferCount; + xfermode = I2C_AUTOEND_MODE; } - + /* Send Slave Address */ - /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */ - if( (hi2c->XferSize == MAX_NBYTE_SIZE) && (hi2c->XferSize < hi2c->XferCount) ) - { - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); - } - else - { - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE); - } - + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE); + /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -1054,12 +1185,11 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t D to avoid the risk of I2C interrupt handle execution before current process unlock */ - /* Enable ERR, TC, STOP, NACK, TXI interrupt */ /* possible to enable all of these */ /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ - __HAL_I2C_ENABLE_IT(hi2c,I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_TXI ); - + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + return HAL_OK; } else @@ -1072,13 +1202,16 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t D * @brief Receive in master mode an amount of data in non-blocking mode with Interrupt * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. - * @param DevAddress Target device address + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shift at right before call interface * @param pData Pointer to data buffer * @param Size Amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) { + uint32_t xfermode = 0U; + if(hi2c->State == HAL_I2C_STATE_READY) { if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) @@ -1088,51 +1221,50 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t De /* Process Locked */ __HAL_LOCK(hi2c); - + hi2c->State = HAL_I2C_STATE_BUSY_RX; hi2c->Mode = HAL_I2C_MODE_MASTER; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - + + /* Prepare transfer parameters */ hi2c->pBuffPtr = pData; hi2c->XferCount = Size; - if(Size > MAX_NBYTE_SIZE) + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Master_ISR_IT; + + if(hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; } else { - hi2c->XferSize = Size; + hi2c->XferSize = hi2c->XferCount; + xfermode = I2C_AUTOEND_MODE; } - + /* Send Slave Address */ - /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */ - if( (hi2c->XferSize == MAX_NBYTE_SIZE) && (hi2c->XferSize < hi2c->XferCount) ) - { - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ); - } - else - { - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); - } - + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); + /* Process Unlocked */ __HAL_UNLOCK(hi2c); /* Note : The I2C interrupts must be enabled after unlocking current process to avoid the risk of I2C interrupt handle execution before current process unlock */ - + /* Enable ERR, TC, STOP, NACK, RXI interrupt */ /* possible to enable all of these */ /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ - __HAL_I2C_ENABLE_IT(hi2c,I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI ); - + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); + return HAL_OK; } else { return HAL_BUSY; - } + } } /** @@ -1147,13 +1279,9 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pD { if(hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL) || (Size == 0)) - { - return HAL_ERROR; - } /* Process Locked */ __HAL_LOCK(hi2c); - + hi2c->State = HAL_I2C_STATE_BUSY_TX; hi2c->Mode = HAL_I2C_MODE_SLAVE; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; @@ -1161,22 +1289,25 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pD /* Enable Address Acknowledge */ hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + /* Prepare transfer parameters */ hi2c->pBuffPtr = pData; - hi2c->XferSize = Size; hi2c->XferCount = Size; - + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Slave_ISR_IT; + /* Process Unlocked */ __HAL_UNLOCK(hi2c); /* Note : The I2C interrupts must be enabled after unlocking current process to avoid the risk of I2C interrupt handle execution before current process unlock */ - + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ /* possible to enable all of these */ /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ - __HAL_I2C_ENABLE_IT(hi2c,I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_TXI ); - + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT); + return HAL_OK; } else @@ -1197,35 +1328,34 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pDa { if(hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL) || (Size == 0)) - { - return HAL_ERROR; - } /* Process Locked */ __HAL_LOCK(hi2c); - + hi2c->State = HAL_I2C_STATE_BUSY_RX; hi2c->Mode = HAL_I2C_MODE_SLAVE; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - + /* Enable Address Acknowledge */ hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + /* Prepare transfer parameters */ hi2c->pBuffPtr = pData; - hi2c->XferSize = Size; hi2c->XferCount = Size; - + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Slave_ISR_IT; + /* Process Unlocked */ __HAL_UNLOCK(hi2c); /* Note : The I2C interrupts must be enabled after unlocking current process to avoid the risk of I2C interrupt handle execution before current process unlock */ - + /* Enable ERR, TC, STOP, NACK, RXI interrupt */ /* possible to enable all of these */ /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ - __HAL_I2C_ENABLE_IT(hi2c,I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI); + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT); return HAL_OK; } @@ -1239,13 +1369,16 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pDa * @brief Transmit in master mode an amount of data in non-blocking mode with DMA * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. - * @param DevAddress Target device address + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shift at right before call interface * @param pData Pointer to data buffer * @param Size Amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) { + uint32_t xfermode = 0U; + if(hi2c->State == HAL_I2C_STATE_READY) { if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) @@ -1255,97 +1388,83 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t /* Process Locked */ __HAL_LOCK(hi2c); - + hi2c->State = HAL_I2C_STATE_BUSY_TX; hi2c->Mode = HAL_I2C_MODE_MASTER; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - + + /* Prepare transfer parameters */ hi2c->pBuffPtr = pData; hi2c->XferCount = Size; - if(Size > MAX_NBYTE_SIZE) + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Master_ISR_DMA; + + if(hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; } else { - hi2c->XferSize = Size; + hi2c->XferSize = hi2c->XferCount; + xfermode = I2C_AUTOEND_MODE; } - - if(hi2c->XferSize > 0) + + if(hi2c->XferSize > 0U) { /* Set the I2C DMA transfer complete callback */ hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt; - + /* Set the DMA error callback */ hi2c->hdmatx->XferErrorCallback = I2C_DMAError; - + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; + /* Enable the DMA channel */ HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); /* Send Slave Address */ - /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */ - if( (hi2c->XferSize == MAX_NBYTE_SIZE) && (hi2c->XferSize < hi2c->XferCount) ) - { - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); - } - else - { - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE); - } + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE); - /* Wait until TXIS flag is set */ - if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, I2C_TIMEOUT_TXIS) != HAL_OK) - { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; - /* Abort DMA */ - HAL_DMA_Abort(hi2c->hdmatx); + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } - } + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR and NACK interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); /* Enable DMA Request */ - hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; } else - { + { + /* Update Transfer ISR function pointer */ + hi2c->XferISR = I2C_Master_ISR_IT; + + /* Send Slave Address */ + /* Set NBYTES to write and generate START condition */ I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE); - /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ - /* Wait until STOPF flag is set */ - if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK) - { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } - } - - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - /* Clear Configuration Register 2 */ - I2C_RESET_CR2(hi2c); + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); } - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - + return HAL_OK; } else @@ -1358,13 +1477,16 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t * @brief Receive in master mode an amount of data in non-blocking mode with DMA * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. - * @param DevAddress Target device address + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shift at right before call interface * @param pData Pointer to data buffer * @param Size Amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) { + uint32_t xfermode = 0U; + if(hi2c->State == HAL_I2C_STATE_READY) { if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) @@ -1378,81 +1500,78 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D hi2c->State = HAL_I2C_STATE_BUSY_RX; hi2c->Mode = HAL_I2C_MODE_MASTER; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - + + /* Prepare transfer parameters */ hi2c->pBuffPtr = pData; hi2c->XferCount = Size; - if(Size > MAX_NBYTE_SIZE) + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Master_ISR_DMA; + + if(hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; } else { - hi2c->XferSize = Size; + hi2c->XferSize = hi2c->XferCount; + xfermode = I2C_AUTOEND_MODE; } - - if(hi2c->XferSize > 0) + + if(hi2c->XferSize > 0U) { /* Set the I2C DMA transfer complete callback */ hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt; - + /* Set the DMA error callback */ hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + /* Enable the DMA channel */ HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize); /* Send Slave Address */ - /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */ - if( (hi2c->XferSize == MAX_NBYTE_SIZE) && (hi2c->XferSize < hi2c->XferCount) ) - { - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ); - } - else - { - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); - } + /* Set NBYTES to read and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); - /* Wait until RXNE flag is set */ - if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, I2C_FLAG_RXNE) != HAL_OK) - { - /* Abort DMA */ - HAL_DMA_Abort(hi2c->hdmarx); + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR and NACK interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } - } - /* Enable DMA Request */ - hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; } else { - I2C_TransferConfig(hi2c, DevAddress, Size, I2C_SOFTEND_MODE, I2C_GENERATE_START_READ); + /* Update Transfer ISR function pointer */ + hi2c->XferISR = I2C_Master_ISR_IT; - /* Wait until TC flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, I2C_TIMEOUT_TC) != HAL_OK) - { - return HAL_TIMEOUT; - } - else - { - /* Generate a Stop command */ - hi2c->Instance->CR2 |= I2C_CR2_STOP; - } + /* Send Slave Address */ + /* Set NBYTES to read and generate START condition */ + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); } - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_OK; } else @@ -1473,7 +1592,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *p { if(hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -1484,62 +1603,41 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *p hi2c->Mode = HAL_I2C_MODE_SLAVE; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferSize = Size; - + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Slave_ISR_DMA; + /* Set the I2C DMA transfer complete callback */ hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt; - + /* Set the DMA error callback */ hi2c->hdmatx->XferErrorCallback = I2C_DMAError; - + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; + /* Enable the DMA channel */ HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); - + /* Enable Address Acknowledge */ hi2c->Instance->CR2 &= ~I2C_CR2_NACK; - /* Wait until ADDR flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, I2C_TIMEOUT_ADDR) != HAL_OK) - { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - return HAL_TIMEOUT; - } - - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR); - - /* If 10bits addressing mode is selected */ - if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) - { - /* Wait until ADDR flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, I2C_TIMEOUT_ADDR) != HAL_OK) - { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - return HAL_TIMEOUT; - } - - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR); - } - - /* Wait until DIR flag is set Transmitter mode */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, I2C_TIMEOUT_BUSY) != HAL_OK) - { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - return HAL_TIMEOUT; - } - - /* Enable DMA Request */ - hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; - /* Process Unlocked */ __HAL_UNLOCK(hi2c); - + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, STOP, NACK, ADDR interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + return HAL_OK; } else @@ -1560,7 +1658,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pD { if(hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -1571,47 +1669,41 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pD hi2c->Mode = HAL_I2C_MODE_SLAVE; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - hi2c->pBuffPtr = pData; - hi2c->XferSize = Size; - hi2c->XferCount = Size; - + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Slave_ISR_DMA; + /* Set the I2C DMA transfer complete callback */ hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt; - + /* Set the DMA error callback */ hi2c->hdmarx->XferErrorCallback = I2C_DMAError; - + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + /* Enable the DMA channel */ - HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, Size); - + HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize); + /* Enable Address Acknowledge */ hi2c->Instance->CR2 &= ~I2C_CR2_NACK; - /* Wait until ADDR flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, I2C_TIMEOUT_ADDR) != HAL_OK) - { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - return HAL_TIMEOUT; - } - - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR); - - /* Wait until DIR flag is set Receiver mode */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, I2C_TIMEOUT_DIR) != HAL_OK) - { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - return HAL_TIMEOUT; - } - - /* Enable DMA Request */ - hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; - /* Process Unlocked */ __HAL_UNLOCK(hi2c); - + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, STOP, NACK, ADDR interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + return HAL_OK; } else @@ -1623,7 +1715,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pD * @brief Write an amount of data in blocking mode to a specific memory address * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. - * @param DevAddress Target device address + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shift at right before call interface * @param MemAddress Internal memory address * @param MemAddSize Size of internal memory address * @param pData Pointer to data buffer @@ -1633,32 +1726,40 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pD */ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) { - uint32_t Sizetmp = 0; + uint32_t tickstart = 0U; /* Check the parameters */ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); if(hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0U)) { - return HAL_ERROR; - } - - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) - { - return HAL_BUSY; + return HAL_ERROR; } /* Process Locked */ __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY_TX; - hi2c->Mode = HAL_I2C_MODE_MEM; + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) + { + return HAL_TIMEOUT; + } + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MEM; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferISR = NULL; + /* Send Slave Address and Memory Address */ - if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout) != HAL_OK) + if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) { if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) { @@ -1674,23 +1775,22 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress } } - /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE */ - /* Size > MAX_NBYTE_SIZE, need to set RELOAD bit */ - if(Size > MAX_NBYTE_SIZE) + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ + if(hi2c->XferCount > MAX_NBYTE_SIZE) { - I2C_TransferConfig(hi2c, DevAddress, MAX_NBYTE_SIZE, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); - Sizetmp = MAX_NBYTE_SIZE; + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); } else { - I2C_TransferConfig(hi2c, DevAddress, Size, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); - Sizetmp = Size; + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); } - + do { /* Wait until TXIS flag is set */ - if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout) != HAL_OK) + if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) { @@ -1701,38 +1801,37 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress return HAL_TIMEOUT; } } - - /* Write data to DR */ - hi2c->Instance->TXDR = (*pData++); - Sizetmp--; - Size--; - if((Sizetmp == 0)&&(Size!=0)) + /* Write data to TXDR */ + hi2c->Instance->TXDR = (*hi2c->pBuffPtr++); + hi2c->XferCount--; + hi2c->XferSize--; + + if((hi2c->XferSize == 0U) && (hi2c->XferCount!=0U)) { /* Wait until TCR flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout) != HAL_OK) + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) { return HAL_TIMEOUT; } - - if(Size > MAX_NBYTE_SIZE) + if(hi2c->XferCount > MAX_NBYTE_SIZE) { - I2C_TransferConfig(hi2c, DevAddress, MAX_NBYTE_SIZE, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); - Sizetmp = MAX_NBYTE_SIZE; + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); } else { - I2C_TransferConfig(hi2c, DevAddress, Size, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); - Sizetmp = Size; + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); } } - - }while(Size > 0); - + + }while(hi2c->XferCount > 0U); + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ /* Wait until STOPF flag is reset */ - if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK) + if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) { @@ -1743,19 +1842,19 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress return HAL_TIMEOUT; } } - + /* Clear STOP Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); /* Clear Configuration Register 2 */ I2C_RESET_CR2(hi2c); - hi2c->State = HAL_I2C_STATE_READY; + hi2c->State = HAL_I2C_STATE_READY; hi2c->Mode = HAL_I2C_MODE_NONE; - + /* Process Unlocked */ __HAL_UNLOCK(hi2c); - + return HAL_OK; } else @@ -1768,7 +1867,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress * @brief Read an amount of data in blocking mode from a specific memory address * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. - * @param DevAddress Target device address + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shift at right before call interface * @param MemAddress Internal memory address * @param MemAddSize Size of internal memory address * @param pData Pointer to data buffer @@ -1778,32 +1878,40 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress */ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) { - uint32_t Sizetmp = 0; + uint32_t tickstart = 0U; /* Check the parameters */ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); - - if(hi2c->State == HAL_I2C_STATE_READY) - { - if((pData == NULL) || (Size == 0)) - { - return HAL_ERROR; - } - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + if(hi2c->State == HAL_I2C_STATE_READY) + { + if((pData == NULL) || (Size == 0U)) { - return HAL_BUSY; + return HAL_ERROR; } /* Process Locked */ __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY_RX; - hi2c->Mode = HAL_I2C_MODE_MEM; + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) + { + return HAL_TIMEOUT; + } + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MEM; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferISR = NULL; + /* Send Slave Address and Memory Address */ - if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout) != HAL_OK) + if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) { if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) { @@ -1820,59 +1928,55 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, } /* Send Slave Address */ - /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */ - /* Size > MAX_NBYTE_SIZE, need to set RELOAD bit */ - if(Size > MAX_NBYTE_SIZE) + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + if(hi2c->XferCount > MAX_NBYTE_SIZE) { - I2C_TransferConfig(hi2c, DevAddress, MAX_NBYTE_SIZE, I2C_RELOAD_MODE, I2C_GENERATE_START_READ); - Sizetmp = MAX_NBYTE_SIZE; + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ); } else { - I2C_TransferConfig(hi2c, DevAddress, Size, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); - Sizetmp = Size; + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); } - + do - { + { /* Wait until RXNE flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout) != HAL_OK) + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK) { return HAL_TIMEOUT; } - + /* Read data from RXDR */ - (*pData++) = hi2c->Instance->RXDR; + (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; + hi2c->XferSize--; + hi2c->XferCount--; - /* Decrement the Size counter */ - Sizetmp--; - Size--; - - if((Sizetmp == 0)&&(Size!=0)) + if((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U)) { /* Wait until TCR flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout) != HAL_OK) + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) { return HAL_TIMEOUT; } - - if(Size > MAX_NBYTE_SIZE) + + if(hi2c->XferCount > MAX_NBYTE_SIZE) { - I2C_TransferConfig(hi2c, DevAddress, MAX_NBYTE_SIZE, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); - Sizetmp = MAX_NBYTE_SIZE; + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); } else { - I2C_TransferConfig(hi2c, DevAddress, Size, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); - Sizetmp = Size; + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); } } - - }while(Size > 0); + }while(hi2c->XferCount > 0U); /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ /* Wait until STOPF flag is reset */ - if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK) + if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) { @@ -1886,16 +1990,16 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, /* Clear STOP Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - + /* Clear Configuration Register 2 */ I2C_RESET_CR2(hi2c); - + hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - + hi2c->Mode = HAL_I2C_MODE_NONE; + /* Process Unlocked */ __HAL_UNLOCK(hi2c); - + return HAL_OK; } else @@ -1907,7 +2011,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, * @brief Write an amount of data in non-blocking mode with Interrupt to a specific memory address * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. - * @param DevAddress Target device address + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shift at right before call interface * @param MemAddress Internal memory address * @param MemAddSize Size of internal memory address * @param pData Pointer to data buffer @@ -1916,14 +2021,17 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, */ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) { + uint32_t tickstart = 0U; + uint32_t xfermode = 0U; + /* Check the parameters */ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); - + if(hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0U)) { - return HAL_ERROR; + return HAL_ERROR; } if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) @@ -1933,24 +2041,33 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr /* Process Locked */ __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Master_ISR_IT; - hi2c->State = HAL_I2C_STATE_BUSY_TX; - hi2c->Mode = HAL_I2C_MODE_MEM; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - if(Size > MAX_NBYTE_SIZE) + if(hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; } else { - hi2c->XferSize = Size; + hi2c->XferSize = hi2c->XferCount; + xfermode = I2C_AUTOEND_MODE; } - + /* Send Slave Address and Memory Address */ - if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG) != HAL_OK) + if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) { if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) { @@ -1966,16 +2083,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr } } - /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE */ - /* Size > MAX_NBYTE_SIZE, need to set RELOAD bit */ - if( (hi2c->XferSize == MAX_NBYTE_SIZE) && (hi2c->XferSize < hi2c->XferCount) ) - { - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); - } - else - { - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); - } + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c,DevAddress, hi2c->XferSize, xfermode, I2C_NO_STARTSTOP); /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -1983,12 +2092,12 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr /* Note : The I2C interrupts must be enabled after unlocking current process to avoid the risk of I2C interrupt handle execution before current process unlock */ - + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ /* possible to enable all of these */ /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ - __HAL_I2C_ENABLE_IT(hi2c,I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_TXI ); - + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + return HAL_OK; } else @@ -2001,7 +2110,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr * @brief Read an amount of data in non-blocking mode with Interrupt from a specific memory address * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. - * @param DevAddress Target device address + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shift at right before call interface * @param MemAddress Internal memory address * @param MemAddSize Size of internal memory address * @param pData Pointer to data buffer @@ -2010,14 +2120,17 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr */ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) { + uint32_t tickstart = 0U; + uint32_t xfermode = 0U; + /* Check the parameters */ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); - + if(hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0U)) { - return HAL_ERROR; + return HAL_ERROR; } if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) @@ -2027,23 +2140,33 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre /* Process Locked */ __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Master_ISR_IT; - hi2c->State = HAL_I2C_STATE_BUSY_RX; - hi2c->Mode = HAL_I2C_MODE_MEM; - - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - if(Size > MAX_NBYTE_SIZE) + if(hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; } else { - hi2c->XferSize = Size; + hi2c->XferSize = hi2c->XferCount; + xfermode = I2C_AUTOEND_MODE; } - + /* Send Slave Address and Memory Address */ - if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG) != HAL_OK) + if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) { if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) { @@ -2058,42 +2181,35 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre return HAL_TIMEOUT; } } - - /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */ - /* Size > MAX_NBYTE_SIZE, need to set RELOAD bit */ - if( (hi2c->XferSize == MAX_NBYTE_SIZE) && (hi2c->XferSize < hi2c->XferCount) ) - { - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ); - } - else - { - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); - } + + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); /* Process Unlocked */ - __HAL_UNLOCK(hi2c); + __HAL_UNLOCK(hi2c); - /* Note : The I2C interrupts must be enabled after unlocking current process + /* Note : The I2C interrupts must be enabled after unlocking current process to avoid the risk of I2C interrupt handle execution before current process unlock */ - + /* Enable ERR, TC, STOP, NACK, RXI interrupt */ /* possible to enable all of these */ /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ - __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_RXI ); - + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); + return HAL_OK; } else { - return HAL_BUSY; - } + return HAL_BUSY; + } } /** * @brief Write an amount of data in non-blocking mode with DMA to a specific memory address * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. - * @param DevAddress Target device address + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shift at right before call interface * @param MemAddress Internal memory address * @param MemAddSize Size of internal memory address * @param pData Pointer to data buffer @@ -2102,16 +2218,19 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre */ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) { + uint32_t tickstart = 0U; + uint32_t xfermode = 0U; + /* Check the parameters */ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); - + if(hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0U)) { - return HAL_ERROR; + return HAL_ERROR; } - + if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) { return HAL_BUSY; @@ -2119,33 +2238,33 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd /* Process Locked */ __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Master_ISR_DMA; - hi2c->State = HAL_I2C_STATE_BUSY_TX; - hi2c->Mode = HAL_I2C_MODE_MEM; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - if(Size > MAX_NBYTE_SIZE) + if(hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; } else { - hi2c->XferSize = Size; + hi2c->XferSize = hi2c->XferCount; + xfermode = I2C_AUTOEND_MODE; } - - /* Set the I2C DMA transfer complete callback */ - hi2c->hdmatx->XferCpltCallback = I2C_DMAMemTransmitCplt; - - /* Set the DMA error callback */ - hi2c->hdmatx->XferErrorCallback = I2C_DMAError; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); - + /* Send Slave Address and Memory Address */ - if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG) != HAL_OK) + if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) { if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) { @@ -2160,37 +2279,39 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd return HAL_TIMEOUT; } } - - /* Send Slave Address */ - /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE */ - if( (hi2c->XferSize == MAX_NBYTE_SIZE) && (hi2c->XferSize < hi2c->XferCount) ) - { - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); - } - else - { - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); - } - - /* Wait until TXIS flag is set */ - if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, I2C_TIMEOUT_TXIS) != HAL_OK) - { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } - } - /* Enable DMA Request */ - hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; - + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt; + + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); + + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_NO_STARTSTOP); + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + /* Process Unlocked */ __HAL_UNLOCK(hi2c); - + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR and NACK interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + return HAL_OK; } else @@ -2203,7 +2324,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd * @brief Reads an amount of data in non-blocking mode with DMA from a specific memory address. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. - * @param DevAddress Target device address + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shift at right before call interface * @param MemAddress Internal memory address * @param MemAddSize Size of internal memory address * @param pData Pointer to data buffer @@ -2212,14 +2334,17 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd */ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) { + uint32_t tickstart = 0U; + uint32_t xfermode = 0U; + /* Check the parameters */ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); - + if(hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0U)) { - return HAL_ERROR; + return HAL_ERROR; } if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) @@ -2229,32 +2354,33 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr /* Process Locked */ __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY_RX; - hi2c->Mode = HAL_I2C_MODE_MEM; - - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - if(Size > MAX_NBYTE_SIZE) + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Master_ISR_DMA; + + if(hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; } else { - hi2c->XferSize = Size; + hi2c->XferSize = hi2c->XferCount; + xfermode = I2C_AUTOEND_MODE; } - /* Set the I2C DMA transfer complete callback */ - hi2c->hdmarx->XferCpltCallback = I2C_DMAMemReceiveCplt; - - /* Set the DMA error callback */ - hi2c->hdmarx->XferErrorCallback = I2C_DMAError; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize); - /* Send Slave Address and Memory Address */ - if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG) != HAL_OK) + if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) { if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) { @@ -2269,29 +2395,38 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr return HAL_TIMEOUT; } } - - /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */ - if( (hi2c->XferSize == MAX_NBYTE_SIZE) && (hi2c->XferSize < hi2c->XferCount) ) - { - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ); - } - else - { - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); - } - /* Wait until RXNE flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, I2C_TIMEOUT_RXNE) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* Enable DMA Request */ - hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; - + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt; + + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize); + + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c,DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + /* Process Unlocked */ __HAL_UNLOCK(hi2c); - + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR and NACK interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + return HAL_OK; } else @@ -2305,16 +2440,17 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr * @note This function is used with Memory devices * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. - * @param DevAddress Target device address + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shift at right before call interface * @param Trials Number of trials * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout) -{ - uint32_t tickstart = 0; +{ + uint32_t tickstart = 0U; - __IO uint32_t I2C_Trials = 0; + __IO uint32_t I2C_Trials = 0U; if(hi2c->State == HAL_I2C_STATE_READY) { @@ -2325,15 +2461,15 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd /* Process Locked */ __HAL_LOCK(hi2c); - + hi2c->State = HAL_I2C_STATE_BUSY; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - + do { /* Generate Start */ hi2c->Instance->CR2 = I2C_GENERATE_START(hi2c->Init.AddressingMode,DevAddress); - + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ /* Wait until STOPF flag is set or a NACK flag is set*/ tickstart = HAL_GetTick(); @@ -2341,7 +2477,7 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd { if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout)) + if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) { /* Device is ready */ hi2c->State = HAL_I2C_STATE_READY; @@ -2351,31 +2487,31 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd } } } - + /* Check if the NACKF flag has not been set */ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET) { /* Wait until STOPF flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout) != HAL_OK) + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) { return HAL_TIMEOUT; } - + /* Clear STOP Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); /* Device is ready */ hi2c->State = HAL_I2C_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(hi2c); - + return HAL_OK; } else { - /* Wait until STOPF flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout) != HAL_OK) + /* Wait until STOPF flag is reset */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) { return HAL_TIMEOUT; } @@ -2386,29 +2522,29 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd /* Clear STOP Flag, auto generated with autoend*/ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); } - + /* Check if the maximum allowed number of trials has been reached */ if (I2C_Trials++ == Trials) { /* Generate Stop */ hi2c->Instance->CR2 |= I2C_CR2_STOP; - + /* Wait until STOPF flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout) != HAL_OK) + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) { return HAL_TIMEOUT; } - + /* Clear STOP Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - } + } }while(I2C_Trials < Trials); hi2c->State = HAL_I2C_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hi2c); - + return HAL_TIMEOUT; } else @@ -2416,6 +2552,385 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd return HAL_BUSY; } } + +/** + * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt. + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shift at right before call interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +{ + uint32_t xfermode = 0U; + uint32_t xferrequest = I2C_GENERATE_START_WRITE; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if(hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Master_ISR_IT; + + /* If size > MAX_NBYTE_SIZE, use reload mode */ + if(hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = hi2c->XferOptions; + + /* If transfer direction not change, do not generate Restart Condition */ + /* Mean Previous state is same as current state */ + if(hi2c->PreviousState == I2C_STATE_SLAVE_BUSY_TX) + { + xferrequest = I2C_NO_STARTSTOP; + } + } + + + /* Send Slave Address and set NBYTES to write */ + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, xferrequest); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shift at right before call interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +{ + uint32_t xfermode = 0U; + uint32_t xferrequest = I2C_GENERATE_START_READ; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if(hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Master_ISR_IT; + + /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */ + if(hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = hi2c->XferOptions; + + /* If transfer direction not change, do not generate Restart Condition */ + /* Mean Previous state is same as current state */ + if(hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) + { + xferrequest = I2C_NO_STARTSTOP; + } + } + + /* Send Slave Address and set NBYTES to read */ + I2C_TransferConfig(hi2c,DevAddress, hi2c->XferSize, xfermode, xferrequest); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with Interrupt + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +{ + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if(hi2c->State == HAL_I2C_STATE_LISTEN) + { + if((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Slave_ISR_IT; + + if(I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) + { + /* Clear ADDR flag after prepare the transfer parameters */ + /* This action will generate an acknowledge to the Master */ + __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* REnable ADDR interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT); + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with Interrupt + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +{ + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if(hi2c->State == HAL_I2C_STATE_LISTEN) + { + if((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Slave_ISR_IT; + + if(I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) + { + /* Clear ADDR flag after prepare the transfer parameters */ + /* This action will generate an acknowledge to the Master */ + __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* REnable ADDR interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT); + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Enable the Address listen mode with Interrupt. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c) +{ + if(hi2c->State == HAL_I2C_STATE_READY) + { + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->XferISR = I2C_Slave_ISR_IT; + + /* Enable the Address Match interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Disable the Address listen mode with Interrupt. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c) +{ + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + uint32_t tmp; + + /* Disable Address listen mode only if a transfer is not ongoing */ + if(hi2c->State == HAL_I2C_STATE_LISTEN) + { + tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK; + hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode); + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->XferISR = NULL; + + /* Disable the Address Match interrupt */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Abort a master I2C IT or DMA process communication with Interrupt. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shift at right before call interface + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress) +{ + if(hi2c->Mode == HAL_I2C_MODE_MASTER) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Disable Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + + /* Set State at HAL_I2C_STATE_ABORT */ + hi2c->State = HAL_I2C_STATE_ABORT; + + /* Set NBYTES to 1 to generate a dummy read on I2C peripheral */ + /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */ + I2C_TransferConfig(hi2c, DevAddress, 1, I2C_AUTOEND_MODE, I2C_GENERATE_STOP); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); + + return HAL_OK; + } + else + { + /* Wrong usage of abort function */ + /* This function should be used only in case of abort monitored by master device */ + return HAL_ERROR; + } +} + /** * @} */ @@ -2432,44 +2947,17 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd */ void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c) { - /* I2C in mode Transmitter ---------------------------------------------------*/ - if (((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TCR) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TC) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR) == SET)) && (__HAL_I2C_GET_IT_SOURCE(hi2c, (I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI | I2C_IT_ADDRI)) == SET)) - { - /* Slave mode selected */ - if (hi2c->Mode == HAL_I2C_MODE_SLAVE) - { - I2C_SlaveTransmit_ISR(hi2c); - } - } - - if (((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TCR) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TC) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)) && (__HAL_I2C_GET_IT_SOURCE(hi2c, (I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI)) == SET)) - { - /* Master or Memory mode selected */ - if ((hi2c->Mode == HAL_I2C_MODE_MASTER) || (hi2c->Mode == HAL_I2C_MODE_MEM)) - { - I2C_MasterTransmit_ISR(hi2c); - } - } - - /* I2C in mode Receiver ----------------------------------------------------*/ - if (((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TCR) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TC) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR) == SET)) && (__HAL_I2C_GET_IT_SOURCE(hi2c, (I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_RXI | I2C_IT_ADDRI)) == SET)) + /* Get current IT Flags and IT sources value */ + uint32_t itflags = READ_REG(hi2c->Instance->ISR); + uint32_t itsources = READ_REG(hi2c->Instance->CR1); + + /* I2C events treatment -------------------------------------*/ + if(hi2c->XferISR != NULL) { - /* Slave mode selected */ - if (hi2c->Mode == HAL_I2C_MODE_SLAVE) - { - I2C_SlaveReceive_ISR(hi2c); - } - } - if (((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TCR) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TC) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)) && (__HAL_I2C_GET_IT_SOURCE(hi2c, (I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_RXI)) == SET)) - { - /* Master or Memory mode selected */ - if ((hi2c->Mode == HAL_I2C_MODE_MASTER) || (hi2c->Mode == HAL_I2C_MODE_MEM)) - { - I2C_MasterReceive_ISR(hi2c); - } - } + hi2c->XferISR(hi2c, itflags, itsources); + } } - + /** * @brief This function handles I2C error interrupt request. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains @@ -2478,18 +2966,21 @@ void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c) */ void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) { + uint32_t itflags = READ_REG(hi2c->Instance->ISR); + uint32_t itsources = READ_REG(hi2c->Instance->CR1); + /* I2C Bus error interrupt occurred ------------------------------------*/ - if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BERR) == SET) && (__HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_ERRI) == SET)) - { + if(((itflags & I2C_FLAG_BERR) != RESET) && ((itsources & I2C_IT_ERRI) != RESET)) + { hi2c->ErrorCode |= HAL_I2C_ERROR_BERR; - + /* Clear BERR flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR); } - + /* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/ - if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_OVR) == SET) && (__HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_ERRI) == SET)) - { + if(((itflags & I2C_FLAG_OVR) != RESET) && ((itsources & I2C_IT_ERRI) != RESET)) + { hi2c->ErrorCode |= HAL_I2C_ERROR_OVR; /* Clear OVR flag */ @@ -2497,8 +2988,8 @@ void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) } /* I2C Arbitration Loss error interrupt occurred -------------------------------------*/ - if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ARLO) == SET) && (__HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_ERRI) == SET)) - { + if(((itflags & I2C_FLAG_ARLO) != RESET) && ((itsources & I2C_IT_ERRI) != RESET)) + { hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO; /* Clear ARLO flag */ @@ -2508,9 +2999,7 @@ void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) /* Call the Error Callback in case of Error detected */ if((hi2c->ErrorCode & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) != HAL_I2C_ERROR_NONE) { - hi2c->State = HAL_I2C_STATE_READY; - - HAL_I2C_ErrorCallback(hi2c); + I2C_ITError(hi2c, hi2c->ErrorCode); } } @@ -2526,7 +3015,7 @@ void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) UNUSED(hi2c); /* NOTE : This function should not be modified, when the callback is needed, - the HAL_I2C_TxCpltCallback could be implemented in the user file + the HAL_I2C_MasterTxCpltCallback could be implemented in the user file */ } @@ -2542,7 +3031,7 @@ __weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c) UNUSED(hi2c); /* NOTE : This function should not be modified, when the callback is needed, - the HAL_I2C_TxCpltCallback could be implemented in the user file + the HAL_I2C_MasterRxCpltCallback could be implemented in the user file */ } @@ -2557,7 +3046,7 @@ __weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c) UNUSED(hi2c); /* NOTE : This function should not be modified, when the callback is needed, - the HAL_I2C_TxCpltCallback could be implemented in the user file + the HAL_I2C_SlaveTxCpltCallback could be implemented in the user file */ } @@ -2573,7 +3062,43 @@ __weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c) UNUSED(hi2c); /* NOTE : This function should not be modified, when the callback is needed, - the HAL_I2C_TxCpltCallback could be implemented in the user file + the HAL_I2C_SlaveRxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Slave Address Match callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param TransferDirection: Master request Transfer Direction (Write/Read), value of @ref I2C_XFERDIRECTION + * @param AddrMatchCode: Address Match Code + * @retval None + */ +__weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + UNUSED(TransferDirection); + UNUSED(AddrMatchCode); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_AddrCallback() could be implemented in the user file + */ +} + +/** + * @brief Listen Complete callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_ListenCpltCallback() could be implemented in the user file */ } @@ -2589,7 +3114,7 @@ __weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c) UNUSED(hi2c); /* NOTE : This function should not be modified, when the callback is needed, - the HAL_I2C_TxCpltCallback could be implemented in the user file + the HAL_I2C_MemTxCpltCallback could be implemented in the user file */ } @@ -2605,7 +3130,7 @@ __weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c) UNUSED(hi2c); /* NOTE : This function should not be modified, when the callback is needed, - the HAL_I2C_TxCpltCallback could be implemented in the user file + the HAL_I2C_MemRxCpltCallback could be implemented in the user file */ } @@ -2625,6 +3150,22 @@ __weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c) */ } +/** + * @brief I2C abort callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_AbortCpltCallback could be implemented in the user file + */ +} + /** * @} */ @@ -2691,447 +3232,397 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c) */ /** - * @brief Handle Interrupt Flags Master Transmit Mode + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with Interrupt. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. + * @param ITFlags Interrupt flags to handle. + * @param ITSources Interrupt sources enabled. * @retval HAL status */ -static HAL_StatusTypeDef I2C_MasterTransmit_ISR(I2C_HandleTypeDef *hi2c) +static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) { - uint16_t DevAddress; - + uint16_t devaddress = 0U; + /* Process Locked */ - __HAL_LOCK(hi2c); - - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == SET) + __HAL_LOCK(hi2c); + + if(((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET)) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set corresponding Error Code */ + /* No need to generate STOP, it is automatically done */ + /* Error callback will be send during stop flag treatment */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + } + else if(((ITFlags & I2C_FLAG_RXNE) != RESET) && ((ITSources & I2C_IT_RXI) != RESET)) + { + /* Read data from RXDR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; + hi2c->XferSize--; + hi2c->XferCount--; + } + else if(((ITFlags & I2C_FLAG_TXIS) != RESET) && ((ITSources & I2C_IT_TXI) != RESET)) { /* Write data to TXDR */ hi2c->Instance->TXDR = (*hi2c->pBuffPtr++); hi2c->XferSize--; hi2c->XferCount--; } - else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TCR) == SET) + else if(((ITFlags & I2C_FLAG_TCR) != RESET) && ((ITSources & I2C_IT_TCI) != RESET)) { - if((hi2c->XferSize == 0)&&(hi2c->XferCount!=0)) + if((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U)) { - DevAddress = (hi2c->Instance->CR2 & I2C_CR2_SADD); + devaddress = (hi2c->Instance->CR2 & I2C_CR2_SADD); if(hi2c->XferCount > MAX_NBYTE_SIZE) - { - I2C_TransferConfig(hi2c, DevAddress, MAX_NBYTE_SIZE, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + { hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); } else { - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferCount, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); hi2c->XferSize = hi2c->XferCount; + if(hi2c->XferOptions != I2C_NO_OPTION_FRAME) + { + I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, hi2c->XferOptions, I2C_NO_STARTSTOP); + } + else + { + I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + } } } else { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Wrong size Status regarding TCR flag event */ - hi2c->ErrorCode |= HAL_I2C_ERROR_SIZE; - HAL_I2C_ErrorCallback(hi2c); - } - } - else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TC) == SET) - { - if(hi2c->XferCount == 0) - { - /* Generate Stop */ - hi2c->Instance->CR2 |= I2C_CR2_STOP; - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Wrong size Status regarding TCR flag event */ - hi2c->ErrorCode |= HAL_I2C_ERROR_SIZE; - HAL_I2C_ErrorCallback(hi2c); - } - } - else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) - { - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) - { - /* Clear NACK Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - } - - /* Disable ERR, TC, STOP, NACK, TXI interrupts */ - __HAL_I2C_DISABLE_IT(hi2c,I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_TXI ); - - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - /* Clear Configuration Register 2 */ - I2C_RESET_CR2(hi2c); - - /* Flush TX register if not empty */ - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET) - { - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE); - } - - /* Call the correct callback to inform upper layer */ - if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) - { - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - HAL_I2C_ErrorCallback(hi2c); - } - else - { - if (hi2c->Mode == HAL_I2C_MODE_MEM) + /* Call TxCpltCallback() if no stop mode is set */ + if(I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) { - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - HAL_I2C_MemTxCpltCallback(hi2c); + /* Call I2C Master Sequential complete process */ + I2C_ITMasterSequentialCplt(hi2c); } else { - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - HAL_I2C_MasterTxCpltCallback(hi2c); + /* Wrong size Status regarding TCR flag event */ + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); } } } - else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) + else if(((ITFlags & I2C_FLAG_TC) != RESET) && ((ITSources & I2C_IT_TCI) != RESET)) { - /* Clear NACK Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - HAL_I2C_ErrorCallback(hi2c); + if(hi2c->XferCount == 0U) + { + if(I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) + { + /* Generate a stop condition in case of no transfer option */ + if(hi2c->XferOptions == I2C_NO_OPTION_FRAME) + { + /* Generate Stop */ + hi2c->Instance->CR2 |= I2C_CR2_STOP; + } + else + { + /* Call I2C Master Sequential complete process */ + I2C_ITMasterSequentialCplt(hi2c); + } + } + } + else + { + /* Wrong size Status regarding TC flag event */ + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); + } } - + + if(((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET)) + { + /* Call I2C Master complete process */ + I2C_ITMasterCplt(hi2c, ITFlags); + } + /* Process Unlocked */ __HAL_UNLOCK(hi2c); - - return HAL_OK; -} + + return HAL_OK; +} /** - * @brief Handle Interrupt Flags Master Receive Mode + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. + * @param ITFlags Interrupt flags to handle. + * @param ITSources Interrupt sources enabled. * @retval HAL status */ -static HAL_StatusTypeDef I2C_MasterReceive_ISR(I2C_HandleTypeDef *hi2c) -{ - uint16_t DevAddress; - - /* Process Locked */ - __HAL_LOCK(hi2c); - - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) - { - /* Read data from RXDR */ - (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; - hi2c->XferSize--; - hi2c->XferCount--; - } - else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TCR) == SET) - { - if((hi2c->XferSize == 0)&&(hi2c->XferCount!=0)) - { - DevAddress = (hi2c->Instance->CR2 & I2C_CR2_SADD); - - if(hi2c->XferCount > MAX_NBYTE_SIZE) - { - I2C_TransferConfig(hi2c, DevAddress, MAX_NBYTE_SIZE, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); - hi2c->XferSize = MAX_NBYTE_SIZE; - } - else - { - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferCount, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); - hi2c->XferSize = hi2c->XferCount; - } - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Wrong size Status regarding TCR flag event */ - hi2c->ErrorCode |= HAL_I2C_ERROR_SIZE; - HAL_I2C_ErrorCallback(hi2c); - } - } - else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TC) == SET) - { - if(hi2c->XferCount == 0) - { - /* Generate Stop */ - hi2c->Instance->CR2 |= I2C_CR2_STOP; - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Wrong size Status regarding TCR flag event */ - hi2c->ErrorCode |= HAL_I2C_ERROR_SIZE; - HAL_I2C_ErrorCallback(hi2c); - } - } - else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) - { - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) - { - /* Clear NACK Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - } - - /* Disable ERR, TC, STOP, NACK, RXI interrupts */ - __HAL_I2C_DISABLE_IT(hi2c,I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_RXI ); - - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - /* Clear Configuration Register 2 */ - I2C_RESET_CR2(hi2c); - - /* Call the correct callback to inform upper layer */ - if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) - { - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - HAL_I2C_ErrorCallback(hi2c); - } - else - { - if (hi2c->Mode == HAL_I2C_MODE_MEM) - { - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - HAL_I2C_MemRxCpltCallback(hi2c); - } - else - { - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - HAL_I2C_MasterRxCpltCallback(hi2c); - } - } - } - else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) - { - /* Clear NACK Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - HAL_I2C_ErrorCallback(hi2c); - } - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; - -} - -/** - * @brief Handle Interrupt Flags Slave Transmit Mode - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_SlaveTransmit_ISR(I2C_HandleTypeDef *hi2c) +static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) { /* Process locked */ __HAL_LOCK(hi2c); - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) != RESET) + if(((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET)) { /* Check that I2C transfer finished */ - /* if yes, normal usecase, a NACK is sent by the MASTER when Transfer is finished */ + /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ /* Mean XferCount == 0*/ /* So clear Flag NACKF only */ - if(hi2c->XferCount == 0) + if(hi2c->XferCount == 0U) { - /* Clear NACK Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + if(((hi2c->XferOptions == I2C_FIRST_AND_LAST_FRAME) || (hi2c->XferOptions == I2C_LAST_FRAME)) && \ + (hi2c->State == HAL_I2C_STATE_LISTEN)) + { + /* Call I2C Listen complete process */ + I2C_ITListenCplt(hi2c, ITFlags); + } + else if((hi2c->XferOptions != I2C_NO_OPTION_FRAME) && (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + /* Last Byte is Transmitted */ + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSequentialCplt(hi2c); + } + else + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + } } else { - /* if no, error usecase, a Non-Acknowledge of last Data is generated by the MASTER*/ + /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/ /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); /* Set ErrorCode corresponding to a Non-Acknowledge */ hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Call the Error callback to prevent upper layer */ - HAL_I2C_ErrorCallback(hi2c); } } - else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR) == SET) + else if(((ITFlags & I2C_FLAG_RXNE) != RESET) && ((ITSources & I2C_IT_RXI) != RESET)) { - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + if(hi2c->XferCount > 0U) + { + /* Read data from RXDR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; + hi2c->XferSize--; + hi2c->XferCount--; + } + + if((hi2c->XferCount == 0U) && \ + (hi2c->XferOptions != I2C_NO_OPTION_FRAME)) + { + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSequentialCplt(hi2c); + } } - /* Check first if STOPF is set */ - /* to prevent a Write Data in TX buffer */ - /* which is stuck in TXDR until next */ - /* communication with Master */ - else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) + else if(((ITFlags & I2C_FLAG_ADDR) != RESET) && ((ITSources & I2C_IT_ADDRI) != RESET)) { - /* Disable ERRI, TCI, STOPI, NACKI, ADDRI, RXI, TXI interrupts */ - __HAL_I2C_DISABLE_IT(hi2c,I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI ); - - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - HAL_I2C_SlaveTxCpltCallback(hi2c); + I2C_ITAddrCplt(hi2c, ITFlags); } - else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == SET) + else if(((ITFlags & I2C_FLAG_TXIS) != RESET) && ((ITSources & I2C_IT_TXI) != RESET)) { /* Write data to TXDR only if XferCount not reach "0" */ /* A TXIS flag can be set, during STOP treatment */ - if(hi2c->XferCount > 0) + /* Check if all Datas have already been sent */ + /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */ + if(hi2c->XferCount > 0U) { /* Write data to TXDR */ hi2c->Instance->TXDR = (*hi2c->pBuffPtr++); hi2c->XferCount--; + hi2c->XferSize--; } + else + { + if((hi2c->XferOptions == I2C_NEXT_FRAME) || (hi2c->XferOptions == I2C_FIRST_FRAME)) + { + /* Last Byte is Transmitted */ + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSequentialCplt(hi2c); + } + } + } + + /* Check if STOPF is set */ + if(((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET)) + { + /* Call I2C Slave complete process */ + I2C_ITSlaveCplt(hi2c, ITFlags); } /* Process Unlocked */ __HAL_UNLOCK(hi2c); - + return HAL_OK; -} +} /** - * @brief Handle Interrupt Flags Slave Receive Mode + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with DMA. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. + * @param ITFlags Interrupt flags to handle. + * @param ITSources Interrupt sources enabled. * @retval HAL status */ -static HAL_StatusTypeDef I2C_SlaveReceive_ISR(I2C_HandleTypeDef *hi2c) +static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) { + uint16_t devaddress = 0U; + uint32_t xfermode = 0U; + /* Process Locked */ __HAL_LOCK(hi2c); - - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) != RESET) + + if(((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET)) { /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - + /* Set corresponding Error Code */ hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - HAL_I2C_ErrorCallback(hi2c); - } - else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR) == SET) - { - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); - } - else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) - { - /* Read data from RXDR */ - (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; - hi2c->XferSize--; - hi2c->XferCount--; - } - else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) - { - /* Disable ERRI, TCI, STOPI, NACKI, ADDRI, RXI, TXI interrupts */ - __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI); - - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); + /* No need to generate STOP, it is automatically done */ + /* But enable STOP interrupt, to treat it */ + /* Error callback will be send during stop flag treatment */ + I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); - HAL_I2C_SlaveRxCpltCallback(hi2c); + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + } + else if(((ITFlags & I2C_FLAG_TCR) != RESET) && ((ITSources & I2C_IT_TCI) != RESET)) + { + /* Disable TC interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_TCI); + + if(hi2c->XferCount != 0U) + { + /* Recover Slave address */ + devaddress = (hi2c->Instance->CR2 & I2C_CR2_SADD); + + /* Prepare the new XferSize to transfer */ + if(hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = I2C_AUTOEND_MODE; + } + + /* Set the new XferSize in Nbytes register */ + I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, xfermode, I2C_NO_STARTSTOP); + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Enable DMA Request */ + if(hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + } + else + { + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + } + } + else + { + /* Wrong size Status regarding TCR flag event */ + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); + } + } + else if(((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET)) + { + /* Call I2C Master complete process */ + I2C_ITMasterCplt(hi2c, ITFlags); } /* Process Unlocked */ __HAL_UNLOCK(hi2c); + + return HAL_OK; +} + +/** + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param ITFlags Interrupt flags to handle. + * @param ITSources Interrupt sources enabled. + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) +{ + /* Process locked */ + __HAL_LOCK(hi2c); - return HAL_OK; -} + if(((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET)) + { + /* Check that I2C transfer finished */ + /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ + /* Mean XferCount == 0 */ + /* So clear Flag NACKF only */ + if(I2C_GET_DMA_REMAIN_DATA(hi2c) == 0U) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + } + else + { + /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/ + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set ErrorCode corresponding to a Non-Acknowledge */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + } + } + else if(((ITFlags & I2C_FLAG_ADDR) != RESET) && ((ITSources & I2C_IT_ADDRI) != RESET)) + { + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + } + else if(((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET)) + { + /* Call I2C Slave complete process */ + I2C_ITSlaveCplt(hi2c, ITFlags); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} /** * @brief Master sends target device address followed by internal memory address for write request. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. - * @param DevAddress Target device address + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shift at right before call interface * @param MemAddress Internal memory address * @param MemAddSize Size of internal memory address * @param Timeout Timeout duration + * @param Tickstart Tick start value * @retval HAL status */ -static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout) +static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart) { - I2C_TransferConfig(hi2c, DevAddress, MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); + I2C_TransferConfig(hi2c,DevAddress,MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); /* Wait until TXIS flag is set */ - if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout) != HAL_OK) + if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) { if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) { @@ -3147,16 +3638,16 @@ static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_ if(MemAddSize == I2C_MEMADD_SIZE_8BIT) { /* Send Memory Address */ - hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); - } + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + } /* If Memory address size is 16Bit */ else { /* Send MSB of Memory Address */ - hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); - + hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); + /* Wait until TXIS flag is set */ - if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout) != HAL_OK) + if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) { if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) { @@ -3169,11 +3660,11 @@ static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_ } /* Send LSB of Memory Address */ - hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); } - + /* Wait until TCR flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout) != HAL_OK) + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK) { return HAL_TIMEOUT; } @@ -3185,18 +3676,20 @@ return HAL_OK; * @brief Master sends target device address followed by internal memory address for read request. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. - * @param DevAddress Target device address + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shift at right before call interface * @param MemAddress Internal memory address * @param MemAddSize Size of internal memory address * @param Timeout Timeout duration + * @param Tickstart Tick start value * @retval HAL status */ -static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout) +static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart) { - I2C_TransferConfig(hi2c, DevAddress, MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE); - + I2C_TransferConfig(hi2c,DevAddress,MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE); + /* Wait until TXIS flag is set */ - if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout) != HAL_OK) + if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) { if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) { @@ -3207,21 +3700,21 @@ static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t return HAL_TIMEOUT; } } - + /* If Memory address size is 8Bit */ if(MemAddSize == I2C_MEMADD_SIZE_8BIT) { /* Send Memory Address */ - hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); - } + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + } /* If Memory address size is 16Bit */ else { /* Send MSB of Memory Address */ - hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); - + hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); + /* Wait until TXIS flag is set */ - if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout) != HAL_OK) + if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) { if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) { @@ -3234,11 +3727,11 @@ static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t } /* Send LSB of Memory Address */ - hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); } - + /* Wait until TC flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout) != HAL_OK) + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK) { return HAL_TIMEOUT; } @@ -3246,6 +3739,541 @@ static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t return HAL_OK; } +/** + * @brief I2C Address complete process callback. + * @param hi2c I2C handle. + * @param ITFlags Interrupt flags to handle. + * @retval None + */ +static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) +{ + uint8_t transferdirection = 0U; + uint16_t slaveaddrcode = 0U; + uint16_t ownadd1code = 0U; + uint16_t ownadd2code = 0U; + + /* In case of Listen state, need to inform upper layer of address match code event */ + if((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN) + { + transferdirection = I2C_GET_DIR(hi2c); + slaveaddrcode = I2C_GET_ADDR_MATCH(hi2c); + ownadd1code = I2C_GET_OWN_ADDRESS1(hi2c); + ownadd2code = I2C_GET_OWN_ADDRESS2(hi2c); + + /* If 10bits addressing mode is selected */ + if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) + { + if((slaveaddrcode & SlaveAddr_MSK) == ((ownadd1code >> SlaveAddr_SHIFT) & SlaveAddr_MSK)) + { + slaveaddrcode = ownadd1code; + hi2c->AddrEventCount++; + if(hi2c->AddrEventCount == 2U) + { + /* Reset Address Event counter */ + hi2c->AddrEventCount = 0U; + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call Slave Addr callback */ + HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); + } + } + else + { + slaveaddrcode = ownadd2code; + + /* Disable ADDR Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call Slave Addr callback */ + HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); + } + } + /* else 7 bits addressing mode is selected */ + else + { + /* Disable ADDR Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call Slave Addr callback */ + HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); + } + } + /* Else clear address flag only */ + else + { + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + } +} + +/** + * @brief I2C Master sequential complete process. + * @param hi2c I2C handle. + * @retval None + */ +static void I2C_ITMasterSequentialCplt(I2C_HandleTypeDef *hi2c) +{ + /* Reset I2C handle mode */ + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* No Generate Stop, to permit restart mode */ + /* The stop will be done at the end of transfer, when I2C_AUTOEND_MODE enable */ + if (hi2c->State == HAL_I2C_STATE_BUSY_TX) + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; + hi2c->XferISR = NULL; + + /* Disable Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ + HAL_I2C_MasterTxCpltCallback(hi2c); + } + /* hi2c->State == HAL_I2C_STATE_BUSY_RX */ + else + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; + hi2c->XferISR = NULL; + + /* Disable Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ + HAL_I2C_MasterRxCpltCallback(hi2c); + } +} + +/** + * @brief I2C Slave sequential complete process. + * @param hi2c I2C handle. + * @retval None + */ +static void I2C_ITSlaveSequentialCplt(I2C_HandleTypeDef *hi2c) +{ + /* Reset I2C handle mode */ + hi2c->Mode = HAL_I2C_MODE_NONE; + + if(hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) + { + /* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; + + /* Disable Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the Tx complete callback to inform upper layer of the end of transmit process */ + HAL_I2C_SlaveTxCpltCallback(hi2c); + } + + else if(hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) + { + /* Remove HAL_I2C_STATE_SLAVE_BUSY_RX, keep only HAL_I2C_STATE_LISTEN */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; + + /* Disable Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the Rx complete callback to inform upper layer of the end of receive process */ + HAL_I2C_SlaveRxCpltCallback(hi2c); + } +} + +/** + * @brief I2C Master complete process. + * @param hi2c I2C handle. + * @param ITFlags Interrupt flags to handle. + * @retval None + */ +static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) +{ + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + /* Reset handle parameters */ + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->XferISR = NULL; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + + if((ITFlags & I2C_FLAG_AF) != RESET) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set acknowledge error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + } + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + /* Disable Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT| I2C_XFER_RX_IT); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ + if((hi2c->ErrorCode != HAL_I2C_ERROR_NONE) || (hi2c->State == HAL_I2C_STATE_ABORT)) + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, hi2c->ErrorCode); + } + /* hi2c->State == HAL_I2C_STATE_BUSY_TX */ + else if(hi2c->State == HAL_I2C_STATE_BUSY_TX) + { + hi2c->State = HAL_I2C_STATE_READY; + + if (hi2c->Mode == HAL_I2C_MODE_MEM) + { + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ + HAL_I2C_MemTxCpltCallback(hi2c); + } + else + { + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ + HAL_I2C_MasterTxCpltCallback(hi2c); + } + } + /* hi2c->State == HAL_I2C_STATE_BUSY_RX */ + else if(hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + hi2c->State = HAL_I2C_STATE_READY; + + if (hi2c->Mode == HAL_I2C_MODE_MEM) + { + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + HAL_I2C_MemRxCpltCallback(hi2c); + } + else + { + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + HAL_I2C_MasterRxCpltCallback(hi2c); + } + } +} + +/** + * @brief I2C Slave complete process. + * @param hi2c I2C handle. + * @param ITFlags Interrupt flags to handle. + * @retval None + */ +static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) +{ + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR); + + /* Disable all interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT | I2C_XFER_RX_IT); + + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + /* If a DMA is ongoing, Update handle size context */ + if(((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) || + ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)) + { + hi2c->XferCount = I2C_GET_DMA_REMAIN_DATA(hi2c); + } + + /* All data are not transferred, so set error code accordingly */ + if(hi2c->XferCount != 0U) + { + /* Set ErrorCode corresponding to a Non-Acknowledge */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + } + + /* Store Last receive data if any */ + if(((ITFlags & I2C_FLAG_RXNE) != RESET)) + { + /* Read data from RXDR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; + + if((hi2c->XferSize > 0U)) + { + hi2c->XferSize--; + hi2c->XferCount--; + + /* Set ErrorCode corresponding to a Non-Acknowledge */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + } + } + + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->XferISR = NULL; + + if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, hi2c->ErrorCode); + + /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ + if(hi2c->State == HAL_I2C_STATE_LISTEN) + { + /* Call I2C Listen complete process */ + I2C_ITListenCplt(hi2c, ITFlags); + } + } + else if(hi2c->XferOptions != I2C_NO_OPTION_FRAME) + { + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ + HAL_I2C_ListenCpltCallback(hi2c); + } + /* Call the corresponding callback to inform upper layer of End of Transfer */ + else if(hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the Slave Rx Complete callback */ + HAL_I2C_SlaveRxCpltCallback(hi2c); + } + else + { + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the Slave Tx Complete callback */ + HAL_I2C_SlaveTxCpltCallback(hi2c); + } +} + +/** + * @brief I2C Listen complete process. + * @param hi2c I2C handle. + * @param ITFlags Interrupt flags to handle. + * @retval None + */ +static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) +{ + /* Reset handle parameters */ + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->XferISR = NULL; + + /* Store Last receive data if any */ + if(((ITFlags & I2C_FLAG_RXNE) != RESET)) + { + /* Read data from RXDR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; + + if((hi2c->XferSize > 0U)) + { + hi2c->XferSize--; + hi2c->XferCount--; + + /* Set ErrorCode corresponding to a Non-Acknowledge */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + } + } + + /* Disable all Interrupts*/ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT); + + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ + HAL_I2C_ListenCpltCallback(hi2c); +} + +/** + * @brief I2C interrupts error process. + * @param hi2c I2C handle. + * @param ErrorCode Error code to handle. + * @retval None + */ +static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) +{ + /* Reset handle parameters */ + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferCount = 0U; + + /* Set new error code */ + hi2c->ErrorCode |= ErrorCode; + + /* Disable Interrupts */ + if((hi2c->State == HAL_I2C_STATE_LISTEN) || + (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) || + (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)) + { + /* Disable all interrupts, except interrupts related to LISTEN state */ + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_TX_IT); + + /* keep HAL_I2C_STATE_LISTEN if set */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->XferISR = I2C_Slave_ISR_IT; + } + else + { + /* Disable all interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT); + + /* If state is an abort treatment on goind, don't change state */ + /* This change will be do later */ + if(hi2c->State != HAL_I2C_STATE_ABORT) + { + /* Set HAL_I2C_STATE_READY */ + hi2c->State = HAL_I2C_STATE_READY; + } + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->XferISR = NULL; + } + + /* Abort DMA TX transfer if any */ + if((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) + { + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Abort DMA TX */ + if(HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); + } + } + /* Abort DMA RX transfer if any */ + else if((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) + { + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Abort DMA RX */ + if(HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) + { + /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */ + hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); + } + } + else if(hi2c->State == HAL_I2C_STATE_ABORT) + { + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ + HAL_I2C_AbortCpltCallback(hi2c); + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ + HAL_I2C_ErrorCallback(hi2c); + } +} + +/** + * @brief I2C Tx data register flush process. + * @param hi2c I2C handle. + * @retval None + */ +static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c) +{ + /* If a pending TXIS flag is set */ + /* Write a dummy data in TXDR to clear it */ + if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET) + { + hi2c->Instance->TXDR = 0x00U; + } + + /* Flush TX register if not empty */ + if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET) + { + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE); + } +} + /** * @brief DMA I2C master transmit process complete callback. * @param hdma DMA handle @@ -3253,157 +4281,38 @@ static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t */ static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma) { - uint16_t DevAddress; I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; - - /* Check if last DMA request was done with RELOAD */ - /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE */ - if( (hi2c->XferSize == MAX_NBYTE_SIZE) && (hi2c->XferSize < hi2c->XferCount) ) + + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + + /* If last transfer, enable STOP interrupt */ + if(hi2c->XferCount == 0U) { - /* Wait until TCR flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, I2C_TIMEOUT_TCR) != HAL_OK) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - } - - /* Disable DMA Request */ - hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; - - /* Check if Errors has been detected during transfer */ - if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) - { - /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ - /* Wait until STOPF flag is reset */ - if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK) - { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - } - else - { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - } - } - - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - /* Clear Configuration Register 2 */ - I2C_RESET_CR2(hi2c); - - hi2c->XferCount = 0; - - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - HAL_I2C_ErrorCallback(hi2c); - } - else - { - hi2c->pBuffPtr += hi2c->XferSize; - hi2c->XferCount -= hi2c->XferSize; - if(hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - } - else - { - hi2c->XferSize = hi2c->XferCount; - } - - DevAddress = (hi2c->Instance->CR2 & I2C_CR2_SADD); - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); - - /* Send Slave Address */ - /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE */ - if( (hi2c->XferSize == MAX_NBYTE_SIZE) && (hi2c->XferSize < hi2c->XferCount) ) - { - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); - } - else - { - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); - } - - /* Wait until TXIS flag is set */ - if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, I2C_TIMEOUT_TXIS) != HAL_OK) - { - /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ - /* Wait until STOPF flag is reset */ - if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK) - { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - } - else - { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - } - } - - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - /* Clear Configuration Register 2 */ - I2C_RESET_CR2(hi2c); - - hi2c->XferCount = 0; - - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - HAL_I2C_ErrorCallback(hi2c); - } - else - { - /* Enable DMA Request */ - hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; - } - } + /* Enable STOP interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); } + /* else prepare a new DMA transfer and enable TCReload interrupt */ else { - /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ - /* Wait until STOPF flag is reset */ - if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK) - { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - } - else - { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - } - } - - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - /* Clear Configuration Register 2 */ - I2C_RESET_CR2(hi2c); + /* Update Buffer pointer */ + hi2c->pBuffPtr += hi2c->XferSize; - /* Disable DMA Request */ - hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; - - hi2c->XferCount = 0; - - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Check if Errors has been detected during transfer */ - if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) + /* Set the XferSize to transfer */ + if(hi2c->XferCount > MAX_NBYTE_SIZE) { - HAL_I2C_ErrorCallback(hi2c); + hi2c->XferSize = MAX_NBYTE_SIZE; } else { - HAL_I2C_MasterTxCpltCallback(hi2c); + hi2c->XferSize = hi2c->XferCount; } + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); + + /* Enable TC interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT); } } @@ -3414,215 +4323,50 @@ static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma) */ static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma) { - I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; - - /* Wait until STOP flag is set */ - if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK) - { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - /* Normal Use case, a AF is generated by master */ - /* to inform slave the end of transfer */ - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - } - else - { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - } - } - - /* Clear STOP flag */ - __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_STOPF); - - /* Wait until BUSY flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY) != HAL_OK) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - } - - /* Disable DMA Request */ - hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; - - hi2c->XferCount = 0; - - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Check if Errors has been detected during transfer */ - if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) - { - HAL_I2C_ErrorCallback(hi2c); - } - else - { - HAL_I2C_SlaveTxCpltCallback(hi2c); - } + /* No specific action, Master fully manage the generation of STOP condition */ + /* Mean that this generation can arrive at any time, at the end or during DMA process */ + /* So STOP condition should be manage through Interrupt treatment */ } /** - * @brief DMA I2C master receive process complete callback + * @brief DMA I2C master receive process complete callback. * @param hdma DMA handle * @retval None */ static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma) { I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; - uint16_t DevAddress; - - /* Check if last DMA request was done with RELOAD */ - /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE */ - if( (hi2c->XferSize == MAX_NBYTE_SIZE) && (hi2c->XferSize < hi2c->XferCount) ) + + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + + /* If last transfer, enable STOP interrupt */ + if(hi2c->XferCount == 0U) { - /* Wait until TCR flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, I2C_TIMEOUT_TCR) != HAL_OK) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - } - - /* Disable DMA Request */ - hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; - - /* Check if Errors has been detected during transfer */ - if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) - { - /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ - /* Wait until STOPF flag is reset */ - if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK) - { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - } - else - { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - } - } - - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - /* Clear Configuration Register 2 */ - I2C_RESET_CR2(hi2c); - - hi2c->XferCount = 0; - - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - HAL_I2C_ErrorCallback(hi2c); - } - else - { - hi2c->pBuffPtr += hi2c->XferSize; - hi2c->XferCount -= hi2c->XferSize; - if(hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - } - else - { - hi2c->XferSize = hi2c->XferCount; - } - - DevAddress = (hi2c->Instance->CR2 & I2C_CR2_SADD); - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize); - - /* Send Slave Address */ - /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE */ - if( (hi2c->XferSize == MAX_NBYTE_SIZE) && (hi2c->XferSize < hi2c->XferCount) ) - { - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); - } - else - { - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); - } - - /* Wait until RXNE flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, I2C_TIMEOUT_RXNE) != HAL_OK) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - } - - /* Check if Errors has been detected during transfer */ - if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) - { - /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ - /* Wait until STOPF flag is reset */ - if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK) - { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - } - else - { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - } - } - - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - /* Clear Configuration Register 2 */ - I2C_RESET_CR2(hi2c); - - hi2c->XferCount = 0; - - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - HAL_I2C_ErrorCallback(hi2c); - } - else - { - /* Enable DMA Request */ - hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; - } - } + /* Enable STOP interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); } + /* else prepare a new DMA transfer and enable TCReload interrupt */ else { - /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ - /* Wait until STOPF flag is reset */ - if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK) - { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - } - else - { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - } - } - - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - /* Clear Configuration Register 2 */ - I2C_RESET_CR2(hi2c); - - /* Disable DMA Request */ - hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; - - hi2c->XferCount = 0; - - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; + /* Update Buffer pointer */ + hi2c->pBuffPtr += hi2c->XferSize; - /* Check if Errors has been detected during transfer */ - if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) + /* Set the XferSize to transfer */ + if(hi2c->XferCount > MAX_NBYTE_SIZE) { - HAL_I2C_ErrorCallback(hi2c); + hi2c->XferSize = MAX_NBYTE_SIZE; } else { - HAL_I2C_MasterRxCpltCallback(hi2c); + hi2c->XferSize = hi2c->XferCount; } + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize); + + /* Enable TC interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT); } } @@ -3633,398 +4377,57 @@ static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma) */ static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma) { - I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; - - /* Wait until STOPF flag is reset */ - if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK) - { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - } - else - { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - } - } - - /* Clear STOPF flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - /* Wait until BUSY flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY) != HAL_OK) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - } - - /* Disable DMA Request */ - hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; - - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - - hi2c->XferCount = 0; - - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Check if Errors has been detected during transfer */ - if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) - { - HAL_I2C_ErrorCallback(hi2c); - } - else - { - HAL_I2C_SlaveRxCpltCallback(hi2c); - } + /* No specific action, Master fully manage the generation of STOP condition */ + /* Mean that this generation can arrive at any time, at the end or during DMA process */ + /* So STOP condition should be manage through Interrupt treatment */ } /** - * @brief DMA I2C Memory Write process complete callback + * @brief DMA I2C communication error callback. * @param hdma DMA handle * @retval None */ -static void I2C_DMAMemTransmitCplt(DMA_HandleTypeDef *hdma) -{ - uint16_t DevAddress; - I2C_HandleTypeDef* hi2c = ( I2C_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - /* Check if last DMA request was done with RELOAD */ - /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE */ - if( (hi2c->XferSize == MAX_NBYTE_SIZE) && (hi2c->XferSize < hi2c->XferCount) ) - { - /* Wait until TCR flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, I2C_TIMEOUT_TCR) != HAL_OK) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - } - - /* Disable DMA Request */ - hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; - - /* Check if Errors has been detected during transfer */ - if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) - { - /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ - /* Wait until STOPF flag is reset */ - if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK) - { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - } - else - { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - } - } - - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - /* Clear Configuration Register 2 */ - I2C_RESET_CR2(hi2c); - - hi2c->XferCount = 0; - - hi2c->State = HAL_I2C_STATE_READY; - HAL_I2C_ErrorCallback(hi2c); - } - else - { - hi2c->pBuffPtr += hi2c->XferSize; - hi2c->XferCount -= hi2c->XferSize; - if(hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - } - else - { - hi2c->XferSize = hi2c->XferCount; - } - - DevAddress = (hi2c->Instance->CR2 & I2C_CR2_SADD); - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); - - /* Send Slave Address */ - /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE */ - if( (hi2c->XferSize == MAX_NBYTE_SIZE) && (hi2c->XferSize < hi2c->XferCount) ) - { - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); - } - else - { - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); - } - - /* Wait until TXIS flag is set */ - if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, I2C_TIMEOUT_TXIS) != HAL_OK) - { - /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ - /* Wait until STOPF flag is reset */ - if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK) - { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - } - else - { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - } - } - - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - /* Clear Configuration Register 2 */ - I2C_RESET_CR2(hi2c); - - hi2c->XferCount = 0; - - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - HAL_I2C_ErrorCallback(hi2c); - } - else - { - /* Enable DMA Request */ - hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; - } - } - } - else - { - /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ - /* Wait until STOPF flag is reset */ - if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK) - { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - } - else - { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - } - } - - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - /* Clear Configuration Register 2 */ - I2C_RESET_CR2(hi2c); - - /* Disable DMA Request */ - hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; - - hi2c->XferCount = 0; - - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Check if Errors has been detected during transfer */ - if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) - { - HAL_I2C_ErrorCallback(hi2c); - } - else - { - HAL_I2C_MemTxCpltCallback(hi2c); - } - } -} - -/** - * @brief DMA I2C Memory Read process complete callback - * @param hdma DMA handle - * @retval None - */ -static void I2C_DMAMemReceiveCplt(DMA_HandleTypeDef *hdma) -{ - I2C_HandleTypeDef* hi2c = ( I2C_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - uint16_t DevAddress; - - /* Check if last DMA request was done with RELOAD */ - /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE */ - if( (hi2c->XferSize == MAX_NBYTE_SIZE) && (hi2c->XferSize < hi2c->XferCount) ) - { - /* Wait until TCR flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, I2C_TIMEOUT_TCR) != HAL_OK) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - } - - /* Disable DMA Request */ - hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; - - /* Check if Errors has been detected during transfer */ - if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) - { - /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ - /* Wait until STOPF flag is reset */ - if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK) - { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - } - else - { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - } - } - - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - /* Clear Configuration Register 2 */ - I2C_RESET_CR2(hi2c); - - hi2c->XferCount = 0; - - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - HAL_I2C_ErrorCallback(hi2c); - } - else - { - hi2c->pBuffPtr += hi2c->XferSize; - hi2c->XferCount -= hi2c->XferSize; - if(hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - } - else - { - hi2c->XferSize = hi2c->XferCount; - } - - DevAddress = (hi2c->Instance->CR2 & I2C_CR2_SADD); - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize); - - /* Send Slave Address */ - /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE */ - if( (hi2c->XferSize == MAX_NBYTE_SIZE) && (hi2c->XferSize < hi2c->XferCount) ) - { - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); - } - else - { - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); - } - - /* Wait until RXNE flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, I2C_TIMEOUT_RXNE) != HAL_OK) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - } - - /* Check if Errors has been detected during transfer */ - if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) - { - /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ - /* Wait until STOPF flag is reset */ - if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK) - { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - } - else - { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - } - } - - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - /* Clear Configuration Register 2 */ - I2C_RESET_CR2(hi2c); - - hi2c->XferCount = 0; - - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - HAL_I2C_ErrorCallback(hi2c); - } - else - { - /* Enable DMA Request */ - hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; - } - } - } - else - { - /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ - /* Wait until STOPF flag is reset */ - if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK) - { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - } - else - { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - } - } - - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - /* Clear Configuration Register 2 */ - I2C_RESET_CR2(hi2c); - - /* Disable DMA Request */ - hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; - - hi2c->XferCount = 0; - - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Check if Errors has been detected during transfer */ - if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) - { - HAL_I2C_ErrorCallback(hi2c); - } - else - { - HAL_I2C_MemRxCpltCallback(hi2c); - } - } -} - -/** - * @brief DMA I2C communication error callback. - * @param hdma DMA handle - * @retval None - */ -static void I2C_DMAError(DMA_HandleTypeDef *hdma) +static void I2C_DMAError(DMA_HandleTypeDef *hdma) { I2C_HandleTypeDef* hi2c = ( I2C_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - + /* Disable Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; - - hi2c->XferCount = 0; - - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; - - HAL_I2C_ErrorCallback(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_DMA); +} + +/** + * @brief DMA I2C communication abort callback + * (To be called at end of DMA Abort procedure). + * @param hdma: DMA handle. + * @retval None + */ +static void I2C_DMAAbort(DMA_HandleTypeDef *hdma) +{ + I2C_HandleTypeDef* hi2c = ( I2C_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + /* Disable Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + /* Reset AbortCpltCallback */ + hi2c->hdmatx->XferAbortCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Check if come from abort from user */ + if(hi2c->State == HAL_I2C_STATE_ABORT) + { + hi2c->State = HAL_I2C_STATE_READY; + + /* Call the corresponding callback to inform upper layer of End of Transfer */ + HAL_I2C_AbortCpltCallback(hi2c); + } + else + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + HAL_I2C_ErrorCallback(hi2c); + } } /** @@ -4034,52 +4437,28 @@ static void I2C_DMAError(DMA_HandleTypeDef *hdma) * @param Flag Specifies the I2C flag to check. * @param Status The new Flag status (SET or RESET). * @param Timeout Timeout duration + * @param Tickstart Tick start value * @retval HAL status */ -static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout) -{ - uint32_t tickstart = HAL_GetTick(); - - /* Wait until flag is set */ - if(Status == RESET) - { - while(__HAL_I2C_GET_FLAG(hi2c, Flag) == RESET) - { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout)) - { - hi2c->State= HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_TIMEOUT; - } - } - } - } - else +static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart) +{ + while(__HAL_I2C_GET_FLAG(hi2c, Flag) == Status) { - while(__HAL_I2C_GET_FLAG(hi2c, Flag) != RESET) + /* Check for the Timeout */ + if(Timeout != HAL_MAX_DELAY) { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) + if((Timeout == 0U)||((HAL_GetTick() - Tickstart ) > Timeout)) { - if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout)) - { - hi2c->State= HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->State= HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_TIMEOUT; - } + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_TIMEOUT; } } } - return HAL_OK; + return HAL_OK; } /** @@ -4087,16 +4466,15 @@ static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uin * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param Timeout Timeout duration + * @param Tickstart Tick start value * @retval HAL status */ -static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout) -{ - uint32_t tickstart = HAL_GetTick(); - +static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) +{ while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET) { /* Check if a NACK is detected */ - if(I2C_IsAcknowledgeFailed(hi2c, Timeout) != HAL_OK) + if(I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK) { return HAL_ERROR; } @@ -4104,7 +4482,7 @@ static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout)) + if((Timeout == 0U)||((HAL_GetTick() - Tickstart) > Timeout)) { hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; hi2c->State= HAL_I2C_STATE_READY; @@ -4117,7 +4495,7 @@ static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, } } } - return HAL_OK; + return HAL_OK; } /** @@ -4125,23 +4503,21 @@ static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param Timeout Timeout duration + * @param Tickstart Tick start value * @retval HAL status */ -static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout) -{ - uint32_t tickstart = 0x00; - tickstart = HAL_GetTick(); - +static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) +{ while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) { /* Check if a NACK is detected */ - if(I2C_IsAcknowledgeFailed(hi2c, Timeout) != HAL_OK) + if(I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK) { return HAL_ERROR; } /* Check for the Timeout */ - if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout)) + if((Timeout == 0U)||((HAL_GetTick() - Tickstart) > Timeout)) { hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; hi2c->State= HAL_I2C_STATE_READY; @@ -4161,17 +4537,15 @@ static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param Timeout Timeout duration + * @param Tickstart Tick start value * @retval HAL status */ -static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout) -{ - uint32_t tickstart = 0x00; - tickstart = HAL_GetTick(); - +static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) +{ while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) { /* Check if a NACK is detected */ - if(I2C_IsAcknowledgeFailed(hi2c, Timeout) != HAL_OK) + if(I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK) { return HAL_ERROR; } @@ -4194,9 +4568,9 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, return HAL_ERROR; } - + /* Check for the Timeout */ - if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout)) + if((Timeout == 0U)||((HAL_GetTick() - Tickstart) > Timeout)) { hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; hi2c->State= HAL_I2C_STATE_READY; @@ -4215,13 +4589,11 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param Timeout Timeout duration + * @param Tickstart Tick start value * @retval HAL status */ -static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout) +static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) { - uint32_t tickstart = 0x00; - tickstart = HAL_GetTick(); - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) { /* Wait until STOP Flag is reset */ @@ -4231,7 +4603,7 @@ static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32 /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout)) + if((Timeout == 0U)||((HAL_GetTick() - Tickstart) > Timeout)) { hi2c->State= HAL_I2C_STATE_READY; hi2c->Mode = HAL_I2C_MODE_NONE; @@ -4249,11 +4621,8 @@ static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32 /* Clear STOP Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - /* Flush TX register if not empty */ - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET) - { - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE); - } + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); /* Clear Configuration Register 2 */ I2C_RESET_CR2(hi2c); @@ -4267,7 +4636,7 @@ static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32 return HAL_ERROR; } - return HAL_OK; + return HAL_OK; } /** @@ -4275,7 +4644,7 @@ static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32 * @param hi2c I2C handle. * @param DevAddress Specifies the slave address to be programmed. * @param Size Specifies the number of bytes to be programmed. - * This parameter must be a value between 0 and MAX_NBYTE_SIZE. + * This parameter must be a value between 0 and 255. * @param Mode New state of the I2C START condition generation. * This parameter can be one of the following values: * @arg @ref I2C_RELOAD_MODE Enable Reload mode . @@ -4291,26 +4660,166 @@ static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32 */ static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request) { - uint32_t tmpreg = 0; - + uint32_t tmpreg = 0U; + /* Check the parameters */ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); assert_param(IS_TRANSFER_MODE(Mode)); assert_param(IS_TRANSFER_REQUEST(Request)); - + /* Get the CR2 register value */ tmpreg = hi2c->Instance->CR2; - + /* clear tmpreg specific bits */ tmpreg &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP)); - + /* update tmpreg */ tmpreg |= (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << 16 ) & I2C_CR2_NBYTES) | \ (uint32_t)Mode | (uint32_t)Request); - + /* update CR2 register */ - hi2c->Instance->CR2 = tmpreg; -} + hi2c->Instance->CR2 = tmpreg; +} + +/** + * @brief Manage the enabling of Interrupts. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition. + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) +{ + uint32_t tmpisr = 0U; + + if((hi2c->XferISR == I2C_Master_ISR_DMA) || \ + (hi2c->XferISR == I2C_Slave_ISR_DMA)) + { + if((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) + { + /* Enable ERR, STOP, NACK and ADDR interrupts */ + tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; + } + + if((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT) + { + /* Enable ERR and NACK interrupts */ + tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; + } + + if((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT) + { + /* Enable STOP interrupts */ + tmpisr |= I2C_IT_STOPI; + } + + if((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT) + { + /* Enable TC interrupts */ + tmpisr |= I2C_IT_TCI; + } + } + else + { + if((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) + { + /* Enable ERR, STOP, NACK, and ADDR interrupts */ + tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; + } + + if((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) + { + /* Enable ERR, TC, STOP, NACK and RXI interrupts */ + tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI; + } + + if((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) + { + /* Enable ERR, TC, STOP, NACK and TXI interrupts */ + tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI; + } + + if((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT) + { + /* Enable STOP interrupts */ + tmpisr |= I2C_IT_STOPI; + } + } + + /* Enable interrupts only at the end */ + /* to avoid the risk of I2C interrupt handle execution before */ + /* all interrupts requested done */ + __HAL_I2C_ENABLE_IT(hi2c, tmpisr); + + return HAL_OK; +} + +/** + * @brief Manage the disabling of Interrupts. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition. + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) +{ + uint32_t tmpisr = 0U; + + if((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) + { + /* Disable TC and TXI interrupts */ + tmpisr |= I2C_IT_TCI | I2C_IT_TXI; + + if((hi2c->State & HAL_I2C_STATE_LISTEN) != HAL_I2C_STATE_LISTEN) + { + /* Disable NACK and STOP interrupts */ + tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; + } + } + + if((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) + { + /* Disable TC and RXI interrupts */ + tmpisr |= I2C_IT_TCI | I2C_IT_RXI; + + if((hi2c->State & HAL_I2C_STATE_LISTEN) != HAL_I2C_STATE_LISTEN) + { + /* Disable NACK and STOP interrupts */ + tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; + } + } + + if((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) + { + /* Disable ADDR, NACK and STOP interrupts */ + tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; + } + + if((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT) + { + /* Enable ERR and NACK interrupts */ + tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; + } + + if((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT) + { + /* Enable STOP interrupts */ + tmpisr |= I2C_IT_STOPI; + } + + if((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT) + { + /* Enable TC interrupts */ + tmpisr |= I2C_IT_TCI; + } + + /* Disable interrupts only at the end */ + /* to avoid a breaking situation like at "t" time */ + /* all disable interrupts request are not done */ + __HAL_I2C_DISABLE_IT(hi2c, tmpisr); + + return HAL_OK; +} /** * @} diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_i2c.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_i2c.h index e605abff9f..581136803a 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_i2c.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_i2c.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f0xx_hal_i2c.h * @author MCD Application Team - * @version V1.3.1 - * @date 29-January-2016 + * @version V1.4.0 + * @date 27-May-2016 * @brief Header file of I2C HAL module. ****************************************************************************** * @attention @@ -33,7 +33,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F0xx_HAL_I2C_H @@ -54,13 +54,13 @@ * @{ */ -/* Exported types ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ /** @defgroup I2C_Exported_Types I2C Exported Types * @{ */ /** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition - * @brief I2C Configuration Structure definition + * @brief I2C Configuration Structure definition * @{ */ typedef struct @@ -73,43 +73,71 @@ typedef struct This parameter can be a 7-bit or 10-bit address. */ uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected. - This parameter can be a value of @ref I2C_addressing_mode */ + This parameter can be a value of @ref I2C_ADDRESSING_MODE */ uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected. - This parameter can be a value of @ref I2C_dual_addressing_mode */ + This parameter can be a value of @ref I2C_DUAL_ADDRESSING_MODE */ uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected This parameter can be a 7-bit address. */ uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address if dual addressing mode is selected - This parameter can be a value of @ref I2C_own_address2_masks */ + This parameter can be a value of @ref I2C_OWN_ADDRESS2_MASKS */ uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected. - This parameter can be a value of @ref I2C_general_call_addressing_mode */ + This parameter can be a value of @ref I2C_GENERAL_CALL_ADDRESSING_MODE */ uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected. - This parameter can be a value of @ref I2C_nostretch_mode */ + This parameter can be a value of @ref I2C_NOSTRETCH_MODE */ }I2C_InitTypeDef; -/** +/** * @} */ /** @defgroup HAL_state_structure_definition HAL state structure definition - * @brief HAL State structure definition + * @brief HAL State structure definition + * @note HAL I2C State value coding follow below described bitmap :\n + * b7-b6 Error information\n + * 00 : No Error\n + * 01 : Abort (Abort user request on going)\n + * 10 : Timeout\n + * 11 : Error\n + * b5 IP initilisation status\n + * 0 : Reset (IP not initialized)\n + * 1 : Init done (IP initialized and ready to use. HAL I2C Init function called)\n + * b4 (not used)\n + * x : Should be set to 0\n + * b3\n + * 0 : Ready or Busy (No Listen mode ongoing)\n + * 1 : Listen (IP in Address Listen Mode)\n + * b2 Intrinsic process state\n + * 0 : Ready\n + * 1 : Busy (IP busy with some configuration or internal operations)\n + * b1 Rx state\n + * 0 : Ready (no Rx operation ongoing)\n + * 1 : Busy (Rx operation ongoing)\n + * b0 Tx state\n + * 0 : Ready (no Tx operation ongoing)\n + * 1 : Busy (Tx operation ongoing) * @{ - */ - + */ typedef enum { - HAL_I2C_STATE_RESET = 0x00, /*!< Peripheral is not yet Initialized */ - HAL_I2C_STATE_READY = 0x20, /*!< Peripheral Initialized and ready for use */ - HAL_I2C_STATE_BUSY = 0x24, /*!< An internal process is ongoing */ - HAL_I2C_STATE_BUSY_TX = 0x21, /*!< Data Transmission process is ongoing */ - HAL_I2C_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */ - HAL_I2C_STATE_TIMEOUT = 0xA0, /*!< Timeout state */ - HAL_I2C_STATE_ERROR = 0xE0 /*!< Error */ + HAL_I2C_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */ + HAL_I2C_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use */ + HAL_I2C_STATE_BUSY = 0x24U, /*!< An internal process is ongoing */ + HAL_I2C_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing */ + HAL_I2C_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */ + HAL_I2C_STATE_LISTEN = 0x28U, /*!< Address Listen Mode is ongoing */ + HAL_I2C_STATE_BUSY_TX_LISTEN = 0x29U, /*!< Address Listen Mode and Data Transmission + process is ongoing */ + HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception + process is ongoing */ + HAL_I2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */ + HAL_I2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */ + HAL_I2C_STATE_ERROR = 0xE0U /*!< Error */ }HAL_I2C_StateTypeDef; @@ -119,61 +147,87 @@ typedef enum /** @defgroup HAL_mode_structure_definition HAL mode structure definition * @brief HAL Mode structure definition + * @note HAL I2C Mode value coding follow below described bitmap :\n + * b7 (not used)\n + * x : Should be set to 0\n + * b6\n + * 0 : None\n + * 1 : Memory (HAL I2C communication is in Memory Mode)\n + * b5\n + * 0 : None\n + * 1 : Slave (HAL I2C communication is in Slave Mode)\n + * b4\n + * 0 : None\n + * 1 : Master (HAL I2C communication is in Master Mode)\n + * b3-b2-b1-b0 (not used)\n + * xxxx : Should be set to 0000 * @{ */ typedef enum { - HAL_I2C_MODE_NONE = 0x00, /*!< No I2C communication on going */ - HAL_I2C_MODE_MASTER = 0x10, /*!< I2C communication is in Master Mode */ - HAL_I2C_MODE_SLAVE = 0x20, /*!< I2C communication is in Slave Mode */ - HAL_I2C_MODE_MEM = 0x40 /*!< I2C communication is in Memory Mode */ + HAL_I2C_MODE_NONE = 0x00U, /*!< No I2C communication on going */ + HAL_I2C_MODE_MASTER = 0x10U, /*!< I2C communication is in Master Mode */ + HAL_I2C_MODE_SLAVE = 0x20U, /*!< I2C communication is in Slave Mode */ + HAL_I2C_MODE_MEM = 0x40U /*!< I2C communication is in Memory Mode */ }HAL_I2C_ModeTypeDef; +/** + * @} + */ + /** @defgroup I2C_Error_Code_definition I2C Error Code definition - * @brief I2C Error Code definition + * @brief I2C Error Code definition * @{ - */ -#define HAL_I2C_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */ -#define HAL_I2C_ERROR_BERR ((uint32_t)0x00000001) /*!< BERR error */ -#define HAL_I2C_ERROR_ARLO ((uint32_t)0x00000002) /*!< ARLO error */ -#define HAL_I2C_ERROR_AF ((uint32_t)0x00000004) /*!< ACKF error */ -#define HAL_I2C_ERROR_OVR ((uint32_t)0x00000008) /*!< OVR error */ -#define HAL_I2C_ERROR_DMA ((uint32_t)0x00000010) /*!< DMA transfer error */ -#define HAL_I2C_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */ -#define HAL_I2C_ERROR_SIZE ((uint32_t)0x00000040) /*!< Size Management error */ + */ +#define HAL_I2C_ERROR_NONE (0x00000000U) /*!< No error */ +#define HAL_I2C_ERROR_BERR (0x00000001U) /*!< BERR error */ +#define HAL_I2C_ERROR_ARLO (0x00000002U) /*!< ARLO error */ +#define HAL_I2C_ERROR_AF (0x00000004U) /*!< ACKF error */ +#define HAL_I2C_ERROR_OVR (0x00000008U) /*!< OVR error */ +#define HAL_I2C_ERROR_DMA (0x00000010U) /*!< DMA transfer error */ +#define HAL_I2C_ERROR_TIMEOUT (0x00000020U) /*!< Timeout error */ +#define HAL_I2C_ERROR_SIZE (0x00000040U) /*!< Size Management error */ /** * @} */ -/** @defgroup I2C_handle_Structure_definition I2C handle Structure definition - * @brief I2C handle Structure definition +/** @defgroup I2C_handle_Structure_definition I2C handle Structure definition + * @brief I2C handle Structure definition * @{ - */ -typedef struct + */ +typedef struct __I2C_HandleTypeDef { - I2C_TypeDef *Instance; /*!< I2C registers base address */ + I2C_TypeDef *Instance; /*!< I2C registers base address */ - I2C_InitTypeDef Init; /*!< I2C communication parameters */ + I2C_InitTypeDef Init; /*!< I2C communication parameters */ - uint8_t *pBuffPtr; /*!< Pointer to I2C transfer buffer */ + uint8_t *pBuffPtr; /*!< Pointer to I2C transfer buffer */ - uint16_t XferSize; /*!< I2C transfer size */ + uint16_t XferSize; /*!< I2C transfer size */ - __IO uint16_t XferCount; /*!< I2C transfer counter */ + __IO uint16_t XferCount; /*!< I2C transfer counter */ - DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */ + __IO uint32_t XferOptions; /*!< I2C sequantial transfer options, this parameter can + be a value of @ref I2C_XFEROPTIONS */ - DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */ + __IO uint32_t PreviousState; /*!< I2C communication Previous state */ - HAL_LockTypeDef Lock; /*!< I2C locking object */ + HAL_StatusTypeDef (*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); /*!< I2C transfer IRQ handler function pointer */ - __IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */ + DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */ - __IO HAL_I2C_ModeTypeDef Mode; /*!< I2C communication mode */ + DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */ - __IO uint32_t ErrorCode; /*!< I2C Error code */ + HAL_LockTypeDef Lock; /*!< I2C locking object */ + __IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */ + + __IO HAL_I2C_ModeTypeDef Mode; /*!< I2C communication mode */ + + __IO uint32_t ErrorCode; /*!< I2C Error code */ + + __IO uint32_t AddrEventCount; /*!< I2C Address Event counter */ }I2C_HandleTypeDef; /** * @} @@ -181,90 +235,111 @@ typedef struct /** * @} - */ + */ /* Exported constants --------------------------------------------------------*/ /** @defgroup I2C_Exported_Constants I2C Exported Constants * @{ */ -/** @defgroup I2C_addressing_mode I2C addressing mode +/** @defgroup I2C_XFEROPTIONS I2C Sequential Transfer Options * @{ */ -#define I2C_ADDRESSINGMODE_7BIT ((uint32_t)0x00000001) -#define I2C_ADDRESSINGMODE_10BIT ((uint32_t)0x00000002) +#define I2C_NO_OPTION_FRAME (0xFFFF0000U) +#define I2C_FIRST_FRAME ((uint32_t)I2C_SOFTEND_MODE) +#define I2C_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE)) +#define I2C_FIRST_AND_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE) +#define I2C_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE) /** * @} */ -/** @defgroup I2C_dual_addressing_mode I2C dual addressing mode +/** @defgroup I2C_ADDRESSING_MODE I2C Addressing Mode * @{ */ -#define I2C_DUALADDRESS_DISABLE ((uint32_t)0x00000000) -#define I2C_DUALADDRESS_ENABLE I2C_OAR2_OA2EN +#define I2C_ADDRESSINGMODE_7BIT (0x00000001U) +#define I2C_ADDRESSINGMODE_10BIT (0x00000002U) /** * @} */ -/** @defgroup I2C_own_address2_masks I2C own address2 masks +/** @defgroup I2C_DUAL_ADDRESSING_MODE I2C Dual Addressing Mode * @{ */ -#define I2C_OA2_NOMASK ((uint8_t)0x00) -#define I2C_OA2_MASK01 ((uint8_t)0x01) -#define I2C_OA2_MASK02 ((uint8_t)0x02) -#define I2C_OA2_MASK03 ((uint8_t)0x03) -#define I2C_OA2_MASK04 ((uint8_t)0x04) -#define I2C_OA2_MASK05 ((uint8_t)0x05) -#define I2C_OA2_MASK06 ((uint8_t)0x06) -#define I2C_OA2_MASK07 ((uint8_t)0x07) +#define I2C_DUALADDRESS_DISABLE (0x00000000U) +#define I2C_DUALADDRESS_ENABLE I2C_OAR2_OA2EN /** * @} */ -/** @defgroup I2C_general_call_addressing_mode I2C general call addressing mode +/** @defgroup I2C_OWN_ADDRESS2_MASKS I2C Own Address2 Masks * @{ */ -#define I2C_GENERALCALL_DISABLE ((uint32_t)0x00000000) -#define I2C_GENERALCALL_ENABLE I2C_CR1_GCEN +#define I2C_OA2_NOMASK ((uint8_t)0x00U) +#define I2C_OA2_MASK01 ((uint8_t)0x01U) +#define I2C_OA2_MASK02 ((uint8_t)0x02U) +#define I2C_OA2_MASK03 ((uint8_t)0x03U) +#define I2C_OA2_MASK04 ((uint8_t)0x04U) +#define I2C_OA2_MASK05 ((uint8_t)0x05U) +#define I2C_OA2_MASK06 ((uint8_t)0x06U) +#define I2C_OA2_MASK07 ((uint8_t)0x07U) /** * @} */ -/** @defgroup I2C_nostretch_mode I2C nostretch mode +/** @defgroup I2C_GENERAL_CALL_ADDRESSING_MODE I2C General Call Addressing Mode * @{ */ -#define I2C_NOSTRETCH_DISABLE ((uint32_t)0x00000000) -#define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH +#define I2C_GENERALCALL_DISABLE (0x00000000U) +#define I2C_GENERALCALL_ENABLE I2C_CR1_GCEN /** * @} */ -/** @defgroup I2C_Memory_Address_Size I2C Memory Address Size +/** @defgroup I2C_NOSTRETCH_MODE I2C No-Stretch Mode * @{ */ -#define I2C_MEMADD_SIZE_8BIT ((uint32_t)0x00000001) -#define I2C_MEMADD_SIZE_16BIT ((uint32_t)0x00000002) +#define I2C_NOSTRETCH_DISABLE (0x00000000U) +#define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH /** * @} - */ + */ + +/** @defgroup I2C_MEMORY_ADDRESS_SIZE I2C Memory Address Size + * @{ + */ +#define I2C_MEMADD_SIZE_8BIT (0x00000001U) +#define I2C_MEMADD_SIZE_16BIT (0x00000002U) +/** + * @} + */ -/** @defgroup I2C_ReloadEndMode_definition I2C ReloadEndMode definition +/** @defgroup I2C_XFERDIRECTION I2C Transfer Direction Master Point of View + * @{ + */ +#define I2C_DIRECTION_TRANSMIT (0x00000000U) +#define I2C_DIRECTION_RECEIVE (0x00000001U) +/** + * @} + */ + +/** @defgroup I2C_RELOAD_END_MODE I2C Reload End Mode * @{ */ #define I2C_RELOAD_MODE I2C_CR2_RELOAD #define I2C_AUTOEND_MODE I2C_CR2_AUTOEND -#define I2C_SOFTEND_MODE ((uint32_t)0x00000000) +#define I2C_SOFTEND_MODE (0x00000000U) /** * @} */ -/** @defgroup I2C_StartStopMode_definition I2C StartStopMode definition +/** @defgroup I2C_START_STOP_MODE I2C Start or Stop Mode * @{ */ -#define I2C_NO_STARTSTOP ((uint32_t)0x00000000) -#define I2C_GENERATE_STOP I2C_CR2_STOP -#define I2C_GENERATE_START_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN) -#define I2C_GENERATE_START_WRITE I2C_CR2_START +#define I2C_NO_STARTSTOP (0x00000000U) +#define I2C_GENERATE_STOP I2C_CR2_STOP +#define I2C_GENERATE_START_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN) +#define I2C_GENERATE_START_WRITE I2C_CR2_START /** * @} */ @@ -275,46 +350,44 @@ typedef struct * - XXXXXXXX : Interrupt control mask * @{ */ -#define I2C_IT_ERRI I2C_CR1_ERRIE -#define I2C_IT_TCI I2C_CR1_TCIE -#define I2C_IT_STOPI I2C_CR1_STOPIE -#define I2C_IT_NACKI I2C_CR1_NACKIE -#define I2C_IT_ADDRI I2C_CR1_ADDRIE -#define I2C_IT_RXI I2C_CR1_RXIE -#define I2C_IT_TXI I2C_CR1_TXIE - +#define I2C_IT_ERRI I2C_CR1_ERRIE +#define I2C_IT_TCI I2C_CR1_TCIE +#define I2C_IT_STOPI I2C_CR1_STOPIE +#define I2C_IT_NACKI I2C_CR1_NACKIE +#define I2C_IT_ADDRI I2C_CR1_ADDRIE +#define I2C_IT_RXI I2C_CR1_RXIE +#define I2C_IT_TXI I2C_CR1_TXIE /** * @} */ - /** @defgroup I2C_Flag_definition I2C Flag definition * @{ - */ -#define I2C_FLAG_TXE I2C_ISR_TXE -#define I2C_FLAG_TXIS I2C_ISR_TXIS -#define I2C_FLAG_RXNE I2C_ISR_RXNE -#define I2C_FLAG_ADDR I2C_ISR_ADDR -#define I2C_FLAG_AF I2C_ISR_NACKF -#define I2C_FLAG_STOPF I2C_ISR_STOPF -#define I2C_FLAG_TC I2C_ISR_TC -#define I2C_FLAG_TCR I2C_ISR_TCR -#define I2C_FLAG_BERR I2C_ISR_BERR -#define I2C_FLAG_ARLO I2C_ISR_ARLO -#define I2C_FLAG_OVR I2C_ISR_OVR -#define I2C_FLAG_PECERR I2C_ISR_PECERR -#define I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT -#define I2C_FLAG_ALERT I2C_ISR_ALERT -#define I2C_FLAG_BUSY I2C_ISR_BUSY -#define I2C_FLAG_DIR I2C_ISR_DIR + */ +#define I2C_FLAG_TXE I2C_ISR_TXE +#define I2C_FLAG_TXIS I2C_ISR_TXIS +#define I2C_FLAG_RXNE I2C_ISR_RXNE +#define I2C_FLAG_ADDR I2C_ISR_ADDR +#define I2C_FLAG_AF I2C_ISR_NACKF +#define I2C_FLAG_STOPF I2C_ISR_STOPF +#define I2C_FLAG_TC I2C_ISR_TC +#define I2C_FLAG_TCR I2C_ISR_TCR +#define I2C_FLAG_BERR I2C_ISR_BERR +#define I2C_FLAG_ARLO I2C_ISR_ARLO +#define I2C_FLAG_OVR I2C_ISR_OVR +#define I2C_FLAG_PECERR I2C_ISR_PECERR +#define I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT +#define I2C_FLAG_ALERT I2C_ISR_ALERT +#define I2C_FLAG_BUSY I2C_ISR_BUSY +#define I2C_FLAG_DIR I2C_ISR_DIR /** * @} */ /** * @} - */ - + */ + /* Exported macros -----------------------------------------------------------*/ /** @defgroup I2C_Exported_Macros I2C Exported Macros @@ -325,28 +398,11 @@ typedef struct * @param __HANDLE__ specifies the I2C Handle. * @retval None */ -#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET) +#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET) /** @brief Enable the specified I2C interrupt. * @param __HANDLE__ specifies the I2C Handle. - * @param __INTERRUPT__: specifies the interrupt source to enable. - * This parameter can be one of the following values: - * @arg @ref I2C_IT_ERRI Errors interrupt enable - * @arg @ref I2C_IT_TCI Transfer complete interrupt enable - * @arg @ref I2C_IT_STOPI STOP detection interrupt enable - * @arg @ref I2C_IT_NACKI NACK received interrupt enable - * @arg @ref I2C_IT_ADDRI Address match interrupt enable - * @arg @ref I2C_IT_RXI RX interrupt enable - * @arg @ref I2C_IT_TXI TX interrupt enable - * - * @retval None - */ - -#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__)) - -/** @brief Disable the specified I2C interrupt. - * @param __HANDLE__ specifies the I2C Handle. - * @param __INTERRUPT__: specifies the interrupt source to disable. + * @param __INTERRUPT__ specifies the interrupt source to enable. * This parameter can be one of the following values: * @arg @ref I2C_IT_ERRI Errors interrupt enable * @arg @ref I2C_IT_TCI Transfer complete interrupt enable @@ -355,15 +411,15 @@ typedef struct * @arg @ref I2C_IT_ADDRI Address match interrupt enable * @arg @ref I2C_IT_RXI RX interrupt enable * @arg @ref I2C_IT_TXI TX interrupt enable - * + * * @retval None */ -#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__))) - -/** @brief Check whether the specified I2C interrupt source is enabled or not. +#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__)) + +/** @brief Disable the specified I2C interrupt. * @param __HANDLE__ specifies the I2C Handle. - * @param __INTERRUPT__: specifies the I2C interrupt source to check. - * This parameter can be one of the following values: + * @param __INTERRUPT__ specifies the interrupt source to disable. + * This parameter can be one of the following values: * @arg @ref I2C_IT_ERRI Errors interrupt enable * @arg @ref I2C_IT_TCI Transfer complete interrupt enable * @arg @ref I2C_IT_STOPI STOP detection interrupt enable @@ -371,15 +427,31 @@ typedef struct * @arg @ref I2C_IT_ADDRI Address match interrupt enable * @arg @ref I2C_IT_RXI RX interrupt enable * @arg @ref I2C_IT_TXI TX interrupt enable - * - * @retval The new state of __INTERRUPT__ (TRUE or FALSE). + * + * @retval None */ -#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) +#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__))) + +/** @brief Check whether the specified I2C interrupt source is enabled or not. + * @param __HANDLE__ specifies the I2C Handle. + * @param __INTERRUPT__ specifies the I2C interrupt source to check. + * This parameter can be one of the following values: + * @arg @ref I2C_IT_ERRI Errors interrupt enable + * @arg @ref I2C_IT_TCI Transfer complete interrupt enable + * @arg @ref I2C_IT_STOPI STOP detection interrupt enable + * @arg @ref I2C_IT_NACKI NACK received interrupt enable + * @arg @ref I2C_IT_ADDRI Address match interrupt enable + * @arg @ref I2C_IT_RXI RX interrupt enable + * @arg @ref I2C_IT_TXI TX interrupt enable + * + * @retval The new state of __INTERRUPT__ (SET or RESET). + */ +#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) /** @brief Check whether the specified I2C flag is set or not. * @param __HANDLE__ specifies the I2C Handle. * @param __FLAG__ specifies the flag to check. - * This parameter can be one of the following values: + * This parameter can be one of the following values: * @arg @ref I2C_FLAG_TXE Transmit data register empty * @arg @ref I2C_FLAG_TXIS Transmit interrupt status * @arg @ref I2C_FLAG_RXNE Receive data register not empty @@ -390,54 +462,58 @@ typedef struct * @arg @ref I2C_FLAG_TCR Transfer complete reload * @arg @ref I2C_FLAG_BERR Bus error * @arg @ref I2C_FLAG_ARLO Arbitration lost - * @arg @ref I2C_FLAG_OVR Overrun/Underrun + * @arg @ref I2C_FLAG_OVR Overrun/Underrun * @arg @ref I2C_FLAG_PECERR PEC error in reception - * @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag + * @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag * @arg @ref I2C_FLAG_ALERT SMBus alert * @arg @ref I2C_FLAG_BUSY Bus busy * @arg @ref I2C_FLAG_DIR Transfer direction (slave mode) - * - * @retval The new state of __FLAG__ (TRUE or FALSE). + * + * @retval The new state of __FLAG__ (SET or RESET). */ -#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) +#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) ? SET : RESET) /** @brief Clear the I2C pending flags which are cleared by writing 1 in a specific bit. * @param __HANDLE__ specifies the I2C Handle. * @param __FLAG__ specifies the flag to clear. - * This parameter can be any combination of the following values: + * This parameter can be any combination of the following values: * @arg @ref I2C_FLAG_TXE Transmit data register empty * @arg @ref I2C_FLAG_ADDR Address matched (slave mode) * @arg @ref I2C_FLAG_AF Acknowledge failure received flag * @arg @ref I2C_FLAG_STOPF STOP detection flag * @arg @ref I2C_FLAG_BERR Bus error * @arg @ref I2C_FLAG_ARLO Arbitration lost - * @arg @ref I2C_FLAG_OVR Overrun/Underrun + * @arg @ref I2C_FLAG_OVR Overrun/Underrun * @arg @ref I2C_FLAG_PECERR PEC error in reception - * @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag + * @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag * @arg @ref I2C_FLAG_ALERT SMBus alert - * + * * @retval None */ #define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == I2C_FLAG_TXE) ? ((__HANDLE__)->Instance->ISR |= (__FLAG__)) \ : ((__HANDLE__)->Instance->ICR = (__FLAG__))) - - + /** @brief Enable the specified I2C peripheral. - * @param __HANDLE__ specifies the I2C Handle. + * @param __HANDLE__ specifies the I2C Handle. * @retval None */ #define __HAL_I2C_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) /** @brief Disable the specified I2C peripheral. - * @param __HANDLE__ specifies the I2C Handle. + * @param __HANDLE__ specifies the I2C Handle. * @retval None */ #define __HAL_I2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) +/** @brief Generate a Non-Acknowledge I2C peripheral in Slave mode. + * @param __HANDLE__: specifies the I2C Handle. + * @retval None + */ +#define __HAL_I2C_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK)) /** * @} - */ - + */ + /* Include I2C HAL Extended module */ #include "stm32f0xx_hal_i2c_ex.h" @@ -456,7 +532,7 @@ void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c); void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c); /** * @} - */ + */ /** @addtogroup I2C_Exported_Functions_Group2 Input and Output operation functions * @{ @@ -479,6 +555,14 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pDa HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c); +HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c); +HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress); + /******* Non-Blocking mode: DMA */ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); @@ -488,24 +572,27 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); /** * @} - */ + */ /** @addtogroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks * @{ - */ - /******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */ + */ +/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */ void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c); void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c); void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c); void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c); void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c); void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); +void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c); void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c); void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c); void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c); /** * @} - */ + */ /** @addtogroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions * @{ @@ -538,47 +625,58 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c); */ #define IS_I2C_ADDRESSING_MODE(MODE) (((MODE) == I2C_ADDRESSINGMODE_7BIT) || \ - ((MODE) == I2C_ADDRESSINGMODE_10BIT)) + ((MODE) == I2C_ADDRESSINGMODE_10BIT)) #define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \ - ((ADDRESS) == I2C_DUALADDRESS_ENABLE)) + ((ADDRESS) == I2C_DUALADDRESS_ENABLE)) #define IS_I2C_OWN_ADDRESS2_MASK(MASK) (((MASK) == I2C_OA2_NOMASK) || \ - ((MASK) == I2C_OA2_MASK01) || \ - ((MASK) == I2C_OA2_MASK02) || \ - ((MASK) == I2C_OA2_MASK03) || \ - ((MASK) == I2C_OA2_MASK04) || \ - ((MASK) == I2C_OA2_MASK05) || \ - ((MASK) == I2C_OA2_MASK06) || \ - ((MASK) == I2C_OA2_MASK07)) + ((MASK) == I2C_OA2_MASK01) || \ + ((MASK) == I2C_OA2_MASK02) || \ + ((MASK) == I2C_OA2_MASK03) || \ + ((MASK) == I2C_OA2_MASK04) || \ + ((MASK) == I2C_OA2_MASK05) || \ + ((MASK) == I2C_OA2_MASK06) || \ + ((MASK) == I2C_OA2_MASK07)) #define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || \ - ((CALL) == I2C_GENERALCALL_ENABLE)) + ((CALL) == I2C_GENERALCALL_ENABLE)) #define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \ - ((STRETCH) == I2C_NOSTRETCH_ENABLE)) + ((STRETCH) == I2C_NOSTRETCH_ENABLE)) #define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \ - ((SIZE) == I2C_MEMADD_SIZE_16BIT)) + ((SIZE) == I2C_MEMADD_SIZE_16BIT)) #define IS_TRANSFER_MODE(MODE) (((MODE) == I2C_RELOAD_MODE) || \ - ((MODE) == I2C_AUTOEND_MODE) || \ - ((MODE) == I2C_SOFTEND_MODE)) + ((MODE) == I2C_AUTOEND_MODE) || \ + ((MODE) == I2C_SOFTEND_MODE)) -#define IS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == I2C_GENERATE_STOP) || \ - ((REQUEST) == I2C_GENERATE_START_READ) || \ - ((REQUEST) == I2C_GENERATE_START_WRITE) || \ - ((REQUEST) == I2C_NO_STARTSTOP)) +#define IS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == I2C_GENERATE_STOP) || \ + ((REQUEST) == I2C_GENERATE_START_READ) || \ + ((REQUEST) == I2C_GENERATE_START_WRITE) || \ + ((REQUEST) == I2C_NO_STARTSTOP)) -#define I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN))) +#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_FIRST_FRAME) || \ + ((REQUEST) == I2C_NEXT_FRAME) || \ + ((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \ + ((REQUEST) == I2C_LAST_FRAME)) -#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= (uint32_t)0x000003FF) -#define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FF) +#define I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN))) -#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00))) >> 8))) -#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF)))) +#define I2C_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 16U) +#define I2C_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U) +#define I2C_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND) +#define I2C_GET_OWN_ADDRESS1(__HANDLE__) ((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1) +#define I2C_GET_OWN_ADDRESS2(__HANDLE__) ((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2) -#define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \ +#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU) +#define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU) + +#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00U))) >> 8U))) +#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU)))) + +#define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \ (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN))) /** * @} @@ -601,11 +699,6 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c); * @} */ -/** - * @} - */ - - #ifdef __cplusplus } #endif @@ -614,4 +707,3 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c); #endif /* __STM32F0xx_HAL_I2C_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_i2c_ex.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_i2c_ex.c index 81ee0752b6..84bb9579a7 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_i2c_ex.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_i2c_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f0xx_hal_i2c_ex.c * @author MCD Application Team - * @version V1.3.1 - * @date 29-January-2016 + * @version V1.4.0 + * @date 27-May-2016 * @brief I2C Extended HAL module driver. * This file provides firmware functions to manage the following * functionalities of I2C Extended peripheral: @@ -97,6 +97,7 @@ =============================================================================== [..] This section provides functions allowing to: (+) Configure Noise Filters + (+) Configure Wake Up Feature @endverbatim * @{ @@ -104,9 +105,9 @@ /** * @brief Configure I2C Analog noise filter. - * @param hi2c : pointer to a I2C_HandleTypeDef structure that contains + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2Cx peripheral. - * @param AnalogFilter : new state of the Analog filter. + * @param AnalogFilter New state of the Analog filter. * @retval HAL status */ HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter) @@ -148,14 +149,14 @@ HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t /** * @brief Configure I2C Digital noise filter. - * @param hi2c : pointer to a I2C_HandleTypeDef structure that contains + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2Cx peripheral. - * @param DigitalFilter : Coefficient of digital noise filter between 0x00 and 0x0F. + * @param DigitalFilter Coefficient of digital noise filter between 0x00 and 0x0F. * @retval HAL status */ HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter) { - uint32_t tmpreg = 0; + uint32_t tmpreg = 0U; /* Check the parameters */ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); @@ -178,7 +179,7 @@ HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_ tmpreg &= ~(I2C_CR1_DNF); /* Set I2Cx DNF coefficient */ - tmpreg |= DigitalFilter << 8; + tmpreg |= DigitalFilter << 8U; /* Store the new register value */ hi2c->Instance->CR1 = tmpreg; @@ -198,17 +199,17 @@ HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_ } } -#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) +#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) /** * @brief Enable I2C wakeup from stop mode. - * @param hi2c : pointer to a I2C_HandleTypeDef structure that contains + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2Cx peripheral. * @retval HAL status */ HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp (I2C_HandleTypeDef *hi2c) { /* Check the parameters */ - assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance)); if(hi2c->State == HAL_I2C_STATE_READY) { @@ -241,14 +242,14 @@ HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp (I2C_HandleTypeDef *hi2c) /** * @brief Disable I2C wakeup from stop mode. - * @param hi2c : pointer to a I2C_HandleTypeDef structure that contains + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2Cx peripheral. * @retval HAL status */ HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp (I2C_HandleTypeDef *hi2c) { /* Check the parameters */ - assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance)); if(hi2c->State == HAL_I2C_STATE_READY) { @@ -281,7 +282,7 @@ HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp (I2C_HandleTypeDef *hi2c) /** * @brief Enable the I2C fast mode plus driving capability. - * @param ConfigFastModePlus: selects the pin. + * @param ConfigFastModePlus Selects the pin. * This parameter can be one of the @ref I2CEx_FastModePlus values * @retval None */ @@ -299,7 +300,7 @@ void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus) /** * @brief Disable the I2C fast mode plus driving capability. - * @param ConfigFastModePlus: selects the pin. + * @param ConfigFastModePlus Selects the pin. * This parameter can be one of the @ref I2CEx_FastModePlus values * @retval None */ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_i2c_ex.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_i2c_ex.h index 3cd7cabc63..999aeb9e87 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_i2c_ex.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_i2c_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f0xx_hal_i2c_ex.h * @author MCD Application Team - * @version V1.3.1 - * @date 29-January-2016 + * @version V1.4.0 + * @date 27-May-2016 * @brief Header file of I2C HAL Extended module. ****************************************************************************** * @attention @@ -64,7 +64,7 @@ /** @defgroup I2CEx_Analog_Filter I2C Extended Analog Filter * @{ */ -#define I2C_ANALOGFILTER_ENABLE ((uint32_t)0x00000000) +#define I2C_ANALOGFILTER_ENABLE (0x00000000U) #define I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF /** * @} @@ -155,7 +155,7 @@ void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus); #define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \ ((FILTER) == I2C_ANALOGFILTER_DISABLE)) -#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000F) +#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU) #if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F042x6) || defined(STM32F048xx) #define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & (I2C_FASTMODEPLUS_PA9)) == I2C_FASTMODEPLUS_PA9) || \ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_i2s.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_i2s.c index bb01bff753..5e589265d1 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_i2s.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_i2s.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f0xx_hal_i2s.c * @author MCD Application Team - * @version V1.3.1 - * @date 29-January-2016 + * @version V1.4.0 + * @date 27-May-2016 * @brief I2S HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Integrated Interchip Sound (I2S) peripheral: diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_i2s.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_i2s.h index c14690ef2c..e75916d4e4 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_i2s.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_i2s.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f0xx_hal_i2s.h * @author MCD Application Team - * @version V1.3.1 - * @date 29-January-2016 + * @version V1.4.0 + * @date 27-May-2016 * @brief Header file of I2S HAL module. ****************************************************************************** * @attention diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_irda.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_irda.c index cb061bc79e..ddc7747b6f 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_irda.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_irda.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f0xx_hal_irda.c * @author MCD Application Team - * @version V1.3.1 - * @date 29-January-2016 + * @version V1.4.0 + * @date 27-May-2016 * @brief IRDA HAL module driver. * This file provides firmware functions to manage the following * functionalities of the IrDA (Infrared Data Association) Peripheral @@ -208,43 +208,10 @@ static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, (+) For the asynchronous mode only these parameters can be configured: (++) Baud Rate (++) Word Length - (++) Parity: If the parity is enabled, then the MSB bit of the data written - in the data register is transmitted but is changed by the parity bit. - According to device capability (support or not of 7-bit word length), - frame length is either defined by the M bit (8-bits or 9-bits) - or by the M1 and M0 bits (7-bit, 8-bit or 9-bit). - Possible IRDA frame formats are as listed in the following table: - - (+++) Table 1. IRDA frame format. - (+++) +-----------------------------------------------------------------------+ - (+++) | M bit | PCE bit | IRDA frame | - (+++) |-------------------|-----------|---------------------------------------| - (+++) | 0 | 0 | | SB | 8-bit data | STB | | - (+++) |-------------------|-----------|---------------------------------------| - (+++) | 0 | 1 | | SB | 7-bit data | PB | STB | | - (+++) |-------------------|-----------|---------------------------------------| - (+++) | 1 | 0 | | SB | 9-bit data | STB | | - (+++) |-------------------|-----------|---------------------------------------| - (+++) | 1 | 1 | | SB | 8-bit data | PB | STB | | - (+++) +-----------------------------------------------------------------------+ - (+++) | M1 bit | M0 bit | PCE bit | IRDA frame | - (+++) |---------|---------|-----------|---------------------------------------| - (+++) | 0 | 0 | 0 | | SB | 8 bit data | STB | | - (+++) |---------|---------|-----------|---------------------------------------| - (+++) | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | | - (+++) |---------|---------|-----------|---------------------------------------| - (+++) | 0 | 1 | 0 | | SB | 9 bit data | STB | | - (+++) |---------|---------|-----------|---------------------------------------| - (+++) | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | | - (+++) |---------|---------|-----------|---------------------------------------| - (+++) | 1 | 0 | 0 | | SB | 7 bit data | STB | | - (+++) |---------|---------|-----------|---------------------------------------| - (+++) | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | | - (+++) +-----------------------------------------------------------------------+ - - (++) Power mode - (++) Prescaler setting - (++) Receiver/transmitter modes + (++) Parity + (++) Power mode + (++) Prescaler setting + (++) Receiver/transmitter modes [..] The HAL_IRDA_Init() API follows the USART asynchronous configuration procedures @@ -254,6 +221,43 @@ static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, * @{ */ +/* + Additional Table: If the parity is enabled, then the MSB bit of the data written + in the data register is transmitted but is changed by the parity bit. + According to device capability (support or not of 7-bit word length), + frame length is either defined by the M bit (8-bits or 9-bits) + or by the M1 and M0 bits (7-bit, 8-bit or 9-bit). + Possible IRDA frame formats are as listed in the following table: + + Table 1. IRDA frame format. + +-----------------------------------------------------------------------+ + | M bit | PCE bit | IRDA frame | + |-------------------|-----------|---------------------------------------| + | 0 | 0 | | SB | 8-bit data | STB | | + |-------------------|-----------|---------------------------------------| + | 0 | 1 | | SB | 7-bit data | PB | STB | | + |-------------------|-----------|---------------------------------------| + | 1 | 0 | | SB | 9-bit data | STB | | + |-------------------|-----------|---------------------------------------| + | 1 | 1 | | SB | 8-bit data | PB | STB | | + +-----------------------------------------------------------------------+ + | M1 bit | M0 bit | PCE bit | IRDA frame | + |---------|---------|-----------|---------------------------------------| + | 0 | 0 | 0 | | SB | 8 bit data | STB | | + |---------|---------|-----------|---------------------------------------| + | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | | + |---------|---------|-----------|---------------------------------------| + | 0 | 1 | 0 | | SB | 9 bit data | STB | | + |---------|---------|-----------|---------------------------------------| + | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | | + |---------|---------|-----------|---------------------------------------| + | 1 | 0 | 0 | | SB | 7 bit data | STB | | + |---------|---------|-----------|---------------------------------------| + | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | | + +-----------------------------------------------------------------------+ + +*/ + /** * @brief Initialize the IRDA mode according to the specified * parameters in the IRDA_InitTypeDef and initialize the associated handle. @@ -272,7 +276,7 @@ HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda) /* Check the USART/UART associated to the IRDA handle */ assert_param(IS_IRDA_INSTANCE(hirda->Instance)); - if(hirda->State == HAL_IRDA_STATE_RESET) + if(hirda->gState == HAL_IRDA_STATE_RESET) { /* Allocate lock resource and initialize it */ hirda->Lock = HAL_UNLOCKED; @@ -281,7 +285,7 @@ HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda) HAL_IRDA_MspInit(hirda); } - hirda->State = HAL_IRDA_STATE_BUSY; + hirda->gState = HAL_IRDA_STATE_BUSY; /* Disable the Peripheral to update the configuration registers */ __HAL_IRDA_DISABLE(hirda); @@ -304,7 +308,7 @@ HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda) /* Enable the Peripheral */ __HAL_IRDA_ENABLE(hirda); - /* TEACK and/or REACK to check before moving hirda->State to Ready */ + /* TEACK and/or REACK to check before moving hirda->gState and hirda->RxState to Ready */ return (IRDA_CheckIdleState(hirda)); } @@ -325,15 +329,15 @@ HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda) /* Check the USART/UART associated to the IRDA handle */ assert_param(IS_IRDA_INSTANCE(hirda->Instance)); - hirda->State = HAL_IRDA_STATE_BUSY; + hirda->gState = HAL_IRDA_STATE_BUSY; /* DeInit the low level hardware */ HAL_IRDA_MspDeInit(hirda); /* Disable the Peripheral */ __HAL_IRDA_DISABLE(hirda); - hirda->ErrorCode = HAL_IRDA_ERROR_NONE; - hirda->State = HAL_IRDA_STATE_RESET; + hirda->gState = HAL_IRDA_STATE_RESET; + hirda->RxState = HAL_IRDA_STATE_RESET; /* Process Unlock */ __HAL_UNLOCK(hirda); @@ -440,33 +444,42 @@ HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda) * the configuration information for the specified IRDA module. * @param pData: Pointer to data buffer. * @param Size: Amount of data to be sent. - * @param Timeout: Specify timeout value. + * @param Timeout: Timeout duration. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits) + * (as sent data will be handled using u16 pointer cast). Depending on compilation chain, + * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData. * @retval HAL status */ HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout) { uint16_t* tmp; - if((hirda->State == HAL_IRDA_STATE_READY) || (hirda->State == HAL_IRDA_STATE_BUSY_RX)) + /* Check that a Tx process is not already ongoing */ + if(hirda->gState == HAL_IRDA_STATE_READY) { if((pData == NULL) || (Size == 0)) { return HAL_ERROR; } + /* In case of 9bits/No Parity transfer, pData buffer provided as input paramter + should be aligned on a u16 frontier, as data to be filled into TDR will be + handled through a u16 cast. */ + if ((hirda->Init.WordLength == UART_WORDLENGTH_9B) && (hirda->Init.Parity == UART_PARITY_NONE)) + { + if((((uint32_t)pData)&1) != 0) + { + return HAL_ERROR; + } + } + /* Process Locked */ __HAL_LOCK(hirda); hirda->ErrorCode = HAL_IRDA_ERROR_NONE; - if(hirda->State == HAL_IRDA_STATE_BUSY_RX) - { - hirda->State = HAL_IRDA_STATE_BUSY_TX_RX; - } - else - { - hirda->State = HAL_IRDA_STATE_BUSY_TX; - } + hirda->gState = HAL_IRDA_STATE_BUSY_TX; hirda->TxXferSize = Size; hirda->TxXferCount = Size; @@ -495,14 +508,8 @@ HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, u return HAL_TIMEOUT; } - if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX) - { - hirda->State = HAL_IRDA_STATE_BUSY_RX; - } - else - { - hirda->State = HAL_IRDA_STATE_READY; - } + /* At end of Tx process, restore hirda->gState to Ready */ + hirda->gState = HAL_IRDA_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hirda); @@ -521,7 +528,11 @@ HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, u * the configuration information for the specified IRDA module. * @param pData: Pointer to data buffer. * @param Size: Amount of data to be received. - * @param Timeout: Specify timeout value. + * @param Timeout: Timeout duration. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits) + * (as received data will be handled using u16 pointer cast). Depending on compilation chain, + * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData. * @retval HAL status */ HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout) @@ -529,26 +540,31 @@ HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, ui uint16_t* tmp; uint16_t uhMask; - if((hirda->State == HAL_IRDA_STATE_READY) || (hirda->State == HAL_IRDA_STATE_BUSY_TX)) + /* Check that a Rx process is not already ongoing */ + if(hirda->RxState == HAL_IRDA_STATE_READY) { if((pData == NULL) || (Size == 0)) { return HAL_ERROR; } + /* In case of 9bits/No Parity transfer, pData buffer provided as input paramter + should be aligned on a u16 frontier, as data to be received from RDR will be + handled through a u16 cast. */ + if ((hirda->Init.WordLength == UART_WORDLENGTH_9B) && (hirda->Init.Parity == UART_PARITY_NONE)) + { + if((((uint32_t)pData)&1) != 0) + { + return HAL_ERROR; + } + } + /* Process Locked */ __HAL_LOCK(hirda); hirda->ErrorCode = HAL_IRDA_ERROR_NONE; - if(hirda->State == HAL_IRDA_STATE_BUSY_TX) - { - hirda->State = HAL_IRDA_STATE_BUSY_TX_RX; - } - else - { - hirda->State = HAL_IRDA_STATE_BUSY_RX; - } + hirda->RxState = HAL_IRDA_STATE_BUSY_RX; hirda->RxXferSize = Size; hirda->RxXferCount = Size; @@ -579,14 +595,8 @@ HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, ui } } - if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX) - { - hirda->State = HAL_IRDA_STATE_BUSY_TX; - } - else - { - hirda->State = HAL_IRDA_STATE_READY; - } + /* At end of Rx process, restore hirda->RxState to Ready */ + hirda->RxState = HAL_IRDA_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hirda); @@ -605,17 +615,33 @@ HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, ui * the configuration information for the specified IRDA module. * @param pData: Pointer to data buffer. * @param Size: Amount of data to be sent. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits) + * (as sent data will be handled using u16 pointer cast). Depending on compilation chain, + * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData. * @retval HAL status */ HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size) { - if((hirda->State == HAL_IRDA_STATE_READY) || (hirda->State == HAL_IRDA_STATE_BUSY_RX)) + /* Check that a Tx process is not already ongoing */ + if(hirda->gState == HAL_IRDA_STATE_READY) { if((pData == NULL) || (Size == 0)) { return HAL_ERROR; } + /* In case of 9bits/No Parity transfer, pData buffer provided as input paramter + should be aligned on a u16 frontier, as data to be filled into TDR will be + handled through a u16 cast. */ + if ((hirda->Init.WordLength == UART_WORDLENGTH_9B) && (hirda->Init.Parity == UART_PARITY_NONE)) + { + if((((uint32_t)pData)&1) != 0) + { + return HAL_ERROR; + } + } + /* Process Locked */ __HAL_LOCK(hirda); @@ -625,20 +651,11 @@ HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData hirda->ErrorCode = HAL_IRDA_ERROR_NONE; - if(hirda->State == HAL_IRDA_STATE_BUSY_RX) - { - hirda->State = HAL_IRDA_STATE_BUSY_TX_RX; - } - else - { - hirda->State = HAL_IRDA_STATE_BUSY_TX; - } + hirda->gState = HAL_IRDA_STATE_BUSY_TX; /* Process Unlocked */ __HAL_UNLOCK(hirda); - /* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */ - __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_ERR); /* Enable the IRDA Transmit Data Register Empty Interrupt */ __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_TXE); @@ -656,17 +673,33 @@ HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData * the configuration information for the specified IRDA module. * @param pData: Pointer to data buffer. * @param Size: Amount of data to be received. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits) + * (as received data will be handled using u16 pointer cast). Depending on compilation chain, + * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData. * @retval HAL status */ HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size) { - if((hirda->State == HAL_IRDA_STATE_READY) || (hirda->State == HAL_IRDA_STATE_BUSY_TX)) + /* Check that a Rx process is not already ongoing */ + if(hirda->RxState == HAL_IRDA_STATE_READY) { if((pData == NULL) || (Size == 0)) { return HAL_ERROR; } + /* In case of 9bits/No Parity transfer, pData buffer provided as input paramter + should be aligned on a u16 frontier, as data to be received from RDR will be + handled through a u16 cast. */ + if ((hirda->Init.WordLength == UART_WORDLENGTH_9B) && (hirda->Init.Parity == UART_PARITY_NONE)) + { + if((((uint32_t)pData)&1) != 0) + { + return HAL_ERROR; + } + } + /* Process Locked */ __HAL_LOCK(hirda); @@ -680,14 +713,7 @@ HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, hirda->ErrorCode = HAL_IRDA_ERROR_NONE; - if(hirda->State == HAL_IRDA_STATE_BUSY_TX) - { - hirda->State = HAL_IRDA_STATE_BUSY_TX_RX; - } - else - { - hirda->State = HAL_IRDA_STATE_BUSY_RX; - } + hirda->RxState = HAL_IRDA_STATE_BUSY_RX; /* Process Unlocked */ __HAL_UNLOCK(hirda); @@ -715,19 +741,35 @@ HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, * the configuration information for the specified IRDA module. * @param pData: pointer to data buffer. * @param Size: amount of data to be sent. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits) + * (as sent data will be handled by DMA from halfword frontier). Depending on compilation chain, + * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData. * @retval HAL status */ HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size) { uint32_t *tmp; - if((hirda->State == HAL_IRDA_STATE_READY) || (hirda->State == HAL_IRDA_STATE_BUSY_RX)) + /* Check that a Tx process is not already ongoing */ + if(hirda->gState == HAL_IRDA_STATE_READY) { if((pData == NULL) || (Size == 0)) { return HAL_ERROR; } + /* In case of 9bits/No Parity transfer, pData buffer provided as input paramter + should be aligned on a u16 frontier, as data copy into TDR will be + handled by DMA from a u16 frontier. */ + if ((hirda->Init.WordLength == UART_WORDLENGTH_9B) && (hirda->Init.Parity == UART_PARITY_NONE)) + { + if((((uint32_t)pData)&1) != 0) + { + return HAL_ERROR; + } + } + /* Process Locked */ __HAL_LOCK(hirda); @@ -737,14 +779,7 @@ HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pDat hirda->ErrorCode = HAL_IRDA_ERROR_NONE; - if(hirda->State == HAL_IRDA_STATE_BUSY_RX) - { - hirda->State = HAL_IRDA_STATE_BUSY_TX_RX; - } - else - { - hirda->State = HAL_IRDA_STATE_BUSY_TX; - } + hirda->gState = HAL_IRDA_STATE_BUSY_TX; /* Set the IRDA DMA transfer complete callback */ hirda->hdmatx->XferCpltCallback = IRDA_DMATransmitCplt; @@ -783,21 +818,35 @@ HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pDat * the configuration information for the specified IRDA module. * @param pData: Pointer to data buffer. * @param Size: Amount of data to be received. - * @note When the IRDA parity is enabled (PCE = 1) the received data contains - * the parity bit (MSB position). + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits) + * (as received data will be handled by DMA from halfword frontier). Depending on compilation chain, + * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData. * @retval HAL status */ HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size) { uint32_t *tmp; - if((hirda->State == HAL_IRDA_STATE_READY) || (hirda->State == HAL_IRDA_STATE_BUSY_TX)) + /* Check that a Rx process is not already ongoing */ + if(hirda->RxState == HAL_IRDA_STATE_READY) { if((pData == NULL) || (Size == 0)) { return HAL_ERROR; } + /* In case of 9bits/No Parity transfer, pData buffer provided as input paramter + should be aligned on a u16 frontier, as data copy from RDR will be + handled by DMA from a u16 frontier. */ + if ((hirda->Init.WordLength == UART_WORDLENGTH_9B) && (hirda->Init.Parity == UART_PARITY_NONE)) + { + if((((uint32_t)pData)&1) != 0) + { + return HAL_ERROR; + } + } + /* Process Locked */ __HAL_LOCK(hirda); @@ -806,14 +855,7 @@ HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData hirda->ErrorCode = HAL_IRDA_ERROR_NONE; - if(hirda->State == HAL_IRDA_STATE_BUSY_TX) - { - hirda->State = HAL_IRDA_STATE_BUSY_TX_RX; - } - else - { - hirda->State = HAL_IRDA_STATE_BUSY_RX; - } + hirda->RxState = HAL_IRDA_STATE_BUSY_RX; /* Set the IRDA DMA transfer complete callback */ hirda->hdmarx->XferCpltCallback = IRDA_DMAReceiveCplt; @@ -855,28 +897,16 @@ HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda) /* Process Locked */ __HAL_LOCK(hirda); - if(hirda->State == HAL_IRDA_STATE_BUSY_TX) + if(hirda->gState == HAL_IRDA_STATE_BUSY_TX) { /* Disable the IRDA DMA Tx request */ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT); } - else if(hirda->State == HAL_IRDA_STATE_BUSY_RX) + if(hirda->RxState == HAL_IRDA_STATE_BUSY_RX) { /* Disable the IRDA DMA Rx request */ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR); } - else if (hirda->State == HAL_IRDA_STATE_BUSY_TX_RX) - { - /* Disable the IRDA DMA Tx & Rx requests */ - CLEAR_BIT(hirda->Instance->CR3, (USART_CR3_DMAT | USART_CR3_DMAR)); - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(hirda); - - return HAL_ERROR; - } /* Process Unlocked */ __HAL_UNLOCK(hirda); @@ -895,32 +925,18 @@ HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda) /* Process Locked */ __HAL_LOCK(hirda); - if(hirda->State == HAL_IRDA_STATE_BUSY_TX) + if(hirda->gState == HAL_IRDA_STATE_BUSY_TX) { /* Enable the IRDA DMA Tx request */ SET_BIT(hirda->Instance->CR3, USART_CR3_DMAT); } - else if(hirda->State == HAL_IRDA_STATE_BUSY_RX) + if(hirda->RxState == HAL_IRDA_STATE_BUSY_RX) { /* Clear the Overrun flag before resuming the Rx transfer*/ __HAL_IRDA_CLEAR_OREFLAG(hirda); /* Enable the IRDA DMA Rx request */ SET_BIT(hirda->Instance->CR3, USART_CR3_DMAR); } - else if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX) - { - /* Clear the Overrun flag before resuming the Rx transfer*/ - __HAL_IRDA_CLEAR_OREFLAG(hirda); - /* Enable the IRDA DMA Tx & Rx request */ - SET_BIT(hirda->Instance->CR3, (USART_CR3_DMAT | USART_CR3_DMAR)); - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(hirda); - - return HAL_ERROR; - } /* Process Unlocked */ __HAL_UNLOCK(hirda); @@ -959,7 +975,8 @@ HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda) HAL_DMA_Abort(hirda->hdmarx); } - hirda->State = HAL_IRDA_STATE_READY; + hirda->gState = HAL_IRDA_STATE_READY; + hirda->RxState = HAL_IRDA_STATE_READY; return HAL_OK; } @@ -979,8 +996,8 @@ void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda) __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_PEF); hirda->ErrorCode |= HAL_IRDA_ERROR_PE; - /* Set the IRDA state ready to be able to start again the process */ - hirda->State = HAL_IRDA_STATE_READY; + /* Set the IRDA Rx state ready to be able to start again the process */ + hirda->RxState = HAL_IRDA_STATE_READY; } /* IRDA frame error interrupt occurred --------------------------------------*/ @@ -989,8 +1006,8 @@ void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda) __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_FEF); hirda->ErrorCode |= HAL_IRDA_ERROR_FE; - /* Set the IRDA state ready to be able to start again the process */ - hirda->State = HAL_IRDA_STATE_READY; + /* Set the IRDA Rx state ready to be able to start again the process */ + hirda->RxState = HAL_IRDA_STATE_READY; } /* IRDA noise error interrupt occurred --------------------------------------*/ @@ -999,8 +1016,8 @@ void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda) __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_NEF); hirda->ErrorCode |= HAL_IRDA_ERROR_NE; - /* Set the IRDA state ready to be able to start again the process */ - hirda->State = HAL_IRDA_STATE_READY; + /* Set the IRDA Rx state ready to be able to start again the process */ + hirda->RxState = HAL_IRDA_STATE_READY; } /* IRDA Over-Run interrupt occurred -----------------------------------------*/ @@ -1009,8 +1026,8 @@ void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda) __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_OREF); hirda->ErrorCode |= HAL_IRDA_ERROR_ORE; - /* Set the IRDA state ready to be able to start again the process */ - hirda->State = HAL_IRDA_STATE_READY; + /* Set the IRDA Rx state ready to be able to start again the process */ + hirda->RxState = HAL_IRDA_STATE_READY; } /* Call IRDA Error Call back function if need be --------------------------*/ @@ -1023,19 +1040,17 @@ void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda) if((__HAL_IRDA_GET_IT(hirda, IRDA_IT_RXNE) != RESET) && (__HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_RXNE) != RESET)) { IRDA_Receive_IT(hirda); - /* Clear RXNE interrupt flag */ - __HAL_IRDA_SEND_REQ(hirda, IRDA_RXDATA_FLUSH_REQUEST); } /* IRDA in mode Transmitter ------------------------------------------------*/ - if((__HAL_IRDA_GET_IT(hirda, IRDA_IT_TXE) != RESET) &&(__HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_TXE) != RESET)) + if((__HAL_IRDA_GET_IT(hirda, IRDA_IT_TXE) != RESET) &&(__HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_TXE) != RESET)) { IRDA_Transmit_IT(hirda); } /* IRDA in mode Transmitter (transmission end) -----------------------------*/ - if((__HAL_IRDA_GET_IT(hirda, IRDA_IT_TC) != RESET) &&(__HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_TC) != RESET)) + if((__HAL_IRDA_GET_IT(hirda, IRDA_IT_TC) != RESET) &&(__HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_TC) != RESET)) { IRDA_EndTransmit_IT(hirda); } @@ -1146,20 +1161,24 @@ __weak void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda) */ /** - * @brief Return the IRDA handle state. - * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified IRDA module. + * @brief Return the IRDA handle state. + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. * @retval HAL state */ HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda) { /* Return IRDA handle state */ - return hirda->State; + uint32_t temp1= 0x00, temp2 = 0x00; + temp1 = hirda->gState; + temp2 = hirda->RxState; + + return (HAL_IRDA_StateTypeDef)(temp1 | temp2); } /** - * @brief Return the IRDA handle error code. - * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains + * @brief Return the IRDA handle error code. + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. * @retval IRDA Error Code */ @@ -1221,16 +1240,16 @@ static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda) switch (clocksource) { case IRDA_CLOCKSOURCE_PCLK1: - hirda->Instance->BRR = (uint16_t)(HAL_RCC_GetPCLK1Freq() / hirda->Init.BaudRate); + hirda->Instance->BRR = (uint16_t)((HAL_RCC_GetPCLK1Freq() + (hirda->Init.BaudRate/2)) / hirda->Init.BaudRate); break; case IRDA_CLOCKSOURCE_HSI: - hirda->Instance->BRR = (uint16_t)(HSI_VALUE / hirda->Init.BaudRate); + hirda->Instance->BRR = (uint16_t)((HSI_VALUE + (hirda->Init.BaudRate/2)) / hirda->Init.BaudRate); break; case IRDA_CLOCKSOURCE_SYSCLK: - hirda->Instance->BRR = (uint16_t)(HAL_RCC_GetSysClockFreq() / hirda->Init.BaudRate); + hirda->Instance->BRR = (uint16_t)((HAL_RCC_GetSysClockFreq() + (hirda->Init.BaudRate/2)) / hirda->Init.BaudRate); break; case IRDA_CLOCKSOURCE_LSE: - hirda->Instance->BRR = (uint16_t)(LSE_VALUE / hirda->Init.BaudRate); + hirda->Instance->BRR = (uint16_t)((LSE_VALUE + (hirda->Init.BaudRate/2)) / hirda->Init.BaudRate); break; case IRDA_CLOCKSOURCE_UNDEFINED: default: @@ -1257,7 +1276,7 @@ static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda) Bits are defined for some specific devices, and are available only for UART instances supporting WakeUp from Stop Mode feature. */ #if !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC) - if (IS_UART_WAKEUP_INSTANCE(hirda->Instance)) + if (IS_UART_WAKEUP_FROMSTOP_INSTANCE(hirda->Instance)) { /* Check if the Transmitter is enabled */ if((hirda->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) @@ -1284,7 +1303,8 @@ static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda) #endif /* !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC) */ /* Initialize the IRDA state*/ - hirda->State= HAL_IRDA_STATE_READY; + hirda->gState= HAL_IRDA_STATE_READY; + hirda->RxState= HAL_IRDA_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hirda); @@ -1321,7 +1341,8 @@ static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_PE); __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR); - hirda->State= HAL_IRDA_STATE_READY; + hirda->gState= HAL_IRDA_STATE_READY; + hirda->RxState= HAL_IRDA_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hirda); @@ -1346,7 +1367,8 @@ static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_PE); __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR); - hirda->State= HAL_IRDA_STATE_READY; + hirda->gState= HAL_IRDA_STATE_READY; + hirda->RxState= HAL_IRDA_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hirda); @@ -1420,14 +1442,8 @@ static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma) in the IRDA CR3 register */ hirda->Instance->CR3 &= ~(USART_CR3_DMAR); - if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX) - { - hirda->State = HAL_IRDA_STATE_BUSY_TX; - } - else - { - hirda->State = HAL_IRDA_STATE_READY; - } + /* At end of Rx process, restore hirda->RxState to Ready */ + hirda->RxState = HAL_IRDA_STATE_READY; } HAL_IRDA_RxCpltCallback(hirda); @@ -1459,7 +1475,8 @@ static void IRDA_DMAError(DMA_HandleTypeDef *hdma) hirda->RxXferCount = 0; hirda->TxXferCount = 0; hirda->ErrorCode |= HAL_IRDA_ERROR_DMA; - hirda->State= HAL_IRDA_STATE_READY; + hirda->gState= HAL_IRDA_STATE_READY; + hirda->RxState= HAL_IRDA_STATE_READY; HAL_IRDA_ErrorCallback(hirda); } @@ -1477,7 +1494,8 @@ static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda) { uint16_t* tmp; - if((hirda->State == HAL_IRDA_STATE_BUSY_TX) || (hirda->State == HAL_IRDA_STATE_BUSY_TX_RX)) + /* Check that a Tx process is ongoing */ + if(hirda->gState == HAL_IRDA_STATE_BUSY_TX) { if(hirda->TxXferCount == 0) { @@ -1514,8 +1532,8 @@ static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda) /** * @brief Wrap up transmission in non-blocking mode. - * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified IRDA module. + * @param hirda pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. * @retval HAL status */ static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda) @@ -1523,18 +1541,8 @@ static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda) /* Disable the IRDA Transmit Complete Interrupt */ __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TC); - /* Check if a receive process is ongoing or not */ - if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX) - { - hirda->State = HAL_IRDA_STATE_BUSY_RX; - } - else - { - /* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */ - __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR); - - hirda->State = HAL_IRDA_STATE_READY; - } + /* Tx process is ended, restore hirda->gState to Ready */ + hirda->gState = HAL_IRDA_STATE_READY; HAL_IRDA_TxCpltCallback(hirda); @@ -1543,11 +1551,11 @@ static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda) /** - * @brief Receive an amount of data in non-blocking mode. + * @brief Receive an amount of data in non-blocking mode. * Function is called under interruption only, once * interruptions have been enabled by HAL_IRDA_Receive_IT(). - * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified IRDA module. + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. * @retval HAL status */ static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda) @@ -1555,7 +1563,8 @@ static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda) uint16_t* tmp; uint16_t uhMask = hirda->Mask; - if ((hirda->State == HAL_IRDA_STATE_BUSY_RX) || (hirda->State == HAL_IRDA_STATE_BUSY_TX_RX)) + /* Check that a Rx process is ongoing */ + if (hirda->RxState == HAL_IRDA_STATE_BUSY_RX) { if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE)) @@ -1573,20 +1582,14 @@ static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda) { __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_RXNE); - if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX) - { - hirda->State = HAL_IRDA_STATE_BUSY_TX; - } - else - { - /* Disable the IRDA Parity Error Interrupt */ - __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_PE); + /* Disable the IRDA Parity Error Interrupt */ + __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_PE); - /* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */ - __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR); + /* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */ + __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR); - hirda->State = HAL_IRDA_STATE_READY; - } + /* Rx process is completed, restore hirda->RxState to Ready */ + hirda->RxState = HAL_IRDA_STATE_READY; HAL_IRDA_RxCpltCallback(hirda); @@ -1597,6 +1600,9 @@ static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda) } else { + /* Clear RXNE interrupt flag */ + __HAL_IRDA_SEND_REQ(hirda, IRDA_RXDATA_FLUSH_REQUEST); + return HAL_BUSY; } } diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_irda.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_irda.h index 03cc2099d3..20d8e37129 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_irda.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_irda.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f0xx_hal_irda.h * @author MCD Application Team - * @version V1.3.1 - * @date 29-January-2016 + * @version V1.4.0 + * @date 27-May-2016 * @brief This file contains all the functions prototypes for the IRDA * firmware library. ****************************************************************************** @@ -94,17 +94,62 @@ typedef struct /** * @brief HAL IRDA State structures definition + * @note HAL IRDA State value is a combination of 2 different substates: gState and RxState. + * - gState contains IRDA state information related to global Handle management + * and also information related to Tx operations. + * gState value coding follow below described bitmap : + * b7-b6 Error information + * 00 : No Error + * 01 : (Not Used) + * 10 : Timeout + * 11 : Error + * b5 IP initilisation status + * 0 : Reset (IP not initialized) + * 1 : Init done (IP not initialized. HAL IRDA Init function already called) + * b4-b3 (not used) + * xx : Should be set to 00 + * b2 Intrinsic process state + * 0 : Ready + * 1 : Busy (IP busy with some configuration or internal operations) + * b1 (not used) + * x : Should be set to 0 + * b0 Tx state + * 0 : Ready (no Tx operation ongoing) + * 1 : Busy (Tx operation ongoing) + * - RxState contains information related to Rx operations. + * RxState value coding follow below described bitmap : + * b7-b6 (not used) + * xx : Should be set to 00 + * b5 IP initilisation status + * 0 : Reset (IP not initialized) + * 1 : Init done (IP not initialized) + * b4-b2 (not used) + * xxx : Should be set to 000 + * b1 Rx state + * 0 : Ready (no Rx operation ongoing) + * 1 : Busy (Rx operation ongoing) + * b0 (not used) + * x : Should be set to 0. */ typedef enum { - HAL_IRDA_STATE_RESET = 0x00, /*!< Peripheral is not initialized */ - HAL_IRDA_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */ - HAL_IRDA_STATE_BUSY = 0x02, /*!< an internal process is ongoing */ - HAL_IRDA_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */ - HAL_IRDA_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */ - HAL_IRDA_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */ - HAL_IRDA_STATE_TIMEOUT = 0x03, /*!< Timeout state */ - HAL_IRDA_STATE_ERROR = 0x04 /*!< Error */ + HAL_IRDA_STATE_RESET = 0x00U, /*!< Peripheral is not initialized + Value is allowed for gState and RxState */ + HAL_IRDA_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use + Value is allowed for gState and RxState */ + HAL_IRDA_STATE_BUSY = 0x24U, /*!< an internal process is ongoing + Value is allowed for gState only */ + HAL_IRDA_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing + Value is allowed for gState only */ + HAL_IRDA_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing + Value is allowed for RxState only */ + HAL_IRDA_STATE_BUSY_TX_RX = 0x23U, /*!< Data Transmission and Reception process is ongoing + Not to be used for neither gState nor RxState. + Value is result of combination (Or) between gState and RxState values */ + HAL_IRDA_STATE_TIMEOUT = 0xA0U, /*!< Timeout state + Value is allowed for gState only */ + HAL_IRDA_STATE_ERROR = 0xE0U /*!< Error + Value is allowed for gState only */ }HAL_IRDA_StateTypeDef; /** @@ -148,7 +193,13 @@ typedef struct HAL_LockTypeDef Lock; /*!< Locking object */ - __IO HAL_IRDA_StateTypeDef State; /*!< IRDA communication state */ + __IO HAL_IRDA_StateTypeDef gState; /*!< IRDA state information related to global Handle management + and also related to Tx operations. + This parameter can be a value of @ref HAL_IRDA_StateTypeDef */ + + __IO HAL_IRDA_StateTypeDef RxState; /*!< IRDA state information related to Rx operations. + This parameter can be a value of @ref HAL_IRDA_StateTypeDef */ + __IO uint32_t ErrorCode; /*!< IRDA Error code This parameter can be a value of @ref IRDA_Error */ @@ -219,7 +270,7 @@ typedef enum * @} */ - /** @defgroup IRDA_State IRDA State +/** @defgroup IRDA_State IRDA State * @{ */ #define IRDA_STATE_DISABLE ((uint32_t)0x00000000) /*!< IRDA disabled */ @@ -228,7 +279,7 @@ typedef enum * @} */ - /** @defgroup IRDA_Mode IRDA Mode +/** @defgroup IRDA_Mode IRDA Mode * @{ */ #define IRDA_MODE_DISABLE ((uint32_t)0x00000000) /*!< Associated UART disabled in IRDA mode */ @@ -364,7 +415,10 @@ typedef enum * @param __HANDLE__: IRDA handle. * @retval None */ -#define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_IRDA_STATE_RESET) +#define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->gState = HAL_IRDA_STATE_RESET; \ + (__HANDLE__)->RxState = HAL_IRDA_STATE_RESET; \ + } while(0) /** @brief Flush the IRDA DR register. * @param __HANDLE__: specifies the IRDA Handle. @@ -376,7 +430,6 @@ typedef enum SET_BIT((__HANDLE__)->Instance->RQR, IRDA_TXDATA_FLUSH_REQUEST); \ } while(0) - /** @brief Clear the specified IRDA pending flag. * @param __HANDLE__: specifies the IRDA Handle. * @param __FLAG__: specifies the flag to check. diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_irda_ex.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_irda_ex.h index 75ee0cdc58..e8bf7330d6 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_irda_ex.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_irda_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f0xx_hal_irda_ex.h * @author MCD Application Team - * @version V1.3.1 - * @date 29-January-2016 + * @version V1.4.0 + * @date 27-May-2016 * @brief Header file of IRDA HAL Extension module. ****************************************************************************** * @attention diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_iwdg.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_iwdg.c index 567fe9f01a..ffe3a9f275 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_iwdg.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_iwdg.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f0xx_hal_iwdg.c * @author MCD Application Team - * @version V1.3.1 - * @date 29-January-2016 + * @version V1.4.0 + * @date 27-May-2016 * @brief IWDG HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Independent Watchdog (IWDG) peripheral: diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_iwdg.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_iwdg.h index 1fefbbb233..ffaf2ae65e 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_iwdg.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_iwdg.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f0xx_hal_iwdg.h * @author MCD Application Team - * @version V1.3.1 - * @date 29-January-2016 + * @version V1.4.0 + * @date 27-May-2016 * @brief Header file of IWDG HAL module. ****************************************************************************** * @attention diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pcd.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pcd.c index 7e21252d7c..b6c56b6f78 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pcd.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pcd.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f0xx_hal_pcd.c * @author MCD Application Team - * @version V1.3.1 - * @date 29-January-2016 + * @version V1.4.0 + * @date 27-May-2016 * @brief PCD HAL module driver. * This file provides firmware functions to manage the following * functionalities of the USB Peripheral Controller: @@ -199,8 +199,8 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) hpcd->Instance->BTABLE = BTABLE_ADDRESS; /*set wInterrupt_Mask global variable*/ - wInterrupt_Mask = USB_CNTR_CTRM | USB_CNTR_WKUPM | USB_CNTR_SUSPM | USB_CNTR_ERRM \ - | USB_CNTR_ESOFM | USB_CNTR_RESETM; + wInterrupt_Mask = USB_CNTR_CTRM | USB_CNTR_WKUPM | USB_CNTR_SUSPM | USB_CNTR_ERRM \ + | USB_CNTR_SOFM | USB_CNTR_ESOFM | USB_CNTR_RESETM; /*Set interrupt mask*/ hpcd->Instance->CNTR = wInterrupt_Mask; @@ -357,7 +357,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_WKUP)) { - hpcd->Instance->CNTR &= ~(USB_CNTR_LPMODE); + hpcd->Instance->CNTR &= (uint16_t)(~(USB_CNTR_LPMODE)); /*set wInterrupt_Mask global variable*/ wInterrupt_Mask = USB_CNTR_CTRM | USB_CNTR_WKUPM | USB_CNTR_SUSPM | USB_CNTR_ERRM \ @@ -615,7 +615,7 @@ HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd) __HAL_LOCK(hpcd); /* Disable DP Pull-Down bit*/ - hpcd->Instance->BCDR &= ~(USB_BCDR_DPPU); + hpcd->Instance->BCDR &= (uint16_t)(~(USB_BCDR_DPPU)); __HAL_UNLOCK(hpcd); return HAL_OK; @@ -688,6 +688,8 @@ HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint case PCD_EP_TYPE_ISOC: PCD_SET_EPTYPE(hpcd->Instance, ep->num, USB_EP_ISOCHRONOUS); break; + default: + break; } PCD_SET_EP_ADDRESS(hpcd->Instance, ep->num, ep->num); @@ -698,19 +700,19 @@ HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint { /*Set the endpoint Transmit buffer address */ PCD_SET_EP_TX_ADDRESS(hpcd->Instance, ep->num, ep->pmaadress); - PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num); + PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num) /* Configure NAK status for the Endpoint*/ - PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_NAK); + PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_NAK) } else { /*Set the endpoint Receive buffer address */ PCD_SET_EP_RX_ADDRESS(hpcd->Instance, ep->num, ep->pmaadress); /*Set the endpoint Receive buffer counter*/ - PCD_SET_EP_RX_CNT(hpcd->Instance, ep->num, ep->maxpacket); - PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num); + PCD_SET_EP_RX_CNT(hpcd->Instance, ep->num, ep->maxpacket) + PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num) /* Configure VALID status for the Endpoint*/ - PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_VALID); + PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_VALID) } } /*Double Buffer*/ @@ -719,29 +721,29 @@ HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint /*Set the endpoint as double buffered*/ PCD_SET_EP_DBUF(hpcd->Instance, ep->num); /*Set buffer address for double buffered mode*/ - PCD_SET_EP_DBUF_ADDR(hpcd->Instance, ep->num,ep->pmaaddr0, ep->pmaaddr1); + PCD_SET_EP_DBUF_ADDR(hpcd->Instance, ep->num,ep->pmaaddr0, ep->pmaaddr1) if (ep->is_in==0) { /* Clear the data toggle bits for the endpoint IN/OUT*/ - PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num); - PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num); + PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num) + PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num) /* Reset value of the data toggle bits for the endpoint out*/ PCD_TX_DTOG(hpcd->Instance, ep->num); - PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_VALID); - PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS); + PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_VALID) + PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS) } else { /* Clear the data toggle bits for the endpoint IN/OUT*/ - PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num); - PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num); + PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num) + PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num) PCD_RX_DTOG(hpcd->Instance, ep->num); /* Configure DISABLE status for the Endpoint*/ - PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS); - PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_DIS); + PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS) + PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_DIS) } } @@ -778,15 +780,15 @@ HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { if (ep->is_in) { - PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num); + PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num) /* Configure DISABLE status for the Endpoint*/ - PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS); + PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS) } else { - PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num); + PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num) /* Configure DISABLE status for the Endpoint*/ - PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_DIS); + PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_DIS) } } /*Double Buffer*/ @@ -795,24 +797,24 @@ HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) if (ep->is_in==0) { /* Clear the data toggle bits for the endpoint IN/OUT*/ - PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num); - PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num); + PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num) + PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num) /* Reset value of the data toggle bits for the endpoint out*/ PCD_TX_DTOG(hpcd->Instance, ep->num); - PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_DIS); - PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS); + PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_DIS) + PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS) } else { /* Clear the data toggle bits for the endpoint IN/OUT*/ - PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num); - PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num); + PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num) + PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num) PCD_RX_DTOG(hpcd->Instance, ep->num); /* Configure DISABLE status for the Endpoint*/ - PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS); - PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_DIS); + PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS) + PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_DIS) } } @@ -861,15 +863,15 @@ HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, u if (ep->doublebuffer == 0) { /*Set RX buffer count*/ - PCD_SET_EP_RX_CNT(hpcd->Instance, ep->num, len); + PCD_SET_EP_RX_CNT(hpcd->Instance, ep->num, len) } else { /*Set the Double buffer counter*/ - PCD_SET_EP_DBUF_CNT(hpcd->Instance, ep->num, ep->is_in, len); + PCD_SET_EP_DBUF_CNT(hpcd->Instance, ep->num, ep->is_in, len) } - PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_VALID); + PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_VALID) __HAL_UNLOCK(hpcd); @@ -931,24 +933,24 @@ HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, else { /*Write the data to the USB endpoint*/ - if (PCD_GET_ENDPOINT(hpcd->Instance, ep->num)& USB_EP_DTOG_TX) + if ((PCD_GET_ENDPOINT(hpcd->Instance, ep->num)& USB_EP_DTOG_TX) == USB_EP_DTOG_TX) { /*Set the Double buffer counter for pmabuffer1*/ - PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, len); + PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, len) pmabuffer = ep->pmaaddr1; } else { /*Set the Double buffer counter for pmabuffer0*/ - PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, len); + PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, len) pmabuffer = ep->pmaaddr0; } PCD_WritePMA(hpcd->Instance, ep->xfer_buff, pmabuffer, len); - PCD_FreeUserBuffer(hpcd->Instance, ep->num, ep->is_in); + PCD_FreeUserBuffer(hpcd->Instance, ep->num, ep->is_in) } - PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_VALID); + PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_VALID) __HAL_UNLOCK(hpcd); @@ -983,17 +985,17 @@ HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) if (ep->num == 0) { /* This macro sets STALL status for RX & TX*/ - PCD_SET_EP_TXRX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_STALL, USB_EP_TX_STALL); + PCD_SET_EP_TXRX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_STALL, USB_EP_TX_STALL) } else { if (ep->is_in) { - PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num , USB_EP_TX_STALL); + PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num , USB_EP_TX_STALL) } else { - PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num , USB_EP_RX_STALL); + PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num , USB_EP_RX_STALL) } } __HAL_UNLOCK(hpcd); @@ -1028,13 +1030,13 @@ HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) if (ep->is_in) { - PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num); - PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_VALID); + PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num) + PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_VALID) } else { - PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num); - PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_VALID); + PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num) + PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_VALID) } __HAL_UNLOCK(hpcd); @@ -1070,7 +1072,7 @@ HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd) */ HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd) { - hpcd->Instance->CNTR &= ~(USB_CNTR_RESUME); + hpcd->Instance->CNTR &= (uint16_t)(~(USB_CNTR_RESUME)); return HAL_OK; } /** @@ -1122,17 +1124,17 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd) */ void PCD_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes) { - uint32_t n = (wNBytes + 1) >> 1; + uint32_t n = ((uint32_t)((uint32_t)wNBytes + 1)) >> 1; uint32_t i; uint16_t temp1, temp2; uint16_t *pdwVal; - pdwVal = (uint16_t *)(wPMABufAddr + (uint32_t)USBx + 0x400); + pdwVal = (uint16_t *)((uint32_t)(wPMABufAddr + (uint32_t)USBx + 0x400)); for (i = n; i != 0; i--) { temp1 = (uint16_t) * pbUsrBuf; pbUsrBuf++; - temp2 = temp1 | (uint16_t) * pbUsrBuf << 8; + temp2 = temp1 | ((uint16_t)((uint16_t) * pbUsrBuf << 8)) ; *pdwVal++ = temp2; pbUsrBuf++; } @@ -1148,13 +1150,13 @@ void PCD_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, u */ void PCD_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes) { - uint32_t n = (wNBytes + 1) >> 1; + uint32_t n = ((uint32_t)((uint32_t)wNBytes + 1)) >> 1; uint32_t i; uint16_t *pdwVal; - pdwVal = (uint16_t *)(wPMABufAddr + (uint32_t)USBx + 0x400); + pdwVal = (uint16_t *)((uint32_t)(wPMABufAddr + (uint32_t)USBx + 0x400)); for (i = n; i != 0; i--) { - *(uint16_t*)pbUsrBuf++ = *pdwVal++; + *(uint16_t*)((uint32_t)pbUsrBuf++) = *pdwVal++; pbUsrBuf++; } } @@ -1242,8 +1244,8 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) /* Process Control Data OUT Packet*/ HAL_PCD_DataOutStageCallback(hpcd, 0); - PCD_SET_EP_RX_CNT(hpcd->Instance, PCD_ENDP0, ep->maxpacket); - PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID); + PCD_SET_EP_RX_CNT(hpcd->Instance, PCD_ENDP0, ep->maxpacket) + PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID) } } } @@ -1271,7 +1273,8 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) } else { - if (PCD_GET_ENDPOINT(hpcd->Instance, ep->num) & USB_EP_DTOG_RX) + + if ((PCD_GET_ENDPOINT(hpcd->Instance, ep->num)& USB_EP_DTOG_RX) == USB_EP_DTOG_RX) { /*read from endpoint BUF0Addr buffer*/ count = PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num); @@ -1289,7 +1292,7 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) PCD_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, count); } } - PCD_FreeUserBuffer(hpcd->Instance, ep->num, PCD_EP_DBUF_OUT); + PCD_FreeUserBuffer(hpcd->Instance, ep->num, PCD_EP_DBUF_OUT) } /*multi-packet on the NON control OUT endpoint*/ ep->xfer_count+=count; @@ -1325,7 +1328,7 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) } else { - if (PCD_GET_ENDPOINT(hpcd->Instance, ep->num) & USB_EP_DTOG_TX) + if ((PCD_GET_ENDPOINT(hpcd->Instance, ep->num)& USB_EP_DTOG_TX) == USB_EP_DTOG_TX) { /*read from endpoint BUF0Addr buffer*/ ep->xfer_count = PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num); @@ -1343,7 +1346,7 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) PCD_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, ep->xfer_count); } } - PCD_FreeUserBuffer(hpcd->Instance, ep->num, PCD_EP_DBUF_IN); + PCD_FreeUserBuffer(hpcd->Instance, ep->num, PCD_EP_DBUF_IN) } /*multi-packet on the NON control IN endpoint*/ ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num); diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pcd.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pcd.h index 0a5ac450c5..1e6505d4d8 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pcd.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pcd.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f0xx_hal_pcd.h * @author MCD Application Team - * @version V1.3.1 - * @date 29-January-2016 + * @version V1.4.0 + * @date 27-May-2016 * @brief Header file of PCD HAL module. ****************************************************************************** * @attention @@ -219,7 +219,7 @@ typedef struct * @{ */ #define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISTR) & (__INTERRUPT__)) == (__INTERRUPT__)) -#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->ISTR) &= ~(__INTERRUPT__)) +#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISTR) &= (uint16_t)(~(__INTERRUPT__)))) #define __HAL_USB_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= USB_WAKEUP_EXTI_LINE #define __HAL_USB_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_WAKEUP_EXTI_LINE) @@ -377,10 +377,10 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); */ /* SetENDPOINT */ -#define PCD_SET_ENDPOINT(USBx, bEpNum,wRegValue) (*(&(USBx)->EP0R + (bEpNum) * 2)= (uint16_t)(wRegValue)) +#define PCD_SET_ENDPOINT(USBx, bEpNum,wRegValue) (*((uint16_t *)(((uint32_t)(&(USBx)->EP0R + (bEpNum) * 2))))= (uint16_t)(wRegValue)) /* GetENDPOINT */ -#define PCD_GET_ENDPOINT(USBx, bEpNum) (*(&(USBx)->EP0R + (bEpNum) * 2)) +#define PCD_GET_ENDPOINT(USBx, bEpNum) (*((uint16_t *)(((uint32_t)(&(USBx)->EP0R + (bEpNum) * 2))))) @@ -392,7 +392,7 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); * @retval None */ #define PCD_SET_EPTYPE(USBx, bEpNum,wType) (PCD_SET_ENDPOINT((USBx), (bEpNum),\ - ((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_MASK) | (wType) ))) + ((((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & ((uint32_t)(USB_EP_T_MASK))) | ((uint32_t)(wType)) ))) /** * @brief gets the type in the endpoint register(bits EP_TYPE[1:0]) @@ -400,7 +400,7 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); * @param bEpNum: Endpoint Number. * @retval Endpoint Type */ -#define PCD_GET_EPTYPE(USBx, bEpNum) (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_FIELD) +#define PCD_GET_EPTYPE(USBx, bEpNum) (((uint16_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EP_T_FIELD) /** @@ -432,9 +432,9 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); */ #define PCD_GET_DB_DIR(USBx, bEpNum)\ {\ - if ((uint16_t)(*PCD_EP_RX_CNT((USBx), (bEpNum)) & 0xFC00) != 0)\ + if ((uint16_t)(*PCD_EP_RX_CNT((USBx), (bEpNum)) & 0xFC00U) != 0)\ return(PCD_EP_DBUF_OUT);\ - else if (((uint16_t)(*PCD_EP_TX_CNT((USBx), (bEpNum))) & 0x03FF) != 0)\ + else if (((uint16_t)(*PCD_EP_TX_CNT((USBx), (bEpNum))) & 0x03FFU) != 0)\ return(PCD_EP_DBUF_IN);\ else\ return(PCD_EP_DBUF_ERR);\ @@ -447,17 +447,20 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); * @param wState: new state * @retval None */ -#define PCD_SET_EP_TX_STATUS(USBx, bEpNum, wState) {\ - register uint16_t _wRegVal; \ +#define PCD_SET_EP_TX_STATUS(USBx, bEpNum, wState) { register uint16_t _wRegVal;\ \ - _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_DTOGMASK;\ + _wRegVal = (uint32_t) (((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPTX_DTOGMASK);\ /* toggle first bit ? */ \ - if((USB_EPTX_DTOG1 & (wState))!= 0) \ - _wRegVal ^= USB_EPTX_DTOG1; \ + if((USB_EPTX_DTOG1 & (wState))!= 0)\ + { \ + _wRegVal ^=(uint16_t) USB_EPTX_DTOG1; \ + } \ /* toggle second bit ? */ \ - if((USB_EPTX_DTOG2 & (wState))!= 0) \ - _wRegVal ^= USB_EPTX_DTOG2; \ - PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX|USB_EP_CTR_TX)); \ + if((USB_EPTX_DTOG2 & ((uint32_t)(wState)))!= 0) \ + { \ + _wRegVal ^=(uint16_t) USB_EPTX_DTOG2; \ + } \ + PCD_SET_ENDPOINT((USBx), (bEpNum), (((uint32_t)(_wRegVal)) | USB_EP_CTR_RX|USB_EP_CTR_TX));\ } /* PCD_SET_EP_TX_STATUS */ /** @@ -470,14 +473,18 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); #define PCD_SET_EP_RX_STATUS(USBx, bEpNum,wState) {\ register uint16_t _wRegVal; \ \ - _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_DTOGMASK;\ + _wRegVal = (uint32_t) (((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPRX_DTOGMASK);\ /* toggle first bit ? */ \ if((USB_EPRX_DTOG1 & (wState))!= 0) \ - _wRegVal ^= USB_EPRX_DTOG1; \ + { \ + _wRegVal ^= (uint16_t) USB_EPRX_DTOG1; \ + } \ /* toggle second bit ? */ \ - if((USB_EPRX_DTOG2 & (wState))!= 0) \ - _wRegVal ^= USB_EPRX_DTOG2; \ - PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX|USB_EP_CTR_TX)); \ + if((USB_EPRX_DTOG2 & ((uint32_t)(wState)))!= 0) \ + { \ + _wRegVal ^= (uint16_t) USB_EPRX_DTOG2; \ + } \ + PCD_SET_ENDPOINT((USBx), (bEpNum), (((uint32_t)(_wRegVal)) | USB_EP_CTR_RX|USB_EP_CTR_TX)); \ } /* PCD_SET_EP_RX_STATUS */ /** @@ -494,16 +501,24 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (USB_EPRX_DTOGMASK |USB_EPTX_STAT) ;\ /* toggle first bit ? */ \ if((USB_EPRX_DTOG1 & ((wStaterx)))!= 0) \ + { \ _wRegVal ^= USB_EPRX_DTOG1; \ + } \ /* toggle second bit ? */ \ if((USB_EPRX_DTOG2 & (wStaterx))!= 0) \ + { \ _wRegVal ^= USB_EPRX_DTOG2; \ + } \ /* toggle first bit ? */ \ if((USB_EPTX_DTOG1 & (wStatetx))!= 0) \ + { \ _wRegVal ^= USB_EPTX_DTOG1; \ + } \ /* toggle second bit ? */ \ if((USB_EPTX_DTOG2 & (wStatetx))!= 0) \ + { \ _wRegVal ^= USB_EPTX_DTOG2; \ + } \ PCD_SET_ENDPOINT((USBx), (bEpNum), _wRegVal | USB_EP_CTR_RX|USB_EP_CTR_TX); \ } /* PCD_SET_EP_TXRX_STATUS */ @@ -514,9 +529,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); * @param bEpNum: Endpoint Number. * @retval status */ -#define PCD_GET_EP_TX_STATUS(USBx, bEpNum) ((uint16_t)PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_STAT) - -#define PCD_GET_EP_RX_STATUS(USBx, bEpNum) ((uint16_t)PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_STAT) +#define PCD_GET_EP_TX_STATUS(USBx, bEpNum) (((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPTX_STAT) +#define PCD_GET_EP_RX_STATUS(USBx, bEpNum) (((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPRX_STAT) /** * @brief sets directly the VALID tx/rx-status into the endpoint register @@ -525,7 +539,6 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); * @retval None */ #define PCD_SET_EP_TX_VALID(USBx, bEpNum) (PCD_SET_EP_TX_STATUS((USBx), (bEpNum), USB_EP_TX_VALID)) - #define PCD_SET_EP_RX_VALID(USBx, bEpNum) (PCD_SET_EP_RX_STATUS((USBx), (bEpNum), USB_EP_RX_VALID)) /** @@ -546,9 +559,9 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); * @retval None */ #define PCD_SET_EP_KIND(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum), \ - (USB_EP_CTR_RX|USB_EP_CTR_TX|((PCD_GET_ENDPOINT((USBx), (bEpNum)) | USB_EP_KIND) & USB_EPREG_MASK)))) + (USB_EP_CTR_RX|USB_EP_CTR_TX|((((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) | USB_EP_KIND) & USB_EPREG_MASK)))) #define PCD_CLEAR_EP_KIND(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum), \ - (USB_EP_CTR_RX|USB_EP_CTR_TX|(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPKIND_MASK)))) + (USB_EP_CTR_RX|USB_EP_CTR_TX|((((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPKIND_MASK)))) /** * @brief Sets/clears directly STATUS_OUT bit in the endpoint register. @@ -575,9 +588,9 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); * @retval None */ #define PCD_CLEAR_RX_EP_CTR(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum),\ - PCD_GET_ENDPOINT((USBx), (bEpNum)) & 0x7FFF & USB_EPREG_MASK)) + PCD_GET_ENDPOINT((USBx), (bEpNum)) & 0x7FFFU & USB_EPREG_MASK)) #define PCD_CLEAR_TX_EP_CTR(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum),\ - PCD_GET_ENDPOINT((USBx), (bEpNum)) & 0xFF7F & USB_EPREG_MASK)) + PCD_GET_ENDPOINT((USBx), (bEpNum)) & 0xFF7FU & USB_EPREG_MASK)) /** * @brief Toggles DTOG_RX / DTOG_TX bit in the endpoint register. @@ -586,9 +599,9 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); * @retval None */ #define PCD_RX_DTOG(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum), \ - USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_RX | (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK))) + USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_RX | (((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPREG_MASK))) #define PCD_TX_DTOG(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum), \ - USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_TX | (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK))) + USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_TX | (((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPREG_MASK))) /** * @brief Clears DTOG_RX / DTOG_TX bit in the endpoint register. @@ -596,10 +609,14 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); * @param bEpNum: Endpoint Number. * @retval None */ -#define PCD_CLEAR_RX_DTOG(USBx, bEpNum) if((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_DTOG_RX) != 0)\ - PCD_RX_DTOG((USBx), (bEpNum)) -#define PCD_CLEAR_TX_DTOG(USBx, bEpNum) if((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_DTOG_TX) != 0)\ - PCD_TX_DTOG((USBx), (bEpNum)) +#define PCD_CLEAR_RX_DTOG(USBx, bEpNum) if((((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EP_DTOG_RX) != 0)\ + { \ + PCD_RX_DTOG((USBx),(bEpNum));\ + } +#define PCD_CLEAR_TX_DTOG(USBx, bEpNum) if((((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EP_DTOG_TX) != 0)\ + {\ + PCD_TX_DTOG((USBx),(bEpNum));\ + } /** * @brief Sets address in an endpoint register. @@ -609,7 +626,7 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); * @retval None */ #define PCD_SET_EP_ADDRESS(USBx, bEpNum,bAddr) PCD_SET_ENDPOINT((USBx), (bEpNum),\ - USB_EP_CTR_RX|USB_EP_CTR_TX|(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK) | (bAddr)) + USB_EP_CTR_RX|USB_EP_CTR_TX|(((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPREG_MASK) | (bAddr)) /** * @brief Gets address in an endpoint register. @@ -619,10 +636,11 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); */ #define PCD_GET_EP_ADDRESS(USBx, bEpNum) ((uint8_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPADDR_FIELD)) -#define PCD_EP_TX_ADDRESS(USBx, bEpNum) ((uint16_t *)(((USBx)->BTABLE+(bEpNum)*8)+ ((uint32_t)(USBx) + 0x400))) -#define PCD_EP_TX_CNT(USBx, bEpNum) ((uint16_t *)(((USBx)->BTABLE+(bEpNum)*8+2)+ ((uint32_t)(USBx) + 0x400))) -#define PCD_EP_RX_ADDRESS(USBx, bEpNum) ((uint16_t *)(((USBx)->BTABLE+(bEpNum)*8+4)+ ((uint32_t)(USBx) + 0x400))) -#define PCD_EP_RX_CNT(USBx, bEpNum) ((uint16_t *)(((USBx)->BTABLE+(bEpNum)*8+6)+ ((uint32_t)(USBx) + 0x400))) +#define PCD_EP_TX_ADDRESS(USBx, bEpNum) ((uint16_t *)((uint32_t)((((USBx)->BTABLE+(bEpNum)*8)+ ((uint32_t)(USBx) + 0x400))))) +#define PCD_EP_TX_CNT(USBx, bEpNum) ((uint16_t *)((uint32_t)((((USBx)->BTABLE+(bEpNum)*8+2)+ ((uint32_t)(USBx) + 0x400))))) +#define PCD_EP_RX_ADDRESS(USBx, bEpNum) ((uint16_t *)((uint32_t)((((USBx)->BTABLE+(bEpNum)*8+4)+ ((uint32_t)(USBx) + 0x400))))) + +#define PCD_EP_RX_CNT(USBx, bEpNum) ((uint16_t *)((uint32_t)((((USBx)->BTABLE+(bEpNum)*8+6)+ ((uint32_t)(USBx) + 0x400))))) /** * @brief sets address of the tx/rx buffer. @@ -653,27 +671,41 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); #define PCD_CALC_BLK32(dwReg,wCount,wNBlocks) {\ (wNBlocks) = (wCount) >> 5;\ if(((wCount) & 0x1f) == 0)\ + { \ (wNBlocks)--;\ - *pdwReg = (uint16_t)(((wNBlocks) << 10) | 0x8000);\ + } \ + *pdwReg = (uint16_t)((uint16_t)((wNBlocks) << 10) | (uint16_t)0x8000); \ }/* PCD_CALC_BLK32 */ + #define PCD_CALC_BLK2(dwReg,wCount,wNBlocks) {\ (wNBlocks) = (wCount) >> 1;\ if(((wCount) & 0x1) != 0)\ + { \ (wNBlocks)++;\ + } \ *pdwReg = (uint16_t)((wNBlocks) << 10);\ }/* PCD_CALC_BLK2 */ + #define PCD_SET_EP_CNT_RX_REG(dwReg,wCount) {\ uint16_t wNBlocks;\ - if((wCount) > 62){PCD_CALC_BLK32((dwReg),(wCount),wNBlocks);}\ - else {PCD_CALC_BLK2((dwReg),(wCount),wNBlocks);}\ + if((wCount) > 62) \ + { \ + PCD_CALC_BLK32((dwReg),(wCount),wNBlocks) \ + } \ + else \ + { \ + PCD_CALC_BLK2((dwReg),(wCount),wNBlocks) \ + } \ }/* PCD_SET_EP_CNT_RX_REG */ + #define PCD_SET_EP_RX_DBUF0_CNT(USBx, bEpNum,wCount) {\ uint16_t *pdwReg = PCD_EP_TX_CNT((USBx), (bEpNum)); \ - PCD_SET_EP_CNT_RX_REG(pdwReg, (wCount));\ + PCD_SET_EP_CNT_RX_REG(pdwReg, (wCount))\ } + /** * @brief sets counter for the tx/rx buffer. * @param USBx: USB peripheral instance register address. @@ -683,8 +715,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); */ #define PCD_SET_EP_TX_CNT(USBx, bEpNum,wCount) (*PCD_EP_TX_CNT((USBx), (bEpNum)) = (wCount)) #define PCD_SET_EP_RX_CNT(USBx, bEpNum,wCount) {\ - uint16_t *pdwReg = PCD_EP_RX_CNT(USBx, bEpNum); \ - PCD_SET_EP_CNT_RX_REG(pdwReg, wCount);\ + uint16_t *pdwReg =PCD_EP_RX_CNT((USBx),(bEpNum)); \ + PCD_SET_EP_CNT_RX_REG((pdwReg), (wCount))\ } /** @@ -703,8 +735,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); * @param wBuf0Addr: buffer 0 address. * @retval Counter value */ -#define PCD_SET_EP_DBUF0_ADDR(USBx, bEpNum,wBuf0Addr) {PCD_SET_EP_TX_ADDRESS((USBx), (bEpNum), (wBuf0Addr));} -#define PCD_SET_EP_DBUF1_ADDR(USBx, bEpNum,wBuf1Addr) {PCD_SET_EP_RX_ADDRESS((USBx), (bEpNum), (wBuf1Addr));} +#define PCD_SET_EP_DBUF0_ADDR(USBx, bEpNum,wBuf0Addr) (PCD_SET_EP_TX_ADDRESS((USBx), (bEpNum), (wBuf0Addr))) +#define PCD_SET_EP_DBUF1_ADDR(USBx, bEpNum,wBuf1Addr) (PCD_SET_EP_RX_ADDRESS((USBx), (bEpNum), (wBuf1Addr))) /** * @brief Sets addresses in a double buffer endpoint. @@ -740,24 +772,27 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); #define PCD_SET_EP_DBUF0_CNT(USBx, bEpNum, bDir, wCount) { \ if((bDir) == PCD_EP_DBUF_OUT)\ /* OUT endpoint */ \ - {PCD_SET_EP_RX_DBUF0_CNT((USBx), (bEpNum),(wCount));} \ + {PCD_SET_EP_RX_DBUF0_CNT((USBx), (bEpNum),(wCount))} \ else if((bDir) == PCD_EP_DBUF_IN)\ - /* IN endpoint */ \ + { \ *PCD_EP_TX_CNT((USBx), (bEpNum)) = (uint32_t)(wCount); \ + } \ } /* SetEPDblBuf0Count*/ #define PCD_SET_EP_DBUF1_CNT(USBx, bEpNum, bDir, wCount) { \ if((bDir) == PCD_EP_DBUF_OUT)\ - /* OUT endpoint */ \ - {PCD_SET_EP_RX_CNT((USBx), (bEpNum),(wCount));}\ + {/* OUT endpoint */ \ + PCD_SET_EP_RX_CNT((USBx), (bEpNum),(wCount)) \ + } \ else if((bDir) == PCD_EP_DBUF_IN)\ - /* IN endpoint */\ + {/* IN endpoint */ \ *PCD_EP_TX_CNT((USBx), (bEpNum)) = (uint32_t)(wCount); \ - } /* SetEPDblBuf1Count */ + } \ + } /* SetEPDblBuf1Count */ #define PCD_SET_EP_DBUF_CNT(USBx, bEpNum, bDir, wCount) {\ - PCD_SET_EP_DBUF0_CNT((USBx), (bEpNum), (bDir), (wCount)); \ - PCD_SET_EP_DBUF1_CNT((USBx), (bEpNum), (bDir), (wCount)); \ + PCD_SET_EP_DBUF0_CNT((USBx), (bEpNum), (bDir), (wCount)) \ + PCD_SET_EP_DBUF1_CNT((USBx), (bEpNum), (bDir), (wCount)) \ } /* PCD_SET_EP_DBUF_CNT */ /** diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pcd_ex.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pcd_ex.c index 626d76c0cc..1ed2554af5 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pcd_ex.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pcd_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f0xx_hal_pcd_ex.c * @author MCD Application Team - * @version V1.3.1 - * @date 29-January-2016 + * @version V1.4.0 + * @date 27-May-2016 * @brief Extended PCD HAL module driver. * This file provides firmware functions to manage the following * functionalities of the USB Peripheral Controller: @@ -42,14 +42,14 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32f0xx_hal.h" -/** @addtogroup STM32F0xx_HAL_Driver - * @{ - */ - #ifdef HAL_PCD_MODULE_ENABLED #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)|| defined(STM32F070x6) +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + /** @defgroup PCDEx PCDEx * @brief PCD Extended HAL module driver * @{ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pcd_ex.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pcd_ex.h index 6fc98660eb..97b8846c7e 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pcd_ex.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pcd_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f0xx_hal_pcd_ex.h * @author MCD Application Team - * @version V1.3.1 - * @date 29-January-2016 + * @version V1.4.0 + * @date 27-May-2016 * @brief Header file of PCD HAL Extension module. ****************************************************************************** * @attention diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pwr.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pwr.c index e195c16d38..8054cdcd2e 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pwr.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pwr.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f0xx_hal_pwr.c * @author MCD Application Team - * @version V1.3.1 - * @date 29-January-2016 + * @version V1.4.0 + * @date 27-May-2016 * @brief PWR HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Power Controller (PWR) peripheral: @@ -250,7 +250,8 @@ void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx) { /* Check the parameters */ assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx)); - PWR->CSR |= (PWR_CSR_EWUP1 << (uint8_t)WakeUpPinx); + /* Enable the EWUPx pin */ + SET_BIT(PWR->CSR, WakeUpPinx); } /** @@ -264,7 +265,8 @@ void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx) { /* Check the parameters */ assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx)); - PWR->CSR &= ~(PWR_CSR_EWUP1 << (uint8_t)WakeUpPinx); + /* Disable the EWUPx pin */ + CLEAR_BIT(PWR->CSR, WakeUpPinx); } /** diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pwr.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pwr.h index f24a1191ac..ab284a7dc6 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pwr.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pwr.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f0xx_hal_pwr.h * @author MCD Application Team - * @version V1.3.1 - * @date 29-January-2016 + * @version V1.4.0 + * @date 27-May-2016 * @brief Header file of PWR HAL module. ****************************************************************************** * @attention diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pwr_ex.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pwr_ex.c index 3392775f86..b9d75ad446 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pwr_ex.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pwr_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f0xx_hal_pwr_ex.c * @author MCD Application Team - * @version V1.3.1 - * @date 29-January-2016 + * @version V1.4.0 + * @date 27-May-2016 * @brief Extended PWR HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Power Controller (PWR) peripheral: diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pwr_ex.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pwr_ex.h index ec2f5f5d4c..de59a9b407 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pwr_ex.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pwr_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f0xx_hal_pwr_ex.h * @author MCD Application Team - * @version V1.3.1 - * @date 29-January-2016 + * @version V1.4.0 + * @date 27-May-2016 * @brief Header file of PWR HAL Extension module. ****************************************************************************** * @attention @@ -92,16 +92,16 @@ typedef struct /** @defgroup PWREx_WakeUp_Pins PWREx Wakeup Pins * @{ */ -#if defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || defined (STM32F070xB) || \ - defined (STM32F091xC) || defined (STM32F098xx) || defined (STM32F030xC) -#define PWR_WAKEUP_PIN1 ((uint32_t)0x00) -#define PWR_WAKEUP_PIN2 ((uint32_t)0x01) -#define PWR_WAKEUP_PIN3 ((uint32_t)0x02) -#define PWR_WAKEUP_PIN4 ((uint32_t)0x03) -#define PWR_WAKEUP_PIN5 ((uint32_t)0x04) -#define PWR_WAKEUP_PIN6 ((uint32_t)0x05) -#define PWR_WAKEUP_PIN7 ((uint32_t)0x06) -#define PWR_WAKEUP_PIN8 ((uint32_t)0x07) +#if defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \ + defined (STM32F091xC) || defined (STM32F098xx) +#define PWR_WAKEUP_PIN1 ((uint32_t)PWR_CSR_EWUP1) +#define PWR_WAKEUP_PIN2 ((uint32_t)PWR_CSR_EWUP2) +#define PWR_WAKEUP_PIN3 ((uint32_t)PWR_CSR_EWUP3) +#define PWR_WAKEUP_PIN4 ((uint32_t)PWR_CSR_EWUP4) +#define PWR_WAKEUP_PIN5 ((uint32_t)PWR_CSR_EWUP5) +#define PWR_WAKEUP_PIN6 ((uint32_t)PWR_CSR_EWUP6) +#define PWR_WAKEUP_PIN7 ((uint32_t)PWR_CSR_EWUP7) +#define PWR_WAKEUP_PIN8 ((uint32_t)PWR_CSR_EWUP8) #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \ ((PIN) == PWR_WAKEUP_PIN2) || \ @@ -111,14 +111,45 @@ typedef struct ((PIN) == PWR_WAKEUP_PIN6) || \ ((PIN) == PWR_WAKEUP_PIN7) || \ ((PIN) == PWR_WAKEUP_PIN8)) -#else -#define PWR_WAKEUP_PIN1 ((uint32_t)0x00) -#define PWR_WAKEUP_PIN2 ((uint32_t)0x01) + +#elif defined(STM32F030xC) || defined (STM32F070xB) +#define PWR_WAKEUP_PIN1 ((uint32_t)PWR_CSR_EWUP1) +#define PWR_WAKEUP_PIN2 ((uint32_t)PWR_CSR_EWUP2) +#define PWR_WAKEUP_PIN4 ((uint32_t)PWR_CSR_EWUP4) +#define PWR_WAKEUP_PIN5 ((uint32_t)PWR_CSR_EWUP5) +#define PWR_WAKEUP_PIN6 ((uint32_t)PWR_CSR_EWUP6) +#define PWR_WAKEUP_PIN7 ((uint32_t)PWR_CSR_EWUP7) + +#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \ + ((PIN) == PWR_WAKEUP_PIN2) || \ + ((PIN) == PWR_WAKEUP_PIN4) || \ + ((PIN) == PWR_WAKEUP_PIN5) || \ + ((PIN) == PWR_WAKEUP_PIN6) || \ + ((PIN) == PWR_WAKEUP_PIN7)) + +#elif defined(STM32F042x6) || defined (STM32F048xx) +#define PWR_WAKEUP_PIN1 ((uint32_t)PWR_CSR_EWUP1) +#define PWR_WAKEUP_PIN2 ((uint32_t)PWR_CSR_EWUP2) +#define PWR_WAKEUP_PIN4 ((uint32_t)PWR_CSR_EWUP4) +#define PWR_WAKEUP_PIN6 ((uint32_t)PWR_CSR_EWUP6) +#define PWR_WAKEUP_PIN7 ((uint32_t)PWR_CSR_EWUP7) + +#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \ + ((PIN) == PWR_WAKEUP_PIN2) || \ + ((PIN) == PWR_WAKEUP_PIN4) || \ + ((PIN) == PWR_WAKEUP_PIN6) || \ + ((PIN) == PWR_WAKEUP_PIN7)) + +#else +#define PWR_WAKEUP_PIN1 ((uint32_t)PWR_CSR_EWUP1) +#define PWR_WAKEUP_PIN2 ((uint32_t)PWR_CSR_EWUP2) + #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \ ((PIN) == PWR_WAKEUP_PIN2)) -#endif /* defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || defined (STM32F070xB) || */ - /* defined (STM32F091xC) || defined (STM32F098xx) || defined (STM32F030xC) */ + +#endif + /** * @} */ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rcc.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rcc.c index cdb54ac804..09a55ab6d3 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rcc.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rcc.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f0xx_hal_rcc.c * @author MCD Application Team - * @version V1.3.1 - * @date 29-January-2016 + * @version V1.4.0 + * @date 27-May-2016 * @brief RCC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Reset and Clock Control (RCC) peripheral: @@ -75,7 +75,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** -*/ +*/ /* Includes ------------------------------------------------------------------*/ #include "stm32f0xx_hal.h" @@ -116,7 +116,6 @@ /** @defgroup RCC_Private_Variables RCC Private Variables * @{ */ -const uint8_t aAPBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; /** * @} */ @@ -193,7 +192,16 @@ const uint8_t aAPBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, (++) IWDG clock which is always the LSI clock. (#) For the STM32F0xx devices, the maximum frequency of the SYSCLK, HCLK and PCLK1 is 48 MHz, - Depending on the SYSCLK frequency, the flash latency should be adapted accordingly: + Depending on the SYSCLK frequency, the flash latency should be adapted accordingly. + + (#) After reset, the System clock source is the HSI (8 MHz) with 0 WS and + prefetch is disabled. + @endverbatim + * @{ + */ + +/* + Additional consideration on the SYSCLK based on Latency settings: +-----------------------------------------------+ | Latency | SYSCLK clock frequency (MHz) | |---------------|-------------------------------| @@ -201,11 +209,6 @@ const uint8_t aAPBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, |---------------|-------------------------------| |1WS(2CPU cycle)| 24 < SYSCLK <= 48 | +-----------------------------------------------+ - - (#) After reset, the System clock source is the HSI (8 MHz) with 0 WS and - prefetch is disabled. - @endverbatim - * @{ */ /** @@ -216,9 +219,9 @@ const uint8_t aAPBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, * - AHB, APB1 prescaler set to 1. * - CSS and MCO1 OFF * - All interrupts disabled - * @note This function doesn't modify the configuration of the - * - Peripheral clocks - * - LSI, LSE and RTC clocks + * @note This function does not modify the configuration of the + * - Peripheral clocks + * - LSI, LSE and RTC clocks * @retval None */ void HAL_RCC_DeInit(void) @@ -246,6 +249,9 @@ void HAL_RCC_DeInit(void) /* Disable all interrupts */ CLEAR_REG(RCC->CIR); + + /* Update the SystemCoreClock global variable */ + SystemCoreClock = HSI_VALUE; } /** @@ -254,6 +260,12 @@ void HAL_RCC_DeInit(void) * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that * contains the configuration information for the RCC Oscillators. * @note The PLL is not disabled when used as system clock. + * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not + * supported by this macro. User should request a transition to LSE Off + * first and then LSE On or LSE Bypass. + * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not + * supported by this macro. User should request a transition to HSE Off + * first and then HSE On or HSE Bypass. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) @@ -281,21 +293,6 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) } else { - /* Reset HSEON and HSEBYP bits before configuring the HSE --------------*/ - __HAL_RCC_HSE_CONFIG(RCC_HSE_OFF); - - /* Get Start Tick */ - tickstart = HAL_GetTick(); - - /* Wait till HSE is disabled */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) - { - if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - /* Set the new HSE configuration ---------------------------------------*/ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); @@ -320,7 +317,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) /* Get Start Tick */ tickstart = HAL_GetTick(); - /* Wait till HSE is bypassed or disabled */ + /* Wait till HSE is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) { if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) @@ -441,41 +438,36 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) /*------------------------------ LSE Configuration -------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) { + FlagStatus pwrclkchanged = RESET; + /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); - - /* Enable Power Clock*/ - __HAL_RCC_PWR_CLK_ENABLE(); - - /* Enable write access to Backup domain */ - SET_BIT(PWR->CR, PWR_CR_DBP); - /* Wait for Backup domain Write protection disable */ - tickstart = HAL_GetTick(); - - while((PWR->CR & PWR_CR_DBP) == RESET) + /* Update LSE configuration in Backup Domain control register */ + /* Requires to enable write access to Backup Domain of necessary */ + if(__HAL_RCC_PWR_IS_CLK_DISABLED()) { - if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } + __HAL_RCC_PWR_CLK_ENABLE(); + pwrclkchanged = SET; } - /* Reset LSEON and LSEBYP bits before configuring the LSE ----------------*/ - __HAL_RCC_LSE_CONFIG(RCC_LSE_OFF); - - /* Get Start Tick */ - tickstart = HAL_GetTick(); - - /* Wait till LSE is disabled */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) + if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) { - if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) + /* Enable write access to Backup domain */ + SET_BIT(PWR->CR, PWR_CR_DBP); + + /* Wait for Backup domain Write protection disable */ + tickstart = HAL_GetTick(); + + while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) { - return HAL_TIMEOUT; + if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } } } - + /* Set the new LSE configuration -----------------------------------------*/ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); /* Check the LSE State */ @@ -507,6 +499,12 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) } } } + + /* Require to disable power clock if necessary */ + if(pwrclkchanged == SET) + { + __HAL_RCC_PWR_CLK_DISABLE(); + } } /*----------------------------- HSI14 Configuration --------------------------*/ @@ -570,7 +568,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) } } -#if defined(RCC_CR2_HSI48ON) +#if defined(RCC_HSI48_SUPPORT) /*----------------------------- HSI48 Configuration --------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) { @@ -588,7 +586,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) } else { - /* Check the HSI State */ + /* Check the HSI48 State */ if(RCC_OscInitStruct->HSI48State != RCC_HSI48_OFF) { /* Enable the Internal High Speed oscillator (HSI48). */ @@ -597,7 +595,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) /* Get Start Tick */ tickstart = HAL_GetTick(); - /* Wait till HSI is ready */ + /* Wait till HSI48 is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == RESET) { if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) @@ -614,7 +612,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) /* Get Start Tick */ tickstart = HAL_GetTick(); - /* Wait till HSI is ready */ + /* Wait till HSI48 is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != RESET) { if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) @@ -625,7 +623,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) } } } -#endif /* RCC_CR2_HSI48ON */ +#endif /* RCC_HSI48_SUPPORT */ /*-------------------------------- PLL Configuration -----------------------*/ /* Check the parameters */ @@ -783,7 +781,7 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui return HAL_ERROR; } } -#if defined(RCC_CR2_HSI48ON) +#if defined(RCC_CFGR_SWS_HSI48) /* HSI48 is selected as System Clock Source */ else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI48) { @@ -793,7 +791,7 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui return HAL_ERROR; } } -#endif /* RCC_CR2_HSI48ON */ +#endif /* RCC_CFGR_SWS_HSI48 */ /* HSI is selected as System Clock Source */ else { @@ -828,7 +826,7 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui } } } -#if defined(RCC_CR2_HSI48ON) +#if defined(RCC_CFGR_SWS_HSI48) else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI48) { while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI48) @@ -839,7 +837,7 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui } } } -#endif /* RCC_CR2_HSI48ON */ +#endif /* RCC_CFGR_SWS_HSI48 */ else { while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI) @@ -865,7 +863,6 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui } } - /*-------------------------- PCLK1 Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) { @@ -873,6 +870,9 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_ClkInitStruct->APB1CLKDivider); } + /* Update the SystemCoreClock global variable */ + SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_BITNUMBER]; + /* Configure the source of time base considering new system clocks settings*/ HAL_InitTick (TICK_INT_PRIORITY); @@ -883,8 +883,8 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui * @} */ -/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions - * @brief RCC clocks control functions +/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions + * @brief RCC clocks control functions * @verbatim =============================================================================== @@ -904,7 +904,7 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui * @note MCO pin should be configured in alternate function mode. * @param RCC_MCOx specifies the output direction for the clock source. * This parameter can be one of the following values: - * @arg @ref RCC_MCO Clock source to output on MCO1 pin(PA8). + * @arg @ref RCC_MCO1 Clock source to output on MCO1 pin(PA8). * @param RCC_MCOSource specifies the clock source to output. * This parameter can be one of the following values: * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected @@ -916,20 +916,38 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui * @arg @ref RCC_MCO1SOURCE_HSI14 HSI14 selected as MCO clock @if STM32F042x6 * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock @elseif STM32F048xx * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock @elseif STM32F071xB * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock @elseif STM32F072xB * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock @elseif STM32F078xx * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock @elseif STM32F091xC * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock @elseif STM32F098xx * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock + @elif STM32F030x6 + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock + @elif STM32F030xC + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock + @elif STM32F031x6 + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock + @elif STM32F038xx + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock + @elif STM32F070x6 + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock + @elif STM32F070xB + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock @endif - * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock (not applicable to STM32F05x devices) * @arg @ref RCC_MCO1SOURCE_PLLCLK_DIV2 PLLCLK Divided by 2 selected as MCO clock * @param RCC_MCODiv specifies the MCO DIV. * This parameter can be one of the following values: @@ -949,7 +967,7 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui * @note MCO pin should be configured in alternate function mode. * @param RCC_MCOx specifies the output direction for the clock source. * This parameter can be one of the following values: - * @arg @ref RCC_MCO Clock source to output on MCO1 pin(PA8). + * @arg @ref RCC_MCO1 Clock source to output on MCO1 pin(PA8). * @param RCC_MCOSource specifies the clock source to output. * This parameter can be one of the following values: * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock @@ -975,15 +993,16 @@ void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_M assert_param(IS_RCC_MCODIV(RCC_MCODiv)); assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource)); - /* MCO Clock Enable */ - MCO1_CLK_ENABLE(); - /* Configure the MCO1 pin in alternate function mode */ - gpio.Pin = MCO1_PIN; gpio.Mode = GPIO_MODE_AF_PP; gpio.Speed = GPIO_SPEED_FREQ_HIGH; gpio.Pull = GPIO_NOPULL; + gpio.Pin = MCO1_PIN; gpio.Alternate = GPIO_AF0_MCO; + + /* MCO1 Clock Enable */ + MCO1_CLK_ENABLE(); + HAL_GPIO_Init(MCO1_GPIO_PORT, &gpio); /* Configure the MCO clock source */ @@ -1073,13 +1092,13 @@ uint32_t HAL_RCC_GetSysClockFreq(void) /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV * PLLMUL */ pllclk = (HSE_VALUE / prediv) * pllmul; } -#if defined(RCC_CR2_HSI48ON) +#if defined(RCC_CFGR_PLLSRC_HSI48_PREDIV) else if ((tmpreg & RCC_CFGR_PLLSRC) == RCC_PLLSOURCE_HSI48) { /* HSI48 used as PLL clock source : PLLCLK = HSI48/PREDIV * PLLMUL */ pllclk = (HSI48_VALUE / prediv) * pllmul; } -#endif /* RCC_CR2_HSI48ON */ +#endif /* RCC_CFGR_PLLSRC_HSI48_PREDIV */ else { #if (defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)) @@ -1093,13 +1112,13 @@ uint32_t HAL_RCC_GetSysClockFreq(void) sysclockfreq = pllclk; break; } -#if defined(RCC_CR2_HSI48ON) +#if defined(RCC_CFGR_SWS_HSI48) case RCC_SYSCLKSOURCE_STATUS_HSI48: /* HSI48 used as system clock source */ { sysclockfreq = HSI48_VALUE; break; } -#endif /* RCC_CR2_HSI48ON */ +#endif /* RCC_CFGR_SWS_HSI48 */ case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ default: /* HSI used as system clock */ { @@ -1121,7 +1140,6 @@ uint32_t HAL_RCC_GetSysClockFreq(void) */ uint32_t HAL_RCC_GetHCLKFreq(void) { - SystemCoreClock = HAL_RCC_GetSysClockFreq() >> aAPBAHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_BITNUMBER]; return SystemCoreClock; } @@ -1134,7 +1152,7 @@ uint32_t HAL_RCC_GetHCLKFreq(void) uint32_t HAL_RCC_GetPCLK1Freq(void) { /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ - return (HAL_RCC_GetHCLKFreq() >> aAPBAHBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE)>> RCC_CFGR_PPRE_BITNUMBER]); + return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE) >> RCC_CFGR_PPRE_BITNUMBER]); } /** @@ -1152,9 +1170,9 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) /* Set all possible values for the Oscillator type parameter ---------------*/ RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI \ | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_HSI14; -#if defined(RCC_CR2_HSI48ON) +#if defined(RCC_HSI48_SUPPORT) RCC_OscInitStruct->OscillatorType |= RCC_OSCILLATORTYPE_HSI48; -#endif /* RCC_CR2_HSI48ON */ +#endif /* RCC_HSI48_SUPPORT */ /* Get the HSE configuration -----------------------------------------------*/ @@ -1207,19 +1225,6 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) RCC_OscInitStruct->LSIState = RCC_LSI_OFF; } - /* Get the PLL configuration -----------------------------------------------*/ - if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON) - { - RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON; - } - else - { - RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF; - } - RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLSRC); - RCC_OscInitStruct->PLL.PLLMUL = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLMUL); - RCC_OscInitStruct->PLL.PREDIV = (uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV); - /* Get the HSI14 configuration -----------------------------------------------*/ if((RCC->CR2 & RCC_CR2_HSI14ON) == RCC_CR2_HSI14ON) { @@ -1232,10 +1237,23 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) RCC_OscInitStruct->HSI14CalibrationValue = (uint32_t)((RCC->CR2 & RCC_CR2_HSI14TRIM) >> RCC_HSI14TRIM_BIT_NUMBER); -#if defined(RCC_CR2_HSI48ON) +#if defined(RCC_HSI48_SUPPORT) /* Get the HSI48 configuration if any-----------------------------------------*/ RCC_OscInitStruct->HSI48State = __HAL_RCC_GET_HSI48_STATE(); -#endif /* RCC_CR2_HSI48ON */ +#endif /* RCC_HSI48_SUPPORT */ + + /* Get the PLL configuration -----------------------------------------------*/ + if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON) + { + RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON; + } + else + { + RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF; + } + RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLSRC); + RCC_OscInitStruct->PLL.PLLMUL = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLMUL); + RCC_OscInitStruct->PLL.PREDIV = (uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV); } /** diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rcc.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rcc.h index bc6f3966cf..62af0cf865 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rcc.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rcc.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f0xx_hal_rcc.h * @author MCD Application Team - * @version V1.3.1 - * @date 29-January-2016 + * @version V1.4.0 + * @date 27-May-2016 * @brief Header file of RCC HAL module. ****************************************************************************** * @attention @@ -68,12 +68,13 @@ #define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT #define CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */ #define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT -#define HSI_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */ -#define LSI_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */ -#define PLL_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */ -#define HSI14_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */ -#define HSI48_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */ - +#define HSI_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms (minimum Tick + 1) */ +#define LSI_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms (minimum Tick + 1) */ +#define PLL_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms (minimum Tick + 1) */ +#define HSI14_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms (minimum Tick + 1) */ +#if defined(RCC_HSI48_SUPPORT) +#define HSI48_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms (minimum Tick + 1) */ +#endif /* RCC_HSI48_SUPPORT */ /** * @} */ @@ -108,10 +109,10 @@ #define BDCR_REG_INDEX ((uint8_t)3) #define CSR_REG_INDEX ((uint8_t)4) -/* Flags in the CFGR register */ -#define RCC_CFGR_PLLMUL_BITNUMBER 18 -#define RCC_CFGR_HPRE_BITNUMBER 4 -#define RCC_CFGR_PPRE_BITNUMBER 8 +/* Bits position in in the CFGR register */ +#define RCC_CFGR_PLLMUL_BITNUMBER 18U +#define RCC_CFGR_HPRE_BITNUMBER 4U +#define RCC_CFGR_PPRE_BITNUMBER 8U /* Flags in the CFGR2 register */ #define RCC_CFGR2_PREDIV_BITNUMBER 0 /* Flags in the CR register */ @@ -225,7 +226,7 @@ typedef struct } RCC_PLLInitTypeDef; -/** +/** * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition */ typedef struct @@ -235,49 +236,49 @@ typedef struct uint32_t HSEState; /*!< The new state of the HSE. This parameter can be a value of @ref RCC_HSE_Config */ - + uint32_t LSEState; /*!< The new state of the LSE. This parameter can be a value of @ref RCC_LSE_Config */ - + uint32_t HSIState; /*!< The new state of the HSI. This parameter can be a value of @ref RCC_HSI_Config */ uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT). This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */ - + uint32_t HSI14State; /*!< The new state of the HSI14. This parameter can be a value of @ref RCC_HSI14_Config */ uint32_t HSI14CalibrationValue; /*!< The HSI14 calibration trimming value (default is RCC_HSI14CALIBRATION_DEFAULT). This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */ - uint32_t HSI48State; /*!< The new state of the HSI48 (only applicable to STM32F07x, STM32F0x2 and STM32F09x devices). - This parameter can be a value of @ref RCCEx_HSI48_Config */ - uint32_t LSIState; /*!< The new state of the LSI. This parameter can be a value of @ref RCC_LSI_Config */ + uint32_t HSI48State; /*!< The new state of the HSI48. + This parameter can be a value of @ref RCC_HSI48_Config */ + RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */ } RCC_OscInitTypeDef; -/** +/** * @brief RCC System, AHB and APB busses clock configuration structure definition */ typedef struct { uint32_t ClockType; /*!< The clock to be configured. This parameter can be a value of @ref RCC_System_Clock_Type */ - + uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock. This parameter can be a value of @ref RCC_System_Clock_Source */ uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). This parameter can be a value of @ref RCC_AHB_Clock_Source */ - + uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). This parameter can be a value of @ref RCC_APB1_Clock_Source */ - + } RCC_ClkInitTypeDef; /** @@ -308,6 +309,9 @@ typedef struct #define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004) #define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008) #define RCC_OSCILLATORTYPE_HSI14 ((uint32_t)0x00000010) +#if defined(RCC_HSI48_SUPPORT) +#define RCC_OSCILLATORTYPE_HSI48 ((uint32_t)0x00000020) +#endif /* RCC_HSI48_SUPPORT */ /** * @} */ @@ -336,8 +340,8 @@ typedef struct /** @defgroup RCC_HSI_Config HSI Config * @{ */ -#define RCC_HSI_OFF ((uint32_t)0x00000000) /*!< HSI clock deactivation */ -#define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */ +#define RCC_HSI_OFF ((uint32_t)0x00000000) /*!< HSI clock deactivation */ +#define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */ #define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x10) /* Default HSI calibration trimming value */ @@ -367,6 +371,18 @@ typedef struct * @} */ +#if defined(RCC_HSI48_SUPPORT) +/** @defgroup RCC_HSI48_Config HSI48 Config + * @{ + */ +#define RCC_HSI48_OFF ((uint8_t)0x00) +#define RCC_HSI48_ON ((uint8_t)0x01) + +/** + * @} + */ +#endif /* RCC_HSI48_SUPPORT */ + /** @defgroup RCC_PLL_Config PLL Config * @{ */ @@ -445,8 +461,8 @@ typedef struct * @{ */ #define RCC_RTCCLKSOURCE_NO_CLK ((uint32_t)0x00000000) /*!< No clock */ -#define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_LSE /*!< LSE oscillator clock used as RTC clock */ -#define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_LSI /*!< LSI oscillator clock used as RTC clock */ +#define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_LSE /*!< LSE oscillator clock used as RTC clock */ +#define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_LSI /*!< LSI oscillator clock used as RTC clock */ #define RCC_RTCCLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL_HSE /*!< HSE oscillator clock divided by 32 used as RTC clock */ /** * @} @@ -587,7 +603,6 @@ typedef struct #if defined(RCC_CSR_V18PWRRSTF) #define RCC_FLAG_V18PWRRST ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_V18PWRRSTF_BitNumber)) #endif -#define RCC_FLAG_RMV ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_RMVF_BitNumber)) #define RCC_FLAG_OBLRST ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_OBLRSTF_BitNumber)) #define RCC_FLAG_PINRST ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_PINRSTF_BitNumber)) /*!< PIN reset flag */ #define RCC_FLAG_PORRST ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_PORRSTF_BitNumber)) /*!< POR/PDR reset flag */ @@ -1028,7 +1043,7 @@ typedef struct * PLL as system clock. In this case, you have to select another source * of the system clock then change the HSE state (ex. disable it). * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. - * @note This function reset the CSSON bit, so if the Clock security system(CSS) + * @note This function reset the CSSON bit, so if the clock security system(CSS) * was previously enabled you have to enable it again after calling this * function. * @param __STATE__ specifies the new state of the HSE. @@ -1272,14 +1287,14 @@ typedef struct /** * @brief Macro to configure the system clock source. - * @param __RCC_SYSCLKSOURCE__ specifies the system clock source. + * @param __SYSCLKSOURCE__ specifies the system clock source. * This parameter can be one of the following values: * @arg @ref RCC_SYSCLKSOURCE_HSI HSI oscillator is used as system clock source. * @arg @ref RCC_SYSCLKSOURCE_HSE HSE oscillator is used as system clock source. * @arg @ref RCC_SYSCLKSOURCE_PLLCLK PLL output is used as system clock source. */ -#define __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) \ - MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__)) +#define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \ + MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__)) /** @brief Macro to get the clock source used as system clock. * @retval The clock source used as system clock. The returned value can be one @@ -1310,21 +1325,39 @@ typedef struct * @arg @ref RCC_MCO1SOURCE_LSE LSE selected as MCO clock * @arg @ref RCC_MCO1SOURCE_HSI14 HSI14 selected as MCO clock @if STM32F042x6 - * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock @elseif STM32F048xx - * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock @elseif STM32F071xB - * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock @elseif STM32F072xB - * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock @elseif STM32F078xx - * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock @elseif STM32F091xC - * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock @elseif STM32F098xx - * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock + @elseif STM32F030x6 + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock + @elseif STM32F030xC + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock + @elseif STM32F031x6 + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock + @elseif STM32F038xx + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock + @elseif STM32F070x6 + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock + @elseif STM32F070xB + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock @endif - * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock * @arg @ref RCC_MCO1SOURCE_PLLCLK_DIV2 PLLCLK Divided by 2 selected as MCO clock * @param __MCODIV__ specifies the MCO clock prescaler. * This parameter can be one of the following values: diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rcc_ex.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rcc_ex.c index 60e11883de..f099becfcf 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rcc_ex.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rcc_ex.c @@ -2,61 +2,14 @@ ****************************************************************************** * @file stm32f0xx_hal_rcc_ex.c * @author MCD Application Team - * @version V1.3.1 - * @date 29-January-2016 - * @brief Extended RCC HAL module driver + * @version V1.4.0 + * @date 27-May-2016 + * @brief Extended RCC HAL module driver. * This file provides firmware functions to manage the following * functionalities RCC extension peripheral: * + Extended Peripheral Control functions - * - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - For CRS, RCC Extention HAL driver can be used as follows: - - (#) In System clock config, HSI48 need to be enabled - - (#] Enable CRS clock in IP MSP init which will use CRS functions - - (#) Call CRS functions like this - (##) Prepare synchronization configuration necessary for HSI48 calibration - (+++) Default values can be set for frequency Error Measurement (reload and error limit) - and also HSI48 oscillator smooth trimming. - (+++) Macro @ref __HAL_RCC_CRS_RELOADVALUE_CALCULATE can be also used to calculate - directly reload value with target and synchronization frequencies values - (##) Call function @ref HAL_RCCEx_CRSConfig which - (+++) Reset CRS registers to their default values. - (+++) Configure CRS registers with synchronization configuration - (+++) Enable automatic calibration and frequency error counter feature - - (##) A polling function is provided to wait for complete Synchronization - (+++) Call function @ref HAL_RCCEx_CRSWaitSynchronization() - (+++) According to CRS status, user can decide to adjust again the calibration or continue - application if synchronization is OK - - (#) User can retrieve information related to synchronization in calling function - @ref HAL_RCCEx_CRSGetSynchronizationInfo() - - (#) Regarding synchronization status and synchronization information, user can try a new calibration - in changing synchronization configuration and call again HAL_RCCEx_CRSConfig. - Note: When the SYNC event is detected during the downcounting phase (before reaching the zero value), - it means that the actual frequency is lower than the target (and so, that the TRIM value should be - incremented), while when it is detected during the upcounting phase it means that the actual frequency - is higher (and that the TRIM value should be decremented). - - (#) To use IT mode, user needs to handle it in calling different macros available to do it - (__HAL_RCC_CRS_XXX_IT). Interuptions will go through RCC Handler (RCC_IRQn/RCC_CRS_IRQHandler) - (++) Call function @ref HAL_RCCEx_CRSConfig() - (++) Enable RCC_IRQn (thnaks to NVIC functions) - (++) Enable CRS IT (@ref __HAL_RCC_CRS_ENABLE_IT) - (++) Implement CRS status management in @ref RCC_CRS_IRQHandler - - (#) To force a SYNC EVENT, user can use function @ref HAL_RCCEx_CRSSoftwareSynchronizationGenerate(). Function can be - called before calling @ref HAL_RCCEx_CRSConfig (for instance in Systick handler) - - @endverbatim + * + Extended Clock Recovery System Control functions + * ****************************************************************************** * @attention * @@ -135,7 +88,7 @@ /** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions * @brief Extended Peripheral Control functions * -@verbatim +@verbatim =============================================================================== ##### Extended Peripheral Control functions ##### =============================================================================== @@ -146,7 +99,7 @@ (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select the RTC clock source; in this case the Backup domain will be reset in order to modify the RTC Clock source, as consequence RTC registers (including - the backup registers) and RCC_BDCR register are set to their reset values. + the backup registers) are set to their reset values. @endverbatim * @{ @@ -180,25 +133,37 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk /* check for RTC Parameters used to output RTCCLK */ assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); - /* Enable Power Clock*/ - __HAL_RCC_PWR_CLK_ENABLE(); - - /* Enable write access to Backup domain */ - SET_BIT(PWR->CR, PWR_CR_DBP); - - /* Wait for Backup domain Write protection disable */ - tickstart = HAL_GetTick(); - - while((PWR->CR & PWR_CR_DBP) == RESET) + FlagStatus pwrclkchanged = RESET; + + /* As soon as function is called to change RTC clock source, activation of the + power domain is done. */ + /* Requires to enable write access to Backup Domain of necessary */ + if(__HAL_RCC_PWR_IS_CLK_DISABLED()) { - if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + __HAL_RCC_PWR_CLK_ENABLE(); + pwrclkchanged = SET; + } + + if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + { + /* Enable write access to Backup domain */ + SET_BIT(PWR->CR, PWR_CR_DBP); + + /* Wait for Backup domain Write protection disable */ + tickstart = HAL_GetTick(); + + while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) { - return HAL_TIMEOUT; + if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } } } - /* Reset the Backup domain only if the RTC Clock source selection is modified */ - if((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)) + /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ + temp_reg = (RCC->BDCR & RCC_BDCR_RTCSEL); + if((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) { /* Store the content of BDCR register before the reset of Backup Domain */ temp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); @@ -209,7 +174,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk RCC->BDCR = temp_reg; /* Wait for LSERDY if LSE was enabled */ - if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSERDY)) + if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSEON)) { /* Get Start Tick */ tickstart = HAL_GetTick(); @@ -223,10 +188,16 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk } } } - __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); + } + __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); + + /* Require to disable power clock if necessary */ + if(pwrclkchanged == SET) + { + __HAL_RCC_PWR_CLK_DISABLE(); } } - + /*------------------------------- USART1 Configuration ------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) { @@ -661,14 +632,85 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) return(frequency); } -#if defined(CRS) /** - * @brief Start automatic synchronization using polling mode + * @} + */ + +#if defined(CRS) + +/** @defgroup RCCEx_Exported_Functions_Group3 Extended Clock Recovery System Control functions + * @brief Extended Clock Recovery System Control functions + * +@verbatim + =============================================================================== + ##### Extended Clock Recovery System Control functions ##### + =============================================================================== + [..] + For devices with Clock Recovery System feature (CRS), RCC Extention HAL driver can be used as follows: + + (#) In System clock config, HSI48 needs to be enabled + + (#) Enable CRS clock in IP MSP init which will use CRS functions + + (#) Call CRS functions as follows: + (##) Prepare synchronization configuration necessary for HSI48 calibration + (+++) Default values can be set for frequency Error Measurement (reload and error limit) + and also HSI48 oscillator smooth trimming. + (+++) Macro @ref __HAL_RCC_CRS_RELOADVALUE_CALCULATE can be also used to calculate + directly reload value with target and synchronization frequencies values + (##) Call function @ref HAL_RCCEx_CRSConfig which + (+++) Reset CRS registers to their default values. + (+++) Configure CRS registers with synchronization configuration + (+++) Enable automatic calibration and frequency error counter feature + Note: When using USB LPM (Link Power Management) and the device is in Sleep mode, the + periodic USB SOF will not be generated by the host. No SYNC signal will therefore be + provided to the CRS to calibrate the HSI48 on the run. To guarantee the required clock + precision after waking up from Sleep mode, the LSE or reference clock on the GPIOs + should be used as SYNC signal. + + (##) A polling function is provided to wait for complete synchronization + (+++) Call function @ref HAL_RCCEx_CRSWaitSynchronization() + (+++) According to CRS status, user can decide to adjust again the calibration or continue + application if synchronization is OK + + (#) User can retrieve information related to synchronization in calling function + @ref HAL_RCCEx_CRSGetSynchronizationInfo() + + (#) Regarding synchronization status and synchronization information, user can try a new calibration + in changing synchronization configuration and call again HAL_RCCEx_CRSConfig. + Note: When the SYNC event is detected during the downcounting phase (before reaching the zero value), + it means that the actual frequency is lower than the target (and so, that the TRIM value should be + incremented), while when it is detected during the upcounting phase it means that the actual frequency + is higher (and that the TRIM value should be decremented). + + (#) In interrupt mode, user can resort to the available macros (__HAL_RCC_CRS_XXX_IT). Interrupts will go + through CRS Handler (RCC_IRQn/RCC_IRQHandler) + (++) Call function @ref HAL_RCCEx_CRSConfig() + (++) Enable RCC_IRQn (thanks to NVIC functions) + (++) Enable CRS interrupt (@ref __HAL_RCC_CRS_ENABLE_IT) + (++) Implement CRS status management in the following user callbacks called from + HAL_RCCEx_CRS_IRQHandler(): + (+++) @ref HAL_RCCEx_CRS_SyncOkCallback() + (+++) @ref HAL_RCCEx_CRS_SyncWarnCallback() + (+++) @ref HAL_RCCEx_CRS_ExpectedSyncCallback() + (+++) @ref HAL_RCCEx_CRS_ErrorCallback() + + (#) To force a SYNC EVENT, user can use the function @ref HAL_RCCEx_CRSSoftwareSynchronizationGenerate(). + This function can be called before calling @ref HAL_RCCEx_CRSConfig (for instance in Systick handler) + +@endverbatim + * @{ + */ + +/** + * @brief Start automatic synchronization for polling mode * @param pInit Pointer on RCC_CRSInitTypeDef structure * @retval None */ void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit) { + uint32_t value = 0; + /* Check the parameters */ assert_param(IS_RCC_CRS_SYNC_DIV(pInit->Prescaler)); assert_param(IS_RCC_CRS_SYNC_SOURCE(pInit->Source)); @@ -677,52 +719,30 @@ void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit) assert_param(IS_RCC_CRS_ERRORLIMIT(pInit->ErrorLimitValue)); assert_param(IS_RCC_CRS_HSI48CALIBRATION(pInit->HSI48CalibrationValue)); - /* CONFIGURATION */ /* Before configuration, reset CRS registers to their default values*/ __HAL_RCC_CRS_FORCE_RESET(); __HAL_RCC_CRS_RELEASE_RESET(); - /* Configure Synchronization input */ - /* Clear SYNCDIV[2:0], SYNCSRC[1:0] & SYNCSPOL bits */ - CRS->CFGR &= ~(CRS_CFGR_SYNCDIV | CRS_CFGR_SYNCSRC | CRS_CFGR_SYNCPOL); - - /* Set the CRS_CFGR_SYNCDIV[2:0] bits according to Prescaler value */ - CRS->CFGR |= pInit->Prescaler; - + /* Set the SYNCDIV[2:0] bits according to Prescaler value */ /* Set the SYNCSRC[1:0] bits according to Source value */ - CRS->CFGR |= pInit->Source; - - /* Set the SYNCSPOL bits according to Polarity value */ - CRS->CFGR |= pInit->Polarity; - - /* Configure Frequency Error Measurement */ - /* Clear RELOAD[15:0] & FELIM[7:0] bits*/ - CRS->CFGR &= ~(CRS_CFGR_RELOAD | CRS_CFGR_FELIM); - + /* Set the SYNCSPOL bit according to Polarity value */ + value = (pInit->Prescaler | pInit->Source | pInit->Polarity); /* Set the RELOAD[15:0] bits according to ReloadValue value */ - CRS->CFGR |= pInit->ReloadValue; - + value |= pInit->ReloadValue; /* Set the FELIM[7:0] bits according to ErrorLimitValue value */ - CRS->CFGR |= (pInit->ErrorLimitValue << CRS_CFGR_FELIM_BITNUMBER); + value |= (pInit->ErrorLimitValue << CRS_CFGR_FELIM_BITNUMBER); + WRITE_REG(CRS->CFGR, value); /* Adjust HSI48 oscillator smooth trimming */ - /* Clear TRIM[5:0] bits */ - CRS->CR &= ~CRS_CR_TRIM; - /* Set the TRIM[5:0] bits according to RCC_CRS_HSI48CalibrationValue value */ - CRS->CR |= (pInit->HSI48CalibrationValue << CRS_CR_TRIM_BITNUMBER); - - + MODIFY_REG(CRS->CR, CRS_CR_TRIM, (pInit->HSI48CalibrationValue << CRS_CR_TRIM_BITNUMBER)); + /* START AUTOMATIC SYNCHRONIZATION*/ - /* Enable Automatic trimming */ - __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE(); - - /* Enable Frequency error counter */ - __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE(); - + /* Enable Automatic trimming & Frequency error counter */ + SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN | CRS_CR_CEN); } /** @@ -731,12 +751,11 @@ void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit) */ void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void) { - CRS->CR |= CRS_CR_SWSYNC; + SET_BIT(CRS->CR, CRS_CR_SWSYNC); } - /** - * @brief Function to return synchronization info + * @brief Return synchronization info * @param pSynchroInfo Pointer on RCC_CRSSynchroInfoTypeDef structure * @retval None */ @@ -746,23 +765,21 @@ void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo assert_param(pSynchroInfo != NULL); /* Get the reload value */ - pSynchroInfo->ReloadValue = (uint32_t)(CRS->CFGR & CRS_CFGR_RELOAD); + pSynchroInfo->ReloadValue = (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD)); /* Get HSI48 oscillator smooth trimming */ - pSynchroInfo->HSI48CalibrationValue = (uint32_t)((CRS->CR & CRS_CR_TRIM) >> CRS_CR_TRIM_BITNUMBER); + pSynchroInfo->HSI48CalibrationValue = (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_BITNUMBER); /* Get Frequency error capture */ - pSynchroInfo->FreqErrorCapture = (uint32_t)((CRS->ISR & CRS_ISR_FECAP) >> CRS_ISR_FECAP_BITNUMBER); + pSynchroInfo->FreqErrorCapture = (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_ISR_FECAP_BITNUMBER); - /* Get FFrequency error direction */ - pSynchroInfo->FreqErrorDirection = (uint32_t)(CRS->ISR & CRS_ISR_FEDIR); - - + /* Get Frequency error direction */ + pSynchroInfo->FreqErrorDirection = (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FEDIR)); } /** -* @brief This function handles CRS Synchronization Timeout. -* @param Timeout Duration of the timeout +* @brief Wait for CRS Synchronization status. +* @param Timeout Duration of the timeout * @note Timeout is based on the maximum time to receive a SYNC event based on synchronization * frequency. * @note If Timeout set to HAL_MAX_DELAY, HAL_TIMEOUT will be never returned. @@ -770,25 +787,25 @@ void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo * This parameter can be a combination of the following values: * @arg @ref RCC_CRS_TIMEOUT * @arg @ref RCC_CRS_SYNCOK -* @arg @ref RCC_CRS_SYNCWARM +* @arg @ref RCC_CRS_SYNCWARN * @arg @ref RCC_CRS_SYNCERR * @arg @ref RCC_CRS_SYNCMISS -* @arg @ref RCC_CRS_TRIMOV +* @arg @ref RCC_CRS_TRIMOVF */ uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout) { uint32_t crsstatus = RCC_CRS_NONE; - uint32_t tickstart = 0; + uint32_t tickstart = 0U; /* Get timeout */ tickstart = HAL_GetTick(); - /* Check that if one of CRS flags have been set */ - while(RCC_CRS_NONE == crsstatus) + /* Wait for CRS flag or timeout detection */ + do { if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout)) + if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) { crsstatus = RCC_CRS_TIMEOUT; } @@ -807,7 +824,7 @@ uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout) if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCWARN)) { /* CRS SYNC warning */ - crsstatus |= RCC_CRS_SYNCWARM; + crsstatus |= RCC_CRS_SYNCWARN; /* Clear CRS SYNCWARN bit */ __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCWARN); @@ -817,7 +834,7 @@ uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout) if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_TRIMOVF)) { /* CRS SYNC Error */ - crsstatus |= RCC_CRS_TRIMOV; + crsstatus |= RCC_CRS_TRIMOVF; /* Clear CRS Error bit */ __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_TRIMOVF); @@ -849,11 +866,132 @@ uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout) /* frequency error counter reached a zero value */ __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_ESYNC); } - } - + } while(RCC_CRS_NONE == crsstatus); + return crsstatus; } - + +/** + * @brief Handle the Clock Recovery System interrupt request. + * @retval None + */ +void HAL_RCCEx_CRS_IRQHandler(void) +{ + uint32_t crserror = RCC_CRS_NONE; + /* Get current IT flags and IT sources values */ + uint32_t itflags = READ_REG(CRS->ISR); + uint32_t itsources = READ_REG(CRS->CR); + + /* Check CRS SYNCOK flag */ + if(((itflags & RCC_CRS_FLAG_SYNCOK) != RESET) && ((itsources & RCC_CRS_IT_SYNCOK) != RESET)) + { + /* Clear CRS SYNC event OK flag */ + WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC); + + /* user callback */ + HAL_RCCEx_CRS_SyncOkCallback(); + } + /* Check CRS SYNCWARN flag */ + else if(((itflags & RCC_CRS_FLAG_SYNCWARN) != RESET) && ((itsources & RCC_CRS_IT_SYNCWARN) != RESET)) + { + /* Clear CRS SYNCWARN flag */ + WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC); + + /* user callback */ + HAL_RCCEx_CRS_SyncWarnCallback(); + } + /* Check CRS Expected SYNC flag */ + else if(((itflags & RCC_CRS_FLAG_ESYNC) != RESET) && ((itsources & RCC_CRS_IT_ESYNC) != RESET)) + { + /* frequency error counter reached a zero value */ + WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC); + + /* user callback */ + HAL_RCCEx_CRS_ExpectedSyncCallback(); + } + /* Check CRS Error flags */ + else + { + if(((itflags & RCC_CRS_FLAG_ERR) != RESET) && ((itsources & RCC_CRS_IT_ERR) != RESET)) + { + if((itflags & RCC_CRS_FLAG_SYNCERR) != RESET) + { + crserror |= RCC_CRS_SYNCERR; + } + if((itflags & RCC_CRS_FLAG_SYNCMISS) != RESET) + { + crserror |= RCC_CRS_SYNCMISS; + } + if((itflags & RCC_CRS_FLAG_TRIMOVF) != RESET) + { + crserror |= RCC_CRS_TRIMOVF; + } + + /* Clear CRS Error flags */ + WRITE_REG(CRS->ICR, CRS_ICR_ERRC); + + /* user error callback */ + HAL_RCCEx_CRS_ErrorCallback(crserror); + } + } +} + +/** + * @brief RCCEx Clock Recovery System SYNCOK interrupt callback. + * @retval none + */ +__weak void HAL_RCCEx_CRS_SyncOkCallback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the @ref HAL_RCCEx_CRS_SyncOkCallback should be implemented in the user file + */ +} + +/** + * @brief RCCEx Clock Recovery System SYNCWARN interrupt callback. + * @retval none + */ +__weak void HAL_RCCEx_CRS_SyncWarnCallback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the @ref HAL_RCCEx_CRS_SyncWarnCallback should be implemented in the user file + */ +} + +/** + * @brief RCCEx Clock Recovery System Expected SYNC interrupt callback. + * @retval none + */ +__weak void HAL_RCCEx_CRS_ExpectedSyncCallback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the @ref HAL_RCCEx_CRS_ExpectedSyncCallback should be implemented in the user file + */ +} + +/** + * @brief RCCEx Clock Recovery System Error interrupt callback. + * @param Error Combination of Error status. + * This parameter can be a combination of the following values: + * @arg @ref RCC_CRS_SYNCERR + * @arg @ref RCC_CRS_SYNCMISS + * @arg @ref RCC_CRS_TRIMOVF + * @retval none + */ +__weak void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(Error); + + /* NOTE : This function should not be modified, when the callback is needed, + the @ref HAL_RCCEx_CRS_ErrorCallback should be implemented in the user file + */ +} + +/** + * @} + */ + #endif /* CRS */ /** diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rcc_ex.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rcc_ex.h index 7603c699f1..b76659324d 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rcc_ex.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rcc_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f0xx_hal_rcc_ex.h * @author MCD Application Team - * @version V1.3.1 - * @date 29-January-2016 + * @version V1.4.0 + * @date 27-May-2016 * @brief Header file of RCC HAL Extension module. ****************************************************************************** * @attention @@ -57,9 +57,7 @@ /** @addtogroup RCC_Private_Macros * @{ */ -#if defined(STM32F042x6) || defined(STM32F048xx)\ - || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ - || defined(STM32F091xC) || defined(STM32F098xx) +#if defined(RCC_HSI48_SUPPORT) #define IS_RCC_OSCILLATORTYPE(OSCILLATOR) (((OSCILLATOR) == RCC_OSCILLATORTYPE_NONE) || \ (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \ (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \ @@ -67,6 +65,7 @@ (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) || \ (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI14) == RCC_OSCILLATORTYPE_HSI14) || \ (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48)) + #define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \ ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \ ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK) || \ @@ -76,11 +75,15 @@ ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSE) || \ ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_PLLCLK) || \ ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI48)) + #define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \ ((SOURCE) == RCC_PLLSOURCE_HSI48) || \ ((SOURCE) == RCC_PLLSOURCE_HSE)) + #define IS_RCC_HSI48(HSI48) (((HSI48) == RCC_HSI48_OFF) || ((HSI48) == RCC_HSI48_ON)) + #else + #define IS_RCC_OSCILLATORTYPE(OSCILLATOR) (((OSCILLATOR) == RCC_OSCILLATORTYPE_NONE) || \ (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \ (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \ @@ -97,12 +100,9 @@ #define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \ ((SOURCE) == RCC_PLLSOURCE_HSE)) -#endif /* STM32F042x6 || STM32F048xx || */ - /* STM32F071xB || STM32F072xB || STM32F078xx || */ - /* STM32F091xC || STM32F098xx */ +#endif /* RCC_HSI48_SUPPORT */ -#if defined(STM32F031x6) || defined(STM32F038xx) || defined(STM32F070x6) || defined(STM32F070xB) \ - || defined(STM32F030xC) +#if defined(RCC_CFGR_PLLNODIV) && !defined(RCC_CFGR_MCO_HSI48) #define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_NOCLOCK) || \ ((SOURCE) == RCC_MCO1SOURCE_LSI) || \ @@ -114,24 +114,7 @@ ((SOURCE) == RCC_MCO1SOURCE_PLLCLK_DIV2) || \ ((SOURCE) == RCC_MCO1SOURCE_HSI14)) -#endif /* STM32F030x6 || STM32F031x6 || STM32F038xx || STM32F070x6 || STM32F070xB || STM32F030xC */ - -#if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F051x8) || defined(STM32F058xx) - -#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_NOCLOCK) || \ - ((SOURCE) == RCC_MCO1SOURCE_LSI) || \ - ((SOURCE) == RCC_MCO1SOURCE_LSE) || \ - ((SOURCE) == RCC_MCO1SOURCE_SYSCLK) || \ - ((SOURCE) == RCC_MCO1SOURCE_HSI) || \ - ((SOURCE) == RCC_MCO1SOURCE_HSE) || \ - ((SOURCE) == RCC_MCO1SOURCE_PLLCLK_DIV2) || \ - ((SOURCE) == RCC_MCO1SOURCE_HSI14)) - -#endif /* STM32F030x8 || STM32F051x8 || STM32F058xx */ - -#if defined(STM32F042x6) || defined(STM32F048xx)\ - || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ - || defined(STM32F091xC) || defined(STM32F098xx) +#elif defined(RCC_CFGR_PLLNODIV) && defined(RCC_CFGR_MCO_HSI48) #define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_NOCLOCK) || \ ((SOURCE) == RCC_MCO1SOURCE_LSI) || \ @@ -144,9 +127,18 @@ ((SOURCE) == RCC_MCO1SOURCE_HSI14) || \ ((SOURCE) == RCC_MCO1SOURCE_HSI48)) -#endif /* STM32F042x6 || STM32F048xx || */ - /* STM32F071xB || STM32F072xB || STM32F078xx || */ - /* STM32F091xC || STM32F098xx */ +#elif !defined(RCC_CFGR_PLLNODIV) && !defined(RCC_CFGR_MCO_HSI48) + +#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_NOCLOCK) || \ + ((SOURCE) == RCC_MCO1SOURCE_LSI) || \ + ((SOURCE) == RCC_MCO1SOURCE_LSE) || \ + ((SOURCE) == RCC_MCO1SOURCE_SYSCLK) || \ + ((SOURCE) == RCC_MCO1SOURCE_HSI) || \ + ((SOURCE) == RCC_MCO1SOURCE_HSE) || \ + ((SOURCE) == RCC_MCO1SOURCE_PLLCLK_DIV2) || \ + ((SOURCE) == RCC_MCO1SOURCE_HSI14)) + +#endif /* RCC_CFGR_PLLNODIV && !RCC_CFGR_MCO_HSI48 */ /** * @} @@ -155,9 +147,7 @@ /** @addtogroup RCC_Exported_Constants * @{ */ -#if defined(STM32F042x6) || defined(STM32F048xx)\ - || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ - || defined(STM32F091xC) || defined(STM32F098xx) +#if defined(RCC_HSI48_SUPPORT) /** @addtogroup RCC_PLL_Clock_Source * @{ @@ -169,14 +159,6 @@ * @} */ -/** @addtogroup RCC_Oscillator_Type - * @{ - */ -#define RCC_OSCILLATORTYPE_HSI48 ((uint32_t)0x00000020) -/** - * @} - */ - /** @addtogroup RCC_Interrupt * @{ */ @@ -224,31 +206,23 @@ * @} */ -#endif /* STM32F042x6 || STM32F048xx || */ - /* STM32F071xB || STM32F072xB || STM32F078xx || */ - /* STM32F091xC || STM32F098xx */ +#endif /* RCC_HSI48_SUPPORT */ /** @addtogroup RCC_MCO_Clock_Source * @{ */ -#if defined(STM32F031x6) || defined(STM32F038xx) || defined(STM32F070x6) || defined(STM32F070xB) \ - || defined(STM32F030xC) +#if defined(RCC_CFGR_PLLNODIV) #define RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCO_PLL | RCC_CFGR_PLLNODIV) -#endif /* STM32F030x6 || STM32F031x6 || STM32F038xx || STM32F070x6 || STM32F070xB || STM32F030xC */ +#endif /* RCC_CFGR_PLLNODIV */ -#if defined(STM32F042x6) || defined(STM32F048xx)\ - || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ - || defined(STM32F091xC) || defined(STM32F098xx) +#if defined(RCC_CFGR_MCO_HSI48) #define RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCO_HSI48 -#define RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCO_PLL | RCC_CFGR_PLLNODIV) -#endif /* STM32F042x6 || STM32F048xx || */ - /* STM32F071xB || STM32F072xB || STM32F078xx || */ - /* STM32F091xC || STM32F098xx */ +#endif /* SRCC_CFGR_MCO_HSI48 */ /** * @} */ @@ -609,7 +583,7 @@ typedef struct This parameter can be a value of @ref RCCEx_CRS_SynchroPolarity */ uint32_t ReloadValue; /*!< Specifies the value to be loaded in the frequency error counter with each SYNC event. - It can be calculated in using macro @ref __HAL_RCC_CRS_RELOADVALUE_CALCULATE(_FTARGET_, _FSYNC_) + It can be calculated in using macro @ref __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) This parameter must be a number between 0 and 0xFFFF or a value of @ref RCCEx_CRS_ReloadValueDefault .*/ uint32_t ErrorLimitValue; /*!< Specifies the value to be used to evaluate the captured frequency error value. @@ -617,7 +591,7 @@ typedef struct uint32_t HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value to the HSI48 oscillator. This parameter must be a number between 0 and 0x3F or a value of @ref RCCEx_CRS_HSI48CalibrationDefault */ - + }RCC_CRSInitTypeDef; /** @@ -626,15 +600,15 @@ typedef struct typedef struct { uint32_t ReloadValue; /*!< Specifies the value loaded in the Counter reload value. - This parameter must be a number between 0 and 0xFFFF*/ + This parameter must be a number between 0 and 0xFFFF */ uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48 oscillator smooth trimming. This parameter must be a number between 0 and 0x3F */ - + uint32_t FreqErrorCapture; /*!< Specifies the value loaded in the .FECAP, the frequency error counter value latched in the time of the last SYNC event. This parameter must be a number between 0 and 0xFFFF */ - + uint32_t FreqErrorDirection; /*!< Specifies the value loaded in the .FEDIR, the counting direction of the frequency error counter latched in the time of the last SYNC event. It shows whether the actual frequency is below or above the target. @@ -654,48 +628,6 @@ typedef struct * @{ */ -#if defined(STM32F042x6) || defined(STM32F048xx)\ - || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ - || defined(STM32F091xC) || defined(STM32F098xx) -/** @defgroup RCCEx_HSI48_Config RCCEx HSI48 Config - * @{ - */ -#define RCC_HSI48_OFF ((uint8_t)0x00) -#define RCC_HSI48_ON ((uint8_t)0x01) - -/** - * @} - */ - -/** @defgroup RCCEx_CRS_Status RCCEx CRS Status - * @{ - */ -#define RCC_CRS_NONE ((uint32_t)0x00000000) -#define RCC_CRS_TIMEOUT ((uint32_t)0x00000001) -#define RCC_CRS_SYNCOK ((uint32_t)0x00000002) -#define RCC_CRS_SYNCWARM ((uint32_t)0x00000004) -#define RCC_CRS_SYNCERR ((uint32_t)0x00000008) -#define RCC_CRS_SYNCMISS ((uint32_t)0x00000010) -#define RCC_CRS_TRIMOV ((uint32_t)0x00000020) - -/** - * @} - */ - -#else - -/** @defgroup RCCEx_HSI48_Config RCCEx HSI48 Config - * @{ - */ -#define RCC_HSI48_OFF ((uint8_t)0x00) -/** - * @} - */ - -#endif /* STM32F042x6 || STM32F048xx */ - /* STM32F071xB || STM32F072xB || STM32F078xx || */ - /* STM32F091xC || STM32F098xx */ - /** @defgroup RCCEx_Periph_Clock_Selection RCCEx Periph Clock Selection * @{ */ @@ -889,21 +821,35 @@ typedef struct #if defined(CRS) -/** @defgroup RCCEx_CRS_SynchroSource RCCEx CRS SynchroSource +/** @defgroup RCCEx_CRS_Status RCCEx CRS Status * @{ */ -#define RCC_CRS_SYNC_SOURCE_GPIO ((uint32_t)0x00) /*!< Synchro Signal soucre GPIO */ -#define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */ -#define RCC_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/ - +#define RCC_CRS_NONE ((uint32_t)0x00000000) +#define RCC_CRS_TIMEOUT ((uint32_t)0x00000001) +#define RCC_CRS_SYNCOK ((uint32_t)0x00000002) +#define RCC_CRS_SYNCWARN ((uint32_t)0x00000004) +#define RCC_CRS_SYNCERR ((uint32_t)0x00000008) +#define RCC_CRS_SYNCMISS ((uint32_t)0x00000010) +#define RCC_CRS_TRIMOVF ((uint32_t)0x00000020) + /** * @} */ -/** @defgroup RCCEx_CRS_SynchroDivider RCCEx CRS SynchroDivider +/** @defgroup RCCEx_CRS_SynchroSource RCCEx CRS Synchronization Source * @{ */ -#define RCC_CRS_SYNC_DIV1 ((uint32_t)0x00) /*!< Synchro Signal not divided (default) */ +#define RCC_CRS_SYNC_SOURCE_GPIO ((uint32_t)0x00000000U) /*!< Synchro Signal source GPIO */ +#define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */ +#define RCC_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/ +/** + * @} + */ + +/** @defgroup RCCEx_CRS_SynchroDivider RCCEx CRS Synchronization Divider + * @{ + */ +#define RCC_CRS_SYNC_DIV1 ((uint32_t)0x00000000U) /*!< Synchro Signal not divided (default) */ #define RCC_CRS_SYNC_DIV2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */ #define RCC_CRS_SYNC_DIV4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */ #define RCC_CRS_SYNC_DIV8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */ @@ -911,57 +857,51 @@ typedef struct #define RCC_CRS_SYNC_DIV32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */ #define RCC_CRS_SYNC_DIV64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */ #define RCC_CRS_SYNC_DIV128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */ - /** * @} */ -/** @defgroup RCCEx_CRS_SynchroPolarity RCCEx CRS SynchroPolarity +/** @defgroup RCCEx_CRS_SynchroPolarity RCCEx CRS Synchronization Polarity * @{ */ -#define RCC_CRS_SYNC_POLARITY_RISING ((uint32_t)0x00) /*!< Synchro Active on rising edge (default) */ -#define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */ - -/** - * @} - */ - -/** @defgroup RCCEx_CRS_ReloadValueDefault RCCEx CRS ReloadValueDefault - * @{ - */ -#define RCC_CRS_RELOADVALUE_DEFAULT ((uint32_t)0xBB7F) /*!< The reset value of the RELOAD field corresponds - to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */ - -/** - * @} - */ - -/** @defgroup RCCEx_CRS_ErrorLimitDefault RCCEx CRS ErrorLimitDefault - * @{ - */ -#define RCC_CRS_ERRORLIMIT_DEFAULT ((uint32_t)0x22) /*!< Default Frequency error limit */ - +#define RCC_CRS_SYNC_POLARITY_RISING ((uint32_t)0x00000000U) /*!< Synchro Active on rising edge (default) */ +#define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */ /** * @} */ -/** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCCEx CRS HSI48CalibrationDefault +/** @defgroup RCCEx_CRS_ReloadValueDefault RCCEx CRS Default Reload Value * @{ */ -#define RCC_CRS_HSI48CALIBRATION_DEFAULT ((uint32_t)0x20) /*!< The default value is 32, which corresponds to the middle of the trimming interval. - The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value - corresponds to a higher output frequency */ - +#define RCC_CRS_RELOADVALUE_DEFAULT ((uint32_t)0x0000BB7FU) /*!< The reset value of the RELOAD field corresponds + to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */ +/** + * @} + */ + +/** @defgroup RCCEx_CRS_ErrorLimitDefault RCCEx CRS Default Error Limit Value + * @{ + */ +#define RCC_CRS_ERRORLIMIT_DEFAULT ((uint32_t)0x00000022U) /*!< Default Frequency error limit */ /** * @} */ -/** @defgroup RCCEx_CRS_FreqErrorDirection RCCEx CRS FreqErrorDirection +/** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCCEx CRS Default HSI48 Calibration vakye * @{ */ -#define RCC_CRS_FREQERRORDIR_UP ((uint32_t)0x00) /*!< Upcounting direction, the actual frequency is above the target */ -#define RCC_CRS_FREQERRORDIR_DOWN ((uint32_t)CRS_ISR_FEDIR) /*!< Downcounting direction, the actual frequency is below the target */ - +#define RCC_CRS_HSI48CALIBRATION_DEFAULT ((uint32_t)0x00000020U) /*!< The default value is 32, which corresponds to the middle of the trimming interval. + The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value + corresponds to a higher output frequency */ +/** + * @} + */ + +/** @defgroup RCCEx_CRS_FreqErrorDirection RCCEx CRS Frequency Error Direction + * @{ + */ +#define RCC_CRS_FREQERRORDIR_UP ((uint32_t)0x00000000U) /*!< Upcounting direction, the actual frequency is above the target */ +#define RCC_CRS_FREQERRORDIR_DOWN ((uint32_t)CRS_ISR_FEDIR) /*!< Downcounting direction, the actual frequency is below the target */ /** * @} */ @@ -969,13 +909,13 @@ typedef struct /** @defgroup RCCEx_CRS_Interrupt_Sources RCCEx CRS Interrupt Sources * @{ */ -#define RCC_CRS_IT_SYNCOK CRS_ISR_SYNCOKF /*!< SYNC event OK */ -#define RCC_CRS_IT_SYNCWARN CRS_ISR_SYNCWARNF /*!< SYNC warning */ -#define RCC_CRS_IT_ERR CRS_ISR_ERRF /*!< error */ -#define RCC_CRS_IT_ESYNC CRS_ISR_ESYNCF /*!< Expected SYNC */ -#define RCC_CRS_IT_TRIMOVF CRS_ISR_TRIMOVF /*!< Trimming overflow or underflow */ -#define RCC_CRS_IT_SYNCERR CRS_ISR_SYNCERR /*!< SYNC error */ -#define RCC_CRS_IT_SYNCMISS CRS_ISR_SYNCMISS /*!< SYNC missed*/ +#define RCC_CRS_IT_SYNCOK CRS_CR_SYNCOKIE /*!< SYNC event OK */ +#define RCC_CRS_IT_SYNCWARN CRS_CR_SYNCWARNIE /*!< SYNC warning */ +#define RCC_CRS_IT_ERR CRS_CR_ERRIE /*!< Error */ +#define RCC_CRS_IT_ESYNC CRS_CR_ESYNCIE /*!< Expected SYNC */ +#define RCC_CRS_IT_SYNCERR CRS_CR_ERRIE /*!< SYNC error */ +#define RCC_CRS_IT_SYNCMISS CRS_CR_ERRIE /*!< SYNC missed */ +#define RCC_CRS_IT_TRIMOVF CRS_CR_ERRIE /*!< Trimming overflow or underflow */ /** * @} @@ -984,13 +924,13 @@ typedef struct /** @defgroup RCCEx_CRS_Flags RCCEx CRS Flags * @{ */ -#define RCC_CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF /* SYNC event OK flag */ -#define RCC_CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF /* SYNC warning flag */ -#define RCC_CRS_FLAG_ERR CRS_ISR_ERRF /* Error flag */ -#define RCC_CRS_FLAG_ESYNC CRS_ISR_ESYNCF /* Expected SYNC flag */ -#define RCC_CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF /*!< Trimming overflow or underflow */ -#define RCC_CRS_FLAG_SYNCERR CRS_ISR_SYNCERR /*!< SYNC error */ -#define RCC_CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS /*!< SYNC missed*/ +#define RCC_CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF /*!< SYNC event OK flag */ +#define RCC_CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF /*!< SYNC warning flag */ +#define RCC_CRS_FLAG_ERR CRS_ISR_ERRF /*!< Error flag */ +#define RCC_CRS_FLAG_ESYNC CRS_ISR_ESYNCF /*!< Expected SYNC flag */ +#define RCC_CRS_FLAG_SYNCERR CRS_ISR_SYNCERR /*!< SYNC error */ +#define RCC_CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS /*!< SYNC missed*/ +#define RCC_CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF /*!< Trimming overflow or underflow */ /** * @} @@ -1790,9 +1730,7 @@ typedef struct * clock cycles. * @{ */ -#if defined(STM32F042x6) || defined(STM32F048xx)\ - || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ - || defined(STM32F091xC) || defined(STM32F098xx) +#if defined(RCC_HSI48_SUPPORT) #define __HAL_RCC_HSI48_ENABLE() SET_BIT(RCC->CR2, RCC_CR2_HSI48ON) #define __HAL_RCC_HSI48_DISABLE() CLEAR_BIT(RCC->CR2, RCC_CR2_HSI48ON) @@ -1803,19 +1741,9 @@ typedef struct * @arg @ref RCC_HSI48_OFF HSI48 disabled */ #define __HAL_RCC_GET_HSI48_STATE() \ - (((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CR2_HSI48ON)) != RESET) ? RCC_HSI48_ON : RCC_HSI48_OFF) + (((uint32_t)(READ_BIT(RCC->CR2, RCC_CR2_HSI48ON)) != RESET) ? RCC_HSI48_ON : RCC_HSI48_OFF) -#else - -/** @brief Macro to get the Internal 48Mhz High Speed oscillator (HSI48) state. - * @retval The clock source can be one of the following values: - * @arg @ref RCC_HSI_OFF HSI48 disabled - */ -#define __HAL_RCC_GET_HSI48_STATE() RCC_HSI_OFF - -#endif /* STM32F042x6 || STM32F048xx || */ - /* STM32F071xB || STM32F072xB || STM32F078xx || */ - /* STM32F091xC || STM32F098xx */ +#endif /* RCC_HSI48_SUPPORT */ /** * @} @@ -1831,7 +1759,11 @@ typedef struct /** @brief Macro to configure the USB clock (USBCLK). * @param __USBCLKSOURCE__ specifies the USB clock source. * This parameter can be one of the following values: - * @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 selected as USB clock (not available for STM32F070x6 & STM32F070xB) +@if STM32F070xB +@elseif STM32F070x6 +@else + * @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 selected as USB clock +@endif * @arg @ref RCC_USBCLKSOURCE_PLL PLL Clock selected as USB clock */ #define __HAL_RCC_USB_CONFIG(__USBCLKSOURCE__) \ @@ -1839,7 +1771,11 @@ typedef struct /** @brief Macro to get the USB clock source. * @retval The clock source can be one of the following values: +@if STM32F070xB +@elseif STM32F070x6 +@else * @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 selected as USB clock +@endif * @arg @ref RCC_USBCLKSOURCE_PLL PLL Clock selected as USB clock */ #define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USBSW))) @@ -1952,51 +1888,50 @@ typedef struct /* Interrupt & Flag management */ /** - * @brief Enables the specified CRS interrupts. + * @brief Enable the specified CRS interrupts. * @param __INTERRUPT__ specifies the CRS interrupt sources to be enabled. * This parameter can be any combination of the following values: - * @arg @ref RCC_CRS_IT_SYNCOK - * @arg @ref RCC_CRS_IT_SYNCWARN - * @arg @ref RCC_CRS_IT_ERR - * @arg @ref RCC_CRS_IT_ESYNC + * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt + * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt + * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt + * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt * @retval None */ -#define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) (CRS->CR |= (__INTERRUPT__)) +#define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) SET_BIT(CRS->CR, (__INTERRUPT__)) /** - * @brief Disables the specified CRS interrupts. + * @brief Disable the specified CRS interrupts. * @param __INTERRUPT__ specifies the CRS interrupt sources to be disabled. * This parameter can be any combination of the following values: - * @arg @ref RCC_CRS_IT_SYNCOK - * @arg @ref RCC_CRS_IT_SYNCWARN - * @arg @ref RCC_CRS_IT_ERR - * @arg @ref RCC_CRS_IT_ESYNC + * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt + * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt + * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt + * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt * @retval None */ -#define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) (CRS->CR &= ~(__INTERRUPT__)) +#define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(CRS->CR, (__INTERRUPT__)) -/** @brief Check the CRS's interrupt has occurred or not. +/** @brief Check whether the CRS interrupt has occurred or not. * @param __INTERRUPT__ specifies the CRS interrupt source to check. * This parameter can be one of the following values: - * @arg @ref RCC_CRS_IT_SYNCOK - * @arg @ref RCC_CRS_IT_SYNCWARN - * @arg @ref RCC_CRS_IT_ERR - * @arg @ref RCC_CRS_IT_ESYNC + * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt + * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt + * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt + * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt * @retval The new state of __INTERRUPT__ (SET or RESET). */ -#define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((CRS->CR & (__INTERRUPT__))? SET : RESET) +#define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((READ_BIT(CRS->CR, (__INTERRUPT__)) != RESET) ? SET : RESET) -/** @brief Clear the CRS's interrupt pending bits - * bits to clear the selected interrupt pending bits. +/** @brief Clear the CRS interrupt pending bits * @param __INTERRUPT__ specifies the interrupt pending bit to clear. * This parameter can be any combination of the following values: - * @arg @ref RCC_CRS_IT_SYNCOK - * @arg @ref RCC_CRS_IT_SYNCWARN - * @arg @ref RCC_CRS_IT_ERR - * @arg @ref RCC_CRS_IT_ESYNC - * @arg @ref RCC_CRS_IT_TRIMOVF - * @arg @ref RCC_CRS_IT_SYNCERR - * @arg @ref RCC_CRS_IT_SYNCMISS + * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt + * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt + * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt + * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt + * @arg @ref RCC_CRS_IT_TRIMOVF Trimming overflow or underflow interrupt + * @arg @ref RCC_CRS_IT_SYNCERR SYNC error interrupt + * @arg @ref RCC_CRS_IT_SYNCMISS SYNC missed interrupt */ #define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) do { \ if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != RESET) \ @@ -2010,31 +1945,32 @@ typedef struct } while(0) /** - * @brief Checks whether the specified CRS flag is set or not. + * @brief Check whether the specified CRS flag is set or not. * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: - * @arg @ref RCC_CRS_FLAG_SYNCOK - * @arg @ref RCC_CRS_FLAG_SYNCWARN - * @arg @ref RCC_CRS_FLAG_ERR - * @arg @ref RCC_CRS_FLAG_ESYNC - * @arg @ref RCC_CRS_FLAG_TRIMOVF - * @arg @ref RCC_CRS_FLAG_SYNCERR - * @arg @ref RCC_CRS_FLAG_SYNCMISS + * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK + * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning + * @arg @ref RCC_CRS_FLAG_ERR Error + * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC + * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow + * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error + * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed * @retval The new state of _FLAG_ (TRUE or FALSE). */ -#define __HAL_RCC_CRS_GET_FLAG(__FLAG__) ((CRS->ISR & (__FLAG__)) == (__FLAG__)) +#define __HAL_RCC_CRS_GET_FLAG(__FLAG__) (READ_BIT(CRS->ISR, (__FLAG__)) == (__FLAG__)) /** - * @brief Clears the CRS specified FLAG. + * @brief Clear the CRS specified FLAG. * @param __FLAG__ specifies the flag to clear. * This parameter can be one of the following values: - * @arg @ref RCC_CRS_FLAG_SYNCOK - * @arg @ref RCC_CRS_FLAG_SYNCWARN - * @arg @ref RCC_CRS_FLAG_ERR - * @arg @ref RCC_CRS_FLAG_ESYNC - * @arg @ref RCC_CRS_FLAG_TRIMOVF - * @arg @ref RCC_CRS_FLAG_SYNCERR - * @arg @ref RCC_CRS_FLAG_SYNCMISS + * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK + * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning + * @arg @ref RCC_CRS_FLAG_ERR Error + * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC + * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow + * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error + * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed + * @note RCC_CRS_FLAG_ERR clears RCC_CRS_FLAG_TRIMOVF, RCC_CRS_FLAG_SYNCERR, RCC_CRS_FLAG_SYNCMISS and consequently RCC_CRS_FLAG_ERR * @retval None */ #define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) do { \ @@ -2056,30 +1992,30 @@ typedef struct * @{ */ /** - * @brief Enables the oscillator clock for frequency error counter. + * @brief Enable the oscillator clock for frequency error counter. * @note when the CEN bit is set the CRS_CFGR register becomes write-protected. * @retval None */ -#define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE() (CRS->CR |= CRS_CR_CEN) +#define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE() SET_BIT(CRS->CR, CRS_CR_CEN) /** - * @brief Disables the oscillator clock for frequency error counter. + * @brief Disable the oscillator clock for frequency error counter. * @retval None */ -#define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE() (CRS->CR &= ~CRS_CR_CEN) +#define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_CEN) /** - * @brief Enables the automatic hardware adjustement of TRIM bits. + * @brief Enable the automatic hardware adjustement of TRIM bits. * @note When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected. * @retval None */ -#define __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE() (CRS->CR |= CRS_CR_AUTOTRIMEN) +#define __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE() SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) /** - * @brief Enables or disables the automatic hardware adjustement of TRIM bits. + * @brief Disable the automatic hardware adjustement of TRIM bits. * @retval None */ -#define __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE() (CRS->CR &= ~CRS_CR_AUTOTRIMEN) +#define __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) /** * @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies @@ -2087,28 +2023,28 @@ typedef struct * of the synchronization source after prescaling. It is then decreased by one in order to * reach the expected synchronization on the zero value. The formula is the following: * RELOAD = (fTARGET / fSYNC) -1 - * @param _FTARGET_ Target frequency (value in Hz) - * @param _FSYNC_ Synchronization signal frequency (value in Hz) + * @param __FTARGET__ Target frequency (value in Hz) + * @param __FSYNC__ Synchronization signal frequency (value in Hz) * @retval None */ -#define __HAL_RCC_CRS_RELOADVALUE_CALCULATE(_FTARGET_, _FSYNC_) (((_FTARGET_) / (_FSYNC_)) - 1) +#define __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U) /** * @} */ - + #endif /* CRS */ - + /** * @} - */ + */ /* Exported functions --------------------------------------------------------*/ /** @addtogroup RCCEx_Exported_Functions * @{ */ -/** @addtogroup RCCEx_Exported_Functions_Group1 +/** @addtogroup RCCEx_Exported_Functions_Group1 * @{ */ @@ -2116,13 +2052,31 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *Perip void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); -#if defined(CRS) -void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit); -void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void); -void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo); -uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout); -#endif /* CRS */ +/** + * @} + */ +#if defined(CRS) + +/** @addtogroup RCCEx_Exported_Functions_Group3 + * @{ + */ + +void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit); +void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void); +void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo); +uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout); +void HAL_RCCEx_CRS_IRQHandler(void); +void HAL_RCCEx_CRS_SyncOkCallback(void); +void HAL_RCCEx_CRS_SyncWarnCallback(void); +void HAL_RCCEx_CRS_ExpectedSyncCallback(void); +void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); + +/** + * @} + */ + +#endif /* CRS */ /** * @} diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rtc.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rtc.c index 7df00ae63a..dfcbc501e0 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rtc.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rtc.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f0xx_hal_rtc.c * @author MCD Application Team - * @version V1.3.1 - * @date 29-January-2016 + * @version V1.4.0 + * @date 27-May-2016 * @brief RTC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Real Time Clock (RTC) peripheral: diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rtc.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rtc.h index fe3b04a013..cfe83fd0b1 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rtc.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rtc.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f0xx_hal_rtc.h * @author MCD Application Team - * @version V1.3.1 - * @date 29-January-2016 + * @version V1.4.0 + * @date 27-May-2016 * @brief Header file of RTC HAL module. ****************************************************************************** * @attention diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rtc_ex.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rtc_ex.c index 7e5aea5c91..d8096c1d98 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rtc_ex.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rtc_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f0xx_hal_rtc_ex.c * @author MCD Application Team - * @version V1.3.1 - * @date 29-January-2016 + * @version V1.4.0 + * @date 27-May-2016 * @brief Extended RTC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Real Time Clock (RTC) Extended peripheral: diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rtc_ex.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rtc_ex.h index 67890444d9..4c44f283e1 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rtc_ex.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rtc_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f0xx_hal_rtc_ex.h * @author MCD Application Team - * @version V1.3.1 - * @date 29-January-2016 + * @version V1.4.0 + * @date 27-May-2016 * @brief Header file of RTC HAL Extended module. ****************************************************************************** * @attention diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_smartcard.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_smartcard.c index 95d76c975a..c1e6b17bb8 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_smartcard.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_smartcard.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f0xx_hal_smartcard.c * @author MCD Application Team - * @version V1.3.1 - * @date 29-January-2016 + * @version V1.4.0 + * @date 27-May-2016 * @brief SMARTCARD HAL module driver. * This file provides firmware functions to manage the following * functionalities of the SMARTCARD peripheral: @@ -213,21 +213,7 @@ static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcar [..] (+) These parameters can be configured: (++) Baud Rate - (++) Parity: parity should be enabled, - Frame Length is fixed to 8 bits plus parity: - the SMARTCARD frame format is given in the following table: - (+++) +---------------------------------------------------------------+ - (+++) | M bit | PCE bit | SMARTCARD frame | - (+++) |---------------------|-----------------------------------------| - (+++) | 1 | 1 | | SB | 8 bit data | PB | STB | | - (+++) +---------------------------------------------------------------+ - (+++) or - (+++) +---------------------------------------------------------------+ - (+++) | M1M0 bits | PCE bit | SMARTCARD frame | - (+++) |-----------------------|---------------------------------------| - (+++) | 01 | 1 | | SB | 8 bit data | PB | STB | | - (+++) +---------------------------------------------------------------+ - + (++) Parity: should be enabled (++) Receiver/transmitter modes (++) Synchronous mode (and if enabled, phase, polarity and last bit parameters) (++) Prescaler value @@ -252,10 +238,28 @@ static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcar * @{ */ +/* + Additional Table: + Frame Length is fixed to 8 bits plus parity: + SMARTCARD frame format is given in the following table + +---------------------------------------------------------------+ + | M bit | PCE bit | SMARTCARD frame | + |---------------------|-----------------------------------------| + | 1 | 1 | | SB | 8 bit data | PB | STB | | + +---------------------------------------------------------------+ + or + +---------------------------------------------------------------+ + | M1M0 bits | PCE bit | SMARTCARD frame | + |-----------------------|---------------------------------------| + | 01 | 1 | | SB | 8 bit data | PB | STB | | + +---------------------------------------------------------------+ + +*/ + /** - * @brief Initialize the SMARTCARD mode according to the specified + * @brief Initialize the SMARTCARD mode according to the specified * parameters in the SMARTCARD_HandleTypeDef and initialize the associated handle. - * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains * the configuration information for the specified SMARTCARD module. * @retval HAL status */ @@ -270,7 +274,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsmartcard) /* Check the USART associated to the SmartCard */ assert_param(IS_SMARTCARD_INSTANCE(hsmartcard->Instance)); - if(hsmartcard->State == HAL_SMARTCARD_STATE_RESET) + if(hsmartcard->gState == HAL_SMARTCARD_STATE_RESET) { /* Allocate lock resource and initialize it */ hsmartcard->Lock = HAL_UNLOCKED; @@ -279,7 +283,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsmartcard) HAL_SMARTCARD_MspInit(hsmartcard); } - hsmartcard->State = HAL_SMARTCARD_STATE_BUSY; + hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY; /* Disable the Peripheral */ __HAL_SMARTCARD_DISABLE(hsmartcard); @@ -307,14 +311,14 @@ HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsmartcard) /* Enable the Peripheral */ __HAL_SMARTCARD_ENABLE(hsmartcard); - /* TEACK and/or REACK to check before moving hsmartcard->State to Ready */ + /* TEACK and/or REACK to check before moving hsmartcard->gState and hsmartcard->RxState to Ready */ return (SMARTCARD_CheckIdleState(hsmartcard)); } /** - * @brief DeInitialize the SMARTCARD peripheral. - * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains + * @brief DeInitialize the SMARTCARD peripheral. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains * the configuration information for the specified SMARTCARD module. * @retval HAL status */ @@ -329,7 +333,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsmartcard) /* Check the parameters */ assert_param(IS_SMARTCARD_INSTANCE(hsmartcard->Instance)); - hsmartcard->State = HAL_SMARTCARD_STATE_BUSY; + hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY; /* Disable the Peripheral */ __HAL_SMARTCARD_DISABLE(hsmartcard); @@ -344,7 +348,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsmartcard) HAL_SMARTCARD_MspDeInit(hsmartcard); hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE; - hsmartcard->State = HAL_SMARTCARD_STATE_RESET; + hsmartcard->gState = HAL_SMARTCARD_STATE_RESET; + hsmartcard->RxState = HAL_SMARTCARD_STATE_RESET; /* Process Unlock */ __HAL_UNLOCK(hsmartcard); @@ -389,7 +394,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsmartcard) */ /** @defgroup SMARTCARD_Exported_Functions_Group2 IO operation functions - * @brief SMARTCARD Transmit and Receive functions + * @brief SMARTCARD Transmit and Receive functions * @verbatim ============================================================================== @@ -453,7 +458,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsmartcard) */ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout) { - if ((hsmartcard->State == HAL_SMARTCARD_STATE_READY) || (hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_RX)) + /* Check that a Tx process is not already ongoing */ + if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY) { if((pData == NULL) || (Size == 0)) { @@ -463,15 +469,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, ui /* Process Locked */ __HAL_LOCK(hsmartcard); hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE; - /* Check if a non-blocking receive process is ongoing or not */ - if(hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_RX) - { - hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_TX_RX; - } - else - { - hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_TX; - } + hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY_TX; hsmartcard->TxXferSize = Size; hsmartcard->TxXferCount = Size; @@ -488,15 +486,9 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, ui { return HAL_TIMEOUT; } - /* Check if a non-blocking receive Process is ongoing or not */ - if(hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX_RX) - { - hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_RX; - } - else - { - hsmartcard->State = HAL_SMARTCARD_STATE_READY; - } + + /* At end of Tx process, restore hsmartcard->gState to Ready */ + hsmartcard->gState = HAL_SMARTCARD_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hsmartcard); @@ -520,7 +512,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, ui */ HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout) { - if ((hsmartcard->State == HAL_SMARTCARD_STATE_READY) || (hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX)) + /* Check that a Rx process is not already ongoing */ + if(hsmartcard->RxState == HAL_SMARTCARD_STATE_READY) { if((pData == NULL) || (Size == 0)) { @@ -531,15 +524,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uin __HAL_LOCK(hsmartcard); hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE; - /* Check if a non-blocking transmit process is ongoing or not */ - if(hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX) - { - hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_TX_RX; - } - else - { - hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_RX; - } + hsmartcard->RxState = HAL_SMARTCARD_STATE_BUSY_RX; hsmartcard->RxXferSize = Size; hsmartcard->RxXferCount = Size; @@ -554,15 +539,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uin *pData++ = (uint8_t)(hsmartcard->Instance->RDR & (uint8_t)0x00FF); } - /* Check if a non-blocking transmit Process is ongoing or not */ - if(hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX_RX) - { - hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_TX; - } - else - { - hsmartcard->State = HAL_SMARTCARD_STATE_READY; - } + /* At end of Rx process, restore hsmartcard->RxState to Ready */ + hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hsmartcard); @@ -585,7 +563,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uin */ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size) { - if ((hsmartcard->State == HAL_SMARTCARD_STATE_READY) || (hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_RX)) + /* Check that a Tx process is not already ongoing */ + if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY) { if((pData == NULL) || (Size == 0)) { @@ -600,15 +579,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, hsmartcard->TxXferCount = Size; hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE; - /* Check if a receive process is ongoing or not */ - if(hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_RX) - { - hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_TX_RX; - } - else - { - hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_TX; - } + hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY_TX; /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */ __HAL_SMARTCARD_ENABLE_IT(hsmartcard, SMARTCARD_IT_ERR); @@ -637,7 +608,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, */ HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size) { - if ((hsmartcard->State == HAL_SMARTCARD_STATE_READY) || (hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX)) + /* Check that a Rx process is not already ongoing */ + if(hsmartcard->RxState == HAL_SMARTCARD_STATE_READY) { if((pData == NULL) || (Size == 0)) { @@ -652,15 +624,10 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard, hsmartcard->RxXferCount = Size; hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE; - /* Check if a transmit process is ongoing or not */ - if(hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX) - { - hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_TX_RX; - } - else - { - hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_RX; - } + hsmartcard->RxState = HAL_SMARTCARD_STATE_BUSY_RX; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmartcard); /* Enable the SMARTCARD Parity Error Interrupt */ __HAL_SMARTCARD_ENABLE_IT(hsmartcard, SMARTCARD_IT_PE); @@ -668,9 +635,6 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard, /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */ __HAL_SMARTCARD_ENABLE_IT(hsmartcard, SMARTCARD_IT_ERR); - /* Process Unlocked */ - __HAL_UNLOCK(hsmartcard); - /* Enable the SMARTCARD Data Register not empty Interrupt */ __HAL_SMARTCARD_ENABLE_IT(hsmartcard, SMARTCARD_IT_RXNE); @@ -694,7 +658,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard { uint32_t *tmp; - if ((hsmartcard->State == HAL_SMARTCARD_STATE_READY) || (hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_RX)) + /* Check that a Tx process is not already ongoing */ + if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY) { if((pData == NULL) || (Size == 0)) { @@ -709,15 +674,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard hsmartcard->TxXferCount = Size; hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE; - /* Check if a receive process is ongoing or not */ - if(hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_RX) - { - hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_TX_RX; - } - else - { - hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_TX; - } + hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY_TX; /* Set the SMARTCARD DMA transfer complete callback */ hsmartcard->hdmatx->XferCpltCallback = SMARTCARD_DMATransmitCplt; @@ -761,7 +718,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsmartcard, { uint32_t *tmp; - if ((hsmartcard->State == HAL_SMARTCARD_STATE_READY) || (hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX)) + /* Check that a Rx process is not already ongoing */ + if(hsmartcard->RxState == HAL_SMARTCARD_STATE_READY) { if((pData == NULL) || (Size == 0)) { @@ -775,15 +733,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsmartcard, hsmartcard->RxXferSize = Size; hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE; - /* Check if a transmit process is ongoing or not */ - if(hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX) - { - hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_TX_RX; - } - else - { - hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_RX; - } + hsmartcard->RxState = HAL_SMARTCARD_STATE_BUSY_RX; /* Set the SMARTCARD DMA transfer complete callback */ hsmartcard->hdmarx->XferCpltCallback = SMARTCARD_DMAReceiveCplt; @@ -823,8 +773,9 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard) { __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_PEF); hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_PE; - /* Set the SMARTCARD state ready to be able to start again the process */ - hsmartcard->State = HAL_SMARTCARD_STATE_READY; + /* Set the SMARTCARD states ready to be able to start again the process */ + hsmartcard->gState = HAL_SMARTCARD_STATE_READY; + hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; } /* SMARTCARD frame error interrupt occurred --------------------------------------*/ @@ -832,8 +783,9 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard) { __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_FEF); hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_FE; - /* Set the SMARTCARD state ready to be able to start again the process */ - hsmartcard->State = HAL_SMARTCARD_STATE_READY; + /* Set the SMARTCARD states ready to be able to start again the process */ + hsmartcard->gState = HAL_SMARTCARD_STATE_READY; + hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; } /* SMARTCARD noise error interrupt occurred --------------------------------------*/ @@ -841,8 +793,9 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard) { __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_NEF); hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_NE; - /* Set the SMARTCARD state ready to be able to start again the process */ - hsmartcard->State = HAL_SMARTCARD_STATE_READY; + /* Set the SMARTCARD states ready to be able to start again the process */ + hsmartcard->gState = HAL_SMARTCARD_STATE_READY; + hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; } /* SMARTCARD Over-Run interrupt occurred -----------------------------------------*/ @@ -850,8 +803,9 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard) { __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_OREF); hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_ORE; - /* Set the SMARTCARD state ready to be able to start again the process */ - hsmartcard->State = HAL_SMARTCARD_STATE_READY; + /* Set the SMARTCARD states ready to be able to start again the process */ + hsmartcard->gState = HAL_SMARTCARD_STATE_READY; + hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; } /* SMARTCARD receiver timeout interrupt occurred -----------------------------------------*/ @@ -859,8 +813,9 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard) { __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_RTOF); hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_RTO; - /* Set the SMARTCARD state ready to be able to start again the process */ - hsmartcard->State = HAL_SMARTCARD_STATE_READY; + /* Set the SMARTCARD states ready to be able to start again the process */ + hsmartcard->gState = HAL_SMARTCARD_STATE_READY; + hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; } /* Call SMARTCARD Error Call back function if need be --------------------------*/ @@ -873,14 +828,12 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard) if((__HAL_SMARTCARD_GET_IT(hsmartcard, SMARTCARD_IT_RXNE) != RESET) && (__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, SMARTCARD_IT_RXNE) != RESET)) { SMARTCARD_Receive_IT(hsmartcard); - /* Clear RXNE interrupt flag */ - __HAL_SMARTCARD_SEND_REQ(hsmartcard, SMARTCARD_RXDATA_FLUSH_REQUEST); } /* SMARTCARD in mode Receiver, end of block interruption ------------------------*/ if((__HAL_SMARTCARD_GET_IT(hsmartcard, SMARTCARD_IT_EOB) != RESET) && (__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, SMARTCARD_IT_EOB) != RESET)) { - hsmartcard->State = HAL_SMARTCARD_STATE_READY; + hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; __HAL_UNLOCK(hsmartcard); HAL_SMARTCARD_RxCpltCallback(hsmartcard); /* Clear EOBF interrupt after HAL_SMARTCARD_RxCpltCallback() call for the End of Block information @@ -889,13 +842,13 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard) } /* SMARTCARD in mode Transmitter ------------------------------------------------*/ - if((__HAL_SMARTCARD_GET_IT(hsmartcard, SMARTCARD_IT_TXE) != RESET) &&(__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, SMARTCARD_IT_TXE) != RESET)) + if((__HAL_SMARTCARD_GET_IT(hsmartcard, SMARTCARD_IT_TXE) != RESET) &&(__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, SMARTCARD_IT_TXE) != RESET)) { SMARTCARD_Transmit_IT(hsmartcard); } /* SMARTCARD in mode Transmitter (transmission end) ------------------------*/ - if((__HAL_SMARTCARD_GET_IT(hsmartcard, SMARTCARD_IT_TC) != RESET) &&(__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, SMARTCARD_IT_TC) != RESET)) + if((__HAL_SMARTCARD_GET_IT(hsmartcard, SMARTCARD_IT_TC) != RESET) &&(__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, SMARTCARD_IT_TC) != RESET)) { SMARTCARD_EndTransmit_IT(hsmartcard); } @@ -975,20 +928,24 @@ __weak void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsmartcard) /** * @brief Return the SMARTCARD handle state. - * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains * the configuration information for the specified SMARTCARD module. * @retval SMARTCARD handle state */ HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsmartcard) { - return hsmartcard->State; + uint32_t temp1= 0x00, temp2 = 0x00; + temp1 = hsmartcard->gState; + temp2 = hsmartcard->RxState; + + return (HAL_SMARTCARD_StateTypeDef)(temp1 | temp2); } /** * @brief Return the SMARTCARD handle error code. - * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains * the configuration information for the specified SMARTCARD module. -* @retval SMARTCARD handle Error Code + * @retval SMARTCARD handle Error Code */ uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsmartcard) { @@ -1017,9 +974,9 @@ uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsmartcard) */ static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard) { - if ((hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX) || (hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX_RX)) + /* Check that a Tx process is ongoing */ + if (hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX) { - if(hsmartcard->TxXferCount == 0) { /* Disable the SMARTCARD Transmit Data Register Empty Interrupt */ @@ -1055,19 +1012,16 @@ static HAL_StatusTypeDef SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmar /* Disable the SMARTCARD Transmit Complete Interrupt */ __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_TC); - /* Check if a receive process is ongoing or not */ - if(hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX_RX) - { - hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_RX; - } - else + /* Check if a receive process is ongoing or not. If not disable ERR IT */ + if(hsmartcard->RxState == HAL_SMARTCARD_STATE_READY) { /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */ __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_ERR); - - hsmartcard->State = HAL_SMARTCARD_STATE_READY; } + /* Tx process is ended, restore hsmartcard->gState to Ready */ + hsmartcard->gState = HAL_SMARTCARD_STATE_READY; + HAL_SMARTCARD_TxCpltCallback(hsmartcard); return HAL_OK; @@ -1084,31 +1038,27 @@ static HAL_StatusTypeDef SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmar */ static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard) { - if ((hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_RX) || (hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX_RX)) + /* Check that a Rx process is ongoing */ + if (hsmartcard->RxState == HAL_SMARTCARD_STATE_BUSY_RX) { - *hsmartcard->pRxBuffPtr++ = (uint8_t)(hsmartcard->Instance->RDR & (uint8_t)0xFF); if(--hsmartcard->RxXferCount == 0) { __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_RXNE); - /* Check if a transmit Process is ongoing or not */ - if(hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX_RX) + /* Check if a transmit process is ongoing or not. If not disable ERR IT */ + if(hsmartcard->gState == HAL_SMARTCARD_STATE_READY) { - hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_TX; - } - else - { - /* Disable the SMARTCARD Parity Error Interrupt */ - __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_PE); - /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */ __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_ERR); - - hsmartcard->State = HAL_SMARTCARD_STATE_READY; } + /* Disable the SMARTCARD Parity Error Interrupt */ + __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_PE); + + hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; + HAL_SMARTCARD_RxCpltCallback(hsmartcard); return HAL_OK; @@ -1118,6 +1068,9 @@ static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcar } else { + /* Clear RXNE interrupt flag */ + __HAL_SMARTCARD_SEND_REQ(hsmartcard, SMARTCARD_RXDATA_FLUSH_REQUEST); + return HAL_BUSY; } } @@ -1151,7 +1104,8 @@ static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDe __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_PE); __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_ERR); - hsmartcard->State= HAL_SMARTCARD_STATE_READY; + hsmartcard->gState = HAL_SMARTCARD_STATE_READY; + hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hsmartcard); @@ -1176,7 +1130,8 @@ static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDe __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_PE); __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_ERR); - hsmartcard->State= HAL_SMARTCARD_STATE_READY; + hsmartcard->gState = HAL_SMARTCARD_STATE_READY; + hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hsmartcard); @@ -1223,15 +1178,8 @@ static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma) in the SMARTCARD associated USART CR3 register */ hsmartcard->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_DMAR); - /* Check if a transmit Process is ongoing or not */ - if(hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX_RX) - { - hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_TX; - } - else - { - hsmartcard->State = HAL_SMARTCARD_STATE_READY; - } + /* At end of Rx process, restore hsmartcard->RxState to Ready */ + hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; HAL_SMARTCARD_RxCpltCallback(hsmartcard); } @@ -1247,7 +1195,8 @@ static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma) SMARTCARD_HandleTypeDef* hsmartcard = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; hsmartcard->RxXferCount = 0; hsmartcard->TxXferCount = 0; - hsmartcard->State= HAL_SMARTCARD_STATE_READY; + hsmartcard->gState = HAL_SMARTCARD_STATE_READY; + hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_DMA; HAL_SMARTCARD_ErrorCallback(hsmartcard); } @@ -1335,16 +1284,16 @@ static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard switch (clocksource) { case SMARTCARD_CLOCKSOURCE_PCLK1: - hsmartcard->Instance->BRR = (uint16_t)(HAL_RCC_GetPCLK1Freq() / hsmartcard->Init.BaudRate); + hsmartcard->Instance->BRR = (uint16_t)((HAL_RCC_GetPCLK1Freq() + (hsmartcard->Init.BaudRate/2)) / hsmartcard->Init.BaudRate); break; case SMARTCARD_CLOCKSOURCE_HSI: - hsmartcard->Instance->BRR = (uint16_t)(HSI_VALUE / hsmartcard->Init.BaudRate); + hsmartcard->Instance->BRR = (uint16_t)((HSI_VALUE + (hsmartcard->Init.BaudRate/2)) / hsmartcard->Init.BaudRate); break; case SMARTCARD_CLOCKSOURCE_SYSCLK: - hsmartcard->Instance->BRR = (uint16_t)(HAL_RCC_GetSysClockFreq() / hsmartcard->Init.BaudRate); + hsmartcard->Instance->BRR = (uint16_t)((HAL_RCC_GetSysClockFreq() + (hsmartcard->Init.BaudRate/2)) / hsmartcard->Init.BaudRate); break; case SMARTCARD_CLOCKSOURCE_LSE: - hsmartcard->Instance->BRR = (uint16_t)(LSE_VALUE / hsmartcard->Init.BaudRate); + hsmartcard->Instance->BRR = (uint16_t)((LSE_VALUE + (hsmartcard->Init.BaudRate/2)) / hsmartcard->Init.BaudRate); break; case SMARTCARD_CLOCKSOURCE_UNDEFINED: default: @@ -1434,7 +1383,7 @@ static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsmar Bits are defined for some specific devices, and are available only for UART instances supporting WakeUp from Stop Mode feature. */ #if !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC) - if (IS_UART_WAKEUP_INSTANCE(hsmartcard->Instance)) + if (IS_UART_WAKEUP_FROMSTOP_INSTANCE(hsmartcard->Instance)) { /* Check if the Transmitter is enabled */ if((hsmartcard->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) @@ -1458,8 +1407,9 @@ static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsmar } #endif /* !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC) */ - /* Initialize the SMARTCARD state*/ - hsmartcard->State= HAL_SMARTCARD_STATE_READY; + /* Initialize the SMARTCARD states */ + hsmartcard->gState = HAL_SMARTCARD_STATE_READY; + hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hsmartcard); diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_smartcard.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_smartcard.h index 32e9301947..b9865d45e0 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_smartcard.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_smartcard.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f0xx_hal_smartcard.h * @author MCD Application Team - * @version V1.3.1 - * @date 29-January-2016 + * @version V1.4.0 + * @date 27-May-2016 * @brief Header file of SMARTCARD HAL module. ****************************************************************************** * @attention @@ -157,18 +157,63 @@ typedef struct }SMARTCARD_AdvFeatureInitTypeDef; /** - * @brief HAL State structures definition + * @brief HAL SMARTCARD State structures definition + * @note HAL SMARTCARD State value is a combination of 2 different substates: gState and RxState. + * - gState contains SMARTCARD state information related to global Handle management + * and also information related to Tx operations. + * gState value coding follow below described bitmap : + * b7-b6 Error information + * 00 : No Error + * 01 : (Not Used) + * 10 : Timeout + * 11 : Error + * b5 IP initilisation status + * 0 : Reset (IP not initialized) + * 1 : Init done (IP not initialized. HAL SMARTCARD Init function already called) + * b4-b3 (not used) + * xx : Should be set to 00 + * b2 Intrinsic process state + * 0 : Ready + * 1 : Busy (IP busy with some configuration or internal operations) + * b1 (not used) + * x : Should be set to 0 + * b0 Tx state + * 0 : Ready (no Tx operation ongoing) + * 1 : Busy (Tx operation ongoing) + * - RxState contains information related to Rx operations. + * RxState value coding follow below described bitmap : + * b7-b6 (not used) + * xx : Should be set to 00 + * b5 IP initilisation status + * 0 : Reset (IP not initialized) + * 1 : Init done (IP not initialized) + * b4-b2 (not used) + * xxx : Should be set to 000 + * b1 Rx state + * 0 : Ready (no Rx operation ongoing) + * 1 : Busy (Rx operation ongoing) + * b0 (not used) + * x : Should be set to 0. */ typedef enum { - HAL_SMARTCARD_STATE_RESET = 0x00, /*!< Peripheral is not initialized */ - HAL_SMARTCARD_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */ - HAL_SMARTCARD_STATE_BUSY = 0x02, /*!< an internal process is ongoing */ - HAL_SMARTCARD_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */ - HAL_SMARTCARD_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */ - HAL_SMARTCARD_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */ - HAL_SMARTCARD_STATE_TIMEOUT = 0x03, /*!< Timeout state */ - HAL_SMARTCARD_STATE_ERROR = 0x04 /*!< Error */ + HAL_SMARTCARD_STATE_RESET = 0x00U, /*!< Peripheral is not initialized + Value is allowed for gState and RxState */ + HAL_SMARTCARD_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use + Value is allowed for gState and RxState */ + HAL_SMARTCARD_STATE_BUSY = 0x24U, /*!< an internal process is ongoing + Value is allowed for gState only */ + HAL_SMARTCARD_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing + Value is allowed for gState only */ + HAL_SMARTCARD_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing + Value is allowed for RxState only */ + HAL_SMARTCARD_STATE_BUSY_TX_RX = 0x23U, /*!< Data Transmission and Reception process is ongoing + Not to be used for neither gState nor RxState. + Value is result of combination (Or) between gState and RxState values */ + HAL_SMARTCARD_STATE_TIMEOUT = 0xA0U, /*!< Timeout state + Value is allowed for gState only */ + HAL_SMARTCARD_STATE_ERROR = 0xE0U /*!< Error + Value is allowed for gState only */ }HAL_SMARTCARD_StateTypeDef; /** @@ -212,7 +257,12 @@ typedef struct HAL_LockTypeDef Lock; /*!< Locking object */ - __IO HAL_SMARTCARD_StateTypeDef State; /*!< SmartCard communication state */ + __IO HAL_SMARTCARD_StateTypeDef gState; /*!< SmartCard state information related to global Handle management + and also related to Tx operations. + This parameter can be a value of @ref HAL_SMARTCARD_StateTypeDef */ + + __IO HAL_SMARTCARD_StateTypeDef RxState; /*!< SmartCard state information related to Rx operations. + This parameter can be a value of @ref HAL_SMARTCARD_StateTypeDef */ __IO uint32_t ErrorCode; /*!< SmartCard Error code This parameter can be a value of @ref SMARTCARD_Error */ @@ -254,10 +304,11 @@ typedef struct * @} */ -/** @defgroup SMARTCARD_Stop_Bits SMARTCARD Stop Bits +/** @defgroup SMARTCARD_Stop_Bits SMARTCARD Number of Stop Bits * @{ */ -#define SMARTCARD_STOPBITS_1_5 USART_CR2_STOP /*!< SMARTCARD frame with 1.5 stop bits */ +#define SMARTCARD_STOPBITS_0_5 ((uint32_t)USART_CR2_STOP_0) /*!< SMARTCARD frame with 0.5 stop bit */ +#define SMARTCARD_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1)) /*!< SMARTCARD frame with 1.5 stop bits */ /** * @} */ @@ -529,11 +580,14 @@ typedef struct * @{ */ -/** @brief Reset SMARTCARD handle state. +/** @brief Reset SMARTCARD handle states. * @param __HANDLE__: SMARTCARD handle. * @retval None */ -#define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SMARTCARD_STATE_RESET) +#define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET; \ + (__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET; \ + } while(0) /** @brief Flush the Smartcard Data registers. * @param __HANDLE__: specifies the SMARTCARD Handle. @@ -801,7 +855,8 @@ typedef struct * @param __STOPBITS__: SMARTCARD frame number of stop bits. * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid) */ -#define IS_SMARTCARD_STOPBITS(__STOPBITS__) ((__STOPBITS__) == SMARTCARD_STOPBITS_1_5) +#define IS_SMARTCARD_STOPBITS(__STOPBITS__) (((__STOPBITS__) == SMARTCARD_STOPBITS_0_5) ||\ + ((__STOPBITS__) == SMARTCARD_STOPBITS_1_5)) /** * @brief Ensure that SMARTCARD frame parity is valid. diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_smartcard_ex.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_smartcard_ex.c index 880397332e..74600ced00 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_smartcard_ex.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_smartcard_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f0xx_hal_smartcard_ex.c * @author MCD Application Team - * @version V1.3.1 - * @date 29-January-2016 + * @version V1.4.0 + * @date 27-May-2016 * @brief SMARTCARD HAL module driver. * * This file provides extended firmware functions to manage the following @@ -139,12 +139,12 @@ HAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut(SMARTCARD_HandleTypeDef /* Process Locked */ __HAL_LOCK(hsmartcard); - hsmartcard->State = HAL_SMARTCARD_STATE_BUSY; + hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY; /* Set the USART RTOEN bit */ hsmartcard->Instance->CR2 |= USART_CR2_RTOEN; - hsmartcard->State = HAL_SMARTCARD_STATE_READY; + hsmartcard->gState = HAL_SMARTCARD_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hsmartcard); @@ -164,12 +164,12 @@ HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef /* Process Locked */ __HAL_LOCK(hsmartcard); - hsmartcard->State = HAL_SMARTCARD_STATE_BUSY; + hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY; /* Clear the USART RTOEN bit */ hsmartcard->Instance->CR2 &= ~(USART_CR2_RTOEN); - hsmartcard->State = HAL_SMARTCARD_STATE_READY; + hsmartcard->gState = HAL_SMARTCARD_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hsmartcard); diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_smartcard_ex.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_smartcard_ex.h index 29487a9c86..d448f5776c 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_smartcard_ex.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_smartcard_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f0xx_hal_smartcard_ex.h * @author MCD Application Team - * @version V1.3.1 - * @date 29-January-2016 + * @version V1.4.0 + * @date 27-May-2016 * @brief Header file of SMARTCARD HAL Extended module. ****************************************************************************** * @attention diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_smbus.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_smbus.c index 24a7777f9e..e248db5e24 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_smbus.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_smbus.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f0xx_hal_smbus.c * @author MCD Application Team - * @version V1.3.1 - * @date 29-January-2016 + * @version V1.4.0 + * @date 27-May-2016 * @brief SMBUS HAL module driver. * This file provides firmware functions to manage the following * functionalities of the System Management Bus (SMBus) peripheral, @@ -438,7 +438,8 @@ HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus) * @brief Transmit in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt. * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains * the configuration information for the specified SMBUS. - * @param DevAddress Target device address + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shift at right before call interface * @param pData Pointer to data buffer * @param Size Amount of data to be sent * @param XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition @@ -526,7 +527,8 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint * @brief Receive in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt. * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains * the configuration information for the specified SMBUS. - * @param DevAddress Target device address + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shift at right before call interface * @param pData Pointer to data buffer * @param Size Amount of data to be sent * @param XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition @@ -608,7 +610,8 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint1 * @note This abort can be called only if state is ready * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains * the configuration information for the specified SMBUS. - * @param DevAddress Target device address + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shift at right before call interface * @retval HAL status */ HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress) @@ -911,7 +914,8 @@ HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus) * @brief Check if target device is ready for communication. * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains * the configuration information for the specified SMBUS. - * @param DevAddress Target device address + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shift at right before call interface * @param Trials Number of trials * @param Timeout Timeout duration * @retval HAL status diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_smbus.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_smbus.h index 325124baf7..381749ceb0 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_smbus.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_smbus.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f0xx_hal_smbus.h * @author MCD Application Team - * @version V1.3.1 - * @date 29-January-2016 + * @version V1.4.0 + * @date 27-May-2016 * @brief Header file of SMBUS HAL module. ****************************************************************************** * @attention diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_spi.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_spi.c index 7af9772925..b0fb287687 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_spi.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_spi.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f0xx_hal_spi.c * @author MCD Application Team - * @version V1.3.1 - * @date 29-January-2016 + * @version V1.4.0 + * @date 27-May-2016 * @brief SPI HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Serial Peripheral Interface (SPI) peripheral: @@ -52,37 +52,9 @@ (#) The CRC feature is not managed when the DMA circular mode is enabled (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks - [..] - Using the HAL it is not possible to reach all supported SPI frequency with the differents - the following table resume the max SPI frequency reached with data size 8bits/16bits, - according to frequency used on APBx Peripheral Clock (fPCLK) used by the SPI instance : - +----------------------------------------------------------------------------------------- - | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line - | Process | Tranfert mode |---------------------|---------------------|------------------ - | | | Master | Slave | Master | Slave | Master | Slave - |========================================================================================= - | T | Polling | fPCLK/32 | fPCLK/32 | NA | NA | NA | NA - | X |----------------|----------|----------|----------|----------|----------|------- - | / | Interrupt | fPCLK/32 | fPCLK/32 | NA | NA | NA | NA - | R |----------------|----------|----------|----------|----------|----------|------- - | X | DMA | fPCLK/32 | fPCLK/16 | NA | NA | NA | NA - |=========|================|==========|==========|==========|==========|==========|======= - | | Polling | fPCLK/32 | fPCLK/16 | fPCLK/16 | fPCLK/16 | fPCLK/16 | fPCLK/ - | |----------------|----------|----------|----------|----------|----------|------- - | R | Interrupt | fPCLK/16 | fPCLK/16 | fPCLK/16 | fPCLK/16 | fPCLK/16 | fPCLK/ - | X |----------------|----------|----------|----------|----------|----------|------- - | | DMA | fPCLK/4 | fPCLK/8 | fPCLK/4 | fPCLK/4 | fPCLK/8 | fPCLK/ - |=========|================|==========|==========|==========|==========|==========|======= - | | Polling | fPCLK/16 | fPCLK/16 | NA | NA | fPCLK/16 | fPCLK/ - | |----------------|----------|----------|----------|----------|----------|------- - | T | Interrupt | fPCLK/32 | fPCLK/16 | NA | NA | fPCLK/16 | fPCLK/ - | X |----------------|----------|----------|----------|----------|----------|------- - | | DMA | fPCLK/2 | fPCLK/16 | NA | NA | fPCLK/8 | fPCLK/ - +----------------------------------------------------------------------------------------- - @note The max SPI frequency depend on SPI data size (4bits, 5bits,..., 8bits,...15bits, 16 - SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling + @note - (#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_S + (#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA() (#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA() (#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA() @@ -117,6 +89,39 @@ ****************************************************************************** */ +/* + Additional Table: + + Using the HAL it is not possible to reach all supported SPI frequency with the differents + the following table resume the max SPI frequency reached with data size 8bits/16bits, + according to frequency used on APBx Peripheral Clock (fPCLK) used by the SPI instance : + +----------------------------------------------------------------------------------------- + | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line + | Process | Tranfert mode |---------------------|---------------------|------------------ + | | | Master | Slave | Master | Slave | Master | Slave + |========================================================================================= + | T | Polling | fPCLK/32 | fPCLK/32 | NA | NA | NA | NA + | X |----------------|----------|----------|----------|----------|----------|------- + | / | Interrupt | fPCLK/32 | fPCLK/32 | NA | NA | NA | NA + | R |----------------|----------|----------|----------|----------|----------|------- + | X | DMA | fPCLK/32 | fPCLK/16 | NA | NA | NA | NA + |=========|================|==========|==========|==========|==========|==========|======= + | | Polling | fPCLK/32 | fPCLK/16 | fPCLK/16 | fPCLK/16 | fPCLK/16 | fPCLK/ + | |----------------|----------|----------|----------|----------|----------|------- + | R | Interrupt | fPCLK/16 | fPCLK/16 | fPCLK/16 | fPCLK/16 | fPCLK/16 | fPCLK/ + | X |----------------|----------|----------|----------|----------|----------|------- + | | DMA | fPCLK/4 | fPCLK/8 | fPCLK/4 | fPCLK/4 | fPCLK/8 | fPCLK/ + |=========|================|==========|==========|==========|==========|==========|======= + | | Polling | fPCLK/16 | fPCLK/16 | NA | NA | fPCLK/16 | fPCLK/ + | |----------------|----------|----------|----------|----------|----------|------- + | T | Interrupt | fPCLK/32 | fPCLK/16 | NA | NA | fPCLK/16 | fPCLK/ + | X |----------------|----------|----------|----------|----------|----------|------- + | | DMA | fPCLK/2 | fPCLK/16 | NA | NA | fPCLK/8 | fPCLK/ + +----------------------------------------------------------------------------------------- + @note The max SPI frequency depend on SPI data size (4bits, 5bits,..., 8bits,...15bits, 16 + SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling +*/ + /* Includes ------------------------------------------------------------------*/ #include "stm32f0xx_hal.h" @@ -868,6 +873,11 @@ __IO uint16_t tmpreg; /* Enable CRC Transmission */ if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) { + /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */ + if(((hspi->Instance->CR1 & SPI_CR1_MSTR) == 0) && ((hspi->Instance->CR2 & SPI_CR2_NSSP) == SPI_CR2_NSSP)) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM); + } hspi->Instance->CR1|= SPI_CR1_CRCNEXT; } } @@ -909,6 +919,11 @@ __IO uint16_t tmpreg; /* Enable CRC Transmission */ if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) { + /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */ + if(((hspi->Instance->CR1 & SPI_CR1_MSTR) == 0) && ((hspi->Instance->CR2 & SPI_CR2_NSSP) == SPI_CR2_NSSP)) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM); + } hspi->Instance->CR1 |= SPI_CR1_CRCNEXT; } } @@ -2282,7 +2297,9 @@ static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi) { if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { - hspi->Instance->CR1 |= SPI_CR1_CRCNEXT; + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE); + return; } /* Disable TXE interrupt */ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE); @@ -2362,7 +2379,9 @@ static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi) { if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { - hspi->Instance->CR1 |= SPI_CR1_CRCNEXT; + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE); + return; } /* Disable TXE interrupt */ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE); @@ -2596,8 +2615,8 @@ static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, if((Timeout == 0) || ((HAL_GetTick()-tickstart) >= Timeout)) { /* Disable the SPI and reset the CRC: the CRC value should be cleared - on both master and slave sides in order to resynchronize the master - and slave for their respective CRC calculation */ + on both master and slave sides in order to resynchronize the master + and slave for their respective CRC calculation */ /* Disable TXE, RXNE and ERR interrupts for the interrupt process */ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); @@ -2714,12 +2733,12 @@ static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi) { if(hspi->State == HAL_SPI_STATE_BUSY_RX) { - hspi->State = HAL_SPI_STATE_READY; + hspi->State = HAL_SPI_STATE_READY; HAL_SPI_RxCpltCallback(hspi); } else { - hspi->State = HAL_SPI_STATE_READY; + hspi->State = HAL_SPI_STATE_READY; HAL_SPI_TxRxCpltCallback(hspi); } } diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_spi.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_spi.h index 2d505ffaee..b802c8ffa8 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_spi.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_spi.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f0xx_hal_spi.h * @author MCD Application Team - * @version V1.3.1 - * @date 29-January-2016 + * @version V1.4.0 + * @date 27-May-2016 * @brief Header file of SPI HAL module. ****************************************************************************** * @attention @@ -99,7 +99,7 @@ typedef struct This parameter can be a value of @ref SPI_CRC_Calculation */ uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. - This parameter must be a number between Min_Data = 0 and Max_Data = 65535 */ + This parameter must be an odd number between Min_Data = 0 and Max_Data = 65535 */ uint32_t CRCLength; /*!< Specifies the CRC Length used for the CRC calculation. CRC Length is only used with Data8 and Data16, not other data size @@ -132,37 +132,37 @@ typedef enum */ typedef struct __SPI_HandleTypeDef { - SPI_TypeDef *Instance; /* SPI registers base address */ + SPI_TypeDef *Instance; /*!< SPI registers base address */ - SPI_InitTypeDef Init; /* SPI communication parameters */ + SPI_InitTypeDef Init; /*!< SPI communication parameters */ - uint8_t *pTxBuffPtr; /* Pointer to SPI Tx transfer Buffer */ + uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */ - uint16_t TxXferSize; /* SPI Tx Transfer size */ + uint16_t TxXferSize; /*!< SPI Tx Transfer size */ - uint16_t TxXferCount; /* SPI Tx Transfer Counter */ + __IO uint16_t TxXferCount; /*!< SPI Tx Transfer Counter */ - uint8_t *pRxBuffPtr; /* Pointer to SPI Rx transfer Buffer */ + uint8_t *pRxBuffPtr; /*!< Pointer to SPI Rx transfer Buffer */ - uint16_t RxXferSize; /* SPI Rx Transfer size */ + uint16_t RxXferSize; /*!< SPI Rx Transfer size */ - uint16_t RxXferCount; /* SPI Rx Transfer Counter */ + __IO uint16_t RxXferCount; /*!< SPI Rx Transfer Counter */ - uint32_t CRCSize; /* SPI CRC size used for the transfer */ + uint32_t CRCSize; /*!< SPI CRC size used for the transfer */ - void (*RxISR)(struct __SPI_HandleTypeDef *hspi); /* function pointer on Rx IRQ handler */ + void (*RxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Rx IRQ handler */ - void (*TxISR)(struct __SPI_HandleTypeDef *hspi); /* function pointer on Tx IRQ handler */ + void (*TxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Tx IRQ handler */ - DMA_HandleTypeDef *hdmatx; /* SPI Tx DMA Handle parameters */ + DMA_HandleTypeDef *hdmatx; /*!< SPI Tx DMA Handle parameters */ - DMA_HandleTypeDef *hdmarx; /* SPI Rx DMA Handle parameters */ + DMA_HandleTypeDef *hdmarx; /*!< SPI Rx DMA Handle parameters */ - HAL_LockTypeDef Lock; /* Locking object */ + HAL_LockTypeDef Lock; /*!< Locking object */ - __IO HAL_SPI_StateTypeDef State; /* SPI communication state */ + __IO HAL_SPI_StateTypeDef State; /*!< SPI communication state */ - uint32_t ErrorCode; /* SPI Error code */ + __IO uint32_t ErrorCode; /*!< SPI Error code */ }SPI_HandleTypeDef; @@ -197,8 +197,6 @@ typedef struct __SPI_HandleTypeDef */ #define SPI_MODE_SLAVE ((uint32_t)0x00000000) #define SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI) -#define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \ - ((MODE) == SPI_MODE_MASTER)) /** * @} */ @@ -209,15 +207,6 @@ typedef struct __SPI_HandleTypeDef #define SPI_DIRECTION_2LINES ((uint32_t)0x00000000) #define SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY #define SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE - -#define IS_SPI_DIRECTION(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \ - ((MODE) == SPI_DIRECTION_2LINES_RXONLY) ||\ - ((MODE) == SPI_DIRECTION_1LINE)) - -#define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES) - -#define IS_SPI_DIRECTION_2LINES_OR_1LINE(MODE) (((MODE) == SPI_DIRECTION_2LINES)|| \ - ((MODE) == SPI_DIRECTION_1LINE)) /** * @} */ @@ -238,19 +227,6 @@ typedef struct __SPI_HandleTypeDef #define SPI_DATASIZE_14BIT ((uint32_t)0x0D00) /*!< SPI Datasize = 14bits */ #define SPI_DATASIZE_15BIT ((uint32_t)0x0E00) /*!< SPI Datasize = 15bits */ #define SPI_DATASIZE_16BIT ((uint32_t)0x0F00) /*!< SPI Datasize = 16bits */ -#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_16BIT) || \ - ((DATASIZE) == SPI_DATASIZE_15BIT) || \ - ((DATASIZE) == SPI_DATASIZE_14BIT) || \ - ((DATASIZE) == SPI_DATASIZE_13BIT) || \ - ((DATASIZE) == SPI_DATASIZE_12BIT) || \ - ((DATASIZE) == SPI_DATASIZE_11BIT) || \ - ((DATASIZE) == SPI_DATASIZE_10BIT) || \ - ((DATASIZE) == SPI_DATASIZE_9BIT) || \ - ((DATASIZE) == SPI_DATASIZE_8BIT) || \ - ((DATASIZE) == SPI_DATASIZE_7BIT) || \ - ((DATASIZE) == SPI_DATASIZE_6BIT) || \ - ((DATASIZE) == SPI_DATASIZE_5BIT) || \ - ((DATASIZE) == SPI_DATASIZE_4BIT)) /** * @} */ @@ -260,8 +236,6 @@ typedef struct __SPI_HandleTypeDef */ #define SPI_POLARITY_LOW ((uint32_t)0x00000000) /*!< SPI polarity Low */ #define SPI_POLARITY_HIGH SPI_CR1_CPOL /*!< SPI polarity High */ -#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_POLARITY_LOW) || \ - ((CPOL) == SPI_POLARITY_HIGH)) /** * @} */ @@ -271,8 +245,6 @@ typedef struct __SPI_HandleTypeDef */ #define SPI_PHASE_1EDGE ((uint32_t)0x00000000) /*!< SPI Phase 1EDGE */ #define SPI_PHASE_2EDGE SPI_CR1_CPHA /*!< SPI Phase 2EDGE */ -#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_PHASE_1EDGE) || \ - ((CPHA) == SPI_PHASE_2EDGE)) /** * @} */ @@ -283,9 +255,6 @@ typedef struct __SPI_HandleTypeDef #define SPI_NSS_SOFT SPI_CR1_SSM #define SPI_NSS_HARD_INPUT ((uint32_t)0x00000000) #define SPI_NSS_HARD_OUTPUT ((uint32_t)0x00040000) -#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT) || \ - ((NSS) == SPI_NSS_HARD_INPUT) || \ - ((NSS) == SPI_NSS_HARD_OUTPUT)) /** * @} */ @@ -295,9 +264,6 @@ typedef struct __SPI_HandleTypeDef */ #define SPI_NSS_PULSE_ENABLE SPI_CR2_NSSP #define SPI_NSS_PULSE_DISABLE ((uint32_t)0x00000000) - -#define IS_SPI_NSSP(NSSP) (((NSSP) == SPI_NSS_PULSE_ENABLE) || \ - ((NSSP) == SPI_NSS_PULSE_DISABLE)) /** * @} */ @@ -313,14 +279,6 @@ typedef struct __SPI_HandleTypeDef #define SPI_BAUDRATEPRESCALER_64 ((uint32_t)0x00000028) #define SPI_BAUDRATEPRESCALER_128 ((uint32_t)0x00000030) #define SPI_BAUDRATEPRESCALER_256 ((uint32_t)0x00000038) -#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_2) || \ - ((PRESCALER) == SPI_BAUDRATEPRESCALER_4) || \ - ((PRESCALER) == SPI_BAUDRATEPRESCALER_8) || \ - ((PRESCALER) == SPI_BAUDRATEPRESCALER_16) || \ - ((PRESCALER) == SPI_BAUDRATEPRESCALER_32) || \ - ((PRESCALER) == SPI_BAUDRATEPRESCALER_64) || \ - ((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \ - ((PRESCALER) == SPI_BAUDRATEPRESCALER_256)) /** * @} */ @@ -330,8 +288,6 @@ typedef struct __SPI_HandleTypeDef */ #define SPI_FIRSTBIT_MSB ((uint32_t)0x00000000) #define SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST -#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FIRSTBIT_MSB) || \ - ((BIT) == SPI_FIRSTBIT_LSB)) /** * @} */ @@ -341,8 +297,6 @@ typedef struct __SPI_HandleTypeDef */ #define SPI_TIMODE_DISABLE ((uint32_t)0x00000000) #define SPI_TIMODE_ENABLE SPI_CR2_FRF -#define IS_SPI_TIMODE(MODE) (((MODE) == SPI_TIMODE_DISABLE) || \ - ((MODE) == SPI_TIMODE_ENABLE)) /** * @} */ @@ -352,8 +306,6 @@ typedef struct __SPI_HandleTypeDef */ #define SPI_CRCCALCULATION_DISABLE ((uint32_t)0x00000000) #define SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN -#define IS_SPI_CRC_CALCULATION(CALCULATION) (((CALCULATION) == SPI_CRCCALCULATION_DISABLE) || \ - ((CALCULATION) == SPI_CRCCALCULATION_ENABLE)) /** * @} */ @@ -368,9 +320,6 @@ typedef struct __SPI_HandleTypeDef #define SPI_CRC_LENGTH_DATASIZE ((uint32_t)0x00000000) #define SPI_CRC_LENGTH_8BIT ((uint32_t)0x00000001) #define SPI_CRC_LENGTH_16BIT ((uint32_t)0x00000002) -#define IS_SPI_CRC_LENGTH(LENGTH) (((LENGTH) == SPI_CRC_LENGTH_DATASIZE) ||\ - ((LENGTH) == SPI_CRC_LENGTH_8BIT) || \ - ((LENGTH) == SPI_CRC_LENGTH_16BIT)) /** * @} */ @@ -521,10 +470,10 @@ typedef struct __SPI_HandleTypeDef */ #define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) \ do{ \ - __IO uint32_t tmpreg; \ - tmpreg = (__HANDLE__)->Instance->SR; \ + __IO uint32_t tmpreg_modf; \ + tmpreg_modf = (__HANDLE__)->Instance->SR; \ (__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE); \ - UNUSED(tmpreg); \ + UNUSED(tmpreg_modf); \ } while(0) /** @brief Clear the SPI OVR pending flag. @@ -535,10 +484,10 @@ typedef struct __SPI_HandleTypeDef */ #define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) \ do{ \ - __IO uint32_t tmpreg; \ - tmpreg = (__HANDLE__)->Instance->DR; \ - tmpreg = (__HANDLE__)->Instance->SR; \ - UNUSED(tmpreg); \ + __IO uint32_t tmpreg_ovr; \ + tmpreg_ovr = (__HANDLE__)->Instance->DR; \ + tmpreg_ovr = (__HANDLE__)->Instance->SR; \ + UNUSED(tmpreg_ovr); \ } while(0) /** @brief Clear the SPI FRE pending flag. @@ -549,9 +498,9 @@ typedef struct __SPI_HandleTypeDef */ #define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) \ do{ \ - __IO uint32_t tmpreg; \ - tmpreg = (__HANDLE__)->Instance->SR; \ - UNUSED(tmpreg); \ + __IO uint32_t tmpreg_fre; \ + tmpreg_fre = (__HANDLE__)->Instance->SR; \ + UNUSED(tmpreg_fre); \ } while(0) /** @brief Enable the SPI peripheral. @@ -599,8 +548,68 @@ typedef struct __SPI_HandleTypeDef #define SPI_RESET_CRC(__HANDLE__) do{(__HANDLE__)->Instance->CR1 &= (uint16_t)(~SPI_CR1_CRCEN);\ (__HANDLE__)->Instance->CR1 |= SPI_CR1_CRCEN;}while(0) +#define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \ + ((MODE) == SPI_MODE_MASTER)) -#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x1) && ((POLYNOMIAL) <= 0xFFFF)) +#define IS_SPI_DIRECTION(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \ + ((MODE) == SPI_DIRECTION_2LINES_RXONLY) ||\ + ((MODE) == SPI_DIRECTION_1LINE)) + +#define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES) + +#define IS_SPI_DIRECTION_2LINES_OR_1LINE(MODE) (((MODE) == SPI_DIRECTION_2LINES)|| \ + ((MODE) == SPI_DIRECTION_1LINE)) + +#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_16BIT) || \ + ((DATASIZE) == SPI_DATASIZE_15BIT) || \ + ((DATASIZE) == SPI_DATASIZE_14BIT) || \ + ((DATASIZE) == SPI_DATASIZE_13BIT) || \ + ((DATASIZE) == SPI_DATASIZE_12BIT) || \ + ((DATASIZE) == SPI_DATASIZE_11BIT) || \ + ((DATASIZE) == SPI_DATASIZE_10BIT) || \ + ((DATASIZE) == SPI_DATASIZE_9BIT) || \ + ((DATASIZE) == SPI_DATASIZE_8BIT) || \ + ((DATASIZE) == SPI_DATASIZE_7BIT) || \ + ((DATASIZE) == SPI_DATASIZE_6BIT) || \ + ((DATASIZE) == SPI_DATASIZE_5BIT) || \ + ((DATASIZE) == SPI_DATASIZE_4BIT)) + +#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_POLARITY_LOW) || \ + ((CPOL) == SPI_POLARITY_HIGH)) + +#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_PHASE_1EDGE) || \ + ((CPHA) == SPI_PHASE_2EDGE)) + +#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT) || \ + ((NSS) == SPI_NSS_HARD_INPUT) || \ + ((NSS) == SPI_NSS_HARD_OUTPUT)) + +#define IS_SPI_NSSP(NSSP) (((NSSP) == SPI_NSS_PULSE_ENABLE) || \ + ((NSSP) == SPI_NSS_PULSE_DISABLE)) + +#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_2) || \ + ((PRESCALER) == SPI_BAUDRATEPRESCALER_4) || \ + ((PRESCALER) == SPI_BAUDRATEPRESCALER_8) || \ + ((PRESCALER) == SPI_BAUDRATEPRESCALER_16) || \ + ((PRESCALER) == SPI_BAUDRATEPRESCALER_32) || \ + ((PRESCALER) == SPI_BAUDRATEPRESCALER_64) || \ + ((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \ + ((PRESCALER) == SPI_BAUDRATEPRESCALER_256)) + +#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FIRSTBIT_MSB) || \ + ((BIT) == SPI_FIRSTBIT_LSB)) + +#define IS_SPI_TIMODE(MODE) (((MODE) == SPI_TIMODE_DISABLE) || \ + ((MODE) == SPI_TIMODE_ENABLE)) + +#define IS_SPI_CRC_CALCULATION(CALCULATION) (((CALCULATION) == SPI_CRCCALCULATION_DISABLE) || \ + ((CALCULATION) == SPI_CRCCALCULATION_ENABLE)) + +#define IS_SPI_CRC_LENGTH(LENGTH) (((LENGTH) == SPI_CRC_LENGTH_DATASIZE) ||\ + ((LENGTH) == SPI_CRC_LENGTH_8BIT) || \ + ((LENGTH) == SPI_CRC_LENGTH_16BIT)) + +#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x1) && ((POLYNOMIAL) <= 0xFFFF) && (((POLYNOMIAL)&0x1) != 0)) /** diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_spi_ex.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_spi_ex.c index b3cc805a6b..b3e44f0d24 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_spi_ex.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_spi_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f0xx_hal_spi_ex.c * @author MCD Application Team - * @version V1.3.1 - * @date 29-January-2016 + * @version V1.4.0 + * @date 27-May-2016 * @brief Extended SPI HAL module driver. * This file provides firmware functions to manage the following * SPI peripheral extended functionalities : diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_spi_ex.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_spi_ex.h index b4acc2155d..0625cca197 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_spi_ex.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_spi_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f0xx_hal_spi_ex.h * @author MCD Application Team - * @version V1.3.1 - * @date 29-January-2016 + * @version V1.4.0 + * @date 27-May-2016 * @brief Header file of SPI HAL Extended module. ****************************************************************************** * @attention diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_tim.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_tim.c index d17dff48a7..f3a032f2c1 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_tim.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_tim.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f0xx_hal_tim.c * @author MCD Application Team - * @version V1.3.1 - * @date 29-January-2016 + * @version V1.4.0 + * @date 27-May-2016 * @brief TIM HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Timer (TIM) peripheral: @@ -159,8 +159,6 @@ static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 uint32_t TIM_ICFilter); static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter); -static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler, - uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter); static void TIM_ITRx_SetConfig(TIM_TypeDef* TIMx, uint16_t InputTriggerSource); static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma); static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma); @@ -1148,7 +1146,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Starts the PWM signal generation in interrupt mode. * @param htim : TIM handle - * @param Channel : TIM Channel to be disabled + * @param Channel : TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -3790,7 +3788,7 @@ HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventS * @arg TIM_CHANNEL_4: TIM Channel 4 * @retval HAL status */ -HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel) +__weak HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel) { uint32_t tmpsmcr = 0; @@ -4893,7 +4891,7 @@ static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) TIMx->CCER = tmpccer; } -void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, +static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig) { uint32_t tmpsmcr = 0; @@ -5331,7 +5329,7 @@ static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t InputTriggerSource) * This parameter must be a value between 0x00 and 0x0F * @retval None */ -static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler, +void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter) { uint32_t tmpsmcr = 0; diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_tim.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_tim.h index c9a902af30..b5181993d7 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_tim.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_tim.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f0xx_hal_tim.h * @author MCD Application Team - * @version V1.3.1 - * @date 29-January-2016 + * @version V1.4.0 + * @date 27-May-2016 * @brief Header file of TIM HAL module. ****************************************************************************** * @attention @@ -230,7 +230,7 @@ typedef struct uint32_t ClearInputState; /*!< TIM clear Input state This parameter can be ENABLE or DISABLE */ uint32_t ClearInputSource; /*!< TIM clear Input sources - This parameter can be a value of @ref TIM_ClearInput_Source */ + This parameter can be a value of @ref TIMEx_Clock_Clear_Input_Source */ uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity This parameter can be a value of @ref TIM_ClearInput_Polarity */ uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler @@ -592,15 +592,6 @@ typedef struct * @} */ -/** @defgroup TIM_ClearInput_Source TIM ClearInput Source - * @{ - */ -#define TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x0001) -#define TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x0000) -/** - * @} - */ - /** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity * @{ */ @@ -969,9 +960,6 @@ typedef struct #define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0xF) -#define IS_TIM_CLEARINPUT_SOURCE(SOURCE) (((SOURCE) == TIM_CLEARINPUTSOURCE_NONE) || \ - ((SOURCE) == TIM_CLEARINPUTSOURCE_ETR)) - #define IS_TIM_CLEARINPUT_POLARITY(POLARITY) (((POLARITY) == TIM_CLEARINPUTPOLARITY_INVERTED) || \ ((POLARITY) == TIM_CLEARINPUTPOLARITY_NONINVERTED)) @@ -1745,6 +1733,16 @@ HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim); * @} */ +/* Private Functions --------------------------------------------------------*/ +/** @addtogroup TIM_Private_Functions + * @{ + */ +void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler, + uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter); +/** + * @} + */ + /** * @} */ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_tim_ex.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_tim_ex.c index 0899a9a342..48671024e4 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_tim_ex.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_tim_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f0xx_hal_tim_ex.c * @author MCD Application Team - * @version V1.3.1 - * @date 29-January-2016 + * @version V1.4.0 + * @date 27-May-2016 * @brief TIM HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Timer Extended peripheral: @@ -167,7 +167,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSen return HAL_ERROR; } - assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); + assert_param(IS_TIM_HALL_INTERFACE_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity)); @@ -295,7 +295,7 @@ __weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim) HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim) { /* Check the parameters */ - assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); + assert_param(IS_TIM_HALL_INTERFACE_INSTANCE(htim->Instance)); /* Enable the Input Capture channel 1 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ @@ -316,7 +316,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim) HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim) { /* Check the parameters */ - assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); + assert_param(IS_TIM_HALL_INTERFACE_INSTANCE(htim->Instance)); /* Disable the Input Capture channels 1, 2 and 3 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ @@ -337,7 +337,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim) HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim) { /* Check the parameters */ - assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); + assert_param(IS_TIM_HALL_INTERFACE_INSTANCE(htim->Instance)); /* Enable the capture compare Interrupts 1 event */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); @@ -361,7 +361,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim) HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim) { /* Check the parameters */ - assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); + assert_param(IS_TIM_HALL_INTERFACE_INSTANCE(htim->Instance)); /* Disable the Input Capture channel 1 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ @@ -387,7 +387,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim) HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length) { /* Check the parameters */ - assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); + assert_param(IS_TIM_HALL_INTERFACE_INSTANCE(htim->Instance)); if((htim->State == HAL_TIM_STATE_BUSY)) { @@ -434,7 +434,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim) { /* Check the parameters */ - assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); + assert_param(IS_TIM_HALL_INTERFACE_INSTANCE(htim->Instance)); /* Disable the Input Capture channel 1 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ @@ -1709,6 +1709,164 @@ HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap) * @} */ +/** @addtogroup TIM_Exported_Functions_Group8 Peripheral Control functions + * @brief Peripheral Control functions + * + * @{ + */ + +#if defined(STM32F051x8) || defined(STM32F058xx) || \ + defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ + defined(STM32F091xC) || defined (STM32F098xx) +/** + * @brief Configures the OCRef clear feature + * @param htim: TIM handle + * @param sClearInputConfig: pointer to a TIM_ClearInputConfigTypeDef structure that + * contains the OCREF clear feature and parameters for the TIM peripheral. + * @param Channel: specifies the TIM Channel + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 + * @arg TIM_CHANNEL_2: TIM Channel 2 + * @arg TIM_CHANNEL_3: TIM Channel 3 + * @arg TIM_CHANNEL_4: TIM Channel 4 + * @arg TIM_Channel_5: TIM Channel 5 + * @retval None + */ +HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, + TIM_ClearInputConfigTypeDef *sClearInputConfig, + uint32_t Channel) +{ + uint32_t tmpsmcr = 0; + + /* Check the parameters */ + assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance)); + assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource)); + + /* Check input state */ + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + switch (sClearInputConfig->ClearInputSource) + { + case TIM_CLEARINPUTSOURCE_NONE: + { + /* Get the TIMx SMCR register value */ + tmpsmcr = htim->Instance->SMCR; + + /* Clear the OCREF clear selection bit */ + tmpsmcr &= ~TIM_SMCR_OCCS; + + /* Clear the ETR Bits */ + tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); + + /* Set TIMx_SMCR */ + htim->Instance->SMCR = tmpsmcr; + } + break; + + case TIM_CLEARINPUTSOURCE_OCREFCLR: + { + /* Clear the OCREF clear selection bit */ + htim->Instance->SMCR &= ~TIM_SMCR_OCCS; + } + break; + + case TIM_CLEARINPUTSOURCE_ETR: + { + /* Check the parameters */ + assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity)); + assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler)); + assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter)); + + TIM_ETR_SetConfig(htim->Instance, + sClearInputConfig->ClearInputPrescaler, + sClearInputConfig->ClearInputPolarity, + sClearInputConfig->ClearInputFilter); + + /* Set the OCREF clear selection bit */ + htim->Instance->SMCR |= TIM_SMCR_OCCS; + } + break; + default: + break; + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + if(sClearInputConfig->ClearInputState != RESET) + { + /* Enable the Ocref clear feature for Channel 1 */ + htim->Instance->CCMR1 |= TIM_CCMR1_OC1CE; + } + else + { + /* Disable the Ocref clear feature for Channel 1 */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE; + } + } + break; + case TIM_CHANNEL_2: + { + if(sClearInputConfig->ClearInputState != RESET) + { + /* Enable the Ocref clear feature for Channel 2 */ + htim->Instance->CCMR1 |= TIM_CCMR1_OC2CE; + } + else + { + /* Disable the Ocref clear feature for Channel 2 */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE; + } + } + break; + case TIM_CHANNEL_3: + { + if(sClearInputConfig->ClearInputState != RESET) + { + /* Enable the Ocref clear feature for Channel 3 */ + htim->Instance->CCMR2 |= TIM_CCMR2_OC3CE; + } + else + { + /* Disable the Ocref clear feature for Channel 3 */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE; + } + } + break; + case TIM_CHANNEL_4: + { + if(sClearInputConfig->ClearInputState != RESET) + { + /* Enable the Ocref clear feature for Channel 4 */ + htim->Instance->CCMR2 |= TIM_CCMR2_OC4CE; + } + else + { + /* Disable the Ocref clear feature for Channel 4 */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE; + } + } + break; + default: + break; + } + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} +#endif /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || defined (STM32F098xx) */ +/** + * @} + */ + /** @defgroup TIMEx_Exported_Functions_Group6 Extension Callbacks functions * @brief Extension Callbacks functions * diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_tim_ex.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_tim_ex.h index c394d958f9..0ba1757eee 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_tim_ex.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_tim_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f0xx_hal_tim_ex.h * @author MCD Application Team - * @version V1.3.1 - * @date 29-January-2016 + * @version V1.4.0 + * @date 27-May-2016 * @brief Header file of TIM HAL Extended module. ****************************************************************************** * @attention @@ -127,23 +127,54 @@ typedef struct #define TIM_TIM14_RTC (0x00000001) /*!< TIM14 TI1 is connected to RTC_clock */ #define TIM_TIM14_HSE (0x00000002) /*!< TIM14 TI1 is connected to HSE/32 */ #define TIM_TIM14_MCO (0x00000003) /*!< TIM14 TI1 is connected to MCO */ +/** + * @} + */ -#define IS_TIM_REMAP(TIM_REMAP) (((TIM_REMAP) == TIM_TIM14_GPIO) ||\ +/** @defgroup TIMEx_Clock_Clear_Input_Source TIMEx Clear Input Source + * @{ + */ +#define TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x00000000U) +#define TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x00000001U) +#if defined(STM32F051x8) || defined(STM32F058xx) || \ + defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ + defined(STM32F091xC) || defined (STM32F098xx) +#define TIM_CLEARINPUTSOURCE_OCREFCLR ((uint32_t)0x00000002U) +#endif /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || defined (STM32F098xx) */ +/** + * @} + */ + +/** + * @} + */ + +/* Private Macros -----------------------------------------------------------*/ +/** @defgroup TIM_Private_Macros TIM Private Macros + * @{ + */ + +#define IS_TIM_REMAP(TIM_REMAP) (((TIM_REMAP) == TIM_TIM14_GPIO) ||\ ((TIM_REMAP) == TIM_TIM14_RTC) ||\ ((TIM_REMAP) == TIM_TIM14_HSE) ||\ ((TIM_REMAP) == TIM_TIM14_MCO)) -/** - * @} - */ -/** @defgroup TIMEx_Clock_Filter TIMEx Clock Filter - * @{ - */ #define IS_TIM_DEADTIME(DEADTIME) ((DEADTIME) <= 0xFF) /*!< BreakDead Time */ -/** - * @} - */ +#if defined(STM32F051x8) || defined(STM32F058xx) || \ + defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ + defined(STM32F091xC) || defined (STM32F098xx) +#define IS_TIM_CLEARINPUT_SOURCE(SOURCE) (((SOURCE) == TIM_CLEARINPUTSOURCE_NONE) || \ + ((SOURCE) == TIM_CLEARINPUTSOURCE_ETR) || \ + ((SOURCE) == TIM_CLEARINPUTSOURCE_OCREFCLR)) +#else +#define IS_TIM_CLEARINPUT_SOURCE(SOURCE) (((SOURCE) == TIM_CLEARINPUTSOURCE_NONE) || \ + ((SOURCE) == TIM_CLEARINPUTSOURCE_ETR)) +#endif /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || defined (STM32F098xx) */ /** * @} */ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_tsc.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_tsc.c index 0e4a016195..d5752dcfcd 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_tsc.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_tsc.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f0xx_hal_tsc.c * @author MCD Application Team - * @version V1.3.1 - * @date 29-January-2016 + * @version V1.4.0 + * @date 27-May-2016 * @brief This file provides firmware functions to manage the following * functionalities of the Touch Sensing Controller (TSC) peripheral: * + Initialization and DeInitialization diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_tsc.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_tsc.h index 56b15d8094..5feda0748b 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_tsc.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_tsc.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f0xx_hal_tsc.h * @author MCD Application Team - * @version V1.3.1 - * @date 29-January-2016 + * @version V1.4.0 + * @date 27-May-2016 * @brief This file contains all the functions prototypes for the TSC firmware * library. ****************************************************************************** diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_uart.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_uart.c index eda2a6f498..171b125cfd 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_uart.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_uart.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f0xx_hal_uart.c * @author MCD Application Team - * @version V1.3.1 - * @date 29-January-2016 + * @version V1.4.0 + * @date 27-May-2016 * @brief UART HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Universal Asynchronous Receiver Transmitter (UART) peripheral: @@ -174,7 +174,6 @@ * @{ */ #define UART_TEACK_REACK_TIMEOUT ((uint32_t) 1000) /*!< UART TX or RX enable acknowledge time-out value */ -#define UART_TXDMA_TIMEOUTVALUE 22000 #define UART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \ USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8)) /*!< UART or USART CR1 fields of parameters set by UART_SetConfig API */ /** @@ -216,39 +215,7 @@ static void UART_DMAError(DMA_HandleTypeDef *hdma); (++) Baud Rate (++) Word Length (++) Stop Bit - (++) Parity: If the parity is enabled, then the MSB bit of the data written - in the data register is transmitted but is changed by the parity bit. - According to device capability (support or not of 7-bit word length), - frame length is either defined by the M bit (8-bits or 9-bits) - or by the M1 and M0 bits (7-bit, 8-bit or 9-bit). - Possible UART frame formats are as listed in the following table: - - (+++) Table 1. UART frame format. - (+++) +-----------------------------------------------------------------------+ - (+++) | M bit | PCE bit | UART frame | - (+++) |-------------------|-----------|---------------------------------------| - (+++) | 0 | 0 | | SB | 8-bit data | STB | | - (+++) |-------------------|-----------|---------------------------------------| - (+++) | 0 | 1 | | SB | 7-bit data | PB | STB | | - (+++) |-------------------|-----------|---------------------------------------| - (+++) | 1 | 0 | | SB | 9-bit data | STB | | - (+++) |-------------------|-----------|---------------------------------------| - (+++) | 1 | 1 | | SB | 8-bit data | PB | STB | | - (+++) +-----------------------------------------------------------------------+ - (+++) | M1 bit | M0 bit | PCE bit | UART frame | - (+++) |---------|---------|-----------|---------------------------------------| - (+++) | 0 | 0 | 0 | | SB | 8 bit data | STB | | - (+++) |---------|---------|-----------|---------------------------------------| - (+++) | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | | - (+++) |---------|---------|-----------|---------------------------------------| - (+++) | 0 | 1 | 0 | | SB | 9 bit data | STB | | - (+++) |---------|---------|-----------|---------------------------------------| - (+++) | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | | - (+++) |---------|---------|-----------|---------------------------------------| - (+++) | 1 | 0 | 0 | | SB | 7 bit data | STB | | - (+++) |---------|---------|-----------|---------------------------------------| - (+++) | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | | - (+++) +-----------------------------------------------------------------------+ + (++) Parity (++) Hardware flow control (++) Receiver/transmitter modes (++) Over Sampling Method @@ -270,6 +237,43 @@ static void UART_DMAError(DMA_HandleTypeDef *hdma); * @{ */ +/* + Additional Table: If the parity is enabled, then the MSB bit of the data written + in the data register is transmitted but is changed by the parity bit. + According to device capability (support or not of 7-bit word length), + frame length is either defined by the M bit (8-bits or 9-bits) + or by the M1 and M0 bits (7-bit, 8-bit or 9-bit). + Possible UART frame formats are as listed in the following table: + + Table 1. UART frame format. + +-----------------------------------------------------------------------+ + | M bit | PCE bit | UART frame | + |-------------------|-----------|---------------------------------------| + | 0 | 0 | | SB | 8-bit data | STB | | + |-------------------|-----------|---------------------------------------| + | 0 | 1 | | SB | 7-bit data | PB | STB | | + |-------------------|-----------|---------------------------------------| + | 1 | 0 | | SB | 9-bit data | STB | | + |-------------------|-----------|---------------------------------------| + | 1 | 1 | | SB | 8-bit data | PB | STB | | + +-----------------------------------------------------------------------+ + | M1 bit | M0 bit | PCE bit | UART frame | + |---------|---------|-----------|---------------------------------------| + | 0 | 0 | 0 | | SB | 8 bit data | STB | | + |---------|---------|-----------|---------------------------------------| + | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | | + |---------|---------|-----------|---------------------------------------| + | 0 | 1 | 0 | | SB | 9 bit data | STB | | + |---------|---------|-----------|---------------------------------------| + | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | | + |---------|---------|-----------|---------------------------------------| + | 1 | 0 | 0 | | SB | 7 bit data | STB | | + |---------|---------|-----------|---------------------------------------| + | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | | + +-----------------------------------------------------------------------+ + +*/ + /** * @brief Initialize the UART mode according to the specified * parameters in the UART_InitTypeDef and initialize the associated handle. @@ -295,7 +299,7 @@ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) assert_param(IS_UART_INSTANCE(huart->Instance)); } - if(huart->State == HAL_UART_STATE_RESET) + if(huart->gState == HAL_UART_STATE_RESET) { /* Allocate lock resource and initialize it */ huart->Lock = HAL_UNLOCKED; @@ -304,7 +308,7 @@ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) HAL_UART_MspInit(huart); } - huart->State = HAL_UART_STATE_BUSY; + huart->gState = HAL_UART_STATE_BUSY; /* Disable the Peripheral */ __HAL_UART_DISABLE(huart); @@ -345,7 +349,7 @@ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) /* Enable the Peripheral */ __HAL_UART_ENABLE(huart); - /* TEACK and/or REACK to check before moving huart->State to Ready */ + /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ return (UART_CheckIdleState(huart)); } @@ -366,7 +370,7 @@ HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart) /* Check UART instance */ assert_param(IS_UART_HALFDUPLEX_INSTANCE(huart->Instance)); - if(huart->State == HAL_UART_STATE_RESET) + if(huart->gState == HAL_UART_STATE_RESET) { /* Allocate lock resource and initialize it */ huart->Lock = HAL_UNLOCKED; @@ -375,7 +379,7 @@ HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart) HAL_UART_MspInit(huart); } - huart->State = HAL_UART_STATE_BUSY; + huart->gState = HAL_UART_STATE_BUSY; /* Disable the Peripheral */ __HAL_UART_DISABLE(huart); @@ -417,7 +421,7 @@ HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart) /* Enable the Peripheral */ __HAL_UART_ENABLE(huart); - /* TEACK and/or REACK to check before moving huart->State to Ready */ + /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ return (UART_CheckIdleState(huart)); } @@ -451,7 +455,7 @@ HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Add /* Check the wake up method parameter */ assert_param(IS_UART_WAKEUPMETHOD(WakeUpMethod)); - if(huart->State == HAL_UART_STATE_RESET) + if(huart->gState == HAL_UART_STATE_RESET) { /* Allocate lock resource and initialize it */ huart->Lock = HAL_UNLOCKED; @@ -460,7 +464,7 @@ HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Add HAL_UART_MspInit(huart); } - huart->State = HAL_UART_STATE_BUSY; + huart->gState = HAL_UART_STATE_BUSY; /* Disable the Peripheral */ __HAL_UART_DISABLE(huart); @@ -510,7 +514,7 @@ HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Add /* Enable the Peripheral */ __HAL_UART_ENABLE(huart); - /* TEACK and/or REACK to check before moving huart->State to Ready */ + /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ return (UART_CheckIdleState(huart)); } @@ -530,7 +534,7 @@ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) /* Check the parameters */ assert_param(IS_UART_INSTANCE(huart->Instance)); - huart->State = HAL_UART_STATE_BUSY; + huart->gState = HAL_UART_STATE_BUSY; /* Disable the Peripheral */ __HAL_UART_DISABLE(huart); @@ -543,7 +547,8 @@ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) HAL_UART_MspDeInit(huart); huart->ErrorCode = HAL_UART_ERROR_NONE; - huart->State = HAL_UART_STATE_RESET; + huart->gState = HAL_UART_STATE_RESET; + huart->RxState = HAL_UART_STATE_RESET; /* Process Unlock */ __HAL_UNLOCK(huart); @@ -645,32 +650,40 @@ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) * @param pData: Pointer to data buffer. * @param Size: Amount of data to be sent. * @param Timeout: Timeout duration. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits) + * (as sent data will be handled using u16 pointer cast). Depending on compilation chain, + * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout) { uint16_t* tmp; - if((huart->State == HAL_UART_STATE_READY) || (huart->State == HAL_UART_STATE_BUSY_RX)) + /* Check that a Tx process is not already ongoing */ + if(huart->gState == HAL_UART_STATE_READY) { if((pData == NULL ) || (Size == 0)) { return HAL_ERROR; } + /* In case of 9bits/No Parity transfer, pData buffer provided as input paramter + should be aligned on a u16 frontier, as data to be filled into TDR will be + handled through a u16 cast. */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + if((((uint32_t)pData)&1) != 0) + { + return HAL_ERROR; + } + } + /* Process Locked */ __HAL_LOCK(huart); huart->ErrorCode = HAL_UART_ERROR_NONE; - /* Check if a non-blocking receive process is ongoing or not */ - if(huart->State == HAL_UART_STATE_BUSY_RX) - { - huart->State = HAL_UART_STATE_BUSY_TX_RX; - } - else - { - huart->State = HAL_UART_STATE_BUSY_TX; - } + huart->gState = HAL_UART_STATE_BUSY_TX; huart->TxXferSize = Size; huart->TxXferCount = Size; @@ -696,15 +709,9 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u { return HAL_TIMEOUT; } - /* Check if a non-blocking receive Process is ongoing or not */ - if(huart->State == HAL_UART_STATE_BUSY_TX_RX) - { - huart->State = HAL_UART_STATE_BUSY_RX; - } - else - { - huart->State = HAL_UART_STATE_READY; - } + + /* At end of Tx process, restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(huart); @@ -723,6 +730,10 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u * @param pData: pointer to data buffer. * @param Size: amount of data to be received. * @param Timeout: Timeout duration. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits) + * (as received data will be handled using u16 pointer cast). Depending on compilation chain, + * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout) @@ -730,26 +741,30 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui uint16_t* tmp; uint16_t uhMask; - if((huart->State == HAL_UART_STATE_READY) || (huart->State == HAL_UART_STATE_BUSY_TX)) + /* Check that a Rx process is not already ongoing */ + if(huart->RxState == HAL_UART_STATE_READY) { if((pData == NULL ) || (Size == 0)) { return HAL_ERROR; } + /* In case of 9bits/No Parity transfer, pData buffer provided as input paramter + should be aligned on a u16 frontier, as data to be received from RDR will be + handled through a u16 cast. */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + if((((uint32_t)pData)&1) != 0) + { + return HAL_ERROR; + } + } + /* Process Locked */ __HAL_LOCK(huart); huart->ErrorCode = HAL_UART_ERROR_NONE; - /* Check if a non-blocking transmit process is ongoing or not */ - if(huart->State == HAL_UART_STATE_BUSY_TX) - { - huart->State = HAL_UART_STATE_BUSY_TX_RX; - } - else - { - huart->State = HAL_UART_STATE_BUSY_RX; - } + huart->RxState = HAL_UART_STATE_BUSY_RX; huart->RxXferSize = Size; huart->RxXferCount = Size; @@ -778,15 +793,9 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui } } - /* Check if a non-blocking transmit Process is ongoing or not */ - if(huart->State == HAL_UART_STATE_BUSY_TX_RX) - { - huart->State = HAL_UART_STATE_BUSY_TX; - } - else - { - huart->State = HAL_UART_STATE_READY; - } + /* At end of Rx process, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + /* Process Unlocked */ __HAL_UNLOCK(huart); @@ -803,17 +812,33 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui * @param huart: UART handle. * @param pData: pointer to data buffer. * @param Size: amount of data to be sent. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits) + * (as sent data will be handled using u16 pointer cast). Depending on compilation chain, + * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { - if((huart->State == HAL_UART_STATE_READY) || (huart->State == HAL_UART_STATE_BUSY_RX)) + /* Check that a Tx process is not already ongoing */ + if(huart->gState == HAL_UART_STATE_READY) { if((pData == NULL ) || (Size == 0)) { return HAL_ERROR; } + /* In case of 9bits/No Parity transfer, pData buffer provided as input paramter + should be aligned on a u16 frontier, as data to be filled into TDR will be + handled through a u16 cast. */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + if((((uint32_t)pData)&1) != 0) + { + return HAL_ERROR; + } + } + /* Process Locked */ __HAL_LOCK(huart); @@ -822,15 +847,7 @@ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData huart->TxXferCount = Size; huart->ErrorCode = HAL_UART_ERROR_NONE; - /* Check if a receive process is ongoing or not */ - if(huart->State == HAL_UART_STATE_BUSY_RX) - { - huart->State = HAL_UART_STATE_BUSY_TX_RX; - } - else - { - huart->State = HAL_UART_STATE_BUSY_TX; - } + huart->gState = HAL_UART_STATE_BUSY_TX; /* Process Unlocked */ __HAL_UNLOCK(huart); @@ -851,17 +868,33 @@ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData * @param huart: UART handle. * @param pData: pointer to data buffer. * @param Size: amount of data to be received. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits) + * (as received data will be handled using u16 pointer cast). Depending on compilation chain, + * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { - if((huart->State == HAL_UART_STATE_READY) || (huart->State == HAL_UART_STATE_BUSY_TX)) + /* Check that a Rx process is not already ongoing */ + if(huart->RxState == HAL_UART_STATE_READY) { if((pData == NULL ) || (Size == 0)) { return HAL_ERROR; } + /* In case of 9bits/No Parity transfer, pData buffer provided as input paramter + should be aligned on a u16 frontier, as data to be received from RDR will be + handled through a u16 cast. */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + if((((uint32_t)pData)&1) != 0) + { + return HAL_ERROR; + } + } + /* Process Locked */ __HAL_LOCK(huart); @@ -873,15 +906,7 @@ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, UART_MASK_COMPUTATION(huart); huart->ErrorCode = HAL_UART_ERROR_NONE; - /* Check if a transmit process is ongoing or not */ - if(huart->State == HAL_UART_STATE_BUSY_TX) - { - huart->State = HAL_UART_STATE_BUSY_TX_RX; - } - else - { - huart->State = HAL_UART_STATE_BUSY_RX; - } + huart->RxState = HAL_UART_STATE_BUSY_RX; /* Enable the UART Parity Error Interrupt */ __HAL_UART_ENABLE_IT(huart, UART_IT_PE); @@ -903,24 +928,120 @@ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, } } +/** + * @brief Handle UART interrupt request. + * @param huart: UART handle. + * @retval None + */ +void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) +{ + /* UART parity error interrupt occurred -------------------------------------*/ + if((__HAL_UART_GET_IT(huart, UART_IT_PE) != RESET) && (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_PE) != RESET)) + { + __HAL_UART_CLEAR_IT(huart, UART_CLEAR_PEF); + + huart->ErrorCode |= HAL_UART_ERROR_PE; + } + + /* UART frame error interrupt occurred --------------------------------------*/ + if((__HAL_UART_GET_IT(huart, UART_IT_FE) != RESET) && (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_ERR) != RESET)) + { + __HAL_UART_CLEAR_IT(huart, UART_CLEAR_FEF); + + huart->ErrorCode |= HAL_UART_ERROR_FE; + } + + /* UART noise error interrupt occurred --------------------------------------*/ + if((__HAL_UART_GET_IT(huart, UART_IT_NE) != RESET) && (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_ERR) != RESET)) + { + __HAL_UART_CLEAR_IT(huart, UART_CLEAR_NEF); + + huart->ErrorCode |= HAL_UART_ERROR_NE; + } + + /* UART Over-Run interrupt occurred -----------------------------------------*/ + if((__HAL_UART_GET_IT(huart, UART_IT_ORE) != RESET) && (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_ERR) != RESET)) + { + __HAL_UART_CLEAR_IT(huart, UART_CLEAR_OREF); + + huart->ErrorCode |= HAL_UART_ERROR_ORE; + } + +#if !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC) + /* UART wakeup from Stop mode interrupt occurred -------------------------------------*/ + if((__HAL_UART_GET_IT(huart, UART_IT_WUF) != RESET) && (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_WUF) != RESET)) + { + __HAL_UART_CLEAR_IT(huart, UART_CLEAR_WUF); + /* Set the UART state ready to be able to start again the process */ + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + HAL_UARTEx_WakeupCallback(huart); + } +#endif /* !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC) */ + + /* UART in mode Receiver ---------------------------------------------------*/ + if((__HAL_UART_GET_IT(huart, UART_IT_RXNE) != RESET) && (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_RXNE) != RESET)) + { + UART_Receive_IT(huart); + } + + + /* UART in mode Transmitter ------------------------------------------------*/ + if((__HAL_UART_GET_IT(huart, UART_IT_TXE) != RESET) &&(__HAL_UART_GET_IT_SOURCE(huart, UART_IT_TXE) != RESET)) + { + UART_Transmit_IT(huart); + } + + /* UART in mode Transmitter (transmission end) -----------------------------*/ + if((__HAL_UART_GET_IT(huart, UART_IT_TC) != RESET) &&(__HAL_UART_GET_IT_SOURCE(huart, UART_IT_TC) != RESET)) + { + UART_EndTransmit_IT(huart); + } + + if(huart->ErrorCode != HAL_UART_ERROR_NONE) + { + /* Set the UART state ready to be able to start again the Tx/Rx process */ + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + + HAL_UART_ErrorCallback(huart); + } +} + /** * @brief Send an amount of data in DMA mode. * @param huart: UART handle. * @param pData: pointer to data buffer. * @param Size: amount of data to be sent. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits) + * (as sent data will be handled by DMA from halfword frontier). Depending on compilation chain, + * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { uint32_t *tmp; - if((huart->State == HAL_UART_STATE_READY) || (huart->State == HAL_UART_STATE_BUSY_RX)) + /* Check that a Tx process is not already ongoing */ + if(huart->gState == HAL_UART_STATE_READY) { if((pData == NULL ) || (Size == 0)) { return HAL_ERROR; } + /* In case of 9bits/No Parity transfer, pData buffer provided as input paramter + should be aligned on a u16 frontier, as data copy into TDR will be + handled by DMA from a u16 frontier. */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + if((((uint32_t)pData)&1) != 0) + { + return HAL_ERROR; + } + } + /* Process Locked */ __HAL_LOCK(huart); @@ -929,15 +1050,7 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pDat huart->TxXferCount = Size; huart->ErrorCode = HAL_UART_ERROR_NONE; - /* Check if a receive process is ongoing or not */ - if(huart->State == HAL_UART_STATE_BUSY_RX) - { - huart->State = HAL_UART_STATE_BUSY_TX_RX; - } - else - { - huart->State = HAL_UART_STATE_BUSY_TX; - } + huart->gState = HAL_UART_STATE_BUSY_TX; /* Set the UART DMA transfer complete callback */ huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt; @@ -975,21 +1088,35 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pDat * @param huart: UART handle. * @param pData: pointer to data buffer. * @param Size: amount of data to be received. - * @note When the UART parity is enabled (PCE = 1), the received data contain - * the parity bit (MSB position). + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits) + * (as received data will be handled by DMA from halfword frontier). Depending on compilation chain, + * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { uint32_t *tmp; - if((huart->State == HAL_UART_STATE_READY) || (huart->State == HAL_UART_STATE_BUSY_TX)) + /* Check that a Rx process is not already ongoing */ + if(huart->RxState == HAL_UART_STATE_READY) { if((pData == NULL ) || (Size == 0)) { return HAL_ERROR; } + /* In case of 9bits/No Parity transfer, pData buffer provided as input paramter + should be aligned on a u16 frontier, as data copy from RDR will be + handled by DMA from a u16 frontier. */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + if((((uint32_t)pData)&1) != 0) + { + return HAL_ERROR; + } + } + /* Process Locked */ __HAL_LOCK(huart); @@ -997,15 +1124,7 @@ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData huart->RxXferSize = Size; huart->ErrorCode = HAL_UART_ERROR_NONE; - /* Check if a transmit process is ongoing or not */ - if(huart->State == HAL_UART_STATE_BUSY_TX) - { - huart->State = HAL_UART_STATE_BUSY_TX_RX; - } - else - { - huart->State = HAL_UART_STATE_BUSY_RX; - } + huart->RxState = HAL_UART_STATE_BUSY_RX; /* Set the UART DMA transfer complete callback */ huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt; @@ -1045,23 +1164,16 @@ HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart) /* Process Locked */ __HAL_LOCK(huart); - if(huart->State == HAL_UART_STATE_BUSY_TX) + if(huart->gState == HAL_UART_STATE_BUSY_TX) { /* Disable the UART DMA Tx request */ huart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAT); } - else if(huart->State == HAL_UART_STATE_BUSY_RX) + if(huart->RxState == HAL_UART_STATE_BUSY_RX) { /* Disable the UART DMA Rx request */ huart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAR); } - else if(huart->State == HAL_UART_STATE_BUSY_TX_RX) - { - /* Disable the UART DMA Tx request */ - huart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAT); - /* Disable the UART DMA Rx request */ - huart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAR); - } /* Process Unlocked */ __HAL_UNLOCK(huart); @@ -1079,12 +1191,12 @@ HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart) /* Process Locked */ __HAL_LOCK(huart); - if(huart->State == HAL_UART_STATE_BUSY_TX) + if(huart->gState == HAL_UART_STATE_BUSY_TX) { /* Enable the UART DMA Tx request */ huart->Instance->CR3 |= USART_CR3_DMAT; } - else if(huart->State == HAL_UART_STATE_BUSY_RX) + if(huart->RxState == HAL_UART_STATE_BUSY_RX) { /* Clear the Overrun flag before resumming the Rx transfer*/ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); @@ -1092,17 +1204,6 @@ HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart) /* Enable the UART DMA Rx request */ huart->Instance->CR3 |= USART_CR3_DMAR; } - else if(huart->State == HAL_UART_STATE_BUSY_TX_RX) - { - /* Clear the Overrun flag before resumming the Rx transfer*/ - __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); - - /* Enable the UART DMA Rx request before the DMA Tx request */ - huart->Instance->CR3 |= USART_CR3_DMAR; - - /* Enable the UART DMA Tx request */ - huart->Instance->CR3 |= USART_CR3_DMAT; - } /* Process Unlocked */ __HAL_UNLOCK(huart); @@ -1140,7 +1241,8 @@ HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart) HAL_DMA_Abort(huart->hdmarx); } - huart->State = HAL_UART_STATE_READY; + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; return HAL_OK; } @@ -1253,12 +1355,12 @@ HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart) /* Process Locked */ __HAL_LOCK(huart); - huart->State = HAL_UART_STATE_BUSY; + huart->gState = HAL_UART_STATE_BUSY; /* Enable USART mute mode by setting the MME bit in the CR1 register */ huart->Instance->CR1 |= USART_CR1_MME; - huart->State = HAL_UART_STATE_READY; + huart->gState = HAL_UART_STATE_READY; return (UART_CheckIdleState(huart)); } @@ -1274,12 +1376,12 @@ HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart) /* Process Locked */ __HAL_LOCK(huart); - huart->State = HAL_UART_STATE_BUSY; + huart->gState = HAL_UART_STATE_BUSY; /* Disable USART mute mode by clearing the MME bit in the CR1 register */ huart->Instance->CR1 &= ~(USART_CR1_MME); - huart->State = HAL_UART_STATE_READY; + huart->gState = HAL_UART_STATE_READY; return (UART_CheckIdleState(huart)); } @@ -1304,14 +1406,14 @@ HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart) { /* Process Locked */ __HAL_LOCK(huart); - huart->State = HAL_UART_STATE_BUSY; + huart->gState = HAL_UART_STATE_BUSY; /* Clear TE and RE bits */ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE)); /* Enable the USART's transmit interface by setting the TE bit in the USART CR1 register */ SET_BIT(huart->Instance->CR1, USART_CR1_TE); - huart->State = HAL_UART_STATE_READY; + huart->gState = HAL_UART_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(huart); @@ -1328,14 +1430,14 @@ HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart) { /* Process Locked */ __HAL_LOCK(huart); - huart->State = HAL_UART_STATE_BUSY; + huart->gState = HAL_UART_STATE_BUSY; /* Clear TE and RE bits */ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE)); /* Enable the USART's receive interface by setting the RE bit in the USART CR1 register */ SET_BIT(huart->Instance->CR1, USART_CR1_RE); - huart->State = HAL_UART_STATE_READY; + huart->gState = HAL_UART_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(huart); @@ -1363,22 +1465,26 @@ HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart) */ /** - * @brief Return the UART handle state. - * @param huart : pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART. + * @brief Return the UART handle state. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART. * @retval HAL state */ HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart) { - return huart->State; + uint32_t temp1= 0x00, temp2 = 0x00; + temp1 = huart->gState; + temp2 = huart->RxState; + + return (HAL_UART_StateTypeDef)(temp1 | temp2); } /** -* @brief Return the UART handle error code. -* @param huart : pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART. -* @retval UART Error Code -*/ + * @brief Return the UART handle error code. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART. + * @retval UART Error Code + */ uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart) { return huart->ErrorCode; @@ -1588,7 +1694,7 @@ HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) Bits are defined for some specific devices, and are available only for UART instances supporting WakeUp from Stop Mode feature. */ #if !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC) - if (IS_UART_WAKEUP_INSTANCE(huart->Instance)) + if (IS_UART_WAKEUP_FROMSTOP_INSTANCE(huart->Instance)) { /* Check if the Transmitter is enabled */ if((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) @@ -1615,7 +1721,8 @@ HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) #endif /* !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC) */ /* Initialize the UART State */ - huart->State= HAL_UART_STATE_READY; + huart->gState= HAL_UART_STATE_READY; + huart->RxState= HAL_UART_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(huart); @@ -1652,7 +1759,8 @@ HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_ __HAL_UART_DISABLE_IT(huart, UART_IT_PE); __HAL_UART_DISABLE_IT(huart, UART_IT_ERR); - huart->State = HAL_UART_STATE_READY; + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(huart); @@ -1677,7 +1785,8 @@ HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_ __HAL_UART_DISABLE_IT(huart, UART_IT_PE); __HAL_UART_DISABLE_IT(huart, UART_IT_ERR); - huart->State = HAL_UART_STATE_READY; + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(huart); @@ -1749,15 +1858,8 @@ static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) in the UART CR3 register */ huart->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAR); - /* Check if a transmit Process is ongoing or not */ - if(huart->State == HAL_UART_STATE_BUSY_TX_RX) - { - huart->State = HAL_UART_STATE_BUSY_TX; - } - else - { - huart->State = HAL_UART_STATE_READY; - } + /* At end of Rx process, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; } HAL_UART_RxCpltCallback(huart); @@ -1785,7 +1887,8 @@ static void UART_DMAError(DMA_HandleTypeDef *hdma) UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; huart->RxXferCount = 0; huart->TxXferCount = 0; - huart->State= HAL_UART_STATE_READY; + huart->gState= HAL_UART_STATE_READY; + huart->RxState= HAL_UART_STATE_READY; huart->ErrorCode |= HAL_UART_ERROR_DMA; HAL_UART_ErrorCallback(huart); } @@ -1801,9 +1904,9 @@ HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart) { uint16_t* tmp; - if ((huart->State == HAL_UART_STATE_BUSY_TX) || (huart->State == HAL_UART_STATE_BUSY_TX_RX)) + /* Check that a Tx process is ongoing */ + if (huart->gState == HAL_UART_STATE_BUSY_TX) { - if(huart->TxXferCount == 0) { /* Disable the UART Transmit Data Register Empty Interrupt */ @@ -1850,15 +1953,8 @@ HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart) /* Disable the UART Transmit Complete Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_TC); - /* Check if a receive process is ongoing or not */ - if(huart->State == HAL_UART_STATE_BUSY_TX_RX) - { - huart->State = HAL_UART_STATE_BUSY_RX; - } - else - { - huart->State = HAL_UART_STATE_READY; - } + /* Tx process is ended, restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; HAL_UART_TxCpltCallback(huart); @@ -1878,9 +1974,9 @@ HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart) uint16_t* tmp; uint16_t uhMask = huart->Mask; - if((huart->State == HAL_UART_STATE_BUSY_RX) || (huart->State == HAL_UART_STATE_BUSY_TX_RX)) + /* Check that a Rx process is ongoing */ + if(huart->RxState == HAL_UART_STATE_BUSY_RX) { - if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) { tmp = (uint16_t*) huart->pRxBuffPtr ; @@ -1896,21 +1992,14 @@ HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart) { __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE); - /* Check if a transmit Process is ongoing or not */ - if(huart->State == HAL_UART_STATE_BUSY_TX_RX) - { - huart->State = HAL_UART_STATE_BUSY_TX; - } - else - { - /* Disable the UART Parity Error Interrupt */ - __HAL_UART_DISABLE_IT(huart, UART_IT_PE); + /* Disable the UART Parity Error Interrupt */ + __HAL_UART_DISABLE_IT(huart, UART_IT_PE); - /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ - __HAL_UART_DISABLE_IT(huart, UART_IT_ERR); + /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + __HAL_UART_DISABLE_IT(huart, UART_IT_ERR); - huart->State = HAL_UART_STATE_READY; - } + /* Rx process is completed, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; HAL_UART_RxCpltCallback(huart); @@ -1921,6 +2010,9 @@ HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart) } else { + /* Clear RXNE interrupt flag */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + return HAL_BUSY; } } diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_uart.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_uart.h index d98b13b461..094107310c 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_uart.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_uart.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f0xx_hal_uart.h * @author MCD Application Team - * @version V1.3.1 - * @date 29-January-2016 + * @version V1.4.0 + * @date 27-May-2016 * @brief Header file of UART HAL module. ****************************************************************************** * @attention @@ -144,17 +144,62 @@ typedef struct /** * @brief HAL UART State structures definition + * @note HAL UART State value is a combination of 2 different substates: gState and RxState. + * - gState contains UART state information related to global Handle management + * and also information related to Tx operations. + * gState value coding follow below described bitmap : + * b7-b6 Error information + * 00 : No Error + * 01 : (Not Used) + * 10 : Timeout + * 11 : Error + * b5 IP initilisation status + * 0 : Reset (IP not initialized) + * 1 : Init done (IP not initialized. HAL UART Init function already called) + * b4-b3 (not used) + * xx : Should be set to 00 + * b2 Intrinsic process state + * 0 : Ready + * 1 : Busy (IP busy with some configuration or internal operations) + * b1 (not used) + * x : Should be set to 0 + * b0 Tx state + * 0 : Ready (no Tx operation ongoing) + * 1 : Busy (Tx operation ongoing) + * - RxState contains information related to Rx operations. + * RxState value coding follow below described bitmap : + * b7-b6 (not used) + * xx : Should be set to 00 + * b5 IP initilisation status + * 0 : Reset (IP not initialized) + * 1 : Init done (IP not initialized) + * b4-b2 (not used) + * xxx : Should be set to 000 + * b1 Rx state + * 0 : Ready (no Rx operation ongoing) + * 1 : Busy (Rx operation ongoing) + * b0 (not used) + * x : Should be set to 0. */ typedef enum { - HAL_UART_STATE_RESET = 0x00, /*!< Peripheral is not initialized */ - HAL_UART_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */ - HAL_UART_STATE_BUSY = 0x02, /*!< an internal process is ongoing */ - HAL_UART_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */ - HAL_UART_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */ - HAL_UART_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */ - HAL_UART_STATE_TIMEOUT = 0x03, /*!< Timeout state */ - HAL_UART_STATE_ERROR = 0x04 /*!< Error */ + HAL_UART_STATE_RESET = 0x00U, /*!< Peripheral is not initialized + Value is allowed for gState and RxState */ + HAL_UART_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use + Value is allowed for gState and RxState */ + HAL_UART_STATE_BUSY = 0x24U, /*!< an internal process is ongoing + Value is allowed for gState only */ + HAL_UART_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing + Value is allowed for gState only */ + HAL_UART_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing + Value is allowed for RxState only */ + HAL_UART_STATE_BUSY_TX_RX = 0x23U, /*!< Data Transmission and Reception process is ongoing + Not to be used for neither gState nor RxState. + Value is result of combination (Or) between gState and RxState values */ + HAL_UART_STATE_TIMEOUT = 0xA0U, /*!< Timeout state + Value is allowed for gState only */ + HAL_UART_STATE_ERROR = 0xE0U /*!< Error + Value is allowed for gState only */ }HAL_UART_StateTypeDef; /** @@ -200,7 +245,12 @@ typedef struct HAL_LockTypeDef Lock; /*!< Locking object */ - __IO HAL_UART_StateTypeDef State; /*!< UART communication state */ + __IO HAL_UART_StateTypeDef gState; /*!< UART state information related to global Handle management + and also related to Tx operations. + This parameter can be a value of @ref HAL_UART_StateTypeDef */ + + __IO HAL_UART_StateTypeDef RxState; /*!< UART state information related to Rx operations. + This parameter can be a value of @ref HAL_UART_StateTypeDef */ __IO uint32_t ErrorCode; /*!< UART Error code */ @@ -231,9 +281,15 @@ typedef struct /** @defgroup UART_Stop_Bits UART Number of Stop Bits * @{ */ -#define UART_STOPBITS_1 ((uint32_t)0x0000) -#define UART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1) -#define UART_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1)) +#ifdef USART_SMARTCARD_SUPPORT +#define UART_STOPBITS_0_5 USART_CR2_STOP_0 /*!< UART frame with 0.5 stop bit */ +#define UART_STOPBITS_1 ((uint32_t)0x00000000) /*!< UART frame with 1 stop bit */ +#define UART_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1)) /*!< UART frame with 1.5 stop bits */ +#define UART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1) /*!< UART frame with 2 stop bits */ +#else +#define UART_STOPBITS_1 ((uint32_t)0x00000000) /*!< UART frame with 1 stop bit */ +#define UART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1) /*!< UART frame with 2 stop bits */ +#endif /** * @} */ @@ -527,11 +583,14 @@ typedef struct * @{ */ -/** @brief Reset UART handle state. +/** @brief Reset UART handle states. * @param __HANDLE__: UART handle. * @retval None */ -#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_UART_STATE_RESET) +#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->gState = HAL_UART_STATE_RESET; \ + (__HANDLE__)->RxState = HAL_UART_STATE_RESET; \ + } while(0) /** @brief Clear the specified UART pending flag. * @param __HANDLE__: specifies the UART Handle. @@ -854,14 +913,14 @@ typedef struct * @param __BAUD__: Baud rate set by the user. * @retval Division result */ -#define UART_DIV_SAMPLING8(__PCLK__, __BAUD__) (((__PCLK__)*2)/((__BAUD__))) +#define UART_DIV_SAMPLING8(__PCLK__, __BAUD__) ((((__PCLK__)*2) + ((__BAUD__)/2)) / (__BAUD__)) /** @brief BRR division operation to set BRR register in 16-bit oversampling mode. * @param __PCLK__: UART clock. * @param __BAUD__: Baud rate set by the user. * @retval Division result */ -#define UART_DIV_SAMPLING16(__PCLK__, __BAUD__) (((__PCLK__))/((__BAUD__))) +#define UART_DIV_SAMPLING16(__PCLK__, __BAUD__) (((__PCLK__) + ((__BAUD__)/2)) / (__BAUD__)) /** @brief Check UART Baud rate * @param __BAUDRATE__: Baudrate specified by the user. @@ -886,11 +945,17 @@ typedef struct /** * @brief Ensure that UART frame number of stop bits is valid. * @param __STOPBITS__: UART frame number of stop bits. - * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid) UART_STOPBITS_1_5 + * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid) */ -#define IS_UART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == UART_STOPBITS_1) || \ - ((__STOPBITS__) == UART_STOPBITS_2) || \ - ((__STOPBITS__) == UART_STOPBITS_1_5)) +#ifdef USART_SMARTCARD_SUPPORT +#define IS_UART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == UART_STOPBITS_0_5) || \ + ((__STOPBITS__) == UART_STOPBITS_1) || \ + ((__STOPBITS__) == UART_STOPBITS_1_5) || \ + ((__STOPBITS__) == UART_STOPBITS_2)) +#else +#define IS_UART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == UART_STOPBITS_1) || \ + ((__STOPBITS__) == UART_STOPBITS_2)) +#endif /** * @brief Ensure that UART frame parity is valid. diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_uart_ex.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_uart_ex.c index 5da4de8e46..6f3c42331f 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_uart_ex.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_uart_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f0xx_hal_uart_ex.c * @author MCD Application Team - * @version V1.3.1 - * @date 29-January-2016 + * @version V1.4.0 + * @date 27-May-2016 * @brief Extended UART HAL module driver. * This file provides firmware functions to manage the following extended * functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). @@ -103,39 +103,7 @@ static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTy (++) Baud Rate (++) Word Length (Fixed to 8-bits only for LIN mode) (++) Stop Bit - (++) Parity: If the parity is enabled, then the MSB bit of the data written - in the data register is transmitted but is changed by the parity bit. - According to device capability (support or not of 7-bit word length), - frame length is either defined by the M bit (8-bits or 9-bits) - or by the M1 and M0 bits (7-bit, 8-bit or 9-bit). - Possible UART frame formats are as listed in the following table: - - (+++) Table 1. UART frame format. - (+++) +-----------------------------------------------------------------------+ - (+++) | M bit | PCE bit | UART frame | - (+++) |-------------------|-----------|---------------------------------------| - (+++) | 0 | 0 | | SB | 8-bit data | STB | | - (+++) |-------------------|-----------|---------------------------------------| - (+++) | 0 | 1 | | SB | 7-bit data | PB | STB | | - (+++) |-------------------|-----------|---------------------------------------| - (+++) | 1 | 0 | | SB | 9-bit data | STB | | - (+++) |-------------------|-----------|---------------------------------------| - (+++) | 1 | 1 | | SB | 8-bit data | PB | STB | | - (+++) +-----------------------------------------------------------------------+ - (+++) | M1 bit | M0 bit | PCE bit | UART frame | - (+++) |---------|---------|-----------|---------------------------------------| - (+++) | 0 | 0 | 0 | | SB | 8 bit data | STB | | - (+++) |---------|---------|-----------|---------------------------------------| - (+++) | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | | - (+++) |---------|---------|-----------|---------------------------------------| - (+++) | 0 | 1 | 0 | | SB | 9 bit data | STB | | - (+++) |---------|---------|-----------|---------------------------------------| - (+++) | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | | - (+++) |---------|---------|-----------|---------------------------------------| - (+++) | 1 | 0 | 0 | | SB | 7 bit data | STB | | - (+++) |---------|---------|-----------|---------------------------------------| - (+++) | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | | - (+++) +-----------------------------------------------------------------------+ + (++) Parity (++) Hardware flow control (++) Receiver/transmitter modes (++) Over Sampling Method @@ -157,6 +125,43 @@ static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTy * @{ */ +/* + Additional Table: If the parity is enabled, then the MSB bit of the data written + in the data register is transmitted but is changed by the parity bit. + According to device capability (support or not of 7-bit word length), + frame length is either defined by the M bit (8-bits or 9-bits) + or by the M1 and M0 bits (7-bit, 8-bit or 9-bit). + Possible UART frame formats are as listed in the following table: + + Table 1. UART frame format. + +-----------------------------------------------------------------------+ + | M bit | PCE bit | UART frame | + |-------------------|-----------|---------------------------------------| + | 0 | 0 | | SB | 8-bit data | STB | | + |-------------------|-----------|---------------------------------------| + | 0 | 1 | | SB | 7-bit data | PB | STB | | + |-------------------|-----------|---------------------------------------| + | 1 | 0 | | SB | 9-bit data | STB | | + |-------------------|-----------|---------------------------------------| + | 1 | 1 | | SB | 8-bit data | PB | STB | | + +-----------------------------------------------------------------------+ + | M1 bit | M0 bit | PCE bit | UART frame | + |---------|---------|-----------|---------------------------------------| + | 0 | 0 | 0 | | SB | 8 bit data | STB | | + |---------|---------|-----------|---------------------------------------| + | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | | + |---------|---------|-----------|---------------------------------------| + | 0 | 1 | 0 | | SB | 9 bit data | STB | | + |---------|---------|-----------|---------------------------------------| + | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | | + |---------|---------|-----------|---------------------------------------| + | 1 | 0 | 0 | | SB | 7 bit data | STB | | + |---------|---------|-----------|---------------------------------------| + | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | | + +-----------------------------------------------------------------------+ + +*/ + /** * @brief Initialize the RS485 Driver enable feature according to the specified * parameters in the UART_InitTypeDef and creates the associated handle. @@ -197,7 +202,7 @@ HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, /* Check the Driver Enable deassertion time */ assert_param(IS_UART_DEASSERTIONTIME(DeassertionTime)); - if(huart->State == HAL_UART_STATE_RESET) + if(huart->gState == HAL_UART_STATE_RESET) { /* Allocate lock resource and initialize it */ huart->Lock = HAL_UNLOCKED; @@ -206,7 +211,7 @@ HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, HAL_UART_MspInit(huart); } - huart->State = HAL_UART_STATE_BUSY; + huart->gState = HAL_UART_STATE_BUSY; /* Disable the Peripheral */ __HAL_UART_DISABLE(huart); @@ -236,7 +241,7 @@ HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, /* Enable the Peripheral */ __HAL_UART_ENABLE(huart); - /* TEACK and/or REACK to check before moving huart->State to Ready */ + /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ return (UART_CheckIdleState(huart)); } @@ -275,7 +280,7 @@ HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLe return HAL_ERROR; } - if(huart->State == HAL_UART_STATE_RESET) + if(huart->gState == HAL_UART_STATE_RESET) { /* Allocate lock resource and initialize it */ huart->Lock = HAL_UNLOCKED; @@ -284,7 +289,7 @@ HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLe HAL_UART_MspInit(huart); } - huart->State = HAL_UART_STATE_BUSY; + huart->gState = HAL_UART_STATE_BUSY; /* Disable the Peripheral */ __HAL_UART_DISABLE(huart); @@ -315,7 +320,7 @@ HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLe /* Enable the Peripheral */ __HAL_UART_ENABLE(huart); - /* TEACK and/or REACK to check before moving huart->State to Ready */ + /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ return (UART_CheckIdleState(huart)); } #endif /* !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC) */ @@ -332,11 +337,7 @@ HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLe ##### IO operation function ##### =============================================================================== [..] - This subsection provides functions allowing to manage the UART interrupts - and to handle Wake up interrupt call-back. - - (#) Non-Blocking mode API with Interrupt is : - (++) HAL_UART_IRQHandler() + This subsection provides function to handle Wake up interrupt call-back. (#) Callback provided in No_Blocking mode: (++) HAL_UARTEx_WakeupCallback() @@ -345,94 +346,6 @@ HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLe * @{ */ - -/** - * @brief Handle UART interrupt request. - * @param huart: UART handle. - * @retval None - */ -void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) -{ - /* UART parity error interrupt occurred -------------------------------------*/ - if((__HAL_UART_GET_IT(huart, UART_IT_PE) != RESET) && (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_PE) != RESET)) - { - __HAL_UART_CLEAR_IT(huart, UART_CLEAR_PEF); - - huart->ErrorCode |= HAL_UART_ERROR_PE; - /* Set the UART state ready to be able to start again the process */ - huart->State = HAL_UART_STATE_READY; - } - - /* UART frame error interrupt occurred --------------------------------------*/ - if((__HAL_UART_GET_IT(huart, UART_IT_FE) != RESET) && (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_ERR) != RESET)) - { - __HAL_UART_CLEAR_IT(huart, UART_CLEAR_FEF); - - huart->ErrorCode |= HAL_UART_ERROR_FE; - /* Set the UART state ready to be able to start again the process */ - huart->State = HAL_UART_STATE_READY; - } - - /* UART noise error interrupt occurred --------------------------------------*/ - if((__HAL_UART_GET_IT(huart, UART_IT_NE) != RESET) && (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_ERR) != RESET)) - { - __HAL_UART_CLEAR_IT(huart, UART_CLEAR_NEF); - - huart->ErrorCode |= HAL_UART_ERROR_NE; - /* Set the UART state ready to be able to start again the process */ - huart->State = HAL_UART_STATE_READY; - } - - /* UART Over-Run interrupt occurred -----------------------------------------*/ - if((__HAL_UART_GET_IT(huart, UART_IT_ORE) != RESET) && (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_ERR) != RESET)) - { - __HAL_UART_CLEAR_IT(huart, UART_CLEAR_OREF); - - huart->ErrorCode |= HAL_UART_ERROR_ORE; - /* Set the UART state ready to be able to start again the process */ - huart->State = HAL_UART_STATE_READY; - } - - /* Call UART Error Call back function if need be --------------------------*/ - if(huart->ErrorCode != HAL_UART_ERROR_NONE) - { - HAL_UART_ErrorCallback(huart); - } - -#if !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC) - /* UART wakeup from Stop mode interrupt occurred -------------------------------------*/ - if((__HAL_UART_GET_IT(huart, UART_IT_WUF) != RESET) && (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_WUF) != RESET)) - { - __HAL_UART_CLEAR_IT(huart, UART_CLEAR_WUF); - /* Set the UART state ready to be able to start again the process */ - huart->State = HAL_UART_STATE_READY; - HAL_UARTEx_WakeupCallback(huart); - } -#endif /* !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC) */ - - /* UART in mode Receiver ---------------------------------------------------*/ - if((__HAL_UART_GET_IT(huart, UART_IT_RXNE) != RESET) && (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_RXNE) != RESET)) - { - UART_Receive_IT(huart); - /* Clear RXNE interrupt flag */ - __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); - } - - - /* UART in mode Transmitter ------------------------------------------------*/ - if((__HAL_UART_GET_IT(huart, UART_IT_TXE) != RESET) &&(__HAL_UART_GET_IT_SOURCE(huart, UART_IT_TXE) != RESET)) - { - UART_Transmit_IT(huart); - } - - /* UART in mode Transmitter (transmission end) -----------------------------*/ - if((__HAL_UART_GET_IT(huart, UART_IT_TC) != RESET) &&(__HAL_UART_GET_IT_SOURCE(huart, UART_IT_TC) != RESET)) - { - UART_EndTransmit_IT(huart); - } - -} - #if !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC) /** * @brief UART wakeup from Stop mode callback @@ -492,14 +405,14 @@ HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huar HAL_StatusTypeDef status = HAL_OK; /* check the wake-up from stop mode UART instance */ - assert_param(IS_UART_WAKEUP_INSTANCE(huart->Instance)); + assert_param(IS_UART_WAKEUP_FROMSTOP_INSTANCE(huart->Instance)); /* check the wake-up selection parameter */ assert_param(IS_UART_WAKEUP_SELECTION(WakeUpSelection.WakeUpEvent)); /* Process Locked */ __HAL_LOCK(huart); - huart->State = HAL_UART_STATE_BUSY; + huart->gState = HAL_UART_STATE_BUSY; /* Disable the Peripheral */ __HAL_UART_DISABLE(huart); @@ -523,7 +436,7 @@ HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huar else { /* Initialize the UART State */ - huart->State = HAL_UART_STATE_READY; + huart->gState = HAL_UART_STATE_READY; } /* Process Unlocked */ @@ -542,17 +455,17 @@ HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huar HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart) { /* Check parameter */ - assert_param(IS_UART_WAKEUP_INSTANCE(huart->Instance)); + assert_param(IS_UART_WAKEUP_FROMSTOP_INSTANCE(huart->Instance)); /* Process Locked */ __HAL_LOCK(huart); - huart->State = HAL_UART_STATE_BUSY; + huart->gState = HAL_UART_STATE_BUSY; /* Set UESM bit */ SET_BIT(huart->Instance->CR1, USART_CR1_UESM); - huart->State = HAL_UART_STATE_READY; + huart->gState = HAL_UART_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(huart); @@ -568,17 +481,17 @@ HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart) HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart) { /* Check parameter */ - assert_param(IS_UART_WAKEUP_INSTANCE(huart->Instance)); + assert_param(IS_UART_WAKEUP_FROMSTOP_INSTANCE(huart->Instance)); /* Process Locked */ __HAL_LOCK(huart); - huart->State = HAL_UART_STATE_BUSY; + huart->gState = HAL_UART_STATE_BUSY; /* Clear UESM bit */ CLEAR_BIT(huart->Instance->CR1, USART_CR1_UESM); - huart->State = HAL_UART_STATE_READY; + huart->gState = HAL_UART_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(huart); @@ -611,7 +524,7 @@ HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *hua /* Check the address length parameter */ assert_param(IS_UART_ADDRESSLENGTH_DETECT(AddressLength)); - huart->State = HAL_UART_STATE_BUSY; + huart->gState = HAL_UART_STATE_BUSY; /* Disable the Peripheral */ __HAL_UART_DISABLE(huart); @@ -622,7 +535,7 @@ HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *hua /* Enable the Peripheral */ __HAL_UART_ENABLE(huart); - /* TEACK and/or REACK to check before moving huart->State to Ready */ + /* TEACK and/or REACK to check before moving huart->gState to Ready */ return (UART_CheckIdleState(huart)); } @@ -641,12 +554,12 @@ HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart) /* Process Locked */ __HAL_LOCK(huart); - huart->State = HAL_UART_STATE_BUSY; + huart->gState = HAL_UART_STATE_BUSY; /* Send break characters */ huart->Instance->RQR |= UART_SENDBREAK_REQUEST; - huart->State = HAL_UART_STATE_READY; + huart->gState = HAL_UART_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(huart); @@ -677,7 +590,7 @@ HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart) static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection) { /* Check parmeters */ - assert_param(IS_UART_WAKEUP_INSTANCE(huart->Instance)); + assert_param(IS_UART_WAKEUP_FROMSTOP_INSTANCE(huart->Instance)); assert_param(IS_UART_ADDRESSLENGTH_DETECT(WakeUpSelection.AddressLength)); /* Set the USART address length */ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_uart_ex.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_uart_ex.h index 7ca548b546..04f6e479a5 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_uart_ex.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_uart_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f0xx_hal_uart_ex.h * @author MCD Application Team - * @version V1.3.1 - * @date 29-January-2016 + * @version V1.4.0 + * @date 27-May-2016 * @brief Header file of UART HAL Extension module. ****************************************************************************** * @attention @@ -800,7 +800,7 @@ typedef struct * @{ */ /* Initialization and de-initialization functions ****************************/ -HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t UART_DEPolarity, uint32_t UART_DEAssertionTime, uint32_t UART_DEDeassertionTime); +HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime); #if !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC) HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength); #endif /* !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC) */ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_usart.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_usart.c index 277a07f105..3166f94c52 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_usart.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_usart.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f0xx_hal_usart.c * @author MCD Application Team - * @version V1.3.1 - * @date 29-January-2016 + * @version V1.4.0 + * @date 27-May-2016 * @brief USART HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Universal Synchronous Asynchronous Receiver Transmitter @@ -212,38 +212,7 @@ static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart); (++) Baud Rate (++) Word Length (++) Stop Bit - (++) Parity: If the parity is enabled, then the MSB bit of the data written - in the data register is transmitted but is changed by the parity bit. - According to device capability (support or not of 7-bit word length), - frame length is either defined by the M bit (8-bits or 9-bits) - or by the M1 and M0 bits (7-bit, 8-bit or 9-bit). - Possible USART frame formats are as listed in the following table: - (+++) Table 1. USART frame format. - (+++) +-----------------------------------------------------------------------+ - (+++) | M bit | PCE bit | USART frame | - (+++) |-------------------|-----------|---------------------------------------| - (+++) | 0 | 0 | | SB | 8-bit data | STB | | - (+++) |-------------------|-----------|---------------------------------------| - (+++) | 0 | 1 | | SB | 7-bit data | PB | STB | | - (+++) |-------------------|-----------|---------------------------------------| - (+++) | 1 | 0 | | SB | 9-bit data | STB | | - (+++) |-------------------|-----------|---------------------------------------| - (+++) | 1 | 1 | | SB | 8-bit data | PB | STB | | - (+++) +-----------------------------------------------------------------------+ - (+++) | M1 bit | M0 bit | PCE bit | USART frame | - (+++) |---------|---------|-----------|---------------------------------------| - (+++) | 0 | 0 | 0 | | SB | 8 bit data | STB | | - (+++) |---------|---------|-----------|---------------------------------------| - (+++) | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | | - (+++) |---------|---------|-----------|---------------------------------------| - (+++) | 0 | 1 | 0 | | SB | 9 bit data | STB | | - (+++) |---------|---------|-----------|---------------------------------------| - (+++) | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | | - (+++) |---------|---------|-----------|---------------------------------------| - (+++) | 1 | 0 | 0 | | SB | 7 bit data | STB | | - (+++) |---------|---------|-----------|---------------------------------------| - (+++) | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | | - (+++) +-----------------------------------------------------------------------+ + (++) Parity (++) USART polarity (++) USART phase (++) USART LastBit @@ -257,6 +226,43 @@ static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart); * @{ */ +/* + Additional Table: If the parity is enabled, then the MSB bit of the data written + in the data register is transmitted but is changed by the parity bit. + According to device capability (support or not of 7-bit word length), + frame length is either defined by the M bit (8-bits or 9-bits) + or by the M1 and M0 bits (7-bit, 8-bit or 9-bit). + Possible USART frame formats are as listed in the following table: + + Table 1. USART frame format. + +-----------------------------------------------------------------------+ + | M bit | PCE bit | USART frame | + |-------------------|-----------|---------------------------------------| + | 0 | 0 | | SB | 8-bit data | STB | | + |-------------------|-----------|---------------------------------------| + | 0 | 1 | | SB | 7-bit data | PB | STB | | + |-------------------|-----------|---------------------------------------| + | 1 | 0 | | SB | 9-bit data | STB | | + |-------------------|-----------|---------------------------------------| + | 1 | 1 | | SB | 8-bit data | PB | STB | | + +-----------------------------------------------------------------------+ + | M1 bit | M0 bit | PCE bit | USART frame | + |---------|---------|-----------|---------------------------------------| + | 0 | 0 | 0 | | SB | 8 bit data | STB | | + |---------|---------|-----------|---------------------------------------| + | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | | + |---------|---------|-----------|---------------------------------------| + | 0 | 1 | 0 | | SB | 9 bit data | STB | | + |---------|---------|-----------|---------------------------------------| + | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | | + |---------|---------|-----------|---------------------------------------| + | 1 | 0 | 0 | | SB | 7 bit data | STB | | + |---------|---------|-----------|---------------------------------------| + | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | | + +-----------------------------------------------------------------------+ + +*/ + /** * @brief Initializes the USART mode according to the specified * parameters in the USART_InitTypeDef and initialize the associated handle. @@ -452,6 +458,10 @@ HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart) * @param pTxData: Pointer to data buffer. * @param Size: Amount of data to be sent. * @param Timeout: Timeout duration. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits) + * (as sent data will be handled using u16 pointer cast). Depending on compilation chain, + * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pTxData. * @retval HAL status */ HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout) @@ -465,6 +475,17 @@ HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxDa return HAL_ERROR; } + /* In case of 9bits/No Parity transfer, pTxData buffer provided as input paramter + should be aligned on a u16 frontier, as data to be filled into TDR will be + handled through a u16 cast. */ + if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + { + if((((uint32_t)pTxData)&1) != 0) + { + return HAL_ERROR; + } + } + /* Process Locked */ __HAL_LOCK(husart); @@ -519,6 +540,10 @@ HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxDa * @param pRxData: Pointer to data buffer. * @param Size: Amount of data to be received. * @param Timeout: Timeout duration. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits) + * (as received data will be handled using u16 pointer cast). Depending on compilation chain, + * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pRxData. * @retval HAL status */ HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout) @@ -532,6 +557,18 @@ HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxDat { return HAL_ERROR; } + + /* In case of 9bits/No Parity transfer, pRxData buffer provided as input paramter + should be aligned on a u16 frontier, as data to be received from RDR will be + handled through a u16 cast. */ + if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + { + if((((uint32_t)pRxData)&1) != 0) + { + return HAL_ERROR; + } + } + /* Process Locked */ __HAL_LOCK(husart); @@ -598,6 +635,10 @@ HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxDat * @param pRxData: pointer to RX data buffer. * @param Size: amount of data to be sent (same amount to be received). * @param Timeout: Timeout duration. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * address of user data buffers containing data to be sent/received, should be aligned on a half word frontier (16 bits) + * (as sent/received data will be handled using u16 pointer cast). Depending on compilation chain, + * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pTxData and pRxData. * @retval HAL status */ HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout) @@ -611,6 +652,18 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t { return HAL_ERROR; } + + /* In case of 9bits/No Parity transfer, pTxData and pRxData buffers provided as input paramter + should be aligned on a u16 frontier, as data to be filled into TDR/retrieved from RDR will be + handled through a u16 cast. */ + if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + { + if(((((uint32_t)pTxData)&1) != 0) || ((((uint32_t)pRxData)&1) != 0)) + { + return HAL_ERROR; + } + } + /* Process Locked */ __HAL_LOCK(husart); @@ -684,6 +737,10 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t * @param husart: USART handle. * @param pTxData: pointer to data buffer. * @param Size: amount of data to be sent. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits) + * (as sent data will be handled using u16 pointer cast). Depending on compilation chain, + * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pTxData. * @retval HAL status */ HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size) @@ -695,6 +752,17 @@ HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pT return HAL_ERROR; } + /* In case of 9bits/No Parity transfer, pTxData buffer provided as input paramter + should be aligned on a u16 frontier, as data to be filled into TDR will be + handled through a u16 cast. */ + if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + { + if((((uint32_t)pTxData)&1) != 0) + { + return HAL_ERROR; + } + } + /* Process Locked */ __HAL_LOCK(husart); @@ -731,6 +799,10 @@ HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pT * @param husart: USART handle. * @param pRxData: pointer to data buffer. * @param Size: amount of data to be received. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits) + * (as received data will be handled using u16 pointer cast). Depending on compilation chain, + * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pRxData. * @retval HAL status */ HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size) @@ -741,6 +813,18 @@ HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRx { return HAL_ERROR; } + + /* In case of 9bits/No Parity transfer, pRxData buffer provided as input paramter + should be aligned on a u16 frontier, as data to be received from RDR will be + handled through a u16 cast. */ + if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + { + if((((uint32_t)pRxData)&1) != 0) + { + return HAL_ERROR; + } + } + /* Process Locked */ __HAL_LOCK(husart); @@ -790,6 +874,10 @@ HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRx * @param pTxData: pointer to TX data buffer. * @param pRxData: pointer to RX data buffer. * @param Size: amount of data to be sent (same amount to be received). + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * address of user data buffers containing data to be sent/received, should be aligned on a half word frontier (16 bits) + * (as sent/received data will be handled using u16 pointer cast). Depending on compilation chain, + * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pTxData and pRxData. * @retval HAL status */ HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) @@ -801,6 +889,18 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint { return HAL_ERROR; } + + /* In case of 9bits/No Parity transfer, pTxData and pRxData buffers provided as input paramter + should be aligned on a u16 frontier, as data to be filled into TDR/retrieved from RDR will be + handled through a u16 cast. */ + if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + { + if(((((uint32_t)pTxData)&1) != 0) || ((((uint32_t)pRxData)&1) != 0)) + { + return HAL_ERROR; + } + } + /* Process Locked */ __HAL_LOCK(husart); @@ -846,6 +946,10 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint * @param husart: USART handle. * @param pTxData: pointer to data buffer. * @param Size: amount of data to be sent. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits) + * (as sent data will be handled by DMA from halfword frontier). Depending on compilation chain, + * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pTxData. * @retval HAL status */ HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size) @@ -858,6 +962,18 @@ HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *p { return HAL_ERROR; } + + /* In case of 9bits/No Parity transfer, pTxData buffer provided as input paramter + should be aligned on a u16 frontier, as data copy into TDR will be + handled by DMA from a u16 frontier. */ + if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + { + if((((uint32_t)pTxData)&1) != 0) + { + return HAL_ERROR; + } + } + /* Process Locked */ __HAL_LOCK(husart); @@ -904,8 +1020,10 @@ HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *p * @param husart: USART handle. * @param pRxData: pointer to data buffer. * @param Size: amount of data to be received. - * @note When the USART parity is enabled (PCE = 1), the received data contain - * the parity bit (MSB position). + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits) + * (as received data will be handled by DMA from halfword frontier). Depending on compilation chain, + * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pRxData. * @note The USART DMA transmit channel must be configured in order to generate the clock for the slave. * @retval HAL status */ @@ -920,6 +1038,17 @@ HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pR return HAL_ERROR; } + /* In case of 9bits/No Parity transfer, pRxData buffer provided as input paramter + should be aligned on a u16 frontier, as data copy from RDR will be + handled by DMA from a u16 frontier. */ + if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + { + if((((uint32_t)pRxData)&1) != 0) + { + return HAL_ERROR; + } + } + /* Process Locked */ __HAL_LOCK(husart); @@ -975,7 +1104,10 @@ HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pR * @param pTxData: pointer to TX data buffer. * @param pRxData: pointer to RX data buffer. * @param Size: amount of data to be received/sent. - * @note When the USART parity is enabled (PCE = 1) the data received contain the parity bit. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * address of user data buffers containing data to be sent/received, should be aligned on a half word frontier (16 bits) + * (as sent/received data will be handled by DMA from halfword frontier). Depending on compilation chain, + * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pTxData and pRxData. * @retval HAL status */ HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) @@ -988,6 +1120,18 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uin { return HAL_ERROR; } + + /* In case of 9bits/No Parity transfer, pTxData and pRxData buffers provided as input paramter + should be aligned on a u16 frontier, as data copy to/from TDR/RDR will be + handled by DMA from a u16 frontier. */ + if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + { + if(((((uint32_t)pTxData)&1) != 0) || ((((uint32_t)pRxData)&1) != 0)) + { + return HAL_ERROR; + } + } + /* Process Locked */ __HAL_LOCK(husart); @@ -1449,16 +1593,16 @@ static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart) switch (clocksource) { case USART_CLOCKSOURCE_PCLK1: - usartdiv = (uint16_t)((2*HAL_RCC_GetPCLK1Freq()) / husart->Init.BaudRate); + usartdiv = (uint16_t)(((2*HAL_RCC_GetPCLK1Freq()) + (husart->Init.BaudRate/2)) / husart->Init.BaudRate); break; case USART_CLOCKSOURCE_HSI: - usartdiv = (uint16_t)((2*HSI_VALUE) / husart->Init.BaudRate); + usartdiv = (uint16_t)(((2*HSI_VALUE) + (husart->Init.BaudRate/2)) / husart->Init.BaudRate); break; case USART_CLOCKSOURCE_SYSCLK: - usartdiv = (uint16_t)((2*HAL_RCC_GetSysClockFreq()) / husart->Init.BaudRate); + usartdiv = (uint16_t)(((2*HAL_RCC_GetSysClockFreq()) + (husart->Init.BaudRate/2)) / husart->Init.BaudRate); break; case USART_CLOCKSOURCE_LSE: - usartdiv = (uint16_t)((2*LSE_VALUE) / husart->Init.BaudRate); + usartdiv = (uint16_t)(((2*LSE_VALUE) + (husart->Init.BaudRate/2)) / husart->Init.BaudRate); break; case USART_CLOCKSOURCE_UNDEFINED: default: @@ -1487,7 +1631,7 @@ static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart) Bits are defined for some specific devices, and are available only for UART instances supporting WakeUp from Stop Mode feature. */ #if !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC) - if (IS_UART_WAKEUP_INSTANCE(husart->Instance)) + if (IS_UART_WAKEUP_FROMSTOP_INSTANCE(husart->Instance)) { /* Check if the Transmitter is enabled */ if((husart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) @@ -1731,7 +1875,7 @@ static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart) if(husart->TxXferCount == 0) { - /* Disable the USART Transmit Complete Interrupt */ + /* Disable the USART Transmit data register empty interrupt */ __HAL_USART_DISABLE_IT(husart, USART_IT_TXE); /* Enable the USART Transmit Complete Interrupt */ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_usart.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_usart.h index 8cfebce1e5..d943623762 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_usart.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_usart.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f0xx_hal_usart.h * @author MCD Application Team - * @version V1.3.1 - * @date 29-January-2016 + * @version V1.4.0 + * @date 27-May-2016 * @brief Header file of USART HAL module. ****************************************************************************** * @attention @@ -183,12 +183,18 @@ typedef struct /** @defgroup USART_Stop_Bits USART Number of Stop Bits * @{ */ -#define USART_STOPBITS_1 ((uint32_t)0x0000) -#define USART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1) -#define USART_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1)) +#ifdef USART_SMARTCARD_SUPPORT +#define USART_STOPBITS_0_5 ((uint32_t)USART_CR2_STOP_0) /*!< USART frame with 0.5 stop bit */ +#define USART_STOPBITS_1 ((uint32_t)0x00000000) /*!< USART frame with 1 stop bit */ +#define USART_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1)) /*!< USART frame with 1.5 stop bits */ +#define USART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1) /*!< USART frame with 2 stop bits */ +#else +#define USART_STOPBITS_1 ((uint32_t)0x00000000) /*!< USART frame with 1 stop bit */ +#define USART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1) /*!< USART frame with 2 stop bits */ +#endif /** * @} - */ + */ /** @defgroup USART_Parity USART Parity * @{ @@ -506,10 +512,10 @@ typedef struct /** @brief Check USART Baud rate * @param __BAUDRATE__: Baudrate specified by the user. - * The maximum Baud Rate is derived from the maximum clock on F0 (i.e. 48 MHz) + * The maximum Baud Rate is derived from the maximum clock on F0 (i.e. 48 MHz) * divided by the smallest oversampling used on the USART (i.e. 8) * @retval Test result (TRUE or FALSE). - */ + */ #define IS_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 6000001) /** @@ -517,9 +523,15 @@ typedef struct * @param __STOPBITS__: USART frame number of stop bits. * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid) */ -#define IS_USART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == USART_STOPBITS_1) || \ +#ifdef USART_SMARTCARD_SUPPORT +#define IS_USART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == USART_STOPBITS_0_5) || \ + ((__STOPBITS__) == USART_STOPBITS_1) || \ ((__STOPBITS__) == USART_STOPBITS_1_5) || \ ((__STOPBITS__) == USART_STOPBITS_2)) +#else +#define IS_USART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == USART_STOPBITS_1) || \ + ((__STOPBITS__) == USART_STOPBITS_2)) +#endif /** * @brief Ensure that USART frame parity is valid. @@ -624,7 +636,7 @@ void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart); /* Peripheral Control functions ***********************************************/ -/** @addtogroup USART_Exported_Functions_Group3 Peripheral State and Error functions +/** @addtogroup USART_Exported_Functions_Group3 Peripheral State and Error functions * @{ */ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_usart_ex.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_usart_ex.h index 738e0a6685..2e818eff1a 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_usart_ex.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_usart_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f0xx_hal_usart_ex.h * @author MCD Application Team - * @version V1.3.1 - * @date 29-January-2016 + * @version V1.4.0 + * @date 27-May-2016 * @brief Header file of USART HAL Extension module. ****************************************************************************** * @attention diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_wwdg.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_wwdg.c index e5ab30571f..6ec77f8435 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_wwdg.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_wwdg.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f0xx_hal_wwdg.c * @author MCD Application Team - * @version V1.3.1 - * @date 29-January-2016 + * @version V1.4.0 + * @date 27-May-2016 * @brief WWDG HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Window Watchdog (WWDG) peripheral: diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_wwdg.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_wwdg.h index 2158678728..b8e7a37fcf 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_wwdg.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_wwdg.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f0xx_hal_wwdg.h * @author MCD Application Team - * @version V1.3.1 - * @date 29-January-2016 + * @version V1.4.0 + * @date 27-May-2016 * @brief Header file of WWDG HAL module. ****************************************************************************** * @attention