mirror of https://github.com/ARMmbed/mbed-os.git
commit
4dcefa604a
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@ -43,7 +43,6 @@ void set_compare(uint16_t count);
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extern volatile uint32_t SlaveCounter;
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extern volatile uint32_t oc_int_part;
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extern volatile uint16_t oc_rem_part;
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extern volatile uint16_t cnt_val;
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// Used to increment the slave counter
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void timer_update_irq_handler(void)
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@ -60,7 +59,7 @@ void timer_update_irq_handler(void)
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// Used for mbed timeout (channel 1) and HAL tick (channel 2)
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void timer_oc_irq_handler(void)
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{
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cnt_val = TIM_MST->CNT;
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uint16_t cval = TIM_MST->CNT;
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TimMasterHandle.Instance = TIM_MST;
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// Channel 1 for mbed timeout
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@ -72,7 +71,7 @@ void timer_oc_irq_handler(void)
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} else {
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if (oc_int_part > 0) {
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set_compare(0xFFFF);
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oc_rem_part = cnt_val; // To finish the counter loop the next time
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oc_rem_part = cval; // To finish the counter loop the next time
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oc_int_part--;
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} else {
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us_ticker_irq_handler();
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@ -129,8 +128,10 @@ HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) {
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// Output compare channel 2 interrupt for HAL tick
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NVIC_SetVector(TIM_MST_UP_IRQ, (uint32_t)timer_update_irq_handler);
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NVIC_EnableIRQ(TIM_MST_UP_IRQ);
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NVIC_SetPriority(TIM_MST_UP_IRQ, 0);
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NVIC_SetVector(TIM_MST_OC_IRQ, (uint32_t)timer_oc_irq_handler);
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NVIC_EnableIRQ(TIM_MST_OC_IRQ);
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NVIC_SetPriority(TIM_MST_OC_IRQ, 1);
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// Enable interrupts
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__HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_UPDATE); // For 32-bit counter
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@ -43,7 +43,6 @@ void set_compare(uint16_t count);
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extern volatile uint32_t SlaveCounter;
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extern volatile uint32_t oc_int_part;
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extern volatile uint16_t oc_rem_part;
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extern volatile uint16_t cnt_val;
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// Used to increment the slave counter
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void timer_update_irq_handler(void)
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@ -60,7 +59,7 @@ void timer_update_irq_handler(void)
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// Used for mbed timeout (channel 1) and HAL tick (channel 2)
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void timer_oc_irq_handler(void)
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{
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cnt_val = TIM_MST->CNT;
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uint16_t cval = TIM_MST->CNT;
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TimMasterHandle.Instance = TIM_MST;
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// Channel 1 for mbed timeout
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@ -72,7 +71,7 @@ void timer_oc_irq_handler(void)
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} else {
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if (oc_int_part > 0) {
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set_compare(0xFFFF);
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oc_rem_part = cnt_val; // To finish the counter loop the next time
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oc_rem_part = cval; // To finish the counter loop the next time
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oc_int_part--;
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} else {
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us_ticker_irq_handler();
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@ -131,8 +130,10 @@ HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) {
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// Output compare channel 2 interrupt for HAL tick
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NVIC_SetVector(TIM_MST_UP_IRQ, (uint32_t)timer_update_irq_handler);
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NVIC_EnableIRQ(TIM_MST_UP_IRQ);
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NVIC_SetPriority(TIM_MST_UP_IRQ, 0);
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NVIC_SetVector(TIM_MST_OC_IRQ, (uint32_t)timer_oc_irq_handler);
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NVIC_EnableIRQ(TIM_MST_OC_IRQ);
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NVIC_SetPriority(TIM_MST_OC_IRQ, 1);
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// Enable interrupts
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__HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_UPDATE); // For 32-bit counter
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@ -41,7 +41,6 @@ static int us_ticker_inited = 0;
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volatile uint32_t SlaveCounter = 0;
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volatile uint32_t oc_int_part = 0;
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volatile uint16_t oc_rem_part = 0;
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volatile uint16_t cnt_val = 0;
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void set_compare(uint16_t count) {
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TimMasterHandle.Instance = TIM_MST;
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@ -59,15 +58,24 @@ void us_ticker_init(void) {
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}
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uint32_t us_ticker_read() {
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uint32_t counter;
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uint32_t counter, counter2;
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if (!us_ticker_inited) us_ticker_init();
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//Current value of TIM_MST->CNT is stored in cnt_val and is
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//updated in interrupt context
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// A situation might appear when Master overflows right after Slave is read and before the
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// new (overflowed) value of Master is read. Which would make the code below consider the
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// previous (incorrect) value of Slave and the new value of Master, which would return a
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// value in the past. Avoid this by computing consecutive values of the timer until they
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// are properly ordered.
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counter = (uint32_t)(SlaveCounter << 16);
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counter += cnt_val;
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return counter;
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counter += TIM_MST->CNT;
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while (1) {
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counter2 = (uint32_t)(SlaveCounter << 16);
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counter2 += TIM_MST->CNT;
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if (counter2 > counter) {
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break;
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}
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counter = counter2;
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}
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return counter2;
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}
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void us_ticker_set_interrupt(timestamp_t timestamp) {
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