cyliangtw
5985dcd268
[M2351] Support secure loader invoke non-secure Mbed OS
2018-07-12 17:51:10 +08:00
deepikabhavnani
2f01120d93
[M2351] Corrected preprocess define usage in toolchain specific linker files
2018-07-12 17:51:09 +08:00
cyliangtw
18ca9b5e6c
[M2351] Fix GCC linker file 'cannot move location counter backwards' issue
2018-07-12 17:51:08 +08:00
cyliangtw
ba9e5fdc29
[M2351] IAR linker file support both of secure & non-secure domain
2018-07-12 17:51:07 +08:00
cyliangtw
f06644a920
[M2351] Linker files support both of secure & non-secure domain
2018-07-12 17:51:06 +08:00
cyliangtw
a2aac528f4
[M2351] Update GCC linker for NSC Veneer
2018-07-12 17:51:05 +08:00
Deepika
f7ea847dfe
[M2351] ARMC6 compiler related changes
2018-07-12 17:51:04 +08:00
Deepika
1117e84d9e
[M2351] Removed device name, till device patch is added to IAR/Keil
2018-07-12 17:51:03 +08:00
Deepika
d46220c7e0
[M2351] Set SAU Region present flag for M2351 device and include security header file.
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As per SAU documents, SAU is always present if the security extension is
available. The functionality differs if the SAU contains SAU regions.
If SAU regions are available it is configured with the macro __SAUREGION_PRESENT
2018-07-12 17:51:02 +08:00
Deepika
11792f60fa
[M2351] Added xx_ticker_fire_interrupt function for M2351 device
2018-07-12 17:51:01 +08:00
Deepika
ffcc438b5a
[M2351] Use Cortex M23 specific header files and interrupts
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1. Update use of correct header files
2. Added missing entry of M2351 device in IAR defines.
3. Removed support of ARM toolchain in targets.json
2018-07-12 17:51:00 +08:00
cyliangtw
e67ed3f86e
[M2351] Revise nu_bitutil.h for M23
2018-07-12 17:50:59 +08:00
cyliangtw
6b85478730
[M2351] Modify Nuvoton common files to avoid conflicting with master
2018-07-12 17:50:58 +08:00
cyliangtw
98c8427a90
[M2351] Add partition header file for CMSE feature
2018-07-12 17:50:57 +08:00
cyliangtw
368f8eef93
[M2351] Remove mbed_sdk_init_forced
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1. mbed_sdk_init is called before C++ global obj constructor in OS 5
2. Refine startup file with GCC_ARM toolchain related to this modification.
2018-07-12 17:50:56 +08:00
cyliangtw
06910bdea5
[M2351] remove progen, not used any more
2018-07-12 17:50:55 +08:00
cyliangtw
c5494eb751
[M2351] Support __vector_table instead of __vector_handlers in IAR
2018-07-12 17:50:54 +08:00
cyliangtw
1f27546480
[M2351] Support GCC & IAR toolchain
2018-07-12 17:50:53 +08:00
cyliangtw
dcdd9fb56e
[M2351] Sync SDH_CardDetection type to avoid GCC compiler error
2018-07-12 17:50:52 +08:00
cyliangtw
205f8dbab2
[M2351] Add one new target M2351, regard as M0+ with some V8M CPU control at first
2018-07-12 17:50:51 +08:00
Cruz Monrreal
e1df16e843
Merge pull request #7365 from jeromecoutant/PR_RTC_SHADOW
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STM32 RTC : bypass shadow registers
2018-07-11 21:29:02 -05:00
Cruz Monrreal
19c6f3b316
Merge pull request #7290 from bcostm/refactor_us_ticker
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STM32: Refactor us_ticker files
2018-07-11 21:28:32 -05:00
Cruz Monrreal
c669655d86
Merge pull request #7042 from shuoo/feature-cm3ds-flash
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Flash API: Enable Flash api on CM3DS
2018-07-11 09:28:17 -05:00
Cruz Monrreal
38c5e9c669
Merge pull request #7453 from marcuschangarm/fix-nrf52-swi
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Fix SWI conflict in SoftDevice for NRF52 series
2018-07-11 08:12:30 -05:00
bcostm
0b133be504
stm32 ticker: change th eplace where timer init in done, fix overflow issue with 16-bit timer
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- Move back the 16/32bit timer initialization in HAL_InitTick() and not in us_ticker_init()
- Use ticker_read_us() and us_ticker_read() in HAL_GetTick() to fix potential overflow issue with the 16bit timer
==> These corrections allow timer, rtc, sleep, tick tests to PASS
2018-07-11 14:45:48 +02:00
bcostm
fc50e28ae6
stm32 ticker: corrections in order to pass tests
2018-07-11 14:44:23 +02:00
bcostm
7097e07b62
stm32 ticker: typo corrections
2018-07-11 14:43:36 +02:00
bcostm
d8e839a789
stm32 ticker: change license
2018-07-11 14:43:16 +02:00
bcostm
32031cbab3
stm32 ticker: rename hal_tick.h in us_ticker_data.h
2018-07-11 14:42:44 +02:00
Cruz Monrreal
dc946b3c34
Merge pull request #7446 from kivaisan/disable_lse_MTB_USI_WM_BN_BM_22
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Disable LSE for MTB_USI_WM_BN_BM_22
2018-07-11 07:39:44 -05:00
bcostm
fbd7a97e19
stm32 ticker: rename macro and update ST HAL Tick functions
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- rename TIM_MST_16BIT in TIM_MST_BIT_WIDTH in order to use it directly in ticker info structure
- change HAL_InitTick() and HAL_GetTick()
2018-07-11 14:39:42 +02:00
bcostm
b1bbd765b7
stm32 ticker: rename files and move functions
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- rename hal_tick_common.c in hal_tick_overrides.c
- move 16 and 32bits timer functions in us_ticker.c
2018-07-11 14:36:58 +02:00
jeromecoutant
1052993236
STM32 RTC : bypass shadow registers
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- RTC_SSR for the subseconds
- RTC_TR for the time
- RTC_DR for the date
These registers were accessed through shadow registers which are synchronized with PCLK1 (APB1 clock).
They are now accessed directly in order to avoid waiting for the synchronization duration.
2018-07-11 10:08:02 +02:00
Kimmo Vaisanen
a5ac795304
Disable LSE for MTB_USI_WM_BN_BM_22
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Current MTB_USI_WM_BN_BM_22 modules do not have OSC32_IN connected, so
external xtal is not in use.
2018-07-10 08:49:38 +03:00
Marcus Chang
4bb84fdb71
Change NRF52 series UART to only use one SWI channel
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This fixes conflicts with the SoftDevice.
2018-07-09 12:54:09 -07:00
Marcus Chang
cfb99d689a
Fix inconsistent SWI configuration in NRF52 series
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All SWI channels except SWI0 is being used by the SoftDevice and
not only SWI1.
2018-07-09 12:54:09 -07:00
Marcus Chang
01135e30ce
Remove white space in config files for NRF52 series
2018-07-09 12:54:08 -07:00
Cruz Monrreal
bcec185754
Merge pull request #7352 from bcostm/fix_rtc_ticker
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STM32: Fix RTC test issue on targets using a 16-bit timer for us_ticker
2018-07-09 10:20:13 -05:00
Karl Zhang
bbb97c803b
Flash API: Enable Flash api on CM3DS
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Implement flash_api.c for CM3DS on MPS2+.
Because MPS2+ board has no physical flash chip, the implementation emulates
flash over SRAM.
2018-07-09 21:07:48 +08:00
Cruz Monrreal
69d8c0bac3
Merge pull request #7429 from codeauroraforum/MXRT_Fix_AnalogIn
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MXRT1050: Ensure the pins are in input mode for analogin
2018-07-06 11:24:40 -05:00
Cruz Monrreal
59defa29e9
Merge pull request #7406 from OpenNuvoton/nuvoton_fix_wakeup_delay
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NANO130: Change PLL clock source to HIRC instead of HXT
2018-07-06 11:20:40 -05:00
Mahesh Mahadevan
19b6ef2e87
MXRT1050: Ensure the pins are in input mode for analogin
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Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
2018-07-05 17:23:07 -05:00
Mahesh Mahadevan
c24d158fb4
MIMXRT1050_EVK: Move clock enable after check of pin
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Enable clock could return an error if pin is NC
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
2018-07-05 10:59:00 -05:00
Cruz Monrreal
9f27672f0f
Merge pull request #7420 from codeauroraforum/Fix_MXRT_GPIO_IRQ
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MIMXRT1050_EVK: Fix the GPIO IRQ number assignements
2018-07-05 10:51:02 -05:00
Cruz Monrreal
4942ec540c
Merge pull request #7413 from mikaleppanen/wiced_removed_def_inst
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Modified Wiced drivers EMAC instance get
2018-07-05 10:42:41 -05:00
Cruz Monrreal
917dc8394c
Merge pull request #7405 from marcuschangarm/fix-nrf52-target
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Fix target definition for NRF52 series
2018-07-05 10:41:55 -05:00
Cruz Monrreal
8b6dfc4050
Merge pull request #7401 from marcuschangarm/fix-nrf52-irq
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Fix interrupt initialization for NRF52 series
2018-07-05 10:41:20 -05:00
Cruz Monrreal
3faedca1cf
Merge pull request #7390 from jeromecoutant/PR_TWO
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DISCO STM32L4 : Add TWO_RAM_REGIONS macro
2018-07-05 10:39:31 -05:00
Cruz Monrreal
513960f17d
Merge pull request #7386 from evva-sfw/feature/make_clock_src_changeable
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Make clock source changeable over mbed_app.json for EFM32-Targets
2018-07-05 10:39:11 -05:00
Cruz Monrreal
1941906f72
Merge pull request #7376 from bcostm/dev_leds_disco_L496ag
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DISCO_L496AG: change LED1 and LED2 pins
2018-07-05 10:37:57 -05:00