00c9005b4e
[CMSIS_5]: Updated to ca812421
2019-04-10 14:41:35 +03:00
d2e9136ddb
Merge pull request #9167 from TomoYamanaka/hanlder_without_RTOS
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Modify IRQ handler processing when unusing RTOS at Cortex-A
2019-01-04 08:42:11 +00:00
65b4e72928
Modify IRQ handler processing without RTOS at Cortex-A IAR Compiler
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In case of unusing RTOS, there is no processing against IRQ handler and it causes a linker error.
Therefore, I added this processing with WEAK attribute. Also I added cmain.S file at cmsis/TARGET_CORTEX_A folder.
2018-12-20 16:24:07 +09:00
91f0be6ac3
Check correct ARMC6 predefine for FP codegen
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For ARMC6, CMSIS headers were checking the `__ARM_PCS_VFP`, which
indicates hardfp ABI in use, when they need to check whether FP
code generation is enabled. Change this to `__ARM_FP`, so it
works for platforms using softfp ABI.
Change already present in CMSIS_5 repo, via commit
969822ae162539d50617d1e5a3634ee2fd3b60f6, but redone with local
search-and-replace.
2018-12-19 13:03:11 +02:00
308dfe3a53
Fix CMSIS __RESTRICT define for IAR
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Revert the define __RESTRICT from "__restrict" to "restrict". This
fixes compilation for IAR.
2018-08-25 20:41:12 -05:00
342841aa0f
[CMSIS_5]: Updated to 0b521765
2018-08-25 20:41:00 -05:00
c37875c690
Add volatile modifier for CP15 accessors
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Add volatile modifier to prevent ARM compiler to remove inline function calls for __set_CP and __get_CP.
2018-06-07 16:47:12 +09:00
b6c4139328
RTX5: ignoring CPUID field in GIC implementation
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updated interrupt handler for GCC and IAR
2018-05-28 13:54:44 +09:00
8afbd66763
[CMSIS_5]: Updated to 49ac527a
2018-05-14 12:18:20 +01:00
063717d90d
Core(A): Changed macro __DEPRECATED to CMSIS_DEPRECATED. (Issue #287 )
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__DEPRECATED conflicts with a predefined macro in GCC C++ mode.
2017-12-21 14:09:25 +09:00
2f06202a9b
Core(A): Refactored L1 Cache maintenance to be compiler agnostic.
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- Added L1 Cache test cases to CoreValidation.
- Adopted FVP Cortex-A configs to simulate cache states.
2017-12-21 14:09:25 +09:00
11ec7a2209
CMSIS-Core(A): Add MMU section_normal_nc macro
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I added the macro definition for non-cache area.
2017-12-21 14:09:25 +09:00
0c1961a724
CMSIS-Core(A): Fixed enumerated type increment in GIC_DistInit and GIC_CPUInterfaceInit functions
2017-12-21 14:09:25 +09:00
56602562ad
Core(A): Updated __FPU_Enable function (VFP register count detection)
2017-12-21 14:09:25 +09:00
5d6abd6572
CMSIS/RTX: Patch RTX includes to match mbed OS scheme
2017-11-01 09:25:42 +00:00
a03591d6e3
CMSIS/RTX: Update CMSIS and RTX to 22b68c
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This includes Cortex A support and directory reshuffle.
2017-11-01 09:25:42 +00:00
dad71c4268
cmsis: add core_ca9 for backward compatibility
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cmsis 5 does not include it but as mbed 2 requires this, we will bring this file
back. This brings back few other dependencies, that we add only for cortex-a.
Once cortex-a gets cmsis5 and rtx2 support it will be updated.
2017-06-15 13:08:48 +01:00
7b022f8785
Modify CMSIS 5 so it is suitable for mbed-os
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Make changes to the files taken from RTX5/CMSIS5 so they work
with mbed-os and uvisor.
2017-05-30 18:53:38 +01:00
a9a29a4529
Pull in CMSIS 5 files
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Pull in unmodified CMSIS5 files from the repository
https://github.com/ARM-software/CMSIS_5.git from the commit
c1b4232f4a98275dd79ebc99cf9b5da5053def4d.
The files were copied as shown below with source->dest_dir.
CMSIS_5/CMSIS/Core/Include/core_*.h -> mbed-os/cmsis/
CMSIS_5/CMSIS/Core_A/Include/core_*.h -> mbed-os/cmsis/
CMSIS_5/CMSIS/DSP/Include/arm_math.h -> mbed-os/cmsis/
CMSIS_5/CMSIS/Core/Include/tz_context.h -> mbed-os/cmsis/
CMSIS_5/CMSIS/Core/Include/cmsis_compiler.h -> mbed-os/cmsis/TARGET_CORTEX_M/
CMSIS_5/CMSIS/Core/Include/cmsis_arm*.h -> mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_ARM/
CMSIS_5/CMSIS/Core/Include/cmsis_gcc*.h -> mbed-os/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/
CMSIS_5/CMSIS/Core_A/Include/cmsis_compiler.h -> mbed-os/cmsis/TARGET_CORTEX_A/
CMSIS_5/CMSIS/Core_A/Include/cmsis_arm*.h -> mbed-os/cmsis/TARGET_CORTEX_A/TOOLCHAIN_ARM/
CMSIS_5/CMSIS/RTOS2/RTX/Library/cmsis_os1.c -> mbed-os/rtos/rtx/
CMSIS_5/CMSIS/RTOS2/Include/cmsis_os2.h -> mbed-os/rtos/rtx2/TARGET_CORTEX_M/
CMSIS_5/CMSIS/RTOS2/RTX/Config/* -> mbed-os/rtos/rtx2/TARGET_CORTEX_M/
CMSIS_5/CMSIS/RTOS2/RTX/Include1/* -> mbed-os/rtos/rtx/
CMSIS_5/CMSIS/RTOS2/RTX/Include/* -> mbed-os/rtos/rtx2/TARGET_CORTEX_M/
CMSIS_5/CMSIS/RTOS2/RTX/Source/rtx_* -> mbed-os/rtos/rtx2/TARGET_CORTEX_M/
CMSIS_5/CMSIS/RTOS2/RTX/Source/core_cm.h -> mbed-os/rtos/rtx2/TARGET_CORTEX_M/
CMSIS_5/CMSIS/RTOS2/RTX/Source/ARM/irq_cm0.s -> mbed-os/rtos/rtx2/TARGET_CORTEX_M/TARGET_M0/TOOLCHAIN_ARM/
CMSIS_5/CMSIS/RTOS2/RTX/Source/GCC/irq_cm0.s -> mbed-os/rtos/rtx2/TARGET_CORTEX_M/TARGET_M0/TOOLCHAIN_GCC/
CMSIS_5/CMSIS/RTOS2/RTX/Source/IAR/irq_cm0.s -> mbed-os/rtos/rtx2/TARGET_CORTEX_M/TARGET_M0/TOOLCHAIN_IAR/
CMSIS_5/CMSIS/RTOS2/RTX/Source/ARM/irq_cm0.s -> mbed-os/rtos/rtx2/TARGET_CORTEX_M/TARGET_M0P/TOOLCHAIN_ARM/
CMSIS_5/CMSIS/RTOS2/RTX/Source/GCC/irq_cm0.s -> mbed-os/rtos/rtx2/TARGET_CORTEX_M/TARGET_M0P/TOOLCHAIN_GCC/
CMSIS_5/CMSIS/RTOS2/RTX/Source/IAR/irq_cm0.s -> mbed-os/rtos/rtx2/TARGET_CORTEX_M/TARGET_M0P/TOOLCHAIN_IAR/
CMSIS_5/CMSIS/RTOS2/RTX/Source/ARM/irq_cm3.s -> mbed-os/rtos/rtx2/TARGET_CORTEX_M/TARGET_M3/TOOLCHAIN_ARM/
CMSIS_5/CMSIS/RTOS2/RTX/Source/GCC/irq_cm3.s -> mbed-os/rtos/rtx2/TARGET_CORTEX_M/TARGET_M3/TOOLCHAIN_GCC/
CMSIS_5/CMSIS/RTOS2/RTX/Source/IAR/irq_cm3.s -> mbed-os/rtos/rtx2/TARGET_CORTEX_M/TARGET_M3/TOOLCHAIN_IAR/
CMSIS_5/CMSIS/RTOS2/RTX/Source/ARM/irq_cm4f.s -> mbed-os/rtos/rtx2/TARGET_CORTEX_M/TARGET_RTOS_M4_M7/TOOLCHAIN_ARM/
CMSIS_5/CMSIS/RTOS2/RTX/Source/GCC/irq_cm4f.s -> mbed-os/rtos/rtx2/TARGET_CORTEX_M/TARGET_RTOS_M4_M7/TOOLCHAIN_GCC/
CMSIS_5/CMSIS/RTOS2/RTX/Source/IAR/irq_cm4f.s -> mbed-os/rtos/rtx2/TARGET_CORTEX_M/TARGET_RTOS_M4_M7/TOOLCHAIN_IAR/
2017-05-30 18:53:37 +01:00
Kevin Bracey
Martin Kojtal
TomoYamanaka
Russ Butler
Toyomasa Watarai
Vladimir Umek
Bartek Szatkowski
Jonatan Antoni
Daniel Brondani
Robert Rostohar
Martin Kojtal