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Modify CMSIS 5 so it is suitable for mbed-os 

Make changes to the files taken from RTX5/CMSIS5 so they work
with mbed-os and uvisor.
pull/4294/head
Bartek Szatkowski 2017-05-15 11:33:34 -05:00 committed by Martin Kojtal
parent 7ae2e6e9ec
commit 7b022f8785
15 changed files with 115 additions and 27 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
cmsis/TARGET_CORTEX_A/TOOLCHAIN_ARM/cmsis_armcc.h
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@ -232,7 +232,7 @@ __STATIC_INLINE void __set_CPSR(uint32_t cpsr)
\return Processor Mode
*/
__STATIC_INLINE uint32_t __get_mode(void) {
return (__get_CPSR() & 0x1FU);
return (__get_CPSR() & 0x1FU);
}
/** \brief Set Mode

16
cmsis/TARGET_CORTEX_A/TOOLCHAIN_ARM/cmsis_armclang.h
View File

@ -224,7 +224,7 @@ __STATIC_INLINE uint32_t __get_CPSR(void)
\return Processor Mode
*/
__STATIC_INLINE uint32_t __get_mode(void) {
return (__get_CPSR() & 0x1FU);
return (__get_CPSR() & 0x1FU);
}
/** \brief Set Mode
@ -579,24 +579,24 @@ __STATIC_INLINE void __L1C_CleanInvalidateCache(uint32_t op) {
*/
__STATIC_INLINE void __FPU_Enable(void) {
__ASM volatile(
//Permit access to VFP/NEON, registers by modifying CPACR
//Permit access to VFP/NEON, registers by modifying CPACR
" MRC p15,0,R1,c1,c0,2 \n"
" ORR R1,R1,#0x00F00000 \n"
" MCR p15,0,R1,c1,c0,2 \n"
//Ensure that subsequent instructions occur in the context of VFP/NEON access permitted
//Ensure that subsequent instructions occur in the context of VFP/NEON access permitted
" ISB \n"
//Enable VFP/NEON
//Enable VFP/NEON
" VMRS R1,FPEXC \n"
" ORR R1,R1,#0x40000000 \n"
" VMSR FPEXC,R1 \n"
//Initialise VFP/NEON registers to 0
//Initialise VFP/NEON registers to 0
" MOV R2,#0 \n"
#if 0 // TODO: Initialize FPU registers according to available register count
".if {TARGET_FEATURE_EXTENSION_REGISTER_COUNT} >= 16 \n"
//Initialise D16 registers to 0
//Initialise D16 registers to 0
" VMOV D0, R2,R2 \n"
" VMOV D1, R2,R2 \n"
" VMOV D2, R2,R2 \n"
@ -616,7 +616,7 @@ __STATIC_INLINE void __FPU_Enable(void) {
".endif \n"
".if {TARGET_FEATURE_EXTENSION_REGISTER_COUNT} == 32 \n"
//Initialise D32 registers to 0
//Initialise D32 registers to 0
" VMOV D16,R2,R2 \n"
" VMOV D17,R2,R2 \n"
" VMOV D18,R2,R2 \n"
@ -635,7 +635,7 @@ __STATIC_INLINE void __FPU_Enable(void) {
" VMOV D31,R2,R2 \n"
".endif \n"
#endif
//Initialise FPSCR to a known state
//Initialise FPSCR to a known state
" VMRS R2,FPSCR \n"
" LDR R3,=0x00086060 \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
" AND R2,R2,R3 \n"

20
cmsis/TARGET_CORTEX_M/cmsis_compiler.h
View File

@ -65,6 +65,26 @@
#include <cmsis_iar.h>
/* CMSIS compiler control architecture macros */
#if (__CORE__ == __ARM6M__) || (__CORE__ == __ARM6SM__)
#ifndef __ARM_ARCH_6M__
#define __ARM_ARCH_6M__ 1
#endif
#elif (__CORE__ == __ARM7M__)
#ifndef __ARM_ARCH_7M__
#define __ARM_ARCH_7M__ 1
#endif
#elif (__CORE__ == __ARM7EM__)
#ifndef __ARM_ARCH_7EM__
#define __ARM_ARCH_7EM__ 1
#endif
#endif
// IAR version 7.8.1 and earlier do not include __ALIGNED
#ifndef __ALIGNED
#define __ALIGNED(x) __attribute__((aligned(x)))
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __noreturn
#endif

37
cmsis/arm_math.h
View File

@ -293,14 +293,30 @@
#ifndef _ARM_MATH_H
#define _ARM_MATH_H
/* ignore some GCC warnings */
#if defined ( __GNUC__ )
/* Compiler specific diagnostic adjustment */
#if defined ( __CC_ARM )
#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
#elif defined ( __GNUC__ )
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wsign-conversion"
#pragma GCC diagnostic ignored "-Wconversion"
#pragma GCC diagnostic ignored "-Wunused-parameter"
#elif defined ( __ICCARM__ )
#elif defined ( __TI_ARM__ )
#elif defined ( __CSMC__ )
#elif defined ( __TASKING__ )
#else
#error Unknown compiler
#endif
#define __CMSIS_GENERIC /* disable NVIC and Systick functions */
#if defined(ARM_MATH_CM7)
@ -7213,9 +7229,24 @@ void arm_rfft_fast_f32(
}
#endif
/* Compiler specific diagnostic adjustment */
#if defined ( __CC_ARM )
#if defined ( __GNUC__ )
#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
#elif defined ( __GNUC__ )
#pragma GCC diagnostic pop
#elif defined ( __ICCARM__ )
#elif defined ( __TI_ARM__ )
#elif defined ( __CSMC__ )
#elif defined ( __TASKING__ )
#else
#error Unknown compiler
#endif
#endif /* _ARM_MATH_H */

16
rtos/rtx/cmsis_os.h
View File

@ -433,23 +433,23 @@ uint32_t osKernelSysTick (void);
/// \param instances number of possible thread instances.
/// \param stacksz stack size (in bytes) requirements for the thread function.
#if defined (osObjectsExternal) // object is external
#define osThreadDef(name, priority, instances, stacksz) \
#define osThreadDef(name, priority, stacksz) \
extern const osThreadDef_t os_thread_def_##name
#else // define the object
#if (osCMSIS < 0x20000U)
#define osThreadDef(name, priority, instances, stacksz) \
#define osThreadDef(name, priority, stacksz) \
const osThreadDef_t os_thread_def_##name = \
{ (name), (priority), (instances), (stacksz) }
{ (name), (priority), (1), (stacksz) }
#else
#define osThreadDef(name, priority, instances, stacksz) \
static uint64_t os_thread_stack##name[(stacksz)?(((stacksz+7)/8)):1] __attribute__((section(".bss.os.thread.stack"))); \
#define osThreadDef(name, priority, stacksz) \
uint64_t os_thread_stack##name[(stacksz)?(((stacksz+7)/8)):1] __attribute__((section(".bss.os.thread.stack"))); \
static osRtxThread_t os_thread_cb_##name __attribute__((section(".bss.os.thread.cb"))); \
const osThreadDef_t os_thread_def_##name = \
{ (name), \
{ NULL, osThreadDetached, \
(instances == 1) ? (&os_thread_cb_##name) : NULL,\
(instances == 1) ? osRtxThreadCbSize : 0U, \
((stacksz) && (instances == 1)) ? (&os_thread_stack##name) : NULL, \
(&os_thread_cb_##name),\
osRtxThreadCbSize, \
(stacksz) ? (&os_thread_stack##name) : NULL, \
8*((stacksz+7)/8), \
(priority), 0U, 0U } }
#endif

2
rtos/rtx2/TARGET_CORTEX_M/RTX_Config.c
View File

@ -24,7 +24,7 @@
*
* -----------------------------------------------------------------------------
*/
#include "cmsis_compiler.h"
#include "rtx_os.h"

7
rtos/rtx2/TARGET_CORTEX_M/RTX_Config.h
View File

@ -1,3 +1,5 @@
/** \addtogroup rtos */
/** @{*/
/*
* Copyright (c) 2013-2017 ARM Limited. All rights reserved.
*
@ -27,7 +29,9 @@
#ifndef RTX_CONFIG_H_
#define RTX_CONFIG_H_
#include "rtx2/mbed_rtx_conf.h"
//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
// <h>System Configuration
@ -377,3 +381,4 @@
//------------- <<< end of configuration section >>> ---------------------------
#endif // RTX_CONFIG_H_
/** @}*/

6
rtos/rtx2/TARGET_CORTEX_M/TARGET_RTOS_M4_M7/TOOLCHAIN_ARM/irq_cm4f.s
View File

@ -66,16 +66,20 @@ SVC_Context
CBNZ R1,SVC_ContextSave ; Branch if running thread is not deleted
TST LR,#0x10 ; Check if extended stack frame
BNE SVC_ContextSwitch
#ifdef __FPU_PRESENT
LDR R1,=0xE000EF34 ; FPCCR Address
LDR R0,[R1] ; Load FPCCR
BIC R0,#1 ; Clear LSPACT (Lazy state)
STR R0,[R1] ; Store FPCCR
B SVC_ContextSwitch
#endif
SVC_ContextSave
STMDB R12!,{R4-R11} ; Save R4..R11
#ifdef __FPU_PRESENT
TST LR,#0x10 ; Check if extended stack frame
VSTMDBEQ R12!,{S16-S31} ; Save VFP S16.S31
#endif
STR R12,[R1,#TCB_SP_OFS] ; Store SP
STRB LR, [R1,#TCB_SF_OFS] ; Store stack frame information
@ -88,8 +92,10 @@ SVC_ContextRestore
LDR R0,[R2,#TCB_SP_OFS] ; Load SP
ORR LR,R1,#0xFFFFFF00 ; Set EXC_RETURN
#ifdef __FPU_PRESENT
TST LR,#0x10 ; Check if extended stack frame
VLDMIAEQ R0!,{S16-S31} ; Restore VFP S16..S31
#endif
LDMIA R0!,{R4-R11} ; Restore R4..R11
MSR PSP,R0 ; Set PSP

7
rtos/rtx2/TARGET_CORTEX_M/TARGET_RTOS_M4_M7/TOOLCHAIN_GCC/irq_cm4f.S
View File

@ -70,17 +70,22 @@ SVC_Context:
CBNZ R1,SVC_ContextSave // Branch if running thread is not deleted
TST LR,#0x10 // Check if extended stack frame
BNE SVC_ContextSwitch
#ifdef __FPU_PRESENT
LDR R1,=0xE000EF34 // FPCCR Address
LDR R0,[R1] // Load FPCCR
BIC R0,#1 // Clear LSPACT (Lazy state)
STR R0,[R1] // Store FPCCR
B SVC_ContextSwitch
#endif
SVC_ContextSave:
STMDB R12!,{R4-R11} // Save R4..R11
#ifdef __FPU_PRESENT
TST LR,#0x10 // Check if extended stack frame
IT EQ
VSTMDBEQ R12!,{S16-S31} // Save VFP S16.S31
#endif
STR R12,[R1,#TCB_SP_OFS] // Store SP
STRB LR, [R1,#TCB_SF_OFS] // Store stack frame information
@ -93,9 +98,11 @@ SVC_ContextRestore:
LDR R0,[R2,#TCB_SP_OFS] // Load SP
ORR LR,R1,#0xFFFFFF00 // Set EXC_RETURN
#ifdef __FPU_PRESENT
TST LR,#0x10 // Check if extended stack frame
IT EQ
VLDMIAEQ R0!,{S16-S31} // Restore VFP S16..S31
#endif
LDMIA R0!,{R4-R11} // Restore R4..R11
MSR PSP,R0 // Set PSP

6
rtos/rtx2/TARGET_CORTEX_M/TARGET_RTOS_M4_M7/TOOLCHAIN_IAR/irq_cm4f.s
View File

@ -69,17 +69,21 @@ SVC_Context
CBNZ R1,SVC_ContextSave ; Branch if running thread is not deleted
TST LR,#0x10 ; Check if extended stack frame
BNE SVC_ContextSwitch
#ifdef __FPU_PRESENT
LDR R1,=0xE000EF34 ; FPCCR Address
LDR R0,[R1] ; Load FPCCR
BIC R0,R0,#1 ; Clear LSPACT (Lazy state)
STR R0,[R1] ; Store FPCCR
B SVC_ContextSwitch
#endif
SVC_ContextSave
STMDB R12!,{R4-R11} ; Save R4..R11
#ifdef __FPU_PRESENT
TST LR,#0x10 ; Check if extended stack frame
IT EQ
VSTMDBEQ R12!,{S16-S31} ; Save VFP S16.S31
#endif
STR R12,[R1,#TCB_SP_OFS] ; Store SP
STRB LR, [R1,#TCB_SF_OFS] ; Store stack frame information
@ -92,9 +96,11 @@ SVC_ContextRestore
LDR R0,[R2,#TCB_SP_OFS] ; Load SP
ORR LR,R1,#0xFFFFFF00 ; Set EXC_RETURN
#ifdef __FPU_PRESENT
TST LR,#0x10 ; Check if extended stack frame
IT EQ
VLDMIAEQ R0!,{S16-S31} ; Restore VFP S16..S31
#endif
LDMIA R0!,{R4-R11} ; Restore R4..R11
MSR PSP,R0 ; Set PSP

4
rtos/rtx2/TARGET_CORTEX_M/cmsis_os2.h
View File

@ -1,3 +1,5 @@
/** \addtogroup rtos */
/** @{*/
/*
* Copyright (c) 2013-2017 ARM Limited. All rights reserved.
*
@ -744,3 +746,5 @@ osStatus_t osMessageQueueDelete (osMessageQueueId_t mq_id);
#endif
#endif // CMSIS_OS2_H_
/** @}*/

10
rtos/rtx2/TARGET_CORTEX_M/core_cm.h
View File

@ -1,3 +1,5 @@
/** \addtogroup rtos */
/** @{*/
/*
* Copyright (c) 2013-2017 ARM Limited. All rights reserved.
*
@ -26,8 +28,10 @@
#ifndef CORE_CM_H_
#define CORE_CM_H_
#include "RTE_Components.h"
#include CMSIS_device_header
#include <stdint.h>
#include "cmsis.h"
#include "cmsis_compiler.h"
#include "arm_math.h"
#ifndef __ARM_ARCH_6M__
#define __ARM_ARCH_6M__ 0U
@ -1526,3 +1530,5 @@ __STATIC_INLINE void atomic_link_put (void **root, void *link) {
#endif // CORE_CM_H_
/** @}*/

2
rtos/rtx2/TARGET_CORTEX_M/rtx_evr.c
View File

@ -27,8 +27,6 @@
#include "cmsis_compiler.h"
#include "rtx_evr.h" // RTX Event Recorder definitions
#include "RTE_Components.h"
#ifdef RTE_Compiler_EventRecorder
#include "EventRecorder.h" // Keil::Compiler:Event Recorder

3
rtos/rtx2/TARGET_CORTEX_M/rtx_evr.h
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@ -1,3 +1,5 @@
/** \addtogroup rtos */
/** @{*/
/*
* Copyright (c) 2013-2017 ARM Limited. All rights reserved.
*
@ -1842,3 +1844,4 @@ extern void EvrRtxMessageQueueDestroyed (osMessageQueueId_t mq_id);
#endif // RTX_EVR_H_
/** @}*/

4
rtos/rtx2/TARGET_CORTEX_M/rtx_lib.h
View File

@ -1,3 +1,5 @@
/** \addtogroup rtos */
/** @{*/
/*
* Copyright (c) 2013-2017 ARM Limited. All rights reserved.
*
@ -210,5 +212,5 @@ extern uint32_t svcRtxMessageQueueGetSpace (osMessageQueueId_t mq_i
extern osStatus_t svcRtxMessageQueueReset (osMessageQueueId_t mq_id);
extern osStatus_t svcRtxMessageQueueDelete (osMessageQueueId_t mq_id);
#endif // RTX_LIB_H_
/** @}*/