The generic code in mbed_ticker_api.c uses run-time polymorphism to
handle different tickers, and has generic run-time calculations for
different ticker widths and frequencies, with a single special-case for
1MHz.
Extend the run-time special casing to handle any conversion cases where
either the multiply or divide can be done as a shift. This is a speed
optimisation for certain platforms.
Add a new option `target.custom-tickers`. If turned off, it promises
that only USTICKER and LPTICKER devices will be used. This then permits
elimination and/or simplification of runtime calculations, saving size
and speed. If either both USTICKER and LPTICKER have the same width, or
same period numerator or denominator, or only one of them exists, then
operations can be hard-coded. This is a significant ROM space saving,
and a minor speed and RAM saving.
We get to optimise all the calculations, but the run-time polymorphism
is retained even if there is only one ticker, as it doesn't
significantly affect code size versus direct calls, and the existence of
lp_ticker_wrapper and various us_ticker optimisations requires it, even
if only LPTICKER is available.
To allow overriding of the boot stack size from the Mbed configuration
system, consistently use MBED_CONF_TARGET_BOOT_STACK_SIZE rather than
MBED_BOOT_STACK_SIZE.
Fixes#10319
Remove all PSA S-mode only code, as it is unused. Only PSA S targets
would use the code, and we've removed those targets in a previous
commit.
Ensure all tests for S-mode code we are deleting is also removed, even
if that code would run in NS-mode. Keep any tests that also test our PSA
emulation support (for single v7-M targets).
Signed-off-by: Jaeden Amero <jaeden.amero@arm.com>
All MBED_SPM targets have been removed previously, via commits
5cc66282dd ("PSOC6: remove PSA targets") and 115b09aba43b ("psoc6:
Remove FUTURE_SEQUANA and FUTURE_SEQUANA_M0"). Remove all the dead
MBED_SPM code, as no targets use it.
Signed-off-by: Jaeden Amero <jaeden.amero@arm.com>
This is a special case since targets do not provide by default GPIO pin-maps.
This extension is required for FPGA GPIO tests - if some pins have limitations (e.g. fixed pull-up) we need to skip these pins while testing.
To do that we were adding a dummy pin-map with commented out pins that can't be tested because of the limitations.
This solution is redundant and the proposition is to provide a list of restricted gpio pins if required (by default weak implementation is provided with an empty list).
This mechanism will be backward compatible, so the old method with dummy gpio pinmap will also work. The switch from dummy pin-maps to pinmap_gpio_restricted_pins() will be performed in separate commits/PRs.
Substantiation for this is that the STDIO UART peripheral is used by Mbed, so it should never be tested.
Also solve the potential problem with accidenty skipped peripherals in FPGA testing. Currently, we have a one `pinmap_restricted_peripherals()` function for all interfaces (UART, I2C, SPI, etc.).
The problem can be encountered if different interfaces have the same peripheral ids (e.g. `UART_0` = 0, `SPI_0` = 0). In this case, if `UART_0` is on the restricted list, then SPI tests will be also skipped for `SPI_0`.
The good news is that usually, the peripheral ids are the base addresses of the peripheral's register set, but we can't rely on this. It is also good that `pinmap_restricted_peripherals()` at this moment is only required for STDIO UART (Nuvoton and STM).
To solve this issue we will change name of `pinmap_restricted_peripherals()` to `pinmap_uart_restricted_peripherals()`, make STDIO UART restricted by default for all targets and update FPGA test utilily functions to use `pinmap_uart_restricted_peripherals()` to skip only uart peripherals.
In the future if needed we can consider to add support to restrict peripherals of other interfaces(SPI, I2C, etc).
* Change "is supported" check to be a macro, so it can be done at
compile-time.
* Eliminate weird shift on 7-bit CRCs.
* Add support for 32-bit CRCs and reversals to TMPM3HQ.
* Change "is supported" check to be a macro, so it can be done at
compile-time.
* Eliminate weird shift on 7-bit CRCs.
* Add support for 32-bit CRCs and reversals to TMPM3HQ.
Add also default weak version of spi_get_capabilities() which provides default/most common SPI parameters.
This function can be replaced if a specific target has different capabilities.
* Refactor some headers to use relative path from Mbed OS root.
* Refactor some data types to compile on 64bit machines.
* Refactor some debug traces to use mbed_trace.
The QSPI spec allows alt to be any size that is a multiple of the
number of data lines. For example, Micron's N25Q128A uses only a
single alt cycle for all read modes (1, 2, or 4 bits depending on
how many data lines are in use).
The contents of the usb directory were moved to appropriate locations and the usb directory removed.
* Public USB headers moved under drivers/
* Internal USB headers moved under drivers/internal/
* USB Source code moved under drivers/source/usb/
* Moved usb/device/hal/ under hal/usb/
* Moved usb/device/USBPhy/ under hal/usb/
* Merged usb/device/targets/ into targets/
* Separated public and private USB API documentation under Doxygen groups drivers-public-api and drivers-internal-api.
Separate drivers, events, and rtos internal APIs from public APIs.
* Move source files to source subdirs
* Move internal headers to internal subdirs
* Add Doxygen comments for documenting internal and public APIs
* Remove source code from header files in order to remove include pre-processor directives
that included header files not directly used by said header files
* Explicitly include header files instead of implicit inclusions via third-party header files.
Release Notes
This will break user code that was using an internal API as the internal header files have been moved.
This will only break if the user was including the header file using a namespace (i.e #include "foo/bar.h" instead of #include "bar.h"
This change is required by the Samsung S111(S5JS100). On this board timer clock used for us ticker operates at 26MHz.
According to current requirements, 8 MHz is the top limit for us ticker timer.
This change relaxes top limit to 100 MHz, but only for 32-bit timers.
Ticker common layer schedules one interrupt per timer rollover to trace elapsed time. We need to ensure that this operation is not performed too frequently. I.e. in case of 16-bit timer at 32 MHz, the timer rollover will happen after ~2 ms. This may cause that there will be no time for other tasks. That is why we increase the top limit, but only for 32-bit timers.
Functions related to serial flow control should not be exposed
if DEVICE_SERIAL_FC is not defined
* serial_set_flow_control,
* serial_cts_pinmap,
* serial_rts_pinmap.
Kevin Bracey
Antti Kauppila
Rajkumar Kanagaraj
Martin Kojtal
Jaeden Amero
Roman Okhrimenko
talorion
Charley Chu
Filip Jagodzinski
Przemyslaw Stekiel
Veijo Pesonen
Heath Petersen
Seppo Takalo
Kyle Kearney
jeromecoutant
Matthew Macovsky
int_szyk
Hugues Kamba
Mariwan
George Psimenos
Russ Butler
Amanda Butler