Commit Graph

21226 Commits (187af9e26f1b3eec9d6cfd2fb9b73c84abc7268c)

Author SHA1 Message Date
Ron Eldor 187af9e26f Update the CC310 IAR libraries
Update the cryptocell 310 IAR libraries, since the previous ones were not
built correct. The libraries were built from the Cryptocell 310
release version 1.1.0.1285, using IAR version 7.80.1.11864.
2018-12-27 22:26:03 -06:00
ccli8 cfd8823d30 Fix crypto AC management
1. For SHA AC, use atomic flag to manage its ownership.
   (1) Nuvoton SHA AC doesn't support SHA context save & restore, so S/W
       SHA fallback has been supported before. To make non-blocking 'acquire'
       semantics clearer, introduce 'try_acquire' to substitute for 'acquire'.
   (2) No biting CPU due to mechanism above.
   (3) No deadlock due to mechanism above.
2. For AES/DES/ECC AC, change to mutex to manage their ownership.
   (1) Change crypto-misc.c to crypto-misc.cpp to utilize C++ SingletonPtr
       which guarantees thread-safe mutex construct-on-first-use.
   (2) With change to crypto-misc.cpp, add 'extern "C"' modifier to CRYPTO_IRQHandler()
       to avoid name mangling in C++.
   (3) No priority inversion because mutex has osMutexPrioInherit attribute
       bit set.
   (4) No deadlock because these AC are all locked for a short sequence
       of operations rather than the whole lifetime of mbedtls context.
   (5) For double mbedtls_internal_ecp_init() issue, it has been fixed in upper
       mbedtls layer. So no need to change ecc init/free flow.
2018-12-27 22:26:03 -06:00
ccli8 5fc51b8aa2 Fix return error code when ECC H/W acceleratioin is failed 2018-12-27 22:26:03 -06:00
Russ Butler 2ad952d29b Update MPU ram/rom split for Nuvoton M2351
Move the start of RAM from 0x10000000 to 0x20000000 on the
NUMAKER_PFM_M2351. This allows the target to work correctly.
2018-12-27 22:26:03 -06:00
Kevin Bracey 204a568abb nRF52840: Set mpu-rom-end to 0x1fffffff
So we have at least one test platform exercising the special case of
mpu-rom-end being 0x1fffffff, set that for nRF52840.
2018-12-27 22:26:03 -06:00
Kevin Bracey 342eed5f29 Fix target.mpu-rom-end setting, for ARMv8-M too
targets.json was not specifying the same macro name as the code was
checking for, so setting was ineffective.

Making this work tripped up not-supported checks in ARMv8-M - rather than deal
with making this work, support it instead.

Both ARMv7-M and ARMv8-M slightly reduce code size and runtime impact if
mpu-rom-end is 0x1fffffff, using one fewer region.

This means default setup for ARMv8-M now requires 5 regions, with
mpu-rom-end set to default 0x0fffffff, but this can be put back to 4 by
changing the setting.
2018-12-27 22:26:03 -06:00
Kevin Bracey 767c7f646e ARMv7-M MPU: correctly protect 80000000 RAM region
Subregion mask for this region was set fully disabled, instead of fully
enabled.
2018-12-27 22:26:03 -06:00
Kevin Bracey 4e992a32ce Assert MPU regions, rather than error
As we build for a specific CPU, a runtime check for number of MPU
regions in release builds is not worthwhile. Make it an assert only.
Saves a little space in develop images, a lot in release.
2018-12-27 22:26:03 -06:00
Kevin Bracey 263129a300 MPU - use higher-level calls, fix ARMv8-M error
Switch to higher-level calls and macros, and fix an error in the ARMv8-M
version - "inner" attributes were not being set correctly due to a
copy/paste error - "outer" was being set twice.

This means RAM would have been marked WTRA rather than WBWA for the
inner cache.

Slightly reduces ARMv7-M init code size by feeding region number
into RBAR instead of using RNR.
2018-12-27 22:26:03 -06:00
Kevin Bracey 60451368a8 Reduce dynamic MPU code size with a loop 2018-12-27 22:26:03 -06:00
Kevin Bracey 4f9b258a03 Fix MPU synchronisation
Synchronisation instructions were not quite right - too strict on entry,
and not quite correctly synchronising the instruction stream on exit.

References:

* https://static.docs.arm.com/dai0321/a/DAI0321A_programming_guide_memory_barriers_for_m_profile.pdf
* https://static.docs.arm.com/100699/0100/armv8m_architecture_memory_protection_unit_100699_0100_00_en.pdf
2018-12-27 22:26:02 -06:00
Russ Butler bfc3d853e4 Use MPU platform deinit rather than hal free
Use the MPU through the platform layer rather than through the HAL.
2018-12-27 22:26:02 -06:00
jeromecoutant 6f6cdc948b DNS tests: improve debug messages 2018-12-27 22:26:02 -06:00
Russ Butler 53e39edcde Fix ESP8266 "Link Type" errors after reset
As part of the ESP8266 connect sequence, ESP8266Interface::connect,
a software reset is performed. If the ESP8266 had been connected
previously then the ESP8266 will sometimes send a "WIFI DISCONNECT" OOB
message before performing the software reset. This causes the
ESP8266::_oob_connection_status to change its state (_conn_status) from
NSAPI_STATUS_DISCONNECTED to NSAPI_STATUS_CONNECTING. This causes
ESP8266Interface::_startup, called later in the boot seqeunce, to skip
ESP8266::startup. Without this call socket mux mode (CIPMUX=1) is never
enabled and all send commands using this format fail with a "Link Type"
error.

This patch fixes that problem by unconditionally calling
ESP8266::startup as part of the ESP8266 connect sequence.
2018-12-27 22:26:02 -06:00
jeromecoutant 3da0d3c0a5 WIFI test: improve debug messages 2018-12-27 22:26:02 -06:00
ccli8 a4ec28046c Change main thread stack size to default for stack size unification
NANO130 just has 16 KiB SRAM. User application may change it through "rtos.main-thread-stack-size"
configuration option.
2018-12-27 22:26:02 -06:00
ccli8 71d32ecef1 Support boot stack size configuration option 2018-12-27 22:26:02 -06:00
Kari Haapalehto c7ced9b42f Initialize the interface at the construction and make sure that it's done only once. 2018-12-27 22:26:02 -06:00
Fred.Li 64f2d5e708 Fix wrong PIN config for RTL8195AM platform
Merge from https://github.com/ARMmbed/sd-driver/pull/110
2018-12-27 22:26:02 -06:00
zhanglu@realtek-sg.com 1853db62d6 Realtek-rtl8195am-Network Socket Updates
This PR addresses the issue of #8124.
It updates and enriches the wifi connection error type to adapt the Network Socket test plan requirement.
In the meantime, it increases the heap size that allows the transmission of larger packet size.

Description
1. Increase heap size in lwipstack\mbed_lib.json to fulfill bursty TCP and UDP transmission requirement.
2. Modify and enrich wifi connection error types in TARGET_AMEBA\RTWInterface.cpp to adapt the decision logic of the wifi test cases.
3. Add new static constants in TARGET_AMEBA\RTWInterface.h, including 'SSID_MAX_LENGTH', 'PASSPHRASE_MAX_LENGTH' and 'PASSPHRASE_MIN_LENGTH' to help verifying the validity of ssid and passphrase.

Pull request type
[x] Fix
[ ] Refactor
[ ] Target update
[ ] Functionality change
[ ] Docs update
[ ] Test update
[ ] Breaking change
2018-12-27 22:26:02 -06:00
fluidblue 81c6402262 Removed GCC_CR toolchain for LPC11U68 2018-12-27 22:26:02 -06:00
Fluidblue 3663fe515e Prevent multiple __aeabi_atexit definition linker error (GCC_CR) 2018-12-27 22:26:02 -06:00
Fluidblue 3ca58fdb80 Prevent multiple __aeabi_atexit definition linker error (GCC_ARM) 2018-12-27 22:26:02 -06:00
kegilbert 637499c63f Add socket stat logging state change update
TCPServer was deprecated and the accept call was added to TCPSocket. Add state change update to that call
2018-12-27 22:26:02 -06:00
Mahesh Mahadevan da62237ac4 Rapid-IoT: Add support for the KW41Z side of the platform
Add support for the KW41Z side of the RapidIoT platform. This requires the latest
DAPLink binary to be programmed on the RapidIoT platform, binary can be downloaded
from the below link:
https://armmbed.github.io/DAPLink/

Also, the KW41Z side on RapidIoT does not have a serial port connected to the Debug
terminal. Therefore a SerialPassThrough program should be flashed and running on the
K64F side of RapidIoT platform for the mbed tests to pass.

Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
2018-12-27 22:26:02 -06:00
Cruz Monrreal II 2c3b420606 Intervaltree version update (3.0.0) caused builds to break. Capping version to latest 2.x 2018-12-27 22:26:02 -06:00
Kevin Bracey b1c23ac15f Disable write buffer in debug builds (M3/M4)
As part of work to improve the debugging of exceptions, have
Mbed OS make an effort to make exceptions more precise in debug builds
at the cost of performance.

Related pyOCD work:

   https://github.com/mbedmicro/pyOCD/pull/430
2018-12-27 22:26:02 -06:00
Kevin Bracey c8e8912d0e CM3: Make ACTLR bit definitions conditional
The ACTLR register itself is conditional on chip revision, but its
bit definitions were always defined.

Make the the bit definitions also conditional, so it is possible to
produce portable code that sets DISDEFWBUF if available:

    #ifdef SCnSCB_ACTLR_DISDEFWBUF_Msk
       SCnSCB->ACTLR |= SCnSCB_ACTLR_DISDEFWBUF_Msk;
    #endif

(cherry-picked from CMSIS b2b04dbeece0a046556bfc320bef6b20bef3f16f)
2018-12-27 22:26:02 -06:00
David Saada d6f22193ff Adjust FAT FS tests to low memory boards
This is achieved by checking whether the board can allocate a certain memory
chunk (threshold) and skipping the test if it can't.
This should prevent these boards from failing in CI.
2018-12-27 22:26:02 -06:00
Mahesh Mahadevan 0a4cb3c8c3 Update to add support for Cortex-M33FD
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
2018-12-27 22:26:02 -06:00
Alastair D'Silva d77f2c4b3a Align prototype & implementation of enet_tasklet_disconnect & friends
Rework of #8698

Signed-off-by: Alastair D'Silva <alastair@d-silva.org>
2018-12-27 22:26:02 -06:00
Laurent Louf 45e7296e05 Add some rounding to determine the pulse value for PWM for the STM target. 2018-12-27 22:26:01 -06:00
Brian Daniels a4a00ff7cf Fixing execution of OS2 tests 2018-12-27 22:26:01 -06:00
Kevin Bracey c401662941 Rework fseek/ftell tests
ARM C library is really good at optimising out calls to underlying
seek. The only ones we were actually detecting in the empty file case
were the ones that the default FileHandle::size() made itself during
the SEEK_END case.

When we implement TestFile::size() directly, we will no longer see
a single seek call from the ARM C library in the empty file case, so
remove those tests.

Beef up the non-empty file case, adding checks that we are making
underlying read+write calls in the correct position, as a proxy for
direct checks for underlying seek being called.
2018-12-27 22:26:01 -06:00
jeromecoutant 0c4d7d4dd6 STM32L4 QSPI: correct register address 2018-12-27 22:26:01 -06:00
jeromecoutant ac0fb3cea0 STM32 QSPI: remove QUADSPI_BK2 as dual bank feature is not supported 2018-12-27 22:26:01 -06:00
jeromecoutant 624695992c STM32 QSPIF: add DISCO_L496AG, DISCO_F746NG and DISCO_F769NI 2018-12-27 22:26:01 -06:00
jeromecoutant 0d9ea35ccf QSPI tests: update STM32 boards configuration
NB: STM directory removed in flash_configs as there is no STM memory
2018-12-27 22:26:01 -06:00
jeromecoutant 5a27a9a699 STM32 QSPI: frequency calculation update 2018-12-27 22:26:01 -06:00
jeromecoutant 2514a71abf Enable QSPI for DISCO F769 and L496 2018-12-27 22:26:01 -06:00
jeromecoutant 41cd8b3d10 STM32L496 : add QSPI definition 2018-12-27 22:26:01 -06:00
jeromecoutant c0ad4621e0 STM32F769 : add QSPI definition 2018-12-27 22:26:00 -06:00
jeromecoutant da806bd59f STM32 DISCO : enable QSPI tests when available 2018-12-27 22:26:00 -06:00
jeromecoutant 356d5756ea NUCLEO_F746ZG : no embedded QSPI 2018-12-27 22:26:00 -06:00
jeromecoutant 018f72d6e4 STM32 : removed unused QSPI pin names 2018-12-27 22:26:00 -06:00
Teppo Järvelin a3d26187d4 Cellular: Fix to use PPP stack in PPP mode
In QUECTEL_BG96 and QUECTEL_BC95 there was missing #ifdefs for
PPP mode and our stack was used. Also BG96 needed to be added
AT_CellularBase::AT_CGDATA as not supported.
2018-12-27 22:26:00 -06:00
Conrad Braam aaed845cce removed abc insanity 2018-12-27 22:26:00 -06:00
Conrad Braam 2d9a5f41c6 removed include statement 2018-12-27 22:26:00 -06:00
Conrad Braam 43f09b862c writes and reads queue, not overflow stack IOTPAN-295 2018-12-27 22:26:00 -06:00
Mel W a88f9bbf52 Editorial changes 2018-12-27 22:26:00 -06:00